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Datasheet S3A1 Microcontroller Group Datasheet Renesas Synergy™ Platform Synergy Microcontrollers S3 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.1.00 Oct 2017 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other disputes involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawing, chart, program, algorithm, application examples. 3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics products. 5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The intended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (space and undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. When using the Renesas Electronics products, refer to the latest product information (data sheets, user's manuals, application notes, "General Notes for Handling and Using Semiconductor Devices" in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat radiation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions or failure or accident arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please ensure to implement safety measures to guard them against the possibility of bodily injury, injury or damage caused by fire, and social damage in the event of failure or malfunction of Renesas Electronics products, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures by your own responsibility as warranty for your products/system. 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You shall not use Renesas Electronics products or technologies for (1) any purpose relating to the development, design, manufacture, use, stockpiling, etc., of weapons of mass destruction, such as nuclear weapons, chemical weapons, or biological weapons, or missiles (including unmanned aerial vehicles (UAVs)) for delivering such weapons, (2) any purpose relating to the development, design, manufacture, or use of conventional weapons, or (3) any other purpose of disturbing international peace and security, and you shall not sell, export, lease, transfer, or release Renesas Electronics products or technologies to any third party whether directly or indirectly with knowledge or reason to know that the third party or any other party will engage in the activities described above. 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(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. (Rev.3.0-1 November 2016) General Precautions 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product. Preface 1. About this document This manual describes the functions and electrical characteristics of the Renesas Synergy™ Microcontroller. This manual is generally organized into an overview of the product, descriptions of the CPU, system control functions, peripheral functions, electrical characteristics, and usage notes. This manual describes the product specification of the microcontroller (MCU) superset. Depending on your product, some pins, registers, or functions might not exist. Address space that store unavailable registers are reserved. 2. Audience This manual is written for system designers who are designing and programming applications using the Renesas Synergy Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU. 3. Renesas Publications Renesas provides the following documents for the Renesas Synergy Microcontroller. Before using any of these documents, visit www.renesas.com for the most up-to-date version of the document. Component Microcontrollers Software Tools & Kits, Solutions Document type Description Datasheet Features, overview, and electrical characteristics of the MCU User’s Manual: Microcontrollers MCU specifications such as pin assignments, memory maps, peripheral functions, electrical characteristics, timing diagrams, and operation descriptions Application Notes Technical notes, board design guidelines, and software migration information Technical Update (TU) Preliminary reports on product specifications such as restriction and errata Datasheet Functional descriptions and specific performance data for software modules that are included in Renesas Synergy Software Package (SSP) User’s Manual: Software API reference including SSP architecture and programming information Application Notes Project files, guidelines for software programming, and application examples to develop embedded software applications User’s Manual: Development Tools User’s manual and quick start guide for developing embedded software applications with Development Kits (DK), Starter Kits (SK), Promotion Kits (PK), Product Examples (PE), and Application Examples (AE) User’s Manual: Software Quick Start Guide Application Notes Project files, guidelines for software programming, and application examples to develop embedded software applications 4. Numbering Notation The following numbering notation is used throughout this manual: Example Description 011b Binary number. For example, the binary equivalent of the number 3 is 011b. 1Fh Hexadecimal number. For example, the hexadecimal equivalent of the number 31 is described 1Fh. In some cases, a hexadecimal number is shown with the prefix 0x, based on C/C++ formatting. 1234 Decimal number. Decimal numbers are generally shown without a suffix. 5. Typographic Notation The following typographic notation is used throughout this manual: Example Description ICU.NMICR.NMIMD Periods separate a function module symbol (ICU), register symbol (NMICR), and bit field symbol (NMIMD) ICU.NMICR A period separates a function module symbol (ICU) and register symbol (NMICR) NMICR.NMIMD A period separates a register symbol (NMICR) and bit field symbol (NMIMD) NFCLKSEL[1:0] In a register bit name, the bit range enclosed in square brackets indicates the number of bits in the field at this location. In this example, NFCLKSEL[1:0] represents a 2-bit field at the specified location in the NMI Pin Interrupt Control Register (NMICR). 6. Unit Prefix The following unit prefixes are sometimes misleading. Those unit prefixes are described throughout this manual with the following meaning: Prefix Description b Bit B Byte. This unit prefix is generally used for memory specification of the MCU and address space. k 1000 = 103. k is also used to denote 1024 (210) but this unit prefix is used to denote 1000 (103) throughout this manual. K 1024 = 210. This unit prefix is used to denote 1024 (210) not 1000 (103) throughout this manual. 7. Special Terms The following terms have special meanings: Term Description NC Not connected pin. NC means the pin is not connected to the MCU. Hi-Z High impedance 8. Register Description Each register description includes both a register diagram that shows the bit assignments and a register bit table that describes the content of each bit. The example of symbols used in these tables are described in the sections that follow. The following is an example of a register description and associated bit field definition. X.X.X NMI Pin Interrupt Control Register (NMICR) Address(es): Value after reset: (1) ICU.NMICR 4000 6100h b7 b6 NFLTE N — 0 0 b5 b4 NFCLKSEL[1:0] 0 0 b3 b2 b1 b0 — — — NMIMD 0 0 0 0 (4) (2) (3) (6) (5) Bit Symbol Bit name Description R/W b0 NMIMD NMI Detection Set 0: Falling edge 1: Rising edge. R/W b3 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W b5, b4 NFCLKSEL[1:0] NMI Digital Filter Sampling Clock Select b5 b4 R/W b6 — Reserved This bit is read as 0. The write value should be 0. R/W b7 NFLTEN NMI Digital Filter Enable 0: Disable the digital filter 1: Enable the digital filter. R/W 0 0 1 1 0: PCLKB 1:PCLKB/8 0: PCLKB/32 1: PCLKB/64. (1) Function module symbol, register symbol, and address assignment Function module symbol, register symbol, and address assignment of this register are generally expressed. ICU.NMICR 4000 6100h means NMI Pin Interrupt Control Register (NMICR) of Interrupt Controller Unit (ICU) is assigned to address 4000 6100h. (2) Bit number This number indicates the bit number. These bits are shown in order from b31 to b0 for a 32-bit register, from b15 to b0 for a 16-bit register, and from b7 to b0 for an 8-bit register. (3) Value after reset This symbol or number indicates the value of each bit after a reset. The value is shown in binary unless specified otherwise. 0: Indicates that the value is 0 after a reset. 1: Indicates that the value is 1 after a reset. x: Indicates that the value is undefined after a reset. (4) Bit symbol Bit symbol indicates the short name of the bit field. Reserved bit is expressed with a —. (5) Bit name Bit name indicates the full name of the bit field. (6) R/W The R/W column indicates access type: whether the bit field is read or write. R/W: The bit field is read and write. R/(W): The bit field is read and write. But writing to this bit field has some limitations. For details on the limitations, see the description or notes of respective registers. R: The bit field is read-only. Writing to this bit field has no effect. W: The bit field is write-only. The read value is undefined. 9. Abbreviations Abbreviations used in this manual are shown in the following table: Abbreviation AES Description Advanced Encryption Standard AHB Advanced High-Performance Bus AHB-AP AHB Access Port APB Advanced Peripheral Bus ARC Alleged RC ATB Advanced Trace Bus BCD Binary Coded Decimal BSDL Boundary Scan Description Language DES Data Encryption Standard DSA Digital Signature Algorithm ETB Embedded Trace Buffer ETM Embedded Trace Macrocell FLL Frequency Locked Loop FPU Floating-Point Unit GSM Global System for Mobile communications HMI Human Machine Interface IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit NVIC Nested Vector Interrupt Controller PC Program Counter PFS Port Function Select PLL Phase Locked Loop POR Power-On Reset PWM Pulse Width Modulation RSA Rivest Shamir Adleman SHA Secure Hash Algorithm S/H Sample and Hold SP Stack Pointer SWD Serial Wire Debug SW-DP Serial Wire-Debug Port TRNG True Random Number Generator UART Universal Asynchronous Receiver/Transmitter 10. Proprietary Notice All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated, transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior written consent from Renesas. Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited. CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium. Magic Packet™ is a trademark of Advanced Micro Devices, Inc. SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective holders. 11. Feedback on the product If you have any comments or suggestions about this product, go to https://www.renesas.com/en-eu/support/contact.html. 12. Feedback on content If you have any comments on the document such as general suggestions for improvements, go to https://www.renesas.com/en-eu/support/contact.html, and provide: - The title of the Renesas Synergy document - The document number - If applicable, the page number(s) to which your comments refer - A detailed explanation of your comments. Contents Features ................................................................................................................................................... 11 1. 2. Overview ........................................................................................................................................ 12 1.1 Function Outline ................................................................................................................... 12 1.2 Block Diagram ..................................................................................................................... 18 1.3 Part Numbering .................................................................................................................... 19 1.4 Function Comparison ........................................................................................................... 20 1.5 Pin Functions ....................................................................................................................... 21 1.6 Pin Assignments .................................................................................................................. 25 1.7 Pin Lists ............................................................................................................................... 32 Electrical Characteristics ................................................................................................................ 37 2.1 Absolute Maximum Ratings ................................................................................................. 38 2.2 DC Characteristics ............................................................................................................... 40 2.2.1 Tj/Ta Definition ............................................................................................................ 40 2.2.2 I/O VIH, VIL .................................................................................................................. 40 2.2.3 I/O IOH, IOL ................................................................................................................... 42 2.2.4 I/O VOH, VOL, and Other Characteristics ..................................................................... 44 2.2.5 I/O Pin Output Characteristics of Low Drive Capacity ................................................. 46 2.2.6 I/O Pin Output Characteristics of Middle Drive Capacity ............................................. 48 2.2.7 P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity ......................... 51 2.2.8 IIC I/O Pin Output Characteristics ............................................................................... 53 2.2.9 Operating and Standby Current ................................................................................... 54 2.2.10 VCC Rise and Fall Gradient and Ripple Frequency .................................................... 62 2.3 2.4 AC Characteristics ............................................................................................................... 63 2.3.1 Frequency .................................................................................................................... 63 2.3.2 Clock Timing ................................................................................................................ 66 2.3.3 Reset Timing ............................................................................................................... 70 2.3.4 Wakeup Time .............................................................................................................. 71 2.3.5 NMI and IRQ Noise Filter ............................................................................................ 74 2.3.6 Bus Timing ................................................................................................................... 75 2.3.7 I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing ................................ 82 2.3.8 CAC Timing ................................................................................................................. 83 2.3.9 SCI Timing ................................................................................................................... 84 2.3.10 SPI Timing ................................................................................................................... 90 2.3.11 QSPI Timing ................................................................................................................ 95 2.3.12 IIC Timing .................................................................................................................... 97 2.3.13 SSIE Timing ................................................................................................................. 99 2.3.14 SD/MMC Host Interface Timing ................................................................................. 101 2.3.15 CLKOUT Timing ........................................................................................................ 102 USB Characteristics ........................................................................................................... 103 2.4.1 USBFS Timing ........................................................................................................... 103 2.4.2 USB External Supply ................................................................................................. 104 2.5 ADC14 Characteristics ...................................................................................................... 105 2.6 DAC12 Characteristics ...................................................................................................... 115 2.7 TSN Characteristics ........................................................................................................... 117 2.8 OSC Stop Detect Characteristics ...................................................................................... 117 2.9 POR and LVD Characteristics ........................................................................................... 118 2.10 VBATT Characteristics ...................................................................................................... 122 2.11 CTSU Characteristics ........................................................................................................ 124 2.12 Segment LCD Controller Characteristics ........................................................................... 124 2.12.1 Resistance Division Method ...................................................................................... 124 2.12.2 Internal Voltage Boosting Method ............................................................................. 125 2.12.3 Capacitor Split Method .............................................................................................. 126 2.13 Comparator Characteristics ............................................................................................... 127 2.14 OPAMP Characteristics ..................................................................................................... 127 2.15 Flash Memory Characteristics ........................................................................................... 128 2.15.1 Code Flash Memory Characteristics ......................................................................... 128 2.15.2 Data Flash Memory Characteristics .......................................................................... 129 2.16 Boundary Scan .................................................................................................................. 130 2.17 Joint European Test Action Group (JTAG) ........................................................................ 131 2.17.1 Serial Wire Debug (SWD) .......................................................................................... 133 Appendix 1. Package Dimensions ........................................................................................................ 135 Features S3A1 Microcontroller Group Datasheet High efficiency 48-MHz Arm® Cortex®-M4 core, 1-MB code flash memory, 192-KB SRAM, Segment LCD Controller, Capacitive Touch Sensing Unit, USB 2.0 Full-Speed, 14-Bit A/D Converter, 12-Bit D/A Converter, security and safety features. Features ■ Arm Cortex-M4 Core with Floating Point Unit (FPU)       Armv7E-M architecture with DSP instruction set Maximum operating frequency: 48 MHz Support for 4-GB address space Arm Memory Protection Unit (MPU) with 8 regions Debug and Trace: ITM, DWT, FPB, TPIU, ETB CoreSight™ debug port: JTAG-DP and SW-DP ■ Memory        1-MB code flash memory 8-KB data flash memory (up to 100000 erase/write cycles) 192-KB SRAM Flash Cache (FCACHE) Memory Protection Units Memory Mirror Function 128-bit unique ID ■ Connectivity  USB 2.0 Full-Speed Module (USBFS) - On-chip transceiver with voltage regulator - Compliant with USB Battery Charging Specification 1.2  Serial Communications Interface (SCI) × 6 - UART - Simple IIC - Simple SPI  Serial Peripheral Interface (SPI) × 2  I2C bus interface (IIC) × 3  CAN module (CAN)  Serial Sound Interface Enhanced (SSIE)  SD/MMC Host Interface (SDHI)  Quad Serial Peripheral Interface (QSPI)  External address space - 8- or 16-bit bus space is selectable per area ■ Analog       14-Bit A/D Converter (ADC14) 12-Bit D/A Converter (DAC12) 8-Bit D/A Converter (DAC8) × 2 (for ACMPLP) Low Power Analog Comparator (ACMPLP) × 2 Operational Amplifier (OPAMP) × 4 Temperature Sensor (TSN) ■ Timers     General PWM Timer 32-Bit (GPT32) × 4 General PWM Timer 16-Bit (GPT16) × 6 Asynchronous General-Purpose Timer (AGT) × 2 Watchdog Timer (WDT) ■ Safety              ECC in SRAM SRAM parity error check Flash area protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO readback level detection Register write protection Main oscillator stop detection Illegal memory access R01DS0324EU0100 Rev.1.00 Oct 30, 2017 ■ System and Power Management         Low power modes Realtime Clock (RTC) with calendar and Battery Backup support Event Link Controller (ELC) DMA Controller (DMAC) × 4 Data Transfer Controller (DTC) Key Interrupt Function (KINT) Power-on reset Low voltage detection with voltage settings ■ Security and Encryption  AES128/256  GHASH  True Random Number Generator (TRNG) ■ Human Machine Interface (HMI)  Segment LCD Controller (SLCDC) - Up to 54 segments × 4 commons - Up to 50 segments × 8 commons  Capacitive Touch Sensing Unit (CTSU) ■ Multiple Clock Sources  Main clock oscillator (MOSC) (1 to 20 MHz when VCC = 2.4 to 5.5 V) (1 to 8 MHz when VCC = 1.8 to 2.4 V) (1 to 4 MHz when VCC = 1.6 to 1.8 V)  Sub-clock oscillator (SOSC) (32.768 kHz)  High-speed on-chip oscillator (HOCO) (24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V) (24, 32, 48 MHz when VCC = 1.8 to 5.5 V) (24, 32 MHz when VCC = 1.6 to 5.5 V)  Middle-speed on-chip oscillator (MOCO) (8 MHz)  Low-speed on-chip oscillator (LOCO) (32.768 kHz)  Independent watchdog timer OCO (15 kHz)  Clock trim function for HOCO/MOCO/LOCO  Clock out support ■ General Purpose I/O Ports  Up to 126 input/output pins - Up to 3 CMOS input - Up to 123 CMOS input/output - Up to 11 input/output 5 V tolerant - Up to 2 pins high current (20 mA) ■ Operating Voltage  VCC: 1.6 to 5.5 V ■ Operating Temperature and Packages  Ta = –40°C to +85°C - 145-pin LGA (7 mm × 7 mm, 0.5 mm pitch) - 121-pin BGA (8 mm × 8 mm, 0.65 mm pitch) - 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch)  Ta = –40°C to +105°C - 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch) - 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) - 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch) - 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch) Page 11 of 145 S3A1 Datasheet 1. 1. Overview Overview The S3A1 MCU group integrates multiple series of software- and pin-compatible Arm®-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. Each MCU provides an optimal combination of low-power, high-performance Arm Cortex®-M4 core running up to 48 MHz, with the following features:  1-MB code flash memory  192-KB SRAM  Segment LCD Controller (SLCDC)  Capacitive Touch Sensing Unit (CTSU)  USB 2.0 Full-Speed Module (USBFS)  14-bit A/D Converter (ADC14)  12-bit D/A Converter (DAC12)  Security features. 1.1 Function Outline Table 1.1 Arm core Feature Functional description Arm Cortex-M4  Maximum operating frequency: up to 48 MHz  Arm Cortex-M4 - Revision: r0p1-01rel0 - Armv7E-M architecture profile - Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.  Arm Memory Protection Unit (MPU) - Armv7 Protected Memory System Architecture - 8 protect regions.  SysTick timer - Driven by LOCO clock. Table 1.2 Memory Feature Functional description Code flash memory Maximum 1-MB code flash memory. See section 47, Flash Memory in the User’s Manual. Data flash memory 8-KB data flash memory. See section 47, Flash Memory in the User’s Manual. Option-setting memory The option-setting memory determines the state of the MCU after a reset. See section 7, Option-Setting Memory in the User’s Manual. Memory Mirror Function (MMF) The MMF can be configured to mirror the target application image load address in code flash memory to the application image link address in the 23-bit unused memory space (memory mirror space addresses). Your application code is developed and linked to run from this MMF destination address. The application code does not need to know the load location where it is stored in code flash memory. See section 5, Memory Mirror Function (MMF) in the User’s Manual. SRAM On-chip high-speed SRAM providing either parity bit or Error Correction Code (ECC). The first 16 KB in SRAM0 provides error correction capability using ECC. See section 46, SRAM in the User’s Manual. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 12 of 145 S3A1 Datasheet Table 1.3 1. Overview System (1 of 2) Feature Functional description Operating modes Two operating modes:  Single-chip mode  SCI/USB boot mode. See section 3, Operating Modes in the User’s Manual. Resets 14 resets:  RES pin reset  Power-on reset  VBATT-selected voltage power-on reset  Independent watchdog timer reset  Watchdog timer reset  Voltage monitor 0 reset  Voltage monitor 1 reset  Voltage monitor 2 reset  SRAM parity error reset  SRAM ECC error reset  Bus master MPU error reset  Bus slave MPU error reset  Stack pointer error reset  Software reset. See section 6, Resets in the User’s Manual. Low Voltage Detection (LVD) Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and the detection level can be selected using a software program. See section 8, Low Voltage Detection (LVD) in the User’s Manual. Clocks  Main clock oscillator (MOSC)  Sub-clock oscillator (SOSC)  High-speed on-chip oscillator (HOCO)  Middle-speed on-chip oscillator (MOCO)  Low-speed on-chip oscillator (LOCO)  PLL frequency synthesizer  Independent watchdog timer on-chip oscillator  Clock out support. See section 9, Clock Generation Circuit in the User’s Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The Clock Frequency Accuracy Measurement Circuit (CAC) checks the system clock frequency with a reference clock signal by counting the number of pulses of the system clock to be measured. The reference clock can be provided externally through a CACREF pin or internally from various on-chip oscillators. Event signals can be generated when the clock does not match or measurement ends. This feature is particularly useful in implementing a fail-safe mechanism for home and industrial automation applications. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in the User’s Manual. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt Controller Unit (ICU) in the User’s Manual. Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function (KINT) in the User’s Manual. Low power modes Power consumption can be reduced in multiple ways, such as by setting clock dividers, controlling EBCLK output, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 11, Low Power Modes in the User’s Manual. Battery backup function A battery backup function is provided for partial powering by a battery. The battery powered area includes the RTC, SOSC, LOCO, wakeup control, backup memory, VBATT_R low voltage detection, and switch between VCC and VBATT. During normal operation, the battery powered area is powered by the main power supply, which is the VCC pin. When a VCC voltage drop is detected, the power source is switched to the dedicated battery backup power pin, the VBATT pin. When the voltage rises again, the power source is switched from the VBATT pin to the VCC pin. See section 12, Battery Backup Function in the User’s Manual. Register write protection The register write protection function protects important registers from being overwritten because of software errors. See section 13, Register Write Protection in the User’s Manual. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 13 of 145 S3A1 Datasheet Table 1.3 1. Overview System (2 of 2) Feature Functional description Memory Protection Unit (MPU) Four MPUs and a CPU stack pointer monitor function are provided for memory protection. See section 16, Memory Protection Unit (MPU) in the User’s Manual. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A refresh-permitted period can be set to refresh the counter and used as the condition for detecting when the system runs out of control. See section 26, Watchdog Timer (WDT) in the User’s Manual. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. It can be used to reset the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the count value in the registers. See section 27, Independent Watchdog Timer (IWDT) in the User’s Manual. Table 1.4 Event link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 19, Event Link Controller (ELC) in the User’s Manual. Table 1.5 Direct memory access Feature Functional description Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an interrupt request. See section 18, Data Transfer Controller (DTC) in the User’s Manual. DMA Controller (DMAC) A 4-channel DMA Controller (DMAC) module is provided for transferring data without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. See section 17, DMA Controller (DMAC) in the User’s Manual. Table 1.6 External bus interface Feature Functional description External bus  CS area: Connected to the external devices (external memory interface)  QSPI area: Connected to the QSPI (external device interface). R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 14 of 145 S3A1 Datasheet Table 1.7 1. Overview Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 4 channels and a 16-bit timer with 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a general-purpose timer. See section 23, General PWM Timer (GPT) in the User’s Manual. Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT) output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in the User’s Manual. Asynchronous General Purpose Timer (AGT) The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting of external events. This 16-bit timer consists of a reload register and a down-counter. The reload register and the down-counter are allocated to the same address, and they can be accessed with the AGT register. See section 24, Asynchronous General Purpose Timer (AGT) in the User’s Manual. Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count mode, that are controlled by the register settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count mode can be used for calendars other than the Gregorian (Western) calendar. See section 25, Realtime Clock (RTC) in the User’s Manual. Table 1.8 Communication interfaces (1 of 2) Feature Functional description Serial Communications Interface (SCI) The Serial Communication Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:  Asynchronous interfaces (UART and asynchronous communications interface adapter (ACIA))  8-bit clock synchronous interface  Simple IIC (master-only)  Simple SPI  Smart card interface. The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. SCI0 and SCI1 have FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. See section 29, Serial Communications Interface (SCI) in the User’s Manual. I2C Bus Interface (IIC) The 3-channel IIC module conforms with and provides a subset of the NXP I2C bus (InterIntegrated Circuit bus) interface functions. See section 30, I2C Bus Interface (IIC) in the User’s Manual. Serial Peripheral Interface (SPI) Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, fullduplex synchronous serial communications with multiple processors and peripheral devices. See section 32, Serial Peripheral Interface (SPI) in the User’s Manual. Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with digital audio devices for transmitting PCM audio data over a serial bus with the MCU. The SSIE supports an audio clock frequency of up to 25 MHz, and can be operated as a slave or master receiver/transmitter/transceiver to suit various applications. The SSIE includes 8-stage FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception and transmission. See section 35, Serial Sound Interface Enhanced (SSIE) in the User’s Manual. Quad Serial Peripheral Interface (QSPI) The QSPI is a memory controller for connecting a serial ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has an SPI-compatible interface. See section 33, Quad Serial Peripheral Interface (QSPI) in the User’s Manual. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 15 of 145 S3A1 Datasheet Table 1.8 1. Overview Communication interfaces (2 of 2) Feature Functional description Controller Area Network (CAN) Module The Controller Area Network (CAN) module provides functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagnetically noisy applications. The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. See section 31, Controller Area Network (CAN) Module in the User’s Manual. USB 2.0 Full-Speed Module (USBFS) The USBFS is a USB controller that can operate as a host controller or device controller. The module supports full-speed and low-speed (only for the host controller) transfer as defined in the Universal Serial Bus specification 2.0. The module has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus specification 2.0. The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned any endpoint number based on the peripheral devices used for communication or based on the your system. The MCU supports revision 1.2 of the Battery Charging specification. Because the MCU can be powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply at 3.3 V. See section 28, USB 2.0 Full-Speed Module (USBFS) in the User’s Manual. SD/MMC Host Interface (SDHI) The Secure Digital Host Interface (SDHI) and MultiMediaCard (MMC) interface provide the functionality needed to connect a variety of external memory cards to the MCU. The SDHI supports both 1-bit and 4-bit buses for connecting different memory cards that support SD, SDHC, and SDXC formats. When developing host devices that are compliant with the SD specifications, you must comply with the SD Host/Ancillary Product License Agreement (SD HALA). The MMC interface supports 1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84-B451) device access. This interface also provides backward compatibility and support for high-speed SDR transfer modes. See section 36, SD/MMC Host Interface (SDHI) in the User’s Manual. Table 1.9 Analog Feature Functional description 14-bit A/D Converter (ADC14) A 14-bit successive approximation A/D converter is provided. Up to 28 analog input channels are selectable. Temperature sensor output and internal reference voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution in generating a digital value. See section 38, 14-Bit A/D Converter (ADC14) in the User’s Manual. 12-bit D/A Converter (DAC12) The 12-bit D/A converts data and includes an output amplifier. See section 39, 12-Bit D/A Converter (DAC12) in the User’s Manual. 8-bit D/A Converter (DAC8) (for ACMPLP) The 8-bit D/A converts data and does not include an output amplifier (DAC8). The DAC8 is used only as the reference voltage for ACMPLP. See section 43, 8-Bit D/A Converter (DAC8) in the User’s Manual. Temperature Sensor (TSN) The on-chip temperature sensor determines and monitors the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. The output voltage is provided to the ADC14 for conversion and can be further used by the end application. See section 40, Temperature Sensor (TSN) in the User’s Manual. Low-Power Analog Comparator (ACMPLP) The analog comparator compares the reference input voltage and analog input voltage. The comparison result can be read through software and also be output externally. The reference input voltage can be selected from an input to the CMPREFi (i = 0, 1) pin, an internal 8-bit D/A converter output, or the internal reference voltage (Vref) generated internally in the MCU. The ACMPLP response speed can be set before starting an operation. Setting the High-speed mode decreases the response delay time, but increases current consumption. Setting the Low-speed mode increases the response delay time, but decreases current consumption. See section 42, Low Power Analog Comparator (ACMPLP) in the User’s Manual. Operational Amplifier (OPAMP) The operational amplifier amplifies small analog input voltages and outputs the amplified voltages. A total of four differential operational amplifier units with two input pins and one output pin are provided. See section 41, Operational Amplifier (OPAMP) in the User’s Manual. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 16 of 145 S3A1 Datasheet Table 1.10 1. Overview Human machine interfaces Feature Functional description Segment LCD Controller (SLCDC) The SLCDC provides the following functions:  Waveform A or B selectable  The LCD driver voltage generator can switch between an internal voltage boosting method, a capacitor split method, and an external resistance division method  Automatic output of segment and common signals based on automatic display data register read  The reference voltage generated when operating the voltage boost circuit can be selected in 16 steps (contrast adjustment)  The LCD can be made to blink. See section 48, Segment LCD Controller (SLCDC) in the User’s Manual. Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor is usually enclosed with an electrical insulator so that fingers do not come into direct contact with the electrodes. See section 44, Capacitive Touch Sensing Unit (CTSU) in the User’s Manual. Table 1.11 Data processing Feature Functional description Cyclic Redundancy Check (CRC) Calculator The CRC calculator generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication. Additionally, various CRC-generating polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This function is useful in applications that require CRC code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See section 34, Cyclic Redundancy Check (CRC) Calculator in the User’s Manual. Data Operation Circuit (DOC) The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 45, Data Operation Circuit (DOC) in the User’s Manual. Table 1.12 Security Feature Functional description Secure Crypto Engine 5 (SCE5)  Security algorithm: - Symmetric algorithm: AES  Other support features: - TRNG (True Random Number Generator) - Hash-value generation: GHASH. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 17 of 145 S3A1 Datasheet 1.2 1. Overview Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Bus Memory 1 MB Code Flash External Arm Cortex-M4 DSP System FPU POR/LVD MOSC/SOSC CSC 8 KB Data Flash Clocks MPU Reset (H/M/L) OCO 192 KB SRAM NVIC Mode Control PLL System Timer Power Control CAC Test and DBG Interface ICU Battery Backup KINT Register Write Protection MPU DMA DTC DMAC × 4 Timers Communication interfaces GPT32 × 4 SCI × 6 GPT16 × 6 SDHI ×1 SPI × 2 CAN × 1 SSIE × 1 USBFS with BC1.2 RTC WDT/IWDT QSPI IIC × 3 AGT × 2 Event Link Human machine interfaces CTSU Data Processing SLCDC Analog ELC CRC ADC14 TSN OPAMP × 4 Security DOC DAC12 DAC8 ACMPLP × 2 SCE5 Figure 1.1 Block diagram R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 18 of 145 S3A1 Datasheet 1.3 1. Overview Part Numbering Figure 1.2 shows the product part number information, including memory capacity, and package type. Table 1.14 shows a product list. R 7 F S 3 A1 7 C 3 A 0 1 C F B #AA 0 Production identification code Packing, Terminal material (Pb-free) #AA: Tray/Sn (Tin) only #AC: Tray/others Package type BJ: BGA 121 pins FB: LQFP 144 pins FP: LQFP 100 pins FM: LQFP 64 pins LK: LGA 145 pins LJ: LGA 100 pins NB: QFN 64 pins Quality ID Software ID Operating temperature 2: -40° C to 85° C 3: -40° C to 105° C Code flash memory size C: 1 MB Feature set 7: Superset Group name A1: S3A1 Group, Arm Cortex-M4, 48 MHz Series name 3: High efficiency Renesas Synergy family Flash memory Renesas microcontroller Renesas Figure 1.2 Table 1.13 Part numbering scheme Product list Operating temperature Product part number Ordering part number Package code Code flash Data flash SRAM R7FS3A17C2A01CLK R7FS3A17C2A01CLK#AC0 PTLG0145KA-A 1 MB 8 KB 192 KB R7FS3A17C3A01CFB R7FS3A17C3A01CFB#AA0 PLQP0144KA-B -40 to +105°C R7FS3A17C2A01CBJ R7FS3A17C2A01CBJ#AC0 PLBG0121JA-A -40 to +85°C -40 to +85°C R7FS3A17C3A01CFP R7FS3A17C3A01CFP#AA0 PLQP0100KB-B -40 to +105°C R7FS3A17C2A01CLJ R7FS3A17C2A01CLJ#AC0 PTLG0100JA-A -40 to +85°C R7FS3A17C3A01CFM R7FS3A17C3A01CFM#AA0 PLQP0064KB-C -40 to +105°C R7FS3A17C3A01CNB R7FS3A17C3A01CNB#AC0 PWQN0064LA-A -40 to +105°C R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 19 of 145 S3A1 Datasheet 1.4 1. Overview Function Comparison Table 1.14 Function comparison Parts number R7FS3A17C2A01CLK R7FS3A17C3A01CFB R7FS3A17C2A01CBJ R7FS3A17C3A01CFP R7FS3A17C2A01CLJ R7FS3A17C3A01CFM/ R7FS3A17C3A01CNB Pin count 145 144 121 100 100 64 Package LGA LQFP BGA LQFP LGA LQFP/QFN 1 MB Code flash memory 8 KB Data flash memory 192 KB SRAM 176 KB Parity 16 KB ECC System 48 MHz CPU clock 512 bytes Backup registers Yes ICU KINT 8 Event control ELC Yes DMA DTC Yes 4 DMAC 16-bit bus 8-bit bus Bus External bus Timers GPT32 4 GPT16 6 Communication AGT 2 RTC Yes WDT/IWDT Yes 6 SCI 3 IIC 2 2 SPI SSIE 1 No QSPI 1 No SDHI 1 Yes USBFS 28 ADC14 26 1 DAC8 2 OPAMP 18 2 4 4 4 SLCDC CTSU CRC DOC Security R01DS0324EU0100 Rev.1.00 Oct 30, 2017 4 4 3 Yes TSN Data processing 25 DAC12 ACMPLP HMI No 1 CAN Analog No 4 com × 50 seg and 4 com/seg 4 com × 42 seg and 4 com/seg 4 com × 34 seg and 4 com/seg 27 4 com × 17 seg and 4 com/seg 24 Yes Yes SCE5 Page 20 of 145 S3A1 Datasheet 1.5 1. Overview Pin Functions Function Signal I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-μF capacitor. The capacitor should be placed close to the pin. VCL Input Connect this pin to the VSS pin by the smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect to the system power supply (0 V). VBATT Input Backup power pin XTAL Output EXTAL Input Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. Clock XCIN Input XCOUT Output Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCOUT and XCIN. EBCLK Output Outputs the external bus clock for external devices CLKOUT Output Clock output pin Operating mode control MD Input Pins for setting the operating mode. The signal levels on these pins must not be changed during operation mode transition on release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin Interrupt NMI Input Non-maskable interrupt request pin IRQ0 to IRQ15 Input Maskable interrupt request pins KINT KR00 to KR07 Input A key interrupt can be generated by inputting a falling edge to the key interrupt input pins On-chip debug TMS I/O On-chip emulator or boundary scan pins TDI Input External bus interface Battery backup TCK Input TDO Output SWDIO I/O Serial wire debug data input/output pin SWCLK Input Serial wire clock pin SWO Output Serial wire trace output pin RD Output Strobe signal indicating that reading from the external bus interface space is in progress, active-low WR Output Strobe signal indicating that writing to the external bus interface space is in progress, in 1-write strobe mode, active-low WR0, WR1 Output Strobe signals indicating that either group of data bus pins (D07 to D00, D15 to D08) is valid in writing to the external bus interface space, in byte strobe mode, active-low BC0, BC1 Output Strobe signals indicating that either group of data bus pins (D07 to D00, D15 to D08) is valid in access to the external bus interface space, in 1-write strobe mode, active-low ALE Output Address latch signal when address/data multiplexed bus is selected WAIT Input Input pin for wait request signals in access to the external space, active-low CS0 to CS3 Output Select signals for CS areas, active-low A00 to A23 Output Address bus D00 to D15 I/O Data bus VBATWIO0 to VBATWIO2 I/O Output wakeup signal for the VBATT wakeup control function. External event input for the VBATT wakeup control function. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 21 of 145 S3A1 Datasheet 1. Overview Function Signal I/O Description GPT GTETRGA, GTETRGB Input External trigger input pin GTIOC0A to GTIOC9A, GTIOC0B to GTIOC9B I/O Input capture, Output capture, or PWM output pin GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase) AGT RTC SCI IIC SSIE SPI GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase) GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase) GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase) GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase) GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase) AGTEE0, AGTEE1 Input External event input enable AGTIO0, AGTIO1 I/O External event input and pulse output AGTO0, AGTO1 Output Pulse output AGTOA0, AGTOA1 Output Output compare match A output AGTOB0, AGTOB1 Output Output compare match B output RTCOUT Output Output pin for 1-Hz/64-Hz clock RTCIC0 to RTCIC2 Input Time capture event input pins SCK0 to SCK4, SCK9 I/O Input/output pins for the clock (clock synchronous mode) RXD0 to RXD4, RXD9 Input Input pins for received data (asynchronous mode/clock synchronous mode) TXD0 to TXD4, TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous mode) CTS0_RTS0 to CTS4_RTS4, CTS9_RTS9 I/O Input/output pins for controlling the start of transmission and reception (asynchronous mode/clock synchronous mode), active-low SCL0 to SCL4, SCL9 I/O Input/output pins for the I2C clock (simple IIC) SDA0 to SDA4, SDA9 I/O Input/output pins for the I2C data (simple IIC) SCK0 to SCK4, SCK9 I/O Input/output pins for the clock (simple SPI) MISO0 to MISO4, MISO9 I/O Input/output pins for slave transmission of data (simple SPI) MOSI0 to MOSI4, MOSI9 I/O Input/output pins for master transmission of data (simple SPI) Slave-select input pins (simple SPI), active-low SS0 to SS4, SS9 Input SCL0 to SCL2 I/O Input/output pins for clock SDA0 to SDA2 I/O Input/output pins for data SSIBCK0 I/O SSIE serial bit clock pin SSILRCK0/SSIFS0 I/O Word select pins SSITXD0 Output Serial data output pins SSIRXD0 Input Serial data input pins AUDIO_CLK Input External clock pin for audio (input oversampling clock) RSPCKA, RSPCKB I/O Clock input/output pin MOSIA, MOSIB I/O Input/output pins for data output from the master MISOA, MISOB I/O Input/output pins for data output from the slave SSLA0, SSLB0 I/O Input/output pins for slave selection SSLA1, SSLA2, SSLA3, SSLB1, SSLB2, SSLB3 Output Output pins for slave selection R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 22 of 145 S3A1 Datasheet 1. Overview Function Signal I/O Description QSPI QSPCLK Output QSPI clock output pin CAN USBFS SDHI Analog power supply QSSL Output QSPI slave output pin QIO0 I/O Master transmit data/data 0 QIO1 I/O Master input data/data 1 QIO2, QIO3 I/O Data 2, Data 3 CRX0 Input Receive data CTX0 Output Transmit data VSS_USB Input Ground pins VCC_USB_LDO Input Power supply pin for USB LDO regulator VCC_USB I/O Input: Power supply pin for USB transceiver. Output: USB LDO regulator output pin. This pin should be connected to an external capacitor. USB_DP I/O D+ I/O pin of the USB on-chip transceiver. This pin should be connected to the D+ pin of the USB bus. USB_DM I/O D– I/O pin of the USB on-chip transceiver. This pin should be connected to the D– pin of the USB bus. USB_VBUS Input USB cable connection monitor pin. This pin should be connected to VBUS on the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a device controller. USB_EXICEN Output Low power control signal for external power supply (OTG) chip USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip USB_OVRCURA, USB_OVRCURB Input Connect the external overcurrent detection signals to these pins. Connect the VBUS comparator signals to these pins when the OTG power supply chip is connected. USB_ID Input Connect the MicroAB connector ID input signal to this pin during operation in OTG mode SD0CLK Output SD clock output pin SD0CMD I/O SD command output, response input signal pin SD0DAT0 to SD0DAT7 I/O SD data bus pins SD0CD Input SD card detection pin SD0WP Input SD write-protect signal AVCC0 Input Analog voltage supply pin AVSS0 Input Analog voltage supply ground pin VREFH0 Input Analog reference voltage supply pin VREFL0 Input Reference power supply ground pin VREFH Input Analog reference voltage supply pin for D/A converter Analog reference ground pin for D/A converter VREFL Input AN000 to AN027 Input Input pins for the analog signals to be processed by the A/D converter ADTRG0 Input Input pins for the external trigger signals that start the A/D conversion, active-low DAC12 DA0 Output Output pins for the analog signals to be processed by the D/A converter Comparator output VCOUT Output Comparator output pin ACMPLP CMPREF0, CMPREF1 Input Reference voltage input pins CMPIN0, CMPIN1 Input Analog voltage input pins OPAMP AMP0+ to AMP3+ Input Analog voltage input pins AMP0- to AMP3- Input Analog voltage input pins AMP0O to AMP3O Output Analog voltage output pins TS00 to TS13, TS17 to TS22, TS27 to TS31, TS34, TS35 Input Capacitive touch detection pins (touch pins) TSCAP — Secondary power supply pin for the touch driver ADC14 CTSU R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 23 of 145 S3A1 Datasheet 1. Overview Function Signal I/O Description I/O ports P000 to P015 I/O General-purpose input/output pins SLCDC P100 to P115 I/O General-purpose input/output pins P200 Input General-purpose input pin P201 to P206, P212, P213 I/O General-purpose input/output pins P214, P215 Input General-purpose input pins P300 to P315 I/O General-purpose input/output pins P400 to P415 I/O General-purpose input/output pins P500 to P507, P511, P512 I/O General-purpose input/output pins P600 to P606, P608 to P614 I/O General-purpose input/output pins P700 to P705, P708 to P713 I/O General-purpose input/output pins P800 to P809 I/O General-purpose input/output pins P900 to P902, P914, P915 I/O General-purpose input/output pins VL1, VL2, VL3, VL4 I/O Voltage pin for driving the LCD CAPH, CAPL I/O Capacitor connection pin for the LCD controller/driver COM0 to COM7 Output Common signal output pins for the LCD controller/driver SEG00 to SEG53 Output Segment signal output pins for the LCD controller/driver R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 24 of 145 S3A1 Datasheet 1.6 1. Overview Pin Assignments Figure 1.3 to Figure 1.9 show the pin assignments. R7FS3A17C2A01CLK 13 12 A B C D E P407 P409 P412 P708 P711 P410 P414 P915/ P914/ USB_DM USB_DP F G H J K L M N VCC P212 /EXTAL P215 /XCIN VCL P702 P405 P402 P400 13 P710 VSS P213 /XTAL P214 /XCOUT VBATT P701 P404 P511 VCC 12 11 VCC_ USB VSS_ USB VCC_ USB_LDO P411 P415 P712 P705 P704 P703 P403 P401 P512 VSS 11 10 P205 P206 P204 P408 P413 P709 P713 P700 P406 P003 P000 P002 P001 10 9 P203 P313 P202 P314 P004 P006 P009 P008 9 8 P900 P901 P200 P315 P005 AVSS0 P011 P010 /VREFL0 /VREFH0 8 7 VSS P902 RES P310 P007 AVCC0 P013 /VREFL P012 /VREFH 7 6 VCC P201/MD P312 P305 P505 P506 P015 P014 6 5 P309 P311 P308 P303 NC P503 P504 VSS VCC 5 4 P307 P306 P304 P109/TDO /SWO P114 P608 P604 P600 P105 P500 P502 P501 P507 4 3 P808 P809 P301 P112 P115 P610 P614 P603 P107 P106 P104 P803 P802 3 2 P302 P300/TCK /SWCLK P111 P806 P609 P612 VSS P605 P601 P805 P800 P101 P801 2 P108/TMS P110/TDI /SWDIO P113 P807 P611 P613 VCC P606 P602 P804 P103 P102 P100 1 C D E F G H J K L 1 A Figure 1.3 B M N Pin assignment for 145-pin LGA (top view) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 25 of 145 VSS VCC P614 P613 P612 P611 P610 P609 P608 P807 P806 P115 P114 P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO 91 90 89 88 87 85 83 81 79 76 75 74 73 P606 92 77 P604 P605 94 78 P602 P603 96 80 P601 97 82 P805 P600 99 84 P804 100 86 P107 101 93 P106 102 95 P104 P105 104 98 P102 P103 103 P101 106 105 P100 107 1. Overview 108 S3A1 Datasheet P800 109 72 P300/TCK/SWCLK P801 110 71 P301 P802 111 70 P302 P803 112 69 P303 P500 113 68 P501 114 67 P809 P808 P502 P503 115 66 P304 116 65 P305 P504 117 64 P306 P505 118 63 P307 P506 119 62 P308 P507 120 61 P309 VCC 121 60 P310 VSS 122 59 P311 P015 123 58 P312 P014 124 57 P013/VREFL P012/VREFH 125 56 P200 P201/MD 55 RES AVCC0 127 54 VCC AVSS0 128 53 VSS P011/VREFL0 129 52 P902 P010VREFH0 130 51 P901 P009 P008 131 50 P900 132 49 P315 P007 133 48 P006 134 47 P314 P313 P005 135 46 P004 136 45 P202 P203 P003 137 44 P204 P002 138 43 P205 P001 P000 139 42 P206 140 41 VCC_USB_LDO VSS VCC P512 141 40 142 39 143 38 VCC_USB P914/USB_DP P915/USB_DM P511 144 37 VSS_USB Figure 1.4 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 P704 P705 VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P713 P712 P711 P710 P709 P708 P415 P414 P413 P412 P411 P410 P409 P408 P407 10 9 P701 P702 5 P404 P405 8 4 P403 7 3 P402 P406 P700 2 P401 6 1 P400 P703 R7FS3A17C3A01CFB 126 Pin assignment for 144-pin LQFP (top view) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 26 of 145 S3A1 Datasheet 1. Overview R7FS3A17C2A01CBJ 11 10 Figure 1.5 A B C D E F G H J K L P407 P408 P411 P414 P212/ EXTAL P215/ XCIN VCL P406 P403 P401 P400 11 P410 P415 P213/ XTAL P214/ XCOUT VBATT P405 P402 P511 P512 10 P915/ P914/ USB_DM USB_DP 9 VCC_ USB VSS_ USB P409 P412 P708 VCC VSS P404 P002 P001 P000 9 8 P205 VCC_ USB_ LDO P206 P204 P413 P710 P702 P006 P004 P003 P005 8 7 P203 P202 P313 P314 P315 P709 P701 P007 AVSS0 P011/ P010/ 7 VREFL0 VREFH0 6 VSS VCC RES P201/MD P200 NC P700 P008 AVCC0 P013/ VREFL P012/ VREFH 6 5 P308 P309 P307 P302 P304 P612 P601 P506 P505 P015 P014 5 4 P305 P306 P808 P114 P611 P603 P600 P504 P503 VSS VCC 4 3 P809 P303 P110/TDI P111 P609 P604 P106 P104 P502 P500 P501 3 2 P301 P108/ TMS/ SWDIO P113 P608 P613 P605 P602 P105 P102 P801 P800 2 1 P300/ TCK/ SWCLK P109/ TDO/ SWO P112 P115 P610 VCC VSS P107 P103 P101 P100 1 A B C D E F G H J K L Pin assignment for 121-pin BGA (top view) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 27 of 145 Figure 1.6 P100 P101 P102 P103 P104 P105 P106 P107 P600 P601 P602 P603 VSS VCC P610 P609 P608 P115 P114 P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1. Overview 75 S3A1 Datasheet P500 76 50 P501 77 49 P300/TCK/SWCLK P301 P502 78 48 P302 P503 79 47 P303 P504 80 46 P809 P505 81 45 P808 VCC 82 44 P304 VSS 83 43 P305 P015 84 42 P306 P014 85 41 P307 P013/VREFL 86 40 P200 P012/VREFH 87 39 P201/MD AVCC0 88 38 RES AVSS0 89 37 VCC P011/VREFL0 90 36 VSS P010/VREFH0 91 35 P202 P008 92 34 P203 P007 93 33 P204 P006 94 32 P205 P005 95 31 P206 P004 96 30 VCC_USB_LDO P003 97 29 VCC_USB P002 98 28 P914/USB_DP P001 99 27 P915/USB_DM P000 100 26 VSS_USB 14 15 16 17 18 19 20 21 22 23 24 25 P212/EXTAL VCC P708 P415 P414 P413 P412 P411 P410 P409 P408 P407 9 VCL 13 8 VBATT P213/XTAL 7 P406 12 6 P405 VSS 5 P404 11 4 P403 P214/XCOUT 3 P402 10 2 P401 P215/XCIN 1 P400 R7FS3A17C3A01CFP Pin assignment for 100-pin LQFP (top view) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 28 of 145 S3A1 Datasheet 1. Overview R7FS3A17C2A01CLJ 10 9 Figure 1.7 A B C D E F G H J K P407 P409 P412 VCC P212/ EXTAL P215/ XCIN VCL P403 P400 P000 10 P413 VSS P213/ XTAL P214/ XCOUT VBATT P405 P401 P001 9 P915/ P914/ USB_DM USB_DP 8 VCC_ USB VSS_ USB VCC_US B_LDO P411 P415 P708 P404 P003 P004 P002 8 7 P205 P204 P206 P408 P414 P406 P006 P007 P008 P005 7 6 VSS VCC P202 P203 P410 P402 P505 AVSS0 P011/ P010/ 6 VREFL0 VREFH0 5 P200 P201/MD P307 RES P113 P600 P504 AVCC0 P013/ VREFL P012/ VREFH 5 4 P305 P304 P808 P306 P115 P601 P503 P100 P015 P014 4 3 P809 P303 P110/TDI P111 P609 P602 P107 P103 VSS VCC 3 2 P300/ TCK/ SWCLK P302 P301 P114 P610 P603 P106 P101 P501 P502 2 1 P108/ TMS/ SWDIO P109/ TDO/ SWO P112 P608 VCC VSS P105 P104 P102 P500 1 A B C D E F G H J K Pin assignment for 100-pin LGA (top view) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 29 of 145 Figure 1.8 P100 P101 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1. Overview 48 S3A1 Datasheet P500 49 32 P300/TCK/SWCLK P501 50 31 P301 P502 51 30 P302 P015 52 29 P303 P014 53 28 P304 P013/VREFL 54 27 P200 P012/VREFH 55 26 P201/MD AVCC0 56 25 RES AVSS0 57 24 P204 P011/VREFL0 58 23 P205 P010/VREFH0 59 22 P206 P004 60 21 VCC_USB_LDO P003 61 20 VCC_USB P002 62 19 P914/USB_DP P001 63 18 P915/USB_DM P000 64 17 VSS_USB 8 9 10 11 12 13 14 15 16 P213/XTAL P212/EXTAL VCC P411 P410 P409 P408 P407 VCL VSS 5 VBATT 7 4 P402 6 3 P401 P215/XCIN 2 P214/XCOUT 1 P400 R7FS3A17C3A01CFM Pin assignment for 64-pin LQFP (top view) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 30 of 145 33 34 35 36 37 38 39 40 41 42 43 44 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO 45 46 47 P100 P101 1. Overview 48 S3A1 Datasheet P500 P501 P502 P015 P014 P013/VREFL P012/VREFH AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P004 P003 P002 P001 49 32 50 31 58 23 59 22 60 21 61 20 62 19 63 18 P300/TCK/SWCLK P301 P302 P303 P304 P200 P201/MD RES P204 P205 P206 VCC_USB_LDO VCC_USB P914/USB_DP P915/USB_DM 51 30 52 29 53 28 54 27 55 26 P000 64 17 VSS_USB 24 16 15 14 13 12 11 10 9 8 7 6 5 4 25 P400 P401 P402 VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P409 P408 P407 3 R7FS3A17C3A01CNB 1 57 2 56 Figure 1.9 Pin assignment for 64-pin QFN (top view) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 31 of 145 S3A1 Datasheet Pin Lists N13 1 L11 1 J10 1 1 CACREF IRQ0 P400 - AGTIO1 - GTIOC6A - L11 2 K11 2 J9 2 2 - IRQ5 P401 - - M1 3 3 J10 3 F6 3 3 VBATWIO0 IRQ4 P402 - AGTIO0/ AGTIO1 - K11 4 J11 4 H10 - - VBATWIO1 - P403 - AGTIO0/ AGTIO1 GTIOC3A RTCIC1 GTETRGA GTIOC6B - RTCIC0 - SCK1 SCK4 CTSU SLCDC ACMPLP ADC14 SDHI SSIE HMI DAC12, OPAMP Analog SPI/QSPI IIC SCI USBFS, CAN RTC GPT GPT_OPS, POEG Communication interfaces AGT I/O port External bus Timers Power, System, Clock, Debug, CAC, VBATT QFN64 LQFP64 LGA100 LQFP100 BGA121 LQFP144 LGA145 Pin number Interrupt 1.7 1. Overview SCL0 - AUDIO_C LK - - - SEG4 TS20 CTX0 TXD1/ SDA0 MOSI1 /SDA1 CTS4_ RTS4/ SS4 - - - - - - SEG5 TS19 CRX0 RXD1/ MISO1 /SCL1 - - - - - - SEG6 TS18 - CTS1_ RTS1/ SS1 - SSIBCK0 - - - - - TS17 L12 5 H9 5 G8 - - VBATWIO2 - P404 - - - GTIOC3B RTCIC2 - - - - SSILRCK0 /SSIFS0 - - - - - L13 6 H10 6 H9 - - - - P405 - - - GTIOC1A - - - - - SSITXD0 - - - - - - J10 7 H11 7 F7 - - - - P406 - - - GTIOC1B - - - - SSLA3 SSIRXD0 - - - - - - H10 8 G6 - - - - - - P700 - - - GTIOC5A - - - - MISOA - - - - - - - K12 9 G7 - - - - - - P701 - - - GTIOC5B - - - - MOSIA - - - - - - - K13 10 G8 - - - - - - P702 - - - GTIOC6A - - - - RSPCKA - - - - - - - J11 11 - - - - - - - P703 - - - GTIOC6B - - - - SSLA0 - - - - VCOUT - - H11 12 - - - - - - - P704 - AGTO0 - - - - - - SSLA1 - - - - - - - G11 13 - - - - - - - P705 - AGTIO0 - - - - - - SSLA2 - - - - - - - J12 14 G10 8 G9 4 4 VBATT - - - - - - - - - - - - - - - - - - J13 15 G11 9 G10 5 5 VCL - - - - - - - - - - - - - - - - - - H13 16 F11 10 F10 6 6 XCIN - P215 - - - - - - - - - - - - - - - - H12 17 F10 11 F9 7 7 XCOUT - P214 - - - - - - - - - - - - - - - - F12 18 G9 12 D9 8 8 VSS - - - - - - - - - - - - - - - - - - G12 19 E10 13 E9 9 9 XTAL IRQ2 P213 - - GTETRGA GTIOC0A - - TXD1/ MOSI1 /SDA1 - - - - - - - - G13 20 E11 14 E10 10 10 EXTAL IRQ3 P212 - AGTEE1 GTETRGB GTIOC0B - - RXD1/ MISO1 /SCL1 - - - - - - - - F13 21 F9 15 D10 11 11 VCC - - - - - - - - - - - - - - - G10 22 - - - - - - - P713 - AGTOA0 - GTIOC2A - - - - - - - - - - - - F11 23 - - - - - - - P712 - AGTOB0 - GTIOC2B - - - - - - - - - - - - E13 24 - - - - - - - P711 AGTEE0 - - - - CTS1_ RTS1/ SS1 - - - - - - - - E12 25 F8 - - - - - - P710 A17 - - - - - SCK1 - - - - - - - - - F10 26 F7 - - - - - IRQ10 P709 - - - - - - TXD1/ MOSI1 /SDA1 - - - - - - - - D13 27 E9 16 F8 - - - IRQ11 P708 - - - - - - RXD1/ MISO1 /SCL1 SSLA3 - - - - - - - E11 28 D10 17 E8 - - - IRQ8 P415 - - - GTIOC0A - - - - SSLA2 - SD0CD - - - - - D12 29 D11 18 E7 - - - IRQ9 P414 - - - GTIOC0B - - - - SSLA1 - SD0WP - - - - - E10 30 E8 19 C9 - - - - P413 - - GTOUUP - - - CTS0_ RTS0/ SS0 SSLA0 - SD0CLK - - - - - C13 31 D9 20 C10 - - - - P412 - - GTOULO - - - SCK0 RSPCKA - SD0CMD - - - - - R01DS0324EU0100 Rev.1.00 Oct 30, 2017 - - - - - Page 32 of 145 S3A1 Datasheet 1. Overview CTSU SLCDC ACMPLP ADC14 SDHI SSIE HMI DAC12, OPAMP Analog SPI/QSPI IIC SCI USBFS, CAN RTC GPT GPT_OPS, POEG Communication interfaces AGT I/O port Interrupt External bus Timers Power, System, Clock, Debug, CAC, VBATT QFN64 LQFP64 LGA100 LQFP100 BGA121 LQFP144 LGA145 Pin number D11 32 C11 21 D8 12 12 - IRQ4 P411 - AGTOA1 GTOVUP GTIOC9A - - TXD0/ MOSI0 /SDA0 CTS3_ RTS3/ SS3 MOSIA - SD0DAT0 - - - SEG7 TS7 C12 33 C10 22 E6 13 13 - IRQ5 P410 - AGTOB1 GTOVLO GTIOC9B - - SCK3 RXD0/ MISO0 /SCL0 MISOA - SD0DAT1 - - - SEG8 TS6 B13 34 C9 B10 14 14 - IRQ6 P409 - - GTOWUP GTIOC5A - USB_ TXD3/ EXIC MOSI3 /SDA3 EN - - - - - - SEG9 TS5 D10 35 B11 24 D7 15 15 - IRQ7 P408 - - GTOWLO GTIOC5B - USB_ CTS1_ SCL0 ID RTS1/ SS1 RXD3/ MISO3 /SCL3 - - - - - - SEG10 TS4 A13 36 A11 25 A10 16 16 - - P407 - AGTIO0 - - RTCOUT USB_ CTS4_ SDA0 VBUS RTS4/ SS4 SSLB3 - - ADTR G0 - - SEG11 TS3 B11 37 B9 26 B8 17 17 VSS_USB - - - - - - - - - - - - - - - - - - A12 38 A10 27 A9 18 18 - - P915 - - - - - USB_ DM - - - - - - - - - B12 39 B10 28 B9 19 19 - - P914 - - - - - USB_ DP - - - - - - - - - A11 40 A9 29 A8 20 20 VCC_USB - - - - - - - - - - - - - - - - - - C11 41 B8 30 C8 21 21 VCC_USB _LDO - - - - - - - - - - - - - - - - - B10 42 C8 31 C7 22 22 - IRQ0 P206 WAI T GTIU - - USB_ RXD4/ SDA1 VBUS MISO4 /SCL4 EN SSLB1 - SD0DAT2 - - - SEG12 TS1 A10 43 A8 32 A7 23 23 CLKOUT IRQ1 P205 A16 AGTO1 GTIV GTIOC4A - USB_ OVR CUR A TXD4/ SCL1 MOSI4 /SDA4 CTS9_ RTS9/ SS9 SSLB0 - SD0DAT3 - - - SEG20 TSCAP C10 44 D8 33 B7 24 24 CACREF - P204 A18 AGTIO1 GTIW GTIOC4B - USB_ SCK4 OVR SCK9 CUR B RSPCKB - SD0DAT4 - - - SEG23 TS0 A9 45 A7 34 D6 - - - IRQ2 P203 A19 - - GTIOC5A - - CTS2_ RTS2/ SS2 TXD9/ MOSI9 /SDA9 MOSIB - SD0DAT5 - - - SEG22 TSCAP C9 46 B7 35 C6 - - - IRQ3 P202 WR1 /BC1 - GTIOC5B - - SCK2 RXD9/ MISO9 /SCL9 MISOB - SD0DAT6 - - - SEG21 - B9 47 C7 - - - - - - P313 A20 - - - - - - - - - SD0DAT7 - - - - - D9 48 D7 - - - - - - P314 A21 - - - - - - - - - - ADTR G0 - - - - D8 49 E7 - - - - - - P315 A22 - - - - - RXD4/ MISO4 /SCL4 - - - - - - - - A8 50 - - - - - - - P900 A23 - - - - - TXD4/ MOSI4 /SDA4 - - - - - - - - B8 51 - - - - - - - P901 - AGTIO1 - - - - SCK4 - - - - - - - - - B7 52 - - - - - - - P902 - AGTO1 - - - - CTS4_ RTS4/ SS4 - - - - - - - - A7 53 A6 36 A6 - - VSS - - - - - - - - - - - - - - - - - - A6 54 B6 37 B6 - - VCC - - - - - - - - - - - - - - - - - - C7 55 C6 38 D5 25 25 RES - - - - - - - - - - - - - - - - - - B6 56 D6 39 B5 26 26 MD - P201 - - - - - - - - - - - - - - - - 23 R01DS0324EU0100 Rev.1.00 Oct 30, 2017 SCL0 Page 33 of 145 S3A1 Datasheet 1. Overview - CTSU SLCDC ACMPLP ADC14 SDHI SSIE HMI DAC12, OPAMP Analog SPI/QSPI IIC SCI USBFS, CAN RTC GPT GPT_OPS, POEG Communication interfaces AGT I/O port Interrupt External bus Timers Power, System, Clock, Debug, CAC, VBATT QFN64 LQFP64 LGA100 LQFP100 BGA121 LQFP144 LGA145 Pin number C8 57 E6 40 A5 27 27 - NMI P200 - - - - - - - - - - - - - - - C6 58 - - - - - - - P312 CS3 AGTOA1 - - - - CTS3_ RTS3/ SS3 - - - - - - - - B5 59 - - - - - - - P311 CS2 AGTOB1 - - - - SCK3 - - - - - - - - D7 60 - - - - - - - P310 A15 AGTEE1 - - - - TXD3/ MOSI3 /SDA3 QIO3 - - - - - - - A5 61 B5 - - - - - - P309 A14 - - - - - RXD3/ MISO3 /SCL3 QIO2 - - - - - - - C5 62 A5 - - - - - - P308 A13 - - - - - - - QIO1 - - - - - SEG13 - A4 63 C5 41 C5 - - - - P307 A12 - - - - - - - QIO0 - - - - - SEG14 - - - B4 64 B4 42 D4 - - - - P306 A11 - - - - - - - QSSL - - - - SEG15 - D6 65 A4 43 A4 - - - IRQ8 P305 A10 - - - - - - - QSPCLK - SD0CD - - - SEG16 - C4 66 E5 44 B4 28 28 - IRQ9 P304 A09 - - GTIOC7A - - - - - - SD0WP - - - SEG17 TS11 A3 67 C4 45 C4 - - - - P808 - - - - - - - - - - SD0CLK - - - SEG18 - B3 68 A3 46 A3 - - - - P809 - - - - - - - - - - SD0CMD - - - SEG19 - D5 69 B3 47 B3 29 29 - - P303 A08 - - GTIOC7B - - - - - - SD0DAT0 - - - SEG3/ TS2 COM7 A2 70 D5 48 B2 30 30 - IRQ5 P302 A07 - GTOUUP GTIOC4A - - TXD2/ MOSI2 /SDA2 SSLB3 - - - - - SEG2/ TS8 COM6 C3 71 A2 49 C2 31 31 - IRQ6 P301 A06 AGTIO0 GTOULO GTIOC4B - - RXD2/ MISO2 /SCL2 CTS9_ RTS9/ SS9 SSLB2 - - - - - SEG1/ TS9 COM5 B2 72 A1 50 A2 32 32 TCK/ SWCLK - P300 - - GTOUUP GTIOC0A - - - - SSLB1 - - - - - - - A1 73 B2 51 A1 33 33 TMS/ SWDIO - P108 - - GTOULO GTIOC0B - - CTS9_ RTS9/ SS9 SSLB0 - - - - - - - D4 74 B1 52 B1 34 34 TDO/SWO/ CLKOUT P109 - - GTOVUP GTIOC1A - CTX0 SCK1 TXD9/ MOSI9 /SDA9 MOSIB - - - - - SEG52 TS10 B1 75 C3 53 C3 35 35 TDI IRQ3 P110 - - GTOVLO GTIOC1B - CRX0 CTS2_ RTS2/ SS2 RXD9/ MISO9 /SCL9 MISOB - - - - VCOUT SEG53 - C2 76 D3 54 D3 36 36 - IRQ4 P111 A05 - - GTIOC3A - - SCK2 SCK9 RSPCKB - - - - - CAPH TS12 D3 77 C1 55 C1 37 37 - - P112 A04 - - GTIOC3B - - TXD2/ MOSI2 /SDA2 SCK1 SSLB0 SSIBCK0 - - - - CAPL C1 78 C2 56 E5 38 38 - - P113 A03 - - GTIOC2A - - RXD2/ MISO2 /SCL2 - SSILRCK0 /SSIFS0 - - - SEG0/ TS27 COM4 E4 79 D4 57 D2 - - - - P114 A02 - - GTIOC2B - - - - - SSIRXD0 - - - - SEG24 TS29 E3 80 D1 58 E4 - - - - P115 A01 - - GTIOC4A - - - - - SSITXD0 - - - - SEG25 TS35 D2 81 - - - - - - - P806 - - - - - - - - - - - - - - SEG26 - D1 82 - - - - - - - P807 - - - - - - - - - - - - - - SEG27 - F4 83 D2 59 D1 - - - - P608 A00/ BC0 - GTIOC4B - - - - - - SD0DAT1 - - - SEG28 - E2 84 E3 60 E3 - - - - P609 CS1 - - GTIOC5A - - - - - - SD0DAT2 - - - SEG29 - F3 85 E1 61 E2 - - - - P610 CS0 - - GTIOC5B - - - - - - SD0DAT3 - - - SEG30 - R01DS0324EU0100 Rev.1.00 Oct 30, 2017 - TSCAP Page 34 of 145 S3A1 Datasheet 1. Overview CTSU SLCDC ACMPLP ADC14 SDHI SSIE HMI DAC12, OPAMP Analog SPI/QSPI IIC SCI USBFS, CAN RTC GPT GPT_OPS, POEG Communication interfaces AGT I/O port Interrupt External bus Timers Power, System, Clock, Debug, CAC, VBATT QFN64 LQFP64 LGA100 LQFP100 BGA121 LQFP144 LGA145 Pin number E1 86 E4 - - - - - - P611 - - - - - - - - - - - - - SEG31 - F2 87 F5 - - - - - - P612 D08 - - - - - - - - - - - - - SEG32 - F1 88 E2 - - - - - - P613 D09 - - - - - - - - - - - - - SEG33 - - - - - - - P614 D10 - - - - - - - - - - - - - SEG34 - G3 89 G1 90 F1 62 E1 39 39 VCC - - - - - - - - - - - - - - - - - - G2 91 G1 63 F1 40 40 VSS - - - - - - - - - - - - - - - - - - H1 92 - - - - - - - P606 - - - - RTCOUT - - - - - - - - - SEG35 - H2 93 F2 - - - - - - P605 D11 - - GTIOC8A - - - - - - - - - - SEG36 - G4 94 F3 - - - - - - P604 D12 - - GTIOC8B - - - - - - - - - - SEG37 - H3 95 F4 64 F2 - - - - P603 D13 - - GTIOC7A - - CTS9_ RTS9/ SS9 - - SD0DAT4 - - - SEG38 - J1 96 G2 65 F3 - - - - P602 EBC LK - GTIOC7B - - TXD9/ MOSI9 /SDA9 - - SD0DAT5 - - - SEG39 - J2 97 G5 66 F4 - - - - P601 WR/ WR0 - GTIOC6A - - RXD9/ MISO9 /SCL9 - - SD0DAT6 - - - SEG40 - H4 98 G4 67 F5 - - - - P600 RD - - GTIOC6B - - SCK9 - - - SD0DAT7 - - - SEG41 - K2 99 - - - - - - - P805 - - GTIOC9A - - - - - - - - - - SEG42 - K1 100 - - - - - - - P804 - - GTIOC9B - - - - - - - - - - SEG43 - J3 101 H1 68 G3 41 41 - KR07 P107 D07 - - GTIOC8A - - - - - - - - - - COM3 - K3 102 G3 69 G2 42 42 - KR06 P106 D06 - - GTIOC8B - - - - SSLA3 - - - - - COM2 - J4 103 H2 70 G1 43 43 - KR05/ P105 D05 IRQ0 GTETRGA GTIOC1A - - - - SSLA2 - - - - - COM1 TS34 L3 104 H3 71 H1 44 44 - KR04/ P104 D04 IRQ1 GTETRGB GTIOC1B - - RXD0/ MISO0 /SCL0 SSLA1 - - - - - COM0 TS13 L1 105 J1 72 H3 45 45 - KR03 P103 D03 - GTOWUP GTIOC2A - CTX0 CTS0_ RTS0/ SS0 SSLA0 - - AN019 - CMPRE VL4 F1 - M1 106 J2 73 J1 46 46 - KR02 P102 D02 AGTO0 GTOWLO GTIOC2B - CRX0 SCK0 TXD2/ MOSI2 /SDA2 RSPCKA - - AN020/ ADTR G0 CMPIN1 VL3 - M2 107 K1 74 H2 47 47 - KR01/ P101 D01 AGTEE0 GTETRGB GTIOC5A IRQ1 - TXD0/ SDA1 MOSI0 /SDA0 CTS1_ RTS1/ SS1 MOSIA - - AN021 - CMPRE VL2 F0 - N1 108 L1 75 H4 48 48 - KR00/ P100 D00 AGTIO0 GTETRGA GTIOC5B IRQ2 - RXD0/ SCL1 MISO0 /SCL0 SCK1 MISOA - - AN022 - CMPIN0 VL1 - L2 109 L2 - - - - - - P800 D14 - - - - - - - - - - - - - SEG44 - N2 110 K2 - - - - - - P801 D15 - - - - - - - - - - - - - SEG45 - N3 111 - - - - - - - P802 - - - - - - - - - - - - - - SEG46 - M3 112 - - - - - - - P803 - - - - - - - - - - - - - - SEG47 - K4 113 K3 76 K1 49 49 - - P500 - AGTOA0 GTIU GTIOC2A - USB_ VBUS EN - QSPCLK - - AN016 - CMPRE SEG48 F1 M4 114 L3 77 J2 50 50 - IRQ11 P501 - AGTOB0 GTIV GTIOC2B - USB_ TXD3/ OVR MOSI3 CUR /SDA3 A QSSL - - AN017 - CMPIN1 SEG49 - L4 78 K2 51 51 - IRQ12 P502 - - GTIOC3B - USB_ RXD3/ OVR MISO3 CUR /SCL3 B QIO0 - - AN018 - CMPRE SEG50 F0 115 J3 R01DS0324EU0100 Rev.1.00 Oct 30, 2017 GTIW Page 35 of 145 S3A1 Datasheet 1. Overview CTSU SLCDC ACMPLP ADC14 SDHI SSIE HMI DAC12, OPAMP Analog SPI/QSPI IIC SCI USBFS, CAN RTC GPT GPT_OPS, POEG Communication interfaces AGT I/O port Interrupt External bus Timers Power, System, Clock, Debug, CAC, VBATT QFN64 LQFP64 LGA100 LQFP100 BGA121 LQFP144 LGA145 Pin number K5 116 J4 79 G4 - - - - P503 - - GTETRGA - - USB_ CTS2_ EXIC RTS2/ SS2 EN SCK3 QIO1 - - AN023 - CMPIN0 SEG51 - L5 117 H4 80 G5 - - - - P504 ALE - GTETRGB - - USB_ SCK2 ID CTS3_ RTS3/ SS3 QIO2 - - AN024 - - - - K6 118 J5 81 G6 - - - IRQ14 P505 - - - - - - RXD2/ MISO2 /SCL2 QIO3 - - AN025 - - - - L6 119 H5 - - - - - IRQ15 P506 - - - - - - TXD2/ MOSI2 /SDA2 - - - AN026 - - - - N4 120 - - - - - - - P507 - - - - - - - - - - - AN027 - - - - N5 121 L4 82 K3 - - VCC - - - - - - - - - - - - - - - - - - M5 122 K4 83 J3 - - VSS - - - - - - - - - - - - - - - - - - M6 123 K5 84 J4 52 52 - IRQ7 P015 - - - - - - - - - - - AN010 - - - TS28 N6 124 L5 85 K4 53 53 - - P014 - - - - - - - - - - - AN009 DA0 - - - M7 125 K6 86 J5 54 54 VREFL - P013 - - - - - - - - - - - AN008 AMP1+ - - - N7 126 L6 87 K5 55 55 VREFH - P012 - - - - - - - - - - - AN007 AMP1- - - - L7 127 J6 88 H5 56 56 AVCC0 - - - - - - - - - - - - - - - - - - L8 128 J7 89 H6 57 57 AVSS0 - - - - - - - - - - - - - - - - - - M8 129 K7 90 J6 58 58 VREFL0 IRQ15 P011 - - - - - - - - - - - AN006 AMP2+ - - TS31 N8 91 K6 59 59 VREFH0 IRQ14 P010 - - - - - - - - - - - AN005 AMP2- - - TS30 M9 131 - - - - - - IRQ13 P009 - - - - - - - - - - - AN015 - - - - N9 132 H6 92 J7 - - - IRQ12 P008 - - - - - - - - - - - AN014 - - - - K7 133 H7 93 H7 - - - P007 - - - - - - - - - - - AN013 AMP3O - - - L9 134 H8 94 G7 - - - IRQ11 P006 - - - - - - - - - - - AN012 AMP3- - - - K8 135 L8 95 K7 - - - IRQ10 P005 - - - - - - - - - - - AN011 AMP3+ - - - K9 136 J8 96 J8 60 60 - IRQ3 - - - - - - - - - - AN004 AMP2O - - - 130 L7 P004 - K10 137 K8 97 H8 61 61 - - P003 - - - - - - - - - - - AN003 AMP1O - - - M1 138 J9 0 98 K8 62 62 - IRQ2 P002 - - - - - - - - - - - AN002 AMP0O - - - N10 139 K9 99 K9 63 63 - IRQ7 P001 - - - - - - - - - - - AN001 AMP0- - TS22 L10 140 L9 100 K10 64 64 - IRQ6 P000 - - - - - - - - - - - AN000 AMP0+ - N11 141 - - - - - VSS - - - - - - - - - - - - - - - - - - N12 142 - - - - - VCC - - - - - - - - - - - - - - - - - - M11 143 L10 - - - - - IRQ14 P512 - - - GTIOC0A - CTX0 TXD4/ SCL2 MOSI4 /SDA4 - - - - - - - - M1 144 K10 2 - - - - IRQ15 P511 - - - GTIOC0B - CRX0 RXD4/ SDA2 MISO4 /SCL4 - - - - - - - - E5 - - - NC - - - - - - - - - - - - - - - F6 - - R01DS0324EU0100 Rev.1.00 Oct 30, 2017 - - - - TS21 Page 36 of 145 S3A1 Datasheet 2. 2. Electrical Characteristics Electrical Characteristics Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions: VCC*1 = AVCC0 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5 V, VRERH = VREFH0 = 1.6 to AVCC0, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = VREFL = VREFL0 = VSS_USB = 0 V, Ta = Topr. Note 1. The typical condition is set to VCC = 3.3V. Note 2. When USBFS is not used. Figure 2.1 shows the timing conditions. For example P100 C VOH = VCC × 0.7, VOL = VCC × 0.3 VIH = VCC × 0.7, VIL = VCC × 0.3 Load capacitance C = 30 pF Figure 2.1 Input or output timing measurement conditions The measurement conditions of timing specifications in each peripheral are recommended for the best peripheral operation. However, make sure to adjust driving abilities of each pin to meet your conditions. Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function pin is mixed, the AC specification of each function is not guaranteed. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 37 of 145 S3A1 Datasheet 2.1 2. Electrical Characteristics Absolute Maximum Ratings Table 2.1 Absolute maximum ratings Parameter Power supply voltage Input voltage ports*1 Symbol Value Unit VCC –0.5 to +6.5 V Vin –0.3 to +6.5 V P000 to P015 Vin –0.3 to AVCC0 + 0.3 V Others Vin –0.3 to VCC + 0.3 V VREFH0 –0.3 to +6.5 V 5V-tolerant Reference power supply voltage VREFH V VBATT power supply voltage VBATT –0.5 to +6.5 V Analog power supply voltage AVCC0 –0.5 to +6.5 V USB power supply voltage VCC_USB –0.5 to +6.5 V VCC_USB_LDO –0.5 to +6.5 V VAN –0.3 to AVCC0 + 0.3 V –0.3 to VCC + 0.3 V Analog input voltage When AN000 to AN015 are used When AN016 to AN027 are used LCD voltage VL1 voltage VL1 –0.3 to +2.8 V VL2 voltage VL2 –0.3 to +6.5 V VL3 voltage VL3 –0.3 to +6.5 V VL4 voltage VL4 –0.3 to +6.5 V Topr –40 to +105 °C Operating temperature*2, *3, *4 –40 to +85 Storage temperature Tstg –55 to +125 °C Note 1. Note 2. Note 3. Ports P205, P206, P400 to P404, P407, P408, P511, P512 are 5V-tolerant. See section 2.2.1, Tj/Ta Definition. Contact Renesas Electronics sales office for information on derating operation under Ta = +85°C to +105°C. Derating is the systematic reduction of load for improved reliability. Note 4. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part Numbering. Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded. To preclude any malfunctions due to noise interference, insert capacitors with high frequency characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the VCC_USB and VSS_USB pins, between the VREFH0 and VREFL0 pins, and between the VREFH and VREFL pins. Place capacitors of about 0.1 μF as close as possible to every power supply pin and use the shortest and heaviest possible traces. Also, connect capacitors as stabilization capacitance. Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. The capacitor must be placed close to the pin. Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause degradation of internal elements. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 38 of 145 S3A1 Datasheet Table 2.2 2. Electrical Characteristics Recommended operating conditions Parameter Symbol Value Min Typ Max Unit Power supply voltages VCC*1, *2 When USBFS is not used 1.6 - 5.5 V When USBFS is used VCC_USB USB Regulator Disable - 3.6 V When USBFS is used VCC_USB USB Regulator _LDO Enable - 5.5 V - 0 - V - VCC - V When USBFS is used 3.0 USB Regulator Disable (Input) 3.3 3.6 V When USBFS is not used - VCC - V When USBFS is used USB Regulator Disable - VCC - V - 5.5 V - 0 - V When the battery backup function is not used - VCC - V When the battery backup function is used 1.6 - 3.6 V AVCC0*1, *2 1.6 - 5.5 V AVSS0 - 0 - V 1.6 - AVCC0 V VSS USB power supply voltages VCC_USB VCC_USB_LDO When USBFS is not used When USBFS is used 3.8 USB Regulator Enable VSS_USB VBATT power supply voltage Analog power supply voltages VBATT VREFH0 VREFL0 VREFH VREFL Note 1. Note 2. When used as ADC14 Reference When used as DAC12 Reference - 0 - V 1.6 - AVCC0 V - 0 - V Use AVCC0 and VCC under the following conditions: AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 ≥ 2.2 V AVCC0 = VCC when VCC < 2.2V or AVCC0 < 2.2V. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pin. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 39 of 145 S3A1 Datasheet 2.2 2. Electrical Characteristics DC Characteristics 2.2.1 Tj/Ta Definition Table 2.3 DC characteristics Conditions: Products with operating temperature (Ta) –40 to +105°C Parameter Symbol Typ Max Unit Test conditions Permissible junction temperature Tj - 125 °C High-speed mode Middle-speed mode Low-voltage mode Low-speed mode Subosc-speed mode 105*1 Note: Note 1. Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC – VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of Tj is 105°C, otherwise, it is 125°C. 2.2.2 I/O VIH, VIL Table 2.4 I/O VIH, VIL (1) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 2.7 to 5.5 V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V Parameter Schmitt trigger input voltage Input voltage (except for Schmitt trigger input pin) IIC*1 (except for SMBus) Typ Max Unit Test conditions V - VIH VCC × 0.7 - 5.8 VIL - - VCC × 0.3 ∆VT VCC × 0.05 - - VIH VCC × 0.8 - - VIL - - VCC × 0.2 ∆VT VCC × 0.1 - - IIC (SMBus)*2 VIH 2.2 - - VCC = 3.6 to 5.5 V VIH 2.0 - - VCC = 2.7 to 3.6 V VIL - - 0.8 - VIH VCC × 0.8 - 5.8 VIL - - VCC × 0.2 VIH VCC_USB × 0.8 - VCC_USB + 0.3 VIL - - VCC_USB × 0.2 VIH AVCC0 × 0.8 - - VIL - - AVCC0 × 0.2 EXTAL D00 to D15 Input ports pins except for P000 to P015, P914, P915 VIH VCC × 0.8 - - VIL - - VCC × 0.2 P402, P403, P404 VIH VBATT × 0.8 - VBATT + 0.3 VIL - - VBATT × 0.2 ∆VT VBATT × 0.05 - - ports*3 P914, P915 P000 to P015 Note 1. Note 2. Note 3. Min RES, NMI Other peripheral input pins excluding IIC 5V-tolerant When VBATT power supply is selected Symbol P205, P206, P400, P401, P407, P408, P511, P512 (total 8 pins). P100, P101, P204, P205, P206, P400, P401, P407, P408, P511, P512 (total 11 pins). P205, P206, P400 to P404, P407, P408, P511, P512 (total 11 pins). R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 40 of 145 S3A1 Datasheet Table 2.5 2. Electrical Characteristics I/O VIH, VIL (2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.6 to 2.7 V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V Parameter Symbol Min Typ Max Unit Test conditions V - Schmitt trigger input voltage RES, NMI Peripheral input pins Input voltage (except for Schmitt trigger input pin) 5V-tolerant ports*1 VIL - - VCC × 0.2 P914, P915 VIH VCC_USB × 0.8 - VCC_USB + 0.3 VIL - - VCC_USB × 0.2 P000 to P015 VIH AVCC0 × 0.8 - - VIL - - AVCC0 × 0.2 EXTAL D00 to D15 Input ports pins except for P000 to P015, P914, P915 VIH VCC × 0.8 - - VIL - - VCC × 0.2 P402, P403, P404 VIH VBATT × 0.8 - VBATT + 0.3 VIL - - VBATT × 0.2 ∆VT VBATT × 0.01 - - When VBATT power supply is selected Note 1. VIH VCC × 0.8 - - VIL - - VCC × 0.2 ∆VT VCC × 0.01 - - VIH VCC × 0.8 - 5.8 P205, P206, P400 to P404, P407, P408, P511, P512 (total 11 pins) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 41 of 145 S3A1 Datasheet 2.2.3 Table 2.6 2. Electrical Characteristics I/O IOH, IOL I/O IOH, IOL (1 of 2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 5.5 V Parameter Permissible output current (average value per pin) Ports P212, P213 Port P408 - Low drive*1 Middle drive for IIC Fast-mode*4 VCC = 2.7 to 5.5 V Middle drive*2 VCC = 3.0 to 5.5 V Port P409 Low drive*1 Middle drive*2 VCC = 2.7 to 3.0 V Middle drive*2 VCC = 3.0 to 5.5 V Ports P100 to P115, P201 to P204, P300 to P315, P500 to P503, P600 to P606, P608 to P614, P800 to P809, P900 to P902 (total 67 pins) Low drive*1 Ports P914, P915 - Other output pin*3 Low drive*1 Middle drive*2 Middle drive*2 R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Symbol Min Typ Max Unit IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –8.0 mA IOL - - 8.0 mA IOH - - –20.0 mA IOL - - 20.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –8.0 mA IOL - - 8.0 mA IOH - - –20.0 mA IOL - - 20.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –4.0 mA IOL - - 8.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –8.0 mA IOL - - 8.0 mA Page 42 of 145 S3A1 Datasheet Table 2.6 2. Electrical Characteristics I/O IOH, IOL (2 of 2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 5.5 V Parameter Permissible output current (Max value per pin) Ports P212, P213 - Port P408 Low drive*1 Middle drive for IIC Fast-mode*4 VCC = 2.7 to 5.5 V Middle drive*2 VCC = 3.0 to 5.5 V Port P409 Low drive*1 Middle drive*2 VCC = 2.7 to 3.0 V Middle drive*2 VCC = 3.0 to 5.5 V Ports P100 to P115, P201 to P204, P300 to P315, P500 to P503, P600 to P606, P608 to P614, P800 to P809, P900 to P902 (total 67 pins) Ports P914, P915 Other output pin*3 Low drive*1 Middle drive*2 - Low drive*1 Middle drive*2 Permissible output current (max value total pins) Total of ports P000 to P015 Ports P914, P915 Total of all output pin*5 Caution: Note 1. Note 2. Note 3. Note 4. Note 5. Symbol Min Typ Max Unit IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –8.0 mA IOL - - 8.0 mA IOH - - –20.0 mA IOL - - 20.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –8.0 mA IOL - - 8.0 mA IOH - - –20.0 mA IOL - - 20.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –4.0 mA IOL - - 8.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –4.0 mA IOL - - 4.0 mA IOH - - –8.0 mA IOL - - 8.0 mA ΣIOH (max) - - –30 mA ΣIOL (max) - - 30 mA ΣIOH (max) - - –4.0 mA ΣIOL (min) - - 4.0 mA ΣIOH (max) - - –60 mA ΣIOL (max) - - 60 mA To protect the reliability of the MCU, the output current values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 μs. This is the value when low driving ability is selected with the Port Drive Capability bit in PmnPFS register. This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register. Except for ports P200, P214, P215, which are input ports. This is the value when middle driving ability for IIC Fast-mode is selected with the Port Drive Capability bit in PmnPFS register. For details on the permissible output current used with CTSU, see section 2.11, CTSU Characteristics. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 43 of 145 S3A1 Datasheet 2.2.4 2. Electrical Characteristics I/O VOH, VOL, and Other Characteristics Table 2.7 I/O VOH, VOL (1) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 4.0 to 5.5 V Parameter Output voltage IIC*1 Ports P408, P409*2, *3 Ports P000 to P015 Low drive Middle drive Ports P914, P915 Other output pins*4 Low drive Middle drive*6 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Symbol Min Typ Max Unit Test conditions VOL - - 0.4 V IOL = 3.0 mA VOL*2, *5 - - 0.6 IOL = 6.0 mA VOH VCC – 1.0 - - IOH = –20 mA VOL - - 1.0 IOL = 20 mA VOH AVCC0 – 0.8 - - IOH = –2.0 mA VOL - - 0.8 IOL = 2.0 mA VOH AVCC0 – 0.8 - - IOH = –4.0 mA VOL - - 0.8 IOL = 4.0 mA VOH VCC_USB – 0.8 - - IOH = –2.0 mA VOL - - 0.8 IOL = 2.0 mA VOH VCC – 0.8 - - IOH = –2.0 mA VOL - - 0.8 IOL = 2.0 mA VOH VCC – 0.8 - - IOH = –4.0 mA VOL - - 0.8 IOL = 4.0 mA P100, P101, P204, P205, P206, P400, P401, P407, P408, P511, P512 (total 11 pins). This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register. Based on characterization data, not tested in production. Except for ports P200, P214, P215, which are input ports. This is the value when middle driving ability for IIC is selected with the Port Drive Capability bit in PmnPFS register for P408. Except for P212, P213. Table 2.8 I/O VOH, VOL (2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 2.7 to 4.0 V Parameter Output voltage IIC*1 Ports P408, P409*2, *3 Ports P000 to P015 Low drive Middle drive Ports P914, P915 Other output pins*4 Low drive Middle drive*6 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Symbol Min Typ Max Unit Test conditions VOL - - 0.4 V IOL = 3.0 mA VOL*2, *5 - - 0.6 IOL = 6.0 mA VOH VCC – 1.0 - - IOH = –20 mA VCC = 3.3 V VOL - - 1.0 IOL = 20 mA VCC = 3.3 V VOH AVCC0 – 0.5 - - IOH = –1.0 mA VOL - - 0.5 IOL = 1.0 mA VOH AVCC0 – 0.5 - - IOH = –2.0 mA VOL - - 0.5 IOL = 2.0 mA VOH VCC_USB – 0.5 - - IOH = –1.0 mA VOL - - 0.5 IOL = 1.0 mA VOH VCC – 0.5 - - IOH = –1.0 mA VOL - - 0.5 IOL = 1.0 mA VOH VCC – 0.5 - - IOH = –2.0 mA VOL - - 0.5 IOL = 2.0 mA P100, P101, P204, P205, P206, P400, P401, P407, P408, P511, P512 (total 11 pins). This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register. Based on characterization data, not tested in production. Except for ports P200, P214, P215, which are input ports. This is the value when middle driving ability for IIC is selected with the Port Drive Capability bit in PmnPFS register for P408. Except for P212, P213. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 44 of 145 S3A1 Datasheet Table 2.9 2. Electrical Characteristics I/O VOH, VOL (3) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 2.7 V Parameter Output voltage Ports P000 to P015 Symbol Min Typ Max Unit Test conditions Low drive VOH AVCC0 – 0.3 - - V IOH = –0.5 mA VOL - - 0.3 IOL = 0.5 mA Middle drive VOH AVCC0 – 0.3 - - IOH = –1.0 mA Ports P914, P915 Other output pins*1 Low drive Middle drive*2 Note 1. Note 2. VOL - - 0.3 IOL = 1.0 mA VOH VCC_USB – 0.3 - - IOH = –0.5 mA VOL - - 0.3 IOL = 0.5 mA VOH VCC – 0.3 - - IOH = –0.5 mA VOL - - 0.3 IOL = 0.5 mA VOH VCC – 0.3 - - IOH = –1.0 mA VOL - - 0.3 IOL = 1.0 mA Except for ports P200, P214, P215, which are input ports. Except for P212, P213. Table 2.10 I/O other characteristics Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Input leakage current RES, P200, P214, P215 | Iin | - - 1.0 μA Vin = 0 V Vin = VCC Three-state leakage current (off state) 5V-tolerant ports | ITSI | - - 1.0 μA Vin = 0 V Vin = 5.8 V - - 1.0 Other ports (except for ports P200, P214, P215 and 5 V tolerant) Vin = 0 V Vin = VCC Input pull-up resistor All ports (except for ports P200, P214, P215, P914, P915) RU 10 20 50 kΩ Vin = 0 V Input capacitance P914, P915, P100 to P103, P111, P112, P200 Cin - - 30 pF Vin = 0 V f = 1 MHz Ta = 25°C - - 15 Other input pins R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 45 of 145 S3A1 Datasheet 2.2.5 2. Electrical Characteristics I/O Pin Output Characteristics of Low Drive Capacity IOH/IOL vs VOH/VOL 60 50 VCC = 5.5 V 40 30 VCC = 3.3 V IOH/IOL [mA] 20 VCC = 2.7 V 10 VCC = 1.6 V 0 VCC = 1.6 V -10 VCC = 2.7 V -20 VCC = 3.3 V -30 -40 -50 VCC = 5.5 V -60 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.2 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when low drive output is selected (reference data) IOH/IOL vs VOH/VOL 3 Ta = -40°C Ta = 25°C Ta = 105°C 2 IOH/IOL [mA] 1 0 -1 Ta = 105°C Ta = 25°C -2 Ta = -40°C -3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH/VOL [V] Figure 2.3 VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 46 of 145 S3A1 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 20 15 Ta = -40°C Ta = 25°C Ta = 105°C IOH/IOL [mA] 10 5 0 -5 Ta = 105°C Ta = 25°C -10 Ta = -40°C -15 -20 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.4 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when low drive output is selected (reference data) IOH/IOL vs VOH/VOL 30 Ta = -40°C Ta = 25°C Ta = 105°C 20 IOH/IOL [mA] 10 0 -10 Ta = 105°C Ta = 25°C -20 Ta = -40°C -30 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.5 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when low drive output is selected (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 47 of 145 S3A1 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 60 Ta = -40°C Ta = 25°C Ta = 105°C 40 IOH/IOL [mA] 20 0 -20 Ta = 105°C -40 Ta = 25°C Ta = -40°C -60 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.6 2.2.6 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected (reference data) I/O Pin Output Characteristics of Middle Drive Capacity IOH/IOL [mA] IOH/IOL vs VOH/VOL 140 120 100 80 60 40 20 VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 1.6 V 0 -20 -40 -60 -80 -100 -120 -140 VCC = 1.6 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.7 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 48 of 145 S3A1 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 6 Ta = -40°C Ta = 25°C Ta = 105°C 4 IOH/IOL [mA] 2 0 -2 Ta = 105°C -4 Ta = 25°C Ta = -40°C -6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH/VOL [V] Figure 2.8 VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when middle drive output is selected (reference data) IOH/IOL vs VOH/VOL 40 Ta = -40°C Ta = 25°C Ta = 105°C 30 IOH/IOL [mA] 20 10 0 -10 -20 Ta = 105°C Ta = 25°C -30 Ta = -40°C -40 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.9 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is selected (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 49 of 145 S3A1 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 60 Ta = -40°C Ta = 25°C 40 Ta = 105°C IOH/IOL [mA] 20 0 -20 Ta = 105°C -40 Ta = 25°C Ta = -40°C -60 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.10 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is selected (reference data) IOH/IOL [mA] IOH/IOL vs VOH/VOL 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 Ta = -40°C Ta = 25°C Ta = 105°C Ta = 105°C Ta = 25°C Ta = -40°C 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.11 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is selected (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 50 of 145 S3A1 Datasheet 2.2.7 2. Electrical Characteristics P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity IOH/IOL [mA] IOH/IOL vs VOH/VOL 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.12 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected (reference data) IOH/IOL vs VOH/VOL 60 Ta = -40°C Ta = 25°C Ta = 105°C 40 IOH/IOL [mA] 20 0 -20 Ta = 105°C -40 Ta = 25°C Ta = -40°C -60 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.13 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is selected (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 51 of 145 S3A1 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 100 Ta = -40°C Ta = 25°C Ta = 105°C 80 60 40 IOH/IOL [mA] 20 0 -20 -40 Ta = 105°C -60 Ta = 25°C -80 Ta = -40°C -100 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.14 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is selected (reference data) IOH/IOL vs VOH/VOL 220 Ta = -40°C Ta = 25°C Ta = 105°C 180 140 IOH/IOL [mA] 100 60 20 -20 -60 -100 -140 Ta = 105°C Ta = 25°C -180 Ta = -40°C -220 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.15 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is selected (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 52 of 145 S3A1 Datasheet 2.2.8 2. Electrical Characteristics IIC I/O Pin Output Characteristics IOL vs VOL 120 110 VCC = 5.5 V (Middle drive) 100 90 IOL [mA] 80 70 60 50 VCC = 3.3 V (Middle drive) VCC = 5.5 V (Low drive) 40 VCC = 2.7 V (Middle drive) 30 VCC = 3.3 V (Low drive) 20 10 VCC = 2.7 V (Low drive) 0 0 1 2 3 4 5 6 VOL [V] Figure 2.16 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 53 of 145 S3A1 Datasheet 2.2.9 Table 2.11 2. Electrical Characteristics Operating and Standby Current Operating and standby current (1) (1 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Supply current*1 High-speed mode*2 Normal mode All peripheral clocks disabled, while (1) code executing from flash*5 All peripheral clocks disabled, CoreMark code executing from flash*5 All peripheral clocks enabled, while (1) code executing from flash*5 Sleep mode ICLK = 48 MHz Symbol Typ*10 Max Unit Test conditions ICC mA *7 9.3 - ICLK = 32 MHz 6.7 - ICLK = 16 MHz 4.1 - ICLK = 8 MHz 2.7 - ICLK = 48 MHz 18.8 - ICLK = 32 MHz 13.1 - ICLK = 16 MHz 7.5 - ICLK = 8 MHz 4.7 - ICLK = 48 MHz 22.4 - *9 ICLK = 32 MHz 16.9 - *8 ICLK = 16 MHz 9.4 - ICLK = 8 MHz 5.5 - All peripheral clocks enabled, code executing from SRAM*5 ICLK = 48 MHz - 62.0 *9 All peripheral clocks disabled*5 ICLK = 48 MHz 4.0 - *7 ICLK = 32 MHz 3.1 - ICLK = 16 MHz 2.3 - ICLK = 8 MHz 1.8 - ICLK = 48 MHz 16.8 - *9 ICLK = 32 MHz 13.0 - *8 All peripheral clocks enabled*5 ICLK = 16 MHz 7.4 - ICLK = 8 MHz 4.5 - Increase during BGO operation*6 Middle-speed mode*2 Normal mode All peripheral clocks disabled, while (1) code executing from flash*5 All peripheral clocks disabled, CoreMark code executing from flash*5 All peripheral clocks enabled, while (1) code executing from flash*5 Sleep mode - 2.8 - ICLK = 8 MHz 2.3 - ICLK = 1 MHz 1.1 - ICLK = 12 MHz 5.4 - ICLK = 8 MHz 4.2 - ICLK = 1 MHz 1.4 - ICLK = 12 MHz 6.9 - ICLK = 8 MHz 5.1 - ICC ICLK = 1 MHz 1.7 - All peripheral clocks enabled, code executing from SRAM*5 ICLK = 12 MHz - 25.0 All peripheral clocks disabled*5 ICLK = 12 MHz 1.5 - ICLK = 8 MHz 1.4 - All peripheral clocks enabled*5 Increase during BGO operation*6 R01DS0324EU0100 Rev.1.00 Oct 30, 2017 2.5 ICLK = 12 MHz ICLK = 1 MHz 1.0 - ICLK = 12 MHz 5.4 - ICLK = 8 MHz 4.1 - ICLK = 1 MHz 1.6 - 2.5 - mA *7 *8 *7 *8 - Page 54 of 145 S3A1 Datasheet Table 2.11 2. Electrical Characteristics Operating and standby current (1) (2 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Supply current*1 Low-speed mode*3 Normal mode Sleep mode Low-voltage mode*3 Normal mode Sleep mode Suboscspeed mode*4 Normal mode Sleep mode Symbol Typ*10 Max Unit Test conditions ICC 0.4 - mA *7 All peripheral clocks disabled, while (1) code executing from flash*5 ICLK = 1 MHz All peripheral clocks disabled, CoreMark code executing from flash*5 ICLK = 1 MHz 0.6 - All peripheral clocks enabled, while (1) code executing from flash*5 ICLK = 1 MHz 1.1 - All peripheral clocks enabled, code executing from SRAM*5 ICLK = 1 MHz - 2.6 All peripheral clocks disabled*5 ICLK = 1 MHz 0.3 - *7 All peripheral clocks enabled*5 ICLK = 1 MHz 1.0 - *8 All peripheral clocks disabled, while (1) code executing from flash*5 ICLK = 4 MHz 2.2 - All peripheral clocks disabled, CoreMark code executing from flash*5 ICLK = 4 MHz 3.3 - All peripheral clocks enabled, while (1) code executing from flash*5 ICLK = 4 MHz 3.7 - All peripheral clocks enabled, code executing from SRAM*5 ICLK = 4 MHz - 10.0 All peripheral clocks disabled*5 ICLK = 4 MHz 1.7 - *7 All peripheral clocks enabled*5 ICLK = 4 MHz 3.2 - *8 All peripheral clocks disabled, while (1) code executing from flash*5 ICLK = 32.768 kHz 10.0 - All peripheral clocks enabled, while (1) code executing from flash*5 ICLK = 32.768 kHz 17.9 - All peripheral clocks enabled, code executing from SRAM*5 ICLK = 32.768 kHz - 154.0 All peripheral clocks disabled*5 ICLK = 32.768 kHz 6.3 - All peripheral clocks enabled*5 ICLK = 32.768 kHz 14.0 - ICC ICC *8 mA *7 *8 μA *8 Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. The clock source is HOCO. Note 3. The clock source is MOCO. Note 4. The clock source is the sub-clock oscillator. Note 5. This does not include BGO operation. Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution. Note 7. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64. Note 8. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are the same frequency as that of ICLK. Note 9. FCLK, BCLK, and PCLKB are set to divided by 2 and PCLKA, PCLKC, and PCLKD are the same frequency as that of ICLK. Note 10. VCC = 3.3 V. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 55 of 145 S3A1 Datasheet 2. Electrical Characteristics Figure 2.17 Voltage dependency in high-speed mode (reference data) Figure 2.18 Voltage dependency in middle-speed mode (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 56 of 145 S3A1 Datasheet 2. Electrical Characteristics Figure 2.19 Voltage dependency in low-speed mode (reference data) Figure 2.20 Voltage dependency in low-voltage mode (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 57 of 145 S3A1 Datasheet Figure 2.21 Table 2.12 2. Electrical Characteristics Voltage dependency in Subosc-speed mode (reference data) Operating and standby current (2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Symbol Typ*4 Max Unit Test conditions ICC 0.9 5.5 μA Ta = 55°C 1.6 10.5 PSMCR.PSMC[1:0] = 01b (48-KB SRAM on) Ta = 85°C 4.5 25.4 Ta = 105°C 12.0 64.7 Ta = 25°C 1.1 7.0 Parameter Supply current*1 Note 1. Note 2. Note 3. Note 4. Software Standby mode*2 Ta = 25°C PSMCR.PSMC[1:0] = 00b (All SRAM on) Ta = 55°C 2.0 14.6 Ta = 85°C 6.6 36.2 Ta = 105°C 17.6 96.3 Increment for RTC operation with low-speed on-chip oscillator*3 0.5 - - Increment for RTC operation with sub-clock oscillator*3 0.4 - SOMCR.SODRV[1:0] are 11b (Low power mode 3) 1.2 - SOMCR.SODRV[1:0] are 00b (Normal mode) Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. The IWDT and LVD are not operating. Includes the current of sub-oscillation circuit or low-speed on-chip oscillator. VCC = 3.3 V. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 58 of 145 S3A1 Datasheet 2. Electrical Characteristics Figure 2.22 Temperature dependency in Software Standby mode 48-KB SRAM on (reference data) Figure 2.23 Temperature dependency in Software Standby mode all SRAM on (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 59 of 145 S3A1 Datasheet Table 2.13 2. Electrical Characteristics Operating and standby current (3) Conditions: VCC = AVCC0 = 0 V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V Parameter Supply current*1 Note 1. RTC operation when VCC is off Symbol Typ Max Unit Test conditions ICC 0.8 - μA Ta = 55°C 0.9 - VBATT = 2.0 V SOMCR.SORDRV[1:0] = 11b (Low power mode 3) Ta = 85°C 1.1 - Ta = 105°C 1.2 - Ta = 25°C 0.9 - Ta = 55°C 1.0 - Ta = 85°C 1.2 - Ta = 105°C 1.3 - Ta = 25°C Ta = 25°C 1.6 - Ta = 55°C 1.8 - Ta = 85°C 2.1 - Ta = 105°C 2.3 - Ta = 25°C 1.7 - Ta = 55°C 1.9 - Ta = 85°C 2.2 - Ta = 105°C 2.4 - VBATT = 3.3 V SOMCR.SORDRV[1:0] = 11b (Low power mode 3) VBATT = 2.0 V SOMCR.SORDRV[1:0] = 00b (Normal mode) VBATT = 3.3 V SOMCR.SORDRV[1:0] = 00b (Normal mode) Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Figure 2.24 Temperature dependency of RTC operation with VCC off (reference data) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 60 of 145 S3A1 Datasheet Table 2.14 2. Electrical Characteristics Operating and standby current (4) Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VREFH0 = 2.7 V to AVCC0 Parameter Analog power supply current Reference power supply current Symbol During A/D conversion (at high-speed conversion) Typ Max Unit Test conditions - - 3.0 mA - During A/D conversion (at low power conversion) - - 1.0 mA - During D/A conversion (per channel)*1 - 0.4 0.8 mA - Waiting for A/D and D/A conversion (all units)*6 - - 1.0 μA - - - 150 μA - - - 60 nA - - 50 100 μA - During A/D conversion IAVCC Min IREFH0 Waiting for A/D conversion (all units) During D/A conversion IREFH - - 100 μA - Temperature sensor Waiting for D/A conversion (all units) ITNS - 75 - μA - Low-Power Analog Comparator operating current Window mode ICMPLP - 15 - μA - Comparator High-speed mode - 10 - μA - Comparator Low-speed mode - 2 - μA - - 820 - μA - Operational Amplifier operating current Low power mode - 2.5 4.0 μA - 2 units operating - 4.5 8.0 μA - 3 units operating - 6.5 11.0 μA - 4 units operating - 8.5 14.0 μA - Comparator Low-speed mode using DAC8 High speed mode 1 unit operating IAMP 1 unit operating - 140 220 μA - 2 units operating - 280 410 μA - 3 units operating - 420 600 μA - 4 units operating LCD operating current USB operating current Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. - 560 780 μA - External resistance division method fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD1*5 - 0.34 - μA - Internal voltage boosting method (VLCD.VLCD = 04) fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD2*5 - 0.92 - μA - Capacitor split method fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD3*5 - 0.19 - μA - During USB communication operation under the following settings and conditions:  Host controller operation is set to full-speed mode Bulk OUT transfer (64 bytes) × 1, bulk IN transfer (64 bytes) × 1  Connect peripheral devices via a 1-meter USB cable from the USB port. IUSBH*2 - 4.3 (VCC) 0.9 (VCC_USB)*4 - mA - During USB communication operation under the following settings and conditions:  Device controller operation is set to full-speed mode Bulk OUT transfer (64 bytes) × 1, bulk IN transfer (64 bytes) × 1  Connect the host device via a 1-meter USB cable from the USB port. IUSBF*2 - 3.6 (VCC) 1.1 (VCC_USB)*4 - mA - During suspended state under the following setting and conditions:  Device controller operation is set to full-speed mode (pull up the USB_DP pin)  Software standby mode  Connect the host device via a 1-meter USB cable from the USB port. ISUSP*3 - 0.35 (VCC) 170 (VCC_USB)*4 - μA - The reference power supply current is included in the power supply current value for D/A conversion. Current consumed only by the USBFS. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition to the current consumed by the MCU during the suspended state. When VCC = VCC_USB = 3.3 V. Current flowing only to the LCD controller. Not including the current that flows through the LCD panel. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC140 Module Stop bit) is in the module-stop state. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 61 of 145 S3A1 Datasheet 2.2.10 2. Electrical Characteristics VCC Rise and Fall Gradient and Ripple Frequency Table 2.15 Rise and fall gradient characteristics Conditions: VCC = AVCC0 = 0 to 5.5 V Parameter Power-on VCC rising gradient Note 1. Note 2. Symbol Min Typ Max Unit Test conditions SrVCC 0.02 - 2 ms/V - Voltage monitor 0 reset enabled at startup*1 0.02 - - SCI/USB Boot mode*2 0.02 - 2 Voltage monitor 0 reset disabled at startup (normal startup) When OFS1.LVDAS = 0. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit. Table 2.16 Rising and falling gradient and ripple frequency characteristics Conditions: VCC = AVCC0 = VCC_USB = 1.6 to 5.5 V The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit (1.6 V). When VCC change exceeds VCC ± 10%, the allowable voltage change rising/falling gradient dt/dVCC must be met. Parameter Symbol Min Typ Max Unit Test conditions Allowable ripple frequency fr(VCC) - - 10 kHz Figure 2.25 Vr(VCC) ≤ VCC × 0.2 - - 1 MHz Figure 2.25 Vr(VCC) ≤ VCC × 0.08 - - 10 MHz Figure 2.25 Vr(VCC) ≤ VCC × 0.06 1.0 - - ms/V When VCC change exceeds VCC ± 10% Allowable voltage change rising and falling gradient dt/dVCC 1/fr(VCC) VCC Figure 2.25 Vr(VCC) Ripple waveform R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 62 of 145 S3A1 Datasheet 2.3 2. Electrical Characteristics AC Characteristics 2.3.1 Frequency Table 2.17 Operation frequency value in high-speed operating mode Conditions: VCC = AVCC0 = 2.4 to 5.5 V Symbol Min Typ Max*5 Unit f 0.032768 - 48 MHz 2.4 to 2.7 V 0.032768 - 16 2.7 to 5.5 V 0.032768 - 32 2.4 to 2.7 V 0.032768 - 16 2.7 to 5.5 V - - 48 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 32 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 64 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 64 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 24 2.4 to 2.7 V - - 16 Parameter Operation frequency System clock (ICLK)*4 FlashIF clock (FCLK)*1, *2, *4 Peripheral module clock Peripheral module clock Peripheral module clock Peripheral module clock External bus clock EBCLK pin output Note 1. Note 2. Note 3. Note 4. Note 5. 2.7 to 5.5 V (PCLKA)*4 (PCLKB)*4 (PCLKC)*3, *4 (PCLKD)*4 (BCLK)*4 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 8 The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. See section 9, Clock Generation Circuit in the User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. The maximum value of operation frequency does not include the internal oscillator errors. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.22, Clock timing. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 63 of 145 S3A1 Datasheet Table 2.18 2. Electrical Characteristics Operation frequency value in Middle-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Symbol Min Typ Max*5 Unit f 0.032768 - 12 MHz 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 2.7 to 5.5 V 0.032768 - 12 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 Parameter Operation frequency System clock (ICLK)*4 FlashIF clock 2.7 to 5.5 V (FCLK)*1, *2, *4 Peripheral module clock (PCLKA)*4 Peripheral module clock Peripheral module clock (PCLKB)*4 (PCLKC)*3, *4 Peripheral module clock (PCLKD)*4 External bus clock (BCLK)*4 EBCLK pin output Note 1. Note 2. Note 3. Note 4. Note 5. 1.8 to 2.4 V - - 8 2.7 to 3.6 V - - 12 2.4 to 2.7 V - - 8 1.8 to 2.4 V - - 8 The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. See section 9, Clock Generation Circuit in the User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. The maximum value of operation frequency does not include errors of the internal oscillator. The operation can be guaranteed with errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.22, Clock timing. Table 2.19 Operation frequency value in Low-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Operation frequency Min Typ Max*4 Unit f 0.032768 - 1 MHz System clock (ICLK)*3 1.8 to 5.5 V FlashIF clock (FCLK)*1, *3 1.8 to 5.5 V 0.032768 - 1 Peripheral module clock (PCLKA)*3 1.8 to 5.5 V - - 1 (PCLKB)*3 1.8 to 5.5 V - - 1 1.8 to 5.5 V - - 1 Peripheral module clock Peripheral module clock (PCLKC)*2, *3 Peripheral module clock Note 1. Note 2. Symbol (PCLKD)*3 1.8 to 5.5 V - - 1 External bus clock (BCLK)*3 1.8 to 5.5 V - - 1 EBCLK pin output 1.8 to 5.5 V - - 1 The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. The lower-limit frequency of PCLKC is 1 MHz when the A/D converter is in use. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 64 of 145 S3A1 Datasheet Note 3. Note 4. 2. Electrical Characteristics See section 9, Clock Generation Circuit in the User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. The maximum value of operation frequency does not include the internal oscillator errors. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.22, Clock timing. Table 2.20 Operation frequency value in Low-voltage mode Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Operation frequency Note 4. Note 5. Max*5 Unit f 0.032768 - 4 MHz FlashIF clock (FCLK)*1, *2, *4 1.6 to 5.5 V 0.032768 - 4 Peripheral module clock (PCLKA)*4 1.6 to 5.5 V - - 4 (PCLKB)*4 1.6 to 5.5 V - - 4 1.6 to 5.5 V - - 4 Peripheral module clock Note 3. Typ 1.6 to 5.5 V Peripheral module clock (PCLKC)*3, *4 Note 2. Min System clock (ICLK)*4 Peripheral module clock Note 1. Symbol (PCLKD)*4 1.6 to 5.5 V - - 4 External bus clock (BCLK)*4 1.6 to 5.5 V - - 4 EBCLK pin output 1.8 to 5.5 V - - 4 1.6 to 1.8 V - - 2 The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. See section 9, Clock Generation Circuit in the User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. The maximum value of operation frequency does not include errors of the internal oscillator. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.22, Clock timing. Table 2.21 Operation frequency value in Subosc-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Operation frequency Symbol System clock (ICLK)*3 Unit kHz 27.8528 32.768 37.6832 27.8528 32.768 37.6832 Peripheral module clock (PCLKA)*3 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKB)*3 1.8 to 5.5 V - - 37.6832 1.8 to 5.5 V - - 37.6832 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKD)*3 External bus clock EBCLK pin output Note 1. Note 2. Note 3. Max 1.8 to 5.5 V (PCLKC)*2, *3 (BCLK)*3 f Typ FlashIF clock (FCLK)*1, *3 Peripheral module clock 1.8 to 5.5 V Min 1.8 to 5.5 V - - 37.6832 1.8 to 5.5 V - - 37.6832 Programming and erasing the flash memory are not possible. The 14-bit A/D converter cannot be used. See section 9, Clock Generation Circuit in the User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 65 of 145 S3A1 Datasheet 2.3.2 Table 2.22 2. Electrical Characteristics Clock Timing Clock timing (1 of 2) Parameter EBCLK pin output cycle time EBCLK pin output high pulse width Symbol Min Typ Max Unit Test conditions tBcyc 83.3 - - ns Figure 2.26 VCC = 1.8 V or above 125 - - VCC = 1.6 V or above 500 - - VCC = 2.7 V or above VCC = 2.7 V or above tCH 20 - - 30 - - 150 - - 20 - - VCC = 1.8 V or above 30 - - VCC = 1.6 V or above 150 - - VCC = 1.8 V or above VCC = 1.6 V or above EBCLK pin output low pulse width EBCLK pin output rise time EBCLK pin output fall time VCC = 2.7 V or above VCC = 2.7 V or above tCL tCr - - 15 VCC = 2.4 V or above - - 25 VCC = 1.8 V or above - - 30 VCC = 1.6 V or above - - 50 VCC = 2.7 V or above tCf - - 15 VCC = 2.4 V or above - - 25 VCC = 1.8 V or above - - 30 VCC = 1.6 V or above - - 50 ns ns ns ns EXTAL external clock input cycle time tXcyc 50 - - ns EXTAL external clock input high pulse width tXH 20 - - ns EXTAL external clock input low pulse width tXL 20 - - ns EXTAL external clock rising time tXr - - 5 ns EXTAL external clock falling time tXf - - 5 ns EXTAL external clock input wait time*1 tEXWT 0.3 - - μs - EXTAL external clock input frequency fEXTAL - - 20 MHz 2.4 ≤ VCC ≤ 5.5 - - 8 Main clock oscillator oscillation frequency fMAIN 1.8 ≤ VCC < 2.4 - - 1 1 - 20 1.6 ≤ VCC < 1.8 1 - 8 1.8 ≤ VCC < 2.4 1 - 4 1.6 ≤ VCC < 1.8 MHz 2.4 ≤ VCC ≤ 5.5 tMAINOSCWT - - -*9 ms - fLOCO 27.8528 32.768 37.6832 kHz - LOCO clock oscillation stabilization time tLOCO - - 100 μs Figure 2.28 IWDT-dedicated clock oscillation frequency fILOCO 12.75 15 17.25 kHz - MOCO clock oscillation frequency fMOCO 6.8 8 9.2 MHz - MOCO clock oscillation stabilization time tMOCO - - 1 μs - Main clock oscillation stabilization wait time LOCO clock oscillation frequency R01DS0324EU0100 Rev.1.00 Oct 30, 2017 (crystal)*9 Figure 2.27 Page 66 of 145 S3A1 Datasheet Table 2.22 2. Electrical Characteristics Clock timing (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions HOCO clock oscillation frequency fHOCO24 23.64 24 24.36 MHz Ta = –40 to –20°C 1.8 ≤ VCC ≤ 5.5 22.68 24 25.32 Ta = –40 to 85°C 1.6 ≤ VCC < 1.8 23.76 24 24.24 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 23.52 24 24.48 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 31.52 32 32.48 Ta = –40 to -20°C 1.8 ≤ VCC ≤ 5.5 30.24 32 33.76 Ta = –40 to 85°C 1.6 ≤ VCC < 1.8 31.68 32 32.32 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 31.36 32 32.64 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 47.28 48 48.72 Ta = –40 to –20°C 1.8 ≤ VCC ≤ 5.5 47.52 48 48.48 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 47.04 48 48.96 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 63.04 64 64.96 Ta = –40 to –20°C 2.4 ≤ VCC ≤ 5.5 63.36 64 64.64 Ta = –20 to 85°C 2.4 ≤ VCC ≤ 5.5 62.72 64 65.28 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 tHOCO24 tHOCO32 - - 37.1 tHOCO48 - - 43.3 fHOCO32 fHOCO48*4 fHOCO64*5 HOCO clock oscillation stabilization time*6, *7 Except Low-voltage mode μs Figure 2.29 - tHOCO64 - - 80.6 tHOCO24 tHOCO32 tHOCO48 tHOCO64 - - 100.9 fPLLIN 4 - 12.5 MHz fPLL 24 - 64 MHz - tPLL - - 55.5 μs Figure 2.31 PLL free-running oscillation frequency fPLLFR - 8 - MHz - Sub-clock oscillator oscillation frequency fSUB - 32.768 - kHz - Sub-clock oscillation stabilization time*3 tSUBOSC - - -*3 s Figure 2.32 Low-voltage mode PLL input frequency*2 PLL circuit oscillation frequency*2 PLL clock oscillation stabilization time*8 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Time until the clock can be used after the Main Clock Oscillator Stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the external clock is stable. The VCC range that the PLL can be used is 2.4 to 5.5 V. After changing the setting of the SOSCCR.SOSTP bit so that the sub-clock oscillator operates, only start using the sub-clock oscillator after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time recommended by the oscillator manufacturer. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V. This is a characteristic when HOCOCR.HCSTP bit is set to 0 (oscillation) in MOCO stop state. When HOCOCR.HCSTP bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 μs. Whether stabilization time has elapsed can be confirmed by OSCSF.HOCOSF. This is a characteristic when PLLCR.PLLSTP bit is set to 0 (operation) in MOCO stop state. When PLLCR.PLLSTP bit is set to 0 (operation) during MOCO oscillation, this specification is shortened by 1 μs. When setting up the main clock, ask the oscillator manufacturer for an oscillation evaluation and use the results as the recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended stabilization time. After changing the setting of the MOSCCR.MOSTP bit so that the main clock oscillator operates, read the OSCSF.MOSCSF flag to confirm that it is 1, then start using the main clock. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 67 of 145 S3A1 Datasheet 2. Electrical Characteristics tBcyc tCH tCf EBCLK pin output tCr tCL Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Figure 2.26 EBCLK pin output timing tXcyc tXL tXH EXTAL external clock input VCC × 0.5 tXr Figure 2.27 tXf EXTAL external clock input timing LOCOCR.LCSTP tLOCO LOCO clock oscillator output Figure 2.28 LOCO clock oscillation start timing HOCOCR.HCSTP tHOCOx*1 HOCO clock Note 1. Figure 2.29 x = 24, 32, 48, 64 HOCO clock oscillation start timing (started by setting HOCOCR.HCSTP bit) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 68 of 145 S3A1 Datasheet 2. Electrical Characteristics MOSCCR.MOSTP Main clock oscillator output tMAINOSCWT Main clock Figure 2.30 Main clock oscillation start timing PLLCR.PLLSTP tPLL PLL clock Figure 2.31 PLL clock oscillation start timing (PLL is operated after main clock oscillation has settled) SOSCCR.SOSTP tSUBOSC Sub-clock oscillator output Figure 2.32 Sub-clock oscillation start timing MOCOCR.MCSTP tMOCO MOCO clock oscillator output Figure 2.33 MOCO clock oscillation start timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 69 of 145 S3A1 Datasheet 2.3.3 2. Electrical Characteristics Reset Timing Table 2.23 Reset timing Symbol Min Typ Max Unit Test conditions At power-on tRESWP 3 - - ms Figure 2.34 Other than above tRESW 30 - - μs Figure 2.35 tRESWT - 0.7 - ms Figure 2.34 - 0.3 - - 0.5 - ms Figure 2.35 - 0.05 - - 0.6 - - 0.15 - Parameter RES pulse width Wait time after RES cancellation (at power-on) LVD0: LVD0: disable*2 LVD0: enable*1 Wait time after RES cancellation (during powered-on state) LVD0: Internal reset cancellation time (Watchdog timer reset, SRAM parity error reset, SRAM ECC error reset, Bus master MPU error reset, Bus slave MPU error reset, Stack pointer error reset, Software reset) Note 1. Note 2. enable*1 tRESWT2 disable*2 LVD0: enable*1 tRESWT3 LVD0: disable*2 ms When OFS1.LVDAS = 0. When OFS1.LVDAS = 1. VCC RES tRESWP Internal reset tRESWT Figure 2.34 Reset input timing at power-on tRESW RES Internal reset tRESWT2 Figure 2.35 Reset input timing (1) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 70 of 145 S3A1 Datasheet 2.3.4 2. Electrical Characteristics Wakeup Time Table 2.24 Timing of recovery from low power modes (1) Parameter Recovery time from Software Standby mode*1 Note 1. Note 2. Note 3. Note 4. Note 5. High-speed mode Typ Max Unit Test conditions Figure 2.36 Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz)*2 tSBYMC - 2 3 ms System clock source is PLL (48 MHz) with Main clock oscillator*2 tSBYPC - 2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz)*3 tSBYEX - 14 25 μs System clock source is PLL (48 MHz) with Main clock oscillator*3 tSBYPE - 53 76 μs System clock source is HOCO*4 (HOCO clock is 32 MHz) tSBYHO - 43 52 μs System clock source is HOCO*4 (HOCO clock is 48 MHz) tSBYHO - 44 52 μs System clock source is HOCO*5 (HOCO clock is 64 MHz) tSBYHO - 82 110 μs System clock source is MOCO tSBYMO - 16 25 μs Timing of recovery from low power modes (2) Parameter Recovery time from Software Standby mode*1 Note 2. Note 3. Min The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h. Table 2.25 Note 1. Symbol Middle-speed mode Symbol Min Typ Max Unit Test conditions Figure 2.36 Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (12 MHz)*2 tSBYMC - 2 3 ms System clock source is PLL (24 MHz) with main clock oscillator*2 tSBYPC - 2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (12 MHz)*3 tSBYEX - 2.9 10 μs System clock source is PLL (24 MHz) with main clock oscillator*3 tSBYPE - 49 76 μs System clock source is HOCO (24 MHz) tSBYHO - 38 50 μs System clock source is MOCO tSBYMO - 3.5 5.5 μs The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 71 of 145 S3A1 Datasheet Table 2.26 2. Electrical Characteristics Timing of recovery from low power modes (3) Parameter Recovery time from Software Standby mode*1 Low-speed mode Note 2. Note 3. Unit Test conditions Figure 2.36 tSBYMC - 2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (1 MHz)*3 tSBYEX - 28 50 μs tSBYMO - 25 35 μs Timing of recovery from low power modes (4) Recovery time from Software Standby mode*1 Low-voltage mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator External clock input to main clock oscillator System clock source is main clock oscillator Symbol Min Typ Max Unit Test conditions tSBYMC - 2 3 ms Figure 2.36 tSBYEX - 108 130 μs tSBYHO - 108 130 μs (4 MHz)*2 (4 MHz)*3 System clock source is HOCO The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined by the following expression. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Table 2.28 Timing of recovery from low power modes (5) Symbol Min Typ Max Unit Test conditions System clock source is sub-clock oscillator (32.768 kHz) tSBYSC - 0.85 1 ms Figure 2.36 System clock source is LOCO (32.768 kHz) tSBYLO - 0.85 1.2 ms Parameter Recovery time from Software Standby mode*1 Note 1. Max System clock source is main clock oscillator (1 MHz)*2 Parameter Note 2. Note 3. Typ The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Table 2.27 Note 1. Min Crystal resonator connected to main clock oscillator System clock source is MOCO Note 1. Symbol Subosc-speed mode The sub-clock oscillator or LOCO itself continues to oscillate in Software Standby mode during Subosc-speed mode. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 72 of 145 S3A1 Datasheet 2. Electrical Characteristics Oscillator ICLK IRQ Software Standby mode tSBYMC, tSBYPC, tSBYEX, tSBYPE, tSBYMO, tSBYHO Oscillator ICLK IRQ Software Standby mode tSBYSC, tSBYLO Figure 2.36 Software Standby mode cancellation timing Table 2.29 Timing of recovery from low power modes (6) Parameter Recovery time from Software Standby mode to Snooze mode Symbol Min Typ Max Unit Test conditions High-speed mode System clock source is HOCO tSNZ - 36 45 μs Figure 2.37 Middle-speed mode System clock source is MOCO tSNZ - 1.3 3.6 μs Low-speed mode System clock source is MOCO tSNZ - 10 13 μs Low-voltage mode System clock source is HOCO tSNZ - 87 110 μs Oscillator ICLK (except DTC, SRAM) ICLK (to DTC, SRAM)*1 PCLK IRQ Software Standby mode Snooze mode tSNZ Note 1. Figure 2.37 When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM. Recovery timing from Software Standby mode to Snooze mode R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 73 of 145 S3A1 Datasheet 2.3.5 2. Electrical Characteristics NMI and IRQ Noise Filter Table 2.30 NMI and IRQ noise filter Parameter Symbol Min Typ Max Unit Test conditions NMI pulse width tNMIW 200 - - ns NMI digital filter disabled tPcyc × 2 ≤ 200 ns - - 200 - - NMI digital filter enabled tNMICK × 3 ≤ 200 ns tNMICK × 3.5*2 - - 200 - - tPcyc × 2*1 - - 200 - - - - tPcyc × IRQ pulse width tIRQW 2*1 tIRQCK × Note: Note 1. Note 2. Note 3. 3.5*3 tPcyc × 2 > 200 ns tNMICK × 3 > 200 ns ns IRQ digital filter disabled tPcyc × 2 ≤ 200 ns tPcyc × 2 > 200 ns IRQ digital filter enabled tIRQCK × 3 ≤ 200 ns tIRQCK × 3 > 200 ns 200 ns minimum in Software Standby mode. tPcyc indicates the cycle of PCLKB. tNMICK indicates the cycle of the NMI digital filter sampling clock. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 15). NMI tNMIW Figure 2.38 NMI interrupt input timing IRQ tIRQW Figure 2.39 IRQ interrupt input timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 74 of 145 S3A1 Datasheet 2.3.6 2. Electrical Characteristics Bus Timing Table 2.31 Bus timing (1) Conditions: Low drive output is selected in the Port Drive Capability in PmnPFS register VCC = 2.7 to 5.5 V Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions Address delay tAD - 55 ns Byte control delay tBCD - 55 ns Figure 2.42 to Figure 2.45 CS delay tCSD - 55 ns ALE delay time tALED - 55 ns RD delay tRSD - 55 ns Read data setup time tRDS 37 - ns Read data hold time tRDH 0 - ns WR delay tWRD - 55 ns Write data delay tWDD - 55 ns Write data hold time tWDH 0 - ns WAIT setup time tWTS 37 - ns WAIT hold time tWTH 0 - ns Table 2.32 Figure 2.46 Bus timing (2) Conditions: Low drive output is selected in the Port Drive Capability in PmnPFS register VCC = 2.4 to 2.7 V Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions Address delay tAD - 55 ns Byte control delay tBCD - 55 ns Figure 2.42 to Figure 2.45 CS delay tCSD - 55 ns ALE delay time tALED - 55 ns RD delay tRSD - 55 ns Read data setup time tRDS 45 - ns Read data hold time tRDH 0 - ns WR delay tWRD - 55 ns Write data delay tWDD - 55 ns Write data hold time tWDH 0 - ns WAIT setup time tWTS 45 - ns WAIT hold time tWTH 0 - ns R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Figure 2.46 Page 75 of 145 S3A1 Datasheet Table 2.33 2. Electrical Characteristics Bus timing (3) Conditions: Low drive output is selected in the Port Drive Capability in PmnPFS register VCC = 1.8 to 2.4 V Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions Address delay tAD - 90 ns Byte control delay tBCD - 90 ns Figure 2.42 to Figure 2.45 CS delay tCSD - 90 ns ALE delay time tALED - 90 ns RD delay tRSD - 90 ns Read data setup time tRDS 70 - ns Read data hold time tRDH 0 - ns WR delay tWRD - 90 ns Write data delay tWDD - 90 ns Write data hold time tWDH 0 - ns WAIT setup time tWTS 70 - ns WAIT hold time tWTH 0 - ns Table 2.34 Figure 2.46 Bus timing (4) Conditions: Low drive output is selected in the Port Drive Capability in PmnPFS register VCC = 1.6 to 1.8 V Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions Address delay tAD - 120 ns Byte control delay tBCD - 120 ns Figure 2.42 to Figure 2.45 CS delay tCSD - 120 ns ALE delay time tALED - 120 ns RD delay tRSD - 120 ns Read data setup time tRDS 90 - ns Read data hold time tRDH 0 - ns WR delay tWRD - 120 ns Write data delay tWDD - 120 ns Write data hold time tWDH 0 - ns WAIT setup time tWTS 90 - ns WAIT hold time tWTH 0 - ns R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Figure 2.46 Page 76 of 145 S3A1 Datasheet 2. Electrical Characteristics Data cycle Address cycle Ta1 Ta1 Tan TW1 TW2 TW3 TW4 Tend TW5 Tn1 Tn2 EBCLK tAD A23 to A00 tAD A15/D15 to A00/ D00 (Read) tRDS tAD tRDH tALED tALED ALE tRSD tRSD RD (Read) tCSD tCSD CS3 to CS0 Figure 2.40 Address/data multiplexed bus read access timing Data cycle Address cycle Ta1 Ta1 Tan TW1 TW2 TW3 TW4 TW5 Tend Tn1 Tn2 Tn3 EBCLK tAD A23 to A00 A15/D15 to A00/ D00 (Write) tAD tAD tALED tWDD tWDH tALED ALE tWRD tWRD WR1, WR0, WR (Write) tCSD tCSD CS3 to CS0 Figure 2.41 Address/data multiplexed bus write access timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 77 of 145 S3A1 Datasheet 2. Electrical Characteristics CSRWAIT: 2 RDON:1 CSROFF: 2 CSON: 0 TW1 TW2 Tend Tn1 Tn2 EBCLK Byte strobe mode tAD tAD tAD tAD A23 to A00 1-write strobe mode A23 to A01 tBCD tBCD tCSD tCSD BC1, BC0 Common to both byte strobe mode and 1-write strobe mode CS3 to CS0 tRSD tRSD RD (Read) tRDS tRDH D15 to D00 (Read) Figure 2.42 External bus timing/normal read cycle (bus clock synchronized) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 78 of 145 S3A1 Datasheet 2. Electrical Characteristics CSWWAIT: 2 WRON: 1 WDON: 1*1 CSWOFF: 2 WDOFF: 1*1 CSON:0 TW1 TW2 Tend Tn1 Tn2 EBCLK Byte strobe mode tAD tAD tAD tAD A23 to A00 1-write strobe mode A23 to A01 tBCD tBCD tCSD tCSD BC1 to BC0 Common to both byte strobe mode and 1-write strobe mode CS3 to CS0 tWRD tWRD WR1, WR0, WR (Write) tWDD tWDH D15 to D00 (Write) Note 1. Figure 2.43 Be sure to specify WDON and WDOFF as at least 1 cycle of EBCLK. External bus timing/normal write cycle (bus clock synchronized) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 79 of 145 S3A1 Datasheet 2. Electrical Characteristics CSRWAIT:2 CSPRWAIT:2 RDON:1 CSON:0 TW1 TW2 Tend CSPRWAIT:2 CSPRWAIT:2 RDON:1 RDON:1 Tpw1 Tpw2 Tend CSROFF:2 RDON:1 Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tn1 Tn2 EBCLK Byte strobe mode tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD A23 to A00 1-write strobe mode A23 to A01 tBCD tBCD tCSD tCSD BC1, BC0 Common to both byte strobe mode and 1-write strobe mode CS3 to CS0 tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD RD (Read) tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH D15 to D00 (Read) Figure 2.44 External bus timing/page read cycle (bus clock synchronized) CSPWWAIT:2 CSWWAIT:2 WRON:1 WDON:1*1 WDOFF:1*1 CSON:0 TW1 TW2 Tend Tdw1 WRON:1 WDON:1*1 Tpw1 CSPWWAIT:2 WDOFF:1*1 Tpw2 Tend Tdw1 WRON:1 WDON:1*1 Tpw1 CSWOFF:2 WDOFF:1*1 Tpw2 Tend Tn1 Tn2 EBCLK Byte strobe mode tAD tAD tAD tAD tAD tAD tAD tAD A23 to A00 1-write strobe mode A23 to A01 tBCD tBCD tCSD tCSD BC1, BC0 Common to both byte strobe mode and 1-write strobe mode CS3 to CS0 tWRD tWRD tWRD tWRD tWRD tWRD WR1, WR0, WR (Write) tWDD tWDH tWDD tWDH tWDD tWDH D15 to D00 (Write) Note 1. Figure 2.45 Be sure to specify WDON and WDOFF as at least 1 cycle of EBCLK. External bus timing/page write cycle (bus clock synchronized) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 80 of 145 S3A1 Datasheet 2. Electrical Characteristics CSRWAIT:3 CSWWAIT:3 TW1 TW2 TW3 (Tend) Tend Tn1 Tn2 EBCLK A23 to A00 CS3 to CS0 RD (Read) WR (Write) External wait tWTS tWTH tWTS tWTH WAIT Figure 2.46 External bus timing/external wait control R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 81 of 145 S3A1 Datasheet 2.3.7 2. Electrical Characteristics I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing Table 2.35 I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing Symbol Min Max Unit Test conditions Input data pulse width tPRW 1.5 - tPcyc Figure 2.47 Input/output data cycle (P002, P003, P004, P007) tPOcyc 10 - us tPOEW 3 - tPcyc Figure 2.48 tGTICW 1.5 - tPDcyc Figure 2.49 2.5 Figure 2.50 Parameter I/O ports POEG POEG input trigger pulse width GPT Input capture pulse width Single edge Dual edge AGT AGTIO, AGTEE input cycle *1 250 - ns 2.4 V ≤ VCC < 2.7 V 500 - ns 1.8 V ≤ VCC < 2.4 V 1000 - ns 2.7 V ≤ VCC ≤ 5.5 V tACYC 1.6 V ≤ VCC < 1.8 V AGTIO, AGTEE input high level width, low-level width AGTIO, AGTO, AGTOA, AGTOB output frequency 2.7 V ≤ VCC ≤ 5.5 V 2.4 V ≤ VCC < 2.7 V tACKWH, tACKWL 2000 - ns 100 - ns 200 - ns 1.8 V ≤ VCC < 2.4 V 400 - ns 1.6 V ≤ VCC < 1.8 V 800 - ns 62.5 - ns 2.7 V ≤ VCC ≤ 5.5 V tACYC2 2.4 V ≤ VCC < 2.7 V 125 - ns 1.8 V ≤ VCC < 2.4 V 250 - ns 1.6 V ≤ VCC < 1.8 V 500 - ns Figure 2.50 ADC14 14-bit A/D converter trigger input pulse width tTRGW 1.5 - tPcyc Figure 2.51 KINT Key interrupt input low-level width tKR 250 - ns Figure 2.52 Note 1. Note: Constraints on AGTIO input: tPcyc × 2 < tACYC tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle Port tPRW Figure 2.47 I/O ports input timing POEG input trigger tPOEW Figure 2.48 POEG input trigger timing Input capture tGTICW Figure 2.49 GPT input capture timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 82 of 145 S3A1 Datasheet 2. Electrical Characteristics tACYC tACKWL tACKWH AGTIO, AGTEE (input) tACYC2 AGTIO, AGTO, AGTOA, AGTOB (output) Figure 2.50 AGT I/O timing ADTRG0 tTRGW Figure 2.51 ADC14 trigger input timing KR00 to KR07 tKR Figure 2.52 2.3.8 Key interrupt input timing CAC Timing Table 2.36 CAC timing Parameter CAC CACREF input pulse width tPBcyc*1 ≤ tcac*2 tPBcyc*1 Note 1. Note 2. > tcac*2 Typ Max Unit Test conditions 4.5 × tcac + 3 × tPBcyc*1 - - ns - tPBcyc*1 - - ns Symbol Min tCACREF 5 × tcac + 6.5 × tPBcyc: PCLKB cycle. tcac: CAC count clock source cycle. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 83 of 145 S3A1 Datasheet 2.3.9 2. Electrical Characteristics SCI Timing Table 2.37 SCI timing (1) Parameter SCI Symbol Input clock cycle Asynchronous tScyc Clock synchronous Unit*1 Test conditions 4 - tPcyc Figure 2.53 6 - Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr - 20 ns tSCKf - 20 ns tScyc 6 - tPcyc 4 - 0.4 0.6 tScyc - 20 ns - 30 Input clock fall time Output clock cycle Asynchronous Clock synchronous Output clock pulse width Output clock rise time tSCKW 1.8 V or above tSCKr 1.6 V or above Output clock fall time 1.8 V or above tSCKf 1.6 V or above - 20 - 30 Transmit data delay (master) Clock synchronous 1.8 V or above - 40 1.6 V or above - 45 Transmit data delay (slave) Clock synchronous 2.7 V or above - 55 2.4 V or above - 60 1.8 V or above - 100 - 125 45 - 2.4 V or above 55 - 1.8 V or above 90 - tTXD 1.6 V or above Receive data setup time (master) Note 1. Max Min Clock synchronous 2.7 V or above tRXS ns ns ns ns 1.6 V or above 110 - 2.7 V or above 40 - 45 - 5 - ns 40 - ns tSCKr tSCKf Receive data setup time (slave) Clock synchronous Receive data hold time (master) Clock synchronous tRXH Receive data hold time (slave) Clock synchronous tRXH 1.6 V or above Figure 2.54 ns tPcyc: PCLKA cycle. tSCKW SCKn (n = 0 to 4, 9) tScyc Figure 2.53 SCK clock input timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 84 of 145 S3A1 Datasheet 2. Electrical Characteristics SCKn tTXD TXDn tRXS tRXH RXDn n = 0 to 4, 9 Figure 2.54 Table 2.38 SCI input/output timing in clock synchronous mode SCI timing (2) (1 of 2) Parameter Symbol Simple SPI tSPcyc SCK clock cycle output (master) 0.4 0.6 tSPCKWL 0.4 0.6 tSPcyc - 20 ns - 30 45 - 2.4 V or above 55 - 1.8 V or above 80 - 1.6 V or above tSPCKr, tSPCKf Data input setup time 2.7 V or above tSU 1.6 V or above 110 - 2.7 V or above 40 - 1.6 V or above Master tH Slave SS input setup time SS input hold time 45 - 33.3 - tLAG 1 - tSPcyc tOD - 40 ns 1.6 V or above - 50 Slave 2.4 V or above - 65 1.8 V or above - 100 1.6 V or above - 125 –10 - 2.4 V or above –20 - 1.8 V or above –30 - tOH 1.6 V or above Master Slave R01DS0324EU0100 Rev.1.00 Oct 30, 2017 1.8 V or above tDr, tDf –40 - –10 - - 20 1.6 V or above - 30 1.8 V or above - 20 1.6 V or above - 30 Figure 2.56 to Figure 2.59 ns 1 1.8 V or above 2.7 V or above ns 40 Master Master tSPcyc tLEAD Slave Data rise and fall time Figure 2.55 tSPCKWH 1.8 V or above Data output hold time tPcyc 65536 SCK clock rise and fall time Data output delay Test conditions 65536 SCK clock low pulse width Data input hold time Unit 4 SCK clock high pulse width Slave Max 6 SCK clock cycle input (slave) Master Min tSPcyc ns ns Page 85 of 145 S3A1 Datasheet Table 2.38 2. Electrical Characteristics SCI timing (2) (2 of 2) Parameter Symbol Min Max Unit Test conditions Simple SPI Slave access time tSA - 10 (PCLKA > 32 MHz), 6 (PCLKA ≤ 32 MHz) tPcyc Figure 2.58 and Figure 2.59 Slave output release time tREL - 10 (PCLKA > 32 MHz), 6 (PCLKA ≤ 32 MHz) tPcyc tSPCKr tSPCKWH VOH SCKn master select output VOH VOL tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH VIH SCKn slave select input VIL (n = 0 to 4, 9) tSPCKf VIH VIL tSPCKWL VIH VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC Figure 2.55 SCI simple SPI mode clock timing SCKn CKPOL = 0 output SCKn CKPOL = 1 output tSU MISOn input tH MSB IN tDr, tDf MOSIn output DATA tOH MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT (n = 0 to 4, 9) Figure 2.56 SCI simple SPI mode timing (master, CKPH = 1) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 86 of 145 S3A1 Datasheet 2. Electrical Characteristics SCKn CKPOL = 1 output SCKn CKPOL = 0 output tSU MISOn input tH MSB IN tOH DATA LSB IN tOD MOSIn output MSB IN tDr, tDf MSB OUT DATA LSB OUT IDLE MSB OUT (n = 0 to 4, 9) Figure 2.57 SCI simple SPI mode timing (master, CKPH = 0) tTD SSn input tLEAD tLAG SCKn CKPOL = 0 input SCKn CKPOL = 1 input tSA tOH MISOn output MSB OUT tSU MOSIn input tOD DATA tREL LSB OUT tH MSB IN MSB IN MSB OUT tDr, tDf DATA LSB IN MSB IN (n = 0 to 4, 9) Figure 2.58 SCI simple SPI mode timing (slave, CKPH = 1) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 87 of 145 S3A1 Datasheet 2. Electrical Characteristics tTD SSn input tLEAD tLAG SCKn CKPOL = 1 input SCKn CKPOL = 0 input tSA tOH tOD LSB OUT (Last data) MISOn output MSB OUT tSU MOSIn input tREL LSB OUT DATA tH MSB OUT tDr, tDf MSB IN DATA LSB IN MSB IN (n = 0 to 4, 9) Figure 2.59 Table 2.39 SCI simple SPI mode timing (slave, CKPH = 0) SCI timing (3) Conditions: VCC = 2.7 to 5.5 V Parameter Simple IIC (Standard mode) Simple IIC (Fast mode) Note 1. Note 2. Symbol Min Max Unit Test conditions SDA input rise time tSr - 1000 ns Figure 2.60 SDA input fall time tSf - 300 ns *1 SDA input spike pulse removal time tSP 0 4 × tIICcyc Data input setup time tSDAS 250 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb*2 - 400 pF SDA input rise time tSr - 300 ns SDA input fall time tSf - 300 ns SDA input spike pulse removal time tSP 0 4 × tIICcyc*1 ns Data input setup time tSDAS 100 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb*2 - 400 pF ns Figure 2.60 For all ports except P408, use PmnPFS.DSCR of middle drive. For port P408, use PmnPFS.DSCR1/ DSCR of middle drive for IIC fast-mode. tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits. Cb indicates the total capacity of the bus line. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 88 of 145 S3A1 Datasheet 2. Electrical Characteristics VIH SDAn VIL tSr tSf tSP SCLn (n = 0 to 4, 9) P*1 tSDAH Note 1. Figure 2.60 S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Restart condition. P*1 Sr*1 S*1 tSDAS Test conditions: VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6 V, IOL = 6 mA SCI simple IIC mode timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 89 of 145 S3A1 Datasheet 2.3.10 Table 2.40 2. Electrical Characteristics SPI Timing SPI timing (1 of 2) Conditions: Middle drive output is selected in the Port Drive Capability in PmnPFS register Parameter SPI RSPCK clock cycle Master Symbol Min Max Unit*1 Test conditions tSPcyc 2*4 4096 tPcyc Figure 2.61 6 4096 (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 - 3 × tPcyc - (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 - 3 × tPcyc - Slave RSPCK clock high pulse width Master tSPCKWH Slave RSPCK clock low pulse width Master tSPCKWL Slave RSPCK clock rise and fall time Output 2.7 V or above tSPCKr, tSPCKf - 10 15 1.8 V or above - 20 1.6 V or above - 30 - 1 µs 10 - ns 2.4 V or above 10 - 1.8 V or above 15 - Master Slave tSU 1.6 V or above Data input hold time 20 - Master (RSPCK is PCLKA/2) tHF 0 - Master (RSPCK is other than above.) tH tPcyc - tH 20 - tLEAD -30 + N × tSpcyc*2 - tSpcyc*2 - Slave SSL setup time Master 1.8 V or above 1.6 V or above -50 + N × Slave SSL hold time Master Slave R01DS0324EU0100 Rev.1.00 Oct 30, 2017 ns - 2.4 V or above Input Data input setup time ns tLAG 6 × tPcyc - -30 + N × tSpcyc*3 - 6 × tPcyc - ns Figure 2.62 to Figure 2.67 ns ns Page 90 of 145 S3A1 Datasheet Table 2.40 2. Electrical Characteristics SPI timing (2 of 2) Conditions: Middle drive output is selected in the Port Drive Capability in PmnPFS register Symbol Min Max Unit*1 Test conditions tOD - 14 ns 2.4 V or above - 20 Figure 2.62 to Figure 2.67 1.8 V or above - 25 Parameter SPI Data output delay Master Slave 2.7 V or above 1.6 V or above - 30 2.7 V or above - 50 2.4 V or above - 60 1.8 V or above - 85 - 110 0 - 0 - tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × tPcyc 1.6 V or above Data output hold time Master Successive transmission delay Master tOH Slave tTD Slave MOSI and MISO rise and fall time Output 6 × tPcyc - - 10 2.4 V or above - 15 1.8 V or above - 20 2.7 V or above tDr, tDf 1.6 V or above Input SSL rise and fall time Output Note 1. Note 2. Note 3. Note 4. ns - 30 - 1 µs ns - 10 15 1.8 V or above - 20 1.6 V or above - 30 - 1 - 2 × tPcyc + 100 ns 1.8 V or above - 2 × tPcyc + 140 1.6 V or above - 2 × tPcyc + 180 tSSLr, tSSLf Input Slave output release time ns - 2.7 V or above 2.4 V or above Slave access time ns 2.4 V or above tSA µs - 2 × tPcyc + 100 ns 1.8 V or above - 2 × tPcyc + 140 1.6 V or above - 2 × tPcyc + 180 2.4 V or above tREL Figure 2.66 and Figure 2.67 tPcyc: PCLKA cycle. N is set as an integer from 1 to 8 by the SPCKD register. N is set as an integer from 1 to 8 by the SSLND register. The upper limit of RSPCK is 16 MHz. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 91 of 145 S3A1 Datasheet 2. Electrical Characteristics tSPCKr tSPCKWH VOH RSPCKn master select output VOH VOL tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH VIH RSPCKn slave select input Figure 2.61 VIH VIL (n = A or B) tSPCKf VIL tSPCKWL VIH VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC SPI clock timing tTD SSLn0 to SSLn3 output tLEAD tLAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn input tH MSB IN tDr, tDf MOSIn output DATA tOH MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT (n = A or B) Figure 2.62 SPI timing (master, CPHA = 0) (bit rate: PCLKA division ratio is set to any value other than 1/2) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 92 of 145 S3A1 Datasheet 2. Electrical Characteristics tTD SSLn0 to SSLn3 output tLEAD tLAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn tHF tHF MSB IN tDr, tDf MOSIn output LSB IN DATA tOH MSB OUT MSB IN tOD DATA LSB OUT IDLE MSB OUT (n = A or B) Figure 2.63 SPI timing (master, CPHA = 0) (bit rate: PCLKA division ratio is set to 1/2) tTD SSLn0 to SSLn3 output tLEAD tLAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn input tH MSB IN tOH MOSIn output DATA LSB IN tOD MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT (n = A or B) Figure 2.64 SPI timing (master, CPHA = 1) (bit rate: PCLKA division ratio is set to any value other than 1/2) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 93 of 145 S3A1 Datasheet 2. Electrical Characteristics tTD SSLn0 to SSLn3 output tLEAD tLAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn input tHF MSB IN tOH tH DATA LSB IN tOD MOSIn output MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT (n = A or B) Figure 2.65 SPI timing (master, CPHA = 1) (bit rate: PCLKA division ratio is set to 1/2) tTD SSLn0 input tLEAD tLAG RSPCKn CPOL = 0 input RSPCKn CPOL = 1 input tSA tOH MISOn output MSB OUT tSU MOSIn input tOD DATA tREL LSB OUT tH MSB IN MSB IN MSB OUT tDr, tDf DATA LSB IN MSB IN (n = A or B) Figure 2.66 SPI timing (slave, CPHA = 0) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 94 of 145 S3A1 Datasheet 2. Electrical Characteristics tTD SSLn0 input tLEAD tLAG RSPCKn CPOL = 0 input RSPCKn CPOL = 1 input tSA tOH tOD LSB OUT (Last data) MISOn output MSB OUT tSU MOSIn input tREL LSB OUT DATA tH MSB OUT tDr, tDf MSB IN DATA LSB IN MSB IN (n = A or B) Figure 2.67 2.3.11 SPI timing (slave, CPHA = 1) QSPI Timing Table 2.41 QSPI timing Conditions: VCC = 1.8 to 5.5 V Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register Symbol Min Max Unit*1 Test conditions QSPCLK clock cycle tQScyc 2*4 48 tPcyc Figure 2.68 QSPCLK clock high-level pulse width tQSWH tQScyc × 0.4 - ns QSPCLK clock low-level pulse width tQSWL tQScyc × 0.4 - ns Data input setup time tSU 25 - ns Data input hold time tIH 2 - ns SSL setup time tLEAD (N + 0.5) × tQscyc - 15*2 (N + 0.5) × tQscyc + 100*2 ns SSL hold time tLAG (N + 0.5) × tQscyc - 15*3 (N + 0.5) × tQscyc + 100*3 ns ns Parameter QSPI Data output delay 2.7 V or above tOD 2.4 V or above 1.8 V or above Data output hold time 2.7 V or above tOH 1.8 V or above Successive transmission delay Note 1. Note 2. Note 3. Note 4. tTD - 14 - 20 - 30 –3.3 - –10 - 1 16 Figure 2.69 ns tQscyc tPcyc: PCLKA cycle. N is set to 0 or 1 in SFMSLD. N is set to 0 or 1 in SFMSHD. The upper limit of QSPCLK is 16MHz. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 95 of 145 S3A1 Datasheet 2. Electrical Characteristics tQSWH tQSWL QSPCLK output tQScyc Figure 2.68 QSPI clock timing tTD QSSL output tLEAD tLAG QSPCLK output tSU QIO0 to 3 input tH MSB IN DATA tOH QIO0 to 3 output Figure 2.69 MSB OUT LSB IN tOD DATA LSB OUT IDLE Transfer/receive timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 96 of 145 S3A1 Datasheet 2.3.12 2. Electrical Characteristics IIC Timing Table 2.42 IIC timing Conditions: VCC = 2.7 to 5.5 V Symbol Min*1 Max Unit Test conditions SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 - ns Figure 2.70 SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time tSr - 1000 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 - ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1 (5) × tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time tSTOS 1000 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 400 pF SCL input cycle time tSCL 6 (12) × tIICcyc + 600 - ns SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time tSr - 300 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 - ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1(5) × tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time tSTOS 300 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 400 pF Parameter IIC (standard mode, SMBus) IIC (Fast mode) Note: Note 1. Figure 2.70 For all ports except P408, use PmnPFS.DSCR of middle drive. For port P408, use PmnPFS.DSCR 1/DSCR of middle drive for IIC fast-mode. tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle The value in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 97 of 145 S3A1 Datasheet 2. Electrical Characteristics VIH SDA0 to SDA2 VIL tBUF tSCLH tSTAH tSTAS tSTOS tSP SCL0 to SCL2 P*1 tSf tSCLL tSr tSCL Note 1. Figure 2.70 P*1 Sr*1 S*1 tSDAS tSDAH S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition I2C bus interface input/output timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 98 of 145 S3A1 Datasheet 2.3.13 Table 2.43 2. Electrical Characteristics SSIE Timing SSIE timing Conditions: VCC = 1.6 to 5.5 V Symbol Min Max Unit Test conditions tAUDIO - 25 MHz - - 4 tO 250 - ns Figure 2.71 tI 250 - ns tHC 100 - ns 200 - 100 - 200 - tRC - 25 ns tDTR - 65 ns 1.8 V or above - 105 1.6 V or above - 140 65 - 90 - Parameter SSIE AUDIO_CLK input frequency 2.7 V or above 1.6 V or above Output clock period Input clock period Clock high pulse width 1.8 V or above Clock low pulse width 1.8 V or above 1.6 V or above tLC 1.6 V or above Clock rise time Data delay 2.7 V or above Set-up time 2.7 V or above tSR 1.8 V or above 1.6 V or above Hold time SSITXD0 output delay from SSILRCK/SSIFS change time 1.8 V or above 1.6 V or above Figure 2.72, Figure 2.73 ns 140 - tHTR 40 - ns tDTRW - 105 ns - 140 Figure 2.74 tRC tHC SSIBCK0 ns tLC tI, tO Figure 2.71 SSIE clock input/output timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 99 of 145 S3A1 Datasheet 2. Electrical Characteristics SSIBCK0 (Input or Output) SSILRCK0/SSIFS0 (Input), SSIRXD0 (Input) tSR tHTR SSILRCK0/SSIFS0 (Output), SSITXD0 (Output) tDTR Figure 2.72 SSIE data transmit/receive timing (SSICR.BCKP = 0) SSIBCK0 (Input or Output) SSILRCK0/SSIFS0 (Input), SSIRXD0 (Input) tSR tHTR SSILRCK0/SSIFS0 (Output), SSITXD0 (Output) tDTR Figure 2.73 SSIE data transmit/receive timing (SSICR.BCKP = 1) SSILRCK0/SSIFS0 (Input) SSITXD0 (Output) tDTRW MSB bit output delay from SSILRCK0/SSIFS0 change time for slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] Figure 2.74 SSIE data output delay from SSILRCK0/SSIFS0 change time R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 100 of 145 S3A1 Datasheet 2.3.14 Table 2.44 2. Electrical Characteristics SD/MMC Host Interface Timing SD/MMC host interface signal timing Conditions: VCC = 2.7 to 5.5 V Middle drive output is selected in the Port Drive Capability in PmnPFS register Parameter Symbol Min Max Unit Test conditions SDCLK clock cycle tSDCYC 62.5 - ns Figure 2.75 SDCLK clock high-level pulse width tSDWH 18.25 - ns SDCLK clock low-level pulse width tSDWL 18.25 - ns SDCLK clock rising time tSDLH - 10 ns SDCLK clock falling time tSDHL - 10 ns SDCMD/SDDAT output data delay tSDODLY –18.25 18.25 ns SDCMD/SDDAT input data setup tSDIS 9.25 - ns SDCMD/SDDAT input data hold tSDIH 23.25 - ns tSDCYC tSDWL SD0CLK (output) tSDHL tSDODLY(max) tSDWH tSDLH tSDODLY(min) SD0CMD/SD0DATm (output) tSDIS tSDIH SD0CMD/SD0DATm (input) (m = 0 to 7) Figure 2.75 SD/MMC host interface signal timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 101 of 145 S3A1 Datasheet 2.3.15 2. Electrical Characteristics CLKOUT Timing Table 2.45 CLKOUT timing Symbol Min Max Unit*1 Test conditions tCcyc 62.5 - ns Figure 2.76 VCC = 1.8 V or above 125 - VCC = 1.6 V or above 250 - 15 - 30 - Parameter CLKOUT CLKOUT pin output cycle*1 CLKOUT pin high pulse width*2 VCC = 2.7 V or above VCC = 2.7 V or above tCH VCC = 1.8 V or above VCC = 1.6 V or above CLKOUT pin low pulse width*2 CLKOUT pin output rise time CLKOUT pin output fall time Note 1. Note 2. 150 - 15 - VCC = 1.8 V or above 30 - VCC = 1.6 V or above 150 - VCC = 2.7 V or above tCL - 12 VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 VCC = 2.7 V or above tCr - 12 VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 VCC = 2.7 V or above tCf ns ns ns ns When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%. When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b). tCcyc tCH tCf CLKOUT pin output tCL tCr Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Figure 2.76 CLKOUT output timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 102 of 145 S3A1 Datasheet 2.4 2. Electrical Characteristics USB Characteristics 2.4.1 Table 2.46 USBFS Timing USB characteristics Conditions: VCC = VCC_USB = 3.0 to 3.6 V, Ta = -20 to +85°C (USBCLKSEL = 1), Ta = -40 to +105°C (USBCLKSEL = 0) Parameter Input characteristics Output characteristics Symbol Min Max Unit Test conditions Input high level voltage VIH 2.0 - V - Input low level voltage VIL - 0.8 V - Differential input sensitivity VDI 0.2 - V | USB_DP - USB_DM | Differential common mode range VCM 0.8 2.5 V - Output high level voltage VOH 2.8 VCC_USB V IOH = –200 μA Output low level voltage VOL 0.0 0.3 V IOL = 2 mA Cross-over voltage VCRS 1.3 2.0 V ns Figure 2.77, Figure 2.78, Figure 2.79 Rise time FS tr LS Fall time FS Rise/fall time ratio FS tf LS tr/tf LS VBUS characteristics Pull-up, pull-down Battery Charging Specification Ver 1.2 4 20 75 300 4 20 75 300 90 111.11 80 125 % Output resistance ZDRV 28 44 Ω (Adjusting the resistance of external elements is not required.) VBUS input voltage VIH VCC × 0.8 - V - VIL - VCC × 0.2 V - Pull-down resistor RPD 14.25 24.80 kΩ - Pull-up resistor RPUI 0.9 1.575 kΩ During idle state RPUA 1.425 3.09 kΩ During reception D+ sink current IDP_SINK 25 175 μA - D– sink current IDM_SINK 25 175 μA - DCD source current IDP_SRC 7 13 μA - Data detection voltage VDAT_REF 0.25 0.4 V - D+ source voltage VDP_SRC 0.5 0.7 V Output current = 250 μA D– source voltage VDM_SRC 0.5 0.7 V Output current = 250 μA USB_DP, USB_DM VCRS 90% 90% 10% 10% tr Figure 2.77 ns tf USB_DP and USB_DM output timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 103 of 145 S3A1 Datasheet 2. Electrical Characteristics Observation point DP 50 pF DM 50 pF Figure 2.78 Test circuit for Full-Speed (FS) connection Observation point DP 200 pF to 600 pF 3.6 V 1.5 K DM 200 pF to 600 pF Observation point Figure 2.79 2.4.2 Table 2.47 Test circuit for Low-Speed (LS) connection USB External Supply USB regulator Parameter VCC_USB supply current Min Typ Max Unit Test conditions VCC_USB_LDO ≥ 3.8V - - 50 mA - VCC_USB_LDO ≥ 4.5V - - 100 mA - 3.0 - 3.6 V - VCC_USB supply voltage R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 104 of 145 S3A1 Datasheet 2.5 2. Electrical Characteristics ADC14 Characteristics VREFH0 VREFH0 5.5 5.5 A/D Conversion Characteristics (1) 5.0 5.0 A/D Conversion Characteristics (2) 4.0 3.0 2.7 2.4 A/D Conversion Characteristics (4) 4.0 3.0 2.7 2.4 A/D Conversion Characteristics (3) 2.0 A/D Conversion Characteristics (5) A/D Conversion Characteristics (6) 2.0 1.8 1.6 1.0 A/D Conversion Characteristics (7) 1.0 2.4 2.7 1.0 2.0 3.0 5.5 4.0 AVCC0 1.8 5.0 1.0 ADCSR.ADHSC = 0 Figure 2.80 2.4 2.7 1.6 2.0 3.0 5.5 4.0 AVCC0 5.0 ADCSR.ADHSC = 1 AVCC0 to VREFH0 voltage range Table 2.48 A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 64 MHz - - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 2.5 (reference data) kΩ High-precision channel - - 6.7 (reference data) kΩ Normal-precision channel 0 - VREFH0 V - - - 12 Bit - 0.70 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.13 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Analog input capacitance*2 Analog input resistance Analog input voltage range Cs Rs Ain 12-bit mode Resolution Conversion time*1 (Operation at PCLKC = 64 MHz) Permissible signal source impedance Max. = 0.3 kΩ Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - - - 14 Bit - 14-bit mode Resolution R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 105 of 145 S3A1 Datasheet Table 2.48 2. Electrical Characteristics A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter time*1 Conversion (Operation at PCLKC = 64 MHz) Permissible signal source impedance Max. = 0.3 kΩ Offset error Full-scale error Min Typ Max Unit Test conditions 0.80 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.22 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - ±2.0 - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.49 A/D conversion characteristics (2) in high-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 48 MHz - capacitance*2 - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 2.5 (reference data) kΩ High-precision channel - - 6.7 (reference data) kΩ Normal-precision channel 0 - VREFH0 V - - - 12 Bit - 0.94 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.50 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Analog input Analog input resistance Analog input voltage range Cs Rs Ain 12-bit mode Resolution Conversion time*1 (Operation at PCLKC = 48 MHz) Permissible signal source impedance Max. = 0.3 kΩ Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 106 of 145 S3A1 Datasheet Table 2.49 2. Electrical Characteristics A/D conversion characteristics (2) in high-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions - - 14 Bit - 1.06 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.63 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - ±2.0 14-bit mode Resolution time*1 Conversion (Operation at PCLKC = 48 MHz) Permissible signal source impedance Max. = 0.3 kΩ Offset error Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.50 A/D conversion characteristics (3) in high-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 32 MHz - Analog input capacitance*2 Analog input resistance Analog input voltage range Cs Rs Ain - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 2.5 (reference data) kΩ High-precision channel - - 6.7 (reference data) kΩ Normal-precision channel 0 - VREFH0 V - - - 12 Bit - 1.41 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.25 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above ±4.5 LSB High-precision channel ±6.0 LSB Other than above 12-bit mode Resolution Conversion time*1 (Operation at PCLKC = 32 MHz) Permissible signal source impedance Max. = 1.3 kΩ Offset error Full-scale error - ±0.75 Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 107 of 145 S3A1 Datasheet Table 2.50 2. Electrical Characteristics A/D conversion characteristics (3) in high-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - - - 14 Bit - 1.59 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.44 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - ±2.0 14-bit mode Resolution time*1 Conversion (Operation at PCLKC = 32 MHz) Permissible signal source impedance Max. = 1.3 kΩ Offset error Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.51 A/D conversion characteristics (4) in low power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 24 MHz - Analog input capacitance*2 Analog input resistance Analog input voltage range Cs Rs Ain - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 2.5 (reference data) kΩ High-precision channel - - 6.7 (reference data) kΩ Normal-precision channel 0 - VREFH0 V - - - 12 Bit - 2.25 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.38 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - ±0.5 12-bit mode Resolution Conversion time*1 (Operation at PCLKC = 24 MHz) Permissible signal source impedance Max. = 1.1 kΩ Offset error Full-scale error Quantization error R01DS0324EU0100 Rev.1.00 Oct 30, 2017 - ±0.75 ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above ±4.5 LSB High-precision channel ±6.0 LSB Other than above - LSB - Page 108 of 145 S3A1 Datasheet Table 2.51 2. Electrical Characteristics A/D conversion characteristics (4) in low power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - - - 14 Bit - 2.50 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.63 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - ±2.0 14-bit mode Resolution time*1 Conversion (Operation at PCLKC = 24 MHz) Permissible signal source impedance Max. = 1.1 kΩ Offset error ±18 LSB High-precision channel ±24.0 LSB Other than above ±18 LSB High-precision channel Full-scale error - ±3.0 ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.52 A/D conversion characteristics (5) in low power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 16 MHz - Analog input capacitance*2 Analog input resistance Analog input voltage range Cs Rs Ain - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 2.5 (reference data) kΩ High-precision channel - - 6.7 (reference data) kΩ Normal-precision channel 0 - VREFH0 V - - - 12 Bit - 3.38 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.06 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - ±0.5 12-bit mode Resolution time*1 Conversion (Operation at PCLKC = 16 MHz) Permissible signal source impedance Max. = 2.2 kΩ Offset error R01DS0324EU0100 Rev.1.00 Oct 30, 2017 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Page 109 of 145 S3A1 Datasheet Table 2.52 2. Electrical Characteristics A/D conversion characteristics (5) in low power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Full-scale error - ±0.75 Max Unit Test conditions ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKC = 16 MHz) Permissible signal source impedance Max. = 2.2 kΩ Offset error Full-scale error - - 14 Bit - 3.75 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.44 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - ±2.0 - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.53 A/D conversion characteristics (6) in low power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Frequency Analog input capacitance*2 Analog input resistance Analog input voltage range Cs Rs Ain Min Typ Max Unit Test conditions 1 - 8 MHz - - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 3.8 (reference data) kΩ High-precision channel - - 8.2 (reference data) kΩ Normal-precision channel 0 - VREFH0 V - - - 12 Bit - 12-bit mode Resolution R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 110 of 145 S3A1 Datasheet Table 2.53 2. Electrical Characteristics A/D conversion characteristics (6) in low power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions 6.75 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.13 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±1.0 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Full-scale error - ±1.5 ±7.5 LSB High-precision channel ±10.0 LSB Other than above time*1 Conversion (Operation at PCLKC = 8 MHz) Permissible signal source impedance Max. = 5 kΩ Quantization error - ±0.5 - LSB - Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel ±12.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - - - 14 Bit - 7.50 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.88 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - ±4.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above 14-bit mode Resolution Conversion time*1 (Operation at PCLKC = 8 MHz) Permissible signal source impedance Max. = 5 kΩ Offset error Full-scale error - ±6.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel ±48.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 111 of 145 S3A1 Datasheet Table 2.54 2. Electrical Characteristics A/D conversion characteristics (7) in low power A/D conversion mode Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Frequency Typ Max Unit Test conditions 1 - 4 MHz - Analog input capacitance*2 Cs - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel Analog input resistance Rs - - 13.1 (reference data) kΩ High-precision channel - - 14.3 (reference data) kΩ Normal-precision channel Analog input voltage range Ain 0 - VREFH0 V - - - 12 Bit - 13.5 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 20.25 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±1.0 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Full-scale error - ±1.5 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel ±12.0 LSB Other than above 12-bit mode Resolution time*1 Conversion (Operation at PCLKC = 4 MHz) Permissible signal source impedance Max. = 9.9 kΩ DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - - - 14 Bit - 15.0 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 21.75 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - ±4.0 14-bit mode Resolution time*1 Conversion (Operation at PCLKC = 4 MHz) Permissible signal source impedance Max. = 9.9 kΩ Offset error Full-scale error - ±6.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above ±30.0 LSB High-precision channel ±40.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel ±48.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 112 of 145 S3A1 Datasheet 2. Electrical Characteristics MCU Analog input ANn Sensor Rs Cin ADC Cs Analog input ANn Rs Cin Figure 2.81 Table 2.55 Equivalent circuit for analog input 14-bit A/D converter channel classification Classification Channel Conditions Remarks High-precision channel AN000 to AN015 AVCC0 = 1.6 to 5.5 V Normal-precision channel AN016 to AN027 Pins AN000 to AN015 cannot be used as general I/O, IRQ2, IRQ3 inputs, and TS transmission, when the A/D converter is in use Internal reference voltage input channel Internal reference voltage AVCC0 = 2.0 to 5.5 V - Temperature sensor input channel Temperature sensor output AVCC0 = 2.0 to 5.5 V - Table 2.56 A/D internal reference voltage characteristics Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1 Parameter Min Typ Max Unit Test conditions Internal reference voltage input channel*2 1.36 1.43 1.50 V - Sampling time 5.0 - - µs - Note 1. Note 2. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V. The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 14-bit A/D converter. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 113 of 145 S3A1 Datasheet 2. Electrical Characteristics 3FFFh Full-scale error Integral nonlinearity error (INL) A/D converter output code Ideal line of actual A/D conversion characteristic Actual A/D conversion characteristic Ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Absolute accuracy 0000h Offset error 0 Figure 2.82 Analog input voltage VREFH0 (full-scale) Illustration of 14-bit A/D converter characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actually output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 114 of 145 S3A1 Datasheet 2.6 2. Electrical Characteristics DAC12 Characteristics Table 2.57 D/A conversion characteristics (1) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = VREFH or VREFL selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Resistive load 30 - - kΩ - Capacitive load - - 50 pF - Output voltage range 0.35 - AVCC0 – 0.47 V - DNL differential nonlinearity error - ±0.5 ±1.0 LSB - INL integral nonlinearity error - ±2.0 ±8.0 LSB - Offset error - - ±20 mV - Full-scale error - - ±20 mV - Output impedance - 5 - Ω - Conversion time - - 30 μs - Table 2.58 D/A conversion characteristics (2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = AVCC0 or AVSS0 selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Resistive load 30 - - kΩ - Capacitive load - - 50 pF - Output voltage range 0.35 - AVCC0 – 0.47 V - DNL differential nonlinearity error - ±0.5 ±2.0 LSB - INL integral nonlinearity error - ±2.0 ±8.0 LSB - Offset error - - ±30 mV - Full-scale error - - ±30 mV - Output impedance - 5 - Ω - Conversion time - - 30 μs - Table 2.59 D/A conversion characteristics (3) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = internal reference voltage selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Internal reference voltage (Vbgr) 1.36 1.43 1.50 V - Resistive load 30 - - kΩ - Capacitive load - - 50 pF - Output voltage range 0.35 - Vbgr V - DNL differential nonlinearity error - ±2.0 ±16.0 LSB - INL integral nonlinearity error - ±8.0 ±16.0 LSB - Offset error - - ±30 mV - Output impedance - 5 - Ω - Conversion time - - 30 μs - R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 115 of 145 S3A1 Datasheet 2. Electrical Characteristics Gain error Full-scale error Upper output limit Integral nonlinearity error (INL) Offset error Output analog voltage 1-LSB width for ideal D/A conversion characteristic Ideal output voltage Differential nonlinearity error (DNL) *1 Lower output limit Actual D/A conversion characteristic Offset error Ideal output voltage 000h Note 1. Figure 2.83 D/A converter input code FFFh Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed. Illustration of D/A converter characteristic terms Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion characteristics and the width of the actual output voltage. Offset error Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal output voltage based on the input code. Full-scale error Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the ideal output voltage based on the input code. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 116 of 145 S3A1 Datasheet 2.7 2. Electrical Characteristics TSN Characteristics Table 2.60 TSN characteristics Conditions: VCC = AVCC0 = 2.0 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Relative accuracy - - ±1.5 - °C 2.4 V or above - - ±2.0 - °C Below 2.4 V Temperature slope - - –3.65 - mV/°C - Output voltage (at 25°C) - - 1.05 - V VCC = 3.3 V Temperature sensor start time tSTART - - 5 μs - Sampling time - 5 - - μs - 2.8 OSC Stop Detect Characteristics Table 2.61 Oscillation stop detection circuit characteristics Parameter Symbol Min Typ Max Unit Test conditions Detection time tdr - - 1 ms Figure 2.84 Main clock Main clock tdr tdr OSTDSR.OSTDF OSTDSR.OSTDF MOCO clock PLL clock ICLK MOCO clock ICLK When the main clock is selected When the PLL clock is selected Figure 2.84 Oscillation stop detection timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 117 of 145 S3A1 Datasheet 2.9 2. Electrical Characteristics POR and LVD Characteristics Table 2.62 Power-on reset circuit and voltage detection circuit characteristics (1) Parameter Voltage detection level*1 Symbol Min Typ Max Unit Test conditions Power-on reset (POR) VPOR 1.27 1.42 1.57 V Figure 2.85, Figure 2.86 Voltage detection circuit (LVD0)*2 Vdet0_0 3.68 3.85 4.00 V Vdet0_1 2.68 2.85 2.96 Figure 2.87 At falling edge VCC Vdet0_2 2.38 2.53 2.64 Vdet0_3 1.78 1.90 2.02 V Figure 2.88 At falling edge VCC V Figure 2.89 At falling edge VCC Voltage detection circuit (LVD1)*3 Voltage detection circuit Note 1. Note 2. Note 3. Note 4. (LVD2)*4 Vdet0_4 1.60 1.69 1.82 Vdet1_0 4.13 4.29 4.45 Vdet1_1 3.98 4.16 4.30 Vdet1_2 3.86 4.03 4.18 Vdet1_3 3.68 3.86 4.00 Vdet1_4 2.98 3.10 3.22 Vdet1_5 2.89 3.00 3.11 Vdet1_6 2.79 2.90 3.01 Vdet1_7 2.68 2.79 2.90 Vdet1_8 2.58 2.68 2.78 Vdet1_9 2.48 2.58 2.68 Vdet1_A 2.38 2.48 2.58 Vdet1_B 2.10 2.20 2.30 Vdet1_C 1.84 1.96 2.05 Vdet1_D 1.74 1.86 1.95 Vdet1_E 1.63 1.75 1.84 Vdet1_F 1.60 1.65 1.73 Vdet2_0 4.11 4.31 4.48 Vdet2_1 3.97 4.17 4.34 Vdet2_2 3.83 4.03 4.20 Vdet2_3 3.64 3.84 4.01 These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage detection. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 118 of 145 S3A1 Datasheet Table 2.63 2. Electrical Characteristics Power-on reset circuit and voltage detection circuit characteristics (2) Parameter Symbol Min Typ Max Unit Test conditions Wait time after power-on reset cancellation LVD0: enable tPOR - 1.7 - ms - LVD0: disable tPOR - 1.3 - ms - Wait time after voltage monitor 0, 1, 2 reset cancellation LVD0: enable*1 tLVD0,1,2 - 0.6 - ms - LVD0: disable*2 tLVD1,2 - 0.2 - ms - Response delay*3 tdet - - 350 μs Figure 2.85, Figure 2.86 Minimum VCC down time tVOFF 450 - - μs Figure 2.85, VCC = 1.0 V or above Power-on reset enable time tW(POR) 1 - - ms Figure 2.86, VCC = below 1.0 V LVD operation stabilization time (after LVD is enabled) td(E-A) - - 300 μs Figure 2.88, Figure 2.89 Hysteresis width (POR) VPORH - 110 - mV - Hysteresis width (LVD0, LVD1, and LVD2) VLVH - 60 - mV - 100 - Vdet1_0 to Vdet1_2 selected - 60 - Vdet1_3 to Vdet1_9 selected - 50 - Vdet1_A or Vdet1_B selected - 40 - Vdet1_C or Vdet1_F selected - 60 - LVD2 selected Note 1. Note 2. Note 3. LVD0 selected When OFS1.LVDAS = 0. When OFS1.LVDAS = 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0, Vdet1, and Vdet2 for the POR/LVD. tVOFF VCC VPOR 1.0 V Internal reset signal (active-low) tdet Figure 2.85 tdet tPOR Voltage detection reset timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 119 of 145 S3A1 Datasheet 2. Electrical Characteristics VPOR VCC 1.0 V tw(POR) Internal reset signal (active-low) *1 tdet Note: Figure 2.86 tPOR tW(POR) is the time required for a power-on reset to be enabled while the external power VCC is being held below the valid voltage (1.0 V). When VCC turns on, maintain tW(POR) for 1.0 ms or more. Power-on reset timing tVOFF VCC VLVH Vdet0 Internal reset signal (active-low) tdet Figure 2.87 tdet tLVD0 Voltage detection circuit timing (Vdet0) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 120 of 145 S3A1 Datasheet 2. Electrical Characteristics tVOFF VCC VLVH Vdet1 LVCMPCR.LVD1E td(E-A) LVD1 Comparator output LVD1CR0.CMPE LVD1SR.MON Internal reset signal (active-low) When LVD1CR0.RN = 0 tdet tdet tLVD1 When LVD1CR0.RN = 1 tLVD1 Figure 2.88 Voltage detection circuit timing (Vdet1) tVOFF VCC VLVH Vdet2 LVCMPCR.LVD2E td(E-A) LVD2 Comparator output LVD2CR0.CMPE LVD2SR.MON Internal reset signal (active-low) When LVD2CR0.RN = 0 tdet tdet tLVD2 When LVD2CR0.RN = 1 tLVD2 Figure 2.89 Voltage detection circuit timing (Vdet2) R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 121 of 145 S3A1 Datasheet 2.10 2. Electrical Characteristics VBATT Characteristics Table 2.64 Battery backup function characteristics Conditions: VCC = AVCC0 = 1.6 V to 5.5 V, VBATT = 1.6 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Voltage level for switching to battery backup (falling) VDETBATT 1.99 2.09 2.19 V Hysteresis width for switching to battery back up VVBATTH - 100 - mV Figure 2.90, Figure 2.91 VCC-off period for starting power supply switching tVOFFBATT 300 - - μs - Voltage detection level VBATT_Power-on reset (VBATT_POR) VVBATPOR 1.30 1.40 1.50 V Figure 2.90, Figure 2.91 Wait time after VBATT_POR reset time cancellation tVBATPOR - - 3 mS - Level for detection of voltage drop on the VBATT pin (falling) VDETBATLVD 2.11 2.2 2.29 V Figure 2.92 1.92 2 2.08 V VBTLVDLVL[1:0] = 10b VBTLVDLVL[1:0] = 11b Hysteresis width for VBATT pin LVD VVBATLVDTH - 50 - mV VBATT pin LVD operation stabilization time td_vbat - - 300 μs Figure 2.92 VBATT pin LVD response delay time tdet_vbat - - 350 μs Allowable voltage change rising/falling gradient dt/dVCC 1.0 - - ms/V - VCC voltage level for access to the VBATT backup registers V_BKBATT 1.8 - - V - Note: The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage level for switching to battery backup (VDETBATT). VLVH Vdet0 VCC VVBATH VDETBATT VPOR VBATT VVBATPOR Internal reset signal (active-low) VCC supplied Figure 2.90 tdet tLVD0 tdet Backup power area VBATT supplied VCC supplied Power supply switching and LVD0 reset timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 122 of 145 S3A1 Datasheet 2. Electrical Characteristics VCC VVBATH VDETBATT VBATT VVBATPOR VBATT_POR (active-low) tVBATPOR Backup power area VCC supplied Figure 2.91 VBATT supplied Not supplied VCC supplied VBATT_POR reset timing VBATT VVBATLVDTH VDETBATLVD VBTCR2.VBTLVDEN td_vbat VBATT pin LVD Comparator output VBTCMPCR.VBTCMPE VBTSR.VBTBLDF tdet_vbat Figure 2.92 tdet_vbat VBATT pin voltage detection circuit timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 123 of 145 S3A1 Datasheet Table 2.65 2. Electrical Characteristics VBATT-I/O characteristics Parameter VBATWIOn I/O output characteristics (n = 0 to 2) VCC > VDETBATT VCC = 4.0 to 5.5 V VCC = 2.7 to 4.0 V Symbol Min Typ Max Unit Test conditions VOH VCC - 0.8 - - V IOH = -200 µA VOL - - 0.8 IOL = 200 µA VOH VCC - 0.5 - - IOH = -100 µA VOL - - 0.5 IOL = 100 µA VCC = VDETBATT to 2.7 V VOH VCC < VDETBATT VBATT = 2.7 to 3.6 V VBATT = 1.6 to 2.7 V 2.11 VCC - 0.3 - - IOH = -50 µA VOL - - 0.3 IOL = 50 µA VOH VBATT - 0.5 - - IOH = -100 µA VOL - - 0.5 IOL = 100 µA VOH VBATT - 0.3 - - IOH = -50 µA VOL - - 0.3 IOL = 50 µA CTSU Characteristics Table 2.66 CTSU characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions External capacitance connected to TSCAP pin Ctscap 9 10 11 nF - TS pin capacitive load Cbase - - 50 pF - Permissible output high current ΣIoH - - -24 mA When the mutual capacitance method is applied 2.12 Segment LCD Controller Characteristics 2.12.1 Resistance Division Method [Static Display Mode] Table 2.67 Resistance division method LCD characteristics (1) Conditions: VL4 ≤ VCC ≤ 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage VL4 2.0 - VCC V - [1/2 Bias Method, 1/4 Bias Method] Table 2.68 Resistance division method LCD characteristics (2) Conditions: VL4 ≤ VCC ≤ 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage VL4 2.7 - VCC V - [1/3 Bias Method] Table 2.69 Resistance division method LCD characteristics (3) Conditions: VL4 ≤ VCC ≤ 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage VL4 2.5 - VCC V - R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 124 of 145 S3A1 Datasheet 2.12.2 2. Electrical Characteristics Internal Voltage Boosting Method [1/3 Bias Method] Table 2.70 Internal voltage boosting method LCD characteristics Conditions: VCC = 1.8 V to 5.5 V Parameter Symbol Conditions LCD output voltage variation range VL1 C1 to C4*1 = 0.47 μF Min Typ Max Unit Test conditions VLCD = 04h 0.90 1.0 1.08 V - VLCD = 05h 0.95 1.05 1.13 V - VLCD = 06h 1.00 1.10 1.18 V - VLCD = 07h 1.05 1.15 1.23 V - VLCD = 08h 1.10 1.20 1.28 V - VLCD = 09h 1.15 1.25 1.33 V - VLCD = 0Ah 1.20 1.30 1.38 V - VLCD = 0Bh 1.25 1.35 1.43 V - VLCD = 0Ch 1.30 1.40 1.48 V - VLCD = 0Dh 1.35 1.45 1.53 V - VLCD = 0Eh 1.40 1.50 1.58 V - VLCD = 0Fh 1.45 1.55 1.63 V - VLCD = 10h 1.50 1.60 1.68 V - VLCD = 11h 1.55 1.65 1.73 V - VLCD = 12h 1.60 1.70 1.78 V - VLCD = 13h 1.65 1.75 1.83 V - Doubler output voltage VL2 C1 to C4*1 = 0.47 μF 2 × VL1 - 0.1 2 × VL1 2 × VL1 V - Tripler output voltage VL4 C1 to C4*1 = 0.47 μF 3 × VL1 - 0.15 3 × VL1 3 × VL1 V - Reference voltage setup time*2 tVL1S 5 - - ms Figure 2.93 LCD output voltage variation range*3 tVLWT 500 - - ms Note 1. Note 2. Note 3. C1 to C4*1 = 0.47 μF This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 μF ± 30% This is the time required to wait from when the reference voltage is specified using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET[1:0] bits in the LCDM0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 125 of 145 S3A1 Datasheet 2. Electrical Characteristics [1/4 Bias Method] Table 2.71 Internal voltage boosting method LCD characteristics Conditions: VCC = 1.8 V to 5.5 V Parameter Symbol Conditions LCD output voltage variation range VL1 Doubler output voltage VL2 C1 to C5*1 = 0.47 μF Min Typ Max Unit Test conditions VLCD = 04h 0.90 1.0 1.08 V - VLCD = 05h 0.95 1.05 1.13 V - VLCD = 06h 1.00 1.10 1.18 V - VLCD = 07h 1.05 1.15 1.23 V - VLCD = 08h 1.10 1.20 1.28 V - VLCD = 09h 1.15 1.25 1.33 V - VLCD = 0Ah 1.20 1.30 1.38 V - VLCD = 0Bh 1.25 1.35 1.43 V - VLCD = 0Ch 1.30 1.40 1.48 V - C1 to C5*1 = 0.47 μF 2VL1 - 0.08 2VL1 2VL1 V - C5*1 Tripler output voltage VL3 C1 to = 0.47 μF 3VL1 - 0.12 3VL1 3VL1 V - Quadruply output voltage VL4*4 C1 to C5*1 = 0.47 μF 4VL1 - 0.16 4VL1 4VL1 V - Reference voltage setup time*2 tVL1S 5 - - ms Figure 2.93 LCD output voltage variation range*3 tVLWT 500 - - ms Note 1. Note 2. Note 3. Note 4. C1 to C5*1 = 0.47 μF This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 μF ± 30% This is the time required to wait from when the reference voltage is specified by using the VLCD register or when the internal voltage boosting method is selected (by setting the MDSET[1] and MDSET[0] bits in the LCDM0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). VL4 must be 5.5 V or lower. 2.12.3 Capacitor Split Method [1/3 Bias Method] Table 2.72 Internal voltage boosting method LCD characteristics Conditions: VCC = 2.2 V to 5.5 V Min Typ Max Unit Test conditions C1 to C4 = 0.47 μF*2 - VCC - V - VL2 C1 to C4 = 0.47 μF*2 2/3 × VL4 - 0.07 2/3 × VL4 2/3 × VL4 + 0.07 V - VL1 μF*2 1/3 × VL4 - 0.08 1/3 × VL4 1/3 × VL4 + 0.08 V - 100 - - ms Figure 2.93 Parameter Symbol Conditions VL4 voltage*1 VL4 VL2 voltage*1 VL1 voltage*1 Capacitor split wait time*1 Note 1. Note 2. tWAIT C1 to C4 = 0.47 This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 μF ± 30%. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 126 of 145 S3A1 Datasheet 2. Electrical Characteristics MDSET0, MDSET1 00b 01b or 10b tVL1S VLCON tVLWT, tWAIT LCDON Figure 2.93 2.13 LCD reference voltage setup time, voltage boosting wait time, and capacitor split wait time Comparator Characteristics Table 2.73 ACMPLP characteristics Conditions: VCC = 1.8 to 5.5 V Parameter Reference voltage range Standard mode Window mode IVREFn (n = 0,1) Max Unit Test conditions - VCC - 1.4 V - VREFH 1.4 - VCC V - VREFL 0 - VCC - 1.4 V - VI 0 - VCC V - - 1.36 1.44 1.50 V - Td - - 1.2 μs Low-speed mode - - 5 μs VCC = 3.0 Slew rate of input signal > 50 mV/μs Window mode - - 2 μs High-speed mode High-speed mode - - - 50 mV - Low-speed mode - - - 40 mV - Window mode - - - 60 mV - Tcmp 100 - - μs - Operation stabilization wait time Note: Note: Typ 0 IVREF1 Internal reference voltage Offset voltage Min VREF IVREF0 Input voltage range Output delay Symbol When 8-bit DAC output is used as the reference voltage, the offset voltage increases up to 2.5 × VCC/256. In window mode, be sure to satisfy the following condition: IVREF1 - IVREF0 > 0.2 V. 2.14 OPAMP Characteristics Table 2.74 OPAMP characteristics (1 of 2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V) Parameter Symbol Conditions Min Typ Max Unit Common mode input range Vicm1 Low-power mode 0.2 - AVCC0 – 0.5 V Vicm2 High-speed mode 0.3 - AVCC0 – 0.6 V Output voltage range Vo1 Low-power mode 0.1 - AVCC0 – 0.1 V Vo2 High-speed mode 0.1 - AVCC0 – 0.1 V Vioff 3σ –10 - 10 mV Input offset voltage Open gain Av 60 120 - dB Gain-bandwidth (GB) product GBW1 Low-power mode - 0.04 - MHz GBW2 High-speed mode - 1.7 - MHz Phase margin PM CL = 20 pF 50 - - deg Gain margin GM CL = 20 pF 10 - - dB R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 127 of 145 S3A1 Datasheet Table 2.74 2. Electrical Characteristics OPAMP characteristics (2 of 2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V) Parameter Symbol Conditions Equivalent input noise Vnoise1 f = 1 kHz Vnoise2 f = 10 kHz Vnoise3 f = 1 kHz Vnoise4 f = 2 kHz Low power mode High-speed mode Min Typ Max Unit - 230 - nV/√Hz - 200 - nV/√Hz - 90 - nV/√Hz - 70 - nV/√Hz Power supply reduction ratio PSRR - 90 - dB Common mode signal reduction ratio CMRR - 90 - dB Stabilization wait time Tstd1 CL = 20 pF Only operational amplifier is activated *1 Low power mode 650 - - μs High-speed mode 13 - - μs CL = 20 pF Operational amplifier and reference current circuit are activated simultaneously Low power mode 650 - - μs Tstd4 High-speed mode 13 - - μs Tset1 CL = 20 pF Low power mode - - 750 μs High-speed mode - - 13 μs Low power mode - 0.02 - V/μs High-speed mode - 1.1 - V/μs Tstd2 Tstd3 Settling time Tset2 Slew rate Tslew1 CL = 20 pF Tslew2 Load current Load capacitance Note 1. 2.15 Iload1 Low power mode –100 - 100 μA Iload2 High-speed mode –100 - 100 μA - - 20 pF CL When the operational amplifier reference current circuit is activated in advance. Flash Memory Characteristics 2.15.1 Code Flash Memory Characteristics Table 2.75 Code flash characteristics (1) Parameter Symbol Min Typ Max Unit Test conditions Reprogramming/erasure cycle*1 NPEC 1000 - - Times - Data hold time tDRP 20*2, *3 - - Year Ta = +85°C Note 1. Note 2. Note 3. After 1000 times of NPEC The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1000), erasing can be done n times for each block. For instance, when 8-byte programming is performed 256 times for different addresses in 2-KB blocks, and the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled (overwriting is prohibited). Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics. This result is obtained from reliability testing. Table 2.76 Code flash characteristics (2) (1 of 2) High-speed operating mode Conditions: VCC = 2.7 to 5.5 V FCLK = 1 MHz Parameter FCLK = 32 MHz Symbol Min Typ Max Min Typ Max Unit Programming time 8-byte tP8 - 116 998 - 54 506 μs Erasure time 2-KB tE2K - 9.03 287 - 5.67 222 ms Blank check time 8-byte tBC8 - - 56.8 - - 16.6 μs 2-KB tBC2K - - 1899 - - 140 μs tSED - - 22.5 - - 10.7 μs Startup area switching setting time tSAS - 21.7 585 - 12.1 447 ms Access window time tAWS - 21.7 585 - 12.1 447 ms Erase suspended time R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 128 of 145 S3A1 Datasheet Table 2.76 2. Electrical Characteristics Code flash characteristics (2) (2 of 2) High-speed operating mode Conditions: VCC = 2.7 to 5.5 V FCLK = 1 MHz Parameter Symbol Min FCLK = 32 MHz Typ Max Min Typ Max Unit OCD/serial programmer ID setting time tOSIS - 21.7 585 - 12.1 447 ms Flash memory mode transition wait time 1 tDIS 2 - - 2 - - μs Flash memory mode transition wait time 2 tMS 5 - - 5 - - μs Note: Note: Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency value, such as 1.5 MHz, cannot be set. The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. Table 2.77 Code flash characteristics (3) Middle-speed operating mode Conditions: VCC = 1.8 to 5.5 V, Ta = –40 to +85°C FCLK = 1 MHz Parameter Programming time 8-byte FCLK = 8 MHz Symbol Min Typ Max Min Typ Max Unit tP8 - 157 1411 - 101 966 μs Erasure time 2-KB tE2K - 9.10 289 - 6.10 228 ms Blank check time 8-byte tBC8 - - 87.7 - - 52.5 μs 2-KB tBC2K - - 1930 - - 414 μs Erase suspended time tSED - - 32.7 - - 21.6 μs Startup area switching setting time tSAS - 22.5 592 - 14.0 464 ms Access window time tAWS - 22.5 592 - 14.0 464 ms OCD/serial programmer ID setting time tOSIS - 22.5 592 - 14.0 464 ms Flash memory mode transition wait time 1 tDIS 2 - - 2 - - μs Flash memory mode transition wait time 2 tMS 720 - - 720 - - ns Note: Note: Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. 2.15.2 Data Flash Memory Characteristics Table 2.78 Data flash characteristics (1) Parameter Reprogramming/erasure Data hold time cycle*1 After 10000 times of NDPEC After 100000 times of NDPEC After 1000000 times of NDPEC Note 1. Note 2. Note 3. Symbol Min Typ Max Unit Test conditions NDPEC 100000 1000000 tDDRP 20*2, *3 - - Times - - Year Ta = +85°C 5*2, *3 - - Year - 1*2, *3 - Year Ta = +25°C The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100000), erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1000 times for different addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited). Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics. These results are obtained from reliability testing. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 129 of 145 S3A1 Datasheet Table 2.79 2. Electrical Characteristics Data flash characteristics (2) High-speed operating mode Conditions: VCC = 2.7 to 5.5 V FCLK = 4 MHz Parameter FCLK = 32 MHz Symbol Min Typ Max Min Typ Max Unit Programming time 1-byte tDP1 - 52.4 463 - 42.1 387 μs Erasure time 1-KB tDE1K - 8.98 286 - 6.42 237 ms Blank check time 1-byte tDBC1 - - 24.3 - - 16.6 μs tDBC1K - - 1872 - - 512 μs Suspended time during erasing tDSED - - 13.0 - - 10.7 μs Data flash STOP recovery time tDSTOP 5 - - 5 - - μs 1-KB Note: Note: Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. Table 2.80 Data flash characteristics (3) Middle-speed operating mode Conditions: VCC = 1.8 to 5.5 V, Ta = –40 to +85°C FCLK = 4 MHz Parameter Programming time 1-byte FCLK = 8 MHz Symbol Min Typ Max Min Typ Max Unit tDP1 - 94.7 886 - 89.3 849 μs Erasure time 1-KB tDE1K - 9.59 299 - 8.29 273 ms Blank check time 1-byte tDBC1 - - 56.2 - - 52.5 μs 1-KB tDBC1K - - 2.17 - - 1.51 ms Suspended time during erasing tDSED - - 23.0 - - 21.7 μs Data flash STOP recovery time tDSTOP 720 - - 720 - - ns Note: Note: Note: 2.16 Does not include the time until each operation of the flash memory is started after instructions are executed by software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. Boundary Scan Table 2.81 Boundary scan Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 100 - - ns Figure 2.94 TCK clock high pulse width tTCKH 45 - - ns TCK clock low pulse width tTCKL 45 - - ns TCK clock rise time tTCKr - - 5 ns TCK clock fall time tTCKf - - 5 ns TMS setup time tTMSS 20 - - ns TMS hold time tTMSH 20 - - ns TDI setup time tTDIS 20 - - ns TDI hold time tTDIH 20 - - ns TDO data delay tTDOD - - 70 ns Boundary Scan circuit start up time*1 tBSSTUP tRESWP - - - Note 1. Figure 2.95 Figure 2.96 Boundary scan does not function until power-on-reset becomes negative. R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 130 of 145 S3A1 Datasheet 2. Electrical Characteristics tTCKcyc tTCKH tTCKf TCK tTCKL Figure 2.94 tTCKr Boundary scan TCK timing TCK tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD TDO Figure 2.95 Boundary scan input/output timing VCC RES tBSSTUP (= tRESWP) Figure 2.96 2.17 Boundary scan execute Boundary scan circuit start up timing Joint European Test Action Group (JTAG) Table 2.82 JTAG (debug) characteristics (1) (1 of 2) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 80 - - ns Figure 2.97 TCK clock high pulse width tTCKH 35 - - ns TCK clock low pulse width tTCKL 35 - - ns TCK clock rise time tTCKr - - 5 ns TCK clock fall time tTCKf - - 5 ns R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 131 of 145 S3A1 Datasheet Table 2.82 2. Electrical Characteristics JTAG (debug) characteristics (1) (2 of 2) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions TMS setup time tTMSS 16 - - ns Figure 2.98 TMS hold time tTMSH 16 - - ns TDI setup time tTDIS 16 - - ns TDI hold time tTDIH 16 - - ns TDO data delay time tTDOD - - 70 ns Table 2.83 JTAG (debug) characteristics (2) Conditions: VCC = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 250 - - ns Figure 2.97 TCK clock high pulse width tTCKH 120 - - ns TCK clock low pulse width tTCKL 120 - - ns TCK clock rise time tTCKr - - 5 ns TCK clock fall time tTCKf - - 5 ns TMS setup time tTMSS 50 - - ns TMS hold time tTMSH 50 - - ns TDI setup time tTDIS 50 - - ns TDI hold time tTDIH 50 - - ns TDO data delay time tTDOD - - 150 ns Figure 2.98 tTCKcyc tTCKH TCK tTCKf tTCKr tTCKL Figure 2.97 JTAG TCK timing TCK tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD TDO Figure 2.98 JTAG input/output timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 132 of 145 S3A1 Datasheet 2.17.1 Table 2.84 2. Electrical Characteristics Serial Wire Debug (SWD) SWD characteristics (1) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 80 - - ns Figure 2.99 SWCLK clock high pulse width tSWCKH 35 - - ns SWCLK clock low pulse width tSWCKL 35 - - ns SWCLK clock rise time tSWCKr - - 5 ns SWCLK clock fall time tSWCKf - - 5 ns SWDIO setup time tSWDS 16 - - ns SWDIO hold time tSWDH 16 - - ns SWDIO data delay time tSWDD 2 - 70 ns Table 2.85 Figure 2.100 SWD characteristics (2) Conditions: VCC = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 250 - - ns Figure 2.99 SWCLK clock high pulse width tSWCKH 120 - - ns SWCLK clock low pulse width tSWCKL 120 - - ns SWCLK clock rise time tSWCKr - - 5 ns SWCLK clock fall time tSWCKf - - 5 ns SWDIO setup time tSWDS 50 - - ns SWDIO hold time tSWDH 50 - - ns SWDIO data delay time tSWDD 2 - 150 ns Figure 2.100 tSWCKcyc tSWCKH SWCLK tSWCKf tSWCKL Figure 2.99 tSWCKr SWD SWCLK timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 133 of 145 S3A1 Datasheet 2. Electrical Characteristics SWCLK tSWDS tSWDH SWDIO (Input) tSWDD SWDIO (Output) tSWDD SWDIO (Output) tSWDD SWDIO (Output) Figure 2.100 SWD input/output timing R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 134 of 145 S3A1 Datasheet Appendix 1. Package Dimensions Appendix 1. Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas Electronics Corporation website. JEITA Package Code P-TFLGA145-7x7-0.50 RENESAS Code PTLG0145KA-A Previous Code 145F0G MASS[Typ.] 0.1g w S B φb1 D φ φb φ w S A ZD A M S AB M S AB e A e N M L K J E H B G F E D C B y S x4 v Index mark (Laser mark) Figure 1.1 S ZE A 1 2 3 4 5 6 7 8 9 10 11 12 13 Reference Dimension Symbol Min D E v w A e b b1 x y ZD ZE in Millimeters Nom 7.0 7.0 Max 0.15 0.20 1.05 0.21 0.29 0.5 0.25 0.34 0.29 0.39 0.08 0.08 0.5 0.5 LGA 145-pin R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 135 of 145 S3A1 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP144-20x20-0.50 PLQP0144KA-B — 1.2 Unit: mm HD *1 D 108 73 *2 E 72 144 37 1 36 NOTE 4 Index area NOTE 3 F S *3 bp 0.25 A1 T c y S A2 A e Lp L1 Detail F Figure 1.2 HE 109 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. Reference Dimensions in millimeters Symbol M Min Nom Max D 19.9 20.0 20.1 20.1 E 19.9 20.0 A2  1.4  HD 21.8 22.0 22.2 HE 21.8 22.0 22.2 A   1.7 A1 0.05  0.15 bp 0.17 0.20 0.27 c 0.09  0.20 T 0q 3.5q 8q e  0.5  x   0.08 y   0.10 Lp 0.45 0.6 0.75 L1  1.0  LQFP 144-pin R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 136 of 145 S3A1 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFBGA121-8x8-0.65 PLBG0121JA-A — 0.15 Unit: mm w S A D A ZD ZE 11 10 9 8 7 6 5 4 3 2 1 B E L K J H G F E D C B A w S B INDEX MARK INDEX MARK A y1 A2 S S Reference Dimensions in millimeters Symbol y e S Ib Figure 1.3 Ix M Min Nom Max D 7.90 8.00 8.10 8.10 A1 S AB E 7.90 8.00 w — 0.20 — A 1.11 1.21 1.31 A1 0.25 0.30 0.35 A2 — 0.91 — e — 0.65 — b 0.35 0.40 0.45 x — 0.08 — y — 0.10 — y1 — 0.20 — ZD — 0.75 — ZE — 0.75 — BGA 121-pin R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 137 of 145 S3A1 Datasheet Appendix 1. Package Dimensions JEITA Package Code P-TFLGA100-7x7-0.65 RENESAS Code PTLG0100JA-A Previous Code 100F0G MASS[Typ.] 0.1g w S B φ b1 D φ× M S φb w S A ZD φ× M S AB e A e A AB K J H G B E F E D C B ×4 y S v Index mark (Laser mark) Figure 1.4 S ZE A 1 2 3 Index mark 4 5 6 7 8 9 10 Reference Symbol Dimension in Millimeters Min Nom D 7.0 E 7.0 v w A e 0.65 b 0.31 0.35 b1 0.385 0.435 x y ZD 0.575 ZE 0.575 Max 0.15 0.20 1.05 0.39 0.485 0.08 0.10 LGA 100-pin R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 138 of 145 S3A1 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP100-14x14-0.50 PLQP0100KB-B — 0.6 HD Unit: mm *1 D 51 75 *2 E 50 100 26 1 25 NOTE 4 Index area NOTE 3 F S y S *3 0.25 T A1 Lp L1 Detail F NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. Reference Dimensions in millimeters Symbol bp M Min Nom Max D 13.9 14.0 14.1 14.1 E 13.9 14.0 A2  1.4  HD 15.8 16.0 16.2 HE 15.8 16.0 16.2 A   1.7 A1 0.05  0.15 bp 0.15 0.20 0.27 c 0.09  0.20 T 0q 3.5q 8q e  0.5  x   0.08 y   0.08 Lp 0.45 0.6 0.75 L1  1.0  c A2 A e Figure 1.5 HE 76 LQFP 100-pin R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 139 of 145 S3A1 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP64-10x10-0.50 PLQP0064KB-C — 0.3 Unit: mm HD *1 D 48 33 64 HE 32 *2 E 49 17 1 16 NOTE 4 Index area NOTE 3 F S y S *3 bp 0.25 c A1 T A2 A e Lp L1 Detail F Figure 1.6 M NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. Reference Dimensions in millimeters Symbol Min Nom Max D 9.9 10.0 10.1 10.1 E 9.9 10.0 A2  1.4  HD 11.8 12.0 12.2 HE 11.8 12.0 12.2 A   1.7 A1 0.05  0.15 bp 0.15 0.20 0.27 c 0.09  0.20 T 0q 3.5q 8q e  0.5  x   0.08 y   0.08 Lp 0.45 0.6 0.75 L1  1.0  LQFP 64-pin R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 140 of 145 S3A1 Datasheet Appendix 1. Package Dimensions JEITA Package code P-HWQFN64-8x8-0.40 RENESAS code Previous code MASS(TYP.)[g] PWQN0064LA-A P64K8-40-9B5-3 0.16 D 33 48 DETAIL OF A PART 32 49 E A A1 17 64 c2 16 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 16 1 64 17 Dimension in Millimeters Min Nom Max D 7.95 8.00 8.05 E 7.95 8.00 8.05 A 0.80 A1 0.00 b 0.17 e Lp B E2 32 49 0.30 33 ZD e b Figure 1.7 x M 0.40 0.50 x 0.05 y 0.05 1.00 ZE c2 48 0.23 0.40 ZD ZE 0.20 1.00 0.15 0.20 D2 6.50 E2 6.50 0.25 S AB QFN 64-pin R01DS0324EU0100 Rev.1.00 Oct 30, 2017 Page 141 of 145 Revision History Rev. Date 1.00 Oct 30, 2017 S3A1 Microcontroller Group Datasheet Summary 1st release Proprietary Notice All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated, transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior written consent from Renesas. Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited. CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium. Magic Packet™ is a trademark of Advanced Micro Devices, Inc. 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