User’s Manual
Cover
S3A1 Microcontroller Group
User’s Manual
Renesas Synergy™ Platform
Synergy Microcontrollers
S3 Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.20
Oct 2018
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorporation or any
other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims
any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits,
software, or information.
2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims
involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas
Electronics products or technical information described in this document, including but not limited to, the product data,
drawings, charts, programs, algorithms, and application examples.
3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property
rights of Renesas Electronics or others.
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(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its
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(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be
used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for
printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a
finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from
the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product
that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the
power reaches the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes
in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during
power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input
pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit
state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows
internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is
generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only
released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an
external resonator or by an external oscillator while program execution is in progress, wait until the target clock
signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take
care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition
period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating
margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number,
implement a system-evaluation test for the given product.
Preface
1.
About this Document
This manual describes the functions and electrical characteristics of the Renesas Synergy™ Microcontroller.
This manual is generally organized into an overview of the product, descriptions of the CPU, system control functions,
peripheral functions, electrical characteristics, and usage notes. This manual describes the product specification of the
microcontroller (MCU) superset. Depending on your product, some pins, registers, or functions might not exist. Address
space that store unavailable registers are reserved.
2.
Audience
This manual is written for system designers who are designing and programming applications using the Renesas Synergy
Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU.
3.
Renesas Publications
Renesas provides the following documents for the Renesas Synergy Microcontroller. Before using any of these
documents, visit renesassynergy.com/docs for the most up-to-date version of the document.
Component
Microcontrollers
Software
Tools & Kits,
Solutions
Document type
Description
Datasheet
Features, overview, and electrical characteristics of the MCU
User’s Manual: Microcontrollers
MCU specifications such as pin assignments, memory maps, peripheral
functions, electrical characteristics, timing diagrams, and operation
descriptions
Application Notes
Technical notes, board design guidelines, and software migration information
Technical Update (TU)
Preliminary reports on product specifications such as restriction and errata
Datasheet
Functional descriptions and specific performance data for software modules
that are included in Renesas Synergy Software Package (SSP)
User’s Manual: Software
API reference including SSP architecture and programming information
Application Notes
Project files, guidelines for software programming, and application examples
to develop embedded software applications
User’s Manual: Development Tools
User’s manual and quick start guide for developing embedded software
applications with Development Kit (DK), Starter Kit (SK), Promotion Kit (PK),
Target Board Kit (TB), Product Examples (PE), and Application Examples (AE)
User’s Manual: Software
Quick Start Guide
Application Notes
Project files, guidelines for software programming, and application examples
to develop embedded software applications
4.
Numbering Notation
The following numbering notation is used throughout this manual:
Example
Description
011b
Binary number. For example, the binary equivalent of the number 3 is 011b.
1Fh
Hexadecimal number. For example, the hexadecimal equivalent of the number 31 is described 1Fh. In
some cases, a hexadecimal number is shown with the prefix 0x, based on C/C++ formatting.
1234
Decimal number. Decimal numbers are generally shown without a suffix.
5.
Typographic Notation
The following typographic notation is used throughout this manual:
Example
Description
ICU.NMICR.NMIMD
Periods separate a function module symbol (ICU), register symbol (NMICR), and bit field symbol
(NMIMD)
ICU.NMICR
A period separates a function module symbol (ICU) and register symbol (NMICR)
NMICR.NMIMD
A period separates a register symbol (NMICR) and bit field symbol (NMIMD)
NFCLKSEL[1:0]
In a register bit name, the bit range enclosed in square brackets indicates the number of bits in the field
at this location. In this example, NFCLKSEL[1:0] represents a 2-bit field at the specified location in the
NMI Pin Interrupt Control Register (NMICR).
6.
Unit Prefix
The following unit prefixes are sometimes misleading. Those unit prefixes are described throughout this manual with the
following meaning:
Prefix
Description
b
Bit
B
Byte. This unit prefix is generally used for memory specification of the MCU and address space.
k
1000 = 103. k is also used to denote 1024 (210) but this unit prefix is used to denote 1000 (103)
throughout this manual.
K
1024 = 210. This unit prefix is used to denote 1024 (210) not 1000 (103) throughout this manual.
7.
Special Terms
The following terms have special meanings:
Term
Description
NC
Not connected pin. NC means the pin is not connected to the MCU.
Hi-Z
High impedance
8.
Register Description
Each register description includes both a register diagram that shows the bit assignments and a register bit table that
describes the content of each bit. The example of symbols used in these tables are described in the sections that follow.
The following is an example of a register description and associated bit field definition.
X.X.X
NMI Pin Interrupt Control Register (NMICR)
Address(es):
Value after reset:
(1)
ICU.NMICR 4000 6100h
b7
b6
NFLTE
N
—
0
0
b5
b4
NFCLKSEL[1:0]
0
0
b3
b2
b1
b0
—
—
—
NMIMD
0
0
0
0
(4)
(2)
(3)
(6)
(5)
Bit
Symbol
Bit name
Description
R/W
b0
NMIMD
NMI Detection Set
0: Falling edge
1: Rising edge.
R/W
b3 to b1 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5, b4
NFCLKSEL[1:0]
NMI Digital Filter Sampling Clock
Select
b5 b4
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
NFLTEN
NMI Digital Filter Enable
0: Disable the digital filter
1: Enable the digital filter.
R/W
0
0
1
1
0: PCLKB
1: PCLKB/8
0: PCLKB/32
1: PCLKB/64.
(1) Function module symbol, register symbol, and address assignment
Function module symbol, register symbol, and address assignment of this register are generally expressed. ICU.NMICR
4000 6100h means NMI Pin Interrupt Control Register (NMICR) of Interrupt Controller Unit (ICU) is assigned to
address 4000 6100h.
(2) Bit number
This number indicates the bit number. These bits are shown in order from b31 to b0 for a 32-bit register, from b15 to b0
for a 16-bit register, and from b7 to b0 for an 8-bit register.
(3) Value after reset
This symbol or number indicates the value of each bit after a reset. The value is shown in binary unless specified
otherwise.
0: Indicates that the value is 0 after a reset.
1: Indicates that the value is 1 after a reset.
x: Indicates that the value is undefined after a reset.
(4) Bit symbol
Bit symbol indicates the short name of the bit field. Reserved bit is expressed with a —.
(5) Bit name
Bit name indicates the full name of the bit field.
(6) R/W
The R/W column indicates access type: whether the bit field is read or write.
R/W: The bit field is read and write.
R/(W): The bit field is read and write. But writing to this bit field has some limitations. For details on the limitations,
see the description or notes of respective registers.
R: The bit field is read-only. Writing to this bit field has no effect.
W: The bit field is write-only. The read value is undefined.
9.
Abbreviations
Abbreviations used in this manual are shown in the following table:
Abbreviation
AES
Description
Advanced Encryption Standard
AHB
Advanced High-Performance Bus
AHB-AP
AHB Access Port
APB
Advanced Peripheral Bus
ARC
Alleged RC
ATB
Advanced Trace Bus
BCD
Binary Coded Decimal
BSDL
Boundary Scan Description Language
DES
Data Encryption Standard
DSA
Digital Signature Algorithm
ECC
Elliptic Curve Cryptography
ETB
Embedded Trace Buffer
ETM
Embedded Trace Macrocell
FLL
Frequency Locked Loop
FPU
Floating-Point Unit
GSM
Global System for Mobile communications
HMI
Human Machine Interface
IrDA
Infrared Data Association
LSB
Least Significant Bit
MSB
Most Significant Bit
NVIC
Nested Vector Interrupt Controller
PC
Program Counter
PFS
Port Function Select
PLL
Phase Locked Loop
POR
Power-On Reset
PWM
Pulse Width Modulation
RSA
Rivest Shamir Adleman
SHA
Secure Hash Algorithm
S/H
Sample and Hold
SP
Stack Pointer
SWD
Serial Wire Debug
SW-DP
Serial Wire-Debug Port
TRNG
True Random Number Generator
UART
Universal Asynchronous Receiver/Transmitter
10. Proprietary Notice
All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained
in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and
trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein,
no part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded,
translated, transmitted or distributed in any other medium for publication or distribution or for any commercial
enterprise, without prior written consent from Renesas.
Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.
CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium.
Magic Packet™ is a trademark of Advanced Micro Devices, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective
holders.
11. Website and Support
Visit the following vanity URLs to learn about key elements of the Synergy Platform, download components and related
documentation, and get support.
Synergy Software
renesassynergy.com/software
Synergy Software Package
renesassynergy.com/ssp
Software add-ons
renesassynergy.com/addons
Software glossary
renesassynergy.com/softwareglossary
Development tools
renesassynergy.com/tools
Synergy Hardware
renesassynergy.com/hardware
Microcontrollers
renesassynergy.com/mcus
MCU glossary
renesassynergy.com/mcuglossary
Parametric search
renesassynergy.com/parametric
Kits
renesassynergy.com/kits
Synergy Solutions Gallery
renesassynergy.com/solutionsgallery
Partner projects
renesassynergy.com/partnerprojects
Application projects
renesassynergy.com/applicationprojects
Self-service support resources:
Documentation
renesassynergy.com/docs
Knowledgebase
renesassynergy.com/knowledgebase
Forums
renesassynergy.com/forum
Training
renesassynergy.com/training
Videos
renesassynergy.com/videos
Chat and web ticket
renesassynergy.com/support
12. Feedback on the Product
If you have any comments or suggestions about this product, go to renesassynergy.com/support.
13. Feedback on Content
If you have any comments on the document such as general suggestions for improvements, go to
renesassynergy.com/support, and provide:
- The title of the Renesas Synergy document
- The document number
- If applicable, the page number(s) to which your comments refer
- A detailed explanation of your comments.
Contents
Features ................................................................................................................................................... 48
1.
2.
Overview ........................................................................................................................................ 49
1.1
Function Outline ................................................................................................................... 49
1.2
Block Diagram ..................................................................................................................... 55
1.3
Part Numbering .................................................................................................................... 56
1.4
Function Comparison ........................................................................................................... 57
1.5
Pin Functions ....................................................................................................................... 58
1.6
Pin Assignments .................................................................................................................. 62
1.7
Pin Lists ............................................................................................................................... 69
CPU ............................................................................................................................................... 74
2.1
Overview .............................................................................................................................. 74
2.1.1
CPU ............................................................................................................................. 74
2.1.2
Debug .......................................................................................................................... 74
2.1.3
Operating Frequency ................................................................................................... 75
2.2
MCU Implementation Options .............................................................................................. 76
2.3
Trace Interface ..................................................................................................................... 76
2.4
JTAG/SWD Interface ........................................................................................................... 77
2.5
Debug Mode ........................................................................................................................ 77
2.5.1
Debug Mode Definition ................................................................................................ 77
2.5.2
Debug Mode Effects .................................................................................................... 77
2.6
Programmers Model ............................................................................................................ 79
2.6.1
Address Spaces .......................................................................................................... 79
2.6.2
Cortex-M4 Peripheral Address Map ............................................................................ 79
2.6.3
CoreSight ROM Table ................................................................................................. 80
2.6.4
DBGREG Module ........................................................................................................ 81
2.6.5
OCDREG Module ........................................................................................................ 84
2.7
CoreSight ATB Funnel ......................................................................................................... 86
2.8
Flash Patch and Break Unit ................................................................................................. 87
2.9
SysTick System Timer ......................................................................................................... 87
2.10
CoreSight Time Stamp Generator ....................................................................................... 87
2.11
OCD Emulator Connection .................................................................................................. 87
2.11.1
DBGEN ........................................................................................................................ 87
2.11.2
Unlock ID Code ........................................................................................................... 87
2.11.3
Restrictions on Connecting an OCD Emulator ............................................................ 88
2.12
3.
References .......................................................................................................................... 89
Operating Modes ........................................................................................................................... 90
3.1
Overview .............................................................................................................................. 90
3.2
Operating Mode Details ....................................................................................................... 90
3.2.1
Single-Chip Mode ........................................................................................................ 90
3.2.2
SCI Boot Mode ............................................................................................................ 90
3.2.3
USB Boot Mode ........................................................................................................... 90
3.3
Operating Mode Transitions ................................................................................................ 90
3.3.1
4.
5.
Address Space ............................................................................................................................... 91
4.1
Overview .............................................................................................................................. 91
4.2
External Address Space ...................................................................................................... 92
Memory Mirror Function (MMF) ..................................................................................................... 93
5.1
Overview .............................................................................................................................. 93
5.2
Register Descriptions ........................................................................................................... 93
5.2.1
MemMirror Special Function Register (MMSFR) ......................................................... 93
5.2.2
MemMirror Enable Register (MMEN) .......................................................................... 94
5.3
6.
Operation ............................................................................................................................. 94
5.3.1
MMF Operation ............................................................................................................ 94
5.3.2
Setting Example .......................................................................................................... 97
Resets ............................................................................................................................................ 98
6.1
Overview .............................................................................................................................. 98
6.2
Register Descriptions ......................................................................................................... 102
6.2.1
Reset Status Register 0 (RSTSR0) ........................................................................... 102
6.2.2
Reset Status Register 1 (RSTSR1) ........................................................................... 103
6.2.3
Reset Status Register 2 (RSTSR2) ........................................................................... 105
6.3
7.
Operating Mode Transitions as Determined by the Mode-Setting Pin ........................ 90
Operation ........................................................................................................................... 106
6.3.1
RES Pin Reset ........................................................................................................... 106
6.3.2
Power-On Reset ........................................................................................................ 106
6.3.3
Voltage Monitor Reset ............................................................................................... 107
6.3.4
Independent Watchdog Timer Reset ......................................................................... 108
6.3.5
Watchdog Timer Reset .............................................................................................. 108
6.3.6
Software Reset .......................................................................................................... 108
6.3.7
Determination of Cold/Warm Start ............................................................................. 108
6.3.8
Determination of Reset Generation Source ............................................................... 109
Option-Setting Memory ................................................................................................................ 110
7.1
Overview ............................................................................................................................ 110
7.2
Register Descriptions ......................................................................................................... 110
7.2.1
Option Function Select Register 0 (OFS0) ................................................................ 110
7.2.2
Option Function Select Register 1 (OFS1) ................................................................ 114
7.2.3
MPU Registers .......................................................................................................... 115
7.2.4
Access Window Setting Control Register (AWSC) .................................................... 116
7.2.5
Access Window Setting Register (AWS) ................................................................... 116
7.2.6
OCD/Serial Programmer ID Setting Register (OSIS) ................................................ 118
7.3
Setting Option-Setting Memory .......................................................................................... 119
7.3.1
Allocation of Data in Option-Setting Memory ............................................................. 119
7.3.2
7.4
Setting Data for Programming Option-Setting Memory ............................................. 119
Usage Note ........................................................................................................................ 119
7.4.1
8.
Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory
.................................................................................................................................... 119
Low Voltage Detection (LVD) ....................................................................................................... 120
8.1
Overview ............................................................................................................................ 120
8.2
Register Descriptions ......................................................................................................... 122
8.2.1
Voltage Monitor 1 Circuit Control Register 1 (LVD1CR1) .......................................... 122
8.2.2
Voltage Monitor 1 Circuit Status Register (LVD1SR) ................................................. 122
8.2.3
Voltage Monitor 2 Circuit Control Register 1 (LVD2CR1) .......................................... 123
8.2.4
Voltage Monitor 2 Circuit Status Register (LVD2SR) ................................................. 123
8.2.5
Voltage Monitor Circuit Control Register (LVCMPCR) ............................................... 124
8.2.6
Voltage Detection Level Select Register (LVDLVLR) ................................................. 125
8.2.7
Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0) .......................................... 125
8.2.8
Voltage Monitor 2 Circuit Control Register 0 (LVD2CR0) .......................................... 127
8.3
VCC Input Voltage Monitor ................................................................................................ 128
8.3.1
Monitoring Vdet0 ......................................................................................................... 128
8.3.2
Monitoring Vdet1 ......................................................................................................... 128
8.3.3
Monitoring Vdet2 ......................................................................................................... 128
8.4
Reset from Voltage Monitor 0 ............................................................................................ 129
8.5
Interrupt and Reset from Voltage Monitor 1 ....................................................................... 129
8.6
Interrupt and Reset from Voltage Monitor 2 ....................................................................... 131
8.7
Event Link Output .............................................................................................................. 133
8.7.1
9.
Interrupt Handling and Event Linking ........................................................................ 133
Clock Generation Circuit .............................................................................................................. 135
9.1
Overview ............................................................................................................................ 135
9.2
Register Descriptions ......................................................................................................... 138
9.2.1
System Clock Division Control Register (SCKDIVCR) .............................................. 138
9.2.2
System Clock Source Control Register (SCKSCR) ................................................... 140
9.2.3
PLL Clock Control Register 2 (PLLCCR2) ................................................................. 141
9.2.4
PLL Control Register (PLLCR) .................................................................................. 141
9.2.5
External Bus Clock Control Register (BCKCR) ......................................................... 142
9.2.6
Memory Wait Cycle Control Register (MEMWAIT) .................................................... 143
9.2.7
Main Clock Oscillator Control Register (MOSCCR) .................................................. 145
9.2.8
Sub-Clock Oscillator Control Register (SOSCCR) .................................................... 146
9.2.9
Low-Speed On-Chip Oscillator Control Register (LOCOCR) .................................... 147
9.2.10
High-Speed On-Chip Oscillator Control Register (HOCOCR) ................................... 148
9.2.11
Middle-Speed On-Chip Oscillator Control Register (MOCOCR) ............................... 149
9.2.12
Oscillation Stabilization Flag Register (OSCSF) ........................................................ 149
9.2.13
Oscillation Stop Detection Control Register (OSTDCR) ............................................ 151
9.2.14
Oscillation Stop Detection Status Register (OSTDSR) .............................................. 152
9.2.15
Main Clock Oscillator Wait Control Register (MOSCWTCR) ..................................... 153
9.2.16
High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR) ..................... 154
9.2.17
Main Clock Oscillator Mode Oscillation Control Register (MOMCR) ......................... 155
9.2.18
Sub-Clock Oscillator Mode Control Register (SOMCR) ............................................ 155
9.2.19
Segment LCD Source Clock Control Register (SLCDSCKCR) ................................. 156
9.2.20
Clock Out Control Register (CKOCR) ....................................................................... 157
9.2.21
External Bus Clock Output Control Register (EBCKOCR) ........................................ 158
9.2.22
LOCO User Trimming Control Register (LOCOUTCR) ............................................. 158
9.2.23
MOCO User Trimming Control Register (MOCOUTCR) ........................................... 159
9.2.24
HOCO User Trimming Control Register (HOCOUTCR) ............................................ 159
9.2.25
Trace Clock Control Register (TRCKCR) .................................................................. 160
9.2.26
USB Clock Control Register (USBCKCR) ................................................................. 160
9.3
Main Clock Oscillator ......................................................................................................... 161
9.3.1
Connecting a Crystal Resonator ................................................................................ 161
9.3.2
External Clock Input .................................................................................................. 161
9.3.3
Notes on External Clock Input ................................................................................... 161
9.4
Sub-Clock Oscillator .......................................................................................................... 162
9.4.1
9.5
Connecting a 32.768-kHz Crystal Resonator ............................................................ 162
Oscillation Stop Detection Function ................................................................................... 162
9.5.1
Oscillation Stop Detection and Operation after Detection ......................................... 162
9.5.2
Oscillation Stop Detection Interrupts ......................................................................... 164
9.6
PLL Circuit ......................................................................................................................... 164
9.7
Internal Clock ..................................................................................................................... 164
9.7.1
System Clock (ICLK) ................................................................................................. 165
9.7.2
Peripheral Module Clock (PCLKA, PCLKB, PCLKC, PCLKD) .................................. 165
9.7.3
Flash Interface Clock (FCLK) .................................................................................... 165
9.7.4
External Bus Clock (BCLK) ....................................................................................... 165
9.7.5
USB Clock (UCLK) .................................................................................................... 166
9.7.6
CAN Clock (CANMCLK) ............................................................................................ 166
9.7.7
CAC Clock (CACCLK) ............................................................................................... 166
9.7.8
RTC-Dedicated Clock (RTCSCLK, RTCLCLK) ......................................................... 166
9.7.9
IWDT-Dedicated Clock (IWDTCLK) .......................................................................... 166
9.7.10
AGT-Dedicated Clock (AGTSCLK, AGTLCLK) ......................................................... 166
9.7.11
SysTick Timer-Dedicated Clock (SYSTICCLK) ......................................................... 166
9.7.12
Segment LCDC Source Clock (LCDSRCCLK) .......................................................... 166
9.7.13
Clock/Buzzer Output Clock (CLKOUT) ...................................................................... 167
9.7.14
JTAG Clock (JTAGTCK) ............................................................................................ 167
9.8
Usage Notes ...................................................................................................................... 167
9.8.1
Notes on Clock Generation Circuit ............................................................................ 167
9.8.2
Notes on Resonator ................................................................................................... 167
9.8.3
Notes on Board Design ............................................................................................. 167
9.8.4
10.
Notes on Resonator Connect Pin .............................................................................. 168
Clock Frequency Accuracy Measurement Circuit (CAC) ............................................................. 169
10.1
Overview ............................................................................................................................ 169
10.2
Register Descriptions ......................................................................................................... 170
10.2.1
CAC Control Register 0 (CACR0) ............................................................................. 170
10.2.2
CAC Control Register 1 (CACR1) ............................................................................. 171
10.2.3
CAC Control Register 2 (CACR2) ............................................................................. 172
10.2.4
CAC Interrupt Control Register (CAICR) ................................................................... 173
10.2.5
CAC Status Register (CASTR) .................................................................................. 174
10.2.6
CAC Upper-Limit Value Setting Register (CAULVR) ................................................. 175
10.2.7
CAC Lower-Limit Value Setting Register (CALLVR) .................................................. 175
10.2.8
CAC Counter Buffer Register (CACNTBR) ............................................................... 175
10.3
Operation ........................................................................................................................... 176
10.3.1
Measuring Clock Frequency ...................................................................................... 176
10.3.2
Digital Filtering of Signals on CACREF Pin ............................................................... 177
10.4
Interrupt Requests ............................................................................................................. 177
10.5
Usage Note ........................................................................................................................ 177
10.5.1
11.
Module-Stop Function Setting ................................................................................... 177
Low Power Modes ....................................................................................................................... 178
11.1
Overview ............................................................................................................................ 178
11.2
Register Descriptions ......................................................................................................... 181
11.2.1
Standby Control Register (SBYCR) ........................................................................... 181
11.2.2
Module Stop Control Register A (MSTPCRA) ........................................................... 182
11.2.3
Module Stop Control Register B (MSTPCRB) ........................................................... 183
11.2.4
Module Stop Control Register C (MSTPCRC) ........................................................... 184
11.2.5
Module Stop Control Register D (MSTPCRD) ........................................................... 185
11.2.6
Operating Power Control Register (OPCCR) ............................................................ 186
11.2.7
Sub Operating Power Control Register (SOPCCR) .................................................. 187
11.2.8
Snooze Control Register (SNZCR) ............................................................................ 188
11.2.9
Snooze End Control Register (SNZEDCR) ............................................................... 188
11.2.10
Snooze Request Control Register (SNZREQCR) ..................................................... 190
11.2.11
Flash Operation Control Register (FLSTOP) ............................................................. 192
11.2.12
Power Save Memory Control Register (PSMCR) ...................................................... 193
11.2.13
System Control OCD Control Register (SYOCDCR) ................................................. 193
11.3
Reducing Power Consumption by Switching Clock Signals .............................................. 194
11.4
Module-Stop Function ........................................................................................................ 194
11.5
Function for Lower Operating Power Consumption ........................................................... 194
11.5.1
Setting Operating Power Control Mode ..................................................................... 194
11.5.2
Operating Range ....................................................................................................... 196
11.6
Sleep Mode ........................................................................................................................ 199
11.6.1
Transition to Sleep Mode ........................................................................................... 199
11.6.2
11.7
Software Standby Mode .................................................................................................... 200
11.7.1
Transition to Software Standby Mode ....................................................................... 200
11.7.2
Canceling Software Standby Mode ........................................................................... 200
11.7.3
Example of Software Standby Mode Application ....................................................... 201
11.8
Snooze Mode ..................................................................................................................... 202
11.8.1
Transition to Snooze Mode ........................................................................................ 202
11.8.2
Canceling Snooze Mode ........................................................................................... 203
11.8.3
Returning to Software Standby Mode ........................................................................ 203
11.8.4
Snooze Operation Example ....................................................................................... 205
11.9
12.
Canceling Sleep Mode .............................................................................................. 199
Usage Notes ...................................................................................................................... 208
11.9.1
Register Access ......................................................................................................... 208
11.9.2
I/O Port States ........................................................................................................... 209
11.9.3
Module-Stop State of DMAC and DTC ...................................................................... 210
11.9.4
Internal Interrupt Sources .......................................................................................... 210
11.9.5
Transition to Low Power Modes ................................................................................ 210
11.9.6
Timing of WFI Instruction ........................................................................................... 210
11.9.7
Writing WDT/IWDT Registers by DMAC or DTC in Sleep Mode or Snooze Mode ... 210
11.9.8
Oscillators in Snooze Mode ....................................................................................... 210
11.9.9
Snooze Mode Entry by RXD0 Falling Edge ............................................................... 210
11.9.10
Using SCI0 in Snooze Mode ..................................................................................... 210
11.9.11
Conditions of A/D Conversion Start in Snooze Mode ................................................ 211
11.9.12
Conditions of CTSU in Snooze Mode ........................................................................ 211
11.9.13
ELC Event in Snooze Mode ...................................................................................... 211
11.9.14
Module-Stop Function for ADC140 ............................................................................ 211
11.9.15
Module-Stop Function for an Unused Circuit ............................................................. 211
Battery Backup Function .............................................................................................................. 212
12.1
Overview ............................................................................................................................ 212
12.1.1
Features of Battery Backup Function ........................................................................ 212
12.1.2
Battery Power Supply Switch .................................................................................... 212
12.1.3
VBATT Pin Low Voltage Detection ............................................................................ 212
12.1.4
VBATT_R Low Voltage Detection ............................................................................. 212
12.1.5
Backup Registers ...................................................................................................... 212
12.1.6
VBATT Wakeup Control Function ............................................................................. 213
12.1.7
Time Capture Pin Detection ...................................................................................... 213
12.2
Register Descriptions ......................................................................................................... 215
12.2.1
VBATT Control Register 1 (VBTCR1) ........................................................................ 215
12.2.2
VBATT Control Register 2 (VBTCR2) ........................................................................ 216
12.2.3
VBATT Status Register (VBTSR) .............................................................................. 217
12.2.4
VBATT Comparator Control Register (VBTCMPCR) ................................................. 218
12.2.5
VBATT Pin Low Voltage Detect Interrupt Control Register (VBTLVDICR) ................ 218
12.2.6
VBATT Backup Register (VBTBKRn) (n = 0 to 511) .................................................. 218
12.2.7
VBATT Wakeup Control Register (VBTWCTLR) ....................................................... 219
12.2.8
VBATT Wakeup I/O 0 Output Trigger Select Register (VBTWCH0OTSR) ................ 219
12.2.9
VBATT Wakeup I/O 1 Output Trigger Select Register (VBTWCH1OTSR) ................ 220
12.2.10
VBATT Wakeup I/O 2 Output Trigger Select Register (VBTWCH2OTSR) ................ 221
12.2.11
VBATT Input Control Register (VBTICTLR) .............................................................. 221
12.2.12
VBATT Output Control Register (VBTOCTLR) .......................................................... 222
12.2.13
VBATT Wakeup Trigger Source Enable Register (VBTWTER) ................................. 223
12.2.14
VBATT Wakeup Trigger Source Edge Register (VBTWEGR) ................................... 223
12.2.15
VBATT Wakeup Trigger Source Flag Register (VBTWFR) ........................................ 224
12.2.16
Backup Register Access Control Register (BKRACR) .............................................. 225
12.3
12.3.1
Battery Backup Function ........................................................................................... 226
12.3.2
VBATT Battery Power Supply Switch Usage ............................................................ 228
12.3.3
VBATT Pin Low Voltage Detection Procedures ........................................................ 228
12.3.4
VBATT Backup Register Usage ................................................................................ 229
12.3.5
VBATT Wakeup Control Function Usage .................................................................. 230
12.4
13.
Operation ........................................................................................................................... 226
Usage Notes ...................................................................................................................... 232
Register Write Protection ............................................................................................................. 233
13.1
Overview ............................................................................................................................ 233
13.2
Register Descriptions ......................................................................................................... 233
13.2.1
14.
Protect Register (PRCR) ........................................................................................... 233
Interrupt Controller Unit (ICU) ...................................................................................................... 234
14.1
Overview ............................................................................................................................ 234
14.2
Register Descriptions ......................................................................................................... 236
14.2.1
IRQ Control Register i (IRQCRi) (i = 0 to 15) ............................................................ 236
14.2.2
Non-Maskable Interrupt Status Register (NMISR) ..................................................... 237
14.2.3
Non-Maskable Interrupt Enable Register (NMIER) ................................................... 240
14.2.4
Non-Maskable Interrupt Status Clear Register (NMICLR) ......................................... 241
14.2.5
NMI Pin Interrupt Control Register (NMICR) ............................................................. 243
14.2.6
ICU Event Link Setting Register n (IELSRn) ............................................................. 244
14.2.7
DMAC Event Link Setting Register n (DELSRn) ....................................................... 245
14.2.8
SYS Event Link Setting Register (SELSR0) .............................................................. 246
14.2.9
Wake Up Interrupt Enable Register (WUPEN) .......................................................... 246
14.3
Vector Table ...................................................................................................................... 249
14.3.1
Interrupt Vector Table ................................................................................................ 249
14.3.2
Event Number ............................................................................................................ 251
14.4
Interrupt Operation ............................................................................................................. 257
14.4.1
Detecting Interrupts ................................................................................................... 257
14.4.2
Selecting Interrupt Request Destinations .................................................................. 258
14.4.3
Digital Filter ................................................................................................................ 259
14.4.4
15.
External Pin Interrupts ............................................................................................... 260
14.5
Non-maskable Interrupt Operation .................................................................................... 261
14.6
Return from Low Power Mode ........................................................................................... 261
14.6.1
Return from Sleep Mode ........................................................................................... 261
14.6.2
Return from Software Standby Mode ........................................................................ 262
14.6.3
Return from Snooze Mode ........................................................................................ 262
14.7
Using the WFI Instruction with Non-maskable Interrupts ................................................... 262
14.8
Reference .......................................................................................................................... 262
Buses ........................................................................................................................................... 263
15.1
Overview ............................................................................................................................ 263
15.2
Description of Buses .......................................................................................................... 264
15.2.1
Main Buses ................................................................................................................ 264
15.2.2
Slave Interface ........................................................................................................... 264
15.2.3
External Bus .............................................................................................................. 264
15.2.4
Parallel Operation ...................................................................................................... 266
15.2.5
Bus Settings .............................................................................................................. 266
15.2.6
Restrictions ................................................................................................................ 266
15.3
Register Descriptions ......................................................................................................... 267
15.3.1
CSn Control Register (CSnCR) (n = 0 to 3) .............................................................. 267
15.3.2
CSn Recovery Cycle Register (CSnREC) (n = 0 to 3) .............................................. 268
15.3.3
CS Recovery Cycle Insertion Enable Register (CSRECEN) ..................................... 269
15.3.4
CSn Mode Register (CSnMOD) (n = 0 to 3) .............................................................. 271
15.3.5
CSn Wait Control Register 1 (CSnWCR1) (n = 0 to 3) .............................................. 272
15.3.6
CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 3) .............................................. 274
15.3.7
Master Bus Control Register (BUSMCNT) ................................................. 277
15.3.8
Slave Bus Control Register (BUSSCNT) ...................................................... 278
15.3.9
Bus Error Address Register (BUSnERRADD) (n = 1 to 4) ........................................ 279
15.3.10
Bus Error Status Register (BUSnERRSTAT) (n = 1 to 4) .......................................... 279
15.4
Endianness and Data Alignment ....................................................................................... 281
15.4.1
15.5
Data Alignment Control for the CS Areas .................................................................. 281
Operation of CS Area Controller ........................................................................................ 284
15.5.1
Separate Bus ............................................................................................................. 284
15.5.2
Address/Data Multiplexed Bus .................................................................................. 294
15.5.3
External Wait Function .............................................................................................. 296
15.5.4
Insertion of Recovery Cycles ..................................................................................... 299
15.5.5
No Access State ........................................................................................................ 303
15.5.6
Write Buffer Function (External Bus) ......................................................................... 303
15.5.7
Constraints ................................................................................................................ 303
15.6
Bus Error Monitoring Section ............................................................................................. 305
15.6.1
Error Type that Occurs by Bus .................................................................................. 305
15.6.2
Operation when a Bus Error Occurs .......................................................................... 305
16.
15.6.3
Conditions Leading to Illegal Address Access Errors ................................................ 305
15.6.4
Timeout ...................................................................................................................... 306
15.7
Notes on Using Flash Cache ............................................................................................. 306
15.8
References ........................................................................................................................ 306
Memory Protection Unit (MPU) .................................................................................................... 307
16.1
Overview ............................................................................................................................ 307
16.2
CPU Stack Pointer Monitor ................................................................................................ 307
16.2.1
Protection of Registers .............................................................................................. 309
16.2.2
Overflow/Underflow Error .......................................................................................... 309
16.2.3
Register Descriptions ................................................................................................ 310
16.3
Arm MPU ........................................................................................................................... 315
16.4
Bus Master MPU ................................................................................................................ 315
16.4.1
Register Descriptions ................................................................................................ 317
16.4.2
Operation ................................................................................................................... 322
16.5
16.5.1
Register Descriptions ................................................................................................ 325
16.5.2
Functions ................................................................................................................... 334
16.6
Security MPU ..................................................................................................................... 334
16.6.1
Register Descriptions (Option-Setting Memory) ........................................................ 335
16.6.2
Memory Protection .................................................................................................... 341
16.6.3
Notes on Debug ......................................................................................................... 342
16.7
17.
Bus Slave MPU .................................................................................................................. 324
References ........................................................................................................................ 342
DMA Controller (DMAC) .............................................................................................................. 343
17.1
Overview ............................................................................................................................ 343
17.2
Register Descriptions ......................................................................................................... 345
17.2.1
DMA Source Address Register (DMSAR) ................................................................. 345
17.2.2
DMA Destination Address Register (DMDAR) .......................................................... 345
17.2.3
DMA Transfer Count Register (DMCRA) ................................................................... 346
17.2.4
DMA Block Transfer Count Register (DMCRB) ......................................................... 347
17.2.5
DMA Transfer Mode Register (DMTMD) ................................................................... 347
17.2.6
DMA Interrupt Setting Register (DMINT) ................................................................... 348
17.2.7
DMA Address Mode Register (DMAMD) ................................................................... 349
17.2.8
DMA Offset Register (DMOFR) ................................................................................. 351
17.2.9
DMA Transfer Enable Register (DMCNT) ................................................................. 351
17.2.10
DMA Software Start Register (DMREQ) .................................................................... 352
17.2.11
DMA Status Register (DMSTS) ................................................................................. 353
17.2.12
DMAC Module Activation Register (DMAST) ............................................................ 354
17.3
Operation ........................................................................................................................... 355
17.3.1
Transfer Mode ........................................................................................................... 355
17.3.2
Extended Repeat Area Function ............................................................................... 358
17.3.3
Address Update Function Using Offset ..................................................................... 359
17.3.4
Activation Sources ..................................................................................................... 363
17.3.5
Operation Timing ....................................................................................................... 363
17.3.6
Execution Cycles of DMAC ....................................................................................... 364
17.3.7
Activating DMAC ....................................................................................................... 365
17.3.8
Starting DMA Transfer ............................................................................................... 366
17.3.9
Registers during DMA Transfer ................................................................................. 366
17.3.10
Channel Priority ......................................................................................................... 367
17.4
18.
Ending DMA Transfer ........................................................................................................ 367
17.4.1
Transfer End by Completion of Specified Total Number of Transfer Operations ...... 367
17.4.2
Transfer End by Repeat Size End Interrupt ............................................................... 367
17.4.3
Transfer End by Interrupt on Extended Repeat Area Overflow ................................. 368
17.4.4
Precautions for the End of DMA Transfer .................................................................. 368
17.5
Interrupts ............................................................................................................................ 368
17.6
Event Link .......................................................................................................................... 369
17.7
Low Power Consumption Function .................................................................................... 369
17.8
Usage Notes ...................................................................................................................... 370
17.8.1
DMA Transfer to External Devices ............................................................................ 370
17.8.2
Access to Registers during DMA Transfer ................................................................ 370
17.8.3
DMA Transfer to Reserved Areas ............................................................................. 370
17.8.4
Setting the DMAC Event Link Setting Register of the Interrupt Controller Unit (ICU.DELSRn) .......................................................................................................................... 370
17.8.5
Suspending or Restarting DMA Activation ................................................................ 370
Data Transfer Controller (DTC) .................................................................................................... 371
18.1
Overview ............................................................................................................................ 371
18.2
Register Descriptions ......................................................................................................... 373
18.2.1
DTC Mode Register A (MRA) .................................................................................... 373
18.2.2
DTC Mode Register B (MRB) .................................................................................... 374
18.2.3
DTC Transfer Source Register (SAR) ....................................................................... 375
18.2.4
DTC Transfer Destination Register (DAR) ................................................................ 375
18.2.5
DTC Transfer Count Register A (CRA) ..................................................................... 376
18.2.6
DTC Transfer Count Register B (CRB) ..................................................................... 377
18.2.7
DTC Control Register (DTCCR) ................................................................................ 377
18.2.8
DTC Vector Base Register (DTCVBR) ...................................................................... 378
18.2.9
DTC Module Start Register (DTCST) ........................................................................ 378
18.2.10
DTC Status Register (DTCSTS) ................................................................................ 379
18.3
Activation Sources ............................................................................................................. 379
18.3.1
18.4
Allocating Transfer Information and DTC Vector Table ............................................. 380
Operation ........................................................................................................................... 381
18.4.1
Transfer Information Read Skip Function .................................................................. 383
18.4.2
Transfer Information Write-Back Skip Function ......................................................... 383
18.4.3
Normal Transfer Mode ............................................................................................... 384
18.4.4
Repeat Transfer Mode ............................................................................................... 385
18.4.5
Block Transfer Mode ................................................................................................. 386
18.4.6
Chain Transfer ........................................................................................................... 387
18.4.7
Operation Timing ....................................................................................................... 388
18.4.8
Execution Cycles of DTC ........................................................................................... 390
18.4.9
DTC Bus Mastership Release Timing ....................................................................... 390
18.5
DTC Setting Procedure ...................................................................................................... 390
18.6
Examples of DTC Usage ................................................................................................... 392
18.6.1
Normal Transfer ......................................................................................................... 392
18.6.2
Chain Transfer ........................................................................................................... 392
18.6.3
Chain Transfer When Counter = 0 ............................................................................ 394
18.7
Interrupt Sources ............................................................................................................... 395
18.8
Event Link .......................................................................................................................... 395
18.9
Snooze Control Interface ................................................................................................... 395
18.10
Module-Stop Function ........................................................................................................ 396
18.11
Usage Notes ...................................................................................................................... 396
18.11.1
19.
Event Link Controller (ELC) ......................................................................................................... 397
19.1
Overview ............................................................................................................................ 397
19.2
Register Descriptions ......................................................................................................... 397
19.2.1
Event Link Controller Register (ELCR) ...................................................................... 397
19.2.2
Event Link Software Event Generation Register n (ELSEGRn) (n = 0, 1) ................. 398
19.2.3
Event Link Setting Register n (ELSRn) (n = 0 to 9, 12, 14 to 18) .............................. 398
19.3
Operation ........................................................................................................................... 404
19.3.1
Relation between Interrupt Handling and Event Linking ............................................ 404
19.3.2
Linking Events ........................................................................................................... 404
19.3.3
Example of Procedure for Linking Events ................................................................. 404
19.4
20.
Transfer Information Start Address ........................................................................... 396
Usage Notes ...................................................................................................................... 404
19.4.1
Linking DMAC or DTC Transfer End Signals as Events ............................................ 404
19.4.2
Setting Clocks ............................................................................................................ 404
19.4.3
Module-Stop Function Setting ................................................................................... 405
19.4.4
ELC Delay Time ........................................................................................................ 405
I/O Ports ....................................................................................................................................... 406
20.1
Overview ............................................................................................................................ 406
20.2
Register Descriptions ......................................................................................................... 408
20.2.1
Port Control Register 1 (PCNTR1/PODR/PDR) ........................................................ 408
20.2.2
Port Control Register 2 (PCNTR2/EIDR/PIDR) ......................................................... 409
20.2.3
Port Control Register 3 (PCNTR3/PORR/POSR) ...................................................... 410
20.2.4
Port Control Register 4 (PCNTR4/EORR/EOSR) ...................................................... 411
20.2.5
Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY)
(m = 0 to 9; n = 00 to 15) ........................................................................................... 412
20.2.6
Write-Protect Register (PWPR) ................................................................................. 414
20.3
Operation ........................................................................................................................... 415
20.3.1
General I/O Ports ....................................................................................................... 415
20.3.2
Port Function Select .................................................................................................. 415
20.3.3
Port Group Function for ELC ..................................................................................... 416
20.4
Handling of Unused Pins ................................................................................................... 417
20.5
Usage Notes ...................................................................................................................... 418
20.5.1
Procedure for Specifying the Pin Functions .............................................................. 418
20.5.2
Procedure for Using Port Group Input ....................................................................... 418
20.5.3
Port Output Data Register (PODR) Summary ........................................................... 418
20.5.4
Notes on Using of Analog Functions ......................................................................... 418
20.5.5
I/O Buffer Specification .............................................................................................. 418
20.5.6
Selecting USB_DP and USB_DM Pins ..................................................................... 419
20.5.7
Pull-up/Pull-down Setting for P914 and P915 using USBFS/GPIO Function ............ 419
20.6
21.
Key Interrupt Function (KINT) ...................................................................................................... 432
21.1
Overview ............................................................................................................................ 432
21.2
Register Descriptions ......................................................................................................... 434
21.2.1
Key Return Control Register (KRCTL) ...................................................................... 434
21.2.2
Key Return Flag Register (KRF) ................................................................................ 434
21.2.3
Key Return Mode Register (KRM) ............................................................................. 434
21.3
Operation ........................................................................................................................... 435
21.3.1
When Not Using Key Interrupt Flag (KRMD = 0) ....................................................... 435
21.3.2
Operation When Using Key Interrupt Flag (KRMD = 1) ............................................ 436
21.4
22.
Peripheral Select Settings for each Product ...................................................................... 419
Usage Notes ...................................................................................................................... 437
Port Output Enable for GPT (POEG) ........................................................................................... 438
22.1
Overview ............................................................................................................................ 438
22.2
Register Descriptions ......................................................................................................... 440
22.2.1
22.3
23.
POEG Group n Setting Register (POEGGn) (n = A, B) ............................................. 440
Output-Disable Control Operation ..................................................................................... 441
22.3.1
Pin Input Level Detection Operation .......................................................................... 441
22.3.2
Output-Disable Request from GPT ............................................................................ 442
22.3.3
Output-Disable Control on Detection of Stopped Oscillation ..................................... 442
22.3.4
Output-Disable Control Using Registers .................................................................... 442
22.3.5
Release from Output-Disable .................................................................................... 442
22.4
Interrupt Sources ............................................................................................................... 442
22.5
External Trigger Output to GPT ......................................................................................... 443
22.6
Usage Notes ...................................................................................................................... 443
22.6.1
Transition to Software Standby Mode ....................................................................... 443
22.6.2
Specifying Pins Associated with GPT ........................................................................ 443
General PWM Timer (GPT) ......................................................................................................... 444
23.1
Overview ............................................................................................................................ 444
23.2
Register Descriptions ......................................................................................................... 448
23.2.1
General PWM Timer Write-Protection Register (GTWP) .......................................... 449
23.2.2
General PWM Timer Software Start Register (GTSTR) ............................................ 449
23.2.3
General PWM Timer Software Stop Register (GTSTP) ............................................ 450
23.2.4
General PWM Timer Software Clear Register (GTCLR) ........................................... 450
23.2.5
General PWM Timer Start Source Select Register (GTSSR) .................................... 451
23.2.6
General PWM Timer Stop Source Select Register (GTPSR) .................................... 453
23.2.7
General PWM Timer Clear Source Select Register (GTCSR) .................................. 456
23.2.8
General PWM Timer Up Count Source Select Register (GTUPSR) ......................... 458
23.2.9
General PWM Timer Down Count Source Select Register (GTDNSR) ..................... 461
23.2.10
General PWM Timer Input Capture Source Select Register A (GTICASR) .............. 463
23.2.11
General PWM Timer Input Capture Source Select Register B (GTICBSR) .............. 466
23.2.12
General PWM Timer Control Register (GTCR) ......................................................... 468
23.2.13
General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC) ....... 470
23.2.14
General PWM Timer I/O Control Register (GTIOR) .................................................. 472
23.2.15
General PWM Timer Interrupt Output Setting Register (GTINTAD) .......................... 475
23.2.16
General PWM Timer Status Register (GTST) ........................................................... 476
23.2.17
General PWM Timer Buffer Enable Register (GTBER) ............................................. 480
23.2.18
General PWM Timer Counter (GTCNT) .................................................................... 481
23.2.19
General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F) .............. 481
23.2.20
General PWM Timer Cycle Setting Register (GTPR) ................................................ 482
23.2.21
General PWM Timer Cycle Setting Buffer Register (GTPBR) ................................... 482
23.2.22
General PWM Timer Dead Time Control Register (GTDTCR) .................................. 483
23.2.23
General PWM Timer Dead Time Value Register U (GTDVU) ................................... 483
23.2.24
Output Phase Switching Control Register (OPSCR) ................................................. 484
23.3
Operation ........................................................................................................................... 486
23.3.1
Basic Operation ......................................................................................................... 486
23.3.2
Buffer Operation ........................................................................................................ 496
23.3.3
PWM Output Operating Mode ................................................................................... 503
23.3.4
Automatic Dead Time Setting Function ..................................................................... 516
23.3.5
Count Direction Changing Function ........................................................................... 520
23.3.6
Function of Output Duty 0% and 100% ..................................................................... 521
23.3.7
Hardware Count Start/Count Stop and Clear Operation ........................................... 522
23.3.8
Synchronized Operation ............................................................................................ 530
23.3.9
PWM Output Operation Examples ............................................................................ 534
23.3.10
Phase Counting Function .......................................................................................... 540
23.3.11
Output Phase Switching (GPT_OPS) ........................................................................ 550
23.4
Interrupt Sources ............................................................................................................... 557
23.4.1
Interrupt Sources ....................................................................................................... 557
23.4.2
DMAC/DTC Activation ............................................................................................... 561
23.5
Operations Linked by ELC ................................................................................................. 561
23.5.1
Event Signal Output to ELC ....................................................................................... 561
23.5.2
23.6
Noise Filter Function .......................................................................................................... 561
23.7
Protection Function ............................................................................................................ 562
23.7.1
Write-Protection for Registers ................................................................................... 562
23.7.2
Disabling of Buffer Operation .................................................................................... 562
23.7.3
GTIOC Pin Output Negate Control ............................................................................ 563
23.8
Initialization Method of Output Pins ................................................................................... 564
23.8.1
Pin Settings after Reset ............................................................................................. 564
23.8.2
Pin Initialization Due to Error during Operation ......................................................... 564
23.9
24.
Event Signal Inputs from ELC ................................................................................... 561
Usage Notes ...................................................................................................................... 565
23.9.1
Module-Stop Function Setting ................................................................................... 565
23.9.2
Settings of GTCCRn during Compare Match Operation (n = A to F) ........................ 565
23.9.3
Setting the Range for the GTCNT Counter ............................................................... 566
23.9.4
GTCNT Counter Start/Stop ....................................................................................... 566
23.9.5
Priority Order of Each Event ...................................................................................... 566
Asynchronous General Purpose Timer (AGT) ............................................................................. 567
24.1
Overview ............................................................................................................................ 567
24.2
Register Descriptions ......................................................................................................... 569
24.2.1
AGT Counter Register (AGT) .................................................................................... 569
24.2.2
AGT Compare Match A Register (AGTCMA) ............................................................ 569
24.2.3
AGT Compare Match B Register (AGTCMB) ............................................................ 570
24.2.4
AGT Control Register (AGTCR) ................................................................................ 570
24.2.5
AGT Mode Register 1 (AGTMR1) ............................................................................. 572
24.2.6
AGT Mode Register 2 (AGTMR2) ............................................................................. 573
24.2.7
AGT I/O Control Register (AGTIOC) ......................................................................... 574
24.2.8
AGT Event Pin Select Register (AGTISR) ................................................................. 575
24.2.9
AGT Compare Match Function Select Register (AGTCMSR) ................................... 575
24.2.10
AGT Pin Select Register (AGTIOSEL) ...................................................................... 576
24.3
Operation ........................................................................................................................... 577
24.3.1
Reload Register and Counter Rewrite Operation ...................................................... 577
24.3.2
Reload Register and Compare Register A/B Rewrite Operation ............................... 579
24.3.3
Timer Mode ............................................................................................................... 580
24.3.4
Pulse Output Mode .................................................................................................... 581
24.3.5
Event Counter Mode .................................................................................................. 582
24.3.6
Pulse Width Measurement Mode .............................................................................. 583
24.3.7
Pulse Period Measurement Mode ............................................................................. 584
24.3.8
Compare Match Function .......................................................................................... 585
24.3.9
Output Settings for Each Mode ................................................................................. 586
24.3.10
Standby Mode ........................................................................................................... 587
24.3.11
Interrupt Sources ....................................................................................................... 588
24.3.12
Event Signal Output to ELC ....................................................................................... 588
24.4
25.
Usage Notes ...................................................................................................................... 588
24.4.1
Count Operation Start and Stop Control .................................................................... 588
24.4.2
Access to Counter Register ....................................................................................... 589
24.4.3
When Changing Mode ............................................................................................... 589
24.4.4
Digital Filter ................................................................................................................ 589
24.4.5
How to Calculate Event Number, Pulse Width, and Pulse Period ............................. 589
24.4.6
When Count is Forcibly Stopped by TSTOP bit ........................................................ 589
24.4.7
When Selecting AGT0 Underflow as the Count Source ............................................ 590
24.4.8
Reset of I/O Register ................................................................................................. 590
24.4.9
When Selecting PCLKB, PCLKB/8, or PCLKB/2 as the Count Source ..................... 590
24.4.10
When Selecting AGTLCLK or AGTSCLK as the Count Source ................................ 590
Realtime Clock (RTC) .................................................................................................................. 591
25.1
Overview ............................................................................................................................ 591
25.2
Register Descriptions ......................................................................................................... 593
25.2.1
64-Hz Counter (R64CNT) .......................................................................................... 593
25.2.2
Second Counter (RSECCNT)/Binary Counter 0 (BCNT0) ......................................... 594
25.2.3
Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1) ........................................... 595
25.2.4
Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2) ............................................... 596
25.2.5
Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3) .................................. 597
25.2.6
Day Counter (RDAYCNT) .......................................................................................... 598
25.2.7
Month Counter (RMONCNT) ..................................................................................... 598
25.2.8
Year Counter (RYRCNT) ........................................................................................... 599
25.2.9
Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register (BCNT0AR) .. 599
25.2.10
Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR) .... 600
25.2.11
Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register
(BCNT2AR) ............................................................................................................... 601
25.2.12
Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register
(BCNT3AR) ............................................................................................................... 602
25.2.13
Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register
(BCNT0AER) ............................................................................................................. 603
25.2.14
Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register
(BCNT1AER) ............................................................................................................. 604
25.2.15
Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register
(BCNT2AER) ............................................................................................................. 605
25.2.16
Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable Register
(BCNT3AER) ............................................................................................................. 606
25.2.17
RTC Control Register 1 (RCR1) ................................................................................ 607
25.2.18
RTC Control Register 2 (RCR2) ................................................................................ 608
25.2.19
RTC Control Register 4 (RCR4) ................................................................................ 611
25.2.20
Frequency Register (RFRH/RFRL) ........................................................................... 612
25.2.21
Time Error Adjustment Register (RADJ) .................................................................... 613
25.2.22
Time Capture Control Register y (RTCCRy) (y = 0 to 2) ........................................... 613
25.2.23
Second Capture Register y (RSECCPy) (y = 0 to 2)/BCNT0 Capture Register y
(BCNT0CPy) (y = 0 to 2) ........................................................................................... 615
25.2.24
Minute Capture Register y (RMINCPy) (y = 0 to 2)/BCNT1 Capture Register y
(BCNT1CPy) (y = 0 to 2) ........................................................................................... 616
25.2.25
Hour Capture Register y (RHRCPy) (y = 0 to 2)/BCNT2 Capture Register y (BCNT2CPy)
(y = 0 to 2) ................................................................................................................. 617
25.2.26
Date Capture Register y (RDAYCPy) (y = 0 to 2)/BCNT3 Capture Register y
(BCNT3CPy) (y = 0 to 2) ........................................................................................... 618
25.2.27
Month Capture Register y (RMONCPy) (y = 0 to 2) .................................................. 619
25.3
Operation ........................................................................................................................... 619
25.3.1
Outline of Initial Settings of Registers after Power On .............................................. 619
25.3.2
Clock and Count Mode Setting Procedure ................................................................ 620
25.3.3
Setting the Time ........................................................................................................ 621
25.3.4
30-Second Adjustment .............................................................................................. 621
25.3.5
Reading 64-Hz Counter and Time ............................................................................. 622
25.3.6
Alarm Function .......................................................................................................... 623
25.3.7
Procedure for Disabling Alarm Interrupt .................................................................... 624
25.3.8
Time Error Adjustment Function ................................................................................ 624
25.4
Interrupt Sources ............................................................................................................... 627
25.5
Event Link Output .............................................................................................................. 628
25.5.1
25.6
26.
Interrupt Handling and Event Linking ........................................................................ 629
Usage Notes ...................................................................................................................... 630
25.6.1
Register Writing during Counting ............................................................................... 630
25.6.2
Use of Periodic Interrupts .......................................................................................... 630
25.6.3
RTCOUT (1-Hz/64-Hz) Clock Output ........................................................................ 631
25.6.4
Transitions to Low Power Modes after Setting Registers .......................................... 631
25.6.5
Notes on Writing to and Reading from Registers ...................................................... 631
25.6.6
Changing the Count Mode ......................................................................................... 631
25.6.7
Initialization Procedure When the Realtime Clock is not to be Used ......................... 631
Watchdog Timer (WDT) ............................................................................................................... 632
26.1
Overview ............................................................................................................................ 632
26.2
Register Descriptions ......................................................................................................... 633
26.2.1
WDT Refresh Register (WDTRR) .............................................................................. 633
26.2.2
WDT Control Register (WDTCR) ............................................................................... 633
26.2.3
WDT Status Register (WDTSR) ................................................................................ 636
26.2.4
WDT Reset Control Register (WDTRCR) .................................................................. 637
26.2.5
WDT Count Stop Control Register (WDTCSTPR) ..................................................... 637
26.2.6
Option Function Select Register 0 (OFS0) ................................................................ 637
26.3
Operation ........................................................................................................................... 638
26.3.1
Count Operation in Each Start Mode ......................................................................... 638
26.3.2
Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers .............. 642
26.3.3
Refresh Operation ..................................................................................................... 642
26.3.4
Reset Output ............................................................................................................. 643
26.3.5
Interrupt Sources ....................................................................................................... 643
26.3.6
Reading the Down-Counter Value ............................................................................. 644
26.3.7
Association between Option Function Select Register 0 (OFS0)
and WDT Registers ................................................................................................... 644
26.4
Link Operation by ELC ....................................................................................................... 645
26.5
Usage Notes ...................................................................................................................... 645
26.5.1
27.
Independent Watchdog Timer (IWDT) ......................................................................................... 646
27.1
Overview ............................................................................................................................ 646
27.2
Register Descriptions ......................................................................................................... 647
27.2.1
IWDT Refresh Register (IWDTRR) ............................................................................ 647
27.2.2
IWDT Status Register (IWDTSR) .............................................................................. 648
27.2.3
Option Function Select Register 0 (OFS0) ................................................................ 649
27.3
28.
ICU Event Link Setting Register n (IELSRn) Setting ................................................. 645
Operation ........................................................................................................................... 651
27.3.1
Auto-Start Mode ........................................................................................................ 651
27.3.2
Refresh Operation ..................................................................................................... 652
27.3.3
Status Flags ............................................................................................................... 653
27.3.4
Reset Output ............................................................................................................. 654
27.3.5
Interrupt Sources ....................................................................................................... 654
27.3.6
Reading the Down-counter Value .............................................................................. 654
27.4
Output to the ELC .............................................................................................................. 654
27.5
Usage Notes ...................................................................................................................... 655
27.5.1
Refresh Operations ................................................................................................... 655
27.5.2
Clock Division Ratio Setting ...................................................................................... 655
USB 2.0 Full-Speed Module (USBFS) ......................................................................................... 656
28.1
Overview ............................................................................................................................ 656
28.2
Register Descriptions ......................................................................................................... 658
28.2.1
System Configuration Control Register (SYSCFG) ................................................... 658
28.2.2
System Configuration Status Register 0 (SYSSTS0) ................................................ 660
28.2.3
Device State Control Register 0 (DVSTCTR0) .......................................................... 661
28.2.4
CFIFO Port Register (CFIFO/CFIFOL)
D0FIFO Port Register (D0FIFO/D0FIFOL)
D1FIFO Port Register (D1FIFO/D1FIFOL) ................................................................ 663
28.2.5
CFIFO Port Select Register (CFIFOSEL)
D0FIFO Port Select Register (D0FIFOSEL)
D1FIFO Port Select Register (D1FIFOSEL) .............................................................. 665
28.2.6
CFIFO Port Control Register (CFIFOCTR)
D0FIFO Port Control Register (D0FIFOCTR)
D1FIFO Port Control Register (D1FIFOCTR) ............................................................ 669
28.2.7
Interrupt Enable Register 0 (INTENB0) ..................................................................... 671
28.2.8
Interrupt Enable Register 1 (INTENB1) ..................................................................... 672
28.2.9
BRDY Interrupt Enable Register (BRDYENB) ........................................................... 673
28.2.10
NRDY Interrupt Enable Register (NRDYENB) .......................................................... 674
28.2.11
BEMP Interrupt Enable Register (BEMPENB) .......................................................... 675
28.2.12
SOF Output Configuration Register (SOFCFG) ........................................................ 676
28.2.13
Interrupt Status Register 0 (INTSTS0) ....................................................................... 676
28.2.14
Interrupt Status Register 1 (INTSTS1) ....................................................................... 679
28.2.15
BRDY Interrupt Status Register (BRDYSTS) ............................................................ 681
28.2.16
NRDY Interrupt Status Register (NRDYSTS) ............................................................ 682
28.2.17
BEMP Interrupt Status Register (BEMPSTS) ............................................................ 683
28.2.18
Frame Number Register (FRMNUM) ......................................................................... 684
28.2.19
USB Request Type Register (USBREQ) ................................................................... 685
28.2.20
USB Request Value Register (USBVAL) ................................................................... 686
28.2.21
USB Request Index Register (USBINDX) ................................................................. 686
28.2.22
USB Request Length Register (USBLENG) .............................................................. 687
28.2.23
DCP Configuration Register (DCPCFG) .................................................................... 687
28.2.24
DCP Maximum Packet Size Register (DCPMAXP) ................................................... 688
28.2.25
DCP Control Register (DCPCTR) .............................................................................. 689
28.2.26
Pipe Window Select Register (PIPESEL) .................................................................. 692
28.2.27
Pipe Configuration Register (PIPECFG) ................................................................... 693
28.2.28
Pipe Maximum Packet Size Register (PIPEMAXP) ................................................... 695
28.2.29
Pipe Cycle Control Register (PIPEPERI) .................................................................. 696
28.2.30
PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) .................................................... 697
28.2.31
PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 1 to 5) ..................... 703
28.2.32
PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5) ................................. 704
28.2.33
Device Address n Configuration Register (DEVADDn) (n = 0 to 5) ........................... 705
28.2.34
USB Module Control Register (USBMC) ................................................................... 706
28.2.35
BC Control Register 0 (USBBCCTRL0) .................................................................... 706
28.3
Operation ........................................................................................................................... 708
28.3.1
System Control .......................................................................................................... 708
28.3.2
Interrupts ................................................................................................................... 716
28.3.3
Interrupt Descriptions ................................................................................................ 719
28.3.4
Pipe Control ............................................................................................................... 728
28.3.5
FIFO Buffer Memory .................................................................................................. 733
28.3.6
FIFO Buffer Clearing ................................................................................................. 734
28.3.7
FIFO Port Functions .................................................................................................. 734
28.3.8
DMA Transfers (D0FIFO and D1FIFO Ports) ............................................................ 735
28.3.9
Control Transfers Using DCP .................................................................................... 736
28.3.10
Bulk Transfers (Pipes 1 to 5) ..................................................................................... 737
28.3.11
Interrupt Transfers (Pipes 6 to 9) ............................................................................... 738
28.3.12
Isochronous Transfers (Pipes 1 and 2) ..................................................................... 738
28.3.13
SOF Interpolation Function ........................................................................................ 745
28.3.14
Pipe Schedule ........................................................................................................... 746
28.3.15
Battery Charging Detection Processing ..................................................................... 747
28.4
29.
Usage Notes ...................................................................................................................... 751
28.4.1
Settings for the Module-Stop State ............................................................................ 751
28.4.2
Clearing the Interrupt Status Register on Exiting Software Standby Mode ............... 751
28.4.3
Clearing the Interrupt Status Register after Setting Up the Port Function ................. 751
Serial Communications Interface (SCI) ........................................................................................ 752
29.1
Overview ............................................................................................................................ 752
29.2
Register Descriptions ......................................................................................................... 756
29.2.1
Receive Shift Register (RSR) .................................................................................... 756
29.2.2
Receive Data Register (RDR) ................................................................................... 756
29.2.3
Receive 9-bit Data Register (RDRHL) ....................................................................... 756
29.2.4
Receive FIFO Data Register H, L, HL (FRDRH, FRDRL, FRDRHL) ......................... 757
29.2.5
Transmit Data Register (TDR) ................................................................................... 758
29.2.6
Transmit 9-Bit Data Register (TDRHL) ...................................................................... 758
29.2.7
Transmit FIFO Data Register H, L, HL (FTDRH, FTDRL, FTDRHL) ......................... 759
29.2.8
Transmit Shift Register (TSR) ................................................................................... 760
29.2.9
Serial Mode Register (SMR) for Non-Smart Card Interface Mode
(SCMR.SMIF = 0) ...................................................................................................... 760
29.2.10
Serial Mode Register for Smart Card Interface Mode (SMR_SMCI) (SCMR.SMIF = 1)
.................................................................................................................................... 762
29.2.11
Serial Control Register (SCR) for Non-Smart Card Interface Mode
(SCMR.SMIF = 0) ...................................................................................................... 763
29.2.12
Serial Control Register for Smart Card Interface Mode (SCR_SMCI) (SCMR.SMIF = 1)
.................................................................................................................................... 765
29.2.13
Serial Status Register (SSR) for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) ................................................................................ 766
29.2.14
Serial Status Register for Non-Smart Card Interface and FIFO Mode (SSR_FIFO) (SCMR.SMIF = 0 and FCR.FM = 1) ................................................................................ 769
29.2.15
Serial Status Register for Smart Card Interface Mode (SSR_SMCI) (SCMR.SMIF = 1) .
.................................................................................................................................... 772
29.2.16
Smart Card Mode Register (SCMR) .......................................................................... 774
29.2.17
Bit Rate Register (BRR) ............................................................................................ 775
29.2.18
Modulation Duty Register (MDDR) ............................................................................ 783
29.2.19
Serial Extended Mode Register (SEMR) ................................................................... 785
29.2.20
Noise Filter Setting Register (SNFR) ......................................................................... 786
29.2.21
I2C Mode Register 1 (SIMR1) .................................................................................... 787
29.2.22
I2C Mode Register 2 (SIMR2) .................................................................................... 788
29.2.23
I2C Mode Register 3 (SIMR3) .................................................................................... 789
29.2.24
I2C Status Register (SISR) ........................................................................................ 790
29.2.25
SPI Mode Register (SPMR) ....................................................................................... 791
29.2.26
FIFO Control Register (FCR) ..................................................................................... 793
29.2.27
FIFO Data Count Register (FDR) .............................................................................. 794
29.2.28
Line Status Register (LSR) ........................................................................................ 795
29.2.29
Compare Match Data Register (CDR) ....................................................................... 796
29.2.30
Data Compare Match Control Register (DCCR) ........................................................ 796
29.2.31
Serial Port Register (SPTR) ...................................................................................... 798
29.3
Operation in Asynchronous Mode ..................................................................................... 798
29.3.1
Serial Data Transfer Format ...................................................................................... 799
29.3.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ....... 801
29.3.3
Clock ......................................................................................................................... 802
29.3.4
Double-Speed Operation and Frequency of 6 Times the Bit Rate ............................ 802
29.3.5
CTS and RTS Functions ............................................................................................ 802
29.3.6
Address Match (Receive Data Match Detection) Function ........................................ 803
29.3.7
SCI Initialization in Asynchronous Mode ................................................................... 806
29.3.8
Serial Data Transmission in Asynchronous Mode .................................................... 808
29.3.9
Serial Data Reception in Asynchronous Mode .......................................................... 814
29.4
Multi-Processor Communications Function ....................................................................... 821
29.4.1
Multi-Processor Serial Data Transmission ................................................................ 823
29.4.2
Multi-Processor Serial Data Reception ...................................................................... 825
29.5
Operation in Clock Synchronous Mode ............................................................................. 830
29.5.1
Clock .......................................................................................................................... 830
29.5.2
CTS and RTS Functions ............................................................................................ 831
29.5.3
SCI Initialization in Clock Synchronous Mode .......................................................... 832
29.5.4
Serial Data Transmission in Clock Synchronous Mode ............................................. 834
29.5.5
Serial Data Reception in Clock Synchronous Mode .................................................. 837
29.5.6
Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode ....
.................................................................................................................................... 842
29.6
Operation in Smart Card Interface Mode ........................................................................... 844
29.6.1
Example Connection ................................................................................................. 844
29.6.2
Data Format (Except in Block Transfer Mode) .......................................................... 844
29.6.3
Block Transfer Mode ................................................................................................. 845
29.6.4
Receive Data Sampling Timing and Reception Margin ............................................. 847
29.6.5
SCI Initialization ......................................................................................................... 848
29.6.6
Serial Data Transmission (Except in Block Transfer Mode) ...................................... 849
29.6.7
Serial Data Reception (Except in Block Transfer Mode) .......................................... 851
29.6.8
Clock Output Control ................................................................................................. 853
29.7
Operation in Simple IIC Mode ............................................................................................ 854
29.7.1
Generation of Start, Restart, and Stop Conditions .................................................... 855
29.7.2
Clock Synchronization ............................................................................................... 856
29.7.3
SDA Output Delay .................................................................................................... 857
29.7.4
SCI Initialization in Simple IIC Mode ......................................................................... 858
29.7.5
Operation in Master Transmission in Simple IIC Mode ............................................ 859
29.7.6
Master Reception in Simple IIC Mode ...................................................................... 861
29.8
Operation in Simple SPI Mode ......................................................................................... 863
29.8.1
States of Pins in Master and Slave Modes ................................................................ 864
29.8.2
SS Function in Master Mode ..................................................................................... 864
29.8.3
SS Function in Slave Mode ....................................................................................... 864
29.8.4
Relationship between Clock and Transmit/Receive Data .......................................... 865
29.8.5
SCI Initialization in Simple SPI Mode ........................................................................ 865
29.8.6
Transmission and Reception of Serial Data in Simple SPI Mode .............................. 865
29.9
Bit Rate Modulation Function ............................................................................................. 866
29.10
Interrupt Sources ............................................................................................................... 866
29.10.1
Buffer Operations for SCIn_TXI and SCIn_RXI Interrupts (non-FIFO selected) ....... 866
29.10.2
Buffer Operation for SCIn_TXI and SCIn_RXI Interrupts (FIFO selected) ................ 866
29.10.3
Interrupts in Asynchronous, Clock Synchronous, and Simple SPI Modes ................ 867
29.10.4
Interrupts in Smart Card Interface Mode ................................................................... 868
29.10.5
Interrupts in Simple IIC Mode .................................................................................... 869
29.11
Event Linking ..................................................................................................................... 869
29.12
Address Mismatch Event Output (SCI0_DCUF) ................................................................ 870
29.13
Noise Cancellation Function .............................................................................................. 871
29.14
Usage Notes ...................................................................................................................... 872
29.14.1
Settings for the Module-Stop Function ...................................................................... 872
29.14.2
SCI Operations during Low Power State ................................................................... 872
29.14.3
Break Detection and Processing ............................................................................... 876
29.14.4
Mark State and Production of Breaks ........................................................................ 876
29.14.5
Receive Error Flags and Transmit Operation in Clock Synchronous Mode and Simple
SPI Mode ................................................................................................................... 876
29.14.6
Restrictions on Clock Synchronous Transmission in Clock Synchronous Mode and Simple SPI Mode ............................................................................................................. 876
29.14.7
Restrictions on Using DMAC or DTC ........................................................................ 877
29.14.8
Notes on Starting Transfer ........................................................................................ 878
29.14.9
External Clock Input in Clock Synchronous Mode and Simple SPI Mode ................. 878
29.14.10 Limitations to Simple SPI Mode ................................................................................. 878
30.
I2C Bus Interface (IIC) .................................................................................................................. 880
30.1
Overview ............................................................................................................................ 880
30.2
Register Descriptions ......................................................................................................... 883
30.2.1
I2C Bus Control Register 1 (ICCR1) .......................................................................... 883
30.2.2
I2C Bus Control Register 2 (ICCR2) .......................................................................... 885
30.2.3
I2C Bus Mode Register 1 (ICMR1) ............................................................................ 888
30.2.4
I2C Bus Mode Register 2 (ICMR2) ............................................................................ 889
30.2.5
I2C Bus Mode Register 3 (ICMR3) ............................................................................ 890
30.2.6
I2C Bus Function Enable Register (ICFER) ............................................................... 892
30.2.7
I2C Bus Status Enable Register (ICSER) .................................................................. 894
30.2.8
I2C Bus Interrupt Enable Register (ICIER) ................................................................ 895
30.2.9
I2C Bus Status Register 1 (ICSR1) ............................................................................ 896
30.2.10
I2C Bus Status Register 2 (ICSR2) ............................................................................ 898
30.2.11
I2C Bus Wakeup Unit Register (ICWUR) ................................................................... 902
30.2.12
I2C Bus Wakeup Unit Register 2 (ICWUR2) .............................................................. 903
30.2.13
Slave Address Register Ly (SARLy) (y = 0 to 2) ....................................................... 904
30.2.14
Slave Address Register Uy (SARUy) (y = 0 to 2) ...................................................... 905
30.2.15
I2C Bus Bit Rate Low-Level Register (ICBRL) ........................................................... 905
30.2.16
I2C Bus Bit Rate High-Level Register (ICBRH) ......................................................... 906
30.2.17
I2C Bus Transmit Data Register (ICDRT) .................................................................. 907
30.2.18
I2C Bus Receive Data Register (ICDRR) .................................................................. 907
30.2.19
I2C Bus Shift Register (ICDRS) ................................................................................. 907
30.3
Operation ........................................................................................................................... 908
30.3.1
Communication Data Format ..................................................................................... 908
30.3.2
Initial Settings ............................................................................................................ 909
30.3.3
Master Transmit Operation ........................................................................................ 910
30.3.4
Master Receive Operation ......................................................................................... 914
30.3.5
Slave Transmit Operation .......................................................................................... 918
30.3.6
Slave Receive Operation ........................................................................................... 921
30.4
SCL Synchronization Circuit .............................................................................................. 923
30.5
SDA Output Delay Function ............................................................................................... 924
30.6
Digital Noise Filter Circuits ................................................................................................. 925
30.7
Address Match Detection ................................................................................................... 926
30.7.1
Slave-Address Match Detection ................................................................................ 926
30.7.2
Detection of General Call Address ............................................................................ 928
30.7.3
Device ID Address Detection ..................................................................................... 928
30.7.4
Host Address Detection ............................................................................................. 930
30.8
Wakeup Function ............................................................................................................... 930
30.8.1
Normal Wakeup Mode 1 ............................................................................................ 931
30.8.2
Normal Wakeup Mode 2 ............................................................................................ 934
30.8.3
Command Recovery Mode and EEP Response Mode (Special Wakeup Modes) .... 936
30.8.4
Precautions for WFI Instruction Execution ................................................................ 939
30.9
Automatic Low-Hold Function for SCL ............................................................................... 940
30.9.1
Function to Prevent Wrong Transmission of Transmit Data ...................................... 940
30.9.2
NACK Reception Transfer Suspension Function ...................................................... 940
30.9.3
Function to Prevent Failure to Receive Data ............................................................. 941
30.10
Arbitration-Lost Detection Functions .................................................................................. 943
30.10.1
Master Arbitration-Lost Detection (MALE Bit) ............................................................ 943
30.10.2
Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) ......... 945
30.10.3
Slave Arbitration-Lost Detection (SALE Bit) .............................................................. 946
30.11
Start, Restart, and Stop Condition Issuing Function .......................................................... 946
30.11.1
Issuing a Start Condition ........................................................................................... 946
30.11.2
Issuing a Restart Condition ....................................................................................... 947
30.11.3
Issuing a Stop Condition ............................................................................................ 949
30.12
Bus Hanging ...................................................................................................................... 949
30.12.1
Timeout Function ....................................................................................................... 950
30.12.2
Extra SCL Clock Cycle Output Function .................................................................... 951
30.12.3
IIC Reset and Internal Reset ..................................................................................... 951
30.13
SMBus Operation .............................................................................................................. 952
30.13.1
SMBus Timeout Measurement .................................................................................. 952
30.13.2
Packet Error Code (PEC) .......................................................................................... 953
30.13.3
SMBus Host Notification Protocol (Notify ARP Master Command) ........................... 953
30.14
Interrupt Sources ............................................................................................................... 954
30.14.1
30.15
Register States When Issuing Each Condition .................................................................. 955
30.16
Output to the Event Link Controller (ELC) ......................................................................... 956
30.16.1
30.17
31.
Buffer Operation for IICn_TXI and IICn_RXI Interrupts ............................................. 954
Interrupt Handling and Event Linking ........................................................................ 956
Usage Notes ...................................................................................................................... 956
30.17.1
Settings for the Module-Stop Function ...................................................................... 956
30.17.2
Notes on Starting Transfer ........................................................................................ 956
Controller Area Network (CAN) Module ....................................................................................... 957
31.1
Overview ............................................................................................................................ 957
31.2
Register Descriptions ......................................................................................................... 959
31.2.1
Control Register (CTLR) ............................................................................................ 959
31.2.2
Bit Configuration Register (BCR) ............................................................................... 962
31.2.3
Mask Register k (MKRk) (k = 0 to 7) ......................................................................... 964
31.2.4
FIFO Received ID Compare Registers 0 and 1 (FIDCR0 and FIDCR1) ................... 965
31.2.5
Mask Invalid Register (MKIVLR) ............................................................................... 966
31.2.6
Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31, m = 0 to 7) .... 966
31.2.7
Mailbox Interrupt Enable Register (MIER) ................................................................. 970
31.2.8
Mailbox Interrupt Enable Register for FIFO Mailbox Mode (MIER_FIFO) ................. 971
31.2.9
Message Control Registers for Transmit (MCTL_TXj) (j = 0 to 31) ........................... 972
31.2.10
Message Control Register for Receive (MCTL_RXj) (j = 0 to 31) .............................. 974
31.2.11
Receive FIFO Control Register (RFCR) .................................................................... 976
31.2.12
Receive FIFO Pointer Control Register (RFPCR) ..................................................... 978
31.2.13
Transmit FIFO Control Register (TFCR) .................................................................... 978
31.2.14
Transmit FIFO Pointer Control Register (TFPCR) ..................................................... 980
31.2.15
Status Register (STR) ................................................................................................ 981
31.2.16
Mailbox Search Mode Register (MSMR) ................................................................... 983
31.2.17
Mailbox Search Status Register (MSSR) ................................................................... 983
31.2.18
Channel Search Support Register (CSSR) ............................................................... 984
31.2.19
Acceptance Filter Support Register (AFSR) .............................................................. 986
31.2.20
Error Interrupt Enable Register (EIER) ...................................................................... 987
31.2.21
Error Interrupt Factor Judge Register (EIFR) ............................................................ 988
31.2.22
Receive Error Count Register (RECR) ...................................................................... 990
31.2.23
Transmit Error Count Register (TECR) ...................................................................... 990
31.2.24
Error Code Store Register (ECSR) ............................................................................ 990
31.2.25
Time Stamp Register (TSR) ....................................................................................... 992
31.2.26
Test Control Register (TCR) ...................................................................................... 992
31.3
31.3.1
CAN Reset Mode ....................................................................................................... 995
31.3.2
CAN Halt Mode .......................................................................................................... 996
31.3.3
CAN Sleep Mode ....................................................................................................... 996
31.3.4
CAN Operation Mode (Excluding Bus-Off State) ....................................................... 997
31.3.5
CAN Operation Mode (Bus-Off State) ....................................................................... 998
31.4
32.
Modes of Operation ........................................................................................................... 994
Data Transfer Rate Configuration ...................................................................................... 999
31.4.1
Clock Setting ............................................................................................................. 999
31.4.2
Bit Timing Setting ...................................................................................................... 999
31.4.3
Data Transfer Rate .................................................................................................. 1000
31.5
Mailbox and Mask Register Structure .............................................................................. 1001
31.6
Acceptance Filtering and Masking Functions .................................................................. 1002
31.7
Reception and Transmission ........................................................................................... 1004
31.7.1
Reception ................................................................................................................ 1005
31.7.2
Transmission ........................................................................................................... 1007
31.8
Interrupts .......................................................................................................................... 1008
31.9
Usage Notes .................................................................................................................... 1009
31.9.1
Settings for the Module-Stop Function .................................................................... 1009
31.9.2
Settings for the Operating Clock .............................................................................. 1009
Serial Peripheral Interface (SPI) ................................................................................................ 1010
32.1
Overview .......................................................................................................................... 1010
32.2
Register Descriptions ....................................................................................................... 1013
32.2.1
SPI Control Register (SPCR) .................................................................................. 1013
32.2.2
SPI Slave Select Polarity Register (SSLP) .............................................................. 1015
32.2.3
SPI Pin Control Register (SPPCR) .......................................................................... 1015
32.2.4
SPI Status Register (SPSR) .................................................................................... 1016
32.2.5
SPI Data Register (SPDR/SPDR_HA) .................................................................... 1019
32.2.6
SPI Sequence Control Register (SPSCR) ............................................................... 1022
32.2.7
SPI Sequence Status Register (SPSSR) ................................................................. 1023
32.2.8
SPI Bit Rate Register (SPBR) ................................................................................. 1024
32.2.9
SPI Data Control Register (SPDCR) ....................................................................... 1025
32.2.10
SPI Clock Delay Register (SPCKD) ........................................................................ 1027
32.2.11
SPI Slave Select Negation Delay Register (SSLND) .............................................. 1027
32.2.12
SPI Next-Access Delay Register (SPND) ................................................................ 1028
32.2.13
SPI Control Register 2 (SPCR2) ............................................................................. 1028
32.2.14
SPI Command Registers (SPCMDm) (m =0 to 7 for SPI0; m = 0 for SPI1) ............ 1030
32.3
Operation ......................................................................................................................... 1033
32.3.1
Overview of SPI Operations .................................................................................... 1033
32.3.2
Controlling SPI Pins ................................................................................................. 1034
32.3.3
SPI System Configuration Examples ....................................................................... 1035
32.3.4
Data Format ............................................................................................................. 1041
32.3.5
Transfer Formats ..................................................................................................... 1050
32.3.6
Data Transfer Modes ............................................................................................... 1052
32.3.7
Transmit Buffer Empty and Receive Buffer Full Interrupts ...................................... 1054
32.3.8
Error Detection ........................................................................................................ 1056
32.3.9
Initializing the SPI .................................................................................................... 1060
32.3.10
SPI Operation .......................................................................................................... 1061
32.3.11
Clock Synchronous Operation ................................................................................. 1076
32.3.12
Loopback Mode ....................................................................................................... 1082
32.3.13
Self-Diagnosis of Parity Bit Function ....................................................................... 1083
32.3.14
Interrupt Sources ..................................................................................................... 1084
32.4
32.4.1
Receive Buffer Full Event Output ............................................................................ 1085
32.4.2
Transmit Buffer Empty Event Output ....................................................................... 1085
32.4.3
Mode-Fault, Underrun, Overrun, or Parity Error Event Output ................................ 1085
32.4.4
SPI Idle Event Output .............................................................................................. 1085
32.4.5
Transmission-Completed Event Output ................................................................... 1086
32.5
33.
Event Link Controller (ELC) Event Output ....................................................................... 1085
Usage Notes .................................................................................................................... 1086
32.5.1
Settings for the Module-Stop Function .................................................................... 1086
32.5.2
Restriction on Low Power Function ......................................................................... 1086
32.5.3
Restrictions on Starting Transfer ............................................................................. 1086
32.5.4
Restrictions on Mode-Fault, Underrun, Overrun or Parity Error Event Output ........ 1086
32.5.5
Restrictions on SPRF/SPTEF Flags ........................................................................ 1086
Quad Serial Peripheral Interface (QSPI) .................................................................................... 1087
33.1
Overview .......................................................................................................................... 1087
33.2
Register Descriptions ....................................................................................................... 1088
33.2.1
Transfer Mode Control Register (SFMSMD) ........................................................... 1088
33.2.2
Chip Selection Control Register (SFMSSC) ............................................................ 1089
33.2.3
Clock Control Register (SFMSKC) .......................................................................... 1090
33.2.4
Status Register (SFMSST) ...................................................................................... 1091
33.2.5
Communication Port Register (SFMCOM) .............................................................. 1092
33.2.6
Communication Mode Control Register (SFMCMD) ............................................... 1092
33.2.7
Communication Status Register (SFMCST) ............................................................ 1093
33.2.8
Instruction Code Register (SFMSIC) ....................................................................... 1093
33.2.9
Address Mode Control Register (SFMSAC) ............................................................ 1094
33.2.10
Dummy Cycle Control Register (SFMSDC) ............................................................. 1095
33.2.11
SPI Protocol Control Register (SFMSPC) ............................................................... 1096
33.2.12
Port Control Register (SFMPMD) ............................................................................ 1096
33.2.13
External QSPI Address Register (SFMCNT1) ......................................................... 1097
33.3
Memory Map .................................................................................................................... 1097
33.3.1
Internal Bus Space .................................................................................................. 1097
33.3.2
Address Width of the SPI Space and SPI Bus ........................................................ 1098
33.4
SPI Bus ............................................................................................................................ 1099
33.4.1
SPI Protocol ............................................................................................................. 1099
33.4.2
SPI Mode ................................................................................................................. 1101
33.5
SPI Bus Timing Adjustment ............................................................................................. 1102
33.5.1
SPI Bus Reference Cycles ...................................................................................... 1102
33.5.2
QSPCLK Signal Duty Ratio ..................................................................................... 1103
33.5.3
Minimum High-Level Width of QSSL Signal ............................................................ 1103
33.5.4
QSSL Signal Setup Time ......................................................................................... 1104
33.5.5
QSSL Signal Hold Time ........................................................................................... 1104
33.5.6
Hold Time of the Serial Data Output Enable ........................................................... 1105
33.5.7
Setup Time of Serial Data Output ............................................................................ 1105
33.5.8
Hold Time for Serial Data Output ............................................................................ 1106
33.5.9
Serial Data Receiving Latency ................................................................................ 1106
33.6
SPI Instruction Set Used for Flash Access ...................................................................... 1107
33.6.1
Types of SPI Instructions that are Automatically Generated ................................... 1107
33.6.2
Standard Read Instruction ....................................................................................... 1108
33.6.3
Fast Read Instruction .............................................................................................. 1109
33.6.4
Fast Read Dual Output Instruction .......................................................................... 1110
33.6.5
Fast Read Dual I/O Instruction ................................................................................ 1111
33.6.6
Fast Read Quad Output Instruction ......................................................................... 1112
33.6.7
Fast Read Quad I/O Instruction ............................................................................... 1113
33.6.8
Enter 4-byte Mode Instruction ................................................................................. 1114
33.6.9
Exit 4-byte Mode Instruction .................................................................................... 1114
33.6.10
Write Enable Instruction .......................................................................................... 1114
33.7
SPI Bus Cycle Arrangement ............................................................................................ 1115
33.7.1
Flash Read Based on Individual Conversion ........................................................... 1115
33.7.2
Flash Read Using Prefetch Function ....................................................................... 1115
33.7.3
Halt of Prefetching ................................................................................................... 1116
33.7.4
Direct Specification of Prefetch Destination ............................................................ 1116
33.7.5
Prefetch State Polling .............................................................................................. 1116
33.7.6
Flash Read Using the SPI Bus Cycle Extension Function ...................................... 1117
33.8
XIP Control ...................................................................................................................... 1117
33.8.1
Setting the XIP Mode ............................................................................................... 1118
33.8.2
Releasing the XIP Mode .......................................................................................... 1118
33.9
QIO2 and QIO3 Pin States .............................................................................................. 1118
33.10
Direct Communication Mode ........................................................................................... 1119
33.10.1
About Direct Communication ................................................................................... 1119
33.10.2
Using Direct Communication Mode ......................................................................... 1119
33.10.3
Generating the SPI Bus Cycle during Direct Communication ................................. 1119
33.11
Operation ......................................................................................................................... 1121
33.11.1
33.12
Interrupt ........................................................................................................................... 1121
33.13
Usage Note ...................................................................................................................... 1121
33.13.1
34.
Setting for the Module-Stop State ........................................................................... 1121
Cyclic Redundancy Check (CRC) Calculator ............................................................................. 1122
34.1
Overview .......................................................................................................................... 1122
34.2
Register Descriptions ....................................................................................................... 1123
34.2.1
CRC Control Register 0 (CRCCR0) ........................................................................ 1123
34.2.2
CRC Control Register 1 (CRCCR1) ........................................................................ 1124
34.2.3
CRC Data Input Register (CRCDIR/CRCDIR_BY) .................................................. 1124
34.2.4
CRC Data Output Register (CRCDOR/CRCDOR_HA/CRCDOR_BY) ................... 1125
34.2.5
Snoop Address Register (CRCSAR) ....................................................................... 1125
34.3
Operation ......................................................................................................................... 1126
34.3.1
Basic Operation ....................................................................................................... 1126
34.3.2
CRC Snoop ............................................................................................................. 1128
34.4
35.
Procedure for Modifying Settings in Multiple Control Registers .............................. 1121
Usage Notes .................................................................................................................... 1128
34.4.1
Settings for the Module-Stop State .......................................................................... 1128
34.4.2
Notes on Transmission ............................................................................................ 1128
Serial Sound Interface Enhanced (SSIE) ................................................................................... 1129
35.1
Overview .......................................................................................................................... 1129
35.2
SSIE Specifications ......................................................................................................... 1129
35.3
Register Descriptions ....................................................................................................... 1133
35.3.1
Control Register (SSICR) ........................................................................................ 1133
35.3.2
Status Register (SSISR) .......................................................................................... 1141
35.3.3
FIFO Control Register (SSIFCR) ............................................................................. 1151
35.3.4
FIFO Status Register (SSIFSR) ............................................................................... 1157
35.3.5
Transmit FIFO Data Register (SSIFTDR) ................................................................ 1160
35.3.6
Receive FIFO Data Register (SSIFRDR) ................................................................ 1162
35.3.7
TDM Mode Register (SSITDMR) ............................................................................. 1163
35.3.8
Status Control Register (SSISCR) ........................................................................... 1167
35.4
Communication Formats .................................................................................................. 1168
35.4.1
I2S Format ............................................................................................................... 1169
35.4.2
Monaural Format ..................................................................................................... 1169
35.5
Communication Modes .................................................................................................... 1171
35.5.1
Slave Mode Communication .................................................................................... 1171
35.5.2
Master Mode Communication .................................................................................. 1171
35.5.3
Transmission ........................................................................................................... 1171
35.5.4
Reception ................................................................................................................ 1172
35.5.5
Transmission and Reception ................................................................................... 1172
35.6
Operation ......................................................................................................................... 1172
35.6.1
Idle State ................................................................................................................. 1172
35.6.2
Communication States ............................................................................................ 1174
35.7
Communication Operation ............................................................................................... 1177
35.7.1
Start Communication ............................................................................................... 1178
35.7.2
Transmission ........................................................................................................... 1179
35.7.3
Reception ................................................................................................................ 1180
35.7.4
Transmission and Reception ................................................................................... 1180
35.7.5
Halt Communication ................................................................................................ 1181
35.7.6
Error Handling ......................................................................................................... 1182
35.7.7
Resume Communication ......................................................................................... 1183
35.8
Interrupts .......................................................................................................................... 1184
35.8.1
SSIE0_SSIF Interrupt .............................................................................................. 1184
35.8.2
SSIE0_SSITXI Interrupt (Full-duplex communication) ............................................ 1185
35.8.3
SSIE0_SSIRXI Interrupt (Full-duplex communication) ............................................ 1185
35.9
Software Resets .............................................................................................................. 1186
35.9.1
35.10
36.
Software Reset Procedure ...................................................................................... 1186
Notes ............................................................................................................................... 1187
35.10.1
Notes on Slave Mode Communication .................................................................... 1187
35.10.2
Notes on Master Mode Communication .................................................................. 1187
35.10.3
Notes on Communication Flow ................................................................................ 1188
35.10.4
Write Access Restriction .......................................................................................... 1189
SD/MMC Host Interface (SDHI) ................................................................................................. 1191
36.1
Overview .......................................................................................................................... 1191
36.2
Register Descriptions ....................................................................................................... 1192
36.2.1
Command Type Register (SD_CMD) ...................................................................... 1192
36.2.2
SD Command Argument Register (SD_ARG) ......................................................... 1193
36.2.3
SD Command Argument Register 1 (SD_ARG1) .................................................... 1194
36.2.4
Data Stop Register (SD_STOP) .............................................................................. 1194
36.2.5
Block Count Register (SD_SECCNT) ...................................................................... 1195
36.2.6
SD Card Response Register 10 (SD_RSP10),
SD Card Response Register 32 (SD_RSP32),
SD Card Response Register 54 (SD_RSP54) ........................................................ 1196
36.2.7
SD Card Response Register 1 (SD_RSP1),
SD Card Response Register 3 (SD_RSP3),
SD Card Response Register 5 (SD_RSP5) ............................................................ 1196
36.2.8
SD Card Response Register 76 (SD_RSP76) ........................................................ 1196
36.2.9
SD Card Response Register 7 (SD_RSP7) ............................................................ 1197
36.2.10
SD Card Interrupt Flag Register 1 (SD_INFO1) ...................................................... 1198
36.2.11
SD Card Interrupt Flag Register 2 (SD_INFO2) ...................................................... 1201
36.2.12
SD INFO1 Interrupt Mask Register (SD_INFO1_MASK) ........................................ 1205
36.2.13
SD INFO2 Interrupt Mask Register (SD_INFO2_MASK) ........................................ 1206
36.2.14
SD Clock Control Register (SD_CLK_CTRL) .......................................................... 1207
36.2.15
Transfer Data Length Register (SD_SIZE) .............................................................. 1208
36.2.16
SD Card Access Control Option Register (SD_OPTION) ....................................... 1208
36.2.17
SD Error Status Register 1 (SD_ERR_STS1) ......................................................... 1209
36.2.18
SD Error Status Register 2 (SD_ERR_STS2) ......................................................... 1211
36.2.19
SD Buffer Register (SD_BUF0) ............................................................................... 1212
36.2.20
SDIO Mode Control Register (SDIO_MODE) .......................................................... 1212
36.2.21
SDIO Interrupt Flag Register (SDIO_INFO1) .......................................................... 1214
36.2.22
SDIO INFO1 Interrupt Mask Register (SDIO_INFO1_MASK) ................................. 1215
36.2.23
DMA Mode Enable Register (SD_DMAEN) ............................................................. 1215
36.2.24
Software Reset Register (SOFT_RST) ................................................................... 1216
36.2.25
SD Interface Mode Setting Register (SDIF_MODE) ................................................ 1217
36.2.26
Swap Control Register (EXT_SWAP) ...................................................................... 1217
36.3
36.3.1
SD/MMC Interface ................................................................................................... 1218
36.3.2
Card Detect/Write Protect ........................................................................................ 1220
36.3.3
Interrupt Request and DMA Transfer Request ........................................................ 1221
36.3.4
Communication Errors and Timeouts ...................................................................... 1223
36.3.5
Command without Data Transfer (SD/MMC) ........................................................... 1224
36.3.6
Single Block Read (SD/MMC) ................................................................................. 1226
36.3.7
Single Block Write (SD/MMC) ................................................................................. 1228
36.3.8
Multiple Block Read (SD/MMC) ............................................................................... 1230
36.3.9
Multiple Block Write (SD/MMC Using Internal Timer) .............................................. 1232
36.3.10
Multiple Block Write (MMC using external timer) ..................................................... 1234
36.3.11
IO_RW_DIRECT Command (SD: CMD52) ............................................................. 1236
36.3.12
IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Read) ...................... 1237
36.3.13
IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Write) ...................... 1239
36.3.14
DMA Transfer (SD/MMC) ........................................................................................ 1241
36.3.15
Example of SD_CMD Register Setting .................................................................... 1242
36.4
37.
Operation ......................................................................................................................... 1218
Usage Notes .................................................................................................................... 1245
36.4.1
SD_BUF Illegal Write Access (SD/MMC) ................................................................ 1245
36.4.2
Block Number Constraint for Multiple Block Read (SD) .......................................... 1245
36.4.3
Automatic Control of SD/MMC Clock Output (SD/MMC) ......................................... 1245
36.4.4
Control of the C52PUB Setting for Multiple Block Write (SD) .................................. 1246
36.4.5
Notes on SD_CLK_CTRL Register Settings (SD/MMC) ......................................... 1246
36.4.6
Specification Limitations .......................................................................................... 1246
36.4.7
STP Bit Setting during Multiple Block Read (SD/MMC) .......................................... 1246
36.4.8
Register Setting Notes ............................................................................................. 1246
Boundary Scan .......................................................................................................................... 1247
37.1
Overview .......................................................................................................................... 1247
37.2
Register Descriptions ....................................................................................................... 1248
37.2.1
Instruction Register (JTIR) ....................................................................................... 1248
37.2.2
ID Code Register (JTIDR) ....................................................................................... 1249
37.2.3
Bypass Register (JTBPR) ........................................................................................ 1249
37.2.4
Boundary Scan Register (JTBSR) ........................................................................... 1249
37.3
37.3.1
TAP Controller ......................................................................................................... 1250
37.3.2
Commands .............................................................................................................. 1250
37.4
38.
Operations ....................................................................................................................... 1250
Usage Notes .................................................................................................................... 1251
14-Bit A/D Converter (ADC14) ................................................................................................... 1252
38.1
Overview .......................................................................................................................... 1252
38.2
Register Descriptions ....................................................................................................... 1255
38.2.1
A/D Data Registers y (ADDRy), A/D Data Duplexing Register (ADDBLDR),
A/D Data Duplexing Register A (ADDBLDRA), A/D Data Duplexing Register B
(ADDBLDRB), A/D Temperature Sensor Data Register (ADTSDR),
A/D Internal Reference Voltage Data Register (ADOCDR) ..................................... 1255
38.2.2
A/D Self-Diagnosis Data Register (ADRD) .............................................................. 1259
38.2.3
A/D Control Register (ADCSR) ................................................................................ 1261
38.2.4
A/D Channel Select Register A0 (ADANSA0) ......................................................... 1264
38.2.5
A/D Channel Select Register A1 (ADANSA1) ......................................................... 1265
38.2.6
A/D Channel Select Register B0 (ADANSB0) ......................................................... 1265
38.2.7
A/D Channel Select Register B1 (ADANSB1) ......................................................... 1266
38.2.8
A/D-Converted Value Addition/Average Channel Select Register 0 (ADADS0) ...... 1266
38.2.9
A/D-Converted Value Addition/Average Channel Select Register 1 (ADADS1) ...... 1267
38.2.10
A/D-Converted Value Addition/Average Count Select Register (ADADC) ............... 1268
38.2.11
A/D Control Extended Register (ADCER) ............................................................... 1269
38.2.12
A/D Conversion Start Trigger Select Register (ADSTRGR) .................................... 1270
38.2.13
A/D Conversion Extended Input Control Register (ADEXICR) ................................ 1271
38.2.14
A/D Sampling State Register n (ADSSTRn) (n = 00 to 15, L, T, O) ........................ 1273
38.2.15
A/D Disconnection Detection Control Register (ADDISCR) .................................... 1274
38.2.16
A/D Group Scan Priority Control Register (ADGSPCR) .......................................... 1275
38.2.17
A/D Compare Function Control Register (ADCMPCR) ........................................... 1276
38.2.18
A/D Compare Function Window A Channel Select Register 0 (ADCMPANSR0) .... 1277
38.2.19
A/D Compare Function Window A Channel Select Register 1 (ADCMPANSR1) .... 1278
38.2.20
A/D Compare Function Window A Extended Input Select Register (ADCMPANSER) ....
.................................................................................................................................. 1278
38.2.21
A/D Compare Function Window A Comparison Condition Setting Register 0 (ADCMPLR0) ...................................................................................................................... 1279
38.2.22
A/D Compare Function Window A Comparison Condition Setting Register 1 (ADCMPLR1) ...................................................................................................................... 1280
38.2.23
A/D Compare Function Window A Extended Input Comparison Condition Setting Register (ADCMPLER) ..................................................................................................... 1280
38.2.24
A/D Compare Function Window A Lower-Side Level Setting Register (ADCMPDR0), A/D
Compare Function Window A Upper-Side Level Setting Register (ADCMPDR1), A/D
Compare Function Window B Lower-Side Level Setting Register (ADWINLLB), A/D
Compare Function Window B Upper-Side Level Setting Register (ADWINULB) .... 1281
38.2.25
A/D Compare Function Window A Channel Status Register 0 (ADCMPSR0) ......... 1283
38.2.26
A/D Compare Function Window A Channel Status Register1 (ADCMPSR1) .......... 1283
38.2.27
A/D Compare Function Window A Extended Input Channel Status Register (ADCMPSER) .......................................................................................................................... 1284
38.2.28
A/D Compare Function Window B Channel Select Register (ADCMPBNSR) ......... 1285
38.2.29
A/D Compare Function Window B Status Register (ADCMPBSR) .......................... 1286
38.2.30
A/D Compare Function Window A/B Status Monitor Register (ADWINMON) ......... 1287
38.2.31
A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT)
.................................................................................................................................. 1288
38.3
Operation ......................................................................................................................... 1289
38.3.1
Scanning Operation ................................................................................................. 1289
38.3.2
Single Scan Mode ................................................................................................... 1290
38.3.3
Continuous Scan Mode ........................................................................................... 1294
38.3.4
Group Scan Mode ................................................................................................... 1296
38.3.5
Compare Function for Window A and Window B .................................................... 1305
38.3.6
Analog Input Sampling and Scan Conversion Time ................................................ 1309
38.3.7
Usage Example of A/D Data Register Automatic Clearing Function ....................... 1311
38.3.8
A/D-Converted Value Addition/Average Mode ........................................................ 1311
38.3.9
Disconnection Detection Assist Function ................................................................ 1312
38.3.10
Starting A/D Conversion with an Asynchronous Trigger ......................................... 1313
38.3.11
Starting A/D Conversion with a Synchronous Trigger from Peripheral Module ....... 1314
38.4
Interrupt Sources and DTC or DMAC Transfer Requests ............................................... 1314
38.4.1
38.5
Interrupt Requests ................................................................................................... 1314
Event Link Function ......................................................................................................... 1315
38.5.1
Event Output to the ELC .......................................................................................... 1315
38.5.2
ADC14 Operation through an Event from the ELC .................................................. 1315
38.6
Selecting Reference Voltage ........................................................................................... 1315
38.7
A/D Conversion Procedure when Selecting Internal Reference Voltage as High-Potential Reference Voltage ................................................................................................................. 1315
38.8
Usage Notes .................................................................................................................... 1316
38.8.1
Notes on Reading Data Registers ........................................................................... 1316
38.8.2
Notes on Stopping A/D Conversion ......................................................................... 1316
38.8.3
A/D Conversion Restarting Timing and Termination Timing ................................... 1317
38.8.4
Restrictions on Scan End Interrupt Handling ........................................................... 1317
38.8.5
Module-Stop Function Settings ............................................................................... 1317
38.8.6
Restrictions on Entering Low-Power States ............................................................ 1318
38.8.7
Error in Absolute Accuracy when Disconnection Detection Assistance is in Use ... 1318
38.8.8
ADHSC Bit Rewriting Procedure ............................................................................. 1318
38.8.9
Notes on Operating Modes and Status Bits ............................................................ 1318
38.8.10
Notes on Board Design ........................................................................................... 1318
38.8.11
Notes on Noise Reduction ....................................................................................... 1318
38.8.12
Port Settings when Using the 14-bit A/D Converter Input ....................................... 1319
39.
38.8.13
Relationship between ADC14, OPAMP, and ACMPLP ........................................... 1319
38.8.14
Notes on Canceling Software Standby Mode .......................................................... 1319
12-Bit D/A Converter (DAC12) ................................................................................................... 1320
39.1
Overview .......................................................................................................................... 1320
39.2
Register Descriptions ....................................................................................................... 1321
39.2.1
D/A Data Register 0 (DADR0) ................................................................................. 1321
39.2.2
D/A Control Register (DACR) .................................................................................. 1321
39.2.3
DADR0 Format Select Register (DADPR) ............................................................... 1322
39.2.4
D/A A/D Synchronous Start Control Register (DAADSCR) ..................................... 1322
39.2.5
D/A VREF Control Register (DAVREFCR) .............................................................. 1323
39.3
40.
39.3.1
Reducing Interference between D/A and A/D Conversion ...................................... 1324
39.3.2
Notes on Using the Internal Reference Voltage as the Reference Voltage ............. 1326
39.4
Event Link Operation Setting Procedure ......................................................................... 1326
39.5
Usage Notes on Event Link Operation ............................................................................ 1326
39.6
Usage Notes .................................................................................................................... 1327
39.6.1
Module-Stop Function Settings ............................................................................... 1327
39.6.2
DAC12 Operation in Module-Stop State .................................................................. 1327
39.6.3
DAC12 Operation in Software Standby Mode ......................................................... 1327
39.6.4
Restriction on Usage when Interference Reduction between D/A and A/D Conversion is
Enabled ................................................................................................................... 1327
Temperature Sensor (TSN) ........................................................................................................ 1328
40.1
Overview .......................................................................................................................... 1328
40.2
Register Descriptions ....................................................................................................... 1328
40.2.1
Temperature Sensor Calibration Data Register H (TSCDRH) ................................. 1328
40.2.2
Temperature Sensor Calibration Data Register L (TSCDRL) .................................. 1329
40.3
41.
Operation ......................................................................................................................... 1323
Using the Temperature Sensor ........................................................................................ 1329
40.3.1
Preparation for Using Temperature Sensor ............................................................. 1329
40.3.2
Procedure for Using the Temperature Sensor ......................................................... 1330
Operational Amplifier (OPAMP) ................................................................................................. 1331
41.1
Overview .......................................................................................................................... 1331
41.2
Register Descriptions ....................................................................................................... 1332
41.2.1
Operational Amplifier Mode Control Register (AMPMC) ......................................... 1332
41.2.2
Operational Amplifier Trigger Mode Control Register (AMPTRM) ........................... 1332
41.2.3
Operational Amplifier Activation Trigger Select Register (AMPTRS) ...................... 1333
41.2.4
Operational Amplifier Control Register (AMPC) ...................................................... 1333
41.2.5
Operational Amplifier Monitor Register (AMPMON) ................................................ 1334
41.3
Operation ......................................................................................................................... 1335
41.3.1
State Transitions ...................................................................................................... 1335
41.3.2
Operational Amplifier Control Operation .................................................................. 1336
41.4
Software Trigger Mode .................................................................................................... 1340
42.
43.
44.
41.5
Activation Trigger Mode ................................................................................................... 1341
41.6
Activation and A/D Trigger Mode ..................................................................................... 1342
41.7
Usage Notes .................................................................................................................... 1342
Low Power Analog Comparator (ACMPLP) ............................................................................... 1343
42.1
Overview .......................................................................................................................... 1343
42.2
Register Descriptions ....................................................................................................... 1346
42.2.1
ACMPLP Mode Setting Register (COMPMDR) ....................................................... 1346
42.2.2
ACMPLP Filter Control Register (COMPFIR) .......................................................... 1347
42.2.3
ACMPLP Output Control Register (COMPOCR) ..................................................... 1347
42.2.4
Comparator Input Select Register (COMPSEL0) .................................................... 1348
42.2.5
Comparator Reference Voltage Select Register (COMPSEL1) ............................... 1348
42.3
Operation ......................................................................................................................... 1349
42.4
Noise Filter ....................................................................................................................... 1351
42.5
ACMPLP Interrupts .......................................................................................................... 1352
42.6
ELC Event Output ............................................................................................................ 1352
42.7
Interrupt Handling and ELC Linking ................................................................................. 1352
42.8
Comparator Pin Output .................................................................................................... 1352
42.9
Usage Notes .................................................................................................................... 1353
42.9.1
Module-Stop Function Settings ............................................................................... 1353
42.9.2
Relationship with A/D Converter .............................................................................. 1353
8-Bit D/A Converter (DAC8) ....................................................................................................... 1354
43.1
Overview .......................................................................................................................... 1354
43.2
Register Descriptions ....................................................................................................... 1354
43.2.1
D/A Conversion Value Setting Register n (DACSn) (n = 0, 1) ................................. 1354
43.2.2
D/A Converter Mode Register (DAM) ...................................................................... 1355
43.3
Operation ......................................................................................................................... 1355
43.4
Usage Notes .................................................................................................................... 1356
43.4.1
Module-Stop State ................................................................................................... 1356
43.4.2
Operation of the 8-bit D/A Converter in Module-Stop State .................................... 1356
43.4.3
8-bit D/A Converter in Software Standby Mode Operation ...................................... 1356
43.4.4
When Not Using the D/A Converter ......................................................................... 1356
Capacitive Touch Sensing Unit (CTSU) ..................................................................................... 1357
44.1
Overview .......................................................................................................................... 1357
44.2
Register Descriptions ....................................................................................................... 1359
44.2.1
CTSU Control Register 0 (CTSUCR0) .................................................................... 1359
44.2.2
CTSU Control Register 1 (CTSUCR1) .................................................................... 1361
44.2.3
CTSU Synchronous Noise Reduction Setting Register (CTSUSDPRS) ................. 1362
44.2.4
CTSU Sensor Stabilization Wait Control Register (CTSUSST) ............................... 1363
44.2.5
CTSU Measurement Channel Register 0 (CTSUMCH0) ......................................... 1364
44.2.6
CTSU Measurement Channel Register 1 (CTSUMCH1) ......................................... 1366
44.2.7
CTSU Channel Enable Control Register 0 (CTSUCHAC0) ..................................... 1367
44.2.8
CTSU Channel Enable Control Register 1 (CTSUCHAC1) ..................................... 1367
44.2.9
CTSU Channel Enable Control Register 2 (CTSUCHAC2) ..................................... 1368
44.2.10
CTSU Channel Enable Control Register 3 (CTSUCHAC3) ..................................... 1368
44.2.11
CTSU Channel Enable Control Register 4 (CTSUCHAC4) ..................................... 1369
44.2.12
CTSU Channel Transmit/Receive Control Register 0 (CTSUCHTRC0) .................. 1369
44.2.13
CTSU Channel Transmit/Receive Control Register 1 (CTSUCHTRC1) .................. 1370
44.2.14
CTSU Channel Transmit/Receive Control Register 2 (CTSUCHTRC2) .................. 1370
44.2.15
CTSU Channel Transmit/Receive Control Register 3 (CTSUCHTRC3) .................. 1371
44.2.16
CTSU Channel Transmit/Receive Control Register 4 (CTSUCHTRC4) .................. 1371
44.2.17
CTSU High-Pass Noise Reduction Control Register (CTSUDCLKC) ..................... 1372
44.2.18
CTSU Status Register (CTSUST) ............................................................................ 1372
44.2.19
CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register (CTSUSSC) ...
.................................................................................................................................. 1374
44.2.20
CTSU Sensor Offset Register 0 (CTSUSO0) .......................................................... 1375
44.2.21
CTSU Sensor Offset Register 1 (CTSUSO1) .......................................................... 1375
44.2.22
CTSU Sensor Counter (CTSUSC) .......................................................................... 1377
44.2.23
CTSU Reference Counter (CTSURC) ..................................................................... 1377
44.2.24
CTSU Error Status Register (CTSUERRS) ............................................................. 1378
44.3
44.3.1
Principles of Measurement Operation ..................................................................... 1378
44.3.2
Measurement Modes ............................................................................................... 1380
44.3.3
Parameters Common to Multiple Modes ................................................................. 1389
44.4
45.
Operation ......................................................................................................................... 1378
Usage Notes .................................................................................................................... 1391
44.4.1
Measurement Result Data (CTSUSC and CTSURC Counters) .............................. 1391
44.4.2
Constraints on Software Trigger .............................................................................. 1391
44.4.3
Constraints on External Trigger ............................................................................... 1392
44.4.4
Constraints on Forced Stops ................................................................................... 1392
44.4.5
TSCAP Pin .............................................................................................................. 1392
44.4.6
Constraints on Measurement Operation (CTSUCR0.CTSUSTRT Bit = 1) .............. 1392
Data Operation Circuit (DOC) .................................................................................................... 1393
45.1
Overview .......................................................................................................................... 1393
45.2
Register Descriptions ....................................................................................................... 1394
45.2.1
DOC Control Register (DOCR) ................................................................................ 1394
45.2.2
DOC Data Input Register (DODIR) .......................................................................... 1395
45.2.3
DOC Data Setting Register (DODSR) ..................................................................... 1395
45.3
Operation ......................................................................................................................... 1395
45.3.1
Data Comparison Mode ........................................................................................... 1395
45.3.2
Data Addition Mode ................................................................................................. 1396
45.3.3
Data Subtraction Mode ............................................................................................ 1396
45.4
Interrupt Request and Output to the Event Link Controller (ELC) ................................... 1397
45.5
Usage Notes .................................................................................................................... 1397
45.5.1
46.
SRAM ......................................................................................................................................... 1398
46.1
Overview .......................................................................................................................... 1398
46.2
Register Descriptions ...................................................................................................... 1398
46.2.1
SRAM Parity Error Operation After Detection Register (PARIOAD) ........................ 1398
46.2.2
SRAM Protection Register (SRAMPRCR) ............................................................... 1399
46.2.3
ECC Operating Mode Control Register (ECCMODE) ............................................. 1399
46.2.4
ECC 2-Bit Error Status Register (ECC2STS) .......................................................... 1400
46.2.5
ECC 1-Bit Error Information Update Enable Register (ECC1STSEN) .................... 1400
46.2.6
ECC 1-Bit Error Status Register (ECC1STS) .......................................................... 1401
46.2.7
ECC Protection Register (ECCPRCR) .................................................................... 1401
46.2.8
ECC Protection Register 2 (ECCPRCR2) ............................................................... 1402
46.2.9
ECC Test Control Register (ECCETST) .................................................................. 1402
46.2.10
SRAM ECC Error Operation After Detection Register (ECCOAD) .......................... 1403
46.3
Operation ......................................................................................................................... 1403
46.3.1
Low Power Consumption Function .......................................................................... 1403
46.3.2
ECC Function .......................................................................................................... 1404
46.3.3
ECC Error Generation ............................................................................................. 1404
46.3.4
ECC Decoder Testing .............................................................................................. 1405
46.3.5
Parity Calculation Function ...................................................................................... 1406
46.3.6
SRAM Error Sources ............................................................................................... 1407
46.3.7
Access Cycle ........................................................................................................... 1407
46.4
47.
Settings for the Module-Stop State .......................................................................... 1397
Usage Notes .................................................................................................................... 1408
46.4.1
Instruction Fetch from SRAM Area .......................................................................... 1408
46.4.2
Store Buffer of SRAM .............................................................................................. 1408
Flash Memory ............................................................................................................................ 1409
47.1
Overview .......................................................................................................................... 1409
47.2
Memory Structure ............................................................................................................ 1410
47.3
Flash Cache ..................................................................................................................... 1411
47.3.1
Overview .................................................................................................................. 1411
47.3.2
Register Descriptions .............................................................................................. 1412
47.4
Operation ......................................................................................................................... 1413
47.4.1
47.5
Operating Modes Associated with the Flash Memory ..................................................... 1413
47.5.1
47.6
Notice to Use Flash Cache ...................................................................................... 1413
ID Code Protection .................................................................................................. 1414
Overview of Functions ..................................................................................................... 1414
47.6.1
Configuration Area Bit Map ..................................................................................... 1416
47.6.2
Startup Area Select ................................................................................................. 1416
47.6.3
Protection by Access Window ................................................................................. 1417
47.7
Programming Commands ................................................................................................ 1418
47.8
Suspend Operation .......................................................................................................... 1418
47.9
Protection ......................................................................................................................... 1418
47.10
Serial Programming Mode ............................................................................................... 1418
47.10.1
SCI Boot Mode ........................................................................................................ 1419
47.10.2
USB Boot Mode ....................................................................................................... 1419
47.11
47.11.1
Serial Programming ................................................................................................. 1420
47.11.2
Programming Environment ...................................................................................... 1420
47.12
Self-Programming ............................................................................................................ 1421
47.12.1
Overview .................................................................................................................. 1421
47.12.2
Background Operation ............................................................................................. 1421
47.13
Reading the Flash Memory .............................................................................................. 1421
47.13.1
Reading the Code Flash Memory ............................................................................ 1421
47.13.2
Reading the Data Flash Memory ............................................................................. 1421
47.14
48.
Using a Serial Programmer ............................................................................................. 1420
Usage Notes .................................................................................................................... 1422
47.14.1
Erase Suspended Area ........................................................................................... 1422
47.14.2
Suspension by Erase Suspend Commands ............................................................ 1422
47.14.3
Constraints on Additional Writes ............................................................................. 1422
47.14.4
Reset during Programming and Erasure ................................................................. 1422
47.14.5
Non-maskable Interrupt Disabled during Programming and Erasure ...................... 1422
47.14.6
Location of Interrupt Vectors during Programming and Erasure ............................. 1422
47.14.7
Programming and Erasure in Low-Speed Operating Mode ..................................... 1422
47.14.8
Abnormal Termination during Programming and Erasure ....................................... 1422
47.14.9
Actions Prohibited during Programming and Erasure ............................................. 1422
Segment LCD Controller (SLCDC) ............................................................................................ 1423
48.1
Overview .......................................................................................................................... 1423
48.2
Register Descriptions ....................................................................................................... 1428
48.2.1
LCD Mode Register 0 (LCDM0) .............................................................................. 1428
48.2.2
LCD Mode Register 1 (LCDM1) .............................................................................. 1429
48.2.3
LCD Clock Control Register 0 (LCDC0) .................................................................. 1430
48.2.4
LCD Boost Level Control Register (VLCD) .............................................................. 1431
48.3
LCD Display Data Registers ............................................................................................ 1432
48.4
Selection of LCD Display Data Register .......................................................................... 1435
48.4.1
A-Pattern Area and B-pattern Area Data Display .................................................... 1435
48.4.2
Blinking Display (Alternately Displaying A-Pattern and B-Pattern Area Data) ......... 1435
48.5
Setting LCD Controller/Driver .......................................................................................... 1437
48.6
Operation Stop Procedure ............................................................................................... 1440
48.7
Supplying LCD Drive Voltages VL1, VL2, VL3, and VL4 ................................................. 1441
48.7.1
External Resistance Division Method ...................................................................... 1441
48.7.2
Internal Voltage Boosting Method ........................................................................... 1443
48.7.3
Capacitor Split Method ............................................................................................ 1444
48.8
Common and Segment Signals ....................................................................................... 1445
48.9
49.
48.9.1
Static Display Example ............................................................................................ 1452
48.9.2
Two-Time-Slice Display Example ............................................................................ 1454
48.9.3
Three-Time-Slice Display Example ......................................................................... 1456
48.9.4
Four-Time-Slice Display Example ........................................................................... 1459
48.9.5
Eight-Time-Slice Display Example .......................................................................... 1462
Secure Cryptographic Engine (SCE5) ....................................................................................... 1466
49.1
Overview .......................................................................................................................... 1466
49.2
Operation ......................................................................................................................... 1468
49.2.1
Encryption Engine ................................................................................................... 1468
49.2.2
Encryption and Decryption ...................................................................................... 1469
49.3
50.
51.
Display Modes ................................................................................................................. 1452
Usage Notes .................................................................................................................... 1469
49.3.1
Software Standby Mode .......................................................................................... 1469
49.3.2
Settings for the Module-Stop Function .................................................................... 1469
Internal Voltage Regulator ......................................................................................................... 1470
50.1
Overview .......................................................................................................................... 1470
50.2
Operation ......................................................................................................................... 1470
Electrical Characteristics ............................................................................................................ 1471
51.1
Absolute Maximum Ratings ............................................................................................. 1472
51.2
DC Characteristics ........................................................................................................... 1474
51.2.1
Tj/Ta Definition ........................................................................................................ 1474
51.2.2
I/O VIH, VIL .............................................................................................................. 1474
51.2.3
I/O IOH, IOL ............................................................................................................... 1476
51.2.4
I/O VOH, VOL, and Other Characteristics ................................................................. 1478
51.2.5
I/O Pin Output Characteristics of Low Drive Capacity ............................................. 1480
51.2.6
I/O Pin Output Characteristics of Middle Drive Capacity ......................................... 1482
51.2.7
P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity ..................... 1485
51.2.8
IIC I/O Pin Output Characteristics ........................................................................... 1487
51.2.9
Operating and Standby Current ............................................................................... 1488
51.2.10
VCC Rise and Fall Gradient and Ripple Frequency ................................................ 1496
51.3
AC Characteristics ........................................................................................................... 1497
51.3.1
Frequency ................................................................................................................ 1497
51.3.2
Clock Timing ............................................................................................................ 1500
51.3.3
Reset Timing ........................................................................................................... 1504
51.3.4
Wakeup Time .......................................................................................................... 1505
51.3.5
NMI and IRQ Noise Filter ........................................................................................ 1508
51.3.6
Bus Timing ............................................................................................................... 1509
51.3.7
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing ............................ 1516
51.3.8
CAC Timing ............................................................................................................. 1517
51.3.9
SCI Timing ............................................................................................................... 1518
51.3.10
SPI Timing ............................................................................................................... 1524
51.3.11
QSPI Timing ............................................................................................................ 1529
51.3.12
IIC Timing ................................................................................................................ 1531
51.3.13
SSIE Timing ............................................................................................................. 1533
51.3.14
SD/MMC Host Interface Timing ............................................................................... 1535
51.3.15
CLKOUT Timing ...................................................................................................... 1536
51.4
USB Characteristics ......................................................................................................... 1537
51.4.1
USBFS Timing ......................................................................................................... 1537
51.4.2
USB External Supply ............................................................................................... 1538
51.5
ADC14 Characteristics .................................................................................................... 1539
51.6
DAC12 Characteristics .................................................................................................... 1549
51.7
TSN Characteristics ......................................................................................................... 1551
51.8
OSC Stop Detect Characteristics .................................................................................... 1551
51.9
POR and LVD Characteristics ......................................................................................... 1552
51.10
VBATT Characteristics .................................................................................................... 1556
51.11
CTSU Characteristics ...................................................................................................... 1558
51.12
Segment LCD Controller Characteristics ......................................................................... 1558
51.12.1
Resistance Division Method .................................................................................... 1558
51.12.2
Internal Voltage Boosting Method ........................................................................... 1559
51.12.3
Capacitor Split Method ............................................................................................ 1560
51.13
Comparator Characteristics ............................................................................................. 1561
51.14
OPAMP Characteristics ................................................................................................... 1561
51.15
Flash Memory Characteristics ......................................................................................... 1562
51.15.1
Code Flash Memory Characteristics ....................................................................... 1562
51.15.2
Data Flash Memory Characteristics ........................................................................ 1563
51.16
Boundary Scan ................................................................................................................ 1564
51.17
Joint Test Action Group (JTAG) ....................................................................................... 1565
51.17.1
Serial Wire Debug (SWD) ........................................................................................ 1567
Appendix 1. Port States in each Processing Mode ............................................................................. 1569
Appendix 2. Package Dimensions ...................................................................................................... 1575
Appendix 3. I/O Registers ................................................................................................................... 1582
3.1
Peripheral Base Addresses ............................................................................................. 1582
3.2
Access Cycles ................................................................................................................. 1584
3.3
Register Descriptions ....................................................................................................... 1586
Revision History ................................................................................................................................... 1615
S3A1 Microcontroller Group
User’s Manual
High efficiency 48-MHz Arm® Cortex®-M4 core, 1-MB code flash memory, 192-KB SRAM, Segment LCD
Controller, Capacitive Touch Sensing Unit, USB 2.0 Full-Speed Module, 14-bit A/D Converter, 12-bit D/A
Converter, security and safety features
Features
■ Arm Cortex-M4 Core with Floating Point Unit (FPU)
Armv7E-M architecture with DSP instruction set
Maximum operating frequency: 48 MHz
Support for 4-GB address space
Arm Memory Protection Unit (Arm MPU) with 8 regions
Debug and Trace: ITM, DWT, FPB, TPIU, ETB
CoreSight™ Debug Port: JTAG-DP and SW-DP
■ Memory
1-MB code flash memory
8-KB data flash memory (100,000 program/erase (P/E) cycles)
192-KB SRAM
Flash Cache (FCACHE)
Memory Protection Unit (MPU)
Memory Mirror Function (MMF)
128-bit unique ID
■ Connectivity
USB 2.0 Full-Speed Module (USBFS)
- On-chip transceiver with voltage regulator
- Compliant with USB Battery Charging Specification 1.2
Serial Communications Interface (SCI) × 6
- UART
- Simple IIC
- Simple SPI
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 3
Controller Area Network (CAN) module
Serial Sound Interface Enhanced (SSIE)
SD/MMC Host Interface (SDHI)
Quad Serial Peripheral Interface (QSPI)
External address space
- 8- or 16-bit bus space is selectable per area
■ Analog
14-bit A/D Converter (ADC14)
12-bit D/A Converter (DAC12)
8-bit D/A Converter (DAC8) × 2 (for ACMPLP)
Low-Power Analog Comparator (ACMPLP) × 2
Operational Amplifier (OPAMP) × 4
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-Bit (GPT32) × 4
General PWM Timer 16-Bit (GPT16) × 6
Asynchronous General-Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
■ Safety
Error Correction Code (ECC) in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
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■ System and Power Management
Low power modes
Realtime Clock (RTC) with calendar and Battery Backup support
Event Link Controller (ELC)
DMA Controller (DMAC) × 4
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
■ Security and Encryption
AES128/256
GHASH
True Random Number Generator (TRNG)
■ Human Machine Interface (HMI)
Segment LCD Controller (SLCDC)
- Up to 54 segments × 4 commons
- Up to 50 segments × 8 commons
Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
Main clock oscillator (MOSC)
(1 to 20 MHz when VCC = 2.4 to 5.5 V)
(1 to 8 MHz when VCC = 1.8 to 2.4 V)
(1 to 4 MHz when VCC = 1.6 to 1.8 V)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO)
(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)
(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)
(24, 32 MHz when VCC = 1.6 to 5.5 V)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
■ General Purpose I/O Ports
Up to 126 input/output pins
- Up to 3 CMOS input
- Up to 123 CMOS input/output
- Up to 11 input/output 5-V tolerant
- Up to 2 high current (20 mA)
■ Operating Voltage
VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
Ta = -40°C to +85°C
- 145-pin LGA (7 mm × 7 mm, 0.5 mm pitch)
- 121-pin BGA (8 mm × 8 mm, 0.65 mm pitch)
- 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch)
Ta = -40°C to +105°C
- 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
- 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch)
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1.
1. Overview
Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a low-power, high-performance Arm Cortex®-M4 core running up to 48 MHz, with
the following features:
1-MB code flash memory
192-KB SRAM
Segment LCD Controller (SLCDC)
Capacitive Touch Sensing Unit (CTSU)
USB 2.0 Full-Speed Module (USBFS)
14-bit A/D Converter (ADC14)
12-bit D/A Converter (DAC12)
Security features.
1.1
Function Outline
Table 1.1
Arm core
Feature
Functional description
Arm Cortex-M4
Maximum operating frequency: up to 48 MHz
Arm Cortex-M4
- Revision: r0p1-01rel0
- Armv7E-M architecture profile
- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.
Arm Memory Protection Unit (Arm MPU)
- Armv7 Protected Memory System Architecture
- 8 protected regions.
SysTick timer
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2
Memory
Feature
Functional description
Code flash memory
Maximum 1-MB code flash memory. See section 47, Flash Memory.
Data flash memory
8-KB data flash memory. See section 47, Flash Memory.
Option-setting memory
The option-setting memory determines the state of the MCU after a reset. See section 7,
Option-Setting Memory.
Memory Mirror Function (MMF)
The Memory Mirror Function (MMF) can be configured to mirror the target application image
load address in code flash memory to the application image link address in the 23-bit unused
memory space (memory mirror space addresses). Your application code is developed and
linked to run from this MMF destination address. The application code does not need to know
the load location where it is stored in code flash memory. See section 5, Memory Mirror
Function (MMF).
SRAM
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). The first 16KB in SRAM0 provides error correction capability using ECC. See section 46, SRAM.
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Table 1.3
1. Overview
System (1 of 2)
Feature
Functional description
Operating modes
Two operating modes:
Single-chip mode
SCI/USB boot mode.
See section 3, Operating Modes.
Resets
14 resets:
RES pin reset
Power-on reset
VBATT-selected voltage power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
CPU stack pointer error reset
Software reset.
See section 6, Resets.
Low Voltage Detection (LVD)
Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and the
detection level can be selected using a software program. See section 8, Low Voltage
Detection (LVD).
Clocks
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
PLL frequency synthesizer
IWDT-dedicated on-chip oscillator
Clock out support.
See section 9, Clock Generation Circuit.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock to be used as a
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.
When measurement is complete or the number of pulses within the time generated by the
measurement reference clock is not within the allowable range, an interrupt request is
generated.
See section 10, Clock Frequency Accuracy Measurement Circuit (CAC).
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt
Controller Unit (ICU).
Key Interrupt Function (KINT)
A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function
(KINT).
Low power modes
Power consumption can be reduced in multiple ways, such as by setting clock dividers,
controlling EBCLK output, stopping modules, selecting power control mode in normal
operation, and transitioning to low power modes. See section 11, Low Power Modes.
Battery backup function
A battery backup function is provided for partial powering by a battery. The battery powered
area includes the RTC, SOSC, LOCO, wakeup control, backup memory, VBATT_R low voltage
detection, and switches between VCC and VBATT.
During normal operation, the battery powered area is powered by the main power supply,
which is the VCC pin. When a VCC voltage drop is detected, the power source is switched to
the dedicated battery backup power pin, the VBATT pin.
When the voltage rises again, the power source is switched from the VBATT pin to the VCC
pin. See section 12, Battery Backup Function.
Register write protection
The register write protection function protects important registers from being overwritten
because of software errors. See section 13, Register Write Protection.
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Table 1.3
1. Overview
System (2 of 2)
Feature
Functional description
Memory Protection Unit (MPU)
Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided
for memory protection. See section 16, Memory Protection Unit (MPU).
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A
refresh-permitted period can be set to refresh the counter and used as the condition to detect
when the system runs out of control. See section 26, Watchdog Timer (WDT).
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. It can be used to reset the MCU or to
generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates
with an independent, dedicated clock source, it is particularly useful in returning the MCU to a
known state as a fail-safe mechanism when the system runs out of control. The IWDT can be
triggered automatically on a reset, underflow, refresh error, or by a refresh of the count value in
the registers. See section 27, Independent Watchdog Timer (IWDT).
Table 1.4
Event link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 19, Event Link Controller (ELC).
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request. See section 18, Data Transfer Controller (DTC).
DMA Controller (DMAC)
A 4-channel DMA Controller (DMAC) module is provided for transferring data without the CPU.
When a DMA transfer request is generated, the DMAC transfers data stored at the transfer
source address to the transfer destination address. See section 17, DMA Controller (DMAC).
Table 1.6
External bus interface
Feature
Functional description
External bus
CS area: Connected to the external devices (external memory interface)
QSPI area: Connected to the QSPI (external device interface).
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Table 1.7
1. Overview
Timers
Feature
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with 4 channels and a 16-bit timer with 6
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or
the up- and down-counter. In addition, PWM waveforms can be generated for controlling
brushless DC motors. The GPT can also be used as a general-purpose timer. See section 23,
General PWM Timer (GPT).
Port Output Enable for GPT (POEG)
Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG).
Asynchronous General Purpose
Timer (AGT)
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
output, external pulse width or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and they can be accessed with the AGT
register. See section 24, Asynchronous General Purpose Timer (AGT).
Realtime Clock (RTC)
The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 25, Realtime Clock (RTC).
Table 1.8
Communication interfaces (1 of 2)
Feature
Functional description
Serial Communications Interface
(SCI)
The Serial Communications Interface (SCI) is configurable to five asynchronous and
synchronous serial interfaces:
Asynchronous interfaces (UART and asynchronous communications interface adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
SCI0 and SCI1 have FIFO buffers to enable continuous and full-duplex communication, and
the data transfer speed can be configured independently using an on-chip baud rate generator.
See section 29, Serial Communications Interface (SCI).
I2C Bus Interface (IIC)
The 3-channel I2C Bus Interface (IIC) module conforms with and provides a subset of the NXP
I2C bus (Inter-Integrated Circuit bus) interface functions. See section 30, I2C Bus Interface
(IIC).
Serial Peripheral Interface (SPI)
Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, fullduplex synchronous serial communications with multiple processors and peripheral devices.
See section 32, Serial Peripheral Interface (SPI).
Serial Sound Interface Enhanced
(SSIE)
The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
digital audio devices for transmitting PCM audio data over a serial bus with the MCU. The
SSIE supports an audio clock frequency of up to 25 MHz, and can be operated as a slave or
master receiver, transmitter, or transceiver to suit various applications. The SSIE includes 8stage FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven
data reception and transmission. See section 35, Serial Sound Interface Enhanced (SSIE).
Quad Serial Peripheral Interface
(QSPI)
The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial
ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM)
that has an SPI-compatible interface. See section 33, Quad Serial Peripheral Interface (QSPI).
Controller Area Network (CAN)
Module
The Controller Area Network (CAN) module provides functionality to receive and transmit data
using a message-based protocol between multiple slaves and masters in electromagnetically
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 31, Controller Area Network (CAN) Module.
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Table 1.8
1. Overview
Communication interfaces (2 of 2)
Feature
Functional description
USB 2.0 Full-Speed Module (USBFS)
The USB 2.0 Full-Speed Module (USBFS) can operate as a host controller or device controller.
The module supports full-speed and low-speed (only for the host controller) transfer as defined
in the Universal Serial Bus specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in the Universal Serial Bus specification 2.0. The USB
has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be
assigned any endpoint number based on the peripheral devices used for communication or
based on the user system. The MCU supports revision 1.2 of the Battery Charging
specification. Because the MCU can be powered at 5 V, the USB LDO regulator provides the
internal USB transceiver power supply at 3.3 V. See section 28, USB 2.0 Full-Speed Module
(USBFS).
SD/MMC Host Interface (SDHI)
The SD/MMC Host Interface (SDHI) provides the functionality needed to connect a variety of
external memory cards to the MCU. The SDHI supports both 1-bit and 4-bit buses for
connecting different memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD specifications, you must comply with
the SD Host/Ancillary Product License Agreement (SD HALA).
The MMC interface supports 1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51
(JEDEC Standard JESD 84-B451) device access. This interface also provides backward
compatibility and support for high-speed SDR transfer modes. See section 36, SD/MMC Host
Interface (SDHI).
Table 1.9
Analog
Feature
Functional description
14-bit A/D Converter (ADC14)
A 14-bit successive approximation A/D converter is provided. Up to 28 analog input channels
are selectable. Temperature sensor output and internal reference voltage are selectable for
conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion
making it possible to optimize the tradeoff between speed and resolution in generating a digital
value. See section 38, 14-Bit A/D Converter (ADC14).
12-bit D/A Converter (DAC12)
The 12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section
39, 12-Bit D/A Converter (DAC12).
8-bit D/A Converter (DAC8) (for
ACMPLP)
The 8-bit D/A Converter (DAC8) converts data and does not include an output amplifier
(DAC8). The DAC8 is used only as the reference voltage for ACMPLP. See section 43, 8-Bit D/
A Converter (DAC8).
Temperature Sensor (TSN)
The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for
reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC14 for conversion and can be further used by the end
application. See section 40, Temperature Sensor (TSN).
Low-Power Analog Comparator
(ACMPLP)
The Low-Power Analog Comparator (ACMPLP) compares the reference input voltage and
analog input voltage. The comparison result can be read through software and also be output
externally. The reference input voltage can be selected from an input to the CMPREFi (i = 0, 1)
pin, an internal 8-bit D/A converter output, or the internal reference voltage (Vref) generated
internally in the MCU.
The ACMPLP response speed can be set before starting an operation. Setting the high-speed
mode decreases the response delay time, but increases current consumption. Setting the lowspeed mode increases the response delay time, but decreases current consumption. See
section 42, Low Power Analog Comparator (ACMPLP).
Operational Amplifier (OPAMP)
The Operational Amplifier (OPAMP) amplifies small analog input voltages and outputs the
amplified voltages. A total of four differential operational amplifier units with two input pins and
one output pin are provided. See section 41, Operational Amplifier (OPAMP).
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Table 1.10
1. Overview
Human machine interfaces
Feature
Functional description
Segment LCD Controller (SLCDC)
The Segment LCD Controller (SLCDC) provides the following functions:
Waveform A or B selectable
The LCD driver voltage generator can switch between an internal voltage boosting method,
a capacitor split method, and an external resistance division method
Automatic output of segment and common signals based on automatic display data register
read
The reference voltage generated when operating the voltage boost circuit can be selected in
16 steps (contrast adjustment)
The LCD can be made to blink.
See section 48, Segment LCD Controller (SLCDC).
Capacitive Touch Sensing Unit
(CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed within an electrical insulator so that fingers do
not come into direct contact with the electrode. See section 44, Capacitive Touch Sensing Unit
(CTSU).
Table 1.11
Data processing
Feature
Functional description
Cyclic Redundancy Check (CRC)
calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC-generating polynomials are available. The snoop
function allows monitoring reads from and writes to specific addresses. This function is useful
in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See
section 34, Cyclic Redundancy Check (CRC) Calculator.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 45,
Data Operation Circuit (DOC).
Table 1.12
Security
Feature
Functional description
Secure Crypto Engine 5 (SCE5)
Security algorithm
- Symmetric algorithm: AES.
Other support features
- TRNG (True Random Number Generator)
- Hash-value generation: GHASH.
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1.2
1. Overview
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.
Bus
Memory
1 MB Code Flash
External
Arm Cortex-M4
DSP
System
FPU
POR/LVD
MOSC/SOSC
CSC
8 KB Data Flash
MPU
Reset
NVIC
Mode Control
192 KB SRAM
(HOCO/
MOCO/
LOCO)
PLL
MPU
System Timer
Power Control
CAC
DMA
DTC
Test and DBG Interface
DMAC × 4
Timers
Communication interfaces
GPT32 × 4
SCI × 6
QSPI
IIC × 3
SDHI × 1
SPI × 2
CAN × 1
SSIE × 1
USBFS with
Battery Charging
revision 1.2
GPT16 × 6
AGT × 2
RTC
WDT/IWDT
Clocks
Event Link
ICU
Battery Backup
KINT
Register Write
Protection
Human machine interfaces
CTSU
Data processing
SLCDC
Analog
ELC
CRC
ADC14
TSN
OPAMP × 4
Security
DOC
DAC12
DAC8
ACMPLP × 2
SCE5
Figure 1.1
Block diagram
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1.3
1. Overview
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity, and package type. Table 1.14 shows
a product list.
R 7 F S 3 A1 7 C 3 A 0 1 C F B #AA 0
Production identification code
Packing, terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
BJ: BGA 121 pins
FB: LQFP 144 pins
FP: LQFP 100 pins
FM: LQFP 64 pins
LK: LGA 145 pins
LJ: LGA 100 pins
NB: QFN 64 pins
Quality ID
Software ID
Operating temperature
2: -40° C to +85° C
3: -40° C to +105° C
Code flash memory size
C: 1 MB
Feature set
7: Superset
Group name
A1: S3A1 Group, Arm Cortex-M4, 48 MHz
Series name
3: High efficiency
Renesas Synergy™ family
Flash memory
Renesas microcontroller
Renesas
Figure 1.2
Table 1.13
Part numbering scheme
Product list
Product part number
Ordering part number
Package code
Code flash
Data flash
SRAM
Operating
temperature
R7FS3A17C2A01CLK
R7FS3A17C2A01CLK#AC0
PTLG0145KA-A
1 MB
8 KB
192 KB
-40 to +85°C
R7FS3A17C3A01CFB
R7FS3A17C3A01CFB#AA0
PLQP0144KA-B
-40 to +105°C
R7FS3A17C2A01CBJ
R7FS3A17C2A01CBJ#AC0
PLBG0121JA-A
-40 to +85°C
R7FS3A17C3A01CFP
R7FS3A17C3A01CFP#AA0
PLQP0100KB-B
-40 to +105°C
R7FS3A17C2A01CLJ
R7FS3A17C2A01CLJ#AC0
PTLG0100JA-A
-40 to +85°C
R7FS3A17C3A01CFM
R7FS3A17C3A01CFM#AA0
PLQP0064KB-C
-40 to +105°C
R7FS3A17C3A01CNB
R7FS3A17C3A01CNB#AC0
PWQN0064LA-A
-40 to +105°C
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1.4
1. Overview
Function Comparison
Table 1.14
Function comparison
Part numbers
R7FS3A17C2A01CLK
R7FS3A17C3A01CFB
R7FS3A17C2A01CBJ
R7FS3A17C3A01CFP
R7FS3A17C2A01CLJ
R7FS3A17C3A01CFM/
R7FS3A17C3A01CNB
Pin count
145
144
121
100
100
64
Package
LGA
LQFP
BGA
LQFP
LGA
LQFP/QFN
1 MB
Code flash memory
8 KB
Data flash memory
192 KB
SRAM
176 KB
Parity
16 KB
ECC
System
48 MHz
CPU clock
512 bytes
Backup
registers
Yes
ICU
KINT
8
Event control
ELC
Yes
DMA
DTC
Yes
4
DMAC
16-bit bus
8-bit bus
Bus
External bus
Timers
GPT32
4
GPT16
6
Communication
AGT
2
RTC
Yes
WDT/IWDT
Yes
6
SCI
3
IIC
2
2
SPI
SSIE
1
No
QSPI
1
No
SDHI
1
Yes
USBFS
28
ADC14
26
1
DAC8
2
OPAMP
18
2
4
4
4
SLCDC
CTSU
CRC
DOC
Security
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4
4
3
Yes
TSN
Data
processing
25
DAC12
ACMPLP
HMI
No
1
CAN
Analog
No
4 com × 54 seg
or
8 com x 50 seg
4 com × 46 seg
or
8 com x 42 seg
4 com × 38 seg
or
8 com x 34 seg
27
4 com × 21 seg
or
8 com x 17 seg
24
Yes
Yes
SCE5
Page 57 of 1619
S3A1 User’s Manual
1.5
1. Overview
Pin Functions
Table 1.15
Pin functions (1 of 4)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect this pin to the system power supply. Connect it to
VSS through a 0.1-μF capacitor. The capacitor should be placed close to the
pin.
VCL
Input
Connect this pin to the VSS pin through the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the pin.
VSS
Input
Ground pin. Connect to the system power supply (0 V).
VBATT
Input
Backup power supply pin
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input through the
EXTAL pin.
XCIN
Input
Clock
XCOUT
Output
Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
EBCLK
Output
Outputs the external bus clock for external devices
CLKOUT
Output
Clock output pin
Operating mode
control
MD
Input
Pins for setting the operating mode. The signal levels on these pins must not
be changed during operation mode transition on release from the reset state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this signal goes
low.
CAC
CACREF
Input
Measurement reference clock input pin
Interrupt
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ15
Input
Maskable interrupt request pins
KINT
KR00 to KR07
Input
Key interrupt input pins.
A key interrupt (KINT) can be generated by inputting a falling edge to the key
interrupt input pins.
On-chip debug
TMS
I/O
On-chip emulator or boundary scan pins
TDI
Input
TCK
Input
TDO
Output
SWDIO
I/O
Serial wire debug data input/output pin
SWCLK
Input
Serial wire clock pin
SWO
Output
Serial wire trace output pin
RD
Output
Strobe signal indicating that reading from the external bus interface space is
in progress, active-low
WR
Output
Strobe signal indicating that writing to the external bus interface space is in
progress, in 1-write strobe mode, active-low
WR0, WR1
Output
Strobe signals indicating that either group of data bus pins (D07 to D00, D15
to D08) is valid in writing to the external bus interface space, in byte strobe
mode, active-low
BC0, BC1
Output
Strobe signals indicating that either group of data bus pins (D07 to D00, D15
to D08) is valid in access to the external bus interface space, in 1-write
strobe mode, active-low
ALE
Output
Address latch signal when address/data multiplexed bus is selected
WAIT
Input
Input pin for wait request signals in access to the external space, active-low
CS0 to CS3
Output
Select signals for CS areas, active-low
A00 to A23
Output
Address bus
External bus
interface
Battery backup
D00 to D15
I/O
Data bus
VBATWIO0 to
VBATWIO2
I/O
Output wakeup signal for the VBATT wakeup control function.
External event input for the VBATT wakeup control function.
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 58 of 1619
S3A1 User’s Manual
Table 1.15
1. Overview
Pin functions (2 of 4)
Function
Signal
I/O
Description
GPT
GTETRGA,
GTETRGB
Input
External trigger input pin
GTIOC0A to
GTIOC9A, GTIOC0B
to GTIOC9B
I/O
Input capture, output capture, or PWM output pin
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U phase)
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U phase)
AGT
RTC
SCI
IIC
SSIE
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W phase)
AGTEE0, AGTEE1
Input
External event input enable signals
AGTIO0, AGTIO1
I/O
External event input and pulse output pins
AGTO0, AGTO1
Output
Pulse output pins
AGTOA0, AGTOA1
Output
Output compare match A output pins
Output compare match B output pins
AGTOB0, AGTOB1
Output
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock
RTCIC0 to RTCIC2
Input
Time capture event input pins
SCK0 to SCK4,
SCK9
I/O
Clock (clock synchronous mode) input/output pins
RXD0 to RXD4,
RXD9
Input
Received data (asynchronous mode/clock synchronous mode) input pins
TXD0 to TXD4,
TXD9
Output
Transmitted data (asynchronous mode/clock synchronous mode) output pins
CTS0_RTS0 to
CTS4_RTS4,
CTS9_RTS9
I/O
Input/output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active-low
SCL0 to SCL4,
SCL9
I/O
I2C clock (simple IIC) input/output pins
SDA0 to SDA4,
SDA9
I/O
I2C data (simple IIC) input/output pins
SCK0 to SCK4,
SCK9
I/O
Clock (simple SPI) input/output pins
MISO0 to MISO4,
MISO9
I/O
Slave transmission of data (simple SPI) input/output pins
MOSI0 to MOSI4,
MOSI9
I/O
Master transmission of data (simple SPI) input/output pins
SS0 to SS4, SS9
Input
Slave-select input pins (simple SPI), active-low
SCL0 to SCL2
I/O
Clock input/output pins
SDA0 to SDA2
I/O
Data input/output pins
SSIBCK0
I/O
SSIE serial bit clock pin
SSILRCK0/SSIFS0
I/O
Word select pins
SSITXD0
Output
Serial data output pin
SSIRXD0
Input
Serial data input pin
AUDIO_CLK
Input
External clock pin for audio (input oversampling clock)
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 59 of 1619
S3A1 User’s Manual
Table 1.15
1. Overview
Pin functions (3 of 4)
Function
Signal
I/O
SPI
RSPCKA, RSPCKB
I/O
Clock input/output pin
MOSIA, MOSIB
I/O
Input/output pins for data output from the master
MISOA, MISOB
I/O
Input/output pins for data output from the slave
SSLA0, SSLB0
I/O
Input/output pins for slave selection
SSLA1, SSLA2,
SSLA3, SSLB1,
SSLB2, SSLB3
Output
Output pins for slave selection
QSPCLK
Output
QSPI clock output pin
QSSL
Output
QSPI slave output pin
QIO0
I/O
Master transmit data/Data 0
QIO1
I/O
Master input data/Data 1
QIO2, QIO3
I/O
Data 2, Data 3
CRX0
Input
Receive data
CTX0
Output
Transmit data
VSS_USB
Input
Ground pin
VCC_USB_LDO
Input
Power supply pin for USB LDO regulator
VCC_USB
I/O
Input: Power supply pin for USB transceiver.
Output: USB LDO regulator output pin. This pin should be connected to an
external capacitor.
USB_DP
I/O
D+ I/O pin of the USB on-chip transceiver. This pin should be connected to
the D+ pin of the USB bus.
USB_DM
I/O
D– I/O pin of the USB on-chip transceiver. This pin should be connected to
the D– pin of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin. This pin should be connected to VBUS
on the USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a device controller.
USB_EXICEN
Output
Low power control signal for external power supply (OTG) chip
USB_VBUSEN
Output
VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA,
USB_OVRCURB
Input
Connect the external overcurrent detection signals to these pins. Connect
the VBUS comparator signals to these pins when the OTG power supply
chip is connected.
USB_ID
Input
Connect the MicroAB connector ID input signal to this pin during operation in
OTG mode
SD0CLK
Output
SD clock output pin
SD0CMD
I/O
SD command output, response input signal pin
SD0DAT0 to
SD0DAT7
I/O
SD data bus pins
QSPI
CAN
USBFS
SDHI
Analog power
supply
Description
SD0CD
Input
SD card detection pin
SD0WP
Input
SD write-protect signal
AVCC0
Input
Analog voltage supply pin
AVSS0
Input
Analog voltage supply ground pin
VREFH0
Input
Analog reference voltage supply pin
VREFL0
Input
Reference power supply ground pin
VREFH
Input
Analog reference voltage supply pin for D/A converter
VREFL
Input
Analog reference ground pin for D/A converter
AN000 to AN027
Input
Input pins for the analog signals to be processed by the A/D converter
ADTRG0
Input
Input pins for the external trigger signals that start the A/D conversion,
active-low
DA0
Output
Output pins for the analog signals to be processed by the D/A converter
Comparator output
VCOUT
Output
Comparator output pin
ACMPLP
CMPREF0,
CMPREF1
Input
Reference voltage input pins
CMPIN0, CMPIN1
Input
Analog voltage input pins
ADC14
DAC12
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 60 of 1619
S3A1 User’s Manual
Table 1.15
1. Overview
Pin functions (4 of 4)
Function
Signal
I/O
Description
OPAMP
AMP0+ to AMP3+
Input
Analog voltage input pins
AMP0- to AMP3-
Input
Analog voltage input pins
AMP0O to AMP3O
Output
Analog voltage output pins
TS00 to TS13,
TS17 to TS22,
TS27 to TS31,
TS34, TS35
Input
Capacitive touch detection pins (touch pins)
CTSU
I/O ports
SLCDC
TSCAP
-
Secondary power supply pin for the touch driver
P000 to P015
I/O
General-purpose input/output pins
P100 to P115
I/O
General-purpose input/output pins
P200
Input
General-purpose input pin
P201 to P206,
P212, P213
I/O
General-purpose input/output pins
P214, P215
Input
General-purpose input pins
P300 to P315
I/O
General-purpose input/output pins
P400 to P415
I/O
General-purpose input/output pins
P500 to P507,
P511, P512
I/O
General-purpose input/output pins
P600 to P606,
P608 to P614
I/O
General-purpose input/output pins
P700 to P705,
P708 to P713
I/O
General-purpose input/output pins
P800 to P809
I/O
General-purpose input/output pins
P900 to P902, P914,
P915
I/O
General-purpose input/output pins
VL1, VL2, VL3, VL4
I/O
Voltage pin for driving the LCD
CAPH, CAPL
I/O
Capacitor connection pin for the LCD controller/driver
COM0 to COM7
Output
Common signal output pins for the LCD controller/driver
SEG00 to SEG53
Output
Segment signal output pins for the LCD controller/driver
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 61 of 1619
S3A1 User’s Manual
1.6
1. Overview
Pin Assignments
Figure 1.3 to Figure 1.9 show the pin assignments.
R7FS3A17C2A01CLK
13
12
A
B
C
D
E
P407
P409
P412
P708
P711
P410
P414
P915/
P914/
USB_DM USB_DP
F
G
H
J
K
L
M
N
VCC
P212
/EXTAL
P215
/XCIN
VCL
P702
P405
P402
P400
13
P710
VSS
P213
/XTAL
P214
/XCOUT
VBATT
P701
P404
P511
VCC
12
11
VCC_
USB
VSS_
USB
VCC_
USB_LDO
P411
P415
P712
P705
P704
P703
P403
P401
P512
VSS
11
10
P205
P206
P204
P408
P413
P709
P713
P700
P406
P003
P000
P002
P001
10
9
P203
P313
P202
P314
P004
P006
P009
P008
9
8
P900
P901
P200
P315
P005
AVSS0
P011
P010
/VREFL0 /VREFH0
8
7
VSS
P902
RES
P310
P007
AVCC0
P013
/VREFL
P012
/VREFH
7
6
VCC
P201/MD
P312
P305
P505
P506
P015
P014
6
5
P309
P311
P308
P303
NC
P503
P504
VSS
VCC
5
4
P307
P306
P304
P109/TDO
/SWO
P114
P608
P604
P600
P105
P500
P502
P501
P507
4
3
P808
P809
P301
P112
P115
P610
P614
P603
P107
P106
P104
P803
P802
3
2
P302
P300/TCK
/SWCLK
P111
P806
P609
P612
VSS
P605
P601
P805
P800
P101
P801
2
P108/TMS
P110/TDI
/SWDIO
P113
P807
P611
P613
VCC
P606
P602
P804
P103
P102
P100
1
C
D
E
F
G
H
J
K
L
1
A
Figure 1.3
B
M
N
Pin assignment for 145-pin LGA (top view)
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 62 of 1619
VSS
VCC
P614
P613
P612
P611
P610
P609
P608
P807
P806
P115
P114
P113
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
91
90
89
88
87
85
83
81
79
76
75
74
73
P606
92
77
P604
P605
94
78
P602
P603
96
80
P601
97
82
P805
P600
99
84
P804
100
86
P107
101
93
P106
102
95
P104
P105
104
98
P102
P103
103
P101
106
105
P100
107
1. Overview
108
S3A1 User’s Manual
P800
109
72
P300/TCK/SWCLK
P801
110
71
P301
P802
111
70
P302
P803
112
69
P303
P500
113
68
P501
114
67
P809
P808
P502
P503
115
66
P304
116
65
P305
P504
117
64
P306
P505
118
63
P307
P506
119
62
P308
P507
120
61
P309
VCC
121
60
P310
VSS
122
59
P311
P015
123
58
P312
P014
124
57
P013/VREFL
P012/VREFH
125
56
P200
P201/MD
55
RES
AVCC0
127
54
VCC
AVSS0
128
53
VSS
P011/VREFL0
129
52
P902
P010VREFH0
130
51
P901
P009
P008
131
50
P900
132
49
P315
P007
133
48
P006
134
47
P314
P313
P005
135
46
P004
136
45
P202
P203
P003
137
44
P204
P002
138
43
P205
P001
P000
139
42
P206
140
41
VCC_USB_LDO
VSS
VCC
P512
141
40
142
39
143
38
VCC_USB
P914/USB_DP
P915/USB_DM
P511
144
37
VSS_USB
Figure 1.4
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P704
P705
VBATT
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P713
P712
P711
P710
P709
P708
P415
P414
P413
P412
P411
P410
P409
P408
P407
10
9
P701
P702
5
P404
P405
8
4
P403
7
3
P402
P406
P700
2
P401
6
1
P400
P703
R7FS3A17C3A01CFB
126
Pin assignment for 144-pin LQFP (top view)
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 63 of 1619
S3A1 User’s Manual
1. Overview
R7FS3A17C2A01CBJ
11
10
Figure 1.5
A
B
C
D
E
F
G
H
J
K
L
P407
P408
P411
P414
P212/
EXTAL
P215/
XCIN
VCL
P406
P403
P401
P400
11
P410
P415
P213/
XTAL
P214/
XCOUT
VBATT
P405
P402
P511
P512
10
P915/
P914/
USB_DM USB_DP
9
VCC_
USB
VSS_
USB
P409
P412
P708
VCC
VSS
P404
P002
P001
P000
9
8
P205
VCC_
USB_
LDO
P206
P204
P413
P710
P702
P006
P004
P003
P005
8
7
P203
P202
P313
P314
P315
P709
P701
P007
AVSS0
P011/
P010/
7
VREFL0 VREFH0
6
VSS
VCC
RES
P201/MD
P200
NC
P700
P008
AVCC0
P013/
VREFL
P012/
VREFH
6
5
P308
P309
P307
P302
P304
P612
P601
P506
P505
P015
P014
5
4
P305
P306
P808
P114
P611
P603
P600
P504
P503
VSS
VCC
4
3
P809
P303
P110/TDI
P111
P609
P604
P106
P104
P502
P500
P501
3
2
P301
P108/
TMS/
SWDIO
P113
P608
P613
P605
P602
P105
P102
P801
P800
2
1
P300/
TCK/
SWCLK
P109/
TDO/
SWO
P112
P115
P610
VCC
VSS
P107
P103
P101
P100
1
A
B
C
D
E
F
G
H
J
K
L
Pin assignment for 121-pin BGA (top view)
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 64 of 1619
Figure 1.6
P100
P101
P102
P103
P104
P105
P106
P107
P600
P601
P602
P603
VSS
VCC
P610
P609
P608
P115
P114
P113
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1. Overview
75
S3A1 User’s Manual
P500
76
50
P501
77
49
P300/TCK/SWCLK
P301
P502
78
48
P302
P503
79
47
P303
P504
80
46
P809
P505
81
45
P808
VCC
82
44
P304
VSS
83
43
P305
P015
84
42
P306
P014
85
41
P307
P013/VREFL
86
40
P200
P012/VREFH
87
39
P201/MD
AVCC0
88
38
RES
AVSS0
89
37
VCC
P011/VREFL0
90
36
VSS
P010/VREFH0
91
35
P202
P008
92
34
P203
P007
93
33
P204
P006
94
32
P205
P005
95
31
P206
P004
96
30
VCC_USB_LDO
P003
97
29
VCC_USB
P002
98
28
P914/USB_DP
P001
99
27
P915/USB_DM
P000
100
26
VSS_USB
14
15
16
17
18
19
20
21
22
23
24
25
P212/EXTAL
VCC
P708
P415
P414
P413
P412
P411
P410
P409
P408
P407
9
VCL
13
8
VBATT
P213/XTAL
7
P406
12
6
P405
VSS
5
P404
11
4
P403
P214/XCOUT
3
P402
10
2
P401
P215/XCIN
1
P400
R7FS3A17C3A01CFP
Pin assignment for 100-pin LQFP (top view)
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 65 of 1619
S3A1 User’s Manual
1. Overview
R7FS3A17C2A01CLJ
10
9
Figure 1.7
A
B
C
D
E
F
G
H
J
K
P407
P409
P412
VCC
P212/
EXTAL
P215/
XCIN
VCL
P403
P400
P000
10
P413
VSS
P213/
XTAL
P214/
XCOUT
VBATT
P405
P401
P001
9
P915/
P914/
USB_DM USB_DP
8
VCC_
USB
VSS_
USB
VCC_US
B_LDO
P411
P415
P708
P404
P003
P004
P002
8
7
P205
P204
P206
P408
P414
P406
P006
P007
P008
P005
7
6
VSS
VCC
P202
P203
P410
P402
P505
AVSS0
P011/
P010/
6
VREFL0 VREFH0
5
P200
P201/MD
P307
RES
P113
P600
P504
AVCC0
P013/
VREFL
P012/
VREFH
5
4
P305
P304
P808
P306
P115
P601
P503
P100
P015
P014
4
3
P809
P303
P110/TDI
P111
P609
P602
P107
P103
VSS
VCC
3
2
P300/
TCK/
SWCLK
P302
P301
P114
P610
P603
P106
P101
P501
P502
2
1
P108/
TMS/
SWDIO
P109/
TDO/
SWO
P112
P608
VCC
VSS
P105
P104
P102
P500
1
A
B
C
D
E
F
G
H
J
K
Pin assignment for 100-pin LGA (top view)
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 66 of 1619
Figure 1.8
P100
P101
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1. Overview
48
S3A1 User’s Manual
P500
49
32
P300/TCK/SWCLK
P501
50
31
P301
P502
51
30
P302
P015
52
29
P303
P014
53
28
P304
P013/VREFL
54
27
P200
P012/VREFH
55
26
P201/MD
AVCC0
56
25
RES
AVSS0
57
24
P204
P011/VREFL0
58
23
P205
P010/VREFH0
59
22
P206
P004
60
21
VCC_USB_LDO
P003
61
20
VCC_USB
P002
62
19
P914/USB_DP
P001
63
18
P915/USB_DM
P000
64
17
VSS_USB
8
9
10
11
12
13
14
15
16
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
VCL
VSS
5
VBATT
7
4
P402
6
3
P401
P215/XCIN
2
P214/XCOUT
1
P400
R7FS3A17C3A01CFM
Pin assignment for 64-pin LQFP (top view)
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 67 of 1619
33
34
35
36
37
38
39
40
41
42
43
44
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
45
46
47
P100
P101
1. Overview
48
S3A1 User’s Manual
P500
P501
P502
P015
P014
P013/VREFL
P012/VREFH
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P004
P003
P002
P001
49
32
50
31
58
23
59
22
60
21
61
20
62
19
63
18
P300/TCK/SWCLK
P301
P302
P303
P304
P200
P201/MD
RES
P204
P205
P206
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
51
30
52
29
53
28
54
27
55
26
P000
64
17
VSS_USB
24
16
15
14
13
12
11
10
9
8
7
6
5
4
25
P400
P401
P402
VBATT
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
3
R7FS3A17C3A01CNB
1
57
2
56
Figure 1.9
Pin assignment for 64-pin QFN (top view)
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 68 of 1619
S3A1 User’s Manual
Pin Lists
N13 1
L11 1
J10 1
1
CACREF
IRQ0
P400 -
AGTIO1 -
GTIOC6A -
L11 2
K11 2
J9
2
2
-
IRQ5
P401 -
-
M1 3
3
J10 3
F6
3
3
VBATWIO0 IRQ4
P402 -
AGTIO0/ AGTIO1
-
K11 4
J11 4
H10 -
-
VBATWIO1 -
P403 -
AGTIO0/ AGTIO1
GTIOC3A RTCIC1
GTETRGA GTIOC6B -
RTCIC0
-
SCK1
SCK4
CTSU
SLCDC
ACMPLP
ADC14
SDHI
SSIE
HMI
DAC12, OPAMP
Analog
SPI/QSPI
IIC
SCI
USBFS, CAN
RTC
GPT
GPT_OPS, POEG
Communication interfaces
AGT
I/O port
External bus
Timers
Power, System, Clock,
Debug, CAC, VBATT
QFN64
LQFP64
LGA100
LQFP100
BGA121
LQFP144
LGA145
Pin number
Interrupt
1.7
1. Overview
SCL0
-
AUDIO_C LK
-
-
-
SEG4
TS20
CTX0 TXD1/ SDA0
MOSI1
/SDA1
CTS4_
RTS4/
SS4
-
-
-
-
-
-
SEG5
TS19
CRX0 RXD1/ MISO1
/SCL1
-
-
-
-
-
-
SEG6
TS18
-
CTS1_ RTS1/
SS1
-
SSIBCK0
-
-
-
-
-
TS17
L12 5
H9
5
G8
-
-
VBATWIO2 -
P404 -
-
-
GTIOC3B RTCIC2
-
-
-
-
SSILRCK0 /SSIFS0
-
-
-
-
-
L13 6
H10 6
H9
-
-
-
-
P405 -
-
-
GTIOC1A -
-
-
-
-
SSITXD0
-
-
-
-
-
-
J10 7
H11 7
F7
-
-
-
-
P406 -
-
-
GTIOC1B -
-
-
-
SSLA3
SSIRXD0 -
-
-
-
-
-
H10 8
G6
-
-
-
-
-
-
P700 -
-
-
GTIOC5A -
-
-
-
MISOA
-
-
-
-
-
-
-
K12 9
G7
-
-
-
-
-
-
P701 -
-
-
GTIOC5B -
-
-
-
MOSIA
-
-
-
-
-
-
-
K13 10
G8
-
-
-
-
-
-
P702 -
-
-
GTIOC6A -
-
-
-
RSPCKA -
-
-
-
-
-
-
J11 11
-
-
-
-
-
-
-
P703 -
-
-
GTIOC6B -
-
-
-
SSLA0
-
-
-
-
VCOUT -
-
H11 12
-
-
-
-
-
-
-
P704 -
AGTO0
-
-
-
-
-
-
SSLA1
-
-
-
-
-
-
-
G11 13
-
-
-
-
-
-
-
P705 -
AGTIO0 -
-
-
-
-
-
SSLA2
-
-
-
-
-
-
-
J12 14
G10 8
G9
4
4
VBATT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J13 15
G11 9
G10 5
5
VCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H13 16
F11 10
F10 6
6
XCIN
-
P215 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H12 17
F10 11
F9
7
7
XCOUT
-
P214 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F12 18
G9
12
D9
8
8
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G12 19
E10 13
E9
9
9
XTAL
IRQ2
P213 -
-
GTETRGA GTIOC0A -
-
TXD1/ MOSI1
/SDA1
-
-
-
-
-
-
-
-
G13 20
E11 14
E10 10 10
EXTAL
IRQ3
P212 -
AGTEE1 GTETRGB GTIOC0B -
-
RXD1/ MISO1
/SCL1
-
-
-
-
-
-
-
-
F13 21
F9
15
D10 11
11
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G10 22
-
-
-
-
-
-
-
P713 -
AGTOA0 -
GTIOC2A -
-
-
-
-
-
-
-
-
-
-
-
F11 23
-
-
-
-
-
-
-
P712 -
AGTOB0 -
GTIOC2B -
-
-
-
-
-
-
-
-
-
-
-
E13 24
-
-
-
-
-
-
-
P711
AGTEE0 -
-
-
-
CTS1_ RTS1/
SS1
-
-
-
-
-
-
-
-
E12 25
F8
-
-
-
-
-
-
P710 A17 -
-
-
-
-
SCK1
-
-
-
-
-
-
-
-
-
F10 26
F7
-
-
-
-
-
IRQ10 P709 -
-
-
-
-
-
TXD1/ MOSI1
/SDA1
-
-
-
-
-
-
-
-
D13 27
E9
16
F8
-
-
-
IRQ11 P708 -
-
-
-
-
-
RXD1/ MISO1
/SCL1
SSLA3
-
-
-
-
-
-
-
E11 28
D10 17
E8
-
-
-
IRQ8
P415 -
-
-
GTIOC0A -
-
-
-
SSLA2
-
SD0CD
-
-
-
-
-
D12 29
D11 18
E7
-
-
-
IRQ9
P414 -
-
-
GTIOC0B -
-
-
-
SSLA1
-
SD0WP
-
-
-
-
-
E10 30
E8
19
C9
-
-
-
-
P413 -
-
GTOUUP
-
-
-
CTS0_ RTS0/
SS0
SSLA0
-
SD0CLK
-
-
-
-
-
C13 31
D9
20
C10 -
-
-
-
P412 -
-
GTOULO
-
-
-
SCK0
RSPCKA -
SD0CMD -
-
-
-
-
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
-
-
-
-
-
Page 69 of 1619
S3A1 User’s Manual
CTSU
SLCDC
ACMPLP
ADC14
SDHI
SSIE
HMI
DAC12, OPAMP
Analog
SPI/QSPI
IIC
SCI
USBFS, CAN
RTC
GPT
GPT_OPS, POEG
Communication interfaces
AGT
I/O port
Interrupt
External bus
Timers
Power, System, Clock,
Debug, CAC, VBATT
QFN64
LQFP64
LGA100
LQFP100
BGA121
LQFP144
LGA145
Pin number
1. Overview
D11 32
C11 21
D8
12 12
-
IRQ4
P411
-
AGTOA1 GTOVUP
GTIOC9A -
-
TXD0/ MOSI0
/SDA0
CTS3_
RTS3/
SS3
MOSIA
-
SD0DAT0 -
-
-
SEG7
TS7
C12 33
C10 22
E6
13 13
-
IRQ5
P410 -
AGTOB1 GTOVLO
GTIOC9B -
-
SCK3 RXD0/
MISO0
/SCL0
MISOA
-
SD0DAT1 -
-
-
SEG8
TS6
B13 34
C9
B10 14 14
-
IRQ6
P409 -
-
GTOWUP GTIOC5A -
USB_ TXD3/ EXIC MOSI3
/SDA3
EN
-
-
-
-
-
-
SEG9
TS5
D10 35
B11 24
D7
15 15
-
IRQ7
P408 -
-
GTOWLO GTIOC5B -
USB_ CTS1_ SCL0
ID
RTS1/
SS1
RXD3/
MISO3
/SCL3
-
-
-
-
-
-
SEG10 TS4
A13 36
A11 25
A10 16 16
-
-
P407 -
AGTIO0 -
-
RTCOUT USB_ CTS4_ SDA0
VBUS RTS4/
SS4
SSLB3
-
-
ADTR
G0
-
-
SEG11 TS3
B11 37
B9
26
B8
17 17
VSS_USB -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A12 38
A10 27
A9
18 18
-
-
P915 -
-
-
-
-
USB_ DM
-
-
-
-
-
-
-
-
-
B12 39
B10 28
B9
19 19
-
-
P914 -
-
-
-
-
USB_ DP
-
-
-
-
-
-
-
-
-
A11 40
A9
29
A8
20 20
VCC_USB -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C11 41
B8
30
C8
21 21
VCC_USB _LDO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B10 42
C8
31
C7
22 22
-
IRQ0
P206 WAI T
GTIU
-
-
USB_ RXD4/ SDA1
VBUS MISO4
/SCL4
EN
SSLB1
-
SD0DAT2 -
-
-
SEG12 TS1
A10 43
A8
32
A7
23 23
CLKOUT
IRQ1
P205 A16 AGTO1
GTIV
GTIOC4A -
USB_
OVR
CUR
A
TXD4/ SCL1
MOSI4
/SDA4
CTS9_
RTS9/
SS9
SSLB0
-
SD0DAT3 -
-
-
SEG20 TSCAP
C10 44
D8
33
B7
24 24
CACREF
-
P204 A18 AGTIO1 GTIW
GTIOC4B -
USB_ SCK4
OVR SCK9
CUR
B
RSPCKB -
SD0DAT4 -
-
-
SEG23 TS0
A9
45
A7
34
D6
-
-
-
IRQ2
P203 A19 -
-
GTIOC5A -
-
CTS2_ RTS2/
SS2
TXD9/
MOSI9
/SDA9
MOSIB
-
SD0DAT5 -
-
-
SEG22 TSCAP
C9
46
B7
35
C6
-
-
-
IRQ3
P202 WR1 /BC1
-
GTIOC5B -
-
SCK2 RXD9/
MISO9
/SCL9
MISOB
-
SD0DAT6 -
-
-
SEG21 -
B9
47
C7
-
-
-
-
-
-
P313 A20 -
-
-
-
-
-
-
-
-
SD0DAT7 -
-
-
-
-
D9
48
D7
-
-
-
-
-
-
P314 A21 -
-
-
-
-
-
-
-
-
-
ADTR
G0
-
-
-
-
D8
49
E7
-
-
-
-
-
-
P315 A22 -
-
-
-
-
RXD4/ MISO4
/SCL4
-
-
-
-
-
-
-
-
A8
50
-
-
-
-
-
-
-
P900 A23 -
-
-
-
-
TXD4/ MOSI4
/SDA4
-
-
-
-
-
-
-
-
B8
51
-
-
-
-
-
-
-
P901 -
AGTIO1 -
-
-
-
SCK4
-
-
-
-
-
-
-
-
-
B7
52
-
-
-
-
-
-
-
P902 -
AGTO1
-
-
-
-
CTS4_ RTS4/
SS4
-
-
-
-
-
-
-
-
A7
53
A6
36
A6
-
-
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A6
54
B6
37
B6
-
-
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C7
55
C6
38
D5
25 25
RES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B6
56
D6
39
B5
26 26
MD
-
P201 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
SCL0
Page 70 of 1619
S3A1 User’s Manual
-
CTSU
SLCDC
ACMPLP
ADC14
SDHI
SSIE
HMI
DAC12, OPAMP
Analog
SPI/QSPI
IIC
SCI
USBFS, CAN
RTC
GPT
GPT_OPS, POEG
Communication interfaces
AGT
I/O port
Interrupt
External bus
Timers
Power, System, Clock,
Debug, CAC, VBATT
QFN64
LQFP64
LGA100
LQFP100
BGA121
LQFP144
LGA145
Pin number
1. Overview
C8
57
E6
40
A5
27 27
-
NMI
P200 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C6
58
-
-
-
-
-
-
-
P312 CS3 AGTOA1 -
-
-
-
CTS3_ RTS3/
SS3
-
-
-
-
-
-
-
-
B5
59
-
-
-
-
-
-
-
P311
CS2 AGTOB1 -
-
-
-
SCK3
-
-
-
-
-
-
-
-
D7
60
-
-
-
-
-
-
-
P310 A15 AGTEE1 -
-
-
-
TXD3/ MOSI3
/SDA3
QIO3
-
-
-
-
-
-
-
A5
61
B5
-
-
-
-
-
-
P309 A14 -
-
-
-
-
RXD3/ MISO3
/SCL3
QIO2
-
-
-
-
-
-
-
C5
62
A5
-
-
-
-
-
-
P308 A13 -
-
-
-
-
-
-
QIO1
-
-
-
-
-
SEG13 -
A4
63
C5
41
C5
-
-
-
-
P307 A12 -
-
-
-
-
-
-
QIO0
-
-
-
-
-
SEG14 -
-
-
B4
64
B4
42
D4
-
-
-
-
P306 A11 -
-
-
-
-
-
-
QSSL
-
-
-
-
SEG15 -
D6
65
A4
43
A4
-
-
-
IRQ8
P305 A10 -
-
-
-
-
-
-
QSPCLK -
SD0CD
-
-
-
SEG16 -
C4
66
E5
44
B4
28 28
-
IRQ9
P304 A09 -
-
GTIOC7A -
-
-
-
-
-
SD0WP
-
-
-
SEG17 TS11
A3
67
C4
45
C4
-
-
-
-
P808 -
-
-
-
-
-
-
-
-
-
SD0CLK
-
-
-
SEG18 -
B3
68
A3
46
A3
-
-
-
-
P809 -
-
-
-
-
-
-
-
-
-
SD0CMD -
-
-
SEG19 -
D5
69
B3
47
B3
29 29
-
-
P303 A08 -
-
GTIOC7B -
-
-
-
-
-
SD0DAT0 -
-
-
SEG3/ TS2
COM7
A2
70
D5
48
B2
30 30
-
IRQ5
P302 A07 -
GTOUUP
GTIOC4A -
-
TXD2/ MOSI2
/SDA2
SSLB3
-
-
-
-
-
SEG2/ TS8
COM6
C3
71
A2
49
C2
31 31
-
IRQ6
P301 A06 AGTIO0 GTOULO
GTIOC4B -
-
RXD2/ MISO2
/SCL2
CTS9_
RTS9/
SS9
SSLB2
-
-
-
-
-
SEG1/ TS9
COM5
B2
72
A1
50
A2
32 32
TCK/
SWCLK
-
P300 -
-
GTOUUP
GTIOC0A -
-
-
-
SSLB1
-
-
-
-
-
-
-
A1
73
B2
51
A1
33 33
TMS/
SWDIO
-
P108 -
-
GTOULO
GTIOC0B -
-
CTS9_ RTS9/
SS9
SSLB0
-
-
-
-
-
-
-
D4
74
B1
52
B1
34 34
TDO/SWO/ CLKOUT
P109 -
-
GTOVUP
GTIOC1A -
CTX0 SCK1 TXD9/
MOSI9
/SDA9
MOSIB
-
-
-
-
-
SEG52 TS10
B1
75
C3
53
C3
35 35
TDI
IRQ3
P110
-
-
GTOVLO
GTIOC1B -
CRX0 CTS2_ RTS2/
SS2
RXD9/
MISO9
/SCL9
MISOB
-
-
-
-
VCOUT SEG53 -
C2
76
D3
54
D3
36 36
-
IRQ4
P111
A05 -
-
GTIOC3A -
-
SCK2
SCK9
RSPCKB -
-
-
-
-
CAPH TS12
D3
77
C1
55
C1
37 37
-
-
P112
A04 -
-
GTIOC3B -
-
TXD2/ MOSI2
/SDA2
SCK1
SSLB0
SSIBCK0
-
-
-
-
CAPL
C1
78
C2
56
E5
38 38
-
-
P113
A03 -
-
GTIOC2A -
-
RXD2/ MISO2
/SCL2
-
SSILRCK0 /SSIFS0
-
-
-
SEG0/ TS27
COM4
E4
79
D4
57
D2
-
-
-
-
P114
A02 -
-
GTIOC2B -
-
-
-
-
SSIRXD0 -
-
-
-
SEG24 TS29
E3
80
D1
58
E4
-
-
-
-
P115
A01 -
-
GTIOC4A -
-
-
-
-
SSITXD0
-
-
-
-
SEG25 TS35
D2
81
-
-
-
-
-
-
-
P806 -
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG26 -
D1
82
-
-
-
-
-
-
-
P807 -
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG27 -
F4
83
D2
59
D1
-
-
-
-
P608 A00/ BC0
-
GTIOC4B -
-
-
-
-
-
SD0DAT1 -
-
-
SEG28 -
E2
84
E3
60
E3
-
-
-
-
P609 CS1 -
-
GTIOC5A -
-
-
-
-
-
SD0DAT2 -
-
-
SEG29 -
F3
85
E1
61
E2
-
-
-
-
P610 CS0 -
-
GTIOC5B -
-
-
-
-
-
SD0DAT3 -
-
-
SEG30 -
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
-
TSCAP
Page 71 of 1619
S3A1 User’s Manual
CTSU
SLCDC
ACMPLP
ADC14
SDHI
SSIE
HMI
DAC12, OPAMP
Analog
SPI/QSPI
IIC
SCI
USBFS, CAN
RTC
GPT
GPT_OPS, POEG
Communication interfaces
AGT
I/O port
Interrupt
External bus
Timers
Power, System, Clock,
Debug, CAC, VBATT
QFN64
LQFP64
LGA100
LQFP100
BGA121
LQFP144
LGA145
Pin number
1. Overview
E1
86
E4
-
-
-
-
-
-
P611
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG31 -
F2
87
F5
-
-
-
-
-
-
P612 D08 -
-
-
-
-
-
-
-
-
-
-
-
-
SEG32 -
F1
88
E2
-
-
-
-
-
-
P613 D09 -
-
-
-
-
-
-
-
-
-
-
-
-
SEG33 -
-
-
-
-
-
-
P614 D10 -
-
-
-
-
-
-
-
-
-
-
-
-
SEG34 -
G3 89
G1 90
F1
62
E1
39 39
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G2 91
G1
63
F1
40 40
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H1
92
-
-
-
-
-
-
-
P606 -
-
-
-
RTCOUT -
-
-
-
-
-
-
-
-
SEG35 -
H2
93
F2
-
-
-
-
-
-
P605 D11 -
-
GTIOC8A -
-
-
-
-
-
-
-
-
-
SEG36 -
G4 94
F3
-
-
-
-
-
-
P604 D12 -
-
GTIOC8B -
-
-
-
-
-
-
-
-
-
SEG37 -
H3
95
F4
64
F2
-
-
-
-
P603 D13 -
-
GTIOC7A -
-
CTS9_ RTS9/
SS9
-
-
SD0DAT4 -
-
-
SEG38 -
J1
96
G2
65
F3
-
-
-
-
P602 EBC LK
-
GTIOC7B -
-
TXD9/ MOSI9
/SDA9
-
-
SD0DAT5 -
-
-
SEG39 -
J2
97
G5
66
F4
-
-
-
-
P601 WR/ WR0
-
GTIOC6A -
-
RXD9/ MISO9
/SCL9
-
-
SD0DAT6 -
-
-
SEG40 -
H4
98
G4
67
F5
-
-
-
-
P600 RD
-
-
GTIOC6B -
-
SCK9
-
-
-
SD0DAT7 -
-
-
SEG41 -
K2
99
-
-
-
-
-
-
-
P805
-
-
GTIOC9A -
-
-
-
-
-
-
-
-
-
SEG42 -
K1
100 -
-
-
-
-
-
-
P804
-
-
GTIOC9B -
-
-
-
-
-
-
-
-
-
SEG43 -
J3
101 H1
68
G3
41 41
-
KR07
P107 D07 -
-
GTIOC8A -
-
-
-
-
-
-
-
-
-
COM3 -
K3
102 G3
69
G2
42 42
-
KR06
P106 D06 -
-
GTIOC8B -
-
-
-
SSLA3
-
-
-
-
-
COM2 -
J4
103 H2
70
G1
43 43
-
KR05/ P105 D05 IRQ0
GTETRGA GTIOC1A -
-
-
-
SSLA2
-
-
-
-
-
COM1 TS34
L3
104 H3
71
H1
44 44
-
KR04/ P104 D04 IRQ1
GTETRGB GTIOC1B -
-
RXD0/ MISO0
/SCL0
SSLA1
-
-
-
-
-
COM0 TS13
L1
105 J1
72
H3
45 45
-
KR03
P103 D03 -
GTOWUP GTIOC2A -
CTX0 CTS0_ RTS0/
SS0
SSLA0
-
-
AN019 -
CMPRE VL4
F1
-
M1 106 J2
73
J1
46 46
-
KR02
P102 D02 AGTO0
GTOWLO GTIOC2B -
CRX0 SCK0 TXD2/
MOSI2
/SDA2
RSPCKA -
-
AN020/ ADTR
G0
CMPIN1 VL3
-
M2 107 K1
74
H2
47 47
-
KR01/ P101 D01 AGTEE0 GTETRGB GTIOC5A IRQ1
-
TXD0/ SDA1
MOSI0
/SDA0
CTS1_
RTS1/
SS1
MOSIA
-
-
AN021 -
CMPRE VL2
F0
-
N1
108 L1
75
H4
48 48
-
KR00/ P100 D00 AGTIO0 GTETRGA GTIOC5B IRQ2
-
RXD0/ SCL1
MISO0
/SCL0
SCK1
MISOA
-
-
AN022 -
CMPIN0 VL1
-
L2
109 L2
-
-
-
-
-
-
P800 D14 -
-
-
-
-
-
-
-
-
-
-
-
-
SEG44 -
N2
110 K2
-
-
-
-
-
-
P801 D15 -
-
-
-
-
-
-
-
-
-
-
-
-
SEG45 -
N3
111 -
-
-
-
-
-
-
P802 -
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG46 -
M3 112 -
-
-
-
-
-
-
P803 -
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG47 -
K4
113 K3
76
K1
49 49
-
-
P500 -
AGTOA0 GTIU
GTIOC2A -
USB_ VBUS
EN
-
QSPCLK -
-
AN016 -
CMPRE SEG48 F1
M4 114 L3
77
J2
50 50
-
IRQ11 P501 -
AGTOB0 GTIV
GTIOC2B -
USB_ TXD3/ OVR MOSI3
CUR /SDA3
A
QSSL
-
-
AN017 -
CMPIN1 SEG49 -
L4
78
K2
51 51
-
IRQ12 P502 -
-
GTIOC3B -
USB_ RXD3/ OVR MISO3
CUR /SCL3
B
QIO0
-
-
AN018 -
CMPRE SEG50 F0
115 J3
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
GTIW
Page 72 of 1619
S3A1 User’s Manual
CTSU
SLCDC
ACMPLP
ADC14
SDHI
SSIE
HMI
DAC12, OPAMP
Analog
SPI/QSPI
IIC
SCI
USBFS, CAN
RTC
GPT
GPT_OPS, POEG
Communication interfaces
AGT
I/O port
Interrupt
External bus
Timers
Power, System, Clock,
Debug, CAC, VBATT
QFN64
LQFP64
LGA100
LQFP100
BGA121
LQFP144
LGA145
Pin number
1. Overview
K5
116 J4
79
G4
-
-
-
-
P503 -
-
GTETRGA -
-
USB_ CTS2_ EXIC RTS2/
SS2
EN
SCK3
QIO1
-
-
AN023 -
CMPIN0 SEG51 -
L5
117 H4
80
G5
-
-
-
-
P504 ALE -
GTETRGB -
-
USB_ SCK2 ID
CTS3_
RTS3/
SS3
QIO2
-
-
AN024 -
-
-
-
K6
118 J5
81
G6
-
-
-
IRQ14 P505 -
-
-
-
-
-
RXD2/ MISO2
/SCL2
QIO3
-
-
AN025 -
-
-
-
L6
119 H5
-
-
-
-
-
IRQ15 P506 -
-
-
-
-
-
TXD2/ MOSI2
/SDA2
-
-
-
AN026 -
-
-
-
N4
120 -
-
-
-
-
-
-
P507 -
-
-
-
-
-
-
-
-
-
-
AN027 -
-
-
-
N5
121 L4
82
K3
-
-
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M5 122 K4
83
J3
-
-
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M6 123 K5
84
J4
52 52
-
IRQ7
P015 -
-
-
-
-
-
-
-
-
-
-
AN010 -
-
-
TS28
N6
124 L5
85
K4
53 53
-
-
P014 -
-
-
-
-
-
-
-
-
-
-
AN009 DA0
-
-
-
M7 125 K6
86
J5
54 54
VREFL
-
P013 -
-
-
-
-
-
-
-
-
-
-
AN008 AMP1+ -
-
-
N7
126 L6
87
K5
55 55
VREFH
-
P012 -
-
-
-
-
-
-
-
-
-
-
AN007 AMP1-
-
-
-
L7
127 J6
88
H5
56 56
AVCC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L8
128 J7
89
H6
57 57
AVSS0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M8 129 K7
90
J6
58 58
VREFL0
IRQ15 P011
-
-
-
-
-
-
-
-
-
-
-
AN006 AMP2+ -
-
TS31
N8
91
K6
59 59
VREFH0
IRQ14 P010 -
-
-
-
-
-
-
-
-
-
-
AN005 AMP2-
-
-
TS30
M9 131 -
-
-
-
-
-
IRQ13 P009 -
-
-
-
-
-
-
-
-
-
-
AN015 -
-
-
-
N9
132 H6
92
J7
-
-
-
IRQ12 P008 -
-
-
-
-
-
-
-
-
-
-
AN014 -
-
-
-
K7
133 H7
93
H7
-
-
-
P007 -
-
-
-
-
-
-
-
-
-
-
AN013 AMP3O -
-
-
L9
134 H8
94
G7
-
-
-
IRQ11 P006 -
-
-
-
-
-
-
-
-
-
-
AN012 AMP3-
-
-
-
K8
135 L8
95
K7
-
-
-
IRQ10 P005 -
-
-
-
-
-
-
-
-
-
-
AN011 AMP3+ -
-
-
K9
136 J8
96
J8
60 60
-
IRQ3
-
-
-
-
-
-
-
-
-
-
AN004 AMP2O -
-
-
130 L7
P004 -
K10 137 K8
97
H8
61 61
-
-
P003 -
-
-
-
-
-
-
-
-
-
-
AN003 AMP1O -
-
-
M1 138 J9
0
98
K8
62 62
-
IRQ2
P002 -
-
-
-
-
-
-
-
-
-
-
AN002 AMP0O -
-
-
N10 139 K9
99
K9
63 63
-
IRQ7
P001 -
-
-
-
-
-
-
-
-
-
-
AN001 AMP0-
-
TS22
L10 140 L9
100 K10 64 64
-
IRQ6
P000 -
-
-
-
-
-
-
-
-
-
-
AN000 AMP0+ -
N11 141 -
-
-
-
-
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N12 142 -
-
-
-
-
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M11 143 L10 -
-
-
-
-
IRQ14 P512 -
-
-
GTIOC0A -
CTX0 TXD4/ SCL2
MOSI4
/SDA4
-
-
-
-
-
-
-
-
M1 144 K10 2
-
-
-
-
IRQ15 P511
-
-
-
GTIOC0B -
CRX0 RXD4/ SDA2
MISO4
/SCL4
-
-
-
-
-
-
-
-
E5
-
-
-
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F6
-
-
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
-
-
-
-
TS21
Page 73 of 1619
S3A1 User’s Manual
2.
2. CPU
CPU
The MCU is based on the Arm® Cortex®-M4 core.
2.1
2.1.1
Overview
CPU
Arm Cortex-M4
Revision: r0p1-01rel0
Armv7E-M architecture profile
Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.
Memory Protection Unit (MPU)
Armv7 Protected Memory System Architecture
8 protected regions.
SysTick timer
Driven by SYSTICCLK (LOCO) or ICLK.
See reference 1. and reference 2. in section 2.12 for details.
2.1.2
Debug
Arm CoreSight™ ETM™-M4
Revision: r0p1-00rel0
Arm ETM Architecture version 3.5.
CoreSight Instrumentation Trace Macrocell (ITM)
Data Watchpoint and Trace Unit (DWT)
4 comparators for watchpoints and triggers.
Flash Patch and Breakpoint Unit (FPB)
Flash Patch (Remap) function is unavailable, only Breakpoint function is available
6 instruction comparators
2 literal comparators.
CoreSight Time Stamp Generator (TSG)
Time stamp for ETM and ITM
Driven by CPU clock.
Debug Register Module (DBGREG)
Reset control
Halt control.
CoreSight Debug Access Port (DAP)
JTAG Debug Port (JTAG-DP)
Serial Wire Debug Port (SW-DP).
Cortex-M4 Trace Port Interface Unit (TPIU)
Serial Wire Output (SWO).
CoreSight Embedded Trace Buffer (ETB)
CoreSight Trace Memory Controller with ETB configuration
Buffer size: 1 KB.
See reference 1. and reference 2. in section 2.12 for details.
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 74 of 1619
S3A1 User’s Manual
2.1.3
2. CPU
Operating Frequency
The operating frequencies for the MCU are as follows:
CPU: maximum 48 MHz
Serial Write Output (SWO) trace interface: maximum 12.5 MHz
Joint Test Action Group (JTAG) interface: maximum 12.5 MHz
Serial Wire Debug (SWD) interface: maximum 12.5 MHz.
Figure 2.1 shows the block diagram of the Cortex-M4 CPU.
OCD access
Trace/debug data
From: OCD emulator (JTAG/SWD)
From: System bus
Cortex-M4 integration
Cortex-M4
SWJ-DP
DAP IC
TS Gen
Cortex-M4
core
(DPU)
APB-AP
NVIC
ETM
DBGREG
To: System control
DWT
MPU
OCDREG
ITM
AHB-AP
FPB
Bus matrix
Funnel
ETB
M4-TPIU
AHB2APB
To: System bus
Figure 2.1
ROM Table
To: Trace pin (SWO)
Cortex-M4 CPU block diagram
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 75 of 1619
S3A1 User’s Manual
2.2
2. CPU
MCU Implementation Options
Table 2.1 shows the implementation options for the MCU and is based on the configurable options in reference 2.
Table 2.1
Implementation options
Option
Implementation
MPU
Included, 8 protected regions
FPB
Flash Patch (Remap) function is unavailable, only Breakpoint function is available
DWT
Included
ITM
Included
ETM
Included
AHB-AP
Included
HTM interface
Not included
TPIU
Included (only Serial Wire Output)
WIC
Not included
The ICU can wake up the CPU instead of the Wakeup Interrupt Controller (WIC). For more details,
see section 14, Interrupt Controller Unit (ICU).
Debug Port
SWJ-DP
FPU
Included
Number of interrupts
64
Number of priority bits
4 bits (16 levels)
Endianness
Little-endian
Time Stamp Generator
Included
ETB
Included
Sleep mode power saving
Sleep mode and other low power modes are supported. For details, see section 11, Low Power
Modes. SCB.SCR.SLEEPDEEP is ignored.
Memory features
Cacheable attribute is utilized in the MCU. See section 15, Buses for more details.
SysTick Timer
SYST_CALIB = 4000 0147h
Bit [31] = 0
Reference clock provided
Bit [30] = 1
TERMS value is inexact
Bits [29:24] = 00h
Reserved
Bits [23:0] = 000147h TERM: (32768 × 10 ms) - 1/32.768 kHz
= 326.66 decimal
= 327 with skew
= 000147h
Event input/output
Not implemented
System reset request output
The SYSRESETREQ bit in the Application Interrupt and Reset Control Register causes a CPU
reset
Auxiliary fault inputs, AUXFAULT
Not implemented
2.3
Trace Interface
A Serial Wire Output (SWO) provides trace output. Table 2.2 shows the MCU pin for the trace function. This pin is
multiplexed with other functions.
Table 2.2
Trace function pin
Name
I/O
Width
Function
When not in use
TDO/SWO
Output
1 bit
Serial wire output multiplexed with JTAG TDO pin
Open
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 76 of 1619
S3A1 User’s Manual
2.4
2. CPU
JTAG/SWD Interface
Table 2.3 shows the JTAG/Serial Wire Data (SWD) pins.
Table 2.3
JTAG/SWD pins
Name
I/O
P/N
Width
Function
When not in use
TCK/SWCLK
Input
Positive
1 bit
JTAG clock pin/SWD clock pin
Pull-up
TMS/SWDIO
I/O
Negative
1 bit
JTAG TMS pin/SWD I/O pin
Pull-up
TDI
Input
Positive
1 bit
JTAG TDI pin
Pull-up
TDO/SWO
Output
Negative
1 bit
JTAG TDO pin multiplexed with SWO pin
Open
2.5
Debug Mode
2.5.1
Debug Mode Definition
In single chip mode, the debugger connection state is defined as OCD (On-Chip Debugger) mode, and the non-connected
debugger state is defined as User mode. Table 2.4 shows the CPU debug modes and usage conditions.
Table 2.4
CPU debug mode and conditions
Conditions
Mode
OCD connect
JTAG/SWD authentication
Debug mode
Debug authentication
Not connected
-
User mode
Disabled
Connected
Failed
User mode
Disabled
Connected
Passed
OCD mode
Enabled
Note 1.
Note 2.
OCD connect is determined by the CDBGPWRUPREQ bit output in the SWJ-DP register. The bit can only be written by the
OCD. However, the level of the bit can be confirmed by reading the DBGSTR.CDBGPWRUPREQ bit.
Debug authentication is defined by the Armv7-M architecture. Enabled means that both invasive and non-invasive CPU
debugging are permitted. Disabled means that both are not permitted.
2.5.2
Debug Mode Effects
This section describes the effects of debug mode, which occur both internally and externally to the CPU.
2.5.2.1
Low power mode
All CoreSight debug components can store register settings even when the CPU enters Software Standby mode or
Snooze mode. However, AHB-AP cannot respond to On-Chip Debug (OCD) access in these low power modes. The
OCD must wait for cancellation of the low power mode to access the CoreSight debug components. To request low
power mode cancellation, the OCD can set the DBIRQ bit in the MCUCTRL register. See section 2.6.5.3, MCU Control
Register (MCUCTRL) for details.
2.5.2.2
Reset
In OCD mode, some resets depend on the CPU status and the DBGSTOPCR setting.
Table 2.5
Reset or interrupt and mode setting (1 of 2)
Control in On-Chip Debug (OCD) mode
Reset or interrupt name
OCD break mode
RES pin reset
Same as user mode
Power-on reset
Same as user mode
Independent watchdog timer reset or interrupt
Does not occur*1
Depends on DBGSTOPCR setting*2
Watchdog timer reset or interrupt
Does not occur*1
Depends on DBGSTOPCR setting*2
Voltage monitor 0 reset
Depends on DBGSTOPCR setting*3
Voltage monitor 1 reset or interrupt
Depends on DBGSTOPCR setting*3
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Table 2.5
2. CPU
Reset or interrupt and mode setting (2 of 2)
Control in On-Chip Debug (OCD) mode
Reset or interrupt name
OCD break mode
Voltage monitor 2 reset or interrupt
Depends on DBGSTOPCR setting*3
SRAM parity error reset or interrupt
Depends on DBGSTOPCR setting*3
SRAM ECC error reset or interrupt
Depends on DBGSTOPCR setting*3
MPU bus master reset or interrupt
Same as user mode
MPU bus slave reset or interrupt
Same as user mode
Stack pointer error reset or interrupt
Same as user mode
Software reset
Same as user mode
Note:
Note 1.
Note 2.
Note 3.
OCD run mode
In OCD break mode, the CPU is halted. In OCD run mode, the CPU is in OCD mode and the CPU is not halted.
The IWDT and WDT always stop in this mode.
The IWDT and WDT operation depends on the DBGSTOPCR setting.
Reset or interrupt masking depends on the DBGSTOPCR setting.
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2.6
2. CPU
Programmers Model
2.6.1
Address Spaces
The MCU debug system includes two CoreSight Access Ports (AP):
AHB-AP, which is connected to the CPU bus matrix and has the same access to the system address space as the
CPU
APB-AP, which has a dedicated address space (OCD address space) and is connected to the OCD register.
Figure 2.2 shows a block diagram of the AP connection and address spaces.
JTAG/SWD
Port 0
SWJ-DP
AHB-AP
System address space
(through CPU bus matrix)
DBGREG
DAP
IC
OCD address space
Port 1
APB-AP
OCDREG
Figure 2.2
JTAG/SWD authentication block diagram
For debugging purposes, there are two register modules, DBGREG and OCDREG. DBGREG is located in the system
address space and can be accessed from the OCD emulator, the CPU, and other bus masters in the MCU. OCDREG is
located in the OCD address space and can be accessed only from the OCD tool. The CPU and other bus masters cannot
access the OCD registers.
2.6.2
Cortex-M4 Peripheral Address Map
In the system address space, the Cortex-M4 core has a Private Peripheral Bus (PPB) that can only be accessed from the
CPU and OCD emulator. The PPB is expanded from the Cortex-M4 original implementation for the MCU. Table 2.6
shows the address map of the MCU.
Table 2.6
Cortex-M4 peripheral address map
Component name
Start address
End address
Note
ITM
E000 0000h
E000 0FFFh
See reference 2.
DWT
E000 1000h
E000 1FFFh
See reference 2.
FPB
E000 2000h
E000 2FFFh
See reference 2.
SCS
E000 E000h
E000 EFFFh
See reference 2.
TPIU
E004 0000h
E004 0FFFh
See reference 2.
ETM
E004 1000h
E004 1FFFh
See reference 5.
ATB funnel
E004 2000h
E004 2FFFh
See section 2.7 and reference 4.
ETB
E004 3000h
E004 3FFFh
See reference 6.
Time Stamp Generator
E004 4000h
E004 4FFFh
See section 2.10 and reference 4.
ROM Table
E00F F000h
E00F FFFFh
See section 2.6.3 and reference 7.
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2.6.3
2. CPU
CoreSight ROM Table
The MCU contains one CoreSight ROM Table, which lists all components implemented in the user area.
2.6.3.1
ROM entries
Table 2.7 shows the ROM entries in the CoreSight ROM table. The OCD emulator can use the ROM entries to determine
which components are implemented in a system. See reference 7. for details.
Table 2.7
CoreSight ROM Table
#
Address
Access size
R/W
Value
Target module
0
E00F F000h
32 bits
R
FFF0F003
SCS
1
E00F F004h
32 bits
R
FFF02003
DWT
2
E00F F008h
32 bits
R
FFF03003
FPB
3
E00F F00Ch
32 bits
R
FFF01003
ITM
4
E00F F010h
32 bits
R
FFF41003
TPIU
5
E00F F014h
32 bits
R
FFF42003
ETM
6
E00F F018h
32 bits
R
FFF43003
Funnel
7
E00F F01Ch
32 bits
R
FFF44003
ETB
8
E00F F020h
32 bits
R
FFF45003
TSG
9
E00F F024h
32 bits
R
00000000
(End of entries)
2.6.3.2
CoreSight component registers
The CoreSight ROM Table lists the CoreSight component registers defined in the Arm CoreSight architecture.
Table 2.8 lists these registers. See reference 7. for details on each register.
Table 2.8
CoreSight component registers in the CoreSight ROM Table
Name
Address
Access size
R/W
Initial value
DEVTYPE
E00F FFCCh
32 bits
R
0000_0001h
PID4
E00F FFD0h
32 bits
R
0000_0004h
PID5
E00F FFD4h
32 bits
R
0000_0000h
PID6
E00F FFD8h
32 bits
R
0000_0000h
PID7
E00F FFDCh
32 bits
R
0000_0000h
PID0
E00F FFE0h
32 bits
R
0000_001Dh
PID1
E00F FFE4h
32 bits
R
0000_0030h
PID2
E00F FFE8h
32 bits
R
0000_000Ah
PID3
E00F FFECh
32 bits
R
0000_0000h
CID0
E00F FFF0h
32 bits
R
0000_000Dh
CID1
E00F FFF4h
32 bits
R
0000_0010h
CID2
E00F FFF8h
32 bits
R
0000_0005h
CID3
E00F FFFCh
32 bits
R
0000_00B1h
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2.6.4
2. CPU
DBGREG Module
The DBGREG module controls the debug functionalities and is implemented as a CoreSight-compliant component.
Table 2.9 shows the DBGREG registers other than the CoreSight component registers.
Table 2.9
Non-CoreSight DBGREG registers
Name
DAP port
Address
Access size
R/W
Debug Status Register
DBGSTR
Port 0
4001 B000h
32 bits
R
Debug Stop Control Register
DBGSTOPCR
Port 0
4001 B010h
32 bits
R/W
Trace Control Register
TRACECTR
Port 0
4001 B020h
32 bits
R/W
2.6.4.1
Debug Status Register (DBGSTR)
Address(es): DBG.DBGSTR 4001 B000h
b31
b30
—
—
0
0
0
b15
b14
—
0
Value after reset:
Value after reset:
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CDBGPW CDBGPW
RUPACK RUPREQ
Bit
Symbol
Bit name
Description
R/W
b27 to b0
—
Reserved
These bits are read as 0
R
b28
CDBGPWRUPREQ
Debug power-up
request
0: OCD is not requesting debug power up
1: OCD is requesting debug power up.
R
b29
CDBGPWRUPACK
Debug power-up
acknowledge
0: Debug power-up request is not acknowledged
1: Debug power-up request is acknowledged.
R
b31, b30
—
Reserved
These bits are read as 0
R
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2.6.4.2
2. CPU
Debug Stop Control Register (DBGSTOPCR)
Address(es): DBG.DBGSTOPCR 4001 B010h
b31
b30
b29
b28
b27
b26
—
—
—
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
Value after reset:
b25
b24
b23
b22
b21
b20
b19
—
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
DBGST DBGST
OP_RE OP_RP
ER
CCR
b18
b16
DBGSTOP_LVD[2:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
b17
0
0
b1
b0
DBGST DBGST
OP_W OP_IW
DT
DT
1
1
Bit
Symbol
Bit name
Description
R/W
b0
DBGSTOP_IWDT
Mask bit for IWDT reset
or interrupt
0: Enable IWDT reset or interrupt
1: Mask IWDT reset or interrupt and stop WDT count when
CPU is in OCD break mode.
R/W
b1
DBGSTOP_WDT
Mask bit for WDT reset
or interrupt
0: Enable WDT reset or interrupt
1: Mask WDT reset or interrupt and stop WDT count when
CPU is in OCD break mode.
R/W
b15 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
DBGSTOP_LVD[2:0]
Mask bit for LVD0 reset
0: Enable LVD0 reset
1: Mask LVD0 reset.
R/W
b17
Mask bit for LVD1 reset
or interrupt
0: Enable LVD1 reset or interrupt
1: Mask LVD1 reset or interrupt.
R/W
b18
Mask bit for LVD2 reset
or interrupt
0: Enable LVD2 reset or interrupt
1: Mask LVD2 reset or interrupt.
R/W
b23 to b19
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b24
DBGSTOP_RPER
Mask bit for SRAM parity
error reset or interrupt
0: Enable SRAM parity error reset or interrupt
1: Mask SRAM parity error reset or interrupt.
R/W
b25
DBGSTOP_RECCR
Mask bit for SRAM ECC
error reset or interrupt
0: Enable SRAM ECC error reset or interrupt
1: Mask SRAM ECC error reset or interrupt.
R/W
b31 to b26
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The Debug Stop Control Register (DBGSTOPCR) specifies the functional stop in OCD mode. All bits in the register are
regarded as 0 when the MCU is not in OCD mode.
2.6.4.3
Trace Control Register (TRACECTR)
Address(es): DBG.TRACECTR 4001 B020h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
ENETB
FULL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b30 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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2. CPU
Bit
Symbol
Bit name
b31
ENETBFULL
Enable bit for halt request on ETB full 0: ETB full does not cause a CPU halt
1: ETB full causes a CPU halt.
2.6.4.4
Description
R/W
R/W
DBGREG CoreSight component registers
The DBGREG module provides the CoreSight component registers defined in the Arm CoreSight architecture. Table
2.10 lists these registers. See reference 7. for details on each register.
Table 2.10
DBGREG CoreSight component registers
Name
Address
Access size
R/W
Initial value
PID4
4001 BFD0h
32 bits
R
0000_0004h
PID5
4001 BFD4h
32 bits
R
0000_0000h
PID6
4001 BFD8h
32 bits
R
0000_0000h
PID7
4001 BFDCh
32 bits
R
0000_0000h
PID0
4001 BFE0h
32 bits
R
0000_0005h
PID1
4001 BFE4h
32 bits
R
0000_0030h
PID2
4001 BFE8h
32 bits
R
0000_001Ah
PID3
4001 BFECh
32 bits
R
0000_0000h
CID0
4001 BFF0h
32 bits
R
0000_000Dh
CID1
4001 BFF4h
32 bits
R
0000_00F0h
CID2
4001 BFF8h
32 bits
R
0000_0005h
CID3
4001 BFFCh
32 bits
R
0000_00B1h
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2.6.5
2. CPU
OCDREG Module
The OCDREG module controls the On-Chip Debug (OCD) emulator functionalities and is implemented as a CoreSightcompliant component. Table 2.11 shows the OCDREG registers.
Table 2.11
OCDREG registers
Name
DAP port
Address
Access size
R/W
ID Authentication Code Register 0
IAUTH0
Port 1
8000 0000h
32 bits
W
ID Authentication Code Register 1
IAUTH1
Port 1
8000 0100h
32 bits
W
ID Authentication Code Register 2
IAUTH2
Port 1
8000 0200h
32 bits
W
ID Authentication Code Register 3
IAUTH3
Port 1
8000 0300h
32 bits
W
MCU Status Register
MCUSTAT
Port 1
8000 0400h
32 bits
R
MCU Control Register
MCUCTRL
Port 1
8000 0410h
32 bits
R/W
Note:
OCDREG is located in the dedicated OCD address space. This address map is independent from the system address map.
2.6.5.1
ID Authentication Code Register (IAUTH0 to 3)
Four authentication registers are provided for writing the 128-bit key. These registers must be written in sequential order
from IAUTH0 to IAUTH3. If the set of register writes is not compliant with this order, the result is unpredictable.
Only 32-bit writes are permitted. The initial value of the registers is all 1s. This means that JTAG/SWD access is initially
permitted when the ID code in the OSIS register has the initial value. See section 2.11.2, Unlock ID Code.
Address(es): IAUTH0 8000 0000h
b31
b0
IAUTH0: AID 31-0 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH1 8000 0100h
b31
b0
IAUTH1: AID 63-32 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH2 8000 0200h
b31
b0
IAUTH2: AID 95-64 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH3 8000 0300h
b31
b0
IAUTH3: AID 127-96 bits
Value after reset: 1
1
1
1
1
1
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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2.6.5.2
2. CPU
MCU Status Register (MCUSTAT)
Address(es): MCUSTAT 8000 0400h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
CPUST CPUSL AUTH
OPCLK EEP
1/0*1
1/0*1
0
Bit
Symbol
Bit name
Description
R/W
b0
AUTH
Authentication Status
0: Authentication failed
1: Authentication succeeded.
R
b1
CPUSLEEP
-
0: CPU is not in Sleep mode
1: CPU is in Sleep mode.
R
b2
CPUSTOPCLK
-
0: CPU clock is not stopped, indicating that the MCU is in
Normal mode or Sleep mode
1: CPU clock is stopped, indicating that the MCU is in Snooze
mode or Software Standby mode.
R
b31 to b3
—
Reserved
These bits are read as 0
R
Note 1.
Depends on the MCU status.
2.6.5.3
MCU Control Register (MCUCTRL)
Address(es): MCUCTRL 8000 0410h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
—
—
—
—
—
—
—
DBIRQ
—
—
—
—
—
—
—
EDBGR
Q
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
EDBGRQ
External Debug
Request
Writing 1 to the bit causes a CPU halt or debug monitor
exception.
0: Debug event not requested
1: Debug event requested.
When the EDBGRQ bit is set to 0 or the CPU is halted, the
EDBCRQ bit is cleared.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
DBIRQ
Debug Interrupt
Request
Writing 1 to the bit wakes up the MCU from low power mode.
0: Debug interrupt not requested
1: Debug interrupt requested.
The condition can be cleared by writing 0 to the DBIRQ bit.
R/W
b31 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Set DBIRQ and EDBGRQ to the same value.
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2.6.5.4
2. CPU
OCDREG CoreSight component registers
The OCDREG module provides the CoreSight component registers defined in the Arm CoreSight architecture. Table
2.12 lists these registers. See reference 7. for details on each register.
Table 2.12
OCDREG CoreSight component registers
Name
Address
Access size
R/W
Initial value
PID4
8000 0FD0h
32 bits
R
0000_0004h
PID5
8000 0FD4h
32 bits
R
0000_0000h
PID6
8000 0FD8h
32 bits
R
0000_0000h
PID7
8000 0FDCh
32 bits
R
0000_0000h
PID0
8000 0FE0h
32 bits
R
0000_0004h
PID1
8000 0FE4h
32 bits
R
0000_0030h
PID2
8000 0FE8h
32 bits
R
0000_000Ah
PID3
8000 0FECh
32 bits
R
0000_0000h
CID0
8000 0FF0h
32 bits
R
0000_000Dh
CID1
8000 0FF4h
32 bits
R
0000_00F0h
CID2
8000 0FF8h
32 bits
R
0000_0005h
CID3
8000 0FFCh
32 bits
R
0000_00B1h
2.7
CoreSight ATB Funnel
There is one CoreSight ATB funnel in the MCU. The funnel has two ATB slaves and one ATB master, and it selects the
debug trace source from ETM and ITM to ETB. Figure 2.3 shows the CoreSight ATB connection in the MCU.
ITM
ETM
ATB
Replicator
ATB
Replicator
ATB
Funnel
ETB
Figure 2.3
TPIU
CoreSight ATB connection
Table 2.13 shows the ATB slave connection for the funnel.
Table 2.13
ATB slave connection
ATB slave number
Connected trace source
#0
ITM
#1
ETM
See reference 4. for details on ATB and funnel.
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2.8
2. CPU
Flash Patch and Break Unit
The MCU has a flash patch and break unit. Breakpoint function is available, but flash patch (Remap) function is
unavailable. Therefore, do not set the REPLACE bits [31:30] in the FP_COMPn register to 0. Bit [28] of FP_REMAP
register is always set to 1. When writing to this register, write 1 to bit [28]. When reading this register, bit [28] is always
read as 1. See reference 1. for details.
2.9
SysTick System Timer
The SysTick system timer provides a simple 24-bit down counter. The reference clock for the timer can be selected as the
CPU clock (ICLK) or SysTick Timer clock (SYSTICCLK). See section 9, Clock Generation Circuit and reference 1.*1
for details.
Note 1. In reference 1., the clock names are as follows:
The IMPLEMENTATION DEFINED external reference clock is SYSTICCLK (LOCO).
The processor clock is ICLK.
2.10
CoreSight Time Stamp Generator
A CoreSight Time Stamp Generator provides a CPU clock-based timestamp to ITM and ETM. The 48 LSB bits of the
64-bit counter are used for the two components. See reference 4. for details.
2.11
OCD Emulator Connection
A JTAG/SWD authentication mechanism checks access permission for debug and MCU resources. To obtain full debug
functionality, a pass result of the authentication mechanism is required. Figure 2.4 shows a block diagram of the
authentication mechanism.
Emulator
host PC
MCU
OCD
emulator
JTAG/SWD
SWJ-DP
To: CPU bus
AHB-AP
APB-AP
OCDREG
Option-setting
memory
To: CPU debug
ID
comparator
IAUTH output
Unlock ID
Figure 2.4
Compare result
(debug enable)
Authentication mechanism block diagram
An ID comparator is available in the MCU for authentication. The comparator compares the 128-bit IAUTH output from
OCDREG and the 128-bit unlock ID code from the option-setting memory. When the two outputs are identical, the CPU
debug functions and system bus access from the OCD emulator are permitted.
2.11.1
DBGEN
After the OCD emulator gets access permission, the OCD emulator must set the DBGEN bit in the System Control OCD
Control Register (SYOCDCR). In addition, the OCD emulator must clear the DBGEN bit before disconnecting it. See
section 11, Low Power Modes for details.
2.11.2
Unlock ID Code
The unlock ID code is used for checking permissions for debug and access to on-chip resources. If the unlock ID code
matches the 128-bit data written in the ID Authentication Registers 0 to 3, the JTAG/SWD debugger obtains access
permission. Unlock ID code is written in the OCD/Serial Programmer ID Setting Register (OSIS) in the option-setting
memory. The initial value of the unlock ID code is all 1s (FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFFh). See section
7, Option-Setting Memory for details.
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2.11.3
2. CPU
Restrictions on Connecting an OCD Emulator
This section describes the restrictions on emulator access.
2.11.3.1
Starting connection while in low power mode
When starting a JTAG/SWD connection from an OCD emulator, the MCU must be in Normal or Sleep mode. If the
MCU is in Software Standby or Snooze mode, the OCD emulator can cause the MCU to hang.
2.11.3.2
Changing low power mode while in OCD mode
When the MCU is in OCD mode, the low power mode can be changed. However, system bus access from AHB-AP is
prohibited in Software Standby or Snooze mode. Only SWJ-DP, APB-AP, and OCDREG can be accessed from the OCD
emulator in these modes. Table 2.14 shows the restrictions.
Table 2.14
Restrictions by mode
Active mode
Start OCD emulator
connection
Change low power
mode
Access AHB-AP and
system bus
Access APB-AP and
OCDREG
Normal
Yes
Yes
Yes
Yes
Sleep
Yes
Yes
Yes
Yes
Software Standby
No
Yes
No
Yes
Snooze
No
Yes
No
Yes
If system bus access is required in Software Standby or Snooze mode, set the MCUCTRL.DBIRQ bit in OCDREG to
wake up the MCU from the low power modes. Simultaneously, using the MCUCTRL.EDBGRQ bit in OCDREG, the
OCD emulator can wake up the MCU without starting CPU execution by using a CPU break.
2.11.3.3
Modifying the unlock ID code in OSIS
After modifying the unlock ID code in OSIS, the OCD emulator must reset the MCU by asserting the RES pin or setting
the SYSRESETREQ bit of the Application Interrupt and Reset Control Register in the system control block to 1. The
modified unlock ID code is reflected after reset.
2.11.3.4
Connecting sequence and JTAG/SWD authentication
Because the OCD emulator is protected by the JTAG/SWD authentication mechanism, the OCD might be required to
input the ID code to the authentication registers. The OSIS value in the option-setting memory determines whether the
code is required. After negation of the reset, a 44 μs wait time is required before comparing the OSIS value at cold start.
(1)
When MSB of OSIS is 0 (bit [127] = 0)
The ID code is always mismatching, and connection to the OCD is prohibited.
(2)
When OSIS is all 1s (default)
OCD authentication is not required and the OCD can use the AHB-AP without authentication.
1. Connect the OCD emulator to the MCU through the JTAG or SWD interface.
2. Set up SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert the CDBGPWRUPREQ bit in
the SWJ-DP Control Status Register, then wait until CSDBGPWRUPACK in the same register is asserted.
3. Set up the AHB-AP to access the system address space. The AHB-AP is connected to DAP bus port 0.
4. Start accessing the CPU debug resources using the AHB-AP.
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(3)
2. CPU
When OSIS[127:126] is 10b
OCD authentication is required and the OCD must write the unlock ID code to the IAUTH registers 0 to 3 in OCDREG
before using the AHB-AP.
1. Connect the OCD debugger to the MCU through the JTAG or SWD interface.
2. Set up SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in SWJ-DP
Control Status Register, then wait until CSDBGPWRUPACK in the same register is asserted.
3. Set up APB-AP to access OCDREG. The APB-AP is connected to the DAP bus port 1.
4. Write the 128-bit ID code to IAUTH registers 0 to 3 in OCDREG using APB-AP.
5. If the 128-bit ID code matches the OSIS value, the AHB-AP is authorized to issue an AHB transaction. The
authorization result can be confirmed in the AUTH bit in the MCUSTAT Register or the DbgStatus bit in the AHBAP Control Status Word Register.
When the DbgStatus bit is 1, the 128-bit ID code is a match with the OSIS value. AHB transfers are permitted.
When the DbgStatus bit is 0, the 128-bit ID code is not a match with the OSIS value. AHB transfers are not
permitted.
6. Set up the AHB-AP to access the system address space. The AHB-AP is connected to the DAP bus port 0.
7. Start accessing the CPU debug resources using the AHB-AP.
(4)
When OSIS[127:126] is 11b
OCD authentication is required and the OCD must write the unlock ID code to IAUTH registers 0 to 3 in OCDREG. The
connection sequence is the same as when OSIS[127:126] is 10b, except for the “ALeRASE” capability.
When IATUH registers 0 to 3 are written with “ALeRASE” in ASCII code
(414C_6552_4153_45FF_FFFF_FFFF_FFFF_FFFFh), contents of the code flash, data flash, and configuration area are
erased immediately. See section 47, Flash Memory for details.
The ALeRASE sequence is as follows:
1. Connect the OCD debugger to the MCU through the JTAG or SWD interface.
2. Set up the SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in the
SWJ-DP Control Status Register, then wait until CSDBGPWRUPACK in the same register is asserted.
3. Set up the APB-AP to access OCDREG. This APB-AP is connected to the DAP bus port 1.
4.
Write the 128-bit ID code to IAUTH registers 0 to 3 in the OCDREG using APB-AP.
5. If the 128-bit ID code is “ALeRASE” in ASCII code, contents of the code flash, data flash, and configuration area
are erased. Thereafter, the MCU transitions to Sleep mode.
2.12
References
1. ARM®v7-M Architecture Reference Manual (ARM DDI 0403D).
2. ARM® Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D).
3. ARM® Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).
4. ARM® CoreSight™ SoC-400 Technical Reference Manual (ARM DDI 0480F).
5. ARM® CoreSight™ ETM-M4 Technical Reference Manual (ARM DDI 0440C).
6. ARM® CoreSight™ Trace Memory Controller Technical Reference Manual (ARM DDI 0461B).
7. ARM® CoreSight™ Architecture Specification (ARM IHI 0029D).
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3.
Operating Modes
3.1
Overview
3. Operating Modes
Table 3.1 shows the selection of operating modes by the mode-setting pin. For details, see section 3.2, Operating Mode
Details. Operation starts when the on-chip flash memory is enabled, regardless of the mode in which operation started.
Table 3.1
Selection of operating modes by the mode-setting pin
Mode-setting pin
MD
Operating mode
On-chip flash memory
1
Single-chip mode
Enable
0
SCI/USB boot mode
Enable
3.2
Operating Mode Details
3.2.1
Single-Chip Mode
In single-chip mode, all I/O pins are available for use as input or output ports, inputs or outputs for peripheral functions,
or as interrupt inputs. When a reset is released while the MD pin is high, the MCU starts in single-chip mode and the onchip flash is enabled.
3.2.2
SCI Boot Mode
In this mode, the on-chip flash memory programming routine (SCI boot program), stored in a dedicated area within the
MCU, is used. The on-chip flash, including the code flash memory and data flash memory, can be modified from outside
the MCU by using a Serial Communication Interface (SCI). For details, see section 47, Flash Memory. The MCU starts
up in SCI boot mode if the MD pin is held low on release from the reset state.
3.2.3
USB Boot Mode
In this mode, the on-chip flash memory programming routine (USB boot program), stored in the boot area within the
MCU, is used. The on-chip flash, including the code flash memory and data flash memory, can be modified from outside
the MCU by using the USB. For details, see section 47, Flash Memory. The MCU starts in USB boot mode if the MD pin
is held low on release from the reset state.
3.3
Operating Mode Transitions
3.3.1
Operating Mode Transitions as Determined by the Mode-Setting Pin
Figure 3.1 shows operating mode transitions determined by the MD pin settings.
MD = 1 and release RES pin
Release POR
Reset
RES pin or POR occurs
RES pin or POR occurs
MD = 0 and release RES pin
Single-chip mode
Figure 3.1
SCI boot mode
USB boot mode
Mode-setting pin level and operating mode
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4.
Address Space
4.1
Overview
4. Address Space
The MCU supports a 4-GB linear address space ranging from 0000 0000h to FFFF FFFFh, that can contain both
programs and data. Figure 4.1 shows the memory map.
FFFF FFFFh
System for Cortex®-M4
E000 0000h
Reserved area*2
8400 0000h
External address space
(CS area)
8000 0000h
Reserved area*2
6800 0000h
6000 0000h
407F B1A0h
407F B19Ch
407F 0000h
407E 0000h
External address space
(SPI area)
Reserved area*2
On-chip flash
(option-setting memory)
Reserved area*2
Flash I/O registers
Reserved area*2
4010 2000h
On-chip flash (data flash)
4010 0000h
Peripheral I/O registers
4000 0000h
Reserved area*2
2003 0000h
On-chip SRAM*1
2000 0000h
0280 0000h
0200 0000h
0101 0034h
0101 0008h
Reserved area*2
Memory mirror area
Reserved area*2
On-chip flash (option-setting memory)
Reserved area*2
0010 0000h
On-chip flash (program flash)
(read only)*1, *3
0000 0000h
Note 1.
Note 2.
Note 3.
Figure 4.1
The capacity of the flash or SRAM depends on the product.
Do not access reserved areas.
Some regions are reserved for the option-setting memory. For details, see section 7, Option-Setting Memory.
Memory map
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4.2
4. Address Space
External Address Space
The external address space is divided into CS areas (CS0 to CS3) and SPI area. The four CS areas (CS0 to CS3) each
corresponds to the CSn signal output from a CSn (n = 0 to 3) pin. The SPI area is divided into two areas, the QSPI I/O
registers, and external SPI device space.
Figure 4.2 shows the address ranges associated with the individual CS areas (CS0 to CS3) and SPI area.
83FF FFFFh
FFFF FFFFh
System for Cortex-M4
CS3 (16 MB)
E000 0000h
8300 0000h
82FF FFFFh
Reserved area*1
CS2 (16 MB)
8400 0000h
External address space
(CS area)
8200 0000h
81FF FFFFh
8000 0000h
CS1 (16 MB)
Reserved area*1
6800 0000h
6000 0000h
407F B1A0h
407F B19Ch
407F 0000h
407E 0000h
External address space
(SPI area)
8100 0000h
80FF FFFFh
CS0 (16 MB)
Reserved area*1
On-chip flash
(option-setting memory)
Reserved area*1
Flash I/O registers
8000 0000h
67FF FFFFh
QSPI I/O registers
Reserved area*1
6400 0000h
63FF FFFFh
4010 2000h
On-chip flash (data flash)
External SPI device
4010 0000h
Peripheral I/O registers
6000 0000h
4000 0000h
Reserved area*1
2003 0000h
On-chip SRAM
2000 0000h
0280 0000h
0200 0000h
0101 0034h
0101 0008h
Reserved area*1
Memory mirror area
Reserved area*1
On-chip flash (option-setting memory)
Reserved area*1
0010 0000h
On-chip flash (program flash)
(read only)
0000 0000h
Note 1.
Figure 4.2
Do not access reserved areas.
Association between external address spaces and CS areas
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5. Memory Mirror Function (MMF)
5.
Memory Mirror Function (MMF)
5.1
Overview
The MCU provides a Memory Mirror Function (MMF). You can configure the MMF to map an application image load
address in the code flash memory to the application image link address in the unused 23-bit memory mirror space
addresses. Your application code must be developed and linked to run from this MMF destination address. The
application code is not required to know the load location where it is stored in the code flash memory.
Table 5.1 lists the MMF specifications.
Table 5.1
MMF specifications
Parameter
Description
Memory mirror space
8 MB (0200 0000h to 027F FFFFh)
Memory mirror boundary
128 bytes
5.2
Register Descriptions
5.2.1
MemMirror Special Function Register (MMSFR)
Address(es): MMF.MMSFR 4000 1000h
b31
b30
b29
b28
b27
b26
b25
b24
KEY[7:0]
b23
b21
—
b20
b19
b18
b17
b16
MEMMIRADDR[15:9]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
0
0
0
0
0
0
0
Value after reset:
MEMMIRADDR[8:0]
0
Value after reset:
Bits
b22
0
0
Symbol
0
0
0
0
Bit name
0
0
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b22 to b7
MEMMIRADDR[15:0]
Memory Mirror Address
0000h to FFFFh (8 MB)
R/W
b23
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b31 to b24
KEY[7:0]
MMSFR Key Code
These bits enable or disable rewriting of the
MEMMIRADDR bits
R/W
MEMMIRADDR[15:0] bits (Memory Mirror Address)
The MEMMIRADDR[15:0] bits specify bits [22:7] of the memory mirror address. They define where the start address of
the memory mirror space addresses (0200 0000h) is linked to. Writing to these bits is enabled only when this register is
accessed in 32-bit units and the value DBh is written to the KEY[7:0] bits.
KEY[7:0] bits (MMSFR Key Code)
The KEY[7:0] bits enable or disable rewriting of the MEMMIRADDR[15:0] bits. Data written to the KEY[7:0] bits is
not saved. These bits are read as 0. The KEY code and MEMMIRADDR[15:0] bits must be written in the same cycle.
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5.2.2
5. Memory Mirror Function (MMF)
MemMirror Enable Register (MMEN)
Address(es): MMF.MMEN 4000 1004h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
KEY[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bits
Symbol
Bit name
Description
R/W
b0
EN
Memory Mirror Function Enable
0: Disable MMF
1: Enable MMF.
R/W
b23 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b31 to b24
KEY[7:0]
MMEN Key Code
These bits enable or disable rewriting of the EN bit
R/W
EN bit (Memory Mirror Function Enable)
Writing to the EN bit is enabled only when the MemMirror Enable register is accessed in 32-bit units and the value DBh
is written to the KEY[7:0] bits.
KEY[7:0] bits (MMEN Key Code)
The KEY[7:0] bits enable or disable rewriting of the EN bit. Data written to the KEY[7:0] bits is not saved. These bits
are read as 0. The KEY code and the EN bit must be written in the same cycle.
5.3
5.3.1
Operation
MMF Operation
The MMF links the memory mirror space (0200 0000h to 027F FFFFh) to the code flash area. If MMEN.EN = 1, the
CPU can access code flash using both normal addresses (starting at 0000 0000h) and memory mirror space addresses
(starting at 0200 0000h). Figure 5.1 shows an overview of the MMF. The MMSFR.MEMMIRADDR[15:0] bits specify
where the starting address of the memory mirror space addresses (0200 0000h) is linked to. Figure 5.2, Figure 5.3, and
Figure 5.4 show the MMF operation. Figure 5.5 shows the setting procedure of the MMF.
b31
b24 b23
Address bus
0
0
0
0
0
0
1
0
0
MemMirror SFR
—
—
—
—
—
—
—
—
—
Code flash address
0
0
0
0
0
0
0
0
0
b16
027F FFFFh - MEMMIRADDR
0200 0000h
Figure 5.1
b7
b0
0
0
Address bus[22:0] + MEMMIRADDR[22:0]
0
0
0
0
0
0
0
MEMMIRADDR - 1
0042 237Fh
Address bus + MemMir SFR
027F FFFFh - MEMMIRADDR + 1
b8
MEMMIRADDR[15:0]
027F FFFFh
Memory mirror space
addresses
b15
Memory mirror space [0200 0000h to 027F FFFFh]
8 MB code flash MAT
addresses
Example: MemMirrorSFR = 0042 2380h
Read from 0200 1000h = Code flash 0042 3380h
Read from 023E 8123h = Code flash 0000 A4A3h
0000 0000h
007F FFFFh
MEMMIRADDR
0042 2380h
MMF operation
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5. Memory Mirror Function (MMF)
Memory mirror space (fixed value)
MemMirror SFR
- : don’t care
CPU
Hex 0 0 4 2 2 3 8 0
32 bits
128-byte boundary
bin
0000 0010 0 - - - - - - - - - - - - - - - - - - - - - - -
Fixed value is acceptable
Fixed mirror area
In this case, it is 0200 0000h to 027F FFFFh
Address bus
9 bits
Comp
Adder*1
32 bits
9 bits
32 bits
Selector
32 bits
Code flash
Note 1.
Figure 5.2
For details, see Figure 5.4.
MMF block diagram
Figure 5.3 shows the addresses handled by each module. The Arm® MPU uses the original address of the CPU. The
Security MPU and code flash memory each use an address after conversion through the Memory Mirror Function.
CPU
Arm MPU
Original address of CPU
Memory Mirror Function
Security MPU
Conversion address by
Memory Mirror Function
Code flash memory
Figure 5.3
MMF address handling
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5. Memory Mirror Function (MMF)
Start
MMEN.EN = 1
Yes
Address bus [31:23] =
000000100b
Yes
No
Compare the address bus and the memory
mirror space (0200 0000h to 027F FFFFh)
No
Add the MEMMIRADDR to the address
bus
Code flash address [6:0] = Address bus [6:0]
Code flash address [22:7] = Address bus [22:7] +
MMSFR.MEMMIRADDR[15:0]
Code flash address [31:23] = 000000000b
Code flash address [31:0] = Address bus [31:0]
End
Figure 5.4
MMF operation flow
Figure 5.5
MMF setup flow
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5.3.2
5. Memory Mirror Function (MMF)
Setting Example
The target application code on the code flash can be accessed from the address of 0200 0000h on the memory mirror
space by setting up the code flash starting address in MMSFR.MEMMIRADDR[15:0] and setting MMEN.EN to 1.
Figure 5.6 shows an example of how to use the MMF.
027F FFFFh
Memory mirror space
0201 0000h
Application code
0200 0000h
003F FFFFh
Code flash
You can choose any version of the application code
in the MMSFR register
Application code ver3
0012 0000h
Application code ver2
0011 0000h
Application code ver1
0010 0000h
0001 0000h
Shared start up code
Jump to the application code after initialization
- Always the same address
0000 0000h
Figure 5.6
MMF setting example
Set the MMSFR register to DB10_0000h to use the application code ver1.
Set the MMSFR register to DB11_0000h to use the application code ver2.
Set the MMSFR register to DB12_0000h to use the application code ver3.
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6.
Resets
6.1
Overview
6. Resets
The MCU provides 14 resets:
RES pin reset
Power-on reset
VBATT-selected voltage power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
CPU stack pointer error reset
Software reset.
Table 6.1 lists the reset names and sources.
Table 6.1
Reset names and sources
Reset name
Source
RES pin reset
Voltage input to the RES pin is driven low
Power-on reset
VCC rise (voltage detection: VPOR)*1
VBATT-selected voltage power-on reset
VCC fall (voltage detection: VDETBATT)*1
Independent watchdog timer reset
IWDT underflow or refresh error
Watchdog timer reset
WDT underflow or refresh error
Voltage monitor 0 reset
VCC fall (voltage detection: Vdet0)*1
Voltage monitor 1 reset
VCC fall (voltage detection: Vdet1)*1
Voltage monitor 2 reset
VCC fall (voltage detection: Vdet2)*1
SRAM parity error reset
SRAM parity error detection
SRAM ECC error reset
SRAM ECC error detection
Bus master MPU error reset
Bus master MPU error detection
Bus slave MPU error reset
Bus slave MPU error detection
CPU stack pointer error reset
CPU stack pointer error detection
Software reset
Register setting (use the Arm® software reset bit, AIRCR.SYSRESETREQ)
Note 1.
For details on the voltages to be monitored (VPOR, Vdet0, Vdet1, Vdet2, and VDETBATT), see section 8, Low Voltage Detection
(LVD), section 12., Battery Backup Function, and section 51, Electrical Characteristics.
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6. Resets
The internal state and pins are initialized by a reset. Table 6.2 and Table 6.3 list the targets initialized by resets.
Table 6.2
Reset detect flags initialized by each reset source
Reset source
Flags to be initialized
RES pin
reset
Power-on
reset
Voltage
monitor 0
reset
Independent
watchdog
timer reset
Watchdog
timer reset
Voltage
monitor 1
reset
Voltage
monitor 2
reset
Software
reset
Power-On Reset Detect Flag (RSTSR0.PORF)
×
×
×
×
×
×
×
Voltage Monitor 0 Reset Detect Flag
(RSTSR0.LVD0RF)
×
×
×
×
×
×
Independent Watchdog Timer Reset Detect Flag
(RSTSR1.IWDTRF)
×
×
×
×
×
Watchdog Timer Reset Detect Flag
(RSTSR1.WDTRF)
×
×
×
×
×
Voltage Monitor 1 Reset Detect Flag
(RSTSR0.LVD1RF)
×
×
×
×
×
Voltage Monitor 2 Reset Detect Flag
(RSTSR0.LVD2RF)
×
×
×
×
×
Software Reset Detect Flag (RSTSR1.SWRF)
×
×
×
×
×
SRAM Parity Error Reset Detect Flag
(RSTSR1.RPERF)
×
×
×
×
×
SRAM ECC Error Reset Detect Flag
(RSTSR1.REERF)
×
×
×
×
×
Bus Slave MPU Error Reset Detect Flag
(RSTSR1.BUSSRF)
×
×
×
×
×
Bus Master MPU Error Reset Detect Flag
(RSTSR1.BUSMRF)
×
×
×
×
×
Stack Pointer Error Reset Detect Flag
(RSTSR1.SPERF)
×
×
×
×
×
Cold Start/Warm Start Determination Flag
(RSTSR2.CWSF)
×
×
×
×
×
×
×
Flags to be initialized
SRAM
parity error
reset
SRAM ECC
error reset
Bus master
MPU error
reset
Bus slave
MPU error
reset
CPU stack
pointer
error reset
VBATT_POR*1
Power-On Reset Detect Flag (RSTSR0.PORF)
×
×
×
×
×
×
Voltage Monitor 0 Reset Detect Flag
(RSTSR0.LVD0RF)
×
×
×
×
×
×
Independent Watchdog Timer Reset Detect Flag
(RSTSR1.IWDTRF)
×
×
×
×
×
×
Watchdog Timer Reset Detect Flag
(RSTSR1.WDTRF)
×
×
×
×
×
×
Voltage Monitor 1 Reset Detect Flag
(RSTSR0.LVD1RF)
×
×
×
×
×
×
Voltage Monitor 2 Reset Detect Flag
(RSTSR0.LVD2RF)
×
×
×
×
×
×
Software Reset Detect Flag (RSTSR1.SWRF)
×
×
×
×
×
×
SRAM Parity Error Reset Detect Flag
(RSTSR1.RPERF)
×
×
×
×
×
×
SRAM ECC Error Reset Detect Flag
(RSTSR1.REERF)
×
×
×
×
×
×
Bus Slave MPU Error Reset Detect Flag
(RSTSR1.BUSSRF)
×
×
×
×
×
×
Bus Master MPU Error Reset Detect Flag
(RSTSR1.BUSMRF)
×
×
×
×
×
×
CPU Stack Pointer Error Reset Detect Flag
(RSTSR1.SPERF)
×
×
×
×
×
×
Cold Start/Warm Start Determination Flag
(RSTSR2.CWSF)
×
×
×
×
×
×
Reset source
: Initialized to 0
×: Not initialized
Note 1.
For VBATT_POR details, see section 12, Battery Backup Function.
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Table 6.3
6. Resets
Module-related registers initialized by each reset source
Reset source
Registers to be initialized
RES pin
reset
Power-on
reset
Voltage
monitor 0
reset
Independent
watchdog
timer
reset
Watchdog
timer
reset
Voltage
monitor 1
reset
Voltage
monitor 2
reset
Software
reset
Watchdog timer registers
WDTRR, WDTCR, WDTSR,
WDTRCR, WDTCSTPR
Voltage monitor function 1
registers
LVD1CR0, LVCMPCR.LVD1E,
LVDLVLR.LVD1LVL
×
×
×
LVD1CR1/LVD1SR
×
×
×
LVD2CR0, LVCMPCR.LVD2E,
LVDLVLR.LVD2LVL
×
×
×
LVD2CR1/LVD2SR
×
×
×
SOSCCR
×
×
×
×
×
×
×
×
SOMCR
×
×
×
×
×
×
×
×
LOCOCR
×
×
×
×
×
×
×
×
LOCOUTCR
×
×
×
×
×
×
×
×
MOMCR
Realtime clock*2 register
×
×
×
×
×
×
×
×
AGT register
×
×
×
×
MPU register
Pin state (except XCIN/XCOUT pin)
Pin state (XCIN/XCOUT pin)
×
×
×
×
×
×
×
×
Voltage monitor function 2
registers
SOSC registers
LOCO registers
MOSC register
Battery backup registers
VBTCR1
×
×
×
×
×
×
×
VBTCR2, VBTSR,
VBTCMPCR, VBTLVDICR,
VBTWCTLR,
VBTWCH0OTSR,
VBTWCH1OTSR,
VBTWCH2OTSR, VBTICTLR,
VBTOCTLR, VBTWTER,
VBTWEGR, VBTWFR
×
×
×
×
×
×
×
×
VBTBKRn (n = 0 to 511)
×
×
×
×
×
×
×
×
SRAM
parity
error reset
SRAM
ECC error
reset
Bus
master
MPU error
reset
Bus slave
MPU error
reset
Stack
pointer
error reset
VBATT_
POR*3
Registers other than those shown, CPU, and internal state
Reset source
Registers to be initialized
Watchdog timer registers
WDTRR, WDTCR, WDTSR,
WDTRCR, WDTCSTPR
×
Voltage monitor function 1
registers
LVD1CR0, LVCMPCR.LVD1E,
LVDLVLR.LVD1LVL
×
×
×
×
×
×
LVD1CR1/LVD1SR
×
×
×
×
×
×
LVD2CR0, LVCMPCR.LVD2E,
LVDLVLR.LVD2LVL
×
×
×
×
×
×
LVD2CR1/LVD2SR
×
×
×
×
×
×
SOSCCR
×
×
×
×
×
*1
SOMCR
×
×
×
×
×
LOCOCR
×
×
×
×
×
LOCOUTCR
×
×
×
×
×
MOMCR
×
Realtime clock*2 register
×
×
×
×
×
×
AGT register
×
×
×
×
×
×
MPU register
×
×
×
×
Pin state (except XCIN/XCOUT pin)
×
Pin state (XCIN/XCOUT pin)
×
×
×
×
×
VBTCR1
×
×
×
×
×
×
VBTCR2, VBTSR,
VBTCMPCR, VBTLVDICR,
VBTWCTLR,
VBTWCH0OTSR,
VBTWCH1OTSR,
VBTWCH2OTSR, VBTICTLR,
VBTOCTLR, VBTWTER,
VBTWEGR, VBTWFR
×
×
×
×
×
VBTBKRn (n = 0 to 511)
×
×
×
×
×
×
Voltage monitor function 2
registers
SOSC registers
LOCO registers
MOSC register
Battery backup registers
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6. Resets
Reset source
Registers to be initialized
SRAM
parity
error reset
SRAM
ECC error
reset
Bus
master
MPU error
reset
Bus slave
MPU error
reset
Stack
pointer
error reset
VBATT_
POR*3
Registers other than the above, CPU, and internal state
×
: Initialized
×: Not initialized
Note 1.
Note 2.
Note 3.
For the initial value of each register, see section 9, Clock Generation Circuit.
The RTC has a software reset. RCR1.RTCOS, CIE and RCR2.RTCOE, ADJ30, RESET bits are initialized by all types of
resets. For details on the target bits, see section 25, Realtime Clock (RTC).
For VBATT_POR details, see section 12, Battery Backup Function.
RTC is not initialized by any reset source. SOSC and LOCO can be selected as the clock sources of RTC and AGT. Table
6.4 and Table 6.5 show the states of SOSC and LOCO when a reset occurs.
Table 6.4
States of SOSC when a reset occurs
Reset source
State
SOSC
VBATT_POR
Other
Initialized to disable
Continue with the state that was selected before the reset occurred
Drive capability
Initialized to Normal mode
Continue with the state that was selected before the reset occurred
XCIN/XCOUT
Initialized to general-purpose
input pins
Continue with the state that was selected before the reset occurred
Enable or disable
Table 6.5
States of LOCO when a reset occurs
Reset source
State
LOCO
VBATT_POR
Other
Enable or disable
Initialized to enable
Continue with the state that was selected before the reset
occurred
Oscillation accuracy
Initialized to accuracy before
trimming by LOCOUTCR
(accuracy: ±15%)
Continue with the accuracy that was trimmed by LOCOUTCR
When a reset is canceled, reset exception handling starts.
Table 6.6 lists the pin related to the reset function.
Table 6.6
Reset I/O pin
Pin name
I/O
Function
RES
Input
Reset pin
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6.2
6. Resets
Register Descriptions
6.2.1
Reset Status Register 0 (RSTSR0)
Address(es): SYSTEM.RSTSR0 4001 E410h
Value after reset:
b7
b6
b5
b4
—
—
—
—
0
0
0
0
b3
b2
b1
b0
LVD2R LVD1R LVD0R PORF
F
F
F
x*1
x*1
x*1
x*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
PORF
Power-On Reset Detect Flag
0: Power-on reset not detected
1: Power-on reset detected.
R(/W)*2
b1
LVD0RF
Voltage Monitor 0 Reset Detect Flag
0: Voltage monitor 0 reset not detected
1: Voltage monitor 0 reset detected.
R(/W)*2
b2
LVD1RF
Voltage Monitor 1 Reset Detect Flag
0: Voltage monitor 1 reset not detected
1: Voltage monitor 1 reset detected.
R(/W)*2
b3
LVD2RF
Voltage Monitor 2 Reset Detect Flag
0: Voltage monitor 2 reset not detected
1: Voltage monitor 2 reset detected.
R(/W)*2
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
The value after reset depends on the reset source.
Only 0 can be written to clear the flag. The flag must be cleared by writing 0 after 1 is read.
PORF flag (Power-On Reset Detect Flag)
The PORF flag indicates that a power-on reset occurred.
[Setting condition]
When a power-on reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to PORF.
LVD0RF flag (Voltage Monitor 0 Reset Detect Flag)
The LVD0RF flag indicates that the VCC voltage fell below Vdet0.
[Setting condition]
When a voltage monitor 0 reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to LVD0RF.
LVD1RF flag (Voltage Monitor 1 Reset Detect Flag)
The LVD1RF flag indicates that the VCC voltage fell below Vdet1.
[Setting condition]
When a voltage monitor 1 reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to LVD1RF.
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6. Resets
LVD2RF flag (Voltage Monitor 2 Reset Detect Flag)
The LVD2RF flag indicates that the VCC voltage fell below Vdet2.
[Setting condition]
When a voltage monitor 2 reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to LVD2RF.
6.2.2
Reset Status Register 1 (RSTSR1)
Address(es): SYSTEM.RSTSR1 4001 E0C0h
b15
b14
b13
—
—
—
0
0
0
Value after reset:
b12
b11
b10
b9
b8
SPERF BUSM BUSSR REERF RPERF
RF
F
x*1
x*1
x*1
x*1
x*1
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SWRF WDTR IWDTR
F
F
x*1
x*1
x*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
IWDTRF
Independent Watchdog Timer Reset
Detect Flag
0: Independent watchdog timer reset not detected
1: Independent watchdog timer reset detected.
R(/W)*2
b1
WDTRF
Watchdog Timer Reset Detect Flag
0: Watchdog timer reset not detected
1: Watchdog timer reset detected.
R(/W)*2
b2
SWRF
Software Reset Detect Flag
0: Software reset not detected
1: Software reset detected.
R(/W)*2
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b8
RPERF
SRAM Parity Error Reset Detect Flag
0: SRAM parity error reset not detected
1: SRAM parity error reset detected.
R(/W)*2
b9
REERF
SRAM ECC Error Reset Detect Flag
0: SRAM ECC error reset not detected
1: SRAM ECC error reset detected.
R(/W)*2
b10
BUSSRF
Bus Slave MPU Error Reset Detect Flag
0: Bus slave MPU error reset not detected
1: Bus slave MPU error reset detected.
R(/W)*2
b11
BUSMRF
Bus Master MPU Error Reset Detect Flag
0: Bus master MPU error reset not detected
1: Bus master MPU error reset detected.
R(/W)*2
b12
SPERF
SP Error Reset Detect Flag
0: SP error reset not detected
1: SP error reset detected.
R(/W)*2
b15 to b13
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note 1.
Note 2.
The value after reset depends on the reset source.
Only 0 can be written to clear the flag. The flag must be cleared by writing 0 after 1 is read.
IWDTRF flag (Independent Watchdog Timer Reset Detect Flag)
The IWDTRF flag indicates that an independent watchdog timer reset occurred.
[Setting condition]
When an independent watchdog timer reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to IWDTRF.
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6. Resets
WDTRF flag (Watchdog Timer Reset Detect Flag)
The WDTRF flag indicates that a watchdog timer reset occurred.
[Setting condition]
When a watchdog timer reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to WDTRF.
SWRF flag (Software Reset Detect Flag)
The SWRF flag indicates that a software reset occurred.
[Setting condition]
When a software reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to SWRF.
RPERF flag (SRAM Parity Error Reset Detect Flag)
The RPERF flag indicates that an SRAM parity error reset occurred.
[Setting condition]
When an SRAM parity error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to RPERF.
REERF flag (SRAM ECC Error Reset Detect Flag)
The REERF flag indicates that an SRAM ECC error reset occurred.
[Setting condition]
When an SRAM ECC error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to REERF.
BUSSRF flag (Bus Slave MPU Error Reset Detect Flag)
The BUSSRF flag indicates that a bus slave MPU error reset occurred.
[Setting condition]
When a bus slave MPU error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to BUSSRF.
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6. Resets
BUSMRF flag (Bus Master MPU Error Reset Detect Flag)
The BUSMRF flag indicates that a bus master MPU error reset occurred.
[Setting condition]
When a bus master MPU error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to BUSMRF.
SPERF flag (SP Error Reset Detect Flag)
The SPERF flag indicates that a stack pointer error reset occurred.
[Setting condition]
When a stack pointer error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to SPERF.
6.2.3
Reset Status Register 2 (RSTSR2)
Address(es): SYSTEM.RSTSR2 4001 E411h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
CWSF
0
0
0
0
0
0
0
x*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
CWSF
Cold/Warm Start Determination Flag
0: Cold start
1: Warm start.
R(/W)*2
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
The value after reset depends on the reset source.
Only 1 can be written to set the flag.
RSTSR2 determines whether a power-on reset caused the reset processing (cold start) or a reset signal input during
operation caused the reset processing (warm start).
CWSF flag (Cold/Warm Start Determination Flag)
The CWSF flag indicates the type of reset processing, either cold start or warm start. The CWSF flag is initialized by a
power-on reset. It is not initialized by a reset signal generated by the RES pin.
[Setting condition]
When 1 is written by software. Writing 0 to CWSF does not set it to 0.
[Clearing condition]
When a reset listed in Table 6.2 occurs.
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6.3
6. Resets
Operation
6.3.1
RES Pin Reset
The RES pin generates this reset. When the RES pin is driven low, all the processing in progress is aborted and the MCU
enters a reset state. For a successful MCU reset, the RES pin must be held low for the power supply stabilization time
specified at power-on.
When the RES pin is driven high from low, the internal reset is canceled after the post-RES cancellation wait time
(tRESWT) elapses. The CPU then starts the reset exception handling.
For details, see section 51, Electrical Characteristics.
6.3.2
Power-On Reset
The power-on reset (POR) is an internal reset generated by the power-on reset circuit. If the RES pin is in a high-level
state when power is supplied, a power-on reset is generated. After VCC exceeds VPOR and the specified power-on reset
time elapses, the internal reset is canceled and the CPU starts the reset exception handling. The power-on reset time is the
stabilization period for the external power supply and the MCU circuit. After a power-on reset is generated, the PORF
flag in the RSTSR0 is set to 1. The PORF flag is initialized by the RES pin reset.
The voltage monitor 0 reset is an internal reset generated by the voltage monitor circuit. If the Voltage Detection 0
Circuit Start (LVDAS) bit in Option Function Select Register 1 (OFS1) is 0 (voltage monitor 0 reset is enabled after a
reset) and VCC falls below Vdet0, the RSTSR0.LVD0RF flag is set to 1 and the voltage detection circuit generates
voltage monitor 0 reset. Clear the OFS1.LVDAS bit to 0 if the voltage monitor 0 reset is to be used.
After VCC exceeds Vdet0 and the voltage monitor 0 reset time (tLVD0) elapses, the internal reset is canceled and the CPU
starts the reset exception handling. The Vdet0 voltage detection level can be changed by the setting in the VDSEL1[2:0]
bits in Option Function Select Register 1 (OFS1).
Figure 6.1 shows an example of operations during a power-on reset and voltage monitor 0 reset.
Vdet0*1
*3
VCCmin.
VPOR
VCC
Power-on reset state
Voltage monitor 0 reset state
Voltage monitor 0 reset state
RES pin
POR monitor
(active-low)
LVD0 enable/disable signal
(active-low)
Set by OFS1.LVDAS
Voltage detection 0 signal
(active-low)
Internal reset signal
(active-low)
RSTSR0.PORF
tLVD0*2
tLVD0*2
Cleared by user
programming
RES pin reset
RSTSR0.LVD0RF
Note:
Note 1.
Note 2.
Note 3.
For details on the electrical characteristics, see section 51, Electrical Characteristics.
Vdet0 shows a voltage monitor 0 reset detection level, and VPOR shows a power-on reset detection level, and VCCmin
shows the minimum guaranteed MCU voltage.
tLVD0 shows the time for voltage monitor 0 reset.
At power-on, VCC should rise to the minimum guaranteed voltage before the POR reset is released.
Figure 6.1
Example of operations during power-on reset and voltage monitor 0 reset
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6.3.3
6. Resets
Voltage Monitor Reset
The voltage monitor 0 reset is an internal reset generated by the voltage monitor circuit. If the Voltage Detection 0
Circuit Start (LVDAS) bit in Option Function Select register 1 (OFS1) is 0 (voltage monitor 0 reset is enabled after a
reset) and VCC falls below Vdet0, the RSTSR0.LVD0RF flag sets to 1 and the voltage detection circuit generates a
voltage monitor 0 reset. Clear the OFS1.LVDAS bit to 0 if the voltage monitor 0 reset is to be used. After VCC exceeds
Vdet0 and the voltage monitor 0 reset time (tLVD0) elapses, the internal reset is canceled and the CPU starts reset
exception handling.
When the Voltage Monitor 1 Interrupt/Reset Enable bit (RIE) is set to 1 (enabling generation of a reset or interrupt by the
voltage detection circuit) and the Voltage Monitor 1 Circuit Mode Select bit (LVD1CR0.RI) is set to 1 (selecting
generation of a reset in response to detection of a low voltage) in the Voltage Monitor 1 Circuit Control Register 0
(LVD1CR0), the RSTSR0.LVD1RF flag is set to 1 and the voltage detection circuit generates a voltage monitor 1 reset if
VCC falls to or below Vdet1.
Likewise, when the Voltage Monitor 2 Interrupt/Reset Enable bit (RIE) is set to 1 (enabling generation of a reset or
interrupt by the voltage detection circuit) and the Voltage Monitor 2 Circuit Mode Select bit (LVD2CR0.RI) is set to 1
(selecting generation of a reset in response to detection of a low voltage) in Voltage Monitor 2 Circuit Control Register 0
(LVD2CR0), the RSTSR0.LVD2RF flag is set to 1 and the voltage detection circuit generates a voltage monitor 2 reset if
VCC falls to or below Vdet2.
Similarly, timing for release from the voltage monitor 1 reset state is selectable in the Voltage Monitor 1 Reset Negate
Select bit (RN) in the LVD1CR0. When the LVD1CR0.RN bit is 0 and VCC falls to or below Vdet1, the CPU is released
from the internal reset state and starts reset exception handling when the LVD1 reset time (tLVD1) elapses after VCC rises
above Vdet1. When the LVD1CR0.RN bit is 1 and VCC falls to or below Vdet1, the CPU is released from the internal
reset state and starts reset exception handling when the LVD1 reset time (tLVD1) elapses.
Likewise, timing for release from the voltage monitor 2 reset state is selectable in the Voltage Monitor 2 Reset Negate
Select bit (RN) in the LVD2CR0 register. Detection levels Vdet1 and Vdet2 can be changed in the Voltage Detection Level
Select Register (LVDLVLR).
Figure 6.2 shows an example of operations during voltage monitor 1 and 2 resets. For details on the voltage monitor 1
reset and voltage monitor 2 reset, see section 8, Low Voltage Detection (LVD).
Vdeti*1
VCC
RES pin
LVDi valid setting
LVCMPCR.LVDiE
Voltage detection i signal
(active-low)
LVDiCR0.RN = 0
RES pin reset
RSTSR0.LVDiRF
tLVDi*2
Internal reset signal
LVDiCR0.RN = 1
RES pin reset
RSTSR0.LVDiRF
Internal reset signal
Note:
Note 1.
Note 2.
Figure 6.2
tLVDi*2
For details on the electrical characteristics, see section 51, Electrical Characteristics.
Vdeti indicates the detection level of voltage monitor 1 reset and voltage monitor 2 reset (i = 1, 2).
tLVDi indicates the time for voltage monitor 1 reset and voltage monitor 2 reset (i = 1, 2).
Example of operations during voltage monitor 1 and voltage monitor 2 resets
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6.3.4
6. Resets
Independent Watchdog Timer Reset
The independent watchdog timer reset is an internal reset generated from the Independent Watchdog Timer (IWDT).
Output of the reset from IWDT can be selected in the Option Function Select Register 0 (OFS0).
When output of the IWDT reset is selected, the reset is generated if the IWDT underflows, or if data is written when
refresh operation is disabled. When the internal reset time (tRESW2) elapses after the independent watchdog timer reset is
generated, the internal reset is canceled and the CPU starts the reset exception handling.
For details on the independent watchdog timer reset, see section 27, Independent Watchdog Timer (IWDT).
6.3.5
Watchdog Timer Reset
The watchdog timer reset is an internal reset generated from the Watchdog Timer (WDT). Output of the WDT reset can
be selected in the WDT Reset Control Register (WDTRCR) or Option Function Select Register 0 (OFS0).
When output of the watchdog timer reset is selected, the reset is generated if the WDT underflows, or if data is written
when refresh operation is disabled. When the internal reset time (tRESW2) elapses after the watchdog timer reset is
generated, the internal reset is canceled and the CPU starts the reset exception handling.
For details on the watchdog timer reset, see section 26, Watchdog Timer (WDT).
6.3.6
Software Reset
The software reset is an internal reset generated by a software setting of the SYSRESETREQ bit in the AIRCR register in
the Arm core. When the SYSRESETREQ bit is set to 1, a software reset is generated. When the internal reset time
(tRESW2) elapses after the software reset is generated, the internal reset is canceled and the CPU starts the reset exception
handling.
For details on the SYSRESETREQ bit, see the ARM® Cortex®-M4 Technical Reference Manual.
6.3.7
Determination of Cold/Warm Start
Read the CWSF flag in RSTSR2 to determine the cause of reset processing. This flag indicates whether a power-on reset
caused the reset processing (cold start) or a reset signal input during operation caused the reset processing (warm start).
The CWSF flag is set to 0 when a power-on reset occurs (cold start). Otherwise, the flag is not set to 0. The flag is set to
1 when 1 is written to it through software. It is not set to 0 even on writing 0 to it.
Figure 6.3 shows an example of a cold/warm start determination operation.
VPOR
VCC
RES pin
POR signal (active-low)
Not driven to 0 when a
low level is applied to
the RES pin
RSTSR2.CWSF flag
Set to 1 through programming
Figure 6.3
Example of a cold/warm start determination operation
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6.3.8
6. Resets
Determination of Reset Generation Source
Read RSTSR0 and RSTSR1 to determine which reset executes the reset exception handling. Figure 6.4 shows an
example flow to identify a reset generation source. The reset flag must be written with 0 after the reset flag is read as 1.
Reset exception
handling
RSTSR1 00h
or
RSTSR0.LVD1RF = 1
or
RSTSR0.LVD2RF = 1
No
Yes
RSTSR0.
LVD0RF = 1
Yes
No
RSTSR0.
PORF = 1
No
Yes
Reset associated with
each bit of RSTSR1,
RSTSR0.LVD1RF, or
RSTSR0.LVD2RF*1
Note 1.
Figure 6.4
Voltage
monitor 0
reset
Power-on
reset
RES pin reset
If a reset associated with each bit of RSTSR1, RSTSR0.LVD1RF, or RSTSR0.LVD2RF occurs at the same
time, all reset flags are set to 1.
Example of reset generation source determination flow
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7. Option-Setting Memory
7.
Option-Setting Memory
7.1
Overview
The option-setting memory determines the state of the MCU after a reset. The option-setting memory is allocated to the
configuration setting area and the program flash area of the flash memory. The available methods of setting are different
for the two areas. Figure 7.1 shows the option-setting memory area.
Address*1
0101 0018h to 0101 0033h
OCD/Serial Programmer ID
Setting Register (OSIS)
0101 0010h to 0101 0013h
Access Window Setting Register
(AWS)
0101 0008h to 0101 000Bh
Access Window Setting Control
Register (AWSC)
0000 0408h to 0000 043Bh
Security MPU (SECMPUxxx)
0000 0404h to 0000 0407h
Option Function Select Register 1
(OFS1)
0000 0400h to 0000 0403h
Option Function Select Register 0
(OFS0)
Note 1.
Figure 7.1
7.2
7.2.1
Configuration setting area
Program flash area
The option-setting memory must be to allocated to the user area of the flash memory.
Option-setting memory area
Register Descriptions
Option Function Select Register 0 (OFS0)
Address(es): OFS0 0000 0400h
b31
b30
b29
—
WDTST
PCTL
—
b28
b27
b26
b25
b24
b23
WDTRS WDTRPSS[1:0] WDTRPES[1:0]
TIRQS
b22
b21
b20
b19
b18
b17
b16
WDTTOPS[1:0] WDTST
RT
WDTCKS[3:0]
—
The value set by the user*1
Value after reset:
b15
b14
—
IWDTS
TPCTL
b13
—
b12
b11
b10
b9
b8
b7
IWDTR IWDTRPSS[1:0] IWDTRPES[1:0]
STIRQS
b6
b5
IWDTCKS[3:0]
b4
b3
b2
b1
b0
IWDTTOPS[1:0] IWDTS
TRT
—
The value set by the user*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
b1
IWDTSTRT
IWDT Start Mode Select
0: Automatically activate IWDT after a reset (auto-start
mode)
1: Disable IWDT.
R
b3, b2
IWDTTOPS[1:0]
IWDT Timeout Period Select
b3 b2
R
b7 to
b4
IWDTCKS[3:0]
IWDT-Dedicated Clock Frequency
Division Ratio Select
b7
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0
0
1
1
0: 128 cycles (007Fh)
1: 512 cycles (01FFh)
0: 1024 cycles (03FFh)
1: 2048 cycles (07FFh).
b4
0 0 0 0: × 1
0 0 1 0: × 1/16
0 0 1 1: × 1/32
0 1 0 0: × 1/64
1 1 1 1: × 1/128
0 1 0 1: × 1/256.
Other settings are prohibited.
R
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7. Option-Setting Memory
Bit
Symbol
Bit name
Description
R/W
b9, b8
IWDTRPES[1:0]
IWDT Window End Position
Select
b9 b8
R
b11,
b10
IWDTRPSS[1:0]
IWDT Window Start Position
Select
b11 b10
R
b12
IWDTRSTIRQS
IWDT Reset Interrupt Request
Select
0: Enable non-maskable interrupt request or interrupt
request
1: Enable reset.
R
b13
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
b14
IWDTSTPCTL
IWDT Stop Control
0: Continue counting
1: Stop counting when in Sleep mode, Snooze mode, or
Software Standby mode.
R
b16,
b15
—
Reserved
When read, these bits return the written value. The write
value should be 1.
R
b17
WDTSTRT
WDT Start Mode Select
0: Automatically activate WDT after a reset (auto-start
mode)
1: Stop WDT after a reset (register-start mode).
R
b19,
b18
WDTTOPS[1:0]
WDT Timeout Period Select
b19 b18
R
b23 to
b20
WDTCKS[3:0]
WDT Clock Frequency Division
Ratio Select
b23
b25,
b24
WDTRPES[1:0]
WDT Window End Position Select
b25 b24
R
b27,
b26
WDTRPSS[1:0]
WDT Window Start Position
Select
b27 b26
R
b28
WDTRSTIRQS
WDT Reset Interrupt Request
Select
WDT Behavior Select:
0: NMI
1: Reset.
R
b29
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
b30
WDTSTPCTL
WDT Stop Control
0: Continue counting
1: Stop counting when entering Sleep mode.
R
b31
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
Note 1.
0
0
1
1
0
0
1
1
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (no window end position setting).
0: 25%
1: 50%
0: 75%
1: 100% (no window start position setting).
0: 1024 cycles (03FFh)
1: 4096 cycles (0FFFh)
0: 8192 cycles (1FFFh)
1: 16384 cycles (3FFFh).
R
b20
0 0 0 1: PCLKB divided by 4
0 1 0 0: PCLKB divided by 64
1 1 1 1: PCLKB divided by 128
0 1 1 0: PCLKB divided by 512
0 1 1 1: PCLKB divided by 2048
1 0 0 0: PCLKB divided by 8192.
Other settings are prohibited.
0
0
1
1
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (No window end position setting).
0: 25%
1: 50%
0: 75%
1: 100% (No window start position setting).
The value in a blank product is FFFF_FFFFh. It is set to the value written by your application.
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7. Option-Setting Memory
IWDTSTRT bit (IWDT Start Mode Select)
The IWDTSTRT bit selects the mode in which the IWDT is activated after a reset (stopped state or activated state).
IWDTTOPS[1:0] bits (IWDT Timeout Period Select)
The IWDTTOPS[1:0] bits select the timeout period, that is, the time it takes for the down counter to underflow, as 128,
512, 1,024, or 2,048 cycles of the frequency-divided clock set in the IWDTCKS[3:0] bits. The number of clock cycles
that the IWDT takes to underflow after a refresh operation is determined by the combination of the IWDTCKS[3:0] and
IWDTTOPS[1:0] bits.
See section 27, Independent Watchdog Timer (IWDT) for details.
IWDTCKS[3:0] bits (IWDT-Dedicated Clock Frequency Division Ratio Select)
The IWDTCKS[3:0] bits select the division ratio of the prescaler for dividing the frequency of the clock for the IWDT as
1/1, 1/16, 1/32, 1/64, 1/128, or 1/256. Using this setting combined with the IWDTTOPS[1:0] bit setting, the IWDT
counting period can be set from 128 to 524,288 IWDT clock cycles.
See section 27, Independent Watchdog Timer (IWDT) for details.
IWDTRPES[1:0] bits (IWDT Window End Position Select)
The IWDTRPES[1:0] bits select the position where the window for the down counter ends as 0%, 25%, 50%, or 75% of
the count value. The value of the window end position must be smaller than the value of the window start position.
Otherwise, only the value for the window start position is valid.
The counter values associated with the settings for the start and end positions of the window in the IWDTRPSS[1:0] and
IWDTRPES[1:0] bits vary depending on the setting in the IWDTTOPS[1:0] bits.
See section 27, Independent Watchdog Timer (IWDT) for details.
IWDTRPSS[1:0] bits (IWDT Window Start Position Select)
The IWDTRPSS[1:0] bits select the position where the window for the down counter starts as 25%, 50%, 75%, or 100%
of the counted value. The point at which counting starts is 100% and the point at which an underflow occurs is 0%. The
interval between the window start and end positions becomes the period in which a refresh is possible. Refresh is not
possible outside this period.
See section 27, Independent Watchdog Timer (IWDT) for details.
IWDTRSTIRQS bit (IWDT Reset Interrupt Request Select)
The IWDTRSTIRQS bit selects the operation on an underflow of the down counter or generation of a refresh error. The
operation is selectable to an independent watchdog timer reset, a non-maskable interrupt request, or an interrupt request.
See section 27, Independent Watchdog Timer (IWDT) for details.
IWDTSTPCTL bit (IWDT Stop Control)
The IWDTSTPCTL bit selects whether to stop counting when entering Sleep mode, Snooze mode, or Software Standby
mode. See section 27, Independent Watchdog Timer (IWDT) for details.
WDTSTRT bit (WDT Start Mode Select)
The WDTSTRT bit selects the mode in which the WDT is activated after a reset (stopped state or activated in auto-start
mode). When WDT is activated in auto-start mode, the OFS0 register setting for the WDT is valid.
WDTTOPS[1:0] bits (WDT Timeout Period Select)
The WDTTOPS[1:0] bits specify the timeout period, the time it takes for the down counter to underflow, as 1,024, 4,096,
8,192, or 16,384 cycles of the frequency-divided clock set in the WDTCKS[3:0] bits. The number of PCLKB cycles that
the counter takes to underflow after a refresh operation is determined by a combination of the WDTCKS[3:0] and
WDTTOPS[1:0] bits.
See section 26, Watchdog Timer (WDT) for details.
WDTCKS[3:0] bits (WDT Clock Frequency Division Ratio Select)
The WDTCKS[3:0] bits select the division ratio of the prescaler for dividing the PCLKB frequency as 1/4, 1/64, 1/128,
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7. Option-Setting Memory
1/512, 1/2,048, or 1/8,192. Using this setting combined with the WDTTOPS[1:0] bit setting, the WDT counting period
can be set from 4,096 to 134,217,728 PCLKB cycles.
See section 26, Watchdog Timer (WDT) for details.
WDTRPES[1:0] bits (WDT Window End Position Select)
The WDTRPES[1:0] bits select the position of the end of the window for the down counter as 0%, 25%, 50%, or 75% of
the counted value. The value of the window end position must be smaller than the value of the window start position.
Otherwise, only the value for the window start position is valid.
The counter values associated with the settings for the start and end positions of the window, in the WDTRPSS[1:0] and
WDTRPES[1:0] bits, vary with the setting in the WDTTOPS[1:0] bits.
See section 26, Watchdog Timer (WDT) for details.
WDTRPSS[1:0] bits (WDT Window Start Position Select)
The WDTRPSS[1:0] bits select the position where the window for the down counter starts as 25%, 50%, 75%, or 100%
of the counted value. The point at which counting starts is 100% and the point at which an underflow occurs is 0%. The
interval between the window start and end positions becomes the period in which a refresh is possible. However, refresh
is not possible outside this period.
See section 26, Watchdog Timer (WDT) for details.
WDTRSTIRQS bit (WDT Reset Interrupt Request Select)
The WDTRSTIRQS bit selects the operation on an underflow of the down counter or generation of a refresh error. The
operation is selectable to a watchdog timer reset, a non-maskable interrupt request, or an interrupt request.
See section 26, Watchdog Timer (WDT) for details.
WDTSTPCTL bit (WDT Stop Control)
The WDTSTPCTL bit specifies whether to stop counting when entering Sleep mode.
See section 26, Watchdog Timer (WDT) for details.
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7.2.2
7. Option-Setting Memory
Option Function Select Register 1 (OFS1)
Address(es): OFS1 0000 0404h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
b5
b4
b3
b2
b1
b0
LVDAS
—
—
The value set by the user*1
Value after reset:
b15
b14
—
b13
b12
HOCOFRQ1[2:0]
b11
—
b10
—
b9
b8
b7
b6
—
HOCO
EN
—
—
VDSEL1[2:0]
The value set by the user*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
When read, these bits return the written value. The write
value should be 1.
R
b2
LVDAS
Voltage Detection 0 Circuit
Start
0: Enable voltage monitor 0 reset after a reset
1: Disable voltage monitor 0 reset after a reset.
R
b5 to b3
VDSEL1[2:0]
Voltage Detection 0 Level
Select
b5
b7, b6
—
Reserved
When read, these bits return the written value. The write
value should be 1.
R
b8
HOCOEN
HOCO Oscillation Enable
0: Enable HOCO oscillation after a reset
1: Disable HOCO oscillation after a reset.
R
b11 to b9
—
Reserved
When read, these bits return the written value. The write
value should be 1.
R
b14 to b12
HOCOFRQ1[2:0]
HOCO Frequency Setting 1
b14
R
b31 to b15
—
Reserved
When read, these bits return the written value. The write
value should be 1.
Note 1.
b3
0 0 0: Selects 3.84 V
0 0 1: Selects 2.82 V
0 1 0: Selects 2.51 V
0 1 1: Selects 1.90 V
1 0 0: Selects 1.70 V.
Other settings are prohibited.
b12
0 0 0: 24 MHz
0 1 0: 32 MHz
1 0 0: 48 MHz
1 0 1: 64 MHz.
Other settings are prohibited.
R
The value in the blank product is FFFF_FFFFh. It is set to the value written by your application.
LVDAS bit (Voltage Detection 0 Circuit Start)
The LVDAS bit selects whether the voltage monitor 0 reset is enabled or disabled after a reset.
VDSEL1[2:0] bits (Voltage Detection 0 Level Select)
The VDSEL1[2:0] bits select the voltage detection level of the voltage detection 0 circuit.
HOCOEN bit (HOCO Oscillation Enable)
The HOCOEN bit selects whether the HOCO oscillation is enabled or disabled after a reset. Setting this bit to 0 allows
the HOCO oscillation to start before the CPU starts operation, which reduces the wait time for oscillation stabilization.
Note:
When the HOCOEN bit is set to 0, the system clock source is not switched to HOCO. The system clock source is
only switched to HOCO by setting the Clock Source Select bits (SCKSCR.CKSEL[2:0]). To use the HOCO clock,
set the OFS1.HOCOFRQ1 bit to an optimum value.
After a reset release, operation is in the low-voltage mode, and so HOCOCR.HCSTP must be immediately set to 0.
HOCOFRQ1[2:0] bits (HOCO Frequency Setting 1)
The HOCOFRQ1[2:0] bits select the HOCO frequency after a reset as 24, 32, 48, or 64 MHz.
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7.2.3
7. Option-Setting Memory
MPU Registers
Table 7.1 shows the registers related to the MPU function. See section 16, Memory Protection Unit (MPU) for details.
The security MPU is disabled on erasure of the flash memory. If incorrect data is written to an MPU register, the MCU
might fail to operate. See section 16, Memory Protection Unit (MPU) to set the proper data.
Table 7.1
MPU registers
Register name
Symbol
Function
Address
Size
(byte)
Security MPU Program Counter Start
Address Register 0
SECMPUPCS0
Specifies the security fetch region of code flash or
SRAM
0000 0408h
4
Security MPU Program Counter End
Address Register 0
SECMPUPCE0
Specifies the security fetch region of code flash or
SRAM
0000 040Ch
4
Security MPU Program Counter Start
Address Register 1
SECMPUPCS1
Specifies the security fetch region of code flash or
SRAM
0000 0410h
4
Security MPU Program Counter End
Address Register 1
SECMPUPCE1
Specifies the security fetch region of code flash or
SRAM
0000 0414h
4
Security MPU Region 0 Start Address
Register
SECMPUS0
Specifies the secure program and code flash data
0000 0418h
4
Security MPU Region 0 End Address
Register
SECMPUE0
Specifies the secure program and code flash data
0000 041Ch
4
Security MPU Region 1 Start Address
Register
SECMPUS1
Specifies the secure data of SRAM
0000 0420h
4
Security MPU Region 1 End Address
Register
SECMPUE1
Specifies the secure data of SRAM
0000 0424h
4
Security MPU Region 2 Start Address
Register
SECMPUS2
Specifies the secure data of security functions
0000 0428h
4
Security MPU Region 2 End Address
Register
SECMPUE2
Specifies the secure data of security functions
0000 042Ch
4
Security MPU Region 3 Start Address
Register
SECMPUS3
Specifies the secure data of security functions
0000 0430h
4
Security MPU Region 3 End Address
Register
SECMPUE3
Specifies the secure data of security functions
0000 0434h
4
Security MPU Access Control
Register
SECMPUAC
Specifies the security enabled/disabled region
0000 0438h
4
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7.2.4
7. Option-Setting Memory
Access Window Setting Control Register (AWSC)
Address(es): AWSC 0101 0008h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
The value set by the user
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
FSPR
—
—
—
—
—
BTFLG
—
—
—
—
—
—
—
—
The value set by the user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b8
BTFLG
Startup Area Select Flag
This bit specifies whether the address of the startup area is
exchanged for the boot swap function.
0: The first 8-KB area (0000 0000h to 0000 1FFFh) and second
8-KB area (0000 2000h to 0000 3FFFh) are exchanged
1: The first 8-KB area (0000 0000h to 0000 1FFFh) and second
8-KB area (0000 2000h to 0000 3FFFh) are not exchanged.
R
b13 to b9
—
Reserved
When read, these bits return the value written by the user. The
write value should be 1.
R
b14
FSPR
Protection of Access Window
and Startup Area Select
Function
This bit controls the programming of the write/erase protection for
the access window, the Startup Area Select Flag (BTFLG), and
the temporary boot swap control. If this bit is set to 0, it cannot be
changed to 1.
0: Executing the configuration setting command for programming
the access window (FAWE[11:0], FAWS[11:0]) and the Startup
Area Select Flag (BTFLG) is invalid.
1: Executing the configuration setting command for programming
the access window (FAWE[11:0], FAWS[11:0]) and the Startup
Area Select Flag (BTFLG) is valid.
R
b31 to b15
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
7.2.5
Access Window Setting Register (AWS)
Address(es): AWS 0101 0010h
b31
b30
b29
b28
—
—
—
—
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b4
b3
b2
b1
b0
FAWE[11:0] *1
The value set by the user
Value after reset:
b15
b14
b13
b12
—
—
—
—
b11
b10
b9
b8
b7
b6
b5
FAWS[11:0] *1
The value set by the user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b11 to b0
FAWS[11:0]
Access Window Start Block
Address*1
These bits specify the start block address for the access window.
They do not represent the block number of the access window.
The access window is only valid in the program flash area. The
block address specifies the first address of the block and consists
of the address bits [21:10].
R
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7. Option-Setting Memory
Bit
Symbol
Bit name
Description
R/W
b15 to b12
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b27 to b16
FAWE[11:0]
Access Window End Block
Address*1
These bits specify the end block address for the access window.
They do not represent the block number of the access window.
The access window is only valid in the program flash area. The
end block address for the access window is the next block to the
acceptable programming and erasure region defined by the
access window. The block address specifies the first address of
the block and consists of the address bits [21:10].
R
b31 to b28
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
Note 1.
The write value should be 0 for FAWE[0] and FAWS[0].
Issuing the program or erase command to an area outside the access window causes a command-locked state. The access
window is only valid in the program flash area. The access window provides protection in self-programming mode, serial
programming mode, and on-chip debug mode. The access window can be locked by the FSPR bit.
The access window is specified in both the FAWS[11:0] and FAWE[11:0] bits.
The settings for the bits are as follows:
FAWE[11:0] = FAWS[11:0]: The P/E command is allowed to execute in the full program flash area
FAWE[11:0] > FAWS[11:0]: The P/E command is only allowed to execute in the window from the block pointed to
by the FAWS[11:0] bits to the block one lower than the block pointed to by the FAWE[11:0] bits
FAWE[11:0] < FAWS[11:0]: The P/E command is not allowed to execute in the program flash area.
P/E
Address
…
Block 7
(FAWE[11:0] = 007h)
Protected
area
Block 6
Access
Window
Block 5
Non-protected
area
Block 4
(FAWS[11:0] = 004h)
Block 3
Block 2
Block 1
Protected
area
Block 0
Figure 7.2
Access window overview
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7.2.6
7. Option-Setting Memory
OCD/Serial Programmer ID Setting Register (OSIS)
The OSIS register stores the ID for ID code protection of the OCD/serial programmer. When connecting the OCD/serial
programmer, write values so that the MCU can determine whether to permit the connection. Use this register to check
whether a code transmitted from the OCD/serial programmer matches the ID code in the option-setting memory. When
the ID codes match, connection with the OCD/serial programmer is permitted. When the ID codes do not match,
connection with the OCD/serial programmer is not possible. The OSIS register must be set in 32-bit units.
Address(es): OSIS 0101 0018h, OSIS 0101 0020h, OSIS 0101 0028h, OSIS 0101 0030h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b5
b4
b3
b2
b1
b0
The value set by the user
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
The value set by the user
Value after reset:
These fields store the ID for use in ID authentication for the OCD/serial programmer.
ID code bits [127] and [126] determine whether the ID code protection is enabled, and the method of authentication to
use with the host. Table 7.2 shows how the ID code determines the method of authentication.
Setting bit [127] to 0 prevents Renesas from accessing the test mode. Therefore, Renesas cannot perform failure analysis
unless provided with the ID code.
Table 7.2
Specifications for ID code protection
Operating mode on
boot up
Serial programming
mode (SCI/USB boot
mode)
On-chip debug mode
(JTAG/SWD boot mode)
ID code
State of
protection
Operations on connection to programmer or onchip debugger
FFh, …, FFh
(all bytes are FFh)
Protection
disabled
The ID code is not checked, the ID code always
matches, and connection to the programmer or on-chip
debugger is permitted
Bit [127] = 1, bit [126] = 1,
and at least one of the 16
bytes is not FFh
Protection
enabled
Matching ID code indicates that authentication is
complete and connection with the programmer or the
on-chip debugger is permitted.
Mismatching ID code indicates transition to the ID code
protection wait state.
When the ID code sent from the programmer or the onchip debugger is ALeRASE in ASCII code
(414C_6552_4153_45FF_FFFF_FFFF_FFFF_FFFFh),
the contents of the user flash (code and data) and
configuration area are erased.
However, forced erasure is not executed when the
FSPR bit is 0.
Bit [127] = 1 and bit [126] = 0 Protection
enabled
Matching ID code indicates that authentication is
complete and connection with the programmer or the
on-chip debugger is permitted.
Mismatching ID code indicates transition to the ID code
protection wait state.
Bit [127] = 0
The ID code is not checked, the ID code is always
mismatching, and the connection with the programmer
or the on-chip debugger is prohibited, and Renesas
cannot access the test mode.
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7.3
7. Option-Setting Memory
Setting Option-Setting Memory
7.3.1
Allocation of Data in Option-Setting Memory
Programming data is allocated to the addresses in the option-setting memory shown in Figure 7.1. The allocated data is
used by tools such as a flash programming software or an on-chip debugger.
Note:
Programming formats vary depending on the compiler. See the compiler manual for details.
7.3.2
Setting Data for Programming Option-Setting Memory
Allocating data according to the procedure described in section 7.3.1, Allocation of Data in Option-Setting Memory,
alone does not actually write the data to the option-setting memory. You must also follow one of the actions described in
this section.
(1)
Changing the option-setting memory by self-programming
Use the programming command to write data to the program flash area. Use the configuration setting command to write
data to the option-setting memory in the configuration setting area. In addition, use the startup area select function to
safely update the boot program that includes the option-setting memory.
See section 47, Flash Memory for details on the programming command, the configuration setting command, and the
startup area select function.
(2)
Debugging through an OCD or programming by a flash writer
This procedure depends on the tool in use, so see the tool manual for details.
The MCU provides two setting procedures as follows:
Read the data allocated as described in section 7.3.1, Allocation of Data in Option-Setting Memory, from an object
file or Motorola S-format file generated by the compiler, and write the data to the MCU
Use the GUI interface of the tool to program the same data allocated as described in section 7.3.1, Allocation of
Data in Option-Setting Memory.
7.4
7.4.1
Usage Note
Data for Programming Reserved Areas and Reserved Bits in the Option-Setting
Memory
When reserved areas and reserved bits in the option-setting memory are available for programming, write 1 to all bits in
the reserved areas and all reserved bits. If 0 is written to these bits, normal operation cannot be guaranteed.
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8. Low Voltage Detection (LVD)
8.
Low Voltage Detection (LVD)
8.1
Overview
The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin, and the detection level can
be selected using a software program. The LVD module consists of three separate voltage level detectors, 0, 1, and 2,
which measure the voltage level input to the VCC pin. LVD voltage detection registers allow your application to
configure the detection of VCC changes at various voltage thresholds.
Each voltage level detector has a voltage monitor associated with it, called voltage monitor 0, 1, and 2. Voltage monitor
registers configure the LVD to trigger an interrupt, event link output, or reset when the thresholds are crossed.
Table 8.1 lists the LVD specifications. Figure 8.1 shows a block diagram of voltage detectors 0, 1, and 2, Figure 8.2
shows a block diagram of the voltage monitor 1 interrupt/reset circuit, and Figure 8.3 shows a block diagram of the
voltage monitor 2 interrupt/reset circuit.
Table 8.1
LVD specifications
Item
VCC
monitoring
Process on
voltage
detection
Voltage monitor 0
Voltage monitor 1
Voltage monitor 2
Monitored
voltage
Vdet0
Vdet1
Vdet2
Detected
event
Voltage falls below Vdet0
Voltage rises or falls past Vdet1
Voltage rises or falls past Vdet2
Detected
voltage
Selectable from five different
levels in the
OFS1.VDSEL1[2:0] bits
Selectable from 16 different levels
in the LVDLVLR.LVD1LVL[4:0] bits
Selectable from four different
levels in the
LVDLVLR.LVD2LVL[2:0] bits
Monitor flag
None
LVD1SR.MON flag: Monitors
whether voltage is higher or lower
than Vdet1
LVD2SR.MON flag: Monitors
whether voltage is higher or lower
than Vdet2
LVD1SR.DET flag: Vdet1 passage
detection
LVD2SR.DET flag: Vdet2 passage
detection
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Reset when Vdet0 > VCC
CPU restart after specified
time with VCC > Vdet0
Reset when Vdet1 > VCC
CPU restart timing selectable:
after specified time with VCC >
Vdet1 or Vdet1 > VCC
Reset when Vdet2 > VCC
CPU restart timing selectable:
after specified time with VCC >
Vdet2 or Vdet2 > VCC
No interrupt
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Non-maskable interrupt or
maskable interrupt selectable
Non-maskable interrupt or
maskable interrupt selectable
Interrupt request issued when
Vdet1 > VCC or VCC > Vdet1
Interrupt request issued when
Vdet2 > VCC or VCC > Vdet2
Available
Output of event signals on
detection of Vdet1 crossings
Available
Output of event signals on
detection of Vdet2 crossings
Reset
Interrupt
Event linking
None
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8. Low Voltage Detection (LVD)
OFS1.LVDAS
VCC
Voltage detection 0 reset signal
+
-
Level selection
Internal reference voltage
circuit
(for detecting Vdet0)
OFS1.VDSEL1[2:0]
Vdet0
LVCMPCR.LVD1E
LVD1CR0.CMPE
Voltage detection 1 signal
+
Internal reference voltage
(for detecting Vdet1)
Level selection
circuit
- V
det1
LVDLVLR.LVD1LVL[4:0]
LVCMPCR.LVD2E
LVD2CR0.CMPE
Voltage detection 2 signal
+
Internal reference voltage
(for detecting Vdet2)
- V
det2
Level selection
circuit
LVDLVLR.LVD2LVL[2:0]
Note:
Figure 8.1
See section 7, Option-Setting Memory.
Voltage detection 0, 1, and 2 block diagram
Voltage monitor 1
The setting of the LVD1SR.DET bit is 0
if 0 (undetected) is written in the program
Voltage detection 1
LVD1SR.MON
VCC
LVCMPCR.LVD1E
b1
LVD1CR0.CMPE
+
Internal reference
voltage
(for detection of
Vdet1)
Level
selection
Voltage
detection 1
signal
Fixed
period
negation
Edge
selection
circuit
LVDLVLR.LVD1LVL[4:0]
Voltage detection 1 signal is high when
the LVCMPCR.LVD1E bit is 0
(disabled)
LVD1CR0.RIE
LVD1CR0.RI
LVD1CR0.RN = 0
LVD1CR0.
RN = 1
LVD1SR.
DET
LVD1CR1.IDTSEL[1:0]
Voltage monitor 1
reset signal
(active-low)
Voltage monitor 1
non-maskable interrupt
signal
LVD1CR1.IRQSEL
Voltage monitor 1
interrupt signal
Event
Figure 8.2
Voltage monitor 1 interrupt/reset circuit block diagram
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8. Low Voltage Detection (LVD)
Voltage monitor 2
The LVD2SR.DET bit sets to 0
if 0 (undetected) is written by the program
Voltage detection 2
LVD2SR.MON
VCC
LVCMPCR.LVD2E
b1
LVD2CR0.CMPE
+
Fixed
period
negation
Voltage
detection 2
signal
-
Internal reference
voltage
Level
(for detection of
selection
Vdet2)
LVD2CR0.RIE
LVD2CR0.RI
LVD2CR0.RN = 0
Edge
selection
circuit
LVDLVLR.LVD2LVL[2:0]
Voltage detection 2 signal is high when the
setting of the LVCMPCR.LVD2E bit is 0
(disabled)
LVD2CR0.
RN = 1
LVD2SR.
DET
LVD2CR1.IDTSEL[1:0]
Voltage monitor 2
reset signal
(active-low)
Voltage monitor 2
non-maskable
interrupt signal
LVD2CR1.IRQSEL
Voltage monitor 2
interrupt signal
Event
Figure 8.3
8.2
Voltage monitor 2 interrupt/reset circuit block diagram
Register Descriptions
8.2.1
Voltage Monitor 1 Circuit Control Register 1 (LVD1CR1)
Address(es): SYSTEM.LVD1CR1 4001 E0E0h
Value after reset:
b7
b6
b5
b4
b3
b2
—
—
—
—
—
IRQSE
L
0
0
0
0
0
0
b1
b0
IDTSEL[1:0]
0
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
IDTSEL[1:0]
Voltage Monitor 1 Interrupt
Generation Condition Select
b1 b0
R/W
b2
IRQSEL
Voltage Monitor 1 Interrupt Type
Select
0: Non-maskable interrupt
1: Maskable interrupt*1.
R/W
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b3
Note:
Note 1.
0
0
1
1
0: When VCC ≥ Vdet1 (rise) is detected
1: When VCC < Vdet1 (fall) is detected
0: When fall and rise are detected
1: Setting prohibited.
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
When enabling maskable interrupts, do not change the NMIER.LVD1EN bit value in the ICU from the reset state.
8.2.2
Voltage Monitor 1 Circuit Status Register (LVD1SR)
Address(es): SYSTEM.LVD1SR 4001 E0E1h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MON
DET
0
0
0
0
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
DET
Voltage Monitor 1 Voltage Change
Detection Flag
0: Not detected
1: Vdet1 passage detected.
*1
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8. Low Voltage Detection (LVD)
Bit
Symbol
Bit name
Description
R/W
b1
MON
Voltage Monitor 1 Signal Monitor Flag
0: VCC < Vdet1
1: VCC ≥ Vdet1 or MON is disabled.
R
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b2
Note:
Note 1.
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Only 0 can be written to this bit. After writing 0 to this bit, 2 system clock cycles are required for the bit to be read as 0.
DET flag (Voltage Monitor 1 Voltage Change Detection Flag)
The DET flag is enabled when the LVCMPCR.LVD1E bit is 1 (voltage detection 1 circuit enabled) and the
LVD1CR0.CMPE bit is 1 (voltage monitor 1 circuit comparison result output enabled).
Set the DET flag to 0 after LVD1CR0.RIE is set to 0 (disabled). LVD1CR0.RIE can be set to 1 (enabled) after 2 or more
PCLKB cycles elapse.
A longer PCLKB wait time might be required, depending on the number of PCLKB cycles required to read a specific I/O
register.
MON flag (Voltage Monitor 1 Signal Monitor Flag)
The MON flag is enabled when the LVCMPCR.LVD1E bit is 1 (voltage detection 1 circuit enabled) and the
LVD1CR0.CMPE bit is 1 (voltage monitor 1 circuit comparison result output enabled).
8.2.3
Voltage Monitor 2 Circuit Control Register 1 (LVD2CR1)
Address(es): SYSTEM.LVD2CR1 4001 E0E2h
b7
Value after reset:
b6
b5
b4
b3
b2
—
—
—
—
—
IRQSE
L
0
0
0
0
0
0
b1
b0
IDTSEL[1:0]
0
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
IDTSEL[1:0]
Voltage Monitor 2 Interrupt
Generation Condition Select
b1 b0
R/W
b2
IRQSEL
Voltage Monitor 2 Interrupt Type
Select
0: Non-maskable interrupt
1: Maskable interrupt*1.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Note 1.
0
0
1
1
0: When VCC ≥ Vdet2 (rise) is detected
1: When VCC < Vdet2 (fall) is detected
0: When fall and rise are detected
1: Setting prohibited.
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
When enabling maskable interrupts, do not change the value of the NMIER.LVD1EN bit in the ICU from the reset state.
8.2.4
Voltage Monitor 2 Circuit Status Register (LVD2SR)
Address(es): SYSTEM.LVD2SR 4001 E0E3h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MON
DET
0
0
0
0
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
DET
Voltage Monitor 2 Voltage Change
Detection Flag
0: Not detected
1: Vdet2 passage detected.
R/W*1
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8. Low Voltage Detection (LVD)
Bit
Symbol
Bit name
Description
R/W
b1
MON
Voltage Monitor 2 Signal Monitor
Flag
0: VCC < Vdet2
1: VCC ≥ Vdet2 or MON is disabled.
R
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b2
Note:
Note 1.
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0.
DET flag (Voltage Monitor 2 Voltage Change Detection Flag)
The DET flag is enabled when the LVCMPCR.LVD2E bit is 1 (voltage detection 2 circuit enabled) and the
LVD2CR0.CMPE bit is 1 (voltage monitor 2 circuit comparison result output enabled).
Set the DET flag to 0 after LVD2CR0.RIE is set to 0 (disabled). LVD2CR0.RIE can be set to 1 (enabled) after 2 or more
PCLKB cycles elapse.
A longer PCLKB wait time might be required, depending on the number of PCLKB cycles required to read a given I/O
register.
MON flag (Voltage Monitor 2 Signal Monitor Flag)
The MON flag is enabled when the LVCMPCR.LVD2E bit is 1 (voltage detection 2 circuit enabled) and the
LVD2CR0.CMPE bit is 1 (voltage monitor 2 circuit comparison result output enabled).
8.2.5
Voltage Monitor Circuit Control Register (LVCMPCR)
Address(es): SYSTEM.LVCMPCR 4001 E417h
b7
—
b6
LVD2E LVD1E
0
Value after reset:
b5
0
0
b4
b3
b2
b1
b0
—
—
—
—
—
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
LVD1E
Voltage Detection 1 Enable
0: Disable voltage detection 1 circuit
1: Enable voltage detection 1 circuit.
R/W
b6
LVD2E
Voltage Detection 2 Enable
0: Disable voltage detection 2 circuit
1: Enable voltage detection 2 circuit.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
LVD1E bit (Voltage Detection 1 Enable)
When using voltage detection 1 interrupt/reset or the LVD1SR.MON bit, set the LVD1E bit to 1. The voltage detection 1
circuit starts when td(E-A) elapses after the LVD1E bit value is changed from 0 to 1.
LVD2E bit (Voltage Detection 2 Enable)
When using voltage detection 2 interrupt/reset or the LVD2SR.MON bit, set the LVD2E bit to 1. The voltage detection 2
circuit starts when td(E-A) elapses after the LVD2E bit value is changed from 0 to 1.
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8.2.6
8. Low Voltage Detection (LVD)
Voltage Detection Level Select Register (LVDLVLR)
Address(es): SYSTEM.LVDLVLR 4001 E418h
b7
b6
b5
b4
b3
LVD2LVL[2:0]
0
Value after reset
0
b2
b1
b0
1
1
LVD1LVL[4:0]
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
LVD1LVL[4:0]
Voltage Detection 1 Level Select
(standard voltage during fall in
voltage)
b4
R/W
b7 to b5
LVD2LVL[2:0]
Voltage Detection 2 Level Select
(standard voltage during fall in
voltage)
b7
Note:
b0
0 0 0 0 0: 4.29 V (Vdet1_0)
0 0 0 0 1: 4.14 V (Vdet1_1)
0 0 0 1 0: 4.02 V (Vdet1_2)
0 0 0 1 1: 3.84 V (Vdet1_3)
0 0 1 0 0: 3.10 V (Vdet1_4)
0 0 1 0 1: 3.00 V (Vdet1_5)
0 0 1 1 0: 2.90 V (Vdet1_6)
0 0 1 1 1: 2.79 V (Vdet1_7)
0 1 0 0 0: 2.68 V (Vdet1_8)
0 1 0 0 1: 2.58 V (Vdet1_9)
0 1 0 1 0: 2.48 V (Vdet1_A)
0 1 0 1 1: 2.20 V (Vdet1_B)
0 1 1 0 0: 1.96 V (Vdet1_C)
0 1 1 0 1: 1.86 V (Vdet1_D)
0 1 1 1 0: 1.75 V (Vdet1_E)
0 1 1 1 1: 1.65 V (Vdet1_F).
Other settings are prohibited.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
R/W
b5
0: 4.29 V (Vdet2_0)
1: 4.14 V (Vdet2_1)
0: 4.02 V (Vdet2_2)
1: 3.84 V (Vdet2_3)
0: Setting prohibited
1: Setting prohibited
0: Setting prohibited
1: Setting prohibited.
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
The contents of the LVDLVLR register can only be changed if the LVCMPCR.LVD1E and LVCMPCR.LVD2E bits
(voltage detection n circuit disable, n = 1, 2) are both 0. Do not set the LVD detectors 1 and 2 to the same voltage
detection level.
8.2.7
Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0)
Address(es): SYSTEM.LVD1CR0 4001 E41Ah
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
RN
RI
—
—
—
CMPE
—
RIE
1
0
0
0
x
0
0
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RIE
Voltage Monitor 1 Interrupt/Reset
Enable
0: Disable
1: Enable.
R/W
b1
—
Reserved
The read value is 0. The write value should be 0.
R/W
b2
CMPE
Voltage Monitor 1 Circuit
Comparison Result Output Enable
0: Disable voltage monitor 1 circuit comparison result output
1: Enable voltage monitor 1 circuit comparison result output.
R/W
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Bit
Symbol
Bit name
8. Low Voltage Detection (LVD)
Description
R/W
b3
—
Reserved
The read value is undefined. The write value should be 1.
R/W
b5, b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
RI
Voltage Monitor 1 Circuit Mode
Select
0: Generate voltage monitor 1 interrupt on Vdet1 passage
1: Enable voltage monitor 1 reset when the voltage falls to and
below Vdet1.
R/W
b7
RN
Voltage Monitor 1 Reset Negate
Select
0: Negate after a stabilization time (tLVD1) when VCC > Vdet1 is
detected
1: Negate after a stabilization time (tLVD1) on assertion of the
LVD1 reset.
R/W
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
RIE bit (Voltage Monitor 1 Interrupt/Reset Enable)
The RIE bit enables or disables the voltage monitor 1 interrupt/reset. Set this bit to ensure that neither a voltage monitor
1 interrupt nor a voltage monitor 1 reset is generated during programming or erasure of the flash memory.
RN bit (Voltage Monitor 1 Reset Negate Select)
If the RN bit is to be set to 1 (negation follows a stabilization time after assertion of the LVD1 reset signal), set the
MOCOCR.MCSTP bit to 0 (the MOCO operates). In addition, for a transition to Software Standby mode, the only
possible value for the RN bit is 0 (negation follows a stabilization time after VCC > Vdet1 is detected). Do not set the RN
bit to 1 (negation follows a stabilization time after assertion of the LVD1 reset signal) when this is the case.
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8.2.8
8. Low Voltage Detection (LVD)
Voltage Monitor 2 Circuit Control Register 0 (LVD2CR0)
Address(es): SYSTEM.LVD2CR0 4001 E41Bh
b7
b6
b5
b4
b3
b2
b1
b0
RN
RI
—
—
—
CMPE
—
RIE
1
0
0
0
x
0
0
0
Value after reset:
x: Undefined
Bit
Symbol
Bit Name
Description
R/W
b0
RIE
Voltage Monitor 2 Interrupt/Reset
Enable
0: Disable
1: Enable.
R/W
b1
—
Reserved
The read value is 0. The write value should be 0.
R/W
b2
CMPE
Voltage Monitor 2 Circuit
Comparison Result Output Enable
0: Disable voltage monitor 2 circuit comparison result
output
1: Enable voltage monitor 2 circuit comparison result
output.
R/W
b3
—
Reserved
The read value is undefined. The write value should be 1.
R/W
b5, b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
RI
Voltage Monitor 2 Circuit Mode
Select
0: Generate voltage monitor 2 interrupt on Vdet2 passage
1: Enable voltage monitor 2 reset when the voltage falls to
or below Vdet2.
R/W
b7
RN
Voltage Monitor 2 Reset Negate
Select
0: Negate after stabilization time (tLVD2) when VCC > Vdet2
is detected
1: Negate after stabilization time (tLVD2) on assertion of the
LVD2 reset.
R/W
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
RIE bit (Voltage Monitor 2 Interrupt/Reset Enable)
The RIE bit enables or disables the voltage monitor 2 interrupt/reset. Set this bit to ensure that neither a voltage monitor
2 interrupt nor a voltage monitor 2 reset is generated during programming or erasure of the flash memory.
RN bit (Voltage Monitor 2 Reset Negate Select)
If the RN bit is to be set to 1 (negation follows a stabilization time after the assertion of the LVD2 reset signal), set the
MOCOCR.MCSTP bit to 0 (the MOCO operates). Additionally, for a transition to Software Standby mode, the only
possible value for the RN bit is 0 (negation follows a stabilization time after VCC > Vdet2 is detected). Do not set the RN
bit to 1 (negation follows a stabilization time after the assertion of the LVD2 reset signal) when this is the case.
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8.3
8.3.1
8. Low Voltage Detection (LVD)
VCC Input Voltage Monitor
Monitoring Vdet0
The comparison results from voltage monitor 0 are not available for reading.
8.3.2
Monitoring Vdet1
Table 8.2 shows the procedure to set up monitoring against Vdet1. After the settings are complete, the comparison results
from voltage monitor 1 can be monitored using the LVD1SR.MON flag.
Table 8.2
Procedure to set up monitoring against Vdet1
Step
Monitoring the comparison results from voltage monitor 1
Setting the voltage
detection 1 circuit
Enabling output
8.3.3
1
Set LVCMPCR.LVD1E = 0 to disable voltage detection 1 before writing to the LVDLVLR register.
2
Select the detection voltage in the LVDLVLR.LVD1LVL[4:0] bits.
3
Set LVCMPCR.LVD1E = 1 to enable the voltage detection 1 circuit.
4
Wait for at least td(E-A) for LVD operation stabilization after LVD is enabled.
5
Set LVD1CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 1.
Monitoring Vdet2
Table 8.3 shows the procedure to set up monitoring against Vdet2. After the settings are complete, the comparison results
from voltage monitor 2 can be monitored using the LVD2SR.MON flag.
Table 8.3
Procedure to set up monitoring against Vdet2
Step
Setting the voltage
detection 2 circuit
Enabling output
Monitoring the comparison results from voltage monitor 2
1
Set LVCMPCR.LVD2E = 0 to disable voltage detection 2 before writing to the LVDLVLR register.
2
Select the detection voltage in the LVDLVLR.LVD2LVL[2:0] bits.
3
Set LVCMPCR.LVD2E = 1 to enable the voltage detection 2 circuit.
4
Wait for at least td(E-A) for LVD operation stabilization after LVD is enabled.
5
Set LVD2CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 2.
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8.4
8. Low Voltage Detection (LVD)
Reset from Voltage Monitor 0
When using the reset from voltage monitor 0, clear the OFS1.LVDAS bit to 0 to enable the voltage monitor 0 reset after
a reset. However, at boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS
bit. Figure 8.4 shows an example operation of a voltage monitor 0 reset.
*3
Vdet0*1
VPOR*1
External voltage VCC
Power-on reset state
Voltage monitor 0 reset state
RES pin
POR detection signal
(active-low)
Set by OFS1.LVDAS
LVD0 enable/disable
signal (active-low)
Voltage detection 0
signal (active-low)
Internal reset signal
(active-low)
tPOR*2
RSTSR0.PORF
tLVD0*2
RES pin reset
RSTSR0.LVD0RF
Note:
Note 1.
For details on the electrical characteristics, see section 51, Electrical Characteristics.
VPOR indicates the detection level for a power-on reset and Vdet0 indicates the detection level for a voltage monitor 0
reset.
tPOR indicates the period of a power-on reset and tLVD0 indicates the period of a voltage monitor 0 reset.
At power-on, VCC rises to the minimum guaranteed voltage before the POR reset is released.
Note 2.
Note 3.
Figure 8.4
8.5
Example of voltage monitor 0 reset operation
Interrupt and Reset from Voltage Monitor 1
An interrupt or reset can be generated in response to the comparison results from the voltage monitor 1 circuit.
Table 8.4 shows the procedure for setting bits related to the voltage monitor 1 interrupt/reset so that voltage monitoring
occurs. Table 8.5 shows the procedure for setting bits related to the voltage monitor 1 interrupt/reset so that voltage
monitoring stops. Figure 8.5 shows an example of operations for a voltage monitor 1 interrupt. For the operation of the
voltage monitor 1 reset, see Figure 6.2 in section 6, Resets.
When using the voltage monitor 1 circuit in Software Standby mode, set up the circuit using the following procedures.
(1)
Setting in Software Standby mode
When VCC > Vdet1 is detected, negate the voltage monitor 1 reset signal (LVD1CR0.RN = 0) following a
stabilization time.
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Table 8.4
8. Low Voltage Detection (LVD)
Procedure for setting bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so
that the voltage monitor operates
Voltage monitor 1 interrupt
(voltage monitor 1 ELC event output)
Step
Setting the voltage
detection 1 circuit
Setting the voltage
monitor 1 interrupt or
reset
Enabling output
Note 1.
Note 2.
Voltage monitor 1 reset
1
Set LVCMPCR.LVD1E = 0 to disable voltage detection 1 before writing to the LVDLVLR register.
2
Select the detection voltage by setting the LVDLVLR.LVD1LVL[3:0] bits.
3
Set LVCMPCR.LVD1E = 1 to enable the voltage detection 1 circuit.
4
Wait for at least td(E-A) for LVD operation stabilization after LVD is enabled.*1
5
Set LVD1CR0.RI = 0 to select the voltage monitor
1 interrupt.
Set LVD1CR0.RI = 1 to select the voltage
monitor 1 reset
Select the type of the reset negation by setting
the LVD1CR0.RN bit.
6
Select the timing of interrupt requests by setting
the LVD1CR1.IDTSEL[1:0] bits
Select the type of interrupt by setting the
LVD1CR1.IRQSEL bit.
-
7
Set LVD1SR.DET = 0.
8
Set LVD1CR0.RIE = 1 to enable the voltage monitor 1 interrupt or reset.*2
9
Set LVD1CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 1.
Steps 5 to 8 can be performed during the wait time of step 4. For details on td(E-A), see section 51, Electrical Characteristics.
Step 8 is not required if only the ELC event signal is to be output.
Table 8.5
Procedure for setting bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so
that the voltage monitor stops
Step
Voltage monitor 1 interrupt (voltage monitor 1 ELC event output), voltage monitor 1 reset
Stopping the enabling
of output
1
Set LVD1CR0.CMPE = 0 to disable output of the comparison results from voltage monitor 1.
2
Set LVD1CR0.RIE = 0 to disable the voltage monitor 1 interrupt or reset.*1
Stopping the voltage
detection 1 circuit
3
Set LVCMPCR.LVD1E = 0 to disable the voltage detection 1 circuit.
Note 1.
Step 2 is not required if only the ELC event signal is to be output.
If the voltage monitor 1 interrupt or voltage monitor 1 reset setting is to be made again after it is used and stopped once,
skip the following steps in the procedures for stopping and setting, depending on the conditions:
Setting or stopping the voltage detection 1 circuit is not required if the settings for the voltage detection 1 circuit do
not change
Setting the voltage monitor 1 interrupt or reset is not required if the settings for the voltage monitor 1 interrupt or
voltage monitor 1 reset do not change.
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8. Low Voltage Detection (LVD)
Figure 8.5 shows an example of the voltage monitor 1 interrupt operation.
VCC
Vdet1
Lower limit on VCC voltage (VCCmin)*1
LVD1SR.MON
Set to 0 by software
LVD1SR.DET bit
LVD1CR1.IDTSEL[1:0] bits are
set to 10b (when drop and rise
are detected)
Voltage monitor 1
interrupt request
Set to 0 by software
LVD1SR.DET bit
LVD1CR1.IDTSEL[1:0] bits are
set to 00b (when rise is detected)
Voltage monitor 1
interrupt request
Set to 0 by software
LVD1SR.DET bit
LVD1CR1.IDTSEL[1:0] bits are
set to 01b (when drop is
detected)
Note 1.
When the voltage monitor 0 reset is not in use, VCC ≥ VCCmin.
Figure 8.5
8.6
Voltage monitor 1
interrupt request
Voltage monitor 1 interrupt operation example
Interrupt and Reset from Voltage Monitor 2
An interrupt or reset can be generated in response to the comparison results from the voltage monitor 2 circuit.
Table 8.6 shows the procedures for setting bits related to the voltage monitor 2 interrupt and voltage monitor 2 reset so
that the voltage monitor operates. Table 8.7 shows the procedure for setting bits related to the voltage monitor 2 interrupt
and voltage monitor 2 reset so that the voltage monitor stops. Figure 8.6 shows an example of operation of the voltage
monitor 2 interrupt. For the operation of the voltage monitor 2 reset, see Figure 6.2 in section 6, Resets.
When using the voltage monitor 2 circuit in Software Standby, set up the circuit using the following procedures:
(1)
Setting in Software Standby mode
When VCC > Vdet2 is detected, clear the LVDD2CR0.RN bit (LVD2CR0.RN = 0) following a stabilization time.
Table 8.6
Procedure for setting bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that
voltage monitor operates (1 of 2)
Voltage monitor 2 interrupt
(voltage monitor 2 ELC event output)
Step
Setting the voltage
detection 2 circuit
Voltage monitor 2 reset
1
Set LVCMPCR.LVD2E = 0 to disable voltage detection 2 before writing to the LVDLVLR register.
2
Select the detection voltage in the LVDLVLR.LVD2LVL[2:0] bits.
3
Set LVCMPCR.LVD2E = 1 to enable the voltage detection 2 circuit.
4
Wait for at least td(E-A) for the LVD operation stabilization after LVD is enabled.*1
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Table 8.6
8. Low Voltage Detection (LVD)
Procedure for setting bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that
voltage monitor operates (2 of 2)
Voltage monitor 2 interrupt
(voltage monitor 2 ELC event output)
Step
Setting the voltage
monitor 2 interrupt or
reset
Enabling output
Note 1.
Note 2.
Voltage monitor 2 reset
5
Set LVD2CR0.RI = 0 to select the voltage monitor
2 interrupt.
Set LVD2CR0.RI = 1 to select the voltage
monitor 2 reset
Select the type of the reset negation by setting
the LVD2CR0.RN bit.
6
Select the timing of interrupt requests by setting
the LVD2CR1.IDTSEL[1:0] bits
Select the type of interrupt by setting the
LVD2CR1.IRQSEL bit.
-
7
Set LVD2SR.DET = 0.
8
Set LVD2CR0.RIE = 1 to enable the voltage monitor 2 interrupt or reset.*2
9
Set LVD2CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 2.
Steps 5 to 8 can be performed during the wait time of step 4. For details on td(E-A), see section 51, Electrical Characteristics.
Step 8 is not required if only the ELC event signal is to be output.
Table 8.7
Procedure for setting bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that
voltage monitor stops
Step
Voltage monitor 2 interrupt (voltage monitor 2 ELC event output), voltage monitor 2 reset
Stopping the enabling
of output
1
Set LVD2CR0.CMPE = 0 to disable output of the comparison results from voltage monitor 2.
2
Set LVD2CR0.RIE = 0 to disable the voltage monitor 2 interrupt or reset*1.
Stopping the voltage
detection 1 circuit
3
Set LVCMPCR.LVD2E = 0 to disable the voltage detection 2 circuit.
Note 1.
Step 2 is not required if only the ELC event signal is to be output.
If the voltage monitor 2 interrupt or reset setting is to be made again after it is used and stopped once, skip the following
steps in the procedures for stopping and setting, depending on the conditions:
Setting or stopping the voltage detection 2 circuit is not required if the settings for the voltage detection 2 circuit do
not change
Setting the voltage monitor 2 interrupt or reset is not required if the settings do not change.
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8. Low Voltage Detection (LVD)
VCC
Vdet2
Lower limit on VCC voltage
(VCCmin)*1
LVD2SR.MON bit
Set to 0 by a program
LVD2CR1.IDTSEL[1:0] bits are
set to 10b (when drop and rise
are detected)
LVD2SR.DET bit
Voltage monitor 2
interrupt request
Set to 0 by a program
LVD2CR1.IDTSEL[1:0] bits are
set to 00b (when rise is
detected)
LVD2SR.DET bit
Voltage monitor 2
interrupt request
Set to 0 by a program
LVD2CR1.IDTSEL[1:0] bits are
set to 01b (when drop is
detected)
Note 1.
Voltage monitor 2
interrupt request
When the voltage monitor 0 reset is not in use, VCC ≥ VCC min.
Figure 8.6
8.7
LVD2SR.DET bit
Example of voltage monitor 2 interrupt operation
Event Link Output
The LVD can output the event signals to the Event Link Controller (ELC).
(1)
Vdet1 Crossing Detection Event
The LVD outputs the event signal when it detects that the voltage has passed the Vdet1 voltage while both the voltage
detection 1 circuit and the voltage monitor 1 circuit comparison result output are enabled.
(2)
Vdet2 Crossing Detection Event
The LVD outputs the event signal when it detects that the voltage has passed the Vdet2 voltage while both the voltage
detection 2 circuit and the voltage monitor 2 circuit comparison result output are enabled.
When enabling the event link output function of the LVD, you must enable the LVD before enabling the LVD event link
function of the ELC. To stop the event link output function of the LVD, you must stop the LVD before disabling the LVD
event link function of the ELC.
8.7.1
Interrupt Handling and Event Linking
The LVD provides bits to individually enable or disable the voltage monitor 1 and 2 interrupts. When an interrupt source
is generated and the interrupt is enabled by the interrupt enable bit, the interrupt signal (LVD1CR0.RIE or
LVD2CR0.RIE) is output to the CPU.
In contrast, as soon as an interrupt source is generated, the event link signal is output as the event signal to the other
module through the ELC, regardless of the state of the interrupt enable bit.
It is possible to output voltage monitor 1 and 2 interrupts in Software Standby mode. The event signals for the ELC in
Software Standby mode are output as follows:
When a Vdet1 or Vdet2 passage event is detected in Software Standby mode, event signals are not generated for the
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8. Low Voltage Detection (LVD)
ELC because the clock is not supplied in Software Standby mode. Because the Vdet1 or Vdet2 passage detection
flags are saved, when the clock supply resumes after returning from Software Standby mode, the event signals for
the ELC are output based on the state of the Vdet1 or Vdet2 detection flags.
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9. Clock Generation Circuit
9.
Clock Generation Circuit
9.1
Overview
The MCU incorporates a clock generation circuit.
Table 9.1 and Table 9.2 list the clock generation circuit specifications. Figure 9.1 shows a block diagram, and Table 9.3
lists the I/O pins.
Table 9.1
Clock generation circuit specifications for the clock sources
Clock source
Description
Specification
Main clock oscillator (MOSC)
Resonator frequency
1 MHz to 20 MHz (up to 5.5 V)
1 MHz to 8 MHz (up to 2.4 V).
External clock input frequency
Up to 20 MHz
External resonator or additional circuit:
ceramic resonator, crystal
Available
Connection pins: EXTAL, XTAL
Drive capability switching
Oscillation stop detection function
Sub-clock oscillator (SOSC)
Resonator frequency
32.768 kHz
External resonator or additional circuit:
crystal resonator
Available
Connection pins: XCIN, XCOUT
Drive capability switching
PLL circuit
Input clock source
MOSC
Input frequency
4 MHz to 12.5 MHz
Frequency multiplication ratio
Selectable from 8 to 31 (1 step)
(multiplication frequency is up to 64 MHz)
Output pulse frequency division ratio
Selectable from 2 and 4
PLL output frequency
24 MHz to 64 MHz
(output frequency division ratio: 2)
24 MHz to 32 MHz
(output frequency division ratio: 4)
High-speed on-chip oscillator
(HOCO)
Oscillation frequency
24/32/48/64 MHz
User trimming
Available
Middle-speed
on-chip oscillator (MOCO)
Oscillation frequency
8 MHz
User trimming
Low-speed on-chip oscillator (LOCO) Oscillation frequency
Available
32.768 kHz
User trimming
Available
IWDT-dedicated on-chip oscillator
(IWDTLOCO)
Oscillation frequency
15 kHz
User trimming
Not available
External clock input for JTAG (TCK)
Input clock frequency
Up to 12.5 MHz
External clock input for SWD
(SWCLK)
Input clock frequency
Up to 12.5 MHz
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Table 9.2
9. Clock Generation Circuit
Clock generation circuit specifications for the internal clocks
Clock
Clock source
Clock supply
Specification
System clock (ICLK)
MOSC/SOSC/HOCO/
MOCO/ LOCO/PLL
CPU, DTC, DMAC, Flash,
SRAM
Up to 48 MHz
Division ratios: 1/2/4/8/16/32/64
Peripheral module clock A
(PCLKA)
MOSC/SOSC/HOCO/
MOCO/LOCO/PLL
Peripheral module (QSPI,
SPI, SCI, SCE5, SDHI, CRC,
GPT bus-clock)
Up to 48 MHz
Division ratios: 1/2/4/8/16/32/64
Peripheral module clock B
(PCLKB)
MOSC/SOSC/HOCO/
MOCO/LOCO/PLL
Peripheral module (DAC12,
IIC, SSIE, DOC, CAC, CAN,
AGT, POEG, CTSU, ELC, I/O
ports, RTC, WDT, IWDT,
ADC14, KINT, USBFS,
ACMPLP, and SLCDC)
Up to 32 MHz
Division ratios: 1/2/4/8/16/32/64
Peripheral module clock C
(PCLKC)
MOSC/SOSC/HOCO/
MOCO/LOCO/PLL
Peripheral module
(ADC14 conversion clock)
Up to 64 MHz
Division ratios: 1/2/4/8/16/32/64
Peripheral module clock D
(PCLKD)
MOSC/SOSC/HOCO/
MOCO/LOCO/PLL
Peripheral module
(GPT count clock)
Up to 64 MHz
Division ratios: 1/2/4/8/16/32/64
Flash interface clock (FCLK)
MOSC/SOSC/HOCO/
MOCO/LOCO/PLL
Flash interface
1 MHz to 32 MHz (P/E)
Up to 32 MHz (Read)
Division ratios: 1/2/4/8/16/32/64
External bus clock (BCLK)
MOSC/SOSC/HOCO/
MOCO/LOCO/PLL
External bus
Up to 24 MHz
Division ratios: 1/2/4/8/16/32/64
EBCLK pin output (EBCLK)
BCLK or 1/2 BCLK
EBCLK pin
Up to 12 MHz
Division ratios: 1 or 2
USB clock (UCLK)
HOCO*1/PLL
USBFS
48 MHz
CAN clock (CANMCLK)
MOSC
CAN
1 MHz to 20 MHz
Segment LCD clock
(LCDSRCCLK)
MOSC/SOSC/HOCO/
MOCO/LOCO
SLCDC
Up to 64 MHz
AGT clock
(AGTSCLK/AGTLCLK)
SOSC/LOCO
AGT
32.768 kHz
CAC main clock (CACMCLK)
MOSC
CAC
Up to 20 MHz
CAC sub-clock (CACSCLK)
SOSC
CAC
32.768 kHz
CAC LOCO clock (CACLCLK)
LOCO
CAC
32.768 kHz
CAC MOCO clock (CACMOCLK)
MOCO
CAC
8 MHz
CAC HOCO clock (CACHCLK)
HOCO
CAC
24/32/48/64 MHz
CAC IWDTLOCO clock
(CACILCLK)
IWDTLOCO
CAC
15 kHz
RTC clock (RTCSCLK/RTCLCLK) SOSC/LOCO
RTC
32.768 kHz
IWDT clock (IWDTCLK)
IWDT
15 kHz
IWDTLOCO
SysTick timer clock (SYSTICCLK) LOCO
SysTick Timer
32.768 kHz
JTAG clock (JTAGTCK)
TCK pin
JTAG
Up to 12.5 MHz
Clock/buzzer output (CLKOUT)
MOSC/SOSC/LOCO/
MOCO/HOCO
CLKOUT pin
Up to 16 MHz
Division ratios: 1/2/4/8/16/32/64/128
Serial wire clock (SWCLK)
SWCLK pin
OCD
Up to 12.5 MHz
Trace clock (TRCLK)
MOSC/SOSC/HOCO/
MOCO/LOCO/PLL
CPU-OCD
Up to 48 MHz
Division ratios: 1/2/4
Note:
Note:
Note 1.
Restrictions on setting the clock frequency: ICLK ≥ PCLKA ≥ PCLKB, PCLKD ≥ PCLKA ≥ PCLKB, ICLK ≥ FCLK, ICLK ≥ BCLK
Restrictions on the clock frequency ratio: (N: integer, and up to 64)
ICLK:FCLK = N:1, ICLK:BCLK = N:1, ICLK:PCLKA = N:1, ICLK:PCLKB = N:1
ICLK:PCLKC = N:1 or 1:N, ICLK:PCLKD = N:1 or 1:N
PCLKB:PCLKC = 1:1 or 1:2 or 1:4 or 2:1 or 4:1 or 8:1.
The minimum FCLK frequency is 1 MHz in Programming/Erasure (P/E) mode.
Only when USBFS is used as the device controller.
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9. Clock Generation Circuit
SCKDIVCR FCK[2:0]
PLLMUL[4:0]
PLLCCR2
PLL circuit
Frequency
divider
Selector
PLODIV[1:0]
PLLCCR2
CKSEL[2:0]
Flash interface clock (FCLK)
To flash interface
XCIN
XCOUT
Main clock
oscillator
Sub-clock
oscillator
Main clock
SCKDIVCR ICK[2:0]
1/1
1/2
1/4
1/8
1/16
1/32
1/64
Oscillation
wait control
System clock (ICLK)
To CPU, DMAC, FLASH,
and SRAM
PCKA[2:0]
SCKDIVCR PCKB[2:0]
PCKC[2:0]
PCKD[2:0]
Sub-clock
Selector
Selector
Selector
EXTAL
Selector
XTAL
Oscillation
wait control
Frequency
divider
Selector
Oscillation
stop detection
circuit
Selector
SCKSCR
Peripheral module clock
PCLKA (High-speed peripheral bus)
PCLKB (Peripheral bus)
PCLKC (ADC14)
PCLKD (GPT)
BCKCR BCLKDIV
Selector
SCKDIVCR BCK[2:0]
Selector
1/2
High-speed
clock
Oscillation
wait control
External bus clock (BCLK)
To external bus controller
TRCKCR
Selector
High-speed on-chip
oscillator
24/32/48/64 MHz
EBCLK pin
TRCK[3:0]
Trace Clock (TRCLK)
To Cortex-M4 Debugger
Low-speed on-chip
oscillator
32.768 kHz
Middlespeed clock
USBCKCR
CKODIV[2:0]
CKOSEL[2:0]
Selector
CKOCR
IWDT dedicated
on-chip oscillator
15 kHz
LCD clock (LCDSRCCLK)
To LCDC
SysTick timer (SYSTICCLK)
AGT clock (AGTSCLK)
To AGT (AGTLCLK)
Low-speed
clock
IWDT
low-speed clock
CKOCR
Selector
Middle-speed
on-chip
oscillator
8 MHz
Selector
SLCDSCKCR LCDSCKSEL[2:0]
USBCLKSEL
USB clock (UCLK)
To USB
Frequency
divider
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Clock/buzzer output (CLKOUT)
To CLKOUT pin
CAN clock (CANMCLK)
To CAN
IWDT clock (IWDTCLK)
To IWDT
CAC clock
To CAC
RTC clock (RTCLCLK)
To RTC (RTCSCLK)
JTAG clock (JTAGTCK)
To TAP controller
Serial wire clock (SWCLK)
To TAP controller
TCK/SWCLK pin
Figure 9.1
(CACILCLK)
(CACLCLK)
(CACMOCLK)
(CACHCLK)
(CACSCLK)
(CACMCLK)
Clock generation circuit block diagram
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9. Clock Generation Circuit
Table 9.3 lists the input and output pins of the clock generation circuit.
Table 9.3
Clock generation circuit input/output pins
Pin name
I/O
Description
XTAL
Output
EXTAL
Input
These pins are used to connect a crystal resonator. The EXTAL pin can also be
used to input an external clock. For details, see section 9.3.2, External Clock Input.
XCIN
Input
XCOUT
Output
TCK/SWCLK
Input
This pin is used to input the clock for the JTAG
EBCLK
Output
This pin is used to supply external devices with the external bus clock (EBCLK)
CLKOUT
Output
This pin is used to output the CLKOUT/BUZZER clock
9.2
These pins are used to connect to a 32.768 kHz crystal resonator
Register Descriptions
9.2.1
System Clock Division Control Register (SCKDIVCR)
Address(es): SYSTEM.SCKDIVCR 4001 E020h
b31
b30
b29
—
Value after reset:
FCK[2:0]
b27
b26
—
b25
b24
ICK[2:0]
b23
b22
b21
b20
b19
—
—
—
—
—
b18
b17
b16
BCK[2:0]
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
Value after reset:
b28
0
PCKA[2:0]
1
0
—
0
0
PCKB[2:0]
1
0
—
0
0
PCKC[2:0]
1
0
—
0
0
PCKD[2:0]
1
0
Bit
Symbol
Bit name
b2 to b0
PCKD[2:0]
Peripheral Module Clock D
(PCLKD) Select*4
b3
—
Reserved
b6 to b4
PCKC[2:0]
Peripheral Module Clock C
(PCLKC) Select*4
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10 to b8
PCKB[2:0]
Peripheral Module Clock B
(PCLKB) Select*3
b10
R/W
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Description
0
b2
R/W
R/W
b0
0 0 0: × 1/1
0 0 1: × 1/2
0 1 0: × 1/4
0 1 1: × 1/8
1 0 0: × 1/16
1 0 1: × 1/32
1 1 0: × 1/64.
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
b6
R/W
b4
0 0 0: × 1/1
0 0 1: × 1/2
0 1 0: × 1/4
0 1 1: × 1/8
1 0 0: × 1/16
1 0 1: × 1/32
1 1 0: × 1/64.
Other settings are prohibited.
b8
0 0 0: × 1/1
0 0 1: × 1/2
0 1 0: × 1/4
0 1 1: × 1/8
1 0 0: × 1/16
1 0 1: × 1/32
1 1 0: × 1/64.
Other settings are prohibited.
R/W
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Bit
Symbol
Bit name
Description
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b14 to b12
PCKA[2:0]
Peripheral Module Clock A
(PCLKA) Select*3
b14
R/W
b15
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b18 to b16
BCK[2:0]
External Bus Clock (BCLK)
Select*2
b18
R/W
b23 to b19
—
Reserved
b12
0 0 0: × 1/1
0 0 1: × 1/2
0 1 0: × 1/4
0 1 1: × 1/8
1 0 0: × 1/16
1 0 1: × 1/32
1 1 0: × 1/64.
Other settings are prohibited.
b16
0 0 0: × 1/1
0 0 1: × 1/2
0 1 0: × 1/4
0 1 1: × 1/8
1 0 0: × 1/16
1 0 1: × 1/32
1 1 0: × 1/64.
Other settings are prohibited.
These bits are read as 0. The write value should be 0. R/W
Select*1,
b26 to b24
ICK[2:0]
System Clock (ICLK)
*2, *3, *4, *5
b27
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b30 to b28
FCK[2:0]
Flash Interface Clock (FCLK)
Select*1
b30
R/W
b31
—
Reserved
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
b26
R/W
b24
0 0 0: × 1/1
0 0 1: × 1/2
0 1 0: × 1/4
0 1 1: × 1/8
1 0 0: × 1/16
1 0 1: × 1/32
1 1 0: × 1/64.
Other settings are prohibited.
b28
0 0 0: × 1/1
0 0 1: × 1/2
0 1 0: × 1/4
0 1 1: × 1/8
1 0 0: × 1/16
1 0 1: × 1/32
1 1 0: × 1/64.
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
R/W
The following association is required between the frequencies of the system clock (ICLK) and the flash interface clock (FCLK):
ICLK:FCLK = N:1 (N: integer)
If a setting is made where ICLK < FCLK, then that setting is ignored.
The following association is required between the frequencies of the system clock (ICLK) and the external bus clock (BCLK):
ICLK:BCLK = N:1 (N: integer)
If a setting is made where ICLK < BCLK, then that setting is ignored.
The following association is required between the frequencies of the system clock (ICLK) and the peripheral module clocks
(PCLKA, PCLKB):ICLK:PCLKA = N:1, ICLK:PCLKB = N:1 (N: integer)
If a setting is made where ICLK < PCLKA or ICLK < PCLKB, then that setting is ignored.
The following association is required between the frequencies of the system clock (ICLK) and the peripheral module clocks
(PCLKC, PCLKD): ICLK:PCLKC, PCLKD = N:1 or 1:N (N: integer)
Selecting division by 1 to ICLK is prohibited when SCKSCR.CKSEL[2:0] bits select the system clock source that is faster than
32 MHz and MEMWAIT.MEMWAIT = 0.
The SCKDIVCR register selects the frequencies of the system clock (ICLK), the peripheral module clock (PCLKA,
PCLKB, PCLKC, PCLKD), the flash interface clock (FCLK), and the external bus clock (BCLK).
PCKD[2:0] bits (Peripheral Module Clock D (PCLKD) Select)
The PCKD[2:0] bits select the frequency of peripheral module clock D (PCLKD).
PCKC[2:0] bits (Peripheral Module Clock C (PCLKC) Select)
The PCKC[2:0] bits select the frequency of peripheral module clock C (PCLKC).
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9. Clock Generation Circuit
PCKB[2:0] bits (Peripheral Module Clock B (PCLKB) Select)
The PCKB[2:0] bits select the frequency of peripheral module clock B (PCLKB).
PCKA[2:0] bits (Peripheral Module Clock A (PCLKA) Select)
The PCKA[2:0] bits select the frequency of peripheral module clock A (PCLKA).
BCK[2:0] bits (External Bus Clock (BCLK) Select)
The BCK[2:0] bits select the frequency of the external bus clock (BCLK).
ICK[2:0] bits (System Clock (ICLK) Select*1, *2, *3, *4, *5)
The ICK[2:0] bits select the frequency of the system clock for the CPU, DMAC, and DTC.
FCK[2:0] bits (Flash Interface Clock (FCLK) Select)
The FCK[2:0] bits select the frequency of the flash interface clock (FCLK).
9.2.2
System Clock Source Control Register (SCKSCR)
Address(es): SYSTEM.SCKSCR 4001 E026h
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
Value after reset:
b2
b0
CKSEL[2:0]
0
Bit
Symbol
Bit name
b2 to b0
CKSEL[2:0]
Clock Source Select*1
b7 to b3
—
Reserved
Note 1.
b1
0
1
Description
b2
R/W
R/W
b0
0 0 0: HOCO
0 0 1: MOCO
0 1 0: LOCO
0 1 1: Main clock oscillator (MOSC)
1 0 0: Sub-clock oscillator (SOSC)
1 0 1: PLL.
Other settings are prohibited.
These bits are read as 0. The write value should be 0.
R/W
Selecting a system clock source that is faster than 32 MHz (system clock source > 32 MHz) is prohibited when the
SCKDIVCR.ICK[2:0] bits select division by 1 and MEMWAIT.MEMWAIT = 0.
The SCKSCR register selects the clock source for the system clock.
CKSEL[2:0] bits (Clock Source Select)
The CKSEL[2:0] bits select the clock source for the following modules:
System clock (ICLK)
Peripheral module clocks (PCLKA, PCLKB, PCLKC, and PCLKD)
Flash interface clock (FCLK)
External bus clock (BCLK).
The bits select from one of the following sources:
Low-speed on-chip oscillator (LOCO)
Middle-speed on-chip oscillator (MOCO)
High-speed on-chip oscillator (HOCO)
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
PLL circuit.
Transitions to clock sources that are not in operation are prohibited.
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9.2.3
9. Clock Generation Circuit
PLL Clock Control Register 2 (PLLCCR2)
Address(es): SYSTEM.PLLCCR2 4001 E02Bh
b7
b6
b5
PLODIV[1:0]
0
Value after reset:
b4
b3
—
0
b2
b1
b0
1
1
PLLMUL[4:0]
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
PLLMUL[4:0]
PLL Frequency Multiplication
Factor Select *1
b4
R/W
b5
—
Reserved
b7, b6
PLODIV[1:0]
PLL Output Frequency Division
Ratio Select *1
b0
0 0 1 1 1: × 8
0 1 0 0 0: × 9
0 1 0 0 1: × 10
…
1 1 1 0 1: × 30
1 1 1 1 0: × 31
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
R/W
R/W
b7 b6
0 0: Reserved
0 1: /2
1 0: /4
Other settings are prohibited.
Note 1. PLLMUL[4:0] and PLODIV[1:0] must be set so that the frequency of the PLL output signal is within the range
shown in Table 9.1.
The PLLCCR2 register sets the operation of the PLL circuit. Writing to the PLLCCR2 is prohibited when the
PLLCR.PLLSTP bit is 0, that is, when the PLL is operating.
PLLMUL[4:0] bits (PLL Frequency Multiplication Factor Select)
The PLLMUL[4:0] bits select the frequency multiplication factor of the PLL circuit.
PLODIV[1:0] bits (PLL Output Frequency Division Ratio Select)
The PLODIV[1:0] bits select the frequency division ratio of the PLL output.
9.2.4
PLL Control Register (PLLCR)
Address(es): SYSTEM.PLLCR 4001 E02Ah
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
PLLST
P
0
0
0
0
0
0
0
1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
PLLSTP
PLL Stop Control
0: PLL is operating*1
1: PLL is stopped.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. When operating the PLL, VCC must be more than 2.4 V (VCC ≥ 2.4 V), and operation power control mode must
be set to High-speed mode or Middle-speed mode.
The PLLCR register controls the operation of the PLL circuit.
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9. Clock Generation Circuit
PLLSTP bit (PLL Stop Control)
The PLLSTP bit starts or stops the PLL circuit.
After setting the PLLSTP bit to 0, confirm that the OSCSF.PLLSF bit is set to 1 before using the PLL clock. A fixed
stabilization wait is required after setting the PLL to start operation. A fixed wait for the oscillations to stop is also
required after stopping the PLL operation.
The following restrictions apply when starting and stopping the PLL operation:
After stopping the PLL, confirm that the OSCSF.PLLSF bit is 0 before restarting the PLL
Confirm that the PLL is in operation and that the OSCSF.PLLSF bit is 1 before stopping the PLL
Regardless of whether the PLL clock is selected as the system clock, after setting the PLL to start operation, confirm
that the OSCSF.PLLSF is set to 1 before executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting to stop the PLL, confirm that the
OSCSF.PLLSF bit is set to 0 before executing the WFI instruction.
Writing 1 to PLLSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 101b (system clock source = PLL).
Make sure that the following conditions apply before writing 0 to PLLSTP:
OSCSF.MOSCSF bit is 1
At least 4 μs has elapsed after PLLSTP is set to 1 (PLL is stopped)
At least 1 μs has elapsed after PLLMUL[4:0] bits are set (to select the PLL frequency multiplication).
9.2.5
External Bus Clock Control Register (BCKCR)
Address(es): SYSTEM.BCKCR 4001 E030h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
BCLKD
IV
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
BCLKDIV
EBCLK Pin Output Select
0: BCLK
1: BCLK/2.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The BCKCR register controls the external bus clock pin.
BCLKDIV bit (EBCLK Pin Output Select)
The BCLKDIV bit selects the clock signal for output from the EBCLK pin. The selected signal can be either the BCLK
clock with frequency selected in the BCK[2:0] bits in SCKDIVCR, or the BCLK clock divided by 2.
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9.2.6
9. Clock Generation Circuit
Memory Wait Cycle Control Register (MEMWAIT)
Address(es): SYSTEM.MEMWAIT 4001 E031h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
MEMW
AIT
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
MEMWAIT
Memory Wait Cycle Select
0: No wait
1: Wait.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Writing 0 to the MEMWAIT bit is prohibited when SCKDIVCR.ICK selects division by 1 and the SCKSCR.CKSEL[2:0] bits
select the system clock source that is faster than 32 MHz (ICLK > 32 MHz).
The MEMWAIT register controls the wait cycle of flash read access.
MEMWAIT bit (Memory Wait Cycle Select)
The MEMWAIT bit selects the wait cycle of flash read access. The wait cycle of flash access is set to no wait
(MEMWAIT = 0) after a reset is released.
Before writing to the MEMWAIT bit, check the ICLK frequency and operation power control mode. The following
restrictions apply when setting the ICLK and operation power control mode, and the MEMWAIT bit:
When setting the ICLK to faster than 32 MHz (ICLK > 32 MHz), set MEMWAIT to 1 while ICLK is 32 MHz or
less (ICLK ≤ 32 MHz) and the operation power control mode is High-speed mode (OPCCR.OPCM[1:0] = 00b).
Setting MEMWAIT to 1 is prohibited in operation modes other than High-speed mode.
Setting the ICLK faster than 32 MHz is prohibited while MEMWAIT = 0.
When setting the ICLK from 32 MHz or faster (ICLK > 32 MHz) to 32 MHz or less (ICLK ≤ 32 MHz), the ICLK
frequency must be set to 32 MHz or less while MEMWAIT = 1.
Setting MEMWAIT to 0 is prohibited while ICLK is faster than 32 MHz. Setting MEMWAIT to 1 is prohibited in
operation modes other than High-speed mode. MEMWAIT can be set to 0 while the ICLK frequency is 32 MHz or
less and operation power control mode is High-speed mode (OPCCR.OPCM[1:0] = 00b).
Table 9.4
MEMWAIT bit setting
MCU operation power control
High-speed mode
MEMWAIT bit
Mode, except High-speed mode
ICLK ≤ 32 MHz
ICLK > 32 MHz
0
×
1
×
: Setting is possible.
×: Setting is not possible.
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9. Clock Generation Circuit
Figure 9.2 shows an example flow when setting the ICLK faster than 32 MHz.
Start
ICLK 32 MHz, MEMWAIT = 0, FCACHEEN = 0
Operation mode
= High-speed mode
No
Set operation mode to
High-speed mode
Yes
Set MEMWAIT bit to 1
Set ICLK > 32 MHz
Write FCACHEIV bit to 1
FCACHEIV = 0?
(Do not invalidate)
No
Yes
Set FCACHEEN bit to 1
End
Figure 9.2
When setting the ICLK > 32 MHz
Figure 9.3 shows an example of setting the ICLK to less than or equal to 32 MHz when ICLK is greater than 32 MHz.
Start
ICLK > 32 MHz, MEMWAIT = 1,
FCACHEEN = 1, High-speed mode
FCACHEEN bit to 0
Set ICLK 32 MHz
Clear MEMWAIT bit to 0
Change the
operation mode from
High-speed mode
No
Yes
Change the operation mode
End
Figure 9.3
When setting the ICLK ≤ 32 MHz when ICLK > 32 MHz
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9.2.7
9. Clock Generation Circuit
Main Clock Oscillator Control Register (MOSCCR)
Address(es): SYSTEM.MOSCCR 4001 E032h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
MOSTP
0
0
0
0
0
0
0
1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
operating*1
b0
MOSTP
Main Clock Oscillator Stop
0: Main clock oscillator is
1: Main clock oscillator is stopped.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
MOMCR register must be set before setting MOSTP to 0.
The MOSCCR register controls the main clock oscillator.
MOSTP bit (Main Clock Oscillator Stop)
The MOSTP bit starts or stops the main clock oscillator.
The main clock oscillator can be started by setting the MOSTP bit to operate. When changing the value of the MOSTP
bit, execute subsequent instructions only after reading the bit to check that its value is updated.
When using the main clock, the Main Clock Oscillator Mode Oscillation Control Register (MOMCR) and the Main
Clock Oscillator Wait Control Register (MOSCWTCR) must be set before setting the MOSTP bit to 0. When the
MOSCCR.MOSTP bit setting is modified for the main clock to run, only use the main clock after confirming that the
OSCSF.MOSCSF bit is set to 1.
A fixed time is required for the oscillation to become stable after setting the main clock oscillator. A fixed time is also
required for the oscillation to stop after stopping the main clock oscillator.
The following restrictions apply when starting and stopping operation:
After stopping the main clock oscillator, confirm that the OSCSF.MOSCSF bit is 0 before restarting the main clock
oscillator
Confirm that the main clock oscillator is operating and that the OSCSF.MOSCSF bit is 1 before stopping the main
clock oscillator
Regardless of whether the main clock oscillator is selected as the system clock, confirm that the OSCSF.MOSCSF
bit is set to 1 before executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting to stop the main clock oscillator, confirm that
the OSCSF.MOSCSF bit is set to 0 before executing the WFI instruction.
Writing 1 to MOSTP is prohibited under the following conditions:
SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC)
SCKSCR.CKSEL[2:0] = 101b (system clock source = PLL)
PLLCR.PLLSTP = 0 (PLL operates).
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9.2.8
9. Clock Generation Circuit
Sub-Clock Oscillator Control Register (SOSCCR)
Address(es): SYSTEM.SOSCCR 4001 E480h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
SOSTP
0
0
0
0
0
0
0
1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
operating*1, *2
b0
SOSTP
Sub-Clock Oscillator Stop
0: Sub-clock oscillator is
1: Sub-clock oscillator is stopped.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
The SOMCR register must be set before setting SOSTP to 0.
The VBTCR1.BPWSWSTP bit must be set before setting the SOSC to operate when the VBATT function is not used. See
section 12, Battery Backup Function for details on the VBTCR1.BPWSWSTP.
The SOSCCR register controls the sub-clock oscillator.
SOSTP bit (Sub-Clock Oscillator Stop)
The SOSTP bit starts or stops the sub-clock oscillator.
When changing the value of the SOSTP bit, execute subsequent instructions after reading the bit and checking that its
value is updated. Use the SOSTP bit when the sub-clock is used as the source for a peripheral module such as the RTC.
When using the sub-clock oscillator, set the Sub-Clock Oscillator Mode Control Register (SOMCR) before setting
SOSTP to 0. After setting SOSTP to 0, use the sub-clock oscillator only after the sub-clock oscillation stabilization time
(tSUBOSCOWT) elapses. A fixed stabilization wait time is required for oscillation to become stable after selecting the subclock operation with the SOSTP bit. A fixed time is also required for oscillation to actually stop after setting the SOSTP
bit.
The following restrictions apply when starting and stopping operation:
When restarting the sub-clock oscillator after it stops, allow a period of at least 5 SOSC clock cycles for it to remain
stopped
Confirm that the sub-clock oscillator is stable when stopping the sub-clock oscillator
Regardless of whether the sub-clock oscillator is selected as the system clock, ensure that the sub-clock oscillator
oscillation is stable before executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting to stop the sub-clock oscillator, wait for at least
3 SOSC clock cycles after setting the sub-clock oscillator to stop, before executing the WFI instruction.
Writing 1 to SOSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 100b (system clock source = SOSC).
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9.2.9
9. Clock Generation Circuit
Low-Speed On-Chip Oscillator Control Register (LOCOCR)
Address(es): SYSTEM.LOCOCR 4001 E490h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
LCSTP
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
clock*1
b0
LCSTP
LOCO Stop
0: Operate the LOCO
1: Stop the LOCO clock.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
The VBTCR1.BPWSWSTP bit must be set before setting the LOCO to operate, when VBATT function is not used. See section
12, Battery Backup Function, for details on VBTCR1.BPWSWSTP.
The LOCOCR register controls the LOCO clock.
LCSTP bit (LOCO Stop)
The LCSTP bit starts or stops the LOCO clock.
After setting the LCSTP bit to start the LOCO clock, only use the clock after the LOCO clock-oscillation stabilization
waiting time (tLOCOWT) elapses. A fixed stabilization wait time is required after setting the LOCO clock to start
operation. A fixed wait time for oscillation to stop is also required.
The following restrictions apply when starting and stopping operation:
After stopping the LOCO clock, allow a stop interval of at least 5 LOCO clock cycles before restarting it
Confirm that LOCO oscillation is stable before stopping the LOCO clock
Regardless of whether the LOCO clock is selected as the system clock, confirm that LOCO oscillation is stable
before executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting to stop the LOCO clock, wait for at least 3
LOCO cycles before executing the WFI instruction.
Writing 1 to LOSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 010b (system clock source = LOCO).
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9.2.10
9. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register (HOCOCR)
Address(es): SYSTEM.HOCOCR 4001 E036h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
HCSTP
0
0
0
0
0
0
0
0/1*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
clock*2, *3
b0
HCSTP
HOCO Stop
0: Operate the HOCO
1: Stop the HOCO clock.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Note:
Note 1.
Note 2.
Note 3.
Writing to OPCCR.OPCM[1:0] is prohibited while HOCOCR.HCSTP = 0 and OSCSF.HOCOSF = 0 (HOCO is in stabilization
wait counting).
Writing to HCSTP is prohibited while OPCCR.OPCMTSF = 1 or SOPCCR.SOPCMTSF = 1 (during transition of operating
power control mode) or FLSTOP.CFLSTOPF = 1 (during transition of flash).
The HCSTP bit value after a reset is 0 when the OFS1.HOCOEN bit is 0. It is 1 when the OFS1.HOCOEN bit is 1.
If the operating frequency of HOCO is 48 MHz, VCC must be more than 1.8 V (VCC ≥ 1.8 V) when operating the HOCO.
If the operating frequency of HOCO is 64 MHz, VCC must be more than 2.4 V (VCC ≥ 2.4 V) when operating the HOCO.
When using the HOCO (HCSTP = 0), you must set the OFS1.HOCOFRQ1 bit to an optimum value. During low-voltage mode,
HOCOCR.HCSTP must always be 0.
The HOCOCR register controls the HOCO clock.
HCSTP bit (HOCO Stop)
The HCSTP bit starts or stops the HOCO clock. For the HOCO clock to operate, the High-Speed On-Chip Oscillator
Wait Control Register (HOCOWTCR) must also be set.
After setting the HCSTP bit to 0 to start the HOCO clock, confirm that the OSCSF.HOCOSF is set to 1 before using the
clock. When OFS1.HOCOEN is set to 1, confirm that the OSCSF.HOCOSF is also set to 1 before using the HOCO
clock. A fixed stabilization wait time is required after setting the HOCO clock to start operation. A fixed wait time for
oscillation to stop is also required.
The following limitations apply when starting and stopping operation:
After stopping the HOCO clock, confirm that the OSCSF.HOCOSF bit is 0 before restarting the HOCO clock
Confirm that the HOCO clock operates and that the OSCSF.HOCOSF bit is 1 before stopping the HOCO clock
Regardless of whether the HOCO clock is selected as the system clock, confirm that the OSCSF.HOCOSF bit is set
to 1 before executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting of the HOCO clock to stop, confirm that the
OSCSF.HOCOSF bit is set to 0, before executing the WFI instruction.
Writing 1 to HCSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 000b (system clock source = HOCO).
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9.2.11
9. Clock Generation Circuit
Middle-Speed On-Chip Oscillator Control Register (MOCOCR)
Address(es): SYSTEM.MOCOCR 4001 E038h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
MCSTP
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
MCSTP
MOCO Stop
0: Operate the MOCO clock
1: Stop the MOCO clock.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The MOCOCR register controls the MOCO clock.
MCSTP bit (MOCO Stop)
The MCSTP bit starts or stops the MOCO clock.
After setting MCSTP to 0, use the MOCO clock only after the MOCO clock oscillation stabilization time (tMOCOWT)
elapses. A fixed stabilization wait time is required after setting MCSTP to 0. A fixed stabilization wait time is also
required for oscillation to stop after setting MCSTP to 1.
The following restrictions apply when starting and stopping the MOCO clock:
After stopping the MOCO clock, allow a stop interval of at least 5 MOCO clock cycles before restarting it
Confirm that MOCO oscillation is stable before stopping the MOCO clock
Regardless of whether the MOCO is selected as the system clock, confirm that MOCO oscillation is stable before
executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting to stop the MOCO clock, wait for at least 3
MOCO clock cycles before executing the WFI instruction.
Writing 1 to MCSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 001b (system clock source = MOCO).
Writing 1 to the MCSTP bit (stopping the MOCO) is prohibited if oscillation stop detection is enabled in the Oscillation
Stop Detection Enable bit (OSTDCR.OSTDE) in the Oscillation Stop Detection Control Register.
Because the MOCO clock is used to measure the waiting time for other oscillators, the MOCO clock continues to
oscillate while measuring this time, regardless of the setting of MOCOCR.MCSTP. The MOCO clock may be
unintentionally supplied even when the MCSTP is set to stop.
9.2.12
Oscillation Stabilization Flag Register (OSCSF)
Address(es): SYSTEM.OSCSF 4001 E03Ch
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
PLLSF
—
MOSC
SF
—
—
HOCO
SF
0
0
0
0
0
0
0
0/1*1
Bit
Symbol
Bit name
Description
R/W
b0
HOCOSF
HOCO Clock Oscillation
Stabilization Flag
0: The HOCO clock is stopped or is not stable yet
1: The HOCO clock is stable, so is available for use as
the system clock.
R
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9. Clock Generation Circuit
Bit
Symbol
Bit name
b2, b1
—
b3
MOSCSF
b4
—
b5
PLLSF
b7, b6
—
Note 1.
Note 2.
Description
R/W
Reserved
These bits are read as 0.
R
Main Clock Oscillation
Stabilization Flag
0: The main clock oscillation is stopped (MOSTP = 1) or
is not stable yet*2
1: The main clock oscillator is stable, so is available for
use as the system clock.
R
Reserved
This bit is read as 0
R
PLL Clock Oscillation Stabilization
Flag
0: The PLL clock is stopped or oscillation of the PLL clock
is not stable yet
1: The PLL clock is stable, so is available for use as the
system clock.
R
Reserved
These bits are read as 0
R
The value after reset depends on the OFS1.HOCOEN bit setting. When setting OFS1.HOCOEN = 1, OSCSF.HOCOSF value
becomes 0 just after reset is released, and OSCSF.HOCOSF value becomes 1 after the HOCO oscillation stabilization time is
elapses.
An appropriate value is set in the Wait Control register for the given oscillator. If the wait time is not sufficient, the oscillation
stabilization flag is set to 1 and supply of the clock signal to the internal circuits starts before oscillation is stable.
The OSCSF register contains flags to indicate the operating status of the counters in the oscillation stabilization wait
circuits for the individual oscillators.
After the oscillation starts, the counters measure the wait time until each oscillator output clock is supplied to the internal
circuits. An overflow of a counter indicates the start of the clock supply from the corresponding oscillator to the internal
circuits.
HOCOSF flag (HOCO Clock Oscillation Stabilization Flag)
The HOCOSF flag indicates the operating state of the counter that measures the wait time for the High-speed Clock
Oscillator (HOCO).
When OFS1.HOCOEN is set to 1, confirm that the OSCSF.HOCOSF is also set to 1 before using the HOCO clock.
[Setting condition]
After the HOCO clock stops and the HOCOCR.HCSTP bit is set to 0, the high-speed clock supply in the MCU
starts after the middle-speed clock cycles set in the HOCOWTCR.HSTS[2:0] bits elapse.
[Clearing condition]
When the high-speed clock oscillator is operating, it is deactivated when the HOCOCR.HCSTP bit is set to 1.
MOSCSF flag (Main Clock Oscillation Stabilization Flag)
The MOSCSF flag indicates the operating state of the counter that measures the wait time for the main clock oscillator.
[Setting condition]
After the main clock oscillator stops and the MOSCCR.MOSTP bit is set to 0, supply of the main clock in the MCU
starts after the number of middle-speed clock cycles associated with the setting in the MOSCWTCR.MSTS[3:0]
bits elapse.
[Clearing condition]
When the main clock oscillator is operating, it is deactivated when the MOSCCR.MOSTP bit is set to 1.
PLLSF flag (PLL Clock Oscillation Stabilization Flag)
The PLLSF flag indicates the operating state of the counter that measures the wait time of the PLL.
[Setting condition]
After the PLL stops and the PLLCR.PLLSTP bit is set to 0, supply of the PLL clock in the MCU starts after
370 cycles of the middle-speed clock are counted. If PLL clock source oscillation is not stable when the PLLSTP bit
is set to 0, counting of the middle-speed clock cycles continues after the PLL clock source oscillation is stabilized.
[Clearing condition]
When the PLL operates, it is deactivated when the PLLCR.PLLSTP bit is set to 1.
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9.2.13
9. Clock Generation Circuit
Oscillation Stop Detection Control Register (OSTDCR)
Address(es): SYSTEM.OSTDCR 4001 E040h
b7
b6
b5
b4
b3
b2
b1
b0
OSTDE
—
—
—
—
—
—
OSTDI
E
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
OSTDIE
Oscillation Stop Detection
Interrupt Enable
0: Disable oscillation stop detection interrupt (do not notify
the POEG)
1: Enable oscillation stop detection interrupt (notify the
POEG).
R/W
b6 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
OSTDE
Oscillation Stop Detection
Function Enable
0: Disable the oscillation stop detection function
1: Enable the oscillation stop detection function.
R/W
The OSTDCR register controls the oscillation stop detection function.
OSTDIE bit (Oscillation Stop Detection Interrupt Enable)
The OSTDIE bit enables the oscillation stop detection function interrupt. This bit also controls whether the POEG is
notified about the oscillation stop detection.
If the Oscillation Stop Detection Flag in the Oscillation Stop Detection Status Register (OSTDSR.OSTDF) requires
clearing, set the OSTDIE bit to 0 before OSTDF is set to 0. Wait for at least 2 PCLKB cycles before setting the OSTDIE
bit to 1. Depending on the number of cycles required to read a given I/O register, a wait time longer than 2 PCLKB
cycles might be required.
OSTDE bit (Oscillation Stop Detection Function Enable)
The OSTDE bit enables the oscillation stop detection function. When the OSTDE bit is 1 (oscillation stop detection
function enabled), the MOCO Stop bit (MOCOCR.MCSTP) is set to 0 and the MOCO operation starts. The MOCO
cannot be stopped when the oscillation stop detection function is enabled. Writing 1 to the MOCOCR.MCSTP bit
(MOCO stopped) is invalid.
When the Oscillation Stop Detection Flag in the Oscillation Stop Detection Status Register (OSTDSR.OSTDF) is 1
(main clock oscillation stop detected), writing 0 to the OSTDE bit is invalid.
The OSTDE bit must be set to 0 before transitioning to Software Standby mode. To transition to Software Standby mode,
first set the OSTDE bit to 0, then execute the WFI instruction.
The following restrictions apply when using the oscillation stop detection function:
In low-speed mode, selecting division by 1, 2, 4, 8 for ICLK, FCLK, BCLK, PCLKA, PCLKB, PCLKC, PCLKD is
prohibited
In low-voltage mode, selecting division by 1, 2 for ICLK, FCLK, BCLK, PCLKA, PCLKB, PCLKC, PCLKD is
prohibited.
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9.2.14
9. Clock Generation Circuit
Oscillation Stop Detection Status Register (OSTDSR)
Address(es): SYSTEM.OSTDSR 4001 E041h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
OSTDF
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
OSTDF
Oscillation Stop Detection Flag
0: Main clock oscillation stop not detected
1: Main clock oscillation stop detected.
R(/W)*1
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
This bit can only be set to 0.
The OSTDSR register indicates the stop detection status of the main clock oscillator.
OSTDF flag (Oscillation Stop Detection Flag)
The OSTDF flag indicates the main clock oscillator status. When this flag is 1, it indicates that the main clock oscillation
stop was detected. After this stop is detected, the OSTDF flag is not set to 0 even when the main clock oscillation is
restarted. The OSTDF flag is set to 0 by writing 0 after reading it as 1.
At least 3 ICLK cycles of wait time are required between writing 0 to OSTDF and reading it as 0. If the OSTDF flag is
set to 0 when the main clock oscillation is stopped, the OSTDF flag becomes 0 and then returns to 1.
OSTDSR.OSTDF cannot be set to 0 under the following conditions:
SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC).
The OSTDF flag must be set to 0 after switching the clock source to sources other than the main clock oscillator and
PLL.
[Setting condition]
The main clock oscillation is stopped when OSTDCR.OSTDE is 1 (oscillation stop detection function enabled).
[Clearing condition]
1 is read and then 0 is written when the SCKSCR.CKSEL[2:0] bits are neither 011b (system clock is MOSC) nor
101b (system clock is PLL).
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9.2.15
9. Clock Generation Circuit
Main Clock Oscillator Wait Control Register (MOSCWTCR)
Address(es): SYSTEM.MOSCWTCR 4001 E0A2h
b7
b6
b5
b4
—
—
—
—
0
0
0
0
Value after reset:
b3
b2
b1
b0
MSTS[3:0]
0
Bit
Symbol
Bit name
b3 to b0
MSTS[3:0]
Main Clock Oscillator Wait
Time Setting
b7 to b4
—
Reserved
1
0
1
Description
b3
b0
R/W
0 0 0 0: Wait time = 2 cycles (0.25 μs)
0 0 0 1: Wait time = 1024 cycles (128 μs)
0 0 1 0: Wait time = 2048 cycles (256 μs)
0 0 1 1: Wait time = 4096 cycles (512 μs)
0 1 0 0: Wait time = 8192 cycles (1024 μs)
0 1 0 1: Wait time = 16384 cycles (2048 μs) (value after reset)
0 1 1 0: Wait time = 32768 cycles (4096 μs)
0 1 1 1: Wait time = 65536 cycles (8192 μs)
1 0 0 0: Wait time = 131072 cycles (16384 μs)
1 0 0 1: Wait time = 262144 cycles (32768 μs).
Other settings are prohibited.
Wait time is calculated at MOCO = 8 MHz (typically 0.125 μs).
These bits are read as 0. The write value should be 0.
R/W
R/W
MSTS[3:0] bits (Main Clock Oscillator Wait Time Setting)
The MSTS[3:0] bits specify the oscillation stabilization wait time for the main clock oscillator.
Set the main clock oscillation stabilization time to a period longer than or equal to the stabilization time recommended by
the oscillator manufacturer. When the main clock is input externally, set these bits to 0000b because the oscillation
stabilization time is not required.
The wait time set in the MSTS[3:0] bits is counted using the MOCO clock. The MOCO automatically oscillates when
necessary, regardless of the value of the MOCOCR.MCSTP bit. After the set wait time elapses, supply of the main clock
starts internally in the MCU, and the OSCSF.MOSCSF flag becomes 1. If the set wait time is short, supply of the main
clock starts before oscillation of the clock becomes stable.
Only rewrite the MOSCWTCR register when the MOSCCR.MOSTP bit is 1 and the OSCSF.MOSCSF flag is 0. Do not
rewrite this register under any other conditions.
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9.2.16
9. Clock Generation Circuit
High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR)
Address(es): SYSTEM.HOCOWTCR 4001 E0A5h
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
Value after reset:
b2
b1
b0
HSTS[2:0]
1
Bit
Symbol
Bit name
b2 to b0
HSTS[2:0]
HOCO Wait Time Setting
b7 to b3
—
Reserved
0
1
Description
b2
b0
R/W
1 0 1:
Wait time is 245 cycles (29.13 μs)
When HOCO operating frequency is 24 MHz or 32 MHz,
and the operation power control mode is other than
low-voltage mode.
Wait time is 287 cycles (35.875 μs) (value after reset)
when HOCO operating frequency is 48 MHz and
operation power control mode is other than low-voltage
mode.
Wait time is 679 cycles (84.88 μs) (value after reset)
when operation power control mode is low-voltage
mode.
1 1 0:
Wait time is 541 cycles (67.63 μs)
when HOCO operating frequency is 64 MHz.
Other settings are prohibited.
Wait time calculated at MOCO is 8 MHz (typically 0.125 μs).
These bits are read as 0. The write value should be 0.
R/W
R/W
HOCOWTCR controls the wait time until output of the signal from the high-speed clock oscillator to the internal circuits
starts. Values can only be written to HOCOWTCR when the HOCOCR.HCSTP bit is 1 or the OSCSF.HOCOSF flag is 1.
Do not write to HOCOWTCR under any other conditions.
HSTS[2:0] bits (HOCO Wait Time Setting)
The oscillation stabilization wait circuit measures the wait time and controls the clock supply in the MCU. When the
high speed clock oscillator starts, the oscillation stabilization wait circuit starts counting cycles of the middle-speed clock
set in the HOCOWTCR register. The MCU clock supply is disabled until counting of the set number of cycles is
complete. After counting completes, supply of the clock signal in the MCU starts and the OSCSF.HOCOSF flag is set to
1.
The oscillation stabilization wait circuit continues to count the middle-speed clock cycles regardless of the
MOCOCR.MCSTP bit setting. Hardware automatically controls the running and stopping of the middle-speed oscillator
for wait time measurement.
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9.2.17
9. Clock Generation Circuit
Main Clock Oscillator Mode Oscillation Control Register (MOMCR)
Address(es): SYSTEM.MOMCR 4001 E413h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
MOSEL
—
—
MODR
V1
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
MODRV1
Main Clock Oscillator Drive
Capability 1 Switching
0: 10 MHz to 20 MHz
1: 1 MHz to 10 MHz.
R/W
b5, b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
MOSEL
Main Clock Oscillator Switching
0: Resonator
1: External clock input.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note:
Note:
The EXTAL/XTAL pin is also used as a port. In the initial setting state, the pin is set as a port.
The MOSTP bit must be 1 (MOSC is stopped) before modifying this register.
MODRV1 bit (Main Clock Oscillator Drive Capability 1 Switching)
The MODRV1 bit switches the drive capability of the main clock oscillator.
MOSEL bit (Main Clock Oscillator Switching)
The MOSEL bit switches the source for the main clock oscillator.
9.2.18
Sub-Clock Oscillator Mode Control Register (SOMCR)
Address(es): SYSTEM.SOMCR 4001 E481h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
—
SODRV[1:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
b1, b0
SODRV[1:0]
Sub-Clock Oscillator Drive
Capability Switching
b7 to b2
—
Reserved
0
b0
0
Description
b1 b0
0
0
1
1
0:
1:
0:
1:
R/W
R/W
Normal mode
Low power mode 1
Low power mode 2
Low power mode 3.
These bits are read as 0. The write value should be 0.
R/W
This register must be modified when SOSCCR.SOSTP is 1 (SOSC is stopped).
SODRV[1:0] bits (Sub-Clock Oscillator Drive Capability Switching)
The SODRV[1:0] bits switch the drive capability of the sub-clock oscillator.
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9.2.19
9. Clock Generation Circuit
Segment LCD Source Clock Control Register (SLCDSCKCR)
Address(es): SYSTEM.SLCDSCKCR 4001 E050h
b7
b6
b5
b4
b3
LCDSC
KEN
—
—
—
—
LCDSCKSEL[2:0]
0
0
0
0
0
0
Value after reset:
b2
b1
b0
0
0
Bit
Symbol
Bit name
Description
b2 to b0
LCDSCKSEL[2:0]
LCD Source Clock
(LCDSRCCLK) Select
b6 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
LCDSCKEN
LCD Source Clock Out Enable
0: LCD source clock out disabled
1: LCD source clock out enabled.
R/W
b2
R/W
R/W
b0
0 0 0: LOCO
0 0 1: SOSC
0 1 0: MOSC
1 0 0: HOCO.
Other settings are prohibited.
Setting the LCDSCKEN bit and LCDSCKSEL[2:0] bits at the same time is prohibited.
LCDSCKSEL[2:0] bits (LCD Source Clock (LCDSRCCLK) Select)
The LCDSCKSEL[2:0] bits select the LOCO, SOSC, MOSC, or HOCO clock as the LCD clock source. Clear the
LCDSCKEN bit to 0 when changing the LCD source clock.
When changing these bits, use the following steps:
1. Set LCDSCKEN to 0 (LCD source clock out is disabled).
2. Wait for 3 LCD source clock cycles and 2 ICLK cycles before the change.
3. Write the changed value to LCDSCKSEL[2:0] bits.
4. Read LCDSCKSEL[2:0] bits to confirm that the LCDSCKSEL[2:0] bits are changed.
LCDSCKEN bit (LCD Source Clock Out Enable)
The LCDSCKEN bit enables output of the LCD source clock to LCD module.
When this bit is set to 1, the selected clock is output. When changing this bit, confirm that the LCD source clock selected
by the LCDSCLKSEL[2:0] bits is stable. When transitioning to Software Standby mode after changing this bit, use the
following steps:
1. Change this bit.
2. Wait for at least 2 cycles of the source clock selected in the LCDSCKSEL[2:0] bits.
3. Execute the WFI instruction.
When stopping the source clock selected in the LCDSCKSEL[2:0] bits after clearing this bit to 0, use the following
steps:
1. Clear this bit to 0 (LCD source clock output is disabled).
2. Wait for at least 2 cycles of the source clock selected by the LCDSCKSEL[2:0] bits.
3. Stop the source clock selected by the LCDSCKSEL[2:0] bits.
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9.2.20
9. Clock Generation Circuit
Clock Out Control Register (CKOCR)
Address(es): SYSTEM.CKOCR 4001 E03Eh
b7
b6
CKOEN
0
Value after reset:
b5
b4
CKODIV[2:0]
0
0
b3
b2
—
0
0
b1
b0
CKOSEL[2:0]
0
Bit
Symbol
Bit name
b2 to b0
CKOSEL[2:0]
Clock Out Source Select
b3
—
Reserved
b6 to b4
CKODIV[2:0]
Clock Out Input Frequency
Division Select
b7
CKOEN
Clock Out Enable
0
0
Description
b2
R/W
R/W
b0
0 0 0: HOCO
0 0 1: MOCO
0 1 0: LOCO
0 1 1: MOSC
1 0 0: SOSC.
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
b6
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b4
0:
1:
0:
1:
0:
1:
0:
1:
R/W
R/W
×1
/2
/4
/8
/16
/32
/64
/128.
0: Disable clock out
1: Enable clock out.
R/W
CKOSEL[2:0] bits (Clock Out Source Select)
The CKOSEL[2:0] bits select the HOCO, MOCO, LOCO, MOSC, or SOSC clock as the source clock to be output from
the CLKOUT pin.
When changing the CLKOUT source clock, set the CKOEN bit to 0.
CKODIV[2:0] bits (Clock Out Input Frequency Division Select)
The CKODIV[2:0] bits select the clock division ratio.
When changing the division ratio, set the CKOEN bit to 0. The division ratio of the output clock frequency must be set to
a value no higher than the characteristics of the CLKOUT pin output frequency. See section 51, Electrical Characteristics
for details on the CLKOUT pin characteristics.
CKOEN bit (Clock Out Enable)
The CKOEN bit enables output from the CLKOUT pin.
When this bit is set to 1, the selected clock is output. When this bit is set to 0, low is output. When changing this bit,
confirm that the clock source selected in the CKOSEL[2:0] bits is stable. Otherwise, a glitch might be generated in the
output.
Clear this bit before entering Software Standby mode if the selected clock source is stopped in that mode.
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9.2.21
9. Clock Generation Circuit
External Bus Clock Output Control Register (EBCKOCR)
Address(es): SYSTEM.EBCKOCR 4001 E052h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
EBCKO
EN
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
EBCKOEN
EBCLK Pin Output Control
0: EBCLK pin output is disabled (fixed high)
1: EBCLK pin output is enabled.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
9.2.22
LOCO User Trimming Control Register (LOCOUTCR)
Address(es): SYSTEM.LOCOUTCR 4001 E492h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
LOCOUTRM[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
LOCOUTRM[7:0]
LOCO User Trimming
b7
R/W
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127.
These bits are added to the original LOCO trimming bits.
MCU operation is not guaranteed when LOCOUTCR is set to a value that causes the LOCO frequency to be outside of
the specification range.
When LOCOUTCR is modified, the frequency stabilization time required corresponds to the frequency stabilization time
at the start of the MCU operation. When the ratio of the LOCO clock frequency and the other oscillation frequency is an
integer value, changing the LOCOUTCR value is prohibited.
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9.2.23
9. Clock Generation Circuit
MOCO User Trimming Control Register (MOCOUTCR)
Address(es): SYSTEM.MOCOUTCR 4001 E061h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
MOCOUTRM[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
MOCOUTRM[7:0]
MOCO User Trimming
b7
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127.
These bits are added to the original MOCO trimming bits.
R/W
MCU operation is not guaranteed when MOCOUTCR is set to a value that causes the MOCO frequency to be outside of
the specification range.
When MOCOUTCR is modified, the frequency stabilization wait time corresponds to the time when it is stabilized at the
start of the MCU operation.
When the ratio of the MOCO frequency to the other oscillation frequency is an integer value, changing the MOCOUTCR
value is prohibited.
9.2.24
HOCO User Trimming Control Register (HOCOUTCR)
Address(es): SYSTEM.HOCOUTCR 4001 E062h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
HOCOUTRM[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
HOCOUTRM[7:0]
HOCO User Trimming
b7
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127.
These bits are added to the original HOCO trimming bits.
R/W
MCU operation is not guaranteed when HOCOUTCR is set to a value that causes the HOCO frequency to be outside of
the specification range. When HOCOUTCR is modified, the frequency stabilization wait time corresponds to the time
when it is stabilized at the start of the MCU operation. When USBCKCR.USBCLKSEL = 1, writing any other value
except 00h to HOCOUTCR is prohibited.
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9.2.25
9. Clock Generation Circuit
Trace Clock Control Register (TRCKCR)
Address(es): SYSTEM.TRCKCR 4001 E03Fh
b7
b6
b5
b4
TRCKE
N
—
—
—
0
0
0
0
Value after reset:
b3
b2
b1
b0
TRCK[3:0]
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b3 to b0
TRCK[3:0]
Trace Clock Operation
Frequency Select
b3
R/W
b6 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
TRCKEN
Trace Clock Operating Enable
0: Disable operation
1: Enable operation.
R/W
Note:
b0
0 0 0 0: /1
0 0 0 1: /2 (value after reset)
0 0 1 0: /4.
Other settings are prohibited.
The TRCKCR register can be initialized by all resets except VBATT_POR.
The Trace Clock Control Register controls the switching of the trace clock. Set TRCKEN to 0 before changing the
TRCLK frequency.
9.2.26
USB Clock Control Register (USBCKCR)
Address(es): SYSTEM.USBCKCR 4001 E0D0h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
USBCL
KSEL
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
USBCLKSEL
USB Clock Source Select
0: PLL (value after reset)
1: HOCO.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
USBCLKSEL bit (USB Clock Source Select)
The USBCLKSEL bit selects the source of the USB clock (UCLK).
Rewrite the USBCKCR register while the SYSCFG.SCKE bit is 0
The USBCKCR.USBCLKSEL bit can only be set to 1 when USBFS is used as the device controller.
Set the USBCKSR.USBCLKSEL bit to 0 to use the host controller and the On-The-Go (OTG) function.
The user trimming function cannot be used when the USBCKCR.USBCLKSEL bit is 1. To use the HOCO user
trimming function, set the bits HOCOUTCR.HOCOUTRM[7:0] to 00h.
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9.3
9. Clock Generation Circuit
Main Clock Oscillator
To supply the clock signal to the main clock oscillator, use one of the following ways:
Connect an oscillator
Connect the input of an external clock signal.
9.3.1
Connecting a Crystal Resonator
Figure 9.4 shows an example of connecting a crystal resonator.
A damping resistor (Rd) can be added, if required. Because the resistor values vary according to the resonator and the
oscillation drive capability, use values recommended by the resonator manufacturer. If the manufacturer recommends the
use of an external feedback resistor (Rf), insert an Rf between EXTAL and XTAL by following the instructions.
When connecting a resonator to supply the clock, the frequency of the resonator must be in the frequency range of the
resonator for the main clock oscillator as described in Table 9.1.
CL1
EXTAL
Rf
XTAL
CL2
Rd
Figure 9.4
9.3.2
Example of crystal resonator connection
External Clock Input
Figure 9.5 shows an example for connecting an external clock input. To operate the oscillator with an external clock
signal, set the MOMCR.MOSEL bit to 1. The XTAL pin goes to high impedance.
EXTAL
XTAL
Figure 9.5
9.3.3
External clock input
Hi-Z
Equivalent circuit for external clock
Notes on External Clock Input
The frequency of the external clock input can only be changed when the main clock oscillator is stopped. Do not change
the frequency of the external clock input when the setting of the Main Clock Oscillator Stop bit (MOSCCR.MOSTP) is
0.
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9.4
9. Clock Generation Circuit
Sub-Clock Oscillator
The only way of supplying a clock signal to the sub-clock oscillator is by connecting a crystal oscillator.
9.4.1
Connecting a 32.768-kHz Crystal Resonator
To supply a clock to the sub-clock oscillator, connect a 32.768-kHz crystal resonator, as shown in Figure 9.6.
A damping resistor (Rd) can be added, if necessary. Because the resistor values vary according to the resonator and the
oscillation drive capability, use values recommended by the resonator manufacturer. If the resonator manufacturer
recommends the use of an external feedback resistor (Rf), insert an Rf between XCIN and XCOUT by following the
instructions. When connecting a resonator to supply the clock, the frequency of the resonator must be in the frequency
range of the resonator for the sub-clock oscillator, as described in Table 9.1.
C1
XCIN
Rf
XCOUT
Rd
Figure 9.6
9.5
9.5.1
C2
Connection example of 32.768-kHz crystal resonator
Oscillation Stop Detection Function
Oscillation Stop Detection and Operation after Detection
The oscillation stop detection function detects the main clock oscillator stop.
When oscillation stop is detected, the system clock switches as follows:
If an oscillation stop is detected with SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC), the system
clock source switches to the MOCO clock
If an oscillation stop is detected with SCKSCR.CKSEL[2:0] = 101b (system clock source = PLL), the PLL clock
remains the system clock source. The frequency becomes a free-running oscillation frequency and the setting of
SCKSCR.CKSEL[2:0] is unchanged.
An oscillation stop detection interrupt request can be generated when an oscillation stop is detected. In addition, the
General PWM Timer (GPT) output can be forced to a high-impedance state on detection.
The main clock oscillation stop is detected when the input clock remains at 0 or 1 for a certain period, for example, when
a malfunction occurs in the main clock oscillator. See section 51, Electrical Characteristics.
Switching between the main clock and MOCO clock or between the PLL clock and PLL free-running clock is controlled
by the Oscillation Stop Detection Flag (OSTDSR.OSTDF).
OSTDF controls the switched clock as follows:
SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC):
When OSTDF changes from 0 to 1, the clock source switches to MOCO clock.
When OSTDF changes from 1 to 0, the clock source switches to MOSC again.
SCKSCR.CKSEL[2:0] = 101b (system clock source = PLL):
When OSTDF changes from 0 to 1, the clock source switches to the PLL free-running oscillation clock.
When OSTDF changes from 1 to 0, the clock source switches to PLL again.
To switch the clock source to the main clock or PLL clock again after the oscillation stop detection, set the CKSEL[2:0]
bits to a clock source other than the main clock or PLL clock, and clear the OSTDF flag to 0. Also, check that the
OSTDF flag is not 1, then set the CKSEL[2:0] bits to the main clock or PLL clock after the specified oscillation
stabilization time elapses.
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9. Clock Generation Circuit
After a reset is released, the main clock oscillator stops and the oscillation stop detection function is disabled. To enable
the oscillation stop detection function, activate the main clock oscillator and write 1 to the Oscillation Stop Detection
Function Enable bit (OSTDCR.OSTDE) after a specified oscillation stabilization time elapses.
The oscillation stop detection function detects when the main clock is stopped by an external cause. Therefore, the
oscillation stop detection function must be disabled before the main clock oscillator is stopped by software or a transition
is made to Software Standby mode.
The oscillation stop detection function switches the following clocks to the MOCO clock (when system clock is MOSC):
All clocks that can be selected as the MOSC or PLL except CLKOUT
The system clock (ICLK) frequency during the MOCO (when system clock is MOSC) or PLL free-running (when
system clock is PLL) operation is specified in the MOCO oscillation frequency and the division ratio set in the
System Clock Select bits (SCKDIVCR.ICK[2:0]).
Example of returning from oscillation stop detection when CKSEL[2:0] =
011b (selecting the main clock oscillator).
Start (oscillation stop is detected)
Switch to clock sources other than MOSC
and PLL
Example: Switch to SCKSCR.CKSEL[2:0] =
001b
(selecting the MOCO)
Set OSTDCR.OSTDIE = 0
Read OSTDSR.OSTDF = 1
Yes
Set OSTDSR.OSTDF = 0
OSTDSR.OSTDF = 0?
No
Try again?
Yes
Wait for the specified oscillation stabilization
time
Switch to SCKSCR.CKSEL[2:0] = 011b
(selecting the main clock oscillator)
End
Note:
Figure 9.7
No
On returning from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation
circuit must be removed from the system to allow oscillation to resume.
Flow of recovery on detection of oscillator stop
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9.5.2
9. Clock Generation Circuit
Oscillation Stop Detection Interrupts
An oscillation stop detection interrupt (MOSC_STOP) is generated when the Oscillation Stop Detection Flag
(OSTDSR.OSTDF) is 1 and the Oscillation Stop Detection Interrupt Enable bit in the Oscillation Stop Detection Control
Register (OSTDCR.OSTDIE) is 1 (enabling interrupt generation on oscillation stop detection). The Port Output Enable
for GPT (POEG) is notified of the main clock oscillator stop. On receiving the notification, the POEG sets the Oscillation
Stop Detection Flag in the POEG Group n Setting Register (POEGGn.OSTPF) to 1 (n = A, B).
After the oscillation stop is detected, wait at least 10 PCLKB cycles before writing to the POEGGn.OSTPF flag. When
the OSTDSR.OSTDF flag requires clearing, do so after clearing the Oscillation Stop Detection Interrupt Enable bit in the
Oscillation Stop Detection Control Register (OSTDCR.OSTDIE). Wait at least 2 PCLKB clock cycles before setting the
OSTDCR.OSTDIE bit to 1 again. A longer PCLKB wait time might be required, depending on the number of cycles
required to read out a given I/O register.
The oscillation stop detection interrupt is a non-maskable interrupt. Because non-maskable interrupts are disabled in the
initial state after a reset release, enable the non-maskable interrupts through software before using the oscillation stop
detection interrupts. For details, see section 14, Interrupt Controller Unit (ICU).
9.6
PLL Circuit
The PLL circuit has a function to multiply the frequency from the oscillator.
9.7
Internal Clock
Clock sources for the internal clock signals include:
Main clock oscillator
Sub-clock oscillator
HOCO clock
MOCO clock
LOCO clock
PLL clock
Dedicated clock for the IWDT
External clock for JTAG.
The following internal clocks are produced from these sources:
Operating clock for the CPU, DMAC, DTC, flash memory, and SRAM — system clock (ICLK)
Operating clocks for peripheral modules — PCLKA, PCLKB, PCLKC, and PCLKD
Operating clock for the flash interface— FCLK
Clock for the external bus controller and external pin output — EBCLK
Operating clock for the USBFS — UCLK
Operating clock for the CAN — CANMCLK
Operating clocks for the CAC — CACCLK
Operating clock for the RTC LOCO clock — RTCLCLK
Operating clock for the RTC sub-clock — RTCSCLK
Operating clock for the IWDT — IWDTCLK
Operating clock for the AGT LOCO clock — AGTLCLK
Operating clock for the AGT sub-clock — AGTSCLK
Operating clock for the SysTick timer — SYSTICCLK
Source clock for the SLCDC — LCDSRCCLK
Clock for external pin output — CLKOUT
Operating clock for the JTAG — JTAGTCK.
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9. Clock Generation Circuit
For details on the registers used to set the frequencies of the internal clocks, see section 9.7.1, System Clock (ICLK) to
section 9.7.14, JTAG Clock (JTAGTCK).
If the value of any of these bits is changed, subsequent operation is at a frequency determined by the new value.
9.7.1
System Clock (ICLK)
The system clock, ICLK, is the operating clock for the CPU, DMAC, DTC, flash memory, and SRAM.
The ICLK frequency is specified in the following bits:
ICK[2:0] bits in SCKDIVCR
CKSEL[2:0] bits in SCKSCR
PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2
HOCOFRQ1[2:0] bits in OFS1.
9.7.2
Peripheral Module Clock (PCLKA, PCLKB, PCLKC, PCLKD)
The peripheral module clocks, PCLKA, PCLKB, PCLKC, and PCLKD, are the operating clocks for the peripheral
modules.
The frequency of the given clock is specified in the following bits:
PCKA[2:0], PCKB[2:0], PCKC[2:0], and PCKD[2:0] bits in SCKDIVCR
CKSEL[2:0] bits in SCKSCR
PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2
HOCOFRQ1[2:0] bits in OFS1.
9.7.3
Flash Interface Clock (FCLK)
The flash interface clock, FCLK, is the operating clock for the flash memory interface. In addition to reading from the
data flash, FCLK is used for the programming and erasure of the code flash and data flash.
The FCLK frequency is specified in the following bits:
FCK[2:0] bits in SCKDIVCR
CKSEL[2:0] bits in SCKSCR
PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2
HOCOFRQ1[2:0] bits in OFS1.
9.7.4
External Bus Clock (BCLK)
The external bus clock, BCLK, is the operating clock for the external bus controller. It is also output externally from the
EBCLK pin for the external connection bus.
BCLK can be output from the EBCLK pin by setting the EBCKOCR.EBCKOEN bit to 1 and setting the
PmnPFS.PSEL[4:0] bits to 01011b. Modification of the PmnPFS.PSEL[4:0] bits to 01011b must always be performed
when the EBCKOCR.EBCKOEN bit is 0. When the BCKCR.BCLKDIV bit is set to 1, BCLK clock divided by 2 is
output from the EBCLK pin.
The BCLK frequency is specified in the following bits:
BCK[2:0] bits in SCKDIVCR
CKSEL[2:0] bits in SCKSCR
PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2
HOCOFRQ1[2:0] bits in OFS1.
A frequency higher than the system clock ICLK, should not be set for the BCLK.
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9.7.5
9. Clock Generation Circuit
USB Clock (UCLK)
The USB clock, UCLK, is the operating clock for the USBFS module. A 48-MHz clock must be supplied to the USBFS
module. When the USBFS module is used, the setting must be 48 MHz for the UCLK clock.
The UCLK frequency is specified in the following bits:
CKSEL[2:0] bits in the SCKSCR
PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2
HOCOFRQ1[2:0] bits in OFS1.
9.7.6
CAN Clock (CANMCLK)
The CAN clock, CANMCLK, is the operating clock for the CAN module. CANMCLK is generated by the main clock
oscillator.
9.7.7
CAC Clock (CACCLK)
The CAC clock, CACCLK, is the operating clock for the CAC.
CACCLK is generated by the following:
Main clock oscillator
Sub-clock oscillator
High-speed clock oscillator
Middle-speed clock oscillator
Low-speed on-chip oscillator
IWDT-dedicated on-chip oscillator.
9.7.8
RTC-Dedicated Clock (RTCSCLK, RTCLCLK)
The RTC-dedicated clocks, RTCSCLK and RTCLCLK, are the operating clocks for the RTC.
RTCSCLK is generated by the sub-clock oscillator, and RTCLCLK is generated by the LOCO clock.
9.7.9
IWDT-Dedicated Clock (IWDTCLK)
The IWDT-dedicated clock, IWDTCLK, is the operating clock for the IWDT.
IWDTCLK is internally generated by the IWDT-dedicated on-chip oscillator.
9.7.10
AGT-Dedicated Clock (AGTSCLK, AGTLCLK)
The AGT-dedicated clocks, AGTSCLK and AGTLCLK, are the operating clocks for the AGT.
AGTSCLK is generated by the sub-clock oscillator, and AGTLCLK is generated by the LOCO clock.
9.7.11
SysTick Timer-Dedicated Clock (SYSTICCLK)
The SysTick timer-dedicated clock, SYSTICKCLK, is the operating clock for the SYSTICCLK.
SYSTICCLK is generated by the LOCO clock.
9.7.12
Segment LCDC Source Clock (LCDSRCCLK)
The Segment LCDC source clock, LCDSRCCLK, is the operating clock for the SLCDC.
The LCDSRCCLK is specified by the LCDSCKSEL[2:0] bits in SLCDSCKCR.
LCDSRCCLK is output when SLCDSCKCR.LCDSCKEN is set to 1. When changing the value of
SLCDSCKCR.LCDSCKSEL[2:0], make sure that the value of SLCDSCKCR.LCDSCKEN is 0.
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9.7.13
9. Clock Generation Circuit
Clock/Buzzer Output Clock (CLKOUT)
The CLKOUT is output externally from the CLKOUT pin, for the clock or buzzer output.
CLKOUT is output to the CLKOUT pin when CKOCR.CKOEN is set to 1. Only change the value of CKODIV[2:0] or
CKOSEL[2:0] bits in CKOCR when CKOCR.CKOEN is 0.
The CLKOUT clock frequency is specified in the following bits:
CKODIV[2:0] or CKOSEL[2:0] in CKOCR
PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2
HOCOFRQ1[2:0] bits in OFS1.
9.7.14
JTAG Clock (JTAGTCK)
The JTAG-dedicated clock, JTAGTCK, is the operating clock for the JTAG.
JTAGTCK is generated by the external clock for JTAG (TCK).
9.8
9.8.1
Usage Notes
Notes on Clock Generation Circuit
The frequencies of the system clock (ICLK), peripheral module clock (PCLKA to PCLKD), flash interface clock
(FCLK), and the external bus clock (BCLK) supplied to each module change according to the settings of SCKDIVCR.
Each frequency must meet the following conditions:
Select each frequency that is within the operation-guaranteed range of the clock cycle time (tcyc) specified in the AC
electrical characteristics. See section 51, Electrical Characteristics.
The frequencies must not exceed the ranges listed in Table 9.2
The peripheral modules operate on PCLKB and PCLKA. The operating speed of modules such as the timer and SCI
varies before and after the frequency is changed.
The system clock (ICLK), peripheral module clock (PCLKA to PCLKD), flash interface clock (FCLK), and
external bus clock (BCLK) must be set according to Table 9.2.
Do not change the clock frequency during external bus access. In addition, when external bus access starts after a change
to the clock frequency, confirm that the frequency changes are complete before accessing the bus.
To ensure correct processing after the clock frequency changes, first modify the relevant clock control register to change
the frequency, then read the value from the register, and finally perform the subsequent processing.
9.8.2
Notes on Resonator
Because various resonator characteristics relate closely to your board design, adequate evaluation is required before use.
See the resonator connection example in Figure 9.6. The circuit constants for the resonator depend on the resonator to be
used and the stray capacitance of the mounting circuit. Therefore, consult the resonator manufacturer when determining
the circuit constants. The voltage to be applied between the resonator pins must be within the absolute maximum rating.
9.8.3
Notes on Board Design
When using a crystal resonator, place the resonator and its load capacitors as close to the XTAL and EXTAL pins as
possible. Other signal lines should be routed away from the oscillation circuit, as shown in Figure 9.8, to prevent
electromagnetic induction from interfering with correct oscillation.
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9. Clock Generation Circuit
Prohibited
Signal A
Signal B
Prohibited
MCU
CL2
XTAL
EXTAL
CL1
Figure 9.8
9.8.4
Signal routing in board design for oscillation circuit (applies to the sub-clock oscillator for the
main clock oscillator)
Notes on Resonator Connect Pin
When the main clock is not used, the EXTAL and XTAL pins can be used as general ports, P212 and P213. When these
pins are used as general ports, the main clock must be stopped by setting MOSCCR.MOSTP to 1.
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10. Clock Frequency Accuracy Measurement Circuit (CAC)
10.
Clock Frequency Accuracy Measurement Circuit (CAC)
10.1
Overview
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement
target clock) within the time generated by the clock to be used as a measurement reference (measurement reference
clock). It determines the accuracy depending on whether the number of pulses is within the allowable range.
When measurement is completed or the number of pulses within the time generated by the measurement reference clock
is not within the allowable range, an interrupt request is generated.
Table 10.1 lists the CAC specifications, Figure 10.1 shows the block diagram, and Table 10.2 shows the I/O pins.
Table 10.1
CAC specifications
Item
Description
Measurement target clocks
Frequency can be measured for:
Main clock oscillator
Sub-clock oscillator
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B (PCLKB).
Measurement reference clocks
Frequency can be referenced to:
External clock input to the CACREF pin
Main clock oscillator
Sub-clock oscillator
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B (PCLKB).
Selectable function
Digital filter
Interrupt sources
Measurement end
Frequency error
Overflow.
Module-stop function
Module-stop state can be set to reduce power consumption
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10. Clock Frequency Accuracy Measurement Circuit (CAC)
DFS[1:0]
CACREFE
CACREF pin
DFS[1:0]
Digital filter
RSCS[2:0]
RCDS[1:0]
EDGES[1:0]
Frequency
dividing circuit
1/32
Reference
signal
generation
clock select
circuit
FMCS[2:0]
Main clock
Sub-clock
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B
(PCLKB)
1/128
Edge detection
circuit
RPS
1/1024
1/8192
Valid edge signal
TCSS[1:0]
Frequency
measurement
clock
Frequency
dividing circuit
Frequency
measurement
clock select
circuit
1/4
1/8
CFME
Count source
clock
16-bit counter
Overflow interrupt request
1/32
CACNTBR
CAC block diagram
Table 10.2
CAC pin configuration
CAULVR
CALLVR
CAICR
CASTR
Internal peripheral bus
Pin name
I/O
Function
CACREF
Input
Measurement reference clock input pin
10.2
Measurement end interrupt
request
Frequency error interrupt
request
Comparator
CFME: Bit in CACR0
CACREFE, FMCS[2:0], TCSS[1:0], EDGES[1:0]: Bits in CACR1
RPS, RSCS[2:0], RCDS[1:0], DFS[1:0]: Bits in CACR2
CAICR: CAC Interrupt Control Register
CASTR: CAC Status Register
CAULVR: CAC Upper-Limit Value Setting Register
CALLVR: CAC Lower-Limit Value Setting Register
CACNTBR: CAC Counter Buffer Register
Figure 10.1
Interrupt control
circuit
Register Descriptions
10.2.1
CAC Control Register 0 (CACR0)
Address(es): CAC.CACR0 4004 4600h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
CFME
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CFME
Clock Frequency Measurement Enable
0: Disable
1: Enable.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CFME bit (Clock Frequency Measurement Enable)
The CFME bit enables or disables the clock frequency measurement. Read the CFME bit to confirm that the bit value has
changed. Additional write accesses are ignored before the change is complete.
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10.2.2
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Control Register 1 (CACR1)
Address(es): CAC.CACR1 4004 4601h
b7
b6
EDGES[1:0]
Value after reset:
0
0
b5
b4
b3
TCSS[1:0]
0
0
b2
b1
b0
CACRE
FE
FMCS[2:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CACREFE
CACREF Pin Input Enable
0: Disable
1: Enable.
R/W
b3 to b1
FMCS[2:0]
Measurement Target Clock Select
b3
R/W
b5, b4
TCSS[1:0]
Measurement Target Clock
Frequency Division Ratio Select
b5 b4
R/W
b7, b6
EDGES[1:0]
Valid Edge Select
b7 b6
R/W
Note:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b1
0: Main clock oscillator
1: Sub-clock oscillator
0: HOCO clock
1: MOCO clock
0: LOCO clock
1: Peripheral module clock (PCLKB)
0: IWDTCLK clock
1: Setting prohibited.
0: No division
1: ×1/4 clock
0: ×1/8 clock
1: ×1/32 clock.
0: Rising edge
1: Falling edge
0: Both rising and falling edges
1: Setting prohibited.
Set the CACR1 register when the CACR0.CFME bit is 0.
CACREFE bit (CACREF Pin Input Enable)
The CACREFE bit enables or disables the CACREF pin input.
FMCS[2:0] bits (Measurement Target Clock Select)
The FMCS[2:0] bits select the measurement target clock whose frequency is to be measured.
TCSS[1:0] bits (Measurement Target Clock Frequency Division Ratio Select)
The TCSS[1:0] bits select the division ratio of the measurement target clock.
EDGES[1:0] bits (Valid Edge Select)
The EDGES[1:0] bits select the valid edge for the reference signal.
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10.2.3
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Control Register 2 (CACR2)
Address(es): CAC.CACR2 4004 4602h
b7
Value after reset:
b6
b5
b4
DFS[1:0]
RCDS[1:0]
0
0
0
0
b3
b2
b1
b0
RSCS[2:0]
0
0
RPS
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPS
Reference Signal Select
0: CACREF pin input
1: Internal clock (internally generated signal).
R/W
b3 to b1
RSCS[2:0]
Measurement Reference Clock
Select
b3
R/W
b5, b4
RCDS[1:0]
Measurement Reference Clock
Frequency Division Ratio Select
b5 b4
R/W
b7, b6
DFS[1:0]
Digital Filter Select
b7 b6
R/W
Note:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b1
0: Main clock oscillator
1: Sub-clock oscillator
0: HOCO clock
1: MOCO clock
0: LOCO clock
1: Peripheral module clock (PCLKB)
0: IWDTCLK clock
1: Setting prohibited.
0: ×1/32 clock
1: ×1/128 clock
0: ×1/1024 clock
1: ×1/8192 clock.
0 0: Disable digital filtering
0 1: Use sampling clock for the digital filter as the frequency
measuring clock
1 0: Use sampling clock for the digital filter as the frequency
measuring clock divided by 4
1 1: Use sampling clock for the digital filter as the frequency
measuring clock divided by 16.
Set the CACR2 register when the CACR0.CFME bit is 0.
RPS bit (Reference Signal Select)
The RPS bit selects whether to use the CACREF pin input or an internal clock (internally generated signal) as the
reference signal.
RSCS[2:0] bits (Measurement Reference Clock Select)
The RSCS[2:0] bits select the reference clock for measurement.
RCDS[1:0] bits (Measurement Reference Clock Frequency Division Ratio Select)
The RCDS[1:0] bits select the division ratio of the reference clock when an internal reference clock is selected (RPS =
1). When RPS = 0 (CACREF pin is used as the reference clock source), the reference clock is not divided.
DFS[1:0] bits (Digital Filter Select)
The DFS[1:0] bits enable or disable the digital filter and select its sampling clock.
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10.2.4
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Interrupt Control Register (CAICR)
Address(es): CAC.CAICR 4004 4603h
b7
—
Value after reset:
b6
b5
b4
OVFFC MENDF FERRF
L
CL
CL
0
0
0
0
b3
—
0
b2
b1
b0
OVFIE MENDI FERRI
E
E
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FERRIE
Frequency Error Interrupt Request
Enable
0: Disable frequency error interrupt request
1: Enable frequency error interrupt request.
R/W
b1
MENDIE
Measurement End Interrupt
Request Enable
0: Disable measurement end interrupt request
1: Enable measurement end interrupt request.
R/W
b2
OVFIE
Overflow Interrupt Request Enable 0: Disable overflow interrupt request
1: Enable overflow interrupt request.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
FERRFCL
FERRF Clear
When 1 is written to this bit, the FERRF flag is cleared. This
bit is read as 0.
R/W
b5
MENDFCL
MENDF Clear
When 1 is written to this bit, the MENDF flag is cleared. This
bit is read as 0.
R/W
b6
OVFFCL
OVFF Clear
When 1 is written to this bit, the OVFF flag is cleared. This bit
is read as 0.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
FERRIE bit (Frequency Error Interrupt Request Enable)
The FERRIE bit enables or disables the frequency error interrupt request.
MENDIE bit (Measurement End Interrupt Request Enable)
The MENDIE bit enables or disables the measurement end interrupt request.
OVFIE bit (Overflow Interrupt Request Enable)
The OVFIE bit enables or disables the overflow interrupt request.
FERRFCL bit (FERRF Clear)
Setting the FERRFCL bit to 1 clears the FERRF flag.
MENDFCL bit (MENDF Clear)
Setting the MENDFCL bit to 1 clears the MENDF flag.
OVFFCL bit (OVFF Clear)
Setting the OVFFCL bit to 1 clears the OVFF flag.
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10.2.5
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Status Register (CASTR)
Address(es): CAC.CASTR 4004 4604h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
OVFF MENDF FERRF
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FERRF
Frequency Error Flag
0: Clock frequency is within the allowable range
1: Clock frequency has deviated beyond the allowable range
(frequency error).
R
b1
MENDF
Measurement End Flag
0: Measurement is in progress
1: Measurement ended.
R
b2
OVFF
Overflow Flag
0: The counter has not overflowed
1: The counter overflowed.
R
b7 to b3
—
Reserved
These bits are read as 0
R
FERRF flag (Frequency Error Flag)
The FERRF flag indicates a deviation of the clock frequency from the set value (frequency error).
[Setting condition]
The clock frequency is outside the allowable range defined in the CAULVR and CALLVR registers.
[Clearing condition]
1 is written to the FERRFCL bit.
MENDF flag (Measurement End Flag)
The MENDF flag indicates the end of measurement.
[Setting condition]
Measurement ends.
[Clearing condition]
1 is written to the MENDFCL bit.
OVFF flag (Overflow Flag)
The OVFF flag indicates that the counter overflowed.
[Setting condition]
The counter overflows.
[Clearing condition]
1 is written to the OVFFCL bit.
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10.2.6
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Upper-Limit Value Setting Register (CAULVR)
Address(es): CAC.CAULVR 4004 4606h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CAULVR is a 16-bit read/write register that specifies the upper value of the allowable range. When the counter value
rises above the value specified in this register, a frequency error is detected. Write to this register when the
CACR0.CFME bit is 0.
The counter value stored in CACNTBR can vary depending on the difference between the phases of the digital filter and
edge-detection circuit, and the signal on the CACREF pin. Ensure that this setting allows an adequate margin.
10.2.7
CAC Lower-Limit Value Setting Register (CALLVR)
Address(es): CAC.CALLVR 4004 4608h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CALLVR is a 16-bit read/write register that specifies the lower value of the allowable range. When the counter value
falls below the value specified in this register, a frequency error is detected. Write to this register when the
CACR0.CFME bit is 0.
The counter value stored in CACNTBR can vary depending on the difference between the phases of the digital filter and
edge-detection circuit, and the signal on the CACREF pin. Ensure that this setting allows an adequate margin.
10.2.8
CAC Counter Buffer Register (CACNTBR)
Address(es): CAC.CACNTBR 4004 460Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CACNTBR is a 16-bit read-only register that stores the measurement result.
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10.3
10. Clock Frequency Accuracy Measurement Circuit (CAC)
Operation
10.3.1
Measuring Clock Frequency
The CAC measures the clock frequency using the CACREF pin input or the internal clock as a reference. Figure 10.2
shows an operating example of the CAC.
CACREF pin or
internal clock
1
0
CFME bit in CACR0
1
0
0 is written to
CFME bit
1 is written to
CFME bit
Counter value
FFFFh
Counter is
cleared by writing
0 to CFME bit
After 1 is written to CFME bit, counting
starts at the first valid edge
CAULVR
CALLVR
0000h
Time
CACNTBR
FERRF flag in CASTR
(frequency error flag)
1
0
MENDF flag in CASTR
(measurement end flag)
1
0
0000h
7FFFh
BFFFh
1 is written to MENDFCL
bit in CAICR
(1)
(2)
(3)
(4)
3FFFh
1 is written to FERRFCL
bit in CAICR
1 is written to FERRFCL
bit in CAICR
1 is written to MENDFCL
bit in CAICR
1 is written to MENDFCL
bit in CAICR
(5)
(6)
When the CACREF pin input is used as a reference:
In CACR1: CACREFE bit = 1, EDGES[1:0] bits = 00b
CAULVR register = AAAAh, CALLVR register = 5555h
When the internal clock is used as a reference:
In CACR1: CACREFE bit = 0, EDGES[1:0] bits = 00b
CAULVR register = AAAAh, CALLVR register = 5555h
Figure 10.2
CAC operating example
1. Before writing 1 to CACR0.CFME, set CACR1 and CACR2 to define the measurement target clock and
measurement reference clock. Writing 1 to the CACR0.CFME bit enables clock frequency measurement.
2. The timer starts counting up if the valid edge selected in the CACR1.EDGES[1:0] bits is input from the
measurement reference clock. The valid edge is a rising edge (CACR1.EDGES[1:0] = 00b) as shown in Figure 10.2.
3. When the next valid edge is input, the counter value is transferred to CACNTBR and compared with the values in
CAULVR and CALLVR. If both CACNTBR ≤ CAULVR and CACNTBR ≥ CALLVR are true, only the MENDF
flag in CASTR is set to 1 because the clock frequency is correct. If the MENDIE bit in CAICR is 1, a measurement
end interrupt is generated.
4. When the next valid edge is input, the counter value is transferred to CACNTBR and compared with the values in
CAULVR and CALLVR. If CACNTBR > CAULVR, the FERRF flag in CASTR is set to 1, because the clock
frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. The MENDF flag
in CASTR is set to 1 at the end of measurement. If the MENDIE bit in CAICR is 1, a measurement end interrupt is
generated.
5. When the next valid edge is input, the counter value is transferred to CACNTBR and compared with the values in
CAULVR and CALLVR. If CACNTBR < CALLVR, the FERRF flag in CASTR is set to 1 because the clock
frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. The MENDF flag
in CASTR is set to 1 at the end of measurement. If the MENDIE bit in CAICR is 1, a measurement end interrupt is
generated.
6. When the CFME bit in CACR0 is 1, the counter value is transferred to CACNTBR and compared with the values in
CAULVR and CALLVR every time a valid edge is input. When the CFME bit is set to 0 in CACR0, the counter is
cleared and stops counting up.
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10.3.2
10. Clock Frequency Accuracy Measurement Circuit (CAC)
Digital Filtering of Signals on CACREF Pin
The CACREF pin has a digital filter, and levels on CACREF pin are transmitted to the internal circuitry after three
consecutive matches in the selected sampling interval. The same level continues to be transmitted internally until the
level on the pin has three consecutive matches again. Enabling or disabling of the digital filter and its sampling clock are
selectable.
The counter value transferred in CACNTBR might be in error by up to 1 cycle of the sampling clock because of the
difference between the phases of the digital filter and the signal input to the CACREF pin. When a frequency dividing
clock is selected as a count source clock, the counter value error is obtained using the following formula:
Counter value error = (1 cycle of the count source clock) / (1 cycle of the sampling clock)
10.4
Interrupt Requests
The CAC generates three types of interrupt requests:
Frequency error interrupt
Measurement end interrupt
Overflow interrupt.
When an interrupt source is generated, the associated status flag becomes 1. Table 10.3 provides information on the CAC
interrupt requests.
Table 10.3
CAC interrupt requests
Interrupt request
Interrupt enable bit
Status flag
Interrupt source
Frequency error
interrupt
CAICR.FERRIE
CASTR.FERRF
The result of comparing CACNTBR with CAULVR and CALLVR is
either CACNTBR > CAULVR or CACNTBR < CALLVR
Measurement end
interrupt
CAICR.MENDIE
CASTR.MENDF
Valid edge is input from the CACREF pin or internal clock
Measurement end interrupt does not occur at the first valid edge
after writing 1 to the CACR0.CFME bit.
Overflow interrupt
CAICR.OVFIE
CASTR.OVFF
The counter overflows
10.5
10.5.1
Usage Note
Module-Stop Function Setting
The CAC operation can be disabled or enabled with the Module Stop Control Register C (MSTPCRC). The CAC module
is initially stopped after reset. Releasing the module-stop state enables access to the registers. See section 11, Low Power
Modes for details.
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11. Low Power Modes
11.
Low Power Modes
11.1
Overview
The MCU provides several functions for reducing power consumption, such as setting clock dividers, controlling
EBCLK output, stopping modules, selecting power control mode in normal mode, and transitioning to low power modes.
Table 11.1 lists the specifications of the low power mode functions. Table 11.2 lists the conditions to transition to low
power modes, the states of the CPU and peripheral modules, and the method for canceling each mode. After a reset, the
MCU enters the program execution state, but only the DMAC, DTC, and SRAM operate.
Table 11.1
Specifications of low power mode functions
Parameter
Specification
Reducing power consumption by
switching clock signals
The frequency division ratio can be selected independently for the system clock (ICLK), peripheral
module clock (PCLKA, PCLKB, PCLKC, PCLKD), external bus clock (BCLK), and flash interface
clock (FCLK)*1
EBCLK output control
Selectable to BCLK output or high-level output
Module-stop
Peripheral module functions can be stopped independently
Low power modes
Sleep mode
Software Standby mode
Snooze mode.
Power control modes
Power consumption can be reduced in Normal, Sleep, and Snooze modes by selecting an
appropriate operating power control mode according to the operating frequency and voltage.
Five operating power control modes are available:
High-speed mode
Middle-speed mode
Low-speed mode
Low-voltage mode
Subosc-speed mode.
Note 1.
For details, see section 9, Clock Generation Circuit.
Table 11.2
Operating conditions of each low power mode (1 of 2)
Parameter
Sleep mode
Software Standby mode
Snooze mode*1
Transition condition
WFI instruction while
SBYCR.SSBY = 0
WFI instruction while
SBYCR.SSBY = 1
Snooze request in Software
Standby mode.
SNZCR.SNZE = 1.
Canceling method
All interrupts.
Any reset available in the
mode.
Interrupts shown in Table
11.3. Any reset available in
the mode.
Interrupts shown in Table
11.3. Any reset available in
the mode.
State after cancellation by an interrupt
Program execution state
(interrupt processing)
Program execution state
(interrupt processing)
Program execution state
(interrupt processing)
State after cancellation by a reset
Reset state
Reset state
Reset state
Main clock oscillator
Selectable
Stop
Selectable*2
Sub-clock oscillator
Selectable
Selectable
Selectable
High-speed on-chip oscillator
Selectable
Stop
Selectable
Middle-speed on-chip oscillator
Selectable
Stop
Selectable
Low-speed on-chip oscillator
Selectable
Selectable
Selectable
IWDT-dedicated on-chip oscillator
Selectable*4
Selectable*4
Selectable*4
PLL
Selectable
Stop
Selectable*2
Oscillation stop detection function
Selectable
Operation prohibited
Operation prohibited
Clock/buzzer output function
Selectable
Selectable*3
Selectable
External bus (EBCLK)
Selectable
Stop (Retained)
Operation prohibited
CPU
Stop (Retained)
Stop (Retained)
Stop (Retained)
SRAM (ECC SRAM included)
Selectable
Stop (Retained)
Selectable
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Table 11.2
11. Low Power Modes
Operating conditions of each low power mode (2 of 2)
Parameter
Sleep mode
Software Standby mode
Snooze mode*1
Flash memory
Operating
Stop (Retained)
Stop (Retained)
DMA Controller (DMAC)
Selectable
Stop (Retained)
Operation prohibited
Data Transfer Controller (DTC)
Selectable
Stop (Retained)
Selectable
(Retained)*5
Operation prohibited*5
USB 2.0 Full-Speed Module (USBFS)
Selectable
Stop
Watchdog Timer (WDT)
Selectable*4
Stop (Retained)
Stop (Retained)
Independent Watchdog Timer (IWDT)
Selectable*4
Selectable*4
Selectable*4
Realtime Clock (RTC)
Selectable
Selectable
Selectable
Asynchronous General Purpose Timer
(AGTn, n = 0, 1)
Selectable
Selectable*6
Selectable*6
14-bit A/D Converter (ADC14)
Selectable
Stop (Retained)
Selectable*12
12-bit D/A Converter (DAC12)
Selectable
Stop (Retained)
Selectable
Capacitive Touch Sensing Unit (CTSU) Selectable
Stop (Retained)
Selectable
Segment LCD Controller (SLCDC)
Selectable
Selectable*7
Selectable
Data Operation Circuit (DOC)
Selectable
Stop (Retained)
Selectable
Serial Communications Interface
(SCI0)
Selectable
Stop (Retained)
Selectable*10
Serial Communications Interface
(SCIn, n = 1 to 4, 9)
Selectable
Stop (Retained)
Operation prohibited
I2C Bus Interface (IIC0)
Selectable
Selectable
Selectable
I2C
Selectable
Stop (Retained)
Operation prohibited
Event Link Controller (ELC)
Selectable
Stop (Retained)
Selectable*8
Low-Power Analog Comparator
(ACMPLP0)
Selectable
Selectable*9
Selectable*9
Low-Power Analog Comparator
(ACMPLP1)
Selectable
Selectable*9
Selectable*9
Operational Amplifier (OPAMP)
Selectable
Selectable
Selectable
NMI, IRQn (n = 0 to 15) pin interrupt
Selectable
Selectable
Selectable
Key Interrupt Function (KINT)
Selectable
Selectable
Selectable
Low Voltage Detection (LVD)
Selectable
Selectable
Selectable
Power-on reset circuit
Operating
Operating
Operating
Other peripheral modules
Selectable
Stop (Retained)
Operation prohibited
I/O ports
Operating
Retained*11
Operating
Bus Interface (IICn, n = 1, 2)
Note:
Selectable means that operating or not operating can be selected in the control registers.
Stop (Retained) means that the contents of the internal registers are retained but the operations are suspended.
Operation prohibited means that the function must be stopped before entering Software Standby mode.
Note 1. All modules whose module-stop bits are 0 start as soon as PCLKs are supplied after entering Snooze mode. To avoid an
increase in power consumption in Snooze mode, set the module-stop bit of modules that are not required in Snooze mode to 1
before entering Software Standby mode.
Note 2. When using SCI0 in Snooze mode, MOSCCR.MOSTP and PLLCR.PLLSTP bits must be 1.
Note 3. Stopped when the Clock Output Source Select bits (CKOCR.CKOSEL[2:0]) are set to a value other than 010b (LOCO) and
100b (SOSC).
Note 4. In IWDT-dedicated on-chip oscillator and IWDT, operating or stopping is selected by setting the IWDT Stop Control bit
(IWDTSTPCTL) in Option Function Select Register 0 (OFS0) in IWDT auto-start mode. In WDT, operating or stopping is
selected by setting the WDT Stop Control bit (WDTSTPCTL) in the Option Function Select Register 0 in WDT auto-start mode.
Note 5. Detection of USBFS resumption is possible.
Note 6. AGT0 operation is possible when 100b (LOCO) or 110b (SOSC) is selected in the AGT0.AGTMR1.TCK[2:0] bits. AGT1
operation is possible when 100b (LOCO), 110b (SOSC), or 101 (underflow event signal from AGT0) is selected in the
AGT1.AGTMR1.TCK[2:0] bits.
Note 7. Operation is possible when 000b (LOCO) or 001b (SOSC) is selected in the SLCDSCKCR.LCDSCKSEL[2:0] bits. Stopping is
selected when the SLCDSCKCR.LCDSCKSEL[2:0] bits are set to a value other than 000b or 001b.
Note 8. Event lists the restrictions described in section 11.9.13, ELC Event in Snooze Mode.
Note 9. Only VCOUT function is permitted. The VCOUT pin operates when ACMPLP uses no digital filter. For details on digital filter,
see section 42, Low Power Analog Comparator (ACMPLP).
Note 10. Serial communication of SCI0 is only in asynchronous mode.
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11. Low Power Modes
Note 11. For the address bus and bus control signals (CS0 to CS3, RD, WR0 to WR1, WR, BC0 to BC1, and ALE), keeping the output
state or changing to the high-impedance state can be selected in the SBYCR.OPE bit.
Note 12. When using the ADC14 in Snooze mode, the ADCMPCR.CMPAE or ADCMPCR.CMPBE bit must be 1.
Table 11.3
Interrupt sources to transition to Normal mode from Snooze mode and Software Standby mode
Interrupt source
Name
NMI
Software Standby mode
Snooze mode
Yes
Yes
Yes
Yes
VBATT
VBATT_LVD
Port
PORT_IRQn (n = 0 to 15)
Yes
Yes
LVD
LVD_LVD1
Yes
Yes
LVD_LVD2
Yes
Yes
IWDT
IWDT_NMIUNDF
Yes
Yes
USBFS
USBFS_USBR
Yes
Yes
RTC
RTC_ALM
Yes
Yes
RTC_PRD
Yes
Yes
KINT
KEY_INTKR
Yes
Yes
AGT1
AGT1_AGTI
Yes
Yes*3
AGT1_AGTCMAI
Yes
Yes
AGT1_AGTCMBI
Yes
Yes
ACMPLP
ACMP_LP0
Yes
Yes
IIC0
IIC0_WUI
Yes
Yes
ADC140
ADC140_WCMPM
No
Yes with SELSR0*1, *3
ADC140_WCMPUM
No
Yes with SELSR0*1, *3
SCI0_AM
No
Yes with SELSR0*1, *2
SCI0_RXI_OR_ERI
No
Yes with SELSR0*1, *2
DTC
DTC_COMPLETE
No
Yes with SELSR0*1, *3
DOC
DOC_DOPCI
No
Yes with SELSR0*1
CTSU
CTSU_CTSUFN
No
Yes with SELSR0*1
SCI0
Note 1.
Note 2.
Note 3.
To use the interrupt request as a trigger for exiting Snooze mode, the request must be selected in SELSR0. See section 14,
Interrupt Controller Unit (ICU). When a trigger selected in SELSR0 occurs after executing a WFI instruction and during the
transition from Normal mode to Software Standby mode, whether the request can be accepted depends on the timing of the
occurrence.
Only one of either SCI0_AM or SCI0_RXI_OR_ERI can be selected.
The event that is enabled by SNZEDCR must not be used.
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11. Low Power Modes
SBYCR.SSBY = 0
Reset state
Sleep mode
WFI instruction*1
RES pin = High*2
SNZCR.SNZE = 1
All interrupts
Snooze mode
Interrupt shown in Table 11.3
Normal mode
(program execution state)*3
Snooze end condition
shown in Table 11.8
Snooze requests
shown in Table 11.6
*1
WFI instruction
SBYCR.SSBY = 1
Software Standby mode
Interrupt shown in Table 11.3
Low power mode (program stopped state)
Note 1.
Note 2.
Note 3.
When an interrupt that acts as a trigger for cancel is received during a transition to the program stopped state after the execution of a WFI
instruction, the MCU executes interrupt exception handling instead of a transition to low power mode.
The MOCO clock is the source of the operating clock following a transition from the reset state to Normal mode.
The transition to Normal mode is made from an interrupt in Sleep mode, Software Standby mode, or Snooze mode. The clock source is
the same as before entering the low power mode.
Figure 11.1
11.2
Mode transitions
Register Descriptions
11.2.1
Standby Control Register (SBYCR)
Address(es): SYSTEM.SBYCR 4001 E00Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
SSBY
OPE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
OPE
Output Port Enable
0: In Software Standby mode, the address bus and bus control signals
are set to the high-impedance state. In Snooze mode, the address
bus and bus control signals are the same as before entering
Software Standby mode.
1: In Software Standby mode, the address bus and bus control signals
keep the output state.
R/W
b15
SSBY
Software Standby
0: Sleep mode
1: Software Standby mode.
R/W
OPE bit (Output Port Enable)
The OPE bit specifies whether to set to the high-impedance state or to retain the output of the address bus and bus control
signals (CS0 to CS3, RD, WR0, WR1, WR, BC0, BC1, and ALE) in Software Standby or Snooze mode.
SSBY bit (Software Standby)
The SSBY bit specifies the transition destination after a WFI instruction is executed.
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When the SSBY bit is set to 1, the MCU enters Software Standby mode after execution of a WFI instruction. When the
MCU returns to Normal mode from Software Standby mode due to an interrupt, the SSBY bit remains 1. The SSBY bit
can be cleared by writing 0 to it.
When the OSTDCR.OSTDE bit is 1, the setting of SSBY bit is ignored. Even if the SSBY bit is 1, the MCU enters Sleep
mode on execution of a WFI instruction.
When the FENTRYR.FENTRY0 bit is 1 or the FENTRYR.FENTRYD bit is 1, the setting of SSBY bit is ignored. Even
if the SSBY bit is 1, the MCU enters Sleep mode on execution of a WFI instruction.
11.2.2
Module Stop Control Register A (MSTPCRA)
Address(es): SYSTEM.MSTPCRA 4001 E01Ch
Value after reset:
Value after reset:
Bit
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
MSTPA
22
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
MSTPA
6
—
—
—
—
1
1
1
1
1
1
1
1
1
0
1
1
1
1
Symbol
Bit name
Stop*1
MSTPA MSTPA
1
0
0
0
Description
R/W
Target module: SRAM0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
R/W
b0
MSTPA0
SRAM0 Module
b1
MSTPA1
SRAM1 Module Stop
Target module: SRAM1
0: Cancel the module-stop state
1: Enter the module-stop state.
b5 to b2
—
Reserved
These bits are read as 1. The write value should be 1. R/W
Stop*1
Target module: ECCSRAM
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b6
MSTPA6
ECCSRAM Module
b21 to b7
—
Reserved
These bits are read as 1. The write value should be 1. R/W
b22
MSTPA22
DMA Controller/Data
Transfer Controller Module
Stop*2
Target module: DMAC, DTC
0: Cancel the module-stop state
1: Enter the module-stop state.
b31 to b23
—
Reserved
These bits are read as 1. The write value should be 1. R/W
Note 1.
Note 2.
R/W
The MSTPA0 and MSTPA6 bit settings must be the same.
When rewriting the MSTPA22 bit from 0 to 1, disable the DMAC and DTC before setting the MSTPA22 bit.
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11. Low Power Modes
Module Stop Control Register B (MSTPCRB)
Address(es): MSTP.MSTPCRB 4004 7000h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
—
—
—
—
MSTPB
22
—
—
1
1
1
1
1
1
1
1
1
b10
b9
b8
b7
b6
b5
b4
MSTPB MSTPB MSTPB MSTPB MSTPB
31
30
29
28
27
Value after reset:
Value after reset:
1
1
1
1
b15
b14
b13
b12
b11
—
1
—
—
—
—
MSTPB
11
1
1
1
1
1
MSTPB MSTPB MSTPB MSTPB
9
8
7
6
1
1
1
1
b19
b18
b17
b16
—
—
1
1
1
b3
b2
b1
b0
—
—
1
1
MSTPB MSTPB
19
18
—
—
—
MSTPB
2
1
1
1
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b2
MSTPB2
Controller Area Network
Module Stop*1
Target module: CAN0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b5 to b3
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b6
MSTPB6
Quad Serial Peripheral
Interface Module Stop
Target Module: QSPI
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b7
MSTPB7
I2C Bus Interface 2 Module
Stop
Target module: IIC2
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b8
MSTPB8
I2C Bus Interface 1 Module
Stop
Target module: IIC1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b9
MSTPB9
I2C Bus Interface 0 Module
Stop
Target module: IIC0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b10
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b11
MSTPB11
Universal Serial Bus 2.0 Full- Target module: USBFS
0: Cancel the module-stop state
Speed Interface Module
1: Enter the module-stop state.
Stop*2
R/W
b17 to b12
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b18
MSTPB18
Serial Peripheral Interface 1
Module Stop
Target module: SPI1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b19
MSTPB19
Serial Peripheral Interface 0
Module Stop
Target module: SPI0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b21, b20
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b22
MSTPB22
Serial Communication
Interface 9 Module Stop
Target module: SCI9
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b26 to b23
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b27
MSTPB27
Serial Communication
Interface 4 Module Stop
Target module: SCI4
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b28
MSTPB28
Serial Communication
Interface 3 Module Stop
Target module: SCI3
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
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Bit
Symbol
Bit name
Description
R/W
b29
MSTPB29
Serial Communication
Interface 2 Module Stop
Target module: SCI2
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b30
MSTPB30
Serial Communication
Interface 1 Module Stop
Target module: SCI1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b31
MSTPB31
Serial Communication
Interface 0 Module Stop
Target module: SCI0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
Note 1.
Note 2.
The MSTPB2 bit must be written while the oscillation of the clock controlled by this bit is stable. To enter Software Standby
mode after writing to this bit, wait for 2 CAN clock (CANMCLK) cycles after writing, then execute a WFI instruction.
To enter Software Standby mode after writing to the MSTPB11 bit, wait for 2 USB clock (UCLK) cycles after writing, then
execute a WFI instruction.
11.2.4
Module Stop Control Register C (MSTPCRC)
Address(es): MSTP.MSTPCRC 4004 7004h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MSTPC
31
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
MSTPC
8
—
—
—
1
1
1
1
1
1
1
—
Value after reset:
MSTPC MSTPC MSTPC
14
13
12
1
1
1
1
MSTPC MSTPC
4
3
1
1
—
1
MSTPC MSTPC
1
0
1
1
Bit
Symbol
Bit name
Description
R/W
b0
MSTPC0
Clock Frequency Accuracy
Measurement Circuit Module Stop*1
Target module: CAC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b1
MSTPC1
Cyclic Redundancy Check Calculator
Module Stop
Target module: CRC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b2
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b3
MSTPC3
Capacitive Touch Sensing Unit
Module Stop
Target module: CTSU
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b4
MSTPC4
Segment LCD Controller Module Stop Target module: SLCDC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b7 to b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b8
MSTPC8
Serial Sound Interface Enhanced
Module Stop
Target module: SSIE0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b11 to b9
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b12
MSTPC12
Secure Digital Host Interface/Multi
Media Card Interface Module Stop
Target module: SDHI/MMC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b13
MSTPC13
Data Operation Circuit Module Stop
Target module: DOC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b14
MSTPC14
Event Link Controller Module Stop
Target module: ELC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
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Bit
Symbol
Bit name
Description
R/W
b30 to b15
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b31
MSTPC31
SCE5 Module Stop*2
Target module: SCE5
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
Note 1.
Note 2.
The MSTPC0 bit must be written while the oscillation of the clock to be controlled by this bit is stable. To enter Software
Standby mode after writing to this bit, wait for 2 cycles of the slowest clock from the clocks output by the oscillators, then
execute a WFI instruction.
Set the MSTPC31 bit to 0 at the beginning of the program, to initialize an unused circuit, even if the SCE5 is not used in this
MCU. See section 11.9.15, Module-Stop Function for an Unused Circuit.
11.2.5
Module Stop Control Register D (MSTPCRD)
Address(es): MSTP.MSTPCRD 4004 7008h
b31
Value after reset:
Value after reset:
b30
b29
MSTPD
31
—
MSTPD
29
b28
b27
b26
b25
b24
b23
b22
b21
b20
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
MSTPD
14
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
MSTPD MSTPD
6
5
1
b19
b17
b16
—
—
MSTPD
16
1
1
1
1
b3
b2
b1
b0
—
—
1
1
MSTPD MSTPD
20
19
1
—
1
b18
MSTPD MSTPD
3
2
1
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b2
MSTPD2
Asynchronous General
Purpose Timer 1 Module
Stop*1
Target module: AGT1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b3
MSTPD3
Asynchronous General
Purpose Timer 0 Module
Stop*2
Target module: AGT0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b4
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b5
MSTPD5
General PWM Timer 323 to
320 Module Stop
Target module: GPT323 to GPT320
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b6
MSTPD6
General PWM Timer 169 to
164 Module Stop
Target module: GPT169 to GPT164
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b13 to b7
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b14
MSTPD14
Port Output Enable for GPT
Module Stop
Target module: POEG
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b15
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b16
MSTPD16
14-Bit A/D Converter Module
Stop
Target module: ADC140
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b18, b17
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b19
MSTPD19
8-Bit D/A Converter Module
Stop*3
Target module: DAC8
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b20
MSTPD20
12-Bit D/A Converter Module
Stop
Target module: DAC12
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b28 to b21
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
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Bit
Symbol
Bit name
Description
R/W
b29
MSTPD29
Low-Power Analog Comparator
Module Stop
Target module: ACMPLP
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b30
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b31
MSTPD31
Operational Amplifier Module
Stop
Target module: OPAMP
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
Note 1.
Note 2.
Note 3.
When the count source is sub-clock oscillator or LOCO, AGT1 counting does not stop even if MSTPD2 is set to 1. If the count
source is the sub-clock oscillator or LOCO, this bit must be set to 1 except when accessing the AGT1 registers.
When the count source is sub-clock oscillator or LOCO, AGT0 counting does not stop even if MSTPD3 is set to 1. If the count
source is the sub-clock oscillator or LOCO, this bit must be set to 1 except when accessing the AGT0 registers.
When using the 8-bit D/A converter (MSTPD19 = 0), set the MSTPD29 bit in ACMPLP to 0.
11.2.6
Operating Power Control Register (OPCCR)
Address(es): SYSTEM.OPCCR 4001 E0A0h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
OPCM
TSF
—
—
OPCM[1:0]
0
0
0
0
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
OPCM[1:0]
Operating Power Control
Mode Select
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
OPCMTSF
Operating Power Control
Mode Transition Status Flag
0: Transition complete
1: Transition in progress.
R
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
0
0
1
1
0: High-speed mode
1: Middle-speed mode
0: Low-voltage mode*1
1: Low-speed mode.
HOCOCR.HCSTP must always be 0.
The OPCCR register is used to reduce power consumption in Normal mode, Sleep mode, and Snooze mode. Power
consumption can be reduced according to the operating frequency and operating voltage used by the OPCCR setting. For
the procedure to change the operating power control modes, see section 11.5, Function for Lower Operating Power
Consumption.
OPCM[1:0] bits (Operating Power Control Mode Select)
The OPCM[1:0] bits select the operating power control mode in Normal mode, Sleep mode, and Snooze mode.
Table 11.4 shows the relationship between the operating power control modes, and the OPCM[1:0], SOPCM bit settings.
Writing to OPCCR.OPCM[1:0] is prohibited while HOCOCR.HCSTP and OSCSF.HOCOSF are 0 as the oscillation of
the HOCO clock is not stable yet.
OPCMTSF flag (Operating Power Control Mode Transition Status Flag)
The OPCMTSF flag indicates the switching control state when the operating power control mode is switched. This flag
sets to 1 when the OPCM[1:0] bits are written, and 0 when mode transition completes. Read this flag to confirm that it is
0 before proceeding.
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11. Low Power Modes
Sub Operating Power Control Register (SOPCCR)
Address(es): SYSTEM.SOPCCR 4001 E0AAh
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
SOPC
MTSF
—
—
—
SOPC
M
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
SOPCM
Sub Operating Power Control
Mode Select
0: Not Subosc-speed mode
1: Subosc-speed mode.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
SOPCMTSF
Sub Operating Power Control
Mode Transition Status Flag
0: Transition completed
1: Transition in progress.
R
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SOPCCR register is used to reduce power consumption in Normal mode, Sleep mode, and Snooze mode by
initiating the entry to and exit from Subosc-speed mode. Subosc-speed mode is available only when using the sub-clock
oscillator or LOCO without dividing the frequency.
The flash cache function should be disabled by setting the CACHEE.FCACHEEN bit to 0 before switching the operating
power control mode. For details, see section 47., Flash Memory.
For the procedure to change operating power control modes, see section 11.5, Function for Lower Operating Power
Consumption.
SOPCM bit (Sub Operating Power Control Mode Select)
The SOPCM bit selects the operating power control mode in Normal mode, Sleep mode, and Snooze mode. Setting this
bit to 1 allows transition to Subosc-speed mode. Setting this bit to 0 allows a return to the operating mode (set in
OPCCR.OPCM[1:0]) before the transition to Subosc-speed mode.
Table 11.4 shows the relationship between the operating power control modes, and the OPCM[1:0], SOPCM bit settings.
SOPCMTSF flag (Sub Operating Power Control Mode Transition Status Flag)
The SOPCMTSF flag indicates the switching control state when the operating power control mode is switched from or to
Subosc-speed mode. This flag sets to 1 when the SOPCM bit is written, and 0 when mode transition completes. Read this
flag to confirm that it is 0 before proceeding.
Table 11.4 shows the operating power control modes.
Table 11.4
Relationship between operating power control modes, and OPCM[1:0], SOPCM bits
Operating power control mode
OPCM[1:0] bits
SOPCM bit
Power consumption
High
High-speed mode
00b
0
Middle-speed mode
01b
0
Low-voltage mode
10b
0
Low-speed mode
11b
0
Subosc-speed mode
xxb
1
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11.2.8
11. Low Power Modes
Snooze Control Register (SNZCR)
Address(es): SYSTEM.SNZCR 4001 E092h
b7
b6
b5
b4
b3
b2
SNZE
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b1
b0
SNZDT RXDRE
CEN
QEN
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RXDREQEN
RXD0 Snooze Request Enable
0: Ignore RXD0 falling edge in Software Standby mode
1: Detect RXD0 falling edge in Software Standby mode.
R/W
b1
SNZDTCEN
DTC Enable in Snooze Mode
0: Disable DTC operation in Snooze mode
1: Enable DTC operation in Snooze mode.
R/W
b6 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
SNZE
Snooze Mode Enable
0: Disable Snooze mode
1: Enable Snooze mode.
R/W
RXDREQEN bit (RXD0 Snooze Request Enable)
The RXDREQEN bit specifies whether to detect a falling edge of the RXD0 pin in Software Standby mode. This bit is
only available when SCI0 operates in asynchronous mode. To detect a falling edge of the RXD0 pin, set this bit before
entering Software Standby mode. When this bit is set to 1, a falling edge of the RXD0 pin in Software Standby mode
causes the MCU to enter Snooze mode.
SNZDTCEN bit (DTC Enable in Snooze Mode)
The SNZDTCEN bit specifies whether to use the DTC and SRAM in Snooze mode. To use the DTC and SRAM in
Snooze mode, set this bit to 1 before entering Software Standby mode. When this bit is set to 1, the DTC can be activated
by setting IELSRn (ICU Event Link Setting Register n).
SNZE bit (Snooze Mode Enable)
The SNZE bit enables or disables a transition from Software Standby mode to Snooze mode. To use Snooze mode, set
this bit to 1 before entering Software Standby mode. When this bit is set to 1, a trigger as shown in Table 11.6 in Software
Standby mode causes the MCU to enter Snooze mode. After the MCU transitions from Software Standby mode or
Snooze mode to Normal mode, clear the SNZE bit once, then set it before re-entering Software Standby mode. For
details, see section 11.8, Snooze Mode.
11.2.9
Snooze End Control Register (SNZEDCR)
Address(es): SYSTEM.SNZEDCR 4001 E094h
Value after reset:
b7
b6
b5
SCI0U
MTED
—
—
0
0
0
b4
b3
b2
b1
b0
AD0UM AD0MA DTCNZ DTCZR AGTUN
TED
TED
RED
ED
FED
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
AGTUNFED
AGT1 Underflow Snooze End Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b1
DTCZRED
Last DTC Transmission Completion
Snooze End Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b2
DTCNZRED
Not Last DTC Transmission
Completion Snooze End Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
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11. Low Power Modes
Bit
Symbol
Bit name
Description
R/W
b3
AD0MATED
ADC140 Compare Match Snooze End
Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b4
AD0UMTED
ADC140 Compare Mismatch Snooze
End Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
SCI0UMTED
SCI0 Address Mismatch Snooze End
Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
To use a trigger shown in Table 11.8 as a condition to switch from Snooze mode to Software Standby mode, set the
associated bit in the SNZEDCR register to 1. The event that is used to return to Normal mode from Snooze mode listed
in Table 11.3 must not be enabled by SNZEDCR.
AGTUNFED bit (AGT1 Underflow Snooze End Enable)
The AGTUNFED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by an AGT1
underflow. For details on the condition of the trigger, see section 24, Asynchronous General Purpose Timer (AGT).
DTCZRED bit (Last DTC Transmission Completion Snooze End Enable)
The DTCZRED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by completion
of the last DTC transmission, that is, CRA or CRB registers in the DTC is 0. For details on the condition of the trigger,
see section 18, Data Transfer Controller (DTC).
DTCNZRED bit (Not Last DTC Transmission Completion Snooze End Enable)
The DTCNZRED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by
completion of each DTC transmission, that is, CRA or CRB registers in the DTC is not 0. For details on the condition of
the trigger, see section 18, Data Transfer Controller (DTC).
AD0MATED bit (ADC140 Compare Match Snooze End Enable)
The AD0MATED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by an
ADC140 event when a conversion result matches the expected data. For details on the condition of the trigger, see
section 38, 14-Bit A/D Converter (ADC14).
AD0UMTED bit (ADC140 Compare Mismatch Snooze End Enable)
The AD0UMTED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by an
ADC140 event when the conversion result does not match the expected data. For details on the condition of the trigger,
see section 38, 14-Bit A/D Converter (ADC14).
SCI0UMTED bit (SCI0 Address Mismatch Snooze End Enable)
The SCI0UMTED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by an SCI0
event when an address received in Software Standby mode does not match the expected data. For details on the condition
of the trigger, see section 29, Serial Communications Interface (SCI). Set this bit to 1 only when SCI0 operates in
asynchronous mode.
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11.2.10
11. Low Power Modes
Snooze Request Control Register (SNZREQCR)
Address(es): SYSTEM.SNZREQCR 4001 E098h
b31
—
Value after reset:
b30
b29
b28
SNZRE SNZRE SNZRE
QEN30 QEN29 QEN28
b27
b26
—
—
b25
b24
b23
SNZRE SNZRE SNZRE
QEN25 QEN24 QEN23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
SNZRE
QEN17
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE
QEN15 QEN14 QEN13 QEN12 QEN11 QEN10 QEN9 QEN8 QEN7 QEN6 QEN5 QEN4 QEN3 QEN2 QEN1 QEN0
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SNZREQEN0
Snooze Request Enable 0
Enable IRQ0 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b1
SNZREQEN1
Snooze Request Enable 1
Enable IRQ1 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b2
SNZREQEN2
Snooze Request Enable 2
Enable IRQ2 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b3
SNZREQEN3
Snooze Request Enable 3
Enable IRQ3 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b4
SNZREQEN4
Snooze Request Enable 4
Enable IRQ4 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b5
SNZREQEN5
Snooze Request Enable 5
Enable IRQ5 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b6
SNZREQEN6
Snooze Request Enable 6
Enable IRQ6 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b7
SNZREQEN7
Snooze Request Enable 7
Enable IRQ7 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b8
SNZREQEN8
Snooze Request Enable 8
Enable IRQ8 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b9
SNZREQEN9
Snooze Request Enable 9
Enable IRQ9 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b10
SNZREQEN10
Snooze Request Enable 10
Enable IRQ10 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b11
SNZREQEN11
Snooze Request Enable 11
Enable IRQ11 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b12
SNZREQEN12
Snooze Request Enable 12
Enable IRQ12 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b13
SNZREQEN13
Snooze Request Enable 13
Enable IRQ13 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
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11. Low Power Modes
Bit
Symbol
Bit name
Description
R/W
b14
SNZREQEN14
Snooze Request Enable 14
Enable IRQ14 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b15
SNZREQEN15
Snooze Request Enable 15
Enable IRQ15 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b16
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b17
SNZREQEN17
Snooze Request Enable 17
Enable Key Interrupt snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b22 to b18
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b23
SNZREQEN23
Snooze Request Enable 23
Enable ACMPLP0 snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b24
SNZREQEN24
Snooze Request Enable 24
Enable RTC alarm snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b25
SNZREQEN25
Snooze Request Enable 25
Enable RTC period snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b27, b26
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28
SNZREQEN28
Snooze Request Enable 28
Enable AGT1 underflow snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b29
SNZREQEN29
Snooze Request Enable 29
Enable AGT1 compare match A snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b30
SNZREQEN30
Snooze Request Enable 30
Enable AGT1 compare match B snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
The SNZREQCR register controls the trigger that causes the MCU to switch from Software Standby mode to Snooze
mode. If a trigger is selected as a request to cancel Software Standby mode by setting the WUPEN register, see section
14, Interrupt Controller Unit (ICU), the MCU enters Normal mode when the trigger is generated while the associated bit
of the SNZREQCR register is 1. WUPEN register settings always have a higher priority than the SNZREQCR register
settings. For details, see section 11.8, Snooze Mode and section 14, Interrupt Controller Unit (ICU).
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11.2.11
11. Low Power Modes
Flash Operation Control Register (FLSTOP)
Address(es): SYSTEM.FLSTOP 4001 E09Eh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
FLSTP
F
—
—
—
FLSTO
P
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FLSTOP
Selecting ON/OFF of the Flash
Memory Operation
0: Code flash and data flash memory operates
1: Code flash and data flash memory stops.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
FLSTPF
Flash Memory Operation Status Flag
0: Transition completed
1: During transition (from the flash-stop-status to flashoperating-status or flash-operating-status to flash-stopstatus).
R
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
FLSTOP bit (Selecting ON/OFF of the Flash Memory Operation)
The FLSTOP bit enables or disables flash memory. The FLSTOP bit must be written in a program executing in the
SRAM. To use an interrupt when the FLSTOP bit is 1, be sure to place the interrupt vector in the SRAM. Set this bit to 0
when low-voltage mode is not selected.
Note:
Note:
When changing the value of the FLSTOP bit from 1 to 0 to start flash memory operation, ensure that the FLSTPF
flag is 0 and OSCSF.HOCOSF is 1 before restarting access to the flash memory. After that, instructions can be
executed in the code flash memory.
Writing to FLSTOP.FLSTOP is prohibited while HOCOCR.HCSTP and OSCSF.HOCOSF are 0 (HOCO is in
stabilization wait counting).
FLSTPF flag (Flash Memory Operation Status Flag)
The FLSTPF flag indicates the status of the transition from the flash-stop-status to flash-operating-status or from the
flash-operating-status to the flash-stop-status. When the transition completes, the flag is read as 0. When using flash
memory again after stopping it once, make sure that the FLSTPF flag is 0 before proceeding.
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11.2.12
11. Low Power Modes
Power Save Memory Control Register (PSMCR)
Address(es): SYSTEM.PSMCR 4001 E09Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
PSMC[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PSMC[1:0]
Power Save Memory Control
b1
R/W
0
0
1
1
b7 to b2
—
Reserved
b0
0: All SRAM are on in Software Standby mode
1: 48-KB SRAM (2000 0000h to 2000 BFFFh) is on in Software
Standby mode
0: Setting prohibited
1: Setting prohibited.
These bits are read as 0. The write value should be 0.
R/W
PSMC[1:0] bits (Power Save Memory Control)
The SRAM retention area in Software Standby mode is selected with the PSMC[1:0] bits. Supply current can be reduced
by setting these bits to 01b (48-KB SRAM in Software Standby mode). A WFI instruction must be executed after setting
the PSMC register.
11.2.13
System Control OCD Control Register (SYOCDCR)
Address(es): SYSTEM.SYOCDCR 4001 E40Eh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
DBGEN
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
DBGEN
Debugger Enable
0: On-chip debugger is disabled
1: On-chip debugger is enabled.
Set to 1 first in on-chip debug mode.
R/W
DBGEN bit (Debugger Enable)
The DBGEN bit enables the on-chip debug mode. This bit must be set to 1 first in the on-chip debugger mode.
[Setting condition]
Writing 1 to the bit when the debugger is connected.
[Clearing condition]
Power-on reset is generated
Writing 0 to the bit.
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11.3
11. Low Power Modes
Reducing Power Consumption by Switching Clock Signals
The clock frequency changes when the following bits are set:
SCKDIVCR.FCK[2:0]
ICK[2:0], BCK[2:0]
PCKA[2:0]
PCKB[2:0]
PCKC[2:0]
PCKD[2:0]
The CPU, DMAC, DTC, flash, and SRAM use the operating clock specified by the ICK[2:0] bits.
Peripheral modules use the operating clock specified in the PCKA[2:0], PCKB[2:0], PCKC[2:0], and PCKD[2:0] bits.
The flash memory interface uses the operating clock specified in the FCK[2:0] bits. The external bus uses the operating
clock specified in the BCK[2:0] bits.
For details, see section 9, Clock Generation Circuit.
11.4
Module-Stop Function
The module-stop function can be set for each on-chip peripheral module.
When the MSTPmi bit (m = A to D; i = 31 to 0) in MSTPCRA to MSTPCRD is set to 1, the specified module stops
operating and enters the module-stop state, but the CPU continues to operate independently. Clearing the MSTPmi bit to
0 cancels the module-stop state, allowing the module to resume operation at the end of the bus cycle. The internal states
of the modules are retained in the module-stop state.
After a reset is canceled, all modules other than the DMAC, DTC, and SRAMs are placed in the module-stop state. Do
not access the module while the corresponding MSTPmi bit is 1, otherwise the read/write data or the operation of the
module is not guaranteed. Also, do not set the MSTPmi bit to 1 while the corresponding module is accessed.
11.5
Function for Lower Operating Power Consumption
By selecting an appropriate operating power consumption control mode according to the operating frequency and
operating voltage, power consumption can be reduced in Normal mode, Sleep mode, and Snooze mode.
11.5.1
Setting Operating Power Control Mode
Make sure that the operating condition such as the voltage range and the frequency range is always within the specified
range before and after switching the operating power control modes. This section provides example procedures for
switching operating power control modes.
Table 11.5 shows the oscillators that can be used in each mode.
Table 11.5
Available oscillators in each mode
Oscillator
High-speed
on-chip
oscillator
Middle-speed
on-chip
oscillator
Low-speed
on-chip
oscillator
Main clock
oscillator
Sub-clock
oscillator
IWDTdedicated
on-chip
oscillator
Mode
PLL*1
High-speed
Available
Available
Available
Available
Available
Available
Available
Middle-speed
Available
Available
Available
Available
Available
Available
Available
Low-voltage
N/A
Available
Available
Available
Available
Available
Available
Low-speed
N/A
Available
Available
Available
Available
Available
Available
Subosc-speed
N/A
N/A
N/A
Available
N/A
Available
Available
Note 1.
The VCC range for the PLL is 2.4 to 5.5 V.
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(1)
11. Low Power Modes
Switching from a higher power mode to a lower power mode
Example 1: From High-speed mode to Low-speed mode
Operation starts in High-speed mode.
1. Disable the flash cache by resetting FCACHEE.FCACHEEN when the flash cache is cacheable in High-speed
mode.
2. Change the oscillator to what is used in Low-speed mode. Set the frequency of each clock lower than the
maximum operating frequency in Low-speed mode.
3. Turn off the oscillator that is not required in Low-speed mode.
4. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed).
5. Set the OPCCR.OPCM bit to 11b (Low-speed mode).
6. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed).
7. Perform the following steps when the flash cache is cacheable in Low-speed mode:
a. Invalidate the flash cache by setting FCACHEIV.FCACHEIV.
b. Check that FCACHEIV.FCACHEIV is 0.
c. Enable the flash cache by setting FCACHEE.FCACHEEN.
Operation is now in Low-speed mode.
Example 2: From High-speed mode to Subosc-speed mode
Operation starts in High-speed mode.
1. Disable the flash cache by resetting FCACHEE.FCACHEEN when the flash cache is cacheable in High-speed
mode.
2. Switch the clock source to sub-clock oscillator.
3. Turn off HOCO, MOCO, MOSC, and PLL.
4. Confirm that all the clock sources other than the sub-clock oscillator are stopped.
5. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed).
6. Set the SOPCCR.SOPCM bit to 1 (Subosc-speed mode).
7. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed).
8. Set the following steps when the flash cache is cacheable in Subosc-speed mode:
a. Invalidate the flash cache by setting the FCACHEIV.FCACHEIV bit.
b. Check that the FCACHEIV.FCACHEIV bit is 0.
c. Enable the flash cache by setting the FCACHEE.FCACHEEN bit.
Operation is now in Subosc-speed mode.
(2)
Switching from a lower power mode to a higher power mode
Example 1: From Subosc-speed mode to High-speed mode
Operation starts in Subosc-speed mode.
1. Disable the flash cache by resetting the FCACHEE.FCACHEEN bit when the flash cache is cacheable in Suboscspeed mode.
2. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed).
3. Set the SOPCCR.SOPCM bit to 0 (High-speed mode).
4. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed).
5. Turn on the oscillator needed in High-speed mode.
6. Set the frequency of each clock to lower than the maximum operating frequency for High-speed mode.
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11. Low Power Modes
7. Set the following steps when the flash cache is cacheable in High-speed mode:
a. Invalidate the flash cache by setting FCACHEIV.FCACHEIV.
b. Check that FCACHEIV.FCACHEIV is 0.
c. Enable the flash cache by setting FCACHEE.FCACHEEN.
Operation is now in High-speed mode.
Example 2: From Low-speed mode to High-speed mode
Operation starts in Low-speed mode.
1. Disable the flash cache by resetting FCACHEE.FCACHEEN when the flash cache is cacheable in Low-speed
mode.
2. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed).
3. Set the OPCCR.OPCM bit to 00b (High-speed mode).
4. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed).
5. Turn on any oscillator needed in High-speed mode.
6. Set the frequency of each clock to lower than the maximum operating frequency for High-speed mode.
7. Set the following steps when the flash cache is cacheable in High-speed mode:
a. Invalidate the flash cache by setting the FCACHEIV.FCACHEIV bit.
b. Check that the FCACHEIV.FCACHEIV is 0.
c. Enable the flash cache by setting FCACHEE.FCACHEEN.
Operation is now in High-speed mode.
11.5.2
Operating Range
High-speed mode
The maximum operating frequency during flash read is 48 MHz for ICLK and 32 MHz for FCLK. The operating voltage
range is 2.4 to 5.5 V during flash read. However, for ICLK and FCLK, the maximum operating frequency during flash
read is 16 MHz when the operating voltage is 2.4 V or larger and smaller than 2.7 V.
During flash programming and erasure, the operating frequency range is 1 to 48 MHz and the operating voltage range is
2.7 to 5.5 V. The PLL can be used when the operating voltage is 2.4 V or above.
Figure 11.2 shows the operating voltages and frequencies in High-speed mode.
VCC
[V]
VCC
[V]
5.5
5.5
P/E
except P/E
2.7
2.7
2.4
2.4
1.8
1.8
1.6
1.6
0.032768
Note 1.
1
4
8
12
16
48*1 ICLK, FCLK
[MHz]
0.032768
1
4
8
12
48*1 ICLK, FCLK
[MHz]
16
Maximum frequency of FCLK is 32 MHz.
Figure 11.2
Operating voltages and frequencies in High-speed mode
Middle-speed mode
The power consumption of this mode is lower than that of High-speed mode under the same conditions.
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11. Low Power Modes
The maximum operating frequency during flash read is 12 MHz for ICLK and FCLK. The operating voltage range is 1.8
to 5.5 V during flash read. However, for ICLK and FCLK, the maximum operating frequency during flash read is 8 MHz
when the operating voltage is 1.8 V or larger and smaller than 2.4 V.
During flash programming and erasure, the operating frequency range is 1 to 12 MHz and the operating voltage range is
1.8 to 5.5 V. The maximum operating frequency during flash programming/erasure is 8 MHz when the operating voltage
is 1.8 V or larger and smaller than 2.4 V. The PLL can be used when the operating voltage is 2.4 V or above.
Figure 11.3 shows the operating voltages and frequencies in Middle-speed mode.
VCC
[V]
VCC
[V]
5.5
5.5
2.7
2.7
except P/E
2.4
2.4
1.8
1.8
1.6
1.6
0.032768
Figure 11.3
1
4
8
12
16
48
ICLK, FCLK
[MHz]
P/E
0.032768
1
4
8
12
16
48
ICLK, FCLK
[MHz]
Operating voltages and frequencies in Middle-speed mode
Low-voltage mode
After a reset is canceled, operation is started from this mode. Using the PLL is prohibited.
The maximum operating frequency during flash read is 4 MHz for ICLK and FCLK. The operating voltage range is 1.6
to 5.5 V during flash read.
During flash programming and erasure, the operating frequency range is 1 to 4 MHz and the operating voltage range is
1.8 to 5.5 V. Using the PLL is prohibited.
Figure 11.4 shows the operating voltages and frequencies in low-voltage mode.
VCC
[V]
VCC
[V]
5.5
5.5
2.7
2.7
P/E
except P/E
2.4
2.4
1.8
1.8
1.6
1.6
0.032768
Figure 11.4
1
4
8
12
16
48
ICLK, FCLK
[MHz]
0.032768
1
4
8
12
16
48
ICLK, FCLK
[MHz]
Operating voltages and frequencies in low-voltage mode
Low-speed mode
The maximum operating frequency during flash read is 1 MHz for ICLK and FCLK. The operating voltage range is 1.8
to 5.5 V during flash read.
P/E operations for flash memory are prohibited. Using the PLL is prohibited.
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11. Low Power Modes
Figure 11.5 shows the operating voltages and frequencies in Low-speed mode.
VCC
[V]
VCC
[V]
5.5
5.5
2.7
2.7
except P/E
2.4
2.4
1.8
1.8
1.6
1.6
0.032768
Figure 11.5
1
4
8
12
16
48
ICLK, FCLK
[MHz]
P/E is prohibited
0.032768
1
4
8
12
16
48
ICLK, FCLK
[MHz]
Operating voltages and frequencies in Low-speed mode
Subosc-speed mode
The maximum operating frequency during flash read is 37.6832 kHz for ICLK and FCLK. The operating voltage range is
1.8 to 5.5 V during flash read.
P/E operations for flash memory are prohibited. Using the oscillators other than the sub-clock oscillator or low-speed onchip oscillator is prohibited.
Figure 11.6 shows the operating voltages and frequencies in Subosc-speed mode.
VCC
[V]
VCC
[V]
5.5
5.5
2.7
except
2.7
P/E
2.4
2.4
1.8
1.8
1.6
1.6
4
8
12
16
48
ICLK, FCLK
[MHz]
2
83
76 8
03 6
0. 327 28
0 5
0. 278
0
0.
2
83
76 8
03 6
0. 327 28
0 5
0. 278
0
0.
Figure 11.6
1
P/E is prohibited
1
4
8
12
16
48
ICLK, FCLK
[MHz]
Operating voltages and frequencies in Subosc-speed mode
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11.6
11.6.1
11. Low Power Modes
Sleep Mode
Transition to Sleep Mode
When a WFI instruction is executed while the SBYCR.SSBY bit is 0, the MCU enters Sleep mode. In this mode, the
CPU stops operating but the contents of its internal registers are retained. Other peripheral functions do not stop.
Available resets or interrupts in Sleep mode cause the MCU to cancel Sleep mode. All interrupt sources are available. If
using an interrupt to cancel Sleep mode, you must set the associated IELSRn register before executing a WFI instruction.
For details, see section 14, Interrupt Controller Unit (ICU).
Counting by IWDT stops when the MCU enters Sleep mode while the IWDT is in auto-start mode and the
OFS0.IWDTSTPCTL bit is 1 (IWDT stops in Sleep mode, Software Standby mode or Snooze mode). Counting by
IWDT continues when the MCU enters Sleep mode while the IWDT is in auto-start mode and the OFS0.IWDTSTPCTL
bit is 0 (IWDT does not stop in Sleep mode, Software Standby mode, or Snooze mode).
Counting by WDT stops when the MCU enters Sleep mode while the WDT is in auto-start mode and the
OFS0.WDTSTPCTL bit is 1 (WDT stops in Sleep mode). Similarly, counting by WDT stops when the MCU enters
Sleep mode while the WDT is in register start mode and the WDTCSTPR.SLCSTP bit in is 1 (WDT stops in Sleep
mode).
Counting by WDT continues when the MCU enters Sleep mode while the WDT is in auto-start mode and the OFS0.
WDTSTPCTL bit is 0 (WDT does not stop in Sleep mode). Similarly, counting by WDT continues when the MCU enters
Sleep mode while the WDT is in register start mode and the WDTCSTPR.SLCSTP bit is 0 (WDT does not stop in Sleep
mode).
11.6.2
Canceling Sleep Mode
Sleep mode is canceled by an interrupt such as:
RES pin reset
Power-on reset
Voltage monitor reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
Reset caused by an IWDT or a WDT underflow.
The operations are as follows:
1. Canceling by an interrupt
When an available interrupt request is generated, Sleep mode is canceled and the MCU starts the interrupt handling.
2. Canceling by RES pin reset
When RES pin is driven low, the MCU enters the reset state. Make sure to keep RES pin low for the time period
specified in section 51, Electrical Characteristics. When RES pin is driven high after the specified time period, the
CPU starts the reset exception handling.
3. Canceling by IWDT reset
Sleep mode is canceled by an internal reset generated by an IWDT underflow and the MCU starts the reset
exception handling. However, IWDT stops in Sleep mode and an internal reset for canceling Sleep mode is not
generated in the following conditions:
OFS0.IWDTSTRT = 0 and OFS0.IWDTSTPCTL = 1.
4. Canceling by WDT reset
Sleep mode is canceled by an internal reset generated by a WDT underflow and the MCU starts the reset exception
handling. However, WDT stops in Sleep mode even when counting in Normal mode and an internal reset for
canceling Sleep mode is not generated in the following conditions:
OFS0.WDTSTRT = 0 (auto-start mode) and OFS0.WDTSTPCTL = 1
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11. Low Power Modes
OFS0.WDTSTRT = 1 (register start mode) and WDTCSTPR.SLCSTP = 1.
5. Canceling by other resets available in Sleep mode
Sleep mode is canceled by other resets and the MCU starts the reset exception handling.
Note:
11.7
11.7.1
For details on proper setting of the interrupts, see section 14, Interrupt Controller Unit (ICU).
Software Standby Mode
Transition to Software Standby Mode
When a WFI instruction is executed while the SBYCR.SSBY bit is 1, the MCU enters Software Standby mode. In this
mode, the CPU, most of the on-chip peripheral functions and oscillators stop. However, the contents of the CPU internal
registers and SRAM data, the states of on-chip peripheral functions and the I/O ports are retained. Software Standby
mode allows a significant reduction in power consumption because most of the oscillators stop in this mode. Table 11.2
shows the status of each on-chip peripheral functions and oscillators. Available resets or interrupts in Software Standby
mode cause the MCU to cancel Software Standby mode. See Table 11.3 for available interrupt sources and section
14.2.9, Wake Up Interrupt Enable Register (WUPEN) for information on how to wake up the MCU from Software
Standby mode. If using an interrupt to cancel Software Standby mode, you must set the associated IELSRn register
before executing a WFI instruction. For details, see section 14, Interrupt Controller Unit (ICU).
Clear the DMAST.DMST and DTCST.DTCST bits to 0 before executing a WFI instruction, except when using the DTC
in Snooze mode. If the DTC is required in Snooze mode, set the DTCST.DTCST bit to 1 before executing a WFI
instruction.
Counting by IWDT stops when the MCU enters Software Standby mode while the IWDT is in auto-start mode and the
OFS0.IWDTSTPCTL bit is 1 (IWDT stops in Sleep mode, Software Standby mode and Snooze mode). Counting by
IWDT continues if the MCU enters Software Standby mode while the IWDT is in auto-start mode and the
OFS0.IWDTSTPCTL bit is 0 (IWDT does not stop in Sleep mode, Software Standby mode, or Snooze mode).
WDT stops counting when the MCU enters Software Standby mode.
Do not enter Software Standby mode while OSTDCR.OSTDE = 1 (oscillation stop detection function is enabled). To
enter Software Standby mode, execute a WFI instruction after disabling the oscillation stop detection function
(OSTDCR.OSTDE = 0). If executing a WFI instruction while OSTDCR.OSTDE = 1, the MCU enters Sleep mode even
when SBYCR.SSBY = 1. In addition, do not enter Software Standby mode while the flash memory performs a
programming or erasing procedure. To enter Software Standby mode, execute a WFI instruction after the programming
or erasing procedure completes.
11.7.2
Canceling Software Standby Mode
Software Standby mode is canceled by an interrupt such as:
RES pin reset
Power-on reset
Voltage monitor reset
Reset caused by an IWDT underflow.
The available interrupts are shown in Table 11.3.
You can cancel Software Standby mode from any of the following ways:
1. Canceling by an interrupt
When an available interrupt request (for available interrupts, see Table 11.3) is generated, an oscillator that operates
before the transition to Software Standby mode restarts. After all the oscillators are stabilized, the MCU returns to
Normal mode from Software Standby mode and starts the interrupt handling. See section 14.2.9, Wake Up Interrupt
Enable Register (WUPEN) for information on how to wake up the MCU from Software Standby mode.
2. Canceling by a RES pin reset
When RES pin is driven low, the MCU enters the reset state, and the oscillators whose default status is operating,
start the oscillation. Be sure to keep the RES pin low for the time period specified in section 51, Electrical
Characteristics. When the RES pin is driven high after the specified time period, the CPU starts the reset exception
handling.
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11. Low Power Modes
3. Canceling by a power-on reset
Software Standby mode is canceled by a power-on reset and the MCU starts the reset exception handling.
4. Canceling by a voltage monitor reset
Software Standby mode is canceled by a voltage monitor reset from the voltage detection circuit and the MCU starts
the reset exception handling.
5. Canceling by IWDT reset
Software Standby mode is canceled by an internal reset generated by an IWDT underflow and the MCU starts the
reset exception handling. However, IWDT stops in Software Standby mode and an internal reset for canceling
Software Standby mode is not generated for the following condition:
OFS0.IWDTSTRT = 0 and OFS0.IWDTSTPCTL = 1.
11.7.3
Example of Software Standby Mode Application
Figure 11.7 shows an example of entry to Software Standby mode on detection of a falling edge of the IRQn pin, and exit
from Software Standby mode by a rising edge of the IRQn pin.
In this example, an IRQn pin interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge)
in Normal mode, and the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge). After that, the SBYCR.SSBY bit is set to
1 and a WFI instruction is executed. As a result, entry to Software Standby mode completes and exit from Software
Standby mode is initiated by a rising edge of the IRQn pin.
Setting the ICU is also required to exit Software Standby mode. For details, see section 14, Interrupt Controller Unit
(ICU). The oscillation stabilization time in Figure 11.7 is specified in section 51, Electrical Characteristics.
Oscillator
ICLK
IRQn pin
IRQMD[1:0]
01b
10b
SBYCR.SSBY
IRQ exception handling
IRQMD[1:0] = 10b
SBYCR.SSBY = 1
WFI instruction
Figure 11.7
IRQ exception handling
Software Standby mode
Oscillation
settling time
Example of Software Standby mode application
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11.8
11. Low Power Modes
Snooze Mode
11.8.1
Transition to Snooze Mode
Figure 11.8 shows Snooze mode entry configuration. When the Snooze control circuit receives a snooze request in
Software Standby mode, the MCU transitions to Snooze mode. In this mode, some peripheral modules operate without
waking up the CPU. Table 11.2 shows the peripheral modules that can operate in Snooze mode. Also, the DTC operation
can be selected in Snooze mode by setting the SNZCR.SNZDTCEN bit.
ICU
Snooze Control Circuit
WUPEN.bn
1
Wakeup request
Interrupt request
0
n = 0 to 15, 17, 23 to 25, 28 to 30
PAD (RXD0)
ELC
SNZCR.b7
SNZREQCR.bn
Control
SYSTEM_SNZREQ
(Snooze entry)
ELSRx
Event control
Snooze request
SNZCR.b0
Noise filter
+
Edge detect
SCI0
rxd
Figure 11.8
Snooze mode entry configuration
Table 11.6 shows the snooze requests that switch the MCU from Software Standby mode to Snooze mode. To use the
listed snooze requests as a trigger to switch to Snooze mode, you must set the associated SNZREQENn bit of the
SNZREQCR register or RXDREQEN bit of the SNZCR register before entering Software Standby mode.
Note:
Do not enable multiple snooze requests at the same time.
Table 11.6
Available snooze requests to switch to Snooze mode
Control Register
Snooze request
Register
Bit
PORT_IRQn (n = 0 to 15)
SNZREQCR
SNZREQENn (n = 0 to 15)
KEY_INTKR
SNZREQCR
SNZREQEN17
ACMP_LP0
SNZREQCR
SNZREQEN23
RTC_ALM
SNZREQCR
SNZREQEN24
RTC_PRD
SNZREQCR
SNZREQEN25
AGT1_AGTI
SNZREQCR
SNZREQEN28
AGT1_AGTCMAI
SNZREQCR
SNZREQEN29
AGT1_AGTCMBI
SNZREQCR
SNZREQEN30
RXD0 falling edge
SNZCR
RXDREQEN*1
Note 1.
RXDREQEN bit must not be set to 1 except in asynchronous mode.
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11.8.2
11. Low Power Modes
Canceling Snooze Mode
Snooze mode is canceled by an interrupt request that is available in Software Standby mode or a reset. Table 11.3 shows
the requests that can be used to exit each mode. After exiting the Snooze mode, the MCU enters Normal mode and
proceeds with exception processing for the given interrupt or reset. An action triggered by the interrupt requests selected
in SELSR0, cancels Snooze mode. The interrupt that cancels the Snooze mode must be selected in IELSRn (n = 0 to 63)
to link to the NVIC for the corresponding interrupt handling. See section 14, Interrupt Controller Unit (ICU) for
information on SELSR0 and IELSRn registers.
WFI
instruction
Trigger
detection
Interrupt
request
High
Standby cancel
signal
Low
Snooze end
signal
Low power mode
Oscillator
for system clock
Low
Normal
mode*3
Software
Standby
mode
Oscillates
Oscillation
stopped
*1
Snooze mode
*2
Normal mode*4
Oscillates
Wait for oscillation accuracy stabilization
Note 1.
Note 2.
Note 3.
Note 4.
Figure 11.9
11.8.3
Transition time from Software Standby mode to Snooze mode.
Transition time from Snooze mode to Normal mode.
Enable Snooze mode (SNZCR.SNZE = 1) immediately before switching to Software Standby mode.
Disable Snooze mode (SNZCR.SNZE = 0) immediately after exiting Snooze mode.
Canceling Snooze mode when an interrupt request signal is generated
Returning to Software Standby Mode
Table 11.7 shows the snooze end requests that can be used as triggers to return to Software Standby mode. The snooze
end requests are available only in Snooze mode. If the requests are generated when the MCU is not in Snooze mode, they
are ignored. When multiple requests are selected, each one of the requests invokes transition to Software Standby mode
from Snooze mode.
Table 11.8 shows the snooze end conditions that consist of the snooze end requests and the conditions of the peripheral
modules. The CTSU, SCI0, ADC140, and DTC modules can keep the MCU in Snooze mode until they complete
operation. However, an AGT1 underflow as a trigger to return to Software Standby mode cancels Snooze mode without
waiting for the completion of SCI0 operation.
Figure 11.10 shows the timing diagram for the transition from Snooze mode to Software Standby mode. This mode
transition occurs depending on which snooze end requests are set in the SNZEDCR register. A snooze request is cleared
automatically after the transition to Software Standby mode.
Table 11.7
Available snooze end requests (triggers for transition to Software Standby mode) (1 of 2)
Enable/disable control
Snooze end request
Register
Bit
AGT1 underflow or measurement complete (AGT1_AGTI)
SNZEDCR
bit [0]
DTC transfer complete (DTC_COMPLETE)
SNZEDCR
bit [1]
DTC transfer not complete (DTC_TRANSFER)
SNZEDCR
bit [2]
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Table 11.7
11. Low Power Modes
Available snooze end requests (triggers for transition to Software Standby mode) (2 of 2)
Enable/disable control
Snooze end request
Register
Bit
ADC140 window A/B compare match (ADC140_WCMPM)
SNZEDCR
bit [3]
ADC140 window A/B compare mismatch (ADC140_WCMPUM)
SNZEDCR
bit [4]
SCI0 address mismatch (SCI0_DCUF)
SNZEDCR
bit [7]
Table 11.8
Snooze end conditions
Operating module when a
snooze end request occurs
DTC
ADC140
Snooze end request
AGT1 underflow
Other than AGT1 underflow
The MCU transitions to Software Standby mode
after all of the modules listed in this table
complete operation
The MCU transitions to Software Standby mode
after all of the modules listed to the left of this
column complete operation
CTSU
SCI0
The MCU transitions to Software Standby mode
immediately after a snooze end request is
generated
All other modules
The MCU transitions to Software Standby mode immediately after a snooze end request is generated
Note:
If the DTC is used to activate the ADC140, CTSU, or SCI, the MCU transitions to Software Standby mode after a snooze end
request is generated.
WFI
instruction
Trigger
detection
Standby release
signal
Low
Snooze end signal
Low power mode
Oscillator
for system clock
Normal
mode*2
Software
Standby
mode
Oscillates
Oscillation
stopped
*1
Snooze mode
Oscillates
Software Standby mode
Oscillation stopped
Wait for oscillation accuracy stabilization
Note 1.
Note 2.
Figure 11.10
Transition time from Software Standby mode to Snooze mode.
Enable Snooze mode (SNZCR.SNZE = 1) immediately before transitioning to Software Standby mode.
Canceling of Snooze mode when an interrupt request signal is not generated
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11.8.4
11. Low Power Modes
Snooze Operation Example
Figure 11.11 shows an example setting for using ELC in Snooze mode.
Start Snooze mode setting
Setting for ELC in Snooze mode
MSTPCRC.MSTPC14 = 0
Cancel ELC module-stop state
Snooze entry (SYSTEM_SNZREQ)
signal is linked to modules
ELSRx.ELS = 01Dh
ELCR.ELCON = 1
ELC function enabled
Setting for Snooze cancel
SELSR0.SELS = 0xxh
Select event number in Table 14.4 as
the source for canceling Snooze mode
IELSRy.DTCE = 0
IELSRy.IELS = 017h
Select canceling Snooze mode as the
interrupt request
Setting for Snooze end
SNZEDCR.bm = 1
Enable Snooze end request m
Setting for snooze request
WUPEN.bn = 0
SNZREQCR.bn = 1
Disable wakeup request n
Enable snooze request n
SNZCR.b7 = 1
(SNZE = 1)
Enable Snooze mode
Complete Snooze mode
setting
WFI instruction
Enter Software Standby mode
Software Standby mode
Snooze request?
No
Yes
Snooze mode
SYSTEM_SNZREQ
by way of ELC
Operating module
SELS event
SELS event or
Snooze end request?
Snooze end request
Snooze end
Interrupt for
canceling Snooze mode
Normal mode
Figure 11.11
Setting example of using ELC in Snooze mode
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11. Low Power Modes
The MCU can transmit and receive data in SCI0 asynchronous mode without CPU intervention. When using the SCI0 in
Snooze mode, use one of the following operating modes:
High-speed mode
Middle-speed mode
Low-speed mode.
Do not use Low-voltage mode or Subosc-speed mode.
Table 11.9 and Table 11.10 show the maximum transfer rate of SCI0 in Snooze mode.
When using SCI0 in the Snooze mode, set the following bits:
Set BGDM to 0
Set ABCS to 0
Set ABCSE to 0.
See section 29, Serial Communications Interface (SCI) for details.
High-speed mode, Middle-speed mode, Low-speed mode
Table 11.9
HOCO: ± 1.0% (Ta = -20 to 85°C)
(Unit: bps)
Maximum division ratio of ICLK,
PCLKA, PCLKB, PCLKC, PCLKD,
FCLK, BCLK, and TRCLK
HOCO frequency
24 MHz
32 MHz
48 MHz
64 MHz
1
9600*1
-
-
-
2
9600*2
9600*4
4800
-
4
9600*3
9600*5
4800
2400
8
4800
4800
4800
2400
16
4800
4800
4800
2400
32
2400
2400
2400
2400
64
2400
2400
2400
2400
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 3Dh, SCI0.MDDR = CEh must be used for 9600 bps.
SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 1Eh, SCI0.MDDR = CEh must be used for 9600 bps.
SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 0Dh, SCI0.MDDR = BAh must be used for 9600 bps.
SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 32h, SCI0.MDDR = FEh must be used for 9600 bps.
SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 18h, SCI0.MDDR = F9h must be used for 9600 bps.
High-speed mode, Middle-speed mode, Low-speed mode
Table 11.10
HOCO: ± 2.0% (Ta = -40 to -20°C, 85 to 105°C)
(Unit: bps)
Maximum division ratio of ICLK,
PCLKA, PCLKB, PCLKC, PCLKD,
FCLK, BCLK, and TRCLK
HOCO frequency
24 MHz
32 MHz
48 MHz
64 MHz
1
2400
-
-
-
2
2400
2400
2400
-
4
2400
2400
2400
1200
8
2400
2400
2400
1200
16
2400
2400
2400
1200
32
1200
1200
1200
1200
64
1200
1200
1200
1200
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11. Low Power Modes
Figure 11.12 shows an example setting for using the SCI0 in Snooze mode entry.
Start Snooze mode setting
Setting for SCI0 in Snooze mode
MSTPCRB.MSTPB31 = 0
Cancel SCI0 module-stop state
Set SCI0
Set as asynchronous UART receive mode
SCKSCR.CKSEL = 0h
The clock source must be HOCO
MOCOCR.MCSTP = 1
MOSCCR.MOSTP = 1
PLLCR.PLLSTP = 1
Stop MOCO, MOSC, and PLL
MSTPCRC.MSTPC0 = 1
Enter CAC module-stop state
Hold the communications line in the mark
state before entering Software Standby
mode
RXD0 = 1
Setting for Snooze cancel
Select SCI0_RXI_OR_ERI event as the
source of canceling Snooze mode
SELSR0.SELS = 0B1h
IELSRy.DTCE = 0
IELSRy.IELS = 017h
Select canceling Snooze mode as the
interrupt request
Setting for snooze end
SNZEDCR.b7 = 1
(SCI0UMTED = 1)
Enable snooze end request by SCI0
address mismatch
Setting for AGT1 to avoid Snooze mode by
a noise on the RXD0 pin
MSTPCRD.MSTPD2 = 0
Cancel AGT1 module stop state
Set as a timer to avoid Snooze mode by a
noise on the RXD0 pin
Set AGT1
SNZEDCR.b0 = 1
(AGTUNFED = 1)
Enable snooze end request by AGT1
Underflow
SNZCR.b0 = 1
(RXDREQEN) = 1
Detect RXD0 falling edge in Software
Standby mode as a request to transition to
Snooze mode
Setting for Snooze request
SNZCR.b7 = 1
(SNZE = 1)
Enable Snooze mode
Complete Snooze mode setting
WFI instruction
Enter Software Standby mode
Software Standby mode
Snooze request?
No
Yes
Snooze mode
SCI0 receive data
is completed before
AGT1 underflow?
Yes
SELS event or
snooze end request?
No
AGT1 underflow
SELS event
(receive data full or receive error)
Snooze end request
(address mismatch)
Snooze end
Interrupt for
canceling Snooze mode
Normal mode
Figure 11.12
Setting example of using SCI0 in Snooze mode entry
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11.9
Usage Notes
11.9.1
(1)
11. Low Power Modes
Register Access
Invalid register write accesses during specific modes or transitions
Do not write to registers listed in this section in any of the following conditions.
[Registers]
All registers with a peripheral name of SYSTEM.
[Conditions]
OPCCR.OPCMTSF = 1 or SOPCCR.SOPCMTSF = 1 (during transition of the operating power control mode)
Time period from executing a WFI instruction to returning to Normal mode
FENTRYR.FENTRY0 = 1 or FENTRYR.FENTRYD = 1 (flash P/E mode, data flash P/E mode)
FLSTOP.FLSTPF = 1 (during transition).
(2)
Valid setting of the clock-related registers
Table 11.11 and Table 11.12 show the valid setting of the clock-related registers in each operating power control mode.
Do not write any value other than the valid setting. Any other value written is ignored. Additionally, each register has
certain prohibited settings under conditions other than those related to the operating power control modes. See section 9,
Clock Generation Circuit for these other conditions for each register.
Table 11.11
Valid settings for clock-related registers (1)
Valid setting
SCKSCR.
CKSEL[2:0],
CKOCR.
CKOSEL[2:0]
SCKDIVCR
.FCK[2:0],
SCKDIVCR
.ICK[2:0]
Highspeed,
Middlespeed
000b (HOCO)
001b (MOCO)
010b (LOCO)
011b (MOSC)
100b (SOSC)
101b (PLL)*1
000b (LOCO)
001b (SOSC)
010b (MOSC)
100b (HOCO)
Lowspeed,
Lowvoltage
000b (HOCO)
001b (MOCO)
010b (LOCO)
011b (MOSC)
100b (SOSC)
000b (1/1)
001b (1/2)
010b (1/4)
011b (1/8)
100b (1/16)
101b (1/32)
110b (1/64)
Suboscspeed
010b (LOCO)
100b (SOSC)
000b (1/1)
000b (LOCO)
001b (SOSC)
Mode
Note 1.
SLCDSCKCR.
LCDSCKSEL[
2:0]
PLLCR.
PLLSTP
HOCOCR.
HCSTP
MOCOCR.
MCSTP
LOCOCR.
LCSTP
MOSCCR.
MOSTP
SOSCCR.S
OSTP
0 (operating)
1 (stopped)
0 (operating)
1 (stopped)
0 (operating)
1 (stopped)
0 (operating)
1 (stopped)
0 (operating)
1 (stopped)
0 (operating)
1 (stopped)
1 (stopped)
1 (stopped)
0 (operating)
1 (stopped)
1 (stopped)
0 (operating)
1 (stopped)
1 (stopped)
1 (stopped)
SCKSCR.CKSEL[2:0] only.
Table 11.12
Valid setting for clock-related registers (2)
Valid setting
Operating oscillator
SOPCCR.SOPCM
OPCCR.OPCM[1:0]
PLL
0
00b, 01b
High-speed on-chip oscillator
0
00b, 01b, 10b, 11b
0, 1
00b, 01b, 10b, 11b
Middle-speed on-chip oscillator
Main clock oscillator
Low-speed on-chip oscillator
Sub-clock oscillator
IWDT-dedicated on-chip oscillator
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(3)
11. Low Power Modes
Invalid register write accesses in subosc-speed mode
Do not write to registers listed in this section for the following condition.
[Registers]
SCKSCR, OPCCR.
[Condition]
SOPCCR.SOPCM = 1 (Subosc-speed mode).
(4)
Invalid register write accesses by DTC or DMAC
Do not write to the registers listed in this section using the DTC or DMAC.
[Registers]
MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD.
(5)
Invalid register write accesses in Snooze mode
Do not write to the registers listed in this section in Snooze mode. They must be set before entering Software Standby
mode.
[Registers]
SNZCR, SNZEDCR, SNZREQCR.
(6)
Invalid write access to set FLSTOP.FLSTOP bit to 1
Do not set the FLSTOP.FLSTOP bit to 1 under any of the following conditions:
[Conditions]
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 00b (High-speed mode)
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 01b (Middle-speed mode)
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 11b (Low-speed mode)
SOPCCR.SOPCM = 1 (Subosc-speed mode).
(7)
Invalid write access to set MEMWAIT.MEMWAIT bit to 1
Do not set the MEMWAIT.MEMWAIT bit to 1 in any of the following conditions:
[Conditions]
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 01 (Middle-speed mode)
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 10 (Low-voltage mode)
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 11 (Low-speed mode)
SOPCCR.SOPCM = 1 (Subosc-speed mode).
(8)
Invalid write access when PRCR.PRC1 bit is 0
Do not write to the registers listed in this section when PRCR.PRC1 bit is 0.
[Registers]
SBYCR, SNZCR, SNZEDCR, SNZREQCR, FLSTOP, PSMCR, OPCCR, SOPCCR.
11.9.2
I/O Port States
The I/O port states in Software Standby mode and Snooze mode (except when modifying in Snooze mode) are the same
before entering the modes. Therefore, power consumption is not reduced while the output signals are held high.
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11.9.3
11. Low Power Modes
Module-Stop State of DMAC and DTC
Before writing 1 to MSTPCRA.MSTPA22, set the DMAST.DMST bit of the DMAC and the DTCST.DTCST bit of the
DTC to 0. For details, see section 17, DMA Controller (DMAC) and section 18, Data Transfer Controller (DTC).
11.9.4
Internal Interrupt Sources
Interrupts do not operate in the module-stop state. If the module-stop bit is set while an interrupt request is generated, a
CPU interrupt source or a DMAC or DTC startup source cannot be cleared. For this reason, make sure you disable the
corresponding interrupts before setting the module-stop bits.
11.9.5
Transition to Low Power Modes
Because the MCU does not support wakeup by event, do not enter low power modes (Sleep mode or Software Standby
mode) by executing a WFE instruction. Also, do not set the SLEEPDEEP bit of the System Control Register in the
Cortex®-M4 core because the MCU does not support low power modes by SLEEPDEEP.
11.9.6
Timing of WFI Instruction
It is possible for the WFI instruction to be executed before I/O register and CS area writes are complete, in which case
operation might not proceed as intended. This can happen if the WFI instruction is executed immediately after a write to
an I/O register or CS area. To avoid this problem, it is recommended that you read back the register and CS area that was
written to confirm that the write completed. For example, reading the MSTPCRB register before executing the WFI
instruction can secure the period to complete writing to the I/O register.
11.9.7
Writing WDT/IWDT Registers by DMAC or DTC in Sleep Mode or Snooze Mode
Do not write to the registers in WDT or IWDT using the DMAC or DTC while WDT or IWDT stops by entering Sleep
mode or Snooze mode.
11.9.8
Oscillators in Snooze Mode
Oscillators that stop by entering Software Standby mode automatically restart when a trigger to switch to Snooze mode is
generated. The MCU does not enter Snooze mode until all the oscillators stabilize. If in Snooze mode, you must disable
oscillators that are not required in Snooze mode before entering Software Standby mode. Otherwise, the transition from
Software Standby mode to Snooze mode takes longer.
11.9.9
Snooze Mode Entry by RXD0 Falling Edge
When the SNZCR.RXDREQEN bit is 1, noise on the RXD0 pin might cause the MCU to transition from Software
Standby mode to Snooze mode. Any subsequent RXD0 data can be received in Snooze mode by a noise on the RXD0
pin. If the MCU does not receive RXD0 data after the noise, interrupts such as SCI0_ERI or SCI0_RXI and address
mismatch events are not generated, and the MCU stays in Snooze mode. To avoid this, an AGT1 underflow interrupt
must be used to return to Software Standby mode or Normal mode when using SCI0 in Snooze mode. However, do not
use the AGT1 underflow as a source to return to Software Standby mode during an SCI communication. This causes the
SCI0 to stop the operation in a half-finished state.
11.9.10
Using SCI0 in Snooze Mode
When using SCI0 in Snooze mode, a wakeup request other than an AGT1 underflow must not be used.
When using SCI0 in Snooze mode, the following conditions must be satisfied:
The clock source must be HOCO
MOCO, MOSC, and PLL must stop before entering Software Standby mode
The RXD0 pin must be kept at high level before entering Software Standby mode
A transition to Software Standby mode must not occur during an SCI communication
The MSTPCRC.MSTPC0 bit must be 1 before entering Software Standby mode.
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11.9.11
11. Low Power Modes
Conditions of A/D Conversion Start in Snooze Mode
The A/D converter can only be triggered by the ELC in Snooze mode. Do not use a software trigger or ADTRG0 pin.
11.9.12
Conditions of CTSU in Snooze Mode
The CTSU can only be started by the ELC in Snooze mode.
11.9.13
ELC Event in Snooze Mode
The ELC events available in Snooze mode are listed in this section. Do not use any other events. If starting peripheral
modules for the first time after entering Snooze mode, the Event Link Setting Register (ELSRn) must set a Snooze mode
entry event (SYSTEM_SNZREQ) as the trigger.
Snooze mode entry (SYSTEM_SNZREQ)
DTC transfer end (DTC_DTCEND)
ADC140 window A/B compare match (ADC140_WCMPM)
ADC140 window A/B compare mismatch (ADC140_WCMPUM)
Data operation circuit interrupt (DOC_DOPCI).
11.9.14
Module-Stop Function for ADC140
When entering Software Standby mode, it is recommended that you set the ADC140 module-stop state to reduce power
consumption. In this case, the ADC140 can be available in Snooze mode by releasing the ADC140 module-stop using
the DTC. Similarly, set the module-stop state using the DTC before returning to Software Standby mode from Snooze
mode.
11.9.15
Module-Stop Function for an Unused Circuit
A circuit that is not used in user mode might not be reset, and might operate in an unstable state because the clocks are
not supplied during an MCU reset. In this case, when the MCU transitions to Low-speed mode or Software Standby
mode, the supply current could increase to a value greater than the specified value (as provided in this User’s Manual),
by up to 600 µA. So, initialize the unused circuit as shown in Figure 11.13.
Turn the power on
Release the protection of the Protect Register
PRCR.PRC1 = 1
Release from the module-stop state
MSTPCRC.MSTPC31 = 0
Wait for 3 PCLKB cycles
for example: dummy = PORT1.PODR.BYTE;
while (dummy != PORT1.PODR.BYTE) { }
Transition to the module-stop state
MSTPCRC.MSTPC31 = 1
Set the Protect Register
PRCR.PRC1 = 0
End
Figure 11.13
Initial setting flow example for an unused circuit
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12. Battery Backup Function
12.
Battery Backup Function
12.1
Overview
The MCU provides a battery backup function that maintains partial battery powering in the event of a power loss.
Switching between VCC and VBATT, the battery-powered area includes RTC, SOSC, LOCO, Wakeup Control/Backup
Memory, VBATT_R Low Voltage Detection, and VBATT Low Voltage Detection.
During normal operation, the battery-powered area is powered by the main power supply, the VCC pin. When a VCC
voltage drop is detected, the power source switches to the dedicated battery backup power pin, the VBATT pin. When the
voltage rises again, the power source switches back from VBATT to VCC. Table 12.1 lists the VBATT wakeup I/O pin
configuration.
Table 12.1
VBATT wakeup I/O pin configuration
Pin Name
I/O
Function
VBATWIOn
Input/Output
Output wakeup signal for the VBATT Wakeup Control function.
External event input for the VBATT Wakeup Control function.
Note:
12.1.1
n = 0 to 2.
Features of Battery Backup Function
Battery backup features include:
Battery power supply switch
VBATT pin low voltage detection
VBATT_R low voltage detection
Backup registers
VBATT wakeup control function
Time capture pin detection.
12.1.2
Battery Power Supply Switch
When the voltage applied to the VCC pin drops, this feature switches the power supply from the VCC pin to the VBATT
pin. When the voltage rises, it switches the power supply from the VBATT pin back to the VCC pin.
The switch is controlled by the VBTCR1.BPWSWSTP bit. By default, switching is enabled. It can be disabled by setting
the VBTCR1.BPWSWSTP bit to 1.
12.1.3
VBATT Pin Low Voltage Detection
The VBATT low voltage detection function supports the battery-powered area. This function monitors whether power is
supplied to the VBATT pin.
It is possible to detect a low voltage condition of the power supply using a flag provided in the VBATT status register.
12.1.4
VBATT_R Low Voltage Detection
VBATT_R low voltage detection function supports the battery-powered area. This function monitors the VBATT_R
voltage level. VBATT_R is the output voltage of the battery power supply switch.
This low voltage detection causes a VBATT_POR reset and initializes the battery-powered area. See details in each
register description. The VBATT status register includes a flag to check for this low voltage detection.
12.1.5
Backup Registers
The battery-powered area provides 512 one-byte backup registers. These registers retain data only when VBATT is
supplied and VCC is powered off. This memory is checked by the VBATT pin low voltage detection.
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12.1.6
12. Battery Backup Function
VBATT Wakeup Control Function
The VBATT wakeup control function is a function that can toggle the VBATWIO[2:0] pins when the RTC alarm,
periodic signal, or VBATWIOn (n = 0 to 2) input signal is asserted when VBATT_R is powered by the VBATT pin.
Note:
12.1.7
The toggle triggered by the wakeup control function does not generate an interrupt to the ICU or a reset to the
reset module. The use case of this function is that the output toggle triggers other devices on board to control the
VCC power supply. For details, see section 12.3.5, VBATT Wakeup Control Function Usage.
Time Capture Pin Detection
The RTC detects input level changes on the time capture pins, RTCICn (n = 0 to 2).
For the function of the RTCICn pins, see section 25, Realtime Clock (RTC). To use RTCICn pins, set the VBTICTLR
register as described in section 12.2, Register Descriptions.
Note:
Note:
When the battery backup function is not used, the VBATT pin must be connected to the VCC pin.
When power is turned on, power is not supplied to the RTC, the SOSC (including multiplexed port), or the LOCO
before setting the VBTCR1.BPWSWSTP bit to 1. It takes the VBATT_POR reset time tVBATPOR as described in
section 51, Electrical Characteristics to supply power to the modules after setting the VBTCR1.BPWSWSTP bit.
The VBTCR1.BPWSWSTP bit must be set to 1 after a power-on reset, regardless of whether the VBATT function
is used. See section 12.2.1, VBATT Control Register 1 (VBTCR1) for details.
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12. Battery Backup Function
Figure 12.1 shows the configuration of the battery backup function.
Internal reference
voltage
+
-
Switch
control
VDETBATT
VCC
VBATT_R
VBATT
Internal reference
voltage
+
-
VDETBATLVD
Internal reference
voltage
Voltage regulator
for backup power
area
+
VVBATPOR
VBATT backup
register
VBATT reset
detect flag
VBATT battery low
detect flag
VCH0OEN
VBATT_POR
Interrupt
(VBATT_LVD)
Non-maskable
interrupt
P402/VBATWIO0/RTCIC0
VCH0INEN
VCH1OEN
P403/VBATWIO1/RTCIC1
VCH1INEN
VCH2OEN
P404/VBATWIO2/RTCIC2
VCH2INEN
LOCO
XCIN
XCOUT
RTC_PRD
Sub-clock
oscillator
RTC
VBATT wakeup
control
RTC_ALM
Backup power area
VCC
VBATT
XCIN
XCOUT
VBATWIOn (n = 0 to 2)
RTCICn (n = 0 to 2)
Figure 12.1
Power supply pin
Backup power pin
SOSC input pin
SOSC output pin
VBATT wakeup output port
RTC time capture input port
Configuration of the battery backup function
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12.2
12. Battery Backup Function
Register Descriptions
12.2.1
VBATT Control Register 1 (VBTCR1)
Address(es): SYSTEM.VBTCR1 4001 E41Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
BPWS
WSTP
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BPWSWSTP
Battery Power Supply Switch Stop
0: Enable battery power supply switch
1: Stop battery power supply switch.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
BPWSWSTP bit (Battery Power Supply Switch Stop)
The BPWSWSTP bit can enable the battery power supply switch to switch the battery backup module supply voltage
from VCC to VBATT when the voltage applied to the VCC pin drops. When stopped, the battery backup module power
supply is always from VCC. To disable the battery backup function, write 1 to this bit. This bit is initialized only by a
power-on reset.
Note:
Note:
This bit can be set without checking the VBATSR.VBTRVLD bit status.
The VBTCR1.BPWSWSTP bit must be set to 1 after a power-on reset, regardless of whether the VBATT function
is used. The setting flow of the VBTCR1.BPWSWSTP bit is shown in Figure 12.2. Also, the
VBTCR1.BPWSWSTP bit must be cleared after other related registers are set, when the VBATT function is used.
Start
VBTCR1.BPWSWSTP = 1
No
VBTSR.VBTRVLD = 1?
Yes
End
Figure 12.2
Note:
Setting flow of the VBTCR1.BPWSWSTP bit
In Figure 12.2, if the VBTSR.VBTRVLD bit is not 1, it takes the VBATT_POR reset time tVBATPOR as described in
section 51, Electrical Characteristics, to exit the loop.
The following registers cannot be accessed when the VBTSR.VBTRVLD bit is 0. Other registers can be
accessed regardless of this condition:
LOCOCR, LOCOUTCR, SOSCCR, and SOMCR described in section 9, Clock Generation Circuit
All registers described in this section except for VBTCR1 and the VBTSR.VBTRVLD bit
All registers described in section 25, Realtime Clock (RTC).
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12.2.2
12. Battery Backup Function
VBATT Control Register 2 (VBTCR2)
Address(es): SYSTEM.VBTCR2 4001 E4B0h
b7
b6
VBTLVDLVL[1:0
]
Value after reset:
0
0
b5
b4
b3
b2
b1
b0
—
VBTLV
DEN
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
VBTLVDEN
VBATT Pin Low Voltage Detect
Enable
0: VBATT pin low voltage detection disabled
1: VBATT pin low voltage detection enabled.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7, b6
VBTLVDLVL[1:0]
VBATT Pin Low Voltage Detect Level
Select
b7 b6
0
0
1
1
0: Reserved
1: Setting prohibited
0: 2.3 V
1: 2.1 V.
R/W
R/W
The VBTCR2 register controls the VBATT pin low voltage detection function. VBTCR2 is reset by the VBATT_POR
signal.
VBTLVDEN bit (VBATT Pin Low Voltage Detect Enable)
The VBTLVDEN bit controls the VBATT pin low voltage detection.
VBTLVDLVL[1:0] bits (VBATT Pin Low Voltage Detect Level Select)
The VBTLVDLVL[1:0] bits select the VBATT pin low voltage detection level.
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12.2.3
12. Battery Backup Function
VBATT Status Register (VBTSR)
Address(es): SYSTEM.VBTSR 4001 E4B1h
Value after reset:
b7
b6
b5
b4
b3
b2
—
—
—
VBTRV
LD
—
—
0
0
0
0*5
0
0
b1
b0
VBTBL VBTRD
DF
F
0*2
1*1
Bit
Symbol
Bit name
Description
R/W
b0
VBTRDF
VBATT_R Reset Detect Flag
0: VBATT_R voltage power-on reset not detected
1: VBATT_R selected voltage power-on reset detected.
R/(W)
*3
b1
VBTBLDF
VBATT Battery Low Detect Flag*4
0: VBATT pin low voltage not detected
1: VBATT pin low voltage detected.
R/(W)
*3
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
VBTRVLD
VBATT_R Valid
0: VBATT_R area not valid
1: VBATT_R area valid.
R
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
This flag is only set by the VBATT_POR reset.
This flag is only reset by the VBATT_POR reset.
Only 0 can be written after reading 1.
This flag is only valid when VBTLVDEN is 1. If VBTLVDEN is 0, this flag is read as 0.
Depends on the VBATT_R voltage level.
VBTRDF flag (VBATT_R Reset Detect Flag)
The VBTRDF flag indicates that a VBATT_R (selected voltage of VCC or VBATT) power-on reset occurs.
[Setting condition]
When a VBATT_R voltage power-on reset occurs.
[Clearing condition]
When VBTRDF is read as 1 and 0 is written to VBTRDF.
VBTBLDF flag (VBATT Battery Low Detect Flag)
The VBTBLDF flag indicates that a VBATT pin low voltage detection occurs.
[Setting condition]
When VBATT pin low voltage detection occurs.
[Clearing condition]
When VBTBLDF is read as 1 and 0 is written to VBTBLDF.
VBTRVLD bit (VBATT_R Valid)
Check whether the VBATT area is valid.
The VBTRVLD bit checks whether the VBATT_R area is valid. It must confirm that the VBTRVLD bit is 1 before
writing to or reading from the following registers:
LOCOCR, LOCOUTCR, SOSCCR, and SOMCR described in section 9, Clock Generation Circuit
All registers described in this section except for VBTCR1 and the VBTSR.VBTRVLD bit
All registers described in section 25, Realtime Clock (RTC).
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12.2.4
12. Battery Backup Function
VBATT Comparator Control Register (VBTCMPCR)
Address(es): SYSTEM.VBTCMPCR 4001 E4B2h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
VBTCM
PE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VBTCMPE
VBATT Pin Low Voltage Detect Circuit
Output Enable
0: VBATT pin low voltage detect circuit output disabled
1: VBATT pin low voltage detect circuit output enabled.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
VBTCMPE bit (VBATT Pin Low Voltage Detect Circuit Output Enable)
The VBTCMPE bit controls the VBATT pin low voltage detection circuit output. This bit is initialized by the
VBATT_POR signal.
12.2.5
VBATT Pin Low Voltage Detect Interrupt Control Register (VBTLVDICR)
Address(es): SYSTEM.VBTLVDICR 4001 E4B4h
b7
Value after reset:
b6
b5
b4
b3
b2
—
—
—
—
—
—
0
0
0
0
0
0
b1
b0
VBTLV VBTLV
DISEL
DIE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VBTLVDIE
VBATT Pin Low Voltage Detect Interrupt
Enable
0: VBATT pin low voltage detection interrupt disabled
1: VBATT pin low voltage detection interrupt enabled.
R/W
b1
VBTLVDISEL
Pin Low Voltage Detect Interrupt Select
0: Non-maskable interrupt
1: Maskable interrupt.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0. R/W
The VBTLVDICR is reset by the VBATT_POR signal.
12.2.6
VBATT Backup Register (VBTBKRn) (n = 0 to 511)
Address(es): SYSTEM.VBTBKR0 4001 E500h to SYSTEM.VBTBKR511 4001 E6FFh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
VBTBKR[7:0]
Value after reset:
x
x
x
x
x
x: Undefined
VBTBKRn is an 8-bit access read/write register to store data powered by VBATT. The value of this register is saved
even in VBATT mode. This register is not initialized by any reset.
Note:
When accessing the VBATT Backup Register, the VCC level must be over V_BKBATT as described in section 51,
Electrical Characteristics.
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12.2.7
12. Battery Backup Function
VBATT Wakeup Control Register (VBTWCTLR)
Address(es): SYSTEM.VBTWCTLR 4001 E4B6h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
VWEN
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VWEN
VBATT Wakeup Enable
0: Disable wakeup function
1: Enable wakeup function.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The VBTWCTLR register controls the VBATT wakeup function. VBTWCTLR is reset by the VBATT_POR signal.
VWEN bit (VBATT Wakeup Enable)
The VWEN bit enables the VBATT wakeup control function. When the VWEN bit is set to 0 and the
VBTOCTLR.VCHnOEN (n = 0 to 2) bit is set to 1, the VBATWIOn (n = 0 to 2) pin output is low level. When the
VWEN bit is set to 1, the output from the VBATWIOn pin changes to the level specified by the
VBTOCTLR.VOUTnLSEL (n = 0 to 2) bit.
Set the VWEN bit to 1 only after setting of the following registers is complete. Set VWEN to 0 first before modifying the
following registers:
VBTWCHnOTSR
VBTICTLR
VBTOCTLR
VBTWTER
VBTWEGR (n = 0 to 2).
12.2.8
VBATT Wakeup I/O 0 Output Trigger Select Register (VBTWCH0OTSR)
Address(es): SYSTEM.VBTWCH0OTSR 4001 E4B8h
b7
Value after reset:
b6
b5
—
—
—
0
0
0
b4
b3
b2
b1
CH0VR CH0VR CH0VC CH0VC
TCATE TCTE H2TE H1TE
0
Bit
Symbol
Bit name
b0
—
b1
CH0VCH1TE
b2
b3
0
0
0
b0
—
0
Description
R/W
Reserved
This bit is read as 0. The write value should be 0.
R/W
VBATWIO0 Output VBATWIO1 Trigger
Enable
0: VBATT wakeup I/O 0 output trigger by the
VBATWIO1 pin disabled
1: VBATT wakeup I/O 0 output trigger by the
VBATWIO1 pin enabled.
R/W
CH0VCH2TE
VBATWIO0 Output VBATWIO2 Trigger
Enable
0: VBATT wakeup I/O 0 output trigger by the
VBATWIO2 pin disabled
1: VBATT wakeup I/O 0 output trigger by the
VBATWIO2 pin enabled.
R/W
CH0VRTCTE
VBATWIO0 Output RTC Periodic
Signal Enable
0: VBATT wakeup I/O 0 output trigger by the RTC
periodic signal disabled
1: VBATT wakeup I/O 0 output trigger by the RTC
periodic signal enabled.
R/W
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12. Battery Backup Function
b4
CH0VRTCATE
VBATWIO0 Output RTC Alarm Signal
Enable
0: VBATT wakeup I/O 0 output trigger by the RTC
alarm signal disabled
1: VBATT wakeup I/O 0 output trigger by the RTC
alarm signal enabled.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0. R/W
The VBTWCH0OTSR controls the VBATT wakeup I/O 0 output trigger source.
If this register bit is set to 1 and the associated wakeup trigger flag in the VBTWFR register is set, the VBATWIO0 pin
outputs a signal based on the VOUT0LSEL bit in the VBTOCTLR register.
The VBTWCH0OTSR register is initialized by the VBATT_POR signal.
12.2.9
VBATT Wakeup I/O 1 Output Trigger Select Register (VBTWCH1OTSR)
Address(es): SYSTEM.VBTWCH1OTSR 4001 E4B9h
Value after reset:
b7
b6
b5
—
—
—
0
0
0
b4
b3
b2
CH1VR CH1VR CH1VC
TCATE TCTE H2TE
0
0
0
b1
b0
—
CH1VC
H0TE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CH1VCH0TE
VBATWIO1 Output VBATWIO0
Trigger Enable
0: VBATT wakeup I/O 1 output trigger by the VBATWIO0
pin disabled
1: VBATT wakeup I/O 1 output trigger by the VBATWIO0
pin enabled.
R/W
b1
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2
CH1VCH2TE
VBATWIO1 Output VBATWIO2
Trigger Enable
0: VBATT wakeup I/O 1 output trigger by the VBATWIO2
pin disabled
1: VBATT wakeup I/O 1 output trigger by the VBATWIO2
pin enabled.
R/W
b3
CH1VRTCTE
VBATWIO1 Output RTC Periodic
Signal Enable
0: VBATT wakeup I/O 1 output trigger by the RTC periodic
signal disabled
1: VBATT wakeup I/O 1 output trigger by the RTC periodic
signal enabled.
R/W
b4
CH1VRTCATE
VBATWIO1 Output RTC Alarm
Signal Enable
0: VBATT wakeup I/O 1 output trigger by the RTC alarm
signal disabled
1: VBATT wakeup I/O 1 output trigger by the RTC alarm
signal enabled.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The VBTWCH1OTSR controls the VBATT wakeup I/O 1 output trigger source.
If this register bit is set to 1 and the associated wakeup trigger flag in the VBTWFR register is set, VBATWIO1 pin
outputs a signal based on the VOUT1LSEL bit in the VBTOCTLR register.
The VBTWCH1OTSR register is initialized by the VBATT_POR signal.
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12.2.10
12. Battery Backup Function
VBATT Wakeup I/O 2 Output Trigger Select Register (VBTWCH2OTSR)
Address(es): SYSTEM.VBTWCH2OTSR 4001 E4BAh
Value after reset:
b7
b6
b5
—
—
—
0
0
0
b4
b3
CH2VR CH2VR
TCATE TCTE
0
0
b2
—
b1
b0
CH2VC CH2VC
H1TE H0TE
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CH2VCH0TE
VBATWIO2 Output VBATWIO0
Trigger Enable
0: Disable VBATT wakeup I/O 2 output trigger by the
VBATWIO0 pin
1: Enable VBATT wakeup I/O 2 output trigger by the
VBATWIO0 pin.
R/W
b1
CH2VCH1TE
VBATWIO2 Output VBATWIO1
Trigger Enable
0: Disable VBATT wakeup I/O 2 output trigger by the
VBATWIO1 pin
1: Enable VBATT wakeup I/O 2 output trigger by the
VBATWIO1 pin.
R/W
b2
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b3
CH2VRTCTE
VBATWIO2 Output RTC Periodic
Signal Enable
0: Disable VBATT wakeup I/O 2 output trigger by the RTC
periodic signal
1: Enable VBATT wakeup I/O 2 output trigger by the RTC
periodic signal.
R/W
b4
CH2VRTCATE
VBATWIO2 Output RTC Alarm
Signal Enable
0: Disable VBATT wakeup I/O 2 output trigger by the RTC
alarm signal
1: Enable VBATT wakeup I/O 2 output trigger by the RTC
alarm signal.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The VBTWCH2OTSR controls the VBATT wakeup I/O 2 output trigger source.
When this register bit is set to 1 and the associated wakeup trigger flag in the VBTWFR register is set, VBATWIO2 pin
outputs a signal based on the VOUT2LSEL bit in the VBTOCTLR register.
The VBTWCH2OTSR register is initialized by the VBATT_POR signal.
12.2.11
VBATT Input Control Register (VBTICTLR)
Address(es): SYSTEM.VBTICTLR 4001 E4BBh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
VCH2I VCH1I VCH0I
NEN
NEN
NEN
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VCH0INEN
VBATT Wakeup I/O 0 Input Enable
0: Disable VBATWIO0, RTCIC0 inputs
1: Enable VBATWIO0, RTCIC0 inputs.
R/W
b1
VCH1INEN
VBATT Wakeup I/O 1 Input Enable
0: Disable VBATWIO1, RTCIC1 inputs
1: Enable VBATWIO1, RTCIC1 inputs.
R/W
b2
VCH2INEN
VBATT Wakeup I/O 2 Input Enable
0: Disable VBATWIO2 and RTCIC2 inputs
1: Enable VBATWIO2 and RTCIC2 inputs.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The VBTICTLR register selects the VBATT wakeup I/O pins input direction. VBTICTLR is reset by the VBATT_POR
signal.
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12. Battery Backup Function
VCHnINEN bit (VBATT Wakeup I/O n Input Enable) (n = 0 to 2)
The VCHnINEN bit defines the VBATT wakeup I/O pin input enable. You must set the VBTICTLR register when using
only the VBATT wakeup control function but also the time capture function of RTC (RTCICn (n = 0 to 2)). For these
functions, see section 25, Realtime Clock (RTC).
12.2.12
VBATT Output Control Register (VBTOCTLR)
Address(es): SYSTEM.VBTOCTLR 4001 E4BCh
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
VOUT2 VOUT1 VOUT0 VCH2O VCH1O VCH0O
LSEL LSEL LSEL
EN
EN
EN
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VCH0OEN
VBATT Wakeup I/O 0 Output Enable
0: Disable VBATWIO0 output
1: Enable VBATWIO0 output.*1, *2
R/W
b1
VCH1OEN
VBATT Wakeup I/O 1 Output Enable
0: Disable VBATWIO1 output
1: Enable VBATWIO1 output.*1, *2
R/W
b2
VCH2OEN
VBATT Wakeup I/O 2 Output Enable
0: Disable VBATWIO2 output
1: Enable VBATWIO2 output.*1, *2
R/W
b3
VOUT0LSEL
VBATT Wakeup I/O 0 Output Level
Selection
0: Output L before VBATT wakeup trigger
1: Output H before VBATT wakeup trigger.
R/W
b4
VOUT1LSEL
VBATT Wakeup I/O 1 Output Level
Selection
0: Output L before VBATT wakeup trigger
1: Output H before VBATT wakeup trigger.
R/W
b5
VOUT2LSEL
VBATT Wakeup I/O 2 Output Level
Selection
0: Output L before VBATT wakeup trigger
1: Output H before VBATT wakeup trigger.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The VBTOCTLR register selects the VBATT wakeup I/O (VBATWIOn (n = 0 to 2)) pin output direction and output
level. VBTOCTLR is reset by the VBATT_POR signal.
VCHnOEN bit (VBATT Wakeup I/O n Output Enable) (n = 0 to 2)
The VCHnOEN bit defines the VBATT output enable.
Note 1. Only one of these I/O pins can be set as an output pin. Therefore, two out of the three bits must set to 0.
Note 2. When the VCH0OEN bit is set to 1, P402PFS.PMR bit must be 0.
When the VCH1OEN bit is set to 1, P403PFS.PMR bit must be 0.
When the VCH2OEN bit is set to 1, P404PFS.PMR bit must be 0.
VOUTnLSEL bit (VBATT Wakeup I/O n Output Level Selection) (n = 0 to 2)
The VOUTnLSEL bit defines the output level from the VBATT wakeup I/O n pin. When the VOUTnLSEL bit is set to 0,
VBATWIOn pin outputs low before receiving the VBATT wakeup trigger and high after receiving the VBATT wakeup
trigger. When the VOUTnLSEL bit is set to 1, the VBATWIOn pin outputs high before the VBATT wakeup trigger and
low after receiving the VBATT wakeup trigger.
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12.2.13
12. Battery Backup Function
VBATT Wakeup Trigger Source Enable Register (VBTWTER)
Address(es): SYSTEM.VBTWTER 4001 E4BDh
Value after reset:
b7
b6
b5
—
—
—
0
0
0
b4
b3
b2
b1
b0
VRTCA VRTCI VCH2E VCH1E VCH0E
E
E
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VCH0E
VBATWIO0 Pin Enable
0: Disable VBATT wakeup triggered by the VBATWIO0 pin
1: Enable VBATT wakeup triggered by the VBATWIO0 pin.
R/W
b1
VCH1E
VBATWIO1 Pin Enable
0: Disable VBATT wakeup triggered by the VBATWIO1 pin
1: Enable VBATT wakeup triggered by the VBATWIO1 pin.
R/W
b2
VCH2E
VBATWIO2 Pin Enable
0: Disable VBATT wakeup triggered by the VBATWIO2 pin
1: Enable VBATT wakeup triggered by the VBATWIO2 pin.
R/W
b3
VRTCIE
RTC Periodic Signal Enable
0: Disable VBATT wakeup triggered by RTC periodic signal
1: Enable VBATT wakeup triggered by RTC periodic signal.
R/W
b4
VRTCAE
RTC Alarm Signal Enable
0: Disable VBATT wakeup triggered by RTC alarm signal
1: Enable VBATT wakeup triggered by RTC alarm signal.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b5 —
The VBTWTER register enables or disables the VBATT wakeup trigger. VBTWTER is reset by the VBATT_POR
signal.
Multiple trigger source selection is possible.
12.2.14
VBATT Wakeup Trigger Source Edge Register (VBTWEGR)
Address(es): SYSTEM.VBTWEGR 4001 E4BEh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
VCH2E VCH1E VCH0E
G
G
G
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VCH0EG
VBATWIO0 Wakeup Trigger Source Edge
Select
0: Wakeup trigger is generated at a falling edge
1: Wakeup trigger is generated at a rising edge.
R/W
b1
VCH1EG
VBATWIO1 Wakeup Trigger Source Edge
Select
0: Wakeup trigger is generated at a falling edge
1: Wakeup trigger is generated at a rising edge.
R/W
b2
VCH2EG
VBATWIO2 Wakeup Trigger Source Edge
Select
0: Wakeup trigger is generated at a falling edge
1: Wakeup trigger is generated at a rising edge.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b3 —
The VBTWEGR register selects the edge of each VBATT wakeup trigger sources. The VBTWEGR register is reset by
the VBATT_POR signal.
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12.2.15
12. Battery Backup Function
VBATT Wakeup Trigger Source Flag Register (VBTWFR)
Address(es): SYSTEM.VBTWFR 4001 E4BFh
Value after reset:
b7
b6
b5
—
—
—
0
0
0
b4
b3
b2
b1
b0
VRTCA VRTCI VCH2F VCH1F VCH0F
F
F
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VCH0F
VBATWIO0 Wakeup Trigger Flag
0: No wakeup trigger by the VBATWIO0 pin is
generated
1: A wakeup trigger by the VBATWIO0 pin is
generated.
R/(W)*1
b1
VCH1F
VBATWIO1 Wakeup Trigger Flag
0: No wakeup trigger by the VBATWIO1 pin is
generated
1: A wakeup trigger by the VBATWIO1 pin is
generated.
R/(W)*1
b2
VCH2F
VBATWIO2 Wakeup Trigger Flag
0: No wakeup trigger by the VBATWIO2 pin is
generated
1: A wakeup trigger by the VBATWIO2 pin is
generated.
R/(W)*1
b3
VRTCIF
VBATT RTC-Periodic Wakeup Trigger Flag
0: No wakeup trigger by the RTC periodic signal is
generated
1: A wakeup trigger by the RTC periodic signal is
generated.
R/(W)*1
b4
VRTCAF
VBATT RTC-Alarm Wakeup Trigger Flag
0: No wakeup trigger by the RTC alarm signal is
generated
1: A wakeup trigger by the RTC alarm signal is
generated.
R/(W)*1
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note 1.
Only 0 can be written to clear the flag after reading 1.
The VBTWFR register indicates the triggering factor of the VBATT wakeup control function. This register is protected
by the VWEN bit (VBTWCTLR register). VBTWFR is valid 5 PCLKB cycles after writing 1 to VWEN bit enable.
Similarly, disabling VBTWFR takes 5 PCLKB cycles after writing 0 to the VWEN bit.
Each flag is set to 1 when a trigger request specified by VBTWEGR is generated.
The VBTWFR register is initialized by VBATT_POR.
VCHnF flags (VBATT Wakeup I/O n Wakeup Trigger Flag) (n = 0 to 2)
The VCHnF flags indicate that a trigger request by the VBATWIOn pin is generated.
[Setting condition]
A trigger request by the VBATWIOn pin specified by VBTWEGR is generated.
[Clearing condition]
Each bit is read as 1, then written as 0.
VRTCIF flag (VBATT RTC-Periodic Wakeup Trigger Flag)
The VRTCIF flag indicates that a trigger request by the RTC periodic signal is generated.
[Setting condition]
A trigger request by the RTC periodic signal is generated.
[Clearing condition]
This bit is read as 1 and written as 0.
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12. Battery Backup Function
VRTCAF flag (VBATT RTC-Alarm Wakeup Trigger Flag)
The VRTCAF flag indicates that a trigger request by the RTC alarm signal is generated.
[Setting condition]
A trigger request by the RTC alarm signal is generated.
[Clearing condition]
This bit is read as 1 and written as 0.
12.2.16
Backup Register Access Control Register (BKRACR)
Address(es): SYSTEM.BKRACR 4001 E0C6h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
Bit
Symbol
Bit name
b2 to b0
BKRACS[2:0]
Backup Register Access
Cycle Select
b7 to b3
—
Reserved
b1
b0
BKRACS[2:0]
1
1
0
Description
b2
b0
R/W
0 0 0: Access cycle control disable when the system clock
source is SOSC or LOCO
1 1 0: Access cycle control enable.
System clock source is other than SOSC or LOCO.
Other settings are prohibited.
These bits are read as 0. The write value should be 0.
R/W
R/W
The BKRACR register controls the access cycle for the backup register to reduce power consumption. When access
cycle control is enabled (110b), the access cycle for the backup register is 64 times that of when it is disabled (000b).
BKRACR is initialized by all the resets except for VBATT_POR.
[Setting Procedure]
To change the system clock from other than SOSC/LOCO to SOSC/LOCO:
1. Change the SCKSCR.CKSEL[2:0] bits.
2. Change the BKRACR.BKRACS[2:0] bits to 000b.
To change the system clock from SOSC/LOCO to other than SOSC/LOCO:
1. Change the BKRACR.BKRACS[2:0] bits to 110b.
2. Change the SCKSCR.CKSEL[2:0] bits.
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12.3
12. Battery Backup Function
Operation
12.3.1
Battery Backup Function
When the voltage at the VCC pin drops, power can be supplied to the RTC, LOCO, and sub-clock oscillator from the
VBATT pin. When the power supply drop from the VCC pin is detected, the connection to power is switched from the
power supply to the VBATT pin. The power supply from the VCC pin resumes when the voltage at the VCC pin exceeds
VDETBATT. This power supply change does not affect the RTC operation. When the voltage level at the VBATT pin
voltage drops below the operation-guaranteed voltage, it is possible to monitor the VBTBLDF bit in the VBATT Status
Register.
The battery backup function can be used after the voltage monitor 0 reset is enabled.
While VBATT supplies the power, the wakeup control function can toggle the output pin of VBATWIOn (n = 0 to 2) by
triggering the RTC alarm/periodic signal or by the assertion of the VBATWIOn (n = 0 to 2) input signal.
The RTC supports time capture pin detection when the time capture pin input level changes.
The VBATT pin supplies power to the following modules:
RTC
Sub-clock oscillator (including XCIN and XCOUT pins)
VBATWIOn pins (including RTCICn) (n = 0 to 2)
LOCO
VBATT Backup Register
VBATT wakeup controller.
Table 12.2 shows the operating states in VBATT mode.
Table 12.2
Operating states in VBATT mode (1 of 2)
Operating state
VBATT mode
Transition condition
Detection of VCC voltage drop
Canceling method other than reset
Detection of VCC voltage rise
Main clock oscillator
Stopped
Sub-clock oscillator
Operation can be selected in the SOSCCR.SOSTP bit. The status of the oscillator is
the same as before entering VBATT mode.
High-speed on-chip oscillator
Stopped
Middle-speed on-chip oscillator
Stopped
Low-speed on-chip oscillator
Operation or non-operation can be selected in the LOCOCR.LCSTP bit. The status of
the oscillator is the same as before entering VBATT mode.
IWDT-dedicated on-chip oscillator
Stopped
PLL
Stopped
CPU
Stopped (undefined)
SRAM (ECC SRAM included)
Stopped (undefined)
VBATT Backup Register
Stopped (retained)
Flash memory
Stopped (retained)
Realtime Clock (RTC)
Selectable when the selecting clock operates as the count source
AGTn (n = 0, 1)
Stopped (undefined)
Low Voltage Detection (LVD)
Stopped
Power-on reset circuit
Stopped
Battery backup voltage monitor
Operating
Other peripheral modules
Stopped (undefined)
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Table 12.2
12. Battery Backup Function
Operating states in VBATT mode (2 of 2)
Operating state
VBATT mode
I/O ports
RTCICn ports (n = 0 to 2): Operating
Other than the specified ports: Undefined
VBATWIOn ports (n = 0 to 2): Operating.
Note:
Selectable means that operation can be selected in the control register. Some modules are also controlled by the
corresponding module-stop bit.
Stopped (retained) means that the contents of the internal registers are retained but the operations are suspended.
Stopped (undefined) means that the contents of the internal registers are undefined and power to the internal circuit is cut off.
Figure 12.3 shows the switching sequence of the battery backup function.
Power supply from VCC pin is halted
LVD0 detection level
VCC
VCC pin voltage
VBATT pin voltage
VDETBATT*1
VBATT
Reset by LVD0
VCC
Automatically switched
Voltage of backup
power area
VBATT
Power supply from
VCC pin
Power supply from
VBATT pin
Power supply from
VCC pin
Note:
For details on the electrical characteristics, see section 51, Electrical Characteristics.
Note 1. VDETBATT indicates the threshold level of the power supply change between the VCC pin and the
VBATT pin.
Figure 12.3
Switching sequence for the battery backup function
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12.3.2
12. Battery Backup Function
VBATT Battery Power Supply Switch Usage
The battery power supply switch can switch the power supply from the VCC pin to the VBATT pin when the voltage
applied to the VCC pin drops. When the voltage rises, this switch changes the power supply from the VBATT pin to the
VCC pin. The switch is controlled by the VBTCR1.BPWSWSTP bit.
The BPWSWSTP bit can enable the battery power supply switch which can switch the battery backup module supply
voltage from VCC to VBATT when the VCC voltage falls. When the battery power supply switch stops, the battery
backup module power supply is always from VCC. If you are not using the battery backup function, you must write 1 to
this bit.
Note:
Note:
12.3.3
You can use the battery backup function after the voltage monitor 0 reset is enabled (OFS1.LVDAS bit is 0).
Voltage monitor 0 level should be higher than the VDETBATT level (OFS1.VDSEL1[2:0] bits are 000b, 001b, or
010b).
This bit can be set without verifying the VBTSR.VBTRVLD bit status.
VBATT Pin Low Voltage Detection Procedures
The VBTSR.VBTBLDF flag and interrupt can be used to monitor the VBATT pin low voltage detection using the
procedures described in this section.
The following procedure shows how to enable the VBATT pin low voltage detection:
1. Set the voltage monitor 0 reset. See section 8, Low Voltage Detection (LVD).
2. Set the VBTCR1.BPWSWSTP bit to 1 if this bit is being accessed for the first time after a power-on reset.
3. Wait for the VBTSR.VBTRVLD bit to be 1 and ensure that the VBTCR2.VBTLVDEN, VBTLVDICR.VBTLVDIE,
and VBTCMPCR.VBTCMPE bits are 0.
4. Specify the detection voltage in the VBTCR2.VBTLVDLVL[1:0] bits (VBATT pin voltage detect level select).
5. Select the type of interrupt in the VBTLVDICR.VBTLVDISEL bit.
6. Set the VBTCR2.VBTLVDEN bit to 1 for enabling VBATT pin low voltage detection.
7. After waiting for the VBATT comparator operation stabilization time (td_vbat) as described in section 51, Electrical
Characteristics, set the VBTCMPCR.VBTCMPE bit to 1 for the VBATT pin voltage detect circuit to be enabled.
8. Make sure that the VBTSR.VBTBLDF flag is 0, and then set the VBTLVDICR.VBTLVDIE bit to 1 for the
VBATT pin low voltage detection interrupt output to be enabled.
9. Clear the VBTCR1.BPWSWSTP bit to 0 to enable the battery power switch. See section 12.3.2, VBATT Battery
Power Supply Switch Usage.
When the VBATT low voltage is detected, disable the VBATT low voltage detection as shown in Figure 12.4.
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12. Battery Backup Function
VBATT
VDETVBTLVD *1
Cleared by
software
Set by
software
VBTLVDIE
Cleared by
software
VBTCMPE
VBTLVDEN
Cleared by
software
Delay
time
VBTBLDF
Cleared by
software (after 1-read)
Set by
software
> td_vbat
Set by
software
Check
Interrupt
(VBATT_LVD)
Note 1. VDETVBTLVD is VBATT low voltage detect level selected in the VBTCR2.VBTLVDLVL[1:0] bits.
Figure 12.4
Basic operation of VBATT low voltage detection interrupt
The following procedures show how to disable the VBATT pin low voltage detection:
1. Make sure that the VBTSR.VBTRVLD bit is 1.
2. Set the VBTLVDICR.VBTLVDIE bit to 0 to disable the voltage detect interrupt.
3. Set the VBTCMPCR.VBTCMPE bit to 0 for VBATT pin voltage detect circuit output to disable.
4. Set the VBTCR2.VBTLVDEN bit to 0 to disable VBATT pin low voltage output.
5. Modify the setting of bits related to the VBATT pin low voltage detection registers other than
VBTCR2.VBTLVDEN, VBTCMPCR.VBTCMPE, and VBTLVDICR.VBTLVDIE.
12.3.4
VBATT Backup Register Usage
The VBATT Backup Register (VBTBKRn), where n = 0 to 511, can be used to store or restore data as described in the
following procedure:
1. The VBTCR1.BPWSWSTP bit must be set to 1 if this bit is being accessed for the first time after a power-on reset.
2. Wait for the VBTSR.VBTRVLD bit to be 1.
3. VBTBKRn, where n = 0 to 511 can be accessed by an 8-bit read or write operation.
4. Clear the VBTCR1.BPWSWSTP bit to 0 to enable the battery power switch. See section 12.3.2, VBATT Battery
Power Supply Switch Usage.
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12.3.5
12. Battery Backup Function
VBATT Wakeup Control Function Usage
The wakeup control function is a function that can toggle the output pin VBATWIOn (n = 0 to 2) when the RTC alarm/
periodic signal or VBATWIOn (n = 0 to 2) input signal is asserted, when VBATT_R is powered by the VBATT pin.
Note:
The toggle that is triggered by the wakeup control function does not generate an interrupt at the ICU or a reset at
the reset module.
Figure 12.5 shows an example using the VBATT wakeup control function. This example uses the VBATWIO0 port as
the wakeup output port, the RTCIC2 port as the external time capture input capture port, and the VBATWIO2 port as the
external time capture input trigger port. The VBATWIO0 output toggle goes from low to high when the trigger target is
asserted. Trigger source for the wakeup control function is the RTC periodic signal or the VBATWIO2 input rising edge.
Use the following steps to set the VBATT wakeup control function:
1. Set the VBTCR1.BPWSWSTP bit to 1 if this bit is being accessed for the first time after a power-on reset.
2. Wait for the VBTSR.VBTRVLD bit to be 1. Then, be sure that the VBTWCTLR.VWEN bit and the
VBTSR.VBTRDF bit are 0. If these bits are not 0, set them to 0.
3. Specify the VBATWIOn port direction in the VBTICTLR.VCHnINEN and VBTOCTLR.VCHnOEN bits. Set the
VBTOCTLR.VOUTnLSEL bit to 0 or 1 as the output level select (n = 0 to 2).
In this example, use the VBATWIO2/RTCIC2 port as the time capture input, the VBATWIO0 port as wakeup
output port.
Set the following bits to 1:
VBTOCTLR.VCH0OEN
VBTICTLR.VCH2INEN.
In addition, set VBTOCTLR.VOUT0LSEL to 0 as a toggle output from low to high.
4. Set the peripheral module setting as required.
In this example, specify the time capture function for time capture setting with the RTC setting. See section 25,
Realtime Clock (RTC) for details.
5. Select the wakeup trigger source with the VBTWTER register.
In this example, set the VBTWTER.VRTCIE and VBTWTER.VCH2E bits to 1 to select the trigger source as the
RTC periodic signal and VBATWIO2 input trigger.
6. Select the wakeup trigger source edge with the VBTWEGR register.
For example, set the VBTWEGR.VCH2EG bit to 1 to select the VBATWIO2 port as the rising edge trigger.
7. Select the VBATT wakeup output trigger source with the VBTWCHnOTSR register (n = 0 to 2).
In this example, set the VBTWCH0OTSR.CH0VRTCTE and VBTWCH0OTSR.CH0VCH2TE bits to 1.
8. Set the VBTWCTLR.VWEN bit to 1 to activate the VBATT wakeup control function, then set the
VBTCR1.BPWSWSTP bit to 0 to enable the battery power supply switch. After setting the VBTWCTLR.VWEN
bit to 1, the VBATT wakeup control function is enabled.
9. Set the I/O registers to output 0 or 1 to the external power management IC to request stopping of the power supply.
After stopping the power supply, if the RTC periodic signal or the VBATWIO2 input trigger is asserted, the VBATT
wakeup trigger source flag of each event (VBTWFR.VRTCIF or VBTWFR.VCH2F) is set to 1, and the toggle
output is started from low to high on the VBATWIO0 port. The MCU is then supplied power, and it starts up from a
low voltage monitor 0 reset (LVD0). In this example, the external power management IC stops power supply when
it detects a positive transition on the I/O port powered by the VCC pin, and starts to supply power when it detects a
positive transition on the VBATWIO0 port.
The timing diagram of VBATT wakeup function is shown in Figure 12.6.
The following procedures show how to set the registers after the MCU starts up as from a low voltage monitor 0 reset
(LVD0) by the VBATT wakeup trigger.
1. Set the VBTCR1.BPWSWSTP bit to 1.
2. Wait for the VBTSR.VBTRVLD bit to be 1 and be sure that the VBTSR.VBTRDF bit is 0.
3. Check the VBATT wakeup trigger source by reading the VBTWFR register. In the example of Figure 12.6, the
VBTWFR.VRTCIF bit is set to 1.
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12. Battery Backup Function
4. Clear the corresponding bit in the VBTWFR register to 0, then the toggle output is started on the VBATWIOn port
(n = 0 to 2). In the example of Figure 12.6, it is toggled from high to low on the VBATWIO0 port.
5. Set the I/O registers for the power supply stop control signal to output 0 or 1 to the external power management IC
as needed.
6. In case you want to repeat the VBATT wakeup operation, clear the VBTCR1.BPWSWSTP bit to 0 and set the I/O
registers for the power supply stop control signal to output 0 or 1 to the external power management IC so as to
request stopping the power supply again.
In case you want to change the wakeup trigger conditions, clear the VBTWCTLR.VWEN bit to 0, and clear the all
bits in the VBTWTER register before setting other registers associated with VBATT.
MCU
VBATT
Battery
Power supply
Power
management
IC
Wakeup control signal
Power supply stop
control signal
VCC
P402
VBATWIO0 (output)
I/O port powered by VCC pin
RTC
Calendar count
RTCIC2
External time capture event
P404
RTC_PRD
Time capture
VBATWIO2 (input)
VBATT
wakeup
control
Time capture pin
VCC:
VBATT:
VBATWIO0:
VBATWIO2:
RTCIC2:
Figure 12.5
Power supply pin
Backup power pin
VBATT wakeup output port
VBATT wakeup trigger input port
RTC time capture input port
VBATT wakeup control function example application
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12. Battery Backup Function
VCC
VLVH*5
Vdet0*1
VVBATTH*4
VDETBATT*2
VBATT
VVBATPOR*3
P402/VBATWIO0
I/O port powered by VCC pin
(pulled up externally)
Set by
software
RTC periodic wakeup signal
(RTC_PRD)
Clear by
software
Wakeup
trigger
Clear by
software
VBTWFR.VRTCIF
Internal reset signal
(active-low)
tdet*6
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Figure 12.6
12.4
tLVD0*7
Vdet0 is the LVD0 voltage detection level selected in the OFS1.VDSEL1[2:0] bits.
VDETBATT is the voltage level for switching to battery backup.
VVBATPOR is the voltage detection level VBATT power-on reset (VBAT_POR).
VVBATTH is the hysteresis width for switching to battery backup.
VLVH is the hysteresis width of LVD0.
tdet is the response delay time of LVD0.
tLVD0 is the wait time after LVD0 reset cancellation.
VBATT wakeup function timing diagram
Usage Notes
1. When the VBATT pin is not in use, connect the VBATT pin to the VCC pin.
2. When the voltage level on VBATT is lower than the guaranteed operation range, operation of the sub-clock
oscillator and RTC cannot be guaranteed. This voltage drop can be verified in the VBTSR register.
3. If a reset is generated while writing to the registers described in this section, the register values may be lost.
4. During RTC operation powered by the VBATT pin, RTC supports the calendar/binary count operation, the alarm/
periodic trigger for the VBATT wakeup function, and the time capture function.
5. The VBATT wakeup control function can be used only when VBATT_R is powered by VBATT pin.
6. The voltage level on the I/O ports powered by the VCC pin transits to high-impedance when the power supply is
stopped. If these ports are used as the power supply stop control pins for the VBATT wakeup function, these ports
should be pulled up or pulled down externally.
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13. Register Write Protection
13.
Register Write Protection
13.1
Overview
The register write protection function protects important registers from being overwritten because of software errors. The
registers to be protected are set with the Protect Register (PRCR).
Table 13.1 lists the association between the PRCR bits and the registers to be protected.
Table 13.1
Association between PRCR bits and registers to be protected
PRCR bit
Registers to be protected
PRC0
Registers related to the clock generation circuit:
SCKDIVCR, SCKSCR, PLLCR, PLLCCR2, BCKCR, MEMWAIT, MOSCCR, HOCOCR, MOCOCR, CKOCR,
TRCKCR, OSTDCR, OSTDSR, SLCDSCKCR, EBCKOCR, MOCOUTCR, HOCOUTCR, MOSCWTCR, MOMCR,
SOSCCR, SOMCR, LOCOCR, LOCOUTCR, HOCOWTCR, USBCKCR
PRC1
Registers related to the low power modes:
SBYCR, SNZCR, SNZEDCR, SNZREQCR, FLSTOP, PSMCR, OPCCR, SOPCCR, SYOCDCR
Registers related to the battery backup function:
VBTCR1, VBTCR2, VBTSR, VBTCMPCR, VBTLVDICR, VBTWCTLR, VBTWCH0OTSR, VBTWCH1OTSR,
VBTWCH2OTSR, VBTICTLR, VBTOCTLR, VBTWTER, VBTWEGR, VBTWFR, VBTBKRn (n = 0 to 511),
BKRACR
PRC3
Registers related to the LVD:
LVD1CR1, LVD1SR, LVD2CR1, LVD2SR, LVCMPCR, LVDLVLR, LVD1CR0, LVD2CR0
13.2
Register Descriptions
13.2.1
Protect Register (PRCR)
Address(es): SYSTEM.PRCR 4001 E3FEh
b15
b14
b13
b12
b11
b10
b9
b8
PRKEY[7:0]
Value after reset:
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
PRC3
—
PRC1
PRC0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Function
R/W
b0
PRC0
Protect Bit 0
Enables or disables writing to the registers related to the clock generation
circuit:
0: Disable writes
1: Enable writes.
R/W
b1
PRC1
Protect Bit 1
Enables or disables writing to the registers related to the low power
modes and the battery backup function:
0: Disable writes
1: Enable writes.
R/W
b2
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b3
PRC3
Protect Bit 3
Enables or disables writing to the registers related to the LVD:
0: Disable writes
1: Enable writes.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
PRKEY[7:0]
PRC Key Code
Control write access to the PRCR register. To modify the PRCR register,
write A5h to the upper 8 bits and the target value to the lower 8 bits as a
16-bit unit.
W*1
Note 1.
Write data is not saved. Always reads 00h.
PRCn bits (Protect Bit n) (n = 0, 1, 3)
The PRCn bits enable or disable writing to the protected registers as shown in Table 13.1. Setting the PRCn bits to 1 or 0
enables or disables writing, respectively.
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14. Interrupt Controller Unit (ICU)
14.
Interrupt Controller Unit (ICU)
14.1
Overview
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller
(NVIC), Data Transfer Control (DTC), and Direct Memory Access Controller (DMAC) modules. The ICU also controls
non-maskable interrupts. Table 14.1 lists the specifications, Figure 14.1 shows a block diagram, and Table 14.2 lists the I/
O pins.
Table 14.1
ICU specifications
Item
Description
Interrupts
Non-maskable
interrupts*2
Peripheral function interrupts
Interrupts from peripheral modules
Number of sources: 209
External pin interrupts
Interrupt detection on low level*4, falling edge, rising edge, or rising and
falling edges
One of these detection methods can be set for each source.
Digital filter function supported
16 sources, with interrupts from IRQ0 to IRQ15 pins.
DTC/DMAC control
The DTC and DMAC can be activated using interrupt sources*1
Interrupt sources for NVIC
64 sources
NMI pin interrupt
Interrupt from the NMI pin
Interrupt detection on falling edge or rising edge
Digital filter function supported.
Oscillation stop detection interrupt*3
Interrupt on detecting that the main oscillation has stopped
WDT underflow/refresh error*3
Interrupt on an underflow of the down-counter or occurrence of a refresh error
IWDT underflow/refresh error*3
Interrupt on an underflow of the down-counter or occurrence of a refresh error
interrupt*3
Voltage monitor interrupt of Low Voltage Detection Detector 1 (LVD_LVD1)
Voltage monitor 2 interrupt*3
Voltage monitor interrupt of Low Voltage Detection Detector 2 (LVD_LVD2)
VBATT interrupt
Voltage monitor interrupt of VBATT monitor
Voltage monitor 1
RPEST
Interrupt on SRAM parity error
RECCST
Interrupt on SRAM ECC error
BUSSST
Interrupt on MPU bus slave error
BUSMST
Interrupt on MPU bus master error
SPEST
Interrupt on CPU stack pointer monitor
Return from low power mode
Note 1.
Note 2.
Note 3.
Note 4.
Sleep mode: Return is initiated by non-maskable interrupts or any other
interrupt source
Software Standby mode: Return is initiated by non-maskable interrupts.
Interrupt can be selected in the WUPEN register
Snooze mode: Return is initiated by non-maskable interrupts.
Interrupt can be selected in the SELSR0 and WUPEN registers.
See section 14.2.8, SYS Event Link Setting Register (SELSR0) and section
14.2.9, Wake Up Interrupt Enable Register (WUPEN).
For the DTC and DMAC activation sources, see Table 14.4, Event table.
Non-maskable interrupts can be enabled only once after a reset release.
These non-maskable interrupts can also be used as event signals. When used as interrupts, do not change the value of the
NMIER register from the reset state. To enable voltage monitor 1 and voltage monitor 2 interrupts, set the LVD1CR1.IRQSEL
and LVD2CR1.IRQSEL bits to 1. To enable the VBATT monitor interrupt, set the VBTLVDICR.VBTLVDISEL bit to 1.
Low level: Interrupt detection is not canceled if you do not clear it after a detection.
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14. Interrupt Controller Unit (ICU)
Interrupt Controller
CPU stack pointer monitor
MPU bus master error
MPU bus slave error
SRAM ECC error
SRAM parity error
IWDT underflow/refresh error
WDT underflow/refresh error
Oscillation stop detection interrupt
Clock recovery request
Voltage monitor 2 interrupt
NMI
SR
Voltage monitor 1 interrupt
VBATT monitor interrupt
Low voltage detection
Digital
filter
Clock recovery
determination
Detection
Clock recovery enable level
Clock
generation
circuit
CPU
NMI pin
NFCL NFLT
KSEL EN
NMI
MD
NMI
CLR
NMI
ER
WUPEN
Non-maskable interrupt request
Module data bus
IRQ
MD
Digital
filter
Detection
DTCE
Wakeup signal
Canceling Snooze mode
(Generated from the output of SELSR0)
NVIC
IRQ0
IRQ15
FCLK FLT
SEL EN
SELSR0
Peripheral
Module
Interrupt request
IELSRn
Control
Destination switchover
to CPU
DTC activation
request
Interrupt
source
[63:0]
DMAC
DTC
IR
DTC
activation
control
DMAC activation
request
DMAC activation request[3:0]
NFLTEN:
IRQMD:
Figure 14.1
DTC response
Switching the interrupt status and the transfer destination
DELSRn
NMISR:
NMIER:
NMICLR:
NMIMD:
NFCLKSEL:
DTC
Non-Maskable Interrupt Status Register
Non-Maskable Interrupt Enable Register
Non-Maskable Interrupt Status Clear Register
NMI Detection Set (NMICR.NMIMD)
NMI Digital Filter Sampling Clock Select
(NMICR.NFCLKSEL)
NMI Digital Filter Enable (NMICR.NFLTEN)
IRQi Detection Sense Select
(IRQCRi.IRQMD (i = 0 to 15))
FCLKSEL:
FLTEN:
SELSR0:
WUPEN:
IELSRn:
IR:
DTCE:
DELSRn:
DMAC
activation
control
DMAC
DMAC response
IRQi Digital Filter Sampling Clock Select
(IRQCRi.FCLKSEL (i = 0 to 15))
IRQi Digital Filter Enable (IRQCRi.FLTEN (i = 0 to 15))
SYS Event Link Setting Register 0
Wake Up Interrupt Enable Register
ICU Event Link Setting Register (n = 0 to 63)
Interrupt Status Flag (IELSRn.IR)
DTC Activation Enable (IELSRn.DTCE)
DMAC Event Link Setting Register (n = 0 to 3)
ICU block diagram
Table 14.2 lists the ICU input/output pins.
Table 14.2
ICU configuration pins
Pin name
I/O
Description
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ15
Input
External interrupt request pins
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14.2
14. Interrupt Controller Unit (ICU)
Register Descriptions
This chapter does not describe the Arm® NVIC internal registers. For information on these registers, see the ARM®
Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D).
14.2.1
IRQ Control Register i (IRQCRi) (i = 0 to 15)
Address(es): ICU.IRQCR0 4000 6000h, ICU.IRQCR1 4000 6001h, ICU.IRQCR2 4000 6002h, ICU.IRQCR3 4000 6003h,
ICU.IRQCR4 4000 6004h, ICU.IRQCR5 4000 6005h, ICU.IRQCR6 4000 6006h, ICU.IRQCR7 4000 6007h,
ICU.IRQCR8 4000 6008h, ICU.IRQCR9 4000 6009h, ICU.IRQCR10 4000 600Ah, ICU.IRQCR11 4000 600Bh,
ICU.IRQCR12 4000 600Ch, ICU.IRQCR13 4000 600Dh, ICU.IRQCR14 4000 600Eh, ICU.IRQCR15 4000 600Fh
b7
b6
FLTEN
—
0
0
Value after reset:
b5
b4
FCLKSEL[1:0]
0
0
b3
b2
b1
—
—
IRQMD[1:0]
0
0
0
b0
0
Bit
Symbol
Bit name
b1, b0
IRQMD[1:0]
IRQi Detection Sense Select
Description
b3, b2
—
Reserved
b5, b4
FCLKSEL[1:0]
IRQi Digital Filter Sampling Clock
Select
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
FLTEN
IRQi Digital Filter Enable
0: Disable digital filter
1: Enable digital filter.
R/W
b1 b0
0
0
1
1
0:
1:
0:
1:
R/W
R/W
Falling edge
Rising edge
Rising and falling edges
Low level.
These bits are read as 0. The write value should be 0.
b5 b4
0
0
1
1
0:
1:
0:
1:
R/W
R/W
PCLKB
PCLKB/8
PCLKB/32
PCLKB/64.
IRQCRi register changes must satisfy the following conditions:
For a CPU interrupt or DTC trigger:
Change the IRQCRi register setting before setting the target IELSRn (n = 0 to 63).
You can change the register values only when the IELSRn.IELS[7:0] bits are 00h.
For a DMAC trigger:
Change the IRQCRi register setting before setting the target DELSRn (n = 0 to 3).
You can change the register values only when the DELSRn.DELS[7:0] bits are 00h.
For a wakeup enable signal:
Change the IRQCRi register setting before setting the target WUPEN.IRQWUPEN[n] (n = 0 to 15).
You can change the register values only when the target WUPEN.IRQWUPEN[n] is 0.
IRQMD[1:0] bits (IRQi Detection Sense Select)
The IRQMD[1:0] bits set the detection sensing method for the external pin interrupt sources IRQi. For more information
on the settings, see section 14.4.4, External Pin Interrupts.
FCLKSEL[1:0] bits (IRQi Digital Filter Sampling Clock Select)
The FCLKSEL[1:0] bits select the digital filter sampling clock for the external pin interrupt request IRQi, selectable to:
PCLKB (every cycle)
PCLKB/8 (once every 8 cycles)
PCLKB/32 (once every 32 cycles)
PCLKB/64 (once every 64 cycles).
For details on the digital filter, see section 14.4.3, Digital Filter.
FLTEN bit (IRQi Digital Filter Enable)
The FLTEN bit enables the digital filter used for the IRQi external pin interrupt sources. The filter is enabled when the
IRQCRi.FLTEN bit is 1, and disabled when the IRQCRi.FLTEN bit is 0. The IRQi pin level is sampled at the cycle
specified in IRQCRi.FCLKSEL[1:0]. When the sampled level matches three times, the output level from the digital filter
changes. For details on the digital filter, see section 14.4.3, Digital Filter.
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14.2.2
14. Interrupt Controller Unit (ICU)
Non-Maskable Interrupt Status Register (NMISR)
Address(es): ICU.NMISR 4000 6140h
Value after reset:
b15
b14
b13
—
—
—
0
0
0
b12
b11
b10
b9
b8
b7
b6
SPEST BUSMS BUSSS RECCS RPEST NMIST OSTST
T
T
T
0
0
0
0
0
0
0
b5
—
0
b4
b3
b2
b1
b0
VBATT LVD2S LVD1S WDTST IWDTS
ST
T
T
T
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IWDTST
IWDT Underflow/Refresh Error Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b1
WDTST
WDT Underflow/Refresh Error Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b2
LVD1ST
Voltage Monitor 1 Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b3
LVD2ST
Voltage Monitor 2 Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b4
VBATTST
VBATT Monitor Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b5
—
Reserved
This bit is read as 0.
R
b6
OSTST
Oscillation Stop Detection Interrupt Status
Flag
0: Interrupt not requested for main oscillation stop
1: Interrupt requested for main oscillation stop.
R
b7
NMIST
NMI Status Flag
0: NMI pin interrupt not requested
1: NMI pin interrupt requested.
R
b8
RPEST
SRAM Parity Error Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b9
RECCST
SRAM ECC Error Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b10
BUSSST
MPU Bus Slave Error Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b11
BUSMST
MPU Bus Master Error Interrupt Status Flag 0: Interrupt not requested
1: Interrupt requested.
R
b12
SPEST
CPU Stack Pointer Monitor Interrupt Status
Flag
0: Interrupt not requested
1: Interrupt requested.
R
Reserved
These bits are read as 0.
R
b15 to b13 —
The NMISR register monitors the status of non-maskable interrupt sources. Writes to the NMISR register are ignored.
The setting in the Non-Maskable Interrupt Enable Register (NMIER) does not affect the status flags in this register.
Before the end of the non-maskable interrupt handler, check that all of the bits in this register are set to 0 to confirm that
no other NMI requests have occurred during handler processing.
IWDTST flag (IWDT Underflow/Refresh Error Status Flag)
The IWDTST flag indicates an IWDT underflow/refresh error interrupt request. It is read-only and cleared by the
NMICLR.IWDTCLR bit.
[Setting condition]
When an IWDT underflow/refresh error interrupt occurs and this interrupt is enabled.
[Clearing condition]
When 1 is written to the NMICLR.IWDTCLR bit.
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14. Interrupt Controller Unit (ICU)
WDTST flag (WDT Underflow/Refresh Error Status Flag)
The WDTST flag indicates a WDT underflow/refresh error interrupt request. It is read-only and cleared by the
NMICLR.WDTCLR bit.
[Setting condition]
When a WDT underflow/refresh error interrupt occurs.
[Clearing condition]
When 1 is written to the NMICLR.WDTCLR bit.
LVD1ST flag (Voltage Monitor 1 Interrupt Status Flag)
The LVD1ST flag indicates a request for voltage monitor 1 interrupt. It is read-only and cleared by the
NMICLR.LVD1CLR bit.
[Setting condition]
When a voltage monitor 1 interrupt occurs and this interrupt is enabled.
[Clearing condition]
When 1 is written to the NMICLR.LVD1CLR bit.
LVD2ST flag (Voltage Monitor 2 Interrupt Status Flag)
The LVD2ST flag indicates a request for voltage monitor 2 interrupt. It is read-only and cleared by the
NMICLR.LVD2CLR bit.
[Setting condition]
When a voltage monitor 2 interrupt occurs and this interrupt is enabled.
[Clearing condition]
When 1 is written to the NMICLR.LVD2CLR bit.
VBATTST flag (VBATT Monitor Interrupt Status Flag)
The VBATTST flag indicates a VBATT monitor interrupt request. It is read-only and cleared by the
NMICLR.VBATTCLR bit.
[Setting condition]
When a VBATT monitor interrupt occurs.
[Clearing condition]
When 1 is written to the NMICLR.VBATTCLR bit.
OSTST flag (Oscillation Stop Detection Interrupt Status Flag)
The OSTST flag indicates a main oscillation stop detection interrupt request. It is read-only and cleared by the
NMICLR.OSTCLR bit.
[Setting condition]
When an oscillation stop detection interrupt occurs.
[Clearing condition]
When 1 is written to the NMICLR.OSTCLR bit.
NMIST flag (NMI Status Flag)
The NMIST flag indicates an NMI pin interrupt request. It is read-only and cleared by the NMICLR.NMICLR bit.
[Setting condition]
When an edge specified by the NMICR.NMIMD bit is input to the NMI pin.
[Clearing condition]
When 1 is written to the NMICLR.NMICLR bit.
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14. Interrupt Controller Unit (ICU)
RPEST flag (SRAM Parity Error Interrupt Status Flag)
The RPEST flag indicates an SRAM parity error interrupt request.
[Setting condition]
When an interrupt occurs in response to an SRAM parity error.
[Clearing condition]
When 1 is written to the NMICLR.RPECLR bit.
RECCST flag (SRAM ECC Error Interrupt Status Flag)
The RECCST flag indicates an SRAM ECC error interrupt request.
[Setting condition]
When an interrupt occurs in response to an SRAM ECC error.
[Clearing condition]
When 1 is written to the NMICLR.RECCCLR bit.
BUSSST flag (MPU Bus Slave Error Interrupt Status Flag)
The BUSSST flag indicates a bus slave error interrupt request.
[Setting condition]
When an interrupt occurs in response to a bus slave error.
[Clearing condition]
When 1 is written to the NMICLR.BUSSCLR bit.
BUSMST flag (MPU Bus Master Error Interrupt Status Flag)
The BUSMST flag indicates a bus master error interrupt request.
[Setting condition]
When an interrupt occurs in response to a bus master error.
[Clearing condition]
When 1 is written to the NMICLR.BUSMCLR bit.
SPEST flag (CPU Stack Pointer Monitor Interrupt Status Flag)
The SPEST flag indicates a CPU stack pointer monitor interrupt request.
[Setting condition]
When an interrupt occurs in response to a CPU stack pointer monitor.
[Clearing condition]
When 1 is written to the NMICLR.SPECLR bit.
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14.2.3
14. Interrupt Controller Unit (ICU)
Non-Maskable Interrupt Enable Register (NMIER)
Address(es): ICU.NMIER 4000 6120h
Value after reset:
b15
b14
b13
—
—
—
0
0
0
b12
b11
b10
b9
b8
b7
b6
SPEEN BUSME BUSSE RECCE RPEEN NMIEN OSTEN
N
N
N
0
0
0
0
0
0
0
b5
—
0
b4
b3
b2
b1
b0
VBATT LVD2E LVD1E WDTE IWDTE
EN
N
N
N
N
0
0
0
0
Bit
Symbol
Bit name
b0
IWDTEN
IWDT Underflow/Refresh Error Interrupt Enable 0: Disabled
1: Enabled.
R/(W)
WDT Underflow/Refresh Error Interrupt Enable
0: Disabled
1: Enabled.
R/(W)
0: Disabled
1: Enabled.
R/(W)
0: Disabled
1: Enabled.
R/(W)
0: Disabled
1: Enabled.
R/(W)
b1
b2
b3
b4
WDTEN
LVD1EN
LVD2EN
VBATTEN
Voltage Monitor 1 Interrupt Enable
Voltage Monitor 2 Interrupt Enable
VBATT Monitor Interrupt Enable
Description
0
R/W
*1, *2
*1, *2
*1, *2
*1, *2
*1, *2
b5
―
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
OSTEN
Oscillation Stop Detection Interrupt Enable
0: Disabled
1: Enabled.
R/(W)
0: Disabled
1: Enabled.
R/(W)
0: Disabled
1: Enabled.
R/(W)
0: Disabled
1: Enabled.
R/(W)
b7
b8
b9
b10
b11
b12
NMIEN
RPEEN
RECCEN
BUSSEN
BUSMEN
SPEEN
b15 to b13 ―
Note 1.
Note 2.
NMI Pin Interrupt Enable
SRAM Parity Error Interrupt Enable
SRAM ECC Error Interrupt Enable
MPU Bus Slave Error Interrupt Enable
MPU Bus Master Error Interrupt Enable
CPU Stack Pointer Monitor Interrupt Enable
Reserved
*1, *2
*1
*1, *2
*1, *2
0: Disabled
1: Enabled.
R/(W)
*1, *2
0: Disabled
1: Enabled.
R/(W)
0: Disabled
1: Enabled.
R/(W)
These bits are read as 0. The write value should
be 0.
R/W
*1, *2
*1, *2
You can write 1 to this bit only after reset, and subsequent write accesses are invalid. Writing 0 to this bit is invalid.
Do not write 1 to this bit when the source is used as an event signal.
IWDTEN bit (IWDT Underflow/Refresh Error Interrupt Enable)
The IWDTEN bit enables or disables IWDT underflow/refresh error interrupt as an NMI trigger.
WDTEN bit (WDT Underflow/Refresh Error Interrupt Enable)
The WDTEN bit enables or disables WDT underflow/refresh error interrupt as an NMI trigger.
LVD1EN bit (Voltage Monitor 1 Interrupt Enable)
The LVD1EN bit enables or disables voltage monitor 1 interrupt as an NMI trigger.
LVD2EN bit (Voltage Monitor 2 Interrupt Enable)
The LVD2EN bit enables or disables voltage monitor 2 interrupt as an NMI trigger.
VBATTEN bit (VBATT Monitor Interrupt Enable)
The VBATTEN bit enables or disables VBATT monitor interrupt as an NMI trigger.
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14. Interrupt Controller Unit (ICU)
OSTEN bit (Oscillation Stop Detection Interrupt Enable)
The OSTEN bit enables or disables main oscillation stop detection interrupt as an NMI trigger.
NMIEN bit (NMI Pin Interrupt Enable)
The NMIEN bit enables or disables NMI pin interrupt as an NMI trigger.
RPEEN bit (SRAM Parity Error Interrupt Enable)
The RPEEN bit enables or disables SRAM parity error interrupt as an NMI trigger.
RECCEN bit (SRAM ECC Error Interrupt Enable)
The RECCEN bit enables or disables SRAM ECC error interrupt as an NMI trigger.
BUSSEN bit (MPU Bus Slave Error Interrupt Enable)
The BUSSEN bit enables or disables bus slave error interrupt as an NMI trigger.
BUSMEN bit (MPU Bus Master Error Interrupt Enable)
The BUSMEN bit enables or disables bus master error interrupt as an NMI trigger.
SPEEN bit (CPU Stack Pointer Monitor Interrupt Enable)
The SPEEN bit enables or disables CPU stack pointer monitor interrupt as an NMI trigger.
14.2.4
Non-Maskable Interrupt Status Clear Register (NMICLR)
Address(es): ICU.NMICLR 4000 6130h
b15
b14
b13
—
—
—
0
0
0
Value after reset:
b12
b11
b10
b9
b8
b7
b6
SPECL BUSM BUSSC RECCC RPECL NMICL OSTCL
R
CLR
LR
LR
R
R
R
0
0
0
0
0
0
0
b5
—
b4
b3
b2
b1
b0
VBATT LVD2C LVD1C WDTCL IWDTC
CLR
LR
LR
R
LR
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IWDTCLR
IWDT Clear
0: No effect
1: Clear the NMISR.IWDTST flag.
R/(W)*1
b1
WDTCLR
WDT Clear
0: No effect
1: Clear the NMISR.WDTST flag.
R/(W)*1
b2
LVD1CLR
LVD1 Clear
0: No effect
1: Clear the NMISR.LVD1ST flag.
R/(W)*1
b3
LVD2CLR
LVD2 Clear
0: No effect
1: Clear the NMISR.LVD2ST flag.
R/(W)*1
b4
VBATTCLR
VBATT Clear
0: No effect
1: Clear the NMISR.VBATTST flag.
R/(W)*1
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
OSTCLR
OST Clear
0: No effect
1: Clear the NMISR.OSTST flag.
R/(W)*1
b7
NMICLR
NMI Clear
0: No effect
1: Clear the NMISR.NMIST flag.
R/(W)*1
b8
RPECLR
SRAM Parity Error Clear
0: No effect
1: Clear the NMISR.RPEST flag.
R/(W)*1
b9
RECCCLR
SRAM ECC Error Clear
0: No effect
1: Clear the NMISR.RECCST flag.
R/(W)*1
b10
BUSSCLR
Bus Slave Error Clear
0: No effect
1: Clear the NMISR.BUSSST flag.
R/(W)*1
b11
BUSMCLR
Bus Master Error Clear
0: No effect
1: Clear the NMISR.BUSMST flag.
R/(W)*1
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14. Interrupt Controller Unit (ICU)
Bit
Symbol
Bit name
Description
R/W
b12
SPECLR
CPU Stack Pointer Monitor Interrupt
Clear
0: No effect.
1: Clear the NMISR.SPEST flag.
R/(W)*1
b15 to b13
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Only 1 can be written to this bit.
IWDTCLR bit (IWDT Clear)
Writing 1 to the IWDTCLR bit clears the NMISR.IWDTST flag. The IWDTCLR bit is read as 0.
WDTCLR bit (WDT Clear)
Writing 1 to the WDTCLR bit clears the NMISR.WDTST flag. The WDTCLR bit is read as 0.
LVD1CLR bit (LVD1 Clear)
Writing 1 to the LVD1CLR bit clears the NMISR.LVD1ST flag. The LVD1CLR bit is read as 0.
LVD2CLR bit (LVD2 Clear)
Writing 1 to the LVD2CLR bit clears the NMISR.LVD2ST flag. The LVD2CLR bit is read as 0.
VBATTCLR bit (VBATT Clear)
Writing 1 to the VBATTCLR clears the NMISR.VBATTST flag. The VBATTCLR bit is read as 0.
OSTCLR bit (OST Clear)
Writing 1 to the OSTCLR bit clears the NMISR.OSTST flag. The OSTCLR bit is read as 0.
NMICLR bit (NMI Clear)
Writing 1 to the NMICLR bit clears the NMISR.NMIST flag. The NMICLR bit is read as 0.
RPECLR bit (SRAM Parity Error Clear)
Writing 1 to the RPECLR clears the NMISR.RPEST flag. The RPECLR bit is read as 0.
RECCCLR bit (SRAM ECC Error Clear)
Writing 1 to the RECCCLR bit clears the NMISR.RECCST flag. The RECCCLR bit is read as 0.
BUSSCLR bit (Bus Slave Error Clear)
Writing 1 to the BUSSCLR clears the NMISR.BUSSST flag. The BUSSCLR bit is read as 0.
BUSMCLR bit (Bus Master Error Clear)
Writing 1 to the BUSMCLR bit clears the NMISR.BUSMSST flag. The BUSMCLR bit is read as 0.
SPECLR bit (CPU Stack Pointer Monitor Interrupt Clear)
Writing 1 to the SPECLR bit clears the NMISR.SPEST flag. The SPECLR bit is read as 0.
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14.2.5
14. Interrupt Controller Unit (ICU)
NMI Pin Interrupt Control Register (NMICR)
Address(es): ICU.NMICR 4000 6100h
b7
b6
NFLTE
N
—
0
0
Value after reset:
b5
b4
NFCLKSEL[1:0]
0
0
b3
b2
b1
b0
—
—
—
NMIMD
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
NMIMD
NMI Detection Set
0: Falling edge
1: Rising edge.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b5, b4
NFCLKSEL[1:0]
NMI Digital Filter Sampling Clock
Select
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
NFLTEN
NMI Digital Filter Enable
0: Disable digital filter
1: Enable digital filter.
R/W
b5 b4
0
0
1
1
0:
1:
0:
1:
R/W
PCLKB
PCLKB/8
PCLKB/32
PCLKB/64.
Change the NMICR register settings before enabling NMI pin interrupt, before setting NMIER.NMIEN to 1.
NMIMD bit (NMI Detection Set)
The NMIMD bit selects the detection sensing method for the NMI pin interrupts.
NFCLKSEL[1:0] bits (NMI Digital Filter Sampling Clock Select)
The NFCLKSEL[1:0] bits select the digital filter sampling clock for NMI pin interrupts, selectable to:
PCLKB (every cycle)
PCLKB/8 (once every 8 cycles)
PCLKB/32 (once every 32 cycles)
PCLKB/64 (once every 64 cycles).
For the digital filter details, see section 14.4.3, Digital Filter.
NFLTEN bit (NMI Digital Filter Enable)
The NFLTEN bit enables the digital filter used for NMI pin interrupts. The filter is enabled when NFLTEN is 1 and
disabled when NFLTEN is 0. The NMI pin level is sampled at the clock cycle specified in NMIFLTC.NFCLKSEL[1:0].
When the sampled level matches three times, the output level from the digital filter changes. For details on the digital
filter, see section 14.4.3, Digital Filter.
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14.2.6
14. Interrupt Controller Unit (ICU)
ICU Event Link Setting Register n (IELSRn)
Address(es): ICU.IELSR0 4000 6300h, ICU.IELSR1 4000 6304h, ICU.IELSR2 4000 6308h, ICU.IELSR3 4000 630Ch……
……ICU.IELSR60 4000 63F0h, ICU.IELSR61 4000 63F4h, ICU.IELSR62 4000 63F8h, ICU.IELSR63 4000 63FCh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
DTCE
—
—
—
—
—
—
—
IR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
IELS[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
IELS[7:0]
ICU Event Link Select
b7
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
IR
Interrupt Status Flag
0: No interrupt request occurred
1: An interrupt request occurred.
R/(W)
These bits are read as 0. The write value should be 0.
R/W
b0
00000000:
00000001 to 11011001:
R/W
Disable interrupts to the associated NVIC/DTC
Event signal number to be linked. For details,
see Table 14.4.
R/W
*1
b23 to b17
—
Reserved
b24
DTCE
DTC Activation Enable 0: Disable DTC activation
1: Enable DTC activation.
R/W
b31 to b25
—
Reserved
R/W
Note:
Note 1.
These bits are read as 0. The write value should be 0.
This register requires halfword or word access.
Writing 1 to the IR flag is prohibited.
The IELSRn register selects the IRQ source used by NVIC. For details, see Table 14.4, Event table.
IELSRn, where n = 0 to 63, corresponds to the NVIC IRQ input source numbers 0 to 63.
IELS[7:0] bits (ICU Event Link Select)
The IELS[7:0] bits link an event signal to the associated NVIC/DTC module.
IR flag (Interrupt Status Flag)
The IR flag indicates an individual interrupt request from the event specified in IELS[7:0].
[Setting condition]
When an interrupt request is received from the associated peripheral module or IRQi pin.
[Clearing conditions]
When 0 is written to the flag. DTCE must be set to 0 before writing 0 to the IR flag.
To clear the IR flag:
1. Negate the input interrupt signal.
2. Read the peripheral once and wait for 2 clock cycles of the target module clock.
3. Clear the IR flag by writing 0.
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14. Interrupt Controller Unit (ICU)
DTCE bit (DTC Activation Enable)
When the DTCE bit is set to 1, the associated event is selected as the source for DTC activation.
[Setting condition]
When 1 is written to the DTCE bit.
[Clearing conditions]
When the specified number of transfers is complete. For chain transfers, when the specified number of transfers for
the last chain transfer is complete
When 0 is written to the bit.
14.2.7
DMAC Event Link Setting Register n (DELSRn)
Address(es): ICU.DELSR0 4000 6280h, ICU.DELSR1 4000 6284h, ICU.DELSR2 4000 6288h, ICU.DELSR3 4000 628Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
DELS[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
DELS[7:0]
DMAC Event Link Select
b7
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
IR
Interrupt Status Flag for DMAC
0: No interrupt request is generated
1: An interrupt request is generated.
R/W*1
b31 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Note 1.
b0
00000000:
Disable DMA start request to the
associated DMAC module.
00000001 to 11011001:
Event signal number to be linked.
Other settings are prohibited. For details, see Table 14.4,
Event table.
This register requires halfword or word access.
Writing 1 to the IR flag is prohibited.
DELS[7:0] bits (DMAC Event Link Select)
The DELS[7:0] bits link an event signal for the DMAC module.
IR flag (Interrupt Status Flag for DMAC)
The IR flag indicates the status of an individual DMA transfer request. This flag corresponds to the DELS[7:0] bits of the
same register.
[Setting condition]
The flag is set to 1 when a DMA transfer request is generated from the corresponding peripheral module or IRQi
pin.
[Clearing conditions]
When 0 is written to the flag
At the start of a DMA transfer after the DMA transfer request is issued.
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14.2.8
14. Interrupt Controller Unit (ICU)
SYS Event Link Setting Register (SELSR0)
Address(es): ICU.SELSR0 4000 6200h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
SELS[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
SELS[7:0]
SYS Event Link Select
b7
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
b0
00000000:
Disable event output to the
associated low power mode module
00000001 to 11011001:
Event signal number to be linked.
Other settings are prohibited. For details, see Table 14.4, Event
table.
R/W
The SELSR0 register selects the events that wake up the CPU from Snooze mode. You can only use the events listed in
Table 14.4 checked as “Canceling Snooze using SELSR0”. Events specified in this register are defined as
ICU_SNZCANCEL (017h) in Table 14.4. When 017h is set in IELSRn.IELS, an SELSR0 event interrupt occurs.
14.2.9
Wake Up Interrupt Enable Register (WUPEN)
Address(es): ICU.WUPEN 4000 61A0h
b31
b30
b29
b28
b27
IIC0WU AGT1C AGT1C AGT1U USBFS
PEN BWUP AWUP DWUP WUPE
N
EN
EN
EN
Value after reset:
b26
—
b25
b24
b23
RTCPR RTCAL ACMPL
DWUP MWUP P0WUP
EN
EN
EN
b22
b21
—
—
b20
b19
b18
b17
b16
VBATT LVD2W LVD1W KEYW IWDTW
WUPE UPEN UPEN UPEN UPEN
N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
IRQWUPEN[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
IRQWUPEN[15:0]
IRQ Interrupt Software
Standby Returns Enable
0: Disable software standby returns by IRQ interrupt
1: Enable software standby returns by IRQ interrupt.
R/W
b16
IWDTWUPEN
IWDT Interrupt Software
Standby Returns Enable
0: Disable software standby returns by IWDT interrupt
1: Enable software standby returns by IWDT interrupt.
R/W
b17
KEYWUPEN
Key Interrupt Software
Standby Returns Enable
0: Disable software standby returns by KEY interrupt
1: Enable software standby returns by KEY interrupt.
R/W
b18
LVD1WUPEN
LVD1 Interrupt Software
Standby Returns Enable
0: Disable software standby returns by LVD1 interrupt
1: Enable software standby returns by LVD1 interrupt.
R/W
b19
LVD2WUPEN
LVD2 Interrupt Software
Standby Returns Enable
0: Disable software standby returns by LVD2 interrupt
1: Enable software standby returns by LVD2 interrupt.
R/W
b20
VBATTWUPEN
VBATT Monitor Interrupt
Software Standby Returns
Enable
0: Disable software standby returns by VBATT monitor
interrupt
1: Enable software standby returns by VBATT monitor
interrupt.
R/W
b22, b21
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b23
ACMPLP0WUPEN
ACMPLP0 Interrupt
Software Standby Returns
Enable
0: Disable software standby returns by ACMPLP0
interrupt
1: Enable software standby returns by ACMPLP0
interrupt.
R/W
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14. Interrupt Controller Unit (ICU)
Bit
Symbol
Bit name
Description
R/W
b24
RTCALMWUPEN
RTC Alarm Interrupt
Software Standby Returns
Enable
0: Disable software standby returns by RTC alarm
interrupt
1: Enable software standby returns by RTC alarm
interrupt.
R/W
b25
RTCPRDWUPEN
RTC Period Interrupt
Software Standby Returns
Enable
0: Disable software standby returns by RTC period
interrupt
1: Enable software standby returns by RTC period
interrupt.
R/W
b26
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b27
USBFSWUPEN
USBFS Interrupt Software
Standby Returns Enable
0: Disable software standby returns by USBFS interrupt
1: Enable software standby returns by USBFS interrupt.
R/W
b28
AGT1UDWUPEN
AGT1 Underflow Interrupt
Software Standby Returns
Enable
0: Disable software standby returns by AGT1 underflow
interrupt
1: Enable software standby returns by AGT1 underflow
interrupt.
R/W
b29
AGT1CAWUPEN
AGT1 Compare Match A
Interrupt Software Standby
Returns Enable
0: Disable software standby returns by AGT1 compare
match A interrupt
1: Enable software standby returns by AGT1 compare
match A interrupt.
R/W
b30
AGT1CBWUPEN
AGT1 Compare Match B
Interrupt Software Standby
Returns Enable
0: Disable software standby returns by AGT1 compare
match B interrupt
1: Enable software standby returns by AGT1 compare
match B interrupt.
R/W
b31
IIC0WUPEN
IIC0 Address Match
Interrupt Software Standby
Returns Enable
0: Disable software standby returns by IIC0 address
match interrupt
1: Enable software standby returns by IIC0 address
match interrupt.
R/W
The bits in this register control whether the associated interrupt can wake up the CPU from Software Standby mode.
IRQWUPEN[15:0] bits (IRQ Interrupt Software Standby Returns Enable)
The IRQWUPEN[15:0] bits enable the use of IRQn interrupts to cancel Software Standby mode.
IWDTWUPEN bit (IWDT Interrupt Software Standby Returns Enable)
The IWDTWUPEN bit enables the use of IWDT interrupts to cancel Software Standby mode.
KEYWUPEN bit (Key Interrupt Software Standby Returns Enable)
The KEYWUPEN bit enables the use of Key interrupts to cancel Software Standby mode.
LVD1WUPEN bit (LVD1 Interrupt Software Standby Returns Enable)
The LVD1WUPEN bit enables the use of LVD1 interrupts to cancel Software Standby mode.
LVD2WUPEN bit (LVD2 Interrupt Software Standby Returns Enable)
The LVD2WUPEN bit enables the use of LVD2 interrupts to cancel Software Standby mode.
VBATTWUPEN bit (VBATT Monitor Interrupt Software Standby Returns Enable)
The VBATTWUPEN bit enables the use of VBATT monitor interrupts to cancel Software Standby mode.
ACMPLP0WUPEN bit (ACMPLP0 Interrupt Software Standby Returns Enable)
The ACMPLP0WUPEN bit enables the use of ACMPLP0 interrupts to cancel Software Standby mode.
RTCALMWUPEN bit (RTC Alarm Interrupt Software Standby Returns Enable)
The RTCALMWUPEN bit enables the use of RTC alarm interrupts to cancel Software Standby mode.
RTCPRDWUPEN bit (RTC Period Interrupt Software Standby Returns Enable)
The RTCPRDWUPEN bit enables the use of RTC period interrupts to cancel Software Standby mode.
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14. Interrupt Controller Unit (ICU)
USBFSWUPEN bit (USBFS Interrupt Software Standby Returns Enable)
The USBFSWUPEN bit enables the use of USBFS interrupts to cancel Software Standby mode.
AGT1UDWUPEN bit (AGT1 Underflow Interrupt Software Standby Returns Enable)
The AGT1UDWUPEN bit enables the use of AGT1 underflow interrupts to cancel Software Standby mode.
AGT1CAWUPEN bit (AGT1 Compare Match A Interrupt Software Standby Returns Enable)
The AGT1CAWUPEN bit enables the use of AGT1 compare match A interrupts to cancel Software Standby mode.
AGT1CBWUPEN bit (AGT1 Compare Match B Interrupt Software Standby Returns Enable)
The AGT1CBWUPEN bit enables the use of AGT1 compare match B interrupts to cancel Software Standby mode.
IIC0WUPEN bit (IIC0 Address Match Interrupt Software Standby Returns Enable)
The IIC0WUPEN bit enables the use of IIC0 interrupts to cancel Software Standby mode.
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14.3
14. Interrupt Controller Unit (ICU)
Vector Table
The ICU detects maskable and non-maskable interrupts. Interrupt priorities are set up in the Arm NVIC. For information
on these registers, see the NVIC chapter of the ARM® Cortex®-M4 Processor Technical Reference Manual (ARM DDI
0439D).
14.3.1
Interrupt Vector Table
Table 14.3 describes the interrupt vector table. The interrupt vector addresses conform to the NVIC specifications.
Table 14.3
Interrupt vector table (1 of 2)
Exception
number
IRQ number
Vector offset Source
Description
0
-
000h
Arm
Initial stack pointer
1
-
004h
Arm
Initial program counter (reset vector)
2
-
008h
Arm
Non-Maskable Interrupt (NMI)
3
-
00Ch
Arm
Hard fault
4
-
010h
Arm
MemManage fault
5
-
014h
Arm
Bus fault
6
-
018h
Arm
Usage fault
7
-
01Ch
Arm
Reserved
8
-
020h
Arm
Reserved
9
-
024h
Arm
Reserved
10
-
028h
Arm
Reserved
11
-
02Ch
Arm
Supervisor Call (SVCall)
12
-
030h
Arm
Debug monitor
13
-
034h
Arm
Reserved
14
-
038h
Arm
Pendable request for system service (PendableSrvReq)
15
-
03Ch
Arm
System tick timer (SysTick)
16
0
040h
ICU.IELSR0
Event selected in the ICU.IELSR0 register
17
1
044h
ICU.IELSR1
Event selected in the ICU.IELSR1 register
18
2
048h
ICU.IELSR2
Event selected in the ICU.IELSR2 register
19
3
04Ch
ICU.IELSR3
Event selected in the ICU.IELSR3 register
20
4
050h
ICU.IELSR4
Event selected in the ICU.IELSR4 register
21
5
054h
ICU.IELSR5
Event selected in the ICU.IELSR5 register
22
6
058h
ICU.IELSR6
Event selected in the ICU.IELSR6 register
23
7
05Ch
ICU.IELSR7
Event selected in the ICU.IELSR7 register
24
8
060h
ICU.IELSR8
Event selected in the ICU.IELSR8 register
25
9
064h
ICU.IELSR9
Event selected in the ICU.IELSR9 register
26
10
068h
ICU.IELSR10
Event selected in the ICU.IELSR10 register
27
11
06Ch
ICU.IELSR11
Event selected in the ICU.IELSR11 register
28
12
070h
ICU.IELSR12
Event selected in the ICU.IELSR12 register
29
13
074h
ICU.IELSR13
Event selected in the ICU.IELSR13 register
30
14
078h
ICU.IELSR14
Event selected in the ICU.IELSR14 register
31
15
07Ch
ICU.IELSR15
Event selected in the ICU.IELSR15 register
32
16
080h
ICU.IELSR16
Event selected in the ICU.IELSR16 register
33
17
084h
ICU.IELSR17
Event selected in the ICU.IELSR17 register
34
18
088h
ICU.IELSR18
Event selected in the ICU.IELSR18 register
35
19
08Ch
ICU.IELSR19
Event selected in the ICU.IELSR19 register
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Table 14.3
14. Interrupt Controller Unit (ICU)
Interrupt vector table (2 of 2)
Exception
number
IRQ number
Vector offset Source
Description
36
20
090h
ICU.IELSR20
Event selected in the ICU.IELSR20 register
37
21
094h
ICU.IELSR21
Event selected in the ICU.IELSR21 register
38
22
098h
ICU.IELSR22
Event selected in the ICU.IELSR22 register
39
23
09Ch
ICU.IELSR23
Event selected in the ICU.IELSR23 register
40
24
0A0h
ICU.IELSR24
Event selected in the ICU.IELSR24 register
41
25
0A4h
ICU.IELSR25
Event selected in the ICU.IELSR25 register
42
26
0A8h
ICU.IELSR26
Event selected in the ICU.IELSR26 register
43
27
0ACh
ICU.IELSR27
Event selected in the ICU.IELSR27 register
44
28
0B0h
ICU.IELSR28
Event selected in the ICU.IELSR28 register
45
29
0B4h
ICU.IELSR29
Event selected in the ICU.IELSR29 register
46
30
0B8h
ICU.IELSR30
Event selected in the ICU.IELSR30 register
47
31
0BCh
ICU.IELSR31
Event selected in the ICU.IELSR31 register
48
32
0C0h
ICU.IELSR32
Event selected in the ICU.IELSR32 register
49
33
0C4h
ICU.IELSR33
Event selected in the ICU.IELSR33 register
50
34
0C8h
ICU.IELSR34
Event selected in the ICU.IELSR34 register
51
35
0CCh
ICU.IELSR35
Event selected in the ICU.IELSR35 register
52
36
0D0h
ICU.IELSR36
Event selected in the ICU.IELSR36 register
53
37
0D4h
ICU.IELSR37
Event selected in the ICU.IELSR37 register
54
38
0D8h
ICU.IELSR38
Event selected in the ICU.IELSR38 register
55
39
0DCh
ICU.IELSR39
Event selected in the ICU.IELSR39 register
56
40
0E0h
ICU.IELSR40
Event selected in the ICU.IELSR40 register
57
41
0E4h
ICU.IELSR41
Event selected in the ICU.IELSR41 register
58
42
0E8h
ICU.IELSR42
Event selected in the ICU.IELSR42 register
59
43
0ECh
ICU.IELSR43
Event selected in the ICU.IELSR43 register
60
44
0F0h
ICU.IELSR44
Event selected in the ICU.IELSR44 register
61
45
0F4h
ICU.IELSR45
Event selected in the ICU.IELSR45 register
62
46
0F8h
ICU.IELSR46
Event selected in the ICU.IELSR46 register
63
47
0FCh
ICU.IELSR47
Event selected in the ICU.IELSR47 register
64
48
100h
ICU.IELSR48
Event selected in the ICU.IELSR48 register
65
49
104h
ICU.IELSR49
Event selected in the ICU.IELSR49 register
66
50
108h
ICU.IELSR50
Event selected in the ICU.IELSR50 register
67
51
10Ch
ICU.IELSR51
Event selected in the ICU.IELSR51 register
68
52
110h
ICU.IELSR52
Event selected in the ICU.IELSR52 register
69
53
114h
ICU.IELSR53
Event selected in the ICU.IELSR53 register
70
54
118h
ICU.IELSR54
Event selected in the ICU.IELSR54 register
71
55
11Ch
ICU.IELSR55
Event selected in the ICU.IELSR55 register
72
56
120h
ICU.IELSR56
Event selected in the ICU.IELSR56 register
73
57
124h
ICU.IELSR57
Event selected in the ICU.IELSR57 register
74
58
128h
ICU.IELSR58
Event selected in the ICU.IELSR58 register
75
59
12Ch
ICU.IELSR59
Event selected in the ICU.IELSR59 register
76
60
130h
ICU.IELSR60
Event selected in the ICU.IELSR60 register
77
61
134h
ICU.IELSR61
Event selected in the ICU.IELSR61 register
78
62
138h
ICU.IELSR62
Event selected in the ICU.IELSR62 register
79
63
13Ch
ICU.IELSR63
Event selected in the ICU.IELSR63 register
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14.3.2
14. Interrupt Controller Unit (ICU)
Event Number
The following table lists heading details for Table 14.4, which describes each event number.
Heading
Description
Interrupt request source
Name of the source generating the interrupt request
Name
Name of the interrupt
Form of interrupt detection (signal)
“Edge” or “level” as the method for detection of the interrupt.
“” indicates usability as an NMI interrupt
Connect to NVIC
“” indicates that the interrupt can be used as a CPU interrupt (IELSRn setting)
Invoke DTC
“” indicates that the interrupt can be used to request DTC activation (IELSRn setting)
Invoke DMAC
“” indicates that the interrupt can be used to request DMAC activation (DELSRn setting)
Canceling Snooze mode
“” indicates that the interrupt can be used to request a return from Snooze mode using
SELSR0. Otherwise, “” indicates that it can be used directly.
Canceling Software Standby mode
“” indicates that the interrupt can be used to request a return from Software Standby mode
Table 14.4
Event table (1 of 6)
IELSRn
DELSRn
Name
Connect to
NVIC
Invoke DTC
Invoke
DMAC
Canceling
Snooze
Canceling
Software
Standby
PORT_IRQ0
002h
PORT_IRQ1
003h
PORT_IRQ2
004h
PORT_IRQ3
005h
PORT_IRQ4
006h
PORT_IRQ5
007h
PORT_IRQ6
008h
PORT_IRQ7
009h
PORT_IRQ8
00Ah
PORT_IRQ9
00Bh
PORT_IRQ10
00Ch
PORT_IRQ11
00Dh
PORT_IRQ12
00Eh
PORT_IRQ13
00Fh
PORT_IRQ14
Event
number
Interrupt request
source
001h
Port
010h
PORT_IRQ15
011h
DMAC0
DMAC0_INT
-
-
-
012h
DMAC1
DMAC1_INT
-
-
-
013h
DMAC2
DMAC2_INT
-
-
-
014h
DMAC3
DMAC3_INT
-
-
-
015h
DTC
DTC_COMPLETE
-
-
*4
017h
ICU
ICU_SNZCANCEL
-
-
-
018h
FCU
FCU_FRDYI
-
-
-
-
019h
LVD
LVD_LVD1
-
-
LVD_LVD2
-
-
01Ah
01Bh
VBATT
VBATT_LVD
-
-
01Ch
MOSC
MOSC_STOP
-
-
-
-
01Dh
Low power mode
SYSTEM_SNZREQ
-
-
-
-
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Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (2 of 6)
IELSRn
DELSRn
Canceling
Snooze
Canceling
Software
Standby
Event
number
Interrupt request
source
Name
Connect to
NVIC
Invoke DTC
Invoke
DMAC
01Eh
AGT0
AGT0_AGTI
-
-
01Fh
AGT0_AGTCMAI
-
-
020h
AGT0_AGTCMBI
-
-
AGT1_AGTI
022h
AGT1_AGTCMAI
023h
AGT1_AGTCMBI
021h
AGT1
024h
IWDT
IWDT_NMIUNDF
-
-
025h
WDT
WDT_NMIUNDF
-
-
-
-
026h
RTC
RTC_ALM
-
-
RTC_PRD
-
-
RTC_CUP
-
-
-
-
ADC140_ADI
-
-
02Ah
ADC140_GBADI
-
-
02Bh
ADC140_CMPAI
-
-
-
-
02Ch
ADC140_CMPBI
-
-
-
-
027h
028h
029h
ADC140
02Dh
ADC140_WCMPM
-
*4
02Eh
ADC140_WCMPUM
-
*4
-
ACMP_LP0
-
-
ACMP_LP1
-
-
-
-
-
-
-
-
02Fh
ACMPLP
030h
USBFS_D0FIFO
031h
032h
USBFS_D1FIFO
033h
USBFS_USBI
-
-
-
-
034h
USBFS_USBR
-
-
IIC0_RXI
-
-
036h
IIC0_TXI
-
-
037h
IIC0_TEI
-
-
-
-
038h
IIC0_EEI
-
-
-
-
035h
USBFS
IIC0
039h
IIC0_WUI
-
-
IIC1_RXI
-
-
03Bh
IIC1_TXI
-
-
03Ch
IIC1_TEI
-
-
-
-
03Dh
IIC1_EEI
-
-
-
-
IIC2_RXI
-
-
03Fh
IIC2_TXI
-
-
040h
IIC2_TEI
-
-
-
-
041h
IIC2_EEI
-
-
-
-
03Ah
03Eh
042h
IIC1
IIC2
SSIE0_SSITXI
-
-
043h
SSIE0_SSIRXI
-
-
045h
SSIE0_SSIF
-
-
-
-
CTSU_CTSUWR
-
-
CTSU_CTSURD
-
-
-
*4
* 1
-
046h
SSIE0
CTSU
047h
048h
CTSU_CTSUFN
-
-
*1
-
-
*4
049h
KINT
KEY_INTKR
04Ah
DOC
DOC_DOPCI
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Page 252 of 1619
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Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (3 of 6)
IELSRn
DELSRn
Canceling
Snooze
Canceling
Software
Standby
Event
number
Interrupt request
source
Name
Connect to
NVIC
Invoke DTC
Invoke
DMAC
04Bh
CAC
CAC_FERRI
-
-
-
-
04Ch
CAC_MENDI
-
-
-
-
04Dh
CAC_OVFI
-
-
-
-
CAN0_ERS
-
-
-
-
04Fh
CAN0_RXF
-
-
-
-
050h
CAN0_TXF
-
-
-
-
051h
CAN0_RXM
-
-
-
-
CAN0_TXM
-
-
-
-
IOPORT_GROUP1
*2
*2
-
-
IOPORT_GROUP2
*2
*2
-
-
*2
04Eh
CAN0
052h
053h
I/O port
054h
055h
IOPORT_GROUP3
*2
-
-
056h
IOPORT_GROUP4
*2
*2
-
-
ELC_SWEVT0
*3
-
-
-
ELC_SWEVT1
*3
-
-
-
POEG_GROUP0
-
-
-
-
POEG_GROUP1
-
-
-
-
057h
ELC
058h
059h
POEG
05Ah
GPT0_CCMPA
05Bh
-
-
05Ch
GPT0_CCMPB
-
-
05Dh
GPT0_CMPC
-
-
05Eh
GPT0_CMPD
-
-
05Fh
GPT0_CMPE
-
-
060h
GPT0_CMPF
-
-
061h
GPT0_OVF
-
-
062h
GPT0_UDF
-
-
GPT1_CCMPA
-
-
064h
GPT1_CCMPB
-
-
065h
GPT1_CMPC
-
-
066h
GPT1_CMPD
-
-
067h
GPT1_CMPE
-
-
068h
GPT1_CMPF
-
-
069h
GPT1_OVF
-
-
06Ah
GPT1_UDF
-
-
GPT2_CCMPA
-
-
06Ch
GPT2_CCMPB
-
-
06Dh
GPT2_CMPC
-
-
06Eh
GPT2_CMPD
-
-
06Fh
GPT2_CMPE
-
-
070h
GPT2_CMPF
-
-
071h
GPT2_OVF
-
-
072h
GPT2_UDF
-
-
063h
06Bh
GPT320
GPT321
GPT322
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Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (4 of 6)
IELSRn
DELSRn
Canceling
Snooze
Canceling
Software
Standby
Event
number
Interrupt request
source
Name
Connect to
NVIC
Invoke DTC
Invoke
DMAC
073h
GPT323
GPT3_CCMPA
-
-
074h
GPT3_CCMPB
-
-
075h
GPT3_CMPC
-
-
076h
GPT3_CMPD
-
-
077h
GPT3_CMPE
-
-
078h
GPT3_CMPF
-
-
079h
GPT3_OVF
-
-
GPT3_UDF
-
-
GPT4_CCMPA
-
-
GPT4_CCMPB
-
-
07Dh
GPT4_CMPC
-
-
07Eh
GPT4_CMPD
-
-
07Fh
GPT4_CMPE
-
-
080h
GPT4_CMPF
-
-
081h
GPT4_OVF
-
-
082h
GPT4_UDF
-
-
07Ah
07Bh
GPT164
07Ch
GPT5_CCMPA
083h
-
-
084h
GPT5_CCMPB
-
-
085h
GPT5_CMPC
-
-
086h
GPT5_CMPD
-
-
087h
GPT5_CMPE
-
-
088h
GPT5_CMPF
-
-
089h
GPT5_OVF
-
-
08Ah
GPT5_UDF
-
-
GPT6_CCMPA
-
-
08Ch
GPT6_CCMPB
-
-
08Dh
GPT6_CMPC
-
-
08Eh
GPT6_CMPD
-
-
08Fh
GPT6_CMPE
-
-
090h
GPT6_CMPF
-
-
091h
GPT6_OVF
-
-
092h
GPT6_UDF
-
-
GPT7_CCMPA
-
-
094h
GPT7_CCMPB
-
-
095h
GPT7_CMPC
-
-
096h
GPT7_CMPD
-
-
097h
GPT7_CMPE
-
-
098h
GPT7_CMPF
-
-
099h
GPT7_OVF
-
-
09Ah
GPT7_UDF
-
-
08Bh
093h
GPT165
GPT166
GPT167
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Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (5 of 6)
IELSRn
DELSRn
Canceling
Snooze
Canceling
Software
Standby
Event
number
Interrupt request
source
Name
Connect to
NVIC
Invoke DTC
Invoke
DMAC
09Bh
GPT168
GPT8_CCMPA
-
-
09Ch
GPT8_CCMPB
-
-
09Dh
GPT8_CMPC
-
-
09Eh
GPT8_CMPD
-
-
09Fh
GPT8_CMPE
-
-
0A0h
GPT8_CMPF
-
-
0A1h
GPT8_OVF
-
-
0A2h
GPT8_UDF
-
-
GPT9_CCMPA
-
-
0A4h
GPT9_CCMPB
-
-
0A5h
GPT9_CMPC
-
-
0A6h
GPT9_CMPD
-
-
0A7h
GPT9_CMPE
-
-
0A8h
GPT9_CMPF
-
-
0A9h
GPT9_OVF
-
-
0AAh
GPT9_UDF
-
-
0A3h
GPT169
0ABh
GPT
GPT_UVWEDGE
-
-
-
-
0ACh
SCI0
SCI0_RXI
-
-
0ADh
SCI0_TXI
-
-
0AEh
SCI0_TEI
-
-
-
-
0AFh
SCI0_ERI
-
-
-
-
-
*4
-
0B0h
SCI0_AM
-
SCI0_RXI_OR_ERI
-
-
-
*4
SCI1_RXI
-
-
0B3h
SCI1_TXI
-
-
0B4h
SCI1_TEI
-
-
-
-
0B5h
SCI1_ERI
-
-
-
-
0B1h
0B2h
SCI1
0B6h
0B7h
SCI2
0B8h
SCI1_AM
-
-
-
-
SCI2_RXI
-
-
SCI2_TXI
-
-
0B9h
SCI2_TEI
-
-
-
-
0BAh
SCI2_ERI
-
-
-
-
0BBh
SCI2_AM
-
-
-
-
0BCh
SCI3_RXI
-
-
0BDh
SCI3_TXI
-
-
0BEh
SCI3_TEI
-
-
-
-
0BFh
SCI3_ERI
-
-
-
-
0C0h
SCI3_AM
-
-
-
-
SCI4_RXI
-
-
0C2h
SCI4_TXI
-
-
0C3h
SCI4_TEI
-
-
-
-
0C4h
SCI4_ERI
-
-
-
-
0C5h
SCI4_AM
-
-
-
-
0C1h
SCI3
SCI4
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Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (6 of 6)
IELSRn
DELSRn
Canceling
Snooze
Canceling
Software
Standby
Event
number
Interrupt request
source
Name
Connect to
NVIC
Invoke DTC
Invoke
DMAC
0C6h
SCI9
SCI9_RXI
-
-
0C7h
SCI9_TXI
-
-
0C8h
SCI9_TEI
-
-
-
-
0C9h
SCI9_ERI
-
-
-
-
0CAh
SCI9_AM
-
-
-
-
SPI0_SPRI
-
-
0CCh
SPI0_SPTI
-
-
0CBh
SPI0
0CDh
SPI0_SPII
-
-
-
-
0CEh
SPI0_SPEI
-
-
-
-
0CFh
SPI0_SPTEND
-
-
-
-
0D0h
SPI1_SPRI
-
-
0D1h
SPI1
SPI1_SPTI
-
-
0D2h
SPI1_SPII
-
-
-
-
0D3h
SPI1_SPEI
-
-
-
-
0D4h
SPI1_SPTEND
-
-
-
-
0D5h
QSPI
QSPI_INTR
-
-
-
-
0D6h
SDHI0
SDHI_MMC0_ACCS
-
-
-
-
0D7h
SDHI_MMC0_SDIO
-
-
-
-
0D8h
SDHI_MMC0_CARD
-
-
-
-
0D9h
SDHI_MMC0_ODMSDBREQ
-
-
-
Note 1.
Note 2.
Note 3.
Note 4.
Only supported when KRCTL.KRMD = 1.
Only the first edge detection is valid.
Only interrupts after DTC transfer are supported.
Using SELSR0.
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14.4
14. Interrupt Controller Unit (ICU)
Interrupt Operation
The ICU performs the following functions:
Detecting interrupts
Enabling and disabling interrupts
Selecting interrupt request destinations such as CPU interrupt, DTC activation, or DMAC activation.
14.4.1
Detecting Interrupts
External pin interrupt requests are detected by either the edge or level (falling edge, rising edge, rising and falling edge,
or low level) of the interrupt signal. Set the IRQMD[1:0] bits in the IRQCRi register to select the detection mode for the
IRQi pins. For interrupt sources associated with peripheral modules, see section 14.3.2, Event Number. Events must be
accepted by the NVIC before an interrupt occurs and is accepted by the CPU.
ICU
CPU : NVIC
IELSRn
Event
factor
Select of event factor
Interrupt
source
Set by S/W interrupt
IR
Set
Reset
pending
Set
Reset
Enable register
Clear by S/W
Figure 14.2
Automatically cleared by
the interrupt completion
Interrupt path of the ICU, CPU: NVIC
General operations during an interrupt
When a non-software interrupt occurs:
The IELSRn.IR flag and Interrupt Set/Clear-Pending Register (NVIC) are set.
When a software interrupt occurs:
Set the Interrupt Set-Pending Register.
When an interrupt is complete:
Clear the IELSRn.IR flag with software.
The Interrupt Set/Clear-Pending Register clears automatically.
When interrupts are enabled:
1)
Set the Interrupt Set-Enable Register.
2)
Set the IELSRn.IELS bits as interrupt source.
3)
Specify the operation settings for the event source.
When interrupts are disabled:
1)
Disable the settings for the event source.
2)
Clear the IELSRn.IELS bits (IELSRn.IELS[7:0] = 00h). Clear the IELSRn.IR flag as required.
3)
Clear the Interrupt Clear-Enable Register. Clear the Interrupt Clear-Pending Register as required.
When polling for interrupts:
1)
Set the Interrupt Clear-Enable Register (disabling interrupts).
2)
Set the IELSRn.IELS bits (selecting the source).
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14. Interrupt Controller Unit (ICU)
3)
Specify the operation settings for the event source.
4)
Poll the Interrupt Set-Pending Register.
5)
When polling is no longer required, follow the procedure for clearing an interrupt when it is complete.
14.4.2
Selecting Interrupt Request Destinations
The interrupt output destination, CPU, DTC or DMAC, can be independently selected for each interrupt source. The
available destinations are fixed for each interrupt, as described in Table 14.4, Event table.
Note:
Do not use an interrupt request destination setting that is not indicated by a in the event list (Table 14.4).
If you select the CPU or DTC in one IELSRn register, setting the same interrupt factor in any other IELSRn register is
prohibited. Similarly, if you select the DMAC in one DELSRn register, setting the same interrupt factor in any other
DELSRn register is prohibited.
Note:
Setting the same interrupt factor for IELSRn and DELSRn is prohibited.
If the DMAC or DTC is selected as the destination for requests from an IRQi pin, be sure to set the IRQMD[1:0] bits in
IRQCRi for that interrupt to select edge detection.
14.4.2.1
CPU interrupt request
When IELSRn.DTCE = 0, the event specified in the IELSRn register is output to the NVIC. Set the IELSRn.IELS bits
and IELSRn.DTCE bit to 0.
14.4.2.2
DTC activation
When IELSRn.DTCE = 1, the event specified in the IELSRn register is output to the DTC. After DTC transmission
completes, the associated interrupt occurs. Use the following procedure:
1. Set the IELSRn.IELS bits to the target event and the IELSRn.DTCE bit to 1.
2. Set the DTC module activation bit DTCST.DTCST to 1.
Table 14.5 shows operation when DTC is the request destination.
Table 14.5
Operations when DTC is activated
Interrupt
request
destination
DISEL*1
Remaining
transfer
operations
DTC*3
1
0
Note 1.
Note 2.
Note 3.
Operations per
request
IR*2
≠0
DTC transfer →
CPU interrupt
Cleared on interrupt acceptance by
the CPU
DTC
=0
DTC transfer →
CPU interrupt
Cleared on interrupt acceptance by
the CPU
The IELSRn.DTCE bit is cleared
and the CPU becomes the
destination
≠0
DTC transfer
Cleared at the start of DTC data
transfer after reading DTC transfer
data
DTC
=0
DTC transfer →
CPU interrupt
Cleared on interrupt acceptance by
the CPU
The IELSRn.DTCE bit is cleared
and the CPU becomes the
destination
Interrupt request destination
after transfer
Set the interrupt request mode for the DTC in the DTC.MRB.DISEL bit.
When the IELSRn.IR flag is 1, an interrupt request (DTC activation request) that occurs again is ignored.
For chain transfers, DTC transfer continues until the last chain transfer ends. At this point, the DISEL bit state and the
remaining transfer count determine whether a CPU interrupt occurs, the IELSRn.IR flag clear timing, and the interrupt request
destination after transfer. See Table 18.3, Chain transfer conditions in section 18, Data Transfer Controller (DTC).
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14.4.2.3
14. Interrupt Controller Unit (ICU)
DMAC activation
When IELSRn.DTCE = 0, the event specified in the IELSRn register is output to the NVIC. To set the interrupt source
for DMAC, use the following procedure:
1. Set the DELSRn.DELS[7:0].
2. Set the IELSRn.IELS bits to the target event and the IELSRn.DTCE bit to 1.
3. Set the activation source for the target DMAC channel (DMACm.DMTMD.DCTG[1:0]) to 01b (interrupt module
detection).
4. Set the DMAC transfer enable bit for the target DMAC channel (DMACm.DMCNT.DTE) to 1.
5. Set the DMAC operation enable bit (DMAST.DMST) to 1.
ICU
IELSRn
Interrupt
source
Event No.17 to 20
(011h to 014h)
CPU
Interrupt request
IR
N
V
I
C
IR
IR
IR
IR
DELSRn
DMAC activation
request
DMAC activation request
DMAC
activation
control
DMAC
DMAC response
DMAC interrupt
Figure 14.3
14.4.3
DMAC request trigger and interrupt path
Digital Filter
A digital filter function is provided for the external interrupt request pins (IRQi, i = 0 to 15) and NMI pin interrupt. It
samples input signals on the filter PCLKB sampling clock and removes any signal with a pulse width less than 3
sampling cycles.
To use the digital filter for a IRQi pin:
1)
Set the sampling clock cycle to PCLKB, PCLKB/8, PCLKB/32, or PCLKB/64 in the IRQCRi.FCLKSEL[1:0] bits (i = 0 to 15).
2)
Set the IRQCRi.FLTEN bit (i = 0 to 15) to 1 (digital filter enabled).
To use the digital filter for the NMI pin:
1)
Set the sampling clock cycle to PCLKB, PCLKB/8, PCLKB/32, or PCLKB/64 in the NMICR.NFCLKSEL[1:0] bits.
2)
Set the NMICR.NFLTEN bit to 1 (digital filter enabled).
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14. Interrupt Controller Unit (ICU)
Figure 14.4 shows an example of digital filter operation.
Sampling clock
for digital filter
IRQCRi.FLTEN bit*1
Pulses removed
The level matches
three times
*1
IRQi pin
The level matches
three times
IRQi_d*1
(internal F/F)
Digital filter enabled
Disabled
Enabled
Operation example with IRQCRi.IRQMD[1:0] = 11b (low)
Note 1.
Figure 14.4
i = 0 to 15
Digital filter operation example
Before entering Software Standby mode, disable the digital filters by clearing the IRQCRi.FLTEN and NMICR.NFLTEN
bits. The ICU clock stops in Software Standby. On exiting Software Standby, the circuit detects the edge by comparing
the state before standby to the state after standby release. If the input changes during Software Standby, an incorrect edge
might be detected. You can enable the digital filters again after exiting Software Standby mode.
14.4.4
External Pin Interrupts
To use external pin interrupts:
1. Clear the IRQCRi.FLTEN bit (i = 0 to 15) to 0 (digital filter disabled).
2. Set or confirm the I/O port settings.
3. Set the IRQMD[1:0] bits, FCLKSEL[1:0] bits and FLTEN bit of IRQCRi register.
4. Set the IRQ pin as follows:
If the IRQ pin is to be used for CPU interrupt request, set the IELSRn.IELS[7:0] bits and IELSRn.DTCE bit to 0
If the IRQ pin is to be used for DTC activation, set the IELSRn.IELS[7:0] bits and IELSRn.DTCE bit to 1
If the IRQ pin is to be used for DMAC activation, set the DELSRn.DELS bits.
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14.5
14. Interrupt Controller Unit (ICU)
Non-maskable Interrupt Operation
The following sources can trigger a non-maskable interrupt:
NMI pin interrupt
Oscillation stop detection interrupt
WDT underflow/refresh error interrupt
IWDT underflow/refresh error interrupt
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
VBATT monitor interrupt
SRAM parity error interrupt
SRAM ECC error interrupt
MPU bus master error interrupt
MPU bus slave error interrupt
CPU stack pointer monitor interrupt.
Non-maskable interrupts can only be used with the CPU, not to activate the DTC or DMAC. Non-maskable interrupts
take precedence over all other interrupts. The non-maskable interrupt states can be verified in the Non-Maskable
Interrupt Status Register (NMISR). Confirm that all bits in the NMISR are 0 before returning from the NMI handler.
Non-maskable interrupts are disabled by default. To use non-maskable interrupts, use the following procedure.
To use the NMI pin, follow steps 1 to 3:
1. Clear the NMICR.NFLTEN bit to 0 (digital filter disabled).
2. Set the NMIMD bit, NFCLKSEL[1:0] bits, and NFLTEN bit of NMICR register.
3. Write 1 to the NMICLR.NMICLR bit to clear the NMISR.NMIST flag to 0.
4. Enable the non-maskable interrupt by writing 1 to the associated bit in the Non-Maskable Interrupt Enable Register
(NMIER).
After 1 is written to the NMIER register, subsequent write access to the NMIEN bit in NMIER is ignored. An NMI
interrupt cannot be disabled when enabled, except by a reset.
14.6
Return from Low Power Mode
Table 14.4, Event table lists the interrupt sources that you can use to exit Sleep or Software Standby mode. For details,
see section 11, Low Power Modes. Sections 14.6.1 to 14.6.3 describe how to use interrupts to return from Sleep,
Software Standby, and Snooze modes.
14.6.1
Return from Sleep Mode
To return from Sleep mode in response to an interrupt:
1. Select the CPU as the interrupt request destination.
2. Enable the interrupt in the NVIC.
To return from Sleep mode in response to a non-maskable interrupt, use the NMIER register to enable the given interrupt
request.
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14.6.2
14. Interrupt Controller Unit (ICU)
Return from Software Standby Mode
The ICU can return from Software Standby mode using a non-maskable interrupt or an interrupt selected in the WUPEN
register. See section 14.2.9, Wake Up Interrupt Enable Register (WUPEN).
To return from Software Standby mode, you must:
1. Select the interrupt source that enables return from Software Standby:
For non-maskable interrupts, use the NMIER register to enable the target interrupt request
For maskable interrupts, use the WUPEN register to enable the target interrupt request.
2. Select the CPU as the interrupt request destination.
3. Enable the interrupt in the NVIC.
Interrupt requests through the IRQ pins that do not satisfy these conditions are not detected while the clock is stopped in
Software Standby mode.
14.6.3
Return from Snooze Mode
The ICU can return to Normal mode from Snooze mode using the interrupts provided for this mode.
To return to Normal mode from Snooze mode:
1. Use either of the following methods to select the event that you want to trigger a return to Normal mode from
Snooze mode:
a. Set the event that you want to trigger a return to Normal mode from Snooze mode in SELSR0.SELS and set the
value 017h (ICU_SNZCANCEL) in IELSRn.IELS.
b. Set the event that you want to trigger a return to Normal mode from Snooze mode in IELSRn.IELS.
2. Select the CPU as the interrupt request destination.
3. Enable the interrupt in the NVIC.
Note:
14.7
In Snooze mode, a clock is supplied to ICU. If an event selected in IELSRn is detected, the CPU can
acknowledge the interrupt after returning to Normal mode from Software Standby mode. If an event selected in
DELSRn is detected, the DMAC can acknowledge the interrupt after returning to Normal mode from Software
Standby mode.
Using the WFI Instruction with Non-maskable Interrupts
Whenever a WFI instruction is executed, confirm that all status flags in the NMISR register are 0.
14.8
Reference
ARM® Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D).
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15.
Buses
15.1
Overview
15. Buses
Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses
assigned for each bus.
Table 15.1
Bus specifications
Bus Type
Main bus
Slave
interface
External
bus
Note 1.
Description
ICode bus (CPU)
Connected to the CPU
Connected to on-chip memory (code flash memory).
DCode bus (CPU)
Connected to the CPU
Connected to on-chip memory (code flash memory).
System bus (CPU)
Connected to the CPU
Connected to on-chip memory, internal peripheral bus, and external bus.
DMA bus
Connected to the DMAC/DTC
Connected to on-chip memory, internal peripheral bus, and external bus.
Memory bus 1
Connected to code flash memory
Memory bus 3
Connected to code flash memory by DMA bus
Memory bus 4
Connected to SRAM0
Memory bus 5
Connected to SRAM1
Internal peripheral bus 1
Connected to system control related to peripheral modules
Internal peripheral bus 3
Connected to peripheral modules (CAC, ELC, I/O ports, POEG, RTC, WDT, IWDT, IIC,
CAN, SSIE, ADC14, DAC12, and DOC)
Internal peripheral bus 4
Connected to peripheral modules (SCI, SPI, CRC, GPT, and SDHI)
Internal peripheral bus 5
Connected to peripheral modules (KINT, AGT, USBFS, OPAMP, ACMPLP, DAC8,
SLCDC, and CTSU)
Internal peripheral bus 7
Connected to Secure IPs
Internal peripheral bus 9
Connected to flash memory (in P/E)*1 and data flash memory
CS area
Connected to the external devices
QSPI area
Connected to the external SPI devices
P/E = Programming/Erasure.
CM4
DMAC/
DTC
ICode bus
DCode bus
System bus
DMA bus
SRAM0
Data flash
memory
Internal
peripherals
External bus
controller
SRAM1
Code flash
memory
Figure 15.1
Bus configuration
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Table 15.2
15. Buses
Addresses assigned for each bus
Address
Bus
Area
0000 0000h to 01FF FFFFh
Memory bus 1, 3
Code flash memory
2000 0000h to 2001 FFFFh
Memory bus 4
SRAM0
2002 0000h to 2002 FFFFh
Memory bus 5
SRAM1
4000 0000h to 4001 FFFFh
Internal peripheral bus 1
Peripheral I/O registers
4004 0000h to 4005 FFFFh
Internal peripheral bus 3
4006 0000h to 4007 FFFFh
Internal peripheral bus 4
4008 0000h to 4009 FFFFh
Internal peripheral bus 5
400C 0000h to 400D FFFFh
Internal peripheral bus 7
Secure IPs
4010 0000h to 407F FFFFh
Internal peripheral bus 9
Flash memory (in P/E)*1 and data flash memory
6000 0000h to 67FF FFFFh
External bus
QSPI area
8000 0000h to 97FF FFFFh
External bus
CS area
Note 1.
15.2
15.2.1
P/E = Programming/Erasure.
Description of Buses
Main Buses
The main bus for the CPU consists of the ICode bus, DCode bus, and system bus:
The ICode bus and the DCode bus are connected to the code flash memory. The ICode bus is used for instruction
access to the CPU and the DCode bus is used for data access to the CPU.
The system bus is connected to SRAM0, SRAM1, the data flash memory, the internal peripheral bus, and the
external bus. The system bus is used for instruction and data accesses to the CPU.
The main bus for modules other than the CPU consists of the DMA bus. The DMA bus is connected to the code flash
memory, SRAM0, SRAM1, data flash memory, internal peripheral bus, and external bus.
Different master and slave transfer combinations can proceed simultaneously.
Arbitration between DMAC and DTC for the mastership of the DMA bus occurs in the DMAC and DTC. The following
fixed-priority order is used:
DMAC0 > DMAC1 > DMAC2 > DMAC3 > DTC.
Only one DTC or DMAC channels that have accepted the activation requests can issue the bus mastership request. In
addition, requests for bus access from masters other than the DTC are not accepted during reads of transfer control
information for the DTC.
15.2.2
Slave Interface
Products using the Cortex®-M4 core contain ICode and DCode bus areas and a system bus area. To create the ICode and
DCode bus areas, a bus matrix connects the ICode bus, the DCode bus, and the memory bus 3 from the main bus to the
slave interfaces of the code flash memory. To create a system bus area, a bus matrix connects the system bus and DMA
bus from the main bus to the slave interfaces of SRAM0, SRAM1, data flash memory, internal peripheral, and the
external bus. For connections from the main bus to the slave interfaces, see the slave interfaces in Table 15.1. For a
description of the external bus, see section 15.2.3, External Bus.
Arbitration between the ICode bus, DCode bus, and memory bus 3 occurs in the slave interface of the ICode and the
DCode bus areas. The arbitration method is selectable from fixed priority and round-robin. For more information, see
section 15.3.8.
Arbitration between the system bus and DMA bus occurs in the slave interface of the system bus area. The arbitration
method is selectable from fixed priority and round-robin. For more information, see section 15.3.8.
Different master and slave transfer combinations can proceed simultaneously.
15.2.3
External Bus
Table 15.3 lists the external bus specifications. The external bus controller arbitrates requests for bus access on the
external address space from the CPU system bus and the DMA bus. The priority order can be set using the external bus
priority control bits (BUSSCNT.ARBMET[1:0]). For more information, see section 15.3.8. The bus system provides an
external space for the QSPI. See section 33, Quad Serial Peripheral Interface (QSPI).
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Table 15.3
15. Buses
External bus specifications
Item
Description
External address space
The external address space is divided into 4 CS areas (CS0 to CS3) for management
Chip select signals can be output for each area
The bus width can be set for each area:
- Separate bus: selectable to 8-bit or 16-bit bus space
- Address/data multiplexed bus: selectable to 8-bit or 16-bit bus space.
Endian mode can be specified for each area.
CS area controller
Recovery cycles can be inserted:
- Read recovery: up to 15 cycles
- Write recovery: up to 15 cycles.
Cycle wait function: wait for up to 31 cycles (for page access up to 7 cycles)
Wait control can be used to set up the following:
- Assertion and negation timing of the chip select signals (CS0 to CS3)
- Assertion timing of the read signal (RD) and write signals (WR0/WR and WR1)
- Timing of the data output starts and ends.
Write access mode:
- Single write strobe mode/byte strobe mode.
Separate bus or address/data multiplexed bus can be set for each area.
Write buffer function
When write data from the bus master is written to the write buffer, write access by the bus master is
complete
Frequency
The CS area controller (CSC) operates in synchronization with the external bus clock (BCLK)
The frequency of the EBCLK pin output is the same as BCLK by default. Half of the BCLK clock cycle can
be supplied by setting the EBCLK Pin Output Select bit, BCKCR.BCLKDIV, in the External Bus Clock
Control Register. For more information, see section 9, Clock Generation Circuit.
Table 15.4 lists the input and output pins of the external bus.
Table 15.4
External pin configurations (1 of 2)
Pin name
I/O
Description
EBCLK
Output
Clock output pin
A23 to
A00*1
Output
Address output pins
D15 to D00
I/O
Data input/output pins:
D15 to D00 pins are enabled when the 16-bit bus space is specified
D07 to D00 pins are enabled when the 8-bit bus space is specified.
BC0*1
Output
Strobe signal (when low) indicates that D07 to D00 are valid during access to an external address
space in single write strobe mode, active-low.
When the 8-bit bus space is specified, this output pin is always held low regardless of the write
access mode.
BC1
Output
Strobe signal (when low) indicates that D15 to D08 are valid during access to an external address
space in single write strobe mode, active-low.
This pin is not used when the 8-bit bus space is specified.
CS0
Output
Chip select signal for area 0 (CS0), active-low
CS1
Output
Chip select signal for area 1 (CS1), active-low
CS2
Output
Chip select signal for area 2 (CS2), active-low
CS3
Output
Chip select signal for area 3 (CS3), active-low
RD
Output
Strobe signal that indicates that a read from an external address space (CS0 to CS3) is in progress,
active-low.
WR0/WR*2
Output
WR0 signal is a strobe signal that indicates (when low) that a write to an external address space is
in progress in byte strobe mode, and D07 to D00 are valid, active-low.
WR signal is a strobe signal that indicates that a write to an external address space is in progress in
single write strobe mode, active-low.
When an 8-bit bus space is specified, this output pin is held low during a write access regardless of
the write access mode.
WR1
Output
Strobe signal (when low) during a write to an external address space in byte strobe mode indicates
that D15 to D08 are valid, active-low.
This signal is invalid in single write strobe mode.
This pin is not used when the 8-bit bus space is specified.
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Table 15.4
15. Buses
External pin configurations (2 of 2)
Pin name
I/O
Description
ALE
Output
Address latch signal when address/data multiplexed bus is selected
WAIT
Input
Wait request signal (when low) when accessing the external address space (CS0 to CS3), activelow
Note 1.
Note 2.
The A00 and BC0 pin functions share the same pin, and either become valid according to the area, with the function being A00
in byte strobe mode and BC0 in single write strobe mode. Setting the 8-bit external bus width is prohibited in single write strobe
mode. For information on other multiplexed pin functions, see section 20, I/O Ports.
The WR0 signal and WR signal are identical. The WR0 signal is particularly referred to as WR in single write strobe mode.
15.2.4
Parallel Operation
Parallel operation is possible when different bus masters request access to different slave modules. For example, if the
CPU fetches an instruction from the flash and an operand from the SRAM, the DMAC can handle transfers between a
peripheral bus and the external bus at the same time.
An example of parallel operations is shown in Figure 15.2. In this example, the CPU uses the instruction and operand
buses for simultaneous access to the flash and SRAM, respectively. Additionally, the DMAC/DTC simultaneously use
the DMA bus for access to a peripheral bus or external bus during access to the flash memory and SRAM by the CPU.
Flash access
CPU instruction fetching
Flash
Flash
Flash
Flash
Flash
Flash
Flash
SRAM
SRAM
SRAM access
CPU operand
SRAM
15.2.5
SRAM
SRAM
SRAM
Peripheral bus access
External bus access
Peripheral bus
External bus
DMAC
Figure 15.2
SRAM
Example of parallel operations
Bus Settings
Set up the external bus with the following registers:
Mode settings:
CSn Mode Register (CSnMOD), CSn Wait Control Register 1 (CSnWCR1), CSn Wait Control Register 2
(CSnWCR2), CSn Control Register (CSnCR), CSn Recovery Cycle Setting Register (CSnREC), CS Recovery
Cycle Insertion Enable Register (CSRECEN), and Bus Priority Control Register (BUSSCNT)
I/O port assignments:
PmnPFS.PMR = 1 and PmnPFS.PSEL[4:0] = 0Bh
Frequency of the external bus clock (BCLK):
SCKDIVCR register.
See section 20, I/O Ports for information on PmnPFS and section 9, Clock Generation Circuit for information on
SCKDIVCR.
15.2.6
(1)
Restrictions
Restriction on endianness
Memory space must be little-endian to execute code on the Cortex-M4 core.
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15.3
15. Buses
Register Descriptions
15.3.1
CSn Control Register (CSnCR) (n = 0 to 3)
Address(es): BUS.CS0CR 4000 3802h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
MPXEN
—
—
—
EMOD
E
—
—
BSIZE[1:0]
—
—
—
EXENB
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
Value after reset:
Address(es): BUS.CS1CR 4000 3812h, BUS.CS2CR 4000 3822h, BUS.CS3CR 4000 3832h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
BSIZE[1:0]
—
—
—
EXENB
0
0
0
0
0
0
0
—
—
—
MPXEN
—
—
—
EMOD
E
0
0
0
0
0
0
0
0
Value after reset:
0
Bit
Symbol
Bit name
Description
R/W
b0
EXENB
Operation Enable
0: Disable operation
1: Enable operation.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b5, b4
BSIZE[1:0]
External Bus Width Select
b5 b4
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b8
EMODE
Endian Mode
0: Little endian
1: Big endian.
b11 to b9
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b12
MPXEN
Address/Data Multiplexed I/O Interface
Select
0: Separate bus interface is selected for area n
1: Address/data multiplexed I/O interface is selected
for area n.
(n = 0 to 3)
b15 to b13
—
Reserved
These bits are read as 0. The write value should be 0. R/W
R/W
0 0: 16-bit bus space
0 1: Setting prohibited
1 0: 8-bit bus space
1 1: Setting prohibited.
R/W
R/W
Do not attempt to write the CSnCR register while the external bus is being accessed.
EXENB bit (Operation Enable)
The EXENB bit enables or disables operation of the associated CS areas. On MCU reset, operation is enabled (EXENB
= 1) only for area 0. Operation in other areas is disabled (EXENB = 0). Attempts to access disabled areas have no effect.
BSIZE[1:0] bits (External Bus Width Select)
The BSIZE[1:0] bits specify the data bus width for the associated area.
EMODE bit (Endian Mode)
The EMODE bit specifies the endianness for the associated area. The Cortex-M4 core is fixed at little-endian order, so
the instruction code can only be allocated to external spaces with little-endian specified. If an area is specified as bigendian, no instruction code can be allocated to it.
MPXEN bit (Address/Data Multiplexed I/O Interface Select)
The MPXEN bit specifies the separate bus interface or address/data multiplexed I/O interface of each area.
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15.3.2
15. Buses
CSn Recovery Cycle Register (CSnREC) (n = 0 to 3)
Address(es): BUS.CS0REC 4000 380Ah, BUS.CS1REC 4000 381Ah, BUS.CS2REC 4000 382Ah, BUS.CS3REC 4000 383Ah
b15
b14
b13
b12
—
—
—
—
0
0
0
0
Value after reset:
b11
b10
b9
b8
WRCV[3:0]
0
0
0
0
b7
b6
b5
b4
—
—
—
—
0
0
0
0
b3
b2
b1
b0
RRCV[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
RRCV[3:0]
Read Recovery
b3
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b11 to b8
WRCV[3:0]
Write Recovery
b11
b15 to b12
—
Reserved
These bits are read as 0. The write value should be 0. R/W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: No recovery cycle is inserted
1: 1 recovery cycle is inserted
0: 2 recovery cycles are inserted
1: 3 recovery cycles are inserted
0: 4 recovery cycles are inserted
1: 5 recovery cycles are inserted
0: 6 recovery cycles are inserted
1: 7 recovery cycles are inserted
0: 8 recovery cycles are inserted
1: 9 recovery cycles are inserted
0: 10 recovery cycles are inserted
1: 11 recovery cycles are inserted
0: 12 recovery cycles are inserted
1: 13 recovery cycles are inserted
0: 14 recovery cycles are inserted
1: 15 recovery cycles are inserted.
b8
0: No recovery cycle is inserted
1: 1 recovery cycle is inserted
0: 2 recovery cycles are inserted
1: 3 recovery cycles are inserted
0: 4 recovery cycles are inserted
1: 5 recovery cycles are inserted
0: 6 recovery cycles are inserted
1: 7 recovery cycles are inserted
0: 8 recovery cycles are inserted
1: 9 recovery cycles are inserted
0: 10 recovery cycles are inserted
1: 11 recovery cycles are inserted
0: 12 recovery cycles are inserted
1: 13 recovery cycles are inserted
0: 14 recovery cycles are inserted
1: 15 recovery cycles are inserted.
R/W
Do not attempt to write the CSnREC register while the external bus is being accessed.
When the preceding bus access is a separate bus access, CSnREC is valid when the recovery cycle insertion is enabled in
the separate bus recovery cycle insertion enable bit (RCVENi (i = 0 to 7)) in CSRECEN. When the preceding bus access
is an address/data multiplexed bus access, CSnREC is valid when the recovery cycle insertion is enabled with the
multiplexed bus recovery cycle insertion enable bit (RCVENMj) (j = 0 to 7)) in CSRECEN. For more information on
insertion of recovery cycles, see section 15.5.4.
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15. Buses
RRCV[3:0] bits (Read Recovery)
The RRCV[3:0] bits specify the number of recovery cycles inserted after a read access on the external bus. The
RRCV[3:0] bits specify each CSn (n = 0 to 3). When recovery cycle insertion is enabled and a value other than 0000b is
written to these bits, 1 to 15 recovery cycles are inserted in the following conditions:
After a read access to the external bus, a read access is made to the external bus in the same area
After a read access to the external bus, a read access is made to the external bus in a different area
After a read access to the external bus, a write access is made to the external bus in the same area
After a read access to the external bus, a write access is made to the external bus in a different area.
WRCV[3:0] bits (Write Recovery)
The WRCV[3:0] bits specify the number of recovery cycles inserted after a write access on the external bus. The
WRCV[3:0] bits specify each CSn (n = 0 to 3).
When the recovery cycle insertion is enabled and a value other than 0000b is written to these bits, 1 to 15 recovery cycles
are inserted in the following conditions:
After a write access to the external bus, a read access is made to the external bus in the same area
After a write access to the external bus, a read access is made to the external bus in a different area
After a write access to the external bus, a write access is made to the external bus in the same area
After a write access to the external bus, a write access is made to the external bus in a different area.
15.3.3
CS Recovery Cycle Insertion Enable Register (CSRECEN)
Address(es): BUS.CSRECEN 4000 3880h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN
M7
M6
M5
M4
M3
M2
M1
M0
7
6
5
4
3
2
1
0
Value after reset:
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
Bit
Symbol
Bit name
Description
R/W
b0
RCVEN0
Separate Bus Recovery Cycle Insertion
Enable 0
0: Disable
1: Enable.
R/W
b1
RCVEN1
Separate Bus Recovery Cycle Insertion
Enable 1
0: Disable
1: Enable.
R/W
b2
RCVEN2
Separate Bus Recovery Cycle Insertion
Enable 2
0: Disable
1: Enable.
R/W
b3
RCVEN3
Separate Bus Recovery Cycle Insertion
Enable 3
0: Disable
1: Enable.
R/W
b4
RCVEN4
Separate Bus Recovery Cycle Insertion
Enable 4
0: Disable
1: Enable.
R/W
b5
RCVEN5
Separate Bus Recovery Cycle Insertion
Enable 5
0: Disable
1: Enable.
R/W
b6
RCVEN6
Separate Bus Recovery Cycle Insertion
Enable 6
0: Disable
1: Enable.
R/W
b7
RCVEN7
Separate Bus Recovery Cycle Insertion
Enable 7
0: Disable
1: Enable.
R/W
b8
RCVENM0
Multiplexed Bus Recovery Cycle Insertion
Enable 0
0: Disable
1: Enable.
R/W
b9
RCVENM1
Multiplexed Bus Recovery Cycle Insertion
Enable 1
0: Disable
1: Enable.
R/W
b10
RCVENM2
Multiplexed Bus Recovery Cycle Insertion
Enable 2
0: Disable
1: Enable.
R/W
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15. Buses
Bit
Symbol
Bit name
Description
R/W
b11
RCVENM3
Multiplexed Bus Recovery Cycle Insertion
Enable 3
0: Disable
1: Enable.
R/W
b12
RCVENM4
Multiplexed Bus Recovery Cycle Insertion
Enable 4
0: Disable
1: Enable.
R/W
b13
RCVENM5
Multiplexed Bus Recovery Cycle Insertion
Enable 5
0: Disable
1: Enable.
R/W
b14
RCVENM6
Multiplexed Bus Recovery Cycle Insertion
Enable 6
0: Disable
1: Enable.
R/W
b15
RCVENM7
Multiplexed Bus Recovery Cycle Insertion
Enable 7
0: Disable
1: Enable.
R/W
Do not attempt to write to the CSRECEN register while the external bus is being accessed. For more information on the
insertion of recovery cycles, see section 15.5.4.
RCVENi bit (Separate Bus Recovery Cycle Insertion Enable i) (i = 0 to 7)
The RCVENi bit enables the insertion of read or write recovery cycles when, after a read or write access on the external
bus, a read or write access is made on the external bus to the same or different area.
RCVENMj bit (Multiplexed Bus Recovery Cycle Insertion Enable j) (j = 0 to 7)
The RCVENMj bit enables the insertion of read or write recovery cycles when, after a read or write access on the
external bus, a read or write access is made on the external bus to the same or different area.
Table 15.5
Access type association with RCVENi/RCVENMj bits
Associated bits
(separate/multiplexed)
Access type
External address space
Insertion of recovery cycles
Read access after read
access
Same area
Recovery cycles specified in the RRCV[3:0]
bits are inserted for the priority access area
RCVEN0/RCVENM0
Different area
Recovery cycles specified in the RRCV[3:0]
bits are inserted for the priority access area
RCVEN1/RCVENM1
Same area
Recovery cycles specified in the RRCV[3:0]
bits are inserted for the priority access area
RCVEN2/RCVENM2
Different area
Recovery cycles specified in the RRCV[3:0]
bits are inserted for the priority access area
RCVEN3/RCVENM3
Same area
Recovery cycles specified in the WRCV[3:0]
bits are inserted for the priority access area
RCVEN4/RCVENM4
Different area
Recovery cycles specified in the WRCV[3:0]
bits are inserted for the priority access area
RCVEN5/RCVENM5
Same area
Recovery cycles specified in the WRCV[3:0]
bits are inserted for the priority access area
RCVEN6/RCVENM6
Different area
Recovery cycles specified in the WRCV[3:0]
bits are inserted for the priority access area
RCVEN7/RCVENM7
Write access after read
access
Read access after write
access
Write access after write
access
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15.3.4
15. Buses
CSn Mode Register (CSnMOD) (n = 0 to 3)
Address(es): BUS.CS0MOD 4000 3002h, BUS.CS1MOD 4000 3012h, BUS.CS2MOD 4000 3022h, BUS.CS3MOD 4000 3032h
Value after reset:
b15
b14
b13
b12
b11
b10
PRMO
D
—
—
—
—
—
0
0
0
0
0
0
b9
b8
PWEN PRENB
B
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
EWEN
B
—
—
WRMO
D
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
WRMOD
Write Access Mode Select
0: Byte strobe mode
1: Single write strobe mode.
R/W
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
EWENB
External Wait Enable
0: Disable
1: Enable.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
PRENB
Page Read Access Enable
0: Disable
1: Enable.
R/W
b9
PWENB
Page Write Access Enable
0: Disable
1: Enable.
R/W
b14 to b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
PRMOD
Page Read Access Mode Select
0: Normal access compatible mode
1: External data read continuous assertion mode.
R/W
Do not write to the CSnMOD register while access to the CSn area is in progress.
WRMOD bit (Write Access Mode Select)
The WRMOD bit selects a write access operating mode. Writing 0 selects the byte strobe mode where data writes are
controlled by the WRn signals (n = 0 and 1) associated with the respective byte positions. Writing 1 selects the single
write strobe mode where data writes are controlled by the BCn (n = 0 and 1) and the WR signals associated with the
respective byte positions.
Note:
Setting the external bus width to 8 bits is prohibited in single write strobe mode.
Table 15.6
Control signals for write access mode
Mode
Pin name
Write access mode
WR1
WR0/WR
BC1
BC0
Byte strobe mode
(WR0)
×
×
Single write strobe mode
×
(WR)
: Enabled, ×: Disabled
EWENB bit (External Wait Enable)
The EWENB bit enables external waits. Writing 0 disables the WAIT signal. Writing 1 selects external wait and allows
the WAIT signal to control the number of waits per cycle. In this state, wait cycles are inserted when the WAIT signal is
low.
PRENB bit (Page Read Access Enable)
The PRENB bit enables page read accesses.
Note:
When the address/data multiplexed I/O interface is selected with the MPXEN bit in CSnCR, the PRENB bit
should not be set to enable page read accesses. Page read accesses are not supported in the address/data
multiplexed I/O interface.
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15. Buses
PWENB bit (Page Write Access Enable)
The PWENB bit enables page write accesses.
Note:
When the address/data multiplexed I/O interface is selected with the MPXEN bit in CSnCR, the PWENB bit
should not be set to enable page write accesses. Page write accesses are not supported in the address/data
multiplexed I/O interface.
PRMOD bit (Page Read Access Mode Select)
The PRMOD bit selects the operating mode for page read accesses. Writing 0 selects normal access compatible mode
where the RD signal is negated and an RD assert wait is inserted each time a unit of data is read. When there is no RD
assert wait, the RD signal is negated only in the final transfer of the external bus access.
Writing 1 selects external data read continuous assertion mode, in which an RD assert wait is inserted and the RD signal
is continuously asserted during the wait.
15.3.5
CSn Wait Control Register 1 (CSnWCR1) (n = 0 to 3)
Address(es): BUS.CS0WCR1 4000 3004h, BUS.CS1WCR1 4000 3014h, BUS.CS2WCR1 4000 3024h, BUS.CS3WCR1 4000 3034h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
—
—
—
0
0
0
0
0
1
1
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
0
0
0
0
0
b24
b23
b22
b21
—
—
—
1
0
0
0
0
0
1
1
1
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
0
0
0
0
0
CSRWAIT[4:0]
CSPRWAIT[2:0]
1
1
1
b20
b19
b18
b17
b16
CSWWAIT[4:0]
CSPWWAIT[2:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CSPWWAIT[2:0]
Page Write Cycle Wait
Select*1
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b10 to b8
CSPRWAIT[2:0]
Page Read Cycle Wait
Select*2
b10
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Normal Write Cycle Wait
Select
b20
R/W
b20 to b16 CSWWAIT[4:0]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
b0
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
0: Wait with a length of 4 clock cycles are inserted
1: Wait with a length of 5 clock cycles are inserted
0: Wait with a length of 6 clock cycles are inserted
1: Wait with a length of 7 clock cycles are inserted.
b8
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
0: Wait with a length of 4 clock cycles are inserted
1: Wait with a length of 5 clock cycles are inserted
0: Wait with a length of 6 clock cycles are inserted
1: Wait with a length of 7 clock cycles are inserted.
0
0
0
0
0
0
1
1
b16
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
Set value = the n-bit number of clock cycles inserted
1 1 1 0 1: Wait with a length of 29 clock cycles are inserted
1 1 1 1 0: Wait with a length of 30 clock cycles are inserted
1 1 1 1 1: Wait with a length of 31 clock cycles are inserted.
b23 to b21 —
Reserved
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R/W
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Bit
Symbol
b28 to b24 CSRWAIT[4:0]
15. Buses
Bit name
Description
R/W
Normal Read Cycle Wait
Select
b28
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
b24
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
Set value = the n-bit number of clock cycles inserted
1 1 1 0 1: Wait with a length of 29 clock cycles are inserted
1 1 1 1 0: Wait with a length of 30 clock cycles are inserted
1 1 1 1 1: Wait with a length of 31 clock cycles are inserted.
b31 to b29 —
Note 1.
Note 2.
Reserved
These bits are read as 0. The write value should be 0.
R/W
The CSPWWAIT[2:0] value is only valid when the PWENB bit in CSnMOD is set to 1.
The CSPRWAIT[2:0] value is only valid when the PRENB bit in CSnMOD is set to 1.
Do not attempt to write the CSnWCR1 register while the external bus is being accessed. Set each of these bits to satisfy
the restrictions described in section 15.5.7 (1) Constraints on using separate bus interface or section 15.5.7 (2)
Constraints on using address/data multiplexed bus interface.
CSPWWAIT[2:0] bits (Page Write Cycle Wait Select)
The CSPWWAIT[2:0] bits specify the number of wait cycles to be inserted into the second and subsequent accesses
during a page write cycle. The setting is enabled when the PWENB bit in CSnMOD is set to 1.
Note:
The settings must satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value and CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value.
CSPRWAIT[2:0] bits (Page Read Cycle Wait Select)
The CSPRWAIT[2:0] bits specify the number of wait cycles to be inserted into the second and subsequent accesses
during a page read cycle. The setting is enabled when the PRENB bit in CSnMOD is set to 1.
Note:
The settings must satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSPRWAIT[2:0] value.
CSWWAIT[4:0] bits (Normal Write Cycle Wait Select)
The CSWWAIT[4:0] bits specify the number of wait cycles to be inserted into the first access during a normal write cycle
or page write cycle.
Note:
The settings must satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value and CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
CSRWAIT[4:0] bits (Normal Read Cycle Wait Select)
The CSRWAIT[4:0] bits specify the number of wait cycles to be inserted into the first access during a normal read cycle
or page read cycle.
Note:
The settings must satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSRWAIT[4:0] value.
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15.3.6
15. Buses
CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 3)
Address(es): BUS.CS0WCR2 4000 3008h, BUS.CS1WCR2 4000 3018h, BUS.CS2WCR2 4000 3028h, BUS.CS3WCR2 4000 3038h
b31
b30
—
b29
b28
CSON[2:0]
b27
b26
—
b25
b24
b23
WDON[2:0]
b22
—
b21
b20
WRON[2:0]
b19
b18
—
b17
b16
RDON[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
AWAIT[1:0]
—
0
0
Value after reset:
Value after reset:
0
0
0
WDOFF[2:0]
0
—
0
0
0
CSWOFF[2:0]
0
0
—
0
0
CSROFF[2:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CSROFF[2:0]
Read-Access CS Extension Cycle
Select
b2
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6 to b4
CSWOFF[2:0]
Write-Access CS Extension Cycle
Select
b6
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10 to b8
WDOFF[2:0]
Write Data Output Extension Cycle
Select
b10
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b13, b12
AWAIT[1:0]
Address Cycle Wait Select
b13 b12
R/W
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
0: Wait with a length of 4 clock cycles are inserted
1: Wait with a length of 5 clock cycles are inserted
0: Wait with a length of 6 clock cycles are inserted
1: Wait with a length of 7 clock cycles are inserted.
b4
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
0: Wait with a length of 4 clock cycles are inserted
1: Wait with a length of 5 clock cycles are inserted
0: Wait with a length of 6 clock cycles are inserted
1: Wait with a length of 7 clock cycles are inserted.
b8
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
0: Wait with a length of 4 clock cycles are inserted
1: Wait with a length of 5 clock cycles are inserted
0: Wait with a length of 6 clock cycles are inserted
1: Wait with a length of 7 clock cycles are inserted.
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles.
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b18 to b16
RDON[2:0]
RD Assert Wait Select
b18
R/W
b19
—
Reserved
This bit is read as 0. The write value should be 0.
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0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b16
0: No wait is inserted.
1: Wait with a length of 1 clock cycle is inserted.
0: Wait with a length of 2 clock cycles are inserted.
1: Wait with a length of 3 clock cycles are inserted.
0: Wait with a length of 4 clock cycles are inserted.
1: Wait with a length of 5 clock cycles are inserted.
0: Wait with a length of 6 clock cycles are inserted.
1: Wait with a length of 7 clock cycles are inserted.
R/W
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15. Buses
Bit
Symbol
Bit name
Description
R/W
b22 to b20
WRON[2:0]
WR Assert Wait Select
b22
R/W
b23
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b26 to b24
WDON[2:0]
Write Data Output Wait Select
b26
R/W
b27
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b30 to b28
CSON[2:0]
CS Assert Wait Select
b30
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b20
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
0: Wait with a length of 4 clock cycles are inserted
1: Wait with a length of 5 clock cycles are inserted
0: Wait with a length of 6 clock cycles are inserted
1: Wait with a length of 7 clock cycles are inserted.
b24
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
0: Wait with a length of 4 clock cycles are inserted
1: Wait with a length of 5 clock cycles are inserted
0: Wait with a length of 6 clock cycles are inserted
1: Wait with a length of 7 clock cycles are inserted.
b28
0: No wait is inserted
1: Wait with a length of 1 clock cycle is inserted
0: Wait with a length of 2 clock cycles are inserted
1: Wait with a length of 3 clock cycles are inserted
0: Wait with a length of 4 clock cycles are inserted
1: Wait with a length of 5 clock cycles are inserted
0: Wait with a length of 6 clock cycles are inserted
1: Wait with a length of 7 clock cycles are inserted.
R/W
Do not attempt to write the CSnWCR2 register while the external bus is being accessed. Set each of these bits to satisfy
the restrictions described in section 15.5.7 (1), Constraints on using separate bus interface or section 15.5.7 (2)
Constraints on using address/data multiplexed bus interface.
CSROFF[2:0] bits (Read-Access CS Extension Cycle Select)
The CSROFF[2:0] bits specify the number of wait cycles to be inserted during the period from the end of a wait cycle
(RD signal negated) until the CSn signal (n = 0 to 3) is negated in read access mode.
CSWOFF[2:0] bits (Write-Access CS Extension Cycle Select)
The CSWOFF[2:0] bits specify the number of wait cycles to be inserted during the period from the end of a wait cycle
(WRn signal (n = 0 and 1) negated) until the CSn signal (n = 0 to 3) is negated in write access mode.
Note:
The settings must satisfy CSnWCR2.WDOFF[2:0] value ≤ CSnWCR2.CSWOFF[2:0] value.
WDOFF[2:0] bits (Write Data Output Extension Cycle Select)
The WDOFF[2:0] bits specify the number of wait cycles to be inserted during the period from the end of a wait cycle
(WRn signal (n = 0 and 1) negated) until the write data output is complete in write access mode.
Note:
The settings must satisfy CSnWCR2.WDOFF[2:0] value ≤ CSnWCR2.CSWOFF[2:0] value.
AWAIT[1:0] bits (Address Cycle Wait Select)
The AWAIT[1:0] bits specify the number of wait cycles to be inserted into an address output cycle with the address/data
multiplexed I/O interface.
Note:
CSnWCR2.CSON[2:0] value ≤ CSnWCR2.AWAIT[1:0] value.
For read access, the settings must satisfy CSnWCR2.AWAIT[1:0] value + 2 ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSRWAIT[4:0] value.
For write access, the settings must satisfy CSnWCR2.AWAIT[1:0] value + 2 ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value and CSnWCR2.AWAIT[1:0] value + 2 ≤ CSnWCR2.WDON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
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15. Buses
RDON[2:0] bits (RD Assert Wait Select)
The RDON[2:0] bits specify the number of wait cycles to be inserted before the RD signal is asserted.
Note:
For normal read access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSRWAIT[4:0] value.
For page read access, the settings must satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSPRWAIT[2:0] value.
When the address/data multiplexed I/O interface is selected, the settings must satisfy CSnWCR2.AWAIT[1:0]
value + 2 ≤ CSnWCR2.RDON[2:0] value ≤ CSnWCR1.CSRWAIT[4:0] value.
WRON[2:0] bits (WR Assert Wait Select)
The WRON[2:0] bits specify the number of wait cycles to be inserted before the WRn signal (n = 0 to 1) is asserted.
Note:
For normal write access, the settings must satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0]
value ≤ CSnWCR1.CSWWAIT[4:0] value and CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
For page write access, the settings must satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value
≤ CSnWCR1.CSPWWAIT[2:0] value and CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value.
When the address/data multiplexed I/O interface is selected, the settings must satisfy CSnWCR2.AWAIT[1:0]
value + 2 ≤ CSnWCR2.WRON[2:0] value ≤ CSnWCR1.CSWWAIT[4:0] value.
WDON[2:0] bits (Write Data Output Wait Select)
The WDON[2:0] bits specify the number of wait cycles to be inserted before the write data is output.
Note:
For normal write access, the settings must satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0]
value ≤ CSnWCR1.CSWWAIT[4:0] value.
For page write access, the settings must satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value
≤ CSnWCR1.CSPWWAIT[2:0] value.
When the address/data multiplexed I/O interface is selected, the settings must satisfy CSnWCR2.AWAIT[1:0]
value + 2 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR1.CSWWAIT[4:0] value.
CSON[2:0] bits (CS Assert Wait Select)
The CSON[2:0] bits specify the number of wait cycles to be inserted before the CSn signal (n = 0 to 3) is asserted.
Note:
For normal read access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSRWAIT[4:0] value.
For page read access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSPRWAIT[2:0] value.
For normal write access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
For page write access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value.
When the address/data multiplexed I/O interface is selected, the settings must satisfy CSnWCR2.CSON[2:0]
value ≤ CSnWCR2.AWAIT[1:0] value.
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15.3.7
15. Buses
Master Bus Control Register (BUSMCNT)
Address(es): BUS.BUSMCNTM4I 4000 4000h, BUS.BUSMCNTM4D 4000 4004h, BUS.BUSMCNTSYS 4000 4008h,
BUS.BUSMCNTDMA 4000 400Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
IERES
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
b14 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b15
IERES
Ignore Error Responses
0: A bus error is reported
1: A bus error is not reported.
Note:
R/W
R/W
Changing the reserved bit value from the initial value of 0 is prohibited. Operation during the change is not guaranteed.
IERES bit (Ignore Error Responses)
The IERES bit enables or disables the error response of the AHB-Lite protocol.
Table 15.7 lists the registers associated with each bus type.
Table 15.7
Relation between bus type and register
Bus type
Master Bus
Control Register
Slave Bus
Control Register
Bus Error Address
Register
Bus Error Status
Register
ICode bus (CPU)
BUSMCNTM4I
-
BUS1ERRADD
BUS1ERRSTAT
DCode bus (CPU)
BUSMCNTM4D
-
BUS2ERRADD
BUS2ERRSTAT
SYSTEM bus (CPU)
BUSMCNTSYS
-
BUS3ERRADD
BUS3ERRSTAT
DMA bus
BUSMCNTDMA
-
BUS4ERRADD
BUS4ERRSTAT
Memory bus 1
-
BUSSCNTFLI
-
-
Memory bus 3
-
BUSSCNTMBIU
-
-
Memory bus 4
-
BUSSCNTRAM0
-
-
Memory bus 5
-
BUSSCNTRAM1
-
-
Internal peripheral bus 1, 3,
4, 5, 7
-
BUSSCNTPnB
[n = 0, 2, 3, 4, 6]
-
-
Internal peripheral bus 9
-
BUSSCNTFBU
-
-
External bus (CS area)
-
BUSSCNTEXT
-
-
External bus (QSPI area)
-
BUSSCNTEXT2
-
-
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15.3.8
15. Buses
Slave Bus Control Register (BUSSCNT)
Address(es): BUS.BUSSCNTFLI 4000 4100h, BUS.BUSSCNTMBIU 4000 4108h, BUS.BUSSCNTRAM0 4000 410Ch,
BUS.BUSSCNTRAM1 4000 4110h, BUS.BUSSCNTP0B 4000 4114h, BUS.BUSSCNTP2B 4000 4118h,
BUS.BUSSCNTP3B 4000 411Ch, BUS.BUSSCNTP4B 4000 4120h, BUS.BUSSCNTP6B 4000 4128h,
BUS.BUSSCNTFBU 4000 4130h, BUS.BUSSCNTEXT 4000 4134h, BUS.BUSSCNTEXT2 4000 4138h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
Value after reset:
b5
b4
ARBMET[1:0]
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b5, b4
ARBMET[1:0]
Arbitration Method
Specify the priority between groups:
R/W
b5 b4
0 0: Fixed priority
0 1: Round-robin
1 0: Setting prohibited
1 1: Setting prohibited.
b15 to b6
Note:
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Changing a reserved bit from the initial value of 0 is prohibited. Operation during the change is not guaranteed.
ARBMET[1:0] bits (Arbitration Method)
The ARBMET[1:0] bits specify the priority of each bus master. For fixed priority, see Table 15.8. For round-robin, see
Table 15.9.
Table 15.7 lists the registers associated with each bus type.
Table 15.8
Fixed priority (ARBMET[1:0] = 00b)
Slave Bus Control Register
Slave interface
Priority order
BUSSCNTFLI
Memory bus 1
Memory bus 3 > DCode bus (CPU) >
ICode bus (CPU)
BUSSCNTRAM0
Memory bus 4
DMA bus > system bus (CPU)
BUSSCNTRAM1
Memory bus 5
DMA bus > system bus (CPU)
BUSSCNTPnB [n = 0, 2, 3, 4, 6]
Internal peripheral bus 1, 3, 4, 5, 7
DMA bus > system bus (CPU)
BUSSCNTFBU
Internal peripheral bus 9
DMA bus > system bus (CPU)
BUSSCNTEXT
External bus (CS area)
DMA bus > system bus (CPU)
BUSSCNTEXT2
External bus (QSPI area)
DMA bus > system bus (CPU)
Table 15.9
Round-Robin priority (ARBMET[1:0] = 01b)
Slave Bus Control Register
Slave interface
Priority order*1
BUSSCNTFLI
Memory bus 1
Memory bus 3 ↔ DCode bus (CPU) ↔ ICode
bus (CPU)
BUSSCNTRAM0
Memory bus 4
DMA bus ↔ system bus (CPU)
BUSSCNTRAM1
Memory bus 5
DMA bus ↔ system bus (CPU)
BUSSCNTPnB (n = 0, 2, 3, 4, 6)
Internal peripheral bus 1, 3, 4, 5, 7
DMA bus ↔ system bus (CPU)
BUSSCNTFBU
Internal peripheral bus 9
DMA bus ↔ system bus (CPU)
BUSSCNTEXT
External bus (CS area)
DMA bus ↔ system bus (CPU)
BUSSCNTEXT2
External bus (QSPI area)
DMA bus ↔ system bus (CPU)
Note 1. Round-robin priority is denoted by “↔.”
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15.3.9
15. Buses
Bus Error Address Register (BUSnERRADD) (n = 1 to 4)
Address(es): BUS.BUS1ERRADD 4000 4800h, BUS.BUS2ERRADD 4000 4810h,
BUS.BUS3ERRADD 4000 4820h, BUS.BUS4ERRADD 4000 4830h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BERAD[31:16]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
BERAD[15:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
BERAD[31:0]
Bus Error Address
When a bus error occurs, these bits store the error
address
R
Note:
This register is cleared only by resets other than MPU related resets. For more information, see section 6, Resets and section
16, Memory Protection Unit (MPU).
Table 15.7 lists the registers associated with each bus type.
BERAD[31:0] bits (Bus Error Address)
The BERAD[31:0] bits store the accessed address when a bus error occurs. For more information, see
BUSnERRSTAT.ERRSTAT and section 15.6, Bus Error Monitoring Section.
A value of the BUSnERRADD.BERAD[31:0] bits (n = 1 to 4) is only valid when the BUSnERRSTAT.ERRSTAT bit (n
= 1 to 4) is set to 1.
15.3.10
Bus Error Status Register (BUSnERRSTAT) (n = 1 to 4)
Address(es): BUS.BUS1ERRSTAT 4000 4804h, BUS.BUS2ERRSTAT 4000 4814h,
BUS.BUS3ERRSTAT 4000 4824h, BUS.BUS4ERRSTAT 4000 4834h
b7
b6
b5
b4
b3
b2
b1
b0
ERRST
AT
—
—
—
—
—
—
ACCST
AT
0
0
0
0
0
0
0
x
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
ACCSTAT
Error Access Status
Access status when the error occurred:
1: Write access
0: Read access.
R
b6 to b1
—
Reserved
These bits are read as 0
R
b7
ERRSTAT
Bus Error Status
0: No bus error occurred
1: Bus error occurred.
R
Note:
This register is cleared only by resets other than MPU-related resets. For more information, see section 6, Resets and section
16, Memory Protection Unit (MPU).
Table 15.7 lists the registers associated with each bus type.
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15. Buses
ACCSTAT bit (Error Access Status)
The ACCSTAT bit indicates the access status, write access or read access, when an error occurs on the associated bus.
For more information, see the BUSnERRSTAT.ERRSTAT bit and section 15.6, Bus Error Monitoring Section.
The value is valid only when BUSnERRSTAT.ERRSTAT (n = 1 to 4) is set to 1.
ERRSTAT bit (Bus Error Status)
The ERRSTAT bit indicates whether a bus error occurred. When an error occurs on the associated bus, the access address
and status of write or read access are stored. The BUSnERRSTAT.ERRSTAT bit (n = 1 to 4) is set to 1.
Four types of errors can occur on each bus:
Illegal address access
Bus master MPU error
Bus slave MPU error
Time out.
When detecting bus master MPU errors or bus slave MPU errors, and reset is selected in the respective OAD bit,
BUSnERRSTAT.ERRSTAT (n = 1 to 4) is not set to 1 if the bus access causing the MPU error completes later than the
internal reset signal being generated, which can occur depending on the wait setting.
When detecting bus master MPU errors or bus slave MPU errors, and the non-maskable interrupt selected in the
respective OAD bit, BUSnERRSTAT.ERRSTAT (n = 1 to 4) is set to 1 after the bus access causing the MPU error
completes.
For more information on errors that occur on each bus, see section 15.6, Bus Error Monitoring Section, and section 16,
Memory Protection Unit (MPU).
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15.4
15. Buses
Endianness and Data Alignment
The external bus has a data alignment function to control which byte of the data bus (D15 to D08, or D07 to D00) is used
when accessing the external address space (the CS area). Alignment is based on the bus specifications of the area to be
accessed (8-bit or 16-bit bus space), the data size, and the endian order.
15.4.1
(1)
Data Alignment Control for the CS Areas
16-bit bus space
When a 16-bit bus space is selected in the BSIZE[1:0] bits in CSnCR, address buses A23 to A01 are enabled to output
address signals in 16-bit units, and the address bus A00 is disabled (always outputting low).
When byte strobe mode is selected (WRMOD = 0 in CSnMOD), the WR0 and WR1 pins are enabled. The BC0 and BC1
pins are not used.
When single write strobe mode is selected (WRMOD = 1 in CSnMOD), only the WR0 pin is enabled, and it always
outputs low during write access, regardless of the data size. The WR1 pin is invalid (always outputs high). The valid byte
position is indicated by the BC0 and BC1 pins.
The valid positions of control signals and data external to the chip differ according to the endian order. See Figure 15.3
and Figure 15.4.
Page access can occur for accesses to data in 32-bit units. Page access can only occur when an access does not extend
over a 32-bit boundary and causes no change in the BC0 and BC1 signals. The situations in which page access occurs are
indicated by the letter (p) in Figure 15.3 and Figure 15.4.
WR1/BC1
WR0/BC0
RD
Data size
8 bits
16 bits
32 bits
Accessed
address
Number of
accesses
Bus cycle
Unit of
data
Address
4n
One
First
8 bits
4n
4n+1
One
First
8 bits
4n
4n+2
One
First
8 bits
4n+2
4n+3
One
First
8 bits
4n+2
4n
One
First
16 bits
4n
4n+2
One
First
16 bits
4n+2
15
8 7
0
First
16 bits
4n
15
8 7
0
Second
16 bits
4n+2
31
24 23
4n
Two
D15
D00
7
0
7
0
7
0
15
8 7
0
7
(p)
Data bus
D08 D07
0
16
(p): Page access (only when page access is enabled with the PRENB and PWENB bits in CSnMOD)
Figure 15.3
Data alignment in 16-bit bus space with little-endian order
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15. Buses
WR1/BC1
WR0/BC0
RD
Data size
8 bits
16 bits
32 bits
Accessed
address
Number of
accesses
Bus cycle
Unit of
data
Address
4n
One
First
8 bits
4n
4n+1
One
First
8 bits
4n
4n+2
One
First
8 bits
4n+2
4n+3
One
First
8 bits
4n+2
4n
One
First
16 bits
4n
15
4n+2
One
First
16 bits
4n+2
4n
Two
First
16 bits
4n
Second
16 bits
4n+2
D15
(p)
Data bus
D08 D07
7
0
7
0
D00
7
0
7
0
8 7
0
15
8 7
0
31
24 23
16
15
8 7
0
(p): Page access (only when page access is enabled with the PRENB and PWENB bits in CSnMOD)
Figure 15.4
(2)
Data alignment in 16-bit bus space with big-endian order
8-Bit bus space
When an 8-bit bus space is selected in the BSIZE[1:0] bits in CSnCR, the address buses A23 to A00 are enabled to
output address signals in byte units.
In 8-bit bus space, only the WR0 pin is valid, regardless of the write access mode, and it always outputs low during write
access. The WR1 pin and the BC0 pin are not used.
The valid positions of data external to the chip are D07 to D00, and WR0 is used as the control signal, regardless of the
endian mode. See Figure 15.5 and Figure 15.6.
Page access can occur for accesses to data in 16-bit or 32-bit units. Page access can only occur when an access does not
extend over a 32-bit boundary. The situations in which page access occurs are indicated by the letter (p) in Figure 15.5
and Figure 15.6.
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15. Buses
WR1/BC1
WR0/BC0
RD
Data size
8 bits
Accessed
address
Number of
accesses
Bus cycle
Unit of
data
4n
One
First
8 bits
4n
7
0
4n+1
One
First
8 bits
4n+1
7
0
4n+2
One
First
8 bits
4n+2
7
0
4n+3
One
First
8 bits
4n+3
7
0
4n
Two
First
8 bits
4n
Second
8 bits
4n+1
4n+2
Two
First
8 bits
4n+2
Second
8 bits
4n+3
16 bits
32 bits
4n
Four
Address
D15
Data bus
D08 D07
D00
7
0
(p)
15
8
7
0
(p)
15
8
7
0
First
8 bits
4n
Second
8 bits
4n+1
(p)
15
8
Third
8 bits
4n+2
(p)
23
16
Fourth
8 bits
4n+3
(p)
31
24
(p): Page access (only when page access is enabled with the PRENB and PWENB bits in CSnMOD)
Figure 15.5
Data alignment in 8-bit bus space with little-endian order
WR1/BC1
WR0/BC0
RD
Data size
8 bits
Access
address
Number of
accesses
Bus cycle
Address
D15
Data bus
D08 D07
D00
4n
One
First
8 bits
4n
7
0
4n+1
One
First
8 bits
4n+1
7
0
4n+2
One
First
8 bits
4n+2
7
0
4n+3
One
First
8 bits
4n+3
7
0
4n
Two
First
8 bits
4n
15
8
16 bits
4n+2
32 bits
Unit of
data
4n
Two
Four
Second
8 bits
4n+1
First
8 bits
4n+2
Second
8 bits
4n+3
First
8 bits
4n
(p)
(p)
7
0
15
8
7
0
31
24
Second
8 bits
4n+1
(p)
23
16
Third
8 bits
4n+2
(p)
15
8
Fourth
8 bits
4n+3
(p)
7
0
(p): Page access (only when page access is enabled with the PRENB and PWENB bits in CSnMOD)
Figure 15.6
Data alignment in 8-bit bus space with big-endian order
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15.5
15. Buses
Operation of CS Area Controller
15.5.1
Separate Bus
This section describes the periods shown in the timing diagrams. The CS area controller (CSC) operates in
synchronization with the external bus clock, BCLK. Operation cycles, such as wait cycles, specified in the CSC register,
are counted on BCLK. In the following description, the frequencies of BCLK and EBCLK pin outputs are the same,
unless otherwise noted. Access through the external bus starts at the same point as the output of a rising edge on the
EBCLK pin. However, if the external bus clock, BCLK and the output on the EBCLK pin are at different frequencies, the
wait settings can cause the start of access for the second and subsequent rounds to coincide with the falling edge of the
output on the EBCLK pin. See Figure 15.12 to Figure 15.16. If recovery cycles are inserted for bus access, the setting for
the number of recovery cycles can also cause the start of access for the second and subsequent rounds to coincide with
the falling edge of the output on the EBCLK pin. See Figure 15.34.
(a)
Tw1 to Twn (clock cycles for waiting for a normal read cycle or normal write cycle)
The period Tw1 to Twn is the number of clock cycles from the start of access through the external bus clock to 1 cycle
before the strobe signal is valid. The number of cycles is selectable from 0 to 31. Within this period, the timing of CSn,
RD, and WRn assertion (placing the signals low) is determined by the respective wait settings. The wait periods are
controlled by the CS assert wait select bits (CSON), the RD assert wait select bits (RDON), the WR assert wait select bits
(WRON), and the write data output wait select bits (WDON) in the CSn Wait Control Register 2 (CSnWCR2). The
number of clock cycles for each of these periods of waiting is selectable as a value from 0 to 7, counted from the start of
external bus access. The selectable numbers of cycles is also within the overall number of clock cycles required for
waiting to read or write.
(b)
Tend (clock cycle where the strobe signal is valid)
Tend is the next clock cycle after completion of the wait period for a normal cycle of read or write or for a cycle of page
reading or page writing. If the wait select bit for a normal cycle of read or write or for a cycle of page reading or page
writing is 0, bus access starts on the clock cycle where the strobe signal is valid. The RD and WRn signals are negated in
the next clock cycle. For a read access, the clock cycle where the strobe signal is valid is where the data to be read is
sampled. If an external wait is enabled, the wait signal is sampled on the cycle where the strobe signal is valid. The bus
cycle is extended if the wait signal is low. The bus cycle completes in the next clock cycle if the wait signal is high. Tend
indicates the cycle where sampling of the wait signal starts.
After the first cycle where the strobe signal is valid during page access, second and subsequent page access operations
(see section (e), Tpw1 to Tpwn (page-read cycle wait or page-write cycle wait)) start in the next cycle, except during
write access with a setting other than 0 for write-data output extension clock cycles (see section (d), Tdw1 to Tdwn
(clock cycles for write-data output extension)). If the setting for the RD or WR assertion wait is any value other than 0,
the RD and WRn signals are negated in the next clock cycle. If the setting is 0, assertion continues. Additionally, the CSn
signal continues to be asserted rather than negated.
(c)
Tn1 to Tnm (clock cycles of CS extension)
For normal access, Tn1 to Tnm represent the clock cycles of the period following the cycle where the strobe signal is
valid (Tend) up to negation of the CSn signal. For read or write access, the negation timing can be controlled by the readaccess CS Extension Cycle Select bits (CSROFF) and the write-access CS Extension Cycle Select bits (CSWOFF) in the
CSn Wait Control Register 2 (CSnWCR2). The number of cycles is counted from the cycle following the cycle where the
strobe signal is valid.
For page access, Tn1 to Tnm represent the clock cycles of the period following the last cycle where the strobe signal is
valid up to negation of the CSn signal.
For write access, setting the write data output extension cycle select bits (WDOFF) controls extension of the period
where the address and output data is valid.
(d)
Tdw1 to Tdwn (clock cycles for write-data output extension)
For write access, if the wait setting for the write-data output extension is any value other than 0, the specified clock
cycles are inserted from the cycle following the cycle where the strobe signal is valid (Tend).
For normal access, this is inserted within the clock period for CS extension (see section (c), Tn1 to Tnm (clock cycles of
CS extension)).
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15. Buses
For page access, this period is inserted within the clock cycle period where the strobe signal is valid and subsequent page
accesses, or within the clock cycle period for the CS extension (see section (c), Tn1 to Tnm (clock cycles of CS
extension)). Valid address and data output are extended over this period, and the WRn signal is negated.
(e)
Tpw1 to Tpwn (page-read cycle wait or page-write cycle wait)
For the second and subsequent bus cycles during page access, the values for a page-read cycle wait or page-write cycle
wait are used instead of the settings for a normal read or write cycle wait. The settings in the WR Assert Wait Select bits
become enabled in the same way as for the first access. The RD assertion control operation depends on the page read
access mode setting (the PRMOD bit in CSnMOD) as follows:
CSnMOD.PRMOD = 0: A wait for RD assertion is inserted in the same way as for the first access, and the RD signal is
negated.
CSnMOD.PRMOD = 1: Although a wait for RD assertion is inserted in the same way as for normal-access compatibility
mode, the RD signal continues to be asserted over this period.
(f)
Tr1 to Trn (recovery cycles)
Recovery cycles can be inserted from the point where a bus cycle is complete (CSn signal negation). The number of
recovery cycles can be controlled by setting the read recovery (RRCV) or write recovery (WRCV) bits in the CSn
Recovery Cycle Register (CSnREC). Both numbers of recovery cycles are counted from the end of a bus cycle (CSn
negation) and can be selected from 0 to 15 cycles. For more information, see section 15.5.4, Insertion of Recovery
Cycles.
(1)
Normal access
When the PRENB and PWENB bits in CSnMOD are set to 0 to disable page-read and page-write access, all bus accesses
take the form of normal read and write operations. Even when the PRENB and PWENB bits in CSnMOD are set to 1 to
enable page read and page write access, bus access other than page access takes the form of normal read and write
operations. Figure 15.7 to Figure 15.9 show the normal access operations.
Next bus access can be started*1
Tw1
External bus clock
(BCLK)
Tw2
...
Twn
Tn1
...
Tnm
Read-access CS extension cycle (CSROFF)
Normal read cycle wait (CSRWAIT)
Address
(A23 to A00)
Tend
A
CS assert wait (CSON)
Chip select
(CSn)
Byte control
(BCm)
RD assert wait (RDON)
Data read
(RD)
Data bus
(D15 to D00)
D
: Indicates the sampling point.
Note 1.
Figure 15.7
When CSnWCR2.CSROFF[2:0] = 000b, the next round of bus access can start 1 cycle later.
Bus timing for normal read operation (n = 0 to 3; m = 0, 1)
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15. Buses
Next bus access can be started
Tw1
External bus clock
(BCLK)
Tw2
...
Twn
Tn1
...
Tnm
Write-access CS extension cycle (CSWOFF)
Normal write cycle wait (CSWWAIT)
Address
(A23 to A00)
Tend
A
CS assert wait (CSON)
Chip select
(CSn)
Byte control
(BCm)
WR assert wait (WRON)
Data write
(WR)
Write data output wait (WDON)
Write data output extension cycle (WDOFF)
Data bus
(D15 to D00)
Figure 15.8
D
Bus timing for normal write operation in single write strobe mode (n = 0 to 3; m = 0, 1)
Tw1
Tw2
Tend
Tn1
Tw1
Tw2
Tend
Tn1
External bus clock
(BCLK)
Address
(A23 to A00)
A1
A2
Normal write cycle wait (CSWWAIT): 2
Normal read cycle wait (CSRWAIT): 2
Chip select/byte
control
(CSn/BCm)
Read-access CS extension
cycle (CSROFF): 1
CS assert wait (CSON): 0
Write-access CS extension cycle
(CSWOFF): 1
RD assert wait (RDON): 1
Data read
(RD)
Data write
(WR)
WR assert wait (WRON): 1
Write data output extension cycle (WDOFF): 1
Write data output wait (WDON): 1
Data bus
(D15 to D00)
D1
D2
: Indicates the sampling point.
Figure 15.9
Example of normal access operation for read and write (n = 0 to 3; m = 0, 1)
When two or more rounds of external bus access are required in response to a single request for transfer from a bus
master, normal access operations are repeated. See section (a), Tw1 to Twn (clock cycles for waiting for a normal read
cycle or normal write cycle) to section (d), Tdw1 to Tdwn (clock cycles for write-data output extension). Figure 15.10
and Figure 15.11 show examples of operations when two rounds of bus access are generated in response to a single
transfer request. If the recovery cycle insertion condition is satisfied, recovery cycles (section (f), Tr1 to Trn (recovery
cycles)) are also inserted in the second and subsequent external bus accesses. See Figure 15.32.
The values in the wait control registers shown in the figures are example settings. In your application, set the register bits
according to the specifications of connected devices.
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15. Buses
Tw1
Tw2
Tend
Tn1
Tw1
Tend
Tw2
Tn1
External bus clock
(BCLK)
Normal read cycle wait (CSRWAIT): 2
Address
(A23 to A00)
A2
A1
Read-access CS extension
cycle (CSROFF): 1
Chip select
(CSn)
CSRWAIT: 2
CSROFF: 1
Byte control
(BCm)
RD assert wait (RDON): 1
RDON: 1
Data read
(RD)
Data bus
(D15 to D00)
D2
D1
CS assert wait (CSON): 0
: Indicates the sampling point.
Figure 15.10
Example of normal read operation when two rounds of bus access are generated in response to a
single transfer request (n = 0 to 3; m = 0, 1)
Tw1
Tw2
Tend
Tn1
Tw1
Tw2
Tend
Tn1
External bus clock
(BCLK)
CSWWAIT: 2
Normal write cycle wait (CSWWAIT): 2
Address
(A23 to A00)
A1
A2
Write-access CS extension cycle (CSWOFF): 1
Chip select
(CSn)
CSWOFF: 1
Byte control
(BCm)
WR assert wait (WRON): 1
WRON: 1
Write data output wait (WDON): 1
WDON: 1
Data write
(WR)
Data bus
(D15 to D00)
D1
WDOFF: 1
D2
Write data output extension cycle (WDOFF): 1
CS assert wait (CSON): 0
Figure 15.11
Example of normal write operation when two rounds of bus access are generated in response to
a single transfer request in single write strobe mode (n = 0 to 3; m = 0, 1)
Figure 15.12 to Figure 15.16 show examples of normal accesses made with BCLK/2 selected in the EBCLK Pin Output
Select bit.
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15. Buses
Tw1
Tw2
Tend
Tn1
Tn2
Tw1
Tw2
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A23 to A00)
Chip select
(CSn)
A1
A2
Read-access CS extension Normal write cycle wait Write-access CS extension cycle
(CSWOFF): 1
(CSWWAIT): 2
cycle (CSROFF): 2
Normal read cycle wait
(CSRWAIT): 2
Byte control
(BCm)
RD assert wait (RDON): 1
Data read
(RD)
Data write
(WR)
WR assert wait (WRON): 1
Write data output extension cycle
(WDOFF): 1
Write data output wait
(WDON): 1
Data bus
(D15 to D00)
D1
D2
CS assert wait (CSON): 0
: Indicates the sampling point.
Figure 15.12
Example of normal access when BCLK/2 is selected with the EBCLK Pin Output Select bit (n = 0
to 3; m = 0, 1)
Tw1
Tw2
Tw3
Tend
Tn1
Tw1
Tw2
Tw3
Tend
Tn1
EBCLK pin
output
External bus clock
(BCLK)
Address
(A23 to A00)
A1
Normal read cycle wait (CSRWAIT): 3
A2
Read-access CS extension
cycle (CSROFF): 1
CSRWAIT: 3
CSROFF: 1
Chip select
(CSn)
CS assert wait (CSON): 1
CSON: 1
Byte control
(BCm)
RD assert wait (RDON): 2
RDON: 2
Data read
(RD)
Data bus
(D15 to D00)
D1
D2
: Indicates the sampling point.
Figure 15.13
Example of normal-read operation when BCLK/2 is selected with the EBCLK pin output select bit
(n = 0 to 3, m = 0, 1)
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15. Buses
Tw1
Tw2
Tw3
Tend
Tn1
Tw1
Tw2
Tw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A23 to A00)
A1
Normal write cycle wait (CSWWAIT): 3
Chip select
(CSn)
A2
Write-access CS extension
cycle (CSWOFF): 1
CS assert wait (CSON): 1
CSWWAIT: 3
CSWOFF : 1
CSON: 1
Byte control
(BCm)
WR assert wait (WRON): 2
WRON: 2
Data write
(WR)
Write data output extension
cycle (WDOFF): 1
Write data output wait (WDON): 2
Data bus
(D15 to D00)
Figure 15.14
WDOFF: 1
WDON: 2
D2
D1
Example of normal-write operation when BCLK/2 is selected with the EBCLK pin output select bit
(n = 0 to 3; m = 0, 1)
Tw1
Tw2
Tw3
Tend
Tn1
Tw1
Tw2
Tw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A23 to A00)
A1
Normal read cycle wait
(CSRWAIT): 3
A2
Read-access CS extension
cycle (CSROFF): 1
CSRWAIT: 3
CSROFF: 1
Chip select
(CSn)
CSON: 1
CS assert wait (CSON): 1
Byte control
(BCm)
RD assert wait (RDON): 2
RDON: 2
Data read
(RD)
Data bus
(D15 to D00)
D1
D2
: Indicates the sampling point.
Figure 15.15
Example of normal-read operation when BCLK/2 is selected with the EBCLK pin output select bit
and two rounds of bus access are generated in response to a single transfer request (n = 0 to 3;
m = 0, 1)
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15. Buses
Tw1
Tw2
Tw3
Tend
Tn1
Tw1
Tw2
Tw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A23 to A00)
A2
A1
Write-access CS
Normal write cycle wait extension cycle
(CSWWAIT): 3 (CSWOFF): 1
CSWWAIT: 3
CSWOFF: 1
Chip select
(CSn)
CS assert wait (CSON): 1
CSON: 1
Byte control
(BCm)
WR assert wait (WRON): 2
WRON: 2
Data write
(WR)
Write data output wait (WDON): 2
Data bus
(D15 to D00)
Figure 15.16
(2)
Write data output extension
WDON: 2
cycle (WDOFF): 1
D1
WDOFF: 1
D2
Example of normal-write operation when BCLK/2 is selected with the EBCLK pin output select bit
and two rounds of bus access are generated in response to a single transfer request (n = 0 to 3;
m = 0, 1)
Page access
When the PRENB and PWENB bits in CSnMOD are set to 1 to enable page read and page write access, the bus access
for page access operations becomes page reading and writing. Page access can only occur when two or more rounds of
external bus access are required for a single transfer request from the bus master. See Figure 15.3 to Figure 15.6 for the
conditions under which page access occurs.
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Figure 15.17 and Figure 15.18 show examples of page access operations.
Next bus access can be started
Tw1
...
Tw2
Twn
Tend
Tpw1
...
Tpwn
Tn1
Tend
Tnm
External bus clock
(BCLK)
Normal read cycle wait (CSRWAIT)
Address
(A23 to A00)
Read-access CS extension cycle
(CSROFF)
Page read cycle wait (CSPRWAIT)
A0
A1
CS assert wait (CSON)
Chip select
(CSn)
Byte control
(BCm)
RD assert wait (RDON)
Data read
(RD)
RD assert wait (RDON)*1
Data bus
(D15 to D00)
D0
D1
: Indicates the sampling point.
Note 1.
The RD assert wait operation in the second and subsequent bus accesses depends on the page read
access mode setting.
Figure 15.17
Page read access timing (n = 0 to 3; m = 0, 1)
Next bus access can be started
Tw1
Tw2
...
Twn
Tend
Tdw1
Tdwn Tpw1 Tpwn
Tend
Tn1
...
Tnm
External bus clock
(BCLK)
Normal write cycle wait (CSWWAIT)
Address
(A23 to A00)
Write-access CS extension cycle
Page write cycle wait (CSPWWAIT) (CSWOFF)
A0
A1
CS assert wait (CSON)
Chip select
(CSn)
Byte control
(BCm)
WR assert wait (WRON)
WR assert wait (WRON)
Data write
(WR)
Write data output extension cycle (WDOFF)
Write data output extension cycle
(WDOFF)
Data bus
(D15 to D00)
Write data output wait (WDON)
Figure 15.18
Write data output wait (WDON)
Page write access timing (n = 0 to 3; m = 0, 1)
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Figure 15.19 and Figure 15.20 show examples of operations for access to a 16-bit bus space in 32 bits. The values of the
wait control registers shown in the figures are example settings. In your application, set the registers according to the
specifications of connected devices.
CSRWAIT: 4
CSPRWAIT: 3
Tw1
Tend
Tpw1
Tend
Tn1
External bus clock
(BCLK)
Address
(A23 to A00)
A0
A1
Chip select
(CSn)
CSROFF: 1
Byte control
(BC1, BC0)
Data read
(RD)
RDON: 1
RDON: 1
Data bus
(D15 to D00)
D0
D1
: Indicates the sampling point.
Figure 15.19
Example of page read access operation when 16-bit bus space is accessed in 32 bits (n = 0 to 3)
CSWWAIT: 4
CSPWWAIT: 4
Tw1
Tend
Tdw1
Tpw1
Tend
Tn1
External bus clock
(BCLK)
Address
(A23 to A00)
A1
A0
CSWOFF: 1
Chip select
(CSn)
Byte control
(BC1, BC0)
Data write
(WR)
WRON: 1
WRON: 1
WDON: 1
Data bus
(D15 to D00)
D0
WDON: 1
Figure 15.20
D1
WDOFF: 1
WDOFF: 1
Example of page write access operation when 16-bit bus space is accessed in 32 bits, in single
write strobe mode (n = 0 to 3)
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Figure 15.21 and Figure 15.22 show examples of page access operations performed with the BCLK/2 selected in the
EBCLK pin output select bit.
CSRWAIT: 5
Tw1
Tw2
Tw3
CSRWAIT: 3
Tw4
Tw5
Tend
Tpw1
Tpw2
Tpw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A23 to A00)
A1
A1
A0
CSROFF: 1
Chip select
(CSn)
Byte control
(BC1, BC0)
RDON: 1
RDON: 1
Data read
(RD)
Data bus
(D15 to D00)
D0
D1
: Indicates the sampling point.
Figure 15.21
Example of page read access operation when BCLK/2 is selected with EBCLK pin output select
bit, two rounds of bus access are generated in response to a single transfer request (n = 0 to 3)
CSPWWAIT: 4
CSWWAIT: 4
Tw1
Tw2
Tw3
Tw4
Tend
Tdw1
Tpw1
Tpw2
Tpw3
Tpw4
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A23 to A00)
A1
A0
CSWOFF: 1
Chip select
(CSn)
Byte control
(BC1, BC0)
WRON: 1
WRON: 1
WDON: 1
WDON: 1
Data write
(WR)
Data bus
(D15 to D00)
D1
D0
WDOFF: 1
Figure 15.22
WDOFF: 1
Example of page write access operation when BCLK/2 is selected with the EBCLK pin output
select bit, two rounds of bus access are generated in response to a single transfer request, in
single write strobe mode (n = 0 to 3)
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15.5.2
15. Buses
Address/Data Multiplexed Bus
When the address/data Multiplexed I/O Interface Select bit (MPXEN) in CSnCR is set to 1, addresses and data can be
multiplexed the input/output to/from the D15 to D00 pins in the corresponding area. Using this function enables the
direct connection of this LSI to peripheral LSIs requiring address/data multiplexing. When an 8-bit width is selected
using the BSIZE[1:0] bits in CSnCR, D07 to D00 are multiplexed with A07 to A00. When a 16-bit width is selected, D15
to D00 are multiplexed with A15 to A00. In the address/data multiplexed I/O space, accesses are controlled with the
ALE, RD, WRn, and BCn signals.
Byte strobe mode or single-write strobe mode is selectable in the same way as for a separate bus. However, with regard
to the BCn signals within the address cycle, the byte-control signal is output for the data being read or written.
During the address/data multiplexed I/O space access, after the number of wait cycles specified by the Address Cycle
Wait Select bits (AWAIT[1:0]) in CSnWCR2 is inserted in the address output cycle, data access is performed.
Ta1 to Tan (Address Cycle Wait)
The period Ta1 to Tan is valid only when the address/data multiplexed I/O space is specified. This period is made up of
the number of clock cycles between the start of an external bus access and 1 cycle before the address latch (ALE) signal
is negated. The number of cycles are selectable within the range from zero to three. Addresses are output until the next
cycle of the ALE signal negation (address cycle). The timing of the ALE signal is the same as that of CS assertion. After
the address cycle, a data cycle is started. CSnWCR1 and CSnWCR2 should be set so that the address cycle and data
cycle do not overlap.
Page access to the address/data multiplexed I/O space is invalid. When the PRENB or PWENB bit in CSnMOD is set to
1 to enable page-read or page-write access, these settings are ignored and normal read or write operation is performed.
Figure 15.23 to Figure 15.25 show examples of operations with the address/data multiplexed I/O interface.
Ta1
...
Tw1
...
Address cycle
Tan
Data cycle
Twn
Tend
Tn1
Tnm
External bus clock
(BCLK)
A
Address
Address cycle wait (AWAIT)
A
Address/data bus
D
1 cycle fixed
Address latch
(ALE)
RD assert wait (RDON)
Data read
(RD)
Normal read cycle wait (CSRWAIT)
Read-access CS extension cycle (CSROFF)
Chip select
(CSn)
CS assert wait (CSON)
: Indicates the sampling point.
Figure 15.23
Example of read access operation with address/data multiplexed I/O interface (n = 0 to 3)
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15. Buses
Address cycle
Ta1
...
Tw1
...
Data cycle
Tan
Twn
Tend
Tn1
External bus clock
(BCLK)
Write data output wait (WDON)
Address
A
Data output extension cycle (WDOFF)
Address cycle wait (AWAIT)
D
A
Address/data bus
1 cycle fixed
\
Address latch
(ALE)
WR assert wait (WRON)
Data write
(WRm)
Write-access CS extension cycle (CSWOFF)
CS assert wait (CSON)
Chip select
(CSn)
Normal write cycle wait (CSWWAIT)
Figure 15.24
Example of write access operation with address/data multiplexed I/O interface (m = 0, 1)
Address cycle
Tw1
Data cycle
Address cycle
Twn Tend Tn1
...
Tw1
Data cycle
Twn Tend Tn1
...
EBCLK output
pin
External bus
clock
(BCLK)
A
Address
A
Write data output wait (WDON): 4
Address cycle wait (AWAIT): 1
Address/data
bus
Data output extension cycle
(WDOFF): 1
D
A
1 cycle fixed
Address latch
(ALE)
Address cycle wait (AWAIT): 1
D
A
1 cycle fixed
WR assert wait (WRON): 5
Data write
(WRm)
Data read
(RD)
RD assert wait (RDON): 4
CS assert wait (CSON):0
Normal write cycle wait (CSWWAIT): 6
Normal read cycle wait (CSRWAIT): 5
Read-access CS extension
cycle (CSROFF): 1
Chip select
(CSn)
Write-access CS extension cycle (CSWOFF): 1
Figure 15.25
Example of bus timing with address/data multiplexed I/O interface (m = 0, 1)
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15.5.3
15. Buses
External Wait Function
Wait cycles can be extended by the WAIT signal beyond the length of normal access cycle wait specified in the
CSRWAIT[4:0] and CSWWAIT[4:0] bits in CSnWCR1, and the page access cycle wait specified in the CSPRWAIT[2:0]
and CSPWWAIT[2:0] bits in CSnWCR1.
When external wait is enabled (EWENB bit = 1 in CSnMOD), wait cycles are inserted while the WAIT signal is held
low. When external wait is disabled (EWENB bit = 0 in CSnMOD), the WAIT signal has no effect. All wait cycles
specified in CSnWCR1 are inserted independently of the WAIT signal.
(1)
Normal access
Sampling of the WAIT signal begins on completion of the wait cycle (Tend) specified in CSnWCR1. The bus cycle is
extended while the WAIT signal is held low. The wait cycle ends (Tend) at the next cycle after the WAIT signal becomes
high.
(2)
Page access
The first access operation is the same as the normal access operation. Sampling of the WAIT signal begins on completion
of the wait cycle (Tend) specified in the CSnWCR1 register. The bus cycle is extended while the WAIT signal is held
low. The wait cycle ends (Tend) at the next cycle after the WAIT signal becomes high.
For the second and subsequent accesses, sampling of the WAIT signal begins on completion of the page access wait
cycle (Tend). The page access wait cycle is extended while the WAIT signal is held low, and ends (Tend) at the next cycle
after the WAIT signal goes high.
Figure 15.26 and Figure 15.29 show examples of external wait insertion timing with the separate bus interface.
Tw1
Tw2
…
Twn (Tend)
Tend Tpw1
…
Tpwn (Tend)
Tend
External bus clock
(BCLK)
Address
(A23 to A00)
A0
A1
Chip select/
byte control
(CSn/BC)
Data read
(RD)
Read cycle wait (CSRWAIT)
Page read cycle wait (CSPRWAIT)
Data bus
(D15 to D00)
D0
D1
External wait
(WAIT)
External wait
External wait
: Indicates sampling point
Figure 15.26
Example external wait timing for page read access to 16-bit bus space when 1/1 BCLK is selected
with the EBCLK Pin Output Select bit (n = 0 to 3; m = 0, 1)
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15. Buses
Tw1
Tw2
…
Twn (Tend)
Tend Tpw1
…
Tpwn (Tend)
Tend
EBCLK pin
output
External bus clock
(BCLK)
Address
(A23 to A00)
A0
A1
Chip select/
Byte control
(CSn/BCm)
Data read
(RD)
Read cycle wait (CSRWAIT)
Page read cycle wait (CSPRWAIT)
Data bus
(D15 to D00)
D0
D1
External wait
(WAIT)
External wait
External wait
: Indicates the sampling point.
Figure 15.27
Example external wait timing for page read access to 16-bit bus space when BCLK/2 is selected
with the EBCLK Pin Output Select bit (n = 0 to 3; m = 0, 1)
Tw1
Tw2
…
Twn (Tend)
Tend Tdw1 Tpw1
…
Tpwn (Tend)
Tend Tdw1
External bus clock
(BCLK)
Address
(A23 to A00)
A0
A1
Chip select
(CSn)
Data read
(RD)
WR assert wait (WRON)
WR assert wait (WRON)
Data write
(WR)
Page write cycle wait (CSPWWAIT)
Write cycle wait (CSWWAIT)
Data bus
(D15 to D00)
D0
Write data output wait (WDON)
D1
Write data output
extension cycle (WDOFF)
Write data output wait (WDON)
Write data output
extension cycle (WDOFF)
External wait
(WAIT)
External wait
External wait
: Indicates sampling point
Figure 15.28
Example external wait timing for page write access to 16-bit bus space in byte strobe mode when
BCLK is selected with the EBCLK pin output select bit (n = 0 to 3; m = 0, 1)
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Tw1
15. Buses
Tw2
…
Twn (Tend)
Tend Tdw1
Tpw1
…
Tpwn (Tend)
Tend Tdw1
EBCLK pin
output
External bus clock
(BCLK)
Address
(A23 to A00)
A0
A1
Chip select
(CSn)
Data read
(RD)
WR assert wait (WRON)
WR assert wait (WRON)
Data write
(WRm)
Page write cycle wait (CSPWWAIT)
Write cycle wait (CSWWAIT)
Data bus
(D15 to D00)
D0
Write data output wait (WDON)
D1
Write data output
extension cycle (WDOFF)
Write data output
extension cycle (WDOFF)
Write data output wait (WDON)
External wait
(WAIT)
External wait
External wait
: Indicates the sampling point.
Figure 15.29
(3)
Example external wait timing for page write access to 16-bit bus space in byte strobe mode when
BCLK/2 is selected with the EBCLK pin output select bit (n = 0 to 3; m = 0, 1)
Address/data multiplexed I/O interface
In a data cycle with the address/data multiplexed I/O interface, programmed waits and pin waits using the WAIT pin can
be inserted in the same way as that with the separate bus interface.
Address cycles are not affected by the wait control settings. Figure 15.30 shows an example of external wait insertion
timing with the address/data multiplexed I/O interface.
Address
cycle
Tw1 Tw2
Data cycle
Tw3
Tw4 (Tend)
Tend
Address
cycle
Tw1 Tw2
Data cycle
Tw3
Tw4 (Tend)
Tend
External bus clock
(BCLK)
A0
Address
Address/data bus
A1
D0
A0
D1
A1
Address latch
(ALE)
Chip select/
byte control
(CSn/BCm)
Data read
(RD)
Normal read cycle wait (CSRWAIT)
Normal read cycle wait (CSRWAIT)
External wait
(WAIT)
External wait
External wait
: Indicates the sampling point.
Figure 15.30
Example external wait Insertion timing with address/data multiplexed I/O interface (m = 0, 1)
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15.5.4
15. Buses
Insertion of Recovery Cycles
Recovery cycles can be inserted between consecutive rounds of external bus access by setting the Recovery Cycle
Insertion Enable bit in CSRECEN to 1.
The number of recovery cycles to be inserted after the read cycles and the write cycles can be independently set for each
area using CSnREC. When the preceding bus cycle is a write access, the number of write recovery cycles must be set
with the WRCV[3:0] bits for the associated area. When the preceding bus cycle is a read access, the number of read
recovery cycles must be set with the RRCV[3:0] bits for the associated area. For example, when a CS1 read access
occurs after a CS0 read access, the number of recovery cycles to be inserted between them is set in the RRCV[3:0] bits in
CS0REC.
The recovery cycle insertion can be enabled or disabled with RCVENi (i = 0 to 7) in CSRECEN when the preceding bus
access is a separate bus access, and with RCVENMj (j = 0 to 7) when the preceding bus access is an address/data
multiplexed bus access.
Recovery cycles can be inserted on any of the following eight conditions:
After a read access to the external bus, a read access is made to the external bus in the same area
After a read access to the external bus, a read access is made to the external bus in a different area
After a read access to the external bus, a write access is made to the external bus in the same area
After a read access to the external bus, a write access is made to the external bus in a different area
After a write access to the external bus, a read access is made to the external bus in the same area
After a write access to the external bus, a read access is made to the external bus in a different area
After a write access to the external bus, a write access is made to the external bus in the same area
After a write access to the external bus, a write access is made to the external bus in a different area.
The recovery cycle starts at the end of the preceding bus cycle, for example, when the CSn signal (n = 0 to 3) is negated.
A high-level period of the CSn signal is inserted for the specified recovery cycle period starting from this point.
In the fastest case, the CSn signal for the next round of bus access is asserted immediately after the end of the recovery
cycles. Even if the next request for access to an external address space is generated during the recovery period, the next
access over the external bus starts immediately after the end of the recovery cycles.
When two or more external bus access cycles are required for a single transfer request from a bus master, and the
recovery cycle insertion condition is satisfied, recovery cycles are also inserted between these bus access cycles.
However, when page read access is enabled (CSnMOD.PRENB = 1) or page write access is enabled (CSnMOD.PWENB
= 1), recovery cycles are not inserted except after the last bus access cycle of the transfer, even if the recovery cycle
insertion condition is satisfied. See Figure 15.33.
Similarly, during normal access with page access enabled, recovery cycles are not inserted between bus access cycles but
only after the last bus access cycle of the transfer. With the address/data multiplexed I/O interface, when the recovery
cycle insertion condition is satisfied, recovery cycles are inserted between bus access cycles regardless of the page access
enable setting.
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15. Buses
Figure 15.31 to Figure 15.33 show examples of recovery cycle insertion with the separate bus interface.
CS0 write
External bus clock
(BCLK)
CS0 write recovery
(CS0REC.WRCV[3:0]): 4
Tw1 Tw2 Tw3 Tend Tr1
Address
(A23 to A00)
Tr2
Tr3
A0
Tr4
CS0 read recovery
(CS0REC.RRCV[3:0]): 4
CS0 read
Tw1 Tw2 Tend
Tn1
Tr1
Tr2
Tr3
Tr4
CS1 read
Tw1 Tw2 Tw3 Tend
A2
A1
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
Data bus
(D15 to D00)
D1
D0
D2
: Indicates the sampling point.
Figure 15.31
Example of recovery cycle insertion with separate bus interface (m = 0, 1)
CS1 read recovery
CS0 write recovery
CS0 write recovery
(CS1REC.RRCV[3:0]): 1
(CS0REC.WRCV[3:0]): 2
(CS0REC.WRCV[3:0]): 2
CS1 read (1)
Write (2)
CS0 write (1)
Read (2)
External bus clock
(BCLK)
Address
(A23 to A00)
Tw1 Tw2 Tend Tr1
A0(1)
Tr2 Tw1 Tw2 Tend Tr1
A0(2)
Tr2
Tw1 Tend Tn1
A1(1)
Tr1
Tw1 Tend Tn1
Tr1
A1(2)
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
Data bus
(D15 to D00)
D0(1)
D0(2)
D1(1)
D1(2)
: Indicates the sampling point.
Figure 15.32
Example of recovery cycle insertion when bus access is split with separate bus interface, normal
access (m = 0, 1)
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15. Buses
CS0 write recovery
(CS0REC.WRCV[3:0]): 2
CS1 read (1)
CS0 write (2)
CS0 write (1)
External bus clock
(BCLK)
Tw1 Tw2 Tw3 Tend Tpw1 Tpw2 Tpw3 Tend Tr1
Address
(A23 to A00)
Data bus
(D15 to D00)
A0(1)
Tr2
A0(2)
D0(1)
CSWWAIT = 3
CS1 read recovery
(CS1REC.RRCV[3:0]): 2
CS1 read (2)
Tw1 Tw2 Tw3 Tend Tpw1 Tpw2 Tpw3 Tend Tr1
A1(1)
A1(2)
D0(2)
CSPWWAIT = 3
D1(2)
D1
Chip select 0
(CS0)
Tr2
CSRWAIT = 3
CSPRWAIT = 3
Chip select 1
(CS1)
Byte control
(BCm)
RDON = 3
Data read
(RD)
Data write
(WR)
Figure 15.33
WRON = 2
RDON = 3
WRON = 2
: Indicates the sampling point.
Example of recovery cycle insertion when bus access is split with separate bus interface, page
access (m = 0, 1)
Figure 15.34 shows an example of operations when the EBCLK pin output selection bits are set for a frequency division
of BCLK/2.
CS0 write
CS0 write recovery
(CS0.WRCV) : 4
CS0 read recovery
(CS0.RRCV) : 4
CS0 read
CS1 read
EBCLK pin output
External bus clock
(BCLK)
Address
(A23 to A00)
Tw1
Tw2
A0
Tend
Tr1
Tr2
Tr3
Tr4
Tw1
Tw2
Tend
A1
Tn1
Tr1
Tr2
Tr3
Tr4
Tw1
Tw3
Tw2
Tend
A2
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
Data bus
(D15 to D00)
D0
D1
D2
: Indicates the sampling point.
Figure 15.34
Example of operation for recovery cycles when EBCLK pin output selection bits are set for
frequency division of BCLK/2 for normal access through a separate bus interface (m = 0, 1)
With the address/data multiplexed I/O interface, recovery cycles are inserted in the same way as with the separate bus
interface.
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15. Buses
Figure 15.35 and Figure 15.36 show an example of recovery cycle insertion with the address/data multiplexed I/O
interface.
CS0 write recovery
(CS0REC.WRCV[3:0]): 3
CS0 write
External bus clock
(BCLK)
Tw1 Tw2 Tw3 Tw4 Tend Tr1
Address
Tr2
Tr3
A0
Address/data bus
A0
CS0 read
CS0 read recovery
(CS0REC.RRCV[3:0]): 2
Tw1 Tw2 Tw3 Tw4 Tend Tr1
Tr2
CS1 read
Tw1 Tw2 Tw3 Tw4 Tend
A2
A1
D1
A1
D0
D2
A2
Address latch
(ALE)
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
: Indicates the sampling point.
Figure 15.35
Example of recovery cycle insertion with address/data multiplexed I/O interface (m = 0, 1)
CS1 read recovery
(CS1REC.RRCV[3:0]): 1
CS0 write recovery
(CS0REC.WRCV[3:0]): 1
CS0 write (1)
External bus clock
(BCLK)
Tw1 Tw2 Tw3 Tend Tr1
Address
Address/data bus
Address latch
(ALE)
Tw1 Tw2 Tw3 Tend Tr1
A0(1)
A0(1)
0(1)
CS1 read (1)
CS0 write (2)
Tw1 Tw2 Tw3 Tend Tr1
A0(2)
D0(1)
A0(2)
0(2)
CS1 read (2)
Tw1 Tw2 Tw3 Tend Tr1
A1(2)
A1(1)
D0(2)
A1(1)
1(1)
D1
A1(2)
D1(2)
1(2)
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
: Indicates the sampling point.
Figure 15.36
Example of recovery cycle insertion when a bus access is split with address/data multiplexed I/O
interface (m = 0, 1)
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15.5.5
15. Buses
No Access State
When no external address space is accessed, the CSn, BCn, WRn, and RDn signals are high, ALE signal is low, and D15
to D00 are in the high-impedance state.
15.5.6
Write Buffer Function (External Bus)
In write access, the main bus is released by writing data to the write buffer before the write access completes. This allows
the next round of bus access to start. However, if the next access is to an external address space or to a register of the
external bus controller, it is suspended until the external bus operations already in progress are complete.
Figure 15.37 shows an example of operation when the write buffer function is in use. When this function is in use, if the
next operation after an external write is an internal access, the internal access is executed in parallel with the external
write, for example, without waiting for completion of the latter operation.
Main bus
External
memory
Peripheral module
External write
External bus
Figure 15.37
15.5.7
(1)
External memory
Example of operation when the write buffer function is in use
Constraints
Constraints on using separate bus interface
Table 15.10 lists the constraints that apply to bits in the CSn Wait Control Register 1 (CSnWCR1) and CSn Wait Control
Register 2 (CSnWCR2) when normal and page accesses occur.
Even if the Page Read Access Enable bit or Page Write Access Enable bit in the CSn Mode Register is set to enable
(CSnMOD.PRENB = 1 or CSnMOD.PWENB = 1), the first page access or access that does not fall within the scope of a
page access is a normal access operation. Because of this, constraints on normal access must be satisfied.
Table 15.10
Constraints on normal access and page access
Constraints on normal access
Constraints on page access
Reading
Writing
Reading
Writing
CSON[2:0] ≤ CSRWAIT
RDON[2:0] ≤ CSRWAIT
CSON[2:0] ≤ RDON
1 ≤ WDON[2:0]
CSON[2:0] ≤ CSWWAIT
WRON[2:0] ≤ CSWWAIT
WDON[2:0] ≤ CSWWAIT
WDOFF[2:0] ≤ CSWOFF
WDON[2:0] ≤ WRON
CSON[2:0] ≤ WRON
CSON[2:0] ≤ CSPRWAIT
RDON[2:0] ≤ CSPRWAIT
CSON[2:0] ≤ RDON
1 ≤ WDON[2:0]
CSON[2:0] ≤ CSPWWAIT
WRON[2:0] ≤ CSPWWAIT
WDON[2:0] ≤ CSPWWAIT
WDOFF[2:0] ≤ CSWOFF
WDON[2:0] ≤ WRON
CSON[2:0] ≤ WRON
Note:
When two or more external bus access cycles are required for a single transfer request from a bus master, and the recovery
cycle insertion condition is satisfied, with page read access enabled (CSnMOD.PRENB = 1) or page write access enabled
(CSnMOD.PWENB = 1), recovery cycles are not inserted between bus access cycles but inserted only after the last bus access
cycle of the transfer.
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(2)
15. Buses
Constraints on using address/data multiplexed bus interface
In the address/data multiplexed I/O space, page accesses are invalid. If a page access setting is specified, the setting is
ignored and the normal read or write operation is performed.
Table 15.11
Constraints at the time of normal access
Constraints at the time of normal access
Reading
Writing
CSON[2:0] ≤ CSRWAIT
RDON[2:0] ≤ CSRWAIT
CSON[2:0] ≤ RDON
AWAIT[1:0] + 2 ≤ RDON
CSON[2:0] ≤ AWAIT
CSON[2:0] ≤ CSWWAIT
WRON[2:0] ≤ CSWWAIT
WDON[2:0] ≤ CSWWAIT
WDOFF[2:0] ≤ CSWOFF
WDON[2:0] ≤ WRON
CSON[2:0] ≤ WRON
AWAIT[1:0] + 2 ≤ WRON
AWAIT[1:0] + 2 ≤ WDON
CSON[2:0] ≤ AWAIT
(3)
Constraint on pin multiplexing between the A00 and BC0 functions
Setting the single write strobe mode is prohibited in the 8-bit bus space.
(4)
Constraints when BCLK/2 is selected in the EBCLK pin output select bit
When a BCLK/2 is selected in the EBCLK Pin Output Select bit, the external bus access cycle starts on the rising edge of
the EBCLK pin output. However, when two or more external bus access cycles are generated for a single transfer request
from a bus master, the second or subsequent external bus access cycle can start on the falling edge of the EBCLK pin
output, depending on the wait cycle settings. Use the appropriate register settings according to the specifications of
connected devices. When BCLK/2 is selected in the EBCLK Pin Output Select bit, enabling an external wait
(CSnMOD.EWENB = 1) is prohibited.
(5)
Restriction on instruction code
You must fix the instruction code to the little-endian order.
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15.6
15. Buses
Bus Error Monitoring Section
This monitoring system monitors each individual area, and whenever it detects an error, it returns the error to the
requesting master IP using the AHB-Lite error response protocol.
15.6.1
Error Type that Occurs by Bus
Four types of errors can occur on each bus:
Illegal address access
Bus master MPU error
Bus slave MPU error
Timeout.
Table 15.12 lists the address ranges where access leads to illegal address access errors. However, the reserved area in the
slave does not trigger an illegal address access error. For more information on bus master MPU and bus slave MPU, see
section 16, Memory Protection Unit (MPU).
15.6.2
Operation when a Bus Error Occurs
When a bus error occurs, operation is not guaranteed and the error is returned to the requesting master IP. The bus errors
that occur for each master are stored in the BUSnERRADD and BUSnERRSTAT registers. These registers must be
cleared by reset only. For more information, see sections 15.3.9 and 15.3.10.
Note:
The DMAC and DTC do not receive bus errors. If the DMAC or DTC accesses the bus, the transfer continues.
15.6.3
Conditions Leading to Illegal Address Access Errors
Table 15.12 lists the address spaces that trigger illegal address access errors for each bus.
Table 15.12
Conditions leading to illegal address access errors (1 of 2)
Master bus
Address
Slave bus name
0000 0000h to 01FF FFFFh
Memory bus 1
Memory bus 3
CPU (ICode/DCode/System)
-
DMA
-
0200 0000h to 027F FFFFh
Memory mirror area
*1
E
0280 0000h to 1FFF FFFFh
Reserved
E
E
2000 0000h to 2001 FFFFh
Memory bus 4
-
-
2002 0000h to 2002 FFFFh
Memory bus 5
-
-
2003 0000h to 3FFF FFFFh
Reserved
E
E
4000 0000h to 4001 FFFFh
Peripheral bus 1
-
-
4002 0000h to 4003 FFFFh
Reserved
E
E
4004 0000h to 4005 FFFFh
Peripheral bus 3
-
-
4006 0000h to 4007 FFFFh
Peripheral bus 4
-
-
4008 0000h to 4009 FFFFh
Peripheral bus 5
-
-
400A 0000h to 400B FFFFh
Reserved
-
-
400C 0000h to 400D FFFFh
Peripheral bus 7
-
-
400E 0000h to 400F FFFFh
Reserved
E
E
4010 0000h to 407F FFFFh
Peripheral bus 9
-
-
4080 0000h to 5FFF FFFFh
Reserved
E
E
6000 0000h to 67FF FFFFh
QSPI area
-
-
6800 0000h to 7FFF FFFFh
Reserved
E
E
8000 0000h to 97FF FFFFh
CS area
-
-
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Table 15.12
15. Buses
Conditions leading to illegal address access errors (2 of 2)
Master bus
Address
Slave bus name
CPU (ICode/DCode/System)
DMA
9800 0000h to DFFF FFFFh
Reserved
E
E
E000 0000h to FFFF FFFFh
System for Cortex-M4
-
E
E indicates the path where an illegal address access error occurs.
“-” indicates the path where illegal address access error does not occur or the path where access does not occur.
Note:
Note 1.
If MMF (Memory Mirror Function) is enabled, the access to mapped area (0200 0000h to 027F FFFFh) is switched to the user
specific area (MMF output address = CPU output address + offset).
The bus module does not detect whether the MMF switched the address. Therefore, if the MMF is enabled and the CPU
accesses 0200 0000h, no error can occur (depends on the switched address). If the MMF is disabled and the CPU accesses
0200 0000h, the bus module can detect the error.
The bus module does not detect whether the MMF switched the address. Therefore, if the MMF is enabled and the CPU
accesses 0200 0000h, no error occurs (depends on the switched address).
If the MMF is disabled and the CPU accesses 0200 0000h, the bus module can detect the error.
The bus module detects an access error resulting from access to a reserved area, such as in the case when no area is
assigned to the slave.
0280 0000h to 1FFF FFFFh: access error detection.
0000 0000h to 01FF FFFFh: memory bus 1 no access error detection.
15.6.4
Timeout
For some peripheral modules, a timeout error occurs with the module-stop function. When there is no response from the
slave for a certain period of time, a timeout error is detected. A timeout error is returned to the requesting master IP using
the AHB-Lite error response protocol.
15.7
Notes on Using Flash Cache
When using flash cache through access from the CPU, Arm® MPU should also be set to cacheable. See references 1. and
2. for more information.
15.8
References
1. ARM®v7-M Architecture Reference Manual (ARM DDI 0403D).
2. ARM® Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).
3. ARM® AMBA 3 AHB-Lite Protocol v1.0 Specification (ARM IHI 0033A).
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16. Memory Protection Unit (MPU)
16.
Memory Protection Unit (MPU)
16.1
Overview
The MCU provides four Memory Protection Units (MPUs) and a CPU stack pointer monitor function. Table 16.1 lists the
supported MPU specifications, and Table 16.2 shows the behavior on detection of each MPU error.
Table 16.1
MPU specifications
Classification
Module/Function
Description
Illegal memory
access
Arm®
Arm CPU has a default memory map. If the CPU makes an illegal access, an
exception interrupt occurs
The MPU can change a default memory map.
CPU
Memory protection
Security
Table 16.2
Cortex®-M4
CPU stack pointer
monitor
2 regions:
Main Stack Pointer (MSP)
Process Stack Pointer (PSP).
Arm MPU
Memory protection function for the CPU:
8 MPU regions with sub regions and background region.
Bus master MPU
Memory protection function for each bus master except for the CPU:
Bus master MPU group A: 16 regions.
Bus slave MPU
Memory protection function for each bus slave
Security MPU
Protects accesses from non-secure programs to the following secure regions:
2 regions (PC)
4 regions (code flash, SRAM, two secure functions).
Behavior on MPU error detection
MPU type
Notification type
Bus access on error detection
Storing of error
access information
CPU stack pointer monitor
Reset or non-maskable interrupt
Don’t care
Not stored
Arm MPU
Hard fault
Does not correctly have write access
Does not correctly have read access.
Stored in the Cortex-M4
processor
Bus master MPU
Reset or non-maskable interrupt
Write access to the protection region
Read access to the protection region.
Stored
Bus slave MPU
Reset or non-maskable interrupt
Hard fault
Write access ignored
Read access read as 0.
Stored
Security MPU
Not notified
Does not correctly have write access
Does not correctly have read access.
Not stored
For information on error access for the Arm MPU, see section 16.7. For information on error access for other MPUs, see
section 15.3.9, Bus Error Address Register (BUSnERRADD) (n = 1 to 4) and section 15.3.10, Bus Error Status Register
(BUSnERRSTAT) (n = 1 to 4) in section 15, Buses.
16.2
CPU Stack Pointer Monitor
The CPU stack pointer monitor detects underflows and overflows of the stack pointer. Because the Arm CPU has two
stack pointers, a Main Stack Pointer (MSP) and a Process Stack Pointer (PSP), it supports two CPU stack pointer
monitors. If a stack pointer underflow or overflow is detected, the CPU stack pointer monitor generates a reset or a nonmaskable interrupt. The CPU stack pointer monitor is enabled by setting the Stack Pointer Monitor Enable bit in the
Stack Pointer Monitor Access Control Register (MSPMPUCTL, PSPMPUCTL) to 1.
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16. Memory Protection Unit (MPU)
Table 16.3 lists the specifications of the CPU stack pointer monitor. Figure 16.1 shows the CPU stack pointer monitor
block diagram, and Figure 16.2 shows the register setting flow.
Table 16.3
CPU stack pointer monitor specifications
Item
Description
SRAM region
Region to be covered by memory protection
Number of regions
2 regions:
Main Stack Pointer (MSP)
Process Stack Pointer (PSP).
Address specification for individual regions
Region start and end addresses configurable
Stack pointer monitor enable or disable setting for
individual regions
Stack pointer monitor for individual regions can be enabled or disabled
Operation on error detection
Reset or non-maskable interrupts can be generated
Register protection
Registers can be protected from illegal writes
CPU processor register set
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13 (SP)
R14 (LR)
R15 (PC)
xPSR
Process Stack
Pointer (PSP)
Main Stack
Pointer (MSP)
CPU stack pointer monitor
Main stack pointer monitor
Start
address
End
address
ENABLE
bit
OAD
bit
Reset
Compare
(within)
Non-maskable
interrupt
ERROR
flag
Process stack pointer monitor
Start
address
End
address
ENABLE
bit
OAD
bit
Compare
(within)
ERROR
flag
Figure 16.1
CPU stack pointer monitor block diagram
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16. Memory Protection Unit (MPU)
Start
Write to Main Stack Pointer (MSP) register
Write to Process Stack Pointer (PSP) register
Write to MSPMPUSA and MSPMPUEA registers
Write to PSPMPUSA and PSPMPUEA registers
Write to MSPMPUCTL and PSPMPUCTL registers
Write to MSPMPUOAD and PSPMPUOAD registers
Write to MSPMPUPT and PSPMPUPT registers
End
Figure 16.2
16.2.1
Register setting flow
Protection of Registers
Registers related to the CPU stack pointer monitor can be protected with the PROTECT bit.
16.2.2
Overflow/Underflow Error
If an overflow or underflow is detected, the CPU stack pointer monitor generates an overflow or underflow error. The
memory protection error is selectable to a non-maskable interrupt or reset in the OAD bit setting.
The non-maskable interrupt status is indicated in ICU.NMISR.SPEST. For details, see section 14, Interrupt Controller
Unit (ICU). The reset status is indicated in SYSTEM.RSTSR1.SPERF. For details, see section 6, Resets.
When ICU.NMISR.SPEST indicates that a CPU stack pointer monitor interrupt occurred, check the ERROR bit in the
MSPMPUCTL and PSPMPUCTL registers to determine whether it is a main stack pointer monitor error or a process
stack pointer monitor error.
A non-maskable interrupt keeps the output when the stack pointer overflows or underflows. When a non-maskable
interrupt flag is cleared, the stack pointer is set after ICU.NMICLR.SPECLR bit is 1. Then, write 0 to clear the ERROR
bit in the MSPMPUCTL and PSPMPUCTL registers.
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16.2.3
Note:
16. Memory Protection Unit (MPU)
Register Descriptions
Bus access must be stopped before writing to the MPU registers.
16.2.3.1
Main Stack Pointer (MSP) Monitor Start Address Register (MSPMPUSA)
Address(es): SPMON.MSPMPUSA 4000 0D08h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MSPMPUSA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
0
0
MSPMPUSA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MSPMPUSA[31:0]
Region Start Address
Address where the region starts, for use in region determination.
The lower 2 bits should be 0. The value range should be
2000 0000h to 200F FFFCh, excluding the reserved areas.
R/W
The MSPMPUSA and MSPMPUEA registers specify the CPU stack region in the SRAM (2000 0000h to 200F FFFFh,
excluding the reserved areas). For the SRAM area to be covered, see Figure 4.1 Memory map.
16.2.3.2
Main Stack Pointer (MSP) Monitor End Address Register (MSPMPUEA)
Address(es): SPMON.MSPMPUEA 4000 0D0Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MSPMPUEA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
1
1
MSPMPUEA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MSPMPUEA[31:0]
Region End Address
Address where the region ends, for use in region determination.
The lower 2 bits should be 1. The value range must be
2000 0003h to 200F FFFFh, excluding the reserved areas.
R/W
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16.2.3.3
16. Memory Protection Unit (MPU)
Process Stack Pointer (PSP) Monitor Start Address Register (PSPMPUSA)
Address(es): SPMON.PSPMPUSA 4000 0D18h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PSPMPUSA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
0
0
PSPMPUSA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
PSPMPUSA[31:0]
Region Start Address
Address where the region starts, for use in region determination.
The lower 2 bits should be 0. The value range must be
2000 0000h to 200F FFFCh, excluding the reserved areas.
R/W
The PSPMPUSA and PSPMPUEA registers specify the CPU stack region in the SRAM (2000 0000h to 200F FFFFh,
excluding the reserved areas). For the SRAM area to be covered, see Figure 4.1, Memory map.
16.2.3.4
Process Stack Pointer (PSP) Monitor End Address Register (PSPMPUEA)
Address(es): SPMON.PSPMPUEA 4000 0D1Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PSPMPUEA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
1
1
PSPMPUEA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
PSPMPUEA[31:0]
Region End Address
Address where the region ends, for use in region determination.
The lower 2 bits should be 1. The value range is from
2000 0003h to 200F FFFFh, excluding the reserved areas.
R/W
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16.2.3.5
16. Memory Protection Unit (MPU)
Stack Pointer Monitor Operation After Detection Register (MSPMPUOAD,
PSPMPUOAD)
Address(es): SPMON.MSPMPUOAD 4000 0D00h, SPMON.PSPMPUOAD 4000 0D10h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
OAD
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
OAD
Operation after Detection
0: Non-maskable interrupt
1: Reset.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the OAD bit
R/(W)*1
Note 1.
Write data is not saved.
OAD bit (Operation after Detection)
The OAD bit selects a reset or a non-maskable interrupt to occur when a stack pointer underflow or overflow is detected
by the CPU stack pointer monitor. The main stack pointer monitor and process stack pointer monitors each use an OAD
bit to determine which signal is generated when a stack pointer underflow or overflow is detected. When writing to the
OAD bit, write A5h simultaneously to the KEY[7:0] bits using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writes to the OAD bit. When writing to the OAD bit, write A5h simultaneously to
the KEY[7:0] bits. When values other than A5h are written to the KEY[7:0] bits, the OAD bit is not updated. The
KEY[7:0] bits are always read as 00h.
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16.2.3.6
16. Memory Protection Unit (MPU)
Stack Pointer Monitor Access Control Register (MSPMPUCTL, PSPMPUCTL)
Address(es): SPMON.MSPMPUCTL 4000 0D04h, SPMON.PSPMPUCTL 4000 0D14h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
ERRO
R
—
—
—
—
—
—
—
ENABL
E
0
0
0
0
0
0
0
0/1*1
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
ENABLE
Stack Pointer Monitor
Enable
0: Disable stack pointer monitor
1: Enable stack pointer monitor.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
ERROR
Stack Pointer Monitor
Error Flag
0: No stack pointer overflow or underflow occurred
1: Stack pointer overflow or underflow occurred.
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
The initial value depends on the reset generation source.
ENABLE bit (Stack Pointer Monitor Enable)
The ENABLE bit enables or disables the stack pointer monitor function, independently set for the main stack pointer
monitor and the process stack pointer monitor.
When the MSPMPUCTL.ENABLE bit is set to 1, the following registers are available:
MSPMPUSA
MSPMPUEA
MSPMPUOAD.
When the PSPMPUCTL.ENABLE bit is set to 1, the following registers are available:
PSPMPUSA
PSPMPUEA
PSPMPUOAD.
ERROR bit (Stack Pointer Monitor Error Flag)
The ERROR bit indicates the state of the stack pointer monitor. Each stack point monitor has an independent ERROR
bit.
[Setting condition]
Overflow or underflow of the stack pointer.
[Clearing conditions]
0 is written to this bit
A reset other than the bus master MPU error reset, bus slave MPU error reset, and stack pointer error reset.
Note:
Only 0 can be written to the ERROR bit.
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16.2.3.7
16. Memory Protection Unit (MPU)
Stack Pointer Monitor Protection Register (MSPMPUPT, PSPMPUPT)
Address(es): SPMON.MSPMPUPT 4000 0D06h, SPMON.PSPMPUPT 4000 0D16h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
PROTE
CT
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PROTECT
Protection of Register
0: Stack pointer monitor register writes are permitted
1: Stack pointer monitor register writes are protected. Reads
are permitted.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the PROTECT bit
R/(W)*1
Note 1.
Write data is not saved.
PROTECT bit (Protection of Register)
The PROTECT bit enables or disables writes to the associated registers to be protected, independently set for the main
stack pointer monitor and the process stack pointer monitor.
MSPMPUPT.PROTECT controls the following main stack pointer protection registers:
MSPMPUCTL
MSPMPUSA
MSPMPUEA.
PSPMPUPT.PROTECT controls the following process stack pointer protection registers:
PSPMPUCTL
PSPMPUSA
PSPMPUEA.
When writing to the PROTECT bit, simultaneously write A5h to the KEY[7:0] bits, using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writing to the PROTECT bit.
When writing to the PROTECT bit, simultaneously write A5h to KEY[7:0]. When values other than A5h are written to
the KEY[7:0] bits, the PROTECT bit is not updated. The KEY[7:0] bits are always read as 0.
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16.3
16. Memory Protection Unit (MPU)
Arm MPU
The Arm MPU has eight region memory protection units and provides full support for:
Protected regions
Overlapping protected regions, with ascending priority:
7 = highest priority
0 = lowest priority
Access permissions
Exporting memory attributes to the system.
Arm MPU mismatches and permission violations invoke the programmable-priority MemManage fault (HardFault)
handler. For details, see section 16.7 2.
16.4
Bus Master MPU
The bus master MPU monitors the addresses accessed by the bus masters in the entire address space (0000 0000h to
FFFF FFFFh). The access control information, consisting of read and write permissions, can be independently set for up
to 16 regions. The bus master MPU monitors access to each region based on these settings. If access to a protected region
is detected, the bus master MPU generates an internal reset or a non-maskable interrupt. For details on error access, see
15.3.9 and 15.3.10 in section 15, Buses.
Table 16.4 lists the specifications of the bus master MPU, and Figure 16.3 shows a block diagram.
Table 16.4
Bus master MPU specifications
Specifications
Description
Protected master groups
Bus master MPU group A: DMA bus
Protected region
0000 0000h to FFFF FFFFh
Number of regions
Bus master MPU group A: 16 regions
Address specification for individual regions
Region start and end addresses configurable
Enable or disable setting for memory
protection in individual regions
Settings enabled or disabled for the associated region
Access-control settings for individual regions
Permission to read and write
Operation on error detection
Reset or non-maskable interrupts
Register protection
Register can be protected from illegal writes
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16. Memory Protection Unit (MPU)
CPU
DCode bus
ICode bus
System bus
DMAC/DTC
Bus master MPU group A
DMA bus
Data flash
memory
Code flash
memory
SRAM0
Bus master MPU
Internal
peripheral
External
bus cont.
SRAM1
Figure 16.3
Bus master MPU block diagram
Figure 16.4 shows the bus master MPU group A.
Bus master MPU group A
Start
address
End
address
Compare
(within)
Enable
Write
protect
Read
protect
Region
control
circuit
Enable
Master
control
circuit
Region 0
Region 1
Region 2
Region 15
Error status
Group A address
Group A write access
OAD
Reset
Group A read access
Non-maskable interrupt
Figure 16.4
MPU bus master group A
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16.4.1
Note:
16. Memory Protection Unit (MPU)
Register Descriptions
Bus access must be stopped before writing to MPU registers.
16.4.1.1
Group A Region n Start Address Register (MMPUSAn) (n = 0 to 15)
Address(es): MMPU.MMPUSA0 4000 0204h, MMPU.MMPUSA1 4000 0214h, MMPU.MMPUSA2 4000 0224h, MMPU.MMPUSA3 4000 0234h,
MMPU.MMPUSA4 4000 0244h, MMPU.MMPUSA5 4000 0254h, MMPU.MMPUSA6 4000 0264h, MMPU.MMPUSA7 4000 0274h,
MMPU.MMPUSA8 4000 0284h, MMPU.MMPUSA9 4000 0294h, MMPU.MMPUSA10 4000 02A4h, MMPU.MMPUSA11 4000 02B4h,
MMPU.MMPUSA12 4000 02C4h, MMPU.MMPUSA13 4000 02D4h, MMPU.MMPUSA14 4000 02E4h, MMPU.MMPUSA15 4000 02F4h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MMPUSA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
0
0
MMPUSA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit Name
Description
R/W
b31 to b0
MMPUSA[31:0]
Region Start Address
Address where the region starts, for use in region
determination. The lower 2 bits should be 0.
R/W
16.4.1.2
Group A Region n End Address Register (MMPUEAn) (n = 0 to 15)
Address(es): MMPU.MMPUEA0 4000 0208h, MMPU.MMPUEA1 4000 0218h, MMPU.MMPUEA2 4000 0228h, MMPU.MMPUEA3 4000 0238h,
MMPU.MMPUEA4 4000 0248h, MMPU.MMPUEA5 4000 0258h, MMPU.MMPUEA6 4000 0268h, MMPU.MMPUEA7 4000 0278h,
MMPU.MMPUEA8 4000 0288h, MMPU.MMPUEA9 4000 0298h, MMPU.MMPUEA10 4000 02A8h, MMPU.MMPUEA11 4000 02B8h,
MMPU.MMPUEA12 4000 02C8h, MMPU.MMPUEA13 4000 02D8h, MMPU.MMPUEA14 4000 02E8h, MMPU.MMPUEA15 4000 02F8h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MMPUEA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
1
1
MMPUEA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MMPUEA[31:0]
Region End Address
Address where the region ends, for use in region
determination. The lower 2 bits should be 1.
R/W
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16.4.1.3
16. Memory Protection Unit (MPU)
Group A Region n Access Control Register (MMPUACAn) (n = 0 to 15)
Address(es): MMPU.MMPUACA0 4000 0200h, MMPU.MMPUACA1 4000 0210h, MMPU.MMPUACA2 4000 0220h, MMPU.MMPUACA3 4000 0230h,
MMPU.MMPUACA4 4000 0240h, MMPU.MMPUACA5 4000 0250h, MMPU.MMPUACA6 4000 0260h, MMPU.MMPUACA7 4000 0270h,
MMPU.MMPUACA8 4000 0280h, MMPU.MMPUACA9 4000 0290h, MMPU.MMPUACA10 4000 02A0h,
MMPU.MMPUACA11 4000 02B0h, MMPU.MMPUACA12 4000 02C0h, MMPU.MMPUACA13 4000 02D0h,
MMPU.MMPUACA14 4000 02E0h, MMPU.MMPUACA15 4000 02F0h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
WP
RP
ENABL
E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
ENABLE
Region Enable
0: Group A region n unit disabled
1: Group A region n unit enabled.
R/W
b1
RP
Read Protection
0: Read access permitted
1: Read access protected.
R/W
b2
WP
Write Protection
0: Write access permitted
1: Write access protected.
R/W
b15 to b3
—
Reserved
These bits are read as 0. The write value should be 0. R/W
The ENABLE, RP, and WP bits are individually configurable for each group A region n unit.
ENABLE bit (Region Enable)
The ENABLE bit enables or disables group A region n unit. When the ENABLE bit is set to 1, the RP bit and the WP bit
can be set to permit or protect access to the region that is set in MMPUSAn and MMPUEAn. When the ENABLE bit is
set to 0, no region is specified for group A region n access.
RP bit (Read Protection)
The RP bit enables or disables read protection for group A region n. The RP bit is available when the ENABLE bit is set
to 1.
WP bit (Write Protection)
The WP bit enables or disables write protection for group A region n. The WP bit is available when the ENABLE bit is
set to 1.
Table 16.5
Function of region control circuit (1 of 2)
MMPUACAn.ENABLE
MMPUACAn.RP
MMPUACAn.WP
Access
Region
Output of group A region n unit
0
-
-
Read
-
Outside of region
Write
-
Outside of region
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Table 16.5
16. Memory Protection Unit (MPU)
Function of region control circuit (2 of 2)
MMPUACAn.ENABLE
MMPUACAn.RP
MMPUACAn.WP
Access
Region
Output of group A region n unit
1
0
0
Read
Inside
Permitted region
Outside
Outside of region
Inside
Permitted region
Outside
Outside of region
Write
0
1
Read
Write
1
0
Read
Write
1
1
Read
Write
Inside
Permitted region
Outside
Outside of region
Inside
Protection region
Outside
Outside of region
Inside
Protection region
Outside
Outside of region
Inside
Permitted region
Outside
Outside of region
Inside
Protection region
Outside
Outside of region
Inside
Protection region
Outside
Outside of region
n = 0 to 15
Table 16.6
Function of master control circuit
MMPUCTLA.ENABLE
Output of group A
region 0 unit
Output of group A
region 1 unit
Output of group A
region 2 to 15 unit
Function of group A
1
Protected region
Don’t care
Don’t care
Generate error
1
Don’t care
Protected region
Don’t care
Generate error
1
Don’t care
Don’t care
Protected region
Generate error
1
Outside of region
Outside of region
Outside of region
Other case
Generate error
No error
A master MPU error occurs on the following conditions:
MMPUCTLA.ENABLE = 1, and output of one or more region n units is to a protected region
MMPUCTLA.ENABLE = 1, and output of all region n units is outside of region.
Other cases are handled as permitted regions.
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16.4.1.4
16. Memory Protection Unit (MPU)
Bus Master MPU Control Register (MMPUCTLA)
Address(es): MMPU.MMPUCTLA 4000 0000h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
OAD
ENABL
E
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ENABLE
Master Group Enable
0: Master group A disabled
1: Master group A enabled.
R/W
b1
OAD
Operation After Detection
0: Non-maskable interrupt
1: Reset.
R/W
b7 to b2
—
Reserved
These bits are read as 0.The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the OAD and
ENABLE bits
R/(W)*1
Note 1.
Write data is not saved.
ENABLE bit (Master Group Enable)
The ENABLE bit enables or disables the bus master MPU function for master group A.
When this bit is set to 1, MMPUACAn is available. When this bit is set to 0, MMPUACAn is unavailable, including
permission for all regions. When the ENABLE bit is set, simultaneously write A5h to KEY[7:0] using halfword access.
OAD bit (Operation After Detection)
The OAD bit generates a reset or non-maskable interrupt when access to the protected region is detected by the bus
master MPU. When the OAD bit is set, simultaneously write A5h to KEY[7:0] using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writes to the ENABLE and OAD bits. When writing to the ENABLE and OAD bits,
simultaneously write A5h to KEY[7:0]. When values other than A5h are written to the KEY[7:0] bits, the ENABLE and
the OAD bits are not updated. The KEY[7:0] bits are always read as 00h.
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16.4.1.5
16. Memory Protection Unit (MPU)
Group A Protection of Register (MMPUPTA)
Address(es): MMPU.MMPUPTA 4000 0102h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
PROTE
CT
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PROTECT
Protection of register
0: All bus master MPU group A register writes are permitted
1: All bus master MPU group A register writes are protected.
Read access is possible.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the PROTECT bit
R/(W)*1
Note 1.
Write data is not saved.
PROTECT bit (Protection of register)
The PROTECT bit enables or disables writes to the associated registers to be protected. MMPUPTA.PROTECT controls
the bus master MPU group A protection registers.
The following registers are protected by MMPUPTA.PROTECT:
MMPUSAn
MMPUEAn
MMPUACAn
MMPUCTLA.
When the PROTECT bit is set, simultaneously write A5h to KEY[7:0] using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writing to the PROTECT bit. When writing to the PROTECT bit, simultaneously
write A5h to KEY[7:0]. When values other than A5h are written to the KEY[7:0] bits, the PROTECT bit is not updated.
The KEY[7:0] bits are always read as 00h.
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16.4.2
16.4.2.1
16. Memory Protection Unit (MPU)
Operation
Memory protection
The bus master MPU monitors memory access using control settings made individually for the access control regions. If
access to a protected region is detected, the bus master MPU generates a memory protection error.
The bus master MPU can be set for up to 16 protected regions. Protected regions include those with overlapping
permitted and protected regions, and those with two overlapping permitted regions.
The bus master MPU has group A. The memory protection function checks the address of the bus for the master group,
and all master group accesses are protected. The bus master MPU sets the permission for all of the regions after reset.
Setting MMPUCTLA.ENABLE to 1 protects all of the regions. A permitted region is set up within the protected region
for each region. If access to the protected region is detected, the bus master MPU generates an error.
Figure 16.5 shows the use case of a bus master MPU.
MMPUCTLA.
ENABLE bit = 0
MMPUCTLA.
ENABLE bit = 1
Setting of all regions
Setting of
regions
All memory is
R/W
after reset
All memory is
protected
region
Clearing of
MMPUACAn.
ENABLE bit
Clearing of
MMPUCTLA.
ENABLE bit
Protected region
Region 0 R/W
Region 1 read only
Region 2 write only
Protected region
Region 3 R/W
Protected region
Figure 16.5
Use case of bus master MPU
Figure 16.6 shows the access permission or protection for the overlapping bus master MPU regions. Access control for
the overlapping regions is as follows:
The region is handled as a protected region when output of one or more region units is a protected region
The region is handled as a protected region when output of all region units is outside of the regions
Other cases are handled as permitted regions.
Protected region
Region 0 R/W
Region 1
read only
(write protection)
Region 2
write only
(read protection)
Read/write protected region (output of every single region unit is
“region where permission has not been set”)
Read/write permitted region
Read permitted/write protected region
Read/write protected region
Read protected/write permitted region
Region 3
(R/W protection)
Read/write protected region
Read/write permitted region
Read/write protected region (output of every single region unit is
“region where permission has not been set”)
Figure 16.6
Access permission or protection by overlap of the bus master MPU regions
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16. Memory Protection Unit (MPU)
Figure 16.7 shows the register setting flow after reset. During this register setting, stop all the masters except the CPU.
Start
Write to the MMPUCTLA.OAD bit
Set the MMPUCTLA.ENABLE bit
All memory is protected region
Write to MMPUSAn and MMPUEAn registers
Write to the MMPUACAn register
Region selected in the MMPUACAn register is
added
Set the MMPUPTA.PROTECT bit
The register is protected
End
Figure 16.7
Register setting flow after reset
Figure 16.8 shows the register setting flow for adding regions. During this register setting, stop all masters except the
CPU.
Start
Clear the MMPUPTA.PROTECT bit
Write to the MMPUSAn and MMPUEAn registers
Write to the MMPUACAn register
Set the MMPUPTA.PROTECT bit
End
Figure 16.8
Register setting flow for region addition
16.4.2.2
Protection of registers
To protect the registers related to the bus master MPU, set the PROTECT bit in the MMPUPTA register.
16.4.2.3
Memory protection error
If access to the protected region is detected, the bus master MPU generates an error. Set the OAD bit to select whether
the error is reported as a non-maskable interrupt or reset. The non-maskable interrupt status is indicated in
ICU.NMISR.BUSMST. For details, see section 14, Interrupt Controller Unit (ICU). The reset status is indicated in
SYSTEM.RSTSR1.BUSMRF. For details, see section 6, Resets.
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16.5
16. Memory Protection Unit (MPU)
Bus Slave MPU
The bus slave MPU monitors access to the bus slave functions, such as flash or SRAM. The bus slave function can be
accessed from two bus masters, the CPU, and the bus master MPU group A. The bus slave MPU has a separate
protection register for each of the two bus masters, with individual access protection control, consisting of read and write
permissions. If access to a protected region is detected, the bus slave MPU generates a reset or a non-maskable interrupt,
and can store the bus error status, error access status, and bus error address in the I/O Registers. For details, see 15.3.9
and 15.3.10 in section 15, Buses.
Table 16.7 lists the specifications of the bus slave MPU, and Figure 16.9 shows a block diagram.
Table 16.7
Specifications of bus slave MPU
Specifications
Description
Protected bus master
Bus master MPU group A: DMA bus
Protected slave functions
Memory bus 3: Code flash memory
Memory bus 4: SRAM0
Memory bus 5: SRAM1
Internal peripheral bus 1: Peripheral modules related system control
Internal peripheral bus 3: CAC, ELC, I/O ports, POEG, RTC, WDT, IWDT, IIC, CAN,
SSIE, ADC14, DAC12, and DOC
Internal peripheral bus 4: SCI, SPI, CRC, and SDHI
Internal peripheral bus 5: KINT, AGT, USBFS, DAC8, OPAMP, ACMPLP, and CTSU
Internal peripheral bus 7: Secure IP (SCE5)
Internal peripheral bus 9: Flash memory (in P/E) and data flash memory
External bus (CS area): External devices
External bus (QSPI area): External SPI devices
Access-control information settings for
individual regions
Permission to read and write
Operation after detection
Reset, non-maskable interrupt, or exception
Protection of register
Register can be protected from illegal writes
The bus slave MPU is located on each bus slave side and controls the permission or protection of access from each bus
master to each bus slave.
CPU
ICode bus
DCode bus
System bus
DMAC/DTC
Bus slave MPU
Bus slave MPU
Code flash
memory
Bus slave MPU
Data flash
memory
Bus slave MPU
SRAM0
Bus slave MPU
Internal
peripheral
Bus slave MPU
External bus
cont.
SRAM1
Figure 16.9
Bus slave MPU block diagram
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16.5.1
Note:
16. Memory Protection Unit (MPU)
Register Descriptions
Bus access must be stopped before writing to MPU registers.
16.5.1.1
Access Control Register for Memory Bus 3 (SMPUMBIU)
Address(es): SMPU.SMPUMBIU 4000 0C10h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
WPGR RPGRP
PA
A
0
b1
b0
—
—
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A read disabled
1: Memory protection for master group A read enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A write disabled
1: Memory protection for master group A write enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for master group A reads on memory bus 3.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for master group A writes on memory bus 3.
16.5.1.2
Access Control Register for Internal Peripheral Bus 9 (SMPUFBIU)
Address(es): SMPU.SMPUFBIU 4000 0C14h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
WPGR RPGRP WPCP RPCPU
PA
A
U
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU read disabled
1: Memory protection for CPU read enabled.
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU write disabled
1: Memory protection for CPU write enabled.
R/W
b2
RPGRPA
Master Group A Read
protection
0: Memory protection for master group A read disabled
1: Memory protection for master group A read enabled.
R/W
b3
WPGRPA
Master Group A Write
protection
0: Memory protection for master group A write disabled
1: Memory protection for master group A write enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables memory protection for CPU reads on internal peripheral bus 9.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables memory protection for CPU writes on internal peripheral bus 9.
RPGRPA bit (Master Group A Read protection)
The RPGRPA bit enables or disables memory protection for master group A reads on internal peripheral bus 9.
WPGRPA bit (Master Group A Write protection)
The WPGRPA bit enables or disables memory protection for master group A writes on internal peripheral bus 9.
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16.5.1.3
16. Memory Protection Unit (MPU)
Access Control Register for Memory Bus 4 (SMPUSRAM0)
Address(es): SMPU.SMPUSRAM0 4000 0C18h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
WPGR RPGRP WPCP RPCPU
PA
A
U
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read protection
0: CPU read memory protection disabled
1: CPU read memory protection enabled.
R/W
b1
WPCPU
CPU Write protection
0: CPU write memory protection disabled
1: CPU write memory protection enabled.
R/W
b2
RPGRPA
Master Group A Read
protection
0: Master group A read memory protection disabled
1: Master group A read memory protection enabled.
R/W
b3
WPGRPA
Master Group A Write
protection
0: Master group A write memory protection disabled
1: Master group A write memory protection enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read protection)
The RPCPU bit enables or disables memory protection for CPU reads on memory bus 4.
WPCPU bit (CPU Write protection)
The WPCPU bit enables or disables memory protection for CPU writes on memory bus 4.
RPGRPA bit (Master Group A Read protection)
The RPGRPA bit enables or disables memory protection for master group A reads on memory bus 4.
WPGRPA bit (Master Group A Write protection)
The WPGRPA bit enables or disables memory protection for master group A writes on memory bus 4.
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16.5.1.4
16. Memory Protection Unit (MPU)
Access Control Register for Memory Bus 5 (SMPUSRAM1)
Address(es): SMPU.SMPUSRAM1 4000 0C1Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
WPGR RPGRP WPCP RPCPU
PA
A
U
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU read disabled
1: Memory protection for CPU read enabled.
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU write disabled
1: Memory protection for CPU write enabled.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A read disabled
1: Memory protection for master group A read enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A write disabled
1: Memory protection for master group A write enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables the memory protection for CPU read memory bus 5.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables the memory protection for CPU write memory bus 5.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables the memory protection for master group A read memory bus 5.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables the memory protection for master group A write memory bus 5.
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16.5.1.5
16. Memory Protection Unit (MPU)
Access Control Register for Internal Peripheral Bus 1 (SMPUP0BIU)
Address(es): SMPU.SMPUP0BIU 4000 0C20h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
WPGR RPGRP WPCP RPCPU
PA
A
U
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read protection
0: Memory protection for CPU read disabled
1: Memory protection for CPU read enabled.
R/W
b1
WPCPU
CPU Write protection
0: Memory protection for CPU write disabled
1: Memory protection for CPU write enabled.
R/W
b2
RPGRPA
Master Group A Read
protection
0: Memory protection for master group A read disabled
1: Memory protection for master group A read enabled.
R/W
b3
WPGRPA
Master Group A Write
protection
0: Memory protection for master group A write disabled
1: Memory protection for master group A write enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read protection)
The RPCPU bit enables or disables memory protection for CPU reads on internal peripheral bus 1.
WPCPU bit (CPU Write protection)
The WPCPU bit enables or disables memory protection for CPU writes on internal peripheral bus 1.
RPGRPA bit (Master Group A Read protection)
The RPGRPA bit enables or disables memory protection for master group A reads on internal peripheral bus 1.
WPGRPA bit (Master Group A Write protection)
The WPGRPA bit enables or disables memory protection for master group A writes on internal peripheral bus 1.
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16.5.1.6
16. Memory Protection Unit (MPU)
Access Control Register for Internal Peripheral Bus 3 (SMPUP2BIU)
Address(es): SMPU.SMPUP2BIU 4000 0C24h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
WPGR RPGRP WPCP RPCPU
PA
A
U
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read protection
0: Memory protection for CPU read disabled
1: Memory protection for CPU read enabled.
R/W
b1
WPCPU
CPU Write protection
0: Memory protection for CPU write disabled
1: Memory protection for CPU write enabled.
R/W
b2
RPGRPA
Master Group A Read
protection
0: Memory protection for master group A read disabled
1: Memory protection for master group A read enabled.
R/W
b3
WPGRPA
Master Group A Write
protection
0: Memory protection for master group A write disabled
1: Memory protection for master group A write enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read protection)
The RPCPU bit enables or disables memory protection for CPU reads on internal peripheral bus 3, internal peripheral
bus 4, and internal peripheral bus 5.
WPCPU bit (CPU Write protection)
The WPCPU bit enables or disables memory protection for CPU writes on internal peripheral bus 3, internal peripheral
bus 4, and internal peripheral bus 5.
RPGRPA bit (Master Group A Read protection)
The RPGRPA bit enables or disables memory protection for master group A reads on internal peripheral bus 3, internal
peripheral bus 4, and internal peripheral bus 5.
WPGRPA bit (Master Group A Write protection)
The WPGRPA bit enables or disables memory protection for master group A writes on internal peripheral bus 3, internal
peripheral bus 4, and internal peripheral bus 5.
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16.5.1.7
16. Memory Protection Unit (MPU)
Access Control Register for Internal Peripheral Bus 7 (SMPUP6BIU)
Address(es): SMPU.SMPUP6BIU 4000 0C28h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
WPGR RPGRP WPCP RPCPU
PA
A
U
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read protection
0: CPU read memory protection disabled
1: CPU read memory protection enabled.
R/W
b1
WPCPU
CPU Write protection
0: CPU write memory protection disabled
1: CPU write memory protection enabled.
R/W
b2
RPGRPA
Master Group A Read
protection
0: Master group A read memory protection disabled
1: Master group A read memory protection enabled.
R/W
b3
WPGRPA
Master Group A Write
protection
0: Master group A write memory protection disabled
1: Master group A write memory protection enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read protection)
The RPCPU bit enables or disables memory protection for CPU reads on internal peripheral bus 7.
WPCPU bit (CPU Write protection)
The WPCPU bit enables or disables memory protection for CPU writes on internal peripheral bus 7.
RPGRPA bit (Master Group A Read protection)
The RPGRPA bit enables or disables memory protection for master group A reads on internal peripheral bus 7.
WPGRPA bit (Master Group A Write protection)
The WPGRPA bit enables or disables memory protection for master group A writes on internal peripheral bus 7.
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16.5.1.8
16. Memory Protection Unit (MPU)
Access Control Register for CS area (SMPUEXBIU)
Address(es): SMPU.SMPUEXBIU 4000 0C30h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
WPGR RPGRP WPCP RPCPU
PA
A
U
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read protection
0: CPU read memory protection disabled
1: CPU read memory protection enabled.
R/W
b1
WPCPU
CPU Write protection
0: CPU write memory protection disabled
1: CPU write memory protection enabled.
R/W
b2
RPGRPA
Master Group A Read
protection
0: Master group A read memory protection disabled
1: Master group A read memory protection enabled.
R/W
b3
WPGRPA
Master Group A Write
protection
0: Master group A write memory protection disabled
1: Master group A write memory protection enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read protection)
The RPCPU bit enables or disables memory protection for CPU reads in the CS area.
WPCPU bit (CPU Write protection)
The WPCPU bit enables or disables memory protection for CPU writes in the CS area.
RPGRPA bit (Master Group A Read protection)
The RPGRPA bit enables or disables memory protection for master group A reads in the CS area.
WPGRPA bit (Master Group A Write protection)
The WPGRPA bit enables or disables memory protection for master group A writes in the CS area.
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16.5.1.9
16. Memory Protection Unit (MPU)
Access Control Register for QSPI area (SMPUEXBIU2)
Address(es): SMPU.SMPUEXBIU2 4000 0C34h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
WPGR RPGRP WPCP RPCPU
PA
A
U
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read protection
0: CPU read memory protection disabled
1: CPU read memory protection enabled.
R/W
b1
WPCPU
CPU Write protection
0: CPU write memory protection disabled
1: CPU write memory protection enabled.
R/W
b2
RPGRPA
Master Group A Read
protection
0: Master group A read memory protection disabled
1: Master group A read memory protection enabled.
R/W
b3
WPGRPA
Master Group A Write
protection
0: Master group A write memory protection disabled
1: Master group A write memory protection enabled.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read protection)
The RPCPU bit enables or disables memory protection for CPU reads in the QSPI area.
WPCPU bit (CPU Write protection)
The WPCPU bit enables or disables memory protection for CPU writes in the QSPI area.
RPGRPA bit (Master Group A Read protection)
The RPGRPA bit enables or disables memory protection for master group A reads in the QSPI area.
WPGRPA bit (Master Group A Write protection)
The WPGRPA bit enables or disables memory protection for master group A writes in the QSPI area.
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16.5.1.10
16. Memory Protection Unit (MPU)
Slave MPU Control Register (SMPUCTL)
Address(es): SMPU.SMPUCTL 4000 0C00h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
PROTE
CT
OAD
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
OAD
Operation after
Detection
0: Non-maskable interrupt
1: Reset.
R/W
b1
PROTECT
Protection of Register
0: All bus slave register writes are permitted
1: All bus slave register writes are protected. Reads are
permitted.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits are used to enable or disable writes to the OAD and
PROTECT bits
R/(W)*1
Note 1.
Write data is not saved.
OAD bit (Operation after Detection)
The OAD bit generates either a reset or non-maskable interrupt when access to the protected region is detected by the bus
slave MPU. When the OAD bit is set, simultaneously write A5h to KEY[7:0] using halfword access.
PROTECT bit (Protection of Register)
The PROTECT bit enables or disables writes to the associated registers to be protected. The following registers are
protected by SMPUCTL.PROTECT:
SMPUMBIU
SMPUFBIU
SMPUSRAM0
SMPUSRAM1
SMPUP0BIU
SMPUP2BIU
SMPUP6BIU
SMPUEXBIU
SMPUEXBIU2.
When the PROTECT bit is set, simultaneously write A5h to KEY[7:0] using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writing to the OAD and PROTECT bits. When writing to the OAD and PROTECT
bits, simultaneously write A5h to KEY[7:0]. When values other than A5h are written to the KEY[7:0] bits, the OAD and
the PROTECT bits are not updated. The KEY[7:0] bits are always read as 00h.
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16.5.2
16. Memory Protection Unit (MPU)
Functions
16.5.2.1
Memory protection
The bus slave MPU monitoring uses access control information that is set for the individual access control registers,
whether or not access by the bus slaves violates the access control settings. If access to the protected region is detected,
the bus slave MPU generates a memory protection error.
The bus slave MPU is enabled by writing 1 to the Write Protect (WPCPU or WPGRPA) bit or the Read Protect (RPCPU
or RPGRPA) bit in the access control register (SMPUMBIU, SMPUFBIU, SMPUSRAM0, SMPUSRAM1,
SMPUP0BIU, SMPUP2BIU, SMPUP6BIU, SMPUEXBIU, and SMPUEXBIU2).
16.5.2.2
Protection of registers
Registers related to the bus slave MPU can be protected with the PROTECT bit in the SMPUCTL register.
16.5.2.3
Memory protection error
If access to a protected region is detected, the bus slave MPU generates a memory protection error. Set the OAD bit to
select whether the error is reported as a non-maskable interrupt or a reset.
The non-maskable interrupt status is indicated in ICU.NMISR.BUSSST. For details, see section 14, Interrupt Controller
Unit (ICU). The reset status is indicated in SYSTEM.RSTSR1.BUSSRF. For details, see section 6, Resets.
16.6
Security MPU
The MCU incorporates a security MPU with four secure regions that include the code flash, SRAM, and two security
functions. The secure regions can be protected from non-secure program accesses. Access to a protected region from a
non-secure program is not permitted.
Table 16.8 lists the specifications of the security MPU and Figure 16.10 shows a block diagram.
Table 16.8
Security MPU specifications
Specifications
Description
Secure regions
Code flash, SRAM, two security functions
Protected regions
0000 0000h to 00FF FFFFh (code flash memory)
1FF0 0000h to 200F FFFFh (SRAM)
400C 0000h to 400D FFFFh
4010 0000h to 407F FFFFh (secure data of security functions)
Number of regions
Program Counter: 2 regions
Data Access: 4 regions
Address specification for individual regions
Setting the address where regions start and end
Enable or disable setting for memory protection in individual
regions
Settings enabled or disabled for the associated region
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16. Memory Protection Unit (MPU)
Monitor for program counter
PC region 0
PC region 1
Program counter
Monitor for DCode bus
Region 0
Region 1
Bus of CPU
Mask of access
of CPU
Monitor for system bus
Region 1
Region 2
Region 3
Mask of access
of CPU
Monitor for master group A
Region 0
Region 1
Region 2
Region 3
Bus of
master group A
Figure 16.10
16.6.1
Mask of access
of master group A
Security MPU block diagram
Register Descriptions (Option-Setting Memory)
All security MPU registers are option-setting memory. Option-setting memory refers to a set of registers that are
available for selecting the state of the microcontroller after a reset. The option-setting memory is allocated in the flash.
16.6.1.1
Security MPU Program Counter Start Address Register (SECMPUPCSn)
(n = 0, 1)
Address(es): SECMPUPCS0 0000 0408h, SECMPUPCS1 0000 0410h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
SECMPUPCS[31:16]
The value set by user
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
SECMPUPCS[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b31 to b0
SECMPUPCS[31:0]
Region Start Address
Address where the region starts, for use in region
determination.
The lower 2 bits are read as 0. The value range
should be 0000 0000h to 00FF FFFCh and
1FF0 0000h to 200F FFFCh excluding the
reserved areas.
When setting this register value in the optionsetting memory, the write value of the lower 2 bits
should be 0.
R
The SECMPUPCSn and SECMPUPCEn registers specify the security fetch region for the code flash (0000 0000h to
00FF FFFFh, excluding the reserved areas) or SRAM (1FF0 0000h to 200F FFFFh, excluding the reserved areas). The
secure program is executed in the memory space defined by the SECMPUPCSn and SECMPUPCEn registers and can
access the secure data specified in the SECMPUSm and SECMPUEm registers (m = 0 to 3). The set up of memory
mirror space (0200 0000h to 027F FFFFh) for MMF is not allowed.
An address space of greater than 12 bytes is required between the last instruction of a non-secure program and the first
instruction of a secure program.
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16.6.1.2
16. Memory Protection Unit (MPU)
Security MPU Program Counter End Address Register (SECMPUPCEn)
(n = 0, 1)
Address(es): SECMPUPCE0 0000 040Ch, SECMPUPCE1 0000 0414h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
SECMPUPCE[31:16]
The value set by user
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
SECMPUPCE[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b31 to b0
SECMPUPCE[31:0]
Region End Address
Address where the region ends, for use in region
determination.
The lower 2 bits are read as 1. The value range
should be 0000 0003h to 00FF FFFFh and
1FF0 0003h to 200F FFFFh, excluding the
reserved areas.
When setting this register value in the optionsetting memory, the write value of the lower 2 bits
should be 1.
R
16.6.1.3
Security MPU Region 0 Start Address Register (SECMPUS0)
Address(es): SECMPUS0 0000 0418h
b31
b30
b29
b28
b27
b26
b25
b24
—
—
—
—
—
—
—
—
SECMPUS0[23:16]
0
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
Value after reset:
b23
b7
b22
b6
b21
b5
b20
b4
b19
b3
b18
b17
b16
b2
b1
b0
SECMPUS0[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b23 to b0
SECMPUS0[23:0]
Region Start Address
Address where the region starts, for use in region
determination.
The lower 2 bits are read as 0. The value range should be
0000 0000h to 00FF FFFCh excluding the reserved areas.
When setting this register value in the option-setting memory,
the write value of the lower 2 bits should be 0.
R
b31 to b24
—
Reserved
These bits are read as 0.
When setting this register value in the option-setting memory,
the write value of these bits should be 0.
R
The SECMPUS0 and SECMPUE0 registers specify the secure program and the flash data (0000 0000h to 00FF FFFFh,
excluding the reserved areas). The memory space defined in the SECMPUS0 and SECMPUE0 registers can only be
accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
Setting of the vector table area is prohibited.
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16.6.1.4
16. Memory Protection Unit (MPU)
Security MPU Region 0 End Address Register (SECMPUE0)
Address(es): SECMPUE0 0000 041Ch
b31
b30
b29
b28
b27
b26
b25
b24
—
—
—
—
—
—
—
—
SECMPUE0[23:16]
0
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
Value after reset:
b23
b7
b22
b6
b21
b5
b20
b4
b19
b3
b18
b17
b16
b2
b1
b0
SECMPUE0[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b23 to b0
SECMPUE0[23:0]
Region End Address
Address where the region ends, for use in region
determination.
The lower 2 bits are read as 1. The value range should be
0000 0003h to 00FF FFFFh, excluding the reserved areas.
When setting this register value in the option-setting memory,
the write value of the lower 2 bits should be 1.
R
b31 to b24
—
Reserved
These bits are read as 0.
When setting this register value in the option-setting memory,
the write value of these bits should be 0.
R
16.6.1.5
Security MPU Region 1 Start Address Register (SECMPUS1)
Address(es): SECMPUS1 0000 0420h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
0
0
SECMPUS1[31:16]
The value set by user
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
SECMPUS1[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b31 to b0
SECMPUS1[31:0]
Region Start Address
Address where the region starts, for use in region
determination.
The lower 2 bits are read as 0. The value range should be
1FF0 0000h to 200F FFFCh, excluding the reserved areas.
When setting this register value in the option-setting memory,
the write value of the lower 2 bits should be 0, and the write
value of bits [31:20] should be 1FFh or 200h.
R
The SECMPUS1 and SECMPUE1 registers specify the secure data of the SRAM (1FF0 0000h to 200F FFFFh,
excluding the reserved areas). The memory space defined in the SECMPUS1 and SECMPUE1 registers can only be
accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
Setting of the stack area and the vector table is prohibited.
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16.6.1.6
16. Memory Protection Unit (MPU)
Security MPU Region 1 End Address Register (SECMPUE1)
Address(es): SECMPUE1 0000 0424h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
1
1
SECMPUE1[31:16]
The value set by user
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
SECMPUE1[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b31 to b0
SECMPUE1[31:0]
Region End Address
Address where the region ends, for use in region
determination.
The lower 2 bits are read as 1. The value range should be
1FF0 0003h to 200F FFFFh, excluding the reserved areas.
When setting this register value in the option-setting memory,
the write value of the lower 2 bits should be 1, and the write
value of bits [31:20] should be 1FFh or 200h.
R
16.6.1.7
Security MPU Region 2 Start Address Register (SECMPUS2)
Address(es): SECMPUS2 0000 0428h
b31
b30
b29
b28
b27
b26
b25
b24
b23
—
—
—
—
—
—
—
—
—
SECMPUS2[22:16]
0
1
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
b7
Value after reset:
b22
b6
b21
b5
b20
b4
b19
b3
b18
b2
b17
b16
b1
b0
0
0
SECMPUS2[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b22 to b0
SECMPUS2[22:0]
Region Start Address
Address where the region starts, for use in region
determination.
The lower 2 bits are read as 0. The value range should be
400C 0000h to 400D FFFCh and 4010 0000h to 407F FFFCh.
When setting this register value in the option-setting memory,
the write value of the lower 2 bits should be 0.
R
b31 to b23
—
Reserved
These bits are read as 0100 0000 0b. When setting this
register value in the option-setting memory, the write value of
these bits should be 0100 0000 0b.
R
The SECMPUS2 and SECMPUE2 registers specify the secure data of the security functions (400C 0000 to 400D FFFFh
and 4010 0000 to 407F FFFFh). The memory space defined in the SECMPUS2 and SECMPUE2 registers can only be
accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
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16.6.1.8
16. Memory Protection Unit (MPU)
Security MPU Region 2 End Address Register (SECMPUE2)
Address(es): SECMPUE2 0000 042Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
—
—
—
—
—
—
—
—
—
SECMPUE2[22:16]
0
1
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
b7
Value after reset:
b22
b6
b21
b5
b20
b4
b19
b3
b18
b2
b17
b16
b1
b0
1
1
SECMPUE2[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b22 to b0
SECMPUE2[22:0]
Region End Address
Address where the region ends, for use in region
determination.
The lower 2 bits are read as 1. The value range should be
400C 0003h to 400D FFFFh and 4010 0003h to 407F FFFFh.
When setting this register value in the option-setting memory,
the write value of the lower 2 bits should be 1.
R
b31 to b23
—
Reserved
These bits are read as 0100 0000 0b. When setting this
register value in the option-setting memory, the write value of
these bits should be 0100 0000 0b.
R
16.6.1.9
Security MPU Region 3 Start Address Register (SECMPUS3)
Address(es): SECMPUS3 0000 0430h
b31
b30
b29
b28
b27
b26
b25
b24
b23
—
—
—
—
—
—
—
—
—
SECMPUS3[22:16]
0
1
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
b7
Value after reset:
b22
b6
b21
b5
b20
b4
b19
b3
b18
b2
b17
b16
b1
b0
0
0
SECMPUS3[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b22 to b0
SECMPUS3[22:0]
Region Start Address
Address where the region starts, for use in region
determination.
The lower 2 bits are read as 0. The value range should be
400C 0000h to 400D FFFCh and 4010 0000h to 407F FFFCh.
When setting this register value in the option-setting memory,
the write value of the lower 2 bits should be 0.
R
b31 to b23
—
Reserved
These bits are read as 0100 0000 0b. When setting this
register value in the option-setting memory, the write value of
these bits should be 0100 0000 0b.
R
The SECMPUS3 and SECMPUE3 registers specify the secure data of the security functions (400C 0000h to
400D FFFFh and 4010 0000h to 407F FFFFh). The memory space defined in the SECMPUS3 and SECMPUE3 registers
can only be accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
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16.6.1.10
16. Memory Protection Unit (MPU)
Security MPU Region 3 End Address Register (SECMPUE3)
Address(es): SECMPUE3 0000 0434h
b31
b30
b29
b28
b27
b26
b25
b24
b23
—
—
—
—
—
—
—
—
—
0
1
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
Value after reset:
b22
b21
b20
b19
b18
b17
b16
b1
b0
1
1
SECMPUE3[22:16]
The value set by user
b6
b5
b4
b3
b2
SECMPUE3[15:0]
The value set by user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b22 to b0
SECMPUE3[22:0]
Region End Address
Address where the region ends, for use in region
determination.
The lower 2 bits are read as 1. The value range should be
400C 0003h to 400D FFFFh and 4010 0003h to
407F FFFFh.
When setting this register value in the option-setting memory,
the write value of the lower 2 bits should be 1.
R
b31 to b23
—
Reserved
These bits are read as 0100 0000 0b. When setting this
register value in the option-setting memory, the write value of
these bits should be 0100 0000 0b.
R
16.6.1.11
Security MPU Access Control Register (SECMPUAC)
Address(es): SECMPUAC 0000 0438h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
DISPC DISPC
1
0
1
1
1
1
1
1
The value set by
user
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
DIS3
DIS2
DIS1
DIS0
1
1
1
1
The value set by user
Bit
Symbol
Bit name
Description
R/W
b0
DIS0
Region 0 Disable
0: Security MPU region 0 enabled
1: Security MPU region 0 disabled.
R
b1
DIS1
Region 1 Disable
0: Security MPU region 1 enabled
1: Security MPU region 1 disabled.
R
b2
DIS2
Region 2 Disable
0: Security MPU region 2 enabled
1: Security MPU region 2 disabled.
R
b3
DIS3
Region 3 Disable
0: Security MPU region 3 enabled
1: Security MPU region 3 disabled.
R
b7 to b4
—
Reserved
These bits are read as 1.
When setting this register value in the option-setting memory,
the write value of bits [7:4] should be 1.
R
b8
DISPC0
PC Region 0 Disable
0: Security MPU PC region 0 enabled
1: Security MPU PC region 0 disabled.
R
b9
DISPC1
PC Region 1 Disable
0: Security MPU PC region 1 enabled
1: Security MPU PC region 1 disabled.
R
b15 to b10
—
Reserved
These bits are read as 1.
When setting this register value in the option-setting memory,
the write value of bits [15:10] should be 1.
R
Note:
Note:
When flash memory is erased, the security MPU is disabled.
To enable and disable the security MPU, see section 16.6.2, Memory Protection.
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16. Memory Protection Unit (MPU)
DIS0 bit (Region 0 Disable)
The DIS0 bit enables or disables the security MPU region 0. If security MPU region 0 is enabled, the code flash region
within the limits set up by SECMPUS0 and SECMPUE0 is secure data.
DIS1 bit (Region 1 Disable)
The DIS1 bit enables or disables the security MPU region 1. If security MPU region 1 is enabled, the SRAM region
within the limits set up by SECMPUS1 and SECMPUE1 is secure data.
DIS2 bit (Region 2 Disable)
The DIS2 bit enables or disables the security MPU region 2. If security MPU region 2 is enabled, the secure data of the
security function region within the limits set up by SECMPUS2 and SECMPUE2 is secure data.
DIS3 bit (Region 3 Disable)
The DIS3 bit enables or disables the security MPU region 3. If security MPU region 3 is enabled, the secure data of the
security function region within the limits set up by SECMPUS3 and SECMPUE3 is secure data.
DISPC0 bit (PC Region 0 Disable)
The DISPC0 bit enables or disables the security MPU PC region 0. If security MPU PC region 0 is enabled, the code
flash or the SRAM region within the limits set up by SECMPUPCS0 and SECMPUPCE0 contains a secure program.
DISPC1 bit (PC Region 1 Disable)
The DISPC1 bit enables or disables the security MPU PC region 1. If security MPU PC region 1 is enabled, the code
flash or the SRAM region within the limits set up by SECMPUPCS1 and SECMPUPCE1 contains a secure program.
16.6.2
Memory Protection
The security MPU protects the secured regions (the code flash, the SRAM, two security functions) from being accessed
by non-secure programs. If access to a protected region is detected, the access becomes invalid.
When the security MPU is enabled, DISPC0 or DISPC1 in the Security MPU Access Control Register (SECMPUAC)
must be set to 0, and DIS0, DIS1, DIS2, or DIS3 in the Security MPU Access Control Register (SECMPUAC) must be
set to 0. When the security MPU is disabled, all bits in DISPC0, DISPC1, DIS0, DIS1, DIS2 and DIS3 in the Security
MPU Access Control Register (SECMPUAC) must be set to 1. Other settings in the Security MPU Access Control
Register (SECMPUAC) are prohibited.
The security MPU provides access protection in the following conditions:
Secure data is accessed from a non-secure program
Secure data is accessed from other than the CPU (DMAC, DTC)
Secure data is accessed from the debugger.
Secure data can be accessed in the following condition:
Secure data can be accessed from a secure program.
Note:
Secure program:
Code flash or SRAM regions within the limits set up by SECMPUPCS0 and SECMPUPCE0,
Code flash or SRAM regions within the limits set up by SECMPUPCS1 and SECMPUPCE1.
Non-secure program: All regions outside the secure program.
Secure data:
Code flash region within the limits set up by SECMPUS0 and SECMPUE0.
SRAM region within the limits set up by SECMPUS1 and SECMPUE1,
security function region within the limits set up by SECMPUS2 and SECMPUE2,
security function region within the limits set up by SECMPUS3 and SECMPUE3.
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16. Memory Protection Unit (MPU)
Security MPU setting
Memory
Memory
Non-secure data
Secure function
Region 3
Secure data
Non-secure data
Secure function
Region 2
Secure data
Non-secure
program
Non-secure data
SRAM
Region 1
Secure data
PC region 1
Code flash
Secure program
Non-secure data
Region 0
Non-secure
program
Secure data
PC region 0
Secure program
Non-secure
program
Secure program in code flash (PC region 0) can access all data (secure data and non-secure data).
Secure program in SRAM (PC region 1) can access all data (secure data and non-secure data).
Non-secure program (not PC region 0 or PC region 1) cannot access secure data (region 0, region 1, region 2, region 3).
Non-secure program (not PC region 0 or PC region 1) can access non-secure data.
Figure 16.11
16.6.3
Use case of security MPU
Notes on Debug
The protected memory cannot be debugged if the security MPU is enabled. Disable the security MPU when debugging a
secure program.
16.7
References
1. ARM®v7-M Architecture Reference Manual (ARM DDI 0403D)
2. ARM® Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D)
3. ARM®Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).
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17. DMA Controller (DMAC)
17.
DMA Controller (DMAC)
17.1
Overview
The MCU includes a 4-channel DMA Controller (DMAC) that can transfer data without intervention from the CPU.
When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer
destination address.
Table 17.1 lists the DMAC specifications and Figure 17.1 shows a block diagram.
Table 17.1
DMAC specifications
Parameter
Description
Number of channels
4 channels (DMACm, m = 0 to 3)
Transfer space
4 GB (0000 0000h to FFFF FFFFh, excluding reserved areas)
Maximum transfer volume
64M data units (maximum number of transfers in block transfer mode: 1024 data units ×
65536 blocks)
DMA activation source
Selectable for each channel:
Software trigger
Interrupt requests from peripheral modules or trigger from external interrupt input pins.*1
Channel priority
Channel 0 > Channel 1 > Channel 2 > Channel 3 (Channel 0: highest)
Transfer data
Transfer mode
Single data
Bit length: 8, 16, 32 bits
Block size
Number of data: 1 to 1024
Normal transfer mode One data transfer by one DMA transfer request
Selectable free running mode (total number of data transfers is not specified).
Repeat transfer mode One data transfer by one DMA transfer request
Program returns to the transfer start address on completion of the repeat size of data
transfer specified for the transfer source or destination
Maximum settable repeat size: 1024.
Block transfer mode
One data block transfer by one DMA transfer request
Maximum settable block size: 1024 data.
Selective
functions
Extended repeat area
function
Allows data to be transferred by repeating the address values in the specified range, with
the upper bit values in the transfer address register remaining fixed
Area of 2 bytes to 128 MB individually selectable as the extended repeat area for transfer
source and destination.
Interrupt
request
(DMACm_INT)
Transfer end interrupt
Generated on completion of transferring data volume specified by the transfer counter
Transfer escape end
interrupt
Generated when:
The repeat size of data transfer is complete
The source address of the extended repeat area overflows
The destination address of the extended repeat area overflows.
Event link activation
(DMACm_INT)
An event link request is generated after each data transfer (for block transfer, after each
block is transferred)
Module-stop function
Module-stop state can be set to reduce power consumption
Note 1.
For details on DMAC activation sources, see Table 14.3, Interrupt Vector Table in section 14, Interrupt Controller Unit (ICU).
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17. DMA Controller (DMAC)
DMAC
DMAC registers
DMAC channels
(CH0 to CH3)
DMSAR
DMDAR
DMCRA
DMCRB
DMOFR
DMTMD
DMAMD
DMSTS
DMCNT
DMCSL
Activation control
4
Interrupt
controller
DMA
transfer
request
arbitration
DMA start
request
DMAC
response
4
Interrupt
request for ICU
(DMACm_INT)
DMAST
DMIST
4
m = 0 to 3
Interrupt
request for ELC
(DMACm_INT)
ELC
Register control
DMAC response
control
4
m = 0 to 3
DMAC core
Source address
Destination address
Transfer counter
Block counter
Transfer mode
DMAC
control
circuit
Bus interface
Internal peripheral bus 1
DMA bus
Code
flash
memory
Figure 17.1
SRAM0
SRAM1
Data
flash
memory
Internal
peripherals
External
bus controller
System bus
DMA bus
DMAC block diagram
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17.2
17. DMA Controller (DMAC)
Register Descriptions
17.2.1
DMA Source Address Register (DMSAR)
Address(es): DMAC0.DMSAR 4000 5000h, DMAC1.DMSAR 4000 5040h, DMAC2.DMSAR 4000 5080h, DMAC3.DMSAR 4000 50C0h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
Setting range
R/W
b31 to b0
Specifies the transfer source start address
0000 0000h to FFFF FFFFh (4 GB)
R/W
Set DMSAR while DMAC activation is disabled (the DMST bit in DMAST = 0) or DMA transfer is disabled (the DTE
bit in DMCNT = 0).
Note:
Address alignment in this register must match the transfer data size value selected in the SZ bit in DMTMD.
17.2.2
DMA Destination Address Register (DMDAR)
Address(es): DMAC0.DMDAR 4000 5004h, DMAC1.DMDAR 4000 5044h, DMAC2.DMDAR 4000 5084h, DMAC3.DMDAR 4000 50C4h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
Setting range
R/W
b31 to b0
Specifies the transfer destination start address
0000 0000h to FFFF FFFFh (4 GB)
R/W
Set DMDAR while DMAC activation is disabled (the DMST bit in DMAST = 0) or DMA transfer is disabled (the DTE
bit in DMCNT = 0).
Note:
Address alignment in this register must match the transfer data size value selected in the SZ bit in DMTMD.
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17.2.3
17. DMA Controller (DMAC)
DMA Transfer Count Register (DMCRA)
Address(es): DMAC0.DMCRA 4000 5008h, DMAC1.DMCRA 4000 5048h, DMAC2.DMCRA 4000 5088h, DMAC3.DMCRA 4000 50C8h
Normal transfer mode
DMCRAH
Value after reset:
b31
b30
b29
b28
b27
b26
—
—
—
—
—
—
0
0
0
0
0
0
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
DMCRAL
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Repeat transfer mode, block transfer mode
DMCRAH
Value after reset:
b31
b30
b29
b28
b27
b26
—
—
—
—
—
—
0
0
0
0
0
0
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
DMCRAL
Value after reset:
b15
b14
b13
b12
b11
b10
0
0
0
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
Symbol
Bit name
Description
R/W
DMCRAL
Lower bits of transfer count
Specifies the number of transfer operations
R/W
DMCRAH
Upper bits of transfer count
Note:
(1)
R/W
In repeat and block transfer modes, set the same value for DMCRAH and DMCRAL.
Normal transfer mode (MD[1:0] bits in DMACm.DMTMD = 00b)
In normal transfer mode, DMCRAL functions as a 16-bit transfer counter. The number of transfer operations is one when
the setting is 0001h, and 65535 when it is FFFFh. The value is decremented by one each time data is transferred. A
setting of 0000h indicates an unspecified number of transfer operations. Data transfer is performed with the transfer
counter stopped, that is, in free running mode. Do not use DMCRAH in normal transfer mode. Write 0000h to
DMCRAH.
(2)
Repeat transfer mode (MD[1:0] bits in DMACm.DMTMD = 01b)
In repeat transfer mode, DMCRAH specifies the repeat size and DMCRAL functions as a 10-bit transfer counter. The
number of transfer operations is one when the setting is 001h, 1023 when it is 3FFh, and 1024 when it is 000h. In this
mode, a value in the range of 000h to 3FFh (1 to 1024) can be set for DMCRAH and DMCRAL.
Setting bits [15:10] in DMCRAL is invalid. Write 0 to these bits. The value in DMCRAL is decremented by 1 each time
data is transferred until it reaches 000h, at which time the value in DMCRAH is loaded into DMCRAL.
(3)
Block transfer mode (MD[1:0] bits in DMACm.DMTMD = 10b)
In block transfer mode, DMCRAH specifies the block size and DMCRAL functions as a 10-bit block size counter. The
block size is one when the setting is 001h, 1023 when it is 3FFh, and 1024 when it is 000h. In this mode, a value in the
range of 000h to 3FFh can be set for DMCRAH and DMCRAL.
Setting bits [15:10] in DMCRAL is invalid. Write 0 to these bits. The value in DMCRAL is decremented by 1 each time
data is transferred until it reaches 000h, at which time the value in DMCRAH is loaded into DMCRAL.
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17.2.4
17. DMA Controller (DMAC)
DMA Block Transfer Count Register (DMCRB)
Address(es): DMAC0.DMCRB 4000 500Ch, DMAC1.DMCRB 4000 504Ch, DMAC2.DMCRB 4000 508Ch, DMAC3.DMCRB 4000 50CCh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
Setting range
R/W
b15 to b0
Specifies the number of block transfer or repeat
transfer operations
0001h to FFFFh (1 to 65535)
0000h (65536).
R/W
DMCRB specifies the number of operations in block and repeat transfer modes. The number of transfer operations is one
when the setting is 0001h, 65535 when it is FFFFh, and 65536 when it is 0000h.
In repeat transfer mode, the value is decremented by one when the final data of one repeat size is transferred. In block
transfer mode, the value is decremented by 1 when the final data of one block size is transferred. Do not use DMCRB in
normal transfer mode as the setting is invalid.
17.2.5
DMA Transfer Mode Register (DMTMD)
Address(es): DMAC0.DMTMD 4000 5010h, DMAC1.DMTMD 4000 5050h, DMAC2.DMTMD 4000 5090h, DMAC3.DMTMD 4000 50D0h
b15
b14
MD[1:0]
Value after reset:
0
0
b13
b12
b11
b10
DTS[1:0]
—
—
0
0
0
0
b9
b8
SZ[1:0]
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
DCTG[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
DCTG[1:0]
Transfer Request
Source Select
b1 b0
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b9, b8
SZ[1:0]
Transfer Data Size
Select
b9 b8
R/W
0
0
1
1
0
0
1
1
0: Software
1: Interrupts*1 from peripheral modules or external interrupt input pins
0: Setting prohibited
1: Setting prohibited.
0: 8 bits
1: 16 bits
0: 32 bits
1: Setting prohibited.
b11, b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13, b12
DTS[1:0]
Repeat Area Select
b13 b12
R/W
b15, b14
MD[1:0]
Transfer Mode Select
b15 b14
R/W
Note 1.
0
0
1
1
0
0
1
1
0: The destination is specified as the repeat area or block area
1: The source is specified as the repeat area or block area
0: The repeat area or block area is not specified
1: Setting prohibited.
0: Normal transfer
1: Repeat transfer
0: Block transfer
1: Setting prohibited.
To select the DMAC activation source, use the DELSRn registers of the ICU. For details on DMAC activation sources, see
Table 14.4, Event table in section 14, Interrupt Controller Unit (ICU).
DTS[1:0] bits (Repeat Area Select)
The DTS[1:0] bits select either the source or destination as the repeat area in repeat transfer mode and the block area in
block transfer mode. In normal transfer mode, these bit settings are invalid.
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17.2.6
17. DMA Controller (DMAC)
DMA Interrupt Setting Register (DMINT)
Address(es): DMAC0.DMINT 4000 5013h, DMAC1.DMINT 4000 5053h, DMAC2.DMINT 4000 5093h, DMAC3.DMINT 4000 50D3h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
DTIE
ESIE
0
0
0
0
0
b2
b1
b0
RPTIE SARIE DARIE
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DARIE
Destination Address Extended Repeat
Area Overflow Interrupt Enable
0: Disable
1: Enable.
R/W
b1
SARIE
Source Address Extended Repeat Area
Overflow Interrupt Enable
0: Disable
1: Enable.
R/W
b2
RPTIE
Repeat Size End Interrupt Enable
0: Disable
1: Enable.
R/W
b3
ESIE
Transfer Escape End Interrupt Enable
0: Disable
1: Enable.
R/W
b4
DTIE
Transfer End Interrupt Enable
0: Disable
1: Enable.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0
R/W
DARIE bit (Destination Address Extended Repeat Area Overflow Interrupt Enable)
When an extended repeat area overflow occurs on the destination address when the DARIE bit is set to 1, the DTE bit in
DMCNT sets to 0. At the same time, the ESIF flag in DMSTS sets to 1 to indicate an interrupt triggered by an extended
repeat area overflow on the destination address.
When block transfer mode is used with the extended repeat area function, an interrupt occurs after completion of a 1block size transfer. When the DTE bit is set to 1 in DMACm.DMCNT of the channel associated with the stopped
transfer, the transfer resumes from the state it was in when the transfer stopped. When the extended repeat area is not
specified for the destination address, this bit is ignored.
SARIE bit (Source Address Extended Repeat Area Overflow Interrupt Enable)
When an extended repeat area overflow occurs on the source address when the SARIE bit is set to 1, the DTE bit in
DMCNT sets to 0. At the same time, the ESIF flag in DMSTS sets to 1 to indicate an interrupt request triggered by an
extended repeat area overflow on the source address.
When block transfer mode is used with the extended repeat area function, an interrupt occurs after completion of a 1block size transfer. When the DTE bit is set to 1 in DMACm.DMCNT of the channel associated with the stopped
transfer, the transfer resumes from the state it was in when the transfer stopped. When the extended repeat area is not
specified for the source address, this bit is ignored.
RPTIE bit (Repeat Size End Interrupt Enable)
When the RPTIE bit is set to 1 in repeat transfer mode, the DTE bit in DMCNT sets to 0 after completion of a 1-repeat
size data transfer. At the same time, the ESIF flag in DMSTS sets to 1 to indicate that the repeat size end interrupt request
occurred. The repeat size end interrupt request can be generated even when the DTS[1:0] bits in DMTMD are 10b
(repeat area or block area is not specified).
When the RPTIE bit is set to 1 in block transfer mode, the DTE bit in DMCNT sets to 0 after completion of a 1-block
data transfer in the same way as repeat transfer mode. At the same time, the ESIF flag in DMSTS sets to 1 to indicate that
the repeat size end interrupt request occurred. The repeat size end interrupt request can be generated even when the
DTS[1:0] bits in DMTMD are 10b (repeat area or block area is not specified).
ESIE bit (Transfer Escape End Interrupt Enable)
The ESIE bit enables the transfer escape end interrupt requests (repeat size end interrupt request and extended repeat area
overflow interrupt request) that occur during DMA transfer. The interrupt occurs when this bit is 1 and the ESIF flag in
DMSTS is set to 1. To clear the transfer escape end interrupt, clear this bit or the ESIF flag in DMSTS to 0.
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17. DMA Controller (DMAC)
DTIE bit (Transfer End Interrupt Enable)
The DTIE bit enables the transfer end interrupt request that occurs on completion of a specified number of data transfers.
The interrupt occurs when this bit is 1 and the DTIF flag in DMSTS is set to 1. To clear the transfer end interrupt, clear
this bit or the DTIF flag in DMSTS to 0.
17.2.7
DMA Address Mode Register (DMAMD)
Address(es): DMAC0.DMAMD 4000 5014h, DMAC1.DMAMD 4000 5054h, DMAC2.DMAMD 4000 5094h, DMAC3.DMAMD 4000 50D4h
b15
b14
SM[1:0]
Value after reset:
0
0
b13
b12
b11
—
0
b10
b9
b8
SARA[4:0]
0
0
0
b7
b6
DM[1:0]
0
0
0
0
b5
b4
b3
—
0
b2
b1
b0
0
0
DARA[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
DARA[4:0]
Destination Address Extended
Repeat Area
Specifies the extended repeat area on the destination address.
For details on the settings, see Table 17.2.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7, b6
DM[1:0]
Destination Address Update
Mode
b7 b6
R/W
b12 to b8
SARA[4:0]
Source Address Extended
Repeat Area
Specifies the extended repeat area on the source address. For
details on the settings, see Table 17.2.
R/W
b13
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b15, b14
SM[1:0]
Source Address Update Mode
b15 b14
R/W
0
0
1
1
0
0
1
1
0: Destination address is fixed
1: Offset addition
0: Destination address is incremented
1: Destination address is decremented.
0: Source address is fixed
1: Offset addition
0: Source address is incremented
1: Source address is decremented.
DARA[4:0] bits (Destination Address Extended Repeat Area)
The DARA[4:0] bits specify the extended repeat area on the destination address. The extended repeat area function is
realized through an update of the specified lower address bits with the remaining upper address bits fixed. The size of the
extended repeat area can be any power of two between 2 bytes and 128 MB. The start address of the extended repeat area
is set when the lower address overflows the extended repeat area on an address increment. Similarly, the end address of
the extended repeat area is set when the lower address underflows the extended repeat area on an address decrement.
Do not specify the extended repeat area on the destination address when a repeat area or block area is specified as the
transfer destination. When repeat or block transfer is selected, and when DMACm.DMTMD.DTS[1:0] = 00b (the
transfer destination is specified as the repeat or block area), write 00000b in the DARA[4:0] bits.
To request an interrupt when an overflow or underflow occurs in the extended repeat area, set the DARIE bit in DMINT
to 1. Table 17.2 lists the extended repeat areas associated with each setting.
DM[1:0] bits (Destination Address Update Mode)
The DM[1:0] bits select the update mode for the destination address as follows:
When increment is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the destination address is
incremented by 1, 2, and 4, respectively
When decrement is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the destination address is
decremented by 1, 2, and 4, respectively
When offset addition is selected, the offset specified in the DMACm.DMOFR register is added to the address.
SARA[4:0] bits (Source Address Extended Repeat Area)
The SARA[4:0] bits specify the extended repeat area on the source address. The extended repeat area function is realized
through an update of the specified lower address bits with the remaining upper address bits fixed. The size of the
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17. DMA Controller (DMAC)
extended repeat area can be any power of two between 2 bytes and 128 MB. The start address of the extended repeat area
is set when the lower address overflows the extended repeat area on an address increment. Similarly, the end address of
the extended repeat area is set when the lower address underflows the extended repeat area on an address decrement.
Do not specify the extended repeat area on the source address when the repeat or block area is specified as a transfer
source. When repeat or block transfer is selected, and when DMACm.DMTMD.DTS[1:0] = 01b (the transfer source is
specified as the repeat area or block area), write 00000b in the SARA[4:0] bits.
To request an interrupt when an overflow or underflow occurs in the extended repeat area, set the SARIE bit in DMINT
to 1. Table 17.2 lists the extended repeat areas associated with each setting.
SM[1:0] (Source Address Update Mode)
The SM[1:0] bits select the update mode for the source address:
When increment is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the source address is
incremented by 1, 2, and 4, respectively
When decrement is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the source address is
decremented by 1, 2, and 4, respectively
When offset addition is selected, the offset specified in the DMACm.DMOFR register is added to the address.
Table 17.2
SARA[4:0] or DARA[4:0] settings and corresponding repeat areas
SARA[4:0] or DARA[4:0]
Extended repeat area
00000b
Not specified
00001b
2 bytes specified as extended repeat area by the lower 1 bit of the address
00010b
4 bytes specified as extended repeat area by the lower 2 bits of the address
00011b
8 bytes specified as extended repeat area by the lower 3 bits of the address
00100b
16 bytes specified as extended repeat area by the lower 4 bits of the address
00101b
32 bytes specified as extended repeat area by the lower 5 bits of the address
00110b
64 bytes specified as extended repeat area by the lower 6 bits of the address
00111b
128 bytes specified as extended repeat area by the lower 7 bits of the address
01000b
256 bytes specified as extended repeat area by the lower 8 bits of the address
01001b
512 bytes specified as extended repeat area by the lower 9 bits of the address
01010b
1 KB specified as extended repeat area by the lower 10 bits of the address
01011b
2 KB specified as extended repeat area by the lower 11 bits of the address
01100b
4 KB specified as extended repeat area by the lower 12 bits of the address
01101b
8 KB specified as extended repeat area by the lower 13 bits of the address
01110b
16 KB specified as extended repeat area by the lower 14 bits of the address
01111b
32 KB specified as extended repeat area by the lower 15 bits of the address
10000b
64 KB specified as extended repeat area by the lower 16 bits of the address
10001b
128 KB specified as extended repeat area by the lower 17 bits of the address
10010b
256 KB specified as extended repeat area by the lower 18 bits of the address
10011b
512 KB specified as extended repeat area by the lower 19 bits of the address
10100b
1 MB specified as extended repeat area by the lower 20 bits of the address
10101b
2 MB specified as extended repeat area by the lower 21 bits of the address
10110b
4 MB specified as extended repeat area by the lower 22 bits of the address
10111b
8 MB specified as extended repeat area by the lower 23 bits of the address
11000b
16 MB specified as extended repeat area by the lower 24 bits of the address
11001b
32 MB specified as extended repeat area by the lower 25 bits of the address
11010b
64 MB specified as extended repeat area by the lower 26 bits of the address
11011b
128 MB specified as extended repeat area by the lower 27 bits of the address
11100b to 11111b
Setting prohibited
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17.2.8
17. DMA Controller (DMAC)
DMA Offset Register (DMOFR)
Address(es): DMAC0.DMOFR 4000 5018h, DMAC1.DMOFR 4000 5058h, DMAC2.DMOFR 4000 5098h, DMAC3.DMOFR 4000 50D8h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
Setting range
R/W
b31 to b0
Specifies the offset when offset addition is selected
as the address update mode for transfer source or
destination
0000 0000h to 00FF FFFFh (0 byte to (16 MB – 1 byte))
FF00 0000h to FFFF FFFFh (-16 MB to -1 byte)
R/W
Only write to this register while the DMAC operation is stopped or DMA transfer is disabled, but not during data
transfer. Setting bits [31:25] is invalid. The value in bit [24] is extended to bits [31:25]. Reading DMOFR returns the
extended value.
17.2.9
DMA Transfer Enable Register (DMCNT)
Address(es): DMAC0.DMCNT 4000 501Ch, DMAC1.DMCNT 4000 505Ch, DMAC2.DMCNT 4000 509Ch, DMAC3.DMCNT 4000 50DCh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DTE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DTE
DMA Transfer Enable
0: Disable
1: Enable.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
DTE bit (DMA Transfer Enable)
The DTE bit enables DMA transfer. To enable DMA transfer, set the DMST bit in DMAST to 1 to enable DMAC
activation, and then set the DTE bit to 1 to enable DMA transfer for the associated channel.
[Setting condition]
When 1 is written to this bit.
[Clearing conditions]
When 0 is written to this bit
When the specified total volume of data transfer is complete
When DMA transfer is stopped by a repeat size end interrupt
When DMA transfer is stopped by an extended repeat area overflow interrupt.
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17.2.10
17. DMA Controller (DMAC)
DMA Software Start Register (DMREQ)
Address(es): DMAC0.DMREQ 4000 501Dh, DMAC1.DMREQ 4000 505Dh, DMAC2.DMREQ 4000 509Dh, DMAC3.DMREQ 4000 50DDh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
CLRS
—
—
—
SWRE
Q
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SWREQ
DMA Software Start
0: DMA transfer is not requested
1: DMA transfer is requested.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
CLRS
DMA Software Start Bit Auto
Clear Select
0: SWREQ bit is cleared after DMA transfer is started by software
1: SWREQ bit is not cleared after DMA transfer is started by software.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
SWREQ bit (DMA Software Start)
Writing 1 to the SWREQ bit generates a DMA transfer request. After the DMA transfer starts, SWREQ sets to 0 if the
CLRS bit is set to 0. SWREQ does not set to 0 if the CLRS bit is 1. The DMA transfer request can be issued again after
the transfer is complete.
Note:
Setting this bit is valid and DMA transfer by software is enabled only when the DCTG[1:0] bits in DMTMD are set
to 00b, specifying software as the DMA activation source. Setting this bit is invalid when the DCTG[1:0] bits in
DMTMD are set to any value other than 00b.
To start DMA transfer through software with the CLRS bit set to 0, ensure that the SWREQ bit is 0, and then write 1 to
the SWREQ bit.
[Setting condition]
When 1 is written to this bit.
[Clearing conditions]
When a DMA transfer request through software is accepted and DMA transfer is started with the CLRS bit set to 0
(the SWREQ bit is cleared after DMA transfer is started through software)
When 0 is written to this bit.
CLRS bit (DMA Software Start Bit Auto Clear Select)
When an SWREQ setting of 1 triggers a transfer request, the CLRS bit specifies whether to clear the SWREQ bit to 0
after the DMA transfer starts. When the CLRS bit is set to 0, SWREQ sets to 0 after the DMA transfer starts. When the
CLRS bit is set to 1, SWREQ does not set to 0. The DMA transfer request can be issued again after the transfer is
complete.
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17.2.11
17. DMA Controller (DMAC)
DMA Status Register (DMSTS)
Address(es): DMAC0.DMSTS 4000 501Eh, DMAC1.DMSTS 4000 505Eh, DMAC2.DMSTS 4000 509Eh, DMAC3.DMSTS 4000 50DEh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
ACT
—
—
DTIF
—
—
—
ESIF
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ESIF
Transfer Escape End Interrupt
Flag
0: No interrupt occurred
1: Interrupt occurred.
R/W*1
b3 to b1
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R/W
b4
DTIF
Transfer End Interrupt Flag
0: No interrupt occurred
1: Interrupt occurred.
R/W*1
b6, b5
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R/W
b7
ACT
DMA Active Flag
0: DMAC operation suspended
1: DMAC operating.
R
Note 1.
Only 0 can be written to clear the flag.
ESIF flag (Transfer Escape End Interrupt Flag)
The ESIF flag indicates that a transfer escape end interrupt occurred.
[Setting conditions]
In repeat transfer mode, when one repeat size data transfer completes with the RPTIE bit in DMINT set to 1
In block transfer mode, when one block data transfer completes with the RPTIE bit in DMINT set to 1
When an extended repeat area overflow on the source address occurs with the SARIE bit in DMINT set to 1, and the
SARA[4:0] bits in DMAMD set to any value other than 00000b (extended repeat area is specified on the transfer
source address)
When an extended repeat area overflow on the destination address occurs with the DARIE bit in DMINT set to 1
and the DARA[4:0] bits in DMAMD set to any value other than 00000b (extended repeat area is specified on the
transfer destination address).
[Clearing conditions]
When 0 is written to this flag
When 1 is written to the DTE bit in DMCNT.
DTIF flag (Transfer End Interrupt Flag)
The DTIF flag indicates that a transfer end interrupt occurred.
[Setting conditions]
In normal transfer mode, when the specified number of unit transfers completes (DMCRAL value becomes 0 on
completion of transfer)
In repeat transfer mode, when the specified number of repeat transfer operations completes (DMCRB value
becomes 0 on completion of transfer)
In block transfer mode, when the specified number of blocks is transferred (DMCRB value becomes 0 on
completion of transfer).
[Clearing conditions]
When 0 is written to this flag
When 1 is written to the DTE bit in DMCNT.
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17. DMA Controller (DMAC)
ACT flag (DMA Active Flag)
The ACT flag indicates whether the DMAC is in the idle or active state.
[Setting condition]
When the DMAC starts a data transfer.
[Clearing condition]
When the data transfer in response to one transfer request completes.
17.2.12
DMAC Module Activation Register (DMAST)
Address(es): DMA.DMAST 4000 5200h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DMST
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DMST
DMAC Operation Enable
0: Disable
1: Enable.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
DMST bit (DMAC Operation Enable)
Setting the DMST bit to 1 enables DMAC activation for all channels. When the DMST bit is set to 1 (DMAC activation
is enabled), and 1 is written to the DMACm.DMCNT.DTE bit (DMA transfer is enabled) for multiple channels, all of the
associated channels can be placed in the transfer request ready state at the same time.
When the DMST bit sets to 0 during DMA transfer, the DMA transfer is suspended after the current data transfer
associated with a single transfer request is complete. To resume the DMA transfer, set the DMST bit to 1 again.
[Setting condition]
When 1 is written to this bit.
[Clearing condition]
When 0 is written to this bit.
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17.3
Operation
17.3.1
(1)
17. DMA Controller (DMAC)
Transfer Mode
Normal transfer mode
In normal transfer mode, one data unit is transferred for one transfer request. You can specify the number of transfer
operations, up to a maximum of 65535, in DMACm.DMCRAL. When these bits are set to 0000h, no number of
operations is specified and data transfer is performed with the transfer counter stopped (free running mode). A transfer
end interrupt request can be generated after completion of the specified number of transfer operations, except when in
free running mode. Setting DMACm.DMCRB is invalid in normal transfer mode.
Table 17.3 summarizes the register update operation in normal transfer mode.
Table 17.3
Register update operation in normal transfer mode
Register
Function
Update operation after completion of a transfer for one transfer request
DMACm.DMSAR
Transfer source address
Increment, decrement, fixed, or offset addition
DMACm.DMDAR
Transfer destination address
Increment, decrement, fixed, or offset addition
DMACm.DMCRAL
Transfer count
Decremented by 1 or not updated (in free running mode)
DMACm.DMCRAH
-
Not updated (not used in normal transfer mode)
DMACm.DMCRB
-
Not updated (not used in normal transfer mode)
Figure 17.2 shows the operation in normal transfer mode.
Transfer source data area
Transfer destination data area
Data 1
Data 1
DMSAR
Data 2
Figure 17.2
(2)
Transfer
DMDAR
Data 2
Data 3
Data 3
Data 4
Data 4
Data 5
Data 5
Data 6
Data 6
Operation in normal transfer mode
Repeat transfer mode
In repeat transfer mode, one data unit is transferred for one transfer request.
The repeat transfer size, up to a maximum of 1K data units, is set in DMACm.DMCRA. The number of repeat transfers,
up to a maximum number of 64K, is set in DMACm.DMCRB. The total data transfer size can be set to a maximum of
64M data units (1K data units × 64K repeat transfers).
You can specify either the transfer source or destination as a repeat area. When transfer of the repeat size data is
complete, the address of the specified repeat area (DMSAR or DMDAR in DMACm) returns to the transfer start address.
In this mode, when all data of the specified repeat size is transferred, the DMA transfer can be stopped and a repeat size
end interrupt can be requested. To resume DMA transfer, write 1 to the DTE bit in DMACm.DMCNT during repeat size
end interrupt handling.
A transfer end interrupt request can be generated after completion of the specified number of repeat transfers.
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17. DMA Controller (DMAC)
Table 17.4 summarizes the register update operation in repeat transfer mode, and Figure 17.3 shows the operation in
repeat transfer mode.
Table 17.4
Register update operation in repeat transfer mode
Update operation after completion of a transfer for one transfer request
When DMACm.DMCRAL is 1
(transfer of the last repeat size data unit)
Register
Function
When DMACm.DMCRAL is not 1
DMACm.DMSAR
Transfer source
address
Increment/decrement/fixed/offset
addition
DMACm.DMTMD.DTS[1:0] = 00b
Increment, decrement, fixed, or offset addition
DMACm.DMTMD.DTS[1:0] = 01b
Initial value of DMACm.DMSAR
DMACm.DMTMD.DTS[1:0] = 10b
Increment, decrement, fixed, or offset
addition.
DMACm.DMDAR
Transfer
destination
address
Increment/decrement/fixed/offset
addition
DMACm.DMTMD.DTS[1:0] = 00b
Initial value of DMACm.DMDAR
DMACm.DMTMD.DTS[1:0] = 01b
Increment, decrement, fixed, offset addition
DMACm.DMTMD.DTS[1:0] = 10b
Increment, decrement, fixed, or offset
addition.
DMACm.DMCRAH
Repeat size
Not updated
Not updated
DMACm.DMCRAL
Transfer count
Decremented by 1
DMACm.DMCRAH
DMACm.DMCRB
Count of repeat
transfer operations
Not updated
Decremented by 1
Transfer source data area
(specified as a repeat area)
Transfer destination data area
Data 1
Data 1
DMSAR
Data 2
Transfer
DMDAR
Data 2
Data 3
Data 3
Data 4
Data 4
Data 1
Data 2
Data 3
Data 4
Figure 17.3
Operation in repeat transfer mode
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(3)
17. DMA Controller (DMAC)
Block transfer mode
In block transfer mode, a single data block is transferred for one transfer request. The block transfer size, up to a
maximum of 1K data units, is set in DMACm.DMCRA. The number of block transfers, up to a maximum of 64K, is set
in DMACm.DMCRB. A total data transfer size up to a maximum of 64M data units (1K data units × 64K block
transfers) can be set.
You can specify either the transfer source or destination as a block area. When transfer of a single data block is complete,
the address of the specified block area (DMSAR or DMDAR in DMACm) returns to the transfer start address. In this
mode, when all data in a single block is transferred, you can stop DMA transfer and request a repeat size end interrupt.
To resume DMA transfer, write 1 to the DTE bit in DMACm.DMCNT during repeat size end interrupt handling.
A transfer end interrupt request can be generated after completion of the specified number of block transfers. Table 17.5
summarizes the register update operation in block transfer mode, and Figure 17.4 shows the operation in block transfer
mode.
Table 17.5
Register update operation in block transfer mode
Update operation after completion of single-block transfer for
one transfer request
Register
Function
DMACm.DMSAR
Transfer source address
DMACm.DMTMD.DTS[1:0] = 00b
Increment, decrement, fixed, or offset addition
DMACm.DMTMD.DTS[1:0] = 01b
Initial value of DMACm.DMSAR
DMACm.DMTMD.DTS[1:0] = 10b
Increment, decrement, fixed, or offset addition.
DMACm.DMDAR
Transfer destination address
DMACm.DMTMD.DTS[1:0] = 00b
Initial value of DMACm.DMDAR
DMACm.DMTMD.DTS[1:0] = 01b
Increment, decrement, fixed, or offset addition
DMACm.DMTMD.DTS[1:0] = 10b
Increment, decrement, fixed, or offset addition.
DMACm.DMCRAH
Block size
Not updated
DMACm.DMCRAL
Transfer count
DMACm.DMCRAH
DMACm.DMCRB
Count of block transfer operations
Decremented by 1
Transfer source data area
DMSAR
First block
Transfer destination data area
(specified as a block area)
Transfer
Block area
DMDAR
Nth block
Figure 17.4
Operation in block transfer mode
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17.3.2
17. DMA Controller (DMAC)
Extended Repeat Area Function
The DMAC supports extended repeat areas on the transfer source and destination addresses, specified separately in the
DMA Source Address Register (DMSAR) and DMA Destination Address Register (DMDAR) of DMACm. When this
function is set, the address registers repeatedly indicate the addresses of the specified extended repeat areas. The
extended repeat area on the source address is specified in the SARA[4:0] bits in DMACm.DMAMD.
The extended repeat area on the destination address is specified in the DARA[4:0] bits in DMACm.DMAMD. You can
specify different sizes for the source and destination. However, you must not specify a transfer source or destination that
is set as the repeat or block area as the extended repeat area.
When the address register value reaches the end address of the extended repeat area and the extended repeat area
overflows, DMA transfer is stopped and an extended repeat area overflow interrupt can be requested. When an overflow
occurs in the extended repeat area on the transfer source while the SARIE bit in DMACm.DMINT is set to 1, the ESIF
flag in DMACm.DMSTS is set to 1 and the DTE bit in DMACm.DMCNT sets to 0 to stop DMA transfer. At this point,
if the ESIE bit in DMACm.DMINT is set to 1, an interrupt by an extended repeat area overflow is requested. When the
DARIE bit in DMINT of DMACm is set to 1, the destination address register becomes a target for the function. To
resume DMA transfer, write 1 to the DTE bit in DMACm.DMCNT during interrupt handling.
Figure 17.5 shows an example of the extended repeat area operation.
Example:
8 bytes are specified as an extended repeat area by the lower 3 bits of DMACm.DMSAR (SARA[4:0] bits in
DMACm.DMAMD = 00011b). The data size is 8 bits (SZ[1:0] bits in DMACm.DMTMD = 00b).
Memory area
00013FFEh
DMSAR value
range
00013FFFh
00014000h
00014000h
00014001h
00014001h
00014002h
00014002h
00014003h
00014003h
00014004h
00014004h
00014005h
00014005h
00014006h
00014006h
00014007h
00014007h
00014008h
Repeat
An extended repeat area overflow interrupt
request can be generated
00014009h
Figure 17.5
Example of extended repeat area operation
When using extended repeat area overflow interrupts in block transfer mode, consider the following points:
When a transfer is stopped by an extended repeat area overflow interrupt, the address register must be set so that the
block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an
overflow on the extended repeat area occurs during a transfer of one block, the overflow interrupt is suspended until
transfer of the block is complete, and the transfer overruns.
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17. DMA Controller (DMAC)
Figure 17.6 shows an example of using the extended repeat area function in block transfer mode.
Example:
8 bytes are specified as an extended repeat area by the lower 3 bits of DMACm.DMSAR (SARA[4:0] bits in DMACm.DMAMD = 00011b),
block transfer mode with block size 5 is set (DMACm.DMCRA = 00050005h), and the transfer source address is not specified as a block area.
Data size is 8 bits (SZ[1:0] bits in DMACm.DMTMD = 00b).
Memory area
Repeated
DMSAR value
range
First block transfer
Second block
transfer
00014000h
00014000h
00014000h
00014000h
00014001h
00014001h
00014001h
00014001h
00014002h
00014002h
00014002h
00014003h
00014003h
00014003h
00014004h
00014004h
00014004h
00014005h
00014005h
00014005h
00014006h
00014006h
00014006h
00014007h
00014007h
00014007h
00013FFEh
00013FFFh
Interrupt request
generated
00014008h
Block transfer
continued
00014009h
Figure 17.6
17.3.3
Example of extended repeat area function in block transfer mode
Address Update Function Using Offset
The source and destination addresses can be updated by fixing, incrementing, decrementing, or adding an offset. When
offset addition is selected, the offset specified in the DMA Offset Register (DMACm.DMOFR) is added to the address
every time the DMAC performs one data transfer. This function performs a data transfer when addresses are allocated to
separated areas. You can also subtract an offset by setting a negative value in DMACm.DMOFR. The negative value
must be in two’s complement.
Table 17.6 shows the address update method in each address update mode.
Table 17.6
Address update method in each address update mode
Address update method for different SZ[1:0] settings in
DMACm.DMTMD
Address update
mode
Settings of
DMACm.DMAMD.SM[1:0] and
DMACm.DMAMD.DM[1:0] for
address update modes
Address fixed
00b
Fixed
Offset addition
01b
+DMACm.DMOFR*1
SZ[1:0] = 00b
SZ[1:0] = 01b
SZ[1:0] = 10b
Increment
10b
+1
+2
+4
Decrement
11b
-1
-2
-4
Note 1.
When setting a negative value in the DMA Offset Register, the value must be in two’s complement, obtained by the following
formula:
Two’s complement of a negative offset value = ~ (offset) + 1 (~: bit inversion)
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(1)
17. DMA Controller (DMAC)
Basic transfer using offset addition
Figure 17.7 shows an example of address updating using offset addition.
Transfer
Data 1
Address A1
Offset value
Data 2
Address A2
= address A1 + offset value
Data 3
Address A3
= address A2 + offset value
Data 4
Address A4
= address A3 + offset value
Data 1
Address B1
Data 2
Address B2 = address B1 + 4
Data 3
Address B3 = address B2 + 4
Data 4
Address B4 = address B3 + 4
Data 5
Address B5 = address B4 + 4
Offset value
Offset value
Offset value
Transfer source: Offset addition
Transfer destination: Increment
Data 5
Figure 17.7
Address A5
= address A4 + offset value
Data size: 32 bits
Example of address updating through offset addition
In Figure 17.7:
The transfer data is 32 bits long
Offset addition is set as the transfer source address update mode
Increment is set as the transfer destination address update mode.
The second and subsequent data units are each read from the source address obtained by adding the offset value to the
previous address. The data read from the addresses at the specified intervals is written to continuous locations on the
destination.
(2)
Example of XY conversion using offset addition
Figure 17.8 shows the XY conversion using offset addition in repeat transfer mode. The settings are as follows:
DMAC0.DMAMD — Transfer source address update mode: offset addition
DMAC0.DMAMD — Transfer destination address update mode: destination address is incremented
DMAC0.DMTMD — Transfer data size select: 32 bits
DMAC0.DMTMD — Transfer mode select: repeat transfer
DMAC0.DMTMD — Repeat area select: the source is specified as the repeat area
DMAC0.DMOFR — Offset address: 10h
DMAC0.DMCRA — Repeat size: 4h
DMAC0.DMINT — The repeat size end interrupt is enabled.
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17. DMA Controller (DMAC)
Data 5
Data 9
Data 13
Data 1
Data 2
Data 3
Data 2
Data 6
Data 10
Data 14
Second cycle
Data 5
Data 6
Data 7
Data 8
Data 3
Data 7
Data 11
Data 15
Third cycle
Data 9
Data 10
Data 11
Data 12
Data 4
Data 8
Data 12
Data 16
Fourth cycle
Data 13
Data 14
Data 15
Data 16
Offset value
Offset value
Offset value
First cycle
Second cycle
Data 1
Data 5
Address
returned
Transfer
Transfer source
address written
by CPU
Data 4
Third cycle
Transfer
Data 1
Data 1
Data 5
Data 5
Data 2
Data 9
Data 3
Address
returned
Data 1
Data 9
Data 9
Data 13
Data 13
Data 13
Data 2
Data 2
Data 2
Data 6
Data 6
Data 6
Data 6
Data 10
Data 10
Data 10
Data 7
Data 14
Data 14
Data 14
Data 8
Data 3
Data 3
Data 3
Data 9
Transfer source
address written by
CPU
Data 5
Data 7
Data 7
Data 7
Data 10
Data 11
Data 11
Data 11
Data 15
Data 15
Data 15
Data 12
Data 4
Data 4
Data 4
Data 13
Data 8
Data 8
Data 14
Data 12
Data 15
Data 12
Interrupt
request
generated
Data 16
Data 12
Data 16
Interrupt
request
generated
Data 16
Interrupt
request
generated
First
cycle
Data 4
Data 11
Data 8
Figure 17.8
First
cycle
Data 1
Second
cycle
Third
cycle
Fourth
cycle
Data 16
XY conversion operation using offset addition in repeat transfer mode
When a transfer starts, the offset value is added to the transfer source address every time data is transferred. The transfer
data is written to continuous destination addresses. When data 4 is transferred:
The repeat size of the transfers is complete
The transfer source address returns to the transfer start address (the address of data 1 on the transfer source)
A repeat size end interrupt is requested.
During the time this interrupt pauses the transfer, perform the following:
DMAC0.DMSAR — Rewrite the DMA transfer source address to the address of data 5
(in this example, the data 1 address + 4)
DMAC0.DMCNT — Set the DTE bit to 1.
The DMA transfer resumes from the state when the DMA transfer was stopped. The same operations are repeated until
the transfer source data is transposed to the destination area (XY conversion).
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17. DMA Controller (DMAC)
Figure 17.9 shows a flow of the XY conversion.
Start
Set the address, repeat size, and number of repeat
operations
Set repeat transfer mode
Enable repeat size end interrupts
Write 1 to the DTE bit in DMAC0.DMCNT
Receive transfer request
Transfer data
Decrement repeat size and number of repeat operations
No
Number of repeat operations = 0?
Yes
Repeat size = 0?
No
Yes
Return to the transfer source address
Generate a repeat size end interrupt
Set “transfer source address + 4”
(When transfer data size = 32 bits)
End
: User side processing
: DMAC side processing
Figure 17.9
XY conversion flow using offset addition in repeat transfer mode
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17.3.4
17. DMA Controller (DMAC)
Activation Sources
Software, the interrupt requests from the peripheral modules, and external interrupt requests can all be specified as
DMAC activation sources. Set the DCTG[1:0] bits in DMACm.DMTMD to select the activation source.
(1)
DMAC activation through software
To start DMA transfer through software:
1. Set the DCTG[1:0] bits in DMACm.DMTMD to 00b.
2. Set the DTE bit in DMACm.DMCNT to 1 (enable DMA transfer).
3. Set the DMST bit in DMAST to 1 (enable DMAC activation).
4. Set the SWREQ bit in DMACm.DMREQ to 1 (request DMA).
When the DMAC is activated by software while the CLRS bit in DMACm.DMREQ is 0, the SWREQ bit in
DMACm.DMREQ sets to 0 after data transfer starts in response to a DMA transfer request.
When the DMAC is activated by software while the CLRS bit is 1, SWREQ does not set to 0 after data transfer starts. A
DMA transfer request is issued again after completion of a transfer.
(2)
DMAC activation through interrupt requests from on-chip peripheral modules or external
interrupt requests
You can specify interrupt requests from on-chip peripheral modules and external interrupt requests as DMAC activation
sources. The activation source can be individually selected for each channel in ICU.DELSRn.DELS[7:0] (n = 0 to 3).
To start DMAC transfer through an interrupt request from an on-chip peripheral module or an external interrupt request:
1. Set the DCTG[1:0] bits in DMACm.DMTMD to 01b (select interrupts from the peripheral modules and the external
interrupt pins).
2. Set the DTE bit in DMACm.DMCNT to 1 (enable DMA transfer).
3. Set ICU.DELSRn.DSEL to the event number (select the DMAC event link).
4. Set the DMST bit in DMAST to 1 (enable DMAC activation).
For interrupt requests specified as DMAC activation sources, see Table 14.3, Interrupt vector table in section 14,
Interrupt Controller Unit (ICU).
17.3.5
Operation Timing
The following timing diagrams show the minimum number of execution cycles.
System clock
Peripheral function
interrupts or
external pin interrupts
DMAC activation
request
DMAC access
R
W
Data transfer
Figure 17.10
R
W
Data transfer
DMAC operation timing example 1 with DMA activation by interrupt from peripheral module or
external interrupt input pin, in normal transfer mode or repeat transfer mode
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17. DMA Controller (DMAC)
System clock
Peripheral function
interrupts or
External pin interrupts
DMAC activation
request
DMAC access
Data transfer
Figure 17.11
17.3.6
DMAC operation timing example 2 with DMA activation by interrupt from peripheral module or
external interrupt input pin, in block transfer mode with block size = 4
Execution Cycles of DMAC
Table 17.7 lists the execution cycles in one DMAC data transfer operation.
Table 17.7
DMAC execution cycles
Transfer mode
Data transfer (read)
Data transfer (write)
Normal
Cr+1
Cw
Repeat
Cr+1
Cw
Block*1
P × Cr
P × Cw
Note:
Note 1.
P = Block size (DMCRAH register setting).
Cr = Read destination access cycle.
Cw = Data write destination access cycle.
This is the case when the block size is 2 or more. When the block size is 1, normal transfer cycle applies.
Cr and Cw depend on the access destination. For the number of cycles for each access destination, see section 46,
SRAM, section 47, Flash Memory, and section 15, Buses. The frequency ratio of the system clock and the peripheral
clock is also taken into consideration.
The unit for +1 in the data transfer (read) column is 1 system clock cycle, ICLK. For the operation example, see section
17.3.5, Operation Timing.
The DMAC response time is the time from when the DMAC activation source is detected until the DMAC transfer starts.
Table 17.7 does not include the time until the DMAC data transfer starts after the DMAC activation source becomes
active.
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17.3.7
17. DMA Controller (DMAC)
Activating DMAC
Figure 17.12 shows the register setting procedure.
Initial settings
D isable the peripheral function as the D M AC m
request source
To use peripheral function
interrupts as D M A activation
sources
To use external pin interrupts as
D M A activation sources
D isable the IR Q pin as the D M AC m request
source
Set the D M AC m Event Link Select
(IC U .D ELSR n.D ELS[7:0]) to 000h
C lear the D TE bit in D M AC m .D M C N T to 0
To use on-chip peripheral
interrupts or external pin
interrupts as D M A activation
sources
To use peripheral function
interrupts as D M A activation
sources
To use external pin interrupts as
D M A activation sources
Disable the control register for the peripheral function
The interrupt should be enabled in the N VIC .
Set the interrupt request as a D M A Cm request
source in the D M ACm Event Link Setting R egister
(IC U.D ELSR n) using the IC U .
Set the peripheral m odule as a DM AC m request
source
Set the IR Q pin function using the ICU
Disable the D M AC m request
D isable D M AC m transfers
Enable the interrupt bit for the activation source
Set the D M AC m activation source
Set the control register for the peripheral function w ithout
starting it
Set the IR Q pin function w ithout enabling it
D M [1:0] bits in D M AC m.D M AM D
SM [1:0] bits in D M AC m.D M AM D
D AR A[4:0] bits in DM AC m .D M AM D
SAR A[4:0] bits in D M AC m.D M A M D
Transfer destination address update m ode bits
Transfer source address update m ode bits
D estination address extended repeat area bits
Source address extended repeat area bits
D CTG[1:0] bits in D M ACm .D M TM D
SZ[1:0] bits in D M AC m .D M TM D
D TS[1:0] bits in D M AC m.D M TM D
M D [1:0] bits in D M AC m.D M TM D
Transfer request select bits
D ata transfer size bits
R epeat area select bits
Transfer m ode select bits
D M AC m.D M SAR
Set the transfer source start address
D M AC m.D M D AR
Set the transfer destination start address
D M AC m.D M C R A
Set the num ber of transfer operations
To use block transfer m ode or repeat transfer m ode
Set the num ber of block transfer operations
D M AC m.D M C R B
To use the address update function w ith offset
Set the offset value
D M AC m.D M OFR
To use D M A transfer end interrupts
Set 1 to DTIE bit in D M AC m .DM INT
Enable D M AC m transfer end interrupts
To use D M A transfer escape interrupts
To use peripheral function
interrupts as DM A activation
sources
To use external pin interrupts as
DM A activation sources
R PTIE bit in D M AC m.D M IN T
SAR IE bit in D M AC m.D M IN T
D AR IE bit in D M AC m.D M IN T
Set the ESIE bit in D M ACm.D M IN T to 1
Set the repeat size end interrupt
Set the transfer source address extended repeat area overflow interrupt
Set the transfer destination address extended repeat area overflow interrupt
Enable the DM A transfer escape end interrupt
Set D TE bit in D M AC m .D M C N T to 1
Enable D M AC m transfer
Set D M ST bit in D M AST to 1
Enable D M AC operation* 1
Enable the peripheral function as a D M AC m request
source
Enable the IR Q pin as a D M AC m request source
m : D M A C channel (m = 0 to 3)
Note 1.
C om m on settings for D M AC
End
For activation by softw are
On com pletion of the initial settings, w riting 1 to the D M A Softw are
Start bit (D M AC m .D M R EQ.SW R EQ ) starts D M A transfer
The DMAST.DMST bit setting does not necessarily have to follow the settings for the individual activation sources.
Figure 17.12
Register setting procedure
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17.3.8
17. DMA Controller (DMAC)
Starting DMA Transfer
To enable a DMA transfer of channel m, set the DTE bit in DMACm.DMCNT to 1 (DMA transfer enabled) and set the
DMST bit in DMAST to 1 (DMAC start enabled). New activation requests are not accepted during the transfer of
another DMAC channel or DTC. When the proceeding transfer is complete, channel arbitration selects the DMA transfer
request of the highest priority channel, and DMA transfer of that channel starts. When DMA transfer starts, the ACT flag
in DMACm.DMSTS sets to 1 (the DMAC is in the active state).
17.3.9
Registers during DMA Transfer
The DMAC registers are updated by a DMA transfer. The value to be updated changes according to the other settings and
the transfer state. The registers to be updated are DMSAR, DMDAR, DMCRA, DMCRB, DMCNT, and
DMACm.DMSTS, described in the following sections. For details on register update operation in each transfer mode,
see Table 17.3 to Table 17.5.
(1)
DMA Source Address Register (DMACm.DMSAR)
After the data for one transfer request is transferred, the contents of DMSAR are updated to the address to be accessed by
the next transfer request.
(2)
DMA Destination Address Register (DMACm.DMDAR)
After the data for one transfer request is transferred, the contents of DMDAR are updated to the address to be accessed
by the next transfer request.
(3)
DMA Transfer Count Register (DMACm.DMCRA)
After the data for one transfer request is transferred, the count value is updated. The update operation depends on the
transfer mode selected.
(4)
DMA Block Transfer Count Register (DMACm.DMCRB)
After the data for one transfer request is transferred, the count value is updated. The update operation depends on the
transfer mode selected.
(5)
DMA Transfer Enable bit (DMACm.DMCNT.DTE)
The DMACm.DMCNT.DTE bit enables or disables data transfer through register write access. It is automatically set to 0
by the DMAC based on the DMA transfer state.
The conditions for clearing this bit by the DMAC are as follows:
When the specified total volume of data transfer is complete
When DMA transfer is stopped by a repeat size end interrupt
When DMA transfer is stopped by an extended repeat area overflow interrupt.
Writing to the registers for channels whose associated DMACm.DMCNT.DTE bit is set to 1 is prohibited except for
DMACm.DMCNT. Writes are only possible after the bit sets to 0.
(6)
DMA Active Flag (DMACm.DMSTS.ACT)
The ACT flag in DMSTS of DMACm indicates whether the DMACm is in the idle or active state. This flag sets to 1
when the DMAC starts data transfer, and sets to 0 when data transfer for one transfer request is complete. Even when
DMA transfer is stopped by write of 0 to the DTE bit in DMACm.DMCNT, this flag remains 1 until DMA transfer is
complete.
(7)
Transfer End Interrupt Flag (DMACm.DMSTS.DTIF)
The DTIF flag in DMACm.DMSTS sets to 1 after DMA transfer of the total transfer size is complete. When both this
flag and the DTIE bit in DMACm.DMINT are 1, a transfer end interrupt is requested. This flag sets to 1 when the DMA
transfer bus cycle is complete and the ACT flag in DMACm.DMSTS sets to 0, indicating the DMA transfer end. The flag
automatically sets to 0 when the DTE bit in DMACm.DMCNT is set to 1 during interrupt handling.
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(8)
17. DMA Controller (DMAC)
Transfer Escape End Interrupt Flag (DMACm.DMSTS.ESIF)
The ESIF flag in DMACm.DMSTS sets to 1 when a repeat size end interrupt or extended repeat area overflow interrupt
is requested. When this bit and the ESIE bit in DMACm.DMINT are 1, a transfer escape end interrupt is requested. This
flag sets to 1 when the bus cycle of the DMA transfer that caused the interrupt request is complete and the ACT flag in
DMACm.DMSTS sets to 0, indicating the DMA transfer end. The flag automatically sets to 0 when the DTE bit in
DMACm.DMCNT is set to 1 during interrupt handling.
You must set the interrupt control register before sending an interrupt request from the DMAC to the CPU or the DTC.
For more information, see section 14, Interrupt Controller Unit (ICU).
17.3.10
Channel Priority
When multiple DMA transfer requests occur, the DMAC determines the priority of channels that have DMA transfer
requests.
The priority is fixed as channel 0 > channel 1 > channel 2 > channel 3 (channel 0 is the highest).
When a DMA transfer request occurs during data transfer, channel arbitration starts after the final data unit is transferred,
and DMA transfer of the highest-priority channel starts.
17.4
Ending DMA Transfer
The operation for ending a DMA transfer depends on the transfer end conditions. When a DMA transfer ends, the DTE
bit in DMCNT and the ACT flag in DMACm.DMSTS change from 1 to 0.
17.4.1
(1)
Transfer End by Completion of Specified Total Number of Transfer Operations
In normal transfer mode (DMACm.DMTMD.MD[1:0] = 00b)
When the DMACm.DMCRAL value changes from 1 to 0, DMA transfer ends on the associated channel, the DTE bit in
DMACm.DMCNT sets to 0, and the DTIF flag in DMACm.DMSTS sets to 1. If the DTIE bit in DMACm.DMINT is 1
at this time, a transfer end interrupt request is sent to the CPU or the DTC.
(2)
In repeat transfer mode (DMACm.DMTMD.MD[1:0] = 01b)
When DMACm.DMCRB changes from 1 to 0, DMA transfer ends on the associated channel, the DTE bit in
DMACm.DMCNT sets to 0, and the DTIF flag in DMACm.DMSTS sets to 1. If the DTIE bit in DMACm.DMINT is 1
at this time, an interrupt request is sent to the CPU or the DTC.
(3)
In block transfer mode (DMACm.DMTMD.MD[1:0] = 10b)
When DMACm.DMCRB changes from 1 to 0, DMA transfer ends on the associated channel, the DTE bit in
DMACm.DMCNT sets to 0, and the DTIF flag in DMACm.DMSTS sets to 1. If the DTIE bit in DMACm.DMINT is 1
at this time, an interrupt request is sent to the CPU or the DTC.
You must set the interrupt control register before sending an interrupt request from the DMAC to the CPU or the DTC.
For more information, see section 14, Interrupt Controller Unit (ICU).
17.4.2
Transfer End by Repeat Size End Interrupt
In repeat transfer mode, if the RPTIE bit in DMACm.DMINT is 1, a repeat size end interrupt is requested when transfer
of a single repeat size of data is complete. The DTE bit in DMACm.DMCNT sets to 0 and the ESIF flag in
DMACm.DMSTS sets to 1. If the ESIE bit in DMACm.DMINT is 1 at this time, an interrupt request is sent to the CPU
or the DTC. To resume the transfer, write 1 to the DTE bit in DMACm.DMCNT.
A repeat size end interrupt can also be requested in block transfer mode. When transfer of a single block size of data is
complete, the interrupt is requested in the same way as in repeat transfer mode.
You must set the interrupt control register before sending an interrupt request from the DMAC to the CPU or the DTC.
For more information, see section 14, Interrupt Controller Unit (ICU).
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17.4.3
17. DMA Controller (DMAC)
Transfer End by Interrupt on Extended Repeat Area Overflow
When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or
DARIE bit in DMACm.DMINT is 1, an extended repeat area overflow interrupt is requested. The DMA transfer is
terminated, the DTE bit in DMACm.DMCNT sets to 0, and the ESIF flag in DMACm.DMSTS sets to 1. If the ESIE bit
in DMACm.DMINT is 1 at this time, an interrupt request is sent to the CPU or the DTC.
If this interrupt is requested during a read cycle, the subsequent write cycle is performed. In block transfer mode, if the
interrupt is requested during a 1-block transfer, the remaining data in the block is transferred before transfer stops.
Before sending an interrupt request from the DMAC to the CPU or the DTC, the interrupt control register must be set.
For more information, see section 14, Interrupt Controller Unit (ICU).
17.4.4
Precautions for the End of DMA Transfer
A DMA activation request source might occur in the next request after a DMA transfer completes. If this happens, the
DMA transfer starts and the DMA activation request is held in DMAC. To prevent this, stop the DMA activation requests
by setting the DELSRn.DELS[7:0] bits in the ICU to 0.
When a DMA activation request occurs after the last round of the DMA transfer is generated, clear the DMA activation
request by setting the ICU.DELSRm.IR bit to 0.
17.5
Interrupts
Each DMAC channel can output an interrupt request (DMACm_INT) to the CPU or DTC after transfer for one request is
complete. When the transfer destination is the external bus, an interrupt request is generated after completion of a data
write to the write buffer, and not to the actual transfer destination.
Table 17.8 lists the interrupt sources and their associated status flags and enable bits. Figure 17.13 shows the schematic
logic diagram of the interrupt outputs (DMAC0 to DMAC3). Figure 17.14 shows the DMAC interrupt handling routine
for resuming and terminating DMA transfers.
Table 17.8
Association between interrupt sources, interrupt status flags, and interrupt enable bits
Interrupt sources
Interrupt enable bits
Interrupt status flags
Request output enable bits
Transfer end
-
DMACm.DMSTS.DTIF
DMACm.DMINT.DTIE
Repeat size end
DMACm.DMINT.RPTIE
DMACm.DMSTS.ESIF
DMACm.DMINT.ESIE
Source address extended repeat
area overflow
DMACm.DMINT.SARIE
Destination address extended
repeat area overflow
DMACm.DMINT.DARIE
Escape
transfer end
DTIE
DTIF
When the specified number of data
transfer operations are complete
1-setting condition
DMACm interrupt request
RPTIE
ESIE
When the specified repeat (or block)
size of data transfer is complete
ESIF
SARIE
1-setting condition
When a source address extended
repeat area overflow occurs
DARIE
When a destination address extended
repeat area overflow occurs
Figure 17.13
Interrupt output logic diagram for DMAC channel m (DMACm)
m = 0 to 3
Schematic logic diagram of interrupt outputs for DMAC0 to DMAC3
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17. DMA Controller (DMAC)
Different procedures are used for canceling an interrupt to restart a DMA transfer in the following cases:
When terminating a DMA transfer
When continuing a DMA transfer.
(1)
When terminating a DMA transfer
Write 0 to the DTIF flag in DMACm.DMSTS to clear a transfer end interrupt, and to the ESIF flag in DMACm.DMSTS
to clear a repeat size interrupt or an extended repeat area overflow interrupt. DMACm remains in the stopped state. When
starting another DMA transfer, set the appropriate registers and set the DTE bit in DMACm.DMCNT to 1 (DMA transfer
enabled).
(2)
When continuing a DMA transfer
Write 1 to the DTE bit in DMACm.DMCNT. The ESIF flag in DMSTS of DMACm automatically sets to 0 (interrupt
source cleared), and the DMA transfer resumes.
Interrupt request from DMAC
Start of DMAC interrupt handling
Continue
Terminate
Continue suspended transfer?
Change register settings if necessary
Write 1 to DTE bit in DMACm.DMCNT
Write 0 to ESIF or DTIF flag in DMACm.DMSTS
(interrupt source cleared)
Discontinue
Perform another data transfer?
End
Start another transfer
ESIF flag in DMACm.DMSTS cleared automatically
(interrupt source cleared)
Change register settings
Transfer resumed
Write 1 to DTE bit in DMACm.DMCNT
DMA transfer restarted
(start of another DMA transfer)
Figure 17.14
17.6
DMAC interrupt handling routine to resume or terminate a DMA transfer
Event Link
Each DMAC channel outputs an event link request signal (DMACm_INT) every time it completes a data transfer, or a
block transfer in block transfer mode. When the transfer destination is the external bus, the signal is generated when
writing to the write buffer is accepted. For more information, see section 19, Event Link Controller (ELC).
17.7
Low Power Consumption Function
Before entering the module-stop state or Software Standby mode, you must first clear the DMST bit in DMAST to 0
(DMAC suspended), and use the settings in the sections that follow.
(1)
Module-stop function
Writing 1 to the MSTPA22 bit in MSTPCRA enables the module-stop function of the DMAC. If a DMA transfer is in
progress when 1 is written to the MSTPA22 bit, the transition to the module-stop state continues after DMA transfer
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17. DMA Controller (DMAC)
ends. Access to the DMAC registers is prohibited while the MSTPA22 bit is 1. Writing 0 to the MSTPA22 bit releases
the DMAC from the module-stop state.
(2)
Software Standby mode
Use the settings described in section 11.7.1, Transition to Software Standby Mode.
If DMA transfer operations are in progress when the WFI instruction is executed, the DMA transfer completes before the
transition to Software Standby mode.
(3)
Notes on low power consumption function
For information on the WFI instruction and register settings, see section 11.9.6, Timing of WFI Instruction.
To perform DMA transfer after returning from low power consumption mode, set the DMST bit in DMAST to 1 again.
To use a request that is generated in Software Standby mode as an interrupt request to the CPU but not as a DMAC
startup request, specify the CPU as the interrupt request destination, as described in section 14.4.2, Selecting Interrupt
Request Destinations, and then execute the WFI instruction.
17.8
Usage Notes
17.8.1
DMA Transfer to External Devices
In a DMA transfer to an external device, the ACT flag in DMACm.DMSTS must be set to 0 (DMAC transfer suspended)
from the beginning of the final data write to the end of the external bus access.
17.8.2
Access to Registers during DMA Transfer
Do not write to the following registers of DMACm while the ACT flag in DMSTS of the associated channel is set to 1
(DMAC active state) or the DTE bit in DMCNT of the associated channel is set to 1 (DMA transfer enabled):
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
DMAMD
DMOFR.
17.8.3
DMA Transfer to Reserved Areas
DMA transfer to reserved areas is prohibited. If such an access is made, transfer results are not guaranteed. For details on
reserved areas, see section 4, Address Space.
17.8.4
Setting the DMAC Event Link Setting Register of the Interrupt Controller Unit
(ICU.DELSRn)
Before setting the DMAC Event Link Setting Register (ICU.DELSRn), make sure that the DMA Transfer Enable bit
(DMACm.DMCNT.DTE) is set to 0, disabling DMA transfer. Additionally, ensure that the DTC Activation Enable bit
(ICU.IELSRn.DTCE) associated with the event number set in the ICU.DELSRn register is not set to 1. For details on
ICU.IELSRn.DTCE and ICU.DELSRn, see section 14, Interrupt Controller Unit (ICU).
17.8.5
Suspending or Restarting DMA Activation
To suspend a DMA activation request, write 0 to the DMAC Event Link Select (ICU.DELSRn.DELS[7:0]) bit. To restart
the DMA transfer, write the event number to the ICU.DELSRn.DELS[7:0] bit with the settings shown in section 17.3.7,
Activating DMAC.
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18. Data Transfer Controller (DTC)
18.
Data Transfer Controller (DTC)
18.1
Overview
The Data Transfer Controller (DTC) performs data transfers when activated by an interrupt request. Table 18.1 lists the
DTC specifications, and Figure 18.1 shows a block diagram.
Table 18.1
DTC specifications
Item
Description
Transfer modes
Normal transfer mode
A single activation leads to a single data transfer.
Repeat transfer mode
A single activation leads to a single data transfer.
The transfer address returns to the start address after the number of data transfers reaches the
specified repeat size.
The maximum number of repeat transfers is 256 and the maximum data transfer size is 256 ×
32 bits (1024 bytes).
Block transfer mode
A single activation leads to the transfer of a single block.
The maximum block size is 256 × 32 bits = 1024 bytes.
Transfer channel
Channel transfer can be associated with the interrupt source (transferred by a DTC activation
request from the ICU)
Multiple data units can be transferred on a single activation source (chain transfer)
Chain transfers are selectable to either execute when the counter is 0, or always execute.
Transfer space
4 GB area from 0000 0000h to FFFF FFFFh, excluding reserved areas
Data transfer units
Single data unit: 1 byte (8 bits), 1 halfword (16 bits), 1 word (32 bits)
Single block size: 1 to 256 data units
CPU interrupt source
An interrupt request can be generated to the CPU on a DTC activation interrupt
An interrupt request can be generated to the CPU after a single data transfer
An interrupt request can be generated to the CPU after a data transfer of a specified volume.
Event link function
An event link request is generated after one data transfer (for block, after one block transfer)
Read skip
Read of transfer information can be skipped
Write-back skip
When the transfer source or destination address is specified as fixed, write-back of transfer
information can be skipped
Module-stop function
Module-stop state can be set to reduce power consumption
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18. Data Transfer Controller (DTC)
CPU
Non-maskable interrupt request
Interrupt request
Activation request
NVIC
DMAC
DMAC response
DTC
Interrupt
controller
MRA
MRB
CRA
CRB
SAR
DAR
Activation
control
Activation request
DTC response
Bus interface
DTCCR
Snooze control
signals
DTCVBR
DTCST
DTC_
DTCEND
System
DTC
response
control
DTCSTS
ELC
Internal peripheral bus 1
System bus
DMA bus
MRA:
MRB:
CRA:
CRB:
SAR:
DAR:
DTCCR:
DTCVBR:
DTCST:
DTCSTS:
Figure 18.1
DTC internal bus
Register
control
Vector number
DMA bus
Code
flash
FCU
Data flash
SRAM0
Transfer
information
SRAM1
Transfer
information
Internal
peripheral buses
External
memory
interface
External device
interface
DTC Mode Register A
DTC Mode Register B
DTC Transfer Count Register A
DTC Transfer Count Register B
DTC Transfer Source Register
DTC Transfer Destination Register
DTC Control Register
DTC Vector Base Register
DTC Module Start Register
DTC Status Register
DTC block diagram
See section 14.1, Overview in section 14, Interrupt Controller Unit (ICU) for the connections between the DTC and
NVIC (in the CPU).
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18.2
18. Data Transfer Controller (DTC)
Register Descriptions
MRA, MRB, SAR, DAR, CRA, and CRB are all DTC internal registers that cannot be directly accessed from the CPU.
Values to be set in these DTC internal registers are placed in the SRAM area as transfer information. When an activation
request is generated, the DTC reads the transfer information from the SRAM area and sets it in its internal registers. After
the data transfer ends, the internal register contents are written back to the SRAM area as transfer information.
18.2.1
DTC Mode Register A (MRA)
Address(es): (inaccessible directly from the CPU. See section 18.3.1)
b7
b6
b5
MD[1:0]
x
Value after reset:
x
b4
SZ[1:0]
x
b3
b2
SM[1:0]
x
x
x
b1
b0
—
—
x
x
x: Undefined
Bit
Symbol
Bit name
Description
b1, b0
—
Reserved
These bits are read as undefined. The write value should be 0. —
b3, b2
SM[1:0]
Transfer Source Address Addressing
Mode
b3 b2
—
b5, b4
SZ[1:0]
DTC Data Transfer Size
b5 b4
—
b7, b6
MD[1:0]
DTC Transfer Mode Select
b7 b6
—
0 0: Address in the SAR register is fixed.
(write-back to SAR is skipped.)
0 1: Address in the SAR register is fixed.
(write-back to SAR is skipped.)
1 0: SAR value is incremented after data transfer:
+1 when SZ[1:0] bits = 00b
+2 when SZ[1:0] bits = 01b
+4 when SZ[1:0] bits = 10b.
1 1: SAR value is decremented after data transfer:
-1 when SZ[1:0] bits = 00b
-2 when SZ[1:0] bits = 01b
-4 when SZ[1:0] bits = 10b.
0
0
1
1
0
0
1
1
0: Byte (8-bit) transfer
1: Halfword (16-bit) transfer
0: Word (32-bit) transfer
1: Setting prohibited.
0: Normal transfer mode
1: Repeat transfer mode
0: Block transfer mode
1: Setting prohibited.
R/W
The MRA cannot be accessed directly from the CPU. However, the CPU can access the SRAM area (transfer
information (n) start address + 03h) and the DTC automatically transfers the MRA transfer information to and from the
MRA register. See section 18.3.1, Allocating Transfer Information and DTC Vector Table.
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18.2.2
18. Data Transfer Controller (DTC)
DTC Mode Register B (MRB)
Address(es): (inaccessible directly from the CPU. See section 18.3.1)
b7
CHNE
x
Value after reset:
b6
b5
CHNS DISEL
x
x
b4
DTS
x
b3
b2
DM[1:0]
x
x
b1
b0
—
—
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as undefined. The write value should be 0.
—
b3, b2
DM[1:0]
Transfer Destination Address
Addressing Mode
b3 b2
—
b4
DTS
DTC Transfer Mode Select
0: Select transfer destination as repeat or block area
1: Select transfer source as repeat or block area.
—
b5
DISEL
DTC Interrupt Select
0: Generate an interrupt request to the CPU when specified data
transfer is complete
1: Generate an interrupt request to the CPU each time DTC data
transfer is performed.
—
b6
CHNS
DTC Chain Transfer Select
0: Select continuous chain transfer
1: Select chain transfer to occur only when the transfer counter is
changed from 1 to 0 or 1 to CRAH.
—
b7
CHNE
DTC Chain Transfer Enable
0: Disable chain transfer
1: Enable chain transfer.
—
0 0: Address in the DAR register is fixed (write-back to DAR is
skipped)
0 1: Address in the DAR register is fixed (write-back to DAR is
skipped)
1 0: DAR value is incremented after data transfer:
+1 when MRA.SZ[1:0] bits = 00b
+2 when SZ[1:0] bits = 01b
+4 when SZ[1:0] bits = 10b.
1 1: DAR value is decremented after data transfer:
-1 when MRA.SZ[1:0] bits = 00b
-2 when SZ[1:0] bits = 01b
-4 when SZ[1:0] bits = 10b.
The MRB register cannot be accessed directly from the CPU. However, the CPU can access the SRAM area (transfer
information (n) start address + 02h) and the DTC automatically transfers the MRB transfer information to and from the
MRB register. See section 18.3.1, Allocating Transfer Information and DTC Vector Table.
DTS bit (DTC Transfer Mode Select)
The DTS bit selects either the transfer source or transfer destination as the repeat area or block area in repeat or block
transfer mode.
CHNS bit (DTC Chain Transfer Select)
The CHNS bit selects the chain transfer condition. When the CHNE bit is 0, the CHNS setting is ignored. For details on
the conditions for chain transfer, see Table 18.3, Chain transfer conditions.
When the next transfer is a chain transfer, completion of the specified number of transfers is not determined, the
activation source flag is not cleared, and an interrupt request to the CPU is not generated.
CHNE bit (DTC Chain Transfer Enable)
The CHNE bit enables chain transfer. The chain transfer condition is selected in the CHNS bit. For details, see section
18.4.6, Chain Transfer.
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18.2.3
18. Data Transfer Controller (DTC)
DTC Transfer Source Register (SAR)
Address(es): (inaccessible directly from the CPU. See section 18.3.1)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The SAR sets the transfer source start address. SAR cannot be accessed directly from the CPU. However, the CPU can
access the SRAM area (transfer information (n) start address + 04h) and the DTC automatically transfers the SAR
transfer information to and from the SAR register. See section 18.3.1, Allocating Transfer Information and DTC Vector
Table.
Note:
Misalignment is prohibited for DTC transfers.
Bit [0] must be 0 when MRA.SZ[1:0] = 01b. Bits [1] and [0] must be 0 when MRA.SZ[1:0] = 10b.
18.2.4
DTC Transfer Destination Register (DAR)
Address(es): (inaccessible directly from the CPU. See section 18.3.1)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The DAR register sets the transfer destination start address. It cannot be accessed directly from the CPU. However, CPU
can access the SRAM area (transfer information (n) start address + 08h) and the DTC automatically transfers the transfer
information to and from the DAR register. See section 18.3.1, Allocating Transfer Information and DTC Vector Table.
Note:
Misalignment is prohibited for DTC transfers. Bit [0] must be 0 when MRA.SZ[1:0] = 01b. Bits [1] and [0] must be
0 when MRA.SZ[1:0] = 10b.
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18.2.5
18. Data Transfer Controller (DTC)
DTC Transfer Count Register A (CRA)
Address(es): (inaccessible directly from the CPU. See section 18.3.1)
Normal transfer mode
CRA
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Repeat transfer mode/block transfer mode
CRAH
Value after reset:
CRAL
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Symbol
Register name
Description
R/W
CRAL
Transfer Counter A Lower Register
Sets the transfer count
—
CRAH
Transfer Counter A Upper Register
Note:
Note:
—
The function depends on the transfer mode.
Set CRAH and CRAL to the same value in repeat transfer mode and block transfer mode.
The CRA register cannot be accessed directly from the CPU. However, the CPU can access the SRAM area (transfer
information (n) start address + 0Eh) and the DTC automatically transfers the transfer information to and from the CRA
register. See section 18.3.1, Allocating Transfer Information and DTC Vector Table.
(1)
Normal transfer mode (MRA.MD[1:0] bits = 00b)
In normal transfer mode, CRA functions as a 16-bit transfer counter. The transfer count is 1, 65,535, and 65,536 when the
set value is 0001h, FFFFh, and 0000h, respectively. The CRA value is decremented (-1) on each data transfer.
(2)
Repeat transfer mode (MRA.MD[1:0] bits = 01b)
In repeat transfer mode, the CRAH register holds the transfer count and the CRAL register functions as an 8-bit transfer
counter. The transfer count is 1, 255, and 256 when the set value is 01h, FFh, and 00h, respectively. The CRAL value is
decremented (-1) on each data transfer. When it reaches 00h, the CRAH value is transferred to CRAL.
(3)
Block transfer mode (MRA.MD[1:0] bits = 10b)
In block transfer mode, the CRAH register holds the block size and the CRAL register functions as an 8-bit block size
counter. The transfer count is 1, 255, and 256 when the set value is 01h, FFh, and 00h, respectively. The CRAL value is
decremented (-1) at each data transfer. When it reaches 00h, the CRAH value is transferred to CRAL.
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18.2.6
18. Data Transfer Controller (DTC)
DTC Transfer Count Register B (CRB)
Address(es): (inaccessible directly from the CPU. See section 18.3.1)
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The CRB register sets the block transfer count for block transfer mode. The transfer count is 1, 65,535, and 65,536 when
the set value is 0001h, FFFFh, and 0000h, respectively. The CRB value is decremented (-1) when the final data of a
single block size is transferred. When normal transfer mode or repeat transfer mode is selected, this register is not used
and the set value is ignored.
The CRB register cannot be accessed directly from the CPU. However, the CPU can access the SRAM area (transfer
information (n) start address + 0Ch) and the DTC automatically transfers the transfer information to and from the CRB
register. See section 18.3.1, Allocating Transfer Information and DTC Vector Table.
18.2.7
DTC Control Register (DTCCR)
Address(es): DTC.DTCCR 4000 5400h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
RRS
—
—
—
—
0
0
0
0
1
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b4
RRS
DTC Transfer Information
Read Skip Enable
0: Transfer information read is not skipped
1: Transfer information read is skipped when vector numbers match.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RRS bit (DTC Transfer Information Read Skip Enable)
The RRS bit enables skipping of transfer information reads when vector numbers match. The DTC vector number is
compared with the vector number in the previous activation process. When these vector numbers match and the RRS bit
is set to 1, the DTC data transfer is performed without reading the transfer information. However, when the previous
transfer is a chain transfer, the transfer information is read regardless of the RRS bit.
When the transfer counter (CRA register) becomes 0 during the previous normal transfer and when the transfer counter
(CRB register) becomes 0 during the previous block transfer, the transfer information is read regardless of the RRS bit
value.
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18.2.8
18. Data Transfer Controller (DTC)
DTC Vector Base Register (DTCVBR)
Address(es): DTC.DTCVBR 4000 5404h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Bit name
Description
b31 to b0
DTC Vector Base Address
Sets the DTC vector base address. The lower 10 bits should be 0. R/W
R/W
The DTCVBR register sets the base address for calculating the DTC vector table address, which can be set in the range
of 0000 0000h to FFFF FFFFh (4 GB) in 1-KB units.
18.2.9
DTC Module Start Register (DTCST)
Address(es): DTC.DTCST 4000 540Ch
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DTCST
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DTCST
DTC Module Start
0: Stop DTC module
1: Start DTC module.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
DTCST bit (DTC Module Start)
Set the DTCST bit to 1 to enable the DTC to accept transfer requests. When the DTCST bit is set to 0, transfer requests
are no longer accepted. If this bit is set to 0 during a data transfer, the accepted transfer request is active until processing
is complete.
DTCST must be set to 0 before transitioning to any one of the following state or mode:
Module-stop state
Software Standby mode without Snooze mode transition.
For details on these transitions, see section 18.10, Module-Stop Function, and section 11, Low Power Modes.
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18.2.10
18. Data Transfer Controller (DTC)
DTC Status Register (DTCSTS)
Address(es): DTC.DTCSTS 4000 540Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
ACT
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
VECN[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
VECN[7:0]
DTC-Activating Vector
Number Monitoring
These bits indicate the vector number for the activation source
when a DTC transfer is in progress.
The value is valid only if a DTC transfer is in progress (ACT flag is
1).
R
b14 to b8
—
Reserved
These bits are read as 0
R
b15
ACT
DTC Active Flag
0: DTC transfer operation is not in progress
1: DTC transfer operation is in progress.
R
VECN[7:0] bits (DTC-Activating Vector Number Monitoring)
While transfer by the DTC is in progress, the VECN[7:0] bits indicate the vector number associated with the activation
source for the transfer. The value read from the VECN[7:0] bits is valid if the ACT flag is 1, indicating that a DTC
transfer is in progress, and invalid if the ACT flag is 0, indicating that no current DTC transfer is in progress.
ACT flag (DTC Active Flag)
The ACT flag indicates the state of the DTC transfer operation.
[Setting condition]
When the DTC is activated by a transfer request.
[Clearing condition]
When transfer by the DTC, in response to a transfer request, is complete.
18.3
Activation Sources
The DTC is activated by an interrupt request. Setting the ICU.IELSRn.DTCE bit to 1 enables activation of the DTC by
the associated interrupt. The selector output n number set in ICU.IELSRn is defined as the interrupt vector number,
where n = 0 to 63. For an enabled interrupt, the specific DTC interrupt source associated with each interrupt vector
number n is selected in ICU.IELSRn.IELS[7:0], where n = 0 to 63, as listed in Table 14.4, Event table in section 14,
Interrupt Controller Unit (ICU). For activation by software, see section 19.2.2, Event Link Software Event Generation
Register n (ELSEGRn) (n = 0, 1).
The interrupt vector number is equivalent to the DTC vector table number. After the DTC accepted an activation request,
it does not accept another activation request until transfer for that single request is complete, regardless of the priority of
the requests. When multiple activation requests are generated during a DMAC or DTC transfer, a highest priority request
is accepted on completion of the transfer. When multiple activation requests are generated while the DTC Module Start
bit (DTCST.DTCST) is 0, the DTC accepts the highest priority request when DTCST.DTCST is subsequently set to 1.
The smaller interrupt vector number has higher priority.
The DTC performs the following operations at the start of a single data transfer or for a chain transfer, after the last of the
consecutive transfers:
On completion of a specified round of data transfer, the ICU.IELSRn.DTCE bit is set to 0 and an interrupt request is
sent to the CPU
If the MRB.DISEL bit is 1, an interrupt request is sent to the CPU on completion of a data transfer
For other transfers, the ICU.IELSRn.IR bit of the activation source is set to 0 at the start of the data transfer.
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18.3.1
18. Data Transfer Controller (DTC)
Allocating Transfer Information and DTC Vector Table
The DTC reads the start address of the transfer information associated with each activation source from the vector table
and reads the transfer information starting at that address.
The vector table must be located so that the lower 10 bits of the base address (start address) are 0. Use the DTC Vector
Base Register (DTCVBR) to set the base address of the DTC vector table. Transfer information is allocated in the SRAM
area. In the SRAM area, the start address of the transfer information (n) with vector number n must be 4n added to the
base address in the vector table.
Figure 18.2 shows the relationship between the DTC vector table and transfer information. Figure 18.3 shows the
allocation of transfer information in the SRAM area.
Upper: DTCVBR
Lower: Vector number 4
DTC vector table
Transfer information (1)
DTC vector address
Transfer information (1)
start address
+4
Transfer information (2)
start address
Transfer information (2)
:
:
:
+4(n-1)
:
:
:
Transfer information (n)
start address
4 bytes
Transfer information (n)
4 bytes
Figure 18.2
DTC vector table and transfer information
Allocation of transfer information
Lower address
Start address
3
2
1
MRA
MRB
0
Reserved (0)
Transfer information
per transfer
(4 words (16 bytes))
SAR
DAR
Chain
transfer
CRA
MRA
CRB
MRB
Reserved (0)
Transfer information for
the second transfer in
chain transfer mode
(4 words (16 bytes))
SAR
DAR
CRA
CRB
4 bytes
Figure 18.3
Allocation of transfer information in the SRAM area
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18.4
18. Data Transfer Controller (DTC)
Operation
The DTC transfers data according to the transfer information. Storage of the transfer information in the SRAM area is
required before a DTC operation. When the DTC is activated, it reads the DTC vector associated with the vector number.
The DTC then reads the transfer information from the transfer information store address referenced by the DTC vector
and transfers the data. After the data transfer, the DTC writes back the transfer information. Storing the transfer
information in the SRAM area allows the data transfer of any number of channels.
The transfer modes include:
Normal transfer mode
Repeat transfer mode
Block transfer mode.
The DTC specifies a transfer source address in the SAR register and a transfer destination address in the DAR register.
The values of these registers are incremented, decremented, or address-fixed independently after the data transfer.
Table 18.2 describes the DTC transfer modes.
Table 18.2
DTC transfer modes
Increment or decrement of
memory address
Settable transfer
count
1 byte (8 bit), 1 halfword (16 bit), or 1 word (32 bit)
Incremented or decremented by
1, 2, or 4 or address fixed
1 to 65,536
Repeat transfer mode*1 1 byte (8 bit), 1 halfword (16 bit), or 1 word (32 bit)
Incremented or decremented by
1, 2, or 4 or address fixed
1 to 256*3
Block transfer mode*2
Incremented or decremented by
1, 2, or 4 or address fixed
1 to 65,536
Transfer mode
Data size transferred on single transfer request
Normal transfer mode
Note 1.
Note 2.
Note 3.
Block size specified in CRAH
(1 to 256 bytes, 1 to 256 halfwords (2 to 512 bytes),
or 1 to 256 words (4 to 1024 bytes))
Set the transfer source or transfer destination as the repeat area.
Set the transfer source or transfer destination as the block area.
After a data transfer of the specified count, the initial state is restored and operation restarts.
Setting the MRB.CHNE bit to 1 allows multiple transfers or chain transfer on a single activation source. It also enables a
chain transfer when the specified data transfer is complete.
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18. Data Transfer Controller (DTC)
Figure 18.4 shows the operation flow of the DTC. Table 18.3 lists the chain transfer conditions. The combination of
control information for the second and subsequent transfers are omitted in this table.
Start
Match and
RRS bit = 1
Compare vector
numbers. Match?
Mismatch or RRS bit = 0
Read DTC vector
Next transfer
Read transfer
information
Update transfer
information start address
Yes
CHNE bit = 1?
Yes
No
CHNS bit = 0
No
Yes
MD[1:0] bits = 01b?
(Repeat transfer mode?)
No
Last data transfer?
(Transfer counter = 1?)*1
Yes
Last data transfer?
(Transfer counter = 1?)*1
No
Yes
No
Yes
DISEL bit = 1?
No
Clear the ICU.IELSRn.IR
bit
Transfer data
Transfer data
Transfer data
Transfer data
Write transfer information
Write transfer information
Write transfer information
Write transfer information
Clear the ICU.IELSRn.DTCE bit.
An interrupt to the CPU is
generated.
An interrupt to the CPU
is generated
End
Note 1.
Figure 18.4
Counter value before starting data transfer.
DTC operation flow
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Table 18.3
18. Data Transfer Controller (DTC)
Chain transfer conditions
Second transfer*3
First transfer
CHNE
bit
CHNS
bit
DISEL
bit
Transfer counter*1, *2
CHNE
bit
CHNS
bit
DISEL
bit
Transfer counter*1, *2
DTC transfer
0
-
0
Other than (1 → 0)
-
-
-
-
Ends after the first
transfer
0
-
0
(1 → 0)
-
-
-
-
0
-
1
-
-
-
-
-
Ends after the first
transfer with an interrupt
request to the CPU
1
0
-
-
0
-
0
Other than (1 → 0)
Ends after the second
transfer
0
-
0
(1 → 0)
0
-
1
-
Ends after the second
transfer with an interrupt
request to the CPU
1
1
0
Other than (1 → *)
-
-
-
-
Ends after the first
transfer
1
1
-
(1 → *)
0
-
0
Other than (1 → 0)
Ends after the second
transfer
0
-
0
(1 → 0)
0
-
1
-
Ends after the second
transfer with an interrupt
request to the CPU
-
-
-
-
1
Note 1.
Note 2.
Note 3.
18.4.1
1
1
Other than (1 → *)
Ends after the first
transfer with an interrupt
request to the CPU
The transfer counter used depends on the transfer modes as follows:
Normal transfer mode — CRA register
Repeat transfer mode — CRAL register
Block transfer mode — CRB register
On completion of a data transfer, the counters operate as follows:
1 → 0 in normal and block transfer modes
1 → CRAH in repeat transfer mode
(1 → *) in the table indicates both of these two operations, depending on the mode.
Chain transfer can be selected for the second or subsequent transfers. The conditions for the combination of the second
transfer and CHNE bit = 1 is omitted.
Transfer Information Read Skip Function
Reading of vector addresses and transfer information can be skipped by setting the DTCCR.RRS bit. When a DTC
activation request is generated, the current DTC vector number is compared to the DTC vector number in the previous
activation process. When these vector numbers match and the RRS bit is set to 1, the DTC data transfer is performed
without reading the vector address and transfer information. However, when the previous transfer is a chain transfer, the
vector address and transfer information are read. Additionally, when the transfer counter (CRA register) becomes 0
during the previous normal transfer, or when the transfer counter (CRB register) becomes 0 during the previous block
transfer, transfer information is read regardless of the RRS bit. Figure 18.12 shows an example of a transfer information
read skip.
To update the vector table and transfer information, set the RRS bit to 0, update the vector table and transfer information,
and then set the RRS bit to 1. The stored vector number is discarded by setting the RRS bit to 0. The updated DTC vector
table and transfer information are read in the next activation process.
18.4.2
Transfer Information Write-Back Skip Function
When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to address fixed, a part of the transfer information is not
written back. Table 18.4 lists the transfer information write-back skip conditions and the associated registers. The CRA
and CRB registers are written back, and the write-back of the MRA and MRB registers is skipped.
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Table 18.4
18. Data Transfer Controller (DTC)
Transfer information write-back skip conditions and applicable registers
MRA.SM[1:0] bits
MRB.DM[1:0] bits
b3
b2
b3
b2
SAR register
DAR register
0
0
0
0
Skip
Skip
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
Skip
Write-back
0
0
1
1
0
1
1
0
0
1
1
1
1
0
0
0
Write-back
Skip
1
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
Write-back
Write-back
1
0
1
1
1
1
1
0
1
1
1
1
18.4.3
Normal Transfer Mode
The normal transfer mode allows a 1-byte (8-bit), 1-halfword (16-bit), 1-word (32-bit) data transfer on a single activation
source. The transfer count can be set from 1 to 65,536. Transfer source and transfer destination addresses can be
independently set to increment, decrement, or remain fixed. This mode enables an interrupt request to the CPU to be
generated at the end of a specified-count transfer.
Table 18.5 lists register functions in normal transfer mode, and Figure 18.5 shows the memory map of normal transfer
mode.
Table 18.5
Register functions in normal transfer mode
Register
Description
Value written back by writing transfer information
SAR
Transfer source address
Increment, decrement, or fixed*1
DAR
Transfer destination address
Increment, decrement, or fixed*1
CRA
Transfer counter A
CRA - 1
CRB
Transfer counter B
Not updated
Note 1.
Write-back operation is skipped in address-fixed mode.
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18. Data Transfer Controller (DTC)
Transfer source data area
SAR
Data 1
Data 2
Figure 18.5
18.4.4
Transfer destination data area
Transfer 6
times
(transfer 1 data
unit per event)
Data 1
DAR
Data 2
Data 3
Data 3
Data 4
Data 4
Data 5
Data 5
Data 6
Data 6
Memory map of normal transfer mode (MRA.SM[1:0] = 10b, MRB.DM[1:0] = 10b, CRA = 0006h)
Repeat Transfer Mode
Repeat transfer mode allows a 1-byte (8-bit), 1-halfword (16-bit), or 1-word (32-bit) data transfer on a single activation
source. Transfer source or transfer destination for the repeat area must be specified in the MRB.DTS bit. The transfer
count can be set from 1 to 256. When the specified-count transfer is complete, the initial value of the address register
specified in the repeat area is restored, the initial value of the transfer counter is restored, and transfer is repeated. The
other address register is incremented or decremented continuously or remains unchanged.
When the transfer counter CRAL decrements to 00h in repeat transfer mode, the CRAL value is updated to the value set
in the CRAH register. As a result, the transfer counter does not become 00h, which disables interrupt requests to the CPU
when the MRB.DISEL bit is set to 0. An interrupt request to the CPU is generated when the specified data transfer is
complete.
Table 18.6 lists the register functions in repeat transfer mode, and Figure 18.6 shows the memory map of repeat transfer
mode.
Table 18.6
Register functions in repeat transfer mode
Value written back by writing transfer information
Register
Description
When CRAL is not 1
When CRAL is 1
SAR
Transfer source
address
Increment, decrement, or fixed*1
When the MRB.DTS bit is 0
Increment, decrement, or fixed*1
When the MRB.DTS bit is 1
SAR register initial value
DAR
Transfer destination
address
Increment, decrement, or fixed*1
When the MRB.DTS bit is 0
DAR register initial value
When the MRB.DTS bit is 1
Increment, decrement, or fixed*1
CRAH
Retains transfer
counter
CRAH
CRAH
CRAL
Transfer counter A
CRAL - 1
CRAH
CRB
Transfer counter B
Not updated
Not updated
Note 1.
Write-back is skipped in address-fixed mode.
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18. Data Transfer Controller (DTC)
Transfer source data area
(set to repeat area)
SAR
Data 1
Data 2
Transfer destination data area
Transfer 8
times
(transfer 1 data
unit per event)
Data 1
DAR
Data 2
Data 3
Data 3
Data 4
Data 4
Data 1
Data 2
Data 3
Data 4
Figure 18.6
18.4.5
Memory map of repeat transfer mode when transfer source is a repeat area (MRA.SM[1:0] = 10b,
MRB.DM[1:0] = 10b, CRAH = 04h)
Block Transfer Mode
This mode allows single-block data transfer on a single activation source. Transfer source or transfer destination for the
block area must be specified in the MRB.DTS bit. The block size can be set from 1 to 256 bytes, 1 to 256 halfwords (2 to
512 bytes), or 1 to 256 words (4 to 1024 bytes). When transfer of the specified block completes, the initial values of the
block size counter CRAL and the address register (the SAR register when the MRB.DTS bit is 1 or the DAR register
when the DTS bit is 0) specified in the block area are restored. The other address register is incremented or decremented
continuously or remains unchanged.
The transfer count (block count) can be set from 1 to 65,536. This mode enables an interrupt request to the CPU to be
generated at the end of the specified-count block transfer.
Table 18.7 lists register functions in block transfer mode, and Figure 18.7 shows the memory map of block transfer
mode.
Table 18.7
Register functions in block transfer mode
Register
Description
Value written back by writing transfer information
SAR
Transfer source address
When MRB.DTS bit is 0
Increment, decrement, or fixed*1
When MRB.DTS bit is 1
SAR register initial value
DAR
Transfer destination address
When MRB.DTS bit is 0
DAR register initial value
When MRB.DTS bit is 1
Increment, decrement, or fixed*1
CRAH
Retains block size
CRAH
CRAL
Block size counter
CRAH
CRB
Block transfer counter
CRB - 1
Note 1.
Write-back is skipped in address-fixed mode.
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18. Data Transfer Controller (DTC)
Transfer source data area
SAR
First block
Transfer destination data area
(set to block area)
Transfer
Block area
DAR
nth block
Figure 18.7
18.4.6
Memory map of block transfer mode
Chain Transfer
Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single activation source. If
MRB.CHNE is set to 1 and CHNS to 0, an interrupt request to the CPU is not generated on completion of the specified
number of rounds of transfer or by setting the MRB.DISEL bit to 1. An interrupt request is sent to the CPU each time
DTC data transfer is performed. Data transfer has no effect on the ICU.IELSRn.IR bit of the activation source.
The SAR, DAR, CRA, CRB, MRA, and MRB registers can be set independently of each other to define data transfer.
Figure 18.8 shows a chain transfer operation.
Data area
Transfer source data (1)
DTC vector table
Transfer information
allocated in the SRAM
Transfer destination data (1)
DTC vector
address
Transfer information start
address
Transfer information
CHNE bit = 1
Transfer information
CHNE bit = 0
Transfer source data (2)
Transfer destination data (2)
Figure 18.8
Chain transfer operation
Writing 1 to the MRB.CHNE and CHNS bits enables chain transfer to be performed only after completion of the
specified data transfer. In repeat transfer mode, chain transfer is performed after completion of the specified data transfer.
For details on chain transfer conditions, see Table 18.3, Chain transfer conditions.
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18.4.7
18. Data Transfer Controller (DTC)
Operation Timing
Figure 18.9 to Figure 18.12 are timing diagrams that show the minimum number of execution cycles.
System clock
ICU.IELSRn.IR
DTC activation request
DTC access
R
Vector read
Figure 18.9
Transfer
information read
W
Data
transfer
Transfer
information write
Example 1 of DTC operation timing in normal transfer mode and repeat transfer mode
System clock
ICU.IELSRn.IR
DTC activation request
DTC access
Vector read
Figure 18.10
Transfer
information read
Data transfer
Transfer
information write
Example 2 of DTC operation timing in block transfer mode when block size = 4
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18. Data Transfer Controller (DTC)
System clock
ICU.IELSRn.IR
DTC activation request
DTC access
R
Vector read
Figure 18.11
Transfer
information read
W
Data
transfer
R
Transfer
information
write
W
Data
transfer
Transfer
information
read
Transfer
information
write
Example 3 of DTC operation timing for chain transfer
System clock
ICU.IELSRn.IR
(2)
(1)
DTC activation request
Read skip enable
R
DTC access
Vector read
Note:
Transfer
information read
W
Data
transfer
RR
Transfer
information write
W
Data
transfer
Transfer
information write
When activation sources (vector numbers) of (1) and (2) are the same and the RRS bit = 1, the transfer information
read for request (2) is skipped.
Figure 18.12
Example of operation when transfer information read is skipped, with the vector, transfer
information, transfer destination data on the SRAM, and the transfer source data on the
peripheral module
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18.4.8
18. Data Transfer Controller (DTC)
Execution Cycles of DTC
Table 18.8 lists the execution cycles of single data transfer of the DTC.
For the order of the execution states, see section 18.4.7, Operation Timing.
Table 18.8
Execution cycles of DTC
Data transfer
Read
Write
Internal
operation
Cr + 1
Cw + 1
2
Repeat
Cr + 1
Cw + 1
Block*5
P × Cr
P × Cw
Transfer
mode
Vector read
Normal
Cv + 1
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
0*1
Transfer information read
4 × Ci + 1
0*1
Transfer information write
3 × Ci + 1*2
2 × Ci + 1*3
Ci*4
0*1
When transfer information read is skipped.
When neither SAR nor DAR is set to address-fixed mode.
When SAR or DAR is set to address-fixed mode.
When SAR and DAR are set to address-fixed mode.
When the block size is 2 or more. If the block size is 1, the cycle number for normal transfer is applied.
P: Block size (initial settings of CRAH and CRAL)
Cv: Cycles for access to vector transfer information storage destination
Ci: Cycles for access to transfer information storage destination address
Cr: Cycles for access to data read destination
Cw: Cycles for access to data write destination
The unit is system clocks (ICLK) for + 1 in the Vector read, Transfer information read, and Data transfer read columns and 2 in the
Internal operation column.
Cv, Ci, Cr, and Cw vary depending on the corresponding access destination. For the number of cycles for respective access
destinations, see section 46, SRAM, section 47, Flash Memory, and section 15, Buses.
The frequency ratio of the system clock and peripheral clock is also taken into consideration.
The DTC response time is the time from when the DTC activation source is detected until DTC transfer starts.
This table does not include the time until DTC data transfer starts after the DTC activation source becomes active.
18.4.9
DTC Bus Mastership Release Timing
The DTC does not release the bus mastership during transfer information reads. Before the transfer information is read or
written, the bus is arbitrated according to the priority determined by the bus master arbitrator. For bus arbitration, see
section 15, Buses.
18.5
DTC Setting Procedure
Before using the DTC, set the DTC Vector Base Register (DTCVBR). Figure 18.13 shows the procedure for setting the
DTC.
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18. Data Transfer Controller (DTC)
Start
Set the ICU.IELSRn.IELS[7:0] bit to 0. Disable the interrupt in
the NVIC and provide the following settings:
Set the DTCCR.RRS bit to 0
[1]
Set transfer information
(MRA, MRB, SAR, DAR, CRA, and CRB)
[2]
[1] Set the DTCCR.RRS bit to 0 to reset the transfer
information read skip flag. After that, transfer information
read is not skipped while the DTC is activated. Specify this
setting when transfer information is updated.
[2] Allocate the transfer information (MRA, MRB, SAR, DAR,
CRA, and CRB) in the data area. To set transfer
information, see section 18.2, Register Descriptions. To
allocate transfer information, see section 18.3.1, Allocating
Transfer Information and DTC Vector Table.
Set transfer information start addresses in
the DTC vector table
[3]
[3] Set the transfer information start addresses in the DTC
vector table. To set the DTC vector table, see section
18.3.1, Allocating Transfer Information and DTC Vector
Table.
Set the DTCCR.RRS bit to 1
[4]
[4] Setting the DTCCR.RRS bit to 1 enables skipping of the
second and the subsequent transfer information read cycles
for continuous DTC activation from the same interrupt
source. The RRS bit can be set to 1, but if this is set during
DTC transfer, it becomes valid from the next transfer.
Set the ICU.IELSRn.DTCE bit to 1.
Set the ICU.IELSRn.IELS as interrupt source.
The interrupt should be enabled in the NVIC.
Set the enable bit for
an activation source interrupt
[5]
[6]
Setting for each activation
source
Common setting
for DTC
Set the DTCST.DTCST bit to 1
[5] Set the ICU.IELSRn.DTCE bit to 1. Set ICU.IELSRn.IELS
as the interrupt sources that trigger DTC. The interrupts
must be enabled in the NVIC. See the Table 14.4, Event
table.
[6] Set the enable bit for an activation source interrupt to 1.
When a source interrupt is generated, the DTC is activated.
To set the interrupt source enable bit, see the settings for
the modules that are to be the activation sources.
[7] Set the DTC Module Start bit (DTCST.DTCST) to 1.
[7]
Note:
The DTCST.DTCST bit can be set even if the
setting for the activation source is not complete.
End
Figure 18.13
DTC setting procedure
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18.6
18. Data Transfer Controller (DTC)
Examples of DTC Usage
18.6.1
Normal Transfer
This section provides an example of DTC usage and its application when receiving 128 bytes of data from an SCI.
(1)
Transfer information settings
In the MRA register, select a fixed source address (MRA.SM[1:0] bits = 00b), normal transfer mode (MRA.MD[1:0] bits
= 00b), and byte-sized transfer (MRA.SZ[1:0] bits = 00b). In the MRB register, specify incrementation of the destination
address (MRB.DM[1:0] bits = 10b) and single data transfer by a single interrupt (MRB.CHNE bit = 0 and MRB.DISEL
bit = 0). The MRB.DTS bit can be set to any value. Set the RDR register address of the SCI in the SAR register, the start
address of the SRAM area for data storage in the DAR register, and 128 (0080h) in the CRA register. The CRB register
can be set to any value.
(2)
DTC vector table settings
The start address of the transfer information for the RXI interrupt is set in the vector table for the DTC.
(3)
ICU settings and DTC module activation
Set the ICU.IELSRn.DTCE bit to 1 and set ICU.IELSRn.IELS as the SCI interrupt. The interrupt must be enabled in the
NVIC. Set the DTCST.DTCST bit to 1.
(4)
SCI settings
Enable the RXI interrupt by setting the SCR.RIE bit in the SCI to 1. If a reception error occurs during the SCI receive
operation, reception stops. To manage this, use settings that allows the CPU to accept receive error interrupts.
(5)
DTC transfer
Every time a reception of 1 byte by the SCI completes, an RXI interrupt is generated to activate the DTC. The DTC
transfers the received byte from the RDR of the SCI to the SRAM, after which the DAR register is incremented and the
CRA register is decremented.
(6)
Interrupt handling
After 128 rounds of data transfer are complete and the value in the CRA register becomes 0, an RXI interrupt request is
generated for the CPU. Complete the process in the handling routine for this interrupt.
18.6.2
Chain Transfer
This section provides an example of chain transfer by the DTC and describes its use in the output of pulses by the
General PWM Timer (GPT). You can use chain transfers to transfer PWM timer compare data and change the period of
the PWM timer for the GPT.
For the first of the chain transfers, normal transfer mode is specified for transfer to the GPTm.GTCCRC register (m =
320 to 323, 164 to 169). For the second transfer, normal transfer mode is specified for transfer to the GPTm.GTCCRE
register (m = 320 to 323, 164 to 169). For the third transfer, normal transfer mode is specified for transfer to the
GPTm.GTPBR register (m = 320 to 323, 164 to 169). This is because clearing of the activation source and generation of
an interrupt on completion of the specified number of transfers are restricted to the third of the chain transfers, that is,
transfer while MRB.CHNE bit = 0.
The following example shows how to use the counter overflow interrupt with a GPT320.GTPR register as an activating
source for the DTC.
(1)
First transfer information setting
Set up transfer to the GPT320.GTCCRC register:
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] bits = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] bits = 00b) and word-sized transfer (MRA.SZ[1:0] bits =
10b).
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] bits = 00b) and set up chain transfer
(MRB.CHNE bit = 1 and MRB.CHNS bit = 0).
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18. Data Transfer Controller (DTC)
4. Set the SAR to the first address of the data table.
5. Set the DAR register to the address of the GPT320.GTCCRC register.
6. Set the CRAH and CRAL registers to the size of the data table. The CRB register can be set to any value.
(2)
Second transfer information setting
Set up transfer to the GPT320.GTCCRE register:
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] bits = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] bits = 00b) and word-sized transfer (MRA.SZ[1:0] bits =
10b).
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] bits = 00b) and set up chain transfer
(MRB.CHNE bit = 1 and MRB.CHNS bit = 0).
4. Set the SAR register to the first address of the data table.
5. Set the DAR register to the address of the GPT320.GTCCRE register.
6. Set the CRAH and CRAL registers to the size of the data table. The CRB register can be set to any value.
(3)
Third transfer information set
Set up transfer to the GPT320.GTPBR register:
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] bits = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] bits = 00b) and word-sized transfer (MRA.SZ[1:0] bits =
10b).
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] bits = 00b) and set up single data
transfer per interrupt (MRB.CHNE bit = 0, MRB.DISEL bit = 0). The MRB.DTS bit can be set to any value.
4. Set the SAR register to the first address of the data table.
5. Set the DAR register to the address of the GPT320.GTPBR register.
6. Set the CRA register to the size of the data table. The CRB register can be set to any value.
(4)
Transfer information assignment
Place the transfer information for use in the transfer to the GPT320.GTPBR immediately after the transfer control
information for use in the GPT320.GTCCRC and GPT320.GTCCRE registers.
(5)
DTC vector table
In the DTC vector table, set the address where the transfer control information for use in transfer to the
GPT320.GTCCRC and GPT320.GTCCRE registers starts.
(6)
ICU setting and DTC module activation
1. Set the ICU.IELSRn.DTCE bit associated with the GPT320 counter overflow interrupt.
2. Set the ICU.IELSRn.IELS[7:0] to 97 (61h) for the GPT320 counter overflow.
3. Set the DTCST.DTCST bit to 1.
(7)
GPT settings
1. Set the GPT320.GTIOR register so that the GTCCRA and GTCCRB registers operate as output compare registers.
2. Set the default PWM timer compare values in the GPT320.GTCCRA and GPT320.GTCCRB registers and the next
PWM timer compare values in the GPT320.GTCCRC and GPT320.GTCCRE registers.
3. Set the default PWM timer period values in the GPT320.GTPR register and the next PWM timer period values in
the GPT320.GTPBR register.
4. Set 1 to the output bit in PmnPFS.PDR, and set 00011b to the Peripheral Select bits in PmnPFS.PSEL[4:0].
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(8)
18. Data Transfer Controller (DTC)
GPT activation
Set the GPT320.GTSTR.CSTRT bits to 1 to start the GPT320.GTCNT counter.
(9)
DTC transfer
Every time a GPT320 counter overflow is generated with the GPT320.GTPR register, the next PWM timer compare
values are transferred to the GPT320.GTCCRC and GPT320.GTCCRE registers. The setting for the next PWM timer
period is transferred to the GPT320.GTPBR register.
(10) Interrupt handling
After the specified rounds of data transfer are complete, for example when the value in the CRA register for GPT transfer
becomes 0, a GPT320 counter overflow interrupt request is issued for the CPU. Complete the process for this interrupt in
the handling routine.
18.6.3
Chain Transfer When Counter = 0
The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data
transfer information is repeatedly changed in the second transfer. Chain transfer enables transfers to be repeated 256
times or more.
The following procedure shows an example of configuring a 128-KB input buffer, where the input buffer is set so that its
lower address starts with 0000h. Figure 18.14 shows a chain transfer when the counter = 0.
1. Set the normal transfer mode to input data for the first data transfer. Set the following:
a. Transfer source address = fixed.
b. CRA register = 0000h (65,536) times.
c. MRB.CHNE bit = 1 (chain transfer is enabled).
d. MRB.CHNS bit = 1 (chain transfer is performed only when the transfer counter is 0).
e. MRB.DISEL bit = 0 (an interrupt request to the CPU is generated when the specified data transfer completes).
2. Prepare the upper 8-bit address of the start address at every 65,536 times of the transfer destination address for the
first data transfer in a different area such as the flash. For example, when setting the input buffer to 20 0000h to
21 FFFFh, prepare 21h and 20h.
3. For the second data transfer:
a. Set the repeat transfer mode (with the source as the repeat area) to reset the transfer destination address of the
first data transfer.
b. Specify the upper 8 bits of the DAR register in the first transfer information area for the transfer destination.
c. Set the MRB.CHNE bit = 0 (chain transfer is disabled).
d. Set the MRB.DISEL bit = 0 (an interrupt request to the CPU is generated when the specified data transfer
completes).
e. When setting the input buffer to 20 0000h to 21 FFFFh, also set the transfer counter to 2.
4. The first data transfer is performed by an interrupt 65,536 times. When the transfer counter of the first data transfer
becomes 0, the second data transfer starts. Set the upper 8 bits of the transfer source address of the first data transfer
to 21h. The lower 16 bits of the transfer destination address and the transfer counter of the first data transfer have
become 0000h.
5. In succession, the first data transfer is performed by an interrupt 65,536 times as specified for the first data transfer.
When the transfer counter of the first data transfer becomes 0, the second data transfer starts. Set the upper 8 bits of
the transfer source address of the first data transfer to 20h. The lower 16 bits of the transfer destination address and
the transfer counter of the first data transfer have become 0000h.
6. Steps 4 and 5 are repeated indefinitely. Because the second data transfer is in repeat transfer mode, no interrupt
request to the CPU is generated.
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18. Data Transfer Controller (DTC)
Input circuit
Transfer information allocated in
the on-chip memory space
Input buffer
First data transfer
Transfer information
Chain transfer
(counter = 0)
Second data transfer
Transfer information
Upper 8 bits of DAR
Figure 18.14
18.7
Chain transfer when counter = 0
Interrupt Sources
When the DTC finishes data transfer of the specified count or when data transfer with the MRB.DISEL bit set to 1 is
complete, a DTC activation source generates an interrupt to the CPU. Interrupts to the CPU are controlled according to
the settings in the NVIC and ICU.IELSRn.IELS[7:0]. See section 14, Interrupt Controller Unit (ICU).
The DTC prioritizes activation sources by granting the smaller interrupt vector numbers higher priority. The priority of
interrupts to the CPU is determined by the NVIC priority.
18.8
Event Link
The DTC is capable of producing an event link request on completion of one transfer request. When the destination for
the transfer is an external bus, the event link request is issued after completion of writing to the write buffer rather than
after completion of writing to the actual transfer destination.
18.9
Snooze Control Interface
To return to Software Standby mode from Snooze mode through the DTC, set SYSTEM.SNZEDCR.DTCZRED or
SYSTEM.SNZEDCR.DTCNZRED to 1. See section 11.8.3, Returning to Software Standby Mode.
SYSTEM.SNZEDCR.DTCZRED enables or disables a Snooze end request on completion of the last DTC transmission,
detected on DTC transmission completion when CRA and CRB are 0.
SYSTEM.SNZEDCR.DTCNZRED enables or disables a Snooze end request on a not last DTC transmission completion,
detected on DTC transmission completion when CRA and CRB are not 0.
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18. Data Transfer Controller (DTC)
18.10 Module-Stop Function
Before transitioning to the module-stop function, Software Standby mode without Snooze mode transition, set the
DTCST.DTCST bit to 0, and then perform the operations described in the following sections. The DTC is available in
Snooze mode by setting SYSTEM.SNZCR.SNZDTCEN to 1. See section 11, Low Power Modes.
(1)
Module-stop function
Writing 1 to the MSTPCRA.MSTPA22 bit enables the module-stop function of the DTC. If the DTC transfer is in
progress at the time 1 is written to the MSTPCRA.MSTPA22 bit, the transition to the module-stop state proceeds after
DTC transfer ends. While the MSTPCRA.MSTPA22 bit is 1, accessing the DTC registers is prohibited.
Writing 0 to the MSTPCRA.MSTPA22 bit releases the DTC from the module-stop state.
(2)
Software Standby mode
Use the settings described in section 11.7.1, Transition to Software Standby Mode.
If DTC transfer operations are in progress when the WFI instruction is executed, the transition to Software Standby mode
follows the completion of the DTC transfer.
When the Snooze control circuit receives a Snooze request in Software Standby mode, the MCU transfers to Snooze
mode. See section 11.8.1, Transition to Snooze Mode. DTC operation in Snooze mode can be selected in the
SYSTEM.SNZCR.SNZDTCEN bit. If DTC operation is enabled in Snooze mode, before transitioning to Software
Standby mode, set the DTCST.DTCST bit to 1. To return to Software Standby mode through the DTC, set the
SYSTEM.SNZEDCR.DTCZRED or SYSTEM.SNZEDCR.DTCNZRED to 1. See section 11.8.3, Returning to Software
Standby Mode. The DTC activation request from the ICU is stopped during Software Standby mode but not during
Snooze mode.
(3)
Notes on module-stop function
For the WFI instruction and the register setting procedure, see section 11, Low Power Modes.
To perform a DTC transfer after returning from a low power mode without Snooze mode transition, set the
DTCST.DTCST bit to 1 again.
To use a request that is generated in Software Standby mode as an interrupt request to the CPU but not as a DTC
activation request, specify the CPU as the interrupt request destination as described in section 14.4.2, Selecting Interrupt
Request Destinations, and then execute a WFI instruction. If DTC operation is enabled in Snooze mode, do not use the
module-stop function of the DTC.
18.11 Usage Notes
18.11.1
Transfer Information Start Address
You must set multiples of 4 for the transfer information start addresses in the vector table. Otherwise, such addresses are
accessed with their lowest 2 bits regarded as 00b.
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19. Event Link Controller (ELC)
19.
Event Link Controller (ELC)
19.1
Overview
The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to
connect them to different modules, allowing direct link between the modules without CPU intervention.
Table 19.1 lists the ELC specifications and Figure 19.1 shows a block diagram.
Table 19.1
ELC specifications
Item
Description
Event link function
179 types of event signals can be directly connected to modules.The ELC can generate an
ELC event signal, and events that activate the DTC.
Module-stop function
Module-stop state can be set to reduce power consumption
Internal peripheral bus
ELC
ELSEGR0, 1
ELCR
ELSRn
DTC
Event control
PORT_IRQn
(n = 0 to 15)
GPT
DMAC
ADC14
DTC
DAC12
LVD
Port 1/2/3/4
SYSTEM_SNZREQ
CTSU
MOSC_STOP
Peripheral module
Port 1/2/3/4
ELSEGR0,1:
ELCR:
ELSRn:
Figure 19.1
19.2
Event Link Software Event Generation Register
Event Link Control Register
Event Link Setting Register n
ELC block diagram (n = 0 to 9, 12, 14 to 18)
Register Descriptions
19.2.1
Event Link Controller Register (ELCR)
Address(es): ELC.ELCR 4004 1000h
b7
b6
b5
b4
b3
b2
b1
b0
ELCON
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
ELCON
All Event Link Enable
0: Disable ELC function
1: Enable ELC function.
R/W
The ELCR register controls the ELC operation.
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19.2.2
19. Event Link Controller (ELC)
Event Link Software Event Generation Register n (ELSEGRn) (n = 0, 1)
Address(es): ELC.ELSEGR0 4004 1002h, ELC.ELSEGR1 4004 1004h
b7
b6
b5
b4
b3
b2
b1
b0
WI
WE
—
—
—
—
—
SEG
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
SEG
Software Event Generation
0: Normal operation
1: Software event is generated.
W
b5 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
WE
SEG Bit Write Enable
0: Disable write to SEG bit
1: Enable write to SEG bit.
R/W
b7
WI
ELSEGR Register Write Disable
0: Enable write to ELSEGR register
1: Disable write to ELSEGR register.
W
SEG bit (Software Event Generation)
When 1 is written to the SEG bit while the WE bit is 1, a software event is generated. This bit is read as 0. Even when 1
is written to this bit, data is not stored. The WE bit must be set to 1 before writing to this bit.
A software event can trigger a linked DTC event.
WE bit (SEG Bit Write Enable)
The SEG bit can only be written to when the WE bit is 1. Clear the WI bit to 0 before writing to this bit.
[Setting condition]
If 1 is written to this bit while the WI bit is 0, this bit becomes 1.
[Clearing condition]
If 0 is written to this bit while the WI bit is 0, this bit becomes 0.
WI bit (ELSEGR Register Write Disable)
The ELSEGR register can only be written to when the write value to the WI bit is 0. This bit is read as 1. Before setting
the WE or SEG bit, the WI bit must be set to 0.
19.2.3
Event Link Setting Register n (ELSRn) (n = 0 to 9, 12, 14 to 18)
Address(es): ELC.ELSR0 4004 1010h, ELC.ELSR1 4004 1014h, ELC.ELSR2 4004 1018h, ELC.ELSR3 4004 101Ch, ELC.ELSR4 4004 1020h,
ELC.ELSR5 4004 1024h, ELC.ELSR6 4004 1028h, ELC.ELSR7 4004 102Ch, ELC.ELSR8 4004 1030h, ELC.ELSR9 4004 1034h,
ELC.ELSR12 4004 1040h, ELC.ELSR14 4004 1048h, ELC.ELSR15 4004 104Ch, ELC.ELSR16 4004 1050h, ELC.ELSR17 4004 1054h,
ELC.ELSR18 4004 1058h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
ELS[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
ELS[7:0]
Event Link Select
b7
R/W
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b0
00000000:
Event output disabled for the associated
peripheral module
00000001 to 11010100:
Number setting for the event signal to be
linked.
Other settings are prohibited.
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19. Event Link Controller (ELC)
Bit
Symbol
Bit name
Description
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The ELSRn register specifies an event signal to be linked to each peripheral module. Table 19.2 shows the association
between the ELSRn registers and the peripheral modules. Table 19.3 shows the association between the event signal
names set in the ELSRn registers and the signal numbers.
Table 19.2
Association between the ELSRn registers and peripheral functions
Register name
Peripheral function (module)
Event name
ELSR0
GPT (A)
ELC_GPTA
ELSR1
GPT (B)
ELC_GPTB
ELSR2
GPT (C)
ELC_GPTC
ELSR3
GPT (D)
ELC_GPTD
ELSR4
GPT (E)
ELC_GPTE
ELSR5
GPT (F)
ELC_GPTF
ELSR6
GPT (G)
ELC_GPTG
ELSR7
GPT (H)
ELC_GPTH
ELSR8
ADC14A
ELC_AD00
ELSR9
ADC14B
ELC_AD01
ELSR12
DAC12
ELC_DA0
ELSR14
PORT 1
ELC_PORT1
ELSR15
PORT 2
ELC_PORT2
ELSR16
PORT 3
ELC_PORT3
ELSR17
PORT 4
ELC_PORT4
ELSR18
CTSU
ELC_CTSU
Table 19.3
Event number
Association between event signal names set in ELSRn.ELS bits and signal numbers (1 of 5)
Interrupt request source
Name
Description
Port
PORT_IRQ0*1
External pin interrupt 0
002h
PORT_IRQ1*1
External pin interrupt 1
003h
PORT_IRQ2*1
External pin interrupt 2
004h
PORT_IRQ3*1
External pin interrupt 3
005h
PORT_IRQ4*1
External pin interrupt 4
006h
PORT_IRQ5*1
External pin interrupt 5
007h
PORT_IRQ6*1
External pin interrupt 6
008h
PORT_IRQ7*1
External pin interrupt 7
009h
PORT_IRQ8*1
External pin interrupt 8
00Ah
PORT_IRQ9*1
External pin interrupt 9
00Bh
PORT_IRQ10*1
External pin interrupt 10
00Ch
PORT_IRQ11*1
External pin interrupt 11
00Dh
PORT_IRQ12*1
External pin interrupt 12
00Eh
PORT_IRQ13*1
External pin interrupt 13
00Fh
PORT_IRQ14*1
External pin interrupt 14
010h
PORT_IRQ15*1
External pin interrupt 15
001h
011h
DMAC0
DMAC0_INT
DMAC transfer end 0
012h
DMAC1
DMAC1_INT
DMAC transfer end 1
013h
DMAC2
DMAC2_INT
DMAC transfer end 2
014h
DMAC3
DMAC3_INT
DMAC transfer end 3
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Table 19.3
Event number
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (2 of 5)
Interrupt request source
Name
Description
016h
DTC
DTC_DTCEND*3
DTC transfer end
019h
LVD
LVD_LVD1
Voltage monitor 1 interrupt
LVD_LVD2
Voltage monitor 2 interrupt
MOSC
MOSC_STOP
Main clock oscillation stop
01Dh
Low power mode
SYSTEM_SNZREQ*2, *3
Snooze entry
01Eh
AGT0
AGT0_AGTI
AGT interrupt
AGT0_AGTCMAI
Compare match A
01Ah
01Ch
01Fh
020h
021h
AGT1
022h
023h
AGT0_AGTCMBI
Compare match B
AGT1_AGTI
AGT interrupt
AGT1_AGTCMAI
Compare match A
AGT1_AGTCMBI
Compare match B
024h
IWDT
IWDT_NMIUNDF
IWDT underflow
025h
WDT
WDT_NMIUNDF
WDT underflow
027h
RTC
RTC_PRD
Periodic interrupt
029h
ADC140
ADC140_ADI
A/D scan end interrupt
02Dh
ADC140_WCMPM*3
Compare match
02Eh
ADC140_WCMPUM*3
Compare mismatch
ACMP_LP0
Low-power analog comparator interrupt 0
ACMP_LP1
Low-power analog comparator interrupt 1
IIC0_RXI
Receive data full
036h
IIC0_TXI
Transmit data empty
037h
IIC0_TEI
Transmit end
038h
IIC0_EEI
Transfer error
IIC1_RXI
Receive data full
03Bh
IIC1_TXI
Transmit data empty
03Ch
IIC1_TEI
Transmit end
03Dh
IIC1_EEI
Transfer error
02Fh
ACMPLP
030h
035h
03Ah
03Eh
IIC0
IIC1
IIC2_RXI
Receive data full
03Fh
IIC2
IIC2_TXI
Transmit data empty
040h
IIC2_TEI
Transmit end
IIC2_EEI
Transfer error
DOC_DOPCI*3
Data operation circuit interrupt
041h
04Ah
DOC
053h
I/O port
IOPORT_GROUP1
Port 1 event
054h
IOPORT_GROUP2
Port 2 event
055h
IOPORT_GROUP3
Port 3 event
056h
057h
ELC
058h
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IOPORT_GROUP4
Port 4 event
ELC_SWEVT0
Software event 0
ELC_SWEVT1
Software event 1
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Table 19.3
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (3 of 5)
Event number
Interrupt request source
Name
Description
05Bh
GPT320
GPT0_CCMPA
Compare match A
05Ch
GPT0_CCMPB
Compare match B
05Dh
GPT0_CMPC
Compare match C
05Eh
GPT0_CMPD
Compare match D
05Fh
GPT0_CMPE
Compare match E
060h
GPT0_CMPF
Compare match F
061h
GPT0_OVF
Overflow
GPT0_UDF
Underflow
GPT1_CCMPA
Compare match A
064h
GPT1_CCMPB
Compare match B
065h
GPT1_CMPC
Compare match C
066h
GPT1_CMPD
Compare match D
067h
GPT1_CMPE
Compare match E
068h
GPT1_CMPF
Compare match F
069h
GPT1_OVF
Overflow
GPT1_UDF
Underflow
GPT2_CCMPA
Compare match A
GPT2_CCMPB
Compare match B
062h
063h
GPT321
06Ah
06Bh
GPT322
06Ch
06Dh
GPT2_CMPC
Compare match C
06Eh
GPT2_CMPD
Compare match D
06Fh
GPT2_CMPE
Compare match E
070h
GPT2_CMPF
Compare match F
071h
GPT2_OVF
Overflow
072h
GPT2_UDF
Underflow
073h
GPT3_CCMPA
Compare match A
074h
GPT323
GPT3_CCMPB
Compare match B
075h
GPT3_CMPC
Compare match C
076h
GPT3_CMPD
Compare match D
077h
GPT3_CMPE
Compare match E
078h
GPT3_CMPF
Compare match F
079h
GPT3_OVF
Overflow
07Ah
GPT3_UDF
Underflow
07Bh
GPT4_CCMPA
Compare match A
07Ch
GPT164
GPT4_CCMPB
Compare match B
07Dh
GPT4_CMPC
Compare match C
07Eh
GPT4_CMPD
Compare match D
07Fh
GPT4_CMPE
Compare match E
080h
GPT4_CMPF
Compare match F
081h
GPT4_OVF
Overflow
082h
GPT4_UDF
Underflow
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Table 19.3
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (4 of 5)
Event number
Interrupt request source
Name
Description
083h
GPT165
GPT5_CCMPA
Compare match A
084h
GPT5_CCMPB
Compare match B
085h
GPT5_CMPC
Compare match C
086h
GPT5_CMPD
Compare match D
087h
GPT5_CMPE
Compare match E
088h
GPT5_CMPF
Compare match F
089h
GPT5_OVF
Overflow
GPT5_UDF
Underflow
GPT6_CCMPA
Compare match A
GPT6_CCMPB
Compare match B
08Ah
08Bh
GPT166
08Ch
08Dh
GPT6_CMPC
Compare match C
08Eh
GPT6_CMPD
Compare match D
08Fh
GPT6_CMPE
Compare match E
090h
GPT6_CMPF
Compare match F
091h
GPT6_OVF
Overflow
GPT6_UDF
Underflow
GPT7_CCMPA
Compare match A
094h
GPT7_CCMPB
Compare match B
095h
GPT7_CMPC
Compare match C
096h
GPT7_CMPD
Compare match D
097h
GPT7_CMPE
Compare match E
098h
GPT7_CMPF
Compare match F
099h
GPT7_OVF
Overflow
09Ah
GPT7_UDF
Underflow
092h
093h
09Bh
GPT167
GPT8_CCMPA
Compare match A
09Ch
GPT8_CCMPB
Compare match B
09Dh
GPT8_CMPC
Compare match C
09Eh
GPT8_CMPD
Compare match D
09Fh
GPT8_CMPE
Compare match E
0A0h
GPT8_CMPF
Compare match F
0A1h
GPT8_OVF
Overflow
0A2h
GPT8_UDF
Underflow
0A3h
GPT168
GPT9_CCMPA
Compare match A
0A4h
GPT9_CCMPB
Compare match B
0A5h
GPT9_CMPC
Compare match C
0A6h
GPT9_CMPD
Compare match D
0A7h
GPT9_CMPE
Compare match E
0A8h
GPT9_CMPF
Compare match F
0A9h
GPT9_OVF
Overflow
0AAh
GPT9_UDF
Underflow
GPT_UVWEDGE
UVW edge event
0ABh
GPT169
GPT
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Table 19.3
Event number
0ACh
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (5 of 5)
Interrupt request source
Name
Description
SCI0
SCI0_RXI*4
Receive data full
0ADh
SCI0_TXI*4
Transmit data empty
0AEh
SCI0_TEI
Transmit end
0AFh
SCI0_ERI*4
Receive error
0B0h
SCI0_AM
Address match event
SCI1_RXI*4
Receive data full
0B3h
SCI1_TXI*4
Transmit data empty
0B4h
SCI1_TEI
Transmit end
0B5h
SCI1_ERI*4
Receive error
0B6h
SCI1_AM
Address match event
0B7h
SCI2_RXI*4
Receive data full
SCI2_TXI*4
Transmit data empty
0B9h
SCI2_TEI
Transmit end
0BAh
SCI2_ERI*4
Receive error
0BBh
SCI2_AM
Address match event
0BCh
SCI3_RXI*4
Receive data full
0BDh
SCI3_TXI*4
Transmit data empty
0BEh
SCI3_TEI
Transmit end
0BFh
SCI3_ERI*4
Receive error
0C0h
SCI3_AM
Address match event
SCI4_RXI*4
Receive data full
0B2h
SCI1
SCI2
0B8h
0C1h
SCI3
SCI4
0C2h
SCI4_TXI*4
Transmit data empty
0C3h
SCI4_TEI
Transmit end
0C4h
SCI4_ERI*4
Receive error
SCI4_AM
Address match event
SCI9_RXI*4
Receive data full
0C7h
SCI9_TXI*4
Transmit data empty
0C8h
SCI9_TEI
Transmit end
0C9h
SCI9_ERI*4
Receive error
0CAh
SCI9_AM
Address match event
0C5h
0C6h
0CBh
SCI9
SPI0_SPRI
Receive buffer full
0CCh
SPI0_SPTI
Transmit buffer empty
0CDh
SPI0_SPII
Idle
0CEh
SPI0_SPEI
Error
0CFh
SPI0_SPTEND
Transmission completed event
0D0h
SPI0
SPI1_SPRI
Receive buffer full
0D1h
SPI1_SPTI
Transmit buffer empty
0D2h
SPI1_SPII
Idle
0D3h
SPI1_SPEI
Error
0D4h
SPI1_SPTEND
Transmission completed event
Note 1.
Note 2.
Note 3.
Note 4.
SPI1
Only pulse (edge detection) is supported.
ELSR8, 9, and ELSR14 to ELSR18 can select this event.
This event can occur in Snooze mode.
This event is not supported in FIFO mode.
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19.3
19. Event Link Controller (ELC)
Operation
19.3.1
Relation between Interrupt Handling and Event Linking
Event number for an event link is the same as that for the associated interrupt source. For information on generating
event signals, see the explanation in the chapter for each event source module.
19.3.2
Linking Events
When an event occurs and that event is already set as a trigger in the Event Link Setting Register (ELSRn), the associated
module is activated. The operation of the module must be set up in advance. Table 19.4 lists the operations of modules
when an event occurs.
Table 19.4
Module operations when event occurs
Module
Operations when event occurs
GPT
ADC14
Starts A/D conversion
DAC12
Starts D/A conversion
I/O ports
Change pin output based on the EORR (reset) or EOSR (set)
Latch pin state to EIDR
The following ports can be used for the ELC:
PORT 1
PORT 2
PORT 3
PORT 4.
CTSU
Starts measurement operation
DTC
Starts DTC data transfer
19.3.3
Start counting
Stop counting
Clear counting
Up counting
Down counting
Input capture.
Example of Procedure for Linking Events
To link events:
1. Set the operation of the module for which an event is to be linked.
2. Set the appropriate ELSRn register for the module to be linked.
3. Set the ELCR.ELCON bit to 1 to enable linkage of all events.
4. Configure the module from which an event is output and activate the module. The link between the two modules is
now active.
5. To stop event linkage of modules individually, set 00000000b in the ELSRn.ELS[7:0] bits associated with the
modules. To stop linkage of all events, set the ELCR.ELCON bit to 0.
If the event link output from the RTC is to be used, set the ELC after the RTC is set, for example, for initialization and
time setting. Unintended events can be generated if the RTC settings are made after the ELC settings.
19.4
19.4.1
Usage Notes
Linking DMAC or DTC Transfer End Signals as Events
When linking the DMAC or DTC transfer end signals as events, do not set the same peripheral module as the DMAC or
DTC transfer destination and event link destination. If set, the peripheral module might be started before DMAC or DTC
transfer to the peripheral module is complete.
19.4.2
Setting Clocks
To link events, you must enable the ELC and the related modules. The modules cannot operate if the related modules are
in the module-stop state or in low power modes in which the module is stopped (Software Standby mode). Some
modules can perform in Snooze mode. For more information, see Table 19.3 and section 11, Low Power Modes.
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19.4.3
19. Event Link Controller (ELC)
Module-Stop Function Setting
ELC operation can be enabled or disabled using the Module Stop Control Register C (MSTPCRC). After a reset, the
ELC is disabled because it is in the module-stop state. The ELCON bit must be set to 0 before disabling ELC operation
using the Module Stop Control Register. For more information, see section 11, Low Power Modes.
19.4.4
ELC Delay Time
As shown in Figure 19.2, module A accesses the module B through ELC. There is a delay time in the ELC module
between module A and module B, called the ELC delay time. The ELC delay time is shown in Table 19.5.
If the clock domains on both module A and B are same, the delay time is 0. But, if the clock domains on modules A and
B are different, ELC module has some delay. The time delay is defined by the slower clock frequency among module A
and module B clocks.
Delay time
Event destination
Event source
Module B
Module A
ELC
Clock = clock_A
Figure 19.2
Table 19.5
Clock = clock_B
ELC delay time
ELC delay time
Clock domain
Clock frequency
ELC delay time
Clock_A = Clock_B
Clock_A = Clock_B
0 cycles
Clock_A ≠ Clock_B
Clock_A = Clock_B
1 cycle to 2 cycles
Clock_A > Clock_B
1 cycle to 2 cycles of B
Clock_A < Clock_B
1 cycle to 2 cycles of A
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20.
I/O Ports
20.1
Overview
20. I/O Ports
The I/O port pins operate as general I/O port pins, I/O pins for peripheral modules, interrupt input pins, analog I/O, port
group function for ELC, or bus control pins. All pins operate as input pins immediately after a reset, and pin functions are
switched by register settings. The I/O ports and peripherals for each pin are specified in the associated registers. Figure
20.1 shows a connection diagram for the I/O port registers. The configuration of the I/O ports differs depending on the
package. Table 20.1 shows the I/O port specifications, and Table 20.2 lists the port functions.
PCR
Peripheral output
enable
1
PDR
0
DSCR1, DSCR, NCODR
Peripheral output
1
0
EOSR
POSR
ELC
Internal peripheral bus
PODR
PORR
EORR
PSEL
PMR
Edge detect
ELC
EOF, EOR
Peripheral input/
interrupt
EIDR
PIDR
Read control
ISEL
ASEL
Analog
input or output
Figure 20.1
Note:
I/O port registers connection diagram
Figure 20.1 shows a basic port configuration. The configuration differs depending on the ports.
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Table 20.1
20. I/O Ports
I/O port specifications
Package
Package
Package
Port
144 pins, 145 pins
Number
of pins
PORT0
P000 to P015
16
P000 to P008,
P010 to P015
15
P000 to P008,
P010 to P015
15
P000 to P004,
P010 to P015
11
PORT1
P100 to P115
16
P100 to P115
16
P100 to P115
16
P100 to P113
14
PORT2
P200 to P206,
P212 to P215
11
P200 to P206,
P212 to P215
11
P200 to P206,
P212 to P215
11
P200, P201,
P204 to P206,
P212 to P215
9
PORT3
P300 to P315
16
P300 to P309,
P313 to P315
13
P300 to P307
8
P300 to P304
5
PORT4
P400 to P415
16
P400 to P415
16
P400 to P415
16
P400 to P402,
P407 to P411
8
PORT5
P500 to P507,
P511, P512
10
P500 to P506,
P511, P512
9
P500 to P505
6
P500 to P502
3
PORT6
P600 to P606,
P608 to P614
14
P600 to P605,
P608 to P613
12
P600 to P603,
P608 to P610
7
N/A
0
PORT7
P700 to P705,
P708 to P713
12
P700 to P702,
P708 to P710
6
P708
1
N/A
0
PORT8
P800 to P809
10
P800, P801,
P808, P809
4
P808, P809
2
N/A
0
PORT9
P900 to P902,
P914, P915
5
P914, P915
2
P914, P915
2
P914, P915
2
Total pins
104
Total pins
84
Total pins
52
Total pins 126
Table 20.2
Port
121 pins
Number
of pins
Package
Number
of pins
100 pins
Number
of pins
64 pins
I/O port functions
Port name
Input pull-up
Open-drain output
Drive capacity switching
5V tolerant
PORT0
P000 to P015
—
Low/Middle
—
PORT1
P100 to P115
Low/Middle
—
PORT2
P200, P214, P215
—
—
—
—
P201 to P204
Low/Middle
—
P205, P206
Low/Middle
P212, P213
—
—
PORT3
P300 to P315
Low/Middle
—
PORT4
P400 to P404, P407
Low/Middle
P405, P406, P409 to P415
Low/Middle
—
P408
Low/Middle/Middle(IIC)
P500 to P507
Low/Middle
—
P511, P512
Low/Middle
PORT6
P600 to P606, P608 to P614
Low/Middle
—
PORT7
P700 to P706, P708 to P713
Low/Middle
—
PORT8
P800 to P809
Low/Middle
—
PORT9
P900 to P902
Low/Middle
—
P914, P915
—
—
—
—
PORT5
: Available
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20.2
20. I/O Ports
Register Descriptions
20.2.1
Port Control Register 1 (PCNTR1/PODR/PDR)
Address(es): PORT0.PCNTR1 4004 0000h, PORT1.PCNTR1 4004 0020h, PORT2.PCNTR1 4004 0040h, PORT3.PCNTR1 4004 0060h,
PORT4.PCNTR1 4004 0080h, PORT5.PCNTR1 4004 00A0h, PORT6.PCNTR1 4004 00C0h, PORT7.PCNTR1 4004 00E0h,
PORT8.PCNTR1 4004 0100h, PORT9.PCNTR1 4004 0120h,
PORT0.PODR 4004 0000h, PORT1.PODR 4004 0020h, PORT2.PODR 4004 0040h, PORT3.PODR 4004 0060h,
PORT4.PODR 4004 0080h, PORT5.PODR 4004 00A0h, PORT6.PODR 4004 00C0h, PORT7.PODR 4004 00E0h,
PORT8.PODR 4004 0100h, PORT9.PODR 4004 0120h,
PORT0.PDR 4004 0002h, PORT1.PDR 4004 0022h, PORT2.PDR 4004 0042h, PORT3.PDR 4004 0062h,
PORT4.PDR 4004 0082h, PORT5.PDR 4004 00A2h, PORT6.PDR 4004 00C2h, PORT7.PDR 4004 00E2h,
PORT8.PDR 4004 0102h, PORT9.PDR 4004 0122h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR
05
04
03
02
01
00
15
14
13
12
11
10
09
08
07
06
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PDR15 PDR14 PDR13 PDR12 PDR11 PDR10 PDR09 PDR08 PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
PDRn
Pmn Direction
0: Input (functions as an input pin)
1: Output (functions as an output pin).
R/W
b31 to b16
PODRn
Pmn Output Data
0: Low output
1: High output.
R/W
m = 0 to 9
n = 00 to 15
The Port Control Register 1 (PCNTR1/PODR/PDR) is a 32-bit and 16-bit read/write register that controls port direction
and port output data.
PCNTR1 specifies the port direction and output data, and is accessed in 32-bit units. PODR (bits [31:16] in PCNTR1)
and PDR (bits [15:0] in PCNTR1) respectively, are accessed in 16-bit units.
The PDRn bits select the input or output direction for individual pins on the associated port when the pins are configured
as general I/O pins. Each pin on port m is associated with a PORTm.PCNTR1.PDRn bit. The I/O direction can be
specified in 1-bit units. The bits associated with non-existent pins are reserved. Reserved bits are read as 0. The write
value should be 0. P200, P214, and P215 are input only, so PORT2.PCNTR1.PDR00, PORT2.PCNTR1.PDR14, and
PORT2.PCNTR1.PDR15 are reserved. The PDRn bits in the PORTm.PCNTR1 register serve the same function as the
PDR bit in the PFS.PmnPFS register.
The PODRn bits hold data to be output from the general I/O pins. The bits associated with non-existent port m are
reserved. Write 0 to these bits. The bits associated with non-existent pins are reserved. P200, P214, P215 are input only,
so PORT2.PCNTR1.PODR00, PORT2.PCNTR1.PODR14, and PORT2.PCNTR1.PODR15 bits are reserved. A reserved
bit is read as 0. The write value should be 0. The PODRn bits in the PORTm.PCNTR1 register serve the same function as
the PODR bit in the PFS.PmnPFS register.
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20.2.2
20. I/O Ports
Port Control Register 2 (PCNTR2/EIDR/PIDR)
Address(es): PORT0.PCNTR2 4004 0004h, PORT1.PCNTR2 4004 0024h, PORT2.PCNTR2 4004 0044h, PORT3.PCNTR2 4004 0064h,
PORT4.PCNTR2 4004 0084h, PORT5.PCNTR2 4004 00A4h, PORT6.PCNTR2 4004 00C4h, PORT7.PCNTR2 4004 00E4h,
PORT8.PCNTR2 4004 0104h, PORT9.PCNTR2 4004 0124h,
PORT1.EIDR 4004 0024h, PORT2.EIDR 4004 0044h, PORT3.EIDR 4004 0064h, PORT4.EIDR 4004 0084h,
PORT0.PIDR 4004 0006h, PORT1.PIDR 4004 0026h, PORT2.PIDR 4004 0046h, PORT3.PIDR 4004 0066h,
PORT4.PIDR 4004 0086h, PORT5.PIDR 4004 00A6h, PORT6.PIDR 4004 00C6h, PORT7.PIDR 4004 00E6h,
PORT8.PIDR 4004 0106h, PORT9.PIDR 4004 0126h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
EIDR15 EIDR14 EIDR13 EIDR12 EIDR11 EIDR10 EIDR09 EIDR08 EIDR07 EIDR06 EIDR05 EIDR04 EIDR03 EIDR02 EIDR01 EIDR00
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIDR15 PIDR14 PIDR13 PIDR12 PIDR11 PIDR10 PIDR09 PIDR08 PIDR07 PIDR06 PIDR05 PIDR04 PIDR03 PIDR02 PIDR01 PIDR00
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b15 to b0
PIDRn
Pmn State
0: Low level
1: High level.
R
b31 to b16
EIDRn
Port Event Input Data*1
When the ELC_PORTx occurs:
0: Low input
1: High input.
R
m = 0 to 9
n = 00 to 15
x = 1 to 4
Note 1.
Supported for PORT1 to PORT4.
The Port Control Register 2 (PCNTR2/EIDR/PIDR) allows read access to the Pmn state and the port event input data by
32-bit and 16-bit access.
The PCNTR2 specifies the Pmn state and the port event input data, and is accessed in 32-bit units. The EIDRn (bits
[31:16] in PCNTR2) and PIDRn (bits [15:0] in PCNTR2) respectively, are accessed in 16-bit units. Bits associated with
non-existent pins are reserved. Reserved bits are read as undefined.
PIDRn reflects the individual pin states of the port, regardless of the values set in PmnPFS.PMR and
PORTm.PCNTR1.PDRn. The PIDRn bit in the PORTm.PCNTR2 register serves the same function as the PIDR bit in the
PFS.PmnPFS register.
A pin state cannot be reflected in PIDRn when one of the following functions is enabled:
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
CS area controller (CSC)
Analog function (ASEL = 1)
Capacitive Touch Sensing Unit (CTSU)
Segment LCD Controller (SLCDC)
USB 2.0 Full-Speed Module (USBFS).
EIDRn latches a pin state when an ELC_PORTx signal occurs. Pin states can only be input to EIDRn when
PmnPFS.PMR = 0 and PORTm.PCNTR1.PDRn = 0. When PmnPFS.ASEL is set to 1, the associated pin state is not
reflected in EIDRn.
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20.2.3
20. I/O Ports
Port Control Register 3 (PCNTR3/PORR/POSR)
Address(es): PORT0.PCNTR3 4004 0008h, PORT1.PCNTR3 4004 0028h, PORT2.PCNTR3 4004 0048h, PORT3.PCNTR3 4004 0068h,
PORT4.PCNTR3 4004 0088h, PORT5.PCNTR3 4004 00A8h, PORT6.PCNTR3 4004 00C8h, PORT7.PCNTR3 4004 00E8h,
PORT8.PCNTR3 4004 0108h, PORT9.PCNTR3 4004 0128h,
PORT0.PORR 4004 0008h, PORT1.PORR 4004 0028h, PORT2.PORR 4004 0048h, PORT3.PORR 4004 0068h,
PORT4.PORR 4004 0088h, PORT5.PORR 4004 00A8h, PORT6.PORR 4004 00C8h, PORT7.PORR 4004 00E8h,
PORT8.PORR 4004 0108h, PORT9.PORR 4004 0128h,
PORT0.POSR 4004 000Ah, PORT1.POSR 4004 002Ah, PORT2.POSR 4004 004Ah, PORT3.POSR 4004 006Ah,
PORT4.POSR 4004 008Ah, PORT5.POSR 4004 00AAh, PORT6.POSR 4004 00CAh, PORT7.POSR 4004 00EAh,
PORT8.POSR 4004 010Ah, PORT9.POSR 4004 012Ah
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR
05
04
03
02
01
00
15
14
13
12
11
10
09
08
07
06
Value after reset:
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
POSR
15
POSR
14
POSR
13
POSR
12
POSR
11
POSR
10
POSR
09
POSR
08
POSR
07
POSR
06
POSR
05
POSR
04
POSR
03
POSR
02
POSR
01
POSR
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
POSRn
Pmn Output Set
0: No affect to output
1: High output.
W
b31 to b16
PORRn
Pmn Output Reset
0: No affect to output
1: Low output.
W
m = 0 to 9
n = 00 to 15
Note:
Note:
When EORRn or EOSRn is set, writing is prohibited to PODRn, PORRn, and POSRn.
PORRn and POSRn should not be set at the same time.
The Port Control Register 3 (PCNTR3/PORR/POSR) is a 32-bit and 16-bit write register that controls the setting or
resetting of the port output data.
The PCNTR3 controls the setting or resetting of the port output data, which is set by 32-bit units.
The PORR (bits [31:16] in PCNTR3) and POSR (bits [15:0] in PCNTR3) respectively, are accessed in 16-bit units.
POSR changes PODR when set by a software write. For example, for P100, when PORT1.POSR00 = 1,
PORT1.PODR00 outputs 1. Bits associated with non-existent pins are reserved. The write value must always be 0. P200,
P214, and P215 are input only, so PORT2.PCNTR3.POSR00, PORT2.PCNTR3.POSR14, and
PORT2.PCNTR3.POSR15 are reserved.
PORR changes PODR when reset by a software write. For example, for P100, when PORT1.PORR00 = 1,
PORT1.PODR00 outputs 0. Bits associated with non-existent pins are reserved. The write value should always be 0.
P200, P214, and P215 are input only, so PORT2.PCNTR3.PORR00, PORT2.PCNTR3.PORR14, and
PORT2.PCNTR3.PORR15 are reserved.
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20.2.4
20. I/O Ports
Port Control Register 4 (PCNTR4/EORR/EOSR)
Address(es): PORT1.PCNTR4 4004 002Ch, PORT2.PCNTR4 4004 004Ch, PORT3.PCNTR4 4004 006Ch, PORT4.PCNTR4 4004 008Ch,
PORT1.EORR 4004 002Ch, PORT2.EORR 4004 004Ch, PORT3.EORR 4004 006Ch, PORT4.EORR 4004 008Ch,
PORT1.EOSR 4004 002Eh, PORT2.EOSR 4004 004Eh, PORT3.EOSR 4004 006Eh, PORT4.EOSR 4004 008Eh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Value after reset:
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
EOSR
15
EOSR
14
EOSR
13
EOSR
12
EOSR
11
EOSR
10
EOSR
09
EOSR
08
EOSR
07
EOSR
06
EOSR
05
EOSR
04
EOSR
03
EOSR
02
EOSR
01
EOSR
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
EOSRn
Pmn Event Output Set
When the ELC_PORTx occurs:
0: No affect on output
1: High output.
R/W
b31 to b16
EORRn
Pmn Event Output Reset
When the ELC_PORTx occurs:
0: No affect on output
1: Low output.
R/W
m = 1 to 4
n = 00 to 15
x = 1 to 4
Note:
Note:
When EORRn or EOSRn is set, writing is prohibited to PODRn, PORRn, and POSRn.
EORRn and EOSRn should not be set at the same time.
The Port Control Register 4 is a 32-bit and 16-bit read/write register that controls the setting or resetting of the port
output data by an event input from the ELC.
The PCNTR4 controls the setting or resetting of the port output data by an event input from the ELC, which is set by 32bit units.
The EORR (bits [31:16] in PCNTR4) and EOSR (bits [15:0] in PCNTR4) are accessed in 16-bit units.
EOSR changes PODR when set because an ELC_PORTx signal occurs. For example, for P100, if PORT1.EOSR00 is set
to 1 when ELC_PORTx occurs, PORT1.PODR00 outputs 1. Bits associated with non-existent pins are reserved. The
write value must always be 0. P200, P214, and P215 are input only, so PORT2.PCNTR3.EOSR00,
PORT2.PCNTR3.EOSR14, and PORT2.PCNTR3.EOSR15 are reserved.
EORR changes PODR when reset because an ELC_PORTx signal occurs. For example, for P100 if PORT1.EORR00 is
set to 1 when ELC_PORTx occurs, PORT1.PODR00 outputs 0. Bits associated with non-existent pins are reserved. The
write value must always be 0. P200, P214, and P215 are input only, so PORT2.PCNTR4.EORR00,
PORT2.PCNTR4.EORR14, and PORT2.PCNTR4.EORR15 bits are reserved.
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20.2.5
20. I/O Ports
Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY)
(m = 0 to 9; n = 00 to 15)
Address(es): PFS.P000PFS 4004 0800h to PFS.P015PFS 4004 083Ch, PFS.P100PFS 4004 0840h to PFS.P115PFS 4004 087Ch,
PFS.P200PFS 4004 0880h to PFS.P206PFS 4004 0898h, PFS.P212PFS 4004 08B0h to PFS.P215PFS 4004 08BCh,
PFS.P300PFS 4004 08C0h to PFS.P315PFS 4004 08FCh, PFS.P400PFS 4004 0900h to PFS.P415PFS 4004 093Ch,
PFS.P500PFS 4004 0940h to PFS.P507PFS 4004 095Ch, PFS.P511PFS 4004 096Ch, PFS.P512PFS 4004 0970h,
PFS.P600PFS 4004 0980h to PFS.P606PFS 4004 0998h, PFS.P608PFS 4004 09A0h to PFS.P614PFS 4004 09B8h,
PFS.P700PFS 4004 09C0h to PFS.P705PFS 4004 09D4h, PFS.P708PFS 4004 09E0h to PFS.P713PFS 4004 09F4h,
PFS.P800PFS 4004 0A00h to PFS.P809PFS 4004 0A24h, PFS.P900PFS 4004 0A40h to PFS.P902PFS 4004 0A48h
PFS.P914PFS 4004 0A78h, PFS.P915PFS 4004 0A7Ch,
PFS.P000PFS_HA 4004 0802h to PFS.P015PFS_HA 4004 083Eh, PFS.P100PFS_HA 4004 0842h to PFS.P115PFS_HA 4004 087Eh,
PFS.P200PFS_HA 4004 0882h to PFS.P206PFS_HA 4004 089Ah, PFS.P212PFS_HA 4004 08B2h to PFS.P215PFS_HA 4004 08BEh,
PFS.P300PFS_HA 4004 08C2h to PFS.P315PFS_HA 4004 08FEh, PFS.P400PFS_HA 4004 0902h to PFS.P415PFS_HA 4004 093Eh,
PFS.P500PFS_HA 4004 0942h to PFS.P507PFS_HA 4004 095Eh, PFS.P511PFS_HA 4004 096Eh, PFS.P512PFS_HA 4004 0972h,
PFS.P600PFS_HA 4004 0982h to PFS.P606PFS_HA 4004 099Ah, PFS.P608PFS_HA 4004 09A2h to PFS.P614PFS_HA 4004 09BAh,
PFS.P700PFS_HA 4004 09C2h to PFS.P705PFS_HA 4004 09D6h, PFS.P708PFS_HA 4004 09E2h to PFS.P713PFS_HA 4004 09F6h,
PFS.P800PFS_HA 4004 0A02h to PFS.P809PFS_HA 4004 0A26h, PFS.P900PFS_HA 4004 0A42h to PFS.P902PFS_HA 4004 0A4Ah,
PFS.P914PFS_HA 4004 0A7Ah, PFS.P915PFS_HA 4004 0A7Eh,
PFS.P000PFS_BY 4004 0803h to PFS.P015PFS_BY 4004 083Fh, PFS.P100PFS_BY 4004 0843h to PFS.P115PFS_BY 4004 087Fh,
PFS.P200PFS_BY 4004 0883h to PFS.P206PFS_BY 4004 089Bh, PFS.P212PFS_BY 4004 08B3h to PFS.P215PFS_BY 4004 08BFh,
PFS.P300PFS_BY 4004 08C3h to PFS.P315PFS_BY 4004 08FFh, PFS.P400PFS_BY 4004 0903h to PFS.P415PFS_BY 4004 093Fh,
PFS.P500PFS_BY 4004 0943h to PFS.P507PFS_BY 4004 095Fh, PFS.P511PFS_BY 4004 096Fh to PFS.P512PFS_BY 4004 0973h,
PFS.P600PFS_BY 4004 0983h to PFS.P606PFS_BY 4004 099Bh,PFS.P608PFS_BY 4004 09A3h to PFS.P614PFS_BY 4004 09BBh,
PFS.P700PFS_BY 4004 09C3h to PFS.P705PFS_BY 4004 09D7h, PFS.P708PFS_BY 4004 09E3h to PFS.P713PFS_BY 4004 09F7h,
PFS.P800PFS_BY 4004 0A03h to PFS.P809PFS_BY 4004 0A27h, PFS.P900PFS_BY 4004 0A43h to PFS.P902PFS_BY 4004 0A4Bh,
PFS.P914PFS_BY 4004 0A7Bh to PFS.P915PFS_BY 4004 0A7Fh
b31
b30
b29
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
ASEL
ISEL
EOF
EOR
0
0
0
0
Value after reset:
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
PMR
0
0
0
0
0
0
0
0
0*2
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
NCOD
R
—
PCR
—
PDR
PIDR
PODR
0
0
0
0
0
0*2
0
0
x
0
PSEL[4:0]
DSCR1 DSCR
0
0*2
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
PODR
Port Output Data
0: Low output
1: High output.
R/W
b1
PIDR
Pmn State
0: Low level
1: High level.
R
b2
PDR
Port Direction
0: Input (functions as an input pin)
1: Output (functions as an output pin).
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
PCR
Pull-up Control
0: Disables input pull-up
1: Enables input pull-up
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
NCODR
N-Channel Open Drain Control
0: CMOS output
1: NMOS open-drain output.
R/W
b9 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
R/W
b11, b10
DSCR1
DSCR
*3 /
Port Drive Capability
b11 b10
0 0: Low drive
0 1: Middle drive
1 0: Middle drive for IIC Fast-mode
1 1: Setting prohibited.
b10
0: Low drive
1: Middle drive.
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20. I/O Ports
Bit
Symbol
Bit name
Description
R/W
b13, b12
EOF/EOR
Event on Falling/Event on
Rising *1
b13 b12
R/W
b14
ISEL
IRQ Input Enable
0: Do not use as an IRQn input pin
1: Use as an IRQn input pin.
R/W
b15
ASEL
Analog Input Enable
0: Do not use as an analog pin
1: Use as an analog pin.
R/W
b16
PMR
Port Mode Control
0: Use as a general I/O pin
1: Use as an I/O port for peripheral functions.
R/W
b23 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28 to b24
PSEL[4:0]
Peripheral Select
Select the peripheral function. For individual pin functions,
see the associated tables in this chapter.
R/W
b31 to b29
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Note 3.
0
0
1
1
0: Don’t care
1: Detect rising edge
0: Detect falling edge
1: Detect both edges.
Supported for PORT1 to PORT4.
The initial value of P108, P109, P110, P201, P300, P914 and P915 is not 0000_0000h.
P108 is 0001_0010h, P109 is 0001_0000h, P110 is 0001_0010h, P201 is 0000_0010h, P300 is 0001_0010h,P914 is
0001_0000h, and P915 is 0001_0000h.
The Port mn Pin Function Select Register (PmnPFS) selects the pin function.
P408 only has DSCR1 bit.
The Port mn Pin Function Select register (PmnPFS/PmnPFS_HA/PmnPFS_BY) is a 32-, 16-, and 8-bit read/write
control register. PmnPFS controls the selection of the port mn function, which is set in 32-bit units. PmnPFS_HA (bits
[15:0] in PmnPFS) is accessed in 16-bit units. PmnPFS_BY (bits [7:0]) is accessed in 8-bit units.
The PDR/PIDR/PODR bits serve the same function as the PCNTR. When these bits are read, the PCNTR value is read.
The PCR bit enables or disables an input pull-up resistor on the individual port pins. When a pin is in the input state with
the associated bit in PmnPFS.PCR set to 1, the pull-up resistor connected to the pin is enabled. When a pin is set as an
external bus pin, a general port output pin, or a peripheral function output pin, the pull-up resistor for the pin is disabled
regardless of the PCR setting. The pull-up resistor is also disabled in the reset state. Bits associated with non-existent
pins are reserved. Reserved bits are read as 0. The write value should be 0.
The NCODR bit specifies the output type for the port pins. Bits associated with non-existent pins are reserved. Reserved
bits are read as 0. The write value should be 0.
The DSCR1 and DSCR bits switch the drive capacity of the port. If the drive capacity of a pin is fixed, the associated bit
is read/write, but the drive capacity cannot be changed. Bits associated with non-existent pins are reserved. Reserved bits
are read as 0. The write value should be 0.
The EOR and EOF bits select the edge detection method for the port group input signal. These bits support rising, falling,
or both edge detections. When the EOR/EOF bits are set to 01b, 10b, or 11b, the input enable of the I/O cell is asserted.
Following that, the event pulse is input from the external pin, and GPIO outputs the event pulse to the ELC. Bits
associated with non-existent pins are reserved. Reserved bits are read as 0. The write value should be 0.
The ISEL bit specifies IRQ input pins. This setting can be used in combination with the peripheral functions, although an
IRQn (external pin interrupt) of the same number must only be enabled for one pin.
The ASEL bit specifies analog pins. When a pin is set to analog pin by this bit:
1. Specify it as a general I/O port in the Port Mode Control bit (PmnPFS.PMR).
2. Disable the pull-up resistor with the Pull-up Control bit (PmnPFS.PCR).
3. Specify input in the Port Direction bit (PmnPFS.PDR). The pin state cannot be read at this point. The PmnPFS
register is protected by the Write-Protect Register (PWPR). Release write-protect before modifying the register.
The ISEL bit for an unspecified IRQn is reserved. The ASEL bit for an unspecified analog input/output is reserved.
The PMR bit specifies the port pin function. Bits associated with non-existent pins are reserved. Reserved bits are read as
0. The write value should be 0.
The PSEL[4:0] bits assign the peripheral function. For details on the peripheral settings for each product, see section
20.6, Peripheral Select Settings for each Product.
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20.2.6
20. I/O Ports
Write-Protect Register (PWPR)
Address(es): PMISC.PWPR 4004 0D03h
b7
b6
B0WI PFSWE
Value after reset:
1
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
PFSWE
PmnPFS Register Write
Enable
0: Writing to the PmnPFS register is disabled
1: Writing to the PmnPFS register is enabled.
R/W
b7
B0WI
PFSWE Bit Write Disable
0: Writing to the PFSWE bit is enabled
1: Writing to the PFSWE bit is disabled.
R/W
PFSWE bit (PmnPFS Register Write Enable)
Writing to the PmnPFS register is enabled only when the PFSWE bit is set to 1. You must first write 0 to the B0WI bit
before setting PFSWE to 1.
B0WI bit (PFSWE Bit Write Disable)
Writing to the PFSWE bit is enabled only when the B0WI bit is set to 0.
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20.3
20.3.1
20. I/O Ports
Operation
General I/O Ports
All pins except P108, P109, P110, P300, P914, and P915 operate as general I/O ports after reset. General I/O ports are
organized as 16 bits per port and can be accessed by port with the Port Control Registers (PCNTRn, where n = 1 to 4), or
by individual pins with the Pin Function Select Registers. For details on these registers, see section 20.2, Register
Descriptions.
Each port has the following bits:
Port Direction bit (PDR), which selects input or output direction
Port Output Data bit (PODR), which holds data for output
Port Input Data bit (PIDR), which indicates the pin states
Event Input Data bit (EIDR), which indicates the pin state when an ELC_PORT1, 2, 3, or 4 signal occurs
Port Output Set bit (POSR), which indicates the output value when a software write occurs
Port Output Reset bit (PORR), which indicates the output value when a software write occurs
Event Output Set bit (EOSR), which indicates the output value when an ELC_PORT1, 2, 3, or 4 signal occurs
Event Output Reset bit (EORR), which indicates the output value when the ELC_PORT1, 2, 3, or 4 signal occurs.
20.3.2
Port Function Select
The following port functions are available for configuring each pin:
I/O configuration — Complementary or open-drain output, pull-up control, and drive strength
General I/O — Port direction, output data setting, and reading input data
Alternate functions — Configured function mapping to the pin.
Each pin is associated with a Pin Function Select Register (PmnPFS), which includes the associated PODR, PIDR, and
PDR bits. In addition, the PmnPFS register includes the following:
PCR: Pull-up resistor control bit that turns the input pull-up MOS on or off
NCODR: N-channel open-drain control bit that selects the output type for each pin
DSCR1, DSCR: Drive capacity control bits that select the drive capacity
EOR: Event on rising bit used to detect rising edges on the port input
EOF: Event on falling bit used to detect falling edges on the port input
ISEL: IRQ input enable bit to specify an IRQ input pin
ASEL: Analog input enable bit to specify an analog pin
PMR: Port mode bit to specify the pin function of each port
PSEL: Port function select bits to select the associated peripheral function.
These configurations can be made by a single-register access to the Pin Function Select Register. For details, see section
20, Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 9; n = 00 to 15).
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20.3.3
20. I/O Ports
Port Group Function for ELC
In the MCU, PORT1 to PORT4 are assigned for the port group function.
20.3.3.1
Behavior when ELC_PORT1, 2, 3, or 4 is input from ELC
The MCU supports two functions when an ELC_PORT1, 2, 3, or 4 signal comes from the ELC.
(1)
Input to EIDR
For the GPI function (PDR = 0 and PMR = 0 in the PmnPFS register), when an ELC_PORT1, 2, 3, or 4 signal comes
from the ELC, the input enable of the I/O cell is asserted, and then the data from the external pins are read into the EIDR
bit.
For the GPO function (PDR = 1) or the peripheral mode (PMR = 1), 0 is input into the EIDR bit from the external pins.
ELC
ELC_PORT1,
2, 3, or 4
EIDR
PAD
en
Figure 20.2
(2)
Event ports input data
Output from PODR by EOSR/EORR
When an ELC_PORT1, 2, 3, or 4 signal occurs, the data is output from the PODR to the external pin based on the EOSR/
EORR bit settings as follows:
If EOSR is set to 1, when an ELC_PORT1, 2, 3, or 4 signal occurs, the PODR register outputs 1 to the external pin.
Otherwise, when EOSR = 0, the PODR value is kept
If 1 is set for the EORR register, when the ELC_PORT1, 2, 3, or 4 occurs, the PODR register outputs 0 to the
external pin.
Otherwise, when EORR = 0, the PODR value is kept.
EOSR
ELC
PODR
PAD
EORR
en
ELC_PORT1, 2, 3, or 4
Figure 20.3
Event ports output data
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20.3.3.2
20. I/O Ports
Behavior when event pulse is output to ELC
To output the event pulse from the external pins to the ELC, set the EOR/EOF bit in the PmnPFS register. For details, see
section 20.2.5, Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 9; n = 00 to 15).
When the EOR/EOF bits are set, the input enable of the I/O cell is asserted.
Data of the external pin is the input. For example, for PORT1, when the data is input from P100 to P115, the data of those
16 pins is organized by OR logic. This data is formed into a one-shot pulse that goes to the ELC. The operation of
PORT2 to PORT4 is the same.
EOR
ELC
EOF
PAD
IOPORT_
GROUP1,
2, 3 or 4
Edge detect
From other PADs
Figure 20.4
20.4
Generation of event pulse
Handling of Unused Pins
Table 20.3, Handling of unused pins shows how to handle unused pins.
Table 20.3
Handling of unused pins
Pin Name
Description
P201/MD
Use as a mode pin
RES
Connect to VCC through a resistor (pulling up)
USB_DP, USB_DM
When both P914PFS.PMR and P915PFS.PMR bits are set to 1, keep these pins open.
When P914PFS.PMR or P915PFS.PMR bit is set to 0, configure it in the same way as port 1 to 9.
P200/NMI
Connect to VCC through a resistor (pulling up)
P212/EXTAL
When the main clock oscillator is not used, set the MOSCCR.MOSTP bit to 1 (general port P212).
When this pin is not used as port P212, configure it in the same way as ports 1 to 9.
P213/XTAL
When the main clock oscillator is not used, set the MOSCCR.MOSTP bit to 1 (general port P213).
When this pin is not used as port P213, configure it in the same way as ports 1 to 9.
When the external clock is input to the EXTAL pin, leave this pin open.
P215/XCIN
When the sub-clock oscillator is not used, set the SOSCCR.SOSTP bit to 1 (general port P215).
When this pin is not used as port P215, configure it in the same way as ports 1 to 9.
P214/XCOUT
When the sub-clock oscillator is not used, set the SOSCCR.SOSTP bit to 1 (general port P214).
When this pin is not used as port P214, configure it in the same way as ports 1 to 9.
P000 to P015
If the direction setting is for input (PCNTR1.PDRn = 0), connect the associated pin to AVCC0 (pulled up)
through a resistor or to AVSS0 (pulled down) through a resistor.*1
P1x to P9x other than
P200, P201 and P212
to P215
If the direction setting is for input (PCNTR1.PDRn = 0), connect the associated pin to VCC (pulled up)
through a resistor or to VSS (pulled down) through a resistor.*1,*2
If the direction setting is for output (PCNTR1.PDRn = 1), release the pin.*1, *3
Note 1.
Note 2.
Note 3.
Clear the PmnPFS.PMR bit, the PmnPFS.ISEL bit, PmnPFS.PCR, and the PmnPFS.ASEL bit to 0.
P108, P110, P300 are recommended to pull up VCC (pulled up) through a resistor, because these pins are input pull-up
enabled from initial value (PmnPFS.PCR=1).
P109 is recommended to be set as an output (PCNTR1.PDRn = 1) as this pin is output from the initial value.
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20.5
20.5.1
20. I/O Ports
Usage Notes
Procedure for Specifying the Pin Functions
To specify the input/output pin functions:
1. Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register.
2. Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register.
3. Clear the Port Mode Control bit (PMR) for the target pin to select the general I/O port.
4. Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register.
5. Set the PMR to 1 as required to switch to the selected input/output function for the pin.
6. Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register.
7. Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register.
20.5.2
Procedure for Using Port Group Input
To use the port group input (PORT1 to PORT4):
1. Set the ELSRx.ELS[7:0] bits to 0000_0000b to ignore unexpected pulses. For more information, see section 19,
Event Link Controller (ELC).
2. Set the EOF/EOR bit of the PmnPFS register to specify the rising, falling, or both edge detections.
3. Execute a dummy read or wait for a short time, for example 100 ns. Ignoring of unexpected pulses depends on the
initial value of the external pin.
4. Set the ELSRx.ELS[8:0] bits to enable the event signals.
20.5.3
Port Output Data Register (PODR) Summary
This register outputs data as follows:
1. Output 0 if PCNTR4.EORR is set to 1 when an ELC_PORT1, 2, 3, or 4 signal occurs.
2. Output 1 if the PCNTR4.EOSR is set to 1 when the ELC_PORT1, 2, 3, or 4 occurs from the ELC.
3. Output 0 if PCNTR3.PORR is set to 1.
4. Output 1 if PCNTR3.POSR is set to 1.
5. Output 0 or 1 because PCNTR1.PODR is set.
6. Output 0 or 1 because PmnPFS.PODR is set.
Numbers in this list correspond to the priority for writing to the PODR. For example, if 1. and number 3. from the list
occur at the same time, the higher priority number 1. is executed.
20.5.4
Notes on Using of Analog Functions
To use an analog function, set the associated bits in both the Port Mode Control bit (PMR) and Port Direction bit (PDR)
to 0 so that the pin acts as a general input port. Next, set the Analog Input Enable bit in the Port mn Pin Function Select
Register (PmnPFS.ASEL) to 1.
20.5.5
I/O Buffer Specification
In case the P402, P403, and P404 pins are configured as outputs or inputs with the internal pull-up resistor, set the
VBTCR1.BPWSWSTP bit to 1 before setting the I/O registers regardless of whether or not the battery backup function is
used. This setting is needed only one time after a power-on reset. Clear the VBTCR1.BPWSWSTP bit to 0 again after
setting registers associated with the battery backup function, when using the battery backup function. The setting flow of
the VBTCR1.BPWSWSTP bit is shown in Figure 12.2.
The P402, P403, and P404 pins can be used as the RTC input pins RTCICn, where n = 0 to 2. When these input pins are
enabled by the VBTICTLR register, the output function of these pins is forced to disable. Therefore, the VBTICTLR
register must be set to 0 to use the port function.
Note:
The VBTICTLR register is not initialized on reset. For more details, see section 12, Battery Backup Function.
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 418 of 1619
S3A1 User’s Manual
20.5.6
20. I/O Ports
Selecting USB_DP and USB_DM Pins
USB_DP and USB_DM pins are shared with P914 and P915 pins, respectively. USB_DP and P914 pins can be set using
the PFS.P914PFS.PMR bit, and USB_DM and P915 pins can be set using the PFS.P915PFS.PMR bit. Table 20.4 shows
the setting values of bits PFS.P914PFS.PMR and PFS.P915PFS.PMR with each selected pin.
Table 20.4
Selecting the USB/PORT pins
PMR bit settings
Pins selected
P914PFS.PMR bit
P915PFS.PMR bit
P914/USB_DP pin
P915/USB_DM pin
0
0
P914
P915
0
1
P914
P915
1
0
P914
P915
1
1
USB_DP
USB_DM
Note:
Note:
Note:
When using P914/USB_DP and P915/USB_DM as GPIO pins (P914 and P915), use the USB registers with their
initial values.
When using P914/USB_DP and P915/USB_DM as USB pins (USB_DP and USB_DM), use the GPIO registers
for P914 and P915 with their initial values.
When using P914/USB_DP and P915/USB_DM as GPIO pins or USB pins, set these pins only after a reset.
20.5.7
Pull-up/Pull-down Setting for P914 and P915 using USBFS/GPIO Function
When P914 and P915 are used as GPIO pins, their operation is affected by the pull-up/pull-down function of the USBFS
registers.
Therefore, before using the GPIO function, disable the pull-up and pull-down control of the USBFS registers using the
SYSCFG.DMRPU, SYSCFG.DPRPU, and SYSCFG.DRPD bits.
20.6
Peripheral Select Settings for each Product
This section provides details on the Pin Function Select configuration by the PmnPFS register. Assigning the same
function to two or more pins simultaneously is prohibited.
Table 20.5
PSEL[4:0] bit
settings
Register settings for input/output pin function (PORT0)
Pin
Function
P000
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
01100b
CTSU
P001
P002
P003
P004
P005
P006
P007
—
—
—
TS21
TS22
—
—
—
ASEL bit
AN000/AMP0+
AN001/AMP0-
AN002/AMP0O AN003/AMP1O AN004/AMP2O AN011/AMP3+
AN012/AMP3-
AN013/AMP3O
ISEL bit
IRQ6
IRQ7
IRQ2
IRQ11
―
―
IRQ3
IRQ10
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
P009
P010
P011
P012
P013
P014
P015
—
—
TS28
PSEL[4:0] bit
settings
Pin
Function
P008
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
01100b
CTSU
—
—
TS30
TS31
—
ASEL bit
AN014
AN015
AN005/
VREFH0/
AMP2-
AN006/
VREFL0/
AMP2+
AN007/VREFH/ AN008/VREFL/ AN009/DA0
AMP1AMP1+
AN010
ISEL bit
IRQ12
IRQ13
IRQ14
IRQ15
―
―
―
IRQ7
PCR bit
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 419 of 1619
S3A1 User’s Manual
PSEL[4:0] bit
settings
20. I/O Ports
Pin
Function
P008
P009
P010
P011
P012
P013
P014
P015
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
Table 20.6
PSEL[4:0] bit
settings
00000b (value
after reset)
Register settings for input/output pin function (PORT1) (1)
Pin
Function
P100
Hi-Z/JTAG/SWD
Hi-Z
P101
P102
P103
P104
P105
P106
P107
―
00001b
AGT
AGTIO0
AGTEE0
AGTO0
―
―
―
―
00010b
GPT
GTETRGA
GTETRGB
GTOWLO
GTOWUP
GTETRGB
GTETRGA
―
―
00011b
GPT
GTIOC5B
GTIOC5A
GTIOC2B
GTIOC2A
GTIOC1B
GTIOC1A
GTIOC8B
GTIOC8A
00100b
SCI
RXD0/MISO0/
SCL0
TXD0/MOSI0/
SDA0
SCK0
CTS0_RTS0/
SS0
RXD0/MISO0/
SCL0
―
―
―
00101b
SCI
SCK1
CTS1_RTS1/
SS1
TXD2/MOSI2/
SDA2
―
―
―
―
―
00110b
SPI
MISOA
MOSIA
RSPCKA
SSLA0
SSLA1
SSLA2
SSLA3
―
00111b
IIC
SCL1
SDA1
―
―
―
―
―
―
01000b
KINT
KR00
KR01
KR02
KR03
KR04
KR05
KR06
KR07
01001b
CLKOUT/
ACMPLP/RTC
―
―
―
―
―
―
―
―
01010b
CAC/ADC14
―
―
ADTRG0
―
―
―
―
―
01011b
BUS
D00
D01
D02
D03
D04
D05
D06
D07
01100b
CTSU
―
―
―
―
TS13
TS34
―
―
01101b
SLCDC
VL1
VL2
VL3
VL4
COM0
COM1
COM2
COM3
10000h
CAN
―
―
CRX0
CTX0
―
―
―
―
10010b
SSIE
―
―
―
―
―
―
―
―
ASEL bit
AN022/
CMPIN0
AN021/
CMPREF0
AN020/
CMPIN1
AN019/
CMPREF1
―
―
―
―
ISEL bit
IRQ2
IRQ1
―
―
IRQ1
IRQ0
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 420 of 1619
S3A1 User’s Manual
Table 20.7
PSEL[4:0] bit
settings
00000b (value
after reset)
20. I/O Ports
Register settings for input/output pin function (PORT1) (2)
Pin
Function
P108
P109
P110
P111
Hi-Z/JTAG/SWD
TMS/SWDIO
TDO/
TRACESWO
TDI
Hi-Z
P112
P113
P114
P115
00001b
AGT
―
―
―
―
―
―
―
―
00010b
GPT
GTOULO
GTOVUP
GTOVLO
―
―
―
―
―
00011b
GPT
GTIOC0B
GTIOC1A
GTIOC1B
GTIOC3A
GTIOC3B
GTIOC2A
GTIOC2B
GTIOC4A
00100b
SCI
―
SCK1
CTS2_RTS2/
SS2
SCK2
TXD2/MOSI2/
SDA2
RXD2/MISO2/
SCL2
―
―
00101b
SCI
CTS9_RTS9/
SS9
TXD9/MOSI9/
SDA9
RXD9/MISO9/
SCL9
SCK9
SCK1
―
―
―
00110b
SPI
SSLB0
MOSIB
MISOB
RSPCKB
SSLB0
―
―
―
00111b
IIC
―
―
―
―
―
―
―
―
01000b
KINT
―
―
―
―
―
―
―
―
01001b
CLKOUT/
ACMPLP/RTC
―
CLKOUT
VCOUT
―
―
―
―
―
01010b
CAC/ADC14
―
―
―
―
―
―
―
―
01011b
BUS
―
―
―
A05
A04
A03
A02
A01
TS35
01100b
CTSU
―
TS10
―
TS12
TSCAP
TS27
TS29
01101b
SLCDC
―
SEG52
SEG53
CAPH
CAPL
SEG00/COM4
SEG24
SEG25
10000b
CAN
―
CTX0
CRX0
―
―
―
―
―
10010b
SSIE
―
―
―
―
SSIBCK0
SSILRCK0/
SSIFS0
SSIRXD0
SSITXD0
ASEL bit
―
―
―
―
―
―
―
―
ISEL bit
―
―
IRQ3
IRQ4
―
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 421 of 1619
S3A1 User’s Manual
Table 20.8
PSEL[4:0] bit
settings
00000b (value
after reset)
20. I/O Ports
Register settings for input/output pin function (PORT2) (1)
Pin
Function
P200
Hi-Z/JTAG/SWD
Hi-Z
P201
P202
P203
P204
P205
P206
00001b
AGT
―
―
―
―
AGTIO1
AGTO1
―
00010b
GPT
―
―
―
―
GTIW
GTIV
GTIU
00011b
GPT
―
―
GTIOC5B
GTIOC5A
GTIOC4B
GTIOC4A
―
00100b
SCI
―
―
SCK2
CTS2_RTS2/
SS2
SCK4
TXD4/MOSI4/
SDA4
RXD4/MISO4/
SCL4
00101b
SCI
―
―
RXD9/MISO9/
SCL9
TXD9/MOSI9/
SDA9
SCK9
CTS9_RTS9/
SS9
―
00110b
SPI
―
―
MISOB
MOSIB
RSPCKB
SSLB0
SSLB1
00111b
IIC
―
―
―
―
SCL0
SCL1
SDA1
01001b
CLKOUT/
ACMPLP/RTC
―
―
―
―
―
CLKOUT
―
01010b
CAC/ADC14
―
―
―
―
CACREF
―
―
01011b
BUS
―
―
WR1/BC1
A19
A18
A16
WAIT
01100b
CTSU
―
―
―
TSCAP
TS00
TSCAP
TS01
01101b
SLCDC
―
―
SEG21
SEG22
SEG23
SEG20
SEG12
10011b
USBFS
―
―
―
―
USB_OVRCUR USB_OVRCUR USB_VBUSEN
B
A
10101b
SDHI
―
―
SD0DAT6
SD0DAT5
SD0DAT4
SD0DAT3
SD0DAT2
ISEL bit
NMI
―
IRQ3
IRQ2
―
IRQ1
IRQ0
NCODR bit
―
PCR bit
―
DSCR bit
―
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 422 of 1619
S3A1 User’s Manual
Table 20.9
PSEL[4:0] bit
settings
00000b (value
after reset)
20. I/O Ports
Register settings for input/output pin function (PORT2) (2)
Pin
Function
P212
Hi-Z/JTAG/SWD
Hi-Z
P213
P214
P215
―
00001b
AGT
AGTEE1
―
―
00010b
GPT
GTETRGB
GTETRGA
―
―
00011b
GPT
GTIOC0B
GTIOC0A
―
―
00100b
SCI
―
―
―
―
00101b
SCI
RXD1/MISO1/
SCL1
TXD1/MOSI1/
SDA1
―
―
00110b
SPI
―
―
―
―
00111b
IIC
―
―
―
―
01001b
CLKOUT/
ACMPLP/
RTC
―
―
―
―
01010b
CAC/ADC14
―
―
―
―
01011b
BUS
―
―
―
―
01100b
CTSU
―
―
―
―
01101b
SLCDC
―
―
―
―
10011b
USBFS
―
―
―
―
10101b
SDHI
―
―
―
―
ISEL bit
IRQ3
IRQ2
―
―
NCODR bit
―
―
PCR bit
―
―
DSCR bit
―
―
―
―
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 423 of 1619
S3A1 User’s Manual
Table 20.10
PSEL[4:0] bit
settings
20. I/O Ports
Register settings for input/output pin function (PORT3)
Pin
Function
P300
P301
00000b (value
after reset)
Hi-Z/JTAG/SWD
TCK/SWCLK
Hi-Z
P302
P303
P304
P305
P306
P307
00001b
AGT
―
00010b
GPT
GTOUUP
AGTIO0
―
―
―
―
―
―
GTOULO
GTOUUP
―
―
―
―
00011b
GPT
―
GTIOC0A
GTIOC4B
GTIOC4A
GTIOC7B
GTIOC7A
―
―
―
00100b
SCI
―
RXD2/MISO2/
SCL2
TXD2/MOSI2/
SDA2
―
―
―
―
―
00101b
SCI
―
CTS9_RTS9/
SS9
―
―
―
―
―
―
00110b
SPI
SSLB1
SSLB2
SSLB3
―
―
―
―
―
01010b
CAC/ADC14
―
―
―
―
―
―
―
―
01011b
BUS
―
A06
A07
A08
A09
A10
A11
A12
01100b
CTSU
―
TS09
TS08
TS02
TS11
―
―
―
01101b
SLCDC
―
SEG01/COM5
SEG02/COM6
SEG03/COM7
SEG17
SEG16
SEG15
SEG14
10001b
QSPI
―
―
―
―
―
QSPCLK
QSSL
QIO0
10101b
SDHI
―
―
―
SD0DAT0
SD0WP
SD0CD
―
―
ISEL bit
―
IRQ6
IRQ5
―
IRQ9
IRQ8
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
P309
P310
P311
P312
P313
P314
P315
PSEL[4:0] bit
settings
Pin
Function
P308
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00001b
AGT
―
―
AGTEE1
AGTOB1
AGTOA1
―
―
―
00010b
GPT
―
―
―
―
―
―
―
―
00011b
GPT
―
―
―
―
―
―
―
―
00100b
SCI
―
―
―
―
―
―
―
RXD4/MISO4/
SCL4
00101b
SCI
―
RXD3/MISO3/
SCL3
TXD3/MOSI3/
SDA3
SCK3
CTS3_RTS3/
SS3
―
―
―
00110b
SPI
―
―
―
―
―
―
―
―
01010b
CAC/ADC14
―
―
―
―
―
―
ADTRG0
―
01011b
BUS
A13
A14
A15
CS2
CS3
A20
A21
A22
01100b
CTSU
―
―
―
―
―
―
―
―
01101b
SLCDC
SEG13
―
―
―
―
―
―
―
10001b
QSPI
QIO1
QIO2
QIO3
―
―
―
―
―
10101b
SDHI
―
―
―
―
―
SD0DAT7
―
―
ISEL bit
―
―
―
―
―
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 424 of 1619
S3A1 User’s Manual
Table 20.11
PSEL[4:0] bit
settings
20. I/O Ports
Register settings for input/output pin function (PORT4) (1)
Pin
Function
P400
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
P401
P402
P403
P404
P405
P406
P407
00001b
AGT
AGTIO1
―
AGTIO0*2/
AGTIO1*2
AGTIO0*2/
AGTIO1*2
―
―
―
AGTIO0
00010b
00011b
GPT
―
GTETRGA
―
―
―
―
―
―
GPT
GTIOC6A
GTIOC6B
―
GTIOC3A
GTIOC3B
GTIOC1A
GTIOC1B
―
00100b
SCI
SCK4
CTS4_RTS4/
SS4
―
―
―
―
―
CTS4_RTS4/
SS4
00101b
SCI
SCK1
TXD1/MOSI1/
SDA1
RXD1/MISO1/
SCL1
CTS1_RTS1/
SS1
―
―
―
―
00110b
SPI
―
―
―
―
―
―
SSLA3
SSLB3
00111b
IIC
SCL0
SDA0
―
―
―
―
―
SDA0
01001b
CLKOUT/
ACMPLP/RTC
―
―
―
―
―
―
―
RTCOUT
01010b
CAC/ADC14
CACREF
―
―
―
―
―
―
ADTRG0
01100b
CTSU
TS20
TS19
TS18
TS17
―
―
―
TS03
01101b
SLCDC
SEG04
SEG05
SEG06
―
―
―
―
SEG11
10000b
CAN
―
CTX0
CRX0
―
―
―
―
―
10010b
SSIE
AUDIO_CLK
―
―
SSIBCK0
SSILRCK0/
SSIFS0
SSITXD0
SSIRXD0
―
10011b
USBFS
―
―
―
―
―
―
―
USB_VBUS
10101b
SDHI
―
―
―
―
―
―
―
―
Don’t care
―
―
RTCIC0*1
RTCIC1*1
RTCIC2*1
―
―
―
ISEL bit
IRQ0
IRQ5
IRQ4
―
―
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
Note 1.
Note 2.
To use this pin function, set the corresponding pin as general input (set the PmnPFS.PDR and PmnPFS.PMR bits to 0).
To use this pin function, set the PmnPFS.PSEL[4:0] bits and the AGTIOSEL.SEL[1:0] bits (described in section 24, AGT Pin
Select Register (AGTIOSEL)).
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 425 of 1619
S3A1 User’s Manual
Table 20.12
PSEL[4:0] bit
settings
20. I/O Ports
Register settings for input/output pin function (PORT4) (2)
Pin
Function
P408
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
P409
P410
P411
P412
P413
P414
P415
00001b
AGT
00010b
GPT
―
―
AGTOB1
AGTOA1
―
―
―
―
GTOWLO
GTOWUP
GTOVLO
GTOVUP
GTOULO
GTOUUP
―
00011b
―
GPT
GTIOC5B
GTIOC5A
GTIOC9B
GTIOC9A
―
―
GTIOC0B
GTIOC0A
00100b
SCI
CTS1_RTS1/
SS1
―
RXD0/MISO0/
SCL0
TXD0/MOSI0/
SDA0
SCK0
CTS0_RTS0/
SS0
―
―
00101b
SCI
RXD3/MISO3/
SCL3
TXD3/MOSI3/
SDA3
SCK3
CTS3_RTS3/
SS3
―
―
―
―
00110b
SPI
―
―
MISOA
MOSIA
RSPCKA
SSLA0
SSLA1
SSLA2
00111b
IIC
SCL0
―
―
―
―
―
―
―
01001b
CLKOUT/
ACMPLP/RTC
―
―
―
―
―
―
―
―
01010b
CAC/ADC14
―
―
―
―
―
―
―
―
01100b
CTSU
TS04
TS05
TS06
TS07
―
―
―
―
01101b
SLCDC
SEG10
SEG09
SEG08
SEG07
―
―
―
―
10000b
CAN
―
―
―
―
―
―
―
―
10010b
SSIE
―
―
―
―
―
―
―
―
10011b
USBFS
USB_ID
USB_EXICEN
―
―
―
―
―
―
10101b
SDHI
―
―
SD0DAT1
SD0DAT0
SD0CMD
SD0CLK
SD0WP
SD0CD
Don’t care
―
―
―
―
―
―
―
―
ISEL bit
IRQ7
IRQ6
IRQ5
IRQ4
―
―
IRQ9
IRQ8
NCODR bit
PCR bit
DSCR bit
L/M/M(IIC)
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
Note:
Note:
To use this pin function, set the corresponding pin as general input (set the PmnPFS.PDR and PmnPFS.PMR bits to 0).
To use this pin function, set the PmnPFS.PSEL[4:0] bits and the AGTIOSEL.SEL[1:0] bits (described in section 24, AGT Pin
Select Register (AGTIOSEL)).
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Oct 29, 2018
Page 426 of 1619
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Table 20.13
PSEL[4:0] bit
settings
00000b (value
after reset)
20. I/O Ports
Register settings for input/output pin function (PORT5)
Pin
Function
P500
Hi-Z/JTAG/SWD
Hi-Z
P501
P502
P503
P504
P505
P506
P507
―
00001b
AGT
AGTOA0
AGTOB0
―
―
―
―
―
00010b
GPT
GTIU
GTIV
GTIW
GTETRGA
GTETRGB
―
―
―
00011b
GPT
GTIOC2A
GTIOC2B
GTIOC3B
―
―
―
―
―
00100b
SCI
―
―
―
CTS2_RTS2/
SS2
SCK2
RXD2/MISO2/
SCL2
TXD2/MOSI2/
SDA2
―
00101h
SCI
―
TXD3/MOSI3/
SDA3
RXD3/MISO3/
SCL3
SCK3
CTS3_RTS3/
SS3
―
―
―
00111b
IIC
―
―
―
―
―
―
―
―
01011b
BUS
―
―
―
―
ALE
―
―
―
01101b
SLCDC
SEG48
SEG49
SEG50
SEG51
―
―
―
―
10000b
CAN
―
―
―
―
―
―
―
―
10001b
QSPI
QSPCLK
QSSL
QIO0
QIO1
QIO2
QIO3
―
―
10011b
USBFS
USB_VBUSEN
USB_OVRCUR USB_OVRCUR USB_EXICEN
A
B
USB_ID
―
―
―
ASEL bit
AN016/
CMPREF1
AN017/
CMPIN1
AN018/
CMPREF0
AN023/
CMPIN0
AN024
AN025
AN026
AN027
ISEL bit
―
IRQ11
IRQ12
―
―
IRQ14
IRQ15
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
PSEL[4:0] bit
settings
Pin
Function
P511
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
P512
00001b
AGT
―
―
00010b
GPT
―
―
00011b
GPT
GTIOC0B
GTIOC0A
00100b
SCI
RXD4/MISO4/
SCL4
TXD4/MOSI4/
SDA4
00101h
SCI
―
―
00111b
IIC
SDA2
SCL2
01011b
BUS
―
―
01101b
SLCDC
―
―
10000b
CAN
CRX0
CTX0
10001b
QSPI
―
―
10011b
USBFS
―
―
ASEL bit
―
―
ISEL bit
IRQ15
IRQ14
NCODR bit
PCR bit
DSCR bit
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 427 of 1619
S3A1 User’s Manual
Table 20.14
PSEL[4:0] bit
settings
20. I/O Ports
Register settings for input/output pin function (PORT6)
Pin
Function
P600
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
P601
P602
P603
P604
P605
P606
00011b
GPT
GTIOC6B
GTIOC6A
GTIOC7B
GTIOC7A
GTIOC8B
GTIOC8A
―
00101b
SCI
SCK9
RXD9/MISO9/
SCL9
TXD9/MOSI9/
SDA9
CTS9_RTS9/
SS9
―
―
―
01001b
CLKOUT/
ACMPLP/RTC
―
―
―
―
―
―
RTCOUT
01011b
BUS
RD
WR/WR0
BCLK
D13
D12
D11
―
01101b
SLCDC
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
10101b
SDHI
SD0DAT7
SD0DAT6
SD0DAT5
SD0DAT4
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
P609
P610
P611
P612
P613
64-pin product
PSEL[4:0] bit
settings
00000b (value
after reset)
Pin
Function
P608
Hi-Z/JTAG/SWD
Hi-Z
P614
00011b
GPT
GTIOC4B
GTIOC5A
GTIOC5B
―
―
―
―
00101b
SCI
―
―
―
―
―
―
―
01001b
CLKOUT/
ACMPLP/RTC
―
―
―
―
―
―
―
01011b
BUS
A00/BC0
CS1
CS0
―
D08
D09
D10
01101b
SLCDC
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
10101b
SDHI
SD0DAT1
SD0DAT2
SD0DAT3
―
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
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Oct 29, 2018
Page 428 of 1619
S3A1 User’s Manual
Table 20.15
PSEL[4:0] bit
settings
20. I/O Ports
Register settings for input/output pin function (PORT7)
Pin
Function
P700
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
P701
P702
P703
P704
P705
00001b
AGT
00011b
GPT
―
―
―
―
AGTO0
AGTIO0
GTIOC5A
GTIOC5B
GTIOC6A
GTIOC6B
―
00101b
―
SCI
―
―
―
―
―
―
00110b
SPI
MISOA
MOSIA
RSPCKA
SSLA0
SSLA1
SSLA2
01001b
CLKOUT/
ACMPLP/RTC
―
―
―
VCOUT
―
―
01011b
BUS
―
―
―
―
―
―
ISEL bit
―
―
―
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
P709
P710
P711
P712
P713
AGTOA0
100-pin product
64-pin product
PSEL[4:0] bit
settings
Pin
Function
P708
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00001b
AGT
―
―
―
AGTEE0
AGTOB0
00011b
GPT
―
―
―
―
GTIOC2B
GTIOC2A
00101b
SCI
RXD1/MISO1/
SCL1
TXD1/MOSI1/
SDA1
SCK1
CTS1_RTS1/
SS1
―
―
00110b
SPI
SSLA3
―
―
―
―
―
01001b
CLKOUT/
ACMPLP/RTC
―
―
―
―
―
―
01011b
BUS
―
―
A17
―
―
―
ISEL bit
IRQ11
IRQ10
―
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 429 of 1619
S3A1 User’s Manual
Table 20.16
PSEL[4:0] bit
settings
00000b (value
after reset)
20. I/O Ports
Register settings for input/output pin function (PORT8)
Pin
Function
P800
Hi-Z/JTAG/SWD
Hi-Z
P801
P802
P803
P804
P805
P806
P807
00011b
GPT
―
―
―
―
GTIOC9B
GTIOC9A
―
―
01011b
BUS
D14
D15
―
―
―
―
―
―
01101b
SLCDC
SEG44
SEG45
SEG46
SEG47
SEG43
SEG42
SEG26
SEG27
10101b
SDHI
―
―
―
―
―
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
PSEL[4:0] bit
settings
Pin
Function
P808
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
P809
00011b
GPT
―
―
01011b
BUS
―
―
01101b
SLCDC
SEG18
SEG19
10101b
SDHI
SD0CLK
SD0CMD
NCODR bit
PCR bit
DSCR bit
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
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Page 430 of 1619
S3A1 User’s Manual
Table 20.17
PSEL[4:0] bit
settings
20. I/O Ports
Register settings for input/output pin function (PORT9)
Pin
Function
P900
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
P901
P902
00001b
AGT
―
AGTIO1
AGTO1
00100b
SCI
TXD4/MOSI4/
SDA4
SCK4
CTS4_RTS4/
SS4
01011b
BUS
A23
―
―
Don’t care
―
―
―
NCODR bit
PCR bit
DSCR bit
L/M
L/M
L/M
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
PSEL[4:0] bit
settings
Pin
Function
P914
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
P915
00001b
AGT
―
―
00100b
SCI
―
―
01011b
BUS
―
―
Don’t care
(USB_DP)
(USB_DM)
NCODR bit
―
―
PCR bit
―
―
DSCR bit
―
―
145-pin product, 144-pin product
121-pin product
100-pin product
64-pin product
: Available
—: Setting prohibited
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Page 431 of 1619
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21. Key Interrupt Function (KINT)
21.
Key Interrupt Function (KINT)
21.1
Overview
A key interrupt (KEY_INTKR) can be generated by setting the Key Return Mode Register (KRM) and inputting a rising
or falling edge to the key interrupt input pins, KR00 to KR07. Table 21.1 shows the assignment for key interrupt
detection, Table 21.2 shows the function configuration, and Figure 21.1 shows a block diagram.
Table 21.1
Assignment of key interrupt detection pins
Flag
Description
KRM0
Controls KR00 signal in 1-bit units
KRM1
Controls KR01 signal in 1-bit units
KRM2
Controls KR02 signal in 1-bit units
KRM3
Controls KR03 signal in 1-bit units
KRM4
Controls KR04 signal in 1-bit units
KRM5
Controls KR05 signal in 1-bit units
KRM6
Controls KR06 signal in 1-bit units
KRM7
Controls KR07 signal in 1-bit units
Table 21.2
Configuration of Key Interrupt Function (KINT)
Item
Configuration
Input
KR00 to KR07
Control registers
Key Return Control Register (KRCTL)
Key Return Mode Register (KRM)
Key Return Flag Register (KRF)
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21. Key Interrupt Function (KINT)
0
1
KR00
KREG
Filter
KRF0
KRM0
0
1
KRMD
0
KR01
Filter
1
KREG
0
KRF1
KRM1
1
KRMD
0
KR02
Filter
1
KREG
0
KRF2
KRM2
1
KRMD
0
KR03
Filter
1
KREG
0
KRF3
KRM3
1
KRMD
0
KR04
Filter
1
KREG
KEY_INTKR
0
KRF4
KRM4
1
KEY_INTKR mask signal
KRMD
0
KR05
Filter
1
KREG
0
KRF5
KRM5
1
KRMD
0
KR06
Filter
1
KREG
0
KRF6
KRM6
1
KRMD
0
KR07
Filter
1
KREG
0
KRF7
KRM7
1
KRMD
Figure 21.1
Key interrupt function block diagram
In Figure 21.1, all key return factors are merged by an OR gate, and the key interrupt (KEY_INTKR) is the output of
AND gate to mask the merged key return factor by the KEY_INTKR mask signal. When using KRFn (KRMD = 1), the
KEY_INTKR mask signal is used as the output mask that is asserted by the clearing KRFn.
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21.2
21. Key Interrupt Function (KINT)
Register Descriptions
21.2.1
Key Return Control Register (KRCTL)
Address(es): KINT.KRCTL 4008 0000h
b7
b6
b5
b4
b3
b2
b1
b0
KRMD
—
—
—
—
—
—
KREG
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
KREG
Detection Edge Selection
(KR00 to KR07)
0: Falling edge
1: Rising edge.
R/W
b6 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
KRMD
Usage of Key Interrupt Flags
(KRF0 to KRF7)
0: Do not use key interrupt flags
1: Use key interrupt flags.
R/W
The KRCTL controls the usage of the key interrupt flags, KRF0 to KRF7, and sets the detection edge.
21.2.2
Key Return Flag Register (KRF)
Address(es): KINT.KRF 4008 0004h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
KRF7
KRF6
KRF5
KRF4
KRF3
KRF2
KRF1
KRF0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
KRFn
Key Interrupt Flag n
0: No key interrupt detected
1: Key interrupt detected.
R/W
n = 0 to 7
Note:
When KRMD = 0, setting the KRFn bit to 1 is prohibited.
When the KRFn bit is set to 1, the KRFn value does not change.
To clear the KRFn bit, confirm that the target bit is 1 before writing 0 to the bit, then write 1 to the other bits.
The KRF controls the key interrupt flags, KRF0 to KRF7.
21.2.3
Key Return Mode Register (KRM)
Address(es): KINT.KRM 4008 0008h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
KRM7
KRM6
KRM5
KRM4
KRM3
KRM2
KRM1
KRM0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
KRMn
Key Interrupt Mode Control n
0: No key interrupt signal detected
1: Key interrupt signal detected.
R/W
n = 0 to 7
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Note:
21. Key Interrupt Function (KINT)
The on-chip pull-up resistors can be applied by setting the associated key interrupt input pin in the pull-up resistor. For details,
see section 20, I/O Ports.
Key interrupts can be assigned in the PmnPFS.PSEL bits. For more information, see section 20, I/O Ports.
An interrupt is generated when the target bit in the KRM is set while a low level (KREG is set to 0) or a high level (KREG is set
to 1) is being input to the key interrupt input pin. To ignore this interrupt, set the KRM after disabling the interrupt handling.
The KRM sets the key interrupt mode.
21.3
Operation
21.3.1
When Not Using Key Interrupt Flag (KRMD = 0)
A key interrupt (KEY_INTKR) is generated when the valid edge specified in the KREG bit is input to a key interrupt pin,
KR00 to KR07. To identify the channel to which the valid edge is input, read the port register and check the port level
after the key interrupt (KEY_INTKR) is generated.
The KEY_INTKR signal changes based on the input level of the key interrupt input pin, KR00 to KR07.
KRn
KEY_INTKR
Delay
Delay
Key interrupt
Note:
When KRMD = 0 and KREG = 0
n = 00 to 07
Figure 21.2
Operation of KEY_INTKR signal when key interrupt is input to a single channel
Figure 21.3 shows the operation when a valid edge is input to multiple key interrupt input pins. The KEY_INTKR signal
is set while a low level is being input to one pin, when KREG is set to 0. Therefore, even if a falling edge is input to
another pin in this period, a key interrupt (KEY_INTKR) is not generated again. See [1] in Figure 21.3.
KR00
KR01
[1]
KEY_INTKR
Delay
Key interrupt
Figure 21.3
Delay
Delay
When KRMD = 0 and KREG = 0
Operation of KEY_INTKR signal when key interrupts are input to multiple channels
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21.3.2
21. Key Interrupt Function (KINT)
Operation When Using Key Interrupt Flag (KRMD = 1)
A key interrupt (KEY_INTKR) is generated when the valid edge specified in the KREG bit is input to a key interrupt pin,
KR00 to KR07. To identify the channels to which the valid edge is input, read the Key Return Flag Register (KRF) after
the key interrupt (KEY_INTKR) is generated. If the KRMD bit is set to 1, clear the KEY_INTKR signal by clearing the
associated bit in the KRF.
As Figure 21.4 shows, only one interrupt is generated each time a falling edge is input to one channel, that is, when
KREG = 0, regardless of whether the KRFn bit is cleared before or after a rising edge is input.
(a) When KRF0 is cleared after a rising edge is input to the KR00 pin
KR00
KRF0
Cleared by
software
KEY_INTKR
Delay
Key interrupt
(b) When KRF0 is cleared before a rising edge is input to the KR00 pin
KR00
KRF0
Cleared by
software
KEY_INTKR
Delay
Key interrupt
Figure 21.4
When KRMD = 1 and KREG = 0
Basic operation of KEY_INTKR signal when key interrupt flag is used
The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 21.5. A falling edge is
also input to the KR01 and KR05 pins after a falling edge is input to the KR00 pin, when KREG = 0. The KRF1 bit is set
when the KRF0 bit is cleared. A key interrupt generates 1 PCLKB clock cycle, after the KRF0 bit is cleared. See [1] in
Figure 21.5. Also, after a falling edge is input to the KR05 pin, the KRF5 bit is set. See [2] in the figure when the KRF1
bit is cleared. A key interrupt generates PCLKB 1 clock cycle, after the KRF1 bit is cleared. See [3] in the figure. It is
therefore possible to generate a key interrupt when a valid edge is input to multiple channels.
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21. Key Interrupt Function (KINT)
KR00
KR01
KR05
KRF0
Delay time
Cleared by software
[2]
KRF1
Cleared by software
Delay time
KRF5
Cleared by
software
Delay time
[1]
[3]
KEY_INTKR
Key interrupt
Key interrupt
Key interrupt
When KRMD = 1 and KREG = 0
Figure 21.5
21.4
Operation of KEY_INTKR signal when key interrupts are input to multiple channels
Usage Notes
If KEY_INTKR is used as the snooze request, the KRMD bit must be set to 0
If KEY_INTKR is used as the interrupt source for returning to Normal mode from Snooze mode and Software
Standby mode, the KRMD bit must be set to 1
When the Key Interrupt function (KINT) is assigned to a pin, this pin input is always enabled in Software Standby
mode, and if this pin level changes, the associated KRFn flag can be set. Therefore, a key interrupt might occur on
canceling Software Standby mode.
To ignore changes to the key interrupt pin during a Software Standby, clear the associated KRM bit before entering
Software Standby mode. After canceling Software Standby mode, you must clear KRFn before the associated KRM bit
can be set.
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22.
22. Port Output Enable for GPT (POEG)
Port Output Enable for GPT (POEG)
Use the Port Output Enable (POEG) function to place the General PWM Timer (GPT) output pins in the output-disable
state in one of the following ways:
Input level detection of the GTETRGn (n = A, B) pins
Output-disable request from the GPT
Comparator interrupt request detection
Oscillation stop detection of the clock generation circuit
Register settings.
The GTETRGn (n = A, B) pins can also be used as GPT external trigger input pins.
22.1
Overview
Table 22.1 lists the POEG specifications, Figure 22.1 shows a block diagram, and Table 22.2 lists the input pins.
Table 22.1
POEG specifications
Item
Description
Output-disable control through input level
detection
The GPT output pins can be disabled when a GTETRGn rising edge or high level is
sampled after polarity and filter selection
Output-disable request from the GPT
When the GTIOCA pin and the GTIOCB pin are driven to an active level
simultaneously, the GPT generates an output-disable request to the POEG. Through
reception of these requests, the POEG can control whether the GTIOCA and GTIOCB
pins are output-disabled.
Output-disable control through oscillation stop
detection
The GPT output pins can be disabled when oscillation of the clock generation circuit
stops
Output-disable control by software (registers)
The GPT output pins can be disabled by modifying the register settings
Interrupts
Allows output-disable control by the input level detection
Allows output-disable requests from GPT.
External trigger output function to the GPT
(count start, count stop, count clear, up-count,
down-count, or input capture function)
The GTETRGn signals can be output to the GPT after polarity and filter selection
Noise filtering
Three times sampling for every PCLKB/1, PCLKB/8, PCLKB/32, or PCLKB/128 can
be set for any of the input pins GTETRGn
Positive or negative polarity can be selected for any of the input pins, GTETRGn
The signal state after polarity and filter selection can be monitored.
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22. Port Output Enable for GPT (POEG)
Group B
POEG Group A
IOCF
IOCE
GPT
Ch 0
GTINTAD.GRPABH,
GTINTAD.GRPABL
Group A
Ch 0
Group B
Ch 9
S
POEG_GROUP0
R
POEG_GROUP1
ICU
GPT
OPS
Ch 1
Ch 9
OPSCR.
GRP[1:0],
OPSCR.
GODF
Comparator detect
Oscillation
Stop Detector
GTOUUP
GTOULO
GTOVUP
GTOVLO
GTOWUP
GTOWLO
OSTPF
OSC stop
detect
OSTPE
S
R
To ch 1
To ch 9
To ch 1
To ch 9
SSF
Digital Filter
INV
GTETRGA
GTETRGB
PIDF
PIDE
NFCS[1:0]
NFEN
GTINTAD.
GRP[1:0],
GTIOR.
OADF[1:0],
GTIOR.
OBDF[1:0]
GTIOC0A
GTIOC0B
GTIOC1A
GTIOC1B
GTIOC9A
To ch 1
To ch 9
GTIOC9B
To ch 1
To ch 9
ST
Ch 0
Ch 1
Ch 9
Figure 22.1
Table 22.2
POEG block diagram
POEG input pins
Pin Name
I/O
Description
GTETRGA
Input
GPT output pin output-disable request signal and GPT external trigger input pin A
GTETRGB
Input
GPT output pin output-disable request signal and GPT external trigger input pin B
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22.2
22. Port Output Enable for GPT (POEG)
Register Descriptions
22.2.1
POEG Group n Setting Register (POEGGn) (n = A, B)
Address(es): POEG.POEGGA 4004 2000h, POEG.POEGGB 4004 2100h
b31
b30
NFCS[1:0]
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
NFEN
INV
—
—
—
—
—
—
—
—
—
—
—
ST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
PIDE
SSF
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
OSTPE IOCE
0
0
OSTPF IOCF
0
PIDF
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIDF
Port Input Detection Flag
0: No output-disable request from the GTETRGn pin occurred
1: Output-disable request from the GTETRGn pin occurred.
R(/W)*1
b1
IOCF
Output-disable Request
Detection Flag from GPT
0: No output-disable request from the GPT disable request
occurred
1: Output-disable request from the GPT disable request occurred.
R(/W)*1
b2
OSTPF
Oscillation Stop Detection
Flag
0: No output-disable request from oscillation stop detection
occurred
1: Output-disable request from oscillation stop detection occurred.
R(/W)*1
b3
SSF
Software Stop Flag
0: No output-disable request from software occurred
1: Output-disable request from software occurred.
R/W
b4
PIDE
Port Input Detection Enable
0: Disable output-disable request from the GTETRGn pins
1: Enable output-disable request from the GTETRGn pins.
R/W*2
b5
IOCE
Output-disable Request
Enable from GPT
0: Disable output-disable request from the GPT disable request
1: Enable output-disable request from the GPT disable request.
R/W*2
b6
OSTPE
Oscillation Stop Detection
Enable
0: Disable output-disable request from the oscillation stop
detection
1: Enable output-disable request from the oscillation stop
detection.
R/W*2
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
ST
GTETRGn Input Status Flag 0: GTETRGn input after filtering is 0
1: GTETRGn input after filtering is 1.
R
b27 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28
INV
GTETRGn Input Reverse
0: GTETRGn input as-is
1: GTETRGn input reversed.
R/W
b29
NFEN
Noise Filter Enable
0: Disable noise filtering
1: Enable noise filtering.
R/W
b31, b30
NFCS[1:0]
Noise Filter Clock Select
b31 b30
R/W
Note 1.
Note 2.
0 0:GTETRGn pin input level sampled three times every PCLKB
0 1:GTETRGn pin input level sampled three times every
PCLKB/8
1 0:GTETRGn pin input level sampled three times every
PCLKB/32
1 1:GTETRGn pin input level sampled three times every
PCLKB/128.
Only 0 can be written to clear the flag.
Can be modified only once after a reset.
The POEGGA to POEGGD registers control the output-disable state of the GPT pin output, interrupts, and the external
trigger input to GPT. In the descriptions, POEGGn represents all the POEGGA to POEGGD registers.
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22.3
22. Port Output Enable for GPT (POEG)
Output-Disable Control Operation
If any of the following conditions is satisfied, the GTIOCxA, GTIOCxB, and the 3-phase PWM output for BLDC motor
control pins can be set to output-disable:
Input level or edge detection of the GTETRGn pins
When POEGGn.PIDE is 1, the POEGGn.PIDF flag is set to 1.
Output-disable request from the GPT
When POEGGn.IOCE is 1, the POEGGn.IOCF flag is set to 1 if the disable request enabled in the
GTINTAD.GRPABH, or GTINTAD.GRPABL applies to the group selected in the GPT registers
GTINTAD.GRP[1:0] and OPSCR.GRP[1:0].
Oscillation stop detection for the clock generation circuit
When POEGGn.OSTPE is 1, the POEGGn.OSTPF flag is set to 1.
SSF bit setting
When POEGGn.SSF is set to 1, the PWM output is disabled.
The output-disable state is controlled in the GPT. The output-disable of the GTIOCxA and GTIOCxB pins is set in the
GTINTAD.GRP[1:0], GTIOR.OADF[1:0], and GTIOR.OBDF[1:0] bits in the GPT. The output-disable of the 3-phase
PWM output for the BLDC motor control pins is set in the OPSCR.GRP[1:0] and OPSCR.GODF bits in GPT_OPS.
22.3.1
Pin Input Level Detection Operation
If the input conditions set by POEGGn.PIDE, POEGGn.NFCS[1:0], POEGGn.NFEN, and POEGGn.INV occur on the
GTETRGn pins, the GPT output pins are output-disabled.
22.3.1.1
Digital filter
Figure 22.2 shows high-level detection by the digital filter. When a high level associated with the POEGGn.INV polarity
setting is detected three times consecutively with the sampling clock selected in POEGGn.NFCS[1:0] and
POEGGn.NFEN, the detected level is recognized as high, and the GPT output pins are output-disabled. If even one low
level is detected during this interval, the detected level is not recognized as high. In addition, in an interval where the
sampling clock is not being output, changes of the levels on the GTETRGn pins are ignored.
1, 8, 32, 128 clock
PCLKB
Sampling clock
GTETRGn input
GTIOCA
GTIOCB
(PCLKD)
When high level is sampled at all points
[1]
[2]
[3]
Flag set (GTETRGn received)
When low level is sampled at least once
[1]
[0]
[1]
Flag not set
Note 1.
Figure 22.2
Each channel output can be set in the GPT setting.
Low level sampling can be set in the POEGGn.INV setting.
Example of digital filter operation
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22.3.2
22. Port Output Enable for GPT (POEG)
Output-Disable Request from GPT
For details on the operation, see section 23.7.3, GTIOC Pin Output Negate Control in chapter 23. General PWM Timer
(GPT).
22.3.3
Output-Disable Control on Detection of Stopped Oscillation
When the oscillation stop detection function in the clock generation circuit detects stopped oscillation while
POEGGn.OSTPE is 1, the GPT output pins are output-disabled for each group.
22.3.4
Output-Disable Control Using Registers
The GPT output pins can be directly controlled by writing to the Software Stop Flag, POEGGn.SSF.
22.3.5
Release from Output-Disable
To release the GPT output pins in the output-disable state, either return them to their initial state with a reset or clear all
of the following:
POEGGn.PIDF flag
POEGGn.IOCF flag
POEGGn.OSTPF flag
POEGGn.SSF flag.
Writing 0 to the POEGGn.PIDF flag is ignored (the flag is not cleared) if the external input pins, GTETRGn, are not
disabled and the POEGGn.ST bit is not set to 0.
Writing 0 to the POEGGn.IOCF flag is valid (the flag is cleared) only if all of the GTST.OABHF, and GTST.OABLF
flags in GPT are set to 0.
Writing 0 to the POEGGn.OSTPF flag is ignored (the flag is not cleared) if the OSTDSR.OSTDF flag in the clock
generation circuit is not set to 0. In addition, when the flag set and release occur at the same time, the flag set takes
precedence.
Figure 22.3 shows the released timing for output-disable. The output-disable is released at the beginning of the next
count cycle of the GPT after the flag is cleared.
GPT320.GTCNT value
GPT320.GTPR
GPT320.GTCCRA
Flag clear
PIDF, IOCF
OSTPF, SSF
GTIOC0A
GTIOC0B
Output-disable
Figure 22.3
22.4
Output-disable release timing for the GPT pin outputs
Interrupt Sources
The POEG generates an interrupt request when triggered by these sources:
Output-disable control by the input level detection
Output-disable request from GPT
Table 22.3 lists the conditions for interrupt requests.
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Table 22.3
22. Port Output Enable for GPT (POEG)
Interrupt sources and conditions
Interrupt source
Symbol
Associated flag
Trigger conditions
POEG group A interrupt
POEG_GROUP0
POEGGA.IOCF
An output-disable request from a GPT disable request
occurred
POEGGA.PIDF
An output-disable request from the GTETRGA pin
occurred
POEGGB.IOCF
An output-disable request from a GPT disable request
occurred
POEGGB.PIDF
An output-disable request from the GTETRGB pin
occurred
POEG group B interrupt
22.5
POEG_GROUP1
External Trigger Output to GPT
The POEG outputs the GTETRGn signals as the GPT operation trigger signal for the following:
Count start
Count stop
Count clear
Up-count
Down-count
Input capture.
For the POEGG.INV polarity setting signal, when the same level is input three times continuously with the sampling
clock selected in the POEGGn.NFCS[1:0] and POEGGn.NFEN, that value is output. Set the control registers the same as
for the input level detection operation described in section 22.3.1, Pin Input Level Detection Operation. The state after
filtering can be monitored in POEGGn.ST.
Figure 22.4 shows the output timing of an external trigger to the GPT.
8, 16, 128 clock
PCLKB
Sampling clock
GTETRGn pin
POEGGn.ST
(GTETRGn after filtering)
[1]
Note 1.
Figure 22.4
22.6
22.6.1
[1]
[2]
[1]
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[1]
Each channel output can be set in the GPT setting.
Polarity can be reversed in the POEGGn.INV setting.
Output timing of external trigger to GPT
Usage Notes
Transition to Software Standby Mode
When using the POEG, do not invoke Software Standby mode. In this mode, the POEG stops and therefore outputdisable of the pins cannot be controlled.
22.6.2
Specifying Pins Associated with GPT
The POEG controls output-disable only when a pin is associated with the GPT in the PmnPFS.PMR and PmnPFS.PSEL
settings. When the pin is specified as a general I/O pin, the POEG does not perform output-disable control.
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23. General PWM Timer (GPT)
23.
General PWM Timer (GPT)
23.1
Overview
The General PWM Timer (GPT) is a 32-bit timer with four GPT32 channels, and a 16-bit timer with six GPT16
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter.
In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a
general-purpose timer.
Table 23.1 lists the GPT specifications, Table 23.2 shows the GPT functions, Figure 23.1 shows a block diagram, and
Table 23.3 lists the I/O pins.
Table 23.1
GPT specifications
Item
Description
Functions
32 bits × 4 channels
16 bits × 6 channels
Up-counting or down-counting (saw waves) or up/down-counting (triangle waves) for each counter
Clock sources independently selectable for each channel
Two I/O pins per channel
Two output compare/input capture registers per channel
For the two output compare/input capture registers of each channel, four registers are provided as
buffer registers and are capable of operating as comparison registers when buffering is not in use
In output compare operation, buffer switching can be at crests or troughs, enabling the generation of
laterally asymmetric PWM waveforms
Registers for setting up frame cycles in each channel with capability for generating interrupts at
overflow or underflow
Generation of dead times in PWM operation
Synchronous starting, stopping and clearing counters for arbitrary channels
Starting, stopping, clearing and up/down counters in response to a maximum of eight ELC events
Starting, stopping, clearing and up/down counters in response to input level comparison
Starting, clearing, stopping and up/down counters in response to a maximum of four external triggers
Output pin disable function by detected short-circuits between output pins
PWM waveform for controlling brushless DC motors can be generated
Compare match A to F event, overflow/underflow event, and input UVW edge event can be output to
the ELC
Enables the noise filter for input capture and input UVW
Bus clock: PCLKA
Core clock: PCLKD
Frequency ratio: PCLKA:PCLKD = 1:N (N = 1/2/4/8/16/32/64).
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Table 23.2
23. General PWM Timer (GPT)
GPT functions
Item
GPT32, GPT16
Count clock
PCLKD
PCLKD/4
PCLKD/16
PCLKD/64
PCLKD/256
PCLKD/1024
Output compare/input capture registers (GTCCR)
GTCCRA
GTCCRB
Compare/buffer registers
GTCCRC
GTCCRD
GTCCRE
GTCCRF
Cycle setting register
GTPR
Cycle setting buffer registers
GTPBR
I/O pins
GTIOCA
GTIOCB
External trigger input pin*1
GTETRGA
GTETRGB
Counter clear sources
GTPR register compare match, input capture, input pin status, ELC event
input, and GTETRGn (n = A, B) pin input
Compare match output
Low output
Available
High output
Available
Toggle output
Available
Input capture function
Available
Automatic addition of dead time
Available
(no dead time buffer)
PWM mode
Available
Phase count function
Available
Buffer operation
Double buffer
One-shot operation
Available
DTC activation
All the interrupt sources
Brushless DC motor control function
Available
Interrupt sources
8 sources:
GTCCRA compare match/input capture (GPTn_CCMPA)
GTCCRB compare match/input capture (GPTn_CCMPB)
GTCCRC compare match (GPTn_CMPC)
GTCCRD compare match (GPTn_CMPD)
GTCCRE compare match (GPTn_CMPE)
GTCCRF compare match (GPTn_CMPF)
GTCNT overflow (GTPR compare match) (GPTn_OVF)
GTCNT underflow (GPTn_UDF).
Note: n = 0 to 9
Event linking (ELC) function
Available
Noise filtering function
Available
Note 1. GTRETRGn connects to GPT through the POEG module. Therefore, in order to use the GPT function, the POEG
clock needs to be supplied by clearing the MSTPD14 bit.
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23. General PWM Timer (GPT)
GPT320
Control registers
Clock source
PCLKD
PCLKD/4
PCLKD/16
PCLKD/64
PCLKD/256
PCLKD/1024
GTDTCR
GTICASR
GTICBSR
GTDVU
GTCR
GTUDDTYC
GTIOR
GTINTAD
GTST
GTBER
GTWP
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GTDNSR
Cycle setting/
Cycle setting buffer registers
GTPBR
GTPR
Interrupt request signals
GPT0_CCMPA
GPT0_CCMPB
GPT0_CMPC
GPT0_CMPD
GPT0_CMPE
GPT0_CMPF
GPT0_OVF
GPT0_UDF
GPT321
GPT322
GPT323
GPT164
GPT165
GPT166
GPT167
GPT168
GPT169
External
trigger (after noise filtering)
GTETRGA
GTETRGB
Counter (GTCNT)
Output disable request
Output compare
Output disable signals
I/O pins
GTIOCA
Comparator
GTIOCB
Input capture
GTCCRA
GTCCRB
ELC event input
ELC_GPTA
ELC_GPTB
ELC_GPTC
ELC_GPTD
ELC_GPTE
ELC_GPTF
ELC_GPTG
ELC_GPTH
GTCCRC
GTCCRD
GTCCRE
GTCCRF
Output compare/input capture registers
GPT_OPS
GPT320.GTIOCA output
I/O pins
GTIU / GTIV / GTIW
3-phase PWM wave generator
for brushless DC motor
GTOUUP / GTOULO
GTOVUP / GTOVLO
GTOWUP / GTOWLO
OPSCR
Output disable signals
Input UVW edge event signal (to ICU/ELC)
GTWP
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GTDNSR
GTICASR
GTICBSR
GTCR
GTUDDTYC
GTIOR
GTINTAD
GTST
GTBER
General PWM Timer Write-Protection Register
General PWM Timer Software Start Register
General PWM Timer Software Stop Register
General PWM Timer Software Clear Register
General PWM Timer Start Source Select Register
General PWM Timer Stop Source Select Register
General PWM Timer Clear Source Select Register
General PWM Timer Up Count Source Select Register
General PWM Timer Down Count Source Select Register
General PWM Timer Input Capture Source Select Register A
General PWM Timer Input Capture Source Select Register B
General PWM Timer Control Register
General PWM Timer Count Direction and Duty Setting Register
General PWM Timer I/O Control Register
General PWM Timer Interrupt Output Setting Register
General PWM Timer Status Register
General PWM Timer Buffer Enable Register
Figure 23.1
GTCNT
GTCCRA
GTCCRB
GTCCRC
GTCCRD
GTCCRE
GTCCRF
GTPR
GTPBR
GTDTCR
GTDVU
OPSCR
General PWM Timer Counter
General PWM Timer Compare Capture Register A
General PWM Timer Compare Capture Register B
General PWM Timer Compare Capture Register C
General PWM Timer Compare Capture Register D
General PWM Timer Compare Capture Register E
General PWM Timer Compare Capture Register F
General PWM Timer Cycle Setting Register
General PWM Timer Cycle Setting Buffer Register
General PWM Timer Dead Time Control Register
General PWM Timer Dead Time Value Register U
Output Phase Switching Control Register
GPT block diagram
Figure 23.2 shows an example using multiple GPTs.
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
GPT169
GPT168
GPT167
GPT166
GPT165
GPT164
GPT323
GPT322
GPT321
GPT320
GPT16
Figure 23.2
GPT32
Correspondence between GPT channels and module names
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Table 23.3
23. General PWM Timer (GPT)
GPT I/O pins
Channel
Pin name
I/O
Function
Shared
GTETRGA
Input
External trigger input pin A (after noise filtering)
GTETRGB
Input
External trigger input pin B (after noise filtering)
GPT320
GTIOC0A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC0B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC1A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC1B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT322
GTIOC2A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC2B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT323
GTIOC3A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC3B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC4A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC4B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC5A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC5B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT166
GTIOC6A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC6B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT167
GTIOC7A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC7B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC8A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC8B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC9A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC9B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GPT321
GPT164
GPT165
GPT168
GPT169
GPT_OPS
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U-phase)
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U-phase)
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V-phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V-phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W-phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W-phase)
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23.2
23. General PWM Timer (GPT)
Register Descriptions
Table 23.4 lists the registers in the GPT.
Table 23.4
Module
symbol
GPT32m*1
GPT16m*2
GPT_OPS
Note 1.
Note 2.
Note 3.
GPT registers
Register name
Register
symbol
Reset value
Address
Access
size
General PWM Timer Write Protection Register
GTWP
00000000h
4007 8000h + 0100h × m
32
General PWM Timer Software Start Register
GTSTR
00000000h
4007 8004h + 0100h × m
32
General PWM Timer Software Stop Register
GTSTP
FFFFFFFFh
4007 8008h + 0100h × m
32
General PWM Timer Software Clear Register
GTCLR
00000000h
4007 800Ch + 0100h × m
32
General PWM Timer Start Source Select Register
GTSSR
00000000h
4007 8010h + 0100h × m
32
General PWM Timer Stop Source Select Register
GTPSR
00000000h
4007 8014h + 0100h × m
32
General PWM Timer Clear Source Select Register
GTCSR
00000000h
4007 8018h + 0100h × m
32
General PWM Timer Up Count Source Select Register
GTUPSR
00000000h
4007 801Ch + 0100h × m
32
General PWM Timer Down Count Source Select Register
GTDNSR
00000000h
4007 8020h + 0100h × m
32
General PWM Timer Input Capture Source Select Register A
GTICASR
00000000h
4007 8024h + 0100h × m
32
General PWM Timer Input Capture Source Select Register B
GTICBSR
00000000h
4007 8028h + 0100h × m
32
General PWM Timer Control Register
GTCR
00000000h
4007 802Ch + 0100h × m
32
General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
00000001h
4007 8030h + 0100h × m
32
General PWM Timer I/O Control Register
GTIOR
00000000h
4007 8034h + 0100h × m
32
General PWM Timer Interrupt Output Setting Register
GTINTAD
00000000h
4007 8038h + 0100h × m
32
General PWM Timer Status Register
GTST
00008000h
4007 803Ch + 0100h × m
32
General PWM Timer Buffer Enable Register
GTBER
00000000h
4007 8040h + 0100h × m
32
32
General PWM Timer Counter
GTCNT
00000000h
4007 8048h + 0100h × m
General PWM Timer Compare Capture Register A
GTCCRA
FFFFFFFFh*3
4007 804Ch + 0100h × m
32
General PWM Timer Compare Capture Register B
GTCCRB
FFFFFFFFh*3
4007 8050h + 0100h × m
32
General PWM Timer Compare Capture Register C
GTCCRC
FFFFFFFFh*3
4007 8054h + 0100h × m
32
General PWM Timer Compare Capture Register E
GTCCRE
FFFFFFFFh*3
4007 8058h + 0100h × m
32
General PWM Timer Compare Capture Register D
GTCCRD
FFFFFFFFh*3
4007 805Ch + 0100h × m
32
General PWM Timer Compare Capture Register F
GTCCRF
FFFFFFFFh*3
4007 8060h + 0100h × m
32
General PWM Timer Cycle Setting Register
GTPR
FFFFFFFFh*3
4007 8064h + 0100h × m
32
General PWM Timer Cycle Setting Buffer Register
GTPBR
FFFFFFFFh*3
4007 8068h + 0100h × m
32
General PWM Timer Dead Time Control Register
GTDTCR
00000000h
4007 8088h + 0100h × m
32
General PWM Timer Dead Time Value Register U
GTDVU
FFFFFFFFh*3
4007 808Ch + 0100h × m
32
Output Phase Switching Control Register
OPSCR
00000000h
4007 8FF0h
32
GPT32m (m = 0 to 3)
GPT16m (m = 4 to 9)
The reset value of GPT16m is 0000FFFFh.
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23.2.1
23. General PWM Timer (GPT)
General PWM Timer Write-Protection Register (GTWP)
Address(es): GPT32m.GTWP 4007 8000h + 0100h × m (m = 0 to 3),
GPT16m.GTWP 4007 8000h + 0100h × m (m = 4 to 9)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
WP
0
0
0
0
0
0
0
0
PRKEY[7:0]
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
WP
Register Write Disable
0: Write to the register enabled
1: Write to the register disabled.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
PRKEY[7:0]
GTWP Key Code
When A5h is written to these bits, the WP bits write is
permitted. These bits are read as 0.
R/W
b31 to b16
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The GTWP enables or disables writing to registers to prevent accidental modification. The following is a list of write
enabled or disabled registers:
GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTICASR, GTICBSR, GTCR, GTUDDTYC, GTIOR, GTINTAD,
GTST, GTBER, GTCNT, GTCCRA, GTCCRB, GTCCRC, GTCCRD, GTCCRE, GTCCRF, GTPR, GTPBR, GTDTCR,
GTDVU.
23.2.2
General PWM Timer Software Start Register (GTSTR)
Address(es): GPT32m.GTSTR 4007 8004h + 0100h × m (m = 0 to 3),
GPT16m.GTSTR 4007 8004h + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
The GTSTR starts the GTCNT counter operation for each channel n, where n = 0 to 9.
The GTSTR bit number represents the channel number. The GTSTR register is shared by all of the channels. The
GTCNT counter starts for the channel associated with the GTSTR bit where 1 is written. Writing 0 has no effect on the
status of the GTCNT counter and the value of the GTSTR register. For the association between GTSTR bit number and
channel number, see Figure 23.2.
CSTRTn bit (Channel n GTCNT Count Start) (n = 0 to 9)
The CSTRTn bit starts channel n of the GTCNT counter operation. Writing to the GTSTR.CSTRTn bit has no effect
unless GPTm.GTSSR.CSTRTn bit is set to 1 (n = 0 to 9, m = 320 to 323, 164 to 169).
The read data shows the counter status of each channel (GTCR.CST bit). Zero means the counter is stopped and 1 means
the counter is running.
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S3A1 User’s Manual
23.2.3
23. General PWM Timer (GPT)
General PWM Timer Software Stop Register (GTSTP)
Address(es): GPT32m.GTSTP 4007 8008h + 0100h × m (m = 0 to 3),
GPT16m.GTSTP 4007 8008h + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
1
1
1
1
1
1
CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
The GTSTP stops the GTCNT counter operation for each channel n, where n = 0 to 9.
The GTSTP bit number represents the channel number. Each channel of the GTSTP register is shared by all the channels.
The GTCNT counter stops for the channel associated with the GTSTP bit number where 1 is written. Writing 0 has no
effect on the status of the GTCNT counter and the value of GTSTP register.
For the association between the GTSTP bit number and a channel number, see Figure 23.2.
CSTOPx bit (Channel n GTCNT Count Stop) (n = 0 to 9)
The CSTOPx bit stops channel n GTCNT counter operation. Writing to the GTSTP.CSTOPn bit has no effect unless the
GPT32m.GTPSR.CSTOPn bit is set to 1 (n = 0 to 9, m = 0 to 9). The read data shows the counter status of each channel
(invert of GTCR.CST bit). Zero means the counter is running and 1 means the counter stops.
23.2.4
General PWM Timer Software Clear Register (GTCLR)
Address(es): GPT32m.GTCLR 4007 800Ch + 0100h × m (m = 0 to 3),
GPT16m.GTCLR 4007 800Ch + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
CCLR
9
CCLR
8
CCLR
7
CCLR
6
CCLR
5
CCLR
4
CCLR
3
CCLR
2
CCLR
1
CCLR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The GTCLR is a write-only register that clears the GTCNT counter operation for each channel x, where x = 0 to 9.
The GTCLR bit number represents the channel number. Each channel of the GTCLR register is shared by all the
channels. The GTCNT counter is cleared for the channel associated with the GTCLR bit number where 1 is written.
Writing 0 has no effect on the status of the GTCNT counter. For the association between the GTCLR bit number and a
channel number, see Figure 23.2.
CCLRn bit (Channel n GTCNT Count Clear) (n = 0 to 9)
Channel n of the GTCNT counter value is cleared on writing 1 to the CCLRn bit. This bit is read as 0.
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Oct 29, 2018
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S3A1 User’s Manual
23.2.5
23. General PWM Timer (GPT)
General PWM Timer Start Source Select Register (GTSSR)
Address(es): GPT32m.GTSSR 4007 8010h + 0100h × m (m = 0 to 3),
GPT16m.GTSSR 4007 8010h + 0100h × m (m = 4 to 9)
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
SSELC SSELC SSELC SSELC SSELC SSELC SSELC SSELC
H
G
F
E
D
C
B
A
CSTRT
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Value after reset:
SSCBF SSCBF SSCBR SSCBR SSCAF SSCAF SSCAR SSCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
0
0
0
0
0
0
0
SSGTR SSGTR SSGTR SSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSGTRGAR
GTETRGA Pin Rising Input Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTETRGA
input
1: Counter start enabled on the rising edge of GTETRGA
input.
R/W
b1
SSGTRGAF
GTETRGA Pin Falling Input Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTETRGA
input
1: Counter start enabled on the falling edge of GTETRGA
input.
R/W
b2
SSGTRGBR
GTETRGB Pin Rising Input Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTETRGB
input
1: Counter start enabled on the rising edge of GTETRGB
input.
R/W
b3
SSGTRGBF
GTETRGB Pin Falling Input Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTETRGB
input
1: Counter start enabled on the falling edge of GTETRGB
input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
SSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTIOCA
input when GTIOCB input is 0
1: Counter start enabled on the rising edge of GTIOCA
input when GTIOCB input is 0.
R/W
b9
SSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTIOCA
input when GTIOCB input is 1
1: Counter start enabled on the rising edge of GTIOCA
input when GTIOCB input is 1.
R/W
b10
SSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTIOCA
input when GTIOCB input is 0
1: Counter start enabled on the falling edge of GTIOCA
input when GTIOCB input is 0.
R/W
b11
SSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTIOCA
input when GTIOCB input is 1
1: Counter start enabled on the falling edge of GTIOCA
input when GTIOCB input is 1.
R/W
b12
SSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTIOCB
input when GTIOCA input is 0
1: Counter start enabled on the rising edge of GTIOCB
input when GTIOCA input is 0.
R/W
b13
SSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTIOCB
input when GTIOCA input is 1
1: Counter start enabled on the rising edge of GTIOCB
input when GTIOCA input is 1.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b14
SSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTIOCB
input when GTIOCA input is 0
1: Counter start enabled on the falling edge of GTIOCB
input when GTIOCA input is 0.
R/W
b15
SSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTIOCB
input when GTIOCA input is 1
1: Counter start enabled on the falling edge of GTIOCB
input when GTIOCA input is 1.
R/W
b16
SSELCA
ELC_GPTA Event Source Counter
Start Enable
0: Counter start disabled at the ELC_GPTA input
1: Counter start enabled at the ELC_GPTA input.
R/W
b17
SSELCB
ELC_GPTB Event Source Counter
Start Enable
0: Counter start disabled at the ELC_GPTB input
1: Counter start enabled at the ELC_GPTB input.
R/W
b18
SSELCC
ELC_GPTC Event Source Counter
Start Enable
0: Counter start disabled at the ELC_GPTC input
1: Counter start enabled at the ELC_GPTC input.
R/W
b19
SSELCD
ELC_GPTD Event Source Counter
Start Enable
0: Counter start disabled at the ELC_GPTD input
1: Counter start enabled at the ELC_GPTD input.
R/W
b20
SSELCE
ELC_GPTE Event Source Counter
Start Enable
0: Counter start disabled at the ELC_GPTE input
1: Counter start enabled at the ELC_GPTE input.
R/W
b21
SSELCF
ELC_GPTF Event Source Counter
Start Enable
0: Counter start disabled at the ELC_GPTF input
1: Counter start enabled at the ELC_GPTF input.
R/W
b22
SSELCG
ELC_GPTG Event Source Counter
Start Enable
0: Counter start disabled at the ELC_GPTG input
1: Counter start enabled at the ELC_GPTG input.
R/W
b23
SSELCH
ELC_GPTH Event Source Counter
Start Enable
0: Counter start disabled at the ELC_GPTH input
1: Counter start enabled at the ELC_GPTH input.
R/W
b30 to b24 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Start
Enable
0: Counter start disabled by the GTSTR register
1: Counter start enabled by the GTSTR register.
R/W
CSTRT
The GTSSR sets the source to start the GTCNT counter.
SSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Start Enable)
The SSGTRGAR bit enables or disables the GTCNT counter start on the rising edge of GTETRGA pin input.
SSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Start Enable)
The SSGTRGAF bit enables or disables the GTCNT counter start on the falling edge of GTETRGA pin input.
SSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Start Enable)
The SSGTRGBR bit enables or disables the GTCNT counter start on the rising edge of GTETRGB pin input.
SSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Start Enable)
The SSGTRGBF bit enables or disables the GTCNT counter start on the falling edge of GTETRGB pin input.
SSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable)
The SSCARBL bit enables or disables the GTCNT counter start on the rising edge of GTIOCA pin input, when GTIOCB
input is 0.
SSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable)
The SSCARBH bit enables or disables the GTCNT counter start on the rising edge of GTIOCA pin input, when
GTIOCB input is 1.
SSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable)
The SSCAFBL bit enables or disables the GTCNT counter start on the falling edge of GTIOCA pin input, when
GTIOCB input is 0.
SSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable)
The SSCAFBH bit enables or disables the GTCNT counter start on the falling edge of GTIOCA pin input, when
GTIOCB input is 1.
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23. General PWM Timer (GPT)
SSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable)
The SSCBRAL bit enables or disables the GTCNT counter start on the rising edge of GTIOCB pin input, when GTIOCA
input is 0.
SSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable)
The SSCBRAH bit enables or disables the GTCNT counter start on the rising edge of GTIOCB pin input, when
GTIOCA input is 1.
SSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable)
The SSCBFAL bit enables or disables the GTCNT counter start on the falling edge of GTIOCB pin input, when
GTIOCA input is 0.
SSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable)
The SSCBFAH bit enables or disables the GTCNT counter start on the falling edge of GTIOCB pin input, when
GTIOCA input is 1.
SSELCm bit (ELC_GPTm Event Source Counter Start Enable) (m = A to H)
The SSELCm bit enables or disables the GTCNT counter start at the ELC_GPTm event input.
CSTRT bit (Software Source Counter Start Enable)
The CSTRT bit enables or disables the GTCNT counter start by GTSTR register.
23.2.6
General PWM Timer Stop Source Select Register (GTPSR)
Address(es): GPT32m.GTPSR 4007 8014h + 0100h × m (m = 0 to 3),
GPT16m.GTPSR 4007 8014h + 0100h × m (m = 4 to 9)
b31
b30
b29
b28
b27
b26
b25
b24
CSTOP
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
Value after reset:
PSCBF PSCBF PSCBR PSCBR PSCAF PSCAF PSCAR PSCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
0
0
0
0
0
0
0
b23
b22
b21
b20
b19
b18
b17
b16
PSELC PSELC PSELC PSELC PSELC PSELC PSELC PSELC
H
G
F
E
D
C
B
A
—
—
—
—
0
0
0
0
0
0
0
0
b3
b2
b1
b0
PSGTR PSGTR PSGTR PSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PSGTRGAR
GTETRGA Pin Rising Input Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTETRGA
input
1: Counter stop enabled on the rising edge of GTETRGA
input.
R/W
b1
PSGTRGAF
GTETRGA Pin Falling Input Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTETRGA
input
1: Counter stop enabled on the falling edge of GTETRGA
input.
R/W
b2
PSGTRGBR
GTETRGB Pin Rising Input Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTETRGB
input
1: Counter stop enabled on the rising edge of GTETRGB
input.
R/W
b3
PSGTRGBF
GTETRGB Pin Falling Input Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTETRGB
input
1: Counter stop enabled on the falling edge of GTETRGB
input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 453 of 1619
S3A1 User’s Manual
23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b8
PSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTIOCA
input when GTIOCB input is 0
1: Counter stop enabled on the rising edge of GTIOCA input
when GTIOCB input is 0.
R/W
b9
PSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTIOCA
input when GTIOCB input is 1
1: Counter stop enabled on the rising edge of GTIOCA input
when GTIOCB input is 1.
R/W
b10
PSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTIOCA
input when GTIOCB input is 0
1: Counter stop enabled on the falling edge of GTIOCA
input when GTIOCB input is 0.
R/W
b11
PSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTIOCA
input when GTIOCB input is 1
1: Counter stop enabled on the falling edge of GTIOCA
input when GTIOCB input is 1.
R/W
b12
PSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTIOCB
input when GTIOCA input is 0
1: Counter stop enabled on the rising edge of GTIOCB input
when GTIOCA input is 0.
R/W
b13
PSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTIOCB
input when GTIOCA input is 1
1: Counter stop enabled on the rising edge of GTIOCB input
when GTIOCA input is 1.
R/W
b14
PSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTIOCB
input when GTIOCA input is 0
1: Counter stop enabled on the falling edge of GTIOCB
input when GTIOCA input is 0.
R/W
b15
PSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTIOCB
input when GTIOCA input is 1
1: Counter stop enabled on the falling edge of GTIOCB
input when GTIOCA input is 1.
R/W
b16
PSELCA
ELC_GPTA Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTA event input
1: Counter stop enabled at the ELC_GPTA event input.
R/W
b17
PSELCB
ELC_GPTB Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTB event input
1: Counter stop enabled at the ELC_GPTB event input.
R/W
b18
PSELCC
ELC_GPTC Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTC event input
1: Counter stop enabled at the ELC_GPTC event input.
R/W
b19
PSELCD
ELC_GPTD Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTD event input
1: Counter stop enabled at the ELC_GPTD event input.
R/W
b20
PSELCE
ELC_GPTE Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTE event input
1: Counter stop enabled at the ELC_GPTE event input.
R/W
b21
PSELCF
ELC_GPTF Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTF event input
1: Counter stop enabled at the ELC_GPTF event input.
R/W
b22
PSELCG
ELC_GPTG Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTG event input
1: Counter stop enabled at the ELC_GPTG event input.
R/W
b23
PSELCH
ELC_GPTH Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTH event input
1: Counter stop enabled at the ELC_GPTH event input.
R/W
b30 to b24 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Stop
Enable
0: Counter stop disabled by the GTSTP register
1: Counter stop enabled by the GTSTP register.
R/W
CSTOP
GTPSR sets the source to stop the GTCNT counter.
PSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Stop Enable)
The PSGTRGAR bit enables or disables the GTCNT counter stop on the rising edge of the GTETRGA pin input.
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23. General PWM Timer (GPT)
PSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Stop Enable)
The PSGTRGAF bit enables or disables the GTCNT counter stop on the falling edge of the GTETRGA pin input.
PSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Stop Enable)
The PSGTRGBR bit enables or disables the GTCNT counter stop on the rising edge of the GTETRGB pin input.
PSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Stop Enable)
The PSGTRGBF bit enables or disables the GTCNT counter stop on the falling edge of the GTETRGB pin input.
PSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable)
The PSCARBL bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCA pin input, when
GTIOCB input is 0.
PSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable)
The PSCARBH bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCA pin input, when
GTIOCB input is 1.
PSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable)
The PSCAFBL bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCA pin input, when
GTIOCB input is 0.
PSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable)
The PSCAFBH bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCA pin input, when
GTIOCB input is 1.
PSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable)
The PSCBRAL bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCB pin input, when
GTIOCA input is 0.
PSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable)
The PSCBRAH bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCB pin input, when
GTIOCA input is 1.
PSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable)
The PSCBFAL bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCB pin input, when
GTIOCA input is 0.
PSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable)
The PSCBFAH bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCB pin input, when
GTIOCA input is 1.
PSELCm bit (ELC_GPTm Event Source Counter Stop Enable) (m = A to H)
The PSELCm bit enables or disables the GTCNT counter stop at the ELC_GPTm event input.
CSTOP bit (Software Source Counter Stop Enable)
The CSTOP bit enables or disables the GTCNT counter stop by the GTSTP register.
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23.2.7
23. General PWM Timer (GPT)
General PWM Timer Clear Source Select Register (GTCSR)
Address(es): GPT32m.GTCSR 4007 8018h + 0100h × m (m = 0 to 3),
GPT16m.GTCSR 4007 8018h + 0100h × m (m = 4 to 9)
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
CSELC CSELC CSELC CSELC CSELC CSELC CSELC CSELC
H
G
F
E
D
C
B
A
CCLR
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Value after reset:
CSCBF CSCBF CSCBR CSCBR CSCAF CSCAF CSCAR CSCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
0
0
0
0
0
0
0
CSGTR CSGTR CSGTR CSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CSGTRGAR
GTETRGA Pin Rising Input Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of the
GTETRGA input
1: Counter clear enabled on the rising edge of the
GTETRGA input.
R/W
b1
CSGTRGAF
GTETRGA Pin Falling Input Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of the
GTETRGA input
1: Counter clear enabled on the falling edge of the
GTETRGA input.
R/W
b2
CSGTRGBR
GTETRGB Pin Rising Input Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of the
GTETRGB input
1: Counter clear enabled on the rising edge of the
GTETRGB input.
R/W
b3
CSGTRGBF
GTETRGB Pin Falling Input Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of the
GTETRGB input
1: Counter clear enabled on the falling edge of the
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
CSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of the GTIOCA
input when GTIOCB input is 0
1: Counter clear enabled on the rising edge of the GTIOCA
input when GTIOCB input is 0.
R/W
b9
CSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of the GTIOCA
input when GTIOCB input is 1
1: Counter clear enabled on the rising edge of the GTIOCA
input when GTIOCB input is 1.
R/W
b10
CSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of the GTIOCA
input when GTIOCB input is 0
1: Counter clear enabled on the falling edge of the GTIOCA
input when GTIOCB input is 0.
R/W
b11
CSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of the GTIOCA
input when GTIOCB input is 1
1: Counter clear enabled on the falling edge of the GTIOCA
input when GTIOCB input is 1.
R/W
b12
CSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of the GTIOCB
input when GTIOCA input is 0
1: Counter clear enabled on the rising edge of the GTIOCB
input when GTIOCA input is 0.
R/W
b13
CSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of the GTIOCB
input when GTIOCA input is 1
1: Counter clear enabled on the rising edge of the GTIOCB
input when GTIOCA input is 1.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b14
CSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of the GTIOCB
input when GTIOCA input is 0
1: Counter clear enabled on the falling edge of the GTIOCB
input when GTIOCA input is 0.
R/W
b15
CSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of the GTIOCB
input when GTIOCA input is 1
1: Counter clear enabled on the falling edge of the GTIOCB
input when GTIOCA input is 1.
R/W
b16
CSELCA
ELC_GPTA Event Source Counter
Clear Enable
0: Counter clear disabled at the ELC_GPTA input
1: Counter clear enabled at the ELC_GPTA input.
R/W
b17
CSELCB
ELC_GPTB Event Source Counter
Clear Enable
0: Counter clear disabled at the ELC_GPTB input
1: Counter clear enabled at the ELC_GPTB input.
R/W
b18
CSELCC
ELC_GPTC Event Source Counter
Clear Enable
0: Counter clear disabled at the ELC_GPTC input
1: Counter clear enabled at the ELC_GPTC input.
R/W
b19
CSELCD
ELC_GPTD Event Source Counter
Clear Enable
0: Counter clear disabled at the ELC_GPTD input
1: Counter clear enabled at the ELC_GPTD input.
R/W
b20
CSELCE
ELC_GPTE Event Source Counter
Clear Enable
0: Counter clear disabled at the ELC_GPTE input
1: Counter clear enabled at the ELC_GPTE input.
R/W
b21
CSELCF
ELC_GPTF Event Source Counter
Clear Enable
0: Counter clear disabled at the ELC_GPTF input
1: Counter clear enabled at the ELC_GPTF input.
R/W
b22
CSELCG
ELC_GPTG Event Source Counter
Clear Enable
0: Counter clear disabled at the ELC_GPTG input
1: Counter clear enabled at the ELC_GPTG input.
R/W
b23
CSELCH
ELC_GPTH Event Source Counter
Clear Enable
0: Counter clear disabled at the ELC_GPTH input
1: Counter clear enabled at the ELC_GPTH input.
R/W
b30 to b24 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Clear
Enable
0: Counter clear disabled by the GTCLR register
1: Counter clear enabled by the GTCLR register.
R/W
CCLR
The GTCSR sets the source to clear the GTCNT counter.
CSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Clear Enable)
The CSGTRGAR bit enables or disables the GTCNT counter clear on the rising edge of the GTETRGA pin input.
CSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Clear Enable)
The CSGTRGAF bit enables or disables the GTCNT counter clear on the falling edge of the GTETRGA pin input.
CSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Clear Enable)
The CSGTRGBR bit enables or disables the GTCNT counter clear on the rising edge of the GTETRGB pin input.
CSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Clear Enable)
The CSGTRGBF bit enables or disables the GTCNT counter clear on the falling edge of the GTETRGB pin input.
CSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable)
The CSCARBL bit enables or disables the GTCNT counter clear on the rising edge of the GTIOCA pin input, when
GTIOCB input is 0.
CSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable)
The CSCARBH bit enables or disables the GTCNT counter clear on the rising edge of the GTIOCA pin input, when the
GTIOCB input is 1.
CSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable)
The CSCAFBL bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 0.
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23. General PWM Timer (GPT)
CSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable)
The CSCAFBH bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 1.
CSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable)
The CSCBRAL bit enables or disables the GTCNT counter clear on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 0.
CSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable)
The CSCBRAH bit enables or disables the GTCNT counter clear on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 1.
CSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable)
The CSCBFAL bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 0.
CSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable)
The CSCBFAH bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 1.
CSELCm bit (ELC_GPTm Event Source Counter Clear Enable) (m = A to H)
The CSELCm bit enables or disables the GTCNT counter clear at the ELC_GPTm event input.
CCLR bit (Software Source Counter Clear Enable)
The CCLR bit enables or disables the GTCNT counter clear by the GTCLR register.
23.2.8
General PWM Timer Up Count Source Select Register (GTUPSR)
Address(es): GPT32m.GTUPSR 4007 801Ch + 0100h × m (m = 0 to 3),
GPT16m.GTUPSR 4007 801Ch + 0100h × m (m = 4 to 9)
b31
Value after reset:
b30
b29
b28
b27
b26
b25
b24
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
USCBF USCBF USCBR USCBR USCAF USCAF USCAR USCAR
AH
AL
AH
AL
BH
BL
BH
BL
Value after reset:
b23
USELC USELC USELC USELC USELC USELC USELC USELC
H
G
F
E
D
C
B
A
0
0
0
0
0
0
0
0
USGTR USGTR USGTR USGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
USGTRGAR
GTETRGA Pin Rising Input Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of the
GTETRGA input
1: Counter count up enabled on the rising edge of the
GTETRGA input.
R/W
b1
USGTRGAF
GTETRGA Pin Falling Input Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of the
GTETRGA input
1: Counter count up enabled on the falling edge of the
GTETRGA input.
R/W
b2
USGTRGBR
GTETRGB Pin Rising Input Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of the
GTETRGB input
1: Counter count up enabled on the rising edge of the
GTETRGB input.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b3
USGTRGBF
GTETRGB Pin Falling Input Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of the
GTETRGB input
1: Counter count up enabled on the falling edge of the
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
USCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of the
GTIOCA input when the GTIOCB input is 0
1: Counter count up enabled on the rising edge of the
GTIOCA input when the GTIOCB input is 0.
R/W
b9
USCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of the
GTIOCA input when the GTIOCB input is 1
1: Counter count up enabled on the rising edge of the
GTIOCA input when the GTIOCB input is 1.
R/W
b10
USCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of the
GTIOCA input when the GTIOCB input is 0
1: Counter count up enabled on the falling edge of the
GTIOCA input when the GTIOCB input is 0.
R/W
b11
USCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of the
GTIOCA input when the GTIOCB input is 1
1: Counter count up enabled on the falling edge of the
GTIOCA input when the GTIOCB input is 1.
R/W
b12
USCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of the
GTIOCB input when the GTIOCA input is 0
1: Counter count up enabled on the rising edge of the
GTIOCB input when the GTIOCA input is 0.
R/W
b13
USCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of the
GTIOCB input when the GTIOCA input is 1
1: Counter count up enabled on the rising edge of the
GTIOCB input when the GTIOCA input is 1.
R/W
b14
USCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of the
GTIOCB input when the GTIOCA input is 0
1: Counter count up enabled on the falling edge of the
GTIOCB input when the GTIOCA input is 0.
R/W
b15
USCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of the
GTIOCB input when the GTIOCA input is 1
1: Counter count up enabled on the falling edge of the
GTIOCB input when the GTIOCA input is 1.
R/W
b16
USELCA
ELC_GPTA Event Source Counter
Count Up Enable
0: Counter count up disabled at the ELC_GPTA input
1: Counter count up enabled at the ELC_GPTA input.
R/W
b17
USELCB
ELC_GPTB Event Source Counter
Count Up Enable
0: Counter count up disabled at the ELC_GPTB input
1: Counter count up enabled at the ELC_GPTB input.
R/W
b18
USELCC
ELC_GPTC Event Source Counter
Count Up Enable
0: Counter count up disabled at the ELC_GPTC input
1: Counter count up enabled at the ELC_GPTC input.
R/W
b19
USELCD
ELC_GPTD Event Source Counter
Count Up Enable
0: Counter count up disabled at the ELC_GPTD input
1: Counter count up enabled at the ELC_GPTD input.
R/W
b20
USELCE
ELC_GPTE Event Source Counter
Count Up Enable
0: Counter count up disabled at the ELC_GPTE input
1: Counter count up enabled at the ELC_GPTE input.
R/W
b21
USELCF
ELC_GPTF Event Source Counter
Count Up Enable
0: Counter count up disabled at the ELC_GPTF input
1: Counter count up is enabled at the ELC_GPTF input
R/W
b22
USELCG
ELC_GPTG Event Source Counter
Count Up Enable
0: Counter count up disabled at the ELC_GPTG input
1: Counter count up is enabled at the ELC_GPTG input
R/W
b23
USELCH
ELC_GPTH Event Source Counter
Count Up Enable
0: Counter count up disabled at the ELC_GPTH input
1: Counter count up enabled at the ELC_GPTH input
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
The GTUPSR sets the source to count up the GTCNT counter.
When at least one bit in the GTUPSR register is set to 1, the GTCNT counter is counted up by the source that is set to 1
in this register, but the GTCNT counter set by GTCR.TPCS does not perform the count.
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23. General PWM Timer (GPT)
USGTRGAR bit (GTETRGA Pin Rising Input Source Counter Count Up Enable)
The USGTRGAR bit enables or disables the GTCNT counter count up on the rising edge of the GTETRGA pin input.
USGTRGAF bit (GTETRGA Pin Falling Input Source Counter Count Up Enable)
The USGTRGAF bit enables or disables the GTCNT counter count up on the falling edge of the GTETRGA pin input.
USGTRGBR bit (GTETRGB Pin Rising Input Source Counter Count Up Enable)
The USGTRGBR bit enables or disables the GTCNT counter count up on the rising edge of the GTETRGB pin input.
USGTRGBF bit (GTETRGB Pin Falling Input Source Counter Count Up Enable)
The USGTRGBF bit enables or disables the GTCNT counter count up on the falling edge of the GTETRGB pin input.
USCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable)
The USCARBL bit enables or disables the GTCNT counter count up on the rising edge of the GTIOCA pin input, when
the GTIOCB input is 0.
USCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable)
The USCARBH bit enables or disables the GTCNT counter count up on the rising edge of the GTIOCA pin input, when
the GTIOCB input is 1.
USCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable)
The USCAFBL bit enables or disables the GTCNT counter count up on the falling edge of the GTIOCA pin input, when
the GTIOCB input is 0.
USCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable)
The USCAFBH bit enables or disables GTCNT counter count up on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 1.
USCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable)
The USCBRAL bit enables or disables the GTCNT counter count up on the rising edge of the GTIOCB pin input, when
the GTIOCA input is 0.
USCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable)
The USCBRAH bit enables or disables the GTCNT counter count up on the rising edge of the GTIOCB pin input, when
the GTIOCA input is 1.
USCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable)
The USCBFAL bit enables or disables the GTCNT counter count up on the falling edge of the GTIOCB pin input, when
the GTIOCA input is 0.
USCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable)
The USCBFAH bit enables or disables the GTCNT counter count up on the falling edge of the GTIOCB pin input, when
the GTIOCA input is 1.
USELCm bit (ELC_GPTm Event Source Counter Count Up Enable) (m = A to H)
The USELCm bit enables or disables the GTCNT counter count up at the ELC_GPTm event input.
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S3A1 User’s Manual
23.2.9
23. General PWM Timer (GPT)
General PWM Timer Down Count Source Select Register (GTDNSR)
Address(es): GPT32m.GTDNSR 4007 8020h + 0100h × m (m = 0 to 3),
GPT16m.GTDNSR 4007 8020h + 0100h × m (m = 4 to 9)
b31
Value after reset:
b30
b29
b28
b27
b26
b25
b24
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
DSCBF DSCBF DSCBR DSCBR DSCAF DSCAF DSCAR DSCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
b23
DSELC DSELC DSELC DSELC DSELC DSELC DSELC DSELC
H
G
F
E
D
C
B
A
0
0
0
0
0
0
0
DSGTR DSGTR DSGTR DSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DSGTRGAR
GTETRGA Pin Rising Input Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of the
GTETRGA input
1: Counter count down enabled on the rising edge of
GTETRGA input.
R/W
b1
DSGTRGAF
GTETRGA Pin Falling Input Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of the
GTETRGA input
1: Counter count down enabled on the falling edge of
GTETRGA input.
R/W
b2
DSGTRGBR
GTETRGB Pin Rising Input Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of the
GTETRGB input
1: Counter count down enabled on the rising edge of
GTETRGB input.
R/W
b3
DSGTRGBF
GTETRGB Pin Falling Input Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of the
GTETRGB input
1: Counter count down enabled on the falling edge of the
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
DSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of the
GTIOCA input when the GTIOCB input is 0
1: Counter count down enabled on the rising edge of the
GTIOCA input when the GTIOCB input is 0.
R/W
b9
DSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of the
GTIOCA input when the GTIOCB input is 1
1: Counter count down enabled on the rising edge of the
GTIOCA input when the GTIOCB input is 1.
R/W
b10
DSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of the
GTIOCA input when the GTIOCB input is 0
1: Counter count down enabled on the falling edge of
GTIOCA input when GTIOCB input is 0.
R/W
b11
DSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of the
GTIOCA input when the GTIOCB input is 1
1: Counter count down enabled on the falling edge of the
GTIOCA input when the GTIOCB input is 1.
R/W
b12
DSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of the
GTIOCB input when the GTIOCA input is 0
1: Counter count down enabled on the rising edge of the
GTIOCB input when the GTIOCA input is 0.
R/W
b13
DSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of the
GTIOCB input when the GTIOCA input is 1
1: Counter count down enabled on the rising edge of the
GTIOCB input when the GTIOCA input is 1.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b14
DSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of the
GTIOCB input when the GTIOCA input is 0
1: Counter count down enabled on the falling edge of the
GTIOCB input when the GTIOCA input is 0.
R/W
b15
DSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of the
GTIOCB input when the GTIOCA input is 1
1: Counter count down enabled on the falling edge of the
GTIOCB input when the GTIOCA input is 1.
R/W
b16
DSELCA
ELC_GPTA Event Source Counter
Count Down Enable
0: Counter count down disabled at the ELC_GPTA input
1: Counter count down enabled at the ELC_GPTA input.
R/W
b17
DSELCB
ELC_GPTB Event Source Counter
Count Down Enable
0: Counter count down disabled at the ELC_GPTB input
1: Counter count down enabled at the ELC_GPTB input.
R/W
b18
DSELCC
ELC_GPTC Event Source Counter
Count Down Enable
0: Counter count down disabled at the ELC_GPTC input
1: Counter count down enabled at the ELC_GPTC input.
R/W
b19
DSELCD
ELC_GPTD Event Source Counter
Count Down Enable
0: Counter count down disabled at the ELC_GPTD input
1: Counter count down enabled at the ELC_GPTD input.
R/W
b20
DSELCE
ELC_GPTE Event Source Counter
Count Down Enable
0: Counter count down disabled at the ELC_GPTE input
1: Counter count down enabled at the ELC_GPTE input.
R/W
b21
DSELCF
ELC_GPTF Event Source Counter
Count Down Enable
0: Counter count down disabled at the ELC_GPTF input
1: Counter count down enabled at the ELC_GPTF input.
R/W
b22
DSELCG
ELC_GPTG Event Source Counter
Count Down Enable
0: Counter count down disabled at the ELC_GPTG input
1: Counter count down enabled at the ELC_GPTG input.
R/W
b23
DSELCH
ELC_GPTH Event Source Counter
Count Down Enable
0: Counter count down disabled at the ELC_GPTH input
1: Counter count down enabled at the ELC_GPTH input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
The GTDNSR sets the source to count down the GTCNT counter.
When at least one bit in the GTDNSR register is set to 1, the GTCNT counter is counted down by the source that is set to
1 in this register, but the GTCNT counter set by GTCR.TPCS does not perform the count.
DSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Count Down Enable)
The DSGTRGAR bit enables or disables the GTCNT counter count down on the rising edge of the GTETRGA pin input.
DSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Count Down Enable)
The DSGTRGAF bit enables or disables the GTCNT counter count down on the falling edge of the GTETRGA pin
input.
DSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Count Down Enable)
The DSGTRGBR bit enables or disables the GTCNT counter count down on the rising edge of the GTETRGB pin input.
DSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Count Down Enable)
The DSGTRGBF bit enables or disables the GTCNT counter count down on the falling edge of the GTETRGB pin input.
DSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down
Enable)
The DSCARBL bit enables or disables the GTCNT counter count down on the rising edge of the GTIOCA pin input,
when GTIOCB input is 0.
DSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down
Enable)
The DSCARBH bit enables or disables the GTCNT counter count down on the rising edge of the GTIOCA pin input,
when GTIOCB input is 1.
DSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down
Enable)
The DSCAFBL bit enables or disables the GTCNT counter count down on the falling edge of the GTIOCA pin input,
when GTIOCB input is 0.
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23. General PWM Timer (GPT)
DSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down
Enable)
The DSCAFBH bit enables or disables the GTCNT counter count down on the falling edge of the GTIOCA pin input,
when the GTIOCB input is 1.
DSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down
Enable)
The DSCBRAL bit enables or disables the GTCNT counter count down on the rising edge of the GTIOCB pin input,
when the GTIOCA input is 0.
DSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down
Enable)
The DSCBRAH bit enables or disables the GTCNT counter count down on the rising edge of the GTIOCB pin input,
when the GTIOCA input is 1.
DSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down
Enable)
The DSCBFAL bit enables or disables the GTCNT counter count down on the falling edge of the GTIOCB pin input,
when the GTIOCA input is 0.
DSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down
Enable)
The DSCBFAL bit enables or disables the GTCNT counter count down on the falling edge of the GTIOCB pin input,
when the GTIOCA input is 1.
DSELCm bit (ELC_GPTm Event Source Counter Count Down Enable) (m = A to H)
The DSELCm bit enables or disables the GTCNT counter count down at the ELC_GPTm event input.
23.2.10
General PWM Timer Input Capture Source Select Register A (GTICASR)
Address(es): GPT32m.GTICASR 4007 8024h + 0100h × m (m = 0 to 3),
GPT16m.GTICASR 4007 8024h + 0100h × m (m = 4 to 9)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
ASCBF ASCBF ASCBR ASCBR ASCAF ASCAF ASCAR ASCAR
AH
AL
AH
AL
BH
BL
BH
BL
Value after reset:
0
0
0
0
0
0
0
0
b23
b22
b21
b20
b19
b18
b17
b16
ASELC ASELC ASELC ASELC ASELC ASELC ASELC ASELC
H
G
F
E
D
C
B
A
—
—
—
—
0
0
0
0
0
0
0
0
b3
b2
b1
b0
ASGTR ASGTR ASGTR ASGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ASGTRGAR
GTETRGA Pin Rising Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of the
GTETRGA input
1: GTCCRA input capture enabled on the rising edge of the
GTETRGA input.
R/W
b1
ASGTRGAF
GTETRGA Pin Falling Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
the GTETRGA input
1: GTCCRA input capture enabled on the falling edge of the
GTETRGA input.
R/W
b2
ASGTRGBR
GTETRGB Pin Rising Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of the
GTETRGB input
1: GTCCRA input capture enabled on the rising edge of the
GTETRGB input.
R/W
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S3A1 User’s Manual
23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b3
ASGTRGBF
GTETRGB Pin Falling Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
the GTETRGB input
1: GTCCRA input capture enabled on the falling edge of the
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
ASCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of the
GTIOCA input when the GTIOCB input is 0
1: GTCCRA input capture enabled on the rising edge of the
GTIOCA input when the GTIOCB input is 0.
R/W
b9
ASCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of the
GTIOCA input when the GTIOCB input is 1
1: GTCCRA input capture enabled on the rising edge of the
GTIOCA input when the GTIOCB input is 1.
R/W
b10
ASCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
the GTIOCA input when the GTIOCB input is 0
1: GTCCRA input capture enabled on the falling edge of the
GTIOCA input when the GTIOCB input is 0.
R/W
b11
ASCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
the GTIOCA input when the GTIOCB input is 1
1: GTCCRA input capture enabled on the falling edge of the
GTIOCA input when the GTIOCB input is 1.
R/W
b12
ASCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of the
GTIOCB input when the GTIOCA input is 0
1: GTCCRA input capture enabled on the rising edge of the
GTIOCB input when the GTIOCA input is 0.
R/W
b13
ASCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of the
GTIOCB input when the GTIOCA input is 1
1: GTCCRA input capture enabled on the rising edge of the
GTIOCB input when the GTIOCA input is 1.
R/W
b14
ASCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
the GTIOCB input when the GTIOCA input is 0
1: GTCCRA input capture enabled on the falling edge of the
GTIOCB input when the GTIOCA input is 0.
R/W
b15
ASCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
the GTIOCB input when the GTIOCA input is 1
1: GTCCRA input capture enabled on the falling edge of the
GTIOCB input when the GTIOCA input is 1.
R/W
b16
ASELCA
ELC_GPTA Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at the ELC_GPTA input
1: GTCCRA input capture enabled at the ELC_GPTA input.
R/W
b17
ASELCB
ELC_GPTB Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at the ELC_GPTB input
1: GTCCRA input capture enabled at the ELC_GPTB input.
R/W
b18
ASELCC
ELC_GPTC Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at the ELC_GPTC input
1: GTCCRA input capture enabled at the ELC_GPTC input.
R/W
b19
ASELCD
ELC_GPTD Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at the ELC_GPTD input
1: GTCCRA input capture enabled at the ELC_GPTD input.
R/W
b20
ASELCE
ELC_GPTE Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at the ELC_GPTE input
1: GTCCRA input capture enabled at the ELC_GPTE input.
R/W
b21
ASELCF
ELC_GPTF Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at the ELC_GPTF input
1: GTCCRA input capture enabled at the ELC_GPTF input.
R/W
b22
ASELCG
ELC_GPTG Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at the ELC_GPTG input R/W
1: GTCCRA input capture enabled at the ELC_GPTG input.
b23
ASELCH
ELC_GPTH Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at the ELC_GPTH input
1: GTCCRA input capture enabled at the ELC_GPTH input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
GTICASR sets the source of input capture for GTCCRA.
R01UM0010EU0120 Rev.1.20
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23. General PWM Timer (GPT)
ASGTRGAR bit (GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable)
The ASGTRGAR bit enables or disables input capture for GTCCRA on the rising edge of the GTETRGA pin input.
ASGTRGAF bit (GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable)
The ASGTRGAF bit enables or disables input capture for GTCCRA on the falling edge of the GTETRGA pin input.
ASGTRGBR bit (GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable)
The ASGTRGBR bit enables or disables input capture for GTCCRA on the rising edge of the GTETRGB pin input.
ASGTRGBF bit (GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable)
The ASGTRGBF bit enables or disables input capture for GTCCRA on the falling edge of the GTETRGB pin input.
ASCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture
Enable)
The ASCARBL bit enables or disables input capture for GTCCRA on the rising edge of GTIOCA pin input, when the
GTIOCB input is 0.
ASCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture
Enable)
The ASCARBH bit enables or disables input capture for GTCCRA on the rising edge of GTIOCA pin input, when the
GTIOCB input is 1.
ASCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture
Enable)
The ASCAFBL bit enables or disables input capture for GTCCRA on the falling edge of GTIOCA pin input, when the
GTIOCB input is 0.
ASCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture
Enable)
The ASCAFBH bit enables or disables input capture for GTCCRA on the falling edge of the GTIOCA pin input, when
the GTIOCB input is 1.
ASCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture
Enable)
The ASCBRAL bit enables or disables input capture for GTCCRA on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 0.
ASCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture
Enable)
The ASCBRAH bit enables or disables input capture for GTCCRA on the rising edge of the GTIOCB pin input, when
the GTIOCA input is 1.
ASCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture
Enable)
The ASCBFAL bit enables or disables input capture for GTCCRA on the falling edge of the GTIOCB pin input, when
the GTIOCA input is 0.
ASCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture
Enable)
The ASCBFAH bit enables or disables input capture for GTCCRA on the falling edge of the GTIOCB pin input, when
the GTIOCA input is 1.
ASELCm bit (ELC_GPTm Event Source Counter GTCCRA Input Capture Enable) (m = A to H)
The ASELCm bit enables or disables input capture for GTCCRA at the ELC_GPTm event input.
R01UM0010EU0120 Rev.1.20
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Page 465 of 1619
S3A1 User’s Manual
23.2.11
23. General PWM Timer (GPT)
General PWM Timer Input Capture Source Select Register B (GTICBSR)
Address(es): GPT32m.GTICBSR 4007 8028h + 0100h × m (m = 0 to 3),
GPT16m.GTICBSR 4007 8028h + 0100h × m (m = 4 to 9)
b31
Value after reset:
b30
b29
b28
b27
b26
b25
b24
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
BSCBF BSCBF BSCBR BSCBR BSCAF BSCAF BSCAR BSCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
b23
BSELC BSELC BSELC BSELC BSELC BSELC BSELC BSELC
H
G
F
E
D
C
B
A
0
0
0
0
0
0
0
BSGTR BSGTR BSGTR BSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BSGTRGAR
GTETRGA Pin Rising Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of the
GTETRGA input
1: GTCCRB input capture enabled on the rising edge of the
GTETRGA input.
R/W
b1
BSGTRGAF
GTETRGA Pin Falling Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
the GTETRGA input
1: GTCCRB input capture enabled on the falling edge of the
GTETRGA input.
R/W
b2
BSGTRGBR
GTETRGB Pin Rising Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of the
GTETRGB input
1: GTCCRB input capture enabled on the rising edge of the
GTETRGB input.
R/W
b3
BSGTRGBF
GTETRGB Pin Falling Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
the GTETRGB input
1: GTCCRB input capture enabled on the falling edge of the
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
BSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of the
GTIOCA input when the GTIOCB input is 0
1: GTCCRB input capture enabled on the rising edge of the
GTIOCA input when the GTIOCB input is 0.
R/W
b9
BSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of the
GTIOCA input when the GTIOCB input is 1
1: GTCCRB input capture enabled on the rising edge of the
GTIOCA input when the GTIOCB input is 1.
R/W
b10
BSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
the GTIOCA input when the GTIOCB input is 0
1: GTCCRB input capture enabled on the falling edge of the
GTIOCA input when the GTIOCB input is 0.
R/W
b11
BSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
the GTIOCA input when the GTIOCB input is 1
1: GTCCRB input capture enabled on the falling edge of the
GTIOCA input when the GTIOCB input is 1.
R/W
b12
BSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of the
GTIOCB input when the GTIOCA input is 0
1: GTCCRB input capture enabled on the rising edge of the
GTIOCB input when the GTIOCA input is 0.
R/W
b13
BSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of the
GTIOCB input when the GTIOCA input is 1
1: GTCCRB input capture enabled on the rising edge of the
GTIOCB input when the GTIOCA input is 1.
R/W
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 466 of 1619
S3A1 User’s Manual
23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b14
BSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
the GTIOCB input when the GTIOCA input is 0
1: GTCCRB input capture enabled on the falling edge of the
GTIOCB input when the GTIOCA input is 0.
R/W
b15
BSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
the GTIOCB input when the GTIOCA input is 1
1: GTCCRB input capture enabled on the falling edge of the
GTIOCB input when the GTIOCA input is 1.
R/W
b16
BSELCA
ELC_GPTA Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at the ELC_GPTA input
1: GTCCRB input capture enabled at the ELC_GPTA input.
R/W
b17
BSELCB
ELC_GPTB Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at the ELC_GPTB input
1: GTCCRB input capture enabled at the ELC_GPTB input.
R/W
b18
BSELCC
ELC_GPTC Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at the ELC_GPTC input
1: GTCCRB input capture enabled at the ELC_GPTC input.
R/W
b19
BSELCD
ELC_GPTD Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at the ELC_GPTD input
1: GTCCRB input capture enabled at the ELC_GPTD input.
R/W
b20
BSELCE
ELC_GPTE Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at the ELC_GPTE input
1: GTCCRB input capture enabled at the ELC_GPTE input.
R/W
b21
BSELCF
ELC_GPTF Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at the ELC_GPTF input
1: GTCCRB input capture enabled at the ELC_GPTF input.
R/W
b22
BSELCG
ELC_GPTG Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at the ELC_GPTG input R/W
1: GTCCRB input capture enabled at the ELC_GPTG input.
b23
BSELCH
ELC_GPTH Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at the ELC_GPTH input
1: GTCCRB input capture enabled at the ELC_GPTH input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
GTICBSR sets the source of the input capture for GTCCRB.
BSGTRGAR bit (GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable)
The BSGTRGAR bit enables or disables the input capture for GTCCRB on the rising edge of the GTETRGA pin input.
BSGTRGAF bit (GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable)
The BSGTRGAF bit enables or disables the input capture for GTCCRB on the falling edge of the GTETRGA pin input.
BSGTRGBR bit (GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable)
The BSGTRGBR bit enables or disables the input capture for GTCCRB on the rising edge of the GTETRGB pin input.
BSGTRGBF bit (GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable)
The BSGTRGBF bit enables or disables the input capture for the GTCCRB on the falling edge of the GTETRGB pin
input.
BSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture
Enable)
The BSCARBL bit enables or disables the input capture for the GTCCRB on the rising edge of the GTIOCA pin input,
when the GTIOCB input is 0.
BSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture
Enable)
The BSCARBH bit enables or disables the input capture for the GTCCRB on the rising edge of the GTIOCA pin input,
when the GTIOCB input is 1.
BSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture
Enable)
The BSCAFBL bit enables or disables the input capture for the GTCCRB on the falling edge of the GTIOCA pin input,
when the GTIOCB input is 0.
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23. General PWM Timer (GPT)
BSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture
Enable)
The BSCAFBH bit enables or disables the input capture for the GTCCRB on the falling edge of the GTIOCA pin input,
when the GTIOCB input is 1.
BSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture
Enable)
The BSCBRAL bit enables or disables the input capture for the GTCCRB on the rising edge of the GTIOCB pin input,
when the GTIOCA input is 0.
BSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture
Enable)
The BSCBRAH bit enables or disables the input capture for the GTCCRB on the rising edge of the GTIOCB pin input,
when the GTIOCA input is 1.
BSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture
Enable)
The BSCBFAL bit enables or disables the input capture for the GTCCRB on the falling edge of the GTIOCB pin input,
when the GTIOCA input is 0.
BSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture
Enable)
The BSCBFAH bit enables or disables the input capture for the GTCCRB on the falling edge of the GTIOCB pin input,
when the GTIOCA input is 1.
BSELCm bit (ELC_GPTm Event Source Counter GTCCRB Input Capture Enable) (m = A to H)
The BSELCm bit enables or disables the input capture for the GTCCRB at the ELC_GPTm event input.
23.2.12
General PWM Timer Control Register (GTCR)
Address(es): GPT32m.GTCR 4007 802Ch + 0100h × m (m = 0 to 3),
GPT16m.GTCR 4007 802Ch + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
—
—
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
—
—
—
—
—
0
0
0
0
0
b24
b23
b22
b21
b20
b19
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
CST
0
0
0
0
0
0
0
0
0
0
0
TPCS[2:0]
b18
b17
b16
MD[2:0]
Bit
Symbol
Bit name
Description
R/W
b0
CST
Count Start
0: Count operation is stopped
1: Count operation is performed.
R/W
b15 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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Bit
Symbol
23. General PWM Timer (GPT)
Bit name
Description
R/W
b18 to b16 MD[2:0]
Mode Select
b18
R/W
b23 to b19 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b26 to b24 TPCS[2:0]
Timer Prescaler Select
b26
R/W
b31 to b27 —
Reserved
These bits are read as 0. The write value should be 0.
b16
0 0 0: Saw-wave PWM mode (single buffer or double
buffer possible)
0 0 1: Saw-wave one-shot pulse mode (fixed buffer
operation)
0 1 0: Setting prohibited
0 1 1: Setting prohibited
1 0 0: Triangle-wave PWM mode 1 (32-bit transfer at
trough) (single buffer or double buffer possible)
1 0 1: Triangle-wave PWM mode 2 (32-bit transfer at crest
and trough) (single buffer or double buffer possible)
1 1 0: Triangle-wave PWM mode 3 (64-bit transfer at
trough) (fixed buffer operation)
1 1 1: Setting prohibited.
0
0
0
0
1
1
0
0
1
1
0
0
b24
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64
0: PCLKD/256
1: PCLKD/1024.
R/W
The GTCR controls the GTCNT.
CST bit (Count Start)
The CST bit controls the GTCNT counter start and stop.
[Setting conditions]
The GTSTR value where the channel number associated with the bit number is set to 1 with the GTSSR.CSTRT bit
at 1
The ELC event input or the GTIOCA/GTIOCB/GTETRGn port input that are enabled by GTSSR for the starting
counter source, occurs
1 is written by software directly.
[Clearing conditions]
The GTSTP value where the channel number associated with the bit number is set to 1 with the GTSSR.CSTOP bit
at 1
The ELC event input or the GTIOCA/GTIOCB/GTETRGn port input that are enabled by GTSSR for the stopping
counter source, occurs
0 is written by software directly.
MD[2:0] bits (Mode Select)
The MD[2:0] bits select the GPT operating mode. The MD[2:0] bits must be set while the GTCNT operation is stopped.
TPCS[2:0] bits (Timer Prescaler Select)
The TPCS[2:0] bits select the clock for GTCNT. A clock prescaler can be selected independently for each channel. The
TPCS[2:0] bits must be set while the GTCNT operation is stopped.
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23.2.13
23. General PWM Timer (GPT)
General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC)
Address(es): GPT32m.GTUDDTYC 4007 8030h + 0100h × m (m = 0 to 3),
GPT16m.GTUDDTYC 4007 8030h + 0100h × m (m = 4 to 9)
b31
b30
b29
b28
b27
b26
OBDTY OBDTY
R
F
b25
—
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
—
—
—
—
—
0
0
0
0
0
Value after reset:
Value after reset:
b24
OBDTY[1:0]
b23
b22
b21
b20
b19
b18
OADTY OADTY
R
F
b17
b16
—
—
—
—
OADTY[1:0]
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
UDF
UD
0
0
0
0
0
0
0
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b0
UD
Count Direction Setting
0: GTCNT counts down
1: GTCNT counts up.
R/W
b1
UDF
Forcible Count Direction
Setting
0: Not forcibly set
1: Forcibly set.
R/W
b15 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b17, 16
OADTY[1:0]
GTIOCA Output Duty Setting
b17 b16
R/W
b18
OADTYF
Forcible GTIOCA Output Duty
Setting
0: Not forcibly set
1: Forcibly set.
R/W
b19
OADTYR
GTIOCA Output Value
Selecting after Releasing
0% or 100% Duty Setting
0: Apply output value set in 0% or 100% duty to GTIOA[3:2]
function after releasing 0% or 100% duty setting.
1: Apply masked compare match output value to GTIOA[3:2]
function after releasing 0% or 100% duty setting.
R/W
0
1
1
x: GTIOCA pin duty depends on compare match
0: GTIOCA pin duty 0%
1: GTIOCA pin duty 100%.
b23 to b20 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25, b24
OBDTY[1:0]
GTIOCB Output Duty Setting
b25 b24
R/W
b26
OBDTYF
Forcible GTIOCB Output Duty
Setting
0: Not forcibly set
1: Forcibly set.
R/W
b27
OBDTYR
GTIOCB Output Value
Selecting after Releasing
0% or 100% Duty Setting
0: Apply output value set in 0% or 100% duty to GTIOB[3:2]
function after releasing 0% or 100% duty setting
1: Apply masked compare match output value to GTIOB[3:2]
function after releasing 0% or 100% duty setting.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b28 —
0
1
1
x: GTIOCB pin duty depends on compare match
0: GTIOCB pin duty 0%
1: GTIOCB pin duty 100%.
x: Don’t care
The GTUDDTYC sets the direction in which GTCNT counts (up-counting or down-counting), and sets the duty of the
GTIOCA/GTIOCB pin output.
Count direction:
In saw-wave mode
When the UD value is set to 0 during up-counting, the count direction changes at an overflow (the timing synchronous
with count clock after the GTCNT value becomes the GTPR value). When the UD value is set to 1 during downcounting, the count direction changes at an underflow (the timing synchronous with count clock after GTCNT value
becomes 0).
When the UD value changes from 1 to 0 with the UDF bit at 0 and while counting stops, the counter starts up-counting
and the count direction changes at an overflow (the timing synchronous with count clock after GTCNT value becomes
GTPR value). When the UD value changes from 0 to 1 with the UDF bit at 0 and while counting stops, the counter starts
down-counting and the count direction changes at an underflow (the timing synchronous with count clock after the
GTCNT value becomes 0).
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23. General PWM Timer (GPT)
When the UDF bit is set to 1 while counting stops, the UD bit value is reflected in the count direction when counting
starts.
Count direction:
In triangle-wave mode
When the UD value changes during counting, the count direction does not change. When the UD value changes while the
UDF bit is 0 and counting stops, the change is not reflected in the count direction when counting starts.
When the UDF bit is set to 1 while counting stops, the UD value is reflected in the count direction when counting starts.
UD bit (Count Direction Setting)
The UD bit sets the count direction (up-counting or down-counting) for GTCNT.
UDF bit (Forcible Count Direction Setting)
The UDF bit forcibly sets the count direction when GTCNT starts operation as the UD value. Only write 0 to this bit
during counter operation. When 1 is written to this bit while counting stops, return this bit to 0 before counting starts.
Output duty
In saw-wave mode
When the OADTY/OBDTY value changes during up-counting, the duty is reflected at an overflow (GTCNT = GTPR).
When the OADTY/OBDTY value changes during down-counting, the duty is reflected at an underflow (GTCNT = 0).
When the OADTY/OBDTY value changes to 1 with the OADTYF/OBDTYF bit at 0 and while counting stops, the
output duty is not reflected at the starting counter operation. When the count direction is up, the output duty is reflected
at an overflow (GTCNT = GTPR). When the count direction is down, the output duty is reflected at an underflow
(GTCNT = 0). When the OADTY/OBDTY value changes to 0 with the OADTYF/OBDTYF bit at 1 and while counting
stops, the output duty is reflected at the starting counter operation.
In triangle-wave mode
When the OADTY/OBDTY value changes during counting, the duty is reflected at an underflow. When the OADTY/
OBDTY value changes to 1 with the OADTYF/OBDTYF bit at 0 and while counting stops, the output duty is not
reflected at the starting counter operation, however, the output duty is reflected at an underflow. When the OADTY/
OBDTY value changes to 0 with the OADTYF/OBDTYF bit at 1 and while counting stops, the output duty is reflected at
the starting counter operation.
OmDTY[1:0] bits (GTIOCm Output Duty Setting) (m = A, B)
The OmDTY[1:0] bits set the output duty of the GTIOCm pin to 0%, 100% or compare match control.
OmDTYF bit (Forcible GTIOCm Output Duty Setting) (m = A, B)
The OmDTYF bit forcibly sets the output duty cycle to the OmDTY setting. Set this bit to 0 during counter operation.
When this bit is set to 1 while counting stops, this bit should be returned to 0 until the first period ends after the counter
starts.
OmDTYR bit (GTIOCm Output Value Selecting after Releasing 0% or 100% Duty Setting) (m = A, B)
The OmDTYR bits select the value that is the object of the output retained or toggled at the cycle end, when the control
changes from 0% or 100% duty setting to compare match for the GTIOCm pin and GTIOR. The GTIOm[3:2] bits are set
to 00b (output retained at cycle end) or the GTIOR.GTIOm[3:2] bits are set to 11b (output toggled at cycle end).
The GPT internally continues to perform compare match operation in performing 0% or 100% duty operation. When the
OmDTYR bit is set to 1, the value of the compare match at cycle end is applied to GTIOR.GTIOm[3:2].
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23.2.14
23. General PWM Timer (GPT)
General PWM Timer I/O Control Register (GTIOR)
Address(es): GPT32m.GTIOR 4007 8034h + 0100h × m (m = 0 to 3),
GPT16m.GTIOR 4007 8034h + 0100h × m (m = 4 to 9)
b31
b30
NFCSB[1:0]
Value after reset:
b28
b27
b26
b25
NFBEN
—
—
OBDF[1:0]
b24
OBE
b23
b22
OBHLD OBDFL
T
b21
b20
b19
—
b18
b17
b16
GTIOB[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NFAEN
—
—
OADF[1:0]
0
0
0
0
0
0
NFCSA[1:0]
0
Value after reset:
b29
0
OAE
0
OAHLD OADFL
T
0
0
0
—
0
GTIOA[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
GTIOA[4:0]
GTIOCA Pin Function Select
See Table 23.5.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
OADFLT
GTIOCA Pin Output Value
Setting at the Count Stop
0: The GTIOCA pin outputs low when counting stops
1: The GTIOCA pin outputs high when counting stops.
R/W
b7
OAHLD
GTIOCA Pin Output Setting at
the Start/Stop Count
0: The GTIOCA pin output level at the start or stop of counting
depends on the register setting
1: The GTIOCA pin output level is retained at the start or stop
of counting.
R/W
b8
OAE
GTIOCA Pin Output Enable
0: Output is disabled
1: Output is enabled.
R/W
b10, b9
OADF[1:0]
GTIOCA Pin Disable Value
Setting
b10 b9
R/W
0
0
1
1
0: Output disable is prohibited
1: GTIOCA pin is set to Hi-Z on output-disable
0: GTIOCA pin is set to 0 on output-disable
1: GTIOCA pin is set to 1 on output-disable.
b12, b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13
NFAEN
Noise Filter A Enable
0: The noise filter for the GTIOCA pin is disabled
1: The noise filter for the GTIOCA pin is enabled.
R/W
b15, b14
NFCSA[1:0]
Noise Filter A Sampling Clock
Select
b15 b14
R/W
b20 to b16 GTIOB[4:0]
GTIOCB Pin Function Select
See Table 23.5.
R/W
b21
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b22
OBDFLT
GTIOCB Pin Output Value
Setting at the Count Stop
0: The GTIOCB pin outputs low when counting stops
1: The GTIOCB pin outputs high when counting stops.
R/W
b23
OBHLD
GTIOCB Pin Output Setting at
the Start/Stop Count
0: The GTIOCB pin output level at the start/stop of counting
depends on the register setting
1: The GTIOCB pin output level is retained at the start/stop of
counting.
R/W
b24
OBE
GTIOCB Pin Output Enable
0: Output is disabled
1: Output is enabled.
R/W
b26, b25
OBDF[1:0]
GTIOCB Pin Disable Value
Setting
b26 b25
R/W
b28, b27
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b29
NFBEN
Noise Filter B Enable
0: Noise filter for the GTIOCB pin is disabled
1: Noise filter for the GTIOCB pin is enabled.
R/W
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0
0
1
1
0
0
1
1
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
0: Output-disable is prohibited
1: GTIOCB pin is set to Hi-Z on output disable
0: GTIOCB pin is set to 0 on output disable
1: GTIOCB pin is set to 1 on output disable.
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b31, b30
NFCSB[1:0]
Noise Filter B Sampling Clock
Select
b31 b30
R/W
0
0
1
1
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
The GTIOR sets the functions of the GTIOCA and GTIOCB pins.
GTIOA[4:0] bits (GTIOCA Pin Function Select)
The GTIOA[4:0] bits select the GTIOCA pin function. For details, see Table 23.5.
OADFLT bit (GTIOCA Pin Output Value Setting at the Count Stop)
The OADFLT bit sets whether the GTIOCA pin outputs high or low when counting stops.
OAHLD bit (GTIOCA Pin Output Setting at the Start/Stop Count)
The OAHLD bit specifies whether the GTIOCA pin output level is retained or the level at the start/stop of counting
depends on the register setting.
When the OAHLD bit is set to 0:
The value specified in bit [4] of the GTIOA[4:0] bits is output when counting starts
The value specified in the OADFLT bit is output when counting stops
If the OADFLT bit is modified while counting stops, the new value is immediately reflected in the output.
When the OAHLD bit is set to 1:
The output is retained when counting starts or stops.
OAE bit (GTIOCA Pin Output Enable)
The OAE bit disables or enables the GTIOCA pin output.
When the GTCCRA register is used as the input capture register (at least one bit in the GTICASR register is set to 1), the
GTIOCA pin does not output regardless of the OAE bit value.
OADF[1:0] bits (GTIOCA Pin Disable Value Setting)
The OADF[1:0] bits select the output value of the GTIOCA pin when an output-disable request occurs.
NFAEN bit (Noise Filter A Enable)
The NFAEN bit disables or enables the noise filter for input from the GTIOCA pin. Because changing the value of the bit
might lead to internal generation of an unexpected edge, select the output compare function for the relevant pin in the
GTIOR register before doing so.
NFCSA[1:0] bits (Noise Filter A Sampling Clock Select)
The NFCSA[1:0] bits set the sampling interval for the noise filter of the GTIOCA pin. When setting these bits, wait for 2
cycles of the selected sampling interval before setting the input capture function.
GTIOB[4:0] bits (GTIOCB Pin Function Select)
The GTIOB[4:0] bits select the GTIOCB pin function. For details, see Table 23.5.
OBDFLT bit (GTIOCB Pin Output Value Setting at the Count Stop)
The OBDFLT bit sets whether the GTIOCB pin outputs high or low when counting stops.
OBHLD bit (GTIOCB Pin Output Setting at the Start/Stop Count)
The OBHLD bit specifies whether the GTIOCB pin output level is retained or the level at the start/stop of counting
depends on the register setting.
When the OBHLD bit is set to 0:
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23. General PWM Timer (GPT)
The value specified in bit [4] of the GTIOB[4:0] bits is output when counting starts
The value specified in the OBDFLT bit is output when counting stops
If the OBDFLT bit is modified while counting stops, the new value is immediately reflected in the output.
When the OBHLD bit is set to 1:
The output is retained when counting starts or stops.
OBE bit (GTIOCB Pin Output Enable)
The OBE bit disables or enables the GTIOCB pin output.
When GTCCRB register is used as the input capture register (at least one bit in GTICBSR register is set to 1), the
GTIOCB pin does not output regardless of the OBE bit value.
OBDF[1:0] bits (GTIOCB Pin Disable Value Setting)
The OBDF[1:0] bits select the output value of GTIOCB pin when an output-disable request occurs.
NFBEN bit (Noise Filter B Enable)
The NFBEN bit disables or enables the noise filter for input from the GTIOCB pin. Because changing the value of the bit
might lead to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the
GTIOR register before doing so.
NFCSB[1:0] bits (Noise Filter B Sampling Clock Select)
The NFCSB[1:0] bits set the sampling interval for the noise filter of the GTIOCB pin. When setting these bits, wait for 2
cycles of the selected sampling interval before setting the input-capture function.
Table 23.5
Settings of GTIOA[4:0] and GTIOB[4:0] bits (1 of 2)
GTIOA/GTIOB[4:0] bits
b4
b3
b2
b1
Function
b0
b4
b3, b2
Initial output is low
Retain output at
cycle end
b1, b0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
High output at GTCCRA/GTCCRB compare match
0
0
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
High output at GTCCRA/GTCCRB compare match
0
1
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Low output at cycle
end
High output at cycle
end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Toggle output at
cycle end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
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Table 23.5
23. General PWM Timer (GPT)
Settings of GTIOA[4:0] and GTIOB[4:0] bits (2 of 2)
GTIOA/GTIOB[4:0] bits
b4
b3
b2
b1
Function
b0
b4
b3, b2
b1, b0
Initial output is high
Retain output at
cycle end
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
High output at GTCCRA/GTCCRB compare match
1
0
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
High output at GTCCRA/GTCCRB compare match
1
1
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
Note:
Note:
Note:
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Low output at cycle
end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at cycle
end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Toggle output at
cycle end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
The cycle end means an overflow (GTCNT changes from GTPR to 0 in up-counting) or underflow (GTCNT changes from 0 to
GTPR in down-counting). The GTCNT counter is cleared for saw waves and for the trough (GTCNT changes from 0 to 1) for
triangle waves.
When the timing of a cycle end and the timing of a GTCCRA/GTCCRB compare match are the same in a compare-match
operation, the b3 and b2 settings are given priority in saw-wave PWM mode, and the b1 and b0 settings are given priority in any
other mode.
In event count operation where at least one bit in GTUPSR or GTDNSR is set to 1, the setting of b3 and b2 is ignored.
23.2.15
General PWM Timer Interrupt Output Setting Register (GTINTAD)
Address(es): GPT32m.GTINTAD 4007 8038h + 0100h × m (m = 0 to 3),
GPT16m.GTINTAD 4007 8038h + 0100h × m (m = 4 to 9)
b31
—
b30
b29
GRPAB GRPAB
L
H
b28
b27
b26
—
—
—
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
GRP[1:0]
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
b23 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b25, b24
GRP[1:0]
Output-Disable Source Select
b25 b24
b28 to b26
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b29
GRPABH
Same Time Output Level High Disable
Request Enable
0: Same time output level high disable request
disabled
1: Same time output level high disable request
enabled.
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
R/W
R/W
0 0: Group A output-disable request
0 1: Group B output-disable request
1 x: Setting prohibited.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b30
GRPABL
Same Time Output Level Low Disable
Request Enable
0: Same time output level low disable request
disabled
1: Same time output level low disable request
enabled.
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
The GTINTAD enables or disables interrupt requests and output-disable requests.
GRP[1:0] bits (Output-Disable Source Select)
The GRP[1:0] bits select the GTIOCA or GTIOCB pin output-disable sources.
The output disable request to POEG outputs to the group which is selected in the GRP[1:0] bits when same time output
level high or same time output level low occurs based on each output disable request enable bit.
GTST.ODF shows the request of output-disable source group that is selected in the GRP[1:0] bits. The GRP[1:0] bits
should be set when both GTIOR.OAE and GTIOR.OBE are 0.
GRPABH bit (Same Time Output Level High Disable Request Enable)
The GRPABH bit enables or disables output-disable request when the GTIOCA and GTIOCB pins output 1 at the same
time.
GRPABL bit (Same Time Output Level Low Disable Request Enable)
The GRPABL bit enables or disables output-disable request when the GTIOCA and GTIOCB pins output 0 at the same
time.
23.2.16
General PWM Timer Status Register (GTST)
Address(es): GPT32m.GTST 4007 803Ch + 0100h × m (m = 0 to 3),
GPT16m.GTST 4007 803Ch + 0100h × m (m = 4 to 9)
b31
—
Value after reset:
Value after reset:
b30
b29
OABLF OABHF
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
ODF
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TUCF
—
—
—
—
—
—
—
TCFE
TCFD
TCFC
TCFB
TCFA
1
0
0
0
0
0
0
0
0
0
0
0
0
TCFPU TCFPO TCFF
0
0
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
TCFA
Input Capture/Compare Match
Flag A
0: No input capture/compare match of GTCCRA is generated
1: An input capture/compare match of GTCCRA is generated.
R/(W)*1
b1
TCFB
Input Capture/Compare Match
Flag B
0: No input capture/compare match of GTCCRB is generated
1: An input capture/compare match of GTCCRB is generated.
R/(W)*1
b2
TCFC
Input Compare Match Flag C
0: No compare match of GTCCRC is generated
1: A compare match of GTCCRC is generated.
R/(W)*1
b3
TCFD
Input Compare Match Flag D
0: No compare match of GTCCRD is generated
1: A compare match of GTCCRD is generated.
R/(W)*1
b4
TCFE
Input Compare Match Flag E
0: No compare match of GTCCRE is generated
1: A compare match of GTCCRE is generated.
R/(W)*1
b5
TCFF
Input Compare Match Flag F
0: No compare match of GTCCRF is generated
1: A compare match of GTCCRF is generated.
R/(W)*1
b6
TCFPO
Overflow Flag
0: No overflow (crest) occurred
1: An overflow (crest) occurred.
R/(W)*1
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b7
TCFPU
Underflow Flag
0: No underflow (trough) occurred
1: An underflow (trough) occurred.
R/(W)*1
b14 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
TUCF
Count Direction Flag
0: GTCNT counter counts downward
1: GTCNT counter counts upward.
R
b23 to b16 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b24
Output-Disable Flag
0: No output-disable request is generated
1: An output-disable request is generated.
R
b28 to b25 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b29
OABHF
Same Time Output Level High
Flag
0: GTIOCA and GTIOCB pins do not output 1 at the same time
1: GTIOCA and GTIOCB pins output 1 at the same time.
R
b30
OABLF
Same Time Output Level Low
Flag
0: GTIOCA and GTIOCB pins do not output 0 at the same time
1: GTIOCA and GTIOCB pins output 0 at the same time.
R
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note 1.
ODF
Only 0 can be written to this bit. Do not write 1.
GTST indicates the status of the GPT.
TCFA flag (Input Capture/Compare Match Flag A)
TCFA is the status flag for the input capture or compare match of GTCCRA.
[Setting conditions]
GTCNT = GTCCRA when the GTCCRA register functions as a compare match register
GTCNT counter value is transferred to GTCCRA by the input capture signal when the GTCCRA register functions
as an input capture register.
[Clearing condition]
0 is written to this flag.
TCFB flag (Input Capture/Compare Match Flag B)
TCFB is the status flag for the input capture or compare match of GTCCRB.
[Setting conditions]
GTCNT = GTCCRB, when the GTCCRB register functions as a compare match register
GTCNT counter value is transferred to GTCCRB by the input capture signal when the GTCCRB register functions
as an input capture register.
[Clearing condition]
0 is written to this flag.
TCFC flag (Input Compare Match Flag C)
TCFC is the status flag for the compare match of GTCCRC.
[Setting condition]
GTCNT = GTCCRC.
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 01b, 10b, 11b (GTCCRC performs buffer operation).
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23. General PWM Timer (GPT)
TCFD flag (Input Compare Match Flag D)
TCFD is the status flag for the compare match of GTCCRD.
[Setting condition]
GTCNT = GTCCRD.
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 10b, 11b (GTCCRD performs buffer operation).
TCFE flag (Input Compare Match Flag E)
TCFE is the status flag for the compare match of GTCCRE.
[Setting condition]
GTCNT = GTCCRE.
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 01b, 10b, 11b (GTCCRE performs buffer operation).
TCFF flag (Input Compare Match Flag F)
TCFF is the status flag for the compare match of GTCCRF.
[Setting condition]
GTCNT = GTCCRF.
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 10b, 11b (GTCCRF performs buffer operation).
TCFPO flag (Overflow Flag)
The TCFPO flag indicates when an overflow or a crest has occurred.
[Setting conditions]
In saw-wave mode, an overflow (GTCNT changes from GTPR to 0 in up-counting) has occurred
In triangle-wave mode, a crest (GTCNT changes from GTPR to GTPR-1) has occurred
In counting by hardware sources, an overflow (GTCNT changes from GTPR to 0 in up count) has occurred.
[Clearing condition]
0 is written to this flag.
R01UM0010EU0120 Rev.1.20
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23. General PWM Timer (GPT)
TCFPU flag (Underflow Flag)
The TCFPU flag indicates when an underflow or a trough has occurred.
[Setting conditions]
In saw-wave mode, an underflow (GTCNT changes from 0 to GTPR in down-counting) has occurred
In triangle-wave mode, a trough (GTCNT changes from 0 to 1) has occurred
In counting by hardware sources, an underflow (GTCNT changes from 0 to GTPR in down-counting) has occurred.
[Clearing condition]
0 is written to this flag.
TUCF flag (Count Direction Flag)
The TUCF flag indicates the count direction of GTCNT. In event count operation, this flag is set to 1 in up-counting and
is set to 0 in down-counting.
ODF flag (Output-Disable Flag)
The ODF flag shows the request of the output-disable source group that is selected in the GRP[1:0] bits.
When output is disabled, an output-disable control is not released within the same cycle in which an output-disable
request is negated. It is released in the next cycle.
OABHF flag (Same Time Output Level High Flag)
The OABHF flag indicates that the GTIOCA and GTIOCB pins output 1 at the same time.
When GTIOCA or GTIOCB pin outputs 0, this flag returns to 0. This flag is read only. Writing 0 to clear the flag is
prohibited.
When an interrupt by the OABHF flag is enabled (GTINTAD.GRPABH = 1), the OABHF flag is output to POEG as an
output-disable request.
[Setting condition]
The GTIOCA and GTIOCB pins output 1 at the same time when both OAE and OBE bits are set to 1.
[Clearing conditions]
The GTIOCA pin output value is different from the GTIOCB pin output value when both OAE and OBE bits are set
to 1
The GTIOCA and GTIOCB pins output 0 at the same time when both OAE and OBE bits are set to 1
Either the OAE bit or OBE bit is set to 0.
OABLF flag (Same Time Output Level Low Flag)
The OABLF flag indicates that the GTIOCA and GTIOCB pins output 0 at the same time.
When the GTIOCA pin or GTIOCB pin outputs 1, this flag returns to 0. This flag is read only. Writing 0 to clear the flag
is prohibited. When an interrupt by the OABLF flag is enabled (GTINTAD.GRPABL = 1), the OABLF flag is output to
the POEG as the output-disable request.
[Setting condition]
The GTIOCA and GTIOCB pins output 0 at the same time when both the OAE and OBE bits are set to 1.
[Clearing conditions]
The GTIOCA pin output value is different from the GTIOCB pin output value when both OAE and OBE bits are set
to 1
The GTIOCA and GTIOCB pins output 1 at the same time when both OAE and OBE bits are set to 1
Either the OAE bit or the OBE bit is set to 0.
The compare-target signals to generate the OABHF/OABLF flag are the compare match outputs (PWM outputs) signals
before they are masked by the output-disable function. When the output-disable state is active, a compare match is also
performed continuously in the GPT and the OABHF/OABLF flag is updated in association with the result of the
compared value.
R01UM0010EU0120 Rev.1.20
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23.2.17
23. General PWM Timer (GPT)
General PWM Timer Buffer Enable Register (GTBER)
Address(es): GPT32m.GTBER 4007 8040h + 0100h × m (m = 0 to 3),
GPT16m.GTBER 4007 8040h + 0100h × m (m = 4 to 9)
b31
Value after reset:
Value after reset:
b30
b29
—
—
0
0
0
b15
b14
—
0
b28
—
b27
b26
b25
b24
—
b23
b22
—
CCRS
WT
b21
—
—
0
0
0
0
0
0
0
0
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b20
PR[1:0]
b19
b18
b17
b16
CCRB[1:0]
CCRA[1:0]
0
0
0
0
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
BD[1]
BD[0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BD[0]
GTCCR Buffer Operation Disable
R/W
b1
BD[1]
GTPR Buffer Operation Disable
0: Buffer operation is enabled
1: Buffer operation is disabled.
b15 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b17, b16
CCRA[1:0]
GTCCRA Buffer Operation
b17 b16
R/W
b19, b18
CCRB[1:0]
GTCCRB Buffer Operation
b19 b18
R/W
b21, b20
PR[1:0]
GTPR Buffer Operation
b21 b20
R/W
b22
CCRSWT
GTCCRA and GTCCRB Forcible
Buffer Operation
Writing 1 to this bit forces a buffer transfer of GTCCRA
and GTCCRB. This bit automatically returns to 0 after 1
is written. This bit is read as 0.
R/W
b31 to b23
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
R/W
0 0: No buffer operation
0 1: Single buffer operation (GTCCRA ↔ GTCCRC)
1 x: Double buffer operation (GTCCRA ↔ GTCCRC
↔ GTCCRD).
0 0: No buffer operation
0 1: Single buffer operation (GTCCRB ↔ GTCCRE)
1 x: Double buffer operation (GTCCRB ↔ GTCCRE
↔ GTCCRF).
0 0: No buffer operation
0 1: Single buffer operation (GTPBR → GTPR)
1 x: Setting prohibited.
The GTBER register provides settings for the buffer operation and must be set while the GTCNT operation stops.
BD[0] bit (GTCCR Buffer Operation Disable)
The BD[0] bit disables buffer operation using GTCCRA, GTCCRC, and GTCCRD combined and the buffer operation
using GTCCRB, GTCCRE, and GTCCRF combined.
When GTDTCR.TDE is 1 and when BD[0] is set to 0, GTCCRB does not perform buffer operation and the GTCCRB
register is automatically set to a compare match value for a negative-phase waveform with dead time.
BD[1] bit (GTPR Buffer Operation Disable)
The BD[1] bit disables buffer operation using GTPR and GTPBR combined.
CCRA[1:0] bits (GTCCRA Buffer Operation)
The CCRA[1:0] bits set buffer operation using GTCCRA, GTCCRC, and GTCCRD combined. When buffer operation is
restricted by the operating mode set in GTCR, the GTCR setting is given priority.*1
CCRB[1:0] bits (GTCCRB Buffer Operation)
The CCRB[1:0] bits set buffer operation using GTCCRB, GTCCRE, and GTCCRF combined. When buffer operation is
restricted by the operating mode set in GTCR, the GTCR setting is given priority.*1
PR[1:0] bits (GTPR Buffer Operation)
The PR[1:0] bits set buffer operation using GTPR and GTPBR combined.
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23. General PWM Timer (GPT)
CCRSWT bit (GTCCRA and GTCCRB Forcible Buffer Operation)
Writing 1 to the CCRSWT bit forces a buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0
after 1 is written. This bit is read as 0 and is only valid when counting is stopped with a specified compare match
operation.
Note 1. The buffer operation mode is fixed in saw-wave one-shot pulse mode, or triangle-wave PWM mode 3 (64-bit
transfer at trough).
23.2.18
General PWM Timer Counter (GTCNT)
Address(es): GPT32m.GTCNT 4007 8048h + 0100h × m (m = 0 to 3),
GPT16m.GTCNT 4007 8048h + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GTCNT is a 32-bit read/write counter for GPT32m (m = 0 to 3). For GPT16m (m = 4 to 9), GTCNT is a 16-bit register.
GTCNT can only be written to after the counting stops. GTCNT must be accessed in 32-bit units. Access in 8-bit/16-bit
units is prohibited.
For GPT16m (m = 4 to 9), the upper 16 bits for access in a 32-bit unit are always read as 0000h and writing to these bits
is ignored. GTCNT must be set within the range of 0 ≤ GTCNT ≤ GTPR.
23.2.19
General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F)
Address(es): GPT32m.GTCCRA 4007 804Ch + 0100h × m (m = 0 to 3),
GPT16m.GTCCRA 4007 804Ch + 0100h × m (m = 4 to 9),
GPT32m.GTCCRB 4007 8050h + 0100h × m (m = 0 to 3),
GPT16m.GTCCRB 4007 8050h + 0100h × m (m = 4 to 9),
GPT32m.GTCCRC 4007 8054h + 0100h × m (m = 0 to 3),
GPT16m.GTCCRC 4007 8054h + 0100h × m (m = 4 to 9),
GPT32m.GTCCRD 4007 805Ch + 0100h × m (m = 0 to 3),
GPT16m.GTCCRD 4007 805Ch + 0100h × m (m = 4 to 9),
GPT32m.GTCCRE 4007 8058h + 0100h × m (m = 0 to 3),
GPT16m.GTCCRE 4007 8058h + 0100h × m (m = 4 to 9),
GPT32m.GTCCRF 4007 8060h + 0100h × m (m = 0 to 3),
GPT16m.GTCCRF 4007 8060h + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
Note 1.
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
For GPT16m (m = 4 to 9), the value of the upper 16 bits after reset is 0000h.
GTCCRn registers are read/write registers. The effective size of GTCCRn is the same as GTCNT (16-bit or 32-bit). If the
effective size of GTCCRn is 16 bits, the upper 16 bits for access in a 32-bit unit are always read as 0000h, and writing to
these bits is ignored.
GTCCRA and GTCCRB are registers used for both output compare and input capture. GTCCRC and GTCCRE are
comparison match registers that can also function as buffer registers for GTCCRA and GTCCRB.
GTCCRD and GTCCRF are compare match registers that can also function as buffer registers for GTCCRC and
GTCCRE (double-buffer registers for GTCCRA and GTCCRB).
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23.2.20
23. General PWM Timer (GPT)
General PWM Timer Cycle Setting Register (GTPR)
Address(es): GPT32m.GTPR 4007 8064h + 0100h × m (m = 0 to 3),
GPT16m.GTPR 4007 8064h + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
Note 1.
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
For GPT16m (m = 4 to 9), the value of the upper 16 bits after reset is 0000h.
GTPR is a read/write register that sets the maximum count value of GTCNT. The effective size of GTPR is the same as
GTCNT (16- or 32-bit). If the effective size of GTPR is 16-bit, the upper 16 bits for access in a 32-bit unit are always
read as 0000h, and writing to these bits is ignored.
For saw waves, the value of (GTPR + 1) is the cycle. For triangle waves, the value of (GTPR value × 2) is the cycle.
23.2.21
General PWM Timer Cycle Setting Buffer Register (GTPBR)
Address(es): GPT32m.GTPBR 4007 8068h + 0100h × m (m = 0 to 3),
GPT16m.GTPBR 4007 8068h + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
Note 1.
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
For GPT16m (m = 4 to 9), the value of the upper 16 bits after reset is 0000h.
GTPBR is a read/write register that functions as a buffer register for GTPR. The effective size of GTPBR is the same as
GTCNT (16- or 32-bit). If the effective size of GTPBR is 16-bit, the upper 16 bits for access in a 32-bit unit are always
read as 0000h, and writing to these bits is ignored.
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23.2.22
23. General PWM Timer (GPT)
General PWM Timer Dead Time Control Register (GTDTCR)
Address(es): GPT32m.GTDTCR 4007 8088h + 0100h × m (m = 0 to 3),
GPT16m.GTDTCR 4007 8088h + 0100h × m (m = 4 to 9)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TDE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TDE
Negative-Phase Waveform Setting
0: GTCCRB is set without using GTDVU
1: GTDVU sets the compare match value for the negativephase waveform with automatic dead time in GTCCRB.
R/W
b31 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
GTDTCR enables automatic setting of a compare match value for negative-phase waveform with dead time. GPT has a
dead time control function and the GTDVU register is used for setting dead time value.
TDE bit (Negative-Phase Waveform Setting)
The TDE bit specifies whether to use GTDVU. When GTDVU is used, the compare match value for a negative-phase
waveform with dead time obtained by the compare match value of a positive-phase waveform (GTCCRA) with dead
time value (GTDVU), is automatically set in GTCCRB. The TDE bit setting is ignored in saw-wave PWM mode, and
automatic setting does not take place.
The GTCCRB value is automatically set and has the following upper and lower limit values. If the obtained GTCCRB
value is not within the upper or lower limit, the following limit value is set in GTCCRB.
Triangle waves:
Upper limit value: GTPR - 1
Lower limit value: 1 in up-counting, 0 in down-counting
Saw-wave one-shot pulse mode:
Upper limit value: GTPR
Lower limit value: 0.
23.2.23
General PWM Timer Dead Time Value Register U (GTDVU)
Address(es): GPT32m.GTDVU 4007 808Ch + 0100h x m (m = 0 to 3),
GPT16m.GTDVU 4007 808Ch + 0100h x m (m = 4 to 9)
Value after reset:
Value after reset:
Note 1.
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
1*1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
For GPT16m (m = 4 to 9), the value of the upper 16 bits after reset is 0000h.
GTDVU is a read/write register that sets the dead time for generating PWM waveforms with dead time. The effective
size of GTDVU is the same as GTCNT (16- or 32-bit). If the effective size of GTDVU is 16-bit, the upper 16 bits for
access in a 32-bit unit are always read as 0000h, and writing to these bits is ignored.
Setting a dead time value that exceeds the cycle value is prohibited. The set value can be confirmed by reading from
GTCCRB. When GTDVU is used, writing to GTCCRB is prohibited. When this register is set to 0, waveforms without
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23. General PWM Timer (GPT)
dead time are output.
While GPT is running, changing the GTDVU values is prohibited. To change GTDVU to a new value, stop the GPT with
the CST bit in the GTCR register. GTDVU must be accessed in 32-bit units. Access in 8-bit/16-bit units is prohibited.
23.2.24
Output Phase Switching Control Register (OPSCR)
Address(es): GPT_OPS.OPSCR 4007 8FF0h
b31
b30
NFCS[1:0]
b29
b28
b27
b26
NFEN
—
—
GODF
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
GRP[1:0]
—
—
ALIGN
—
INV
N
P
FB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
EN
—
W
V
U
—
WF
VF
UF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
UF
Input Phase Soft Setting
R/W
b1
VF
These bits set the input phase from software settings.
Setting these bits is valid when the OPSCR.FB bit = 1.
R/W
b2
WF
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
R/W
b4
U
Input U-Phase Monitor
V
Input V-Phase Monitor
These bits monitor the state of the input phase:
OPSCR.FB = 0: External input monitoring by PCLKD
OPSCR.FB = 1: Software settings (UF/VF/WF)
R
b5
b6
W
Input W-Phase Monitor
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b8
EN
Enable-Phase Output Control
0: Do not output (Hi-Z external pin)
1: Output.*1
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
FB
External Feedback Signal Enable
This bit selects the input phase from software settings and
external input.
0: Select the external input
1: Select the software setting (OPSCR.UF, VF, WF).
R/W
b17
P
Positive-Phase Output (P) Control
0: Output level signal
1: Output PWM signal (PWM of GPT320).
R/W
b18
N
Negative-Phase Output (N) Control
0: Output level signal
1: Output PWM signal (PWM of GPT320).
R/W
b19
INV
Invert-Phase Output Control
0: Output positive logic (active-high)
1: Output negative logic (active-low).
R/W
b20
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b21
ALIGN
Input Phase Alignment
0: Input phase aligned to PCLKD
1: Input phase aligned PWM.
R/W
b23, b22
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25, b24
GRP[1:0]
Output-Disabled Source Selection
b25 b24
R/W
b26
GODF
Group Output Disable Function
0: This bit function is ignored
1: Group disable clears the OPSCR.EN bit.*1
R/W
b28, b27
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b29
NFEN
External Input Noise Filter Enable
0: Do not use a noise filter on the external input
1: Use a noise filter on the external input.
R/W
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R
R
0 0: Select Group A output disable source
0 1: Select Group B output disable source
1 x: Setting prohibited.
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b31, b30
NFCS[1:0]
External Input Noise Filter Clock
Selection
Noise filter sampling clock setting of the external input:
R/W
Note 1.
b31 b30
0
0
1
1
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
When OPSCR.GODF = 1 and the signal value selected by the OPSCR.GRP[1:0] bit is high, the OPSCR.EN bit is set to 0.
The OPSCR register sets the output of the signal waveform required for the brushless DC motor control.
UF, VF, WF bits (Input Phase Soft Setting)
The UF, VF, WF bits set the input phase from the software settings. When OPSCR.FB bit is 1, these bits are valid. The
set value of the UF/VF/WF take the place of the U/V/W external inputs.
U, V, W bits (Input Phase Monitor)
When the OPSCR.FB bit is 0, external inputs that are synchronized by PCLKD are monitored by these bits. When the
OPSCR.FB bit is 1, the OPSCR.U, OPSCR.V, and OPSCR.W bits can read the OPSCR.UF, OPSCR.VF, and
OPSCR.WF bits.
EN bit (Enable-Phase Output Control)
The EN bit controls the output enable signal output phase (positive phase/reverse phase).
When OPSCR.EN bit is 1, the signal waveform is output.
When OPSCR.EN bit is 0, first set OPSCR.FB, OPSCR.UF/VF/WF (software setting is selected), OPSCR.P/N,
OPSCR.INV, OPSCR.ALIGN, OPSCR.RV, OPSCR.GRP[1:0], OPSCR.GODF, OPSCR.NFEN, OPSCR.NFCS[1:0].
Then, set the EN bit to 1. Also when OPSCR.GODF is 1 and the signal value selected in the OPSCR.GRP[1:0] bit is
high, the OPSCR.EN bit is set to 0.
FB bit (External Feedback Signal Enable)
The FB bit selects the input phase from the software settings (OPSCR.UF, VF, WF) and external input such as a Hall
element.
P bit (Positive-Phase Output (P) Control)
The P bit selects one of the level signal output (PWM of GPT320) or PWM signal output for the positive-phase output
(GTOUUP pin, GTOVUP pin, GTOWUP pin).
N bit (Negative-Phase Output (N) Control)
The N bit selects one of the level signal output (PWM of GPT320) or PWM signal output for the negative-phase output
(GTOULO pin, GTOVLO pin, GTOWLO pin).
INV bit (Invert-Phase Output Control)
The INV bit selects either the positive logic (active-high) output or negative logic (active-low) output for the output
phase.
ALIGN bit (Input Phase Alignment)
The ALIGN bit selects the PCLKD or PWM for the sampling of the input phase (input phase is specified in the
OPSCR.FB bit).
When OPSCR.ALIGN bit is 0, input phase is aligned to PCLKD.
Note:
Note:
When PWM output is selected (OPSCR.P/N is 1) and the PCLKD input phase is aligned, the PWM pulse can be
short-pulsed.
When OPSCR.ALIGN bit is 1, input phase is aligned with PWM output.
GRP[1:0] bits (Output-Disabled Source Selection)
The GRP[1:0] bits select the output-disable source (A, B).
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23. General PWM Timer (GPT)
GODF bit (Group Output Disable Function)
When the OPSCR.GODF is 1 and the signal value selected by the OPSCR.GRP[1:0] bit is high, the OPSCR.EN bit is set
to 0. When the OPSCR.GODF bit is 0, this bit is ignored.
NFEN bit (External Input Noise Filter Enable)
The NFEN bit selects the noise filter for external input. When OPSCR.NFEN bit is 0, a noise filter is not used for the
external input.
Note:
When this bit is switched because of an unintentional internal edge, set the OPSCR.EN bit to 0.
NFCS[1:0] bits (External Input Noise Filter Clock Selection)
The NFCS[1:0] bits select the clock for the external input noise filter. When the OPSCR.NFEN bit is 1, noise filter
sampling clock setting of the external input is enabled.
1. Set the NFCS[1:0] bits.
2. Wait for 2 cycles.
3. Set the OPSCR.EN bit to 1.
23.3
Operation
23.3.1
Basic Operation
Each channel has a 32-bit timer that performs a periodic count operation using the count clock and hardware sources.
The count function provides both up-counting and down-counting. The GTPR controls the count cycle. When the
GTCNT counter value matches the value in GTCCRA or GTCCRB, the output from the corresponding pin GTIOCA or
GTIOCB can be changed. GTCCRA or GTCCRB can be used as an input capture register with hardware resources.
GTCCRC and GTCCRD can function as buffer registers for GTCCRA. GTCCRE and GTCCRF can function as buffer
registers for GTCCRB.
23.3.1.1
(1)
Counter operation
Counter start and stop
The counter for each channel starts the count operation when GTCR.CST is set to 1. The GTCR.CST bit value is
changed by the following sources:
Writing to GTCR register
Writing 1 to the bit in GTSTR associated with the GPT channel number when the GTSSR.CSTRT bit set to 1
Writing 1 to the bit in GTSTP associated with the GPT channel number when the GTPSR.CSTOP bit set to 1
The hardware source selected in the GTSSR register
The hardware source selected in the GTPSR register.
(2)
Periodic count operation in up-counting by count clock
The GTCNT counter in each channel starts up-counting when the associated GTCR.CST bit is set to 1 with GTUPSR
and GTDNSR registers set to 0000 0000h. When the GTCNT value changes from the GTPR value to 0 (overflow), the
GTST.TCFPO flag is set to 1. When GTCNT overflows, up-counting resumes from 0000 0000h.
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23. General PWM Timer (GPT)
Figure 23.3 shows an example of a periodic count operation in up-counting.
GTCNT counter value
GPT320.GTPR register
0000 0000h
GTCR.CST bit
Time
Flag is cleared by software
GTST.TCFPO flag
Figure 23.3
Example of periodic count operation in up-counting by the count clock
Figure 23.4 shows an example for setting periodic count operation in up-counting.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.3, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction with the GTUDDTYC register.
In Figure 23.3, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.3, 0000_0000h is set.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.4
Example for setting a periodic count operation in up-counting by the count clock
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23. General PWM Timer (GPT)
Periodic count operation in down-counting by count clock
The GTCNT counter in each channel can perform down-counting by setting GTUDDTYC.UD with GTUPSR and
GTDNSR registers set to 0000 0000h. When GTCNT changes from 0 to the GTPR value (underflow), GTST.TCFPU is
set to 1. When the GTCNT counter underflows, down-counting resumes from the GTPR value.
Figure 23.5 shows an example of periodic count operation in down-counting by the count clock.
GTCNT counter value
GTCNT counter is written by software.
GTPR register
0000 0000h
GTCR.CST bit
Time
Flag is cleared by software
GTST.TCFPU flag
Figure 23.5
Example of periodic count operation in down-counting by the count clock
Figure 23.6 shows an example for setting periodic count operation in down-counting by the count clock.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.5, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction with the GTUDDTYC register.
In Figure 23.5, after 10b is set in GTUDDTYC[1:0], 00b is set in
GTUDDTYC[1:0] (down-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.5, the GTPR value is set.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.6
Example for setting periodic count operation in down-counting by count clock
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23. General PWM Timer (GPT)
Event count operation in up-counting using hardware sources
The GTCNT counter in each channel can perform up-counting using hardware sources as set in GTUPSR.
When GTUPSR is set to enable, the count clock selected in GTCR.TPCS[2:0] and the count direction selected in
GTUDDTYC.UD are ignored. If up-counting and down-counting using hardware sources occur at the same time, the
GTCNT counter value does not change. The overflow behavior for up-counting using hardware sources is the same as
for up-counting by the count clock.
When GTCR.CST bit is set to 1 to count up using hardware sources, the count operation is enabled. When GTCR.CST is
set to 1, the counter cannot count up for 1 clock cycle as specified in GTCR.TPCS[2:0] because the count operation is
synchronized by the count clock selected in GTCR.TPCS[2:0]. Set GTCR.TPCS[2:0] to 000b to count up with 1 PCLKD
clock delay after GTCR.CST is set to 1.
Figure 23.7 shows an example of a periodic count operation in up-counting by a hardware resource (rising edge of the
GTETRGA pin).
PCLKD
GTETRGA
N
GTCNT
Figure 23.7
N+1
Example of periodic count operation in up-counting using hardware sources
Figure 23.8 shows an example for setting periodic count operation in down-counting by the count clock.
Set count source
Select the counting-up source with the GTUPSR register.
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.8
Example for setting an event count operation in up-counting using hardware sources
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23. General PWM Timer (GPT)
Event count operation in down-counting using hardware sources
The GTCNT counter in each channel can perform down-counting using hardware sources set in the GTDNSR register.
When GTDNSR is set to enable, the count clock selected in GTCR.TPCS[2:0] and the count direction selected in
GTUDDTYC.UD are ignored. If up-counting and down-counting using hardware sources occur at the same time,
GTCNT counter value does not change. The underflow behavior for down-counting using hardware sources is the same
as for down-counting by the count clock.
When GTCR.CST bit is set to 1 to count down using hardware sources, the count operation is enabled. When
GTCR.CST is set to 1, the counter cannot count down for 1 clock cycle as specified in GTCR.TPCS[2:0] because the
count operation is synchronized with the count clock selected in GTCR.TPCS[2:0]. Set GTCR.TPCS[2:0] to 000b to
count down with a 1 PCLKD delay after GTCR.CST is set to 1.
Figure 23.9 shows an example of a periodic count operation in down-counting by a hardware resource (rising edge of the
GTETRGA pin).
PCLKD
GTETRGA
GTCNT
Figure 23.9
N+1
N
Example of event count operation in down-counting using hardware sources
Figure 23.10 shows an example for setting a periodic count operation in down-counting using a hardware resource.
Set count source
Select the counting-down source with the GTDNSR register.
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.10
(6)
Example for setting an event count operation in down-counting using hardware sources
Counter clear operation
The counter of each channel is cleared by the following sources.
Writing 0 to GTCNT register
Writing 1 to the bit in GTCLR associated with the GPT channel number when the GTCSR.CCLR bit set to 1
The hardware source selected in GTCSR register.
Writing to the GTCNT register is prohibited during count operation. The GTCNT counter can be cleared both by writing
1 to the GTCLR and by the clear request of hardware sources, whether GTCNT is counting (GTCR.CST = 1) or not
(GTCR.CST = 0).
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23. General PWM Timer (GPT)
For saw waves selected by setting GTCR.MD[2:0] and the count direction flag showing down-counting (GTST.TUCF =
0), the GTCNT register is set to the value of the GTPR register when writing 1 to the GTCLR register and when clearing
by hardware sources is performed. When not in saw-wave mode and down-counting, the GTCNT register is set to 0
when writing 1 to the GTCLR register and when clearing by hardware sources is performed.
In event count operation, when at least one bit in GTUPSR or GTDNSR is set to 1, after clear sources occur, both writing
to the GTCLR register and clearing by hardware sources are performed immediately to synchronize with PCLKD. If
other settings are used, clear is synchronized with the counter clock selected in GTCR.TPCS[2:0].
23.3.1.2
Waveform output by compare match
Compare match means that the GTCNT counter value matches the value of GTCCRA or GTCCRB. When a compare
match occurs, the compare match flag is generated synchronously with the count clock, including the event count. At the
same time the GPT can output low, high, or toggled output from the corresponding GTIOCA or GTIOCB output pin. In
addition, the GTIOCA or GTIOCB pin output can be low, high, or toggled at the cycle end which is determined by
GTPR.
The cycle end is:
For saw waves in up-counting – when GTCNT changes from the GTPR value to 0 (overflow)
For saw waves in down-counting – when GTCNT changes from 0 to the GTPR value (underflow)
For saw waves – when the GTCNT counter is cleared
For triangle waves – when the GTCNT changes from 0 to 1 (trough).
(1)
Low output and high output
Figure 23.11 shows an example of low output and high output operation by a compare match of GTCCRA and
GTCCRB.
In this example, the GPT320.GTCNT counter performs up-counting, and settings are made so that high is output from
the GTIOC0A pin by a GPT320.GTCCRA compare match, and low is output from the GTOC0B pin by a
GPT320.GTCCRB compare match. The pin level does not change when the specified level and pin level match.
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
GPT320.GTCCRB register
Time
0000 0000h
No change
No change
GTIOC0A pin output
GTIOC0B pin output
No change
No change
[Setting examples]
GPT320.GTIOR.GTIOA[4:0] bits: Initial output is low, high output at compare match, output retained at cycle end
GPT320.GTIOR.GTIOB[4:0] bits: Initial output is high, low output at compare match, output retained at cycle end
Figure 23.11
Example of low output and high output operation
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23. General PWM Timer (GPT)
Figure 23.12 shows an example for setting low output and high output operation.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.11, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.11, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.11, GTIOA[4:0] = 00010b, GTIOB[4:0] = 10001b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set compare match value
Set compare match values in the GTCCRA and GTCCRB registers.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.12
Example setting for low output and high output operation
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(2)
23. General PWM Timer (GPT)
Toggled output
Figure 23.13 and Figure 23.14 show examples of toggled output operation by compare matches of GTCCRA and
GTCCRB. In Figure 23.13, the GPT320.GTCNT counter performs up-counting, and settings are made so that the
GTIOC0A pin output by a GPT320.GTCCRA compare match and the GTIOC0B pin output by a GPT320.GTCCRB
compare match are toggled.
In Figure 23.14, the GPT320.GTCNT counter performs up-counting, and settings are made so that the GTIOC0A output
is toggled by a compare match of GPT320.GTCCRA, and the GTIOC0B output is toggled at the cycle end.
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRB register
GPT320.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
GTIOC0B pin output
[Setting examples]
GPT320.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end
GPT320.GTIOR.GTIOB[4:0] bits: Initial output is low, output toggled at compare match, output retained at cycle end
Figure 23.13
Example of toggled output operation (1)
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
GTIOC0B pin output
[Setting examples]
GPT320.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end
GPT320.GTIOR.GTIOB[4:0] bits: Initial output is low, output retained at compare match, output toggled at cycle end
Figure 23.14
Example of toggled output operation (2)
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23. General PWM Timer (GPT)
Figure 23.15 shows an example setting for toggled output operation.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.13 and Figure 23.14, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.13 and Figure 23.14, after 11b is set in GTUDDTYC[1:0],
01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.13, GTIOA[4:0] = 10011b, GTIOB[4:0] = 00011b.
In Figure 23.14, GTIOA[4:0] = 10011b, GTIOB[4:0] = 01100b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set compare match value
Set compare match values in the GTCCRA and GTCCRB registers.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.15
Example for setting toggled output operation
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23.3.1.3
23. General PWM Timer (GPT)
Input capture function
The GTCNT counter value can be transferred to either GTCCRA or GTCCRB on detection of the hardware source that is
set in GTICASR and GTICBSR.
Figure 23.16 shows an example of the input capture function.
In this example, the GPT320.GTCNT counter performs up-counting by the count clock, and settings are made so that an
input capture is performed to GTICCRA at both edges of the GTIOC0A input pin and to GTICCRB on the rising edge of
the GTIOC0B input pin.
GPT320.GTCNT counter value
GPT320.GTPR register
E400h
C154h
9682h
1100h
Time
0000 0000h
GTIOC0A pin input
GTIOC0B pin input
GPT320.GTCCRA register
1100h
GPT320.GTCCRB register
E400h
9682h
C154h
[Setting examples]
GTICASR setting input capture at both edges
GTICBSR setting input capture at the rising edge
Figure 23.16
Example of input capture operation
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23. General PWM Timer (GPT)
Figure 23.17 shows an example for setting an input capture operation with count operation by the count clock.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.16, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.16, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Select input capture source
Select the input capture source in GTICASR and GTICBSR.
In Figure 23.16, GTICASR = 0000_0F00h, GTICBSR = 0000_3000h.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.17
23.3.2
Example for setting input capture operation
Buffer Operation
The following buffer operations can be set with GTBER:
GTPR and GTPBR
GTCCRA, GTCCRC, and GTCCRD
GTCCRB, GTCCRE, and GTCCRF.
23.3.2.1
GTPR register buffer operation
GTPBR can function as a buffer register for GTPR. The buffer transfer is performed at an overflow (during up-counting)
or an underflow (during down-counting) in saw-wave mode or in event count, and at a trough in triangle-wave mode.
In saw-wave mode or in event count, the buffer transfer is performed when the following counter clear operations occur
during counting:
Clear by hardware sources (the clear source is selected in GTCSR[23:0])
Clear by software (when GTCSR.CCLR bit is 1 and GTCLR[n] bit is set to 1, n = channel number).
Figure 23.18 to Figure 23.20 show examples of GTPR buffer operation and Figure 23.21 shows an example setting for
GTPR buffer operation.
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23. General PWM Timer (GPT)
GTCNT counter value
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GTPBR register
Register write
bbbb
Register write
cccc
Buffer transfer
at overflow
GTPR register
Figure 23.18
Register write
aaaa
Buffer transfer
at overflow
bbbb
Buffer transfer
at overflow
cccc
Example of GTPR buffer operation in saw waves in up-counting
GTCNT counter value
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GTPBR register
aaaa
Buffer transfer
at underflow
Figure 23.19
cccc
bbbb
GTPR register
Register write
Register write
Buffer transfer
at underflow
aaaa
Buffer transfer
at underflow
bbbb
cccc
Example of GTPR buffer operation in saw waves in down-counting
GTCNT counter value
cccc
bbbb
aaaa
Time
0000 0000h
GTPBR register
aaaa
bbbb
Buffer transfer at trough
GTPR register
Figure 23.20
aaaa
cccc
Buffer transfer at trough
bbbb
Buffer transfer at trough
cccc
Example of GTPR buffer operation with triangle waves
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.18 and Figure 23.19 000b (saw-wave PWM mode) is set,
and in Figure 23.20 100b (triangle-wave PWM mode 1) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.18, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting). In Figure 23.19, after 10b is set in
GTUDDTYC[1:0], 00b is set in GTUDDTYC[1:0] (down-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set buffer operation
Set buffer operation with GTBER.PR[1:0].
In Figure 23.18, Figure 23.19, and Figure 23.20, PR[1:0] = 01b.
Set buffer value
For buffer operation, set a value for 1 cycle after the current cycle in
GTPBR.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set a value for 1 cycle after the current cycle in
GTPBR.
Figure 23.21
Example setting for GTPR buffer operation
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23.3.2.2
23. General PWM Timer (GPT)
Buffer operation for GTCCRA and GTCCRB
GTCCRC can function as the GTCCRA buffer register and GTCCRD can function as the GTCCRC buffer register
(double-buffer register for GTCCRA). Similarly, GTCCRE can function as the GTCCRB buffer register and GTCCRF
can function as the GTCCRE buffer register (double-buffer register for GTCCRB).
To set GTCCRA or GTCCRB to function as a double buffer, set GTBER.CCRA[1:0] or GTBER.CCRB[1:0] to 10b or
11b. For a single buffer operation, set GTBER.CCRA[1:0] or GTBER.CCRB[1:0] to 01b. To set GTCCRA or GTCCRB
to not function as a buffer, set GTBER.CCRA[1:0] or GTBER.CCRB[1:0] to 00b.
(1)
When GTCCRA or GTCCRB functions as an output compare register
Buffer transfer has the following cases:
Buffer transfer by overflow or underflow
Buffer transfer is performed at an overflow (during up-counting) or an underflow (during down-counting) in sawwave mode or in event count operation. In triangle-wave mode, buffer transfer is performed at a trough (trianglewave PWM mode 1) or a crest and trough (triangle-wave PWM mode 2).
Buffer transfer by counter clear
In saw-wave mode or in event count operation, during counting, buffer transfer (which is the same as an overflow
during up-counting or an underflow during down-counting) is performed by the counter clear sources similar to the
case shown in section 23.3.2.1, GTPR register buffer operation. In triangle-wave mode, buffer transfer is not
performed by the counter clear.
Forcible buffer transfer
When GTBER.CCRSWT bit is set to 1 while the count operation stops, the GTCCRA and the GTCCRB register
buffer transfers are performed forcibly in saw-wave mode, in event count operation and in triangle-wave mode.
Additionally, buffer transfer from the GTCCRD register to temporary register A and from the GTCCRF register to
temporary register B are performed in saw-wave 1 shot pulse mode or triangle-wave PWM mode 3.
Figure 23.22 to Figure 23.24 show examples of GTCCRA and GTCCRB buffer operation and Figure 23.25 shows an
example for setting GTCCRA and GTCCRB buffer operation.
GPT320.GCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT320.GTCCRC register
Register write
bbbb
Register write
cccc
Buffer transfer
at overflow
GPT320.GTCCRA register
aaaa
Register write
bbbb
Buffer transfer
at overflow
Buffer transfer
at overflow
cccc
GTIOC0A pin output
Figure 23.22
Example of GTCCRA and GTCCRB buffer operation with output compare, saw waves in upcounting, high output at GTCCRA compare match, and low output at cycle end
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23. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
Register write
cccc
GPT320.GTCCRD register
Buffer transfer at
trough
bbbb
GPT320.GTCCRC register
cccc
Buffer transfer at
trough
GPT320.GTCCRA register
Buffer transfer at
trough
aaaa
Buffer transfer at
trough
bbbb
cccc
GTIOC0A pin output
Figure 23.23
Example of GTCCRA and GTCCRB double buffer operation with output compare, triangle waves,
buffer operation at trough, output toggled at GTCCRA compare match, and output retained at
cycle end
GPT320.GTCNT counter value
GPT320.GTPR register
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT320.GTCCRF register
cccc
bbbb
Buffer transfer at
trough
GPT320.GTCCRE register
aaaa
GPT320.GTCCRB register
Register write
Register write
dddd
Buffer transfer at
crest
Buffer transfer at
trough
cccc
bbbb
dddd
Buffer transfer at
trough
Buffer transfer at
crest
Buffer transfer at
trough
aaaa
cccc
bbbb
Buffer transfer at
crest
Buffer transfer at
crest
dddd
GTIOC0B pin output
Figure 23.24
Example of GTCCRA and GTCCRB double buffer operation with output compare, triangle waves,
buffer operation at both troughs and crests, output toggled at GTCCRB compare match, and
output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.22, 000b (saw-wave PWM mode) is set, in Figure 23.23, 100b (triangle-wave PWM mode 1) is set, and in
Figure 23.24, 101b (triangle-wave PWM mode 2) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.22, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.22, GTIOA[4:0] = 00110b, in Figure 23.23, GTIOA[4:0] = 00011b, and in Figure 23.24, GTIOB[4:0] =
00011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
In Figure 23.22, CCRA[1:0] = 01b, in Figure 23.23, CCRA[1:0] = 1xb, and in Figure 23.24, CCRB[1:0] = 1xb.
Set compare match value
Set the GTIOCA pin transition in GTCCRA and GTIOCB pin transition in the GTCCRB.
Set buffer value
For buffer operation, set the GTIOCA and GTIOCB pin transitions in 1 cycle after the current cycle (in saw-wave mode
or triangle-wave mode with buffer transfer at trough or crest) or half cycle after the current cycle (in triangle-wave
mode with buffer transfer at both trough and crest) in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA and GTIOCB pin transitions in 2 cycles after the current cycle (in
saw-wave mode or triangle-wave mode with buffer transfer at trough or crest) or 1 cycle after the current cycle (in
triangle-wave mode with buffer transfer at both trough and crest) in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA and GTIOCB pin transitions in 1 cycle after the current cycle (in saw-wave mode
or triangle-wave mode with buffer transfer at trough or crest) or half cycle after the current cycle (in triangle-wave
mode with buffer transfer at both trough and crest) in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA and GTIOCB pin transitions in 2 cycles after the current cycle (in
saw-wave mode or triangle-wave mode with buffer transfer at trough or crest) or 1 cycle after the
current cycle (in triangle-wave mode with buffer transfer at both trough and crest) in GTCCRD and GTCCRF,
respectively.
Figure 23.25
Example for setting GTCCRA and GTCCRB buffer operation with output compare
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23. General PWM Timer (GPT)
When GTCCRA or GTCCRB functions as an Input Capture Register
When an input capture is generated, the GTCNT counter value is transferred to GTCCRA and GTCCRB and the stored
GTCCRA and GTCCRB register values are transferred to the buffer registers. In input capture operation, the buffer
transfer is not performed by the counter clear.
Figure 23.26 and Figure 23.27 show examples of GTCCRA and GTCCRB buffer operation and Figure 23.28 shows an
example for setting the GTCCRA and GTCCRB buffer operation.
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
GTIOC0A pin input
GPT320.GTCCRA register
aaaa
Buffer transfer at input
capture
Buffer transfer at input
capture
aaaa
GPT320.GTCCRC register
Figure 23.26
bbbb
cccc
Buffer transfer at
input capture
bbbb
Example of GTCCRA and GTCCRB buffer operation with input capture at both edges of GTIOC0A
input, saw waves in up-counting, and GTCNT counter cleared at both edges of GTIOC0A input
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
GTIOC0B pin input
GPT320.GTCCRB register
aaaa
Buffer transfer at input
capture
GPT320.GTCCRE register
Figure 23.27
Buffer transfer at input
capture
aaaa
Buffer transfer at input
capture
GPT320.GTCCRF register
bbbb
Buffer transfer at input
capture
cccc
Buffer transfer at
input capture
bbbb
Buffer transfer at
input capture
aaaa
Example of GTCCRA and GTCCRB double buffer operation with input capture at both edges of
GTIOC0B input, saw waves in up-counting, and GTCNT counter cleared at both edges of
GTIOC0B input
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0] and count clear source with GTCSR.
In Figure 23.26, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 0F00h, and in Figure
23.27, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 F000h.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.26, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Select input capture source
Select input capture source in the GTICASR register and GTICBSR register.
In Figure 23.26, GTICASR = 0000 0F00h, and in Figure 23.27, GTICBSR = 0000 F000h.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
In Figure 23.26, CCRA[1:0] = 01b, and in Figure 23.27, CCRB = 1xb.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.28
23.3.3
Example for setting GTCCRA and GTCCRB buffer operation with input capture
PWM Output Operating Mode
The GPT can output PWM waveforms to the GTIOCA or GTIOCB pin by a compare match between the GTCNT
counter and GTCCRA or GTCCRB. By setting GTDTCR and GTDVU, the compare match value for a negative-phase
waveform with dead time can be automatically set to GTCCRB.
23.3.3.1
Saw-wave PWM mode
In saw-wave PWM mode, GTCNT performs saw-wave (half-wave) operation by setting the cycle in GTPR. A PWM
waveform is output to the GTIOCA or GTIOCB pin when a GTCCRA or GTCCRB compare match occurs. The pin
output value can be selected from low output, high output, or toggle output separately for a compare match and for the
cycle end according to the GTIOR setting
Figure 23.29 shows an example of saw-wave PWM mode operation, and Figure 23.30 shows an example for setting sawwave PWM mode.
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23. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT320.GTCCRC register
Register write
cccc
eeee
Buffer transfer
at overflow
GPT320.GTCCRA register
aaaa
Register write
GPT320.GTCCRE register
cccc
Register write
dddd
bbbb
Buffer transfer
at overflow
Buffer transfer
at overflow
eeee
Register write
Register write
ffff
Buffer transfer
at overflow
GPT320.GTCCRB register
Register write
dddd
Buffer transfer
at overflow
Buffer transfer
at overflow
ffff
GTIOC0A pin output
GTIOC0B pin output
Figure 23.29
Example of saw-wave PWM mode operation with up-counting, buffer operation, high output at
GTCCRA/GTCCRB compare match, and low output at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]. In Figure 23.29, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.29, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.29, GTIOA[4:0] = 00110b and GTIOB[4:0] = 00110b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER. In Figure 23.29, CCRA[1:0] = 01b and CCRB[1:0] = 01b.
Set compare match value
Set the GTIOCA pin transition in GTCCRA and GTIOCB pin transition in GTCCRB.
Set buffer value
For buffer operation, set the GTIOCA and GTIOCB pin transitions in 1 cycle after the current cycle in GTCCRC and
GTCCRE, respectively.
For double buffer operation, also set the GTIOCA and GTIOCB pin transitions in 2 cycles after the current cycle in
GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA and GTIOCB pin transitions in 1 cycle after the current cycle in GTCCRC and
GTCCRE, respectively.
For double buffer operation, also set the GTIOCA and GTIOCB pin transitions in 2 cycles after the current cycle in
GTCCRD and GTCCRF, respectively.
Figure 23.30
Example for setting saw-wave PWM mode
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23.3.3.2
23. General PWM Timer (GPT)
Saw-wave one-shot pulse mode
The saw-wave one-shot pulse mode is a mode in which the cycle is set in GTPR. The GTCNT counter performs sawwave (half-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of
GTCCRA or GTCCRB with buffer operation fixed.
Buffer operation in saw-wave one-shot pulse mode is different from the usual buffer operation. Buffer transfer is
performed from the following:
GTCCRC to GTCCRA at the cycle end
GTCCRE to GTCCRB at the cycle end
GTCCRD to temporary register A at the cycle end
GTCCRF to temporary register B at the cycle end
Temporary register A to GTCCRA at a GTCCRA compare match
Temporary register B to GTCCRB at a GTCCRB compare match.
The pin output value can be selected from low output, high output, or toggle output separately for a compare match and
the cycle end according to the GTIOR setting. When the GTBER.CCRSWT bit is set to 1 while the count operation
stops, the buffer is transferred forcibly from the GTCCRD register to temporary register A and from the GTCCRF
register to temporary register B. By setting GTDTCR and GTDVU, a compare match value for a negative-phase
waveform with dead time can automatically be set to GTCCRB.
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23. General PWM Timer (GPT)
Figure 23.31 shows an example of saw-wave one-shot pulse mode operation, and Figure 23.32 shows an example for
setting saw-wave one-shot pulse mode.
GPT320.GTCNT counter value
GPT320.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT320.GTCCRD register
Register write
eeee
Buffer transfer
at overflow
gggg
Temporary register A
eeee
Register write
GPT320.GTCCRC register
Buffer transfer
at overflow
Register write
Register write
dddd
Buffer transfer at
compare match
GPT320.GTCCRA register
gggg
bbbb
Register write
GPT320.GTCCRF register
Buffer transfer
at overflow
Buffer transfer at
compare match
Buffer transfer
at overflow
eeee
dddd
Register write
Register write
ffff
Buffer transfer
at overflow
Temporary register B
hhhh
Register write
Register write
Register write
cccc
GPT320.GTCCRE register
Buffer transfer at
compare match
GPT320.GTCCRB register
ffff
aaaa
hhhh
Buffer transfer
at overflow
cccc
Buffer transfer at
compare match
Buffer transfer
at overflow
ffff
GTIOC0A pin output
GTIOC0B pin output
Figure 23.31
Example of saw-wave one-shot pulse mode operation with up-counting, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at GTCCRA/
GTCCRB compare match, and output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.31, 001b (saw-wave one-shot pulse mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.31, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0]
(up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.31, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer value
Set the GTIOCA pin transition immediately after the count start in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Set forcible buffer transfer
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly.
Set buffer value
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Figure 23.32
Example for setting saw-wave one-shot pulse mode
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23.3.3.3
23. General PWM Timer (GPT)
Triangle-wave PWM mode 1 (32-bit transfer at trough)
The triangle-wave PWM mode 1 is a mode in which the cycle is set in GTPR. The GTCNT counter performs trianglewave (full-wave) operation, and a PWM waveform is output to the GTIOCA or GTIOCB pin when a GTCCRA or
GTCCRB compare match occurs. Buffer transfer is performed at the trough. The pin output value can be selected from
low output, high output, or toggle output separately for a compare match and for the cycle end based on the GTIOR
setting.
By setting GTDTCR and GTDVU, a compare match value for a negative-phase waveform with dead time can
automatically be set to GTCCRB.
Figure 23.33 shows an example of a triangle-wave PWM mode 1 operation, and Figure 23.34 shows an example setting
for a triangle-wave PWM mode 1.
GPT320.GTCNT counter value
GPT320.GTPR register
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT320.GTCCRC register
Register write
dddd
Register write
ffff
Buffer transfer at
trough
GPT320.GTCCRA register
bbbb
Register write
GPT320.GTCCRE register
dddd
Register write
cccc
aaaa
ffff
Register write
eeee
Buffer transfer at
trough
GPT320.GTCCRB register
Buffer transfer at
trough
cccc
Buffer transfer at
trough
eeee
GTIOC0A pin output
GTIOC0B pin output
Figure 23.33
Example of triangle-wave PWM mode 1 operation with buffer operation, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at GTCCRA/
GTCCRB register compare match, and output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.33, 100b (triangle-wave PWM mode 1) is set.
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.33, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
In Figure 23.33, CCRA[1:0] = 01b and CCRB[1:0] = 01b.
Set compare match value
Set the GTIOCA and GTIOCB pin transitions in GTCCRA and GTCCRB,
respectively.
Set buffer value
For buffer operation, set the GTIOCA and GTIOCB pin transitions in 1 cycle after
the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA and GTIOCB pin transitions in 2
cycles after the current cycle in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA and GTIOCB pin transitions in 1 cycle after
the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA and GTIOCB pin transitions in 2
cycles after the current cycle in GTCCRD and GTCCRF, respectively.
Figure 23.34
Example for setting triangle-wave PWM mode 1
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23.3.3.4
23. General PWM Timer (GPT)
Triangle-wave PWM mode 2 (32-bit transfer at crest and trough)
Similar to triangle-wave PWM mode 1, in triangle-wave PWM mode 2, the cycle is set in GTPR. The GTCNT counter
performs triangle-wave (full-wave) operation, and a PWM waveform is output to the GTIOCA or GTIOCB pin when a
GTCCRA or GTCCRB compare match occurs. The buffer transfer is performed at both crests and troughs. The pin
output value can be selected from low output, high output, or toggle output separately for a compare match and for the
cycle end according to the GTIOR setting. By setting GTDTCR and GTDVU, a compare match value for a negativephase waveform with dead time can automatically be set to GTCCRB.
Figure 23.35 shows an example of triangle-wave PWM mode 2 operation, and Figure 23.36 shows an example for setting
triangle-wave PWM mode 2.
GPT320.GTCNT counter value
GPT320.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT320.GTCCRC register
GPT320.GTCCRA register
Register write
ffff
GPT320.GTCCRE register
dddd
hhhh
Buffer transfer at
trough
Register write
cccc
Buffer transfer at
crest
GPT320.GTCCRB register
aaaa
dddd
ffff
Register write
eeee
Register write
Buffer transfer at
crest
bbbb
Register write
Register write
eeee
Buffer transfer at
crest
hhhh
Register write
gggg
Buffer transfer at
trough
cccc
Buffer transfer at
crest
gggg
GTIOC0A pin output
GTIOC0B pin output
Figure 23.35
Example of triangle-wave PWM mode 2 operation with buffer operation, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at GTCCRA/
GTCCRB compare match, and output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.35, 101b (triangle-wave PWM mode 2) is set.
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.35, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
In Figure 23.35, CCRA[1:0] = 01b and CCRB[1:0] = 01b.
Set compare match value
Set the GTIOCA and GTIOCB pin transitions in GTCCRA and GTCCRB,
respectively.
Set buffer value
For buffer operation, set the GTIOCA and GTIOCB pin transitions in half cycle after
the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA and GTIOCB pin transitions in 1
cycle after the current cycle in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA and GTIOCB pin transitions in half cycle after
the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA and GTIOCB pin transitions in 1
cycle after the current cycle in GTCCRD and GTCCRF, respectively.
Figure 23.36
Example for setting triangle-wave PWM mode 2
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23.3.3.5
23. General PWM Timer (GPT)
Triangle-wave PWM mode 3 (64-bit transfer at trough)
The triangle-wave PWM mode 3 is a mode in which the cycle is set in GTPR. The GTCNT counter performs trianglewave (full-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of
GTCCRA or GTCCRB with buffer operation fixed. Buffer operation in triangle-wave PWM mode 3 is different from the
usual buffer operation. Buffer transfer is performed from the following:
GTCCRC to GTCCRA at the trough
GTCCRE to GTCCRB at the trough
GTCCRD to temporary register A at the trough
GTCCRF to temporary register B at the trough
Temporary register A to GTCCRA at the crest
Temporary register B to GTCCRB at the crest.
The pin output value can be selected from low output, high output, or toggle output separately for a compare match and
for the cycle end based on the GTIOR setting. By setting GTDTCR and GTDVU, a compare match value for a negativephase waveform with dead time can automatically be set to GTCCRB.
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23. General PWM Timer (GPT)
Figure 23.37 shows an example of triangle-wave PWM mode 3 operation, and Figure 23.38 shows an example for setting
triangle-wave PWM mode 3.
GPT320.GTCNT counter value
GPT320.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT320.GTCCRD register
hhhh
Buffer transfer at
trough
Temporary register A
hhhh
ffff
Register write
Register write
GPT320.GTCCRC register
dddd
Buffer transfer at
crest
GPT320.GTCCRA register
bbbb
Buffer transfer at
trough
dddd
ffff
Register write
Buffer transfer at
crest
hhhh
Register write
gggg
GPT320.GTCCRF register
Buffer transfer at
trough
eeee
Temporary register B
gggg
Register write
Register write
GPT320.GTCCRE register
cccc
Buffer transfer at
crest
GPT320.GTCCRB register
aaaa
eeee
Buffer transfer at
trough
cccc
Buffer transfer at
crest
gggg
GTIOC0A pin output
GTIOC0B pin output
Figure 23.37
Example of triangle-wave PWM mode 3 operation with low output from the GTIOC0A pin and high
output from the GTIOC0B pin at count start, output toggled at GTCCRA/GTCCRB compare match,
and output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 23.37, 110b (triangle-wave PWM mode 3) is set.)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.37, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer value
Set the GTIOCA pin transition immediately after the count start in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Set forcible buffer transfer
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly.
Set buffer value
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Figure 23.38
Example for setting triangle-wave PWM mode 3
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23.3.4
23. General PWM Timer (GPT)
Automatic Dead Time Setting Function
By setting GTDTCR, a compare match value for a negative waveform with dead time obtained by a compare match
value for a positive waveform (GTCCRA value) and specified dead time value (GTDVU value) can automatically be set
to GTCCRB. The automatic dead time setting function can be used in saw-wave one-shot pulse mode and all the triangle
PWM modes.
Writing to GTCCRB is prohibited when the automatic dead time setting function is used. Dead time setting beyond the
cycle is also prohibited. Values for automatic dead time setting can be read from GTCCRB. The automatic dead time
value setting to GTCCRB is performed at the next count clock cycle when registers that are used for calculating the
automatic dead time value are updated.
Figure 23.39 to Figure 23.42 show examples of automatic dead time setting function operation. Figure 23.43 and Figure
23.44 show the setting examples.
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
00000000h
Buffer transfer
at overflow
Time
Buffer transfer
at compare match
Buffer transfer
Buffer transfer
at overflow
at compare match
GPT320.GTCCRA register
GPT320.GTCCRB register
(Automatic setting)
GTCCRA - GTDVU
GTCCRA + GTDVU
GTCCRA
- GTDVU
GTCCRA + GTDVU
GTIOC0A pin output
GTDVU
GTIOC0B pin output
Figure 23.39
GTDVU
GTDVU
GTDVU
Example of automatic dead time setting function operation with saw-wave one-shot pulse mode,
up-counting, and active-high
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
00000000h
Buffer transfer
at underflow
Time
Buffer transfer
at compare match
Buffer transfer
Buffer transfer
at underflow at compare match
GPT320.GTCCRA register
GPT320.GTCCRB register
(Automatic setting)
GTCCRA + GTDVU
GTCCRA - GTDVU
GTCCRA
+ GTDVU
GTCCRA - GTDVU
GTIOC0A pin output
GTIOC0B pin output
Figure 23.40
GTDVU
GTDVU
GTDVU
GTDVU
Example of automatic dead time setting function operation with saw-wave one-shot pulse mode,
down-counting, and active-high
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23. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
Time
00000000h
Buffer transfer at trough
Buffer transfer at trough
GPT320.GTCCRA register
GPT320.GTCCRB register
(Automatic setting)
GTCCRA - GTDVU
GTCCRA - GTDVU
GTIOC0A pin output
GTDVU
GTIOC0B pin output
Figure 23.41
GTDVU
GTDVU
GTDVU
Example of automatic compare-match value setting function with dead time with triangle-wave
PWM mode 1, and active-high
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
Time
00000000h
Buffer transfer
at trough
Buffer transfer
at crest
Buffer transfer
at trough
Buffer transfer
at crest
GPT320.GTCCRA register
GPT320.GTCCRB register
(Automatic setting)
GTCCRA - GTDVU
GTCCRA - GTDVU
GTCCRA - GTDVU
GTCCRA - GTDVU
GTIOC0A pin output
GTDVU
GTDVU
GTDVU
GTDVU
GTIOC0B pin output
Figure 23.42
Example of automatic compare-match value setting function with dead time with triangle-wave
PWM mode 2 or 3, and active-high
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.39 and Figure 23.40, 001b (saw-wave one-shot pulse mode) is set. In Figure 23.42, 110b (triangle-wave
PWM mode 3) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.39, 01b is set after 11b is set in GTUDDTYC[1:0] (up count) In Figure 23.40, 00b is set after 10b is set in
GTUDDTYC[1:0] (down count).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.39, Figure 23.41, and Figure 23.42, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer value for compare match
Set the GTIOCA pin transition immediately after the count start in GTCCRC and GTCCRD.
Set forcible buffer transfer for compare match
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly to GTCCRA.
Set buffer value for compare match
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and GTCCRD.
Set automatic dead time setting function
Set GTDTCR.TDE to 1 to enable the automatic dead time setting function.
Set dead time value
Set the dead time value in GTDVU.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and GTCCRD.
Figure 23.43
Example for setting automatic dead time setting function with saw-wave one-shot pulse mode,
and triangle-wave PWM mode 3
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]. In Figure 23.41, 100b (triangle-wave PWM mode 1) is set. In Figure
23.42, 101b (triangle-wave PWM mode 2) is set.
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.41 and Figure 23.42, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation for compare match
Set buffer operation with CCRA in GTBER.
Set compare match value
Set the GTIOCA pin transition in GTCCRA.
Set buffer value for compare match
For buffer operation, set the GTIOCA pin transition in 1 cycle after the current cycle (in triangle-wave PWM mode 1) or
half cycle after the current cycle (in triangle-wave PWM mode 2) in GTCCRC. For double buffer operation, also set the
GTIOCA pin transition in 2 cycles after the current cycle (in triangle-wave PWM mode 1) or 1 cycle after the current
cycle (in triangle-wave PWM mode 2) in GTCCRD.
Set automatic dead time setting function
Set GTDTCR.TDE to 1 to enable the automatic dead time setting function.
Set dead time value
Set the dead time value in GTDVU.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
When the compare match register is used for buffer operation, set the GTIOCA pin transition in 1 cycle after the
current cycle (in triangle-wave PWM mode 1) or half cycle after the current cycle (in triangle-wave PWM mode 2) in
GTCCRC.
Figure 23.44
Example for setting automatic dead time setting function in triangle-wave PWM mode 1 or 2
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23.3.5
23. General PWM Timer (GPT)
Count Direction Changing Function
The count direction of the GTCNT counter can be changed by modifying the UD bit in GTUDDTYC.
In saw-wave mode, if the UD bit in GTUDDTYC is modified during count operation, the count direction is changed at an
overflow (when modified during up-counting) or an underflow (when modified during down-counting). If the
GTUDDTYC.UD bit is modified while the count operation stops and the GTUDDTYC.UDF bit is 0, the
GTUDDTYC.UD bit modification is not reflected at the start of counting and the count direction changes at an overflow
or an underflow. If the UDF bit is set to 1 while the count operation stops, the GTUDDTYC.UD bit value at that time is
reflected at the start of counting.
In triangle-wave mode, the count direction does not change even though the UD bit in GTUDDTYC is modified during
the count operation. Similarly, even though the GTUDDTYC.UD bit is modified while the count operation stops and
GTUDDTYC.UDF bit is 0, the GTUDDTYC.UD bit value is not reflected to the count operation. If the
GTUDDTYC.UDF bit is set to 1 while the count operation stops, the GTUDDTYC.UD bit value at that time is reflected
at the start of counting.
If the count direction changes during a saw-wave count operation, the GTPR value after the start of up-counting is
reflected in the count cycle during up-counting and the GTPR value before the start of down-counting is reflected during
down-counting.
Figure 23.45 shows an example of the count direction changing function operation.
GTCNT counter value
bbbb
aaaa
0000 0000h
Time
Register write
GTUDDTYC.UD bit
(Count direction setting)
Up-counting
GTST.TUCF flag
(Count direction flag)
aaaa
Up-counting
Down-counting
Register write
bbbb
GTPBR register
Figure 23.45
Down-counting
Up-counting
Register write
GTPR register
Register write
Register write
aaaa
Up-counting
Register write
Register write
bbbb
Buffer transfer at
overflow
Buffer transfer at
overflow
bbbb
aaaa
Buffer transfer at
underflow
Buffer transfer at
underflow
Buffer transfer at
overflow
bbbb
Example of a count direction changing function operation during buffer operation
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23.3.6
23. General PWM Timer (GPT)
Function of Output Duty 0% and 100%
The output duty of the GTIOCA pin and the GTIOCB pin is set to 0% or 100% by changing the GTUDDTYC.OADTY
bit or GTUDDTYC.OBDTY bit.
In saw-wave mode, if the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified during the count
operation, the output duty setting is reflected at an overflow (when modified during up-counting) or an underflow (when
modified during down-counting). If the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified while
the count operation stops and the GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is 0, the output duty
modification is not reflected at the start of counting. The output duty changes at an overflow or an underflow. If the
GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is set to 1 while the count operation stops, the
GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit value at that time is reflected at the start of counting.
In triangle-wave mode, if the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified during the count
operation, the output duty setting is reflected at an underflow.
If the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified while the count operation stops and the
GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is 0, the output duty modification is not reflected at the start
of counting. The output duty changes at an underflow. If the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit
is modified while the count operation stops and the GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is 1, the
output duty modification is reflected at the start of counting.
In performing 0% or 100% duty operation, GPT internally continues to:
Perform compare match operation
Set compare match flag
Output interrupt
Perform buffer operation.
When the control is changed from 0% or 100% duty setting to compare match, the output value of the GTIOCA pin at
cycle end is determined by GTIOR.GTIOA[3:2] and GTUDDTYC.OADTYR. The output value of GTIOCB pin at cycle
end is decided by GTIOR.GTIOB[3:2] and GTUDDTYC.OBDTYR.
When GTIOR.GTIOA[3:2] and GTIOR.GTIOB[3:2] are set to 01b, the output pins output low at cycle end. When
GTIOR.GTIOA[3:2] and GTIOR.GTIOB[3:2] are set to 10b, the output pins output high at cycle end.
GTUDDTYC.OADTYR selects the value that is the object of output retained/toggled at cycle end, when
GTIOR.GTIOm[3:2] are set to 00b (output retained at cycle end) or when GTIOR.GTIOm[3:2] are set to 11b (output
toggled at cycle end). Table 23.6 shows the values of GTIOCA/GTIOCB pin output at cycle end.
Table 23.6
Output values after releasing 0% or 100% duty setting (m = A, B)
GTIOR.GTIOm[3:2]
Compare match value at
cycle end masked by 0% or
100% duty setting
GTUDDTYC.OmDTYR
in duty 0% setting
GTUDDTYC.OmDTYR
in duty 100% setting
0
1
0
1
00
(output retained at cycle end)
0
0
0
1
0
1
0
1
1
1
01
(low output at cycle end)
-
0
0
0
0
10
(high output at cycle end)
-
1
1
1
1
11
(output toggled at cycle end)
0
1
1
0
1
1
1
0
0
0
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23. General PWM Timer (GPT)
Figure 23.46 shows an example of output duty 0% and 100% function operation.
GPT320.GTCNT counter value
GPT320.GTPR register
bbbb
aaaa
0000 0000h
Time
Register write
GTUDDTYC.OADTY
00b
Register write
Register write
11b
10b
00b
GTIOC0A pin output
GTIOC0B pin output
0%
100%
[Setting examples]
GPT320.GTIOR.GTIOA[4:0] bits:
00011b
Initial output of low, output toggled at compare match, output retained at cycle end
GPT320.GTUDDTYC.OADTYR bit: 0b
Applied the value of duty 0% or 100% output to GTIOA[3:2] bits function after 0% or 100%
duty setting is released
GPT320.GTIOR.GTIOB[4:0] bits: 00011b
Initial output of low, output toggled at compare match, output retained at cycle end
GPT320.GTUDDTYC.OBDTYR bit: 1
Applied the value of masked compare match output to GTIOB[3:2] bits function after 0% or
100% duty setting is released
Figure 23.46
23.3.7
Example of output duty 0% and 100% function
Hardware Count Start/Count Stop and Clear Operation
The GTCNT counter can be started, stopped, or cleared by the following hardware sources:
Output trigger input
ELC event input
GTIOCA/GTIOCB pin input.
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23.3.7.1
23. General PWM Timer (GPT)
Hardware start operation
The GTCNT counter can be started by selecting a hardware source using GTSSR.
Figure 23.47 shows an example of a count start operation by a hardware source. Figure 23.48 shows the setting example.
GTCNT counter value
GTPR register
Count started at ELC input
0000 0000h
Time
ELC_GPTA input
Figure 23.47
Example of count start operation by a hardware source started at the input of the signal from the
ELC_GPTA event
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.47, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.47, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.47, 0000_0000h is set.
Set hardware count start
Select a hardware source for starting count operation in GTSSR register.
In Figure 23.47, GTSSR.SSELCA = 1.
Set hardware source operation
Set operation of the hardware source selected by GTSSR register and
start counting.
In Figure 23.47, the ELC_GPTA input operation is set.
Figure 23.48
Example setting for count start operation by a hardware source
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23.3.7.2
23. General PWM Timer (GPT)
Hardware stop operation
The GTCNT counter can be stopped by selecting a hardware source using GTPSR.
Figure 23.49 shows an example of a count stop operation by a hardware source. Figure 23.50 shows the setting example.
In this example, the count operation stops and restarts at the edge of the ELC event input.
GTCNT counter value
Count stopped at Count started at
ELC event input ELC event input
GTPR register
Software start
0000 0000h
Time
ELC_GPTA input
ELC_GPTB input
Figure 23.49
Example of count stop operation by a hardware source started by software, stopped at
ELC_GPTA input, and restarted at ELC_GPTB input
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.49, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.49, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.49, 0000_0000h is set.
Set hardware count start
Select a hardware source for starting count operation in GTSSR register,
and wait for count start by the hardware source.
In Figure 23.49, GTSSR.SSELCB = 1.
Set hardware count stop
Select a hardware source for stopping count operation in GTPSR
register and wait for count stop by the hardware source.
In Figure 23.49, GTPSR.PSELCA = 1.
Set hardware source operation
Set operation of the hardware source selected in GTSSR register or
GTPSR register, and start or stop counting.
In Figure 23.49, ELC_GPTA input operation and ELC_GPTB input
operation are set.
Figure 23.50
Example for setting count stop operation by a hardware source
Figure 23.51 shows an example of a count start/stop operation by a hardware source. Figure 23.52 shows the setting
example. In this example, the counter operates during the high-level periods of the external trigger input GTETRGA.
Count stopped at the falling Count started at the rising
edge of GTETRGA
edge of GTETRGA
GTCNT counter value
GTPR register
Count started at the rising
edge of GTETRGA
0000 0000h
Time
GTETRGA pin input
Figure 23.51
Example of count start/stop operation by hardware source started on rising edge of GTETRGA
pin input, and stopped at falling edge of GTETRGA pin input
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.51, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.51, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.51, 0000_0000h is set.
Set hardware count start
Select a hardware source for starting count operation with the GTSSR
register and wait for count start by the hardware source.
In Figure 23.51, GTSSR.SSGTRGAR = 1.
Set hardware count stop
Select a hardware source for stopping count operation with the GTPSR
register and wait for count stop by the hardware source.
In Figure 23.51, GTPSR.PSGTRGAF = 1.
Set hardware source operation
Set operation of the hardware source selected in GTSSR or GTPSR and
start or stop counting.
In Figure 23.51, the GTETRGA pin operation is set.
Figure 23.52
Example for setting count start/stop operation by a hardware source
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23.3.7.3
23. General PWM Timer (GPT)
Hardware clear operation
The GTCNT counter can be cleared by selecting a hardware source using GTCSR. The GPTn_OVF/GPTn_UDF (n = 0
to 9) interrupt (overflow/underflow interrupt) is not generated when the GTCNT counter is cleared by a hardware source
or by software.
Figure 23.53 and Figure 23.54 show examples of the GTCNT counter clearing operation by a hardware source. Figure
23.55 shows the setting example. In this example, the GTCNT counter starts at the edge of the ELC_GPTA input, and the
counter stops and clears at the edge of the ELC_GPTB input.
GTCNT counter value
Count stopped/cleared at
ELC event input
Count started at
ELC event input
Clear by software (by writing 1 to the
corresponding channel number bit of
GTCLR register)
Count started at
ELC event input
0000 0000h
Time
ELC_GPTA input
ELC_GPTB input
Figure 23.53
Examples of count clearing operation by hardware source with saw wave up-counting, started at
ELC_GPTA input, and stopped/cleared at ELC_GPTB input
GTCNT counter value
Count started at
ELC event input
Count stopped/cleared at
ELC event input
Count started at
ELC event input
GTPR register
0000 0000h
Clear by software (by writing 1 to
the corresponding channel number
bit of GTCLR register)
Time
ELC_GPTA input
ELC_GPTB input
Figure 23.54
Examples of count clearing operation by hardware source with saw wave down-counting, started
at ELC_GPTA input, and stopped/cleared at ELC_GPTB input
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.53 and Figure 23.54, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.53, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting). In
Figure 23.54, after 10b is set in GTUDDTYC[1:0], 00b is set in GTUDDTYC[1:0] (down-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in the GTPR register.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.53, 0000_0000h is set. In Figure 23.54, the GTPR value is set.
Set hardware count start
Select a hardware source for starting count operation in the GTSSR register and wait for count start by
the hardware source. In Figure 23.53 and Figure 23.54, GTSSR.SSELCA = 1.
Set hardware count stop
Select a hardware source for stopping count operation in the GTPSR register and wait for count stop
by the hardware source.In Figure 23.53 and Figure 23.54, GTPSR.PSELCB = 1.
Set hardware count clear
Select a hardware source for clearing count operation in the GTCSR register and wait for count clear
by the hardware source. In Figure 23.53 and Figure 23.54, GTCSR.CSELCB = 1.
Set hardware source operation
Set operation of the hardware source selected in the GTSSR, GTPSR, or GTCSR register and start,
stop, or clear counting.
In Figure 23.53 and Figure 23.54, the ELC_GPTA input and ELC_GPTB input are set.
Figure 23.55
Example for setting count clearing operation by a hardware source
The GPTn_OVF/GPTn_UDF (n = 0 to 9) interrupt (overflow/underflow interrupt) is not generated when the counter is
cleared by a hardware source or by software.
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23. General PWM Timer (GPT)
Figure 23.56 shows the relationship between the counter clearing by a hardware source and the GPTn_OVF (n = 0 to 9)
interrupt.
GTCNT counter value
GTPR register
Counter cleared
at overflow
Counter cleared by
hardware source
Clear by software (by
writing 1 to corresponding
channel number bit of
GTCLR register)
0000 0000h
Time
Hardware source counter
clear signal
GPTn_OVF (n = 0 to 9)
interrupt request
GPTn_OVF (n = 0 to 9) interrupt not generated
Figure 23.56
Relationship between counter clearing by hardware source and GPTn_OVF (n = 0 to 9) interrupt
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23.3.8
23. General PWM Timer (GPT)
Synchronized Operation
Synchronized operation on channels such as a synchronized start, stop, and clear operation can be performed.
23.3.8.1
Synchronized operation by software
The GTCNT counters can be started, stopped, and cleared on multiple channels by setting the associated GTSTR,
GTSTP, or GTCLR bits simultaneously to 1.
Count start with a phase difference is possible by setting the initial value in the GTCNT counter and setting the
associated GTSTR bits simultaneously to 1.
Figure 23.57 shows an example of a simultaneous start, stop, and clear by software. Figure 23.58 shows an example of a
phase start operation by software.
GPT320.GTCNT counter value
GPT320.GTPR register
0000 0000h
Time
GPT321.GTCNT counter value
GPT321.GTPR register
Time
0000 0000h
GPT322.GTCNT counter value
GPT322.GTPR register
Time
0000 0000h
GPT323.GTCNT counter value
GPT323.GTPR register
Time
0000 0000h
Write 0000 000Fh in
GTSTR register
(count operation started
in channel 0/1/2/3)
Figure 23.57
Write 0000 000Fh in
GTSTP or GTCLR register
(count operation stopped or
cleared in channel 0/1/2/3)
Write 0000 000Fh in
GTSTR register
(count operation started
in channel 0/1/2/3)
Example of a simultaneous start, stop, and clear by software with the same count cycle (GTPR
register value)
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23. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
GPT321.GTCNT counter value
GPT321.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
GPT322.GTCNT counter value
GPT322.GTPR register
cccc
bbbb
aaaa
Set initial value
Time
0000 0000h
GPT323.GTCNT counter value
GPT323.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
Write 0000 000Fh in GTSTR register.
(Start count operation in channel 0/1/2/3.)
Figure 23.58
Example of software phase start with the same count cycle (GTPR register value)
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23.3.8.2
23. General PWM Timer (GPT)
Synchronized operation by hardware
The GTCNT counters can be started simultaneously by the following hardware sources:
External trigger input
ELC event input.
Figure 23.59 shows an example of a simultaneous start, stop, and clear operation by a hardware source. Figure 23.60
shows the setting example.
GPT320.GTCNT counter value
GPT320.GTPR register
0000 0000h
Time
GPT321.GTCNT counter value
GPT321.GTPR register
0000 0000h
Time
GPT322.GTCNT counter value
GPT322.GTPR register
0000 0000h
Time
GPT323.GTCNT counter value
GPT323.GTPR register
0000 0000h
ELC_GPTA input
Count operation of channel
0/1/2/3 started by
ELC event input.
Count operation of channel
0/1/2/3 stopped or cleared
by ELC event input.
Time
Count operation of channel
0/1/2/3 started by
ELC event input.
ELC_GPTB input
Figure 23.59
Example of a simultaneous start, stop, and clear by a hardware source with the same count cycle
(GTPR register value)
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.59, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.59, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in the GTPR register.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.59, 0000_0000h is set.
Set hardware count start
Select a hardware source for starting count operation with the GTSSR register and wait for count start
by the hardware source.
In Figure 23.59, GTSSR.SSELCA = 1.
Set hardware count stop
Select a hardware source for stopping count operation with the GTPSR register and wait for count
stop by the hardware source.
In Figure 23.59, GTPSR.PSELCB = 1.
Set hardware count clear
Select a hardware source for clearing count operation with the GTCSR register and wait for count
clear by the hardware source.
In Figure 23.59, GTCSR.CSELCB = 1.
Set hardware source operation
Set operation of the hardware source selected in GTSSR or GTPSR or GTCSR and start or stop or
clear counting.
In Figure 23.59, ELC_GPTA input and ELC_GPTB input are set.
Figure 23.60
Example setting for simultaneous start by a hardware source
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23.3.9
(1)
23. General PWM Timer (GPT)
PWM Output Operation Examples
Synchronized PWM output
The GPT outputs 20 phases of linked PWM waveforms for a maximum of 10 channels by multiple GPTs.
Figure 23.61 shows an example in which four channels perform synchronized operation in saw-wave PWM mode and
eight phases of PWM waveforms are output. The GTIOCA is set so that it outputs low as the initial value, high at a
GTCCRA compare match, and low at the cycle end. The GTIOCB is set so that it outputs low as the initial value, high at
a GTCCRB compare match, and low at the cycle end.
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRB register
GPT320.GTCCRA register
GPT321.GTCNT counter
GPT321.GTPR register
GPT321.GTCCRB register
GPT321.GTCCRA register
GPT322.GTCNT counter
GPT322.GTPR register
GPT322.GTCCRB register
GPT322.GTCCRA register
GPT323.GTCNT counter
GPT323.GTPR register
GPT323.GTCCRB register
GPT323.GTCCRA register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2A pin output
GTIOC2B pin output
GTIOC3A pin output
GTIOC3B pin output
Figure 23.61
Example of synchronized PWM output
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23. General PWM Timer (GPT)
3-phase saw-wave complementary PWM output
Figure 23.62 shows an example in which three channels perform synchronized operation in saw-wave PWM mode and
3-phase complementary PWM waveforms are output. The GTIOCA pin is set so that it outputs low as the initial value,
high at a GTCCRA compare match, and low at the cycle end. The GTIOCB pin is set so that it outputs high as the initial
value, low at a GTCCRB compare match, and high at the cycle end.
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRA register
= GPT320.GTCCRB register
GPT321.GTCNT counter
GPT321.GTPR register
GPT321.GTCCRA register
= GPT321.GTCCRB register
GPT322.GTCNT counter
GPT322.GTPR register
GPT322.GTCCRA register
= GPT322.GTCCRB register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2B pin output
GTIOC2A pin output
Figure 23.62
Example of 3-phase saw-wave complementary PWM output
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23. General PWM Timer (GPT)
3-phase saw-wave complementary PWM output with automatic dead time setting
Figure 23.63 shows an example in which three channels perform synchronized operation in saw-wave one-shot pulse
mode with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set
so that it outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the
cycle end. The GTIOCB pin is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare
match, and retains the output at the cycle end.
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRD register
GPT320.GTCCRC register
GPT321.GTCNT counter
GPT321.GTPR register
GPT321.GTCCRD register
GPT321.GTCCRC register
GPT322.GTCNT counter
GPT322.GTPR register
GPT322.GTCCRD register
GPT322.GTCCRC register
GTIOC0A pin output
GTIOC0B pin output
GPT320.GTDVU
GPT320.GTDVU
GTIOC1A pin output
GTIOC1B pin output
GPT321.GTDVU
GPT321.GTDVU
GTIOC2A pin output
GTIOC2B pin output
GPT322.GTDVU
Figure 23.63
GPT322.GTDVU
Example of 3-phase saw-wave complementary PWM output with automatic dead time setting
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23. General PWM Timer (GPT)
3-phase triangle-wave complementary PWM output
Figure 23.64 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 1
and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set so that it outputs low as the initial
value, toggles the output at a GTCCRA compare match, and retains the output at the cycle end. The GTIOCB pin is set
so that it outputs high as the initial value, toggles the output at a GTCCRB compare match, and retains the output at the
cycle end.
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRA register
GPT320.GTCCRB register
GPT321.GTCNT counter
GPT321.GTPR register
GPT321.GTCCRA register
GPT321.GTCCRB register
GPT322.GTCNT counter
GPT322.GTPR register
GPT322.GTCCRA register
GPT322.GTCCRB register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2A pin output
GTIOC2B pin output
Figure 23.64
Example of 3-phase triangle-wave complementary PWM output
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23. General PWM Timer (GPT)
3-phase triangle-wave complementary PWM output with automatic dead time setting
Figure 23.65 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 1
with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set so
that it outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the
cycle end. The GTIOCB pin is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare
match, and retains the output at the cycle end.
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRA register
GPT321.GTCNT counter
GPT321.GTPR register
GPT321.GTCCRA register
GPT322.GTCNT counter
GPT322.GTPR register
GPT322.GTCCRA register
GPT320.GTDVU
GPT320.GTDVU
GTIOC0A pin output
GTIOC0B pin output
GPT321.GTDVU
GTIOC1A pin output
GPT321.GTDVU
GTIOC1B pin output
GTIOC2A pin output
GPT322.GTDVU
GPT322.GTDVU
GTIOC2B pin output
Figure 23.65
Example of 3-phase triangle-wave complementary PWM output with automatic dead time setting
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23. General PWM Timer (GPT)
3-phase asymmetric triangle-wave complementary PWM output with automatic dead time
setting
Figure 23.66 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 3
with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA is set so that it
outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the cycle end.
The GTIOCB is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare match, and
retains the output at the cycle end.
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRC register
GPT320.GTCCRD register
GPT321.GTCNT counter
GPT321.GTPR register
GPT321.GTCCRC register
GPT321.GTCCRD register
GPT322.GTCNT counter
GPT322.GTPR register
GPT322.GTCCRC register
GPT322.GTCCRD register
GPT320.GTDVU
GPT320.GTDVU
GTIOC0A pin output
GTIOC0B pin output
GPT321.GTDVU
GTIOC1A pin output
GPT321.GTDVU
GPT322.GTDVU
GTIOC1B pin output
GTIOC2A pin output
GPT322.GTDVU
GTIOC2B pin output
Figure 23.66
Example of 3-phase asymmetric triangle-wave complementary PWM output with automatic dead
time setting
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23.3.10
23. General PWM Timer (GPT)
Phase Counting Function
The phase difference between the GTIOCA and GTIOCB pin inputs is detected and the associated GTCNT counts up or
counts down. The detectable phase difference is available in any combination with the relationship between the edge and
the level of GTIOCA and GTIOCB pin inputs being set in the GTUPSR and GTDNSR registers. For details on count
operation, see section 23.3.1.1, Counter operation.
Figure 23.67 to Figure 23.76 show phase counting modes 1 to 5. Table 23.7 to Table 23.16 show conditions of upcounting or down-counting and list settings for the GTUPSR and GTDNSR registers.
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.67
Table 23.7
Example of phase counting mode 1
Conditions of up-counting/down-counting in phase counting mode 1
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Up-counting
GTUPSR = 0000 6900h
GTDNSR = 0000 9600h
Low
Low
High
High
Down-counting
Low
High
Low
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.68
Table 23.8
Example of phase counting mode 2 (A)
Conditions of up-counting/down-counting in phase counting mode 2 (A)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 0000 0800h
GTDNSR = 0000 0400h
Low
Low
High
High
Up-counting
Don’t care
Low
High
Low
Down-counting
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Down-counting
Up-counting
Time
Figure 23.69
Table 23.9
Example of phase counting mode 2 (B)
Conditions of up-counting/down-counting in phase counting mode 2 (B)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 0000 0200h
GTDNSR = 0000 0100h
Low
Low
Down-counting
High
Don’t care
High
Up-counting
Low
Don’t care
High
Low
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.70
Table 23.10
Example of phase counting mode 2 (C)
Conditions of up-counting/down-counting in phase counting mode 2 (C)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 0000 0A00h
GTDNSR = 0000 0500h
Low
Low
Down-counting
High
Up-counting
High
Don't care
Low
High
Up-counting
Low
Down-counting
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Down-counting
Up-counting
Time
Figure 23.71
Table 23.11
Example of phase counting mode 3 (A)
Conditions of up-counting/down-counting in phase counting mode 3 (A)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 0000 0800h
GTDNSR = 0000 8000h
Low
Low
High
Up-counting
High
Down-counting
Low
Don’t care
High
Low
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Down-counting
Up-counting
Time
Figure 23.72
Table 23.12
Example of phase counting mode 3 (B)
Conditions of up-counting/down-counting in phase counting mode 3 (B)
GTIOCA pin input
Operation
Register setting
High
GTIOCB pin input
Down-counting
Low
Don’t care
GTUPSR = 0000 0200h
GTDNSR = 0000 2000h
Low
High
High
Low
High
Up-counting
Low
Don’t care
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.73
Table 23.13
Example of phase counting mode 3 (C)
Conditions of up-counting/down-counting in phase counting mode 3 (C)
GTIOCA pin input
GTIOCB pin input
Operation
Register setting
High
Down-counting
Low
Don’t care
GTUPSR = 0000 0A00h
GTDNSR = 0000 A000h
Low
High
High
Up-counting
Down-counting
Low
Don’t care
High
Up-counting
Low
Don’t care
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT Counter
Down-counting
Up-counting
Time
Figure 23.74
Table 23.14
Example of phase counting mode 4
Conditions of up-counting/down-counting in phase counting mode 4
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Up-counting
GTUPSR = 0000 6000h
GTDNSR = 0000 9000h
Low
Low
Don’t care
High
High
Down-counting
Low
High
Don’t care
Low
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT
Up-counting
Time
Figure 23.75
Table 23.15
Example of phase counting mode 5 (A)
Conditions of up-counting/down-counting in phase counting mode 5 (A)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 0000 0C00h
GTDNSR = 0000 0000h
Low
Low
High
High
Up-counting
Don’t care
Low
High
Low
Up-counting
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT
Up-counting
Time
Figure 23.76
Table 23.16
Example of phase counting mode 5 (B)
Conditions of up-counting/down-counting in phase counting mode 5 (B)
GTIOCA pin input
GTIOCB pin input
High
Low
Operation
Register setting
Don’t care
GTUPSR = 0000 C000h
GTDNSR = 0000 0000h
Up-counting
Low
Don’t care
High
High
Up-counting
Low
Don’t care
High
Low
: Rising edge
: Falling edge
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23.3.11
23. General PWM Timer (GPT)
Output Phase Switching (GPT_OPS)
GPT_OPS provides a function for easy control of brushless DC motor operation using the Output Phase Switching
Control Register (OPSCR).
GPT_OPS outputs a PWM signal to be used for chopper control or level signal for each phase (U-positive phase/negative
phase, V-positive phase/negative phase, W-positive phase/negative phase) of the 6-phase motor control. This function
uses a soft setting value (OPSCR.UF, VF, WF) set by software or the external signals detected by the Hall element, a
PWM waveform of GPT320.GTIOCA.
Figure 23.77 shows the GPT_OPS control flow conceptual diagram.
(1)
OPSCR.
UF/VF/WF
From Hall element
GTIU
GTIV
GTIW
Synchronize
noise filter
Input select
Soft setting (UF/VF/WF)
(5)
PCLKD
sample
Input phase
PWM edge
sample
Hall sensor
input edge sample
(every PCLKD)
GPT_UVWEDGE
(Input U-phase)
(Input V-phase)
(Input W-phase)
PCLKD
External input (U/V/W)
Input selection
selector
OPS internal node name
(gtu_sync)
(gtv_sync)
(gtw_sync)
Input phase de-code
6-phase enable gen
(2)
OPS internal node name
(gtuup_en, gtulo_en)
(gtvup_en, gtvlo_en)
(gtwup_en, gtwlo_en)
(3)
Output select control
From GPT320.GTIOCA
PWM
Bus clock
(PCLKA)
GPT core clock
(PCLKD)
Figure 23.77
To brushless DC motor
GTOUUP,
GTOULO,
GTOVUP,
GTOVLO,
GTOWUP,
GTOWLO
GPT_OPS control flow conceptual diagram
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23. General PWM Timer (GPT)
Figure 23.78 shows a 6-phase level signals output example of a GPT_OPS operation.
The GPT_UVWEDGE signal in Figure 23.78 is the Hall sensor input edge to ELC output.
Input sel after “U-phase”
GTIU
Input sel after “V-phase”
GTIV
Input sel after “W-phase”
GTIW
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Figure 23.78
Register settings: OPSCR.ALIGN = 0, OPSCR.EN = 1, OPSCR.P = 0, OPSCR.N = 0, OPSCR.INV = 0
6-phase level output operation example
Figure 23.79 shows a 6-phase PWM output example of a GPT_OPS operation (chopper control).
GPT320 PWM
Input sel after “U-phase”
GTIU
Input sel after “V-phase”
GTIV
Input sel after “W-phase”
GTIW
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Figure 23.79
Register settings: OPSCR.ALIGN = 1, OPSCR.EN = 1, OPSCR.P = 1, OPSCR.N = 1, OPSCR.INV = 0
6-phase PWM output operation example with chopper control
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23. General PWM Timer (GPT)
Figure 23.80 shows an example of output disable control (6-phase PWM output operation).
GPT320 PWM
"U-phase" after input
selection
GTIU
"V-phase" after input
selection
GTIV
"W-phase" after input
selection
GTIW
Output enable
OPSCR.EN
Output Disabled Source
Select
OPSCR.GRP
Auto clear
Setting by software
00b (Group A output disable request)
Group output disable
OPSCR.GODF
Clear by software
Output disable signal
from POEG to OPS
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Register settings: OPSCR.P = 1, OPSCR.N = 1, OPSCR.INV = 0
Figure 23.80
Example of group output disable control operation
23.3.11.1
Input selection and synchronization of external input signal
In the GPT_OPS control flow conceptual diagram shown in Figure 23.77, (1) is a selection of input phase from software
settings and external input by the OPSCR.FB bit.
When OPSCR.FB bit = 0, select the external input. Enable the input signal after synchronization with the GPT clock
(PCLKD). After carrying out noise filtering (optional), set the external input to the input phase of PWM (PWM of
GPT320.GTIOCA) using falling edge sampling with OPSCR.ALIGN bit = 1.
When OPSCR.FB bit = 1, select the soft setting (OPSCR.UF, VF, WF) with the value of the input phase of PWM (PWM
of GPT320.GTIOCA) using falling edge sampling with OPSCR.ALIGN bit = 1.
When OPSCR.ALIGN bit = 0, GPT_OPS operates with the input phase of PCLKD synchronization with either
OPSCR.FB bit = 0 or OPSCR.FB bit = 1. However, in some situations, the PWM pulse width of the output U/V/W
phases (PWM output mode) of switch timing (just before/just after) is shortened.
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23. General PWM Timer (GPT)
Table 23.17 shows the input selection process and setting of associated OPSCR bits.
Table 23.17
Input selection processing method
OPSCR register
FB bit
ALIGN bit Selection of input phase sampling method (U/V/W-phase)
0
1
External Input at PWM Falling Edge Sampling
(PCLKD Sync + falling edge sample)
0
External Input at PCLKD Synchronization Output
(PCLKD Sync + Through mode)
1
Software Settings at PWM Falling Edge Sampling
(OPSCR.UF, VF, WF of falling edge sample)
0
Software Setting Value Selection
(= OPSCR.UF/VF/WF value) (= PCLKD synchronization)
1
23.3.11.2
Synchronization input/output selection
process (GPT_OPS internal node name)
Input Phase
Input U-Phase (gtu_sync)
Input V-Phase (gtv_sync)
Input W-Phase (gtw_sync)
Input sampling
The OPSCR.U, V, W bits indicate the PCLKD sampling results of the input selected by the OPSCR.FB bit.
When OPSCR.FB bit = 0 and after synchronization with the GPT clock (PCLKD) and noise filtering (optional),
OPSCR.U, V, W bits indicate the sampling results of the external input. When OPSCR.FB bit = 1, OPSCR.U, V, W bits
have the value (OPSCR.UF, VF, WF) of the soft setting.
23.3.11.3
Input phase decode
In the GPT_OPS control flow conceptual diagram shown in Figure 23.77, (2) enables the 6-phase signals by decoding
the input phase selected by the OPSCR.FB bit. The 6-phase enable signal is used for the internal processing of
GPT_OPS.
Table 23.18 shows the decode table of the input phase.
Table 23.18
Decode table of input phase
Input phase (U/V/W)
(GPT_OPS internal node name)
6-phase enable {U/V/W (Up/Lo)} by decoding input phase
(GPT_OPS internal node name)
Input Uphase
Input Vphase
Input Wphase
U-phase
(Up)
U-phase
(Lo)
V-phase
(Up)
V-phase
(Lo)
W-phase
(Up)
W-phase
(Lo)
(gtu_sync)
(gtv_sync)
(gtw_sync)
(gtuup_en)
(gtulo_en)
(gtvup_en)
(gtvlo_en)
(gtwup_en)
(gtwlo_en)
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
23.3.11.4
Output selection control
In the GPT_OPS control flow conceptual diagram in Figure 23.77, (3) represents the selection of the output waveform by
setting the OPSCR register bit.
For output selection, the following bits are relevant:
The OPSCR.EN bit controls whether to output the 6-phase output, or to stop
The OPSCR.P and OPSCR.N bits can choose from the level signal or PWM signal (chopper output) for the output
phase
The polarity of the output phase can be set to positive logic or negative logic by the OPSCR.INV bit.
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23. General PWM Timer (GPT)
Table 23.19 and Table 23.20 show the output selection control method using the OPSCR register bit.
Table 23.19
Enable-phase
output control
Output selection control method (positive phase)
Positive-phase
output (P) control
Invert-phase
output control
Output port name (positive phase = up)
(output selection internal node allocation)
OPSCR.EN bit
OPSCR.P bit
OPSCR.INV bit
GTOUUP
GTOVUP
GTOWUP
0
x
x
0
Output Stop
(External pin: Hi-Z)
GPT_OPS → 0 output
1
0
0
Level signal
(gtuup_en)
(gtvup_en)
(gtwup_en)
Level Output Mode
(Positive phase)
(Positive logic)
1
0
1
Level signal
( ~gtuup_en)
( ~gtvup_en)
( ~gtwup_en)
Level Output Mode
(Positive phase)
(Negative logic)
1
1
0
PWM signal
(PWM & gtuup_en)
(PWM & gtvup_en)
(PWM & gtwup_en)
PWM Output Mode
(Positive phase)
(Positive logic)
1
1
1
PWM signal
(~(PWM & gtuup_en))
(~(PWM & gtvup_en))
(~(PWM & gtwup_en))
PWM Output Mode
(Positive phase)
(Negative logic)
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Table 23.20
Enable-phase
output control
23. General PWM Timer (GPT)
Output selection control method (negative phase)
Negative-phase
output (N) control
Invert-phase
output control
Output port name (negative phase = Lo)
(output selection internal node allocation)
OPSCR.EN bit
OPSCR.N bit
OPSCR.INV bit
GTOULO
GTOVLO
GTOWLO
0
x
x
0
Output Stop
(External pin: Hi-Z)
GPT_OPS → 0 output
1
0
0
Level signal
(gtulo_en)
(gtvlo_en)
(gtwlo_en)
Level Output Mode
(Negative phase)
(Positive logic)
1
0
1
Level signal
( ~gtulo_en)
( ~gtvlo_en)
( ~gtwlo_en)
Level Output Mode
(Negative phase)
(Negative logic)
1
1
0
PWM signal
(PWM & gtulo_en)
(PWM & gtvlo_en)
(PWM & gtwlo_en)
PWM Output Mode
(Negative phase)
(Positive logic)
1
1
1
PWM signal
(~(PWM & gtulo_en))
(~(PWM & gtvlo_en))
(~(PWM & gtwlo_en))
PWM Output Mode
(Negative phase)
(Negative logic)
23.3.11.5
Mode
Output selection control (group output disable function)
When OPSCR.GODF = 1 and the signal value selected in the OPSCR.GRP[1:0] bit is high (output disable request), the
GPT_OPS output pins are changed to Hi-Z asynchronously and the OPSCR.EN bit is set to 0 by the output disable
request signal synchronized with PCLKD. For the return, set the OPSCR.EN = 1 after clearing the output disable request
with software.
The timing of OPSCR.EN bit set to 0 is 3 PCLKD cycles after generating the output disable request. To perform output
disable control reliably, allow at least 4 PCLKD cycles after generating the output disable request (by clearing the output
disable request flag in POEG) until the output disable request is terminated. For an example of the operation of group
output disable control, see Figure 23.80.
23.3.11.6
Event Link Controller (ELC) output
In the GPT_OPS control flow conceptual diagram shown in Figure 23.77, (5) outputs the Hall sensor input signal edge to
the ELC.
The Hall sensor input edge signal is the logical OR of the rising and falling edge signals of each U-phase/V-phase/Wphase of input sampled at PCLKD. That is, if the high period of each of the U-phase/V-phase/W-phase input is short in
duration, the Hall sensor edge input signal is not output at that time.
When OPSCR.FB bit = 0, the Hall sensor input edge signal is the logical OR of the edge signals of the external input
phase sampled at PCLKD. When OPSCR.FB bit = 1, the Hall sensor input edge signal is the logical OR of the edge of
the soft setting (OPSCR.UF, VF, WF) sampled at PCLKD.
See Figure 23.78 to Figure 23.80 for examples of the output signal to the ELC.
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23.3.11.7
23. General PWM Timer (GPT)
GPT_OPS start operation setting flow
GPT320 operation mode setting
GPT320.GTIOCA set the PWM output operation mode of the saw-wave or triangle-wave.
For details, see section 23.3.3, PWM Output Operating Mode.
Counting of GPT320
Start the count operation of GPT320 and output a PWM waveform.
GPT_OPS input data set (only software setting is selected)
Set software setting to OPSCR.UF, VF, and WF bits.
Noise filter settings of GPT_OPS external input (only external input is selected)
When using a noise filter, set the sampling clock of the noise filter in the OPSCR.NFCS[1:0] bits.
Then, the noise filter is enabled if OPSCR.NFEN bit = 1.
GPT_OPS input phase selection setting/input phase alignment setting
Select the input phase from the external input or software setting in the OPSCR.FB bit.
Select the alignment of the input phase in the OPSCR.ALIGN bit.
Setting the GPT_OPS output phase
Set the level output/PWM output of the positive/negative phase output in the OPSCR.P/OPSCR.N bit.
Set the positive logic/negative logic of the output phase in the OPSCR.INV bit.
GPT_OPS setting the group output disable function
Set the selection of the output disable source in the OPSCR.GRP[1:0] bit.
Perform the setting of on/off of the group output disable function in the OPSCR.GODF bit.
GPT_OPS Working
Setting the OPSCR.EN bit = 1 outputs the 6-phase output to drive the brushless DC motor from the
GPT_OPS.
Figure 23.81
Example for setting of GPT_OPS start operation
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23.4
23. General PWM Timer (GPT)
Interrupt Sources
23.4.1
Interrupt Sources
The GPT provides the following interrupt sources:
GTCCR input capture/compare match
GTCNT counter overflow (GTPR compare match)/underflow.
Each interrupt source has its own status flag. When an interrupt source signal is generated, the associated status flag in
GTST is set to 1. The associated status flag in GTST can be cleared by writing 0. If flag set and flag clear occur at the
same time, flag clear takes priority over flag set. These flags are automatically updated by the internal state. Table 23.21
lists the GPT interrupt sources.
Table 23.21
Interrupt sources (1 of 3)
Channel
Name
Interrupt source
Interrupt flag
DMAC/DTC
activation
0
GPT0_CCMPA
GPT320.GTCCRA input capture/compare match
TCFA
Possible
1
2
3
GPT0_CCMPB
GPT320.GTCCRB input capture/compare match
TCFB
Possible
GPT0_CMPC
GPT320.GTCCRC compare match
TCFC
Possible
GPT0_CMPD
GPT320.GTCCRD compare match
TCFD
Possible
GPT0_CMPE
GPT320.GTCCRE compare match
TCFE
Possible
GPT0_CMPF
GPT320.GTCCRF compare match
TCFF
Possible
GPT0_OVF
GPT320.GTCNT overflow (GPT320.GTPR compare match)
TCFPO
Possible
GPT0_UDF
GPT320.GTCNT underflow
TCFPU
Possible
GPT1_CCMPA
GPT321.GTCCRA input capture/compare match
TCFA
Possible
GPT1_CCMPB
GPT321.GTCCRB input capture/compare match
TCFB
Possible
GPT1_CMPC
GPT321.GTCCRC compare match
TCFC
Possible
GPT1_CMPD
GPT321.GTCCRD compare match
TCFD
Possible
GPT1_CMPE
GPT321.GTCCRE compare match
TCFE
Possible
GPT1_CMPF
GPT321.GTCCRF compare match
TCFF
Possible
GPT1_OVF
GPT321.GTCNT overflow (GPT321.GTPR compare match)
TCFPO
Possible
GPT1_UDF
GPT321.GTCNT underflow
TCFPU
Possible
GPT2_CCMPA
GPT322.GTCCRA input capture/compare match
TCFA
Possible
GPT2_CCMPB
GPT322.GTCCRB input capture/compare match
TCFB
Possible
GPT2_CMPC
GPT322.GTCCRC compare match
TCFC
Possible
GPT2_CMPD
GPT322.GTCCRD compare match
TCFD
Possible
GPT2_CMPE
GPT322.GTCCRE compare match
TCFE
Possible
GPT2_CMPF
GPT322.GTCCRF compare match
TCFF
Possible
GPT2_OVF
GPT322.GTCNT overflow (GPT322.GTPR compare match)
TCFPO
Possible
GPT2_UDF
GPT322.GTCNT underflow
TCFPU
Possible
GPT3_CCMPA
GPT323.GTCCRA input capture/compare match
TCFA
Possible
GPT3_CCMPB
GPT323.GTCCRB input capture/compare match
TCFB
Possible
GPT3_CMPC
GPT323.GTCCRC compare match
TCFC
Possible
GPT3_CMPD
GPT323.GTCCRD compare match
TCFD
Possible
GPT3_CMPE
GPT323.GTCCRE compare match
TCFE
Possible
GPT3_CMPF
GPT323.GTCCRF compare match
TCFF
Possible
GPT3_OVF
GPT323.GTCNT overflow (GPT323.GTPR compare match)
TCFPO
Possible
GPT3_UDF
GPT323.GTCNT underflow
TCFPU
Possible
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Table 23.21
23. General PWM Timer (GPT)
Interrupt sources (2 of 3)
Name
Interrupt source
4
GPT4_CCMPA
GPT164.GTCCRA input capture/compare match
TCFA
Possible
GPT4_CCMPB
GPT164.GTCCRB input capture/compare match
TCFB
Possible
GPT4_CMPC
GPT164.GTCCRC compare match
TCFC
Possible
GPT4_CMPD
GPT164.GTCCRD compare match
TCFD
Possible
GPT4_CMPE
GPT164.GTCCRE compare match
TCFE
Possible
GPT4_CMPF
GPT164.GTCCRF compare match
TCFF
Possible
GPT4_OVF
GPT164.GTCNT overflow (GPT164.GTPR compare match)
TCFPO
Possible
GPT4_UDF
GPT164.GTCNT underflow
TCFPU
Possible
GPT5_CCMPA
GPT165.GTCCRA input capture/compare match
TCFA
Possible
5
6
7
8
Interrupt flag
DMAC/DTC
activation
Channel
GPT5_CCMPB
GPT165.GTCCRB input capture/compare match
TCFB
Possible
GPT5_CMPC
GPT165.GTCCRC compare match
TCFC
Possible
GPT5_CMPD
GPT165.GTCCRD compare match
TCFD
Possible
GPT5_CMPE
GPT165.GTCCRE compare match
TCFE
Possible
GPT5_CMPF
GPT165.GTCCRF compare match
TCFF
Possible
GPT5_OVF
GPT165.GTCNT overflow (GPT165.GTPR compare match)
TCFPO
Possible
GPT5_UDF
GPT165.GTCNT underflow
TCFPU
Possible
GPT6_CCMPA
GPT166.GTCCRA input capture/compare match
TCFA
Possible
GPT6_CCMPB
GPT166.GTCCRB input capture/compare match
TCFB
Possible
GPT6_CMPC
GPT166.GTCCRC compare match
TCFC
Possible
GPT6_CMPD
GPT166.GTCCRD compare match
TCFD
Possible
GPT6_CMPE
GPT166.GTCCRE compare match
TCFE
Possible
GPT6_CMPF
GPT166.GTCCRF compare match
TCFF
Possible
GPT6_OVF
GPT166.GTCNT overflow (GPT166.GTPR compare match)
TCFPO
Possible
GPT6_UDF
GPT166.GTCNT underflow
TCFPU
Possible
GPT7_CCMPA
GPT167.GTCCRA input capture/compare match
TCFA
Possible
GPT7_CCMPB
GPT167.GTCCRB input capture/compare match
TCFB
Possible
GPT7_CMPC
GPT167.GTCCRC compare match
TCFC
Possible
GPT7_CMPD
GPT167.GTCCRD compare match
TCFD
Possible
GPT7_CMPE
GPT167.GTCCRE compare match
TCFE
Possible
GPT7_CMPF
GPT167.GTCCRF compare match
TCFF
Possible
GPT7_OVF
GPT167.GTCNT overflow (GPT167.GTPR compare match)
TCFPO
Possible
GPT7_UDF
GPT167.GTCNT underflow
TCFPU
Possible
GPT8_CCMPA
GPT168.GTCCRA input capture/compare match
TCFA
Possible
GPT8_CCMPB
GPT168.GTCCRB input capture/compare match
TCFB
Possible
GPT8_CMPC
GPT168.GTCCRC compare match
TCFC
Possible
GPT8_CMPD
GPT168.GTCCRD compare match
TCFD
Possible
GPT8_CMPE
GPT168.GTCCRE compare match
TCFE
Possible
GPT8_CMPF
GPT168.GTCCRF compare match
TCFF
Possible
GPT8_OVF
GPT168.GTCNT overflow (GPT168.GTPR compare match)
TCFPO
Possible
GPT8_UDF
GPT168.GTCNT underflow
TCFPU
Possible
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Table 23.21
23. General PWM Timer (GPT)
Interrupt sources (3 of 3)
Name
Interrupt source
9
GPT9_CCMPA
GPT169.GTCCRA input capture/compare match
TCFA
Possible
GPT9_CCMPB
GPT169.GTCCRB input capture/compare match
TCFB
Possible
GPT9_CMPC
GPT169.GTCCRC compare match
TCFC
Possible
GPT9_CMPD
GPT169.GTCCRD compare match
TCFD
Possible
GPT9_CMPE
GPT169.GTCCRE compare match
TCFE
Possible
GPT9_CMPF
GPT169.GTCCRF compare match
TCFF
Possible
GPT9_OVF
GPT169.GTCNT overflow (GPT169.GTPR compare match)
TCFPO
Possible
GPT9_UDF
GPT169.GTCNT underflow
TCFPU
Possible
(1)
Interrupt flag
DMAC/DTC
activation
Channel
GPTn_CCMPA interrupt (n = 0 to 9)
An interrupt request is generated under the following conditions:
When the GTCCRA register functions as a compare match register, the GTCNT counter value matches with the
GTCCRA register
When the GTCCRA register functions as an input capture register, the input-capture signal causes transfer of the
GTCNT counter value to the GTCCRA register.
(2)
GPTn_CCMPB interrupt (n = 0 to 9)
An interrupt request is generated under the following conditions:
When the GTCCRB register functions as a compare match register, the GTCNT counter value matches with the
GTCCRB register
When the GTCCRB register functions as an input capture register, the input-capture signal causes transfer of the
GTCNT counter value to the GTCCRB register.
(3)
GPTn_CMPC interrupt (n = 0 to 9)
An interrupt request is generated under the following condition:
When the GTCCRC register functions as a compare match register, the GTCNT counter value matches with the
GTCCRC register.
A compare match is not performed and an interrupt is not requested under the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 01b, 10b, 11b (buffer operation with the GTCCRC register).
(4)
GPTn_CMPD interrupt (n = 0 to 9)
An interrupt request is generated under the following condition:
When the GTCCRD register functions as a compare match register, the GTCNT counter value matches with the
GTCCRD register.
A compare match is not performed and an interrupt is not requested under the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 10b, 11b (buffer operation with the GTCCRD register).
(5)
GPTn_CMPE interrupt (n = 0 to 9)
An interrupt request is generated under the following condition:
When the GTCCRE register functions as a compare match register, the GTCNT counter value matches with the
GTCCRE register.
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23. General PWM Timer (GPT)
A compare match is not performed and an interrupt is not requested under the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 01b, 10b, 11b (buffer operation with the GTCCRE register).
(6)
GPTn_CMPF interrupt (n = 0 to 9)
An interrupt request is generated under the following condition:
When the GTCCRF register functions as a compare match register, the GTCNT counter value matches with the
GTCCRF register.
A compare match is not performed and an interrupt is not requested under the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 10b, 11b (buffer operation with the GTCCRF register).
(7)
GPTn_OVF interrupt (n = 0 to 9)
An interrupt request is generated under the following conditions:
In saw-wave mode, interrupt requests are enabled at overflows (when the GTCNT counter value changes from
GTPR to 0 during up-counting)
In triangle-wave mode, interrupt requests are enabled at crests (GTCNT changes from GTPR to GTPR-1)
In counting by hardware sources, overflow (GTCNT changes from GTPR to 0 in up count) has occurred.
(8)
GPTn_UDF interrupt (n = 0 to 9)
An interrupt request is generated under the following conditions:
In saw-wave mode, interrupt requests are enabled at underflows (when the GTCNT counter value changes from 0 to
GTPR during down-counting)
In triangle-wave mode, interrupt requests are enabled at troughs (GTCNT changes from 0 to 1)
In counting by hardware sources, underflow (GTCNT changes from 0 to GTPR in down count) has occurred.
Table 23.22
Interrupt signals and interrupt status flags
Interrupt signal
Interrupt status flag
GPTn_UDF
GTST[7] (TCFPU)
GPTn_OVF
GTST[6] (TCFPO)
GPTn_CMPF
GTST[5] (TCFF)
GPTn_CMPE
GTST[4] (TCFE)
GPTn_CMPD
GTST[3] (TCFD)
GPTn_CMPC
GTST[2] (TCFC)
GPTn_CCMPB
GTST[1] (TCFB)
GPTn_CCMPA
GTST[0] (TCFA)
Note:
n = 0 to 9
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23.4.2
23. General PWM Timer (GPT)
DMAC/DTC Activation
The DMAC and DTC can be activated by the interrupt in each channel. For details, see section 14, Interrupt Controller
Unit (ICU), section 17, DMA Controller (DMAC), and section 18, Data Transfer Controller (DTC).
23.5 Operations Linked by ELC
23.5.1
Event Signal Output to ELC
GPT is capable of operation linked with another module set in advance when its interrupt request signal is used as an
event signal by the Event Link Controller (ELC).
The GPT has the following ELC event signals:
Generation of compare match A interrupt (GPTn_CCMPA)
Generation of compare match B interrupt (GPTn_CCMPB)
Generation of compare match C interrupt (GPTn_CMPC)
Generation of compare match D interrupt (GPTn_CMPD)
Generation of compare match E interrupt (GPTn_CMPE)
Generation of compare match F interrupt (GPTn_CMPF)
Generation of overflow interrupt (GPTn_OVF)
Generation of underflow interrupt (GPTn_UDF).
Note:
n = 0 to 9
23.5.2
Event Signal Inputs from ELC
The GPT can perform the following operations in response to a maximum of eight events from the ELC:
Start counting, stop counting, clear counting
Up-counting, down counting
Input capture.
See section 23.3, Operation for details on hardware resources.
23.6
Noise Filter Function
Each pin for use in input capture and Hall sensor input to the GPT is equipped with a noise filter. The noise filter samples
input signals at the sampling clock and removes the pulses whose length is less than 3 sampling cycles.
The noise filter functionality includes enabling and disabling the noise filter for each pin and setting of the sampling
clock for each channel.
Figure 23.82 shows the timing of noise filtering.
Sampling clock
Noise filter enable/
disable register
Input capture input pin or
external trigger input pin
Eliminated
pulse
Matching
three times
Signal conveyed
internally
Noise filter disabled
Figure 23.82
Noise filter enabled
Timing of noise filtering
If noise filtering is enabled, the input capture operation or external trigger operation is performed on the edges of the
noise filtered signal after a delay of a minimum sampling interval × 2 + PCLKD. This is caused by the noise filtering for
the input capture input or external trigger operation.
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23.7
23. General PWM Timer (GPT)
Protection Function
23.7.1
Write-Protection for Registers
To prevent registers from being accidentally modified, registers can be write-protected in channel units by setting
GTWP.WP.
Write-protection can be set for the following registers:
GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTICASR, GTICBSR, GTCR, GTUDDTYC, GTIOR, GTINTAD,
GTST, GTBER, GTCNT, GTCCRA, GTCCRB, GTCCRC, GTCCRD, GTCCRE, GTCCRF, GTPR, GTPBR, GTDTCR,
GTDVU.
23.7.2
Disabling of Buffer Operation
If the timing of the buffer register write is delayed relative to the timing for the buffer transfer, buffer operation can be
suspended with the GTBER.BD setting. Buffer transfer can be temporarily disabled even though a buffer transfer
condition is generated during a buffer register write. This can be done by setting the associated GTBER.BD bit to 1
(buffer operation disabled) before buffer register write and clearing the bit to 0 (buffer operation enabled) after
completion of writing to all buffer registers.
Figure 23.83 shows an example of operation for disabling buffer operation.
GPT320.GTCNT counter value
GPT320.GTPR register
Time
0000 0000h
Register write timing is too late
for buffer transfer timing
Register write
GPT320.GTCCRF register
bbbb
cccc
Buffer transfer at trough
GPT320.GTCCRE register
aaaa
Buffer transfer at crest
bbbb
eeee
Buffer transfer at crest
cccc
Buffer transfer at trough
eeee
Buffer transfer at crest
aaaa
GPT320.GTCCRB register
dddd
Register write
Buffer transfer at crest
bbbb
cccc
GTBER.BD[0]
Set to 1 before
GPT320.GTCCRF
register is written
Set to 1 before
GPT320.GTCCRF
register is written
Cleared to 0 after
GPT320.GTCCRF
register is written
Buffer transfer not performed
when GTBER.BD[0] = 1
Figure 23.83
Cleared to 0 after
GPT320.GTCCRF
register is written
Cleared to 0 after
GPT320.GTCCRF
register is written
Set to 1 before
GPT320.GTCCRF
register is written
Set to 1 before
GPT320.GTCCRF
register is written
Cleared to 0 after
GPT320.GTCCRF
register is written
Example of operation for disabling buffer operation with triangle waves, double buffer operation,
buffer transfer at both troughs and crests
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23.7.3
23. General PWM Timer (GPT)
GTIOC Pin Output Negate Control
For protection from system failure, the output disable control that changes the GTIOC pin output value forcibly is
provided for GTIOC pin output by the request of output disable from POEG.
When the GTIOCA pin output value is the same as the GTIOCB pin output value, output protection is required. GPT
detects this condition and generates output disable requests to POEG based on the settings in the output disable request
permission bits, such as GTINTAD.GRPABH, GTINTAD.GRPABL. When the POEG receives output disable requests
from each channel and calculates external input using an OR operation, the POEG generates output disable requests to
GPT.
One output disable signal (representing the shared output disable request signal of the GTIOCA pin and the GTIOCB
pin) out of four output disable requests generated by the POEG is selected by setting GTINTAD.GRP[1:0]. The status of
the selected disable output request is monitored by reading the GTST.ODF bit. The output level during output disable is
set based on the GTIOR.OADF[1:0] setting for the GTIOCA pin and the GTIOR.OBDF[1:0] setting for the GTIOCB
pin.
The change to the output disable state is performed asynchronously by generating the output disable request from the
POEG. The release of the output disable state is performed at end of cycle by terminating the output disable request. The
timing of release of the output disable state is a minimum of 3 PCLKD cycles after terminating the output disable
request. To perform output disable control reliably, allow at least 4 PCLKD cycles after generating the output disable
request (by clearing the output disable request flag in POEG) until the output disable request is terminated.
When event count is performed or when the output disable state should be released immediately without waiting for the
end of cycle, GTIOR.OADF[1:0] should be set to 00b (for GTIOCA pin) or GTIOR.OBDF[1:0] should be set to 00b (for
GTIOCB pin).
Figure 23.84 shows an example of the GTIOC pin output disable control operation.
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
GPT320.GTCCRC register
bbbb
aaaa
Register write
cccc
Buffer transfer
at overflow
GPT320.GTCCRA register
Register write
Register write
Register write
bbbb
Buffer transfer
at overflow
Buffer transfer
at overflow
cccc
Negate control source
GTIOC0A pin output
GTIOC pin output low forcibly when the output
disable source is requested
Figure 23.84
Example of GTIOC pin output disable control operation in saw-wave up-counting, buffer
operation, active level 1, high output at GTCCRA compare match, low output at cycle end, and
low output at output disable
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23.8
23. General PWM Timer (GPT)
Initialization Method of Output Pins
23.8.1
Pin Settings after Reset
The GPT registers are initialized at reset. Start counting after selecting the port pin function by PmnPFS register, setting
GTIOR.OAE and GTIOR.OBE bits, and outputting the GPT function to external pins.
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
GPT320.GTCCRB register
0000 0000h
Time
Hi-Z
GTIOC0A pin output
Hi-Z
GTIOC0B pin output
Reset is released. GTIOR.OAE and OBE bits Count operation starts.
are set.
Reset
GPT initialization settings
Count operation
[Setting examples]
GTIOR.GTIOA[4:0] bits: Initial output of low, output retained at cycle end, output toggled at compare match
GTIOR.GTIOB[4:0] bits: Initial output of high, output retained at cycle end, output toggled at compare match
Figure 23.85
23.8.2
Example of pin settings after reset
Pin Initialization Due to Error during Operation
If an error occurs during GPT operation, the following four types of pin processing can be performed before pin
initialization:
Set the OAHLD and OBHLD bits in GTIOR to 1 and retain the outputs at count stop
Set the OAHLD and OBHLD bits in GTIOR to 0, specify arbitrary output values at OADFLT and OBDFLT in
GTIOR, and output the arbitrary values at count stop
Set the pin to output an arbitrary value as a general output port by setting the PDR, PODR, and PmnPFS registers of
the I/O port in advance. Set the OAE and OBE bits in GTIOR to 0, and the control bit associated with the pin in the
PmnPFS.PMR to 0 to allow arbitrary values to be output from the pin set as a general output port when an error
occurs.
Drive the output to a high impedance state using the POEG function.
When the automatic dead time setting is made, clear the GTDTCR.TDE bit to 0 after counting stops. When counting
stops, only the values of registers that are changed by a GPT external source change. If counting resumes, operation
continues from where it stopped. If counting stops, registers should be initialized before counting starts.
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23.9
23. General PWM Timer (GPT)
Usage Notes
23.9.1
Module-Stop Function Setting
Operation of the GPT can be disabled or enabled by the Module Stop Control Register. The initial setting is for operation
of the GPT to be stopped. Register access is enabled by clearing the module-stop state. For details, see section 11, Low
Power Modes.
23.9.2
(1)
Settings of GTCCRn during Compare Match Operation (n = A to F)
When automatic dead time setting is made in triangle-wave PWM mode
The GTCCRA register must satisfy the following conditions: GTDVU < GTCCRA and 0 < GTCCRA < GTPR.
(2)
When automatic dead time setting is not made in triangle-wave PWM mode
The GTCCRA register must be set within the range of 0 < GTCCRA < GTPR. If GTCCRA = 0 or GTCCRA = GTPR is
set, a compare match occurs within the cycle only when GTCCRA = 0 or GTCCRA = GTPR is satisfied. When
GTCCRA > GTPR, no compare match occurs.
Similarly, GTCCRB should be set within the range of 0 < GTCCRB < GTPR. If GTCCRB = 0 or GTCCRB = GTPR is
set, a compare match occurs within the cycle only when GTCCRB = 0 or GTCCRB = GTPR is satisfied. When
GTCCRB > GTPR, no compare match occurs.
(3)
When automatic dead time setting is made in saw-wave one-shot pulse mode
The GTCCRC and GTCCRD registers must be set to satisfy the following restrictions. If the restrictions are not satisfied,
correct output waveforms with secured dead time may not be obtained.
In up-counting: GTCCRC < GTCCRD, GTCCRC > GTDVU, GTCCRD < GTPR - GTDVU
In down-counting: GTCCRC > GTCCRD, GTCCRC < GTPR – GTDVU, GTCCRD > GTDVU.
(4)
When automatic dead time setting is not made in saw-wave one-shot pulse mode
The GTCCRC and GTCCRD registers must be set to satisfy the following restrictions. If the restrictions are not satisfied,
two compare matches do not occur and pulse output cannot be performed.
In up-counting: 0 < GTCCRC < GTCCRD < GTPR
In down-counting: GTPR > GTCCRC > GTCCRD > 0.
Similarly, GTCCRE and GTCCRF must be set to satisfy the following restrictions. If the restrictions are not satisfied,
two compare matches do not occur and pulse output cannot be performed.
In up-counting: 0 < GTCCRE < GTCCRF < GTPR
In down-counting: GTPR > GTCCRE > GTCCRF > 0.
(5)
In saw-wave PWM mode
The GTCCRA register must be set with the range of 0 < GTCCRA < GTPR. If GTCCRA = 0 or GTCCRA = GTPR is
set, a compare match occurs within the cycle only when GTCCRA = 0 or GTCCRA = GTPR is satisfied. If GTCCRA >
GTPR is set, no compare match occurs.
Similarly, GTCCRB must be set with the range of 0 < GTCCRB < GTPR. If GTCCRB = 0 or GTCCRB = GTPR is set, a
compare match occurs within the cycle only when GTCCRB = 0 or GTCCRB = GTPR is satisfied. If GTCCRB > GTPR
is set, no compare match occurs.
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23.9.3
23. General PWM Timer (GPT)
Setting the Range for the GTCNT Counter
The GTCNT counter register must be set with the range of 0 ≤ GTCNT ≤ GTPR.
23.9.4
GTCNT Counter Start/Stop
The control timing of starting and stopping the GTCNT counter by the GTCR.CST bit synchronizes the count clock that
is selected in GTCR.TPCS[2:0]. When GTCR.CST is updated, the GTCNT counter starts/stops after a count clock that is
selected in GTCR.TPCS[2:0]. Therefore, an event generated before the GTCNT counter actually starts is ignored,
resulting in cases where an event is accepted or an interrupt occurs after GTCR.CST is set to 0.
23.9.5
(1)
Priority Order of Each Event
GTCNT register
Table 23.23 shows a priority order of events updating GTCNT register.
Table 23.23
Priority order of sources updating GTCNT
Source updating GTCNT
Writing by CPU (writing to GTCNT/GTCLR)
Priority order
High
Clear by hardware sources set in GTCSR
Count up or down by hardware sources set in GTUPSR/GTDNSR
Count operation
Low
If up-counting and down-counting by hardware sources occur at the same time, the GTCNT counter value does not
change. When there is a conflict between updating the GTCNT register and reading by the CPU, pre-update data is read.
(2)
GTCR.CST bit
When there is a conflict between starting/stopping by hardware sources set in the GTSSR/GTPSR registers and writing
by the CPU (writing to GTCR/GTSTR/GTSTP registers), writing by CPU has a priority over starting/stopping by
hardware sources.
When there is a conflict between starting by hardware sources set in the GTSSR register and stopping by hardware
sources set in GTPSR register, the GTCR.CST bit value does not change. When there is a conflict between updating the
GTCR.CST bit and reading by the CPU, pre-update data is read.
(3)
GTCCRm registers (m = A to F)
When there is a conflict between input capture/buffer transfer operation and writing to GTCCRm registers, writing to
GTCCRm registers has a priority over input capture/buffer transfer operation. When there is a conflict between input
capture and writing to the counter register by the CPU or updating the counter register by hardware sources, the preupdate counter value is captured. When there is a conflict between updating the GTCCRm registers and reading by the
CPU, pre-update data is read.
(4)
GTPR registers
When there is a conflict between buffer transfer operation and writing to the GTPR register, writing to GTPR register has
a priority over buffer transfer operation. When there is a conflict between updating GTPR register and reading by the
CPU, pre-update data is read.
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24. Asynchronous General Purpose Timer (AGT)
24.
Asynchronous General Purpose Timer (AGT)
24.1
Overview
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width
or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down counter. The reload register and the down counter are allocated
in the same address, and they can be accessed with the AGT register.
Table 24.1 lists the AGT specifications, Figure 24.1 shows the AGT block diagram, and Table 24.2 lists the AGT I/O
pins.
Table 24.1
AGT specifications
Parameter
Operating modes
Description
Timer mode
The count source is counted
Pulse output mode
The count source is counted and the output is inverted at each timer underflow
Event counter mode
An external event is counted
Pulse width
measurement mode
An external pulse width is measured
Pulse period
measurement mode
An external pulse period is measured
Count source (operating clock)*2
PCLKB, PCLKB/2, PCLKB/8, AGTLCLK/d, AGTSCLK/d, or underflow signal of
AGT0*1 selectable (d = 1, 2, 4, 8, 16, 32, 64, or 128)
Interrupt/Event link function (output)
Underflow event signal or measurement complete event signal
When the counter underflows
When the measurement of the active width of the external input (AGTIOn)
is complete in pulse width measurement mode
When the set edge of the external input (AGTIOn) is input in pulse period
measurement mode.
Compare match A event signal
When the values of AGT and AGTCMA matched (compare match A
function enabled)
Compare match B event signal
When the values of AGT and AGTCMB matched (compare match B
function enabled)
Recovery from Software Standby mode can be perfomed with AGT1_AGTI,
AGT1_AGTCMAI, or AGT1_AGTCMBI.
Selectable functions
Compare match function
One or two of the compare match A register and compare match B register is
selectable.
Note 1.
Note 2.
AGT0 cannot use it. AGT1 connects directly with the underflow event signal from the AGT0 timer.
Satisfy the frequency of the peripheral module clock (PCLKB) ≥ the frequency of the count source clock.
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24. Asynchronous General Purpose Timer (AGT)
Data bus
16-bit
reload
register
CKS[2:0]
Prescaler
1, 2, 4, 8, 16,
32, 64, 128
= 110b
AGTSCLK
(Sub clock for AGT)
AGTLCLK or AGTSCLK after division
= 000b
PCLKB
PCLKB/8
= 001b
= 011b
PCLKB/2
= 100b or 110b
Underflow event signal from AGT0*2
16-bit
reload
register
TCMEA or
TCMEB = 1
TCK[2:0]
TCK[2:0]
= 100b
AGTLCLK
(LOCO clock for AGT)
16-bit
reload
register
AGT Underflows
AGT Underflows or
AGT is rewritten
TCMEA and
TCMEB = 0
AGTCMA
AGTCMB
Comparison
circuit
Comparison
circuit
TMOD[2:0]
= other than
010b
TCMEA
TSTART
Event is counted during polarity = 01b
period specified for AGTEEn*1
TCMEB
AGT
counter
Underflow
event signal/
Measurement
complete event
signal
TIPF[1:0]
TMOD[2:0]
= 011b or 100b
P403/AGTIOn pin = 11b
P402/AGTIOn pin = 10b
One edge/
both edges
switching
Polarity
selection
TEDGPL
TEDGSEL
Compare
match A event
signal
16-bit counter
= 010b
Digital
filter
Compare
match B event
signal
= 101b
TIOGT[1:0]
= 00b
Event is always counted
SEL[1:0]
TCM TCM TUN TED
AF
BF DF GF
Counter
control
circuit
Measurement
complete signal
= 00b
TMOD[2:0] = 001b
TEDGSEL = 1
Other AGTIOn pin
Q
Toggle flip-flop
TEDGSEL = 0
Q
AGTOn pin
TOE
AGTOAn pin
TOEA
TOPOLA = 1
Q
Toggle flip-flop
TOPOLA = 0
Q
AGTOBn pin
TOPOLB = 1
TOEB
Toggle flip-flop
Q
Note 1.
Note 2.
CLR
Q
TOPOLB = 0
TSTART, TSTOP, TUNDF, TCMAF, TCMBF:
TEDGSEL, TOE, TIPF[1:0], TIOGT[1:0]:
TMOD[2:0], TEDGPL, TCK[2:0]:
CKS[2:0]:
TCMEA, TOEA, TOPOLA, TCMEB, TOEB, TOPOLB:
SEL[1:0]:
CLR
CLR
Bits in AGTCR register
Bits in AGTIOC register
Bits in AGTMR1 register
Bits in AGTMR2 register
Bits in AGTCMSR register
Bits in AGTIOSEL register
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
The polarity can be selected by the EEPS bit in the AGTISR register.
AGT0 cannot use it. AGT1 uses the underflow of AGT0.
Figure 24.1
Table 24.2
AGT block diagram
AGT I/O pins
Pin name
I/O
Function
AGTEEn
Input
External event input for AGT
AGTIOn*1
Input*1/output
External event input and pulse output for AGT
AGTOn
Output
Pulse output for AGT
AGTOAn
Output
Output compare match A output for AGT
AGTOBn
Output
Output compare match B output for AGT
Note:
Note 1.
Channel number (n = 0, 1)
When AGTIOn are assigned P402 and P403, AGTIOn can only be used as input.
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24.2
24. Asynchronous General Purpose Timer (AGT)
Register Descriptions
24.2.1
AGT Counter Register (AGT)
Address(es): AGT0.AGT 4008 4000h, AGT1.AGT 4008 4100h
Value after reset:
Bit
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
b15 to b0
Note 1.
Note 2.
b15
16-bit counter and reload register
*1, *2
Setting Range
R/W
0000h to FFFFh
R/W
When 1 is written to the TSTOP bit in the AGTCR register, the 16-bit counter is forcibly stopped and set to FFFFh.
When the TCK[2:0] bit setting in the AGTMR1 register is a value other than 001b (PCLKB/8) or 011b (PCLKB/2), if the AGT
register is set to 0000h, a request signal to the ICU, the DTC and the ELC are generated once immediately after the count
starts. The AGTOn and AGTIOn output is toggled.
When the AGT register is set to 0000h in event counter mode, regardless of the value of TCK[2:0] bits, a request signal to the
ICU, the DTC and the ELC is generated once immediately after the count starts.
In addition, the AGTOn output toggles even during a period other than the specified count period. When the AGT register is set
to 0001h or more, a request signal is generated each time AGT underflows.
AGT is a 16-bit register. The write value is written to the reload register and the read value is read from the counter.
The states of the reload register and the counter change according to the TSTART bit in the AGTCR register and the
TCMEA/TCMEB bit in the AGTCMSR register. For details, see section 24.3.1, Reload Register and Counter Rewrite
Operation. The AGT register can be set with a 16-bit memory manipulation instruction.
24.2.2
AGT Compare Match A Register (AGTCMA)
Address(es): AGT0.AGTCMA 4008 4002h, AGT1.AGTCMA 4008 4102h
Value after reset:
Bit
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
b15 to b0
Note 1.
b15
16-bit compare match A data is
stored*1
Setting range
R/W
0000h to FFFFh
R/W
Set the AGTCMA register to FFFFh when compare match A is not to be used.
The AGTCMA register is a read/write register to set a value for compare match with the AGT counter. The states of the
reload register and the compare register A change according to the TSTART bit in the AGTCR register. For details, see
section 24.3.2, Reload Register and Compare Register A/B Rewrite Operation. The AGTCMA register can be set by a
16-bit memory manipulation instruction.
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24.2.3
24. Asynchronous General Purpose Timer (AGT)
AGT Compare Match B Register (AGTCMB)
Address(es): AGT0.AGTCMB 4008 4004h, AGT1.AGTCMB 4008 4104h
Value after reset:
Bit
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
b15 to b0
Note 1.
b15
16-bit compare match B data is
stored*1
Setting range
R/W
0000h to FFFFh
R/W
Set the AGTCMB register to FFFFh when compare match B is not used.
The AGTCMB register is a read/write register to set a value for compare match with the AGT counter. The states of the
reload register and the compare register B change according to the TSTART bit in the AGTCR register. For details, see
section 24.3.2, Reload Register and Compare Register A/B Rewrite Operation. The AGTCMB register can be set by a
16-bit memory manipulation instruction.
24.2.4
AGT Control Register (AGTCR)
Address(es): AGT0.AGTCR 4008 4008h, AGT1.AGTCR 4008 4108h
b7
b6
b5
b4
TCMBF TCMAF TUNDF TEDGF
Value after reset:
0
0
0
b3
—
0
b2
b1
b0
TSTOP TCSTF TSTAR
T
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TSTART
AGT Count Start *2
0: Count stops
1: Count starts.
R/W
b1
TCSTF
AGT Count Status Flag *2
0: Count stops
1: Count in progress.
R
b2
TSTOP
AGT Count Forced Stop *1
0: Writing is invalid
1: The count is forcibly stopped.
W
b3
—
Reserved
The read value is 0. The write value should be 0.
R/W
b4
TEDGF
Active Edge Judgment Flag
0: No active edge received
1: Active edge received.
R/(W)*3
b5
TUNDF
Underflow Flag
0: No underflow
1: Underflow.
R/(W)*3
b6
TCMAF
Compare Match A Flag
0: No match
1: Match.
R/(W)*3
b7
TCMBF
Compare Match B Flag
0: No match
1: Match.
R/(W)*3
Note 1.
Note 2.
Note 3.
When 1 (count is forcibly stopped) is written to the TSTOP bit, the TSTART and TCSTF bits are initialized at the same time.
The pulse output level is also initialized. The read value is 0.
For information on using TSTART and TCSTF bits, see section 24.4.1, Count Operation Start and Stop Control.
Only 0 can be written to clear the flag.
TSTART bit (AGT Count Start)
The count operation is started by writing 1 to the TSTART bit and stopped by writing 0. When this bit is set to 1, the
TCSTF bit is set to 1 (count in progress) in synchronization with the count source. Also, after 0 is written to the TSTART
bit, the TCSTF bit is set to 0 (count stops) in synchronization with the count source. For details, see section 24.4.1, Count
Operation Start and Stop Control.
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24. Asynchronous General Purpose Timer (AGT)
TCSTF bit (AGT Count Status Flag)
[Setting condition]
When 1 is written to the TSTART bit (the TCSTF bit is set to 1 in synchronization with the count source).
[Clearing conditions]
When 0 is written to the TSTART bit (the TCSTF bit is set to 0 in synchronization with the count source)
When 1 is written to the TSTOP bit.
TSTOP bit (AGT Count Forced Stop)
When 1 is written to this bit, the count is forcibly stopped. The read value is 0.
TEDGF bit (Active Edge Judgment Flag)
The TEDGF bit indicates that an active edge was detected.
[Setting condition]
When the measurement of the active width of the external input (AGTIOn) is complete in pulse width measurement
mode
When the set edge of the external input (AGTIOn) is input in pulse period measurement mode.
[Clearing condition]
When 0 is written to this bit by software.
TUNDF bit (Underflow Flag)
The TUNDF bit indicates that the counter underflowed.
[Setting condition]
When the counter underflows.
[Clearing condition]
When 0 is written to this flag by software.
TCMAF bit (Compare Match A Flag)
The TCMAF bit indicates that compare match A was detected.
[Setting condition]
When the value in the AGT register matches the value in the AGTCMA register.
[Clearing condition]
When 0 is written to this bit by software.
TCMBF bit (Compare Match B Flag)
The TCMBF bit indicates that compare match B was detected.
[Setting condition]
When the value in the AGT register matches the value in the AGTCMB register.
[Clearing condition]
When 0 is written to this bit by software.
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24.2.5
24. Asynchronous General Purpose Timer (AGT)
AGT Mode Register 1 (AGTMR1)
Address(es): AGT0.AGTMR1 4008 4009h, AGT1.AGTMR1 4008 4109h
b7
b6
—
0
Value after reset:
Bit
b5
b4
Symbol
0
b2
TEDGP
L
TCK[2:0]
0
b3
0
0
Bit name
mode *3
b1
b0
TMOD[2:0]
0
0
0
Description
R/W
b2
R/W
b2 to b0
TMOD[2:0]
Operating
b3
TEDGPL
Edge polarity *4
0: Single-edge
1: Both-edge.
R/W
b6 to b4
TCK[2:0]
Count source *1, *2, *5
b6
R/W
b7
—
Reserved
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
b0
0 0 0: Timer mode
0 0 1: Pulse output mode
0 1 0: Event counter mode
0 1 1: Pulse width measurement mode
1 0 0: Pulse period measurement mode.
Other settings are prohibited.
0
0
0
1
0
0
1
0
b4
0: PCLKB
1: PCLKB/8
1: PCLKB/2
0: Divided clock AGTLCLK specified by CKS[2:0] bits in the
AGTMR2 register
1 0 1: Underflow event signal from AGT0*6
1 1 0: Divided clock AGTSCLK specified by CKS[2:0] bits in the
AGTMR2 register.
Other settings are prohibited.
The read value is 0. The write value should be 0.
R/W
Write access to the AGTMR1 register initializes the output from the AGTOn, AGTIOn, AGTOAn and AGTOBn pins of the AGT
(n = 0, 1). For details on the output level at initialization, see the description of section 24.2.7, AGT I/O Control Register
(AGTIOC).
When event counter mode is selected, the external input (AGTIOn) is selected as the count source regardless of the setting of
TCK[2:0] bits.
Do not switch count sources during count operation. Only switch count sources when both the TSTART and TCSTF bits in the
AGTCR register are set to 0 (count stops).
The operating mode can only be changed when the count is stopped while both the TSTART and TCSTF bits in the AGTCR
register are set to 0 (count stops). Do not change the operating mode during count operation.
The TEDGPL bit is enabled only in event counter mode.
To run AGT in Software Standby mode, select AGTLCLK or AGTSCLK.
AGT0 cannot use AGT0 underflow (setting prohibited). AGT1 uses the AGT0 underflow.
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24.2.6
24. Asynchronous General Purpose Timer (AGT)
AGT Mode Register 2 (AGTMR2)
Address(es): AGT0.AGTMR2 4008 400Ah, AGT1.AGTMR2 4008 410Ah
Value after reset:
b7
b6
b5
b4
b3
LPM
—
—
—
—
0
0
0
0
0
b2
b1
b0
CKS[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CKS[2:0]
AGTLCLK/AGTSCLK
count source clock
frequency division ratio
*1, *2, *3
b2
R/W
b6 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
LPM
Low Power Mode
0: Normal mode
1: Low power mode.
R/W
Note 1.
Note 2.
Note 3.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1/1
1: 1/2
0: 1/4
1: 1/8
0: 1/16
1: 1/32
0: 1/64
1: 1/128.
Do not rewrite to the CKS[2:0] bit during count operation. Only rewrite to CKS[2:0] when both the TSTART and TCSTF bits in
the AGTCR register are set to 0 (count stops).
When the count source is AGTLCLK or AGTSCLK, CKS[2:0] switch is valid.
Do not switch the TCK[2:0] bits in the AGTMR1 register when CKS[2:0] are not 000b. Switch the TCK[2:0] bits in the AGTMR1
register after CKS[2:0] are set to 000b, and wait for 1 cycle of the count source.
LPM bit (Low Power Mode)
The LPM bit sets the low power operation, which impacts access to certain AGT registers. Set this bit to 1 to operate in
low power. When this bit is 1, access to the following registers is prohibited:
AGT/AGTCMA/AGTCMB/AGTCR.
After this bit is switched from 1 to 0, the first access to the register is constrained as follows:
AGT — Read AGT register twice. Only the second reading of data is valid.
AGT, AGTCMA, AGTCMB, and AGTCR— Allow at least 2 cycles of the count source clock when writing to the
register.
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24.2.7
24. Asynchronous General Purpose Timer (AGT)
AGT I/O Control Register (AGTIOC)
Address(es): AGT0.AGTIOC 4008 400Ch, AGT1.AGTIOC 4008 410Ch
b7
Value after reset:
b6
b5
b4
b3
b2
b1
b0
TIOGT[1:0]
TIPF[1:0]
—
TOE
—
TEDGS
EL
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TEDGSEL
I/O polarity switch
Function varies depending on the operating mode (see Table 24.3 and
Table 24.4).
The TEDGSEL bit switches the AGTOn output polarity and the AGTIOn
input/output edge and polarity. In pulse output mode, it only controls the
polarity of the AGTOn output and AGTIOn output. AGTOn output and
AGTIOn output are initialized when the AGTMR1 register is written and
the TSTOP bit in the AGTCR register is written with 1.
R/W
b1
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2
TOE
AGTOn output enable
0: AGTOn output disabled
1: AGTOn output enabled.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5 b4
R/W
b7 b6
R/W
*3
b5, b4
TIPF[1:0]
Input filter
b7, b6
TIOGT[1:0]
Count control *1, *2
Note 1.
Note 2.
Note 3.
0 0: No filter
0 1: Filter sampled at PCLKB
1 0: Filter sampled at PCLKB/8
1 1: Filter sampled at PCLKB/32.
These bits specify the sampling frequency of the filter for the AGTIOn
input. If the input to the AGTIOn pin is sampled and the value matches
three successive times, that value is taken as the input value.
0 0: Event is always counted
0 1: Event is counted during polarity period specified for AGTEEn.
Other settings are prohibited.
When AGTEEn pin is used, the polarity to count an event can be selected with the EEPS bit in the AGTISR register.
TIOGT[1:0] bits are enabled only in event counter mode.
When event counter mode operation is performed during Software Standby mode, the digital filter function cannot be used.
Table 24.3
AGTIOn I/O edge and polarity switching
Operating mode
Function
Timer mode
Not used
Pulse output mode
0: Output is started at high (initialization level: high)
1: Output is started at low (initialization level: low).
Event counter mode
0: Count on rising edge
1: Count on falling edge.
Pulse width measurement mode
0: Low-level width is measured
1: High-level width is measured.
Pulse period measurement mode
0: Measure from one rising edge to the next rising edge
1: Measure from one falling edge to the next falling edge.
Table 24.4
AGTOn output polarity switching
Operating mode
Function
All modes
0: Output is started at low (initialization level: low)
1: Output is started at high (initialization level: high).
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24.2.8
24. Asynchronous General Purpose Timer (AGT)
AGT Event Pin Select Register (AGTISR)
Address(es): AGT0.AGTISR 4008 400Dh, AGT1.AGTISR 4008 410Dh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
EEPS
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
EEPS
AGTEEn Polarity
Selection
0: An event is counted during the low-level period
1: An event is counted during the high-level period.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
24.2.9
AGT Compare Match Function Select Register (AGTCMSR)
Address(es): AGT0.AGTCMSR 4008 400Eh, AGT1.AGTCMSR 4008 410Eh
b7
—
Value after reset:
0
b6
b5
b4
TOPOL TOEB TCMEB
B
0
0
0
b3
—
0
b2
b1
b0
TOPOL TOEA TCMEA
A
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TCMEA
Compare Match A
Register Enable *1, *2
0: Disable compare match A register
1: Enable compare match A register.
R/W
b1
TOEA
AGTOAn Output
Enable *1, *2
0: AGTOAn output disabled
1: AGTOAn output enabled.
R/W
b2
TOPOLA
AGTOAn Polarity
Select *1, *2
0: AGTOAn output is started at low
1: AGTOAn output is started at high.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
TCMEB
Compare Match B
Register Enable *1, *2
0: Disable compare match B register
1: Enable compare match B register.
R/W
b5
TOEB
AGTOBn Output
Enable *1, *2
0: AGTOBn output disabled
1: AGTOBn output enabled.
R/W
b6
TOPOLB
AGTOBn Polarity
Select *1, *2
0: AGTOBn output is started at low
1: AGTOBn output is started at high.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Do not rewrite the AGTCMSR register during a count operation. Only rewrite the AGTCMSR register when both the TSTART
and TCSTF bits in the AGTCR register are set to 0 (count stops).
Do not set to 1 when in pulse width measurement mode or pulse period measurement mode.
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24.2.10
24. Asynchronous General Purpose Timer (AGT)
AGT Pin Select Register (AGTIOSEL)
Address(es): AGT0.AGTIOSEL 4008 400Fh, AGT1.AGTIOSEL 4008 410Fh
Value after reset:
Bit
b7
b6
b5
b4
b3
b2
—
—
—
TIES
—
—
SEL[1:0]
0
0
0
0
0
0
0
Symbol
b1
Bit name
Select*1
b0
0
Description
R/W
b1 b0
R/W
b1, b0
SEL[1:0]
AGTIOn Pin
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
TIES
AGTIOn Input Enable
0: External event input is disabled during Software
Standby mode
1: External event input is enabled during Software
Standby mode.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
0 0: Select the AGTIOn except for the following pins
0 1: Setting prohibited
1 0: Select the P402/AGTIOn.
P402/AGTIOn is input only. It is not possible to
output
1 1: Select the P403/AGTIOn.
P403/AGTIOn is input only. It is not possible to
output.
You must set the Pin Function Select Register. See section 20, I/O Ports.
The AGTIOSEL register sets the AGTIOn pin when using the AGTIOn in Software Standby mode. The AGTIOSEL
register can be set with an 8-bit memory manipulation instruction.
SEL[1:0] bits (AGTIOn Pin Select)
The SEL[1:0] bits select the AGTIOn pin function.
TIES bit (AGTIOn Input Enable)
The TIES bit enables or disables an external event input.
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24.3
24. Asynchronous General Purpose Timer (AGT)
Operation
24.3.1
Reload Register and Counter Rewrite Operation
Regardless of the operating mode, the timing of the rewrite operation to the reload register and the counter differs
depending on the value of the TSTART bit in the AGTCR register and of the TCMEA or TCMEB bit in the AGTCMSR
register. When the TSTART bit is 0 (count stops), the count value is directly written to the reload register and the counter.
When the TSTART bit is 1 (count starts) and the TCMEA bit and TCMEB bit are 0 (compare match A/B registers are
invalid), the value is written to the reload register in synchronization with the count source, and then to the counter in
synchronization with the next count source. When the TSTART bit is 1 (count starts) and the TCMEA bit or TCMEB bit
is 1 (compare match A register or compare match B register is valid), the value is written to the reload register in
synchronization with the count source, and then to the counter in synchronization with the underflow of the counter.
Figure 24.2 and Figure 24.3 show the timing of rewrite operation with TSTART bit value and TCMEA or TCMEB bit
value.
Write 1 to TSTART bit in AGTCR register with software
Write 1234h to AGT register with software
Write 5678h to AGT register with software
Register write clock
Count source
TSTART bit in AGTCR
register
TCMEB bit in AGTCMSR
register
TCMEA bit in AGTCMSR
register
AGT register
FFFFh
5678h
1234h
Reload register load signal
Reload register load clock
Counter load signal
Counter load clock
Figure 24.2
Reload register
FFFFh
AGT counter
FFFFh
5678h
5678h
1234h
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh 1234h 1233h 1232h 1231h 1230h
Timing of rewrite operation with TSTART bit value and TCMEA or TCMEB bit value
when compare match A register or compare match B register is invalid
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24. Asynchronous General Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register with software
Write 1234h to AGT register with software
Write 5678h to AGT register with software
Register write clock
Count source
TSTART bit in AGTCR
register
TCMEB bit in AGTCMSR
register
or
TCMEA bit in AGTCMSR
register
AGT register
FFFFh
5678h
1234h
Reload register load signal
Reload register load clock
Counter load signal
Counter load clock
Reload register
FFFFh
AGT counter
FFFFh
Figure 24.3
5678h
5678h
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh •••••
1234h
••••• 0002h 0001h 0000h 1234h1233h 1232h1231h
Timing of rewrite operation with TSTART bit value and TCMEA or TCMEB bit value
when compare match A register or compare match B register is valid
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24.3.2
24. Asynchronous General Purpose Timer (AGT)
Reload Register and Compare Register A/B Rewrite Operation
Regardless of the operating mode, the timing of the rewrite operation to compare register A/B depends on the value in
the TSTART bit in the AGTCR register. When the TSTART bit is 0 (count stops), the count value is directly written to
the reload register and compare register A/B. When the TSTART bit is 1 (count starts), the value is written to the reload
register in synchronization with the count source, and then to the compare register in synchronization with the underflow
of the counter.
Figure 24.4 shows the timing of the rewrite operation with TSTART bit value for compare register A. Compare register B
has the same timing as compare register A.
Write 1 to TSTART bit in AGTCR register with software
Write 1234h to AGTCMA register with software
Write 2345h to AGTCMA register with software
Register write clock
Count source
TSTART bit in AGTCR
register
5678h
AGT counter
AGTCMA register
FFFFh
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh 566Eh
1234h
...
0000h 5678h 5677h
2345h
Reload register A load signal
Reload register A load clock
Compare register A load signal
Compare register A load clock
Reload register of
compare match A
FFFFh
Compare register A
FFFFh
1234h
2345h
1234h
2345h
Underflow signal
Figure 24.4
Timing of rewrite operation with the TSTART bit value for compare register A
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24.3.3
24. Asynchronous General Purpose Timer (AGT)
Timer Mode
In this mode, the AGT counter is decremented by the count source selected with TCK[2:0] bits in the AGTMR1 register.
In timer mode, the count value is decremented by 1 on each rising edge of the count source. When the count value
reaches 0000h and the next count source is input, an underflow occurs and an interrupt request is generated.
Figure 24.5 shows the operation example in timer mode.
Count source
Reload register
Previous value
(0300h)
New value (1010h)
Counter reloading occurs
AGT counter
02FAh 02F9h 02F8h 02F7h 1010h 100Fh 100Eh •••••
••••• 0000h 1010h 100Fh 100Eh 100Dh 100Ch 100Bh
TUNDF bit in AGTCR
register
An underflow
occurs
Set to 0 with
software
Underflow signal
Figure 24.5
Operation example in timer mode
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24.3.4
24. Asynchronous General Purpose Timer (AGT)
Pulse Output Mode
In this mode, the counter is decremented by the count source selected with the TCK[2:0] bits in the AGTMR1 register,
and the output level of the AGTIOn and AGTOn pins is inverted each time an underflow occurs.
In pulse output mode, the count value is decremented by 1 on each rising edge of the count source. When the count value
reaches 0000h and the next count source is input, an underflow occurs and an interrupt request is generated. In addition,
a pulse can be output from the AGTIOn and AGTOn pins. The output level is inverted each time an underflow occurs.
The pulse output from the AGTOn pin can be stopped with the TOE bit in the AGTIOC register. The output level can be
selected with the TEDGSEL bit in the AGTIOC register.
Figure 24.6 shows the operation example in pulse output mode.
Write 1 to TSTART bit in AGTCR register
through software
Write 0002h to
AGT register
through software
Write 0004h to
AGT register
through software
Count source
TSTART bit in
AGTCR register
AGT register
FFFFh
Reload register
FFFFh
AGT counter
FFFFh
0002h
0004h
0002h
0002h
0004h
0001h 0000h 0002h 0001h 0000h 0002h 0001h 0000h 0002h 0001h 0004h 0003h 0002h 0001h 0000h 0004h 0003h
TEDGSEL bit in
AGTIOC register
0
AGTOn pin output
AGTIOn pin output
TUNDF bit in
AGTCR register
Set to 0 by a program
Underflow signal
Figure 24.6
Operation example in pulse output mode
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24.3.5
24. Asynchronous General Purpose Timer (AGT)
Event Counter Mode
In this mode, the counter is decremented by an external event signal input to the AGTIOn pin. Various periods for
counting events can be set with the TIOGT[1:0] bits in the AGTIOC and AGTISR registers. In addition, the filter
function for the AGTIOn input can be specified with the TIPF[1:0] bits in the AGTIOC register. The output from the
AGTOn pin can be toggled even in event counter mode.
Figure 24.7 shows the operation example in event counter mode.
Event counter mode is entered
TMOD[2:0] bits in
AGTMR1 register
010b
Event is counted at rising edge
00h
AGTIOC register
TSTART bit
in AGTCR register
Event input is started
Event input is completed
AGTIOn pin
event input
AGT counter
FFFFh
FFFEh FFFDh
0000h
FFFFh
FFFEh
Counter initial value is set
TUNDF bit in
AGTCR register
Set to 0 by a program
Underflow signal
Figure 24.7
Operation example 1 in event counter mode
Figure 24.8 shows an operation example for counting during the specified period in event counter mode (TIOGT[1:0]
bits in the AGTIOC register are set to 01b).
Timing example when the setting of operating mode is as follows :
AGTMR1 register: TMOD[2:0] = 010b (event counter mode)
AGTIOC register: TIOGT[1:0] = 01b (event is counted during specified period for external interrupt pin)
TIPF[1:0] = 00b (no filter)
TEDGSEL = 1 (count at rising edge)
AGTISR register: EEPS = 1 (high-level period is counted)
TSTART bit in
AGTCR register
Event input starts
*2
Event input to AGTIOn
pin
*1
AGTEEn pin
AGT counter
FFFFh
FFFEh
FFFDh
FFFCh
FFFBh
FFFAh
FFF9h
FFF8h
The counter initial value is set
Note 1.
Note 2.
To control synchronization, there is a delay of 2 cycles of the count source until the count operation is affected. It is also possible that the
count start timing is shifted by 1 cycle due to the phase difference between the AGTEEn and the sampling clock.
Count operation can be performed for 2 cycles of the count source immediately after the count starts, depending on the previous state
before the count stops.
To disable the count for 2 cycles immediately after the count starts, write 1 to the TSTOP bit in the AGTCR register to initialize the
internal circuit, then complete the operation settings before starting the count operation.
Figure 24.8
Operation example 2 in event counter mode
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24.3.6
24. Asynchronous General Purpose Timer (AGT)
Pulse Width Measurement Mode
In this mode, the pulse width of an external signal input to the AGTIOn pin is measured.
When the level specified by the TEDGSEL bit in the AGTIOC register is input to the AGTIOn pin, the counter is
decremented by the count source selected by TCK[2:0] bits in the AGTMR1 register. When the specified level on the
AGTIOn pin ends, the counter is stopped, the TEDGF bit in the AGTCR register is set to 1 (active edge received), and an
interrupt request is generated. The measurement of pulse width data is performed by reading the count value while the
counter is stopped. Also, when the counter underflows during measurement, the TUNDF bit in the AGTCR register is set
to 1 and an interrupt request is generated.
Figure 24.9 shows the operation example in pulse width measurement mode.
This example applies when the high-level width of the measurement pulse is measured (TEDGSEL bit in AGTIOC register = 1)
FFFFh
n = AGT register content
Measurement is started
Counter content (hex)
n
Measurement
is stopped
Measurement
is started
0000h
Underflow
Measurement
is stopped
Measurement
is started
Time
TSTART bit in
AGTCR register
Set to 1 by a program
Measurement pulse
input to AGTIOn pin
Underflow event signal/
Measurement complete event signal
TEDGF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
TUNDF bit in
AGTCR register
Set to 0 by a program
Figure 24.9
Operation example in pulse width measurement mode
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24.3.7
24. Asynchronous General Purpose Timer (AGT)
Pulse Period Measurement Mode
In this mode, the pulse period of an external signal input to the AGTIOn pin is measured. The counter is decremented by
the count source selected by the TCK[2:0] bits in the AGTMR1 register. When a pulse with the period specified by the
TEDGSEL bit in the AGTIOC register is input to the AGTIOn pin, the count value is transferred to the read-out buffer
on the rising edge of the count source. The value in the reload register is loaded to the counter at the next rising edge.
Simultaneously, the TEDGF bit in the AGTCR register is set to 1 (active edge received) and an interrupt request is
generated. The read-out buffer (AGT register) is read at this time and the difference from the reload value (see section
24.4.5, How to Calculate Event Number, Pulse Width, and Pulse Period) is the period data of the input pulse. The period
data is retained until the read-out buffer is read. When the counter underflows, the TUNDF bit in the AGTCR register is
set to 1 and an interrupt request is generated.
Figure 24.10 shows the operation example in pulse period measurement mode.
Only input pulses with a period longer than twice the period of the count source are measured. Also, the low-level and
high-level widths must both be longer than the period of the count source. If a pulse period shorter than these conditions
is input, the input might be ignored.
Count source
TSTART bit
in AGTCR register
Measurement pulse input
Counter is reloaded
AGT counter
Content of read-out buffer
0300h
0300h
02FFh 02FEh 0300h 02FFh 02FEh 02FDh02FCh 02FBh 02FAh 02F9h 02F8h 02F7h 0300h 02FFh ••••
02FFh
02FEh
02FBh 02FAh 02F9h 02F8h
02F7h
•••• 0001h 0000h 0300h 02FFh 02FEh
••••
•••• 0001h 0000h 0300h 02FFh
Counter value is read*1
Read signal of counter
*2
02FEh
*2
02F7h
Read data
TEDGF bit in
AGTCR register
TUNDF bit in
AGTCR register
*3
*3
Set to 0 with software*4
Underflow event signal/
Measurement complete event signal
Set to 0 with software*5
This example applies when the initial value of the AGT register is set to 0300h, the TEDGSEL bit in the AGTIOC register is set to 0,
and the period from one rising edge to the next edge of the measurement pulse is measured.
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Reading from the AGT register must be performed during the period from when the TEDGF bit is set to 1 (active edge received) until the
next active edge is input. The content of the read-out buffer is retained until the AGT register is read. If it is not read before the active edge
is input, the measurement result of the previous period is retained.
When the AGT register is read in pulse period measurement mode, the content of the read-out buffer is read.
When the active edge of the measurement pulse and the set edge of an external pulse are input, the TEDGF bit in the AGTCR register is
set to 1 (active edge received).
To set to 0 with software, write 0 to the TEDGF bit in the AGTCR register using an 8-bit memory manipulation instruction.
To set to 0 with software, write 0 to the TUNDF bit in the AGTCR register using an 8-bit memory manipulation instruction.
Figure 24.10
Operation example in pulse period measurement mode
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24.3.8
24. Asynchronous General Purpose Timer (AGT)
Compare Match Function
The compare match function detects matches (compare match) between the content of the AGTCMA or AGTCMB
register and the content of the AGT register. This function is enabled when the TCMEA bit or the TCMEB bit in the
AGTCMSR register is 1 (compare match A register or compare match B register is valid). The counter is decremented by
the count source selected with the TCK[2:0] bits in the AGTMR1 register, and when the values of AGT and AGTCMA
or AGTCMB match, the TCMAF/TCMBF bit in the AGTCR register is set to 1 (match), and an interrupt request is
generated.
When the compare match function is enabled, the timing of the rewrite operation to the reload register and the counter
differs. See section 24.3.1, Reload Register and Counter Rewrite Operation for details. In addition, the output level of the
AGTOAn and AGTOBn pins is inverted by the match and by the underflow. The output level can be selected with the
TOPOLA or the TOPOLB bit in the AGTCMSR register.
Figure 24.11 shows the operation example in compare match mode.
n = AGT register content
m = Compare Match A register setting value
p = Compare Match B register setting value
FFFFh
Count starts
Counter content (hex)
Underflow
Underflow
n
Matched
Matched
m
Matched
Matched
p
Time
0000h
TSTART bit in
AGTCR register
Set to 1 by a program
AGTOAn pin
output
Output inverted by compare match
Output inverted by underflow
Output inverted by compare match
Output inverted by underflow
TCMAF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Compare match A
event signal
AGTOBn pin output
Output inverted by underflow
Output inverted by compare match
Output inverted by underflow
Output inverted by compare match
TCMBF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Compare match B
event signal
AGTOn pin output
Output inverted by underflow
Output inverted by underflow
TUNDF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Underflow
event signal
Figure 24.11
Operation example in compare match mode (TOPOLA = 0, TOPOLB = 0)
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24.3.9
24. Asynchronous General Purpose Timer (AGT)
Output Settings for Each Mode
Table 24.5 to Table 24.8 list the states of pins AGTOn, AGTIOn, AGTOAn, and AGTOBn in each mode.
Table 24.5
AGTOn pin setting
AGTIOC register
Operating mode
TOE bit
TEDGSEL bit
1
1
Inverted output
0
Normal output
0
0 or 1
All modes
Table 24.6
AGTOn pin output
Output disabled
AGTIOn pin setting
AGTIOC register
Operating mode
TEDGSEL bit
Timer mode
0 or 1
Pulse output mode
Event counter mode
AGTIOn pin I/O
Input (not used)
1
Normal output
0
Inverted output
0 or 1
Input
Pulse width measurement mode
Pulse period measurement mode
Table 24.7
AGTOAn pin setting
AGTCMSR register
Operating mode
TOEA bit
TOPOLA bit
AGTOAn pin output
Timer mode
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled (not used)
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled (not used)
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled (not used)
0
0
Prohibited
Pulse output mode
Event counter mode
Pulse width measurement mode
Pulse period measurement mode
Table 24.8
AGTOBn pin setting (1 of 2)
AGTCMSR register
Operating mode
TOEB bit
Timer mode
1
Pulse output mode
AGTOBn pin output
1
Inverted output
0
Normal output
0
0 or 1
Output disabled (not used)
1
1
Inverted output
0
Normal output
0 or 1
Output disabled (not used)
0
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Table 24.8
24. Asynchronous General Purpose Timer (AGT)
AGTOBn pin setting (2 of 2)
AGTCMSR register
Operating mode
TOEB bit
TOPOLB bit
AGTOBn pin output
Event counter mode
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(Not used)
0
0
Prohibited
Pulse width measurement mode
Pulse period measurement mode
24.3.10
Standby Mode
The AGT can operate in Software Standby mode. Set it to Software Standby mode with count operation start (TSTART =
1, TCSTF = 1).
Table 24.9 and Table 24.10 show the settings that can be used in Software Standby mode.
Table 24.9
Usable settings in Software Standby mode (AGT0)
Operating mode
TCK[2:0] bits of
AGTMR1 register
Operating clock
Resurgence factor of CPU
Timer mode
100b or 110b
AGTLCLK or AGTSCLK
–
Pulse output mode
100b or 110b
AGTLCLK or AGTSCLK
–
Event counter mode
–
(invalid)
AGTIOn
–
Pulse width measurement mode
100b or 110b
AGTLCLK or AGTSCLK
–
Pulse period measurement mode
100b or 110b
AGTLCLK or AGTSCLK
–
Table 24.10
Usable settings in Software Standby mode (AGT1)
Operating mode
TCK[2:0] bits of
AGTMR1 register
Operating clock
Resurgence factor of CPU
Timer mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Compare match A/B
Pulse output mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Compare match A/B
Event counter mode
–
(Invalid)
AGTIOn
Underflow
Compare match A/B
Pulse width measurement mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Active edge
Pulse period measurement mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Active edge
Note:
Note 1.
Release of Software Standby mode is only for AGT1.
Only when AGT0 operates in Table 24.9.
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24.3.11
24. Asynchronous General Purpose Timer (AGT)
Interrupt Sources
The AGT has three interrupt sources described in Table 24.11.
Table 24.11
AGT interrupt sources
DMAC/DTC
activation
Name
Interrupt source
AGTn_AGTI
When the counter underflows
When measurement of the active width of the external input (AGTIOn) is complete in
pulse width measurement mode
When the set edge of the external input (AGTIOn) is input in pulse period measurement
mode.
Possible
AGTn_AGTCMAI
When the values of AGT and AGTCMA match
Possible
AGTn_AGTCMBI
When the values of AGT and AGTCMB match
Possible
Note:
Channel number (n = 0, 1)
24.3.12
Event Signal Output to ELC
The AGT uses the Event Link Controller (ELC) to perform a link operation to a specified module using the interrupt
request signal as the event signal. The AGT outputs compare match A, compare match B, and underflow/measurement
complete signals as event signals. For details, see section 19, Event Link Controller (ELC).
24.4
24.4.1
Usage Notes
Count Operation Start and Stop Control
When the operating mode is set to other than the event counter mode, or the count source is set to other than AGT0
underflow (TCK[2:0] = 101b):
After 1 (count starts) is written to the TSTART bit in the AGTCR register while the count is stopped, the TCSTF
bit in the AGTCR register remains 0 (count stops) for 3 cycles of the count source. Do not access the registers
associated with AGT*1 other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for 3
cycles of the count source. When the TCSTF bit is set to 0, the count stops. Do not access the registers
associated with AGT*1 other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TSTART bit from 0 to 1. See section 14, Interrupt Controller
Unit (ICU) for details.
Note 1. Registers associated with AGT— AGT, AGTCMA, AGTCMB, AGTCR, AGTMR1, AGTMR2, AGTIOC, AGTISR
and AGTCMSR
When event counter mode is set or the count source is set to AGT0 underflow (TCK[2:0] = 101b):
After 1 (count starts) is written to the TSTART bit in the AGTCR register while the count is stopped, the TCSTF
bit in the AGTCR register remains 0 (count stops) for 2 cycles of the PCLKB. Do not access the registers
associated with AGT*1 other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for 2
cycles of the PCLKB. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers
associated with AGT*1 other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TSTART bit from 0 to 1. See section 14, Interrupt Controller
Unit (ICU) for details.
Note 1. Registers associated with AGT— AGT, AGTCMA, AGTCMB, AGTCR, AGTMR1, AGTMR2, AGTIOC, AGTISR
and AGTCMSR
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24.4.2
24. Asynchronous General Purpose Timer (AGT)
Access to Counter Register
When the TSTART and TCSTF bits in the AGTCR register are both 1 (count starts), allow at least 3 cycles of the count
source clock between writes when writing to the AGT register successively.
24.4.3
When Changing Mode
The registers associated with AGT operating mode (AGTMR1, AGTMR2, AGTIOC, AGTISR, AGTCMSR, and
AGTIOC) can be changed only when the count is stopped with both the TSTART and TCSTF bits set to 0 (count stops).
Do not change these registers during count operation.
When the registers associated with AGT operating mode are changed, the values of TEDGF, TUNDF, TCMAF, and
TCMBF bits are undefined. Before starting the count, write 0 to the following bits:
TEDGF (no active edge received)
TUNDF (no underflow)
TCMAF (no match)
TCMBF (no match).
24.4.4
Digital Filter
When using the digital filter, do not start the timer operation for 5 cycles of the digital filter clock after setting TIPF[1:0]
bits and when the TEDGSEL bit in the AGTIOC register changes.
24.4.5
How to Calculate Event Number, Pulse Width, and Pulse Period
In event counter mode, event number is expressed mathematically as follows:
Event number = initial value of counter [AGT register] - counter value of active event end
In pulse width measurement mode, pulse width is expressed mathematically as follows:
Pulse width = counter value of stopping measurement - counter value of next stopping measurement
In pulse period measurement mode, input pulse period is expressed mathematically as follows:
Period of input pulse = (initial value of counter [AGT register] - reading value of the read-out buffer) + 1.
24.4.6
When Count is Forcibly Stopped by TSTOP bit
After the counter is forcibly stopped by the TSTOP bit in the AGTCR register, do not access the following I/O registers
for 1 cycle of the count source:
AGT
AGTCMA
AGTCMB
AGTCR
AGTMR1
AGTMR2.
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24.4.7
24. Asynchronous General Purpose Timer (AGT)
When Selecting AGT0 Underflow as the Count Source
Operate the AGT according to the procedures described in this section when selecting the underflow signal of AGT as
the count source.
(1)
Procedure for starting operation
1. Set AGT0 and AGT1.
2. Start the count operation of AGT1.
3. Start the count operation of AGT0.
(2)
Procedure for stopping operation
1. Stop the count operation of AGT0.
2. Stop the count operation of AGT1.
3. Stop the count source clock of AGT1 (write 000b in AGT1.AGTMR1.TCK[2:0] bits).
24.4.8
Reset of I/O Register
The I/O register of AGT is not initialized by different types of resets. For details, see section 6, Resets.
24.4.9
When Selecting PCLKB, PCLKB/8, or PCLKB/2 as the Count Source
When a reset is generated, the operation of AGT cannot be guaranteed. Set the registers associated with AGT again.
24.4.10
When Selecting AGTLCLK or AGTSCLK as the Count Source
The MSTPD2 bit in the MSTPCRD register must be set to 1 except when accessing the AGT1 registers. The MSTPD3
bit in MSTPCRD register must be set to 1 except when accessing the AGT0 registers. When a reset occurs while
MSTPD2 or MSTPD3 bit is 0, the operation of AGT1 or AGT0 cannot be guaranteed. Set the registers associated with
AGT again.
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25. Realtime Clock (RTC)
25.
Realtime Clock (RTC)
25.1
Overview
The RTC has two counting modes, calendar count mode and binary count mode, that are used by switching register
settings. For calendar count mode, the RTC has a 100 year calendar from 2000 to 2099 and automatically adjusts dates
for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count
mode can be used for calendars other than the Gregorian (Western) calendar.
The sub-clock oscillator or LOCO can be selected as the count source of the time counters. The RTC uses a 128-Hz clock
acquired by dividing the count source by a prescaler. Year, month, date, day-of-week, a.m./p.m. (in 12-hour mode), hour,
minute, second, or 32-bit binary is counted by 1/128 second.
Note:
Regardless of the use of VBATT function, set the VBTCR1.BPWSWSTP bit to 1 before the accessing the RTC
registers after cold start. For details, see Figure 12.2, Setting flow of the VBTCR1.BPWSWSTP bit, in section 12,
Battery Backup Function.
Table 25.1 lists the RTC specification, Figure 25.1 shows a block diagram, and Table 25.2 lists the I/O pins.
Table 25.1
RTC specifications
Item
Description
Count mode
Calendar count mode/binary count mode
Count source*1
Sub-clock oscillator (XCIN) or LOCO
Clock and calendar
functions
Calendar count mode
Year, month, date, day of week, hour, minute, second are counted, BCD display
12 hours/24 hours mode switching function
30 seconds adjustment function (a number less than 30 is rounded down to 00 seconds, and 30 seconds or
more are rounded up to 1 minute)
Automatic adjustment function for leap years
Binary count mode
Count seconds in 32 bits, binary display
Common to both modes
Start/stop function
The sub-second digit is displayed in binary units (1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, or 64 Hz).
Clock error correction function
Clock (1 Hz/64 Hz) output.
Interrupts
Alarm interrupt (RTC_ALM)
As an alarm interrupt condition, selectable for comparison with the following:
Calendar count mode: Year, month, date, day-of-week, hour, minute, or second can be selected
Binary count mode: Each bit of the 32-bit binary counter
Periodic interrupt (RTC_PRD)
2 seconds, 1 second, 1/2 second, 1/4 second, 1/8 second, 1/16 second, 1/32 second, 1/64 second, 1/128
second, or 1/256 second can be selected as an interrupt period
Carry interrupt (RTC_CUP)
An interrupt is generated at either of the following conditions:
- When a carry from the 64-Hz counter to the second counter is generated
- When the 64-Hz counter is changed and the R64CNT register is read at the same time.
Recovery from Software Standby mode can be performed by an alarm interrupt or periodic interrupt.
Time capture function
Times can be captured when the edge of the time capture event input pin is detected.
For every event input, month, date, hour, minute, and second are captured or the 32-bit binary counter value
is captured.
Event link function
Periodic event output (RTC_PRD)
Note 1.
The frequency of the peripheral module clock (PCLKB) ≥ the frequency of the count source clock.
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25. Realtime Clock (RTC)
Internal peripheral bus
Realtime clock (RTC)
Bus interface
To each
function
Prescaler
RCR2
XCIN
Sub-clock
oscillator
XCOUT
128 Hz
generation
for XCIN
32.768 kHz
Time counter 1 Hz/64 Hz output
128 Hz
RADJ
R64CNT
RSECCNT/
BCNT0
RHRCNT/
BCNT2
RMINCNT/
BCNT1
RDAYCNT
RWKCNT/
BCNT3
RMONCNT
RYRCNT
RTCOUT
Alarm function
RSECAR/
BCNT0AR
RMINAR/
BCNT1AR
RHRAR/
BCNT2AR
RWKAR/
BCNT3AR
RDAYAR/
BCNT0AER
RMONAR/
BCNT1AER
RYRAR
BCNT2AER
RYRAREN/
BCNT3AER
RCR4
128 Hz
generation for
LOCO
LOCO
Alarm comparison
Interrupt control
RTC_ALM
RFRH/
RFRL
RTC_PRD
RCR1
RTC_CUP
Event signal output
(RTC_PRD)
Time capture control unit
Time capture
event input pins
RTCICn
RSECCPn/
BCNT0CPn
RMINCPn/
BCNT1CPn
RHRCPn/
BCNT2CPn
RDAYCPn/
BCNT3CPn
RMONCPn
RTCCRn
R64CNT:
64 Hz counter
RSECCNT/BCNT0: Second Counter/Binary Counter 0
RMINCNT/BCNT1: Minute Counter/Binary Counter 1
RHRCNT/BCNT2: Hour Counter/Binary Counter 2
RWKCNT/BCNT3: Day-of-week Counter/Binary Counter 3
RDAYCNT:
Date Counter
RMONCNT:
Month Counter
RYRCNT:
Year Counter
RCR1:
RTC Control Register 1
RCR2:
RTC Control Register 2
RCR4:
RTC Control Register 4
RADJ:
Time Error Adjustment Register
RFRH/RFRL:
Frequency Register
Note:
Table 25.2
XCIN
Second Alarm Register/Binary Counter 0 Alarm Register
Minute Alarm Register/Binary counter 1 Alarm Register
Hour Alarm Register/Binary Counter 2 Alarm Register
Day-of-week Alarm Register/Binary Counter 3 Alarm Register
Date Alarm Register/Binary Counter 0 Alarm Enable Register
Month Alarm Register/Binary Counter 1 Alarm Enable Register
Year Alarm Register/Binary Counter 2 Alarm Enable Register
Year Alarm Enable Register/Binary Counter 3 Alarm Enable Register
Time Capture Control Register n
Second Capture Register n/BCNT0 Capture Register n
Minute Capture Register n/BCNT1 Capture Register n
Hour Capture Register n/BCNT2 Capture Register n
Date Capture Register n/BCNT3 Capture Register n
Month Capture Register n
n = 0 to 2
Figure 25.1
Pin name
RSECAR/BCNT0AR:
RMINAR/BCNT1AR:
RHRAR/BCNT2AR:
RWKAR/BCNT3AR:
RDAYAR/BCNT0AER:
RMONAR/BCNT1AER:
RYRAR/BCNT2AER:
RYRAREN/BCNT3AER:
RTCCRn:
RSECCPn/BCNT0CPn:
RMINCPn/BCNT1CPn:
RHRCPn/BCNT2CPn:
RDAYCPn/BCNT3CPn:
RMONCPn:
RTC block diagram
RTC I/O pins
I/O
Function
Input
XCOUT
Output
RTCOUT
Output
RTCIC0
Input
RTCIC1
Input
RTCIC2
Input
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Oct 29, 2018
Connect a 32.768-kHz crystal to these pins
This pin is used to output a 1-Hz/64-Hz waveform
Time capture event input pins
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25.2
25. Realtime Clock (RTC)
Register Descriptions
Write or read from the RTC registers in section 25.6.5, Notes on Writing to and Reading from Registers.
If the value in an RTC register after a reset is given as x (undefined bits) in the list, it is not initialized by a reset. When
RTC enters the reset state or a low power consumption state during counting operations, for example while the
RCR2.START bit is 1, the year, month, day of the week, date, hours, minutes, seconds, and 64-Hz counters continue to
operate.
Note:
A reset generated while writing to a register might destroy the register value. In addition, do not allow the MCU to
enter Software Standby mode immediately after setting any of these registers. For details, see section 25.6.4,
Transitions to Low Power Modes after Setting Registers.
25.2.1
64-Hz Counter (R64CNT)
Address(es): RTC.R64CNT 4004 4000h
Value after reset:
b7
b6
b5
b4
b3
—
F1HZ
F2HZ
F4HZ
F8HZ
0
x
x
x
x
b2
b1
b0
F16HZ F32HZ F64HZ
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
F64HZ
64 Hz
F32HZ
32 Hz
Indicates the state between 1 Hz and 64 Hz of the sub-second
digit
R
b1
b2
F16HZ
16 Hz
R
b3
F8HZ
8 Hz
R
b4
F4HZ
4 Hz
R
b5
F2HZ
2 Hz
R
b6
F1HZ
1 Hz
R
b7
—
Reserved
This bit is read as 0
R
R
The R64CNT counter is used in both calendar count mode and in binary count mode. The 64-Hz counter (R64CNT)
generates the period for a second by counting up periods of the 128-Hz clock. The state in the sub-second range can be
confirmed by reading this counter.
This counter is set to 00h by an RTC software reset or an execution of a 30-second adjustment. To read this counter,
follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
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25.2.2
(1)
25. Realtime Clock (RTC)
Second Counter (RSECCNT)/Binary Counter 0 (BCNT0)
In calendar count mode
Address(es): RTC.RSECCNT 4004 4002h
b7
b6
—
b4
b3
SEC10[2:0]
x
Value after reset:
b5
x
x
b2
b1
b0
SEC1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
SEC1[3:0]
1-Second Count
Counts from 0 to 9 every second. When a carry is generated, 1 is
added to the tens place.
R/W
b6 to b4
SEC10[2:0]
10-Second Count
Counts from 0 to 5 for 60-second counting
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RSECCNT counter sets and counts the BCD-coded second value. It counts the carries generated once per second in
the 64-Hz counter.
The setting range is decimal 00 to 59. The RTC does not operate normally if any other value is set. Before writing to this
register, be sure to stop the count operation using the START bit in RCR2.
To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
(2)
In binary count mode
Address(es): RTC.BCNT0 4004 4002h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[7:0]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT0 is a read/write 32-bit binary counter b7 to b0. The 32-bit binary counter performs count operation by a carry
generated for each second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using
the START bit in RCR2. To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
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25.2.3
(1)
25. Realtime Clock (RTC)
Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1)
In calendar count mode
Address(es): RTC.RMINCNT 4004 4004h
b7
b6
—
x
Value after reset:
b5
b4
b3
MIN10[2:0]
x
x
b2
b1
b0
MIN1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MIN1[3:0]
1-Minute Count
Counts from 0 to 9 every minute. When a carry is generated, 1 is
added to the tens place.
R/W
b6 to b4
MIN10[2:0]
10-Minute Count
Counts from 0 to 5 for 60-minute counting
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RMINCNT counter sets and counts the BCD-coded minute value. It counts carries generated once per minute in the
second counter.
A value from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
(2)
In binary count mode
Address(es): RTC.BCNT1 4004 4004h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[15:8]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT1 counter is a read/write 32-bit binary counter b15 to b8. The 32-bit binary counter performs count operation
by a carry generated for each second of the 64-Hz counter. Before writing to this register, be sure to stop the count
operation using the START bit in RCR2. To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz
Counter and Time.
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25.2.4
(1)
25. Realtime Clock (RTC)
Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2)
In calendar count mode
Address(es): RTC.RHRCNT 4004 4006h
Value after reset:
b7
b6
b5
—
PM
HR10[1:0]
x
x
x
b4
x
b3
b2
b1
b0
HR1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
HR1[3:0]
1-Hour Count
Counts from 0 to 9 once every hour. When a carry is generated, 1
is added to the tens place.
R/W
b5, b4
HR10[1:0]
10-Hour Count
Counts from 0 to 2 once per carry from the ones place.
R/W
b6
PM
PM
Time counter setting for AM/PM.
0: AM
1: PM.
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RHRCNT counter sets and counts the BCD-coded hour value. It counts carries generated once every hour in the
minute counter. The specifiable time differs according to the setting in the hours mode bit (RCR2.HR24):
When the RCR2.HR24 bit is 0 – from 00 to 11 (in BCD)
When the RCR2.HR24 bit is 1 – from 00 to 23 (in BCD).
If a value outside of this range is specified, the RTC does not operate correctly. Before writing to this register, be sure to
stop the count operation using the START bit in RCR2. The PM bit is only enabled when the RCR2.HR24 bit is 0.
Otherwise, the setting in the PM bit has no effect. To read this counter, follow the procedure in section 25.3.5, Reading
64-Hz Counter and Time.
(2)
In binary count mode
Address(es): RTC.BCNT2 4004 4006h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[23:16]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT2 counter is a read/write 32-bit binary counter b23 to b16. The 32-bit binary counter performs count operation
by a carry generated for each second of the 64-Hz counter. Before writing to this register, be sure to stop the count
operation using the START bit in RCR2. To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz
Counter and Time.
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25.2.5
(1)
25. Realtime Clock (RTC)
Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3)
In calendar count mode
Address(es): RTC.RWKCNT 4004 4008h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
x
x
x
x
x
b2
b1
b0
DAYW[2:0]
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b2 to b0
DAYW[2:0]
Day-of-Week Counting
b2
R/W
b7 to b3
—
Reserved
Set these bits to 0. They are read as the set value.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: Sunday
1: Monday
0: Tuesday
1: Wednesday
0: Thursday
1: Friday
0: Saturday
1: Setting prohibited.
R/W
The RWKCNT counter sets and counts in the coded day-of-week value. It counts the carries generated once per day in
the hour counter. A value from 0 through 6 can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
(2)
In binary count mode
Address(es): RTC.BCNT3 4004 4008h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[31:24]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT3 is a read/write 32-bit binary counter b31 to b24 that performs count operation by a carry generated for each
second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START bit in
RCR2. To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
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25.2.6
25. Realtime Clock (RTC)
Day Counter (RDAYCNT)
Address(es): RTC.RDAYCNT 4004 400Ah
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
DATE10[1:0]
x
x
b2
b1
b0
DATE1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DATE1[3:0]
1-Day Count
Counts from 0 to 9 once per day. When a carry is generated, 1 is
added to the tens place.
R/W
b5, b4
DATE10[1:0]
10-Day Count
Counts from 0 to 3 once per carry from the ones place
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RDAYCNT counter is used in calendar count mode to set and count the BCD-coded date value. It counts carries
generated once per day in the hour counter. The count operation depends on the month and whether the year is a leap
year. Leap years are determined according to whether the year counter (RYRCNT) value is divisible by 400, 100, and 4.
A value from 01 through 31 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. When specifying a value, the range of specifiable days depends on the month and whether the year is a
leap year. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To read this
counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
25.2.7
Month Counter (RMONCNT)
Address(es): RTC.RMONCNT 4004 400Ch
Value after reset:
b7
b6
b5
b4
—
—
—
MON10
0
0
0
x
b3
b2
b1
b0
MON1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MON1[3:0]
1-Month Count
Counts from 0 to 9 once per month. When a carry is generated, 1
is added to the tens place
R/W
b4
MON10
10-Month Count
Counts from 0 to 1 once per carry from the ones place
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RMONCNT counter is used in calendar count mode to set and count the BCD-coded month value. It counts carries
generated once per month in the date counter.
A value from 01 through 12 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
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25.2.8
25. Realtime Clock (RTC)
Year Counter (RYRCNT)
Address(es): RTC.RYRCNT 4004 400Eh
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Value after reset:
b7
b6
b5
b4
b3
YR10[3:0]
x
x
x
b2
b1
b0
YR1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
YR1[3:0]
1-Year Count
Counts from 0 to 9 once per year. When a carry is generated, 1 is
added to the tens place.
R/W
b7 to b4
YR10[3:0]
10-Year Count
Counts from 0 to 9 once per carry from ones place. When a carry
is generated in the tens place, 1 is added to the hundreds place.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RYRCNT counter is used in calendar count mode to set and count the BCD-coded year value. It counts carries
generated once per year in the month counter.
A value from 00 through 99 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
25.2.9
(1)
Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register
(BCNT0AR)
In calendar count mode
Address(es): RTC.RSECAR 4004 4010h
b7
b6
ENB
x
Value after reset:
b5
b4
b3
SEC10[2:0]
x
x
b2
b1
b0
SEC1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
SEC1[3:0]
1 Second
Value for the ones place of seconds
R/W
b6 to b4
SEC10[2:0]
10 Seconds
Value for the tens place of seconds
R/W
b7
ENB
ENB
0: The register value is not compared with the RSECCNT counter value
1: The register value is compared with the RSECCNT counter value.
R/W
RSECAR is an alarm register associated with the BCD-coded second counter RSECCNT. When the ENB bit is set to 1,
the RSECAR value is compared with the RSECCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
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25. Realtime Clock (RTC)
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RSECAR
values from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. This register is set to 00h by an RTC software reset.
(2)
In binary count mode
Address(es): RTC.BCNT0AR 4004 4010h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[7:0]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT0AR is a read/write alarm register associated with the 32-bit binary counter b7 to b0. This register is set to 00h by
an RTC software reset.
25.2.10
(1)
Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR)
In calendar count mode
Address(es): RTC.RMINAR 4004 4012h
b7
b6
ENB
x
Value after reset:
b5
b4
b3
MIN10[2:0]
x
x
b2
b1
b0
MIN1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MIN1[3:0]
1 Minute
Value for the ones place of minutes
R/W
b6 to b4
MIN10[2:0]
10 Minutes
Value for the tens place of minutes
R/W
b7
ENB
ENB
0: The register value is not compared with the RMINCNT counter value
1: The register value is compared with the RMINCNT counter value.
R/W
RMINAR is an alarm register associated with the BCD-coded minute counter RMINCNT. When the ENB bit is set to 1,
the RMINAR value is compared with the RMINCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RMINAR
values from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. This register is set to 00h by an RTC software reset.
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25. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT1AR 4004 4012h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[15:8]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT1AR is a read/write alarm register associated with the 32-bit binary counter from b15 to b8. This register is set to
00h by an RTC software reset.
25.2.11
(1)
Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register
(BCNT2AR)
In calendar count mode
Address(es): RTC.RHRAR 4004 4014h
b7
b6
b5
ENB
PM
HR10[1:0]
x
x
Value after reset:
x
b4
x
b3
b2
b1
b0
HR1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
HR1[3:0]
1 Hour
Value for the ones place of hours
R/W
b5, b4
HR10[1:0]
10 Hours
Value for the tens place of hours
R/W
b6
PM
PM
Time Alarm Setting for AM/PM:
0: AM
1: PM.
R/W
b7
ENB
ENB
0: The register value is not compared with the RHRCNT counter value
1: The register value is compared with the RHRCNT counter value.
R/W
RHRAR is an alarm register associated with the BCD-coded hour counter RHRCNT. When the ENB bit is set to 1, the
RHRAR value is compared with the RHRCNT value. From the following alarm registers, only those selected with the
ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The specifiable
time differs according to the setting in the hours mode bit (RCR2.HR24):
When the RCR2.HR24 bit is 0 – From 00 to 11 (in BCD)
When the RCR2.HR24 bit is 1 – From 00 to 23 (in BCD).
If a value outside of this range is specified, the RTC does not operate correctly. When the RCR2.HR24 bit is 0, be sure to
set the PM bit. When the RCR2.HR24 bit is 1, the setting in the PM bit has no effect. This register is set to 00h by an
RTC software reset.
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25. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT2AR 4004 4014h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[23:16]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT2AR is a read/write alarm register associated with the 32-bit binary counter b23 to b16. This register is set to 00h
by an RTC software reset.
25.2.12
(1)
Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register
(BCNT3AR)
In calendar count mode
Address(es): RTC.RWKAR 4004 4016h
b7
b6
b5
b4
b3
ENB
—
—
—
—
x
x
x
x
x
Value after reset:
b2
b1
b0
DAYW[2:0]
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b2 to b0
DAYW[2:0]
Day-of-Week Setting
b2
R/W
b6 to b3
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RWKCNT counter value
1: The register value is compared with the RWKCNT counter value.
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: Sunday
1: Monday
0: Tuesday
1: Wednesday
0: Thursday
1: Friday
0: Saturday
1: Setting prohibited.
RWKAR is an alarm register associated with the coded day-of-week counter RWKCNT. When the ENB bit is set to 1,
the RWKAR value is compared with the RWKCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the corresponding counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values all match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RWKAR
values from 0 through 6 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate
correctly. This register is set to 00h by an RTC software reset.
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25. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT3AR 4004 4016h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[31:24]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT3AR is a read/write alarm register associated with the 32-bit binary counter b31 to b24. This register is set to 00h
by an RTC software reset.
25.2.13
(1)
Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register
(BCNT0AER)
In calendar count mode
Address(es): RTC.RDAYAR 4004 4018h
b7
b6
ENB
—
x
x
Value after reset:
b5
b4
b3
DATE10[1:0]
x
x
b2
b1
b0
DATE1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DATE1[3:0]
1 Day
Value for the ones place of days
R/W
b5, b4
DATE10[1:0]
10 Days
Value for the tens place of days
R/W
b6
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RDAYCNT counter value
1: The register value is compared with the RDAYCNT counter value.
R/W
RDAYAR is an alarm register associated with the BCD-coded date counter RDAYCNT. When the ENB bit is set to 1, the
RDAYAR value is compared with the RDAYCNT value. From the following alarm registers, only those selected with the
ENB bits set to 1 are compared with the corresponding counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RDAYAR
values from 01 through 31 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. This register is set to 00h by an RTC software reset.
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25. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT0AER 4004 4018h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[7:0]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT0AER is a read/write register to set the alarm enable associated with the 32-bit binary counter b7 to b0. The binary
counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm register
(BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt becomes 1. This register is
set to 00h by an RTC software reset.
25.2.14
(1)
Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register
(BCNT1AER)
In calendar count mode
Address(es): RTC.RMONAR 4004 401Ah
b7
b6
b5
b4
ENB
—
—
MON10
x
x
x
x
Value after reset:
b3
b2
b1
b0
MON1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MON1[3:0]
1 Month
Value for the ones place of months
R/W
b4
MON10
10 Months
Value for the tens place of months
R/W
b6, b5
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RMONCNT counter value
1: The register value is compared with the RMONCNT counter value.
R/W
RMONAR is an alarm register associated with the BCD-coded month counter RMONCNT. When the ENB bit is set to 1,
the RMONAR value is compared with the RMONCNT value. From the following alarm registers, only those selected
with the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RMONAR
values from 01 through 12 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. This register is set to 00h by an RTC software reset.
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25. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT1AER 4004 401Ah
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[15:8]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT1AER is a read/write register for setting the alarm enable associated with the 32-bit binary counter b15 to b8. The
binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm
register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt sets to 1. This
register is set to 00h by an RTC software reset.
25.2.15
(1)
Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register
(BCNT2AER)
In calendar count mode
Address(es): RTC.RYRAR 4004 401Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
YR10[3:0]
x
x
x
b2
b1
b0
YR1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
YR1[3:0]
1 Year
Value for the ones place of years
R/W
b7 to b4
YR10[3:0]
10 Years
Value for the tens place of years
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RYRAR is an alarm register associated with the BCD-coded year counter RYRCNT. The RYRAR values from 00
through 99 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate correctly.
This register is set to 0000h by an RTC software reset.
(2)
In binary count mode
Address(es): RTC.BCNT2AER 4004 401Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[23:16]
x
x
x
x
x
x: Undefined
BCNT2AER is a read/write register for setting the alarm enable associated with the 32-bit binary counter b23 to b16. The
binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm
register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt sets to 1. This
register is set to 0000h by an RTC software reset.
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25.2.16
(1)
25. Realtime Clock (RTC)
Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable
Register (BCNT3AER)
In calendar count mode
Address(es): RTC.RYRAREN 4004 401Eh
b7
b6
b5
b4
b3
b2
b1
b0
ENB
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
Value after reset:
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RYRCNT counter value
1: The register value is compared with the RYRCNT counter value.
R/W
When the ENB bit in RYRAREN is set to 1, the RYRAR value is compared with the RYRCNT value. From the
following alarm registers, only those selected with the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. This register is set
to 00h by an RTC software reset.
(2)
In binary count mode
Address(es): RTC.BCNT3AER 4004 401Eh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[31:24]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT3AER is a read/write register for setting the alarm enable associated with the 32-bit binary counter b31 to b24. The
binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm
register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt is set to 1. This
register is set to 00h by an RTC software reset.
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25.2.17
25. Realtime Clock (RTC)
RTC Control Register 1 (RCR1)
Address(es): RTC.RCR1 4004 4022h
b7
b6
b5
b4
PES[3:0]
x
Value after reset:
x
x
b3
b2
b1
b0
RTCOS
PIE
CIE
AIE
0
x
0
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
AIE
Alarm Interrupt Enable
0: An alarm interrupt request is disabled
1: An alarm interrupt request is enabled.
R/W
b1
CIE
Carry Interrupt Enable
0: A carry interrupt request is disabled
1: A carry interrupt request is enabled.
R/W
b2
PIE
Periodic Interrupt Enable
0: A periodic interrupt request is disabled
1: A periodic interrupt request is enabled.
R/W
b3
RTCOS
RTCOUT Output Select
0: RTCOUT outputs 1 Hz
1: RTCOUT outputs 64 Hz.
R/W
b7 to b4
PES[3:0]
Periodic Interrupt Select
b7
R/W
Note 1.
b4
0 1 1 0: A periodic interrupt is generated every 1/256 second*1
0 1 1 1: A periodic interrupt is generated every 1/128 second
1 0 0 0: A periodic interrupt is generated every 1/64 second
1 0 0 1: A periodic interrupt is generated every 1/32 second
1 0 1 0: A periodic interrupt is generated every 1/16 second
1 0 1 1: A periodic interrupt is generated every 1/8 second
1 1 0 0: A periodic interrupt is generated every 1/4 second
1 1 0 1: A periodic interrupt is generated every 1/2 second
1 1 1 0: A periodic interrupt is generated every 1 second
1 1 1 1: A periodic interrupt is generated every 2 seconds.
Other settings: No periodic interrupts are generated.
When LOCO is selected (RCR4.RCKSEL = 1) while PES[3:0] = 0110b, a periodic interrupt is generated every 1/128 second.
The RCR1 register is used in both calendar count mode and in binary count mode. Bits AIE, PIE, and PES[3:0] are
updated synchronously with the count source. When the RCR1 register is modified, check that all the bits are updated
before proceeding.
AIE bit (Alarm Interrupt Enable)
The AIE bit enables or disables alarm interrupt requests.
CIE bit (Carry Interrupt Enable)
The CIE bit enables and disables interrupt requests when a carry to the RSECCNT/BCNT0 register occurs, or when a
carry to the 64-Hz counter (R64CNT) occurs while reading the 64-Hz counter.
PIE bit (Periodic Interrupt Enable)
The PIE bit enables or disabled a periodic interrupt.
RTCOS bit (RTCOUT Output Select)
The RTCOS bit selects the RTCOUT output period. The RTCOS bit must be rewritten while the count operation is
stopped (the RCR2.START bit is 0) and the RTCOUT output is disabled (the RCR2.RTCOE bit is 0). When the
RTCOUT is output to an external pin, the RCR2.RTCOE bit must be enabled. For details on controlling I/O ports, see
section 20.5.1, Procedure for Specifying the Pin Functions.
PES[3:0] bits (Periodic Interrupt Select)
The PES[3:0] bits specify the period for the periodic interrupt. A periodic interrupt is generated with the period specified
by these bits.
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25.2.18
(1)
25. Realtime Clock (RTC)
RTC Control Register 2 (RCR2)
In calendar count mode
Address(es): RTC.RCR2 4004 4024h
b7
CNTM
D
Value after reset:
x
b6
b5
b4
b3
b2
b1
b0
HR24 AADJP AADJE RTCOE ADJ30 RESET START
x
x
x
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
START
Start
0: Prescaler and time counter are stopped
1: Prescaler and time counter operate normally.
R/W
b1
RESET
RTC Software Reset
In writing
0: Writing is invalid
1: The prescaler and the target registers for RTC software
reset *1 are initialized.
In reading
0: In normal time operation, or an RTC software reset has
completed
1: During an RTC software reset.
R/W
b2
ADJ30
30-Second Adjustment
In writing
0: Writing is invalid
1: 30-second adjustment is executed.
In reading
0: In normal time operation, or 30-second adjustment has
completed
1: During 30-second adjustment.
R/W
b3
RTCOE
RTCOUT Output Enable
0: RTCOUT output disabled
1: RTCOUT output enabled.
R/W
b4
AADJE
Automatic Adjustment Enable *2
0: Automatic adjustment is disabled
1: Automatic adjustment is enabled.
R/W
b5
AADJP
Automatic Adjustment Period
Select *2
0: The RADJ.ADJ[5:0] setting value is adjusted from the count
value of the prescaler every minute
1: The RADJ.ADJ[5:0] setting value is adjusted from the count
value of the prescaler every 10 seconds.
R/W
b6
HR24
Hours Mode
0: RTC operates in 12-hour mode
1: RTC operates in 24-hour mode.
R/W
b7
CNTMD
Count Mode Select
0: Calendar count mode
1: Binary count mode.
R/W
Note 1.
Note 2.
R64CNT, RSECAR/BCNT0AR, RMINAR/BCNT1AR, RHRAR/BCNT2AR, RWKAR/BCNT3AR, RDAYAR/BCNT0AER,
RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RTCCRy, RSECCPy/BCNT0CPy, RMINCPy/
BCNT1CPy, RHRCPy/BCNT2CPy, RDAYCPy/BCNT3CPy, RMONCPy, RCR2.ADJ30, RCR2.AADJE, RCR2.AADJP.
When LOCO is selected, the setting of this bit is disabled.
The RCR2 register is related to hours mode, automatic adjustment function, enabling RTCOUT output, 30-second
adjustment, RTC software reset, and controlling count operation.
START bit (Start)
The START bit stops or restarts the prescaler or time counter operation.
The START bit is updated in synchronization with the next cycle of the count source. When the START bit is modified,
check that the bit is updated before proceeding.
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25. Realtime Clock (RTC)
RESET bit (RTC Software Reset)
The RESET bit initializes the prescaler and registers to be reset by RTC software.
When 1 is written to the RESET bit, initialization starts in synchronization with the count source. When the initialization
is completed, the RESET bit is automatically set to 0. Check that this bit is set to 0 before proceeding.
ADJ30 bit (30-Second Adjustment)
The ADJ30 bit is for 30-second adjustment.
When 1 is written to the ADJ30 bit, the RSECCNT value of 30 seconds or less is rounded down to 00 second and the
value of 30 seconds or more is rounded up to 1 minute.
The 30-second adjustment is performed in synchronization with the count source. When 1 is written to this bit, the
ADJ30 bit is automatically set to 0 after the 30-second adjustment is completed. If 1 is written to the ADJ30 bit, check
that the bit is set to 0 before proceeding. When the 30-second adjustment is performed, the prescaler and R64CNT are
also reset. The ADJ30 bit is set to 0 by an RTC software reset.
RTCOE bit (RTCOUT Output Enable)
The RTCOE bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin.
Use the START bit to stop counting before changing the value of the RTCOE bit. Do not stop counting (write 0 to the
START bit) and change the value of the RTCOE bit at the same time.
When RTCOUT is to be output from an external pin, enable the RTCOE bit and set up the port control for the pin.
AADJE bit (Automatic Adjustment Enable)
The AADJE bit controls (enables or disables) automatic adjustment.
Set the plus–minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJE bit.
The AADJE bit is set to 0 by an RTC software reset.
AADJP bit (Automatic Adjustment Period Select)
The AADJP bit selects the automatic-adjustment period.
Set the plus–minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJP bit.
The AADJP bit is set to 0 by an RTC software reset.
HR24 bit (Hours Mode)
The HR24 bit specifies whether the RTC operates in 12- or 24-hour mode.
Use the START bit to stop counting before changing the value of the HR24 bit. Do not stop counting (write 0 to the
START bit) and change the value of the HR24 bit at the same time.
CNTMD bit (Count Mode Select)
The CNTMD bit specifies whether the RTC count mode operates in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings. This bit is updated
synchronously with the count source, and its value is fixed before the RTC software reset is complete.
For details on initial settings, see section 25.3.1, Outline of Initial Settings of Registers after Power On.
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25. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.RCR2 4004 4024h
b7
b6
CNTM
D
—
x
x
Value after reset:
b5
b4
b3
AADJP AADJE RTCOE
x
x
0
b2
—
b1
b0
RESET START
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
START
Start
0: The 32-bit binary counter, 64-Hz counter, and prescaler are
stopped
1: The 32-bit binary counter, 64-Hz counter, and prescaler are
in normal operation.
R/W
b1
RESET
RTC Software Reset
In writing
0: Writing is invalid
1: The prescaler and the target registers for RTC software
reset*1 are initialized.
In reading
0: In normal time operation, or an RTC software reset has
completed
1: During an RTC software reset.
R/W
b2
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b3
RTCOE
RTCOUT Output Enable
0: RTCOUT output disabled
1: RTCOUT output enabled.
R/W
b4
AADJE
Automatic Adjustment Enable *2
0: Automatic adjustment is disabled
1: Automatic adjustment is enabled.
R/W
b5
AADJP
Automatic Adjustment Period
Select *2
0: Add or subtract the RADJ.ADJ[5:0] bits from the prescaler
count value every 32 seconds
1: Add or subtract the RADJ.ADJ[5:0] bits from the prescaler
count value every 8 seconds
R/W
b6
—
Reserved
This bit is undefined. The write value should be 0.
R/W
b7
CNTMD
Count Mode Select
0: Calendar count mode
1: Binary count mode.
R/W
Note 1.
Note 2.
R64CNT, RSECAR/BCNT0AR, RMINAR/BCNT1AR, RHRAR/BCNT2AR, RWKAR/BCNT3AR, RDAYAR/BCNT0AER,
RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RTCCRy, RSECCPy/BCNT0CPy, RMINCPy/
BCNT1CPy, RHRCPy/BCNT2CPy, RDAYCPy/BCNT3CPy, RMONCPy, RCR2.ADJ30, RCR2.AADJE, RCR2.AADJP.
When LOCO is selected, the setting of this bit is disabled.
START bit (Start)
The START bit stops or restarts the prescaler or counter (clock) operation.
The START bit is updated in synchronization with the count source. When the START bit is modified, check that the bit
is updated before proceeding.
RESET bit (RTC Software Reset)
The RESET bit initializes the prescaler and registers to be reset by RTC software.
When 1 is written to the RESET bit, initialization starts in synchronization with the count source. When the initialization
is completed, the RESET bit is automatically set to 0. When 1 is written to the RESET bit, check that the bit is set to 0
before proceeding.
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25. Realtime Clock (RTC)
RTCOE bit (RTCOUT Output Enable)
The RTCOE bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin.
Use the START bit to stop counting before changing the value of the RTCOE bit. Do not stop counting (write 0 to the
START bit) and change the value of the RTCOE bit at the same time. When an RTCOUT signal is to be output from an
external pin, enable the port control in addition to setting this bit.
AADJE bit (Automatic Adjustment Enable)
The AADJE bit controls (enables or disables) automatic adjustment.
Set the plus–minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJE bit. The AADJE bit is set to 0 by an RTC software reset.
AADJP bit (Automatic Adjustment Period Select)
The AADJP bit selects the automatic-adjustment period.
Correction period can be selected from 32 second units or 8 second units in binary count mode.
Set the plus–minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJP bit. The AADJP bit is set to 0 by an RTC software reset.
CNTMD bit (Count Mode Select)
The CNTMD bit specifies whether the RTC count mode operates in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings. This bit is updated
synchronously with the count source, and its value is fixed before the RTC software reset is complete.
For details on initial settings, see section 25.3.1, Outline of Initial Settings of Registers after Power On.
25.2.19
RTC Control Register 4 (RCR4)
Address(es): RTC.RCR4 4004 4028h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
RCKSE
L
0
0
0
0
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RCKSEL
Count Source Select
0: Sub-clock oscillator is selected
1: LOCO is selected.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RCR4 register selects the count source and is used in both calendar count mode and binary count mode.
When the RCKSEL bit is set to 0, the time is counted with the sub-clock oscillator. When the bit is set to 1, the time is
counted with LOCO.
RCKSEL bit (Count Source Select)
The RCKSEL bit selects the count source from the sub-clock and LOCO.
The count source must be selected only once before specifying the initial settings of the RTC registers at power-on.
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25.2.20
25. Realtime Clock (RTC)
Frequency Register (RFRH/RFRL)
Address(es): RTC.RFRH 4004 402Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RFC16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RFC16
Reserved
Write 0 before writing to the RFRL register after a cold start
R/W
b15 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Address(es): RTC.RFRL 4004 402Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
RFC[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b15 to b0
RFC[15:0]
Frequency Comparison
Value
Write 00FFh to this register when using the LOCO
R/W
RFRL is a register for controlling the prescaler when LOCO is selected.
The RTC time counter operates on a 128-Hz clock signal as the base clock. Therefore, when LOCO is selected, LOCO is
divided by the prescaler to generate a 128-Hz clock signal. Set the frequency comparison value in the RFC[15:0] bits to
generate a 128-Hz clock from the LOCO frequency. Before writing to RFC[15:0] after a cold start, write 0000h to the
RFRH.
A value from 0007h through 01FFh can be specified as the frequency comparison value. If a value outside of this range
is specified, the RTC does not operate correctly. Before writing to this register, be sure to stop the count operation
through the setting of the START bit in RCR2. The operating frequency of the peripheral module clock and the LOCO
should be such that the peripheral module clock is greater than or equal to the LOCO.
Calculation method of frequency comparison value:
RFC[15:0] = (LOCO clock frequency) / 128 - 1
When the LOCO frequency is 32.768 kHz, the RFRL register should be set to 00FFh.
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25.2.21
25. Realtime Clock (RTC)
Time Error Adjustment Register (RADJ)
Address(es): RTC.RADJ 4004 402Eh
b7
b6
b5
b4
PMADJ[1:0]
x
Value after reset:
x
b3
b2
b1
b0
x
x
ADJ[5:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b5 to b0
ADJ[5:0]
Adjustment Value
These bits specify the adjustment value from the prescaler
R/W
b7, b6
PMADJ[1:0]
Plus–Minus
b7 b6
R/W
0
0
1
1
0: Adjustment is not performed
1: Adjustment is performed by the addition to the prescaler
0: Adjustment is performed by the subtraction from the prescaler
1: Setting prohibited.
Adjustment is performed by the addition to or subtraction from the prescaler. If the automatic adjustment enable
(RCR2.AADJE) bit is 0, adjustment is performed when writing to the RADJ. If the RCR2.AADJE bit is 1, adjustment is
performed in the interval specified by the automatic adjustment period select (RCR2.AADJP) bit.
The current adjustment by software (disabling automatic adjustment) might be invalid if the following adjustment value
is specified within 320 cycles of the count source after the register setting. To perform adjustment consecutively, wait for
320 cycles or more of the count source after the register setting, then specify the next adjustment value.
RADJ is updated in synchronization with the count source. When RADJ is modified, check that all the bits are updated
before continuing with further processing. This register is set to 00h by an RTC software reset. The setting of this register
is enabled only when the sub-clock oscillator is selected. When LOCO is selected, adjustment is not performed.
ADJ[5:0] bits (Adjustment Value)
The ADJ[5:0] bits specify the adjustment value (the number of sub-clock cycles) from the prescaler.
PMADJ[1:0] bits (Plus–Minus)
The PMADJ[1:0] bits select whether the clock is set ahead or back depending on the error-adjustment value set in the
ADJ[5:0] bits.
25.2.22
Time Capture Control Register y (RTCCRy) (y = 0 to 2)
Address(es): RTC.RTCCR0 4004 4040h, RTC.RTCCR1 4004 4042h, RTC.RTCCR2 4004 4044h
b7
b6
b5
b4
b3
b2
TCEN
—
TCNF[1:0]
—
TCST
x
x
x
x
x
Value after reset:
x
b1
b0
TCCT[1:0]
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b1, b0
TCCT[1:0]
Time Capture Control
b1 b0
R/W
b2
TCST
Time Capture Status
0: No event is detected
1: An event is detected.*1
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
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0
0
1
1
0: No event is detected
1: Rising edge is detected
0: Falling edge is detected
1: Both edges are detected.
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25. Realtime Clock (RTC)
Bit
Symbol
Bit name
Description
R/W
b5, b4
TCNF[1:0]
Time Capture Noise
Filter Control
b5 b4
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
TCEN
Time Capture Event
Input Pin Enable
0: The RTCICn (n = 0 to 2) pin is disabled as the time capture event
input
1: The RTCICn (n = 0 to 2) pin is enabled as the time capture event
input.
R/W
Note 1.
0
0
1
1
0: Noise filter is off
1: Setting prohibited
0: Noise filter is on (count source)
1: Noise filter is on (count source by divided by 32).
Indicates that an event has been detected. Writing 1 to this bit has no effect. Writing 0 sets this bit to 0.
The RTCCRy register is used both in calendar count mode and in binary count mode. RTCCR0, RTCCR1, and RTCCR2
control the RTCIC0, RTCIC1, and RTCIC2 pins, respectively.
RTCCRy is updated in synchronization with the count source. When RTCCRy is modified, check that all the bits except
for the TCST bit are updated before continuing with further processing. This register is set to 00h by an RTC software
reset. When RTCICn is used as the time capture pin, VBTICTLR.VCHnIEN (n = 0 to 2) must be set to 1. For more
information, see section 12, Battery Backup Function.
TCCT[1:0] bits (Time Capture Control)
The TCCT[1:0] bits control the edge detection of the time capture event input pins, RTCIC0, RTCIC1, and RTCIC2. The
detection edge is selectable. The TCCT[1:0] bits must be set while the VBTICTLR.VCHnIEN bit is 1.
TCST bit (Time Capture Status)
The TCST bit indicates that an event of the time capture event input pins, RTCIC0, RTCIC1, and RTCIC2, has been
detected. When the TCST bit is 0, no event is detected. When the TCST bit is 1, this bit indicates that an event of the
associated pin has been detected and the capture register is valid. When multiple events are detected, the capture time for
the first event is retained.
If an event is detected while the count operation stops, that is, the RCR2.START bit is 0, the captured value is not
guaranteed. In this case, set the TCST bit to 0 to delete the captured value. Writing 0 sets the TCST bit to 0. Writing any
other value other than 0 has no effect.
Set the TCST bit while the TCCT[1:0] bits are 00b (no event is detected). The TCST bit is set to 0 in synchronization
with the count source. When the TCST bit is set to 0, check that the bit is updated before continuing with further
processing.
TCNF[1:0] bits (Time Capture Noise Filter Control)
The TCNF[1:0] bits control the noise filter of the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2).
When the noise filter is on, the count source divided by 1 or divided by 32 is selectable. In this case, when the input level
on the time capture event input pin matches three consecutive times at the set sampling period, the input level is
determined.
Set the TCNF[1:0] bits while the TCCT[1:0] bits are 00b (no event is detected). When the noise filter is used, set the
TCNF[1:0] bits, wait for 3 cycles of the specified sampling period, then set the TCCT[1:0] bits. Set the TCNF[1:0] bits
when the VBTICTLR.VCHnIEN bit is 1.
TCEN bit (Time Capture Event Input Pin Enable)
The TCEN bit enables or disables the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2). When the
functions of the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2) are multiplexed, set VBTICTLR first. If
the TCEN bit is set to 0, set also the TCCT[1:0] bits to 00b.
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25.2.23
(1)
25. Realtime Clock (RTC)
Second Capture Register y (RSECCPy) (y = 0 to 2)/BCNT0 Capture Register y
(BCNT0CPy) (y = 0 to 2)
In calendar count mode
Address(es): RTC.RSECCP0 4004 4052h, RTC.RSECCP1 4004 4062h, RTC.RSECCP2 4004 4072h
b7
b6
—
b4
b3
SEC10[2:0]
x
Value after reset:
b5
x
x
b2
b1
b0
SEC1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
SEC1[3:0]
1-Second Capture
Capture value for the ones place of seconds
R
b6 to b4
SEC10[2:0]
10-Second Capture
Capture value for the tens place of seconds
R
b7
—
Reserved
This bit is read as 0 after an RTC software reset
R
RSECCPy is a read-only register that captures the RSECCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RSECCP0, RSECCP1,
and RSECCP2 registers, respectively. This register is set to 00h by an RTC software reset. Before reading from this
register, be sure to stop the time capture event detection using the RTCCRy.TCCT[1:0] bits.
(2)
In binary count mode
Address(es): RTC.BCNT0CP0 4004 4052h, RTC.BCNT0CP1 4004 4062h, RTC.BCNT0CP2 4004 4072h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTCPy[7:0]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT0CPy is a read-only register that captures the BCNT0 value when a time capture event is detected. The event
detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the BCNT0CP0, BCNT0CP1, and
BCNT0CP2 registers, respectively. This register is set to 00h by an RTC software reset. Before reading from this register,
be sure to stop the time capture event detection using the RTCCRy.TCCT[1:0] bits.
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25.2.24
(1)
25. Realtime Clock (RTC)
Minute Capture Register y (RMINCPy) (y = 0 to 2)/BCNT1 Capture Register y
(BCNT1CPy) (y = 0 to 2)
In calendar count mode
Address(es): RTC.RMINCP0 4004 4054h, RTC.RMINCP1 4004 4064h, RTC.RMINCP2 4004 4074h
b7
b6
—
x
Value after reset:
b5
b4
b3
MIN10[2:0]
x
x
b2
b1
b0
MIN1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MIN1[3:0]
b6 to b4
MIN10[2:0]
1-Minute Capture
Capture value for the ones place of minutes
R
10-Minute Capture
Capture value for the tens place of minutes
R
b7
—
Reserved
This bit is read as 0 after an RTC software reset
R
RMINCPy is a read-only register that captures the RMINCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RMINCP0, RMINCP1,
and RMINCP2 registers, respectively.
This register is set to 00h by an RTC software reset. Before reading from this register, be sure to stop the time capture
event detection using the RTCCRy.TCCT[1:0] bits.
(2)
In binary count mode
Address(es): RTC.BCNT1CP0 4004 4054h, RTC.BCNT1CP1 4004 4064h, RTC.BCNT1CP2 4004 4074h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTCPy[15:8]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT1CPy is a read-only register that captures the BCNT1 value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the BCNT1CP0,
BCNT1CP1, and BCNT1CP2 registers, respectively.
This register is set to 00h by an RTC software reset. Before reading from this register, be sure to stop the time capture
event detection using the RTCCRy.TCCT[1:0] bits.
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25.2.25
(1)
25. Realtime Clock (RTC)
Hour Capture Register y (RHRCPy) (y = 0 to 2)/BCNT2 Capture Register y
(BCNT2CPy) (y = 0 to 2)
In calendar count mode
Address(es): RTC.RHRCP0 4004 4056h, RTC.RHRCP1 4004 4066h, RTC.RHRCP2 4004 4076h
Value after reset:
b7
b6
b5
b4
—
PM
HR10[1:0]
x
x
x
x
b3
b2
b1
b0
HR1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
HR1[3:0]
1-Hour Capture
Capture value for the ones place of hours
R
b5, b4
HR10[1:0]
10-Hour Capture
Capture value for the tens place of hours
R
b6
PM
PM
0: AM
1: PM.
R
b7
—
Reserved
This bit is read as 0 after an RTC software reset
R
RHRCPy is a read-only register that captures the RHRCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RHRCP0, RHRCP1, and
RHRCP2 registers, respectively. The PM bit is only enabled when the RCR2.HR24 bit is 0 (in 12-hour mode).
This register is set to 00h by an RTC software reset. Before reading from this register, be sure to stop the time capture
event detection using the RTCCRy.TCCT[1:0] bits.
(2)
In binary count mode
Address(es): RTC.BCNT2CP0 4004 4056h, RTC.BCNT2CP1 4004 4066h, RTC.BCNT2CP2 4004 4076h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTCPy[23:16]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT2CPy is a read-only register that captures the BCNT2 value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the BCNT2CP0,
BCNT2CP1, and BCNT2CP2 registers, respectively.
This register is set to 00h by an RTC software reset. Before reading from this register, be sure to stop the time capture
event detection using the RTCCRy.TCCT[1:0] bits.
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25.2.26
(1)
25. Realtime Clock (RTC)
Date Capture Register y (RDAYCPy) (y = 0 to 2)/BCNT3 Capture Register y
(BCNT3CPy) (y = 0 to 2)
In calendar count mode
Address(es): RTC.RDAYCP0 4004 405Ah, RTC.RDAYCP1 4004 406Ah, RTC.RDAYCP2 4004 407Ah
Value after reset:
b7
b6
—
—
x
x
b5
b4
b3
DATE10[1:0]
x
x
b2
b1
b0
DATE1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DATE1[3:0]
b5, b4
DATE10[1:0]
1-Day Capture
Capture value for the ones place of days
R
10-Day Capture
Capture value for the tens place of days
R
b7, b6
—
Reserved
These bits are read as 0 after an RTC software reset
R
RDAYCPy is a read-only register that captures the RDAYCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RDAYCP0, RDAYCP1,
and RDAYCP2 registers, respectively.
This register is set to 00h by an RTC software reset. Before reading from this register, be sure to stop the time capture
event detection using the RTCCRy.TCCT[1:0] bits.
(2)
In binary count mode
Address(es): RTC.BCNT3CP0 4004 405Ah, RTC.BCNT3CP1 4004 406Ah, RTC.BCNT3CP2 4004 407Ah
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTCPy[31:24]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT3CPy is a read-only register that captures the BCNT3 value when a time capture event is detected.
The event detection times detected by the RTCTC0, RTCTC1, and RTCTC2 pins are stored in the BCNT3CP0,
BCNT3CP1, and BCNT3CP2 registers, respectively.
This register is set to 00h by an RTC software reset. Before reading from this register, be sure to stop the time capture
event detection using the RTCCRy.TCCT[1:0] bits.
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25.2.27
(1)
25. Realtime Clock (RTC)
Month Capture Register y (RMONCPy) (y = 0 to 2)
In calendar count mode
Address(es): RTC.RMONCP0 4004 405Ch, RTC.RMONCP1 4004 406Ch, RTC.RMONCP2 4004 407Ch
Value after reset:
b7
b6
b5
b4
—
—
—
MON10
x
x
x
x
b3
b2
b1
b0
MON1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MON1[3:0]
b4
MON10
1-Month Capture
Capture value for the ones place of months
R
10-Month Capture
Capture value for the tens place of months
R
b7 to b5
—
Reserved
These bits are read as 0
R
RMONCPy is a read-only register that captures the RMONCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RMONCP0,
RMONCP1, and RMONCP2 registers, respectively.
This register is set to 00h by an RTC software reset. Before reading from this register, be sure to stop the time capture
event detection using the RTCCRy.TCCT[1:0] bits.
25.3
Operation
25.3.1
Outline of Initial Settings of Registers after Power On
After the power is turned on, perform the initial settings for the clock setting, count mode setting, time error adjustment,
time setting, alarm, interrupt, and time capture control register.
Power on
Clock and count mode settings
Clock supply setting and count mode setting
Set the time
Time setting in the clock counter and initial
setting of the time error adjustment register
Set the alarm
Set the interrupt
Set the time capture control register
Figure 25.2
Initial setting of the alarm register
Initial setting of the interrupt control register
Initial setting of the time capture control register
Outline of initial settings after a power on
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25.3.2
25. Realtime Clock (RTC)
Clock and Count Mode Setting Procedure
Figure 25.3 shows how to set the clock and the count mode.
Select the count source
RCR4.RCKSEL bit setting
Supply 6 clocks of the count source
Supply 6 clocks of the clock selected by the
RCR4.RCKSEL bit
Set the START bit to 0
No
START = 0?
Wait for the RCR2.START bit to become 0
Yes
No (LOCO)
RCKSEL = 0?
Set frequency register
Yes (Sub-clock)
Select count mode
Execute RTC software reset
No
RESET = 0?
RCR2.CNTMD bit setting*1
Write 1 to the RCR2.RESET bit
Wait for the RCR2.RESET bit to become 0
Yes
Note 1.
Figure 25.3
This step is not required if the count mode is set concurrently by setting the START bit to 0.
A value associated with the count mode setting must be written to the RCR2.CNTMD bit.
Clock and count mode setting procedure
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25.3.3
25. Realtime Clock (RTC)
Setting the Time
Figure 25.4 shows how to set the time.
Set the START bit to 0
No
Write 0 to the RCR2.START bit
Wait for the RCR2.START bit to become 0
START = 0?
Yes
Write 1 to the RCR2.RESET bit*1
Execute an RTC software reset
No
Wait for the RCR2.RESET bit to become 0
RESET = 0?
Yes
Set the year, month, day of the week,
date, hour, minute, and second/binary
counters 3 to 0
Settings in arbitrary order is possible
No (LOCO)
RCKSEL = 0?
Yes (Sub-clock)
Set clock error
adjustment values
Set clock error adjustment values
Set the START bit to 1
No
Write 1 to the RCR2.START bit
Wait for the RCR2.START bit to become 1
START = 1?
Yes
Note 1.
Figure 25.4
25.3.4
This step is not required for the time-setting procedure because an RTC software reset is executed
in the clock setting procedure of the initial settings for the power supply.
Setting the time
30-Second Adjustment
Figure 25.5 shows how to execute a 30-second adjustment.
Clock is in operation
Set the RCR2.ADJ30 bit to 1
No
ADJ30 = 0?
Execute 30-second adjustment while the clock is in operation
(the RCR2.START bit is 1)
Write 1 to the RCR2.ADJ30 bit
Wait for the RCR2.ADJ30 bit to become 0
Yes
Figure 25.5
30-second adjustment
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25.3.5
25. Realtime Clock (RTC)
Reading 64-Hz Counter and Time
Figure 25.6 shows how to read a 64-Hz counter and time.
(a) To read the time without using interrupt
Disable the NVIC carry interrupt request
Write 1 to the Interrupt Clear-Enable Register
corresponding to the RTC_CUP interrupt
Enable the RTC carry interrupt request
Write 1 to the RCR1.CIE bit
Clear the interrupt flag
Write 0 to the IELSRn.IR bit and write 1 to
the Interrupt Clear-Pending Register
corresponding to the RTC_CUP interrupt
Read the counter
Yes
Pending status = 1?
Read the counter again when the Interrupt
Set-Pending Register corresponding to the
RTC_CUP interrupt is 1
No
(b) To read the time using interrupts
Clear the interrupt flag
Enable the NVIC carry interrupt request
Enable the RTC carry interrupt request
Clear the interrupt flag
Write 0 to the IELSRn.IR bit and write
1 to the Interrupt Clear-Pending
Register corresponding to the
RTC_CUP interrupt
Write 1 to the Interrupt Set-Enable Register
corresponding to the RTC_CUP interrupt
Write 1 to the RCR1.CIE bit
Write 0 to the IELSRn.IR bit and write 1
to the Interrupt Clear-Pending Register
corresponding to the RTC_CUP interrupt
Read the counter
Yes
Interrupt?
No
Disable the RTC carry interrupt
Note 1.
Figure 25.6
Write 0 to the RCR1.CIE bit*1
Disable interrupts if required.
Reading time
If a carry occurs while the 64-Hz counter and time are read, the correct time is not obtained, therefore they must be read
again. The procedure for reading the time without using interrupts is shown in (a) in Figure 25.6, and the procedure using
carry interrupts is shown in (b). To keep the program simple, method (a) should be used in most cases.
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25.3.6
25. Realtime Clock (RTC)
Alarm Function
Figure 25.7 shows how to use the alarm function.
Disable the NVIC alarm interrupt request
Set alarm time
Enable the RTC alarm interrupt request
Wait for the completion of the alarm time
setting
Clear the interrupt flag
Enable the NVIC alarm interrupt request
Monitor alarm time
(wait for interrupt or check alarm flag)
Figure 25.7
Write 1 to the Interrupt Clear-Enable Register
corresponding to the RTC_ALM interrupt
Set alarm enable at the same time as or after the
alarm time setting
Write 1 to the RCR1.AIE bit
Wait for 200 µs or more
Write 0 to the IELSRn.IR bit and write 1 to the Interrupt
Clear-Pending Register corresponding to the RTC_ALM
interrupt, since the flag may have been set while the alarm
time was being set
Write 1 to the Interrupt Set-Enable Register
corresponding to the RTC_ALM interrupt
Wait for alarm interrupt or the Interrupt Active Bit
Register corresponding to the RTC_ALM interrupt to
become 1
Using the alarm function
In calendar count mode, an alarm can be generated by any one of year, month, date, day-of-week, hour, minute or second,
or any combination of those. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm
time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting.
In binary count mode, an alarm can be generated in any bit combination of 32 bits. Write 1 to the ENB bit of the alarm
enable register associated with the target bit of the alarm, and set the alarm time in the alarm register. For bits that are not
the target of the alarm, write 0 to the ENB bit of the alarm enable register.
When the counter and the alarm time match, the IELSRn.IR bit and Interrupt Set-Pending/Clear-Pending Register
associated with the RTC_ALM interrupt is set to 1. Alarm detection can be confirmed by reading the Interrupt SetPending Register associated with the RTC_ALM interrupt, but an interrupt should be used in most cases. If 1 is set in the
Interrupt Set-Enable Register associated with the RTC_ALM interrupt, an alarm interrupt is generated in the event of the
alarm, enabling the alarm to be detected.
Writing 0 sets the IELSRn.IR bit associated with the RTC_ALM interrupt to 0. If interrupt is enabled, the Interrupt SetPending/Clear-Pending Register and Interrupt Active Bit Register associated with the RTC_ALM interrupt is cleared
automatically after exiting the interrupt handler. Otherwise, write 1 to the Interrupt Clear-Pending Register associated
with the RTC_ALM interrupt to clear it.
When the counter and the alarm time match in a low power state, the MCU returns from the low power state.
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25.3.7
25. Realtime Clock (RTC)
Procedure for Disabling Alarm Interrupt
Figure 25.8 shows the procedure for disabling the enabled alarm interrupt request.
Enable the alarm interrupt
The RCR1.AIE bit register is set to 1
Disable the alarm interrupt request of
the NVIC
Write 0 to the Interrupt Clear-Enable Register
associated with the RTC_ALM interrupt
Disable the alarm interrupt request of
the RTC
Write 0 to the RCR1.AIE bit
No
AIE bit = 0?
Wait for the RCR1.AIE bit to be cleared to 0
Yes
Clear the interrupt flag
Figure 25.8
25.3.8
Write 0 to the IELSRn.IR bit and write 1 to the
Interrupt Clear-Pending Register associated with the
RTC_ALM interrupt because the flag might have
been set before the RCR1.AIE bit becomes 0
Procedure for disabling alarm interrupt request
Time Error Adjustment Function
The time error adjustment function is used to correct errors, running fast or slow, in the time due to variation in the
precision of oscillation of the sub-clock. Because 32,768 cycles of the sub-clock constitute 1 second of operation when
the sub-clock is selected, the clock runs fast if the sub-clock frequency is high and slow if the sub-clock frequency is low.
There time error adjustment functions include:
Automatic adjustment
Adjustment by software.
Use the RCR2.AADJE bit to select automatic adjustment or adjustment by software.
25.3.8.1
Automatic adjustment
Enable automatic adjustment by setting the RCR2.AADJE bit to 1. Automatic adjustment is the addition or subtraction of
the value counted by the prescaler to or from the value in the RADJ register every time the adjustment period selected by
the RCR2.AADJP bit elapses.
(1)
Example 1: Sub-clock running at 32.769 kHz
(a)
Adjustment procedure
When the sub-clock oscillator is running at 32.769 kHz, 1 second elapses every 32,769 clock cycles. The RTC is meant
to run at 32,768 clock cycles, so the clock runs fast by 1 clock cycle every second. The time on the clock is fast by 60
clock cycles per minute, so adjustment can take the form of setting the clock back by 60 cycles every minute.
Register settings (when RCR2.CNTMD = 0):
RCR2.AADJP = 0 (adjustment every minute)
RADJ.PMADJ[1:0] = 10b (adjustment is performed by the subtraction from the prescaler)
RADJ.ADJ[5:0] = 60 (3Ch).
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(2)
Example 2: Sub-clock running at 32.766 kHz
(a)
Adjustment procedure
25. Realtime Clock (RTC)
When the sub-clock is running at 32.766 kHz, 1 second elapses every 32766 clock cycles. The RTC is meant to run at
32768 clock cycles, so the clock runs slow by 2 clock cycles every second. The time on the clock is slow by 20 clock
cycles every 10 seconds, so adjustment can take the form of setting the clock forward by 20 cycles every 10 seconds.
Register settings (when RCR2.CNTMD = 0):
RCR2.AADJP = 1 (adjustment every 10 seconds)
RADJ.PMADJ[1:0] = 01b (adjustment is performed by the addition to the prescaler)
RADJ.ADJ[5:0] = 20 (14h).
(3)
Example 3: Sub-clock running at 32.764 kHz
(a)
Adjustment procedure
At 32.764 kHz, 1 second elapses on 32,764 clock cycles. Because the RTC operates for 32,768 clock cycles as 1 second,
the clock is delayed for 4 clock cycles per second. In 8 seconds, the delay is 32 clock cycles, therefore correction can be
made by advancing the clock for 32 clock cycles every 8 seconds.
Register settings when the RCR2.CNTMD bit is 1:
RCR2.AADJP = 1 (adjustment every 8 seconds)
RADJ.PMADJ[1:0] = 01b (adjustment is performed by the addition to the prescaler)
RADJ.ADJ[5:0] = 32 (20h).
25.3.8.2
Adjustment by software
Enable adjustment by software by setting the RCR2.AADJE bit to 0. Adjustment by software is the addition or
subtraction of the value counted by the prescaler to or from the value in the RADJ register on execution of a write
instruction to the RADJ register.
(1)
Example 1: Sub-clock running at 32.769 kHz
(a)
Adjustment procedure
When the sub-clock is running at 32.769 kHz, 1 second elapses every 32,769 clock cycles. The RTC is meant to run at
32,768 clock cycles, so the clock runs fast by 1 clock cycle every second. The time on the clock is fast by 1 clock cycle
per second, so adjustment can take the form of setting the clock back by 1 cycle every second.
(b)
Register settings
RADJ.PMADJ[1:0] = 10b (adjustment is performed by subtraction from the prescaler)
RADJ.ADJ[5:0] = 1 (01h)
This is written to the RADJ register once per 1-second interrupt.
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25.3.8.3
25. Realtime Clock (RTC)
Procedure for changing the mode of adjustment
When changing the mode of adjustment, change the value of the AADJE bit in RCR2 after setting the
RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
To change adjustment by software to automatic adjustment:
1.
Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
2.
Set the RCR2.AADJE bit to 1 (automatic adjustment is enabled).
3.
Use the RCR2.AADJP bit to select the period of adjustment.
4.
In RADJ, set the PMADJ[1:0] bits for addition or subtraction and the ADJ[5:0] bits to the value for use in time
error adjustment.
To change automatic adjustment to adjustment by software:
1. Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
2. Set the RCR2.AADJE bit to 0 (adjustment by software is enabled).
3. Proceed with the adjustment by setting the RADJ.PMADJ[1:0] bits for addition or subtraction and the
RADJ.ADJ[5:0] bits to the value for use in time error adjustment at the target time. After that, the time is adjusted
every time a value is written to the RADJ register.
25.3.8.4
Procedure for stopping adjustment
Stop the adjustment by setting the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
25.3.8.5
Capturing the time
The RTC is capable of storing the month, date, hour, minute and second/binary counters 3 to 0 by detecting an edge of a
signal on a time capture event input pin.
A noise filter can also be used on a time capture event input pin. If the noise filter is enabled, the TCST bit is set to 1
when the input level on the pin matches three times.
The noise filter can be switched on or off for each of the time capture event input pins. VBTICTLR.VCHnIEN (n = 0 to
2) should be set to 1 to enable the RTCICn input. Operation when the noise filter is off is shown in Figure 25.9 and
operation when the noise filter is on is shown in Figure 25.10.
Count source
RTCICn (n = 0 to 2)
Internal event-input signal
Time counters
Capture register
AAAA
0
BBBB
AAAA
TCST
Detection of the
rising edge
Figure 25.9
No capturing when
TCST = 1
Timing of a time capture operation with the filter off
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25. Realtime Clock (RTC)
Count source
RTCICn (n = 0 to 2)
Internal event-input signal
(1)
(2)
(1)
(2)
(1)
Since the level has only matched
twice, it is not conveyed to the
internal circuits.
(2)
(3)
Since the level has matched three
times, it is conveyed to the internal
circuits.
Internal event-detection signal
Time counters
Capture register
AAAA
BBBB
0
BBBB
TCST
Detection of the rising edge
Figure 25.10
25.4
Timing of a time capture operation with the filter on
Interrupt Sources
The RTC has three interrupt sources and are listed in Table 25.3.
Table 25.3
Name
RTC Interrupt sources
Interrupt sources
RTC_ALM
Alarm interrupt
RTC_PRD
Periodic interrupt
RTC_CUP
Carry interrupt
(1)
Alarm interrupt (RTC_ALM)
This interrupt is generated based on the result of comparison between the alarm registers and realtime clock counters. For
details, see section 25.3.6, Alarm Function.
Because there is a possibility that the interrupt flag might be set to 1 when the settings of the alarm registers match the
clock counters, wait for the alarm time settings to be confirmed and clear the IELSRn.IR bit and the interrupt SetPending Register associated with the RTC_ALM interrupt to 0 again after modifying values of the alarm registers. After
the interrupt flag for the alarm interrupt is set to 1 and the state is returned to mismatching of the alarm registers and
clock counters, the flag does not set again until there is a further match or the values of the alarm registers are modified
again.
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25. Realtime Clock (RTC)
Sequence for setting the alarm
Alarm-register settings
in progress
Wait until the alarm
time setting is
confirmed
Alarm registers
Clock counters
Interrupt flag
(the IELSRn.IR bit and the
Interrupt Set-Pending
Register corresponding to
the RTC_ALM interrupt *1)
Note 1.
Flag clearing by
software
Alarm interrupt
accepted
See section 14, Interrupt Controller Unit (ICU) for details on the associated interrupt vector number.
Figure 25.11
(2)
Match while settings are being made
Timing diagram for the alarm interrupt (RTC_ALM)
Periodic interrupt (RTC_PRD)
This interrupt is generated at intervals of 2 seconds, 1 second, 1/2 second, 1/4 second, 1/8 second, 1/16 second, 1/32
second, 1/64 second, 1/128 second, or 1/256 second. The interrupt interval can be selected through the RCR1.PES[3:0]
bits.
(3)
Carry interrupt (RTC_CUP)
This interrupt is generated when a carry to the second counter/binary counter 0 occurred or a carry to the R64CNT
counter occurred during read access to the 64-Hz counter.
R64CNT
signal
64 Hz
Interrupt generated by the simultaneous
occurrence of the selected edge of the
64-Hz signal and register reading
1 Hz
An interrupt is generated by a
carry to the second counter/
binary counter 0
Interrupt
Detail
Rising edges of the R64CNT signals
are detected in the same way
64-Hz signal in R64CNT
Detection of the selected edge of
the 64-Hz signal
Register reading by the CPU
R64CNT
Interrupt generated by the simultaneous occurrence of
the edge of the 64-Hz signal and reading of R64CNT
Interrupt flag
(the IELSRn.IR bit and Interrupt
Set-Pending Register
corresponding to the RTC_CUP
interrupt)
Figure 25.12
25.5
Carry interrupt (RTC_CUP) timing diagram
Event Link Output
The RTC generates periodic event output (RTC_PRD) event signals for the Event Link Controller (ELC), and these can
be used to initiate operations by other modules selected in advance.
The periodic event signal is output at the interval selected from 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2, 1, and 2
seconds by setting the RCR1.PES[3:0] bits. The event generation period immediately after the event generation is
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25. Realtime Clock (RTC)
selected is not guaranteed.
Note:
25.5.1
If event linking from the RTC is used, only set the ELC after setting the RTC, for example initialization and time
settings. Setting the RTC after the ELC can lead to output of unexpected event signals.
Interrupt Handling and Event Linking
The RTC has a bit to enable or disable periodic interrupts. An interrupt request signal is output to the CPU when an
interrupt source is generated while the corresponding enable bit is enabled.
In contrast, an event link output signal is sent to other modules as an event signal through the ELC when an interrupt
source is generated, regardless of the setting of the associated interrupt enable bit.
Note:
Although alarm and periodic interrupts can still be output during Software Standby mode, the periodic event
signals for the ELC are not output.
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25.6
25. Realtime Clock (RTC)
Usage Notes
25.6.1
Register Writing during Counting
The following registers must not be written to during counting, that is, while the RCR2.START bit = 1.
RSECCNT/BCNT0
RMINCNT/BCNT1
RHRCNT/BCNT2
RDAYCNT
RWKCNT/BCNT3
RMONCNT
RYRCNT
RCR1.RTCOS
RCR2.RTCOE
RCR2.HR24
RFRL.
The counter must be stopped before writing to any of the these registers.
25.6.2
Use of Periodic Interrupts
The procedure for using periodic interrupts is shown in Figure 25.13.
The generation and period of the periodic interrupt can be changed by setting the RCR1.PES[3:0] bits. However, because
the prescaler R64CNT and RSECCNT/BCNT0 are used to generate interrupts, the interrupt period is not guaranteed
immediately after setting the RCR1.PES[3:0] bits. In addition, any of the following can affect the interrupt period:
Stopping/restarting or resetting counter operation
Reset by RTC software
30-second adjustment by changing the RCR2 value.
When the time error adjustment function is used, the interrupt generation period after adjustment is added or subtracted
based on the adjustment value.
Set the period and enable interrupt requests
Set the RCR1.PES[3:0] bits and
write 1 to the RCR1.PIE bit
The period is not guaranteed.
The first interrupt is generated
Confirm generation of the first periodic interrupt*1
The set period elapses
Interrupts are generated with the specified period.
An interrupt is generated
Note 1.
Figure 25.13
Confirm generation of a periodic interrupt
When a interrupt generation period is changed while the periodic interrupt is used, an interrupt may be
generated at the completion of the setting. If the interrupt is generated immediately after the setting, the period is
not guaranteed for two interrupts including the current interrupt.
Using the periodic interrupt function
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25.6.3
25. Realtime Clock (RTC)
RTCOUT (1-Hz/64-Hz) Clock Output
Stopping/restarting or resetting counter operation, reset by RTC software, and the 30-second adjustment by changing the
RCR2 value affects the period of RTCOUT (1-Hz/64-Hz) output. When the time error adjustment function is used, the
period of RTCOUT (1-Hz/64-Hz) output after adjustment is added or subtracted according to the adjustment value.
25.6.4
Transitions to Low Power Modes after Setting Registers
A transition to a low power state (Software Standby mode or battery backup) during writing to an RTC register might
corrupt the value of the register. After setting the register, confirm that the setting is in place before initiating a transition
to a low power state.
25.6.5
Notes on Writing to and Reading from Registers
When reading a counter register such as the second counter after having written to the counter register, follow the
procedure in section 25.3.5, Reading 64-Hz Counter and Time
The value written to the count registers, alarm registers, year alarm enable register, bits RCR2.AADJE, AADJP, and
HR24, RCR4 register, or frequency register is reflected when four read operations are performed after writing
The values written to the RCR1.CIE, RCR1.RTCOS, and RCR2.RTCOE bits can be read immediately after writing
To read the value from the timer counter after return from a reset, period in Software Standby mode, or the battery
backup state, wait for1/128 second while the clock is operating (RCR2.START bit = 1)
After a reset is generated, write to the RTC register after 6 cycles of the count source clock elapse.
25.6.6
Changing the Count Mode
When changing the count mode (calendar/binary), set the RCR2.START bit to 0, stop the counting operation, then restart
it from the initial setting. For details on the initial setting, see section 25.3.1, Outline of Initial Settings of Registers after
Power On.
25.6.7
Initialization Procedure When the Realtime Clock is not to be Used
Registers in the RTC are not initialized by a reset. Depending on the initial state, the generation of an unintentional
interrupt request or operation of the counter might lead to increased power consumption.
For applications that do not require a realtime clock, initialize the registers by following the initialization procedure
shown in Figure 25.14.
Alternatively, when the sub-clock is not used as the system clock or realtime clock, the counter can be stopped by writing
0 (sub-clock oscillator is selected) to the RCR4.RCKSEL bit and stopping the sub-clock oscillator. To stop the sub-clock
oscillator, write 1 to the SOSCCR.SOSTP bit. For details on the setting of the SOSCCR.SOSTP bit, see section 9, Clock
Generation Circuit.
Select the count source
Supply 6 clocks of the count source
RCR4.RCKSEL bit setting
Supply 6 clocks of the clock selected by the
RCR4.RCKSEL bit
Clear the START bit to 0
No
START = 0
Wait for the RCR2.START bit to become 0
Yes
Select count mode
Execute RTC software reset
No
RESET = 0
RCR2.CNTMD bit setting*1
Write 1 to the RCR2.RESET bit
Wait for the RCR2.RESET bit to become 0
Yes
Disable interrupt requests
Note 1.
Figure 25.14
Write 0 to the RCR1.AIE, CIE, and PIE bits
This step is not required if the count mode has been set concurrently with setting the START bit to 0.
Initialization procedure
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26. Watchdog Timer (WDT)
26.
Watchdog Timer (WDT)
26.1
Overview
The Watchdog Timer (WDT) is a 14-bit down-counter and can be used to reset the MCU when the counter underflows
because the system has run out of control and is unable to refresh the WDT. In addition, the WDT can be used to generate
a non-maskable interrupt or an underflow interrupt. The refresh-permitted period can be set to refresh the counter and to
detect when the system runs out of control. Table 26.1 lists the WDT specifications and Figure 26.1 shows a block
diagram.
Table 26.1
WDT specifications
Item
Specifications
Count source
Peripheral clock (PCLKB)
Clock division ratio
Divide by 4, 64, 128, 512, 2,048, or 8,192
Counter operation
Counting down using a 14-bit down-counter
Conditions for starting the counter Auto-start mode: Counting automatically starts after a reset or after an underflow or refresh error
occurs
Register start mode: Counting is started with a refresh by writing to the WDTRR register.
Conditions for stopping the
counter
Reset (the down-counter and other registers return to their initial values)
A counter underflows or a refresh error is generated.
Window function
Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods)
Watchdog timer
Reset sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Non-maskable interrupt/interrupt
sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Reading the counter value
The down-counter value can be read by the WDTSR register
Event link function (output)
Down-counter underflow event output
Refresh error event output.
Output signal (internal signal)
Reset output
Interrupt request output
Sleep mode count stop control output.
Interrupt request (WDT_NMIUNDF)
WDT output
Clock frequency
divider
Interrupt Control Unit (ICU)
Reset control circuit
PCLKB/4
PCLKB
PCLKB/64
PCLKB/128
WDT control circuit
PCLKB/512
14-bit down-counter
WDTRR
WDTCR
WDTSR
WDTRCR
Option Function Select Register 0
(OFS0)
WDTCSTPR
PCLKB/2048
PCLKB/8192
Count stop control output
in sleep mode
Event signal output
Internal peripheral bus
Figure 26.1
WDTRR:
WDTCR:
WDTSR:
WDTRCR:
WDTCSTPR:
Clock control circuit
Event Link Controller (ELC)
WDT Refresh Register
WDT Control Register
WDT Status Register
WDT Reset Control Register
WDT Stop Control Register
WDT block diagram
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26.2
26. Watchdog Timer (WDT)
Register Descriptions
26.2.1
WDT Refresh Register (WDTRR)
Address(es): WDT.WDTRR 4004 4200h
Value after reset:
Bit
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
Description
b7 to b0
R/W
The down-counter is refreshed by writing 00h and then writing FFh to this register
R/W
The WDTRR register refreshes the down-counter of the WDT.
The down-counter of the WDT is refreshed by writing 00h and then writing FFh to WDTRR (refresh operation) within
the refresh-permitted period. After the down-counter is refreshed, it starts counting down from the value selected by
setting the WDT Timeout Period Select bits (OFS0.WDTTOPS[1:0]) in the Option Function Select Register 0 in autostart mode. In register start mode, counting down starts from the value selected by setting the Timeout Period Select bits
(WDTCR.TOPS[1:0]) in the WDT Control Register.
When 00h is written, the read value is 00h. When a value other than 00h is written, the read value is FFh. For details on
the refresh operation, see section 26.3.3, Refresh Operation.
26.2.2
WDT Control Register (WDTCR)
Address(es): WDT.WDTCR 4004 4202h
Value after reset:
b15
b14
—
—
0
0
b13
b12
b11
b10
RPSS[1:0]
—
—
RPES[1:0]
1
0
0
1
1
b9
b8
b7
b6
b5
b4
CKS[3:0]
1
1
1
1
1
b3
b2
b1
b0
—
—
TOPS[1:0]
0
0
1
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
TOPS[1:0]
Timeout Period Selection
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0 and cannot be modified.
R/W
b7 to b4
CKS[3:0]
Clock Division Ratio Selection
b7
R/W
b9, b8
RPES[1:0]
Window End Position Selection
b9 b8
R/W
b11, b10
—
Reserved
These bits are read as 0 and cannot be modified.
R/W
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
0
0
1
1
0: 1024 cycles (03FFh)
1: 4096 cycles (0FFFh)
0: 8192 cycles (1FFFh)
1: 16384 cycles (3FFFh).
b4
0 0 0 1: PCLKB/4
0 1 0 0: PCLKB/64
1 1 1 1: PCLKB/128
0 1 1 0: PCLKB/512
0 1 1 1: PCLKB/2048
1 0 0 0: PCLKB/8192.
Other settings are prohibited.
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (window end position is not specified).
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26. Watchdog Timer (WDT)
Bit
Symbol
Bit name
Description
R/W
b13, b12
RPSS[1:0]
Window Start Position Selection
b13 b12
R/W
b15, b14
—
Reserved
These bits are read as 0 and cannot be modified.
R/W
0
0
1
1
0: 25%
1: 50%
0: 75%
1: 100% (window start position is not specified).
There are some restrictions in writing to the WDTCR register. For details, see section 26.3.2, Controlling Writes to the
WDTCR, WDTRCR, and WDTCSTPR Registers.
In auto-start mode, the settings in the WDTCR register are disabled, and the settings in the Option Function Select
Register 0 (OFS0) are enabled. The settings for the WDTCR register can also be made for the OFS0 register. For details,
see section 26.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
TOPS[1:0] bits (Timeout Period Selection)
The TOPS[1:0] bits select the timeout period (the period until the down-counter underflows) from 1024, 4096, 8192, and
16384 cycles, taking the divided clock specified by the CKS[3:0] bits as 1 cycle.
After the down-counter is refreshed, the combination of the CKS[3:0] and TOPS[1:0] bits determines the number of
PCLKB cycles until the counter underflows.
Table 26.2 lists the relationship between the CKS[3:0] and TOPS[1:0] bit settings, the timeout period, and the number of
PCLKB cycles.
Table 26.2
Timeout period settings
CKS[3:0] bits
TOPS[1:0] bits
b7
b6
b5
b4
b1
b0
Clock division ratio
Timeout period
(number of cycles)
PCLKB clock cycles
0
0
0
1
0
0
PCLKB/4
1,024
4,096
0
1
4,096
16,384
1
0
8,192
32,768
1
1
16,384
65,536
0
0
1,024
65,536
0
1
4,096
262,144
1
0
8,192
524,288
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
0
PCLKB/64
16,384
1,048,576
1,024
131,072
1
4,096
524,288
1
0
8,192
1,048,576
1
1
16,384
2,097,152
0
0
1,024
524,288
0
1
4,096
2,097,152
1
0
8,192
4,194,304
1
1
16,384
8,388,608
0
0
1,024
2,097,152
0
1
4,096
8,388,608
1
0
8,192
16,777,216
1
1
16,384
33,554,432
0
0
1,024
8,388,608
0
1
4,096
33,554,432
1
0
8,192
67,108,864
1
1
16,384
134,217,728
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PCLKB/128
PCLKB/512
PCLKB/2048
PCLKB/8192
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26. Watchdog Timer (WDT)
CKS[3:0] bits (Clock Division Ratio Selection)
The CKS[3:0] bits specify the division ratio of the clock used for the down-counter. The division ratio can be selected
from the peripheral clock (PCLKB) divided by 4, 64, 128, 512, 2,048, and 8,192. Combined with the TOPS[1:0] bit
setting, a count period between 4,096 and 134,217,728 cycles of the PCLKB clock can be selected for the WDT.
RPES[1:0] bits (Window End Position Selection)
The RPES[1:0] bits specify the window end position that indicates the refresh-permitted period. 75%, 50%, 25%, or 0%
of the timeout period can be selected for the window end position. The selected window end position should be a value
less than the value for the window start position (window start position > window end position). If the window end
position is greater than the window start position, only the window start position setting is enabled.
RPSS[1:0] bits (Window Start Position Selection)
The RPSS[1:0] bits specify the window start position that indicates the refresh-permitted period. 100%, 75%, 50%, or
25% of the timeout period can be selected for the window end position. The window start position should be set to a
value greater than the value for the window end position. If the window start position is set to a value smaller than or
equal to the window end position, the window end position is set to 0%.
Table 26.3 lists the counter values for the window start and end positions and Figure 26.2 shows the refresh-permitted
period set in the RPSS[1:0], RPES[1:0], and TOPS[1:0] bits.
Table 26.3
Relationship between timeout period and window start and end counter values
Timeout period
Window start and end counter value
TOPS[1:0] bits
Cycles
Counter value
100%
75%
50%
25%
0
0
1024
03FFh
03FFh
02FFh
01FFh
00FFh
0
1
4096
0FFFh
0FFFh
0BFFh
07FFh
03FFh
1
0
8192
1FFFh
1FFFh
17FFh
0FFFh
07FFh
1
1
16384
3FFFh
3FFFh
2FFFh
1FFFh
0FFFh
RPES[1:0] bits
RPSS[1:0] bits
b13
b12
1
b8
1
1
1
0
0
1
0
0
1
1
0
1
0
25
0
1
0
0
75
1
1
0
1
0
0
1
0
0
75
1
1
0
1
0
0
1
0
0
0
0
1
0
End
(%)
b9
1
1
Window
Start
(%)
0
Counting
started
Underflow
0
100
25
50
75
75
50
25
50
25
50
25
50
75
100%
75%
50%
25%
0%
Refresh-permitted period
Refresh-prohibited period
Note:
If window end setting ≥ window start setting, the window end setting is set to 0%.
Figure 26.2
RPSS[1:0] and RPES[1:0] bit settings and refresh-permitted period
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26.2.3
26. Watchdog Timer (WDT)
WDT Status Register (WDTSR)
Address(es): WDT.WDTSR 4004 4204h
b15
b14
b13
b12
b11
b10
b9
b8
REFEF UNDFF
Value after reset:
Bit
0
0
Symbol
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CNTVAL[13:0]
0
0
0
0
0
0
0
0
Bit Name
Description
R/W
b13 to b0
CNTVAL[13:0]
Down-Counter Value
Value counted by the down-counter
R
b14
UNDFF
Underflow Flag
0: No underflow occurred
1: Underflow occurred.
R(/W)
*1
b15
REFEF
Refresh Error Flag
0: No refresh error occurred
1: Refresh error occurred.
R(/W)
*1
Note 1.
Only 0 can be written to clear the flag.
CNTVAL[13:0] bits (Down-Counter Value)
Read the CNTVAL[13:0] bits to confirm the value of the down-counter. The read value might differ from the actual
count by a value of one count.
UNDFF flag (Underflow Flag)
Read the UNDFF flag to confirm whether an underflow occurred in the down-counter. The value 1 indicates that the
down-counter underflowed. Write 0 to the UNDFF flag to set the value to 0. Writing 1 has no effect.
Clearing of the UNDFF flag takes (N+1) PCLKB cycles. In addition, clearing of the flag is ignored for (N+1) PCLKB
cycles after an underflow. N is specified in the WDTCR.CKS[3:0] bits as follows:
When WDTCR.CKS[3:0] = 0001b, N = 4
When WDTCR.CKS[3:0] = 0100b, N = 64
When WDTCR.CKS[3:0] = 1111b, N = 128
When WDTCR.CKS[3:0] = 0110b, N = 512
When WDTCR.CKS[3:0] = 0111b, N = 2,048
When WDTCR.CKS[3:0] = 1000b, N = 8,192.
REFEF flag (Refresh Error Flag)
Read the REFEF flag to confirm whether a refresh error occurred. The value 1 indicates that a refresh error occurred.
Write 0 to the REFEF flag to set the value to 0. Writing 1 has no effect.
Clearing of the REFEF flag takes (N+1) PCLKB cycles. In addition, clearing of the flag is ignored for (N+1) PCLKB
cycles after a refresh error. N is specified in the WDTCR.CKS[3:0] bits as follows:
When WDTCR.CKS[3:0] = 0001b, N = 4
When WDTCR.CKS[3:0] = 0100b, N = 64
When WDTCR.CKS[3:0] = 1111b, N = 128
When WDTCR.CKS[3:0] = 0110b, N = 512
When WDTCR.CKS[3:0] = 0111b, N = 2,048
When WDTCR.CKS[3:0] = 1000b, N = 8,192.
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26.2.4
26. Watchdog Timer (WDT)
WDT Reset Control Register (WDTRCR)
Address(es): WDT.WDTRCR 4004 4206h
b7
b6
b5
b4
b3
b2
b1
b0
RSTIR
QS
—
—
—
—
—
—
—
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0 and cannot be modified
R/W
b7
RSTIRQS
Reset Interrupt Request Selection
0: Non-maskable interrupt request or interrupt request output
is enabled
1: Reset output is enabled.
R/W
There are some restrictions with writing to the WDTRCR register. For details, see section 26.3.2, Controlling Writes to
the WDTCR, WDTRCR, and WDTCSTPR Registers.
In auto-start mode, the WDTRCR register settings are disabled, and the settings in the Option Function Select Register 0
(OFS0) are enabled. The settings for the WDTCR register can also be made for the OFS0 register. For details, see section
26.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
26.2.5
WDT Count Stop Control Register (WDTCSTPR)
Address(es): WDT.WDTCSTPR 4004 4208h
b7
b6
b5
b4
b3
b2
b1
b0
SLCST
P
—
—
—
—
—
—
—
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0 and cannot be modified
R/W
b7
SLCSTP
Sleep-Mode Count Stop Control
0: Count stop is disabled
1: Count is stopped when transition to Sleep mode.
R/W
The WDTCSTPR register controls whether to stop the WDT counter in a low power state. There are some restrictions
with writing to the WDTCSTPR register. For details, see section 26.3.2, Controlling Writes to the WDTCR, WDTRCR,
and WDTCSTPR Registers.
In auto-start mode, the WDTCSTPR register settings are disabled, and the settings in the Option Function Select Register
0 (OFS0) are enabled. The settings for the WDTCSTPR register can also be made for the OFS0 register. For details, see
section 26.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
SLCSTP bit (Sleep-Mode Count Stop Control)
The SLCSTP bit selects whether to stop counting when transition to Sleep mode.
26.2.6
Option Function Select Register 0 (OFS0)
For details on the OFS0 register, see section 26.3.7, Association between Option Function Select Register 0 (OFS0) and
WDT Registers.
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26.3
26. Watchdog Timer (WDT)
Operation
26.3.1
Count Operation in Each Start Mode
The WDT has two start modes:
Auto-start mode, in which counting automatically starts after release from the reset state
Register start mode, in which counting starts with a refresh by writing to the register.
In auto-start mode, counting automatically starts after release from the reset state in accordance with the settings in the
Option Function Select Register 0 (OFS0) in the flash.
In register start mode, counting start with a refresh by writing to the register after the respective registers are set after
release from the reset state.
Select auto-start mode or register start mode by setting the WDT Start Mode Select bit (OFS0.WDTSTRT) in the OFS0
register. When the auto-start mode is selected, the settings in the WDT Control Register (WDTCR), WDT Reset Control
Register (WDTRCR), and WDT Count Stop Control Register (WDTCSTPR) are disabled while the settings in the OFS0
register are enabled.
When the register start mode is selected, the setting for the OFS0 register is disabled while the settings for the WDT
Control Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT Count Stop Control Register
(WDTCSTPR) are enabled.
26.3.1.1
Register start mode
When the WDT Start Mode Select bit (OFS0.WDTSTRT) is 1, register start mode is selected and the WDT Control
Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT Count Stop Control Register (WDTCSTPR)
are enabled.
After the reset state is released, set the following:
Clock division ratio
Window start and end positions
Timeout period in the WDTCR register
Reset output or interrupt request output in the WDTRCR register
Counter stop control during transitions to Sleep mode in the WDTCSTPR register.
Refresh the down-counter to start counting down from the value set by the Timeout Period Selection bits
(WDTCR.TOPS[1:0]).
Thereafter, as long as the counter is refreshed in the refresh-permitted period, the value in the counter is reset each time
the counter is refreshed, and counting down continues. The WDT does not output the reset signal as long as counting
continues. However, if the down-counter underflows because the down-counter cannot be refreshed due to a program
runaway, or if a refresh error occurs because the counter was refreshed outside the refresh-permitted period, the WDT
outputs a reset signal or a non-maskable interrupt request/interrupt request (WDT_NMIUNDF). Reset output or interrupt
request output can be selected by setting the WDT Reset Interrupt Request Selection bit (WDTRCR.RSTIRQS). Nonmaskable interrupt request or interrupt request can be selected by setting the WDT Underflow/Refresh Error Interrupt
Enable bit (NMIER.WDTEN).
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26. Watchdog Timer (WDT)
Figure 26.3 shows an example of operation under the following conditions:
Register start mode (OFS0.WDTSTRT = 1)
Reset output is enabled (WDTRCR.RSTIRQS = 1)
The window start position is 75% (WDTCR.RPSS[1:0] = 10b)
The window end position is 25% (WDTCR.RPES[1:0] = 10b).
Counter value
100%
Refreshprohibited
period
75%
Refreshpermitted
period
50%
25%
Refreshprohibited
period
0%
RES pin
Control
register
(WDTCR)
(1) Initial value
(2) Set value
Refresh
the counter
(active-high)
(2)
(1)
Writing to the
register is valid
(1)
Writing to the
register is invalid *1
(1)
Writing to Writing to the
the register register is invalid *1
is valid
(2)
Writing to the
register is valid
H
L
Counting starts
Counting starts
Underflow
Refresh error
flag
(active-high)
H
L
Underflow flag
(active-high)
H
L
Interrupt request
(WDT_NMIUNDF)
(active-high)
L
Reset output
from WDT
(active-high)
H
L
Note 1.
(2)
Counting starts
Refresh error
Refresh error
Status flag
cleared
Status flag
cleared
See section 26.3.2 Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers.
Figure 26.3
Operation example in register start mode
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26.3.1.2
26. Watchdog Timer (WDT)
Auto-start mode
When the WDT Start Mode Select bit (OFS0.WDTSTRT) in the Option Function Select Register 0 (OFS0) is 0, autostart mode is selected. The WDT Control Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT
Count Stop Control Register (WDTCSTPR) are disabled while the settings in the OFS0 register are enabled.
Within the reset state, the following values in the Option Function Select Register 0 (OFS0) are set in the WDT registers:
Clock division ratio
Window start and end positions
Timeout period
Reset output or interrupt request
Counter control stop at transition to Sleep mode.
When the reset state is released, the down-counter automatically starts counting down from the value set by the WDT
timeout period select bits (OFS0.WDTTOPS[1:0]).
Thereafter, as long as the counter is refreshed in the refresh-permitted period, the value in the counter is reset each time
the counter is refreshed and counting down continues. The WDT does not output the reset signal as long as counting
continues.
However, if the down-counter underflows because refreshing of the down-counter is not possible due to a runaway
program or if a refresh error occurs due to refreshing outside the refresh-permitted period, the WDT outputs a reset signal
or non-maskable interrupt request/interrupt request (WDT_NMIUNDF).
After the reset signal or non-maskable interrupt request/interrupt request is generated, the counter reloads the timeout
period after counting for 1 cycle. The value of the timeout period is set in the down-counter and counting restarts.
Reset output or interrupt request output can be selected by setting the WDT Reset Interrupt Request Select bit
(OFS0.WDTRSTIRQS). Non-maskable interrupt request or interrupt request can be selected by setting the WDT
Underflow/Refresh Error Interrupt Enable bit (NMIER.WDTEN).
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26. Watchdog Timer (WDT)
Figure 26.4 shows an example of operation (non-maskable interrupt) under the following conditions:
Auto start mode (OFS0.WDTSTRT = 0)
Non-maskable interrupt request output is enabled (OFS0.WDTRSTIRQS = 0)
The window start position is 75% (WDTCR.RPSS[1:0] = 10b)
The window end position is 25% (WDTCR.RPES[1:0] = 10b).
Counter value
100%
Refreshprohibited
period
75%
Refreshpermitted
period
50%
25%
Refreshprohibited
period
0%
RES pin
Refresh
the counter
(active-high)
H
L
Counting starts
Counting starts
Underflow
Refresh error
flag
(active-high)
H
L
Underflow flag
(active-high)
H
L
Interrupt request
(WDT_NMIUNDF)
(active-high)
H
L
Reset output
from WDT
(active-high)
L
Figure 26.4
Counting starts
Refresh error
Counting starts
Refresh error
Status flag
cleared
Status flag
cleared
Operation example in auto-start mode
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26.3.2
26. Watchdog Timer (WDT)
Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers
Writing to the WDT Control Register (WDTCR), WDT Reset Control Register (WDTRCR), or WDT Count Stop
Control Register (WDTCSTPR) is possible between the release from the reset state and the first refresh operation.
After a refresh, (counting starts) or writing to WDTCR, WDTRCR or WDTCSTPR, the protection signal in the WDT
becomes 1 to protect WDTCR, WDTRCR and WDTCSTPR against subsequent writing attempts. This protection is
released by a reset source of the WDT. With other reset sources, the protection is not released.
Figure 26.5 shows control waveforms produced in response to writing to the WDTCR.
RES pin
Peripheral clock (PCLKB)
Data written to WDTCR
register
xxxxh
WDTCR register write
signal (internal signal)
WDTCR register
Writing disabled
33F3h (initial value)
Register
protection signal
(internal signal)
Writing is possible
Figure 26.5
26.3.3
3300h
00F3h
00F3h
00F3h
33F3h (initial value)
WDTCR register is protected
(writing-disabled period)
Control waveforms produced in response to writing to WDTCR register
Refresh Operation
The down-counter is refreshed by writing the values 00h and FFh to the WDT Refresh Register (WDTRR). If a value
other than FFh is written after 00h, the down-counter is not refreshed. After an invalid value is written, correct refreshing
resumes by writing to 00h and FFh to the WDTRR register.
When a register other than WDTRR is accessed or WDTRR is read between writing 00h and writing FFh to WDTRR,
correct refreshing is performed.
Writing to refresh the counter must be performed within the refresh-permitted period and whether this is done is
determined by writing FFh. For this reason, correct refreshing is performed even when 00h is written outside the refreshpermitted period.
[Example sequences of writing that are valid when refreshing the counter]
00h → FFh
00h ((n–1)th time) → 00h (nth time) → FFh
00h → access to another register or read from WDTRR → FFh.
[Example sequences of writing that are not valid when refreshing the counter]
23h (a value other than 00h) → FFh
00h → 54h (a value other than FFh)
00h → AAh (00h and a value other than FFh) → FFh.
After FFh is written to the WDT Refresh Register (WDTRR), refreshing the down-counter requires up to 4 cycles of the
signal for counting. To meet this requirement, complete writing FFh to the WDTRR 4 cycle counts before the downcounter underflows.
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26. Watchdog Timer (WDT)
Figure 26.6 shows the WDT refresh-operation waveforms when the clock division ratio = PCLKB/64.
Peripheral clock
(PCLKB)
Data written to
WDTRR register
00h
54h
00h
FFh
WDTRR register
write signal
(internal signal)
WDTRR register
Valid
FFh
00h
FFh
FFh
Invalid
Refresh
synchronization
signal
Refresh signal
(after synchronization
with count cycle)
Counter value
00h
Refresh request
(n+1)h
(n)h
(n)h
(n-1)h
(n-1)h 0FFFh
Refreshing
Figure 26.6
26.3.4
WDT refresh operation waveforms (WDTCR.CKS[3:0] = 0100b, WDTCR.TOPS[1:0] = 01b)
Reset Output
When the Reset Interrupt Selection bit (WDTRCR.RSTIRQS) is set to 1 in register start mode or when the WDT Reset
Interrupt Request Select bit (OFS0.WDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 1 in autostart mode, a reset signal is output for 1 cycle count when an underflow in the down-counter or a refresh error occurs.
In register start mode, the down-counter is initialized (all bits set to 0) and stopped in that state after output of a reset
signal. After the reset state is released and the program restarts, the counter is set up and counting down starts again with
a refresh. In auto-start mode, counting down automatically starts after the reset state is released.
26.3.5
Interrupt Sources
When the Reset Interrupt Selection bit (WDTRCR.RSTIRQS) is set to 0 in register start mode or when the WDT Reset
Interrupt Request Select bit (OFS0.WDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 0 in autostart mode, an interrupt (WDT_NMIUNDF) signal is generated when an underflow in the counter or a refresh error
occurs. This interrupt can be used as a non-maskable interrupt or an interrupt. For details, see section 14, Interrupt
Controller Unit (ICU).
Table 26.4
WDT interrupt sources
Name
Interrupt source
DTC activation
WDT_NMIUNDF
Down-counter underflow
Refresh error.
Not possible
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26.3.6
26. Watchdog Timer (WDT)
Reading the Down-Counter Value
The WDT stores the counter value in the down-counter value (WDTSR.CNTVAL[13:0]) bits in the WDT Status
Register. Therefore, the counter value can be checked with these bits.
Figure 26.7 shows the processing for reading the WDT down-counter value when the clock division ratio = PCLKB/64.
Peripheral clock
(PCLKB)
Refreshing
Counter value
(n+1)h
Bits WDTSR.CNTVAL
[13:0]
(n+1)h
(n)h
(n-1)h
(n)h
(n-1)h
(n-1)h
0FFFh
(n-1)h
0FFFh
WDTSR.CNTVAL
[13:0] read signal
(internal signal)
WDTSR.CNTVAL
[13:0] read data
Figure 26.7
26.3.7
xxxxh
(n+1)h
(n)h
(n)h
0FFFh
Processing for reading WDT down-counter value when WDTCR.CKS[3:0] = 0100b,
WDTCR.TOPS[1:0] = 01b
Association between Option Function Select Register 0 (OFS0)
and WDT Registers
Table 26.5 lists the association between the Option Function Select Register 0 (OFS0) used in auto-start mode and the
registers used in register start mode.
Do not change the OFS0 register setting during WDT operation. For details on the Option Function Select Register 0
(OFS0), see section 7.2.1, Option Function Select Register 0 (OFS0).
Table 26.5
Association between Option Function Select Register 0 (OFS0) and WDT Registers
WDT registers
(enabled in register start mode)
OFS0.WDTSTRT = 1
Control target
Function
OFS0 register
(enabled in auto-start mode)
OFS0.WDTSTRT = 0
Down-counter
Timeout period selection
OFS0.WDTTOPS[1:0]
WDTCR.TOPS[1:0]
Clock division ratio selection
OFS0.WDTCKS[3:0]
WDTCR.CKS[3:0]
Window start position selection
OFS0.WDTRPSS[1:0]
WDTCR.RPSS[1:0]
Window end position selection
OFS0.WDTRPES[1:0]
WDTCR.RPES[1:0]
Reset output or interrupt
request output
Reset output or interrupt request
output selection
OFS0.WDTRSTIRQS
WDTRCR.RSTIRQS
Count stop
Sleep-mode count stop control
OFS0.WDTSTPCTL
WDTCSTPR.SLCSTP
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26.4
26. Watchdog Timer (WDT)
Link Operation by ELC
The WDT is capable of a link operation for the previously specified module when interrupt request signal is used as an
event signal by the ELC. The event signal is output by the counter underflow and refresh error.
An event signal is output regardless of the setting in the Reset Interrupt Request Selection bit (WDTRCR.RSTIRQS) in
register start mode or auto-start mode. An event signal can also be output when the next interrupt source is generated and
while the Refresh Error Flag (WDTSR.REFEF) or Underflow Flag (WDTSR.UNDFF) is 1. For details, see section 19,
Event Link Controller (ELC).
26.5
26.5.1
Usage Notes
ICU Event Link Setting Register n (IELSRn) Setting
Setting 25h to the ICU Event Link Setting Register n (IELSRn.IELS[7:0]) is prohibited when enabling the WDT reset
assertion (OFS0.WDTRSTIRQS = 1 or WDTRCR.RSTIRQS = 1) or when enabling the event link operation (25h is set
to ELSRm.ELS[7:0]).
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27. Independent Watchdog Timer (IWDT)
27.
Independent Watchdog Timer (IWDT)
27.1
Overview
The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to
prevent counter underflow. It can be used to reset the MCU or to generate a non-maskable interrupt/interrupt on a timer
underflow. Because the timer operates using an independent, dedicated clock source, it is particularly useful in returning
the MCU to a known state as a failsafe mechanism when the system runs out of control. The Watchdog Timer can be
triggered automatically by a reset, underflow, refresh error, or a refresh of the count value in the registers.
The functions of the IWDT are different from those of the WDT in the following respects:
The divided IWDT-dedicated clock (IWDTCLK) is used as the count source (not affected by the PCLKB)
IWDT does not support the register start mode
When transitioning to low power mode, the OFS0.IWDTSTPCTL bit can be used to select whether to stop the
counter or not.
Table 27.1 lists the IWDT specifications and Figure 27.1 shows a block diagram.
Table 27.1
IWDT specifications
Item
Count
Description
source*1
IWDT-dedicated clock (IWDTCLK)
Clock division ratio
Division by 1, 16, 32, 64, 128, or 256
Counter operation
Counting down using a 14-bit down-counter
Condition for starting the counter
Counting automatically starts after a reset
Conditions for stopping the
counter
Reset (the down-counter and other registers return to their initial values)
A counter underflows or a refresh error is generated.
Counting restarts automatically.
Window function
Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods)
Reset output sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Non-maskable interrupt/interrupt
sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Reading the counter value
The down-counter value can be read by the IWDTSR register
Event link function (output)
Down-counter underflow event output
Refresh error event output.
Output signal (internal signal)
Reset output
Interrupt request output
Sleep-mode count stop control output.
Auto-start mode
Configurable to the following triggers:
Clock frequency division ratio after a reset (OFS0.IWDTCKS[3:0] bits)
Timeout period of the Independent Watchdog Timer (OFS0.IWDTTOPS[1:0] bits)
Window start position in the Independent Watchdog Timer (OFS0.IWDTRPSS[1:0] bits)
Window end position in the Independent Watchdog Timer (OFS0.IWDTRPES[1:0] bits)
Reset output or interrupt request output (OFS0.IWDTRSTIRQS bit)
Down-count stop function at transition to Sleep mode, Software Standby mode, or Snooze mode
(OFS0.IWDTSTPCTL bit).
Note 1.
This must satisfy the frequency of the peripheral module clock (PCLKB) ≥ 4 × (the frequency of the count clock source after
division).
To use the IWDT, supply the IWDT-dedicated clock (IWDTCLK). The bus interface and registers operate with PCLKB,
and the 14-bit counter and control circuits operate with IWDTCLK.
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27. Independent Watchdog Timer (IWDT)
Interrupt request (IWDT_NMIUNDF)
Interrupt Controller Unit (ICU)
IWDT reset output
Reset control circuit
Clock
frequency
divider
IWDTCLK
IWDTCLK/16
IWDTCLK/32
IWDTCLK/64
IWDTCLK/128
IWDTCLK/256
IWDT control circuit
IWDTSR
Option Function Select Register 0
(OFS0)
14-bit counter
Count stop control output
in Sleep mode, Snooze mode, or
Software Standby mode
IWDTRR
IWDTCLK
Clock control circuit
Event signal output
Event Link Controller (ELC)
IWDTRR:
IWDTSR:
Internal peripheral bus
Figure 27.1
27.2
IWDT Refresh Register
IWDT Status Register
IWDT block diagram
Register Descriptions
27.2.1
IWDT Refresh Register (IWDTRR)
Address(es): IWDT.IWDTRR 4004 4400h
Value after reset:
Bit
b7 to b0
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
Description
The counter is refreshed by writing 00h and then writing FFh to this register
R/W
R/W
The IWDTRR register refreshes the down-counter of the IWDT. The down-counter of the IWDT is refreshed by writing
00h and then writing FFh to IWDTRR (refresh operation) within the refresh-permitted period. After the down-counter is
refreshed, it starts counting down from the value selected in the IWDT Timeout Period Select bits
(OFS0.IWDTTOPS[1:0]) in the Option Function Select Register 0 (OFS0).
When 00h is written, the read value is 00h. When a value other than 00h is written, the read value is FFh. For details on
the refresh operation, see section 27.3.2, Refresh Operation.
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27.2.2
27. Independent Watchdog Timer (IWDT)
IWDT Status Register (IWDTSR)
Address(es): IWDT.IWDTSR 4004 4404h
b15
b14
b13
b12
b11
b10
b9
b8
REFEF UNDFF
Value after reset:
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CNTVAL[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
b13 to b0
CNTVAL[13:0]
Counter Value
Value counted by the down-counter
R
b14
UNDFF
Underflow Flag
0: No underflow occurred
1: Underflow occurred.
R/(W)*1
b15
REFEF
Refresh Error Flag
0: No refresh error occurred
1: Refresh error occurred.
R/(W)*1
Note 1.
Description
R/W
Only 0 can be written to clear the flag.
CNTVAL[13:0] bits (Counter Value)
Read the CNTVAL[13:0] bits to confirm the value of the down-counter. The read value might differ from the actual
count by 1.
UNDFF flag (Underflow Flag)
Read the UNDFF flag to confirm whether an underflow occurred in the down-counter. The value 1 indicates that the
down-counter underflowed. Write 0 to the UNDFF flag to set the value to 0. Writing 1 has no effect.
Clearing of the UNDFF flag takes (N+2) IWDTCLK cycles and 2 PCLKB cycles. In addition, clearing of the flag is
ignored for (N+2) IWDTCLK cycles after an underflow. N is specified in the IWDTCKS[3:0] bits as follows:
When IWDTCKS[3:0] = 0000b, N = 1
When IWDTCKS[3:0] = 0010b, N = 16
When IWDTCKS[3:0] = 0011b, N = 32
When IWDTCKS[3:0] = 0100b, N = 64
When IWDTCKS[3:0] = 1111b, N = 128
When IWDTCKS[3:0] = 0101b, N = 256
REFEF flag (Refresh Error Flag)
Read the REFEF flag to confirm whether a refresh error occurred. The value 1 indicates that a refresh error occurred.
Write 0 to the REFEF flag to set the value to 0. Writing 1 has no effect.
Clearing of the REFEF flag takes (N+2) IWDTCLK cycles and 2 PCLKB cycles. In addition, clearing of the flag is
ignored for (N+2) IWDTCLK cycles after a refresh error. N is specified in the IWDTCKS[3:0] bits as follows:
When IWDTCKS[3:0] = 0000b, N = 1
When IWDTCKS[3:0] = 0010b, N = 16
When IWDTCKS[3:0] = 0011b, N = 32
When IWDTCKS[3:0] = 0100b, N = 64
When IWDTCKS[3:0] = 1111b, N = 128
When IWDTCKS[3:0] = 0101b, N = 256.
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27.2.3
27. Independent Watchdog Timer (IWDT)
Option Function Select Register 0 (OFS0)
For information on the Option Function Select Register 0 (OFS0), see section 7.2.1, Option Function Select Register 0
(OFS0).
IWDTTOPS[1:0] bits (IWDT Timeout Period Select)
The IWDTTOPS[1:0] bits select the timeout period, that is, the period until the down-counter underflows, from 128, 512,
1,024, or 2,048 cycles, taking the divided clock specified by the IWDTCKS[3:0] bits as 1 cycle.
After the down-counter is refreshed, the combination of the IWDTCKS[3:0] and IWDTTOPS[1:0] bits determines the
time, that is, the number of IWDTCLK cycles until the counter underflows. Table 27.2 lists the relationship between the
IWDTCKS[3:0] and IWDTTOPS[1:0] bit setting, the timeout period, and the number of IWDTCLK cycles.
Table 27.2
Timeout period settings
IWDTCKS[3:0] bits
b7
b6
b5
b4
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
0
IWDTTOPS[1:0] bits
0
1
0
1
1
b1
Clock division ratio
b0
IWDTCLK
Timeout period
(number of cycles)
IWDTCLK cycles
0
0
128
128
0
1
512
512
1
0
1,024
1,024
1
1
2,048
2,048
0
0
128
2,048
0
1
512
8,192
1
0
1,024
16,384
1
1
2,048
32,768
0
0
128
4,096
0
1
512
16,384
1
0
1,024
32,768
2,048
65,536
128
8,192
IWDTCLK/16
IWDTCLK/32
1
1
0
0
0
1
512
32,768
1
0
1,024
65,536
1
1
2,048
131,072
0
0
128
16,384
0
1
512
65,536
1
0
1,024
131,072
1
1
2,048
262,144
0
0
128
32,768
0
1
512
131,072
1
0
1,024
262,144
1
1
2,048
524,288
IWDTCLK/64
IWDTCLK/128
IWDTCLK/256
IWDTCKS[3:0] bits (IWDT-Dedicated Clock Frequency Division Ratio Select)
The IWDTCKS[3:0] bits specify the division ratio of the clock used for the down-counter. The division ratio can be
selected from the IWDT-dedicated clock (IWDTCLK) divided by 1, 16, 32, 64, 128, and 256. Combination with the
IWDTTOPS[1:0] bit setting, a count period between 128 and 524,288 cycles of the IWDTCLK clock can be selected for
the IWDT.
IWDTRPES[1:0] bits (IWDT Window End Position Select)
The IWDTRPES[1:0] bits specify the window end position that indicates the refresh-permitted period. 75%, 50%, 25%,
or 0% of the timeout period can be selected for the window end position. The selected window end position should be a
value smaller than the window start position. If the window end position is greater than the window start position, only
the window start position setting is enabled.
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27. Independent Watchdog Timer (IWDT)
IWDTRPSS[1:0] bits (IWDT Window Start Position Select)
The IWDTRPSS[1:0] bits specify the window start position that indicates the refresh-permitted period. 100%, 75%,
50%, or 25% of the timeout period can be selected for the window start position. The window start position should be a
value greater than the window end position. If the window start position is smaller than or equal to the window end
position, the window end position is set to 0%.
Table 27.3 lists the counter values for the window start and end positions, and Figure 27.2 shows the refresh-permitted
period set in the IWDTRPSS[1:0], IWDTRPES[1:0], and IWDTTOPS[1:0] bits.
Table 27.3
Relationship between timeout period and window start and end counter values
IWDTTOPS[1:0] bits
b1
b0
0
Timeout period
Window start and end counter value
Cycles
Counter value
100%
75%
50%
25%
0
128
007Fh
007Fh
005Fh
003Fh
001Fh
0
1
512
01FFh
01FFh
017Fh
00FFh
007Fh
1
0
1,024
03FFh
03FFh
02FFh
01FFh
00FFh
1
1
2,048
07FFh
07FFh
05FFh
03FFh
01FFh
IWDTRPSS[1:0] bits
b13
b12
IWDTRPES[1:0] bits
1
b8
1
1
1
0
0
1
0
0
1
1
0
1
0
25
0
1
0
0
1
1
0
1
0
25
0
1
0
0
75
1
1
0
1
0
0
1
0
0
0
0
1
0
End
(%)
b9
1
1
Window
Start
(%)
0
Counting
started
Underflow
0
100
25
50
75
75
50
75
50
25
50
25
50
75
100%
75%
50%
25%
0%
Refresh-permitted period
Refresh-prohibited period
Note:
If window end setting ≥ window start setting, the window end setting is set to 0%.
Figure 27.2
IWDTRPSS[1:0] and [IWDTRPES[1:0] bit settings and refresh-permitted period
IWDTRSTIRQS bit (IWDT Reset Interrupt Request Select)
The IWDTRSTIRQS bit specifies the behavior when an underflow or a refresh error occurred. The value 1 indicates that
reset output is selected. The value 0 indicates that a non-maskable interrupt/interrupt is selected.
IWDTSTPCTL bit (IWDT Stop Control)
The IWDTSTPCTL bit selects whether the stop counting at a transition to Sleep mode, Snooze mode, or Software
Standby mode.
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27.3
27.3.1
27. Independent Watchdog Timer (IWDT)
Operation
Auto-Start Mode
When the IWDT Start Mode Select bit (OFS0.IWDTSTRT) in the Option Function Select Register 0 is 0, auto-start
mode is selected, otherwise IWDT is disabled.
Within the reset state, the following values in the Option Function Select Register 0 (OFS0) are set in the IWDT
registers:
Clock division ratio
Window start and end positions
Timeout period
Reset output or interrupt request
Counter stop control at transitions to low power mode.
When the reset state is released, the counter automatically starts counting down from the value selected by the IWDT
Timeout Period Select bits (OFS0.IWDTTOPS[1:0]).
After that, as long as the program continues normal operation and the counter is refreshed within the refresh-permitted
period, the value in the counter is reset each time the counter is refreshed and counting down continues. The IWDT does
not output the reset signal as long as this procedure continues. However, if the counter underflows because the program
crashed or because a refresh error occurs when an attempt to refresh is made outside the refresh-permitted period, the
IWDT asserts the reset signal or non-maskable interrupt request/interrupt request (IWDT_NMIUNDF).
After the reset signal or non-maskable interrupt request/interrupt request is generated, the counter reloads the timeout
period after counting for 1 cycle, and restarts the count. The reset output or interrupt request can be selected by setting
the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS). Non-maskable interrupt request or interrupt
request can be selected in the IWDT Underflow/Refresh Error Interrupt Enable bit (NMIER.IWDTEN).
Figure 27.3 shows an example of operation under the following conditions:
Auto-start mode (OFS0.IWDTSTRT = 0)
Non-maskable interrupt request output is enabled (OFS0.IWDTRSTIRQS = 0)
The window start position is 75% (OFS0.IWDTRPSS[1:0] = 10b)
The window end position is 25% (OFS0.IWDTRPES[1:0] = 10b).
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27. Independent Watchdog Timer (IWDT)
Counter value
100%
75%
50%
25%
0%
Refreshprohibited period
Refreshpermitted period
Refreshprohibited period
RES pin
Refresh
the counter
(active-high)
H
L
Counting starts
Counting starts
Underflow
Refresh error flag
(active-high)
H
Underflow flag
(active-high)
H
Interrupt request
(IWDT_NMIUNDF)
(active-high)
Counting starts
Refresh error
Counting starts
Refresh error
Status flag
cleared
L
L
Status flag
cleared
H
L
Reset output
from IWDT
(active-high) L
Figure 27.3
27.3.2
Operation example in auto-start mode
Refresh Operation
The down-counter is refreshed by writing the values 00h and FFh to the IWDT Refresh Register (IWDTRR). If a value
other than FFh is written after 00h, the down-counter is not refreshed. If an invalid value is written, correct refreshing
resumes on writing 00h and FFh to the IWDT Refresh Register (IWDTRR) again.
When writing is done in the order of 00h (first time) → 00h (second time), and if FFh is written after that, the writing
order 00h → FFh is satisfied. Writing 00h ((n–1)th time) → 00h (nth time) → FFh is valid, and the correct refresh is
done. When the first value written before 00h is not 00h, correct refreshing is performed if the operation contains the
write sequence 00h → FFh. Correct refreshing is also performed regardless of whether a register other than IWDTRR is
accessed or IWDTRR is read between writing 00h and writing FFh to IWDTRR.
[Example sequences of writing that are valid for refreshing the counter]
00h → FFh
00h ((n–1)th time) → 00h (nth time) → FFh
00h → access to another register or read from IWDTRR → FFh.
[Example sequences of writing that are not valid for refreshing the counter]
23h (a value other than 00h) → FFh
00h → 54h (a value other than FFh)
00h → AAh (00h and a value other than FFh) → FFh.
When 00h is written to IWDTRR outside the refresh-permitted period, if FFh is written to IWDTRR in the refreshpermitted period, the writing sequence is valid and refreshing is done.
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27. Independent Watchdog Timer (IWDT)
After FFh is written to the IWDTRR register, refreshing the counter requires up to 4 cycles of the signal for counting (the
IWDT-Dedicated Clock Frequency Division Ratio Select bits (OFS0.IWDTCKS[3:0]) determine how many cycles of the
IWDT-dedicated clock (IWDTCLK) make up 1 cycle for counting). To meet this requirement, complete writing FFh to
the IWDTRR 4 count cycles before the end of the refresh-permitted period or a counter underflow. The value of the
counter can be checked in the counter bits (IWDTSR.CNTVAL[13:0]).
[Sample refreshing timings]
When the window start position is set to 1FFFh, even if 00h is written to IWDTRR before 1FFFh is reached (2002h,
for example), refreshing occurs if FFh is written to IWDTRR after the value of the IWDTSR.CNTVAL[13:0] bits
reaches 1FFFh.
When the window end position is set to 1FFFh, refreshing occurs if 2003h (4 count cycles before 1FFFh) or a
greater value is read from the IWDTSR.CNTVAL[13:0] bits immediately after writing 00h → FFh to IWDTRR.
When the refresh-permitted period continues until count 0000h, refreshing can be performed immediately before an
underflow. In this case, if 0003h (4 count cycles before an underflow) or a greater value is read from the
IWDTSR.CNTVAL[13:0] bits immediately after writing 00h → FFh to IWDTRR, no underflow occurs and
refreshing is performed.
Figure 27.4 shows the IWDT refresh-operation waveforms when PCLKB > IWDTCLK and the clock division ratio is
IWDTCLK.
Peripheral clock
(PCLKB)
IWDT-dedicated
clock (IWDTCLK)
Data written to
IWDTRR register
00h
54h
00h
FFh
IWDTRR register write
signal (internal signal)
IWDTRR register
Valid
FFh
00h
FFh
FFh
Invalid
Refresh
synchronization signal
Refresh signal
(after synchronization
with IWDTCLK)
Counter value
00h
Refresh request
(n+2)h
(n+1)h
(n)h
(n-1)h
(n-2)h
(n-3)h
3FFFh
Refreshing
Figure 27.4
27.3.3
IWDT refresh operation waveforms when OFS0.IWDTCKS[3:0] = 0000b, OFS0.IWDTTOPS[1:0] =
11b
Status Flags
The refresh error (IWDTSR.REFEF) and underflow (IWDTSR.UNDFF) flags retain the source of the reset signal output
from the IWDT or the source of the interrupt request from the IWDT. Therefore, after a release from the reset state or
interrupt request generation, read the IWDTSR.REFEF and UNDFF flags to check for the reset or interrupt source. For
each flag, writing 0 clears the bit and writing 1 has no effect.
Leaving the status flags unchanged does not affect operation. If the flags are not cleared at the next reset or interrupt
request from the IWDT, the earlier reset or interrupt source is cleared and the new reset or interrupt source is written.
After 0 is written to each flag, up to 3 IWDTCLK cycles and 2 PCLKB cycles are required before the value is reflected.
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27.3.4
27. Independent Watchdog Timer (IWDT)
Reset Output
When the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS) in the Option Function Select Register 0
(OFS0) is set to 1, a reset signal is output when an underflow in the counter or a refresh error occurs. Counting down
automatically starts after the reset output.
27.3.5
Interrupt Sources
When the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS) in the Option Function Select Register 0
(OFS0) is set to 0, an interrupt (IWDT_NMIUNDF) signal is generated when an underflow in the counter or a refresh
error occurs. This interrupt can be used as a non-maskable interrupt or an interrupt. For details, see section 14, Interrupt
Controller Unit (ICU).
Table 27.4
IWDT interrupt source
Name
Interrupt source
DTC activation
IWDT_NMIUNDF
Down-counter underflow
Refresh error
Not possible
27.3.6
Reading the Down-counter Value
As the counter in IWDT-dedicated clock (IWDTCLK), the counter value cannot be read directly. The IWDT
synchronizes the counter value with the peripheral clock (PCLKB) and stores it in the down-counter value bits
(IWDTSR.CNTVAL[13:0]) of the IWDT Status register. Therefore, the counter value can be checked indirectly through
the IWDTSR.CNTVAL[13:0] bits.
Reading the counter value requires multiple PCLKB clock cycles (up to 4 clock cycles), and the read counter value might
differ from the actual counter value by a value of one count.
Figure 27.5 shows the processing for reading the IWDT counter value when PCLKB > IWDTCLK and the clock division
ratio is IWDTCLK.
Peripheral clock
(PCLKB)
IWDT-dedicated
clock (IWDTCLK)
Refreshing
(after synchronization with IWDTCLK)
Counter value
Bits
IWDTSR.CNTVAL
[13:0]
(n+1)h
(n)h
(n+1)h
(n-1)h
(n)h
(n-2)h
(n-1)h
3FFFh
(n-3)h
(n-2)h
(n-3)h
3FFEh
3FFFh
IWDTSR.CNTVAL
[13:0] read signal
(internal signal)
IWDTSR.CNTVAL
[13:0] read data
Figure 27.5
27.4
xxxxh
(n+1)h
(n)h
(n-2)h
3FFFh
Processing for reading IWDT counter value when OFS0.IWDTCKS[3:0] = 0000b,
OFS0.IWDTTOPS[1:0] = 11b
Output to the ELC
The IWDT is capable of link operation for a specified module when the interrupt request signal is used as an event signal
by the Event Link Controller (ELC). The event signal is output by the counter underflow and refresh error.
An event signal is output regardless of the setting in the OFS0.WDTRSTIRQS bit. An event signal can also be output
when the next interrupt source is generated while the Refresh Error flag (IWDTSR.REFEF) or Underflow Flag
(IWDTSR.UNDFF) is 1. For details, see section 19, Event Link Controller (ELC).
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27.5
27.5.1
27. Independent Watchdog Timer (IWDT)
Usage Notes
Refresh Operations
While configuring the refresh time, consider variations in the range of errors due to the accuracy of PCLKB and
IWDTCLK, and set values to ensure that refreshing is possible.
27.5.2
Clock Division Ratio Setting
Satisfy the following required frequency of the peripheral module clock (PCLKB):
PCLKB ≥ 4 × (the frequency of the count clock source after division).
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28. USB 2.0 Full-Speed Module (USBFS)
28.
USB 2.0 Full-Speed Module (USBFS)
28.1
Overview
The MCU provides a USB 2.0 Full-Speed module (USBFS) that operates as a host or device controller compliant with
the Universal Serial Bus (USB) specification revision 2.0. The host controller supports USB 2.0 full-speed and lowspeed transfers, and the device controller supports USB 2.0 full-speed transfers. The USBFS has an internal USB
transceiver and supports all of the transfer types defined in the USB 2.0 specification.
The USBFS has FIFO buffer for data transfers, providing a maximum of 10 pipes. Any endpoint number can be assigned
to pipes 1 to 9, based on the peripheral devices or the communication requirements for your system.
The MCU supports revision 1.2 of the Battery Charging Specification. Because the MCU can be powered at 5 V, the
USB LDO regulator provides the internal USB transceiver power supply at 3.3 V.
Table 28.1 lists the USBFS specifications, Figure 28.1 shows a block diagram, and Table 28.2 lists the I/O pins.
Table 28.1
USBFS specifications
Item
Specifications
Features
USB Device Controller (UDC) and USB 2.0 transceiver supporting host controller, device
controller, and On-The-Go (OTG) functions (one channel)
Host and device controller can be switched by software
Self-power or bus power mode selectable
Revision 1.2 of Battery Charging Specification is supported
The USB LDO regulator is used to power the internal USB transceiver.
Host controller features:
Full-speed transfer (12 Mbps) and low-speed transfer (1.5 Mbps)
Automatic scheduling for SOF and packet transmissions
Programmable intervals for isochronous and interrupt transfers
Device controller features:
Full-speed transfer (12 Mbps) and low-speed transfer (1.5 Mbps)
Control transfer stage control function
Device state control function
Auto response function for SET_ADDRESS request
SOF interpolation.
Communication data transfer type
Pipe configuration
FIFO buffer for USB communication
Up to 10 pipes selectable, including the default control pipe
Pipes 1 to 9 assignable to any endpoint number.
Control transfer
Bulk transfer
Interrupt transfer
Isochronous transfer.
Transfer conditions specifiable for each pipe:
Pipe 0: Control transfer with 64-byte single buffer
Pipes 1 and 2: Selectable to bulk transfer with 64-byte double buffer or isochronous transfer
with 256-byte double buffer
Pipes 3 to 5: Bulk transfer with 64-byte double buffer
Pipes 6 to 9: Interrupt transfer with 64-byte single buffer.
Others
Reception end function using transaction count
Function that changes the BRDY interrupt event notification timing (BFRE)
Automatic clearing of the FIFO buffer after the data for the pipe specified in the DnFIFO port (n
= 0, 1) is read (DCLRM)
NAK setting function for response PID generated on transfer end (SHTNAK)
On-chip pull-up and pull-down resistors for USB_DP/USB_DM
HOCO clock that can be used as USB clock.
Module-stop function
Module-stop state can be set to reduce power consumption
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28. USB 2.0 Full-Speed Module (USBFS)
VCC_USB_LDO
USB LDO
Regulator
VCC_USB
BC
control
Battery charging
controller
LINK core
Bus interface controller
Registers
USB device
controller
USB_DP
Interrupt
controller
USB_DM
USB protocol
engine
Internal peripheral bus
Registers
FIFO buffer
controller
Memory
controller
FIFO
controller
PCLKB
USB transceiver
USB clock (48 MHz)
Figure 28.1
USB clock control
1-port SRAM
(16-bit width)
USB clock (48 MHz)
PCLKB
USBFS block diagram
Table 28.2 lists the I/O pins of the USBFS.
Table 28.2
USBFS pin configuration
Port
Pin name
I/O
Function
USBFS
USB_DP
I/O
D+ I/O pin for the on-chip USB transceiver.
Must be connected to the D+ data line of the USB bus.
USB_DM
I/O
D– I/O pin for the on-chip USB transceiver.
Must be connected to the D- data line of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin.
Must be connected to VBUS signal on the USB bus. VBUS pin status (connected or
disconnected) can be detected when the USBFS is a device controller.*1
USB_EXICEN
Output
Low-power control signal for the OTG power supply IC
USB_VBUSEN
Output
VBUS (5 V) enable signal for the external power supply IC
USB_OVRCURA
USB_OVRCURB
Input
Overcurrent pins for USBFS.
Must be connected to external overcurrent detection signals. When the OTG power
supply chip is connected, must be connected to the VBUS comparator signals.
USB_ID
Input
Must be connected to MicroAB connector ID input signal in OTG mode
VCC_USB
I/O
Input: Power supply for USB transceiver.
Output: USB LDO regulator output pin. This pin should be connected to an
external capacitor.
VCC_USB_LDO
Input
Power supply pin for USB LDO regulator
VSS_USB
Input
USB ground pin
Common
Note 1.
P407 is 5-V tolerant.
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28.2
28. USB 2.0 Full-Speed Module (USBFS)
Register Descriptions
28.2.1
System Configuration Control Register (SYSCFG)
Address(es): USBFS.SYSCFG 4009 0000h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
SCKE
—
CNEN
—
0
0
0
0
0
0
0
0
0
b6
b5
b4
b3
DCFM DRPD DPRPU DMRP
U
0
0
0
0
b2
b1
b0
—
—
USBE
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
USBE
USBFS Operation Enable
0: Disabled
1: Enabled.
R/W
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Control*1
0: Line pull-up disabled
1: Line pull-up enabled.
R/W
b3
DMRPU
D- Line Resistor
b4
DPRPU
D+ Line Resistor Control*1
0: Line pull-up disabled
1: Line pull-up enabled.
R/W
b5
DRPD
D+/D– Line Resistor Control
0: Line pull-down disabled
1: Line pull-down enabled.
R/W
b6
DCFM
Controller Function Select
0: Device controller selected
1: Host controller selected.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b8
CNEN
CNEN Single-ended Receiver
Enable
0: Single-ended receiver disabled
1: Single-ended receiver enabled.
R/W
b9
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
0: Clock supply to the USBFS stopped
1: Clock supply to the USBFS enabled.
R/W
These bits are read as 0. The write value should be 0.
R/W
b10
SCKE
USB Clock
b15 to b11
—
Reserved
Note 1.
Note 2.
Enable*2
Do not enable the DMRPU and DPRPU bits at the same time.
After writing 1 to the SCKE bit, read it to confirm that it is set to 1.
USBE bit (USBFS Operation Enable)
The USBE bit enables or disables operation of the USBFS.
Changing the USBE bit from 1 to 0 initializes the bits listed in Table 28.3. Only change this bit while the SCKE bit is 1.
In host controller mode, this bit must be set to 1 after setting the DRPD bit to 1, eliminating SYSSTS0.LNST[1:0] bit
chattering, and confirming that the USB bus state is stable.
Table 28.3
Registers initialized by writing 0 to SYSCFG.USBE bit
Selected function
Register
Bit
Remarks
Device controller
SYSSTS0
LNST[1:0]
Value is saved in host controller mode
DVSTCTR0
RHST[2:0]
-
INTSTS0
DVSQ[2:0]
Value is saved in host controller mode
USBREQ
BREQUEST[7:0],
BMREQUESTTYPE[7:0]
Value is saved in host controller mode
USBVAL
WVALUE[15:0]
Value is saved in host controller mode
USBINDX
WINDEX[15:0]
Value is saved in host controller mode
USBLENG
WLENTUH[15:0]
Value is saved in host controller mode
DVSTCTR0
RHST[2:0]
-
FRMNUM
FRNM[10:0]
Value is saved in device controller mode
Host controller
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28. USB 2.0 Full-Speed Module (USBFS)
DMRPU bit (D- Line Resistor Control*1)
The DMRPU bit enables or disables pulling up the D- line in device controller mode.
When the DMRPU bit is set to 1 in device controller mode, the USBFS pulls up the D- line to notify the USB host that it
attached as a low-speed device. Changing the DMRPU bit from 1 to 0 releases the pull-up, thereby notifying the USB
host that it detached.
Set this bit to 0 in host controller mode.
DPRPU bit (D+ Line Resistor Control*1)
The DPRPU bit enables or disables pulling up the D+ line in device controller mode.
When the DPRPU bit is set to 1 in device controller mode, the USBFS pulls up the D+ line to notify the USB host that it
attached. Changing the DPRPU bit from 1 to 0 releases the pull-up, thereby notifying the USB host that it detached.
Set this bit to 0 in host controller mode.
DRPD bit (D+/D– Line Resistor Control)
The DRPD bit enables or disables pulling down D+ and D- lines in host controller mode.
Set this bit to 1 in host controller mode and to 0 in device controller mode.
DCFM bit (Controller Function Select)
The DCFM bit selects the host or device function of the USBFS.
Only change this bit when the DMRPU, DPRPU, and DRPD bits are 0.
CNEN bit (CNEN Single-ended Receiver Enable)
Setting the CNEN bit to 1 enables the single-ended receiver and sets the LNST bit to monitor the status of D+ and Dlines.
The CNEN bit is used when the USBFS operates as a portable device for battery charging.
SCKE bit (USB Clock Enable*2)
The SCKE bit stops or enables supplying 48-MHz clock supply to the USB.
When this bit is 0, only SYSCFG can be read from and written to. No other USB-related registers can be read from or
written to.
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28.2.2
28. USB 2.0 Full-Speed Module (USBFS)
System Configuration Status Register 0 (SYSSTS0)
Address(es): USBFS.SYSSTS0 4009 0004h
b15
b14
OVCMON[1:0]
0*1
Value after reset:
0*1
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
—
—
—
—
—
—
—
HTACT
—
—
—
IDMON
0
0
0
0
0
0
0
0
0
0
0
0*1
b1
b0
LNST[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
LNST[1:0]
USB Data Line Status Monitor
Indicates the status of the USB data lines. See Table 28.4.
R
b2
IDMON
External ID0 Input Pin Monitor
0: USB_ID pin is low
1: USB_ID pin is high.
R
b5 to b3
—
Reserved
These bits are read as 0
R
b6
HTACT
USB Host Sequencer Status
Monitor
0: Host sequencer completely stopped
1: Host sequencer not completely stopped.
R
b13 to b7
—
Reserved
These bits are read as 0
R
b15, b14
OVCMON[1:0] External USB_OVRCURA/
USB_OVRCURB Input Pin
Monitor
OVCMON[1] bit indicates the USB_OVRCURA pin status.
OVCMON[0] bit indicates the USB_OVRCURB pin status.
R
Note 1.
Depends on the status of the USB_OVRCURA/USB_OVRCURB and USB_ID pins.
LNST[1:0] bits (USB Data Line Status Monitor)
The LNST[1:0] bits indicate the state of the USB data lines, D+ and D-. For details, see Table 28.4.
In device controller mode, read the LNST[1:0] bits after connection processing (SYSCFG.DPRPU bit = 1) or after
enabling pull-down of the lines (SYSCFG.DRPD bit = 1) in host controller mode.
HTACT bit (USB Host Sequencer Status Monitor)
The HTACT bit is 0 when the host sequencer of the USBFS is completely stopped.
In host controller mode, check that the HTACT bit is 0 before setting the DVSTCTR0.UACT bit to 0 to place the USBFS
in a suspended state or setting the SCKE bit to 0 to stop the clock supply during communication.
OVCMON[1:0] bits (External USB_OVRCURA/ USB_OVRCURB Input Pin Monitor)
The OCVMON[1:0] bits indicate the status of the overcurrent signals from an external power supply IC.
Table 28.4
Status of USB data bus lines (D+ Line, D- Line)
LNST[1:0] bits
During full-speed operation
During low-speed operation
00b
SE0
SE0
01b
J-State
K-State
10b
K-State
J-State
11b
SE1
SE1
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28.2.3
28. USB 2.0 Full-Speed Module (USBFS)
Device State Control Register 0 (DVSTCTR0)
Address(es): USBFS.DVSTCTR0 4009 0008h
Value after reset:
b15
b14
b13
b12
—
—
—
—
0
0
0
0
b11
b10
b9
b8
b7
b6
b5
HNPBT EXICE VBUSE WKUP RWUP USBRS RESU
OA
N
N
E
T
ME
0
0
0
0
0
0
b4
b3
UACT
—
0
0
0
b2
b1
b0
RHST[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
RHST[2:0]
USB Bus Reset Status
In host controller mode:
R
b2
b0
0 0 0: Communication speed indeterminate
(powered state or no connection)
1 x x: USB bus reset in progress
0 0 1: Low-speed connection
0 1 0: Full-speed connection.
In device controller mode:
b2
b0
0 0 0: Communication speed indeterminate
0 0 1: USB bus reset in progress or low-speed connection
0 1 0: USB bus reset in progress or full-speed connection.
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
UACT
USB Bus Enable
0: Downstream port disabled (SOF transmission disabled)
1: Downstream port enabled (SOF transmission enabled).
R/W
b5
RESUME
Resume Output
0: Resume signal not output
1: Resume signal output.
R/W
b6
USBRST
USB Bus Reset Output
0: USB bus reset signal not output
1: USB bus reset signal output.
R/W
b7
RWUPE
Wakeup Detection Enable
0: Downstream port wakeup disabled
1: Downstream port wakeup enabled.
R/W
b8
WKUP
Wakeup Output
0: Remote wakeup signal not output
1: Remote wakeup signal output.
R/W
b9
VBUSEN
USB_VBUSEN Output Pin
Control
0: External USB_VBUSEN pin outputs low
1: External USB_VBUSEN pin outputs high.
R/W
b10
EXICEN
USB_EXICEN Output Pin
Control
0: External USB_EXICEN pin outputs low
1: External USB_EXICEN pin outputs high.
R/W
b11
HNPBTOA
Host Negotiation Protocol (HNP)
Control
This bit is used when switching from device B to device A in
OTG mode. If the HNPBTOA bit is 1, the internal function
control remains in the suspended state until the HNP
processing ends even if SYSCFG.DPRPU = 0 or
SYSCFG.DCFM = 1.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b12 —
x: Don’t care
RHST[2:0] bits (USB Bus Reset Status)
The RHST[2:0] bits indicate the status of the USB bus reset.
In host controller mode, writing 1 to the USBRST bit causes the RHST[2:0] bits to set to 100b. When 0 is written to the
USBRST bit and the USBFS ends the SE0 state, the RHST[2:0] bits update to a new value.
In device controller mode, if the USBFS detects a USB bus reset, the RHST[2:0] bits are set to 010b if the DPRPU bit is
1 or 001b if the DMRPU is 1, and a DVST interrupt is generated.
UACT bit (USB Bus Enable)
When set to 1 in host controller mode, the UACT bit enables USB bus operation by controlling SOF packet transmission
to the USB bus in addition to data and reception. The USBFS starts SOF packet output within one frame period after this
bit is set to 1. When UACT is set to 0, the USB enters the idle state after the SOF packet output.
With this bit set to 0, the USB enters an idle state after outputting SOF packets.
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28. USB 2.0 Full-Speed Module (USBFS)
The USB sets the UACT bit to 0 on any of the following conditions:
A DTCH interrupt is detected during communication (when UACT = 1)
An EOFERR interrupt is detected during communication (when UACT = 1).
Always write 1 to the UACT bit at the end of the USB bus reset processing (writing 0 to the USBRST bit) or at the end
of resume processing from the suspended state (writing 0 to the RESUME bit).
In device controller mode, always set this bit to 0.
RESUME bit (Resume Output)
The RESUME bit controls the resume signal output in host controller mode.
When this bit is set to 1, the USBFS drives the USB port to the K-state and outputs the resume signal. The USBFS sets
the bit to 1 on detection of a remote wakeup signal while the RWUPE bit is 1 and in the USB suspended state.
The USBFS continues outputting the K-state while the RESUME bit is 1, until the bit is set to 0 by software. The
RESUME bit must be 1 (resume period) for the time defined in the USB 2.0 specification. Only set this bit to 1 while the
interface is in the suspended state. Write 1 to the UACT bit simultaneously with the end of the resume processing
(writing 0 to the RESUME bit).
Always set this bit to 0 in device controller mode.
USBRST bit (USB Bus Reset Output)
The USBRST bit controls the output of the USB bus reset signal in host controller mode. When this bit is set to 1, the
USBFS drives the USB port to the SE0 state to reset the USB bus. The USBFS continues outputting SE0 while the
USBRST bit is 1, until the bit is cleared to 0 by software. The USBRST bit must be 1 (USB bus reset period) for the time
defined in the USB 2.0 specification.
Writing 1 to this bit during communication (UACT bit = 1) or during resume processing (RESUME bit = 1) prevents the
USBFS from starting USB bus reset processing until both the UACT and RESUME bits become 0. Write 1 to the UACT
bit simultaneously with the end of the USB bus reset processing (writing 0 to the USBRST bit).
Always set this bit to 0 in device controller mode.
RWUPE bit (Wakeup Detection Enable)
The RWUPE bit enables or disables remote wakeup signals (resume signals) from downstream peripheral devices in host
controller mode. When this bit is set to 1, the USBFS detects a remote wakeup signal (K-state for 2.5 μs) from a
downstream peripheral device, and it performs resume processing, driving the K-state.
When this bit set to 0, the USBFS ignores remote wakeup signals (K-states) from peripheral devices connected to the
USB port. Do not stop the internal clock while the RWUPE bit is 1, even in the suspended state (SYSCFG.SCKE bit must
be set to 1). Always set this bit to 0 in device controller mode.
WKUP bit (Wakeup Output)
The WKUP bit enables or disables remote wakeup signals (resume signals) to the USB bus in device controller mode.
The USBFS controls the output timing of the remote wakeup signals. When this bit is set to 1, the USBFS clears it to 0
after outputting the K-state for 10 ms. The USB 2.0 specification specifies that the USB bus idle state must be kept for
5 ms or longer before a remote wakeup signal is sent. If the USB writes 1 to this bit immediately after detecting the
suspended state, the K-state is output after 2 ms.
Only write 1 to this bit when the device is in the suspended state (INTSTS0.DVSQ[2:0] bits = 1xxb) and the USB host
enables the remote wakeup signal. Do not stop the internal clock while this bit is 1, even in the suspended state
(SYSCFG.SCKE bit is 1). Set this bit to 0 in host controller mode.
HNPBTOA bit (Host Negotiation Protocol (HNP) Control)
The HNPBTOA bit is used when switching from device B to device A while in OTG mode.
If the HNPBTOA bit is 1, the internal function control maintains the suspended state until the HNP processing ends, even
if the SYSCFG.DPRPU bit is 0 or the SYSCFG.DCFM bit is set to 1. Resume (RESM) interrupts are not generated even
if the falling edge of the D+ signal is detected.
The HNP processing ends when a host attach event is detected, because of a pull-up by the initiating party, or the
HNPBTOA bit is set to 0 by software because the HNP processing times out.
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28.2.4
28. USB 2.0 Full-Speed Module (USBFS)
CFIFO Port Register (CFIFO/CFIFOL)
D0FIFO Port Register (D0FIFO/D0FIFOL)
D1FIFO Port Register (D1FIFO/D1FIFOL)
(1) When the MBW bit is 1
Address(es): USBFS.CFIFO 4009 0014h, USBFS.D0FIFO 4009 0018h, USBFS.D1FIFO 4009 001Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
FIFOPORT[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
(2) When the MBW bit is 0
Address(es): USBFS.CFIFOL 4009 0014h, USBFS.D0FIFOL 4009 0018h, USBFS.D1FIFOL 4009 001Ch
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
FIFOPORT[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
FIFOPORT[15:0]*1
FIFO Port
Read receive data from the FIFO buffer or write transmit data to
the FIFO buffer by accessing these bits
R/W
Note 1.
The valid bits depend on the MBW settings (CFIFOSEL.MBW, D0FIFOSEL.MBW, and D1FIFOSEL.MBW) and BIGEND
settings (CFIFOSEL.BIGEND, D0FIFOSEL.BIGEND, and D1FIFOSEL.BIGEND) in the associated port select register. See
Table 28.5 and Table 28.6.
Three FIFO ports are available:
CFIFO
D0FIFO
D1FIFO.
Each FIFO port is configured with:
A port register (CFIFO, D0FIFO, or D1FIFO) that handles reading of data from the FIFO buffer and writing of data
to the FIFO buffer
A port select register (CFIFOSEL, D0FIFOSEL, or D1FIFOSEL) that selects the pipe assigned to the FIFO port
A port control register (CFIFOCTR, D0FIFOCTR, or D1FIFOCTR).
Each FIFO port has the following restrictions:
Access to the FIFO buffer for DCP control transfers is through the CFIFO port
Access to the FIFO buffer for DMA or DTC transfers is through the D0FIFO or D1FIFO port
The D0FIFO and D1FIFO ports can also be accessed by the CPU
When using functions specific to the FIFO port, such as the DMA or DTC transfer function, the pipe number
selected in the CURPIPE[3:0] bits of the Port Select Register cannot be changed
Registers configuring a FIFO port do not affect other FIFO ports
The same pipe must not be assigned to two or more FIFO ports
There are two FIFO buffer states, one giving access rights to the CPU and the other to the serial interface engine
(SIE). When the SIE has access rights, the FIFO buffer cannot be accessed by the CPU.
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28. USB 2.0 Full-Speed Module (USBFS)
FIFOPORT[15:0] bits (FIFO Port)
When the FIFOPORT bit is accessed, the USBFS reads the received data from the FIFO buffer or writes the transmission
data to the FIFO buffer. The FIFO port register can be accessed only when the FRDY bit in the associated port control
register (CFIFOCTR, D0FIFOCTR, or D1FIFOCTR) is 1.
The valid bits in the FIFO port register depend on the MBW and BIGEND settings in the port select register
(CFIFOSEL, D0FIFOSEL, or D1FIFOSEL). See Table 28.5 and Table 28.6.
Table 28.5
Endian operation in 16-bit access
CFIFOSEL.BIGEND bit
D0FIFOSEL.BIGEND bit
D1FIFOSEL.BIGEND bit
Bits [15:8]
Bits [7:0]
0
N + 1 data
N + 0 data
1
N + 0 data
N + 1 data
Table 28.6
Endian operation in 8-bit access
CFIFOSEL.BIGEND bit
D0FIFOSEL.BIGEND bit
D1FIFOSEL.BIGEND bit
Bits [15:8]
Bits [7:0]
0
Access
prohibited*1
N + 0 data
1
Access prohibited*1
N + 0 data
Note 1.
Writing to or reading from these areas is not allowed.
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28.2.5
28. USB 2.0 Full-Speed Module (USBFS)
CFIFO Port Select Register (CFIFOSEL)
D0FIFO Port Select Register (D0FIFOSEL)
D1FIFO Port Select Register (D1FIFOSEL)
CFIFOSEL
Address(es): USBFS.CFIFOSEL 4009 0020h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
RCNT
REW
—
—
—
MBW
—
BIGEN
D
—
—
ISEL
—
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
b3
b2
b1
b0
CURPIPE[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
CURPIPE
[3:0]
CFIFO Port Access Pipe Specification
b3
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
ISEL
CFIFO Port Access Direction When
DCP is Selected
0: Reading from the buffer memory is selected
1: Writing to the buffer memory is selected.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
BIGEND
CFIFO Port Endian Control
0: Little endian
1: Big endian.
R/W
b0
0 0 0 0: No pipe specification
0 0 0 1: Pipe 1
0 0 1 0: Pipe 2
0 0 1 1: Pipe 3
0 1 0 0: Pipe 4
0 1 0 1: Pipe 5
0 1 1 0: Pipe 6
0 1 1 1: Pipe 7
1 0 0 0: Pipe 8
1 0 0 1: Pipe 9.
Other settings are prohibited.
b9
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10
MBW
CFIFO Port Access Bit Width
0: 8-bit width
1: 16-bit width.
R/W
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
REW
Buffer Pointer Rewind
0: The buffer pointer is not rewound
1: The buffer pointer is rewound.
R/W*1
b15
RCNT
Read Count Mode
0: The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0],
D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) are
cleared when all receive data is read from the CFIFO.
In double buffer mode, the DTLN[8:0] bit value is
cleared when all data is read from only a single plane.
1: The DTLN[8:0] bits decrement each time the receive
data is read from the CFIFO.
R/W
Note 1.
Only 0 can be read.
Do not specify the same pipe number in the CURPIPE[3:0] bits in the CFIFOSEL, D0FIFOSEL, and D1FIFOSEL
registers. When the CURPIPE[3:0] bits in the D0FIFOSEL and D1FIFOSEL registers are set to 0000b, no pipe is
selected.
Do not change the pipe number while DMA or DTC transfer is enabled.
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28. USB 2.0 Full-Speed Module (USBFS)
CURPIPE[3:0] bits (CFIFO Port Access Pipe Specification)
The CURPIPE[3:0] bits specify the pipe number used to read or write data through the CFIFO port. After writing to these
bits, read them to check that the written value agrees with the read value before proceeding to the next process.
Do not set the same pipe number to the CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL.
During FIFO buffer access, the current pipe specification is maintained until the access is complete, even if software
attempts to change the CURPIPE[3:0] setting. Access continues after the current value is written back to the
CURPIPE[3:0] bits.
ISEL bit (CFIFO Port Access Direction When DCP is Selected)
After writing a new value to the ISEL bit with the DCP as the selected pipe, read this bit to check that the written value
agrees with the read value before proceeding to the next process. Set the ISEL bit and the CURPIPE[3:0] bits
simultaneously.
MBW bit (CFIFO Port Access Bit Width)
The MBW bit specifies the bit width for accessing the CFIFO port.
When the selected pipe is receiving, set the CURPIPE[3:0] bits and MBW bits simultaneously. After a write to these bits
starts a data read from the FIFO buffer, do not change the bits until all of the data is read. When you read the FIFO buffer,
read with the access size that is set in the MBW bit.
When the selected pipe is transmitting, the bit width cannot be changed from 8-bit width to 16-bit width while data is
being written to the buffer memory.
An odd number of bytes can also be written through byte-access control even when 16-bit width is selected.
REW bit (Buffer Pointer Rewind)
The REW bit specifies whether to rewind the buffer pointer.
When the selected pipe is receiving, setting this bit to 1 while the FIFO buffer is being read allows re-reading of the FIFO
buffer from the first data. In double buffering, this setting enables re-reading of the currently-read FIFO buffer plane
from the first entry.
Do not set this bit to 1 while simultaneously changing the CURPIPE[3:0] bits. Before setting the REW bit to 1, be sure to
check that the FRDY bit is 1.
To rewrite to the FIFO buffer from the first data for the transmitting pipe, use the BCLR bit.
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28. USB 2.0 Full-Speed Module (USBFS)
D0FIFOSEL, D1FIFOSEL
Address(es): USBFS.D0FIFOSEL 4009 0028h, USBFS.D1FIFOSEL 4009 002Ch
b15
RCNT
Value after reset:
0
b14
b13
b12
REW DCLRM DREQE
0
0
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
0
0
0
0
—
MBW
—
BIGEN
D
0
0
0
0
0
b3
b2
b1
b0
CURPIPE[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
CURPIPE
[3:0]
FIFO Port Access Pipe
Specification
b3
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
BIGEND
FIFO Port Endian Control
0: Little endian
1: Big endian.
R/W
b9
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10
MBW
FIFO Port Access Bit Width
0: 8-bit width
1: 16-bit width.
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b12
DREQE
DMA/DTC Transfer Request
Enable
0: DMA/DTC transfer request is disabled
1: DMA/DTC transfer request is enabled.
R/W
b13
DCLRM
Auto Buffer Memory Clear
Mode Accessed after
Specified Pipe Data is Read
0: Auto buffer clear mode is disabled
1: Auto buffer clear mode is enabled.
R/W
b14
REW
Buffer Pointer Rewind
0: The buffer pointer is not rewound
1: The buffer pointer is rewound.
R/W*1
b15
RCNT
Read Count Mode
0: DTLN[8:0] bits (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0],
D1FIFOCTR.DTLN[8:0]) cleared when all receive data is read
from DnFIFO.
In double buffer mode, the DTLN bit Value is cleared when all data
is read from only a single plane.
1: DTLN[8:0] bits decrement each time receive data is read from
DnFIFO.
n = 0, 1
R/W
Note 1.
b0
0 0 0 0: No pipe specification
0 0 0 1: Pipe 1
0 0 1 0: Pipe 2
0 0 1 1: Pipe 3
0 1 0 0: Pipe 4
0 1 0 1: Pipe 5
0 1 1 0: Pipe 6
0 1 1 1: Pipe 7
1 0 0 0: Pipe 8
1 0 0 1: Pipe 9.
Other settings are prohibited.
Only 0 can be read.
The same pipe must not be specified in the CURPIPE[3:0] bits in the CFIFOSEL, D0FIFOSEL, and D1FIFOSEL
registers. When the CURPIPE[3:0] bits in the D0FIFOSEL and D1FIFOSEL registers are set to 0000b, no pipe is
selected. The pipe number must not be changed while DMA or DTC transfer is enabled.
CURPIPE[3:0] bits (FIFO Port Access Pipe Specification)
The CURPIPE[3:0] bits specify the pipe number used to read or write data through the D0FIFO port or D1FIFO port.
After writing to these bits, read them to check that the written value agrees with the read value before proceeding to the
next process. Do not set the same pipe number to the CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL.
During FIFO buffer access, the current pipe specification is maintained until the access is complete, even if software
attempts to change the CURPIPE[3:0] setting. Access continues after the current value is written back to the
CURPIPE[3:0] bits.
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28. USB 2.0 Full-Speed Module (USBFS)
MBW bit (FIFO Port Access Bit Width)
The MBW bit specifies the bit width for accessing the D0FIFO port or D1FIFO port.
When the selected pipe is receiving, after a write to these bits starts a data read from the FIFO buffer, do not change the
bits until all of the data is read. When you read the FIFO buffer, read with the access size which is set in MBW bit. Set
the CURPIPE[3:0] bits and the MBW bit simultaneously.
When the selected pipe is transmitting, the bit width cannot be changed from 8-bit width to 16-bit width while data is
being written to the FIFO memory.
An odd number of bytes can also be written through byte-access control even when 16-bit width is selected.
DREQE bit (DMA/DTC Transfer Request Enable)
The DREQE bit enables or disables issuing of DMA or DTC transfer requests. To enable DMA or DTC transfer requests,
set this bit to 1 after setting the CURPIPE[3:0] bits. To change the CURPIPE[3:0] setting, first set this bit to 0.
DCLRM bit (Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read)
The DCLRM bit enables or disables automatic FIFO buffer clearing after data in the selected pipe is read.
When this bit is set to 1, on receiving a zero-length packet while the FIFO buffer assigned to the selected pipe is empty,
or when reading of a received short packet is complete while the PIPECFG.BFRE bit is 1, the USBFS sets the BCLR bit
in the FIFO Port Control Register to 1.
When using the USBFS with the SOFCFG.BRDYM bit set to 1, set this bit to 0.
REW bit (Buffer Pointer Rewind)
The REW bit specifies whether to rewind the buffer pointer.
When the selected pipe is receiving, setting this bit to 1 while the FIFO buffer is being read allows re-reading of the FIFO
buffer from the first data. In double buffering, this setting enables re-reading of the currently-read FIFO buffer plane
from the first entry.
Do not set this bit to 1 while simultaneously changing the CURPIPE[3:0] bits. Before setting this bit to 1, always check
that the FRDY bit is 1.
To rewrite to the FIFO buffer from the first data for the transmitting pipe, use the BCLR bit.
RCNT bit (Read Count Mode)
The RCNT bit specifies the read mode for the value in the CFIFOCTR.DTLN bit. When accessing DnFIFO with the
PIPECFG.BFRE bit set to 1, set the RCNT bit to 0.
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28.2.6
28. USB 2.0 Full-Speed Module (USBFS)
CFIFO Port Control Register (CFIFOCTR)
D0FIFO Port Control Register (D0FIFOCTR)
D1FIFO Port Control Register (D1FIFOCTR)
Address(es): USBFS.CFIFOCTR 4009 0022h, USBFS.D0FIFOCTR 4009 002Ah, USBFS.D1FIFOCTR 4009 002Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
BVAL
BCLR
FRDY
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
DTLN[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
DTLN[8:0]
Receive Data Length
Indicates the receive data length.
The meaning of the values differs depending on the RCNT bit setting
in the port select register. For details, see the description of the
DTLN[8:0] bits.
R
b12 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13
FRDY
FIFO Port Ready
0: FIFO port access disabled
1: FIFO port access enabled.
R
b14
BCLR
CPU Buffer Clear
0: Does not operate
1: FIFO buffer cleared on the CPU side.
R/W*1
b15
BVAL
Buffer Memory Valid Flag
0: Invalid
1: Writing ended.
R/W
Note 1.
Only 0 can be read.
The CFIFOCTR, D0FIFOCTR, and D1FIFOCTR registers correspond to the CFIFO, D0FIFO, and D1FIFO buffers.
DTLN[8:0] bits (Receive Data Length)
The DTLN[8:0] bits indicate the length of the receive data.
While the FIFO buffer is being read, the DTLN[8:0] bits indicate different values depending on the DnFIFOSEL.RCNT
bit (n = 0, 1), as follows:
RCNT = 0
The USBFS sets the DTLN[8:0] bits to indicate the length of the receive data until the CPU or DMA/DTC has read
all of the received data from a single FIFO buffer plane.
While the PIPECFG.BFRE bit = 1, the USB retains the length of the receive data until the BCLR bit is set to 1, even
after all the data is read.
RCNT = 1
The USBFS decrements the value indicated by the DTLN[8:0] bits each time data is read from the FIFO buffer. The
value is decremented by 1 when the MBW bit is 0, and by 2 when the MBW bit is 1.
The USBFS sets these bits to 0 when all the data is read from one FIFO buffer plane. In double buffer mode, if data
is received in one FIFO buffer plane before all the data is read from the other plane, the USBFS sets these bits to
indicate the length of the receive data in the former plane when all of the data is read from the latter plane.
FRDY bit (FIFO Port Ready)
The FRDY bit indicates whether the FIFO port can be accessed by the CPU or DMA/DTC.
In the following cases, the USBFS sets the FRDY bit to 1 but data cannot be read through the FIFO port because there is
no data to be read:
A zero-length packet is received when the FIFO buffer assigned to the selected pipe is empty
A short packet is received and the data is completely read while the PIPECFG.BFRE bit = 1.
In these cases, set the BCLR bit to 1 to clear the FIFO buffer, and enable transmission and reception of the next data.
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28. USB 2.0 Full-Speed Module (USBFS)
BCLR bit (CPU Buffer Clear)
Set the BCLR bit to 1 to clear the FIFO buffer on the CPU side for the selected pipe.
When double buffer mode is set for the FIFO buffer assigned to the selected pipe, the USBFS clears only one plane of the
FIFO buffer even when both planes are read-enabled.
When the DCP is the selected pipe, setting the BCLR bit to 1 allows the USBFS to clear the FIFO buffer regardless of
whether the CPU or SIE has access rights. To clear the buffer when the SIE has access rights, set the DCPCTR.PID[1:0]
bits to 00b (NAK response) before setting the BCLR bit to 1.
When the selected pipe is transmitting, if 1 is written to the BVAL flag and the BCLR bit simultaneously, the USBFS
clears the data that is already written, enabling transmission of a zero-length packet.
When the selected pipe is not the DCP, only write 1 to the BCLR bit while the FRDY bit in the FIFO Port Control
Register is 1 (set by the USBFS).
BVAL flag (Buffer Memory Valid Flag)
Set the BVAL flag to 1 when data is completely written to the FIFO buffer on the CPU side for the pipe selected in
CURPIPE[3:0].
When the selected pipe is transmitting, set this flag to 1 in the following cases:
To transmit a short packet, set this flag to 1 after data is written
To transmit a zero-length packet, set this flag to 1 before data is written to the FIFO buffer.
The USBFS switches the FIFO buffer from the CPU to the SIE, enabling transmission.
When data of the maximum packet size is written for the pipe in continuous transfer mode, the USBFS sets the BVAL
flag to 1 and switches the FIFO buffer from the CPU to the SIE, enabling transmission.
Only write 1 to the BVAL flag while the FRDY bit is 1 (set by the USBFS). When the selected pipe is receiving, do not
set the BVAL flag to 1.
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28.2.7
28. USB 2.0 Full-Speed Module (USBFS)
Interrupt Enable Register 0 (INTENB0)
Address(es): USBFS.INTENB0 4009 0030h
b15
b14
b13
b12
VBSE
RSME
SOFE
DVSE
0
0
0
0
Value after reset:
b11
b10
b9
b8
CTRE BEMPE NRDYE BRDYE
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
These bits are read as 0. The write value
should be 0.
R/W
b8
BRDYE
Buffer Ready Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b9
NRDYE
Buffer Not Ready Response Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b10
BEMPE
Buffer Empty Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b11
CTRE
Control Transfer Stage Transition Interrupt
Enable*1
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b12
DVSE
Device State Transition Interrupt Enable*1
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b13
SOFE
Frame Number Update Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b14
RSME
Resume Interrupt Enable*1
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b15
VBSE
VBUS Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
Note 1.
The RSME, DVSE, and CTRE bits can only be set to 1 in device controller mode. Do not set these bits to 1 in host controller
mode.
When a status flag in the INTSTS0 register sets to 1 and the associated interrupt request enable bit setting in the
INTENB0 register is 1, the USBFS issues a USBFS interrupt request.
Regardless of the INTENB0 register setting, the status flag in the INTSTS0 register sets to 1 in response to a state change
that satisfies the associated condition.
When an interrupt request enable bit in the INTENB0 register is switched from 0 to 1 while the associated status flag in
the INTSTS0 register is set to 1, a USBFS interrupt is requested.
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28.2.8
28. USB 2.0 Full-Speed Module (USBFS)
Interrupt Enable Register 1 (INTENB1)
Address(es): USBFS.INTENB1 4009 0032h
b15
b14
OVRC BCHGE
RE
Value after reset:
0
0
b13
—
b12
b11
DTCHE ATTCH
E
0
0
0
b10
b9
b8
b7
—
—
—
—
0
0
0
0
b6
b5
b4
EOFER SIGNE SACKE
RE
0
0
0
b3
b2
b1
b0
—
—
—
PDDET
INTE0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PDDETINTE0
PDDETINT0 Detection Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
SACKE
Setup Transaction Normal Response
Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b5
SIGNE
Setup Transaction Error Interrupt
Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b6
EOFERRE
EOF Error Detection Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b10 to b7
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b11
ATTCHE
Connection Detection Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b12
DTCHE
Disconnection Detection Interrupt
Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b13
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b14
BCHGE
USB Bus Change Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b15
OVRCRE
Overcurrent Input Change Interrupt
Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
Note:
The bits in INTENB1 can only be set to 1 in host controller mode. Do not set these bits to 1 in device controller mode.
INTENB1 specifies the interrupt masks in host controller mode and for the setup transaction.
When a status flag in the INTSTS1 register sets to 1 and the associated interrupt request enable bit setting in the
INTENB1 register is 1, the USBFS issues a USBFS interrupt request.
Regardless of the INTENB1 register setting, the status flag in the INTSTS1 register sets to 1 in response to a state change
that satisfies the associated condition.
When an interrupt request enable bit in the INTENB1 register is switched from 0 to 1 while the associated status flag in
the INTSTS1 register is set to 1, a USBFS interrupt is requested.
Do not enable interrupts in device controller mode.
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28.2.9
28. USB 2.0 Full-Speed Module (USBFS)
BRDY Interrupt Enable Register (BRDYENB)
Address(es): USBFS.BRDYENB 4009 0036h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B
RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BRDYE
BRDY Interrupt Enable for Pipe 0
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b1
PIPE1BRDYE
BRDY Interrupt Enable for Pipe 1
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b2
PIPE2BRDYE
BRDY Interrupt Enable for Pipe 2
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b3
PIPE3BRDYE
BRDY Interrupt Enable for Pipe 3
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b4
PIPE4BRDYE
BRDY Interrupt Enable for Pipe 4
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b5
PIPE5BRDYE
BRDY Interrupt Enable for Pipe 5
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b6
PIPE6BRDYE
BRDY Interrupt Enable for Pipe 6
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b7
PIPE7BRDYE
BRDY Interrupt Enable for Pipe 7
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b8
PIPE8BRDYE
BRDY Interrupt Enable for Pipe 8
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b9
PIPE9BRDYE
BRDY Interrupt Enable for Pipe 9
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
The BRDYENB register enables or disables the INTSTS0.BRDY bit to be set to 1 when the BRDY interrupt is detected
for each pipe.
When a status flag in the BRDYSTS register sets to 1 and the associated PIPEnBRDYE bit (n = 0 to 9) setting in the
BRDYENB register is 1, the INTSTS0.BRDY flag sets to 1. In this case, if the BRDYE bit in INTENB0 is 1, the USBFS
generates a BRDY interrupt request. While at least one PIPEnBRDY bit indicates 1, the USBFS generates the BRDY
interrupt request when the associated interrupt request enable bit in the BRDYENB register is changed from 0 to 1 by
software.
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28.2.10
28. USB 2.0 Full-Speed Module (USBFS)
NRDY Interrupt Enable Register (NRDYENB)
Address(es): USBFS.NRDYENB 4009 0038h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9N PIPE8N PIPE7N PIPE6N PIPE5N PIPE4N PIPE3N PIPE2N PIPE1N PIPE0N
RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0NRDYE
NRDY Interrupt Enable for Pipe 0
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b1
PIPE1NRDYE
NRDY Interrupt Enable for Pipe 1
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b2
PIPE2NRDYE
NRDY Interrupt Enable for Pipe 2
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b3
PIPE3NRDYE
NRDY Interrupt Enable for Pipe 3
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b4
PIPE4NRDYE
NRDY Interrupt Enable for Pipe 4
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b5
PIPE5NRDYE
NRDY Interrupt Enable for Pipe 5
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b6
PIPE6NRDYE
NRDY Interrupt Enable for Pipe 6
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b7
PIPE7NRDYE
NRDY Interrupt Enable for Pipe 7
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b8
PIPE8NRDYE
NRDY Interrupt Enable for Pipe 8
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b9
PIPE9NRDYE
NRDY Interrupt Enable for Pipe 9
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
NRDYENB enables or disables the INTSTS0.NRDY bit to be set to 1 when the NRDY interrupt is detected for each
pipe.
When a status flag in the NRDYSTS register sets to 1 and the associated PIPEnNRDYE (n = 0 to 9) bit setting in the
NRDYENB register is 1, the INTSTS0.NRDY flag sets to 1. In this case, if the NRDYE bit in INTENB0 is 1, the USBFS
generates a NRDY interrupt request. While at least one PIPEnNRDY bit indicates 1, the USBFS generates the NRDY
interrupt request when the associated interrupt request enable bit in the NRDYENB register is changed from 0 to 1 by
software.
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28.2.11
28. USB 2.0 Full-Speed Module (USBFS)
BEMP Interrupt Enable Register (BEMPENB)
Address(es): USBFS.BEMPENB 4009 003Ah
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B
EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BEMPE
BEMP Interrupt Enable for Pipe 0
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b1
PIPE1BEMPE
BEMP Interrupt Enable for Pipe 1
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b2
PIPE2BEMPE
BEMP Interrupt Enable for Pipe 2
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b3
PIPE3BEMPE
BEMP Interrupt Enable for Pipe 3
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b4
PIPE4BEMPE
BEMP Interrupt Enable for Pipe 4
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b5
PIPE5BEMPE
BEMP Interrupt Enable for Pipe 5
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b6
PIPE6BEMPE
BEMP Interrupt Enable for Pipe 6
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b7
PIPE7BEMPE
BEMP Interrupt Enable for Pipe 7
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b8
PIPE8BEMPE
BEMP Interrupt Enable for Pipe 8
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b9
PIPE9BEMPE
BEMP Interrupt Enable for Pipe 9
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
The BEMPENB register enables or disables the INTSTS0.BEMP bit to be set to 1 when the BEMP interrupt is detected
for each pipe.
When a status flag in the BEMPSTS register sets to 1 and the associated PIPEnBEMPE (n = 0 to 9) bit setting in the
BEMPENB register is 1, the INTSTS0.BEMP flag sets to 1. In this case, if the BEMPE bit in INTENB0 is 1, the USBFS
generates a BEMP interrupt request. While at least one PIPEnBEMP bit indicates 1, the USBFS generates the BEMP
interrupt request when the associated interrupt request enable bit in the BEMPENB register is changed from 0 to 1 by
software.
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28.2.12
28. USB 2.0 Full-Speed Module (USBFS)
SOF Output Configuration Register (SOFCFG)
Address(es): USBFS.SOFCFG 4009 003Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
TRNEN
SEL
—
BRDY
M
—
EDGES
TS
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
EDGESTS
Edge Interrupt Output Status Monitor*1
Indicates 1 during the edge processing of an edge
interrupt output signal
R
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
BRDYM
BRDY Interrupt Status Clear Timing
0: BRDY flag cleared by software
1: BRDY flag cleared by the USBFS through a data
read from the FIFO buffer or data write to the FIFO
buffer.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
0: Not low-speed communication
1: Low-speed communication.
R/W
These bits are read as 0. The write value should be 0.
R/W
b8
TRNENSEL
Transaction-Enabled Time
b15 to b9
—
Reserved
Note 1.
Select*1
R/W
Confirm that these bits are 0 before stopping the clock supply to the USBFS.
EDGESTS bit (Edge Interrupt Output Status Monitor)
The EDGESTS bit indicates 1 during the edge processing of an edge interrupt output signal. Confirm that this bit is 0
before stopping the clock supply to the USBFS.
BRDYM bit (BRDY Interrupt Status Clear Timing)
The BRDYM bit specifies how the BRDY interrupt status flags for the pipes are cleared.
TRNENSEL bit (Transaction-Enabled Time Select)
When the USB port is in use for full- or low-speed communications, the TRNENSEL bit specifies the timing with which
the USBFS issues tokens in a frame (transaction-enabled time).
Set this bit to 1 when a low-speed device is connected. The bit is only valid in host controller mode. Set this bit to 0 in
device controller mode.
28.2.13
Interrupt Status Register 0 (INTSTS0)
Address(es): USBFS.INTSTS0 4009 0040h
b15
b14
VBINT RESM
Value after reset:
0
0
b13
b12
b11
b10
b9
SOFR
DVST
CTRT
BEMP
NRDY
0
0/1*1
0
0
0
b8
b7
b6
BRDY VBSTS
0
0*2
b5
b4
DVSQ[2:0]
0*3
0*3
b3
b2
VALID
0/1*3
0
b1
b0
CTSQ[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CTSQ[2:0]
Control Transfer Stage
b2
R
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b0
0 0 0: Idle or setup stage
0 0 1: Control read data stage
0 1 0: Control read status stage
0 1 1: Control write data stage
1 0 0: Control write status stage
1 0 1: Control write (no data) status stage
1 1 0: Control transfer sequence error.
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28. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b3
VALID
USB Request Reception
0: Setup packet is not received
1: Setup packet is received.
R/W*4
b6 to b4
DVSQ[2:0]
Device State
b6
R
b7
VBSTS
VBUS Input Status
0: USB_VBUS pin is low
1: USB_VBUS pin is high.
R
b8
BRDY
Buffer Ready Interrupt Status
0: BRDY interrupts are not generated
1: BRDY interrupts are generated.
R
b9
NRDY
Buffer Not Ready Interrupt
Status
0: NRDY interrupts are not generated
1: NRDY interrupts are generated.
R
b10
BEMP
Buffer Empty Interrupt Status
0: BEMP interrupts are not generated
1: BEMP interrupts are generated.
R
b11
CTRT
Control Transfer Stage
Transition Interrupt Status *5
0: Control transfer stage transition interrupts are not generated
1: Control transfer stage transition interrupts are generated.
R/W*4
b12
DVST
Device State Transition
Interrupt Status *5
0: Device state transition interrupts are not generated
1: Device state transition interrupts are generated.
R/W*4
b13
SOFR
Frame Number Refresh
Interrupt Status
0: SOF interrupts are not generated
1: SOF interrupts are generated.
R/W*4
b14
RESM
Resume Interrupt Status *5, *6
0: Resume interrupts are not generated
1: Resume interrupts are generated.
R/W*4
b15
VBINT
VBUS Interrupt Status *6
0: VBUS interrupts are not generated
1: VBUS interrupts are generated.
R/W*4
b4
0 0 0: Powered state
0 0 1: Default state
0 1 0: Address state
0 1 1: Configured state
1 x x: Suspended state.
x: Don’t care
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
The value is 0 when the MCU is reset and 1 after a USB bus reset.
The value is 1 when the USB_VBUS pin is high and 0 when the USB_VBUS pin is low.
The value is 000b when the MCU is reset and 001b after a USB bus reset.
To clear the VBINT, RESM, SOFR, DVST, CTRT, or VALID bits, write 0 only to the bits to be cleared. Write 1 to the other bits.
Do not write 0 to the status bits indicating 0.
The status of the RESM, DVST, and CTRT bits are changed only in device controller mode. Set the associated interrupt enable
bits to 0 (disabled) in host controller mode.
The USBFS detects a change in the status indicated by the VBINT and RESM bits even while the clock supply is stopped
(SCKE bit = 0), and it requests the interrupt when the associated interrupt request bit is 1. Enable the clock supply before
clearing the status by software.
CTSQ[2:0] bits (Control Transfer Stage)
In host controller mode, the read value of the CTSQ[2:0] bits is invalid.
VALID bit (USB Request Reception)
In host controller mode, the read value of the VALID bit is invalid.
DVSQ[2:0] bits (Device State)
The DVSQ[2:0] bits are initialized by a USB bus reset. In host controller mode, the read value is invalid.
BRDY bit (Buffer Ready Interrupt Status)
The BRDY bit indicates the BRDY interrupt status.
The USBFS sets the BRDY bit to 1 when it detects a BRDY interrupt status (PIPEnBRDY = 1, n = 0 to 9) on at least one
pipe for which BRDY interrupts are enabled (BRDYENB.PIPEnBRDYE = 1).
For the conditions that cause the PIPEnBRDY status to be asserted, see section 28.3.3.1, BRDY interrupt.
The USBFS sets the BRDY bit to 0 when software writes 0 to all the PIPEnBRDY bits associated with the
PIPEnBRDYE bits that are set to 1. Writing 0 to the BRDY bit in software does not clear the bit.
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28. USB 2.0 Full-Speed Module (USBFS)
NRDY bit (Buffer Not Ready Interrupt Status)
The NRDY bit indicates the NRDY interrupt status.
The USBFS sets the NRDY bit to 1 when it detects a NRDY interrupt status (PIPEnNRDY = 1, n = 0 to 9) on at least one
pipe for which NRDY interrupts are enabled (NRDYENB.PIPEnNRDYE = 1).
For the conditions that cause the PIPEnNRDY status to be asserted, see section 28.3.3.2, NRDY interrupt.
The USBFS sets the NRDY bit to 0 when software writes 0 to all the PIPEnNRDY bits associated with the
PIPEnNRDYE bits that are set to 1. Writing 0 to the NRDY bit in software does not clear the bit.
BEMP bit (Buffer Empty Interrupt Status)
The BEMP bit indicates the BEMP interrupt status.
The USBFS sets the BEMP bit to 1 when it detects a BEMP interrupt status (PIPEnBEMP = 1, n = 0 to 9) on at least one
pipe for which BEMP interrupts are enabled (BEMPENB.PIPEnBEMPE = 1).
For the conditions that cause the PIPEnBEMP status to be asserted, see section 28.3.3.3, BEMP interrupt.
The USBFS sets the BEMP bit to 0 when software writes 0 to all of the PIPEnBEMP bits associated with the
PIPEnBEMPE bits that are set to 1. Writing 0 to the BEMP bit in software does not clear the bit.
CTRT bit (Control Transfer Stage Transition Interrupt Status)
In device controller mode, the USBFS updates the value of the CTSQ[2:0] bits and sets the CTRT bit to 1 on detecting a
transition in the control transfer stage. When a control transfer stage transition interrupt is generated, clear the CTRT bit
before the USBFS detects the next control transfer stage transition.
Values read from the CTRT bit in host controller mode are invalid.
DVST bit (Device State Transition Interrupt Status)
In device controller mode, the USBFS updates the value of the DVSQ[2:0] bits and sets the DVST bit to 1 on detecting a
change in the device state. When a device state transition interrupt is generated, clear the DVST bit before the USBFS
detects the next device state transition.
Values read from the DVST bit in host controller mode are invalid.
SOFR bit (Frame Number Refresh Interrupt Status)
In host controller mode, the USBFS sets the SOFR bit to 1 on updating the frame number when the DVSTCTR0.UACT
bit has been set to 1 by software. An SOFR interrupt is detected every 1 ms.
In device controller mode, the USBFS sets the SOFR bit to 1 on updating the frame number. A frame number refresh
interrupt is detected every 1 ms.
The USBFS can detect an SOFR interrupt through the internal interpolation function even when a corrupted SOF packet
is received from the USB host.
RESM bit (Resume Interrupt Status)
In device controller mode, the USBFS sets the RESM bit to 1 on detecting the falling edge of the signal on the USB_DP
pin in the suspended state (DVSQ[2:0] = 1xxb). Values read from the RESM bit in host controller mode are invalid.
VBINT bit (VBUS Interrupt Status)
The USBFS sets the VBINT bit to 1 on detecting a level change (high to low or low to high) in the USB_VBUS pin input
value. The USBFS sets the VBSTS bit to indicate the USB_VBUS pin input value. When a VBUS interrupt is generated,
eliminate transient elements by reading the VBSTS flag at least three times through software processing and check that
the values read are the same.
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28.2.14
28. USB 2.0 Full-Speed Module (USBFS)
Interrupt Status Register 1 (INTSTS1)
Address(es): USBFS.INTSTS1 4009 0042h
b15
b14
OVRC BCHG
R
Value after reset:
0
0
b13
—
0
b12
b11
DTCH ATTCH
0
0
b10
b9
b8
b7
—
—
—
—
0
0
0
0
b6
b5
EOFER SIGN
R
0
0
b4
b3
b2
b1
b0
SACK
—
—
—
PDDET
INT0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PDDETINT0
PDDET0 Detection Interrupt Status
0: PDDET0 detection interrupts are not generated
1: PDDET0 detection interrupts are generated.
R/W
*1
b3 to b1
—
Reserved
These bits are read as 0. The write value should
be 0.
R/W
b4
SACK
Setup Transaction Normal Response
Interrupt Status
0: SACK interrupts are not generated
1: SACK interrupts are generated.
R/W
*1
b5
SIGN
Setup Transaction Error Interrupt Status
0: SIGN interrupts are not generated
1: SIGN interrupts are generated.
R/W
*1
b6
EOFERR
EOF Error Detection Interrupt Status
0: EOFERR interrupts are not generated
1: EOFERR interrupts are generated.
R/W
*1
b10 to b7
—
Reserved
These bits are read as 0. The write value should
be 0.
R/W
b11
ATTCH
ATTCH Interrupt Status
0: ATTCH interrupts are not generated
1: ATTCH interrupts are generated.
R/W
*1
b12
DTCH
USB Disconnection Detection Interrupt
Status
0: DTCH interrupts are not generated.
1: DTCH interrupts are generated.
R/W
*1
b13
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b14
BCHG
USB Bus Change Interrupt Status*2
0: BCHG interrupts are not generated
1: BCHG interrupts are generated.
R/W
*1
b15
OVRCR
Overcurrent Input Change Interrupt
Status*2
0: OVRCR interrupts are not generated
1: OVRCR interrupts are generated.
R/W
*1
Note 1.
Note 2.
To clear the bits in INTSTS1, write 0 only to the bits to be cleared. Write 1 to the other bits.
The USBFS detects a change in the status in the OVRCR or BCHG bit even when the clock supply is stopped (SYSCFG.SCKE
= 0), and it requests the interrupt when the associated interrupt request bit is 1. Enable the clock supply (SYSCFG.SCKE = 1)
before clearing the status through software. No other interrupts can be detected while the clock supply is stopped
(SYSCFG.SCKE bit = 0).
INTSTS1 is used to confirm the status of each interrupt in host controller mode. Only enable the status change interrupts
indicated in the bits in INTSTS1 in host controller mode.
PDDETINTE0 bit (PDDET0 Detection Interrupt Status)
The PDDETINT0 bit indicates the status of the portable device detection interrupt in host controller mode. This bit is set
to 1 when the USBFS detects a level change (high to low or low to high) in the input value to the VDPDET pin of the
USB physical layer transceiver (PHY). The USBFS sets the PDDETSTS0 bit to indicate the VDPDET input value. When
the PDDETINT interrupt is generated, eliminate transient elements by reading the PDDETSTS0 bit at least three times
through software processing and check that the values read are the same.
SACK bit (Setup Transaction Normal Response Interrupt Status)
The SACK bit indicates the status of the setup transaction normal response interrupt in host controller mode.
The USBFS detects the SACK interrupt and sets this bit to 1 when an ACK response is returned from the peripheral
device during the setup transactions issued by the USBFS. If the associated interrupt enable bit is set to 1 by software, the
USBFS generates the interrupt.
Values read from the SACK bit in device controller mode are invalid.
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28. USB 2.0 Full-Speed Module (USBFS)
SIGN bit (Setup Transaction Error Interrupt Status)
The SIGN bit indicates the status of the setup transaction error interrupt in host controller mode.
The USBFS detects the SIGN interrupt and sets this bit to 1 when an ACK response is not returned from the peripheral
device three consecutive times during the setup transactions issued by the USBFS. If the associated interrupt enable bit is
set to 1 by software, the USBFS generates the interrupt.
The USBFS detects the SIGN interrupt when any of the following response conditions occur for three consecutive setup
transactions:
Timeout is detected by the USBFS when the peripheral device has returned no response
A corrupted ACK packet is received
A handshake other than ACK (NAK, NYET, or STALL) is received.
Values read from the SIGN bit in device controller mode are invalid.
EOFERR bit (EOF Error Detection Interrupt Status)
The EOFERR bit indicates the status of the EOFERR interrupt in host controller mode.
The USBFS detects the EOFERR interrupt and sets this bit to 1 on detecting that communication did not complete at the
EOF2 timing defined in the USB 2.0 specification. If the associated interrupt enable bit is set to 1 by software, the
USBFS generates the interrupt.
After detecting the EOFERR interrupt, the USBFS controls the hardware as follows, regardless of the associated
interrupt enable bit setting:
Sets the DVSTCTR0.UACT bit for the port in which the EOFERR interrupt was detected to 0
Puts the port in which the EOFERR interrupt occurred into the idle state.
Software must terminate all pipes in which communications are currently being carried out and re-enumerate the USB
port. Values read from the EOFERR bit in device controller mode are invalid.
ATTCH bit (ATTCH Interrupt Status)
The ATTCH bit indicates the status of USB attach detection interrupts in host controller mode.
The USBFS detects the ATTCH interrupt and sets this bit to 1 on detecting a J- or K-state on the full- or low-speed signal
level for 2.5 μs. If the associated interrupt enable bit is set to 1 by software, the USBFS generates the interrupt.
The USBFS detects the ATTCH interrupt on any of the following conditions:
K-state, SE0, or SE1 changes to J-state, and J-state continues for 2.5 µs
J-state, SE0, or SE1 changes to K-state, and K-state continues for 2.5 µs.
Values read from the ATTCH bit in device controller mode are invalid.
DTCH bit (USB Disconnection Detection Interrupt Status)
The DTCH bit indicates the status of USB disconnection detection interrupts in host controller mode.
The USBFS detects the DTCH interrupt and sets this bit to 1 on detecting a USB bus detach event. If the associated
interrupt enable bit is set to 1 by software, the USBFS generates the interrupt.
The USBFS detects bus detach events based on the USB 2.0 specification.
After detecting the DTCH interrupt, the USBFS controls hardware as follows, regardless of the associated interrupt
enable bit setting:
Sets the DVSTCTR0.UACT bit for the port in which the DTCH interrupt was detected to 0
Puts the port in which the DTCH interrupt occurred into the idle state.
Software must terminate all pipes in which communications are currently being carried out and invoke the wait state for
attaching to the USB port (waiting for ATTCH interrupt generation).
Values read from the DTCH flag in device controller mode are invalid.
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28. USB 2.0 Full-Speed Module (USBFS)
BCHG bit (USB Bus Change Interrupt Status)
The BCHG bit indicates the status of USB bus change interrupts in host controller mode.
The USBFS detects the BCHG interrupt and sets this bit to 1 when a change in the full- speed or low-speed signal level
occurs on the USB port. This includes any change from J-state, K-state, or SE0 to J-state, K-state, or SE0. If the
associated interrupt enable bit is set to 1 by software, the USBFS generates the interrupt.
The USBFS sets the LNST[1:0] bits to indicate the current input state of the USB port. When a BCHG interrupt is
generated, eliminate transient elements by repeat reading the LNST[1:0] bits through software until the same value is
read at least three times.
Change in the USB bus state can be detected while the internal clock is stopped.
Values read from the BCHG flag in device controller mode are invalid.
OVRCR bit (Overcurrent Input Change Interrupt Status)
The OVRCR bit indicates the status of the USB_OVRCURA and USB_OVRCURB input pin change interrupts.
The USBFS detects the OVRCR interrupt and sets this bit to 1 when a change (high to low or low to high) occurs in at
least one of the input values to the USB_OVRCURA and USB_OVRCURB pins. If the associated interrupt enable bit is
set to 1 by software, the USBFS generates the interrupt.
28.2.15
BRDY Interrupt Status Register (BRDYSTS)
Address(es): USBFS.BRDYSTS 4009 0046h
Value after reset:
Bit
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
Symbol
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
0
Bit name
0
0
0
0
0
0
0
0
0
Description
R/W
0*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b0
PIPE0BRDY
BRDY Interrupt Status for Pipe
b1
PIPE1BRDY
BRDY Interrupt Status for Pipe 1*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b2
PIPE2BRDY
BRDY Interrupt Status for Pipe 2*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b3
PIPE3BRDY
BRDY Interrupt Status for Pipe 3*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b4
PIPE4BRDY
BRDY Interrupt Status for Pipe 4*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b5
PIPE5BRDY
BRDY Interrupt Status for Pipe 5*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b6
PIPE6BRDY
BRDY Interrupt Status for Pipe 6*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b7
PIPE7BRDY
BRDY Interrupt Status for Pipe 7*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b8
PIPE8BRDY
BRDY Interrupt Status for Pipe 8*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b9
PIPE9BRDY
BRDY Interrupt Status for Pipe 9*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
Reserved
These bits are read as 0. The write value should be 0. R/W
b15 to b10 —
Note 1.
Note 2.
When the SOFCFG.BRDYM bit is set to 0, to clear the status indicated in the bits in BRDYSTS, write 0 only to the bits to be
cleared. Write 1 to the other bits.
When the SOFCFG.BRDYM bit is set to 0, clear the BRDY interrupts before accessing the FIFO.
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28.2.16
28. USB 2.0 Full-Speed Module (USBFS)
NRDY Interrupt Status Register (NRDYSTS)
Address(es): USBFS.NRDYSTS 4009 0048h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9N PIPE8N PIPE7N PIPE6N PIPE5N PIPE4N PIPE3N PIPE2N PIPE1N PIPE0N
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0NRDY
NRDY Interrupt Status for Pipe 0
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
b1
b2
b3
b4
b5
b6
b7
b8
b9
PIPE1NRDY
PIPE2NRDY
PIPE3NRDY
PIPE4NRDY
PIPE5NRDY
PIPE6NRDY
PIPE7NRDY
PIPE8NRDY
PIPE9NRDY
b15 to b10 —
Note 1.
NRDY Interrupt Status for Pipe 1
NRDY Interrupt Status for Pipe 2
NRDY Interrupt Status for Pipe 3
NRDY Interrupt Status for Pipe 4
NRDY Interrupt Status for Pipe 5
NRDY Interrupt Status for Pipe 6
NRDY Interrupt Status for Pipe 7
NRDY Interrupt Status for Pipe 8
NRDY Interrupt Status for Pipe 9
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These bits are read as 0. The write value should be 0. R/W
To clear the status indicated in the bits in NRDYSTS, write 0 only to the bits to be cleared. Write 1 to the other bits.
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28.2.17
28. USB 2.0 Full-Speed Module (USBFS)
BEMP Interrupt Status Register (BEMPSTS)
Address(es): USBFS.BEMPSTS 4009 004Ah
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B
EMP
EMP
EMP
EMP
EMP
EMP
EMP
EMP
EMP
EMP
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BEMP
BEMP Interrupt Status for Pipe 0
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
b1
b2
b3
b4
b5
b6
b7
b8
b9
PIPE1BEMP
PIPE2BEMP
PIPE3BEMP
PIPE4BEMP
PIPE5BEMP
PIPE6BEMP
PIPE7BEMP
PIPE8BEMP
PIPE9BEMP
b15 to b10 —
Note 1.
BEMP Interrupt Status for Pipe 1
BEMP Interrupt Status for Pipe 2
BEMP Interrupt Status for Pipe 3
BEMP Interrupt Status for Pipe 4
BEMP Interrupt Status for Pipe 5
BEMP Interrupt Status for Pipe 6
BEMP Interrupt Status for Pipe 7
BEMP Interrupt Status for Pipe 8
BEMP Interrupt Status for Pipe 9
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These bits are read as 0. The write value should be 0. R/W
To clear the status indicated by the bits in BEMPSTS, write 0 only to the bits to be cleared. Write 1 to the other bits.
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28.2.18
28. USB 2.0 Full-Speed Module (USBFS)
Frame Number Register (FRMNUM)
Address(es): USBFS.FRMNUM 4009 004Ch
b15
b14
b13
b12
b11
OVRN
CRCE
—
—
—
0
0
0
0
0
Value after reset:
Bit
Symbol
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
FRNM[10:0]
0
0
0
0
0
0
Bit name
Description
R/W
R
b10 to b0
FRNM[10:0]
Frame Number
Latest frame number
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b14
CRCE
Receive Data Error
0: No error
1: An error occurred
R/W*1
b15
OVRN
Overrun/Underrun Detection Status
0: No error
1: An error occurred
R/W*1
Note 1.
To clear the status, write 0 only to the bits to be cleared. Write 1 to the other bits.
FRNM[10:0] bits (Frame Number)
The USBFS sets the FRNM[10:0] bits to indicate the latest frame number, which is updated every 1 ms, when an SOF
packet is issued or received.
CRCE bit (Receive Data Error)
The CRCE bit is set to 1 when a CRC error or bit stuffing error occurs during isochronous transfer. On detecting a CRC
error in host controller mode, the USBFS generates an internal NRDY interrupt.
To clear the CRCE bit, write 0 to it while writing 1 to the other bits in the FRMNUM register.
OVRN bit (Overrun/Underrun Detection Status)
The OVRN bit is set to 1 when an overrun or underrun error occurs during isochronous transfer. To clear the bit, write 0
to it while writing 1 to the other bits in the FRMNUM register.
In host controller mode, the OVRN bit is set to 1 on any of the following conditions:
For a transmitting isochronous pipe, the time to issue an OUT token comes before all of the transmit data is written
to the FIFO buffer
For a receiving isochronous pipe, the time to issue an IN token comes when no FIFO buffer planes are empty.
In device controller mode, the OVRN bit is set to 1 on any of the following conditions:
For a transmitting isochronous pipe, the IN token is received before all of the transmit data is written to the FIFO
buffer
For a receiving isochronous pipe, the OUT token is received when no FIFO buffer planes are empty.
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28.2.19
28. USB 2.0 Full-Speed Module (USBFS)
USB Request Type Register (USBREQ)
Address(es): USBFS.USBREQ 4009 0054h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
BREQUEST[7:0]
Value after reset:
0
0
0
0
0
b4
b3
b2
b1
b0
0
0
BMREQUESTTYPE[7:0]
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
BMREQUESTTYPE[7:0]
Request Type
USB request bmRequestType value
R/W
*1
b15 to b8
BREQUEST[7:0]
Request
USB request bRequest value
R/W
*1
Note 1.
In device controller mode, these bits are readable, but writing to them has no effect. In host controller mode, these bits are
read/write.
USBREQ stores setup requests for control transfers.
In device controller mode, the USBREQ stores the received bRequest and bmRequestType values. In host controller
mode, it sets the bRequest and bmRequestType values to be transmitted.
USBREQ is initialized by a USB bus reset.
BMREQUESTTYPE[7:0] bits (Request Type)
The BMREQUESTTYPE[7:0] bits hold the bmRequestType value of USB requests.
In host controller mode:
Set these bits to the value of the USB request data in transmission setup transactions. Do not change the value of the
bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the value of the USB request data in reception setup transactions. Writing to the bits has no
effect.
BREQUEST[7:0] bits (Request)
The BREQUEST[7:0] bits store bRequest value of the USB request.
In host controller mode:
Set these bits to the value of the USB request data in setup transmission transactions. Do not change the value of the
bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the value of the USB request data in reception setup transactions. Writing to the bits has no
effect.
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28.2.20
28. USB 2.0 Full-Speed Module (USBFS)
USB Request Value Register (USBVAL)
Address(es): USBFS.USBVAL 4009 0056h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WVALUE[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WVALUE[15:0]
Value
These bits store the USB request wValue value
R/W
*1
Note 1.
In device controller mode, these bits are readable, but writing to them has no effect. In host controller mode, these bits are both
read/write.
In device controller mode, USBVAL stores the received wValue value. In host controller mode, it sets to the wValue
value to be transmitted is set.
USBVAL is initialized by a USB bus reset.
WVALUE[15:0] bits (Value)
The WVALUE[15:0] bits store wValue value of the USB request.
In host controller mode:
Set these bits to the value of the wValue field in USB requests of transmission setup transactions. Do not change the
value of the bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the wValue value of USB requests in reception setup transactions. Writing to the bits has no
effect.
28.2.21
USB Request Index Register (USBINDX)
Address(es): USBFS.USBINDX 4009 0058h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WINDEX[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WINDEX[15:0]
Index
These bits store the USB request wIndex value
R/W
*1
Note 1.
In device controller mode, these bits are readable, but writing to them has no effect. In host controller mode, these bits are both
read/write.
USBINDX stores setup requests for control transfers. In device controller mode, it stores the received wIndex value. In
host controller mode, it sets to the wIndex value to be transmitted.
USBINDX is initialized by a USB bus reset.
WINDEX[15:0] bits (Index)
The WINDEX[15:0] bits hold the value of a USB request.
In host controller mode:
Set these bits to the wIndex value in USB requests in transmission setup transactions. Do not change the value of the
bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the wIndex value in USB requests received in reception setup transactions. Writing to the bits
has no effect.
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28.2.22
28. USB 2.0 Full-Speed Module (USBFS)
USB Request Length Register (USBLENG)
Address(es): USBFS.USBLENG 4009 005Ah
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WLENTUH[15:0]
0
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WLENTUH[15:0]
Length
These bits store the USB request wLength value
R/W*1
Note 1.
In device controller mode, these bits are readable, but writing to them has no effect. In host controller mode, these bits are both
read/write.
USBLENG stores setup requests for control transfers.When the device controller is selected, the value of wLength that is
received is stored. In host controller mode, the value of wLength to be transmitted is set. USBLENG is initialized by a
USB bus reset.
WLENTUH[15:0] bits (Length)
The WLENTUH[15:0] bits hold the wLength value of a USB request.
In host controller mode:
Set these bits to the wLength value in USB requests in transmission setup transactions. Do not change the value of
the bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the wLength value in USB requests received in reception setup transactions. Writing to the bits
has no effect.
28.2.23
DCP Configuration Register (DCPCFG)
Address(es): USBFS.DCPCFG 4009 005Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
SHTNA
K
—
—
DIR
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
DIR
Transfer Direction *1
0: Data receiving direction
1: Data transmitting direction.
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
SHTNAK
Pipe Disabled at End of Transfer *1
0: Pipe kept open at the end of transfer
1: Pipe disabled at the end of transfer.
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note 1.
R/W
R/W
R/W
Only set this bit while the PID is NAK. Before setting this bit, check that the DCPCTR.PBUSY bit is 0, and then change the
DCPCTR.PID[1:0] bits for the DCP from BUF to NAK. If the PID[1:0] bits are changed to NAK by the USBFS, checking the
PBUSY bit through software is not necessary.
DIR bit (Transfer Direction)
In host controller mode, the DIR bit sets the transfer direction of the data stage and status stage for control transfers. In
device controller mode, set the DIR bit to 0.
SHTNAK bit (Pipe Disabled at End of Transfer)
The SHTNAK bit specifies whether to change PID to NAK on transfer end when the selected pipe is receiving. It is only
valid when the selected pipe is receiving. When the SHTNAK bit is 1, the USBFS changes the DCPCTR.PID[1:0] bits
for the DCP to NAK on determining that a transfer has ended. The USBFS determines transfer end on the following
condition:
A short packet, including a zero-length packet, is successfully received.
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28.2.24
28. USB 2.0 Full-Speed Module (USBFS)
DCP Maximum Packet Size Register (DCPMAXP)
Address(es): USBFS.DCPMAXP 4009 005Eh
b15
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
0
0
0
0
0
DEVSEL[3:0]
0
Value after reset:
Bit
0
Symbol
b6 to b0
MXPS[6:0]
0
0
Bit name
Maximum Packet
Size *1
b6
b5
b4
b3
b2
b1
b0
0
0
0
MXPS[6:0]
1
0
0
0
Description
R/W
These bits set the maximum amount of data (maximum packet size)
in payloads for the DCP.
R/W
b6
b0
0 0 0 1 0 0 0: 8 bytes
0 0 1 0 0 0 0: 16 bytes
0 0 1 1 0 0 0: 24 bytes
0 1 0 0 0 0 0: 32 bytes
0 1 0 1 0 0 0: 40 bytes
0 1 1 0 0 0 0: 48 bytes
0 1 1 1 0 0 0: 56 bytes
1 0 0 0 0 0 0: 64 bytes
1 0 0 1 0 0 0: 72 bytes
1 0 1 0 0 0 0: 80 bytes
1 0 1 1 0 0 0: 88 bytes
1 1 0 0 0 0 0: 96 bytes
1 1 0 1 0 0 0: 104 bytes
1 1 1 0 0 0 0: 112 bytes
1 1 1 1 0 0 0: 120 bytes
Other settings are prohibited.
b11 to b7
—
b15 to b12 DEVSEL[3:0]
Note 1.
Note 2.
Reserved
These bits are read as 0. The write value should be 0.
R/W
Device Select *2
b15
R/W
b12
0 0 0 0: Address 0000
0 0 0 1: Address 0001
0 0 1 0: Address 0010
0 0 1 1: Address 0011
0 1 0 0: Address 0100
0 1 0 1: Address 0101
Other settings are prohibited.
Only set the MXPS[6:0] bits while PID is NAK. Before setting these bits, check that the DCPCTR.PBUSY bit is 0, and then
change the DCPCTR.PID[1:0] bits for the DCP from BUF to NAK. If the PID[1:0] bits are changed to NAK by the USBFS,
checking the PBUSY bit through software is not necessary. After the MXPS[6:0] bits are set and the DCP is set to the
CURPIPE[3:0] bits in a port select register, clear the buffer by setting the BCLR bit the port control register to 1.
Only set the DEVSEL[3:0] bits while PID is NAK and the DCPCTR.SUREQ bit is 0. Before setting these bits, check that the
DCPCTR.PBUSY bit is 0, and then change the DCPCTR.PID[1:0] bits for the DCP from BUF to NAK. If the PID[1:0] bits are
changed to NAK by the USBFS, checking the PBUSY bit through software is not necessary.
MXPS[6:0] bits (Maximum Packet Size)
The MXPS[6:0] bits specify the maximum data payload (maximum packet size) for the DCP. The initial value is 40h (64
bytes). Set the bits to a USB 2.0-compliant value. Do not write to the FIFO buffer or set PID = BUF while MXPS[6:0] is
set to 00h.
DEVSEL[3:0] bits (Device Select)
In host controller mode, the DEVSEL[3:0] bits specify the address of the target peripheral device for a control transfer.
Set up the device address in the associated DEVADDn (n = 0 to 5) register first, and then set these bits to the
corresponding value. To set the DEVSEL[3:0] bits to 0010b, for example, first set the address in the DEVADD2 register.
In device controller mode, set these bits to 0000b.
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28.2.25
28. USB 2.0 Full-Speed Module (USBFS)
DCP Control Register (DCPCTR)
Address(es): USBFS.DCPCTR 4009 0060h
b15
b14
BSTS SUREQ
Value after reset:
0
0
b13
b12
b11
b10
b9
—
—
SUREQ
CLR
—
—
0
0
0
0
0
b8
b7
b6
b5
SQCLR SQSET SQMO PBUSY
N
0
0
1
0
b4
b3
b2
—
—
CCPL
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b2
CCPL
Control Transfer End Enable
0: Invalid
1: Control transfer completion enabled.
R/W
0
0
1
1
0: NAK response
1: BUF response (depending on the buffer state)
0: STALL response
1: STALL response.
b4, b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: DCP not used for the transaction
1: DCP in used for the transaction.
R
b6
SQMON
Sequence Toggle Bit Monitor
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set *2
Sets the sequence toggle bit in DCP transfers:
0: Invalid (writing 0 has no effect)
1: Set the expected value for the next transaction to
DATA1.
R/W*1
b8
SQCLR
Sequence Toggle Bit Clear *2
Clears the sequence toggle bit in DCP transfers:
0: Invalid (writing 0 has no effect)
1: Clear the expected value for the next transaction to
DATA0.
R/W*1
b10, b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b11
SUREQCLR
SUREQ Bit Clear
Clears the SUREQ bit in host controller mode:
0: Invalid (writing 0 has no effect)
1: Clear SUREQ to 0.
R/W*1
b13, b12
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
SUREQ
Setup Token Transmission
Sets up token transmission in host controller mode:
0: Invalid (writing 0 has no effect)
1: Transmit setup packet.
R/W
b15
BSTS
Buffer Status
0: Buffer access disabled
1: Buffer access enabled.
R
Note 1.
Note 2.
This bit is read as 0.
Only set the SQSET and SQCLR bits to 1 while PID is NAK. Before setting these bits, check that the PBUSY bit is 0, and then
change the PID[1:0] bits for the DCP from BUF to NAK. If the PID[1:0] bits are changed to NAK by the USBFS, checking the
PBUSY bit through software is not necessary.
PID[1:0] bits (Response PID)
The PID[1:0] bits control the USB response type during control transfers.
In host controller mode, to change the PID[1:0] setting from NAK to BUF:
When the transmitting direction is set:
a. Write all of the transmit data to the FIFO buffer while the DVSTCTR0.UACT bit is 1 and PID is NAK.
b. Set PID[1:0] bits to 01b (BUF).
The USBFS then executes the OUT transaction.
When the receiving direction is set:
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28. USB 2.0 Full-Speed Module (USBFS)
a. Check that the FIFO buffer is empty (or empty the buffer) while the DVSTCTR0.UACT bit is 1 and PID is
NAK.
Set PID[1:0] bits to 01b (BUF).
The USBFS then executes the IN transaction.
The USBFS changes the PID[1:0] setting as follows:
When the PID[1:0] bits are set to BUF (01b) by software and the USBFS has received data exceeding
MaxPacketSize, the USBFS sets the PID[1:0] to STALL (11b)
When a reception error, such as a CRC error, is detected three times consecutively, the USBFS sets the PID[1:0]
bits to NAK (00b)
On receiving the STALL handshake, the USBFS sets PID[1:0] to STALL (11b).
In device controller mode, the USBFS changes the PID[1:0] setting as follows:
On receiving a setup packet, the USBFS sets PID[1:0] to NAK (00b). The USBFS then sets the INTSTS0.VALID
flag to 1, and the PID[1:0] setting cannot be changed until software clears the VALID flag to 0.
When the PID[1:0] bits are set to BUF (01b) by software and the USBFS has received data exceeding
MaxPacketSize, the USBFS sets PID[1:0] to STALL (11b)
On detecting a control transfer sequence error, the USBFS sets PID[1:0] to STALL (1xb)
On detecting a USBFS bus reset, the USBFS sets PID[1:0] to NAK.
The USBFS does not check the PID[1:0] setting while processing a SET_ADDRESS request. The PID[1:0] bits are
initialized by a USB bus reset.
CCPL bit (Control Transfer End Enable)
In device controller mode, setting the CCPL bit to 1 enables the status stage of the control transfer to be completed.
When the bit is set to 1 by software while the associated PID[1:0] bits are set to BUF, the USBFS completes the control
transfer status stage.
During control read transfers, the USBFS transmits the ACK handshake in response to the OUT transaction from the
USB host. During control write or no-data control transfers, it transmits the zero-length packet in response to the IN
transaction from the USB host. On detecting a SET_ADDRESS request, the USBFS operates in auto response mode
from the setup stage up to status stage completion regardless of the CCPL bit setting.
The USBFS changes the CCPL bit from 1 to 0 on receiving a new setup packet. Software cannot write 1 to the bit while
the INTSTS0.VALID bit is 1. The bit is initialized by a USB bus reset.
In host controller mode, always write 0 to the CCPL bit.
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether DCP is used for the transaction when USBFS changes the PID[1:0] bits from BUF to
NAK. The USBFS changes the PBUSY bit from 0 to 1 on start of a USBFS transaction for the selected pipe. It changes
the PBUSY bit from 1 to 0 on completion of one transaction.
After PID is set to NAK by software, the value in the PBUSY bit indicates whether changes to pipe settings can proceed.
For details, see section 28.3.4.1, Pipe control register switching procedures.
SQMON bit (Sequence Toggle Bit Monitor)
The SQMON bit indicates the expected value of the sequence toggle bit for the next transaction during a DCP transfer.
The USBFS toggles the bit on normal completion of the transaction. It does not toggle the bit, however, when a DATAPID mismatch occurs during a transfer in the receiving direction.
In device controller mode, the USBFS sets the SQMON bit to 1 (specifies DATA1 as the expected value) on successful
reception of the setup packet. In device controller mode, the USBFS does not reference this bit during IN or OUT
transactions at the status stage, and it does not toggle the bit on normal completion.
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28. USB 2.0 Full-Speed Module (USBFS)
SQSET bit (Sequence Toggle Bit Set)
The SQSET bit specifies DATA1 as the expected value of the sequence toggle bit for the next transaction during a DCP
transfer.
Do not set the SQCLR and SQSET bits to 1 simultaneously.
SQCLR bit (Sequence Toggle Bit Clear)
The SQCLR bit specifies DATA0 as the expected value of the sequence toggle bit for the next transaction during a DCP
transfer. It is read as 0.
Do not set the SQCLR and SQSET bits to 1 simultaneously.
SUREQCLR bit (SUREQ Bit Clear)
In host controller mode, setting the SUREQCLR bit to 1 clears the SUREQ bit to 0. The bit is read as 0.
If transfer stops while the SUREQ bit is set to 1 in a setup transaction, set the SUREQCLR bit to 1 by software. This is
not required at the end of a normal setup transaction, because the USBFS automatically clears the SUREQ bit to 0.
Only control the SUREQ bit through the SUREQCLR bit while the DVSTCTR0.UACT bit is 0. When UACT is 0,
communication is halted or no transfer is occurring because a bus disconnection was detected.
In device controller mode, always write 0 to this bit.
SUREQ bit (Setup Token Transmission)
In host controller mode, setting the SUREQ bit to 1 triggers the USBFS to transmit the setup packet. After completing
the setup transaction process, the USBFS generates either the SACK or SIGN interrupt and clears the SUREQ bit to 0.
The USBFS also clears the SUREQ bit to 0 when software sets the SUREQCLR bit to 1.
Before setting the SUREQ bit to 1, set the DCPMAXP.DEVSEL[3:0] bits, USBREQ, USBVAL, USBINDX, and
USBLENG appropriately to transmit the target USB request in the setup transaction. Also check that the PID[1:0] bits
for the DCP are set to NAK. After setting the SUREQ bit to 1, do not change the DCPMAXP.DEVSEL[3:0] bits,
USBREQ, USBVAL, USBINDX, or USBLENG until the setup transaction is complete (SUREQ bit = 1). Write 1 to the
SUREQ bit only when transmitting the setup token. Otherwise, write 0.
In device controller mode, always write 0 to this bit.
BSTS bit (Buffer Status)
The BSTS bit indicates the status of access to the DCP FIFO buffer. The meaning of this bit varies as follows depending
on the CFIFOSEL.ISEL setting:
When ISEL = 0, the bit indicates whether receive data can be read from the buffer
When ISEL = 1, the bit indicates whether transmit data can be written to the buffer.
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28.2.26
28. USB 2.0 Full-Speed Module (USBFS)
Pipe Window Select Register (PIPESEL)
Address(es): USBFS.PIPESEL 4009 0064h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
PIPESEL[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
PIPESEL[3:0]
Pipe Window Select
b3
R/W
b15 to b4
—
Reserved
b0
0 0 0 0: No pipe selected
0 0 0 1: Pipe 1
0 0 1 0: Pipe 2
0 0 1 1: Pipe 3
0 1 0 0: Pipe 4
0 1 0 1: Pipe 5
0 1 1 0: Pipe 6
0 1 1 1: Pipe 7
1 0 0 0: Pipe 8
1 0 0 1: Pipe 9.
Other settings are prohibited.
These bits are read as 0. The write value should be 0.
R/W
Set pipes 1 to 9 using the PIPESEL, PIPECFG, PIPEMAXP, PIPEPERI, PIPEnCTR, PIPEnTRE, and PIPEnTRN
registers (n = 0 to 9).
After selecting the pipe in the PIPESEL register, pipe functions must be set in the associated PIPECFG, PIPEMAXP, and
PIPEPERI registers. PIPEnCTR, PIPEnTRE, and PIPEnTRN can be set independently of the pipe selection in this
register.
PIPESEL[3:0] bits (Pipe Window Select)
The PIPESEL[3:0] bits select the pipe number associated with the PIPECFG, PIPEMAXP, and PIPEPERI registers used
for data writing and reading. Selecting a pipe number in the PIPESEL[3:0] bits allows writing to and reading from
PIPECFG, PIPEMAXP, and PIPEPERI associated with the selected pipe number.
When PIPESEL[3:0] = 0000b, 0 is read from all of the bits in PIPECFG, PIPEMAXP, and PIPEPERI. Writing to these
bits is invalid.
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28.2.27
28. USB 2.0 Full-Speed Module (USBFS)
Pipe Configuration Register (PIPECFG)
Address(es): USBFS.PIPECFG 4009 0068h
b15
Value after reset:
Bit
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
TYPE[1:0]
—
—
—
BFRE
DBLB
—
SHTNA
K
—
—
DIR
0
0
0
0
0
0
0
0
0
0
0
0
Symbol
Bit name
Number *1
b3 to b0
EPNUM[3:0]
Endpoint
b4
DIR
Transfer Direction *2, *3
b6, b5
—
Reserved
b7
SHTNAK
Pipe Disabled at End of
b8
—
b9
DBLB
b10
b3
b2
b1
b0
EPNUM[3:0]
0
0
0
0
Description
R/W
Specifies the endpoint number for the selected pipe.
Setting 0000b indicates that the pipe is not used.
R/W
0: Receiving direction
1: Transmitting direction.
R/W
These bits are read as 0. The write value should be 0. R/W
Transfer *1
0: Continue pipe operation after transfer ends
1: Disable pipe operation after transfer ends.
R/W
Reserved
This bit is read as 0. The write value should be 0.
R/W
Double Buffer Mode *2, *3
0: Single buffer
1: Double buffer.
R/W
BFRE
BRDY Interrupt Operation
Specification *2, *3
0: BRDY interrupt generated on transmitting or
receiving data
1: BRDY interrupt generated on completion of reading
data.
R/W
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b15, b14
TYPE[1:0]
Transfer Type *1
Pipes 1 and 2
R/W
b15 b14
0 0: Pipe not used
0 1: Bulk transfer
1 0: Setting prohibited
1 1: Isochronous transfer.
Pipes 3 to 5
b15 b14
0 0: Pipe not used
0 1: Bulk transfer
1 0: Setting prohibited
1 1: Setting prohibited.
Pipes 6 to 9
b15 b14
0
0
1
1
Note 1.
Note 2.
Note 3.
0: Pipe not used
1: Setting prohibited
0: Interrupt transfer
1: Setting prohibited.
Only set the TYPE[1:0], SHTNAK, and EPNUM[3:0] bits while PID is NAK. Before setting these bits, check that the
PIPEnCTR.PBUSY bit is 0, and then change the PIPEnCTR.PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are
changed to 00 (NAK) by the USBFS, checking the PBUSY bit through software is not necessary.
Only set the BFRE, DBLB, and DIR bits while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port
select register. Before setting these bits, check that the PIPEnCTR.PBUSY bit is 0, and then change the PIPEnCTR.PID[1:0]
bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit through
software is not necessary.
To modify the BFRE, DBLB, or DIR bits after completing USB communication on the selected pipe, in addition to the
restrictions described in Note 2, write 1 and 0 to the PIPEnCTR.ACLRM bit continuously through software and clear the FIFO
buffer assigned to the pipe.
PIPECFG specifies the transfer type, FIFO buffer access direction, and endpoint numbers for pipes 1 to 9. It also selects
single or double buffer mode, and whether to continue or disable pipe operation at the end of transfer.
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28. USB 2.0 Full-Speed Module (USBFS)
EPNUM[3:0] bits (Endpoint Number)
The EPNUM[3:0] bits specify the endpoint number for the selected pipe. Setting 0000b indicates that the pipe is not
used.
Set these bits so that the combination of the DIR and EPNUM[3:0] settings is different from those for other pipes. The
EPNUM[3:0] bits can be set to 0000b for all pipes.
DIR bit (Transfer Direction)
The DIR bit specifies the transfer direction for the selected pipe.
When software sets this bit to 0, the USBFS uses the selected pipe for receiving. When software sets this bit to 1, the
USBFS uses the selected pipe for transmitting.
SHTNAK bit (Pipe Disabled at End of Transfer)
The SHTNAK bit specifies whether to change the PIPEnCTR.PID[1:0] bits to 00b (NAK) at the end of transfer when the
selected pipe is set in the receiving direction. The bit is valid for pipes 1 to 5 in the receiving direction.
When software sets this bit to 1 for a receiving pipe, the USBFS changes the associated PIPEnCTR.PID[1:0] bits to 00b
(NAK) on determining the transfer end. The USBFS determines that the transfer has ended on the following conditions:
A short packet (including a zero-length packet) is successfully received
The transaction counter is used and the number of packets specified for the transaction counter are successfully
received.
DBLB bit (Double Buffer Mode)
The DBLB bit selects either single or double buffer mode for the FIFO buffer used by the selected pipe. The bit is valid
for pipes 1 to 5.
BFRE bit (BRDY Interrupt Operation Specification)
The BFRE bit specifies the BRDY interrupt generation timing from the USBFS to the CPU for the selected pipe.
When software sets the BFRE bit to 1 and the selected pipe is in the receiving direction, the USBFS detects the transfer
completion and generates the BRDY interrupt on reading the packet.
When a BRDY interrupt is generated with this setting, software must write 1 to the BCLR bit in the port control register.
The FIFO buffer assigned to the selected pipe is not enabled for reception until 1 is written to the BCLR bit.
When the BFRE bit is set to 1 by software and the selected pipe is in the transmitting direction, the USBFS does not
generate the BRDY interrupt. For details, see section 28.3.3.1, BRDY interrupt.
TYPE[1:0] bits (Transfer Type)
The TYPE[1:0] bits specify the transfer type for the pipe selected in the PIPESEL.PIPESEL[3:0] bits. Before setting PID
to BUF and starting USB communication on the selected pipe, set the TYPE[1:0] bits to a value other than 00b.
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28.2.28
28. USB 2.0 Full-Speed Module (USBFS)
Pipe Maximum Packet Size Register (PIPEMAXP)
Address(es): USBFS.PIPEMAXP 4009 006Ch
b15
b14
b13
b12
b11
b10
b9
—
—
—
0
0
0
DEVSEL[3:0]
0
Value after reset:
Bit
0
Symbol
0
0
Bit name
Size *2
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
MXPS[8:0]
0
0
0/1
*1
0
0
Description
R/W
Pipes 1 and 2:
1 byte (001h) to 256 bytes (100h)
Pipes 3 to 5:
8 bytes (008h), 16 bytes (010h)
32 bytes (020h), 64 bytes (040h)
Bits [8:7] and [2:0] are not supported.
Pipes 6 to 9:
1 byte (001h) to 64 bytes (040h)
Bits [8:7] are not supported.
R/W
b8 to b0
MXPS[8:0]
Maximum Packet
b11 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Device Select *3
b3
R/W
b15 to b12 DEVSEL[3:0]
Note 1.
Note 2.
Note 3.
b0
0 0 0 0: Address 0000
0 0 0 1: Address 0001
0 0 1 0: Address 0010
0 0 1 1: Address 0011
0 1 0 0: Address 0100
0 1 0 1: Address 0101.
Other settings are prohibited.
The value of the MXPS[8:0] bits is 000h when no pipe is selected in the PIPESEL.PIPESEL[3:0] bits and 040h when a pipe is
selected.
Only set the MXPS[8:0] bits while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port select
register. Before setting these bits, check that the PIPEnCTR.PBUSY bit is 0, and then change the PIPEnCTR.PID[1:0] bits from
01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit through software
is not necessary.
Only set the DEVSEL[3:0] bits while PID is NAK. Before setting these bits, check that the PIPEnCTR.PBUSY bit is 0, and then
change the PIPEnCTR.PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS,
checking the PBUSY bit through software is not necessary.
PIPEMAXP specifies the maximum packet size for pipes 1 to 9.
MXPS[8:0] bits (Maximum Packet Size)
The MXPS[8:0] bits specify the maximum data payload (maximum packet size) for the selected pipe.
Set these bits to the appropriate value for each transfer type based on the USB 2.0 specification.
When MXPS[8:0] = 000h, do not write to the FIFO buffer or set PID to BUF. These writes have no effect.
DEVSEL[3:0] bits (Device Select)
In host controller mode, the DEVSEL[3:0] bits specify the address of the target device for USB communication. Set up
the device address in the associated DEVADDn (n = 0 to 5) register first, and then set these bits to the corresponding
value. To set the DEVSEL[3:0] bits to 0010b, for example, first set the address in the DEVADD2 register.
In device controller mode, set these bits to 0000b.
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28.2.29
28. USB 2.0 Full-Speed Module (USBFS)
Pipe Cycle Control Register (PIPEPERI)
Address(es): USBFS.PIPEPERI 4009 006Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
—
—
—
IFIS
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
b2
b1
b0
IITV[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
IITV[2:0]
*1
Interval Error Detection Interval
Specifies the interval error detection timing for the selected pipe
as the n-th power of 2 of the frame timing
R/W
b11 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b12
IFIS
Isochronous IN Buffer Flush
0: The buffer is not flushed
1: The buffer is flushed.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b13 —
Note 1.
Only set the IITV[2:0] bits while PID is NAK. Before setting these bits, check that the PBUSY bit is 0, and then change the
PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit
through software is not necessary.
PIPEPERI selects whether the buffer is flushed or not when an interval error occurred during isochronous IN transfers,
and sets the interval error detection interval for pipes 1 to 9.
IITV[2:0] bits (Interval Error Detection Interval)
To change the IITV[2:0] bits to another value after they are set and USB communication is performed, set the
PIPEnCTR.PID[1:0] bits to 00b (NAK) and then set the PIPEnCTR.ACLRM bit to 1 to initialize the interval timer.
The IITV[2:0] bits are not provided for pipes 3 to 5. Write 000b to bit positions of the IITV[2:0] bits associated with
pipes 3 to 5.
IFIS bit (Isochronous IN Buffer Flush)
The IFIS bit specifies whether to flush the buffer when the pipe selected in the PIPESEL.PIPESEL[3:0] bits is used for
isochronous IN transfers.
In device controller mode when the selected pipe is for isochronous IN transfers, the USBFS automatically clears the
FIFO buffer if the USBFS fails to receive the IN token from the USB host within the interval set in the IITV[2:0] bits in
terms of frames.
When double buffering is specified (PIPECFG.DBLB = 1), the USBFS only clears the data in the previously used plane.
The USBFS clears the FIFO buffer on receiving the SOF packet immediately after the frame in which the USBFS
expected to receive the IN token. Even if the SOF packet is corrupted, the FIFO buffer is cleared at the time the SOF
packet is expected to be received by using the internal interpolation function.
When the host controller function is selected, set this bit to 0.
Set this bit to 0 when the selected pipe is not for isochronous transfers.
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28.2.30
28. USB 2.0 Full-Speed Module (USBFS)
PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)
PIPEnCTR (n = 1 to 5)
Address(es): USBFS.PIPE1CTR 4009 0070h, USBFS.PIPE2CTR 4009 0072h, USBFS.PIPE3CTR 4009 0074h,
USBFS.PIPE4CTR 4009 0076h, USBFS.PIPE5CTR 4009 0078h
b15
b14
b13
b12
b11
BSTS
INBUF
M
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
ATREP ACLRM SQCLR SQSET SQMO PBUSY
N
M
0
0
0
0
0
0
b4
b3
b2
—
—
—
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: Pipe n is not in use for the transaction
1: Pipe n is in use for the transaction.
R
b6
SQMON
Sequence Toggle Bit
Confirmation
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set *2
Sets the sequence toggle bit for pipe n.
0: Invalid (writing 0 has no effect)
1: Set the expected value for the next transaction to DATA1.
R/W*1
b8
SQCLR
Sequence Toggle Bit
Clear *2
Clears the sequence toggle bit for pipe n.
0: Invalid (writing 0 has no effect)
1: Clear the expected value for the next transaction to DATA0.
R/W*1
b9
ACLRM
Auto Buffer Clear Mode *3
0: Disabled
1: Enabled (all buffers initialized).
R/W
b10
ATREPM
Auto Response Mode *2
0: Auto response disabled
1: Auto response enabled.
R/W
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
INBUFM
Transmit Buffer Monitor
0: No data to be transmitted is in the FIFO buffer
1: Data to be transmitted is in the FIFO buffer.
R
b15
BSTS
Buffer Status
0: Buffer access by the CPU disabled
1: Buffer access by the CPU enabled.
R
Note 1.
Note 2.
Note 3.
0
0
1
1
0: NAK response
1: BUF response (depends on the buffer state)
0: STALL response
1: STALL response.
Only 0 can be read.
Only set the ATREPM bit or write 1 to the SQCLR or SQSET bit while PID is NAK. Before setting these bits, check that the
PBUSY bit is 0, and then change the PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by
the USBFS, checking the PBUSY bit through software is not necessary.
Only set the ACLRM bit while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port select register.
Before setting this bit, check that the PBUSY bit is 0, and then change the PID[1:0] bits from 01b (BUF) to 00b (NAK). If the
PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit through software is not necessary.
PIPEnCTR can be set for any pipe selection in the PIPESEL register.
PID[1:0] bits (Response PID)
The PID[1:0] bits specify the response type for the next transaction on the selected pipe.
The default PID[1:0] setting is NAK. Change the PID[1:0] setting to BUF to use the associated pipe for USB transfer.
Table 28.7 and Table 28.8 show the basic operations of the USBFS (when there are no errors in the communication
packets) based on the PID[1:0] bit setting.
After changing the PID[1:0] setting from BUF to NAK through software during USB communication on the selected
pipe, check that the PBUSY bit is 1 to determine if USB transfer on the pipe has actually entered the NAK state. If the
USBFS changes the PID[1:0] bits to NAK, checking the PBUSY bit through software is not necessary.
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28. USB 2.0 Full-Speed Module (USBFS)
The USBFS changes the PIPEnCTR.PID[1:0] setting in the following cases:
The USBFS sets PID to NAK on recognizing completion of the transfer when the selected pipe is in the receiving
direction and the PIPECFG.SHTNAK bit for the selected pipe is set to 1 by software
The USBFS sets PID to STALL (11b) on receiving a data packet with a payload exceeding the maximum packet
size of the selected pipe
The USBFS sets PID to NAK on detecting a USB bus reset in device controller mode
The USBFS sets PID to NAK on detecting a reception error, such as a CRC error, three consecutive times in host
controller mode
The USBFS sets PID to STALL (11b) on receiving the STALL handshake in host controller mode.
To specify the response type, set the PID[1:0] bits as follows:
To transition from NAK (00b) to STALL, set 10b
To transition from BUF (01b) to STALL, set 11b
To transition from STALL (11b) to NAK, set 10b and then 00b
To transition from STALL to BUF, transition to NAK and then BUF.
Table 28.7
Operation of the USBFS based on the PID[1:0] setting in host controller mode
PID[1:0] value
Transfer type
Transfer direction
(DIR bit)
00b (NAK)
Does not depend on
the setting
Does not depend on
the setting
Does not issue tokens
01b (BUF)
Bulk or interrupt
Does not depend on
the setting
Issues tokens when the DVSTCTR0.UACT bit is 1 and the FIFO
buffer associated with the selected pipe is ready for transmission
and reception.
Does not issue tokens when the DVSTCTR0.UACT bit is 0 or the
FIFO buffer associated with the selected pipe is not ready for
transmission or reception.
Isochronous
Does not depend on
the setting
Issues tokens regardless of the status of the FIFO buffer associated
with the selected pipe
Does not depend on
the setting
Does not depend on
the setting
Does not issue tokens
10b (STALL) or
11b (STALL)
Table 28.8
USBFS operation
Operation of the USBFS based on the PID[1:0] setting in device controller mode (1 of 2)
Transfer direction
(DIR bit)
PID[1:0] value
Transfer type
00b (NAK)
Bulk or interrupt
Does not depend on
the setting
Returns NAK in response to the token from the USB host
Isochronous
Does not depend on
the setting
Returns nothing in response to the token from the USB host
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Table 28.8
28. USB 2.0 Full-Speed Module (USBFS)
Operation of the USBFS based on the PID[1:0] setting in device controller mode (2 of 2)
Transfer direction
(DIR bit)
PID[1:0] value
Transfer type
01b (BUF)
Bulk
Receiving direction
(DIR = 0)
Receives data and returns ACK in response to the OUT token from
the USB host if the FIFO buffer associated with the selected pipe is
ready for reception
Interrupt
Receiving direction
(DIR = 0)
Receives data and returns ACK in response to the OUT token from
the USB host if the FIFO buffer associated with the selected pipe is
ready for reception
Bulk or interrupt
Transmitting direction
(DIR = 1)
Transmits data in response to the token from the USB host if the
FIFO buffer associated with the selected pipe is ready for
transmission. Otherwise, returns NAK.
Isochronous
Receiving direction
(DIR = 0)
Receives data in response to the OUT token from the USB host if the
FIFO buffer associated with the selected pipe is ready for reception.
Otherwise, discards the data.
Isochronous
Transmitting direction
(DIR = 1)
Transmits data in response to the token from the USB host if the
associated FIFO buffer is ready for transmission. Otherwise,
transmits a zero-length packet.
Bulk or interrupt
Does not depend on
the setting
Returns STALL in response to the token from the USB host
Isochronous
Does not depend on
the setting
Returns nothing in response to the token from the USB host
10b (STALL) or
11b (STALL)
USBFS operation
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether the selected pipe is being used for the current transaction.
The USBFS changes the PBUSY bit from 0 to 1 on start of the USB transaction for the selected pipe, and changes the
PBUSY bit from 1 to 0 on completion of one transaction.
Reading the PBUSY bit by software after PID is set to NAK allows you to check whether changing the pipe setting is
possible. For details, see section 28.3.4.1, Pipe control register switching procedures.
SQMON bit (Sequence Toggle Bit Confirmation)
The SQMON bit indicates the expected value of the sequence toggle bit for the next transaction of the selected pipe.
When the selected pipe is not the isochronous transfer type, the USBFS toggles the SQMON bit on successful
completion of the transaction. However, the USBFS does not toggle the SQMON flag when a DATA-PID mismatch
occurs during transfer in the receiving direction.
SQSET bit (Sequence Toggle Bit Set)
Setting the SQSET bit to 1 through software causes the USBFS to set DATA1 as the expected value of the sequence
toggle bit for the next transaction on the selected pipe. The USBFS clears the SQSET bit to 0.
SQCLR bit (Sequence Toggle Bit Clear)
Setting the SQCLR bit to 1 through software causes the USBFS to clear the expected value of the sequence toggle bit for
the next transaction on the selected pipe to DATA0. The USBFS clears the SQCLR bit to 0.
ACLRM bit (Auto Buffer Clear Mode)
The ACLRM bit enables or disables auto buffer clear mode for the selected pipe. To completely clear the data in the
FIFO buffer allocated to the selected pipe, write 1 and then 0 to the ACLRM bit continuously.
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28. USB 2.0 Full-Speed Module (USBFS)
Table 28.9 shows the data cleared by writing 1 and 0 to the ACLRM bit continuously and the cases in which this
processing is required.
Table 28.9
Number
Data cleared by the USBFS when ACLRM = 1
Data cleared by setting the ACLRM bit
Situations requiring data clear
1
All data in the FIFO buffer allocated to the selected pipe (two
FIFO buffers in double buffer mode)
When initializing the selected pipe
2
Interval count value when the selected pipe is the isochronous
transfer type
When resetting the interval count value
3
Internal flags related to the PIPECFG.BFRE bit
When changing the PIPECFG.BFRE setting
4
FIFO buffer toggle control
When changing the PIPECFG.DBLB setting
5
Internal flags related to the transaction count
When forcing the transaction count function to terminate
ATREPM bit (Auto Response Mode)
The ATREPM bit enables or disables auto response mode for the selected pipe.
This bit can be set to 1 in device controller mode when the selected pipe is the bulk transfer type. When the bit is set to 1,
the USBFS responds to the token from the USB host as follows:
When the selected pipe is set for bulk IN transfers (PIPECFG.TYPE[1:0] = 01b and PIPECFG.DIR = 1):
a. When the ATREPM bit = 1 and PID = BUF, the USBFS transmits a zero-length packet in response to the IN
token.
b. The USBFS updates (allows toggling of) the sequence toggle bit (DATA-PID) each time the USBFS receives
ACK from the USB host. In a single transaction, the IN token is received, a zero-length packet is transmitted,
and then ACK is received. The USBFS does not generate the BRDY or BEMP interrupt.
When the selected pipe is set for bulk OUT transfers (PIPECFG.TYPE[1:0] = 01b and PIPECFG.DIR = 0):
When the ATREPM bit = 1 and PID = BUF, the USBFS returns NAK in response to the OUT token and generates
an NRDY interrupt.
For USB communication in auto response mode, set the ATREPM bit to 1 while the FIFO buffer is empty. Do not write
to the FIFO buffer during USB communication in auto response mode. When the selected pipe uses isochronous transfer,
always set this bit to 0.
In host controller mode, always set the ATREPM bit to 0.
INBUFM bit (Transmit Buffer Monitor)
The INBUMFM bit indicates the FIFO buffer status for the selected pipe in the transmitting direction.
When the selected pipe is set in the transmitting direction (PIPECFG.DIR = 1), the USBFS sets this bit to 1 when the
CPU or DMA/DTC completes writing data to at least one FIFO buffer plane.
The USBFS sets this bit to 0 when the USBFS completes transmitting the data from the FIFO buffer plane to which all
the data is written. In double buffer mode (PIPECFG.DBLB = 1), the USBFS sets the INBUFM bit to 0 when the USBFS
completes transmitting the data from the two FIFO buffer planes before the CPU or DMA/DTC completes writing data to
one FIFO buffer plane.
The INBUFM bit indicates the same value as the BSTS bit when the selected pipe is in the receiving direction
(PIPECFG.DIR = 0).
BSTS bit (Buffer Status)
The BSTS bit indicates the FIFO buffer status for the selected pipe.
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28. USB 2.0 Full-Speed Module (USBFS)
The meaning of the BSTS bit depends on the PIPECFG.DIR, PIPECFG.BFRE, and DnFIFOSEL.DCLRM settings, as
shown in Table 28.10.
Table 28.10
BSTS bit operation
DIR value
BFRE value
DCLRM value
BSTS bit function
0
0
0
Sets to 1 when receive data can be read from the FIFO buffer, and sets to 0 on
completion of data read
1
Setting prohibited
1
0
Sets to 1 when receive data can be read from the FIFO buffer, and sets to 0 when
software sets the BCLR bit in the Port Control Register to 1 after the data read is
complete
1
Sets to 1 when receive data can be read from the FIFO buffer, and sets to 0 on
completion of data read
0
Sets to 1 when transmit data can be written to the FIFO buffer, and sets to 0 on
completion of data write
1
Setting prohibited
0
Setting prohibited
1
Setting prohibited
1
0
1
PIPEnCTR (n = 6 to 9)
Address(es): USBFS.PIPE6CTR 4009 007Ah, USBFS.PIPE7CTR 4009 007Ch, USBFS.PIPE8CTR 4009 007Eh, USBFS.PIPE9CTR 4009 0080h
b15
b14
b13
b12
b11
b10
BSTS
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b9
b8
b7
b6
b5
b4
b3
b2
—
—
—
0
0
0
ACLRM SQCLR SQSET SQMO PBUSY
N
0
0
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: Pipe n is not in use for the transaction
1: Pipe n is in use for the transaction.
R
b6
SQMON
Sequence Toggle Bit
Confirmation
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set *2
Sets the sequence toggle bit for pipe n:
0: Invalid (writing 0 has no effect)
1: Set the expected value for the next transaction to DATA1.
This bit is read as 0.
R/W*1
b8
SQCLR
Sequence Toggle Bit Clear *2
Clears the sequence toggle bit for pipe n:
0: Invalid (writing 0 has no effect)
1: Clear the expected value for the next transaction to DATA0.
This bit is read as 0.
R/W*1
b9
ACLRM
Auto Buffer Clear Mode *2, *3
0: Disabled
1: Enabled (all buffers are initialized).
R/W
b14 to b10 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
Buffer Status
0: Buffer access disabled
1: Buffer access enabled.
R
Note 1.
Note 2.
Note 3.
BSTS
0 0: NAK response
0 1: BUF response (depends on the buffer state)
1 0: STALL response
1 1: STALL response.
Only 0 can be read. Only 1 can be written.
Only write 1 to the SQCLR or SQSET bit while PID is NAK. Before setting these bits, check that the PBUSY bit is 0, and then
change the PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking
the PBUSY bit through software is not necessary.
Only set the ACLRM bit while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port select register.
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28. USB 2.0 Full-Speed Module (USBFS)
Before setting this bits, check that the PIPEnCTR.PBUSY bit is 0, and then change the PIPEnCTR.PID[1:0] bits from 01b (BUF)
to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit through software is not
necessary.
PID[1:0] bits (Response PID)
The PID[1:0] bits specify the response type for the next transaction of the selected pipe.
The default PID[1:0] setting is NAK. Change the PID[1:0] setting to BUF to use the associated pipe for USB transfer.
Table 28.7 and Table 28.7 show the basic operation (when there are no errors in the transmitted and received packets) of
the USB depending on the PID[1:0] setting.
After changing the PID[1:0] setting from BUF to NAK through software during USB communication on the selected
pipe, check that the PBUSY bit is 1 to determine if USB transfer on the selected pipe has actually entered the NAK state.
If the USBFS changes the PID[1:0] bits to NAK, checking the PBUSY bit through software is not necessary.
The USBFS changes the PIPEnCTR.PID[1:0] setting in the following cases:
The USBFS sets PID to STALL (11b) on receiving a data packet with a payload exceeding the maximum packet
size of the selected pipe
The USBFS sets PID to NAK on detecting a USB bus reset in device controller mode
The USBFS sets PID to NAK on detecting a reception error, such as a CRC error, three consecutive times in host
controller mode
The USBFS sets PID to STALL (11b) on receiving the STALL handshake in host controller mode.
To specify each response type, set the PID[1:0] bits as follows:
To transition from NAK (00b) to STALL, set 10b
To transition from BUF (01b) to STALL, set 11b
To transition from STALL (11b) to NAK, set 10b and then 00b
To transition from STALL to BUF, set 00b (NAK) and then 01b (BUF).
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether the selected pipe is being used for the current transaction.
The USBFS changes the PBUSY bit from 0 to 1 on start of the USB transaction for the selected pipe, and changes the
PBUSY bit from 1 to 0 on completion of one transaction.
Reading the PBUSY bit by software after PID is set to NAK allows you to check whether changing the pipe setting is
possible.
SQMON bit (Sequence Toggle Bit Confirmation)
The SQMON flag indicates the expected value of the sequence toggle bit for the next transaction of the selected pipe.
The USBFS toggles the SQMON flag on successful completion of the transaction. However, the USBFS does not toggle
the SQMON bit when a DATA-PID mismatch occurs during transfer in the receiving direction.
SQSET bit (Sequence Toggle Bit Set)
Setting the SQSET bit to 1 through software causes the USBFS to set DATA1 as the expected value of the sequence
toggle bit for the next transaction on the selected pipe. The USBFS sets the SQSET bit to 0.
SQCLR bit (Sequence Toggle Bit Clear)
Setting the SQCLR bit to 1 through software causes the USBFS to clear the expected value of the sequence toggle bit for
the next transaction on the selected pipe to DATA0. The USBFS sets the SQCLR bit to 0.
ACLRM bit (Auto Buffer Clear Mode)
The ACLRM bit enables or disables auto buffer clear mode for the selected pipe. To completely clear the data in the
FIFO buffer allocated to the selected pipe, write 1 and then 0 to the ACLRM bit continuously.
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28. USB 2.0 Full-Speed Module (USBFS)
Table 28.11 shows the data cleared by writing 1 and 0 continuously to the ACLRM bit and the cases in which this
processing is required.
Table 28.11
Number
Data cleared by USBFS when ACLRM = 1
Data cleared by setting the ACLRM bit
Situations requiring data clear
1
All data in the FIFO buffer allocated to the selected pipe
When initializing the selected pipe
2
The interval count value when the selected pipe is for
interrupt transfer and the host controller is selected
When resetting the interval count value
3
Internal flags related to the PIPECFG.BFRE bit
When changing the PIPECFG.BFRE setting
4
Internal flags related to the transaction count
When forcing the transaction count function to terminate
BSTS bit (Buffer Status)
The BSTS bit indicates the FIFO buffer status for the selected pipe.
The meaning of the BSTS bit depends on the PIPECFG.DIR, PIPECFG.BFRE, and DnFIFOSEL.DCLRM settings, as
shown in Table 28.10.
28.2.31
PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 1 to 5)
Address(es): USBFS.PIPE1TRE 4009 0090h, USBFS.PIPE2TRE 4009 0094h, USBFS.PIPE3TRE 4009 0098h,
USBFS.PIPE4TRE 4009 009Ch, USBFS.PIPE5TRE 4009 00A0h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
TRENB TRCLR
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
b7 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
TRCLR
Transaction Counter Clear
0: Invalid (writing 0 has no effect)
1: Clear the current counter value.
R/W
b9
TRENB
Transaction Counter Enable
0: Transaction counter disabled
1: Transaction counter enabled.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
Note:
Description
R/W
Set each bit in PIPEnTRE while PID is NAK. Before setting these bits after changing the PIPEnCTR.PID[1:0] bits for the
selected pipe from BUF to NAK, check that the PIPEnCTR.PBUSY bit is 0. However, if the PID[1:0] bits are changed to NAK by
the USBFS, checking the PBUSY bit through software is not necessary.
TRCLR bit (Transaction Counter Clear)
When the TRCLR bit sets to 1, the USBFS clears the current value of the transaction counter associated with the selected
pipe and then sets the TRCLR bit to 0.
TRENB bit (Transaction Counter Enable)
The TRENB bit enables or disables the transaction counter.
For receiving pipes, setting the TRENB bit to 1 after setting the total number of the packets to be received in the
PIPEnTRN.TRNCNT[15:0] bits through software allows the USBFS to control hardware on having received the number
of packets equal to the TRNCNT[15:0] setting, as follows:
When the PIPECFG.SHTNAK bit is 1, the USBFS changes the PID bits to NAK for the associated pipe on having
received the number of packets equal to the TRNCNT[15:0] setting
When the PIPECFG.BFRE bit is 1, the USBFS asserts the BRDY interrupt on having received the number of
packets equal to the TRNCNT[15:0] setting and then reading the last received data.
For transmitting pipes, set the TRENB bit to 0.
When the transaction counter is not used, set this bit to 0. When the transaction counter is used, set the TRNCNT[15:0]
bits before setting this bit to 1. Set this bit to 1 before receiving the first packet to be counted by the transaction counter.
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28.2.32
28. USB 2.0 Full-Speed Module (USBFS)
PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5)
Address(es): USBFS.PIPE1TRN 4009 0092h, USBFS.PIPE2TRN 4009 0096h, USBFS.PIPE3TRN 4009 009Ah,
USBFS.PIPE4TRN 4009 009Eh, USBFS.PIPE5TRN 4009 00A2h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
TRNCNT[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
TRNCNT[15:0]
Transaction Counter
When written to, this bit specifies the total packets
(number of transactions) to be received by the selected
pipe.
When read from, with PIPEnTRE.TRENB at 0, this bit
indicates the specified number of transactions.
When PIPEnTRE.TRENB is 1, this bit indicates the
current transaction count.
R/W
The PIPEnTRN registers retain their current setting during a USB bus reset.
TRNCNT[15:0] bits (Transaction Counter)
The USBFS increments the value of the TRNCNT[15:0] bits by 1 when all of the following conditions are satisfied on
receiving the packet:
The PIPEnTRE.TRENB bit = 1
(TRNCNT[15:0] set value ≠ current counter value + 1) on receiving the packet
The payload of the received packet agrees with the PIPEMAXP.MXPS[8:0] setting.
The USBFS clears the value of the TRNCNT[15:0] bits to 0 when any of the following conditions are satisfied:
All of the following conditions are satisfied:
The PIPEnTRE.TRENB bit = 1
(TRNCNT[15:0] set value = current counter value + 1) on receiving the packet
The payload of the received packet agrees with the PIPEMAXP.MXPS[8:0] setting.
Both of the following conditions are satisfied:
The PIPEnTRE.TRENB bit = 1
The USBFS received a short packet.
Both of the following conditions are satisfied:
The PIPEnTRE.TRENB bit = 1
The PIPEnTRE.TRCLR bit is set to 1 by software.
For transmitting pipes, set the TRNCNT[15:0] bits to 0. When the transaction counter is not used, set the TRNCNT[15:0]
bits to 0.
Setting the number of transactions to be transferred to the TRNCNT[15:0] bits is only enabled when the
PIPEnTRE.TRENB bit is 0. To set the number of transactions to be transferred, set the TRCLR bit to 1 to clear the
current counter value before setting the PIPEnTRE.TRENB bit to 1.
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28.2.33
28. USB 2.0 Full-Speed Module (USBFS)
Device Address n Configuration Register (DEVADDn) (n = 0 to 5)
Address(es): USBFS.DEVADD0 4009 00D0h, USBFS.DEVADD1 4009 00D2h, USBFS.DEVADD2 4009 00D4h,
USBFS.DEVADD3 4009 00D6h, USBFS.DEVADD4 4009 00D8h, USBFS.DEVADD5 4009 00DAh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
USBSPD[1:0]
0
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7, b6
USBSPD[1:0]
Transfer Speed of Communication
Target Device
b7 b6
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: DEVADDn not used
1: Low-speed
0: Full-speed
1: Setting prohibited.
The DEVADDn register specifies the transfer speed of the peripheral device that is the communication target for pipes 0
to 9.
In host controller mode, set all DEVADDn bits before starting communication with any pipes. Only change the bits in
DEVADDn when no valid pipes are using the bit settings. A valid pipe is defined as one that satisfies both of the
following conditions:
DEVADDn is selected in the DEVSEL[3:0] bits
The PID[1:0] bits are set to BUF for the selected pipe, or the selected pipe is the DCP with the DCPCTR.SUREQ bit
set to 1.
In device controller mode, set all bits in this register to 0.
USBSPD[1:0] bits (Transfer Speed of Communication Target Device)
The USBSPD[1:0] bits specify the USB transfer speed of the target peripheral device.
In host controller mode, the USBFS generates packets based on the USBSPD[1:0] setting. In device controller mode, set
these bits to 00b.
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28.2.34
28. USB 2.0 Full-Speed Module (USBFS)
USB Module Control Register (USBMC)
Address(es): USBFS.USBMC 4009 00CCh
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
VDCEN
—
—
—
—
—
—
VDDUS
BE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
VDDUSBE
USB Reference Power Supply Circuit
On/Off Control
0: USB reference power supply circuit off
1: USB reference power supply circuit on.
R/W
R/W
b1
—
Reserved
This bit is read as 1. The write value should be 1.
b6 to b2
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
VDCEN
USB Regulator On/Off Control
0: USB regulator off
1: USB regulator on.
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0. R/W
R/W
VDDUSBE bit (USB Reference Power Supply Circuit On/Off Control)
The USB reference power supply circuit generates the reference voltage for battery charging. Set this bit to 1 when using
the battery charging function.
VDCEN bit (USB Regulator On/Off Control)
The VDCEN bit is used to control the USB regulator circuit. Set this bit to 1 when using the USB regulator circuit.
28.2.35
BC Control Register 0 (USBBCCTRL0)
Address(es): USBFS.USBBCCTRL0 4009 00B0h
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b9
b8
b7
PDDET CHGDE BATCH
STS0 TSTS0 GE0
0
0
0
b6
—
0
b5
b4
b3
b2
b1
b0
VDMS IDPSIN VDPSR IDMSIN IDPSR RPDM
RCE0
KE0
CE0
KE0
CE0
E0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPDME0
D- Pin Pull-Down Control
0: Pull-down off
1: Pull-down on.
R/W
b1
IDPSRCE0
D+ Pin IDPSRC Output Control
0: Stop
1: 10 μA output.
R/W
b2
IDMSINKE0
D- Pin 0.6 V Input Detection
(Comparator and Sink) Control
0: Detection off
1: Detection on (comparator and sink current on).
R/W
b3
VDPSRCE0
D+ Pin VDPSRC (0.6 V) Output
Control
0: Stop
1: 0.6 V output.
R/W
b4
IDPSINKE0
D+ Pin 0.6 V Input Detection
(Comparator and Sink) Control
0: Detection off
1: Detection on (comparator and sink current on).
R/W
b5
VDMSRCE0
D- Pin VDMSRC (0.6 V) Output
Control
0: Stop
1: 0.6 V output.
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
BATCHGE0
BC (Battery Charger) Function
General Enable Control
0: Disabled
1: Enabled.
R/W
b8
CHGDETSTS0
D- Pin 0.6 V Input Detection Status *1
0: Not detected
1: Detected.
R
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28. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b9
PDDETSTS0
D+ Pin 0.6 V Input Detection
Status *2
0: Not detected
1: Detected.
R
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b15 to b10
Note 1.
Note 2.
Valid when IDMSINKE0 = 1.
Valid when IDPSINKE0 = 1.
RPDME0 bit (D- Pin Pull-Down Control)
When using the battery charging function, set the RPDME0 bit to 1 to control the pull-down resistor of the D- pin.
IDPSRCE0 bit (D+ Pin IDPSRC Output Control)
With the IDPSRCE0 bit set to 1 in device controller mode, the current output is enabled on detection of the data
connection pin and the D+ pin is pulled up.
IDMSINKE0 bit (D- Pin 0.6 V Input Detection (Comparator and Sink) Control)
With the IDMSINKE0 bit set to 1 in device controller mode, the USBFS detects whether VDMSRC (0.6 V) that is output
from the host to D- on primary detection is connected, or whether VDPSRC (0.6 V) that is output from the function to
D+ is connected to the function of D- through the host.
VDPSRCE0 bit (D+ Pin VDPSRC (0.6 V) Output Control)
With the VDPSRCE0 bit set to 1 in device controller mode, output is enabled on primary detection and VDPSRC (0.6 V)
is applied to D+.
IDPSINKE0 bit (D+ Pin 0.6 V Input Detection (Comparator and Sink) Control)
With the IDPSINKE0 bit set to 1 in device controller mode, the USBFS detects whether VDMSRC (0.6 V) that is output
from the function to D- is connected to the function of D+ (DCP) through the host. In host controller mode, the USBFS
detects whether VDPSRC (0.6 V) that is output from the device to D+ on primary detection is connected.
VDMSRCE0 bit (D- Pin VDMSRC (0.6 V) Output Control)
With the VDMSRCE0 bit set to 1 in device controller mode, output is enabled on secondary detection and VDMSRC
(0.6 V) is applied to D-. In host controller mode, output is enabled on primary detection and VDMSRC (0.6 V) is applied
to D-.
CHGDETSTS0 flag (D- Pin 0.6 V Input Detection Status)
In host controller mode, the CHGDETSTS0 flag is set to 1 if the USBFS detects whether VDMSRC (0.6 V) that is output
from the host to D- on primary detection is connected, or whether VDPSRC (0.6 V) that is output from the function to
D+ is connected to the function of D- through the host.
PDDETSTS0 flag (D+ Pin 0.6 V Input Detection Status)
In device controller mode, the PDDETSTS0 flag is set to 1 if the USBFS detects whether VDMSRC (0.6 V) that is
output from the function to D- on secondary detection is connected to the function of D+ (DCP) through the host.
In host controller mode, this bit is set to 1 if the USBFS detects whether VDPSRC (0.6 V) that is output from the
function to D+ on primary detection is connected.
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28.3
28. USB 2.0 Full-Speed Module (USBFS)
Operation
28.3.1
System Control
This section describes register settings required for initializing the USBFS and controlling power consumption.
28.3.1.1
Setting data to the USB-related register
Setting the SYSCFG.USBE bit to 1 after starting the clock supply (SYSCFG.SCKE bit = 1) enables and starts USBFS
operation.
28.3.1.2
Selecting the controller function
The USBFS can operate as either a host or device controller.
Use the SYSCFG.DCFM bit to select one of these USBFS functions. The DCFM bit must be changed in the initial
settings immediately after a reset or in the D+ pull-up-disabled state (SYSCFG.DPRPU bit = 0) and D+ and D- pulldown-disabled state (SYSCFG.DRPD bit = 0).
28.3.1.3
Controlling the USB data bus using resistors
The USBFS provides pull-up and pull-down resistors for the D+ and D- lines. Pull these lines up or down by setting the
SYSCFG.DPRPU, DMRPU, and DRPD bits.
In device controller mode, confirm that connection to the USB host is made, and then set the SYSCFG.DPRPU bit to 1
and pull up the D+ line (in full-speed communication), or set the SYSCFG.DMRPU bit to 1 and pull up the D- line (in
low-speed communication).
When the SYSCFG.DPRPU (during full speed) or the SYSCFG.DMRPU (during low speed) bit is set to 0 during
communication with a PC, the USBFS disables the pull-up resistor of the USB data line, thereby notifying the USB host
of disconnection.
In host controller mode, set the SYSCFG.DRPD bit to 1 to pull down the D+ and D- lines.
Table 28.12
USB data bus resistor control
SYSCFG register settings
USB data bus control
DRPD bit
DPRPU bit
DMRPU bit
D–
D+
Function
0
0
0
Open
Open
When resistors not used
0
1
0
Open
Pull-up
When operating as the device controller at full-speed
0
0
1
Pull-up
Open
When operating as the device controller at low-speed
1
0
0
Pull-down
Pull-down
When operating as a host controller
-
-
Setting prohibited
Other settings
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28.3.1.4
28. USB 2.0 Full-Speed Module (USBFS)
Example of USB power supply connection
Figure 28.2 shows an example of power supply connection when the USB regulator is not used. Figure 28.3 and Figure
28.4 show examples of power supply connection when the USB regulator is used.
Input the same voltage as VCC to
VCC_USB_LDO and VCC_USB
VCC_
USB_LDO
VCC 3.0 V to 3.6 V
USB LDO
Regulator
VCC_USB
BC
Control
USB_DP
0
USB_DM
0
VDCEN
VDDUSBE
USB Module Control Register (USBMC)
USBFS
USB
Transceiver
Figure 28.2
MCU
Example of power supply connection when the USB LDO regulator is not used
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28. USB 2.0 Full-Speed Module (USBFS)
Input the same voltage as
VCC to VCC_USB_LDO
VCC 3.8 V to 5.5 V
VCC_USB_LDO
USB LDO
Regulator
*1
1.0 µF
VCC_USB
BC
Control
USB_DP
1
USB_DM
1
VDCEN
VDDUSBE
USB Module Control Register (USBMC)
USBFS
USB
Transceiver
MCU
Note 1. Make sure that the resistance of the connected wiring is 0.5 Ω or less to connect a capacitor of ESR ≤ 1 Ω.
Figure 28.3
Example of power supply connection when the USB LDO regulator is used (BC used)
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28. USB 2.0 Full-Speed Module (USBFS)
Input the same voltage as
VCC to VCC_USB_LDO
VCC_USB_LDO
USB LDO
Regulator
*1
1.0 µF
VCC 4.0 V to 5.5 V
VCC_USB
BC
Control
USB_DP
1
USB_DM
0
VDCEN
VDDUSBE
USB Module Control Register (USBMC)
USBFS
USB
Transceiver
MCU
Note 1. Make sure that the resistance of the connected wiring is 0.5 Ω or less to connect a capacitor of ESR ≤ 1 Ω.
Figure 28.4
Example of power supply connection when the USB LDO regulator is used (BC not used)
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28.3.1.5
28. USB 2.0 Full-Speed Module (USBFS)
Example of USB external connection circuits
The host recognizes a USB device when one of the data lines is pulled up. The MCU can use switching of the internal
pull-up resistor for this. Also, bus-powered devices do not require external regulators because the MCU provides a power
supply in the USB-PHY.
Figure 28.5 and Figure 28.6 show examples of external circuits for the USB connection.
Figure 28.5 shows an example of OTG connection of the USB connector in the self-powered state.
The USBFS controls the pull-up resistor of the D+ line and the pull-down resistor of D+ and D- lines. Select pull-up and
pull-down for the lines in the SYSCFG.DPRPU and SYSCFG.DRPD bits. In device controller mode, the pull-up resistor
of USB data line is disabled if SYSCFG.DPRPU bit is set to 0 while communicating with the USB host. The USBFS can
use this to notify the USB host of a device disconnect.
External connection
OTG power
supply IC
MCU
USB0_EXICEN
USB0_VBUSEN
USB0_OVRCURA
USB0_OVRCURB
USB0_ID
SHDN#
OFFVBUS#
STATUS1
STATUS2
ID_OUT
ID_IN
VBUS
USB transceiver
RPU
USB
AB connector
RPU
ID
VBUS
ZDRV
USB0_DP
USB0_DM
D+
D–
ZDRV
RPD
RPD
ZDRV: Output impedance
RPU: Pull-up resistor
RPD: Pull-down resistor
Figure 28.5
Example OTG connection in self-powered state
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28. USB 2.0 Full-Speed Module (USBFS)
Figure 28.6 shows an example of functional connection of the USB connector in the self-powered state.
External connection
MCU
USB_VBUS*1
1 M
100
*2
0.1 µF
USB
transceiver
RPU
RPU
VBUS
ZDRV
USB_DP
D+
USB_DM
D–
ZDRV
ZDRV: Output impedance
RPU: Pull-up resistor
Note 1.
Note 2.
Figure 28.6
USB_VBUS is 5 V tolerant.
Design the board so that the total VBUS capacitance ranges from 1.0 to 10 μF.
Example device connection in self-powered state
Figure 28.7 shows an example of host connection of the USB connector.
External connection
MCU
USB_VBUSEN
USB_OVRCURA
Non-OTG
power
supply IC
for USB
host*1
*1
VBUS
USB
A connector
USB
transceiver
ZDRV
USB_DP
USB_DM
ZDRV
RPD
At least 120 µF
VBUS
D+
D–
RPD
ZDRV: Output impedance
RPD: Pull-down resistor
Note 1.
Figure 28.7
When Battery Charging Specification Rev 1.2 is to be supported, ensure that the power supply IC and the VBUS wiring
width are enough for at least 1.5 A.
Example host connection
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28. USB 2.0 Full-Speed Module (USBFS)
Figure 28.8 shows an example of functional connection of the USB connector in bus-powered state.
External connection
USB
B connector
Each system power
supply (3.3 V)
MCU
System power
supply (3.3 V)
Regulator
*2
VBUS
USB_VBUS*1
USB
transceiver
RPU
RPU
ZDRV
USB_DP
D+
USB_DM
D–
ZDRV
ZDRV : Output impedance
RPU: Pull-up resistor
Note 1.
Note 2.
Figure 28.8
USB_VBUS is 5 V tolerant.
Design the board so that the total VBUS capacitance ranges from 1.0 to 10 μF.
Example device connection in bus-powered state 1
Figure 28.9 shows an example of functional connection of the USB connector in bus-powered state 2.
External connection
USB
B connector
MCU
*1
USB_VBUS
VBUS
USB
transceiver
RPU
ZDRV
RPU
USB_DP
USB_DM
D+
D–
ZDRV
ZDRV : Output impedance
RPU: Pull-up resistor
Note 1.
Note 2.
Figure 28.9
USB_VBUS is 5 V tolerant.
Design the board so that the total VBUS capacitance ranges from 1.0 to 10 µF.
Example device connection in bus-powered state 2
The examples of external circuits given in this section are simplified circuits, and their operation in every system is not
guaranteed.
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28. USB 2.0 Full-Speed Module (USBFS)
Figure 28.10 shows an example of functional connection of the USB connector with Battery Charging Rev 1.2
supported.
External connection
Charging IC
supporting Battery
Charging Spec 1.2
MCU
SCL0
SDA0
SCL0
Charging battery
SDA0
USB_VBUS*3
*1, *4
VBUS
10 k
*2
USB
transceiver
100
USB
B connector
0.1 µF
RPU
RPU
VBUS
ZDRV
USB_DP
USB_DM
D+
D–
ZDRV
ZDRV: Output impedance
RPU: Pull-up resistor
Note 1.
Note 2.
Note 3.
Note 4.
When Battery Charging Specification Rev 1.2 is to be supported, ensure that the VBUS wiring width is
enough for at least 1.5 A (shown in bold lines).
Use a resistor value such that the discharging time of VBUS is within 500 ms.
USB_VBUS is 5 V tolerant.
Design the board so that the total VBUS capacitance ranges from 1.0 to 10 µF.
Figure 28.10
Example of functional connection with Battery Charging Specification Rev 1.2 supported
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28.3.2
28. USB 2.0 Full-Speed Module (USBFS)
Interrupts
Table 28.13 lists the interrupt sources in the USBFS. When an interrupt generation condition is satisfied and the interrupt
output is enabled using the associated interrupt enable register, a USBFS interrupt request is issued to the Interrupt
Controller Unit (ICU) and an USBFS interrupt is generated.
Table 28.13
Interrupt sources (1 of 2)
Bit to be
set
Name
Interrupt source
Applicable
controller
function
VBINT
VBUS interrupt
A change in the state of the USB_VBUS input pin was
detected (low to high or high to low)
Host or
device*1
INTSTS0.VBSTS
RESM
Resume interrupt
A change in the state of the USB bus was detected in
the suspended state (J-state to K-state or J-state to
SE0).
Device
-
SOFR
Frame number
update interrupt
In host controller mode:
An SOF packet with a different frame number was
transmitted.
In device controller mode:
An SOF packet with a different frame number was
received.
Host or
device
-
DVST
Device state
transition interrupt
One of the following device state transitions was detected: Device
USB bus reset detected
Suspended state detected
SET_ADDRESS request received
SET_CONFIGURATION request received.
INTSTS0.DVSQ[2:0]
CTRT
Control transfer
stage transition
interrupt
A control transfer stage transition was detected because
of one of the following:
Setup stage completed
Control write transfer status stage transition occurred
Control read transfer status stage transition occurred
Control transfer completed
Control transfer sequence error occurred.
Device
INTSTS0.CTSQ[2:0]
BEMP
Buffer empty
interrupt
The buffer is empty after all FIFO buffer data was
transmitted
A packet larger than the maximum packet size was
received.
Host or
device
BEMPSTS.PIPEnBEMP
NRDY
Buffer not ready
interrupt
In host controller mode:
A STALL response was received from the peripheral
device in response to the issued token
The response from the peripheral device in response to
the issued token was not received successfully (no
response three times consecutively or packet reception
error three times consecutively)
An overrun or underrun error occurred during
isochronous transfer
In device controller mode:
NAK was returned for an IN or OUT token while the
PID[1:0] bits were set to 01b (BUF)
A CRC error or bit stuffing error occurred during data
reception in isochronous transfer
An overrun or underrun occurred during data reception
in isochronous transfer.
Host or
device
NRDYSTS.PIPEnNRDY
BRDY
Buffer ready
interrupt
The buffer is ready (read or write state).
Host or
device
BRDYSTS.PIPEnBRDY
OVRCR
Overcurrent input
change interrupt
USB_OVRCURA or USB_OVRCURB input pin state
change was detected (low to high or high to low).
Host
INTSTS1.OVRCR
BCHG
Bus change
interrupt
USB bus state change was detected.
Host or
device
SYSSTS0.LNST[1:0]
DTCH
Disconnection
Peripheral device disconnect was detected in full-speed
detection during fulloperation.
speed operation
Host
DVSTCTR0.RHST[2:0]
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Table 28.13
Bit to be
set
28. USB 2.0 Full-Speed Module (USBFS)
Interrupt sources (2 of 2)
Applicable
controller
function
Status flag
Name
Interrupt source
ATTCH
Device connection
detection
J-state or K-state was detected on the USB bus for
2.5 µs continuously
This interrupt can be used to check whether peripheral
devices are connected.
Host
-
EOFERR
EOF error detection
An EOF error was detected for a peripheral device.
Host
-
SACK
Normal setup
operation
A setup transaction normal response (ACK) was
received.
Host
-
SIGN
Setup error
A setup transaction error (no response or ACK packet
corruption) was detected three consecutive times.
Host
-
PDDEINT
0
Portable device
detection interrupt
A connection of the portable device was detected.
Host
INTSTS1.PDDETINT0
Note 1.
Although this interrupt can be generated in host controller mode, it is not usually used in this mode.
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28. USB 2.0 Full-Speed Module (USBFS)
Figure 28.11 shows the circuits related to the USBFS interrupts.
USBFS_USBR
USB bus reset detected
INTENB0
INTSTS0
VBSE
Set_Address detected
VBINT
Set_Configuration
detected
RSME
USBFS_USBI
RESM
SOFE
Suspended state detected
SOFR
Control Write Data Stage
DVSE
DVST
Control Read Data Stage
CTRE
CTRT
Control Transfer End
BEMPE
BEMP
Control Transfer Error
NRDYE
NRDY
Control Transfer Setup Receive
BRDYE
BRDY
Edge/level
detector
BEMP Interrupt Enable Register
OVRCRE
OVRCR
b9
b1
b0
BCHGE
b9
BCHG
DTCHE
BEMP Interrupt
Status Register
DTCH
ATTCHE
b1
ATTCH
b0
EOFERRE
EOFERR
NRDY Interrupt Enable Register
b9
SIGNE
b1
b0
SIGN
SACKE
b9
SACK
NRDY Interrupt
Status Register
PDDETINTE0
PDDETINT0
INTENB1
b1
INTSTS1
b0
BRDY Interrupt Enable Register
D0FIFOSEL
b9
b1
b0
DREQE
DMA/DTC
transfer
request 0
USBFS_D0FIFO
b9
BRDY Interrupt
Status Register
D1FIFOSEL
b1
DREQE
USBFS_D1FIFO
Figure 28.11
DMA/DTC
transfer
request 1
b0
USBFS interrupt-related circuits
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28. USB 2.0 Full-Speed Module (USBFS)
Table 28.14 shows the interrupts generated by the USBFS.
Table 28.14
USBFS interrupts
Interrupt
name
Interrupt status flag
DTC
activation
DMAC
activation
D0FIFO
DMA transfer request 0
Possible
Possible
D1FIFO
DMA transfer request 1
Possible
Possible
USBFS_USBI
VBUS interrupt, resume interrupt, frame number update interrupt, device
state transition interrupt, control transfer stage transition interrupt, buffer
empty interrupt, buffer not ready interrupt, buffer ready interrupt,
overcurrent input change interrupt, bus change interrupt, disconnection
detection during full-speed operation, device connection detection, EOF
error detection, normal setup operation, setup error, and portable device
detection interrupt
Not possible
Not possible
USBFS_USBR
VBUS interrupt, resume interrupt, overcurrent input change interrupt, and
portable device detection interrupt
Not possible
Not possible
28.3.3
28.3.3.1
Priority
High
Low
-
Interrupt Descriptions
BRDY interrupt
The BRDY interrupt is generated in both host and device controller modes. This section describes the conditions in
which the USBFS sets the associated bit in BRDYSTS to 1. Under these conditions, the USBFS generates a BRDY
interrupt if software has set the bit in BRDYENB associated with the given pipe to 1 and the INTENB0.BRDYE bit to 1.
The conditions for generating and clearing the BRDY interrupt depend on the SOFCFG.BRDYM and PIPECFG.BFRE
settings for each pipe as follows:
(1)
When SOFCFG.BRDYM = 0 and PIPECFG.BFRE = 0
With these settings, the BRDY interrupt indicates that the FIFO port is accessible.
On any of the following conditions, the USBFS generates an internal BRDY interrupt request trigger and sets the
BRDYSTS.PIPEnBRDY bit associated with the selected pipe to 1.
(a)
For transmitting pipes
When the DIR bit is changed from 0 to 1 by software
When packet transmission is complete for a pipe while write-access from the CPU to the FIFO buffer for the pipe is
disabled (when the BSTS bit is read as 0)
When one FIFO buffer is empty on completion of writing data to the other FIFO buffer in double buffer mode
No request trigger is generated until completion of writing data to the currently-written FIFO buffer even if
transmission to the other FIFO buffer is complete
When the hardware flushes the buffer of the pipe for isochronous transfers
When 1 is written to the PIPEnCTR.ACLRM bit, which causes the FIFO buffer to transition from the write-disabled
to write-enabled state.
No request trigger is generated for the DCP, that is, during data transmission for control transfers.
(b)
For receiving pipes
When packet reception is successfully complete, enabling the FIFO buffer to be read while read-access from the
CPU to the FIFO buffer for the given pipe is disabled (when the BSTS bit is read as 0). No request trigger is
generated for transactions in which a DATA-PID mismatch has occurred.
When one FIFO buffer is read-enabled on completion of reading data from the other FIFO buffer in double buffer
mode. No request trigger is generated until completion of reading data from the currently-read FIFO buffer, even if
reception by the other FIFO buffer is complete.
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28. USB 2.0 Full-Speed Module (USBFS)
In device controller mode, the BRDY interrupt is not generated in the status stage of control transfers. The PIPEnBRDY
interrupt status of the selected pipe can be set to 0 by writing 0 to the associated PIPEnBRDY bit through software. In
this case, the other PIPEnBRDY bits must be set to 1.
Clear the BRDY status before accessing the FIFO buffer.
(2)
When SOFCFG.BRDYM = 0 and PIPECFG.BFRE = 1
With these settings, the USBFS generates a BRDY interrupt on completion of reading all data for a single transfer using
the receiving pipe, and sets the bit in BRDYSTS associated with the pipe to 1.
On any of the following conditions, the USBFS determines that the last data for a single transfer was received:
When a short packet including a zero-length packet is received
When the PIPEn Transaction Counter Register (PIPEnTRN) is used and the number of packets specified in the
PIPEnTRN.TRNCNT[15:0] bits are completely received.
When the data is completely read after any of the above conditions is satisfied, the USBFS determines that all data for a
single transfer is completely read.
When a zero-length packet is received while the FIFO buffer is empty, the USBFS determines that all data for a single
transfer is completely read when the FRDY bit in the FIFO Port Control Register is 1 and the DTLN[8:0] bits are 0. In
this case, to start the next transfer, write 1 to the BCLR bit in the associated port control register through software. With
these settings, the USBFS does not detect a BRDY interrupt for the transmitting pipe.
The PIPEnBRDY interrupt status of a pipe can be set to 0 by writing 0 to the associated BRDYSTS.PIPEnBRDY bit
through software. In this case, the other PIPEnBRDY bits must be set to 1.
In this mode, do not change the PIPECFG.BFRE bit setting until all data for a single transfer is processed. When it is
required to change the PIPECFG.BFRE bit before completion of processing, all FIFO buffers for the pipe must be cleared
using the PIPEnCTR.ACLRM bit.
(3)
When SOFCFG.BRDYM = 1 and PIPECFG.BFRE = 0
With these settings, the BRDYSTS.PIPEnBRDY values are linked to the BSTS bit setting for each pipe. In other words,
the BRDY interrupt status bits (PIPEnBRDY) are set to 1 or 0 by the USB depending on the FIFO buffer status.
(a)
For transmitting pipes
The BRDY interrupt status bits are set to 1 when the FIFO buffer is ready for write access, and are set to 0 when it is not
ready. The BRDY interrupt is not generated for the DCP in the transmitting direction even when it is ready for write
access.
(b)
For receiving pipes
The BRDY interrupt status bits are set to 1 when the FIFO buffer is ready for read access, and are set to 0 when all data
is read (not ready for read access).
When a zero-length packet is received while the FIFO buffer is empty, the associated bit is set to 1 and the BRDY
interrupt is continuously generated until software writes 1 to BCLR. With this setting, the PIPEnBRDY bit cannot be set
to 0 by software.
When the SOFCFG.BRDYM bit is set to 1, set the PIPECFG.BFRE bit for all pipes to 0.
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28. USB 2.0 Full-Speed Module (USBFS)
Figure 28.12 shows the timing of BRDY interrupt generation.
(1) Example of zero-length packet reception or data packet reception when BFRE = 0 (single-buffer mode)
*1
Data Packet
Token Packet
USB bus
ACK Handshake
Ready for reception
FIFO buffer status
Ready for read access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
A BRDY interrupt is generated because the
FIFO buffer becomes ready for read access.*2
(2) Example of data packet reception when BFRE = 1 (single-buffer mode)
USB bus
Token Packet
Data Packet
ACK Handshake
*1
Ready for reception
FIFO buffer status
Ready for read access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
The FIFO buffer becomes
ready for read access.*2
A BRDY interrupt is generated
because the transfer has ended.*3
(3) Example of packet transmission (single-buffer mode)
*1
USB bus
Token Packet
Data Packet
Ready for transmission
FIFO buffer status
ACK Handshake
Ready for write access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
A BRDY interrupt is generated
because the FIFO buffer
becomes ready for write access.
Packet transmitted by host device
Note 1.
Note 2.
Note 3.
Packet transmitted by function device
The ACK handshake is not used in isochronous transfers.
The FIFO buffer becomes ready for read access under the following condition:
When a packet is received while no data remains unread in the FIFO buffer in the CPU.
A transfer ends under either of the following conditions:
(1) When a short packet including a zero-length packet is received.
(2) When the number of packets specified in the transaction counter are received.
Figure 28.12
Timing of BRDY interrupt generation
The condition for clearing the INTSTS0.BRDY bit depends on the SOFCFG.BRDYM bit setting, as shown in Table
28.15.
Table 28.15
Conditions for clearing BRDY bit
BRDYM bit
Condition for clearing BRDY bit
0
When all bits in BRDYSTS are set to 0 by software
1
When the BSTS bits for all pipes become 0
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28.3.3.2
28. USB 2.0 Full-Speed Module (USBFS)
NRDY interrupt
On generating an internal NRDY interrupt request for the pipe whose PID bits are set to BUF by software, the USBFS
sets the associated PIPEnNRDY bit in NRDYSTS to 1. If the associated bit in NRDYENB is set to 1 by software, the
USBFS sets the INTSTS0.NRDY bit to 1 and generates a USBFS interrupt.
This section describes the conditions in which the USBFS generates the internal NRDY interrupt request for a given
pipe.
The internal NRDY interrupt request is not generated during setup transaction execution in host controller mode. During
setup transactions in host controller mode, the SACK or SIGN interrupt is detected.
The internal NRDY interrupt request is not generated during status stage execution of the control transfer in device
controller mode.
(1)
In host controller mode
(a)
For transmitting pipes
On any of the following conditions, the USBFS detects an NRDY interrupt:
For isochronous transfer pipes, when the time to issue an OUT token comes while there is no data to be transmitted
in the FIFO buffer. In this case, the USBFS transmits a zero-length packet following the OUT token and sets the
associated NRDYSTS.PIPEnNRDY bit and the FRMNUM.OVRN bit to 1.
During communications other than setup transactions on pipes not used for isochronous transfers, when any
combinations of the following two cases occur three consecutive times:
No response is returned from the peripheral device (when timeout is detected before detection of the handshake
packet from the peripheral device
An error is detected in the packet from the peripheral device. In this case, the USBFS sets the associated
PIPEnNRDY bit to 1 and changes the associated PID[1:0] setting for the pipe to NAK.
During communications other than setup transactions, when the STALL handshake is received from the peripheral
device. In this case, the USBFS sets the associated PIPEnNRDY bit to 1 and changes the PID[1:0] setting for the
associated pipe to STALL (11b).
(b)
For receiving pipes
For isochronous transfer pipes, when the time to issue an IN token comes but there is no space available in the FIFO
buffer. In this case, the USBFS discards the received data for the IN token and sets the PIPEnNRDY bit associated
with the pipe and the OVRN bit to 1. When a packet error is detected in the received data for the IN token, the
USBFS also sets the FRMNUM.CRCE bit to 1.
For non-isochronous transfer pipes, when any combination of the following two cases occur three consecutive
times:
No response is returned from the peripheral device for the IN token issued by the USBFS (when timeout is
detected before detection of the DATA packet from the peripheral device)
An error is detected in the packet from the peripheral device. In this case, the USBFS sets the associated
PIPEnNRDY bit to 1 and changes the associated PID[1:0] setting for the pipe to NAK.
For isochronous transfer pipes, when no response is returned from the peripheral device for the IN token (when
timeout is detected before detection of the DATA packet from the peripheral device) or an error is detected in the
packet from the peripheral device. In this case, the USBFS sets the PIPEnNRDY bit associated with the pipe to 1.
The PID[1:0] setting for the pipe is not changed.
For isochronous transfer pipes, when a CRC error or a bit stuffing error is detected in the received data packet. In
this case, the USBFS sets the PIPEnNRDY bit associated with the pipe and the CRCE bit to 1.
When the STALL handshake is received. In this case, the USBFS sets the PIPEnNRDY bit associated with the pipe
to 1 and changes the PID[1:0] setting for the associated pipe to STALL.
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28. USB 2.0 Full-Speed Module (USBFS)
(2)
In device controller mode
(a)
For transmitting pipes
When an IN token is received while there is no data to be transmitted in the FIFO buffer. In this case, the USBFS
generates a NRDY interrupt request on reception of the IN token and sets the NRDYSTS.PIPEnNRDY bit to 1. For
an isochronous transfer pipe in which an interrupt is generated, the USBFS transmits a zero-length packet and sets
the FRMNUM.OVRN bit to 1.
(b)
For receiving pipes
When an OUT token is received but there is no space available in the FIFO buffer. For an isochronous transfer pipe
in which an interrupt is generated, the USBFS generates a NRDY interrupt request on reception of the OUT token
and sets the PIPEnNRDY bit to 1 and OVRN bit to 1. For a non-isochronous transfer pipe in which an interrupt is
generated, the USBFS generates a NRDY interrupt request when a NAK handshake is transferred after the data
following the OUT token is received, and sets the PIPEnNRDY bit to 1. The NRDY interrupt request is not
generated during retransmission because of a DATA-PID mismatch. In addition, the NRDY interrupt request is not
generated if an error occurs in the DATA packet.
For isochronous transfer pipes, when a token is not received successfully within an interval frame. In this case, the
USBFS generates an NRDY interrupt request when the SOF is received, and sets the PIPEnNRDY bit to 1.
Figure 28.13 shows the timing of NRDY interrupt generation when the device controller is selected.
(1) Example of data transmission (single-buffer mode)
*1
IN token packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
NAK handshake
Ready for write access (there is no data to be transmitted)
*3
An NRDY interrupt is generated
(2) Example of data reception: OUT token reception (single-buffer mode)
*1
OUT token packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
Data packet
NAK handshake
Ready for read access (there is no space to receive data)
*3
(CRCE bit)*2
An NRDY interrupt is generated
(3) Example of data reception: PING token reception (single-buffer mode)
PING packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
NAK handshake
Ready for read access (there is no space to receive data)
*3
An NRDY interrupt is generated
Packet transmitted by host device
Note 1.
Note 2.
Note 3.
Packet transmitted by function device
The handshake is not used in isochronous transfers.
The CRCE and OVRN bits change only while the target pipe is set to isochronous transfers.
The value of the PIPEnNRDY bit changes to 1 only when the PIPEnPID[1:0] bits are set to 01b (BUF response).
Figure 28.13
Timing of NRDY interrupt generation in device controller mode
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28.3.3.3
28. USB 2.0 Full-Speed Module (USBFS)
BEMP interrupt
On detecting a BEMP interrupt for the pipe whose PID bits are set to BUF by software, the USBFS sets the associated
BEMPSTS.PIPEnBEMP bit to 1. If the associated bit in BEMPENB is set to 1 by software, the USBFS sets the
INTSTS0.BEMP bit to 1 and generates a USBFS interrupt. This section describes the conditions in which the USBFS
generates an internal BEMP interrupt request.
(1)
For transmitting pipes
When the FIFO buffer of the associated pipe is empty on completion of transmission, including zero-length packet
transmission, and in single buffer mode, an internal BEMP interrupt request is generated simultaneously with the BRDY
interrupt for a non-DCP pipe. The internal BEMP interrupt request is not generated on any of the following conditions:
When the CPU or DMA/DTC has already started writing data to the FIFO buffer of the CPU on completion of
transmitting data from one FIFO buffer in double buffer mode
When the buffer is cleared (emptied) by setting the PIPEnCTR.ACLRM or the BCLR bit to 1 in the port control
register
When an IN transfer (zero-length packet transmission) is performed during the control transfer status stage in device
controller mode.
(2)
For receiving pipes
When a successfully-received data packet size exceeds the specified maximum packet size. In this case, the USBFS
generates a BEMP interrupt request, sets the associated BEMPSTS.PIPEnBEMP bit to 1, discards the received data, and
changes the associated PID[1:0] setting for the pipe to STALL (11b). The USBFS returns no response in host controller
mode, and returns STALL response in device controller mode.
The internal BEMP interrupt request is not generated in any of the following conditions:
When a CRC error or a bit stuffing error is detected in the received data
When a setup transaction is performed:
Writing 0 to the BEMPSTS.PIPEnBEMP bit clears the status
Writing 1 to the BEMPSTS.PIPEnBEMP bit has no effect.
Figure 28.14 shows the timing of BEMP interrupt generation in device controller mode.
(1) Example of data transmission
USB bus
*1
IN token packet
Data packet
ACK handshake
Ready for transmission
FIFO buffer status
Ready for write access
(there is no data to be
transmitted)
BEMP interrupt
(BEMPSTS.PIPEnBEMP bit)
A BEMP interrupt is generated
(2) Example of data reception
OUT token packet
USB bus
Data packet (maximum
packet size over)
STALL handshake
BEMP interrupt
(BEMPSTS.PIPEnBEMP bit)
A BEMP interrupt is generated
Packet transmitted by host device
Note 1.
Packet transmitted by function device
The handshake is not used in isochronous transfers.
Figure 28.14
Timing of BEMP interrupt generation in device controller mode
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28.3.3.4
28. USB 2.0 Full-Speed Module (USBFS)
Device state transition interrupt (device controller mode)
Figure 28.15 shows a diagram of the USBFS device state transitions. The USBFS controls device states and generates
device state transition interrupts. However, recovery from the suspended state (resume signal detection) is detected by
means of the resume interrupt. Device state transition interrupts can be enabled or disabled independently in INTENB0.
Devices whose states have changed can be checked in the INTSTS0.DVSQ[2:0] bits.
When a transition is made to the default state, a device state transition interrupt is generated after a USB bus reset is
detected.
The USBFS controls device states, and device state transition interrupts can be generated, only in device controller
mode.
Suspended state detection
(DVST is set to 1)
Powered
state
(DVSQ = 000b)
Suspended
state
(DVSQ = 100b)
Resume (RESM is set to 1)
USB bus reset detection
(DVST is set to 1)
USB bus reset detection
(DVST is set to 1)
Suspended state detection
(DVST is set to 1)
Default
state
(DVSQ = 001b)
Suspended
state
(DVSQ = 101b)
Resume (RESM is set to 1)
SetAddress
execution
(Address = 0)
(DVST is set to 1)
(Address > 0)
SetAddress execution
(DVST is set to 1)
Suspended state detection
(DVST is set to 1)
Suspended
state
(DVSQ = 110b)
Address
state
(DVSQ = 010b)
SetConfiguration
execution
(configuration value = 0)
(DVST is set to 1)
Resume (RESM is set to 1)
SetConfiguration execution
(configuration value 0)
(DVST is set to 1)
Suspended state detection
(DVST is set to 1)
Suspended
state
(DVSQ = 111b)
Configured
state
(DVSQ = 011b)
Resume (RESM is set to 1)
Note:
Figure 28.15
For a transition indicated by a solid line, the DVST bit is set to 1.
For a resume indicated by a dashed line, the RESM bit is set to 1.
Device state transitions
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28.3.3.5
28. USB 2.0 Full-Speed Module (USBFS)
Control transfer stage transition interrupt (device controller mode)
Figure 28.16 shows a diagram of the control transfer stage transitions of the USBFS. The USBFS controls the control
transfer sequence and generates control transfer stage transition interrupts. Control transfer stage transition interrupts can
be enabled or disabled independently in INTENB0. Transfer stages that have transitioned can be checked in the
INTSTS0.CTSQ[2:0] bits.
Control transfer stage transition interrupts are generated only in device controller mode. This section describes control
transfer sequence errors. If an error occurs, the DCPCTR.PID[1:0] bits are set to 1xb (STALL response).
(1)
Control read transfer errors
An OUT token is received but no data is transferred in response to the IN token at the data stage
An IN token is received at the status stage
A data packet with DATAPID = DATA0 is received at the status stage.
(2)
Control write transfer errors
An IN token is received but no ACK is returned in response to the OUT token at the data stage
A data packet with DATAPID = DATA0 is received as the first data packet at the data stage
An OUT token is received at the status stage.
(3)
Control write no data transfer errors
An OUT token is received at the status stage.
At the control write transfer data stage, if the receive data length exceeds the wLength value of the USB request, it is not
recognized as a control transfer sequence error. At the control read transfer status stage, packets other than zero-length
packets are received by an ACK response and the transfer ends normally.
When a CTRT interrupt occurs in response to a sequence error (INTSTS0.CTRT = 1), the CTSQ[2:0] = 110b value is
saved until the CTRT bit is set to 0, clearing the interrupt status. While CTSQ[2:0] = 110b is being saved, no CTRT
interrupt for ending the setup stage is generated, even if a new USB request is received. The USBFS saves the setup stage
completion status, and it generates a CTRT interrupt after the interrupt status is cleared by software.
Setup token reception
Setup token reception
CTSQ = 110b
control transfer
sequence error
5
Error
detection
Error detection and setup token
reception are valid at all stages
in the box.
Setup
token reception
CTSQ = 000b
setup stage
ACK
transmission
1
CTSQ = 001b
control read
data stage
OUT token
2
CTSQ = 010b
control read
status stage
ACK
transmission
4
CTSQ = 000b
idle stage
4
ACK
transmission
1
CTSQ = 011b
control write
data stage
IN token
3
CTSQ = 100b
control write
status stage
1
CTSQ = 101b
no data control
status stage
ACK
transmission
ACK
reception
ACK
reception
Note:
CTRT interrupts
1 Setup stage completed
2 Control read transfer status stage transition
3 Control write transfer status stage transition
4 Control transfer completed
5 Control transfer sequence error
Figure 28.16
Control transfer stage transitions
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28.3.3.6
28. USB 2.0 Full-Speed Module (USBFS)
Frame update interrupt
In host controller mode, an interrupt is generated when the frame number is updated.
In device controller mode, an SOFR interrupt is generated when the frame number is updated. The USBFS updates the
frame number and generates an SOFR interrupt if it detects a new SOF packet during full-speed operation.
28.3.3.7
VBUS interrupt
When the USB_VBUS pin level changes, a VBUS interrupt is generated. The level of the USB_VBUS pin can be
checked with the INTSTS0.VBSTS bit. Whether the host controller is connected or disconnected can be confirmed using
the VBUS interrupt. If the system is activated with the host controller connected, the first VBUS interrupt is not
generated, because there is no change in the USB_VBUS pin level.
28.3.3.8
Resume interrupt
In device controller mode, a resume interrupt is generated when the device state is the Suspend state and the USB bus
state has changed (from J-state to K-state, or from J-state to SE0). Recovery from the Suspend state is detected by means
of the resume interrupt.
In host controller mode, no resume interrupt is generated. Use the BCHG interrupt to detect a change in the USB bus
state.
28.3.3.9
OVRCR interrupt
An OVRCR interrupt is generated when the USB_OVRCURA or USB_OVRCURB pin level has changed. The levels of
the USB_OVRCURA and USB_OVRCURB pins can be checked in the SYSSTS0.OVCMON[1:0] bits. The external
power supply IC can check whether overcurrent is detected using the OVRCR interrupt.
For OTG connections, the OVRCR interrupt allows you to check whether a change is detected in the VBUS comparator.
28.3.3.10
BCHG interrupt
A BCHG interrupt is generated when the USB bus state has changed. The BCHG interrupt can be used to detect whether
a peripheral device is connected and can also be used to detect a remote wakeup in host controller mode. The BCHG
interrupt is generated in both host and device controller modes.
28.3.3.11
DTCH interrupt
A DTCH interrupt is generated when a USB bus disconnect is detected in host controller mode. The USBFS detects bus
disconnects in compliance with the USB 2.0 specification.
On interrupt detection, all pipes in which communications being are carried out for the relevant port must be terminated
by software. The pipes enter the wait state for a bus connection to the port, waiting for an ATTCH interrupt to occur.
Regardless of the value set in the associated interrupt enable bit, the USBFS hardware:
Sets the DVSTCTR0.UACT bit for the port in which the DTCH interrupt is detected to 0
Puts the port in which the DTCH interrupt occurred into the idle state.
28.3.3.12
SACK interrupt
A SACK interrupt is generated when an ACK response for the transmitted setup packet is received from the peripheral
device in host controller mode. The SACK interrupt can be used to confirm that the setup transaction is successfully
complete.
28.3.3.13
SIGN interrupt
A SIGN interrupt is generated when an ACK response for the transmitted setup packet is not correctly received from the
peripheral device three consecutive times in host controller mode. The SIGN interrupt can be used to detect no ACK
response transmitted from the peripheral device or the corruption of an ACK packet.
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28.3.3.14
28. USB 2.0 Full-Speed Module (USBFS)
ATTCH interrupt
An ATTCH interrupt is generated when J-state or K-state of the full-speed signal level is detected on the USB port for
2.5 μs in host controller mode. More specifically, an ATTCH interrupt is detected on any of the following conditions:
When K-state, SE0, or SE1 changes to J-state, and J-state continues 2.5 µs
When J-state, SE0, or SE1 changes to K-state, and K-state continues 2.5 µs.
28.3.3.15
EOFERR interrupt
An EOFERR interrupt occurs when the USBFS detects that communication is not complete at the EOF2 timing defined
in the USB 2.0 specification.
On interrupt detection, all pipes in which communications are being carried out for the relevant port must be terminated
by software, and the port must be re-enumerated. Regardless of the value set in the associated interrupt enable bit, the
USBFS hardware:
Sets the DVSTCTR0.UACT bit for the port in which the EOFERR interrupt is detected to 0
Puts the port in which the EOFERR interrupt is generated into the idle state.
28.3.3.16
Portable device detection interrupt
A portable device detection interrupt is generated when the USBFS detects a level change (high to low or low to high) in
the PDDET output from the USB-PHY. When a portable device detection interrupt is generated, use software to repeat
the reading of the PDDETSTS0 bit until the same value is read three or more times to debounce the signal.
28.3.4
Pipe Control
Table 28.16 lists the pipe settings for the USBFS. USB data transfer is performed through logical pipes that software
associates with endpoints. The USBFS provides 10 pipes that are used for data transfer. Set up the pipes based on your
system specifications.
Table 28.16
Register
name
DCPCFG
PIPECFG
DCPMAXP
PIPEMAXP
PIPEPERI
Pipe settings (1 of 2)
Bit name
Setting
Remarks
TYPE
Transfer type
Pipes 1 to 9: Settable
BFRE
BRDY interrupt mode
Pipes 1 to 5: Settable
DBLB
Double buffer select
Pipes 1 to 5: Settable
DIR
Transfer direction select
IN or OUT settable
EPNUM
Endpoint number
Pipes 1 to 9: Settable
A value other than 0000b must be set when the pipe is used.
SHTNAK
Disabled state select for
pipe when transfer ends
Pipes 1 and 2: Settable only for bulk transfers
Pipes 3 to 5: Settable
DEVSEL
Device select
Referenced only in host controller mode
MXPS
Maximum packet size
Compliant with the USB 2.0 specification
IFIS
Buffer flush
Pipes 1 and 2: Settable only for isochronous transfers
Pipes 3 to 9: Setting disabled
IITV
Interval counter
Pipes 1 and 2: Settable only for isochronous transfers
Pipes 3 to 5: Setting disabled
Pipes 6 to 9: Settable only in host controller mode
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Table 28.16
Register
name
DCPCTR
PIPEnCTR
PIPEnTRE
PIPEnTRN
28.3.4.1
28. USB 2.0 Full-Speed Module (USBFS)
Pipe settings (2 of 2)
Bit name
Setting
Remarks
BSTS
Buffer status
For the DCP, receive buffer status and transmit buffer status are switched
with the ISEL bit
INBUFM
IN buffer monitor
Available only for pipes 1 to 5
SUREQ
Setup request
Settable only for the DCP and controlled in host controller mode
SUREQCLR
SUREQ clear
Settable only for the DCP and controlled in host controller mode
ATREPM
Auto response mode
Pipes 1 to 5: Settable only in device controller mode
ACLRM
Auto buffer clear
Pipes 1 to 9: Settable
SQCLR
Sequence clear
Clears the data toggle bit
SQSET
Sequence set
Sets the data toggle bit
SQMON
Sequence monitor
Monitors the data toggle bit
PBUSY
Pipe busy status
-
PID
Response PID
See section 28.3.4.6, Response PID
TRENB
Transaction counter enable
Pipes 1 to 5: Settable
TRCLR
Current transaction counter
clear
Pipes 1 to 5: Settable
TRNCNT
Transaction counter
Pipes 1 to 5: Settable
Pipe control register switching procedures
The following bits in the pipe control registers can be changed only when USB communication is prohibited (PID =
NAK).
Do not change the following registers and bits when USB communication is enabled (PID = BUF):
Bits in DCPCFG and DCPMAXP
SQCLR and SQSET bits in DCPCTR
Bits in PIPECFG, PIPEMAXP, and PIPEPERI
ATREPM, ACLRM, SQCLR, and SQSET bits in PIPEnCTR
Bits in PIPEnTRE and PIPEnTRN.
To set these bits when USB communication is enabled (PID = BUF):
1. A request to change the bits in the pipe control register occurs.
2. Set the PID[1:0] bits associated with the pipe to NAK.
3. Wait until the associated PBUSY bit sets to 0.
4. Set the bits in the pipe control register.
The following bits in the pipe control registers can be changed only when the selected pipe information has not been set
in the CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL.
Do not set the following registers when the CURPIPE[3:0] bits are set:
Bits in DCPCFG and DCPMAXP
Bits in PIPECFG, PIPEMAXP and PIPEPERI.
To change pipe information, you must set the CURPIPE[3:0] bits in the port select registers to a pipe other than the one
to be changed. For the DCP, the buffer must be cleared using the BCLR bit in the Port Control Register after the pipe
information is changed.
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28.3.4.2
28. USB 2.0 Full-Speed Module (USBFS)
Transfer types
The PIPECFG.TYPE[1:0] bits specify the following transfer types for each pipe:
DCP: No setting is required (fixed at control transfer)
Pipes 1 and 2: Set to bulk or isochronous transfer
Pipes 3 to 5: Set to bulk transfer
Pipes 6 to 9: Set to interrupt transfer.
28.3.4.3
Endpoint number
The PIPECFG.EPNUM[3:0] bits are used to set the endpoint number for each pipe. The DCP is fixed at endpoint 0. The
other pipes can be set from endpoint 1 to 15.
DCP: No setting is required (fixed at endpoint 0)
Pipes 1 to 9: Select and set the endpoint numbers from 1 to 15 so that the combination of the PIPECFG.DIR and
EPNUM[3:0] bits is unique.
28.3.4.4
Maximum packet size setting
Specify the maximum packet size for each pipe in the DCPMAXP.MXPS[6:0] and PIPEMAXP.MXPS[8:0] bits. The
DCP and pipes 1 to 5 can be set to any of the maximum pipe sizes defined in the USB 2.0 specification. For pipes 6 to 9,
the maximum packet size is 64 bytes. Set the maximum packet size as follows before starting a transfer (PID = BUF):
DCP: Set to 8, 16, 32, or 64
Pipes 1 to 5: Set to 8, 16, 32, or 64 for bulk transfers
Pipes 1 and 2: Set between 1 and 256 for isochronous transfers
Pipes 6 to 9: Set between 1 and 64.
28.3.4.5
Transaction counter for pipes 1 to 5 in the receiving direction
When the specified number of transactions is complete in the data packet receiving direction, the USBFS recognizes that
the transfer ended. Two transaction counters are provided: one is the PIPEnTRN register that specifies the number of
transactions to be executed, and the other is the current counter that internally counts the number of executed
transactions. If the PIPECFG.SHTNAK bit is set to 1, when the current counter value matches the specified number of
transactions, the associated PIPEnCTR.PID[1:0] bits are set to NAK and the subsequent transfer is disabled. The
transactions can be counted again from the beginning by initializing the current counter of the transaction counter
function through the PIPEnTRE.TRCLR bit. The data read from PIPEnTRN differs depending on the
PIPEnTRE.TRENB setting as follows:
The TRENB bit = 0: Specified transaction counter value can be read
The TRENB bit = 1: Current counter value indicating the internally counted number of executed transactions can be
read.
The following restrictions apply when working with the TRCLR bit:
If the transactions are being counted and PID = BUF, the current counter cannot be cleared
If there is any data left in the buffer, the current counter cannot be cleared.
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28.3.4.6
28. USB 2.0 Full-Speed Module (USBFS)
Response PID
Specify the response PID for each pipe in the PID[1:0] bits in DCPCTR and PIPEnCTR. This section describes the
USBFS operation with different response PID settings.
(1)
Software response PID settings in host controller mode
Select the response PID to specify the execution of transactions as follows:
NAK setting: Using pipes is disabled and no transactions are executed
BUF setting: Transactions are executed based on the FIFO buffer state:
OUT direction: An OUT token is issued if the FIFO buffer contains transmit data
IN direction: An IN token is issued if the FIFO buffer is not full and can receive data.
STALL setting: Using pipes is disabled and no transactions are executed.
Note:
(2)
Use the DCPCTR.SUREQ bit to execute setup transactions for the DCP.
Software response PID settings in device controller mode
Select the response PID to respond as follows to transactions from the host:
NAK setting: A NAK response is returned to all generated transactions
BUF setting: A response is returned to transactions based on the FIFO buffer
STALL setting: A STALL response is returned to all generated transactions.
Note:
For setup transactions, an ACK response is always returned, regardless of the PID[1:0] bits setting, and the USB
request is stored in the register.
Sections (3) and (4) describe situations in which the USBFS writes to the PID[1:0] bits because of specific transaction
results.
(3)
Hardware response PID settings in host controller mode
NAK setting: PID = NAK is set in the following cases, and issuing of tokens is automatically stopped:
When a non-isochronous transfer is performed and an NRDY interrupt is generated.
For details, see section 28.3.3.2, NRDY interrupt.
If a short packet is received when the PIPECFG.SHTNAK bit is set to 1 for bulk transfers
If transaction counting ends when the SHTNAK bit is set to 1 for bulk transfers.
BUF setting: The USBFS does not write this setting
STALL setting: PID = STALL is set in the following cases, and issuing of tokens is automatically stopped:
When STALL is received in response to a transmitted token
When a received data packet exceeds the maximum packet size.
(4)
Hardware response PID settings in device controller mode
NAK setting: PID = NAK is set in the following cases, and a NAK response is returned to transactions:
When the setup token is received normally (DCP only)
If transaction counting ends or a short packet is received when the PIPECFG.SHTNAK bit is set to 1 for bulk
transfers.
BUF setting: There is no BUF writing by the USBFS
STALL setting: PID = STALL is set in the following cases, and a STALL response is returned to transactions:
When a received data packet exceeds the maximum packet size
When a control transfer sequence error is detected (DCP only).
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28.3.4.7
28. USB 2.0 Full-Speed Module (USBFS)
Data PID sequence bit
The USBFS automatically toggles the sequence bit in the data PID when data is transferred successfully in the control
transfer data stage, bulk transfer, and interrupt transfer. The sequence bit of the next data PID to be transmitted can be
confirmed with the SQMON bit in DCPCTR and PIPEnCTR. When data is transmitted, the sequence bit toggles on ACK
handshake reception. When data is received, the sequence bit toggles on ACK handshake transmission. The SQCLR and
SQSET bits in DCPCTR and PIPEnCTR registers can be used to change the data PID sequence bit.
In device controller mode, when control transfers are used, the USBFS automatically sets the sequence bit for stage
transitions. DATA1 is returned when the setup stage ends. The sequence bit is not referenced and PID = DATA1 is
returned in the status stage. Therefore, no software settings are required. However, in host controller mode when control
transfers are used, the sequence bit must be set by software for the stage transitions.
For ClearFeature requests for transmission or reception, the data PID sequence bit must be set by software in both host
and device controller modes.
28.3.4.8
Response PID = NAK function
The USBFS provides a function for disabling pipe operation (PID response = NAK) when the final data packet of a
transaction is received. The USBFS automatically distinguishes this based on reception of a short packet or the
transaction counter. Enable this function by setting the PIPECFG.SHTNAK bit to 1.
When the double buffer mode is being used for the FIFO buffer, using this function enables reception of data packets in
transfer units. If pipe operation is disabled, software must enable the pipe again (PID response = BUF).
The response PID = NAK function can be used only for bulk transfers.
28.3.4.9
Auto response mode
For bulk transfer pipes (1 to 5), when the PIPEnCTR.ATREPM bit is set to 1, a transition is made to auto response mode.
During an OUT transfer (PIPECFG.DIR = 0), OUT-NAK mode is invoked, and during an IN transfer (DIR = 1), null auto
response mode is invoked.
28.3.4.10
OUT-NAK mode
For bulk OUT transfer pipes, NAK is returned in response to an OUT token, and an NRDY interrupt is output when the
PIPEnCTR.ATREPM bit is set to 1. To transition from normal mode to OUT-NAK mode, specify OUT-NAK mode while
pipe operation is disabled (PID[1:0] = 00b for NAK response). Next, enable pipe operation (PID[1:0] = 01b for BUF
response), on which OUT-NAK mode becomes valid. If an OUT token is received immediately before pipe operation is
disabled, the token data is normally received, and an ACK is returned to the host.
To transition from OUT-NAK mode to normal mode, cancel OUT-NAK mode while pipe operation is disabled (NAK).
Next, enable pipe operation (BUF). In normal mode, reception of OUT data is enabled.
28.3.4.11
Null auto response mode
For bulk IN transfer pipes, zero-length packets are continuously transmitted when the PIPEnCTR.ATREPM bit is set to
1.
To transition from normal mode to null auto response mode, specify null auto response mode while pipe operation is
disabled (response PID = NAK). Next enable pipe operation (response PID = BUF) on which null auto response mode
becomes valid. Before setting null auto response mode, check that PIPEnCTR.INBUFM = 0, because the mode can be
set only when the buffer is empty. If the INBUFM bit is 1, empty the buffer using the PIPEnCTR.ACLRM bit. Do not
write data from the FIFO port while a transition to null auto response mode is being made.
To transition from null auto response mode to normal mode, keep pipe operation disabled (response PID = NAK) for the
period of the zero-length packet transmission (about 10 µs) before canceling the null auto response mode. In normal
mode, data can be written from the FIFO port, so packet transmission to the host is enabled by enabling pipe operation
(response PID = BUF).
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28.3.5
28. USB 2.0 Full-Speed Module (USBFS)
FIFO Buffer Memory
The USBFS provides a FIFO buffer for data transfers, and it manages the memory area used for each pipe. The FIFO
buffer has two states depending on whether the access right is assigned to the system (CPU side) or the USBFS (SIE
side).
(1)
Buffer status
Table 28.17 and Table 28.18 show the buffer status in the USBFS. The FIFO buffer status can be confirmed using the
DCPCTR.BSTS and PIPEnCTR.INBUFM bits. The transfer direction for the FIFO buffer can be specified in either the
PIPECFG.DIR or CFIFOSEL.ISEL bit (when DCP is selected).
The INBUFM bit is valid for pipes 0 to 5 in the transmitting direction.
When a transmitting pipe uses double buffering, software can read the BSTS bit to monitor the FIFO buffer status on the
CPU side, and read the INBUFM bit to monitor the FIFO buffer status on the SIE side. When write access to the FIFO
port by the CPU or DMA/DTC is slow and the buffer empty status cannot be determined using the BEMP interrupt,
software can use the INBUFM bit to confirm the end of transmission.
Table 28.17
Buffer status indicated by BSTS bit
ISEL or DIR
BSTS
Buffer memory status
0 (receiving direction)
0
There is no received data, or data is being received.
Reading from the FIFO port is disabled.
0 (receiving direction)
1
There is received data, or a zero-length packet is received.
Reading from the FIFO port is allowed. When a zero-length packet is received, reading is not
possible and the buffer must be cleared.
1 (transmitting direction) 0
The transmission is not complete.
Writing to the FIFO port is disabled.
1 (transmitting direction) 1
The transmission is complete.
CPU write is allowed.
Table 28.18
Buffer status indicated by INBUFM bit
DIR
INBUFM
Buffer memory status
0 (receiving direction)
Invalid
Invalid
1 (transmitting direction)
0
The transmission is complete
There is no waiting data to be transmitted.
1 (transmitting direction)
1
The FIFO port has written data to the buffer.
There is data to be transmitted.
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28.3.6
28. USB 2.0 Full-Speed Module (USBFS)
FIFO Buffer Clearing
Table 28.19 shows the methods for clearing the FIFO buffer. The FIFO buffer can be cleared using BCLR in the port
control register, DnFIFOSEL.DCLRM, or the PIPEnCTR.ACLRM bit. Single or double buffering can be selected for
pipes 1 to 5 in the PIPECFG.DBLB bit.
Table 28.19
Buffer clearing methods
Mode for automatically clearing
the FIFO buffer after reading the
specified pipe data
Auto buffer clear mode for
discarding all received packets
CFIFOCTR
DnFIFOCTR
DnFIFOSEL
PIPEnCTR
Bit used
BCLR
DCLRM
ACLRM
Clearing condition
Cleared by writing 1
1: Mode valid
0: Mode invalid.
1: Mode valid
0: Mode invalid.
FIFO buffer
clearing mode
Clearing FIFO buffer on the
CPU side
Register used
(1)
Auto buffer clear mode function
The USBFS discards all received data packets if the PIPEnCTR.ACLRM bit is set to 1. If a correct data packet is
received, the ACK response is returned to the host controller. The auto buffer clear mode function can only be set in the
FIFO buffer reading direction.
Setting the ACLRM bit to 1 and then to 0 clears the FIFO buffer of the selected pipe regardless of the access direction.
An access cycle of at least 100 ns is required for the internal hardware sequence processing between ACLRM = 1 and
ACLRM = 0.
28.3.7
FIFO Port Functions
Table 28.20 shows the settings for the FIFO port functions. In write access, writing data until the maximum packet size is
reached automatically enables transmission of the data. To enable transmission before the maximum packet size is
reached, set the BVAL flag in the port control register to end writing. To send a zero-length packet, use the BCLR bit to
clear the buffer, and then set the BVAL flag to end writing.
In reading, reception of new packets is automatically enabled when all data is read. Data cannot be read when a zerolength packet is received (DTLN[8:0] = 0), so the buffer must be cleared with the BCLR bit. The length of the receive
data can be confirmed in the DTLN[8:0] bits in the port control register.
Table 28.20
FIFO port function settings
Register name
Bit name
Description
CFIFOSEL,
DnFIFOSEL
(n = 0, 1)
RCNT
Selects DTLN[8:0] read mode
REW
FIFO buffer rewind (re-read, rewrite)
DCLRM
Automatically clears receive data for a specified pipe after the data is read (only for DnFIFO)
DREQE
Enables DMA/DTC transfers (only for DnFIFO)
MBW
FIFO port access bit width
BIGEND
Selects FIFO port endian
ISEL
FIFO port access direction (only for DCP)
CFIFOCTR,
DnFIFOCTR
(n = 0, 1)
CURPIPE
Selects the current pipe
BVAL
Ends writing to the FIFO memory
BCLR
Clears the FIFO buffer on the CPU side
DTLN
Checks the length of receive data
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(1)
28. USB 2.0 Full-Speed Module (USBFS)
FIFO port selection
Table 28.21 shows the pipes that can be selected with the different FIFO ports.
The pipe to be accessed must be selected in the CURPIPE[3:0] bits in the port select register. After the pipe is selected,
software must check whether the written value can be read correctly from the CURPIPE[3:0] bits. If the previous pipe
number is read, it indicates that the USBFS is modifying the pipe. Next, software checks that the FRDY bit in the port
control register is 1. In addition, software must specify the bus width to be accessed in the MBW bit in the port select
register. The FIFO buffer access direction conforms to the PIPECFG.DIR setting. For the DCP only, the ISEL bit in the
port select register determines the direction.
Table 28.21
FIFO port access by pipe
Pipe
Access method
Port that can be used
DCP
CPU access
CFIFO Port Register
Pipe 1 to Pipe 9
CPU access
CFIFO Port Register
D0FIFO/D1FIFO Port Register
DMA/DTC access
D0FIFO/D1FIFO Port Register
(2)
REW bit
It is possible to temporarily stop access to the pipe currently being accessed, access a different pipe, and then continue
processing for the current pipe again. The REW bit in the port select register is used for this processing.
If a pipe is selected in the CURPIPE[3:0] bits in the port select register with the REW bit set to 1, the pointer used for
reading from and writing to the FIFO buffer is reset, and reading or writing can be carried out from the first byte. If a pipe
is selected with 0 set for the REW bit, data can be read and written in continuation from the previous selection, without
the pointer being reset.
To access the FIFO port, software must check that the FRDY bit in the port control register is 1 after selecting a pipe.
28.3.8
(1)
DMA Transfers (D0FIFO and D1FIFO Ports)
Overview of DMA transfers
For pipes 1 to 9, the FIFO port can be accessed using the DMAC. When buffer access for a pipe targeted for DMA
transfer is enabled, a DMA transfer request is issued.
Select the unit of transfer to the FIFO port in the DnFIFOSEL.MBW bit, and select the pipe targeted for the DMA
transfer in the DnFIFOSEL.CURPIPE[3:0] bits. Do not change the selected pipe during the DMA transfer.
(2)
DnFIFO auto clear mode (D0FIFO and D1FIFO port reading direction)
If 1 is set in the DnFIFOSEL.DCLRM bit, the USBFS automatically clears the FIFO buffer of the selected pipe when
reading of data from the FIFO buffer is complete.
Table 28.22 shows the packet reception and FIFO buffer clearing processing by software for each of the settings. As
shown in the table, the buffer clearing conditions depend on the value set in the PIPECFG.BFRE bit. Using the
DnFIFOSEL.DCLRM bit eliminates the need for the buffer to be cleared by software in any situation that requires buffer
clearing. This enables DMA transfers without involving software.
The DnFIFO auto clear mode can only be set in the FIFO buffer reading direction.
Table 28.22
Packet reception and FIFO buffer clearing processing by software
Register setting
Buffer status
when packet is received
DCLRM = 0
DCLRM = 1
BFRE = 0
BFRE = 1
BFRE = 0
BFRE = 1
Buffer full
No clearing required
No clearing required
No clearing required
No clearing required
Zero-length packet reception
Clearing required
Clearing required
No clearing required
No clearing required
Normal short packet reception
No clearing required
Clearing required
No clearing required
No clearing required
Transaction count end
No clearing required
Clearing required
No clearing required
No clearing required
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28.3.9
28. USB 2.0 Full-Speed Module (USBFS)
Control Transfers Using DCP
The Default Control Pipe (DCP) is used for data transfers in the control transfer data stage. The FIFO buffer of the DCP
is a 64-byte single buffer with a fixed area for both control reads and control writes. The FIFO buffer can be accessed
only through the CFIFO port.
28.3.9.1
(1)
Control transfers in host controller mode
Setup stage
The USQREQ, USBVAL, USBINDX, and USBLENG registers are used to transmit USB requests for setup transactions.
Writing the setup packet data to the registers and then writing 1 to the DCPCTR.SUREQ bit transmits the specified data
for the setup transaction. On completion of the transaction, the SUREQ bit sets to 0. Do not change these USB request
registers while SUREQ = 1.
When an attached function device is detected, software must issue the first setup transaction for the device using this
sequence with the DCPMAXP.DEVSEL[3:0] bits set to 0 and the DEVADD0.USBSPD[1:0] bits set appropriately.
When an attached function device is shifted to the Address state, software must issue setup transactions using this
sequence with the assigned USB address set in the DEVSEL[3:0] bits, and the bits in DEVADDn associated with the
specified USB address set appropriately. For example, when PIPEMAXP.DEVSEL[3:0] = 0010b, make appropriate
settings in DEVADD2. When PIPEMAXP.DEVSEL[3:0] = 0101b, make appropriate settings in DEVADD5.
When the setup transaction data is sent, an interrupt request is generated based on the response from the peripheral
device (SIGN or SACK bit in INTSTS1). This interrupt request allows software to check the setup transaction result.
A DATA0 data packet (USB request) for the setup transaction is always transmitted regardless of the status of the
DCPCTR.SQMON bit.
(2)
Data stage
The data stage is used to transfer data using the DCP FIFO buffer.
Before accessing the DCP FIFO buffer, specify the access direction in the CFIFOSEL.ISEL bit. Specify the transfer
direction in the DCPCFG.DIR bit. For the first data packet of the data stage, the data PID must be transferred as DATA1.
Set data PID = DATA1 in the DCPCTR.SQSET bit and set the PID bits = BUF. Completion of data transfer is detected
using the BRDY or BEMP interrupt.
For control write transfers, when the number of data bytes to be sent is an integer multiple of the maximum packet size,
software must send a zero-length packet at the end.
(3)
Status stage
The status stage is used for zero-length packet data transfers in the reverse direction of the data stage. As in the data
stage, data is transfered using the DCP FIFO buffer. Transactions are executed using the same procedure as the data
stage.
Data packets in the status stage must be transmitted and received with the data PID set to DATA1 using the
DCPCTR.SQSET bit.
When a zero-length packet is received, check the receive-data length in the CFIFOCTR.DTLN[8:0] bits after a BRDY
interrupt is generated, and then clear the FIFO buffer using the BCLR bit.
28.3.9.2
(1)
Control transfers in device controller mode
Setup stage
The USBFS sends an ACK response to a normal setup packet for the USBFS. The USBFS operates in the setup stage as
follows:
On receiving a new setup packet, the USBFS sets the following bits:
Sets the INTSTS0.VALID bit to 1
Sets the DCPCTR.PID[1:0] bits to NAK
Sets the DCPCTR.CCPL bit to 0.
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28. USB 2.0 Full-Speed Module (USBFS)
When the USBFS receives a data packet following a setup packet, it stores the USB request parameters in USBREQ,
USBVAL, USBINDX, and USBLENG.
Before performing the response processing for a control transfer, set the VALID flag to 0. When the VALID bit = 1, PID
= BUF cannot be set, and the data stage cannot be terminated.
Using the VALID bit function, the USBFS can suspend the current request being processed when it receives a new USB
request during a control transfer and return a response to the latest request.
In addition, the USBFS automatically detects the direction bit (bmRequestType bit [8]) and the request data length
(wLength) in the received USB request. It distinguishes between control read transfers, control write transfers, and nodata control transfers, and it controls stage transitions. For an incorrect sequence, a sequence error occurs in the control
transfer stage transition interrupt, and the interrupt is reported to software. For a diagram of the stage control by the
USBFS, see Figure 28.16.
(2)
Data stage
The DCP must be used to execute data transfers for received USB requests. Before accessing the DCP FIFO buffer,
specify the access direction in the CFIFOSEL.ISEL bit.
If the transfer data is larger than the size of the DCP FIFO buffer, execute the data transfer using the BRDY interrupt for
control write transfers and the BEMP interrupt for control read transfers.
(3)
Status stage
Control transfers are terminated by setting the DCPCTR.CCPL bit to 1 while the DCPCTR.PID[1:0] bits are set to BUF.
After this setting is made, the USBFS automatically executes the status stage based on the data transfer direction
determined at the setup stage. The procedure is as follows:
For control read transfers
The USBFS receives a zero-length packet from the USB host and transmits an ACK response.
For control write transfers and no-data control transfers
The USBFS transmits a zero-length packet and receives an ACK response from the USB host.
(4)
Control transfer auto response function
The USBFS automatically responds to a correct SET_ADDRESS request. If any of the following errors occur in the
SET_ADDRESS request, a response from software is necessary:
bmRequestType is not 00h: Any transfer other than a control write transfer
wIndex is not 00h: Request error
wLength is not 00h: Any transfer other than a no-data control transfer
wValue is larger than 7Fh: Request error
INTSTS0.DVSQ[2:0] are 011b (Configured state): Control transfer of a device state error.
For all requests other than the SET_ADDRESS request, a response is required from the corresponding software.
28.3.10
Bulk Transfers (Pipes 1 to 5)
The FIFO buffer usage (single/double buffer setting) is configurable for bulk transfers. The USBFS provides the
following functions for bulk transfers:
BRDY interrupt function (PIPECFG.BFRE bit). See section 28.3.3.1, (2) When SOFCFG.BRDYM = 0 and
PIPECFG.BFRE = 1.
Transaction count function (PIPEnTRE.TRENB, TRCLR, and PIPEnTRN.TRNCNT[15:0] bits). See section
28.3.4.5, Transaction counter for pipes 1 to 5 in the receiving direction.
Response PID = NAK function (PIPECFG.SHTNAK bit). See section 28.3.4.8, Response PID = NAK function.
Auto response mode (PIPEnCTR.ATREPM bit). See section 28.3.4.9, Auto response mode.
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28.3.11
28. USB 2.0 Full-Speed Module (USBFS)
Interrupt Transfers (Pipes 6 to 9)
In device controller mode, the USBFS performs interrupt transfers based on the timing dictated by the host controller.
In host controller mode, software can set the timing for issuing tokens using the interval counter.
28.3.11.1
Interval counter for interrupt transfers in host controller mode
Specify the transaction interval for interrupt transfers in the PIPEPERI.IITV[2:0] bits.
(1)
The USBFS issues interrupt transfer tokens based on this interval.Counter initialization
The USBFS initializes the interval counter under the following conditions:
Power-on reset
This initializes the IITV[2:0] bits.
FIFO buffer initialization using the PIPEnCTR.ACLRM bit:
This does not initialize the IITV[2:0] bits, but does initialize the count value. Setting the PIPEnCTR.ACLRM bit to
0 starts counting from the value set in IITV[2:0].
The interval counter is not initialized in the following case:
USB bus reset or USB suspended:
The IITV[2:0] bits are not initialized. Setting 1 to the DVSTCTR0.UACT bit starts counting from the value saved
before entering the USB bus reset state or USB suspended state.
(2)
Operation when tokens cannot be transmitted or received even on token generation
No token is generated in the following cases even at token generation time. In these cases, the USBFS tries to execute the
transaction in the next interval.
When the PID is set to NAK or STALL
When the FIFO buffer is full at token transmit time in the receiving (IN) direction
When there is no data to be transmitted in the FIFO buffer at token transmit time in the transmitting (OUT)
direction.
28.3.12
Isochronous Transfers (Pipes 1 and 2)
The USBFS provides the following functions for isochronous transfers:
Notification of isochronous transfer error
Interval counter specified in the PIPEPERI.IITV[2:0] bits
Isochronous IN transfer data setup control (IDLY function)
Isochronous IN transfer buffer flush function specified in the PIPEPERI.IFIS bit.
28.3.12.1
Error detection in isochronous transfers
The USBFS provides a function for detecting the errors described in this section, so that when errors occur in
isochronous transfers, they can be controlled by software. Table 28.23 and Table 28.24 show the priority order for errors
detected by the USBFS and the associated interrupts.
(a)
PID errors
The PID value of the received packet is invalid.
(b)
CRC errors and bit stuffing errors
A CRC error is found in a received packet or the bit stuffing is invalid.
(c)
Maximum packet size exceeded
The data size of the received packet exceeds the specified maximum packet size.
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(d)
28. USB 2.0 Full-Speed Module (USBFS)
Overrun and underrun errors
In host controller mode:
The FIFO buffer is full at token transmit time in the IN (receiving) direction
There is no data to be sent in the FIFO buffer at token transmit time in the OUT (transmitting) direction.
In device controller mode:
There is no data to be sent in the FIFO buffer at token receive time in the IN (transmitting) direction
The FIFO buffer is full at token receive time in the OUT (receiving) direction.
(e)
Interval errors
In device controller mode, the following cases are treated as an interval error:
Failure to receive an IN token in the interval frame during an isochronous IN transfer
Failure to receive an OUT token in the interval frame during an isochronous OUT transfer.
Table 28.23
Detection
priority
Error detection for token transmission and reception
Error
Generated interrupt and status
1
PID error
No interrupts are generated in either host or device controller mode (ignored as a
corrupted packet)
2
CRC or bit stuffing error
No interrupts are generated in either host or device controller mode (ignored as a
corrupted packet)
3
Overrun or underrun error
An NRDY interrupt is generated to set the FRMNUM.OVRN bit to 1 in both host and
device controller modes.
In device controller mode, a zero-length packet is transmitted in response to an IN token.
No data packets are received in response to OUT token.
4
Interval error
An NRDY interrupt is generated in device controller mode. No interrupt is generated in
host controller mode.
Table 28.24
Detection
priority
Error detection for data packet reception
Error
Generated interrupt and status
1
PID error
No interrupts are generated (ignored as a corrupted packet)
2
CRC or bit stuffing error
An NRDY interrupt is generated and the FRMNUM.CRCE bit is set to 1 in both host and
device controller modes
3
Maximum packet size
exceeded error
A BEMP interrupt is generated and the PID[1:0] bits set to STALL in both host and device
controller modes
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28.3.12.2
28. USB 2.0 Full-Speed Module (USBFS)
DATA-PID
In device controller mode, the USBFS responds as follows to a received PID:
(1)
IN direction
DATA0: Transmitted as data packet PID
DATA1: Not transmitted
DATA2: Not transmitted
mDATA: Not transmitted.
(2)
OUT direction
DATA0: Received normally as data packet PID
DATA1: Received normally as data packet PID
DATA2: Packets ignored
mDATA: Packets ignored.
28.3.12.3
Interval counter
The isochronous transfer interval can be set in the PIPEPERI.IITV[2:0] bits. In device controller mode, the interval
counter enables the functions as shown in Table 28.25. In host controller mode, the USBFS generates the token issuance
timing, and the interval counter operation is the same as that for interrupt transfers.
Table 28.25
Transfer
direction
IN
OUT
Interval counter function in device controller mode
Function
Conditions for detection
Transmit buffer flush
Failure to receive an IN token successfully in the interval frame during an isochronous IN
transfer
Notification of no reception of
token
Failure to receive an OUT token successfully in the interval frame during an isochronous
OUT transfer
The interval count is performed when an SOF is received or for interpolated SOFs, so the isochronism can be maintained
even if an SOF is corrupt. The frame interval can be set to 2IITV frames.
(1)
Counter initialization in device controller mode
The USBFS initializes the interval counter under the following conditions:
Power-on reset:
This initializes the PIPEPERI.IITV[2:0] bits.
FIFO buffer initialization using the ACLRM bit:
This does not initialize the IITV[2:0] bits, but does initialize the count value.
After the interval counter is initialized, the interval count starts under either of the following conditions when a packet is
transferred successfully:
An SOF is received after data is transmitted in response to an IN token when PID = BUF
An SOF is received after data is received in response to an OUT token when PID = BUF.
The interval counter is not initialized in the following conditions:
When the PID[1:0] bits are set to NAK or STALL
This does not stop the interval timer. The USBFS attempts the transaction in the next interval.
When the USB bus is reset or USBFS is suspended
This does not initialize the IITV[2:0] bits. When an SOF is received, the interval counter starts counting from the
value set before SOF was received.
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(2)
28. USB 2.0 Full-Speed Module (USBFS)
Interval counting and transfer control in host controller mode
The USBFS controls the interval between token issuance operations based on the PIPEPERI.IITV[2:0] bit settings.
Specifically, the USBFS issues a token for a selected pipe once every 2IITV frames.
PID bit setting
Token
DATA
SOF
OUT
DATA
SOF
OUT
SOF
USB bus
SOF
The USBFS starts counting the token issuance interval at the frame following the frame in which the PID[1:0] bits are set
to BUF by software.
NAK
BUF
BUF
BUF
Token
not issued
Token
not issued
Token
issued
Token
issued
Interval counter started
PID bit setting
Token
DATA
SOF
OUT
SOF
DATA
SOF
OUT
SOF
DATA
SOF
OUT
USB bus
SOF
Token issuance when IITV[2:0] = 0
SOF
Figure 28.17
NAK
BUF
BUF
BUF
BUF
BUF
BUF
Token
not issued
Token
not issued
Token
issued
Token
not issued
Token
issued
Token
not issued
Token
issued
Interval counter started
Figure 28.18
Token issuance when IITV[2:0] = 1
When the selected pipe is set for isochronous transfers, the USB carries out the following operation in addition to
controlling the token issuance interval. The USB issues a token even when the NRDY interrupt generation condition is
satisfied.
(a)
When the selected pipe is for isochronous IN transfers
The USBFS generates an NRDY interrupt when the USBFS issues an IN token but does not receive a packet successfully
from a peripheral device (no response or packet error).
The USBFS sets the FRMNUM.OVRN bit to 1, generating an NRDY interrupt, when the time to issue an IN token
comes while the USBFS cannot receive data because the FIFO buffer is full, because the CPU or DMAC/DTC is too
slow in reading data from the FIFO buffer.
(b)
When the selected pipe is for isochronous OUT transfers
The USBFS sets the OVRN bit to 1, generating an NRDY interrupt and transmitting a zero-length packet, when the time
to issue an OUT token comes while there is no data to be transmitted in the FIFO buffer, because the CPU or DMAC/
DTC is too slow in writing data to the FIFO buffer.
The token issuance interval is reset on any of the following conditions:
When the USBFS is reset through a reset pin:
This initializes the IITV[2:0] bits.
When the PIPEnCTR.ACLRM bit is set to 1 by software.
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28. USB 2.0 Full-Speed Module (USBFS)
(3)
Interval counting and transfer control in device controller mode
(a)
When the selected pipe is for isochronous OUT transfers
The USBFS generates an NRDY interrupt when it fails to receive a data packet within the interval set in the
PIPEPERI.IITV[2:0] bits.
The USBFS also generates an NRDY interrupt when it fails to receive data because of a CRC error or other errors
contained in the data packet or because of FIFO buffer is full.
The NRDY interrupt is generated on SOF packet reception. Even if the SOF packet is corrupted, internal interpolation
allows the interrupt to be generated when the SOF packet is received. However, when the IITV[2:0] bits are set to a value
other than 0, the USBFS generates an NRDY interrupt on receiving an SOF packet for every interval after interval
counting starts.
When the PID[1:0] bits are set to NAK by software after starting the interval timer, the USBFS does not generate an
NRDY interrupt on receiving an SOF packet.
The timing for starting interval counting depend on the IITV[2:0] setting as follows:
PID bit setting
Token
NAK
DATA
SOF
BUF
OUT
DATA
SOF
NAK
OUT
SOF
USB bus
SOF
When the IITV[2:0] bits = 0:
Interval counting starts at the next frame after software changes the PID[1:0] bits of the selected pipe to BUF.
BUF
Token
Token
Token
reception
reception
reception
is not delayed is not delayed is delayed
Token
reception
is delayed
Interval counter started
Figure 28.19
Relationship between frames and expected token reception when IITV[2:0] = 0
PID bit setting
Token
NAK
BUF
Token
Token
Token
reception
reception
reception
is not delayed is not delayed is delayed
BUF
Token
Token
reception
reception
is not delayed is delayed
DATA
SOF
OUT
SOF
DATA
SOF
BUF
OUT
SOF
DATA
SOF
BUF
OUT
SOF
USB bus
SOF
When the IITV[2:0] ≠ 0: The interval counting starts on completion of successful reception of the first data packet
after the PID[1:0] bits for the selected pipe are modified to BUF.
BUF
BUF
Token
reception
is not delayed
Token
reception
is delayed
Interval counter started
Figure 28.20
(b)
Relationship between frames and expected token reception when IITV[2:0] ≠ 0
When the selected pipe is for isochronous IN transfers
The PIPEPERI.IFIS bit must be 1 for this use case. When IFIS = 0, the USBFS transmits a data packet in response to a
received IN token regardless of the PIPEPERI.IITV[2:0] setting.
When IFIS is 1 and there is data to be transmitted in the FIFO buffer, the USBFS clears the FIFO buffer when it fails to
receive an IN token in the frame at the interval set in the IITV[2:0] bits.
The USBFS also clears the FIFO buffer when it fails to receive an IN token successfully because of a bus error, such as a
CRC error, contained in the IN token.
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28. USB 2.0 Full-Speed Module (USBFS)
The FIFO buffer is cleared on SOF packet reception. Even if the SOF packet is corrupted, the internal interpolation
allows the FIFO buffer to be cleared when the SOF packet is received.
The timing to start interval counting depends on the IITV[2:0] setting, as with OUT transfers.
The interval is counted on any of the following conditions in device controller mode:
When a hardware reset is applied to the USBFS (which also sets the IITV[2:0] bits to 000b)
When the PIPEnCTR.ACLRM bit is set to 1 by software
When the USBFS detects a USB bus reset.
(4)
Transmit data setup for isochronous transfers in device controller mode
With isochronous data transmission using the USBFS in device controller mode, after data is written to the FIFO buffer,
a data packet can be transmitted in the first frame after the SOF packet is detected. This isochronous transfer transmit
data setup function can identify the frame that started transmission.
When the double buffering is used, transmission is only enabled for the buffer where data writing was completed first,
even after the data write to both buffers is complete. Accordingly, even if multiple IN tokens are received, only the one
packet of FIFO buffer data is transmitted.
When the FIFO buffer is ready to transmit data when an IN token is received, the data is transferred and a normal
response is returned. However, if the FIFO buffer cannot transmit data, a zero-length packet is transmitted and an
underrun error occurs.
Figure 28.21 shows an example transmission using the isochronous transfer transmission data setup function when
IITV[2:0] = 0 (every frame) is set.
(1) Reception starting example 1 (when transmit data is ready before IN token reception starts)
SOF
SOF
SOF
SOF
Receive token
Transmit packet
Empty
Buffer A
Writing
Empty
Buffer B
Writing
ended
Transfer enabled
Writing
Writing ended
(2) Reception starting example 2 (when transmit data is ready after IN token reception starts (1))
SOF
IN
Receive token
IN
Zerolength
Transmit packet
Empty
Buffer A
Writing
IN
Zerolength
Data-A
Transfer enabled
Writing ended
Empty
Empty
Buffer B
(3) Reception starting example 3 (when transmit data is ready after IN token reception starts (2))
SOF
SOF
SOF
IN
Receive token
IN
Zerolength
Transmit packet
Empty
Buffer A
Writing
Empty
Buffer B
SOF
IN
Data-A
Writing
ended
Transfer enabled
Data-B
Empty
Writing ended
Writing
Writing ended
Writing
Transfer enabled
Empty
(4) Example of IN token reception outside the interval
Receive token
SOF
SOF
IN
Zerolength
Transmit packet
Buffer A
Empty
Buffer B
Figure 28.21
Writing
Empty
SOF
IN
Writing
ended
Writing
IN
Zerolength
Data-A
Transfer enabled
Empty
Writing ended
SOF
IN
Data-B
Writing
Writing ended
Transfer enabled
Empty
Example data setup operation
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(5)
28. USB 2.0 Full-Speed Module (USBFS)
Transmit buffer flush for isochronous transfers in device controller mode
In device controller mode during isochronous data transmission, if the USBFS receives an SOF packet for the next frame
without receiving an IN token in the interval frame, it operates as if the IN token is corrupt and clears the buffer that is
enabled for transmission, putting that buffer in the writing enabled state.
When double buffering is used and writing to both buffers is complete, the cleared FIFO buffer is assumed to be the one
where the data was transmitted in the interval frame, and transmission is enabled for the FIFO buffer that was not cleared
on SOF packet reception.
The timing of the buffer flush function depends on the PIPEPERI.IITV[2:0] setting as follows:
When IITV[2:0] = 0:
The buffer flush operation starts from the first frame after the pipe is enabled
When IITV[2:0] ≠ 0:
The buffer flush operation starts after the first normal transaction.
Figure 28.22 shows an example buffer flush. When an unanticipated token is received before the interval frame, the
USBFS sends the write data or a zero-length packet as an underrun error, depending on the data setup status.
SOF
SOF
Buffer A
Empty
Writing
Writing
ended
SOF
Transfer enabled
SOF
Empty
Writing
Writing
ended
Buffer is flushed
Buffer B
Figure 28.22
Empty
Writing
Writing ended
Transfer enabled
Example buffer flush operation
Figure 28.23 shows an example interval error occurrence. There are five types of interval errors, as shown in the figure.
An interval error occurs at timing 1 in the figure, and the buffer flush function is activated.
If an interval error occurs during an IN transfer, the buffer flush function is activated. If it occurs during an OUT transfer,
an NRDY interrupt is generated. Use the FRMNUM.OVRN bit to distinguish between this and NRDY interrupts
triggered by received packet errors and overrun errors.
For tokens that are shaded in the figure, responses are returned based on the FIFO buffer status.
IN direction:
If the buffer is ready to transfer data, the data is transferred and a normal response is returned
If the buffer is not ready to transfer data, a zero-length packet is transmitted and an underrun error occurs.
OUT direction:
If the buffer is ready to receive data, the data is received and a normal response is returned
If the buffer is not ready to receive data, the received data is discarded and an overrun error occurs.
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28. USB 2.0 Full-Speed Module (USBFS)
SOF
(1) Normal transfer
Token
(2) Token corrupted
Token
(3) Packet inserted
Token
(4) Frame misaligned 1
Token
(5) Frame misaligned 2
Token
(6) Token delayed
Token
Token
1
Token
Token
1
Token
1
Token
Token
Token
Token
Token
Token
Token
1
Token
1
Token
1
Token
1
Token
Token
Token
Interval when IITV = 1
Token
Token received in the specified interval
Token
Token received in the frame outside the interval
Figure 28.23
28.3.13
Example interval error occurrence when IITV[2:0] = 1
SOF Interpolation Function
In device controller mode, if packet reception is disabled at intervals of 1 ms because the SOF packet is corrupted or
missing, the USBFS interpolates the SOF. SOF interpolation begins when the USBE and SCKE bits in SYSCFG are set
to 1 and an SOF packet is received. The interpolation function is initialized under the following conditions:
MCU reset
USB bus reset
Suspended state detection.
The SOF interpolation operates as follows:
The interpolation function is not activated until an SOF packet is received.
When the first SOF packet is received, interpolation is performed by counting 1 ms on the 48-MHz internal clock
When the second and subsequent SOF packets are received, interpolation is performed at the previous reception
interval
Interpolation is not performed in the suspended state or on reception of a USB bus reset.
The USBFS supports the following functions controlled by SOF packet reception. These functions operate normally with
SOF interpolation if the SOF packet is missing:
Updating of the frame number
SOFR interrupt timing
Isochronous transfer interval count.
If an SOF packet is missing during full-speed operation, the FRMNUM.FRNM[10:0] bits are not updated.
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28.3.14
28. USB 2.0 Full-Speed Module (USBFS)
Pipe Schedule
28.3.14.1
Conditions for generating transactions
In host controller mode and when the DVSTCTR0.UACT bit is set to 1, the USBFS generates transactions under the
conditions shown in Table 28.26.
Table 28.26
Conditions for generating transactions
Conditions for generation
Transaction
DIR
Setup
Control transfer data stage, status stage,
bulk transfer
Interrupt transfer
Isochronous transfer
Note 1.
Note 2.
Note 3.
PID
IITV0
Buffer state
SUREQ
—*1
—*1
—*1
—*1
1 setting
IN
BUF
Invalid
Receive area
exists
—*1
OUT
BUF
Invalid
Transmit data
exists
—*1
IN
BUF
Valid
Receive area
exists
—*1
OUT
BUF
Valid
Transmit data
exists
—*1
IN
BUF
Valid
*2
—*1
OUT
BUF
Valid
*3
—*1
An em dash (—) in the table indicates that the condition is unrelated to the generating of tokens. “Valid” indicates that, for
interrupt transfers and isochronous transfers, a transaction is generated only in transfer frames that are based on the interval
counter. “Invalid” indicates that a transaction is generated regardless of the interval counter.
This indicates that a transaction is generated regardless of whether there is a receive area. If there is no receive area, however,
the received data is discarded.
This indicates that a transaction is generated regardless of whether there is any data to be transmitted. If there is no data to be
transmitted, however, a zero-length packet is transmitted.
28.3.14.2
Transfer schedule
This section describes the transfer scheduling within a frame of the USBFS. After the USBFS sends an SOF, the transfer
is carried out in the following sequence:
1. Execution of periodic transfers:
A pipe is searched for in the order of pipe 1 → pipe 2 → pipe 6 → pipe 7 → pipe 8 → pipe 9, and then if there is a
pipe for which an isochronous or interrupt transfer transaction can be generated, the transaction is generated.
2. Setup transactions for control transfers:
The DCP is checked, and if a setup transaction is possible, it is sent.
3. Execution of bulk transfers, control transfer data stages, and control transfer status stages:
A pipe is searched for in the order of DCP → pipe 1 → pipe 2 → pipe 3 → pipe 4→ pipe 5, and then if there is a
pipe for which a transaction for a bulk transfer, a control transfer data stage, or a control transfer status stage can be
generated, the transaction is generated.
When a transaction is generated, processing moves to the next pipe transaction regardless of whether the response
from the peripheral device is ACK or NAK. If there is time for transfer within the frame, step 3 is repeated.
28.3.14.3
Enabling USB communication
Setting the DVSTCTR0.UACT bit to 1 initiates an SOF transmission, and transaction generation is enabled. Setting the
UACT bit to 0 stops SOF transmission and the suspended state is invoked. If the UACT setting is changed from 1 to 0,
processing stops after the next SOF is sent.
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28.3.15
28. USB 2.0 Full-Speed Module (USBFS)
Battery Charging Detection Processing
It is possible to control the processing for data contact detection (D+ line contact check), primary detection (charger
detection), and secondary detection (charger verification), which are defined in the battery charging specification. The
following section describes the required operations for an individual function device and a host device.
28.3.15.1
Processing in device controller mode
The following processing is required when operating the USBFS as a portable device for battery charging:
1. Detect when the data lines (D+ and D-) have made contact and start the processing for primary detection.
2. After primary detection starts, wait 40 ms for masking, then check the D- voltage level to confirm the primary
detection result.
3. If the charger is detected during primary detection, start secondary detection.
4. After secondary detection starts, wait 40 ms for masking, then check the D+ voltage level to confirm the secondary
detection result.
For step 1, after VBUS is detected using the VBINT and VBSTS bits:
1. Wait for 300 to 900 ms, then set the VDPSRCE0 and IDMSINKE0 bits in the USBBCCTRL0 register.
2. Set the IDPSRCE0 bit.
3. After a change from high to low on the D+ line is detected using the LNST bits, clear the IDPSRCE0 bit, and set the
VDPSRCE0 and IDMSINKE0 bits simultaneously*1.
For step 2, set the VDPSRCE0 and IDMSINKE0 bits and wait 40 ms, then use the CHGDETSTS0 bit to verify the
primary detection result*2.
For step 3, if the CHGDETSTS0 bit is set in step 2, verify that the charger is detected, then clear the VDPSRCE0 and
IDMSINKE0 bits and set the VDMSRCE0 and IDPSINKE0 bits.
For step 4, set the VDMSRCE0 and IDPSINKE0 bits and wait for 40 ms, then use the PDDETSTS0 bit to verify the
secondary detection result.
Figure 28.24 shows the process flow.
Note 1. The battery charging specification describes two implementation methods for data contact detection (D+/D- line
contact check). One of the methods is to detect a change to logic low due to the pull-down resistor of the host
device when the D+ and D- lines have made contact with the target while the D+ line is held at logic high by
applying a current of 7 to 13 µA on the D+ line. The other method is to wait for 300 to 900 ms after VBUS is
detected.
Note 2. During primary detection, when the voltage on the D- line is detected to be 0.25 to 0.4 V or higher and 0.8 to 2.0
V or lower, the target device is recognized as the host device for battery charging, that is, charging the
downstream port. When using a PHY in which the CHGDETSTS0 bit only indicates that the voltage on the D- line
is 0.25 to 0.4 V or higher, add the processing to check that the voltage on D- line is 0.8 V to 2.0 V or lower using
the LNST bits, as required.
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28. USB 2.0 Full-Speed Module (USBFS)
Detect VBUS
Set BATCHGE0 bit
Set CNEN bit
Data Contact Detection
(software waiting method)
Wait for a minimum of 300 ms?
Yes
Data Contact
Detection
(hardware
detection
method)
Set RPDME0 bit
Set IDPSRCE0 bit
No
Use LNST[1:0] for
check
Is D+ low?
No
Yes
Clear RPDME0 bit
Clear IDPSRCE0 bit
Primary
Detection
Set VDPSRCE0 and
IDMSINKE0 bits
Wait for a minimum of 40 ms?
No
Yes
Read CHGDETSTS0 bit
CHGDETSTS0 = 1?
No
Yes
Target is SDP
Target is DCP or CDP
Clear VDPSRCE0 and
IDMSINKE0 bits
Secondary
Detection
Set VDMSRCE0 and
IDPSINKE0 bits
Wait for a minimum of 40 ms?
No
Yes
Read PDDETSTS0 bit
PDDETSTS0 = 1?
Yes
No
Target is CDP
Target is DCP
Figure 28.24
Process flow for operating as a portable device
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28.3.15.2
28. USB 2.0 Full-Speed Module (USBFS)
Processing when host controller is selected
The following processing is required when operating the USBFS as a charging downstream port for battery charging:
1. Start driving the VBUS.
2. Enable the portable device detection circuit.
3. Monitor the portable device detection signal, and start driving the D- line if the detection signal is high.
4. Detect when the portable device detection signal is low and stop driving the D- line.
The following processing can also be used in associated with the battery charging specification:
a. After disconnection is detected, start driving the D- line within 200 ms.
b. After connection is detected, stop driving the D- line within 10 ms.
The D- line must be driven to allow the portable device to detect the primary detection described in section 28.3.15.1,
Processing in device controller mode. Steps 1 to 4 apply when the portable device detection function is provided by
hardware. This method is to drive the D- line when the portable device is detected.
Steps a and b apply when the portable device function is not provided or available by hardware. Regardless of detection
of the portable device, the D- line is driven in the disconnected state and not in the connected state. In the battery
charging specification, either of these methods can be used.
For steps 3 and 4, after a change in the portable device detection signal is detected using the PDDETINT interrupt, the
current signal state can be confirmed by reading the PDDETSTS0 bit. Steps a and b can be performed only in a software
timer.
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28. USB 2.0 Full-Speed Module (USBFS)
Figure 28.25 show the process flow for steps 1 to 4 and the process flow for steps a to b, respectively.
Portable device detection processing
Drive VBUS
PD detection circuit enabled
(IDPSINKE0 = 1)
PD detection interrupt enabled
(PDDETINTE = 1)
PD detection interrupt?
(PDDETINT)
Repeat reading several times
to perform debouncing.
No
Yes
Connection detected?
(D+ pull-up detected?)
PDDETSTS0 bit = 1?
Yes
No
Yes
No
If SCKE = 0, use BCHG interrupt and
LNST for verification.
If SCKE = 1, use ATTCH interrupt for
verification.
Target is normal peripheral
device
Target is normal portable device
D– line drive control
Set VDMSRCE0 bit
PD detection interrupt?
(PDDETINT)
Repeat reading several times
to perform debouncing.
Yes
No
Connection detected?
(D+ pull-up detected?)
PDDETSTS0 bit = 0?
No
Yes
Yes
No
If SCKE = 0, use BCHG interrupt and
LNST for verification.
If SCKE = 1, use ATTCH interrupt for
verification.
Clear VDMSRCE0 bit
Figure 28.25
Process flow for operating as charging downstream port (steps 1 to 4)
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28. USB 2.0 Full-Speed Module (USBFS)
D-Line Drive Control
Drive VBUS
Set VDMSRCE0 bit
Connection detected?
No
Yes
Clear VDMSRCE0 bit
(within 10 ms)
Normal state
Disconnection detected?
No
Yes
Set VDMSRCE0 bit
(within 200 ms)
Figure 28.26
28.4
28.4.1
Process flow for operating as charging downstream port (steps a to b)
Usage Notes
Settings for the Module-Stop State
USBFS operation can be disabled or enabled using Module Stop Control Register B (MSTPCRB). The USBFS is
initially stopped after reset. Releasing the module-stop state enables access to the registers. For details, see section 11,
Low Power Modes.
28.4.2
Clearing the Interrupt Status Register on Exiting Software Standby Mode
Because the input buffer is always enabled in Software Standby mode, an unexpected interrupt might occur under the
following conditions:
When the interrupt is enabled in Normal mode
When the interrupt is disabled in Software Standby mode
When the input level of the pin that cancels Software Standby is changed in Software Standby mode.
These conditions might cause the associated interrupt flag in the Interrupt Status Register to set unexpectedly. After the
MCU exits Software Standby mode, the unexpected interrupt might be sent to the interrupt controller. To avoid this,
always clear the INTSTS0 and INTSTS1 registers in the canceling sequence.
28.4.3
Clearing the Interrupt Status Register after Setting Up the Port Function
The input buffer is disabled before the PmnPFS.PSEL and PmnPFS.PMR ports are set up, so the internal signal is fixed
high or low. The input buffer is enabled after the port is set so that the external pin state is propagated to the MCU. An
unexpected interrupt might occur at this time, causing the VBINT and OVRCR bits in INTSTS0 and INTSTS1, or other
interrupt status flags to set to 1. To avoid a malfunction, always clear the INTSTS0 and INTSTS1 registers after setting
up the port.
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29. Serial Communications Interface (SCI)
29.
Serial Communications Interface (SCI)
29.1
Overview
The Serial Communications Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:
Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter (ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol.
Each SCI channel has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can
be configured independently using an on-chip baud rate generator.
Table 29.1 lists the SCI specifications, Figure 29.1 shows a block diagram, and Table 29.2 lists the I/O pins by mode.
Note:
In this section, PCLK refers to PCLKA.
Table 29.1
SCI specifications (1 of 2)
Item
Description
Serial communication modes
Transfer speed
Bit rate specifiable with the on-chip baud rate generator
Full-duplex communications
Transmitter: Continuous transmission possible using double-buffering
Receiver: Continuous reception possible using double-buffering.
I/O pins
See Table 29.2
Data transfer
Selectable as LSB-first or MSB-first transfer
Interrupt sources
Transmit end, transmit data empty, receive data full, receive error, receive
data ready, and address match
Completion of generation of a start condition, restart condition, or stop
condition (for simple IIC mode).
Asynchronous
Clock synchronous
Smart card interface
Simple IIC
Simple SPI.
Module-stop function
Module-stop state can be set for each channel
Snooze end request
SCI0 address mismatch (SCI0_DCUF)
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Table 29.1
29. Serial Communications Interface (SCI)
SCI specifications (2 of 2)
Item
Description
Asynchronous mode
Clock synchronous
mode
Smart card interface
mode
Data length
7, 8, or 9 bits
Transmission stop bit
1 or 2 bits
Parity
Even parity, odd parity, or no parity
Receive error detection
Parity, overrun, and framing errors
Hardware flow control
Transmission and reception controllable with CTSn_RTSn pins
Transmission/reception
Selectable to 1-stage register or 16-stage FIFO
(only SCI0 and SCI1 support FIFO)
Address match
Interrupt request/event output can be issued on detecting a match between
the received data and the value in the compare match register
Address mismatch (SCI0
only) receive data
Snooze end request can be issued on detecting a mismatch between the
received data and the value in the compare match register
Start-bit detection
Selectable to low level or falling edge detection
Break detection
Breaks from framing errors detectable by reading from the SPTR register
Clock source
Selectable to internal or external clock
Double-speed mode
Baud rate generator double-speed mode is selectable
Multi-processor
communications function
Serial communication enabled between multiple processors
Noise cancellation
Digital noise filters included on signal paths from RXDn pin inputs
Data length
8 bits
Receive error detection
Overrun error
Clock source
Selectable to internal clock (master mode) or external clock (slave mode)
Hardware flow control
Transmission and reception controllable with CTSn_RTSn pins
Transmission/reception
Selectable to 1-stage register or 16-stage FIFO
Error processing
Error signal can be automatically transmitted on detecting a parity error during
reception
Data can be automatically retransmitted on receiving an error signal during
transmission
Simple IIC mode
Simple SPI mode
Data type
Both direct and inverse convention supported
Transfer format
I2C bus format (MSB-first only)
Operating mode
Master (single-master operation only)
Transfer rate
Up to 400 kbps
Noise cancellation
The signal paths from input on the SCLn and SDAn pins incorporate digital
noise filters and provide an adjustable interval for noise cancellation
Data length
8 bits
Detection of errors
Overrun error
Clock source
Selectable to internal clock (master mode) or external clock (slave mode)
SS input pin function
High impedance state can be invoked on the output pins by driving the SSn
pin high
Clock settings
Configurable between four clock phase and clock polarity settings
Bit rate modulation function
Error reduction through correction of outputs from the on-chip baud rate
generator
Event link function
Error event output (SCIn_ERI)*1 for receive error or error signal detection
Receive data full event output (SCIn_RXI)*1, *2
Transmit data empty event output (SCIn_TXI)*1, *2
Transmit end event output (SCIn_TEI)*1, *2
Address match event output (SCIn_AM)*1
Note 1.
Note 2.
Channel number, n = 0 to 4, 9.
Using this event link function is prohibited when FIFO operation is selected in asynchronous mode.
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29. Serial Communications Interface (SCI)
Bus interface
S3A1 User’s Manual
Module data bus
RDRHL FRDRH
RDR
FRDRL
RXDn/SCLn/
MISOn
TDRHL
TDR
RSR
FTDRH
FTDRL
TSR
Parity addition
Match check
Parity check
TXDn/SDAn/
MOSIn
SCMR
SSR/SSR_SMCI/
SSR_FIFO
SCR/SCR_SMCI
SMR/SMR_SMCI
SEMR
SPMR
FCR
FDR
LSR
CDR
DCCR
SPTR
BRR
MDDR
Baud rate
generator
Clock
SCIn_TEI
SCIn_TXI (interrupt request)
SCIn_RXI (n = 0 to 4, 9)
SCIn_ERI
SCIn_AM
SIMR1/2/3
SISR
SNFR
SCI0_DCUF
(Snooze end request)
External clock
RSR:
Receive Shift Register
RDR:
Receive Data Register
TSR:
Transmit Shift Register
TDR:
Transmit Data Register
SMR/SMR_SMCI:Serial Mode Register
SCR/SCR_SMCI:Serial Control Register
SSR/SSR_SMCI/SSR_FIFO*1:Serial Status Register
SCMR:
Smart Card Mode Register
BRR:
Bit Rate Register
MDDR:
Modulation Duty Register
SEMR:
Serial Extended Mode Register
SPMR:
SPI Mode Register
SNFR:
Noise Filter Setting Register
SIMR1/2/3: I2C Mode Register 1/2/3
SISR:
I2C Status Register
Figure 29.1
PCLK
PCLK/4
PCLK/16
PCLK/64
Transmission
and reception
control
CTSn_RTSn/
SSn
SCKn
Internal
peripheral bus
RDRHL:
FRDRH/L*1:
TDRHL:
FTDRH/L*1:
FCR*1:
FDR*1:
LSR*1:
CDR:
DCCR:
SPTR:
Note 1.
Receive 9-bit Data Register
Receive FIFO Data Register
Transmit 9-bit Data Register
Transmit FIFO Data Register
FIFO Control Register
FIFO Data Count Register
Line Status Register
Compare Match Data Register
Data Compare Match Control Register
Serial Port Register
SCI0 and SCI1 only
SCI block diagram
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Table 29.2
29. Serial Communications Interface (SCI)
SCI input/output pins
Channel
Pin name
Input/output
Function
SCI0
SCK0
Input/Output
SCI0 clock input/output
RXD0/SCL0/
MISO0
Input/Output
SCI0 receive data input
SCI0 I2C clock input/output
SCI0 slave transmit data input/output
TXD0/SDA0/
MOSI0
Input/Output
SCI0 transmit data output
SCI0 I2C data input/output
SCI0 master transmit data input/output
SS0/CTS0_RTS0
Input/Output
SCI0 chip select input, active-low
SCI0 transfer start control input/output, active-low
SCK1
Input/Output
SCI1 clock input/output
RXD1/SCL1/
MISO1
Input/Output
SCI1 receive data input
SCI1 I2C clock input/output
SCI1 slave transmit data input/output
TXD1/SDA1/
MOSI1
Input/Output
SCI1 transmit data output
SCI1 I2C data input/output
SCI1 master transmit data input/output
SS1/CTS1_RTS1
Input/Output
SCI1 chip select input, active-low
SCI1 transfer start control input/output, active-low
SCK2
Input/Output
SCI2 clock input/output
RXD2/SCL2/
MISO2
Input/Output
SCI2 receive data input
SCI2 I2C clock input/output
SCI2 slave transmit data input/output
TXD2/SDA2/
MOSI2
Input/Output
SCI2 transmit data output
SCI2 I2C data input/output
SCI2 master transmit data input/output
SS2/CTS2_RTS2
Input/Output
SCI2 chip select input, active-low
SCI2 transfer start control input/output, active-low
SCK3
Input/Output
SCI3 clock input/output
RXD3/SCL3/
MISO3
Input/Output
SCI3 receive data input
SCI3 I2C clock input/output
SCI3 slave transmit data input/output
TXD3/SDA3/
MOSI3
Input/Output
SCI3 transmit data output
SCI3 I2C data input/output
SCI3 master transmit data input/output
SS3/CTS3_RTS3
Input/Output
SCI3 chip select input, active-low
SCI3 transfer start control input/output, active-low
SCK4
Input/Output
SCI4 clock input/output
RXD4/SCL4/
MISO4
Input/Output
SCI4 receive data input
SCI4 I2C clock input/output
SCI4 slave transmit data input/output
TXD4/SDA4/
MOSI4
Input/Output
SCI4 transmit data output
SCI4 I2C data input/output
SCI4 master transmit data input/output
SS4/CTS4_RTS4
Input/Output
SCI4 chip select input, active-low
SCI4 transfer start control input/output, active-low
SCK9
Input/Output
SCI9 clock input/output
RXD9/SCL9/
MISO9
Input/Output
SCI9 receive data input
SCI9 I2C clock input/output
SCI9 slave transmit data input/output
TXD9/SDA9/
MOSI9
Input/Output
SCI9 transmit data output
SCI9 I2C data input/output
SCI9 master transmit data input/output
SS9/CTS9_RTS9
Input/Output
SCI9 chip select input, active-low
SCI9 transfer start control input/output, active-low
SCI1
SCI2
SCI3
SCI4
SCI9
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29.2
29. Serial Communications Interface (SCI)
Register Descriptions
29.2.1
Receive Shift Register (RSR)
RSR is a shift register that receives serial data input from the RXDn pin and converts it into parallel data. When one
frame of data is received, the data is automatically transferred to the RDR register, RDRHL register, or the receive FIFO.
The RSR register cannot be directly accessed by the CPU.
29.2.2
Receive Data Register (RDR)
Address(es): SCI0.RDR 4007 0005h, SCI1.RDR 4007 0025h, SCI2.RDR 4007 0045h,
SCI3.RDR 4007 0065h, SCI4.RDR 4007 0085h, SCI9.RDR 4007 0125h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
RDR is an 8-bit register that stores receive data. When one frame of serial data is received, the received serial data is
transferred from RSR to RDR, and the RSR register can receive more data. Because RSR and RDR function as a double
buffer, continuous receive operations can be performed.
Read the RDR register only after a receive data full interrupt (SCIn_RXI) occurs.
Note:
If the next frame of data is received before the receive data is read from the RDR register, an overrun error
occurs. RDR cannot be written to by the CPU.
29.2.3
Receive 9-bit Data Register (RDRHL)
Address(es): SCI0.RDRHL 4007 0010h, SCI1.RDRHL 4007 0030h, SCI2.RDRHL 4007 0050h,
SCI3.RDRHL 4007 0070h, SCI4.RDRHL 4007 0090h, SCI9.RDRHL 4007 0130h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RDRHL is a 16-bit register that stores receive data. Use this register when asynchronous mode and 9-bit data length are
selected.
The lower 8 bits of RDRHL are a shadow register of RDR, so access to RDRHL affects RDR. Access to RDRHL is
prohibited if 7-bit or 8-bit data length is selected.
After one frame of data is received, the received data is transferred from RSR to the RDR or RDRHL register, allowing
the RSR register to receive more data.
RSR and RDRHL form a double-buffered structure to enable continuous reception. RDRHL should be read only when a
receive data full interrupt (SCIn_RXI) request is issued. An overrun error occurs when the next frame of data is received
before the received data is read from RDRHL. The CPU cannot write to the RDRHL register.
Bits [15:9] of the RDRHL register are fixed to 0. These bits are read as 0. The write value should be 0.
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29.2.4
29. Serial Communications Interface (SCI)
Receive FIFO Data Register H, L, HL (FRDRH, FRDRL, FRDRHL)
Receive FIFO Data Register H (FRDRH)
Address(es): SCI0.FRDRH 4007 0010h, SCI1.FRDRH 4007 0030h
Receive FIFO Data Register L (FRDRL)
Address(es): SCI0.FRDRL 4007 0011h, SCI1.FRDRL 4007 0031h
Receive FIFO Data Register HL (FRDRHL)
Address(es): SCI0.FRDRHL 4007 0010h, SCI1.FRDRHL 4007 0030h
SCIn.FRDRHL
SCIn.FRDRH
SCIn.FRDRL
b15
b14
b13
b12
b11
b10
b9
—
RDF
ORER
FER
PER
DR
MPB
0
0
0
0
0
0
0
Value after reset:
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
RDAT[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
RDAT[8:0]
Serial Receive Data
Received serial data, valid only in asynchronous mode, including
multi-processor mode or clock synchronous mode, with FIFO
selected
R
b9
MPB
Multi-Processor Bit Flag
Multi-processor bit associated with serial receive data
(RDAT[8:0]):
0: Data transmission cycle
1: ID transmission cycle.
MPB is valid only in asynchronous mode with SMR.MP = 1, and
with FIFO selected.
R
b10
DR
Receive Data Ready Flag
0: Receiving is in progress, or no received data remains in
FRDRH and FRDRL after successfully completed reception
1: Next receive data is not received for a period after reception is
successfully completed.
R*1
b11
PER
Parity Error Flag
0: No parity error occurred in the first data of FRDRH and FRDRL R
1: A parity error occurred in the first data of FRDRH and FRDRL.
b12
FER
Framing Error Flag
0: No framing error occurred in the first data of FRDRH and
FRDRL
1: A framing error occurred in the first data of FRDRH and
FRDRL.
R
b13
ORER
Overrun Error Flag
0: No overrun error occurred
1: Overrun error occurred.
R*1
b14
RDF
Receive FIFO Data Full Flag
0: The amount of receive data written in FRDRH and FRDRL is
less than the specified receive triggering number
1: The amount of receive data written in FRDRH and FRDRL is
equal to or greater than the specified receive triggering
number.
R*1
b15
—
Reserved
This bit is read as 0
R
Note 1.
If this flag is read, it is same as a read from the SSR_FIFO register. Write 0 to the SSR_FIFO register to clear the flag.
FRDRHL is a 16-bit register that consists of the 8-bit FRDRH and FRDRL registers. FRDRH and FRDRL constitute a
16-stage FIFO register that stores serial receive data and related status information. This register is valid only in
asynchronous mode, including multi-processor mode, or clock synchronous mode.
The SCI completes reception of one frame of serial data by transferring the received data from the RSR register into
FRDRH and FRDRL for storage. Continuous reception is executed until 16 stages are stored. If data is read when there is
no received data in FRDRH and FRDRL, the value is undefined. When FRDRH and FRDRL are full, subsequent serial
receive data is lost. The CPU can read from FRDRH and FRDRL but cannot write to them.
Reading 1 from the RDF, ORER, or DR flags of the FRDRH register is the same as reading those bits in the SSR_FIFO
register. When writing 0 to clear a flag in the SSR_FIFO register after reading the FRDRH register, write 0 only to the
flag that is to be cleared and write 1 to the other flags. When reading both the FRDRH and FRDRL registers, read in the
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29. Serial Communications Interface (SCI)
order from FRDRH to FRDRL. FRDRHL can be accessed in 16-bit units.
29.2.5
Transmit Data Register (TDR)
Address(es): SCI0.TDR 4007 0003h, SCI1.TDR 4007 0023h, SCI2.TDR 4007 0043h,
SCI3.TDR 4007 0063h, SCI4.TDR 4007 0083h, SCI9.TDR 4007 0123h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
TDR is an 8-bit register that stores transmit data.
When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission.
The double-buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data is
already written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue
transmission.
The CPU can read from or write to TDR at any time. Only write transmit data to TDR once after each instance of the
transmit data empty interrupt (SCIn_TXI).
29.2.6
Transmit 9-Bit Data Register (TDRHL)
Address(es): SCI0.TDRHL 4007 000Eh, SCI1.TDRHL 4007 002Eh, SCI2.TDRHL 4007 004Eh,
SCI3.TDRHL 4007 006Eh, SCI4.TDRHL 4007 008Eh, SCI9.TDRHL 4007 012Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TDRHL is a 16-bit register that stores transmit data. Use this register when asynchronous mode and 9-bit data length are
selected.
The lower 8 bits of TDRHL are the shadow register of TDR, so access to TDRHL affects TDR. Access to the TDRHL
register is prohibited if 7-bit or 8-bit data length is selected.
When empty space is detected in TSR, the transmit data stored in TDRHL is transferred to TSR and transmission starts.
TSR and TDRHL form a double-buffered structure to support continuous transmission. When the next data to be
transmitted is stored in TDRHL after one frame of data is transmitted, the transmitting operation is continued by
transferring the data to TSR.
The CPU can read and write to TDRHL. Bits [15:9] in TDRHL are fixed to 1. These bits are read as 1. The write value
should be 1.
Write transmit data to TDRHL only when a transmit data empty interrupt (SCIn_TXI) request is issued.
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29.2.7
29. Serial Communications Interface (SCI)
Transmit FIFO Data Register H, L, HL (FTDRH, FTDRL, FTDRHL)
Transmit FIFO Data Register H (FTDRH)
Address(es): SCI0.FTDRH 4007 000Eh, SCI1.FTDRH 4007 002Eh
Transmit FIFO Data Register L (FTDRL)
Address(es): SCI0.FTDRL 4007 000Fh, SCI1.FTDRL 4007 002Fh
Transmit FIFO Data Register HL (FTDRHL)
Address(es): SCI0.FTDRHL 4007 000Eh, SCI1.FTDRHL 4007 002Eh
SCIn.FTDRHL
SCIn.FTDRH
SCIn.FTDRL
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
MPBT
1
1
1
1
1
1
1
Value after reset:
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
TDAT[8:0]
1
1
1
1
1
Bit
Symbol
Bit name
Description
R/W
b8 to b0
TDAT[8:0]
Serial Transmit Data
Serial transmit data, valid only in asynchronous mode,
including multi-processor, or clock synchronous mode, with
FIFO selected
W
b9
MPBT
Multi-Processor Transfer Bit Flag
Specifies the multi-processor bit in the transmission frame:
0: Data transmission cycle
1: ID transmission cycle.
Valid only in asynchronous mode with SMR.MP = 1, with FIFO
selected.
W
b15 to b10
—
Reserved
The write value should be 1
W
FTDRHL is a 16-bit register that consists of 8-bit registers, FTDRH and FTDRL.
FTDRH and FTDRL constitute a 16-stage FIFO register that stores data for serial transmission and a multi-processor
transfer bit. This register is valid only in asynchronous mode, including multi-processor mode, or clock synchronous
mode.
When the SCI detects that the Transmit Shift Register (TSR) register is empty, it transmits data written in FTDRH and
FTDRL to TSR and starts serial transmission. Continuous serial transmission is executed until no transmit data is left in
FTDRH and FTDRL. When FTDRHL is full of transmit data, no more data can be written. If writing new data is
attempted, the data is ignored. The CPU can write to FTDRH and FTDRL but cannot read them.
When writing to both the FTDRH and FTDRL registers, write in the order from FTDRH to FTDRL.
MPBT flag (Multi-Processor Transfer Bit Flag)
The MPBT flag specifies the value of the multi-processor bit of the transmit frame. When FCR.FM = 1, SSR.MPBT is
not valid.
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29.2.8
29. Serial Communications Interface (SCI)
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers
transmit data from TDR, TDRHL, or transmit FIFO to TSR, then sends the data to the TXDn pin. The CPU cannot
directly access TSR.
29.2.9
Serial Mode Register (SMR) for Non-Smart Card Interface Mode
(SCMR.SMIF = 0)
Address(es): SCI0.SMR 4007 0000h, SCI1.SMR 4007 0020h, SCI2.SMR 4007 0040h,
SCI3.SMR 4007 0060h, SCI4.SMR 4007 0080h, SCI9.SMR 4007 0120h
b7
b6
b5
b4
b3
b2
CM
CHR
PE
PM
STOP
MP
0
0
0
0
0
0
Value after reset:
b1
b0
CKS[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKS[1:0]
Clock Select
b1 b0
R/W*4
b2
MP
Multi-Processor Mode
Valid only in asynchronous mode:
0: Multi-processor communications function is disabled
1: Multi-processor communications function is enabled.
R/W*4
b3
STOP
Stop Bit Length
Valid only in asynchronous mode:
0: 1 stop bit
1: 2 stop bits.
R/W*4
b4
PM
Parity Mode
Valid only when the PE bit is 1:
0: Selects even parity
1: Selects odd parity.
R/W*4
b5
PE
Parity Enable
Valid only in asynchronous mode:
When transmitting:
0: Parity bit is not added
1: Parity bit is added.
When receiving:
0: Parity bit is not checked
1: Parity bit is checked.
R/W*4
b6
CHR
Character Length
Selects transmit/receive character length in combination with
the SCMR.CHR1 bit:
R/W*4
0
0
1
1
0: PCLK clock (n = 0)*1
1: PCLK/4 clock (n = 1)*1
0: PCLK/16 clock (n = 2)*1
1: PCLK/64 clock (n = 3)*1.
CHR1 CHR
0 0: Transmit/receive in 9-bit data length
0 1: Transmit/receive in 9-bit data length
1 0: Transmit/receive in 8-bit data length (initial value)
1 1: Transmit/receive in 7-bit data length*3.
Valid only in asynchronous mode.*2
b7
Note 1.
Note 2.
Note 3.
Note 4.
CM
Communication Mode
R/W*4
0: Asynchronous mode or simple IIC mode
1: Clock synchronous mode or simple SPI mode.
n is the decimal notation of the value of n in BRR. See section 29.2.17, Bit Rate Register (BRR).
In any mode other than asynchronous mode, this bit setting is invalid and a fixed data length of 8 bits is used.
LSB-first is fixed and the MSB (bit [7]) in TDR is not transmitted.
Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
SMR sets the communication format and clock source for the on-chip baud rate generator.
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29. Serial Communications Interface (SCI)
CKS[1:0] bits (Clock Select)
The CKS[1:0] bits select the clock source for the on-chip baud rate generator.
For the relationship between the settings of these bits and the baud rate, see section 29.2.17, Bit Rate Register (BRR).
MP bit (Multi-Processor Mode)
The MP bit disables or enables the multi-processor communications function. The settings of the PE and PM bits are
invalid in multi-processor mode.
STOP bit (Stop Bit Length)
The STOP bit selects the stop bit length in transmission.
In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the
start bit of the next transmit frame.
PM bit (Parity Mode)
The PM bit selects the parity mode (even or odd) for transmission and reception.
The PM bit setting is invalid in multi-processor mode.
PE bit (Parity Enable)
When the PE bit is set to 1, the parity bit is added to the transmit data, and the parity bit is checked at reception.
Regardless of the setting of the PE bit, the parity bit is not added or checked in multi-processor format.
CHR bit (Character Length)
The CHR bit selects the data length for transmission and reception in combination with the CHR1 bit in SCMR.
In modes other than asynchronous mode, a fixed data length of 8 bits is used.
CM bit (Communication Mode)
The CM bit selects the communication mode:
Asynchronous mode or simple IIC mode
Clock synchronous mode or simple SPI mode.
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29.2.10
29. Serial Communications Interface (SCI)
Serial Mode Register for Smart Card Interface Mode (SMR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SMR_SMCI 4007 0000h, SCI1.SMR_SMCI 4007 0020h, SCI2.SMR_SMCI 4007 0040h,
SCI3.SMR_SMCI 4007 0060h, SCI4.SMR_SMCI 4007 0080h, SCI9.SMR_SMCI 4007 0120h
b7
b6
b5
b4
GM
BLK
PE
PM
0
0
0
0
Value after reset:
b3
b2
b1
b0
BCP[1:0]
CKS[1:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKS[1:0]
Clock Select
b1 b0
R/W*2
b3, b2
BCP[1:0]
Base Clock Pulse
Selects the number of base clock cycles in combination with
the BCP2 bit in SCMR.
Table 29.3 lists the combinations of the SCMR.BCP2 and
SMR.BCP[1:0] bits.
R/W*2
b4
PM
Parity Mode
Valid only when the PE bit is 1:
0: Selects even parity
1: Selects odd parity.
R/W*2
b5
PE
Parity Enable
When this bit is set to 1, a parity bit is added to transmit data,
and the parity of received data is checked. Set this bit to 1 in
smart card interface mode.
R/W*2
b6
BLK
Block Transfer Mode
0: Non-block transfer mode operation
1: Block transfer mode operation.
R/W*2
b7
GM
GSM Mode
0: Non-GSM mode operation
1: GSM mode operation.
R/W*2
Note 1.
Note 2.
0 0: PCLK clock (n = 0)*1
0 1: PCLK/4 clock (n = 1)*1
1 0: PCLK/16 clock (n = 2)*1
1 1: PCLK/64 clock (n = 3)*1.
n is the decimal notation of the value of n in the BRR register. See section 29.2.17, Bit Rate Register (BRR).
Writable only when SCR_SMCI.TE = 0 and SCR_SMCI.RE = 0 (both serial transmission and reception are disabled).
The SMR_SMCI register sets the communication format and clock source for the on-chip baud rate generator.
CKS[1:0] bits (Clock Select)
The CKS[1:0] bits select the clock source for the on-chip baud rate generator. For the relationship between the settings of
these bits and the baud rate, see section 29.2.17, Bit Rate Register (BRR).
BCP[1:0] bits (Base Clock Pulse)
The BCP[1:0] bits select the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set
these bits in combination with the SCMR.BCP2 bit. For details, see section 29.6.4, Receive Data Sampling Timing and
Reception Margin.
Table 29.3
Note 1.
Combinations of SCMR.BCP2 bit and SMR_SMCI.BCP[1:0] bits
SCMR.BCP2 bit
SMR_SMCI.BCP[1:0] bits
Number of base clock cycles for 1-bit transfer period
0
00
93 clock cycles (S = 93)*1
0
01
128 clock cycles (S = 128)*1
0
10
186 clock cycles (S = 186)*1
0
11
512 clock cycles (S = 512)*1
1
00
32 clock cycles (S = 32)*1 (initial value)
1
01
64 clock cycles (S = 64)*1
1
10
372 clock cycles (S = 372)*1
1
11
256 clock cycles (S = 256)*1
S indicates the value of S in the BRR register. See section 29.2.17, Bit Rate Register (BRR)).
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29. Serial Communications Interface (SCI)
PM bit (Parity Mode)
The PM bit selects the parity mode for transmission and reception (even or odd). For details on the usage of this bit in
smart card interface mode, see section 29.6.2, Data Format (Except in Block Transfer Mode).
PE bit (Parity Enable)
Set the PE bit to 1. The parity bit is added to the transmit data before transmission, and the parity bit is checked at
reception.
BLK bit (Block Transfer Mode)
Setting the BLK bit to 1 enables the block transfer mode operation. For details, see section 29.6.3, Block Transfer Mode.
GM bit (GSM Mode)
Setting the GM bit to 1 enables GSM mode operation. In GSM mode, the SSR_SMCI.TEND flag set timing is moved
forward to 11.0 ETU (elementary time unit = 1-bit transfer time) from the start, and the clock output control function is
enabled. For details, see section 29.6.6, Serial Data Transmission (Except in Block Transfer Mode) and section 29.6.8,
Clock Output Control.
29.2.11
Serial Control Register (SCR) for Non-Smart Card Interface Mode
(SCMR.SMIF = 0)
Address(es): SCI0.SCR 4007 0002h, SCI1.SCR 4007 0022h, SCI2.SCR 4007 0042h,
SCI3.SCR 4007 0062h, SCI4.SCR 4007 0082h, SCI9.SCR 4007 0122h
Value after reset:
b7
b6
b5
b4
b3
b2
TIE
RIE
TE
RE
MPIE
TEIE
0
0
0
0
0
0
b1
b0
CKE[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKE[1:0]
Clock Enable
Asynchronous mode:
R/W*1
b1 b0
0 0: On-chip baud rate generator.
The SCKn pin is available for use as an I/O port
according to the I/O port settings.
0 1: On-chip baud rate generator.
A clock with the same frequency as the bit rate is
output from the SCKn pin.
1 x: External clock.
A clock with a frequency 16 times the bit rate
should be input from the SCKn pin when
SEMR.ABCS bit is 0. Input a clock signal with a frequency eight times the bit rate when the
SEMR.ABCS bit is 1.
Clock synchronous mode:
b1 b0
0 x: Internal clock.
The SCKn pin functions as the clock output pin.
1 x: External clock.
The SCKn pin functions as the clock input pin.
b2
TEIE
Transmit End Interrupt Enable
0: SCIn_TEI interrupt request is disabled
1: SCIn_TEI interrupt request is enabled.
R/W
b3
MPIE
Multi-Processor Interrupt Enable
Valid in asynchronous mode when SMR.MP = 1:
0: Non-multi-processor reception
1: When data with the multi-processor bit set to 0 is
received, the data is not read, and setting the RDRF,
ORER, and FER status flags in SSR to 1 is disabled.
When data with the multi-processor bit set to 1 is
received, the MPIE bit is automatically set to 0, and
non-multi-processor reception is resumed.
R/W*3
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29. Serial Communications Interface (SCI)
Bit
Symbol
Bit name
Description
R/W
b4
RE
Receive Enable
0: Serial reception is disabled
1: Serial reception is enabled.
R/W*2
b5
TE
Transmit Enable
0: Serial transmission is disabled
1: Serial transmission is enabled.
R/W*2
b6
RIE
Receive Interrupt Enable
0: SCIn_RXI and SCIn_ERI interrupt requests are
disabled
1: SCIn_RXI and SCIn_ERI interrupt requests are
enabled.
R/W
b7
TIE
Transmit Interrupt Enable
0: SCIn_TXI interrupt request is disabled
1: SCIn_TXI interrupt request is enabled.
R/W
x: Don’t care
Note 1.
Note 2.
Note 3.
Writable only when TE = 0 and RE = 0.
1 can be written only when TE = 0 and RE = 0, when the SMR.CM bit is 1. After setting TE or RE to 1, only 0 can be written to
TE and RE. When the SMR.CM bit is 0 and the SIMR1.IICM bit is 0, writing is enabled under any condition.
When writing a new value to a bit other than the MPIE bit of this register during multi-processor mode (SMR.MP bit = 1), write 0
to the MPIE bit using the store instruction to avoid accidentally setting the MPIE bit to 1 by a read-modify-write operation when
using a bit manipulation instruction.
The SCR register controls operation and clock source selection for transmission and reception.
CKE[1:0] bits (Clock Enable)
The CKE[1:0] bits select the clock source and the SCKn pin function.
TEIE bit (Transmit End Interrupt Enable)
The TEIE bit enables or disables an SCIn_TEI interrupt request. Set the TEIE bit to 0 to disable the interrupt request.
In simple IIC mode, SCIn_TEI is allocated to the interrupt on completion of issuing a start, restart, or stop condition
(STI). In this case, the TEIE bit can be used to enable or disable the STI.
MPIE bit (Multi-Processor Interrupt Enable)
When the MPIE bit is set to 1 and data with the multi-processor bit set to 0 is received, the data is not read, and setting
the status flags RDRF, RDF, ORER, and FER in SSR/SSR_FIFO to 1 is disabled. When data with the multi-processor bit
set to 1 is received, the MPIE is automatically cleared to 0, and non-multi-processor reception resumes. For details, see
section 29.4, Multi-Processor Communications Function.
When the MPB bit in the SSR register is 0, the receive data is not transferred from the RSR to the RDR, a receive error is
not detected, and setting the flags ORER and FER to 1 is disabled.
When the MPB bit is set to 1, the MPIE bit is automatically set to 0, the SCIn_RXI and SCIn_ERI interrupt requests are
enabled (if the RIE bit in SCR is set to 1), and the setting of the ORER and FER flags to 1 is enabled.
Set MPIE to 0 if the multi-processor communications function is not used.
RE bit (Receive Enable)
The RE bit enables or disables serial reception. When the RE bit is set to 1, serial reception starts by detecting the start bit
in asynchronous mode or the synchronous clock input in clock synchronous mode. Set the reception format in the SMR
before setting the RE bit to 1.
When non-FIFO operation is selected and reception is halted by setting the RE bit to 0, the RDRF, ORER, FER, and PER
flags in SSR are not affected, and the previous values are saved.
When FIFO operation is selected and reception is halted by setting the RE bit to 0, the RDF, ORER, FER, PER, and DR
flags in SSR_FIFO are not affected and the previous values are saved.
TE bit (Transmit Enable)
The TE bit enables or disables serial transmission.
When the TE bit is set to 1, serial transmission starts by writing transmit data to TDR. Set the transmission format in the
SMR register before setting the TE bit to 1.
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29. Serial Communications Interface (SCI)
RIE bit (Receive Interrupt Enable)
The RIE bit enables or disables SCIn_RXI and SCIn_ERI interrupt requests.
Set the RIE bit to 0 to disable SCIn_RXI and SCIn_ERI interrupt requests.
To cancel an SCIn_ERI interrupt request, read 1 from the ORER, FER, or PER flag in SSR/SSR_FIFO, then set the flag
to 0, or set the RIE bit to 0.
TIE bit (Transmit Interrupt Enable)
The TIE bit enables or disables SCIn_TXI interrupt requests. Set the TIE bit to 0 to disable an SCIn_TXI interrupt
request. Set TIE to 1 when the TE bit is 1. For the SCIn_TXI interrupt to occur, set the TE and TIE bits to 1
simultaneously, before transfer starts.
29.2.12
Serial Control Register for Smart Card Interface Mode (SCR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SCR_SMCI 4007 0002h, SCI1.SCR_SMCI 4007 0022h, SCI2.SCR_SMCI 4007 0042h,
SCI3.SCR_SMCI 4007 0062h, SCI4.SCR_SMCI 4007 0082h, SCI9.SCR_SMCI 4007 0122h
b7
b6
b5
b4
b3
b2
TIE
RIE
TE
RE
MPIE
TEIE
0
0
0
0
0
0
Value after reset:
b1
b0
CKE[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKE[1:0]
Clock Enable
When GM in SMR_SMCI = 0:
R/W*1
b1 b0
0 0: Output disabled.
The SCKn pin is available for use as an I/O port
according to the I/O port settings.
0 1: Clock output.
1 x: Setting prohibited.
When GM in SMR_SMCI = 1:
b1 b0
0 0: Output fixed low.
x 1: Clock output.
1 0: Output fixed high.
b2
TEIE
Transmit End Interrupt Enable
Set this bit to 0 in smart card interface mode
R/W
b3
MPIE
Multi-Processor Interrupt Enable
Set this bit to 0 in smart card interface mode
R/W
b4
RE
Receive Enable
0: Serial reception is disabled
1: Serial reception is enabled.
R/W*2
b5
TE
Transmit Enable
0: Serial transmission is disabled
1: Serial transmission is enabled.
R/W*2
b6
RIE
Receive Interrupt Enable
0: SCIn_RXI and SCIn_ERI interrupt requests are
disabled
1: SCIn_RXI and SCIn_ERI interrupt requests are
enabled.
R/W
b7
TIE
Transmit Interrupt Enable
0: SCIn_TXI interrupt request is disabled
1: SCIn_TXI interrupt request is enabled.
R/W
x: Don’t care
Note 1.
Note 2.
Writable only when TE = 0 and RE = 0.
1 can be written only when TE = 0 and RE = 0. After setting TE or RE to 1, only 0 can be written to TE and RE.
SCR_SMCI sets transmission and reception control, interrupt control, and clock source selection for transmission and
reception.
For details on interrupt requests, see section 29.10, Interrupt Sources.
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29. Serial Communications Interface (SCI)
CKE[1:0] bits (Clock Enable)
The CKE[1:0] bits control the clock output from the SCKn pin.
In GSM mode, clock output can be dynamically switched. For details, see section 29.6.8, Clock Output Control.
TEIE bit (Transmit End Interrupt Enable)
Set the TEIE bit to 0 in smart card interface mode.
RE bit (Receive Enable)
The RE bit enables or disables serial reception.
When this bit is set to 1, serial reception starts by detecting the start bit. Set the reception format in the SMR_SMCI
register before setting the RE bit to 1.
If reception is halted by setting the RE bit to 0, the ORER, FER, and PER flags in SSR_SMCI are not affected and the
previous values are saved.
TE bit (Transmit Enable)
The TE bit enables or disables serial transmission.
Set the TE bit to 1 to start serial transmission by writing transmit data to TDR. Set the transmission format in the
SMR_SMCI register before setting the TE bit to 1.
RIE bit (Receive Interrupt Enable)
The RIE bit enables or disables SCIn_RXI and SCIn_ERI interrupt requests.
Set RIE to 0 to disable SCIn_RXI and SCIn_ERI interrupt requests.
To cancel an SCIn_ERI interrupt request, read 1 from the ORER, FER, or PER flag in the SSR_SMCI register, then set
the flag to 0, or set the RIE bit to 0.
TIE bit (Transmit Interrupt Enable)
The TIE bit enables or disables an SCIn_TXI interrupt request.
Set the TIE bit to 0 to disable an SCIn_TXI interrupt request. Set TIE to 1 when the TE bit is 1. For the SCIn_TXI
interrupt to occur, set the TE and TIE bits to 1 simultaneously before transfer starts.
29.2.13
Serial Status Register (SSR) for Non-Smart Card Interface and Non-FIFO Mode
(SCMR.SMIF = 0 and FCR.FM = 0)
Address(es): SCI0.SSR 4007 0004h, SCI1.SSR 4007 0024h, SCI2.SSR 4007 0044h,
SCI3.SSR 4007 0064h, SCI4.SSR 4007 0084h, SCI9.SSR 4007 0124h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MPBT
Multi-Processor Bit Transfer
Value of the multi-processor bit in the transmission
frame:
0: Data transmission cycle
1: ID transmission cycle.
R/W
b1
MPB
Multi-Processor
Value of the multi-processor bit in the reception frame:
0: Data transmission cycle
1: ID transmission cycle.
R
b2
TEND
Transmit End Flag
0: A character is being transmitted
1: Character transfer is complete.
R
b3
PER
Parity Error Flag
0: No parity error occurred
1: Parity error occurred.
R/(W)*1
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29. Serial Communications Interface (SCI)
Bit
Symbol
Bit name
Description
R/W
b4
FER
Framing Error Flag
0: No framing error occurred
1: Framing error occurred.
R/(W)*1
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: Overrun error occurred.
R/(W)*1
b6
RDRF
Receive Data Full Flag
0: No received data in RDR register
1: Received data in RDR register.
R/(W)*1
b7
TDRE
Transmit Data Empty Flag
0: Transmit data in TDR register
1: No transmit data in TDR register.
R/(W)*1
Note 1.
Only 0 can be written to clear the flag after reading 1.
The SSR register provides the SCI status flags and transmission and reception multi-processor bits.
MPBT bit (Multi-Processor Bit Transfer)
The MPBT bit selects the multi-processor bit in the transmit frame.
MPB bit (Multi-Processor)
The MPB bit holds the value of the multi-processor bit in the reception frame. This bit does not change when the
SCR.RE bit is 0.
TEND flag (Transmit End Flag)
The TEND flag indicates completion of transmission.
[Setting conditions]
When the SCR.TE bit is set to 0 to disable serial transmission and the FCR.FM bit is set to 0 (non-FIFO selected).
When the SCR.TE bit is set to 1, the TEND flag is not affected and keeps the value 1.
When the TDR register is not updated on transmission of the tail-end bit of a character.
[Clearing conditions]
When transmit data is written to the TDR register while the SCR.TE bit is 1
When 0 is written to TDRE after reading TDRE = 1 while the SCR.TE bit is 1.
PER flag (Parity Error Flag)
The PER flag indicates that a parity error occurred during reception in asynchronous mode and the reception ended
abnormally.
[Setting condition]
When a parity error is detected during reception in asynchronous mode and the address match function is disabled
(DCCR.DCME = 0).
Although receive data is transferred to RDR when the parity error occurs, no SCIn_RXI interrupt request occurs.
When the PER flag is set to 1, the subsequent receive data is not transferred to RDR.
[Clearing condition]
When 0 is written to PER after reading PER = 1. After writing 0 to PER, read the PER bit to check that it was
actually set to 0.
When the SCR.RE is set to 0 to disable serial reception, the PER flag is not affected and keeps its previous value.
FER flag (Framing Error Flag)
The FER flag indicates that a framing error occurred during reception in asynchronous mode and the reception ended
abnormally.
[Setting condition]
When 0 is sampled as the stop bit during reception in asynchronous mode and the address match function is disabled
(DCCR.DCME = 0).
In 2-stop-bit mode, only the first stop bit is checked, but the second stop bit is not checked. Although receive data is
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29. Serial Communications Interface (SCI)
transferred to RDR when the framing error occurs, no SCIn_RXI interrupt request occurs. Also, when the FER flag
is set to 1, the subsequent receive data is not transferred to RDR.
[Clearing condition]
When 0 is written to FER after reading FER = 1. After writing 0 to FER, read the FER bit to check that it is actually
set to 0.
When the SCR.RE bit is set to 0, the FER flag is not affected and keeps its previous value.
ORER flag (Overrun Error Flag)
The ORER flag indicates that an overrun error occurred during reception and the reception ended abnormally.
[Setting condition]
When the next data is received before the receive data that does not have a parity error and a framing error is read
from RDR.
In RDR, data received prior to an overrun error occurrence is saved, but data received after the overrun error is lost.
When the ORER flag is set to 1, data received is not forwarded to RDR. In clock synchronous mode, serial
transmission and reception are stopped.
[Clearing condition]
When 0 is written to ORER after reading ORER = 1. After writing 0 to ORER, read the ORER bit to check that it is
actually set to 0.
When the RE bit in SCR is set to 0, the ORER flag is not affected and keeps its previous value.
RDRF flag (Receive Data Full Flag)
The RDRF flag indicates the presence of receive data in the RDR register.
[Setting condition]
When the reception ends normally, and receive data is forwarded from the RSR register to the RDR register.
[Clearing conditions]
When RDRF is set to 0 after 1 is read
When data is read from the RDR register.
Note:
Do not clear the RDRF flag by accessing the RDRF bit in the SSR register unless communication is aborted.
TDRE flag (Transmit Data Empty Flag)
The TDRE flag indicates the presence of transmit data in the TDR register.
[Setting conditions]
When the SCR.TE bit is 0
When data is transmitted from the TDR register to the TSR register.
[Clearing conditions]
When TDRE is set to 0 after 1 is read
When SCR.TE is 1, data is written to the TDR register.
Note:
Do not clear the TDRE flag by accessing the TDRE bit in the SSR register unless communication is aborted.
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29.2.14
29. Serial Communications Interface (SCI)
Serial Status Register for Non-Smart Card Interface and FIFO Mode
(SSR_FIFO) (SCMR.SMIF = 0 and FCR.FM = 1)
Address(es): SCI0.SSR_FIFO 4007 0004h, SCI1.SSR_FIFO 4007 0024h
b7
b6
b5
b4
b3
b2
b1
b0
TDFE
RDF
ORER
FER
PER
TEND
—
DR
1
0
0
0
0
0
x
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
DR
Receive Data Ready Flag
0: Reception is in progress, or no received data remains
in FRDRHL after reception is successfully completed
(receive FIFO is empty)
1: Next receive data is not received for a period after
normal reception is complete, when the amount of data
stored in the FIFO is equal to or less than the receive
triggering number.
R/(W)*1
b1
—
Reserved
The read value is undefined. The write value should be 1. R/W
b2
TEND
Transmit End Flag
0: A character is being transmitted
1: Character transfer is complete.
R/(W)*1
b3
PER
Parity Error Flag
0: No parity error occurred
1: A parity error occurred.
R/(W)*1
b4
FER
Framing Error Flag
0: No framing error occurred
1: A framing error occurred.
R/(W)*1
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: An overrun error occurred.
R/(W)*1
b6
RDF
Receive FIFO Data Full Flag
0: The amount of receive data written in FRDRHL is less
than the specified receive triggering number
1: The amount of receive data written in FRDRHL is
equal to or greater than the specified receive triggering
number.
R/(W)*1
b7
TDFE
Transmit FIFO Data Empty Flag
0: The amount of transmit data written in FTDRHL
exceeds the specified transmit triggering number
1: The amount of transmit data written in FTDRHL is
equal to or less than the specified transmit triggering
number.
R/(W)*1
Note 1.
Only 0 can be written to this bit to clear the flag after reading 1.
The SSR_FIFO register provides the SCI with FIFO mode status flags.
DR flag (Receive Data Ready Flag)
The DR flag indicates that the amount of data stored in the Receive FIFO Data Register (FRDRHL) falls below the
specified receive triggering number, and that no next data is received after 15 ETUs (elementary time units) from the last
stop bit in asynchronous mode. This flag bit is valid only in asynchronous mode, including multi-processor mode, when
the FIFO operation is selected.
In clock synchronous mode, this flag is not set to 1.
[Setting condition]
When FRDRHL contains less data than the specified receive triggering number, and no next data is received after
15 ETUs*1 from the last stop bit, and the SSR_FIFO.FER and SSR_FIFO.PER flags are 0.
[Clearing conditions]
When 1 is read from DR, after all the received data is read
When the FCR.FM bit is changed from 0 to 1.
Note 1. This is equivalent to 1.5 frames in the 8-bit format with 1 stop bit.
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29. Serial Communications Interface (SCI)
TEND flag (Transmit End Flag)
The TEND flag indicates that FTDRHL does not contain valid data when transmitting the last bit of a serial character, so
the transmission is halted.
[Setting condition]
When FTDRHL does not contain transmit data when the last bit of a 1-byte serial character is transmitted.
[Clearing conditions]
When transmit data is written to FTDRHL when the SCR.TE bit is 1
When 0 is written to TEND after 1 is read from TEND, when the SCR.TE bit is 1
When the FCR.FM bit is changed from 0 to 1.
PER flag (Parity Error Flag)
The PER flag indicates whether there is a parity error in the data read from the FRDRHL register in asynchronous mode
when the address match function is disabled (DCCR.DCME = 0).
[Setting condition]
When data is received and a parity error is detected, when the address match function is disabled (DCCR.DCME =
0).
[Clearing condition]
When 0 is written to PER after reading PER = 1.
The reception operation is continuous, and receive data is stored to the FRDRHL register even when a parity error occurs
during reception.
When the SCR.RE bit is set to 0, the PER flag is not affected and keeps it previous value.
FER flag (Framing Error Flag)
The FER flag indicates whether there is a framing error in the data read from the FRDRHL register in asynchronous
mode when the address match function is disabled (DCCR.DCME = 0).
[Setting condition]
When 0 is sampled as the stop bit during reception and the address match function is disabled (DCCR.DCME = 0).
[Clearing condition]
When 0 is written to FER after reading FER = 1.
The reception operation is continuous, and the receive data is stored to the FRDRHL register even when a framing error
occurs during reception.
When the SCR.RE bit is set to 0, the FER flag is not affected and the previous state is kept.
ORER flag (Overrun Error Flag)
The ORER flag indicates that the receive operation stopped abnormally because an overrun error occurred.
[Setting condition]
When the next serial reception completes while the receive FIFO is full with 16-byte receive data.
[Clearing condition]
When 0 is written after 1 is read from ORER.
When the SCR.RE bit is set to 0, the ORER flag is not affected and keeps its previous state.
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29. Serial Communications Interface (SCI)
RDF flag (Receive FIFO Data Full Flag)
The RDF flag indicates that receive data is transferred to FRDRHL and the amount of data in FRDRHL is equal to or
exceeds the specified receive triggering number. When RTRG is set to 0, the RDF flag is not set even when the amount
of data in the receive FIFO is equal to 0.
[Setting condition]
When the amount of receive data equal to or greater than the specified receive triggering number is stored in
FRDRHL,*1 and the FIFO is not empty.
[Clearing conditions]
When 0 is written after 1 is read from RDF
When FRDRHL is read by the DMAC or DTC, but only when the block transfer is the last transmission
When the setting condition and clearing condition occur at the same time. After that, when the amount of data stored
in the FRDRHL register is the same as or greater than the RTRG value, RDF is set to 1 after 1 PCLK.
Note 1. Because the FRDRHL is a 16-stage FIFO register, the maximum amount of data that can be read when RDF is 1
is equivalent to the specified receive triggering number. If an attempt is made to read after all the data in
FRDRHL is read, the data is undefined.
Note:
Do not clear the RDF flags by accessing the RDF bit in the SSR register before reading receive data unless
communication is aborted.
TDFE flag (Transmit FIFO Data Empty Flag)
The TDFE flag indicates that when data is transferred from FTDRHL into TSR, the amount of data in FTDRHL is less
than the specified transmit triggering number, and writing of transmit data to FTDRHL is enabled.
[Setting conditions]
When the TE bit in SCR is 0
When the amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering
number.*1
[Clearing conditions]
When writing to FTDRHL is executed on the last transmission while the DTC or DMAC is activated
When 0 is written to the TDFE bit after reading TDFE = 1.
When the setting condition and the clearing condition occur at the same time, the TDFE flag is cleared. After that,
when the amount of data stored in FTDRHL register is equal to or less than the TTRG value, TDFE is set to 1 after
1 PCLK.
Note 1. Because the FTDRHL register is a 16-stage FIFO register, the maximum amount of data that can be written
when the TDFE flag is set to 1 is 16 minus FDR.T[4:0]. If more data is written, data is discarded.
Note:
Do not clear the TDFE flags by accessing the TDFE bit in the SSR register before writing the transmit data unless
communication is aborted.
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29.2.15
29. Serial Communications Interface (SCI)
Serial Status Register for Smart Card Interface Mode (SSR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SSR_SMCI 4007 0004h, SCI1.SSR_SMCI 4007 0024h, SCI2.SSR_SMCI 4007 0044h,
SCI3.SSR_SMCI 4007 0064h, SCI4.SSR_SMCI 4007 0084h, SCI9.SSR_SMCI 4007 0124h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MPBT
Multi-Processor Bit Transfer
Set this bit to 0 in smart card interface mode
R/W
b1
MPB
Multi-Processor
Set this bit to 0 in smart card interface mode
R
b2
TEND
Transmit End Flag
0: A character is being transmitted
1: Character transfer is complete.
R
b3
PER
Parity Error Flag
0: No parity error occurred
1: A parity error occurred.
R/(W)*1
b4
ERS
Error Signal Status Flag
0: Low error signal is not sampled
1: Low error signal is sampled.
R/(W)*1
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: An overrun error occurred.
R/(W)*1
b6
RDRF
Receive Data Full Flag
0: No received data in RDR
1: Received data in RDR.
R/(W)*1
b7
TDRE
Transmit Data Empty Flag
0: Transmit data in TDR
1: No transmit data in TDR.
R/(W)*1
Note 1.
Only 0 can be written to clear the flag after reading 1.
The SSR_SMCI register provides SCI with smart card interface mode status flags.
TEND flag (Transmit End Flag)
With no error signal from the receiving side, the TEND flag is set to 1 when more data is ready to be transferred to the
TDR register.
[Setting conditions]
When the SCR_SMCI.TE bit = 0, to disable serial transmission. When the SCR_SMCI.TE bit changes from 0 to 1,
the TEND flag is not affected and keeps the value 1.
When a specified period elapses after the latest transmission of 1 byte, the ERS flag is 0, and the TDR register is not
updated.
The set timing is determined by the following register settings:
When SMR_SMCI.GM = 0 and SMR_SMCI.BLK = 0, 12.5 ETU after the start of transmission
When SMR_SMCI.GM = 0 and SMR_SMCI.BLK = 1, 11.5 ETU after the start of transmission
When SMR_SMCI.GM = 1 and SMR_SMCI.BLK = 0, 11.0 ETU after the start of transmission
When SMR_SMCI.GM = 1 and SMR_SMCI.BLK = 1, 11.0 ETU after the start of transmission.
[Clearing conditions]
When transmit data is written to the TDR register when the SCR_SMCI.TE bit is 1
When 0 is written to TDRE after reading TDRE = 1, when the SCR_SMCI.TE bit is 1.
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29. Serial Communications Interface (SCI)
PER flag (Parity Error Flag)
The PER flag indicates that a parity error occurs during reception in asynchronous mode and the reception ended
abnormally.
[Setting condition]
When a parity error is detected during reception. Although receive data is transferred to RDR when a parity error
occurs, no SCIn_RXI interrupt request occurs. When the PER flag is set to 1, the subsequent receive data is not
transferred to RDR.
[Clearing condition]
When 0 is written to the PER bit after reading PER = 1. After writing 0 to the PER bit, read the PER bit to check that
it is actually set to 0.
When the RE bit in SCR_SMCI is set to 0 (serial reception is disabled), the PER flag is not affected and keeps its
previous value.
ERS flag (Error Signal Status Flag)
[Setting condition]
When a low error signal is sampled.
[Clearing condition]
When 0 is written to ERS after reading ERS = 1.
ORER flag (Overrun Error Flag)
The ORER flag indicates that an overrun error occurred during reception and the reception ended abnormally.
[Setting condition]
When the next data is received before receive data that does not have a parity error is read from the RDR register. In
RDR, the data received before an overrun error occurred is saved, but data received after the overrun error is lost.
When the ORER flag is set to 1, the received data is not forwarded to the RDR register.
[Clearing condition]
When 0 is written to ORER after reading ORER = 1. After writing 0 to the ORER bit, read the ORER bit to check
that it is actually set to 0.
When the RE bit in SCR_SMCI is set to 0, the ORER flag is not affected and keeps its previous value.
RDRF flag (Receive Data Full Flag)
The RDRF flag indicates the presence of receive data in RDR.
[Setting condition]
When the reception ends normally, and receive data is forwarded from the RSR register to the RDR register.
[Clearing conditions]
When 0 is written to RDRF after 1 is read
When data is read from the RDR register.
Note:
Do not clear the RDRF flags by accessing the RDRF bit in the SSR register unless communication is aborted.
TDRE flag (Transmit Data Empty Flag)
The TDRE flag indicates the presence of transmit data in the TDR register.
[Setting conditions]
When the SCR_SMCI.TE bit is 0
When data is transmitted from the TDR register to the TSR register.
[Clearing conditions]
When 0 is written to TDRE after 1 is read
When the SCR_SMCI.TE bit is 1 and data is forwarded to the TDR register.
Note:
Do not clear the TDRE flags by accessing the TDRE bit in the SSR register unless communication is aborted.
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S3A1 User’s Manual
29.2.16
29. Serial Communications Interface (SCI)
Smart Card Mode Register (SCMR)
Address(es): SCI0.SCMR 4007 0006h, SCI1.SCMR 4007 0026h, SCI2.SCMR 4007 0046h,
SCI3.SCMR 4007 0066h, SCI4.SCMR 4007 0086h, SCI9.SCMR 4007 0126h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
BCP2
—
—
CHR1
SDIR
SINV
—
SMIF
1
1
1
1
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
SMIF
Smart Card Interface Mode Select
0: Non-smart card interface mode
(asynchronous mode, clock synchronous mode, simple
SPI mode, or simple IIC mode)
1: Smart card interface mode.
R/W*1
b1
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b2
SINV
Transmitted/Received Data Invert
0: TDR contents are transmitted as is. Receive data is stored
as received in the RDR
1: TDR contents are inverted before being transmitted.
Receive data is stored in inverted form in the RDR.
This bit can be used in the following modes:
Smart card interface mode
Asynchronous mode including multi-processor mode
Clock synchronous mode
Simple SPI mode.
Set this bit to 0 for operation in simple IIC mode.
R/W*1
b3
SDIR
Transmitted/Received Data
Transfer Direction
0: Transfer with LSB-first
1: Transfer with MSB-first.
This bit can be used in the following modes:
Smart card interface mode
Asynchronous mode including multi-processor mode
Clock synchronous mode
Simple SPI mode.
Set the SDIR bit to 1 for operation in simple IIC mode.
R/W*1
b4
CHR1
Character Length 1
Valid only in asynchronous mode.*2
Selects the character length in combination with the CHR bit
in SMR:
R/W*1
CHR1 CHR
0
0
1
1
0: Transmit/receive in 9-bit data length
1: Transmit/receive in 9-bit data length
0: Transmit/receive in 8-bit data length (initial value)
1: Transmit/receive in 7-bit data length*3.
b6, b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b7
BCP2
Base Clock Pulse 2
Selects the number of base clock cycles in combination with
the SMR_SMCI.BCP[1:0] bits.
Table 29.4 lists the combinations of the SCMR.BCP2 bit and
SMR_SMCI.BCP[1:0] bits.
R/W*1
Note 1.
Note 2.
Note 3.
Writable only when TE and RE in SCR/SCR_SMCI are 0 (both serial transmission and reception are disabled).
The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.
LSB-first should be selected and the value of the MSB bit [7] in TDR cannot be transmitted.
The SCMR register selects the smart card interface and communication format.
SMIF bit (Smart Card Interface Mode Select)
Setting the SMIF bit to 1 selects the smart card interface mode. Setting it to 0 selects all the other modes as follows:
Asynchronous mode, including multi-processor mode
Clock synchronous mode
Simple SPI mode
Simple IIC mode.
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S3A1 User’s Manual
29. Serial Communications Interface (SCI)
SINV bit (Transmitted/Received Data Invert)
The SINV bit inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit.
To invert the parity bit, invert the PM bit in SMR or SMR_SMCI.
CHR1 bit (Character Length 1)
The CHR1 bit selects the data length of transmit/receive data in combination with the CHR bit in SMR.
A fixed data length of 8 bits is used in modes other than asynchronous mode.
BCP2 bit (Base Clock Pulse 2)
The BCP2 bit selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode.
Set this bit in combination with the SMR_SMCI.BCP[1:0] bits.
Table 29.4
Combinations of the SCMR.BCP2 and SMR_SMCI.BCP[1:0] bits
SCMR.BCP2 bit
SMR_SMCI.BCP[1:0] bits
Number of base clock cycles for 1-bit transfer period
0
00
93 clock cycles (S = 93)*1
0
01
128 clock cycles (S = 128)*1
0
10
186 clock cycles (S = 186)*1
0
11
512 clock cycles (S = 512)*1
1
00
32 clock cycles (S = 32)*1 (initial value)
1
01
64 clock cycles (S = 64)*1
1
10
372 clock cycles (S = 372)*1
1
11
256 clock cycles (S = 256)*1
Note 1.
For S, see section 29.2.17, Bit Rate Register (BRR).
29.2.17
Bit Rate Register (BRR)
Address(es): SCI0.BRR 4007 0001h, SCI1.BRR 4007 0021h, SCI2.BRR 4007 0041h,
SCI3.BRR 4007 0061h, SCI4.BRR 4007 0081h, SCI9.BRR 4007 0121h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
BRR is an 8-bit register that adjusts the bit rate.
As each SCI channel has independent baud rate generator control, different bit rates can be set for each. Table 29.5 shows
the relationship between the setting (N) and the bit rate (B) in the BRR for asynchronous mode, multi-processor transfer,
clock synchronous mode, smart card interface mode, simple SPI mode, and simple IIC mode.
The initial value of BRR is FFh. BRR can be read by the CPU, but it can be written to only when the TE and RE bits in
SCR/SCR_SMCI are 0.
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S3A1 User’s Manual
Table 29.5
29. Serial Communications Interface (SCI)
Relationship between N setting in BRR and bit rate B
SEMR settings
Mode
BGDM ABCS
bit
bit
Asynchronous,
multi-processor
transfer
0
ABCSE
bit
0
BRR setting
0
N=
1
0
1
0
1
1
0
N=
N=
Don’t
care
PCLK × 106
64 × 22n-1 × B
-1
Error (%) = {
-1
Error (%) = {
-1
Error (%) = {
-1
Error (%) = {
PCLK × 106
B × 64 × 22n-1 × (N + 1)
- 1 } × 100
0
0
Don’t
care
Error
1
Clock synchronous,
simple SPI
N=
N=
Smart card interface
N=
Simple IIC*1
N=
PCLK × 106
32 ×
22n-1
×B
PCLK × 106
16 ×
22n-1
×B
PCLK × 106
12 × 22n-1 × B
PCLK × 106
PCLK × 106
B × 32 × 22n-1 × (N + 1)
PCLK × 106
B × 16 × 22n-1 × (N + 1)
PCLK × 106
B × 12 × 22n-1 × (N + 1)
- 1 } × 100
- 1 } × 100
- 1 } × 100
-1
8 × 22n-1 × B
PCLK × 106
-1
S × 22n+1 × B
PCLK × 106
Error (%) = {
PCLK × 106
B × S × 22n+1 × (N + 1)
- 1 } × 100
-1
64 × 22n-1 × B
B: Bit rate (bps)
N: BRR setting for on-chip baud rate generator (0 ≤ N ≤ 255)
PCLK: Operating frequency (MHz)
n and S: Determined by the settings of the SMR/SMR_SMCI and SCMR registers as listed in Table 29.7 and Table 29.8.
Note 1.
Adjust the bit rate so that the widths at high and low level of the SCLn output in simple IIC mode satisfy the I2C standard.
Table 29.6
Calculating widths at high and low level for SCL
Mode
SCL
Formula (result in seconds)
IIC
Width at high level
(minimum value)
(N+1) × 4 × 2
Width at low level
(minimum value)
(N+1) × 4 × 2
Table 29.7
2n-1
2n-1
×7×
×8×
1
PCLK × 10
6
1
PCLK × 10
6
Clock source settings
SMR or SMR_SMCI.CKS[1:0] bit setting
CKS[1:0] bits
Clock source
n
00
PCLK clock
0
01
PCLK/4 clock
1
10
PCLK/16 clock
2
11
PCLK/64 clock
3
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Oct 29, 2018
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S3A1 User’s Manual
Table 29.8
29. Serial Communications Interface (SCI)
Base clock settings in smart card interface mode
SCMR.BCP2 bit setting
SMR_SMCI.BCP[1:0] bit setting
Base clock cycles for 1-bit period
S
0
00
93 clock cycles
93
0
01
128 clock cycles
128
0
10
186 clock cycles
186
0
11
512 clock cycles
512
1
00
32 clock cycles
32
1
01
64 clock cycles
64
1
10
372 clock cycles
372
1
11
256 clock cycles
256
Table 29.9 and Table 29.10 list examples of BRR (N) settings in asynchronous mode. Table 29.11 lists the maximum bit
rate selectable for each operating frequency. Table 29.14 lists the examples of BRR (N) settings in smart card interface
mode.
Table 29.17 lists the examples of BRR (N) settings in simple IIC mode. In smart card interface mode, the number of base
clock cycles S in a 1-bit data transfer time can be selected. For details, see section 29.6.4, Receive Data Sampling Timing
and Reception Margin. Table 29.12 and Table 29.14 list the maximum bit rates with external clock input.
When either the Asynchronous Mode Base Clock Select (ABCS) bit or the Baud Rate Generator Double-Speed Mode
Select (BGDM) bit in the Serial Extended Mode Register (SEMR) is set to 1 in asynchronous mode, the bit rate becomes
twice the value listed in Table 29.16. When both of those bits are set to 1, the bit rate becomes four times the listed value.
Table 29.9
Examples of BRR settings for different bit rates in asynchronous mode (1)
Operating frequency PCLK (MHz)
Bit rate
(bps)
8
9.8304
10
12
12.288
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
2
141
0.03
2
174
-0.26
2
177
-0.25
2
212
0.03
2
217
0.08
150
2
103
0.16
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
207
0.16
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
103
0.16
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
207
0.16
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
103
0.16
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
51
0.16
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
25
0.16
0
31
0.00
0
32
-1.36
0
38
0.16
0
39
0.00
19200
0
12
0.16
0
15
0.00
0
15
1.73
0
19
-2.34
0
19
0.00
31250
0
7
0.00
0
9
-1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
-
-
-
0
7
0.00
0
7
1.73
0
9
-2.34
0
9
0.00
Operating frequency PCLK (MHz)
Bit rate
(bps)
14
16
17.2032
18
19.6608
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
2
248
-0.17
3
70
0.03
3
75
0.48
3
79
-0.12
3
86
0.31
150
2
181
0.16
2
207
0.16
2
223
0.00
2
233
0.16
2
255
0.00
300
2
90
0.16
2
103
0.16
2
111
0.00
2
116
0.16
2
127
0.00
600
1
181
0.16
1
207
0.16
1
223
0.00
1
233
0.16
1
255
0.00
1200
1
90
0.16
1
103
0.16
1
111
0.00
1
116
0.16
1
127
0.00
2400
0
181
0.16
0
207
0.16
0
223
0.00
0
233
0.16
0
255
0.00
4800
0
90
0.16
0
103
0.16
0
111
0.00
0
116
0.16
0
127
0.00
9600
0
45
-0.93
0
51
0.16
0
55
0.00
0
58
-0.69
0
63
0.00
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29. Serial Communications Interface (SCI)
Operating frequency PCLK (MHz)
Bit rate
(bps)
14
16
17.2032
18
19.6608
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
19200
0
22
-0.93
0
25
0.16
0
27
0.00
0
28
1.02
0
31
0.00
31250
0
13
0.00
0
15
0.00
0
16
1.20
0
17
0.00
0
19
-1.70
38400
-
-
-
0
12
0.16
0
13
0.00
0
14
-2.34
0
15
0.00
Note:
In this example, SEMR.ABCS = 0 and SEMR.ABCSE = 0 and SEMR.BGDM = 0.
When either the ABCS or BGDM bit is set to 1, the bit rate doubles.
When both ABCS and BGDM are set to 1, the bit rate quadruples.
Table 29.10
Examples of BRR settings for different bit rates in asynchronous mode (2)
Operating frequency PCLK (MHz)
Bit rate
(bps)
20
25
30
33
n
N
Error (%)
n
N
Error (%)
n
N
n
N
n
N
110
3
88
-0.25
3
110
-0.02
3
132 0.13
3
145 0.33
3
177 -0.25
150
3
64
0.16
3
80
0.47
3
97
3
106 0.39
3
129 0.16
300
2
129 0.16
2
162 -0.15
2
194 0.16
2
214 -0.07
3
64
600
2
64
0.16
2
80
2
97
2
106 0.39
2
129 0.16
1,200
1
129 0.16
1
162 -0.15
1
194 0.16
1
214 -0.07
2
64
0.47
-0.35
-0.35
Error (%)
0.16
0.16
1
64
0.16
1
80
1
97
1
106 0.39
1
129 0.16
4,800
0
129 0.16
0
162 -0.15
0
194 0.16
0
214 -0.07
1
64
9,600
0
64
0.16
0
80
0.47
0
97
-0.35
0
106 0.39
0
129 0.16
19,200
0
32
-1.36
0
40
-0.76
0
48
-0.35
0
53
-0.54
0
64
0.16
31,250
0
19
0.00
0
24
0.00
0
29
0.00
0
32
0.00
0
39
0.00
38,400
0
15
1.73
0
19
1.73
0
23
1.73
0
26
-0.54
0
32
-1.36
0.16
In this example, SEMR.ABCS = 0 and SEMR.ABCSE = 0 and SEMR.BGDM = 0.
When either the ABCS bit or BGDM bit is set to 1, the bit rate doubles.
When both ABCS and BGDM are set to 1, the bit rate quadruples.
Table 29.11
Maximum bit rate for each operating frequency in asynchronous mode (1 of 2)
SEMR settings
PCLK
(MHz)
BGDM
bit
ABCS
bit
ABCSE
bit
n
N
Maximum
bit rate
(bps)
8
0
0
0
0
0
250000
1
0
0
0
500000
1
0
0
0
0
1
0
0
0
1000000
Don’t
care
Don’t
care
1
0
0
1333333
0
0
0
0
0
307200
1
0
0
0
614400
1
0
0
0
0
1
0
0
0
1228800
Don’t
care
1
0
0
1638400
9.8304
-0.35
Error (%)
2,400
Note:
0.47
Error (%)
40
Don’t
care
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
SEMR settings
PCLK
(MHz)
BGDM
bit
ABCS
bit
ABCSE
bit
n
N
Maximum
bit rate
(bps)
17.2032
0
0
0
0
0
537600
1
0
0
0
1075200
0
0
0
0
1
0
0
0
2150400
Don’t
care
Don’t
care
1
0
0
2867200
0
0
0
0
0
562500
1
0
0
0
1125000
0
0
0
0
1
0
0
0
2250000
Don’t
care
1
0
0
3000000
1
18
1
Don’t
care
Page 778 of 1619
S3A1 User’s Manual
Table 29.11
29. Serial Communications Interface (SCI)
Maximum bit rate for each operating frequency in asynchronous mode (2 of 2)
SEMR settings
PCLK
(MHz)
BGDM
bit
ABCS
bit
ABCSE
bit
n
N
Maximum
bit rate
(bps)
10
0
0
0
0
0
312500
1
0
0
0
625000
1
0
0
0
0
1
0
0
0
1250000
Don’t
care
Don’t
care
1
0
0
1666666
0
0
0
0
0
375000
1
0
0
0
750000
1
0
0
0
0
12
12.288
14
16
40
0
0
0
1500000
Don’t
care
1
0
0
2000000
0
0
0
0
0
384000
1
0
0
0
768000
0
0
0
0
1
0
0
0
1536000
Don’t
care
1
0
0
2048000
0
0
0
0
0
437500
1
0
0
0
875000
0
0
0
0
1
0
0
0
1750000
Don’t
care
Don’t
care
1
0
0
2333333
0
0
0
0
0
500000
1
0
0
0
1000000
1
0
0
0
0
1
0
0
0
2000000
Don’t
care
Don’t
care
1
0
0
2666666
0
0
0
0
0
1250000
1
0
0
0
2500000
1
0
0
0
0
1
0
0
0
5000000
Don’t
care
1
0
0
6666666
Table 29.12
ABCS
bit
ABCSE
bit
n
N
Maximum
bit rate
(bps)
19.6608
0
0
0
0
0
614400
1
0
0
0
1228800
0
0
0
0
1
0
0
0
2457600
Don’t
care
Don’t
care
1
0
0
3276800
0
0
0
0
0
625000
1
0
0
0
1250000
0
0
0
0
20
25
1
0
0
0
2500000
Don’t
care
Don’t
care
1
0
0
3333333
0
0
0
0
0
781250
1
0
0
0
1562500
0
0
0
0
1
Don’t
care
Don’t
care
BGDM
bit
1
1
1
PCLK
(MHz)
1
Don’t
care
1
SEMR settings
30
1
0
0
0
3125000
Don’t
care
Don’t
care
1
0
0
4166666
0
0
0
0
0
937500
1
0
0
0
1875000
1
33
0
0
0
0
1
0
0
0
3750000
Don’t
care
Don’t
care
1
0
0
5000000
0
0
0
0
0
1031250
1
0
0
0
2062500
0
0
0
0
1
0
0
0
4125000
Don’t
care
1
0
0
5500000
1
Don’t
care
Maximum bit rate with external clock input in asynchronous mode (1 of 2)
Maximum bit rate (bps)
PCLK (MHz)
External input clock (MHz)
SEMR.ABCS bit = 0
SEMR.ABCS bit = 1
8
2.0000
125000
250000
9.8304
2.4576
153600
307200
10
2.5000
156250
312500
12
3.0000
187500
375000
12.288
3.0720
192000
384000
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 779 of 1619
S3A1 User’s Manual
Table 29.12
29. Serial Communications Interface (SCI)
Maximum bit rate with external clock input in asynchronous mode (2 of 2)
Maximum bit rate (bps)
PCLK (MHz)
External input clock (MHz)
SEMR.ABCS bit = 0
SEMR.ABCS bit = 1
14
3.5000
218750
437500
16
4.0000
250000
500000
17.2032
4.3008
268800
537600
18
4.5000
281250
562500
19.6608
4.9152
307200
614400
20
5.0000
312500
625000
25
6.2500
390625
781250
30
7.5000
468750
937500
33
8.2500
515625
1031250
40
10.0000
625000
1250000
Table 29.13
BRR settings for different bit rates in clock synchronous mode and simple SPI mode
Operating frequency PCLK (MHz)
8
Bit rate (bps)
10
16
20
n
N
n
N
n
N
250
3
124
—
—
3
249
25
n
N
30
33
n
N
n
N
3
233
3
97
3
40
n
N
n
N
116
3
128
3
155
110
500
2
249
—
—
3
124
—
—
1k
2
124
—
—
2
249
—
—
2.5 k
1
199
1
249
2
99
2
124
2
155
2
187
2
205
2
249
5k
1
99
1
124
1
199
1
249
2
77
2
93
2
102
2
124
10 k
0
199
0
249
1
99
1
124
1
155
1
187
1
205
1
249
25 k
0
79
0
99
0
159
0
199
0
249
1
74
1
82
1
99
50 k
0
39
0
49
0
79
0
99
0
124
0
149
0
164
1
49
100 k
0
19
0
24
0
39
0
49
0
62
0
74
0
82
0
99
250 k
0
7
0
9
0
15
0
19
0
24
0
29
0
32
0
39
500 k
0
3
0
4
0
7
0
9
—
—
0
14
—
—
0
19
1M
0
1
0
3
0
4
—
—
—
—
—
—
0
9
0
0*1
0
1
—
—
0
2
—
—
0
3
0
0*1
—
—
—
—
—
—
0
1
0
0*1
2.5 M
5M
7.5 M
Space: Setting prohibited.
—: Can be set, but an error will occur.
Note 1.
Continuous transmission or reception is impossible. After transmitting or receiving one frame of data, a 1-bit period elapses
before starting to transmit or receive the next frame of data. The output of the synchronization clock is stopped for a 1-bit
period. Therefore, it takes 9 bits worth of time to transfer one frame (8 bits) of data, and the average transfer rate is 8/9 times
the bit rate.
Table 29.14
Maximum bit rate with external clock input in clock synchronous mode and simple SPI mode (1 of
2)
PCLK (MHz)
External input clock (MHz)
Maximum bit rate (Mbps)
8
1.3333
1.3333333
10
1.6667
1.6666667
12
2.0000
2.0000000
14
2.3333
2.3333333
16
2.6667
2.6666667
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 780 of 1619
S3A1 User’s Manual
Table 29.14
29. Serial Communications Interface (SCI)
Maximum bit rate with external clock input in clock synchronous mode and simple SPI mode (2 of
2)
PCLK (MHz)
External input clock (MHz)
Maximum bit rate (Mbps)
18
3.0000
3.0000000
20
3.3333
3.3333333
25
4.1667
4.1666667
30
5.0000
5.0000000
33
5.5000
5.5000000
40
6.6667
6.6666667
Table 29.15
BRR settings for different bit rates in smart card interface mode, n = 0, S = 372
Operating frequency PCLK (MHz)
7.1424
10.00
10.7136
13.00
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9,600
0
0
0.00
0
1
-30
0
1
-25
0
1
-8.99
Operating frequency PCLK (MHz)
14.2848
16.00
18.00
20.00
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9,600
0
1
0.00
0
1
12.01
0
2
-15.99
0
2
-6.66
Operating frequency PCLK (MHz)
25.00
30.00
33.00
40.00
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9,600
0
3
-12.49
0
3
5.01
0
4
-7.59
0
5
-6.66
Table 29.16
Maximum bit rate for each operating frequency in smart card interface mode, S = 32
PCLK (MHz)
Maximum bit rate (bps)
n
N
10.00
156250
0
0
10.7136
167400
0
0
13.00
203125
0
0
16.00
250000
0
0
18.00
281250
0
0
20.00
312500
0
0
25.00
390625
0
0
30.00
468750
0
0
33.00
515625
0
0
40.00
625000
0
0
Table 29.17
BRR settings for different bit rates in simple IIC mode (1 of 2)
Operating frequency PCLK (MHz)
Bit rate
(bps)
8
10
16
20
25
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
10 k
0
24
0.0
0
30
0.8
1
12
-3.8
1
15
-2.3
1
19
-2.3
25 k
0
9
0.0
0
12
-3.8
1
4
0.0
1
5
4.2
1
7
-2.3
50 k
0
4
0.0
0
5
4.2
1
2
-16.7
1
2
4.2
1
3
-2.3
100 k*1
0
2
-16.7
0
3
-21.9
0
4
0.0
0
6
-10.7
1
1
-2.3
250 k
0
0
0.0
0
0
25
0
1
0.0
0
2
-16.7
0
2
4.2
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 781 of 1619
S3A1 User’s Manual
Table 29.17
29. Serial Communications Interface (SCI)
BRR settings for different bit rates in simple IIC mode (2 of 2)
Operating frequency PCLK (MHz)
Bit rate
(bps)
8
n
10
N
Error (%)
n
16
N
Error (%)
n
20
N
Error (%)
25
n
N
Error (%)
n
N
Error (%)
350 k
0
1
-10.7
0
1
11.6*2
400 k*1
0
1
-21.9
0
1
-2.3*2
Operating frequency PCLK (MHz)
Bit rate
(bps)
30
33
40
n
N
Error (%)
n
N
Error (%)
n
N
10 k
1
22
1.9
1
25
-0.8
0
124 0.0
Error (%)
25 k
1
8
4.2
1
9
3.1
0
49
50 k
1
4
-6.3
1
4
3.1
0
24
0.0
100 k*1
1
2
-21.9
1
2
-14.1
0
12
-3.9
250 k
0
3
-6.3
0
3
3.1
0
4
0.0
350 k
0
2
-10.7
0
2
-1.8
0
3
-10.7
400 k*1
0
2
-21.9
0
2
-14.1
0
3
-21.9
0.0
Note 1. The bit rate of 100 kbps and 400 kbps indicate the set value at which the error is on the negative side.
Note 2. The minimum value of the low width is smaller than 1.3 µs, which is the standard value in the Fast mode.
Table 29.18
Minimum widths at high and low level for SCL at different bit rates in simple IIC mode
Operating frequency PCLK (MHz)
8
10
16
N
Min. widths at
high/low level
for SCL (μs)
n
20
N
Min. widths at
high/low level
for SCL (μs)
n
N
Min. widths at
high/low level
for SCL (μs)
Bit rate
(bps)
n
N
Min. widths at
high/low level
for SCL (μs)
10 k
0
24
43.75/50.00
0
30
43.40/49.60
1
12
45.5/52.00
1
15
44.80/51.20
25 k
0
9
17.50/20.00
0
12
18.2/20.80
1
4
17.50/20.00
1
5
16.80/19.20
50 k
0
4
8.75/10.00
0
5
8.40/9.60
1
2
10.50/12.00
1
2
8.40/9.60
100 k
0
2
5.25/6.00
0
3
5.60/6.40
0
4
4.38/5.00
0
6
4.90/5.60
250 k
0
0
1.75/2.00
0
0
1.40/1.60
0
1
1.75/2.00
n
0
2
2.10/2.40
350 k
0
1
1.40/1.60
400 k
0
1
1.40/1.60
Min. widths at
high/low level
for SCL (μs)
Operating frequency PCLK (MHz)
25
30
N
n
N
25
44.12/50.42
0
124 43.75/50.00
1
9
16.97/19.39
0
49
17.50/20.00
9.33/10.66
1
4
8.48/9.70
0
24
8.75/10.00
5.60/6.40
1
2
5.09/5.82
0
12
4.55/5.20
3
1.86/2.13
0
3
1.70/1.94
0
4
1.75/2.00
0
2
1.40/1.60
0
2
1.27/1.45
0
3
1.40/1.60
0
2
1.40/1.60
0
2
1.27 /1.45
0
3
1.40/1.60
N
n
22
42.93/49.60
1
1
8
16.80/19.20
8.96/10.24
1
4
4.48/5.12
1
2
2
1.68/1.92
0
N
n
19
44.80/51.20
1
1
7
17.92/20.48
50 k
1
3
100 k
1
1
250 k
0
n
10 k
1
25 k
350 k
0
1
1.12/1.28*1
400 k
0
1
1.12/1.28*1
40
Min. widths at
high/low level
for SCL (μs)
Min. widths at
high/low level
for SCL (μs)
Min. widths at
high/low level
for SCL (μs)
Bit rate
(bps)
33
Note 1. The minimum value of the low width is smaller than 1.3 µs, which is the standard value of the Fast mode. The
setting values are the same as in Table 29.17.
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 782 of 1619
S3A1 User’s Manual
29.2.18
29. Serial Communications Interface (SCI)
Modulation Duty Register (MDDR)
Address(es): SCI0.MDDR 4007 0012h, SCI1.MDDR 4007 0032h, SCI2.MDDR 4007 0052h,
SCI3.MDDR 4007 0072h, SCI4.MDDR 4007 0092h, SCI9.MDDR 4007 0132h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
MDDR corrects the bit rate adjusted by the BRR register.
When the BRME bit in SEMR is set to 1, the bit rate generated by the on-chip baud rate generator is evenly corrected
using the settings in MDDR (M/256). Table 29.19 shows the relationship between the MDDR setting (M) and the bit rate
(B).
The initial value of MDDR is FFh. Bit [7] in this register is fixed to 1. The CPU can read the MDDR register, but this
register is only writable when the TE and RE bits in SCR/SCR_SMCI are 0.
Table 29.19
Relationship between MDDR setting (M) and bit rate (B) when bit rate modulation function is used
SEMR settings
Mode
BGDM ABCS ABCSE
bit
bit
bit
Asynchronous,
multi-processor
transfer
0
0
BRR setting
0
N=
1
0
1
0
1
1
0
N=
N=
Don’t
care
Clock synchronous,
simple SPI*1
64 ×
22n-1
× (256/M) × B
-1
Error (%)
={
-1
Error (%)
={
-1
Error (%)
={
-1
Error (%)
={
PCLK × 106
B × 64 ×
22n-1
B × 32 ×
22n-1
× (256/M) × (N + 1)
- 1} × 100
0
0
Don’t
care
PCLK × 106
Error
PCLK × 106
32 ×
N=
16 × 22n-1 × (256/M) × B
PCLK × 106
12 ×
Simple IIC*2
N=
22n-1
× (256/M) × B
PCLK × 106
8 × 22n-1 × (256/M) × B
Smart card interface
N=
× (256/M) × B
PCLK × 106
1
N=
22n-1
PCLK × 106
S×
22n+1
× (256/M) × B
PCLK × 106
64 × 22n-1 × (256/M) × B
PCLK × 106
PCLK × 106
B × 16 × 22n-1 × (256/M) × (N + 1)
PCLK × 106
B × 12 ×
22n-1
-1
× (256/M) × (N + 1)
- 1} × 100
- 1} × 100
- 1} × 100
-
-1
-1
× (256/M) × (N + 1)
Error (%)
={
PCLK × 106
B×S×
22n+1
× (256/M) × (N + 1)
- 1} × 100
-
B: Bit rate (bps)
M: MDDR setting (128 ≤ MDDR ≤ 255)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
PCLK: Operating frequency (MHz)
n and S: Determined by the settings of the SMR/SMR_SMCI and SCMR registers as listed in Table 29.7 and Table 29.8. See section
29.2.17, Bit Rate Register (BRR) for details.
Note 1.
Note 2.
Do not use this function in clock synchronous mode or in the highest speed settings in simple SPI mode (SMR.CKS[1:0] = 00b,
SCR.CKE[1] = 0, and BRR = 0).
Adjust the bit rate so that the high and low-level widths of the SCLn output in simple IIC mode satisfy the I2C standard.
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 783 of 1619
S3A1 User’s Manual
29. Serial Communications Interface (SCI)
Table 29.20 lists examples of N settings in BRR and M settings in MDDR in asynchronous mode.
Table 29.20
Examples of BRR and MDDR settings for different bit rates in asynchronous mode (1)
Operating frequency PCLK (MHz)
8
9.8304
Bit rate
(bps)
n
N
38400
0
57600
16
M
BGDM
bit
Error
(%)
BGDM
bit
Error
(%)
n
N
M
5
236
0
0.03
0
7
(256)*1
0
0.00
0
10
173
1
-0.01
0
3
236
0
0.03
0
4
240
0
0.00
0
4
236
0
0.03
115200
0
1
236
0
0.03
0
1
192
0
0.00
0
4
236
1
0.03
230400
0
0
236
0
0.03
0
0
192
0
0.00
0
1
189
1
0.14
460800
0
0
236
1
0.03
0
0
192
1
0.00
0
0
189
1
0.14
BGDM
bit
Error
(%)
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
Operating frequency PCLK (MHz)
12
12.288
Bit rate
(bps)
n
N
38400
0
57600
14
M
BGDM
bit
Error
(%)
n
N
M
8
236
0
0.03
0
9
(256)*1
0
0.00
0
16
191
1
0.00
0
5
236
0
0.03
0
4
192
0
0.00
0
13
236
1
0.03
115200
0
2
236
0
0.03
0
4
192
1
0.00
0
6
236
1
0.03
230400
0
2
236
1
0.03
0
2
230
1
-0.17
0
2
202
1
-0.11
460800
0
0
157
1
-0.18
0
0
154
1
-0.26
0
0
135
1
0.14
Error
(%)
n
N
M
BGDM
bit
Error
(%)
n
Operating frequency PCLK (MHz)
16
17.2032
Bit rate
(bps)
n
N
38400
0
57600
115200
18
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
11
236
0
0.03
0
13
(256)*1
0
0.00
0
18
166
1
-0.01
0
7
236
0
0.03
0
6
192
0
0.00
0
18
249
1
-0.01
0
3
236
0
0.03
0
6
192
1
0.00
0
8
236
1
0.03
230400
0
1
236
0
0.03
0
3
219
1
-0.20
0
1
210
0
0.14
460800
0
1
236
1
0.03
0
1
219
1
-0.20
0
0
210
0
0.14
M
BGDM
bit
Error
(%)
N
M
BGDM
bit
Error
(%)
Operating frequency PCLK (MHz)
19.6608
20
BGDM
bit
Error
(%)
25
Bit rate
(bps)
n
N
M
38400
0
15
(256)*1
0
0.00
0
10
173
0
-0.01
0
11
151
0
0.00
57600
0
9
240
0
0.00
0
9
236
0
0.03
0
7
151
0
0.00
115200
0
4
240
0
0.00
0
4
236
0
0.03
0
3
151
0
0.00
230400
0
1
192
0
0.00
0
4
236
1
0.03
0
1
151
0
0.00
460800
0
0
192
0
0.00
0
0
189
0
0.14
0
0
151
0
0.00
Error
(%)
N
M
BGDM
bit
Error
(%)
n
N
n
Operating frequency PCLK (MHz)
30
33
Bit rate
(bps)
n
N
38400
0
57600
0
115200
230400
460800
Note 1.
40
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
36
194
1
0.01
0
14
143
0
0.01
0
21
173
0
-0.01
10
173
0
-0.01
0
9
143
0
0.01
0
38
230
1
-0.01
0
10
173
1
-0.01
0
4
143
0
0.01
0
9
236
0
0.03
0
6
220
1
-0.09
0
4
143
1
0.01
0
4
236
0
0.03
0
3
252
1
0.14
0
1
229
0
0.10
0
4
236
1
0.03
n
In this example, the ABCS and ABCSE bits in SEMR are 0.
SEMR.BRME = 0 (M = 256) disables the bit rate modulation function.
R01UM0010EU0120 Rev.1.20
Oct 29, 2018
Page 784 of 1619
S3A1 User’s Manual
29.2.19
29. Serial Communications Interface (SCI)
Serial Extended Mode Register (SEMR)
Address(es): SCI0.SEMR 4007 0007h, SCI1.SEMR 4007 0027h, SCI2.SEMR 4007 0047h,
SCI3.SEMR 4007 0067h, SCI4.SEMR 4007 0087h, SCI9.SEMR 4007 0127h
b7
b6
b5
RXDES BGDM NFEN
EL
Value after reset:
0
0
0
b4
b3
b2
ABCS ABCSE BRME
0
0
0
b1
b0
—
—
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
BRME
Bit Rate Modulation
Enable
0: Bit rate modulation function is disabled
1: Bit rate modulation function is enabled.
R/W*1
b3
ABCSE
Asynchronous Mode
Extended Base Clock
Select 1
Valid only in asynchronous mode with SCR.CKE[1] = 0:
0: Clock cycle number for 1-bit period is decided with combination of BGDM
and ABCS in SEMR
1: Baud rate is 6 base clock cycles for 1-bit period.
R/W*1
b4
ABCS
Asynchronous Mode
Base Clock Select
Valid only in asynchronous mode:
0: Selects 16 base clock cycles for 1-bit period
1: Selects 8 base clock cycles for 1-bit period.
R/W*1
b5
NFEN
Digital Noise Filter
Function Enable
In asynchronous mode:
0: Noise cancellation function for the RXDn input signal is disabled
1: Noise cancellation function for the RXDn input signal is enabled.
In simple IIC mode:
0: Noise cancellation function for the SCLn and SDAn input signals is
disabled
1: Noise cancellation function for the SCLn and SDAn input signals is
enabled.
The NFEN bit must be 0 in all other modes.
R/W*1
b6
BGDM
Baud Rate Generator
Double-Speed Mode
Select
Valid only in asynchronous mode with SCR.CKE[1] = 0:
0: Baud rate generator outputs the clock with single frequency
1: Baud rate generator outputs the clock with double frequency.
R/W*1
b7
RXDESEL
Asynchronous Start Bit
Edge Detection Select
Valid only in asynchronous mode:
0: A low level on the RXDn pin is detected as the start bit
1: A falling edge on the RXDn pin is detected as the start bit.
R/W*1
Note 1.
Writable only when TE and RE bits in SCR/SCR_SMCI are 0 (both serial transmission and reception are disabled).
SEMR selects the clock source for a 1-bit period in asynchronous mode.
BRME bit (Bit Rate Modulation Enable)
The BRME bit enables and disables the bit rate modulation function. The bit rate generated by the on-chip baud rate
generator is evenly corrected when this function is enabled.
ABCSE bit (Asynchronous Mode Extended Base Clock Select 1)
The ABCSE bit sets the pulse number for the base clock in a 1-bit period to 6, and the double-frequency clock is output
from the baud rate generator. When the bit rate is set to 6 while dividing the bus clock frequency, use the ABCSE bit and
set SMR.CKS[1:0] = 00b and BRR = 0. Set this bit to 0 except in asynchronous mode.
ABCS bit (Asynchronous Mode Base Clock Select)
The ABCS bit selects the clock cycles for a 1-bit period. Set this bit to 0 except in asynchronous mode.
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29. Serial Communications Interface (SCI)
NFEN bit (Digital Noise Filter Function Enable)
The NFEN bit enables or disables the digital noise filter function.
When the digital noise filter function is enabled:
Noise cancellation is applied to the RXDn input signal in asynchronous mode
Noise cancellation is applied to the SDAn and SCLn input signals in simple IIC mode.
In all other modes, set the NFEN bit to 0 to disable the digital noise filter function.
When the digital noise filter function is disabled, input signals are transferred as received.
BGDM bit (Baud Rate Generator Double-Speed Mode Select)
The BGDM bit selects the cycle of output clock for the baud rate generator to be either single or double frequency.
The BGDM bit is valid when the on-chip baud rate generator is selected as the clock source (SCR.CKE[1] = 0) in
asynchronous mode (SMR.CM = 0). The base clock is generated by the clock output from the baud rate generator. When
the BGDM bit is set to 1, the base clock cycle is halved and the bit rate is doubled.
Set this bit to 0 in modes other than asynchronous mode.
RXDESEL bit (Asynchronous Start Bit Edge Detection Select)
The RXDESEL bit selects the detection method of the start bit for reception in asynchronous mode. When a break
occurs, set RXDESEL bit to 1 to stop reception, or to start reception without retaining the RXDn pin input at a high level
for the period of one data frame or longer after completion of the break.
Set this bit to 0 in modes other than asynchronous mode.
29.2.20
Noise Filter Setting Register (SNFR)
Address(es): SCI0.SNFR 4007 0008h, SCI1.SNFR 4007 0028h, SCI2.SNFR 4007 0048h,
SCI3.SNFR 4007 0068h, SCI4.SNFR 4007 0088h, SCI9.SNFR 4007 0128h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
NFCS[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
NFCS[2:0]
Noise Filter Clock Select
In asynchronous mode, the standard setting for the base clock is as
follows:
R/W*1
b2
b0
0 0 0: The clock signal divided by 1 is used with the noise filter.
In simple IIC mode, the standard settings for the clock source of the
on-chip baud rate generator selected by the SMR.CKS[1:0] bits are
as follows:
b2
b0
0 0 1: The clock signal divided by 1 is used with the noise filter
0 1 0: The clock signal divided by 2 is used with the noise filter
0 1 1: The clock signal divided by 4 is used with the noise filter
1 0 0: The clock signal divided by 8 is used with the noise filter.
Other settings are prohibited.
b7 to b3
Note 1.
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Writing to these bits is only possible when the RE and TE bits in SCR/SCR_SMCI are 0 (serial reception and transmission
disabled).
The SNFR register sets the digital noise filter clock.
NFCS[2:0] bits (Noise Filter Clock Select)
The NFCS[2:0] bits select the sampling clock for the digital noise filter. To use the noise filter in asynchronous mode, set
these bits to 000b. In simple IIC mode, set the bits to a value in the range from 001b to 100b.
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29. Serial Communications Interface (SCI)
I2C Mode Register 1 (SIMR1)
29.2.21
Address(es): SCI0.SIMR1 4007 0009h, SCI1.SIMR1 4007 0029h, SCI2.SIMR1 4007 0049h,
SCI3.SIMR1 4007 0069h, SCI4.SIMR1 4007 0089h, SCI9.SIMR1 4007 0129h
b7
b6
b5
b4
b3
IICDL[4:0]
Value after reset:
0
0
0
0
0
b2
b1
b0
—
—
IICM
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICM
Simple IIC Mode Select
SMIF IICM
R/W*1
0
0
1
1
0: Asynchronous mode including multi-processor mode,
clock synchronous mode, or simple SPI mode
1: Simple IIC mode
0: Smart card interface mode
1: Setting prohibited.
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b3
IICDL[4:0]
SDA Delay Output Select
SDA signal output delay in cycles of the clock signal from the on-chip
baud rate generator are as follows:
R/W*1
b7
b3
0 0 0 0 0: No output delay
0 0 0 0 1: 0 to 1 cycle
0 0 0 1 0: 1 to 2 cycles
0 0 0 1 1: 2 to 3 cycles
0 0 1 0 0: 3 to 4 cycles
0 0 1 0 1: 4 to 5 cycles
:
:
1 1 1 1 0: 29 to 30 cycles
1 1 1 1 1: 30 to 31 cycles.
Note 1.
Writing to these bits is only possible when the RE and TE bits in SCR are 0 (both serial transmission and reception are
disabled).
SIMR1 selects simple IIC mode and the number of delay stages for the SDAn output.
IICM bit (Simple IIC Mode Select)
In combination with the SMIF bit in SCMR, the IICM bit selects the operating mode.
IICDL[4:0] bits (SDA Delay Output Select)
The IICDL[4:0] bits specify an output delay on the SDAn pin relative to the falling edge of the output on the SCLn pin.
The available delay settings range from no delay to 31 cycles, with the clock signal from the on-chip baud rate generator
as the base. The signal obtained by frequency-dividing PCLK by the divisor set in SMR.CKS[1:0] is supplied as the
clock signal from the on-chip baud rate generator. Set these bits to 00000b unless operation is in simple IIC mode. In
simple IIC mode, set the bits to a value in the range from 00001b to 11111b.
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29. Serial Communications Interface (SCI)
I2C Mode Register 2 (SIMR2)
29.2.22
Address(es): SCI0.SIMR2 4007 000Ah, SCI1.SIMR2 4007 002Ah, SCI2.SIMR2 4007 004Ah,
SCI3.SIMR2 4007 006Ah, SCI4.SIMR2 4007 008Ah, SCI9.SIMR2 4007 012Ah
Value after reset:
Bit
b7
b6
b5
b4
b3
b2
—
—
IICACK
T
—
—
—
0
0
0
0
0
0
b1
b0
IICCSC IICINT
M
0
0
Symbol
Bit name
Description
R/W
b0
IICINTM
I2C
0: Use ACK/NACK interrupts
1: Use reception and transmission interrupts.
R/W*1
b1
IICCSC
Clock Synchronization
0: Do not synchronize with the clock signal
1: Synchronize with the clock signal.
R/W*1
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
IICACKT
ACK Transmission Data
0: ACK transmission
1: NACK transmission and ACK/NACK reception.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Interrupt Mode Select
Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (serial reception and transmission disabled).
SIMR2 selects how reception and transmission are controlled in simple IIC mode.
IICINTM bit (I2C Interrupt Mode Select)
The IICINTM bit selects the sources of interrupt requests in simple IIC mode.
IICCSC bit (Clock Synchronization)
Set the IICCSC bit to 1 to synchronize the internally generated SCLn clock signal when the SCLn pin is driven low
because of a wait inserted by another device, for example.
The SCLn clock signal is not synchronized if this bit is 0. The SCLn clock signal is generated according to the rate
selected in the BRR regardless of the level input on the SCLn pin.
Set this bit to 1 except during debugging.
IICACKT bit (ACK Transmission Data)
Transmitted data contains ACK bits. Set the IICACKT bit to 1 when ACK and NACK bits are received.
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29. Serial Communications Interface (SCI)
I2C Mode Register 3 (SIMR3)
29.2.23
Address(es): SCI0.SIMR3 4007 000Bh, SCI1.SIMR3 4007 002Bh, SCI2.SIMR3 4007 004Bh,
SCI3.SIMR3 4007 006Bh, SCI4.SIMR3 4007 008Bh, SCI9.SIMR3 4007 012Bh
b7
b6
IICSCLS[1:0]
Value after reset:
0
0
b5
b4
IICSDAS[1:0]
0
b3
b2
b1
b0
IICSTIF IICSTP IICRST IICSTA
REQ AREQ REQ
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICSTAREQ
Start Condition Generation
0: Do not generate start condition
1: Generate start condition.*1, *3, *5, *6
R/W
b1
IICRSTAREQ
Restart Condition
Generation
0: Do not generate restart condition
1: Generate restart condition.*2, *3, *5, *6
R/W
b2
IICSTPREQ
Stop Condition Generation
0: Do not generate stop condition
1: Generate stop condition.*2, *3, *5, *6
R/W
b3
IICSTIF
Issuing of Start, Restart, or
Stop Condition Completed
Flag
0: No requests made for generating conditions, or a condition is
being generated
1: Generation of start, restart, or stop condition is complete.
When 0 is written to IICSTIF, it is cleared to 0.*4
R/W*4
b5, b4
IICSDAS[1:0]
SDA Output Select
b5 b4
R/W
b7, b6
IICSCLS[1:0]
SCL Output Select
b7 b6
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
0
0
1
1
0
0
1
1
0: Serial data output
1: Generate start, restart, or stop condition
0: Output low level on the SDAn pin
1: Drive SDAn pin to high-impedance state.
0: Serial clock output
1: Generate a start, restart, or stop condition
0: Output low level on the SCLn pin
1: Drive SCLn pin to high-impedance state.
Only generate a start condition after checking the bus state and confirming that the bus is free.
Generate a restart or stop condition after checking the bus state and confirming that the bus is busy.
Do not set more than one of the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits to 1 at a given time.
Write only 0. When 1 is written, the value is ignored.
Execute the generation of a condition after the value of the IICSTIF flag is 0.
Do not write 0 to this bit while it is 1. Generation of a condition is suspended by writing 0 to this bit while it is 1.
IICSTAREQ bit (Start Condition Generation)
When a start condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b in addition to setting
the IICSTAREQ bit to 1.
[Setting condition]
When 1 is written to this bit.
[Clearing condition]
When generation of a start condition is complete.
IICRSTAREQ bit (Restart Condition Generation)
When a restart condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b and set the
IICRSTAREQ bit to 1.
[Setting condition]
When 1 is written to this bit.
[Clearing condition]
When generation of a restart condition is complete.
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29. Serial Communications Interface (SCI)
IICSTPREQ bit (Stop Condition Generation
When a stop condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b and set the
IICSTPREQ bit to 1.
[Setting condition]
When 1 is written to this bit.
[Clearing condition]
When generation of a stop condition is complete.
IICSTIF flag (Issuing of Start, Restart, or Stop Condition Completed Flag)
After generating a condition, the IICSTIF flag indicates that the generation is complete. When using the IICSTAREQ,
IICRSTAREQ, or IICSTPREQ bit to cause generation of a condition, do so after setting the IICSTIF flag to 0.
When the IICSTIF flag is 1 when an interrupt request is enabled by setting the SCR.TEIE bit, an STI request is output.
[Setting condition]
When generation of a start, restart, or stop condition completes.
If this conflicts with any of the clearing conditions for the flag, the clearing condition takes precedence.
[Clearing conditions]
When 0 is written to this bit (then, confirm that the IICSTIF flag is 0)
When 0 is written to the SIMR1.IICM bit (when operation is not in simple IIC mode)
When 0 is written to the SCR.TE bit.
IICSDAS[1:0] bits (SDA Output Select)
The IICSDAS[1:0] bits control the output from the SDAn pin. Set the IICSDAS[1:0] and IICSCLS[1:0] bits to the same
value.
IICSCLS[1:0] bits (SCL Output Select)
The IICSCLS[1:0] bits control the output from the SCLn pin. Set the IICSCLS[1:0] and IICSDAS[1:0] bits to the same
value.
I2C Status Register (SISR)
29.2.24
Address(es): SCI0.SISR 4007 000Ch, SCI1.SISR 4007 002Ch, SCI2.SISR 4007 004Ch,
SCI3.SISR 4007 006Ch, SCI4.SISR 4007 008Ch, SCI9.SISR 4007 012Ch
b7
Value after reset:
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
IICACK
R
0
0
x
x
0
x
0
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
IICACKR
ACK Reception Data Flag
0: ACK received
1: NACK received.
R
b1
—
Reserved
This bit is read as 0
R
b2
—
Reserved
The read value is undefined
R
b3
—
Reserved
This bit is read as 0
R
b5, b4
—
Reserved
The read values are undefined
R
b7, b6
—
Reserved
These bits are read as 0
R
SISR monitors the state in simple IIC mode.
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29. Serial Communications Interface (SCI)
IICACKR flag (ACK Reception Data Flag)
Received ACK and NACK bits can be read from the IICACKR flag. The IICACKR flag is updated on the rising edge of
the SCLn clock for the received ACK/NACK bit.
29.2.25
SPI Mode Register (SPMR)
Address(es): SCI0.SPMR 4007 000Dh, SCI1.SPMR 4007 002Dh, SCI2.SPMR 4007 004Dh,
SCI3.SPMR 4007 006Dh, SCI4.SPMR 4007 008Dh, SCI9.SPMR 4007 012Dh
b7
b6
CKPH CKPOL
Value after reset:
0
0
b5
b4
b3
b2
b1
b0
—
MFF
—
MSS
CTSE
SSE
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSE
SSn Pin Function Enable
0: Disable SSn pin function
1: Enable SSn pin function.
R/W*1
b1
CTSE
CTS Enable
0: Disable CTS function (RTS output function is enabled)
1: Enable CTS function.
R/W*1
b2
MSS
Master Slave Select
0: Transmit through the TXDn pin and receive through the RXDn pin
(master mode)
1: Receive through the TXDn pin and transmit through the RXDn pin
(slave mode).
R/W*1
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
MFF
Mode Fault Flag
0: No mode fault error
1: Mode fault error.
R/W*2
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
CKPOL
Clock Polarity Select
0: Do not invert clock polarity
1: Invert clock polarity.
R/W*1
b7
CKPH
Clock Phase Select
0: Do not delay clock
1: Delay clock.
R/W*1
Note 1.
Note 2.
Writing to these bits is only possible when the RE and TE bits in SCR are 0 (both serial transmission and reception are
disabled).
Only 0 can be written to these bits, to clear the flag.
SPMR selects the extension settings in asynchronous and clock synchronous modes.
SSE bit (SSn Pin Function Enable)
Set the SSE bit to 1 to use the SSn pin to control transmission and reception in simple SPI mode. Set this bit to 0 in all
other modes. When master mode (SCR.CKE[1:0] = 00b and MSS = 0) is selected and there is a single master, the SSn
pin on the master side is not required to control reception and transmission. In such a case, set the SSE bit to 0. Do not
enable both the SSE and CTSE bits as the operation is the same as that when these bits are set to 0.
CTSE bit (CTS Enable)
Set the CTSE bit to 1 if the SSn pin is to be used for inputting the CTS control signal to control transmission and
reception. The RTS signal is output when this bit is set to 0. Set this bit to 0 in smart card interface mode, simple SPI
mode, and simple IIC mode. Do not set both the CTSE and SSE bits to 1 as the operation is the same as that when these
bits are set to 0.
MSS bit (Master Slave Select)
The MSS bit selects the master or slave operation in simple SPI mode. The functions of the TXDn and RXDn pins are
reversed when the MSS bit is set to 1, so that data is received through the TXDn pin and transmitted through the RXDn
pin. Set this bit to 0 in modes other than simple SPI mode.
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29. Serial Communications Interface (SCI)
MFF flag (Mode Fault Flag)
The MFF flag indicates mode fault errors. In a multi-master configuration, determine the mode fault error occurrence by
reading this flag.
[Setting condition]
When input on the SSn pin is low during master operation in simple SPI mode (SSE bit = 1 and MSS bit = 0).
[Clearing condition]
When 0 is written to the bit after it is read as 1.
CKPOL bit (Clock Polarity Select)
The CKPOL bit selects the polarity of the clock signal output through the SCKn pin. See Figure 29.70 for details.
Set the bit to 0 in modes other than simple SPI mode and clock synchronous mode.
CKPH bit (Clock Phase Select)
The CKPH bit selects the phase of the clock signal output through the SCKn pin. See Figure 29.70 for details.
Set the bit to 0 in modes other than simple SPI mode and clock synchronous mode.
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29.2.26
29. Serial Communications Interface (SCI)
FIFO Control Register (FCR)
Address(es): SCI0.FCR 4007 0014h, SCI1.FCR 4007 0034h
b15
b14
b13
b12
b11
RSTRG[3:0]
Value after reset:
1
1
1
b10
b9
b8
b7
RTRG[3:0]
1
1
0
0
b6
b5
b4
TTRG[3:0]
0
0
0
0
b3
b2
b1
DRES TFRST RFRST
0
0
0
0
b0
FM
0
Bit
Symbol
Bit name
Description
R/W
b0
FM
FIFO Mode Select
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode:
0: Non-FIFO mode.
Selects TDR/RDR or TDRHL/RDRHL for communication.
1: FIFO mode.
Selects FTDRHL/FRDRHL for communication.
R/W*1
b1
RFRST
Receive FIFO Data Register
Reset
Valid only when FCR.FM = 1:
0: Do not reset FRDRHL
1: Reset FRDRHL.
R/W
b2
TFRST
Transmit FIFO Data
Register Reset
Valid only when FCR.FM = 1:
0: Do not reset FTDRHL
1: Reset FTDRHL.
R/W
b3
DRES
Receive Data Ready Error
Select
Select the interrupt request when detecting a receive data ready:
0: Receive data full interrupt (SCIn_RXI)
1: Receive error interrupt (SCIn_ERI).
R/W
b7 to b4
TTRG[3:0]
Transmit FIFO Data Trigger
Number
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode:
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
b11 to b8
RTRG[3:0]
Receive FIFO Data Trigger
Number
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode:
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
b15 to b12
RSTRG[3:0]
RTS Output Active Trigger
Number Select
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode, while FCR.FM = 1, SPMR.CTSE = 0,
and SPMR.SSE = 0:
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
Note 1.
Writable only when TE = 0 and RE = 0.
FCR selects FIFO mode, resets FTDRHL/FRDRHL, selects the FIFO data trigger number for transmission or reception,
and selects the RTS output active trigger number.
FM bit (FIFO Mode Select)
When the FM bit is set to 1, FTDRHL and FRDRHL are selected for communication. When the FM bit is set to 0, TDR
and RDR, or TDRHL and RDRHL are selected for communication.
RFRST bit (Receive FIFO Data Register Reset)
When the RFRST bit is set to 1, the FRDRHL register is reset and the receive data count is reset to 0. When 1 is written
to RFRST, this bit is set to 0 after 1 PCLK.
TFRST bit (Transmit FIFO Data Register Reset)
When the TFRST bit is set to 1, the FTDRHL register is reset and the transmit data count is reset to 0. When 1 is written,
this bit is set to 0 after 1 PCLK.
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29. Serial Communications Interface (SCI)
DRES bit (Receive Data Ready Error Select)
On detecting a receive data ready error, the DRES bit selects the interrupt request from an SCIn_RXI interrupt request or
an SCIn_ERI interrupt request. Set the DRES bit to 1 when starting the DMAC or DTC and reading the FRDRH and
FRDRL registers.
TTRG[3:0] bits (Transmit FIFO Data Trigger Number)
The TDFE flag is set to 1 when the amount of transmit data in the Transmit FIFO Data Register (FTDRHL) is equal to or
less than the specified transmit triggering number, and software can write data to FTDRHL. If SCR.TIE = 1, an
SCIn_TXI interrupt request occurred.
RTRG[3:0] bits (Receive FIFO Data Trigger Number)
The RDF flag is set to 1 when the amount of receive data in the Receive FIFO Data Register (FRDRHL) is equal to or
greater than the specified receive triggering number, and software can read data from FRDRHL. If SCR.RIE = 1, an
SCIn_RXI interrupt request occurred.
When RTRG[3:0] is set to 0, the RDF flag is not set even when the amount of data in the receive FIFO is equal to 0, and
an SCIn_RXI interrupt does not occur.
RSTRG[3:0] bits (RTS Output Active Trigger Number Select)
When the amount of receive data stored in the Receive FIFO Data Register (FRDRHL) is equal to or greater than the
specified receive triggering number, the RTS signal goes high. When RSTRG[3:0] is set to 0, the RTS signal does not go
high even when the quality of the data in the receive FIFO is equal to 0.
29.2.27
FIFO Data Count Register (FDR)
Address(es): SCI0.FDR 4007 0016h, SCI1.FDR 4007 0036h
Value after reset:
b15
b14
b13
—
—
—
0
0
0
b12
b11
b10
b9
b8
T[4:0]
0
0
0
0
0
b7
b6
b5
—
—
—
0
0
0
b4
b3
b2
b1
b0
0
0
R[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
R[4:0]
Receive FIFO Data Count
Indicates the amount of receive data stored in FRDRHL (valid only in
asynchronous mode, including multi-processor or clock synchronous
mode, when FCR.FM = 1)
R
b7 to b5
—
Reserved
These bits are read as 0
R
b12 to b8
T[4:0]
Transmit FIFO Data Count
Indicates the amount of non-transmit data stored in FTDRHL (valid
only in asynchronous mode, including multi-processor or clock
synchronous mode, when FCR.FM = 1)
R
Reserved
These bits are read as 0
R
b15 to b13 —
This register indicates the amount of data stored in FRDRHL/FTDRHL.
R[4:0] bits (Receive FIFO Data Count)
The R[4:0] bits indicate the amount of receive data stored in FRDRHL. 00h indicates no receive data, and 10h indicates
that the maximum received data is stored in FRDRHL.
T[4:0] bits (Transmit FIFO Data Count)
The T[4:0] bits indicate the amount of non-transmitted data stored in FTDRHL. 00h indicates no transmit data, and 10h
indicates that all (maximum count) of the data to be transmitted is stored in FTDRHL.
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29.2.28
29. Serial Communications Interface (SCI)
Line Status Register (LSR)
Address(es): SCI0.LSR 4007 0018h, SCI1.LSR 4007 0038h
b15
b14
b13
—
—
—
0
0
0
Value after reset:
b12
b11
b10
b9
b8
PNUM[4:0]
0
0
0
b7
b6
b5
—
0
0
0
b4
b3
b2
FNUM[4:0]
0
0
0
0
0
b1
b0
—
ORER
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ORER
Overrun Error Flag
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode, with FIFO operation selected:
0: No overrun error occurred
1: Overrun error occurred.
R*1
b1
—
Reserved
This bit is read as 0
R
b6 to b2
FNUM[4:0]
Framing Error Count
Indicates the amount of data with a framing error in the receive data
stored in the Receive FIFO Data Register (FRDRHL)
R
b7
—
Reserved
This bit is read as 0
R
b12 to b8
PNUM[4:0]
Parity Error Count
Indicates the amount of data with a parity error among the receive
data stored in the Receive FIFO Data Register (FRDRHL)
R
b15 to b13
—
Reserved
These bits are read as 0
R
Note 1.
If this flag is 1, write 0 to SSR_FIFO.ORER to clear the flag.
The LSR register indicates the status of receive error.
ORER bit (Overrun Error Flag)
The ORER bit reflects the value in SSR_FIFO.ORER.
FNUM[4:0] bits (Framing Error Count)
The FNUM[4:0] bit value indicates the amount of data with a framing error stored in the FRDRHL register.
PNUM[4:0] bits (Parity Error Count)
The PNUM[4:0] bit value indicates the amount of data with a parity error stored in the FRDRHL register.
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29.2.29
29. Serial Communications Interface (SCI)
Compare Match Data Register (CDR)
Address(es): SCI0.CDR 4007 001Ah, SCI1.CDR 4007 003Ah, SCI2.CDR 4007 005Ah,
SCI3.CDR 4007 007Ah, SCI4.CDR 4007 009Ah, SCI9.CDR 4007 013Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
CMPD[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
CMPD[8:0]
Compare Match Data
Compare data pattern for address match wakeup function
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The CDR register sets the compare data for the address match function.
CMPD[8:0] bits (Compare Match Data)
The CMPD[8:0] bits set the data to be compared to receive data for the address match function, when the address match
function is enabled (DCCR.DCME = 1).
Three bit lengths are available:
CMPD[6:0] with 7-bit length
CMPD[7:0] with 8-bit length
CMPD[8:0] with 9-bit length.
29.2.30
Data Compare Match Control Register (DCCR)
Address(es): SCI0.DCCR 4007 0013h, SCI1.DCCR 4007 0033h, SCI2.DCCR 4007 0053h,
SCI3.DCCR 4007 0073h, SCI4.DCCR 4007 0093h, SCI9.DCCR 4007 0133h
b7
b6
DCME IDSEL
Value after reset:
0
1
b5
b4
b3
b2
b1
b0
—
DFER
DPER
—
—
DCMF
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DCMF
Data Compare Match Flag
0: Not matched
1: Matched.
R/(W)*1
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
DPER
Data Compare Match Parity
Error Flag
0: No parity error occurred
1: A parity error occurred.
R/(W)*1
b4
DFER
Data Compare Match
Framing Error Flag
0: No framing error occurred
1: A framing error occurred.
R/(W)*1
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
IDSEL
ID Frame Select
Valid only in asynchronous mode, including multi-processor:
0: Always compare data regardless of the MPB bit value
1: Compare data when the MPB bit is 1 (ID frame).
R/W
b7
DCME
Data Compare Match
Enable
Valid only in asynchronous mode, including multi-processor:
0: Address match function is disabled
1: Address match function is enabled.
R/W
Note 1.
Only 0 can be written to clear the flag after reading 1.
DCCR controls the address match function.
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29. Serial Communications Interface (SCI)
DCMF flag (Data Compare Match Flag)
The DCMF flag indicates that the SCI detects a match of the comparison data (CDR.CMPD) with receive data.
[Setting condition]
When comparison data (CDR.CMPD) matches the receive data, when DCCR.DCME = 1.
[Clearing condition]
When 0 is written after 1 is read from DCMF.
Clearing the RE bit to 0 in the Serial Control Register (SCR) does not affect the DCMF flag, which keeps its previous
value.
DPER flag (Data Compare Match Parity Error Flag)
The DPER flag indicates that a parity error occurred on address match detection (reception data match detection).
[Setting condition]
When a parity error is detected in the frame in which an address match is detected.
[Clearing conditions]
When 0 is written after 1 is read from DPER.
Clearing the RE bit in SCR to 0 (serial reception is disabled) does not affect the DPER flag, which keeps its previous
value.
DFER flag (Data Compare Match Framing Error Flag)
The DFER flag indicates that a framing error occurred on address match detection (reception data match detection).
[Setting conditions]
When a stop bit is 0 in the frame in which an address match is detected. When in 2-stop-bit mode, only the 1st stop
bit is checked for a value of 1, and the 2nd bit is not checked.
[Clearing conditions]
When 0 is written after 1 is read from DFER.
When the RE bit in SCR is set to 0 (serial reception is disabled), the DFER flag is not affected and keeps its previous
value.
IDSEL bit (ID Frame Select)
The IDSEL bit selects whether to compare data regardless of the value of the MPB bit or to compare data only when
MPB = 1 (ID frame), when the address match function is enabled.
DCME bit (Data Compare Match Enable)
The DCME bit selects whether the address match function (data compare match function) is used or not.
If SCI detects a match between the comparison data (CDR.CMPD) and receive data, DCME is cleared automatically and
the SCI operates in receive mode without the data compare match function. See section 29.3.6, Address Match (Receive
Data Match Detection) Function.
The write value should be 0 for any mode other than asynchronous mode.
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29.2.31
29. Serial Communications Interface (SCI)
Serial Port Register (SPTR)
Address(es): SCI0.SPTR 4007 001Ch, SCI1.SPTR 4007 003Ch, SCI2.SPTR 4007 005Ch,
SCI3.SPTR 4007 007Ch, SCI4.SPTR 4007 009Ch, SCI9.SPTR 4007 013Ch
b7
Value after reset:
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SPB2I SPB2D RXDM
O
T
ON
0
1
1
Bit
Symbol
Bit name
Description
R/W
b0
RXDMON
Serial Input Data Monitor
Indicates the state of the RXDn pin:
0: RXDn pin is low
1: RXDn pin is high.
R
b1
SPB2DT
Serial Port Break Data
Select
Indicates the output level of the TXDn pin when SCR.TE = 0:
0: Output low on TXDn pin
1: Output high on TXDn pin.
R/W
b2
SPB2IO
Serial Port Break I/O
Selects whether the value of SPB2DT is output to the TXDn pin:
0: Do not output value of SPB2DT bit on TXDn pin
1: Output value of SPB2DT bit on TXDn pin.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SPTR register provides confirmation of the serial reception pin (RXDn pin) status and sets the transmission pin
(TXDn pin) status. This register can only be used in asynchronous mode.
The TXDn pin status is determined by the combination of SCR.TE, SPTR.SPB2IO, and SPTR.SPB2DT bit settings, as
shown in Table 29.21.
Table 29.21
TXDn pin status
Value of SCR.TE
Value of SPTR.SPB2IO
Value of SPTR.SPB2DT
TXDn pin status
0
0
x
Hi-Z (initial value)
0
1
0
Low-level output
0
1
1
High-level output
1
x
x
Serial transmit data is output
x: Don’t care.
Note:
29.3
Use the SPTR register in asynchronous mode only. The operation of this register in any other mode is not guaranteed.
Operation in Asynchronous Mode
Figure 29.2 shows the general format for asynchronous serial communications. One frame consists of a start bit (low
level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the
communications line is held in the mark state (high level) when not communicating.
The SCI monitors the communications line. When the SCI detects a low, it regards that as a start bit and starts serial
communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communications. Both the
transmitter and the receiver have a double-buffered structure in addition to FIFO mode, so that the data can be read or
written during transmission or reception, enabling continuous data transmission and reception.
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29. Serial Communications Interface (SCI)
Idle state
(mark state)
1
LSB
0
Serial data
1
MSB
D0
D1
D2
D3
D4
D5
D6
D7
Transmit/receive data
Start bit
7, 8, or 9 bits
1 bit
0/1
1
1
Parity bit
Stop bit
1 or 0 bit
1 or 2 bits
One unit of transfer data (character or frame)
Figure 29.2
29.3.1
Data format in asynchronous serial communications with 8-bit data, parity bit, and 2 stop bits
Serial Data Transfer Format
Table 29.22 lists the serial data transfer formats that can be used in asynchronous mode. Any of the 18 transfer formats
can be selected in the SMR and SCMR settings. For details on the multi-processor function, see section 29.4, MultiProcessor Communications Function.
Table 29.22
Serial transfer formats in asynchronous mode (1 of 2)
SCMR
setting
SMR setting
CHR1
CHR
PE
MP
STOP
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
Serial transfer format and frame length
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
S
9-bit data
STOP
S
9-bit data
STOP
STOP
S
9-bit data
P
STOP
S
9-bit data
P
STOP
S
8-bit data
STOP
S
8-bit data
STOP
STOP
S
8-bit data
P
STOP
S
8-bit data
P
STOP
13
1
0
1
STOP
0
1
0
1
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Table 29.22
29. Serial Communications Interface (SCI)
Serial transfer formats in asynchronous mode (2 of 2)
SCMR
setting
SMR setting
CHR1
CHR
PE
MP
STOP
1
1
0
0
0
1
1
1
0
0
1
1
1
1
S:
STOP:
P:
MPB:
1
1
1
0
0
0
0
1
1
0
1
1
-
-
-
-
-
-
Serial transfer format and frame length
0
0
0
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
10
11
12
S
7-bit data
STO
P
S
7-bit data
STO
P
STOP
S
7-bit data
P
STOP
S
7-bit data
P
STOP
S
9-bit data
MPB
STOP
S
9-bit data
MPB
STOP
S
8-bit data
MPB
STOP
S
8-bit data
MPB
STOP
S
7-bit data
MPB
STOP
S
7-bit data
MPB
STOP
13
1
0
1
STOP
0
1
STOP
0
1
STOP
0
1
STOP
Start bit
Stop bit
Parity bit
Multi-processor bit
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29.3.2
29. Serial Communications Interface (SCI)
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times*1 the bit rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Because receive data is sampled on the rising edge of the 8th pulse*1 of the base clock, data is latched at the middle of
each bit, as shown in Figure 29.3. The reception margin in asynchronous mode is determined by the following formula
(1):
M=
(0.5 -
D - 0.5
N
1
) - (L - 0.5) F 2N
(1 + F)
× 100 [%] ... Formula (1)
M: Reception margin
N: Ratio of bit rate to clock
(N = 16 when ABCSE in SEMR = 0 and ABCS in SEMR = 0,
N = 8 when ABCS in SEMR = 1,
N = 6 when ABCSE in SEMR = 1)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 13)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the following formula:
M = {0.5 - 1/(2 × 16)} × 100 (%) = 46.875%
However, this is only the computed value. Renesas recommends that a margin of 20% to 30% should be allowed in
system design.
Note 1. In this example, the ABCS bit in SEMR is 0 and ABCSE bit in SEMR is 0. When the ABCS bit is 1 and the ABCSE
bit is 0, a frequency of 8 times the bit rate is used as a base clock, and receive data is sampled on the rising edge
of the 4th pulse of the base clock.
When the ABCSE bit is 1, a frequency of 6 times the bit rate is used as a base clock, and the receive data is
sampled on the rising edge of the 3rd pulse of the base clock.
16 clock pulses
8 clock pulses
0
7
15
0
7
15 0
Internal base clock
Receive data (RXDn)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 29.3
Receive data sampling timing in asynchronous mode
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29.3.3
29. Serial Communications Interface (SCI)
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be
selected as the SCI transfer clock, based on the CM setting in SMR and the CKE[1:0] setting in SCR.
When an external clock is input to the SCKn pin, the clock frequency must be 16 times the bit rate (when ABCS in
SEMR = 0) or 8 times the bit rate (when ABCS in SEMR = 1).
When the SCI uses its internal clock, the clock can be output from the SCKn pin. The frequency of the clock output in
this case is equal to the bit rate, and the phase is configured so that the rising edge of the clock is in the middle of the
transmit data, as shown in Figure 29.4.
SCKn
TXDn
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 29.4
29.3.4
Phase relationship between output clock and transmit data in asynchronous mode when
SMR.CHR = 0, PE = 1, MP = 0, and STOP = 1
Double-Speed Operation and Frequency of 6 Times the Bit Rate
When the ABCS bit in SEMR is set to 1 and 8 pulses of the base clock for a 1-bit period is selected, the SCI operates on
the bit rate that is equal to twice when ABCS is set to 0. When the BGDM bit in SEMR is set to 1, the cycle of the base
clock is half and the bit rate is double the value when BGDM is set to 0. When the CKE[1] bit in SCR is set to 0 and the
on-chip baud rate generator is selected, setting the ABCS and BGDM bits to 1 allows the SCI to operate at a bit rate
equal to four times the value where the ABCS and BGDM bits are set to 0. When the ABCSE bit in SEMR is set to 1, the
number of basic clock pulses is 6 during a period of 1 bit, and the SCI operates at a bit rate that is equal to 16/3 times the
value when SEMR.ABCS = 0, SEMR.BGDM = 0, and SMER.ABCSE = 0.
As shown by formula (1) in section 29.3.2, Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode, the reception margin decreases when the ABCS or ABCSE in SEMR is set to 1. Therefore, if the target bit rate can
be obtained with ABCS or ABCSE set to 0, it is recommended that you use the SCI with ABCS and ABCSE set to 0.
29.3.5
CTS and RTS Functions
The CTS function uses the input on the CTSn_RTSn pin in transmission control. Setting the CTSE bit in SPMR to 1
enables the CTS function. When the CTS function is enabled, driving the CTSn_RTSn pin low causes transmission to
start.
Driving the CTSn_RTSn pin high while transmission is in progress does not affect transmission of the current frame.
In the RTS function that uses the output on the CTSn_RTSn pin, a low level is output when reception becomes possible.
Conditions for low-level and high-level output are shown in this section.
[Conditions for low-level output]
(a)
Non-FIFO selected, when all of the following conditions are satisfied
The value of the RE bit in SCR is 1
Reception is not in progress
There is no received data yet to be read
The ORER, FER, and PER flags in SSR are all 0.
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(b)
29. Serial Communications Interface (SCI)
FIFO selected, when all of the following conditions are satisfied
The value of the RE bit in SCR is 1
When the amount of receive data written in FRDRHL is equal to or less than the specified receive triggering number
The ORER flag in SSR_FIFO (ORER in the FRDRH) is 0.
[Condition for high-level output]
(a)
Non-FIFO selected
The conditions for low-level output are not satisfied.
When reception is terminated with SCR.RE = 0 without reading the RDR register after reception is complete, RTS
remains high. At this time, read the SCR register for dummy values after writing SCR.RE = 0.
(b)
FIFO selected
The conditions for low-level output are not satisfied.
29.3.6
Address Match (Receive Data Match Detection) Function
The address match function can be used only in asynchronous mode.
If the DCCR.DCME bit is set to 1*4, when one frame of data is received, the SCI compares that received data with the
data set in CDR.CMPD. If the SCI detects a match between the comparison data (CDR.CMPD*3) and the received data,
the SCI can issue the SCIn_RXI interrupt request.
If the SMR.MP bit is set to 0, comparison occurs only for valid data in receive format. In multi-processor mode
(SMR.MP = 1), if the DCCR.IDSEL bit is set to 1, receive data where the MPB bit is 1 is subject to comparison for
address match. Receive data where the MPB bit is 0 is always treated as a mismatch.
If DCCR.IDSEL is set to 0, the SCI performs address match detection regardless of the MPB bit value of the received
data. Until the SCI detects a match between the comparison data (CDR.CMPD*3) and receive data, the received data is
skipped (discarded), and the SCI cannot detect parity error or framing error. When the SCI detects a match,
DCCR.DCME is automatically cleared, and DCCR.DCMF is set to 1.
If DCCR.IDSEL is set to 1, the SCR.MPIE bit is automatically cleared. If DCCR.IDSEL is set to 0, the value of
SCR.MPIE bit is retained. If SCR.RIE is set to 1, the SCI issues an SCIn_RXI interrupt request. If the SCI detects a
framing error in the receive data for which a match is detected, DCCR.DFER is set to 1, and if the SCI detects a parity
error in that frame, DCCR.DPER is set to 1. The compared receive data is not stored in RDR*1, and SSR.RDRF remains
at 0.*2
After the SCI detects a match, and DCCR.DCME is automatically cleared, the SCI receives the next data continuously
based on the current register setting.
When the DCCR.DFER or DCCR.DPER flag is set, the address match is not performed. Before enabling the address
match function, set the DCCR.DFER and DCCR.DPER flags to 0.
Examples of the address match function are shown in Figure 29.5 and Figure 29.6.
Note 1. When FCR.FM = 1, this refers to the FRDRHL register.
Note 2. When FCR.FM = 1, this refers to the SSR_FIFO.RDF flag.
Note 3. This comparative target can select one length of 3 types: CMPD[6:0] with 7-bit length, CMPD[7:0] with 8-bit
length, or CMPD[8:0] with 9-bit length.
Note 4. Set the DCCR.DCME bit to 1 before receiving the start bit of the received frame that performs address matching.
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29. Serial Communications Interface (SCI)
Data (ID1)
1
Data (Data1)
Start bit
0
Stop bit Start bit
D0
D1
D7
Parity
1
0
D0
D1
D7
Parity
SCIn_AM
SCI0_DCUF
DCME
DCMF flag
SCIn_RXI interrupt flag
(ICU.IELSRn.IR)
RDRF flag
DPER flag
DFER flag
RDR
If compare mismatches,
the flag is NOT set
Not stored to RDR if CDR
setting value mismatches
with receive data
(a) Example of compare mismatch between receive data and CDR (8-bit length/parity/non-multi-processor mode)
Data (ID2)
1
Data (Data2)
Start bit
0
Stop bit Start bit
D0
D1
D7
Parity
1
0
Stop bit Start bit
D0
D1
D7
Parity
1
0
SCIn_AM
SCI0_DCUF
DCME
DCMF flag
MPIE
Clear the flag
SCIn_RXI interrupt flag
(ICU.IELSRn.IR)
RDRF flag
DFER flag
RDR
Data2
DCME = 0
If error occurs,
flag is set
Not stored to RDR if CDR
setting value matches with
receive data
Non-address
match receive,
and
set to the flag
Stored
receive data
(b) Example of compare match between receive data and CDR (8-bit length/parity/non-multi-processor mode)
Figure 29.5
Example of address match (1) in non-multi-processor mode
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29. Serial Communications Interface (SCI)
Data (ID1)
Data (Data0)
1
Start bit
0
MPB
D0
D1
D7
0
Stop bit Start bit
1
0
MPB Stop bit Start bit
D0
D1
D7
1
1
SCIn_AM
SCI0_DCUF
DCME
DCMF flag
SCIn_RXI interrupt flag
(ICU.IELSRn.IR)
RDRF flag
DPER flag
DFER flag
RDR
If compare is mismatches, Not stored to RDR, if CDR
flag is NOT set.
setting value mismatches
with receive data
(a) Example of compare mismatch between receive data and CDR (8-bit length/IDSEL = 1/multi-processor mode)
Data (Data2)
Data (ID2)
1
Start bit
0
MPB Stop bit Start bit
D0
D1
D7
1
1
0
Stop bit Start bit
D0
D1
D7
MPB
1
0
SCIn_AM
SCI0_DCUF
DCME
DCMF flag
MPIE
Clear the flag
SCIn_RXI interrupt flag
(ICU.IELSRn.IR)
RDRF flag
DFER flag
RDR
Data2
DCME = 0
If error occurs,
flag is set
Not stored to RDR, if CDR
setting value matches with
receive data
Non-address
match and
non-multiprocessor, and
set to the flag
Stored
receive data
(b) Example of compare match between receive data and CDR (8-bit length/IDSEL = 1/multi-processor mode)
Figure 29.6
Example of address match (2) in multi-processor mode
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29.3.7
29. Serial Communications Interface (SCI)
SCI Initialization in Asynchronous Mode
Before transmitting and receiving data, start by writing the initial value 00h to SCR, and then continue through the SCI
procedure (select non-FIFO or FIFO) shown in Figure 29.7 and Figure 29.8. Whenever the operating mode or transfer
format is to be changed, the SCR must be initialized before the change is made.
When the external clock is used in asynchronous mode, ensure that the clock signal is supplied during initialization.
Note:
Note:
When the SCR.RE bit is set to 0, the ORER, FER, RDRF, RDF, PER, and DR flags in SSR/SSR_FIFO, and RDR
and RDRHL are not initialized. When the SCR.TE bit is set to 0, the TEND flag for the selected FIFO buffer is not
initialized.
Switching the value of the SCR.TE bit from 1 to 0 or 0 to 1 while the SCR.TIE bit is 1 leads to the generation of an
SCIn_TXI interrupt request.
Start initialization
Set SCR.TIE, RIE, TE, RE, and TEIE to 0
Set FCR.FM to 0
[1]
Set clock configuration in SCR.CKE[1:0]
[2]
Set SIMR1.IICM to 0.
Set SPMR.CKPH and SPMR.CKPOL to 0.
[3]
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[1]
Set FCR.FM to 0.
[2]
Set the clock selection in SCR.
When clock output is selected in asynchronous mode, the
clock is output immediately after SCR settings are made.
[3]
Set SIMR1.IICM to 0.
Set SPMR.CKPH and SPMR.CKPOL to 0.
Step [3] can be skipped if the values are not changed from
the initial values.
[4]
Set data transmission/reception format in SMR, SCMR, and
SEMR.
[5]
Write a value corresponding to the bit rate to BRR.
This step is not required if an external clock is used.
[6]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not required if the BRME bit in SEMR is
set to 0 or an external clock is used.
[7]
Make I/O port settings to enable input and output functions
as required for the TXDn, RXDn, and SCKn pins.
[8]
Set SCR.TE or SCR.RE to 1. Also set SCR.TIE and
SCR.RIE.
Setting SCR.TE and SCR.RE allows TXDn and RXDn to be
used.
[4]
Set a value in BRR
[5]
Set a value in MDDR
[6]
Set the I/O port functions
[7]
Set SCR.TE or SCR.RE to 1, and
set SCR.TIE and SCR.RIE
[8]
Initialization complete
Figure 29.7
Example SCI initialization flow in asynchronous mode with non-FIFO selected
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29. Serial Communications Interface (SCI)
Start initialization
[1]
Set FCR.FM, TFRST, and RFRST to 1.
This enables FIFO mode and clears the FIFOs.
Set trigger values in FCR.TTRG[3:0], RTRG[3:0], and
RSTRG[3:0].
[2]
Set the clock selection in SCR.
When the clock output is selected in asynchronous mode,
the clock is output immediately after SCR settings are made.
[3]
Set SIMR1.IICM to 0.
Set SPMR.CKPH and SPMR.CKPOL to 0.
Step [3] can be skipped if the values are not changed from
the initial values.
[4]
Set data transmission/reception format in SMR, SCMR, and
SEMR.
[5]
Write a value associated with the bit rate to BRR.
This step is not required if an external clock is used.
[6]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not required if the BRME bit in SEMR is
set to 0 or an external clock is used.
[7]
Set FCR.TFRST and FCR.RFRST to 0.
[8]
Make I/O port settings to enable input and output functions
as required for the TXDn, RXDn, and SCKn pins.
[9]
Set SCR.TE or SCR.RE to 1. Also set SCR.TIE and RIE.
Setting SCR.TE and SCR.RE allows TXDn and RXDn to be
used.
Set SCR.TIE, RIE, TE, RE, and TEIE to 0
Set FCR.FM, TFRST, and RFRST to 1.
Set FCR.TTRG[3:0], RTRG[3:0], and
RSTRG[3:0].
[1]
Set SCR.CKE[1:0]
[2]
Set SIMR1.IICM to 0.
Set SPMR.CKPH and CKPOL to 0.
[3]
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[4]
Set a value in BRR
[5]
Set a value in MDDR
[6]
Set FCR.TFRST and RFRST to 0
[7]
Set the I/O port functions
[8]
Set SCR.TE or RE to 1.
Set SCR.TIE and RIE.
[9]
Initialization completion
Figure 29.8
Example SCI initialization flow in synchronous mode with FIFO selected
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29.3.8
(1)
29. Serial Communications Interface (SCI)
Serial Data Transmission in Asynchronous Mode
Non-FIFO selected
Figure 29.9, Figure 29.10, and Figure 29.11 show examples of serial transmission in asynchronous mode.
In serial transmission, the SCI operates as described in this section. When the SCR.TE bit is set to 1, the high level for
one frame (preamble) is output to TXD.
1. The SCI transfers data from TDR*1 to TSR when data is written to TDR*1 in the SCIn_TXI interrupt handling
routine.
The SCIn_TXI interrupt request at the beginning of transmission is generated when the TE and TIE bits in SCR are
set to 1 simultaneously by a single instruction.
2. Transmission starts after the CTSE bit in SPMR is set to 0 (CTS function is disabled) or a low level on the
CTSn_RTSn pin causes data transfer from TDR*1 to TSR. If the TIE bit in SCR is 1, an SCIn_TXI interrupt request
is generated. Continuous transmission is possible by writing the next transmit data to TDR*1 in the SCIn_TXI
interrupt handling routine before transmission of the current transmit data is complete. When SCIn_TEI interrupt
requests are in use, set TIE to 0 (an SCIn_TXI interrupt request is disabled) and TEIE to 1 (an SCIn_TEI interrupt
request is enabled) in the SCR register after the last of the data to be transmitted is written to the TDR*1 from the
handling routine for SCIn_TXI requests.
3. Data is sent from the TXDn pin in the following order:
Start bit
Transmit data
Parity bit or multi-processor bit (can be omitted depending on the format)
Stop bit.
4. The SCI checks for an update of TDR on the output of the stop bit.
5. When TDR is updated, setting the CTSE bit in SPMR to 0 (CTS function is disabled) or a low-level input on the
CTSn_RTSn pin causes the transfer of the next transmit data from TDR*1 to TSR and transmission of the stop bit,
after which serial transmission of the next frame starts.
6. If TDR is not updated, the TEND flag in SSR is set to 1, the stop bit is sent, and the mark state is entered, where 1 is
output. If the TEIE bit in SCR is 1, the TEND flag in SSR is set to 1 and an SCIn_TEI interrupt request is generated.
Note 1. Only write data to TDRHL when 9-bit data length is selected.
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29. Serial Communications Interface (SCI)
Figure 29.9, Figure 29.10, and Figure 29.11 show examples of serial transmission in asynchronous mode.
Data
Start bit
1
0
Parity bit Stop bit
D7 0/1 1
D0 D1
SCR.TE bit
0
D0
D7 0/1
D1
1
0
1 frame
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Note 1.
Figure 29.9
Data written to TDR in
SCIn_TXI interrupt
handling routine
SCIn_TXI interrupt
request generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
Data written to TDR in
SCIn_TXI interrupt
handling routine
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example operation of serial transmission in asynchronous mode (1) with 8-bit data, parity bit, 1
stop bit, CTS function not used, and at the beginning of transmission
CTSn_RTSn pin
Start bit
1
SCR.TE bit
Data
0 D0 D1
Parity bit
D7 0/1 1
Stop bit
0 D0 D1
D7 0/1 1
Idle state
(mark state)
0
1 frame
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Note 1.
Figure 29.10
Data written to TDR
Data written to TDR in
in SCIn_TXI interrupt
SCIn_TXI interrupt
handling routine
handling routine
SCIn_TXI interrupt
request generated
Data written to TDR in
SCIn_TXI interrupt handling
routine
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example operation for serial transmission in asynchronous mode (2) with 8-bit data, parity bit, 1
stop bit, CTS function used, and at the beginning of transmission
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29. Serial Communications Interface (SCI)
Start bit
1
SCR.TE bit
Data
0 D0 D1
Parity bit
Stop bit
D7 0/1 1
1
0 D0 D1
D7 0/1 1
Data written to TDR in
SCIn_TXI interrupt
handling routine
1 frame
Figure 29.11
Idle state
(mark state)
(TIE = 0)
SSR.TEND flag
Note 1.
D7 0/1 1
(TIE = 1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SCIn_TXI interrupt
request generated
0 D0 D1
Data written to TDR in SCIn_TXI
interrupt handling routine
(Set the TIE bit to 0 and the TEIE bit to
1 after writing the last data)
SCIn_TEI interrupt
request generated
SCIn_TXI interrupt
request generated
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example operation of serial transmission in asynchronous mode (3) with 8-bit data, parity bit, 1
stop bit, CTS function not used, and from the middle of transmission until transmission
completion
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29. Serial Communications Interface (SCI)
[1]
Initialization
[1]
SCI Initialization:
Set data transmission.
After SCR.TE is set to 1, 1 is output for a frame
(preamble), and transmission is enabled.
[2]
Transmit data write to TDR by an SCIn_TXI interrupt
request:
When transmit data is transferred from TDR to TSR,
a transmit data empty interrupt (SCIn_TXI) request is
generated.
Write transmit data to TDR while in the SCIn_TXI
interrupt processing routine.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write transmit data
to TDR once using an SCIn_TXI interrupt request.
Transmit data can also be written to TDR by
activating the DMAC or DTC.
When SCIn_TEI interrupt requests are in use, set
SCR.TIE to 0 and SCR.TEIE to 1 after the last of the
data to be transmitted is written to TDR.
[4]
Break output at the end of serial transmission:
To output a break in serial transmission, after setting
the output state (low-level output) of the TXDn pin
using SPTR.SPB2IO and SPTR.SPB2DT bits, set
SCR.TE to 0.
Start transmission
SCIn_TXI interrupt?
No
[2]
Yes
Write transmit data to TDR
All data transmitted?
No
[3]
Yes
Set SCR.TIE to 0 and set SCR.TEIE to 1
SCIn_TEI interrupt?
No
Yes
Break output?
Note:
No
TDR becomes TDRHL when 9-bit data length is
selected.
[4]
Yes
Set TXD port function
Set SCR.TIE, TE, and TEIE to 0
End
Figure 29.12
Example flow of serial transmission in asynchronous mode with non-FIFO selected
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(2)
29. Serial Communications Interface (SCI)
FIFO selected
Figure 29.13 shows an example of a data format that is written to FTDRH and FTDRL in asynchronous mode.
Data corresponding to the data length is set to FTDRH and FTDRL. Write 0 for unused bits. Write in the order from
FTDRH to FTDRL.
Data
Length
Transmit data in FTDRH, FTDRL
Register
Setting
FTDRHL
FTDRH
SCMR.
CHR1
SMR.
CHR
b7
7 bits
1
0
8 bits
1
0
9 bits
FTDRL
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
Don’t
care
—
—
—
—
—
—
—
b7
b6
—
b5
b4
b3
b2
b1
b0
7-bit transmit data
8-bit transmit data
9-bit transmit data
—: Invalid. The write value should be 0.
Figure 29.13
Data format written to FTDRH and FTDRL with FIFO selected
In serial transmission, the SCI operates as described in this section. When the TE bit in SCR is set to 1, the high level is
output to TXD for one frame (preamble).
1. The SCI transfers data from FTDRL*1 to TSR when data is written to FTDRL*1 in the SCIn_TXI interrupt handling
routine. The amount of data that can be written to FTDRL is 16 minus FDR.T[4:0] bytes. The SCIn_TXI interrupt
request at the beginning of transmission is generated when the TE and TIE bits in SCR are set to 1 simultaneously
by a single instruction.
2. Transmission starts after the CTSE bit in SPMR is set to 0 (CTS function is disabled) and a low level on the
CTSn_RTSn pin causes data transfer from FTDRL*1 to TSR. When the amount of transmit data written in FTDRL
is equal to or less than the specified transmit triggering number, TDFE bit in SSR_FIFO is set to 1. If the TIE bit in
SCR is 1, an SCIn_TXI interrupt request is generated. Continuous transmission is possible by writing the next
transmit data to FTDRL*1 in the SCIn_TXI interrupt handling routine before transmission of the current transmit
data is complete. When SCIn_TEI interrupt requests are in use, set TIE to 0 (an SCIn_TXI interrupt request is
disabled) and TEIE to 1 (an SCIn_TEI interrupt request is enabled) in the SCR register after the last of the data to be
transmitted is written to the FTDRL*1, *2 from the handling routine for SCIn_TXI requests.
3. Data is sent from the TXDn pin in the following order:
Start bit
Transmit data
Parity bit or multi-processor bit (may be omitted depending on the format)
Stop bit.
4. On output of the stop bit, the SCI checks whether the non-transmitted data remains in FTDRL*3.
5. When data is set to FTDRL*3, setting of CTSE to 0 (CTS function is disabled) in the SPMR register or a low-level
input on the CTSn_RTSn pin causes transfer of the next transmit data from FTDRL*1 to TSR and transmission of
the stop bit, after which serial transmission of the next frame starts.
6. If data is not set in FTDRL*3, the TEND flag in SSR_FIFO is set to 1, the stop bit is sent, and the mark state is
entered where 1 is output. If the TEIE bit in SCR is 1, the TEND flag in SSR_FIFO is set to 1 and an SCIn_TEI
interrupt request is generated.
Note 1. Write data to the FTDRH and FTDRL registers when 9-bit data length is selected.
Note 2. Write data in the order from FTDRH to FTDRL when 9-bit data length is selected.
Note 3. The SCI only checks for an update to the FTDRL register and not the FTDRH register, when 9-bit data length is
selected.
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29. Serial Communications Interface (SCI)
Figure 29.14 shows an example flow of serial transmission in asynchronous mode with FIFO selected.
Initialization
[1]
[1]
SCI initialization:
Set data transmission.
After SCR.TE is set to 1, 1 is output for a frame
(preamble), and transmission is enabled.
[2]
Transmit data write to FTDRL*1 by an SCIn_TXI interrupt
request:
For data transmission from FTDRL to TSR, when the
amount of transmit data written in FTDRL is equal to or
less than the specified transmit triggering number, a
transmit data FIFO empty interrupt (SCIn_TXI) request is
generated. Write transmit data to FTDRL*1, *2 once in the
SCIn_TXI interrupt handling routine.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write all transmit data to
FTDRL using an SCIn_TXI interrupt request and clear
the SSR_FIFO.TDFE flag to 0.
The amount of transmission data that is possible to write
is 16 minus the amount of data stored in the transmit
FIFO.
Transmit data can also be written to FTDRL by activating
the DMAC or DTC. When data is written to FTDRL by the
DMAC or DTC, the TDFE flag is cleared automatically.
Therefore, do not write to the TDFE flag.
When SCIn_TEI interrupt requests are in use, set
SCR.TIE to 0 and SCR.TEIE to 1 after the last of the data
to be transmitted is written to the FTDRL.
[4]
Break output at the end of serial transmission:
To output a break in serial transmission, after setting the
output state (low-level output) of TXDn pin using
SPTR.SPB2IO and SPTR.SPB2DT bits, set SCR.TE to
0.
Start data transmission
SCIn_TXI interrupt?
No
[2]
Yes
Write transmit data to FTDRL*1, *2
All transmit data
written to FTDRL*1, *2 register?
[3]
No
Yes
Set SCR.TIE to 0 and set SCR.TEIE to 1
No
SCIn_TEI interrupt?
Yes
Break output?
Yes
Set TXD port functions
No
[4]
Note 1.
Set SCR.TE, TIE, and TEIE to 0
Note 2.
When data length is 9 bits, FTDRH and FTDRL
registers are used.
When data length is 9 bits, write in order from FTDRH
to FTDRL.
End
Figure 29.14
Example flow of serial transmission in asynchronous mode with FIFO selected
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29.3.9
(1)
29. Serial Communications Interface (SCI)
Serial Data Reception in Asynchronous Mode
Non-FIFO selected
Figure 29.15 and Figure 29.16 show an example of the operation for serial data reception in asynchronous mode.
In serial data reception, the SCI operates as follows:
1. When the value of the RE bit in SCR becomes 1, the output signal on the CTSn_RTSn pin goes low.
2. When the SCI monitors the communications line and detects a start bit, it performs internal synchronization, stores
receive data in RSR, and checks the parity bit and stop bit.
3. If an overrun error occurs, the ORER flag in SSR is set to 1. If the RIE bit in SCR is 1, an SCIn_ERI interrupt
request is generated. Receive data is not transferred to RDR*1.
4. If a parity error is detected, the PER flag in SSR is set to 1 and receive data is transferred to RDR*1. If the RIE bit in
SCR is 1, an SCIn_ERI interrupt request is generated.
5. If a framing error is detected, the FER flag in the SSR is set to 1 and receive data is transferred to RDR*1. If the RIE
bit in the SCR is 1, an SCIn_ERI interrupt request is generated.
6. When reception finishes successfully, receive data is transferred to RDR*1. If the RIE bit in the SCR is 1, an
SCIn_RXI interrupt request is generated. Continuous reception is enabled by reading the receive data transferred to
RDR in the SCIn_RXI interrupt handling routine before reception of the next receive data completes. Reading the
received data that was transferred to RDR causes the CTSn_RTSn pin to output low.
Note 1. Only read data in RDRHL when 9-bit data length is selected.
1
Data
Start bit
0
D0
D1
Parity Stop
bit
bit
D7
0/1
1
Data
Start bit
0
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.FER flag
SCIn_RXI interrupt
request generated
RDR data read in SCIn_RXI
interrupt handling routine
SCIn_ERI interrupt request
generated by framing error
1 frame
Note 1.
Figure 29.15
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI operation for serial reception in asynchronous mode (1) when the RTS function is
not used, and with 8-bit data, parity bit, and 1 stop bit
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29. Serial Communications Interface (SCI)
1
Data
Start bit
0
D0
Parity Stop
bit
bit
D7
0/1
Data
Start bit
1
0
D0
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
Start bit
0
Data
D0
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.FER flag
SCIn_RXI interrupt
request generated
RDR data read in SCIn_RXI
interrupt handling routine
SCIn_ERI interrupt request
generated by framing error
Error flag is cleared
CTSn_RTSn pin
1 frame
Note 1.
Figure 29.16
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI operation for serial reception in asynchronous mode (2) when RTS function is
used, and with 8-bit data, parity bit, and 1 stop bit
Table 29.23 lists the states of the flags in the SSR register and the receive data handling when a receive error is detected.
If a receive error is detected, an SCIn_ERI interrupt request is generated but an SCIn_RXI interrupt request is not
generated. Data reception cannot be resumed when the receive error flag is 1. Also, set the ORER, FER, and PER flags to
0 before resuming reception. In addition, be sure to read RDR or RDRHL during overrun error processing. When
reception is forcibly terminated by setting the RE bit in SCR to 0 during operation, read RDR or RDRHL because the
received data that is not read might be left in RDR or RDRHL.
Figure 29.17 and Figure 29.18 show example flows for serial data reception.
Table 29.23
Flags in SSR Status Register and receive data handling
Flags in the SSR Status Register
ORER
FER
PER
Received data
Receive error type
1
0
0
Lost
Overrun error
0
1
0
Transferred to RDR
Framing error
0
0
1
Transferred to RDR
Parity error
1
1
0
Lost
Overrun error + framing error
1
0
1
Lost
Overrun error + parity error
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
Lost
Overrun error + framing error + parity error
Note:
Only read data in the RDRHL register when 9-bit data length is selected.
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29. Serial Communications Interface (SCI)
[1]
Initialization
[1]
Start data reception
Read ORER, PER, and FER flags in SSR
[2]
Yes
SSR.ORER = 1,
SSR.PER = 1, or
SSR.FER = 1?
[3]
No
Error processing
[ 2 ] [ 3 ] Receive error processing and break detection:
If a receive error occurs, an SCIn_ERI interrupt is
generated. The error type is identified by reading
the ORER, PER, and FER flags in SSR. After
performing the appropriate error processing, be
sure to set the ORER, PER, and FER flags to 0.
Reception cannot be resumed if any of these flags
is set to 1. In the case of a framing error, a break
can be detected by reading the value of the input
port associated with the RXDn pin.
(Continued to next page) [ 4 ]
[5]
No
SCIn_RXI interrupt?
Yes*1
No
Read receive data in RDR*2
[4]
All data received?
[5]
SCI initialization:
Set data reception.
Read the receive data in RDR once in the
SCIn_RXI interrupt handling routine.
Serial reception continuation procedure:
To continue serial reception, before the stop bit of
the current frame is received, read data from RDR
in the SCIn_RXI interrupt processing routine. The
RDR data can also be read by activating the
DMAC or DTC.
Yes
Set SCR.RIE and RE to 0
Note 1.
Note 2.
End
Figure 29.17
Do not set RE to 0 before reading RDR.
RDR becomes RDRHL when 9-bit data length is
selected.
Example flow of serial reception in asynchronous mode with non-FIFO selected (1)
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29. Serial Communications Interface (SCI)
[3]
Error processing
No
SSR.ORER flag = 1?
Yes
Overrun error processing
No
[6]
[ 6 ] Processing in response to an overrun error:
Read the RDR. In combination with step [7], this
makes correct reception of the next frame possible.
SSR.FER flag = 1?
Yes
Break?
Yes
No
Framing error processing
No
Set SCR.RE to 0
SSR.PER flag = 1?
Yes
Parity error processing
Set SSR.ORER, PER, FER to 0
[7]
[ 7 ] Clearing the error flag:
Write 0 to the error flag.
Read SSR.ORER, PER, and FER
[8]
[ 8 ] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
Note:
End
Figure 29.18
RDR becomes RDRHL when 9-bit data length is
selected.
Example flow of serial reception in asynchronous mode with non-FIFO selected (2)
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29. Serial Communications Interface (SCI)
FIFO selected
Figure 29.19 shows an example of a data format that is written to FRDRH and FRDRL in asynchronous mode.
In asynchronous mode, 0 is written to the MPB flag bit in the FRDRH register. Data that corresponds to the data length is
written to FRDRH and FRDRL. Unused bits are written as 0. Read in the order from FRDRH to FRDRL. If software
reads FRDRL, SCI updates FER, PER, and receive data (RDAT[8:0]) in the FRDRL register with the next data. The
RDF, ORER, and DR flags in FRDRH always reflect the associated flags in the SSR_FIFO register.
Data
Length
Receive data in FRDRH, FRDRL
Register
Setting
FRDRHL
FRDRH
SCMR.
CHR1
SMR.
CHR
b7
b6
7 bits
1
0
—
RDF
8 bits
1
1
—
0
Don’t
care
—
9 bits
Note:
b5
FRDRL
b4
b3
b2
b1
b0
ORER
FER
PER
DR
0
0
RDF
ORER
FER
PER
DR
0
0
RDF
ORER
FER
PER
DR
0
b7
b6
0
b5
b4
b3
b2
b1
b0
7-bit receive data
8-bit receive data
9-bit receive data
0 is always read for MPB flag (FRDRH[1]).
When data length is 7 bits, 0 is always read for FRDRH[0] and FRDRL[7].
When data length is 8 bits, 0 is always read for FRDRH[0].
FRDRH[7] bit is read as an indefinite value.
Figure 29.19
Data format stored in FRDRH and FRDRL with FIFO selected
In serial data reception, the SCI operates as follows:
1. When the value of the RE bit in SCR becomes 1, the output signal on the CTSn_RTSn pin goes low.
2. When the SCI monitors the communications line and detects a start bit, it performs internal synchronization, stores
receive data in RSR, and checks the parity bit and stop bit.
3. When the FRDRL register is full, an overrun error occurs. If an overrun error occurs, the ORER flag in SSR_FIFO
is set to 1. When the RIE bit is 1, an SCIn_ERI interrupt request is generated. Receive data is not transferred to
FRDRL*1.
4. If a parity error is detected, the PER flag and receive data are transferred to FRDRL*1. When the RIE bit is set to 1,
an SCIn_ERI interrupt request is generated.
5. If a framing error is detected, the FER flag and receive data are transferred to FRDRL*1. When RIE is set to 1, an
SCIn_ERI interrupt request is generated.
6. After a framing error is detected and when SCI detects that the continuous receive data is for one frame, reception
stops.
7. When the amount of data stored in the Receive FIFO Data Register (FRDRL) falls below the specified receive
triggering number, and the next data is not received after 15 ETUs from the last stop bit in asynchronous mode, the
DR bit in SSR_FIFO is set to 1. When RIE is 1 and the DRES bit in FCR register is 0, SCI generates an SCIn_RXI
interrupt request. When the DRES bit is 1, SCI generates an SCIn_ERI interrupt request.
8. When reception finishes successfully, receive data is transferred to FRDRL*1. RDF is set to 1 when the amount of
receive data written to FRDRHL is equal to or greater than the specified receive triggering number. When the RIE is
1, an SCIn_RXI interrupt request is generated. Continuous reception is enabled by reading the receive data
transferred to FRDRL*2 in the SCIn_RXI interrupt handling routine, before an overrun error occurs. If the received
data that is transferred to FRDRL*3 is less than the RTS trigger number, the CTSn_RTSn pin outputs low.
Note 1. Only read the data in the FRDRH and FRDRL registers when 9-bit data length is selected.
Note 2. Read the data in the order from FRDRH to FRDRL when 9-bit data length is selected.
Note 3. The SCI only checks for updates to the FRDRL register and not to the FRDRH register when 9-bit data length is
selected.
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29. Serial Communications Interface (SCI)
[1]
Initialization
[1]
Start data reception
Read ORER*1, PER, FER, and DR*1
flags in SSR_FIFO
SSR_FIFO.ORER*1 = 1,
SSR_FIFO.PER = 1,
SSR_FIFO.FER = 1, or
SSR_FIFO.DR*1 = 1?
[2]
Yes
[3]
Error processing
No
No
[ 2 ] [ 3 ] Receive error processing and break detection:
If a receive error occurs, an SCIn_ERI interrupt
is generated. A break can be detected by
reading the SPTR.RXDMON bit. An error is
identified by reading the ORER*1, PER, DR*1,
and FER flags in SSR_FIFO. After performing
the appropriate error processing, be sure to set
the ORER*1 flag to 0. Reception cannot be
resumed if the ORER*1 flag is set to 1. The
reception operation is continuous, even if FER =
1 or PER = 1 or DR*1 = 1.
(Continued to next page)
[4]
Read the receive data in FRDRHL in the
SCIn_RXI interrupt handling routine. The receive
data stored in the FRDRHL register is read until
the amount of stored data is below the
FCR.RTRG value. Confirm the amount of the
receive data bits in the FIFO by reading the
FDR.R bits.
[5]
Serial reception continuation procedure:
To continue serial reception, before an overrun
error occurs, read data from FRDRHL in the
SCIn_RXI interrupt handling routine and clear
the RDF and DR flags to 0.
The FRDRHL data can also be read by
activating the DMAC or DTC. The RDF flag is
cleared automatically in this case. Therefore, do
not write to the RDF flag.
SCIn_RXI interrupt?
Yes
No
Read receive data in FRDRHL
[4]
All data received?
[5]
Yes
SCI initialization:
Set data reception.
Set SCR.RIE and RE to 0
Note 1.
End
Figure 29.20
Can be read by the FRDRHL.ORER and DR
flags.
Example flow of serial reception in asynchronous mode with FIFO selected (1)
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29. Serial Communications Interface (SCI)
[3]
Error processing
No
SSR_FIFO.ORER flag = 1?
Yes
Overrun error processing
No
[6]
[ 6 ] Processing in response to an overrun error:
FRDRHL is read and a space is made in FRDRHL.
SSR_FIFO.FER flag = 1?
Yes
Yes
Break?
No
Framing error processing
Break flow
[8]
No
[7]
[ 7 ] When a break is detected, transfer of the
receive data to FRDRHL stops after the
detection. When the break ends at
SEMR.RXDESEL = 0, the last stored data of
FRDRHL is break error frame (all 0 data).
SSR_FIFO.PER flag = 1?
Yes
Parity error processing
No
[8]
[ 8 ] Framing error processing/parity error processing:
All error occurrence data stored in FRDRHL is read.
(Or write 1 to FCR.RFRST to empty FRDRHL.)
[ 9 ] Reading of the receive data (when FCR.DRES is 1):
All receive data stored in FRDRHL is read.
SSR_FIFO.DR flag = 1?
Yes
Read receive data in FRDRHL
[9]
Set SSR_FIFO.ORER, PER, DR, and
FER to 0
[10]
[10] Clearing the error flag:
Write 0 to the error flag.
Read SSR_FIFO.ORER, PER, DR, and
FER
[11]
[11] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
End
Figure 29.21
Example flow of serial reception in asynchronous mode with FIFO selected (2)
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29.4
29. Serial Communications Interface (SCI)
Multi-Processor Communications Function
The multi-processor communication function enables the SCI to transmit and receive data by sharing a communication
line between multiple processors, using asynchronous serial communication in which the multi-processor bit is added. In
multi-processor communication, a unique ID code is allocated to each receiving station. Serial communication cycles
consist of an ID transmission cycle to specify the receiving station and a data transmission cycle to transmit data to the
specified receiving station.
The multi-processor bit is used to distinguish between the ID transmission cycle and the data transmission cycle:
When the multi-processor bit is set to 1, the transmission cycle is the ID transmission cycle
When the multi-processor bit is set to 0, the transmission cycle is the data transmission cycle.
Figure 29.22 shows an example of communication between processors using a multi-processor format. First, a
transmitting station transmits communication data in which the multi-processor bit set to 1 is added to the ID code of the
receiving station. Next, the transmitting station transmits communication data in which the multi-processor bit set to 0 is
added to the transmit data. After receiving communication data with the multi-processor bit set to 1, the receiving station
compares the received ID with the ID of the receiving station itself. If the two match, the receiving station receives
communication data that is subsequently transmitted. If the received ID does not match with the ID of the receiving
station, the receiving station skips the communication data until it receives the data again in which the multi-processor
bit is set to 1.
(1)
Non-FIFO selected
To support this function, the SCI provides the MPIE bit in SCR. When MPIE is set to 1, the following operations are
disabled until the reception of data in which the multi-processor bit is set to 1:
Transfer of receive data from RSR to RDR (RDRHL when 9-bit data length is selected)
Detection of a receive error
Setting the respective status flags RDRF, ORER, and FER in SSR.
When the SCI receives a character in which the multi-processor bit is set to 1, the MPBT bit in SSR is set to 1 and the
MPIE bit in SCR is automatically cleared, returning the SCI to a non-multi-processor reception operation. An SCIn_RXI
interrupt is generated if the RIE bit in SCR is set.
When the multi-processor format is specified, the parity bit function is disabled. Apart from this, there is no difference
from operation in non-multi-processor asynchronous mode. The clock used for the multi-processor communication is the
same as the clock used in non-multi-processor asynchronous mode.
Transmitting
station
Communication line
Receiving
station A
(ID = 01)
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 02)
(ID = 03)
(ID = 04)
(MPB = 1)
Serial data
01h
AAh
(MPB = 1)
ID transmission cycle =
specification of a receiving station
(MPB = 0)
Data transmission cycle = data
transmission to the receiving
station specified by ID
MPB: Multi-processor bit
Figure 29.22
Example of communication using multi-processor format with transmission of data AAh to
receiving station A
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29. Serial Communications Interface (SCI)
FIFO selected
For data transmission, software must write data to the MPBT bit in FTDRHL register that corresponds to transmit data in
the TDAT bit in FTDRHL register. For data reception, the multi-processor bit that is part of the receive data is written to
the MPB bit in FRDRHL register, and receive data is written to FRDRL register.
When the MPIE bit is set to 1, the following operations are disabled until reception of data in which the multi-processor
bit is set to 1:
Transfer of receive data from RSR to FRDRHL register
Detection of a receive error
Break
Setting of the respective status flags RDF, ORER, and FER in the SSR_FIFO register.
On receiving an 8-bit character in which the multi-processor bit is set to 1, the MPB bit in FRDRHL is set to 1 and
receive data is written to the RDAT bit in FRDRHL. The MPIE bit in SCR is automatically cleared, therefore returning
the SCI to non-multi-processor reception operation. An SCIn_RXI interrupt is generated if the RIE bit in SCR is set.
When the multi-processor format is specified, the parity bit function is disabled. Apart from this, there is no difference in
operation from non-multi-processor asynchronous mode with non-FIFO selected.
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29.4.1
(1)
29. Serial Communications Interface (SCI)
Multi-Processor Serial Data Transmission
Non-FIFO selected
Figure 29.23 shows an example flow of multi-processor data transmission. In the ID transmission cycle, the ID must be
transmitted with the MPBT bit in SSR set to 1. In the data transmission cycle, the data must be transmitted with the
MPBT bit set to 0. The rest of the operations are the same as in asynchronous mode.
Initialization
[1]
Start data transmission
SCIn_TXI interrupt?
No
[2]
[1]
SCI initialization:
Set data transmission.
After SCR.TE is set to 1, 1 is output for a frame, and
transmission is enabled.
[2]
SCIn_TXI interrupt request:
When transmit data is transferred from TDR to TSR, a
transmit data empty interrupt (SCIn_TXI) request is
generated.
Set SSR.MPBT to 0 or 1, and write transmit data to TDR in
the SCIn_TXI interrupt processing routine.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write transmit data to TDR
once using an SCIn_TXI interrupt request.
Transmit data can also be written to TDR by activating the
DMAC or DTC.
When SCIn_TEI interrupt requests are in use, set SCR.TIE
to 0 and SCR.TEIE to 1 after the last of the data to be
transmitted is written to TDR.
[4]
Break output at the end of serial transmission:
To output a break in serial transmission, after setting the
output state (low-level output) of TXDn pin using
SPTR.SPB2IO and SPTR.SPB2DT bits, set SCR.TE to 0.
Yes
Set SSR.MPBT
Write transmit data to TDR
All transmit data
written to the TDR register?
No
[3]
Yes
Set SCR.TIE to 0 and SCR.TEIE to 1
No
SCIn_TEI interrupt?
Yes
Break output?
No
[4]
Yes
Set TXD port functions
Set SCR.TE, TIE, and TEIE to 0
End
Figure 29.23
Example flow of multi-processor serial transmission with non-FIFO selected
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29. Serial Communications Interface (SCI)
FIFO selected
Figure 29.24 shows an example of the data format that is written to FTDRH and FTDRL in multi-processor mode.
MPBT is set to 1 in FTDRH register. Data is set to FTDRH and FTDRL with the correct data length. Write 0 for unused
bits. Write in the order from FTDRH to FTDRL.
Data
Length
Transmit data in FTDRH, FTDRL
Register
Setting
FTDRHL
FTDRH
FTDRL
SCMR.
CHR1
SMR.
CHR
b7
b6
b5
b4
b3
b2
b1
b0
b7
7 bits
1
0
—
—
—
—
—
—
MPBT
—
—
8 bits
1
1
—
—
—
—
—
—
MPBT
—
0
Don’t
care
—
—
—
—
—
—
MPBT
9 bits
b6
b5
b4
b3
b2
b1
b0
7-bit transmit data
8-bit transmit data
9-bit transmit data
—: Invalid. The write value should be 0.
Figure 29.24
Data format written to FTDRH and FTDRL in multi-processor mode with FIFO selected
Figure 29.25 shows an example flow of multi-processor data transmission with FIFO selected. In the ID transmission
cycle, the ID must be transmitted with the MPBT bit in FTDRH set to 1. In the data transmission cycle, the data must be
transmitted with the MPBT bit set to 0. Rest of the operations are the same as operations in asynchronous mode with
non-FIFO selected.
Initialization
[1]
Start data transmission
SCIn_TXI interrupt?
SCI initialization:
Set data transmission.
After SCR.TE is set to 1, 1 is output for a frame, and
transmission is enabled.
[2]
Transmit data write to FTDRHL by an SCIn_TXI interrupt
request:
For data transmission from FTDRHL to TSR, when the
amount of receive data written in FTDRHL is equal to or
less than the specified transmit triggering number, a
transmit data FIFO empty interrupt (SCIn_TXI) request is
generated.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write transmit data and
MPBT to FTDRHL once using an SCIn_TXI interrupt
request.
Transmit data can also be written to FTDRHL by activating
the DMAC or DTC.
When SCIn_TEI interrupt requests are in use, set SCR.TIE
to 0 and SCR.TEIE to 1 after the last of the data to be
transmitted is written to the FTDRHL.
[4]
Break output at the end of serial transmission:
To output a break in serial transmission, after setting the
output state (low-level output) of TXDn pin by
SPTR.SPB2IO and SPTR.SPB2DT bits, set SCR.TE to 0.
No
[2]
Yes
Write transmit data and MPBT
to FTDRHL
All transmit data
written to FTDRHL?
[1]
[3]
No
Yes
Set SCR.TIE to 0 and SCR.TEIE to 1
No
SCIn_TEI interrupt?
Yes
Break output?
Yes
Set TXD port functions
No
[4]
Set SCR.TE, TIE, and TEIE to 0
End
Figure 29.25
Example flow of serial transmission in multi-processor mode with FIFO selected
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29.4.2
(1)
29. Serial Communications Interface (SCI)
Multi-Processor Serial Data Reception
Non-FIFO selected
Figure 29.26 and Figure 29.27 show example flows of multi-processor data reception. When the MPIE bit in SCR is set
to 1, reading communication data is skipped until the reception of communication data in which the multi-processor bit is
set to 1. When communication data in which the multi-processor bit is set to 1 is received, the received data is transferred
to RDR, or RDRHL when 9-bit data length is selected, and the SCIn_RXI interrupt request is generated. The rest of the
operations are the same as in asynchronous mode.
Figure 29.26 shows an example operation for data reception.
Data (ID1)
1
Data (Data1)
Start bit
0
MPB Stop bit Start bit
D0
D1
D7
1
1
0
D0
D1
D7
MPB
Stop bit
1
0
1
Idle state
(mark state)
MPIE
SCIn_RXI interrupt flag
(IELSRn.IR*1)
RDR value
ID1
MPIE = 0
SCIn_RXI interrupt
request (multi-processor
interrupt) generated
RDR data read in
SCIn_RXI interrupt
handling routine
MPIE bit set to 1 again
when the received ID
does not match the ID of
the receiving station itself
SCIn_RXI interrupt
request not generated.
RDR retains the state.
(a) When the received ID does not match the ID of the receiving station itself
Data (ID2)
1
Data (Data2)
Start bit
0
MPB Stop bit Start bit
D0
D1
D7
1
1
0
MPB
D0
D1
D7
0
Stop bit
1
1
Idle state
(mark state)
MPIE
SCIn_RXI interrupt flag
(IELSRn.IR*1)
ID1
RDR value
MPIE = 0
ID2
SCIn_RXI interrupt
request (multi-processor
interrupt) generated
RDR data read in
SCIn_RXI interrupt
handling routine
Since the received ID matches
the ID of the receiving station
itself, reception continued and
data received in SCIn_RXI
interrupt handling routine
Data2
MPIE bit set to 1 again
(b) When the received ID matches the ID of the receiving station itself
Note 1.
Figure 29.26
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI reception with 8-bit data, multi-processor bit, and 1 stop bit
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29. Serial Communications Interface (SCI)
Initialization
[1]
[1]
SCI initialization:
Set data reception.
[2]
ID reception cycle:
Set SCR.MPIE to 1 and wait for ID reception.
[3]
SCI status confirmation and reception and
comparison of ID:
Read data in RDR*1 at the first SCIn_RXI
interrupt and compare it with the ID of the
receiving station itself. If the ID does not
match the ID of the receiving station itself, set
MPIE to 1 again, and wait for another
SCIn_RXI interrupt request.
[4]
Data reception at an SCIn_RXI interrupt:
Read data in RDR*1 in the SCIn_RXI
interrupt routine.
[5]
Receive error processing and break
detection:
If a receive error occurs, an error is identified
by reading the ORER and FER flags in SSR.
After performing the appropriate error
processing, be sure to set the ORER and
FER flags to 0. Reception cannot be resumed
if any of these flags is set to 1. In the case of
a framing error, a break can be detected by
reading SPTR.RXDMON.
Start data reception
Set SCR.MPIE to 1
[2]
Read ORER and FER flags in SSR
FER flag = 1 or ORER flag = 1?
Yes
No
No
SCIn_RXI interrupt?
[3]
Yes
Read receive data in RDR
No
ID of receiving station itself?
Yes
Read ORER and FER flags in SSR
FER flag = 1 or ORER flag = 1?
Yes
No
No
SCIn_RXI interrupt?
[4]
Yes
Read receive data in RDR
No
[5]
All data received?
Error processing
Yes
Set SCR.RE and RIE to 0
End
Figure 29.27
(Continued to next page)
Note 1.
RDR becomes RDRHL when 9-bit data length is selected.
Example flow of multi-processor serial reception (1) with non-FIFO selected
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29. Serial Communications Interface (SCI)
[5]
Error processing
No
SSR.ORER flag = 1?
Yes
Overrun error processing
No
[6]
[ 6 ] Processing in response to an overrun error:
Read the RDR*1. In combination with step [7],
this makes correct reception of the next frame
possible.
SSR.FER flag = 1?
Yes
Break?
Yes
No
Framing error processing
Set RE bit in SCR to 0
Set SSR.ORER, PER, and FER to 0
[7]
[ 7 ] Clearing the error flag:
Write 0 to the error flag.
Read SSR.ORER, PER, and FER
[8]
[ 8 ] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
End
Note 1.
Figure 29.28
RDR becomes RDRHL when 9-bit data length is selected.
Example flow of multi-processor serial reception (2) with non-FIFO selected
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29. Serial Communications Interface (SCI)
FIFO selected
Figure 29.29 shows an example of a data format that is written to FRDRH and FRDRL in multi-processor mode.
In multi-processor mode, the MPB value that is a part of the receive data is written to the MPB flag in FRDRH. A value
of 0 is written to the PER flag in FRDRH. Data is written to FRDRH and FRDRL with the correct data length. Unused
bits are written with 0. The read order is from FRDRH to FRDRL. When software reads FRDRL, the SCI updates FER,
MPB, and receive data (RDAT[8:0]) in FRDRL with the next data. The RDF, ORER, and DR flags in FRDRH always
reflect the associated flags in the SSR_FIFO register.
Data
Length
Receive data in FRDRH, FRDRL
Register
Setting
FRDRHL
FRDRH
SCMR.
CHR1
SMR.
CHR
b7
b6
7 bits
1
0
—
RDF
8 bits
1
1
—
0
Don’t
care
—
9 bits
Note:
b5
FRDRL
b4
b3
b2
b1
b0
ORER
FER
0
DR
MPB
0
RDF
ORER
FER
0
DR
MPB
0
RDF
ORER
FER
0
DR
MPB
b7
0
b6
b5
b4
b3
b2
b1
b0
7-bit receive data
8-bit receive data
9-bit receive data
When data length is 7 bits, 0 is always read for FRDRH[0] and FRDRL[7].
When data length is 8 bits, 0 is always read for FRDRH[0].
FRDRH[7] bit is read as an indefinite value.
Figure 29.29
Data format stored in FRDRH and FRDRL in multi-processor mode with FIFO selected
Figure 29.30 shows an example flow of multi-processor data reception with FIFO selected. When the MPIE bit in SCR is
set to 1, reading communication data is skipped until the reception of communication data in which the multi-processor
bit is set to 1. When communication data in which the multi-processor bit is set to 1 is received, the received data, MPB,
and the associated errors are transferred to FRDRHL. The MPIE bit in SCR register is automatically cleared and nonmulti-processor reception continues.
If a framing error occurs and the FER bit in SSR_FIFO is set to 1, the SCI continues data reception. The rest of the
operations are the same as in asynchronous mode with non-FIFO selected.
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29. Serial Communications Interface (SCI)
Initialization
[1]
Start data reception
No
Set MPIE bit in SCR to 1
[2]
SCIn_RXI interrupt?
[3]
[1]
SCI initialization:
Set data reception.
[2]
ID reception cycle:
Set SCR.MPIE to 1 and wait for ID reception.
[3]
SCI status confirmation and reception and
comparison of ID:
SCI stores first data (MPB = 1), after which all
received data are stored in FRDRHL.
RDF is set to 1 and an SCIn_RXI interrupt
request is generated when the amount of
receive data is equal to or greater than the
specified receive triggering number stored in
FRDRHL.
When the amount of data stored in the Receive
FIFO Data Register (FRDRHL) falls below the
specified receive triggering number and
received data is equal to or greater than 1, and
no new data is received after the elapse of 15
ETUs from the last stop bit, SSR_FIFO.DR is
set to 1. An SCIn_RXI interrupt request is
generated when FCR.DRES bit is 0.
Read data in FRDRHL at the first SCIn_RXI
interrupt, and compare it with the ID of the
receiving station itself.
If the ID does not match the ID of the receiving
station itself, read until the data with MPB is 1,
and compare next ID. If the data does not have
MPB = 1 in FRDRHL, set MPIE to 1 again, and
wait for another SCIn_RXI interrupt request.
[4]
Data reception at an SCIn_RXI interrupt:
Read data in FRDRHL in the SCIn_RXI
interrupt routine.
[5]
Receive error processing and break detection:
If a receive error occurs, an error is identified by
reading the ORER and FER flags in SSR_FIFO.
After performing the appropriate error
processing, be sure to set SSR_FIFO.ORER
and SSR_FIFO.FER to 0. Reception cannot be
resumed if SSR_FIFO.ORER is set to 1. If a
framing error occurs, a break can be detected
by reading SPTR.RXDMON.
Yes
Read receive data and flags in FRDRHL*1
FER flag = 1 or ORER flag = 1?
Yes
No
No
Yes
ID of receiving station itself?
Yes
Receive data is
still in FRDRHL?
No
No
SCIn_RXI interrupt?
[4]
Yes
Read receive data and flags in FRDRHL*1
FER flag = 1 or ORER flag = 1?
Yes
No
Note 1.
No
All data received?
If FRDRH and FRDRL are used instead of
FRDRHL, read in the order from FRDRH to
FRDRL.
[5]
Error processing
Yes
(Same as Figure 29.28)
Set SCR.RE and RIE to 0
End
Figure 29.30
Example flow of serial reception in multi-processor mode with FIFO selected
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29.5
29. Serial Communications Interface (SCI)
Operation in Clock Synchronous Mode
Figure 29.31 shows the data format for clock synchronous serial data communications.
In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in
transfer data consists of 8-bit data. In clock synchronous mode, no parity bit can be added.
In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data
reception, the SCI receives data in synchronization with the rising edge of the synchronization clock.
After 8-bit data is output, the transmission line holds the last bit as the output state. When the CKPH bit in SPMR register
is 1 in slave mode, the SCI holds the first bit as the output state.
Within the SCI, the transmitter and receiver are independent units, enabling full-duplex communications by using a
common clock. Both the transmitter and the receiver have a double-buffered structure, so that the next transmit data can
be written during transmission or the previous receive data can be read during reception, enabling continuous data
transfer.
However, it is not possible to perform continuous transfer in the fastest bit rate setting (BRR = 00h and SMR.CKS[1:0] =
00b). Therefore, when the FIFO is selected, this setting (BRR = 00h and SMR.CKS[1:0] = 00b) is not available.
One unit of transfer data (character or frame)
*
1
*1
Synchronization
clock
LSB
Serial data
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Note 1.
Figure 29.31
29.5.1
Don't care
Holds a high level except during continuous transfer.
Data format in clock synchronous serial communications with LSB-first order
Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the
SCKn pin can be selected based on the setting of the CKE[1:0] bits in the SCR register.
When the SCI operates on an internal clock, the synchronization clock is output from the SCKn pin. 8 synchronization
clock pulses are output in the transfer of one character. When no transfer is performed, the clock is held high. However,
when only data reception is performed while the CTS function is disabled, the synchronization clock output starts when
the RE bit in SCR is set to 1. The synchronization clock stops when it is held high*1 and when an overrun error occurs, or
when the RE bit is set to 0.
When only data reception occurs and the CTS function is enabled, the clock output does not start when the RE is set to 1
and the CTSn_RTSn input is high. The synchronization clock output starts when the RE bit is set to 1 and the
CTSn_RTSn input is low. When the CTSn_RTSn input is high on completion of the frame reception, the synchronization
clock output stops when it goes high. If the CTSn_RTSn input continues to be low, the synchronization clock stops when
it is held high*1 and an overrun error occurs, or when the RE bit is set to 0.
Note 1. The signal is held high when SPMR.CKPH bit is 0 and SPMR.CKPOL bit is 0, or when SPMR.CKPH bit is 1 and
SPMR.CKPOL bit is 1.
It is held low when SPMR.CKPH bit is 0 and SPMR.CKPOL bit is 1, or when SPMR.CKPH bit is 1 and
SPMR.CKPOL bit is 0.
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29.5.2
29. Serial Communications Interface (SCI)
CTS and RTS Functions
In the CTS function, the CTSn_RTSn input controls the start of data reception or transmission when the clock source is
the internal clock. Setting the CTSE bit in SPMR register to 1 enables the CTS function. When the CTS function is
enabled, setting the CTSn_RTSn pin low causes data reception or transmission to start.
Setting the CTSn_RTSn pin high while the data transmission or reception is in progress does not affect transmission or
reception of the current frame.
In the RTS function, the CTSn_RTSn output is used to request the start of data reception or transmission when the clock
source is an external synchronizing clock. The CTSn_RTSn output goes low when serial communication becomes
possible. Conditions for output of CTSn_RTSn low and high are as follows:
[Conditions for low output]
(a)
Non-FIFO selected, when all of the following conditions are satisfied
The value of the RE or TE bit in SCR is 1
When serial communication is enabled
There is no received data available to be read when SCR.RE is 1
Data is available for transmission in TSR when SCR.TE is 1
The SSR.ORER flag is 0.
(b)
FIFO selected, when all of the following conditions are satisfied
The value of the RE or TE bit in the SCR is 1
When serial communication is enabled
When the amount of receive data written in FRDRHL is less than the specified CTSn_RTSn output triggering
number when SCR.RE = 1
Data that has not been transmitted is available in FTDRHL when SCR.TE is 1 and SCR.CKE[1] is 0
Data is available for transmission in TSR when SCR.TE is 1 and SCR.CKE[1] is 1
The SSR_FIFO.ORER flag is 0.
[Condition for high output]
(a)
Non-FIFO selected
The conditions for low output are not satisfied.
When reception is terminated with SCR.RE = 0 without reading the RDR register after reception is completed, RTS
remains high. At this time, read the SCR register for dummy values after writing SCR.RE = 0.
(b)
FIFO selected
The conditions for low output are not satisfied.
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29.5.3
29. Serial Communications Interface (SCI)
SCI Initialization in Clock Synchronous Mode
Before transmitting and receiving data, start by writing the initial value 00h to SCR, then continue through the SCI
procedure in 29.5.2 CTS and RTS Functions. Any time the operating mode or transfer format is to be changed, SCR must
be initialized before the change can be made.
Note:
Note:
When the SCR.RE bit is set to 0, the ORER, FER, RDRF, RDF, PER, and DR flags in SSR/SSR_FIFO, and the
RDR and RDRHL registers are not initialized. When the TE bit in the SCR register is set to 0, the TEND flag for
the selected FIFO buffer is not initialized.
Switching the value of the TE bit from 1 to 0 or 0 to 1 when the TIE bit is 1 generates an SCIn_TXI interrupt
request.
Start initialization
Set SCR.TIE, RIE, TE, RE, and TEIE to 0
Set FCR.FM to 0
[1]
Set SCR.CKE[1:0]
[2]
Set SIMR1.IICM to 0.
Set SPMR.CKPH and CKPOL.
[1]
Set FCR.FM to 0.
[2]
Set the clock selection in SCR.
[3]
Set SIMR1.IICM to 0.
Set SPMR.CKPH and CKPOL.
Step [3] can be skipped if the values are not changed from
the initial values.
[4]
Set data transmission/reception format in SMR, SCMR, and
SEMR.
[5]
Write a value associated with the bit rate to BRR.
This step is not required if an external clock is used.
[6]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not required if SEMR.BRME is set to 0
or an external clock is used.
[7]
Make I/O port settings to enable input and output functions
as required for the TXDn, RXDn, and SCKn pins.
[8]
Set SCR.TE or RE to 1. Also set SCR.TIE and RIE.
Setting TE and RE allows TXDn and RXDn to be used.
[3]
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[4]
Set a value in BRR
[5]
Set a value in MDDR
[6]
Set the I/O port functions
[7]
Note:
Set SCR.TE or RE to 1
Set SCR.TIE and RIE
[8]
In simultaneous transmit and receive operations, SCR.TE
and SCR.RE should both be set to 0 or set to 1
simultaneously.
Initialization completion
Figure 29.32
Example flow of SCI initialization in clock synchronous mode with non-FIFO selected
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29. Serial Communications Interface (SCI)
Start initialization
[1]
Set FCR.FM, TFRST, and RFRST to 1.
This enables FIFO mode and clears the FIFOs.
Set the trigger values in FCR.TTRG[3:0], RTRG[3:0], and
RSTRG[3:0].
[2]
Set the clock selection in SCR.
[1]
[3]
Set SIMR1.IICM to 0.
Set the SPMR.CKPH and CKPOL bits.
Step [3] can be skipped if the values are not changed from
the initial values.
Set SCR.CKE[1:0]
[2]
[4]
Set data transmission/reception format in SMR, SCMR, and
SEMR.
Set SIMR1.IICM to 0
Set SPMR.CKPH and CKPOL
[3]
[5]
Write the value associated with the bit rate to BRR.
This step is not required if an external clock is used.
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[6]
[4]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not required if SEMR.BRME is set to 0
or an external clock is used.
Set a value in BRR
[5]
[7]
Set FCR.TFRST and RFRST to 0.
[8]
Make I/O port settings to enable input and output functions
as required for the TXDn, RXDn, and SCKn pins.
[9]
Set SCR.TE or RE to 1. Also set SCR.TIE and RIE.
Setting TE and RE allows TXDn and RXDn to be used.
Set SCR.TIE, RIE, TE, RE, and TEIE to 0
Set FCR.FM, TFRST, and RFRST to 1
Set FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0]
Set a value in MDDR
[6]
Set FCR.TFRST and RFRST to 0
[7]
Set the I/O port functions
[8]
Set SCR.TE or RE to 1
Set SCR.TIE and RIE
[9]
Note:
In simultaneous transmit and receive operations,
SCR.TE and RE should both be set to 0 or set to 1
simultaneously.
Initialization completion
Figure 29.33
Example flow of SCI initialization in clock synchronous mode with FIFO selected
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29.5.4
(1)
29. Serial Communications Interface (SCI)
Serial Data Transmission in Clock Synchronous Mode
Non-FIFO selected
Figure 29.34, Figure 29.35, and Figure 29.36 show examples of serial transmission in clock synchronous mode.
In serial data transmission, the SCI operates as follows:
1. The SCI transfers data from TDR to TSR when data is written to TDR in the SCIn_TXI interrupt handling routine.
The SCIn_TXI interrupt request at the beginning of transmission is generated when the TE bit in SCR is set to 1 but
only after SCR.TIE is also set to 1, or when SCR.TE and SCR.TIE are both set to 1 simultaneously by a single
instruction.
2. After transferring data from TDR to TSR, the SCI starts transmission. When the TIE bit in SCR is set to 1, an
SCIn_TXI interrupt request is generated. Continuous transmission is enabled by writing the next transmit data to
TDR in the SCIn_TXI interrupt handling routine before transmission of the current transmit data finishes. When
SCIn_TEI interrupt requests are in use, set the TIE bit in SCR to 0 and the TEIE bit in SCR to 1 after the last of the
data to be transmitted is written to TDR.
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is
specified, and in synchronization with the input clock when the use of an external clock is specified. Output of the
clock signal is suspended until the input signal CTSn_RTSn is low when the CTSE bit in SPMR register is 1.
4. The SCI checks for updates to TDR on output of the last bit.
5. When TDR is updated, the next transmit data is transferred from TDR to TSR, and serial transmission of the next
frame starts.
6. If TDR is not updated, the TEND flag in SSR register is set to 1. The TXDn pin retains the output state of the last
bit. If the TEIE bit in SCR register is 1, an SCIn_TEI interrupt request is generated and the SCKn pin is held high.
Figure 29.34, Figure 29.35, and Figure 29.36 show example flows of serial data transmission.
Transmission does not start while a receive error flag (ORER, FER, or PER in SSR) is set to 1. Be sure to set the receive
error flags to 0 before starting transmission.
Note:
Setting the RE bit in SCR register to 0 does not clear the receive error flags.
Synchronization clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
Bit 0
SCR.TE bit
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Data written to TDR in SCIn_TXI
interrupt handling routine
SCIn_TXI
interrupt
request
generated
SCIn_TXI
interrupt
request
generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
SCIn_TXI interrupt
request generated
Data written to TDR in SCIn_TXI
interrupt handling routine
1 frame
Note 1.
Figure 29.34
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of serial data transmission in clock synchronous mode when the CTS function is not
used at the beginning of transmission
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29. Serial Communications Interface (SCI)
CTSn_RTSn pin
Synchronization clock
Bit 0
Serial data
Bit 1
Bit 7
Bit 0
SCR.TE bit
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
SCIn_TXI interrupt
request generated
SCIn_TXI interrupt
Request generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
Data written to TDR in
SCIn_TXI interrupt handling
routine
Data written to TDR in
SCIn_TXI interrupt
handling routine
1 frame
Note 1.
Figure 29.35
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example of serial data transmission in clock synchronous mode when the CTS function is used
at the beginning of transmission
Synchronization
clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
(TIE = 1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
(TIE = 0)
SSR.TEND flag
SCIn_TXI
interrupt request
generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
SCIn_TXI
interrupt
request
generated
Data written to TDR in SCIn_TXI
interrupt handling routine
(Set the TIE bit to 0 and the TEIE
bit to 1 after writing the last data)
SCIn_TEI
interrupt request
generated
1 frame
Note 1.
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Figure 29.36
Example of serial data transmission in clock synchronous mode from the middle of transmission
until transmission completion
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29. Serial Communications Interface (SCI)
[1]
Initialization
[1]
SCI initialization:
Set data transmission.
[2]
Writing transmit data to TDR by an SCIn_TXI interrupt
request:
When transmit data is transferred from TDR to TSR, a
transmit data empty interrupt (SCIn_TXI) request is
generated.
Transmit data is written to TDR once from the handling
routine for SCIn_TXI requests.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write transmit data to
TDR on accepting a transmit data empty interrupt
(SCIn_TXI) request. Transmit data can also be written to
TDR by activating the DMAC or DTC by the SCIn_TXI
interrupt request.
When SCIn_TEI interrupt requests are in use, set
SCR.TIE to 0 and SCR.TEIE to 1 after the last of the data
to be transmitted is written to TDR.
Start transmission
SCIn_TXI interrupt?
No
[2]
Yes
Write transmit data to TDR
All data transmitted?
No
Yes
Set SCR.TIE to 0 and SCR.TEIE to 1
SCIn_TEI interrupt?
[3]
No
Yes
Set SCR.TIE, TE, and TEIE to 0
End
Note:
When the external clock is in use (the value of SCR.CKE[1:0] is 10b or 11b), the rising edge on the SCK pin for the last
bit sets the SSR.TEND flag to 1. Setting SCR.TE to 0 immediately after this may lead to insufficient hold time for
received data on the receiver side.
Figure 29.37
(2)
Example flow of serial transmission in clock synchronous mode with non-FIFO selected
FIFO selected
Figure 29.38 shows an example of serial transmission in clock synchronous mode with FIFO selected.
In serial data transmission, the SCI operates as follows:
1. The SCI transfers data from FTDRL*1 to TSR when data is written to FTDRL*1 in the SCIn_TXI interrupt handling
routine. The amount of data that can be written to FTDRL is 16 minus FDR.T[4:0] bytes. The SCIn_TXI interrupt
request at the beginning of transmission is generated when SCR.TE is set to 1, but only after SCR.TIE is also set to
1, or when SCR.TE and SCR.TIE are both set to 1 simultaneously by a single instruction.
2. After transferring data from FTDRL to TSR, the SCI starts transmission. When the amount of transmit data written
in FTDRL is equal to or less than the specified transmit triggering number, the TDFE flag in SSR_FIFO is set to 1.
When the TIE bit in SCR is set to 1, an SCIn_TXI interrupt request is generated. Continuous transmission is enabled
by writing the next transmit data to FTDRL in the SCIn_TXI interrupt handling routine before transmission of the
current transmit data is complete. When SCIn_TEI interrupt requests are in use, set the TIE bit in SCR to 0 and the
TEIE bit in SCR to 1 after the last of the data to be transmitted is written to FTDRL.
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is
specified, and in synchronization with the input clock when use of an external clock is specified. Output of the clock
signal is suspended until the CTSn_RTSn input signal is low, when the CTSE bit in SPMR is 1.
4. The SCI checks whether non-transmitted data remains in FTDRL on the output of the stop bit.
5. When FTDRL is updated, the next transmit data is transferred from FTDRL to TSR and serial transmission of the
next frame starts.
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29. Serial Communications Interface (SCI)
6. If FTDRL is not updated, the TEND flag in SSR_FIFO is set to 1. The TXDn pin keeps the output state of the last
bit. If the EIE bit in SCR is 1, an SCIn_TEI interrupt request is generated and the SCKn pin is held high.
Note 1. In clock synchronous mode, FTDRH is not used.
Initialization
[1]
[1]
SCI initialization:
Set data transmission.
After SCR.TE is set to 1, 1 is output for a frame, and transmission is
enabled.
[2]
Transmit data write to FTDRL by an SCIn_TXI interrupt request:
When transmit data is transferred from FTDRL to TSR, when the
amount of transmit data written in FTDRL is equal to or less than the
specified transmit triggering number, a transmit data FIFO empty
interrupt (SCIn_TXI) request is generated. Write transmit data to
FTDRL once in the SCIn_TXI interrupt handling routine.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write the next transmit data to
FTDRL in the SCIn_TXI interrupt handling routine and clear the
SSR_FIFO.TDFE flag to 0 before transmission of the current transmit
data is complete.
Transmit data can also be written to FTDRL by activating the DMAC
or DTC. The TDFE flag is cleared automatically in this case. Do not
write to the TDFE flag.
When SCIn_TEI interrupt requests are in use, set SCR.TIE to 0 and
SCR.TEIE to 1 after the last of the data to be transmitted is written to
FTDRL.
Start data transmission
SCIn_TXI interrupt?
No
[2]
Yes
Write transmit data to FTDRL
All transmit data
written to FTDRL register?
[3]
No
Yes
Set SCR.TIE to 0 and set SCR.TEIE to 1
No
SCIn_TEI interrupt?
Yes
Note:
Set SCR.TE, TIE, and TEIE to 0
When the external clock is in use (the value of SCR.CKE[1:0] is 10b or
11b), the rising edge on the SCK pin for the last bit sets the
SSR_FIFO.TEND flag to 1. Setting SCR.TE to 0 immediately after this
may lead to insufficient hold time for receive data on the receiver side.
End
Figure 29.38
29.5.5
(1)
Example flow of serial transmission in clock synchronous mode with FIFO selected
Serial Data Reception in Clock Synchronous Mode
Non-FIFO selected
Figure 29.39 and Figure 29.40 show examples of SCI operation for serial reception in clock synchronous mode.
In serial data reception, the SCI operates as follows:
1. When the value of SCR.RE becomes 1, the CTSn_RTSn pin goes low.
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
input or output, and stores the receive data in RSR.
3. If an overrun error occurs, the SSR.ORER flag is set to 1. If SCR.RIE is 1, an SCIn_ERI interrupt request is
generated. Receive data is not transferred to RDR.
4. When reception completes successfully, receive data is transferred to RDR. If SCR.RIE is 1, an SCIn_RXI interrupt
request is generated. Continuous reception is enabled by reading the receive data transferred to RDR in the
SCIn_RXI interrupt handling routine before reception of the next receive data completes. Reading the received data
from RDR causes the CTSn_RTSn pin to output low.
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29. Serial Communications Interface (SCI)
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.ORER flag
SCIn_RXI
interrupt request
generated
RDR data read in SCIn_RXI
interrupt handling routine
SCIn_RXI
interrupt request
generated
SCIn_ERI interrupt request
generated by overrun error
1 frame
Note 1.
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Figure 29.39
Example operation of serial reception in clock synchronous mode (1) when the RTS function is
not used
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.ORER flag
SCIn_RXI
interrupt request
generated
SCIn_RXI interrupt
request generated
RDR data read in
SCIn_RXI interrupt
handling routine
SCIn_ERI interrupt request
generated by overrun error
CTSn_RTSn pin
1 frame
Note 1.
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Figure 29.40
Example operation of serial reception in clock synchronous mode (2) when RTS function is used
Data transfer cannot resume while the receive error flag is 1. Therefore, clear the ORER, FER, and PER flags in SSR to
0 before resuming data reception. Additionally, be sure to read the RDR during overrun error processing. When a data
reception is forcibly terminated by setting the RE bit in SCR to 0 during operation, read RDR because the received data
that is not read yet might be left in the RDR.
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29. Serial Communications Interface (SCI)
Figure 29.41 shows an example flow of serial data reception.
Initialization
[1]
Start data reception
No
SCI initialization:
Make input port settings for pins to be used as
RXDn pins.
[2]
[ 3 ] Receive error processing:
If a receive error occurs, read SSR.ORER,
perform the relevant error processing, and set
SSR.ORER to 0. Data reception cannot be
resumed while SSR.ORER is 1.
[4]
Read the receive data in RDR in the receive data
full interrupt (SCIn_RXI) request handling routine.
[5]
Serial reception continuation procedure:
To continue serial reception, before the MSB (bit
[7]) of the current frame is received, finish reading
the receive data in RDR. The RDR data can also
be read by activating the DMAC or DTC by an
SCIn_RXI interrupt request.
[6]
Processing in response to an overrun error:
Read the RDR. In combination with step [ 7 ], this
makes correct reception of the next frame
possible.
[7]
Clearing the error flag:
Write 0 to the error flag.
[8]
Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
[2]
Read SSR.ORER
SSR.ORER = 1?
[1]
Yes
[3]
Error processing
(Continued below)
No
SCIn_RXI interrupt?
Yes
Read receive data in RDR
No
All data received?
[4]
[5]
Yes
Set SCR.RIE and RE to 0
End
[3]
Error processing
Overrun error processing
[6]
Clear SSR.ORER to 0
[7]
Read SSR.ORER
[8]
End
Figure 29.41
Example flow of serial reception in clock synchronous mode with non-FIFO selected
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29. Serial Communications Interface (SCI)
FIFO selected
Figure 29.42 shows an example of serial reception in clock synchronous mode with FIFO operation selected.
In serial data reception, the SCI operates as follows:
1. When the value of SCR.RE becomes 1, the CTSn_RTSn pin goes low.
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
input or output, and stores the receive data in RSR.
3. If an overrun error occurs, the ORER flag in SSR_FIFO is set to 1. If the RIE bit in SCR is 1, an SCIn_ERI interrupt
request is generated. Receive data is not transferred to FRDRL*1.
4. When data reception completes successfully, the receive data is transferred to FRDRL*1. The RDF in SSR_FIFO is
set to 1 when the amount of the receive data is equal to or greater than the specified receive triggering number stored
in FRDRHL. If the RIE bit in SCR register is 1, an SCIn_RXI interrupt request is generated. Continuous data
reception is enabled by reading the receive data transferred to FRDRL*2 in the SCIn_RXI interrupt handling routine
before an overrun error occurs. If the amount of received data that has been transferred to FRDRL is less than the
RTS trigger number, the CTSn_RTSn pin goes low.
Note 1. In clock synchronous mode, FRDRH is not used.
Note 2. Read data in the order from FRDRH to FRDRL when RDF and ORER are read with receive data.
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29. Serial Communications Interface (SCI)
Initialization
Start data reception
Yes
SSR_FIFO.ORER = 1?
[3]
[2]
[ 3 ] Receive error processing:
If a receive error occurs, read the
SSR_FIFO.ORER flag, perform the relevant error
processing, then set SSR_FIFO.ORER to 0. Data
reception cannot be resumed while
SSR_FIFO.ORER is 1.
[4]
The receive data stored in FRDRL is read until the
amount of stored data is less than the FCR.RTRG
value. Software can check readable data in
FDR.R[4:0].
[5]
Serial reception continuation procedure:
To continue serial reception before overrun error
occurs, finish reading the receive data in FRDRL
and clear SSR_FIFO.RDF to 0. The FRDRL data
can also be read by activating the DMAC or DTC
by an SCIn_RXI interrupt request. The RDF flag is
cleared automatically in this case. Do not write to
the RDF flag.
[6]
Processing in response to an overrun error:
Read FRDRL. In combination with step [7], this
makes correct reception of the next frame
possible.
[7]
Clearing the error flag:
Write 0 to the error flag.
[8]
Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
Error processing
(Continued below)
No
SCI initialization:
Make input port settings for pins to be used as
RXDn pins.
[2]
Read ORER*1 flag in SSR_FIFO
No
[1]
[1]
SCIn_RXI interrupt?*2
Yes
Read receive data in FRDRL
No
All data received?
[4]
[5]
Yes
Set SCR.RIE and RE to 0
End
[3]
Error processing
Overrun error processing
[6]
Clear the SSR_FIFO.ORER flag to 0
[7]
Note 1.
Read the SSR_FIFO.ORER flag
[8]
Note 2.
ORER can also be read from FRDRH.ORER.
However, to clear the ORER flag, write 0 to
SSR_FIFO.ORER.
All receive data is an integer multiple of the
FIFO triggering number.
End
Figure 29.42
Example flow of serial reception in clock synchronous mode with FIFO selected
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29.5.6
(1)
29. Serial Communications Interface (SCI)
Simultaneous Serial Data Transmission and Reception in Clock Synchronous
Mode
Non-FIFO selected
Figure 29.43 shows an example flow of simultaneous serial transmit and receive operations in clock synchronous mode.
After initializing the SCI, the following procedure should be used for simultaneous serial data transmission and receive
operations.
To switch from transmit mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the data transmission by verifying that the TEND flag in the SSR register is set to 1.
2. Initialize the SCR register and then set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously using
a single instruction.
To switch from receive mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the data reception.
2. Set the RIE and RE bits to 0 in the SCR register and then check that the receive error flag ORER in SSR is 0.
3. Set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously using a single instruction.
[1]
Initialization
[1]
SCI initialization:
The TXDn pin can act as the output pin for transmitted data
and the RXDn pin can act as the input pin for received data at
the same time.
[2]
Transmit data write:
Write transmit data to TDR in the SCIn_TXI interrupt request
handling routine.
[3]
Receive error processing:
If a receive error occurs, read the SSR.ORER flag, perform
the relevant error processing, then set SSR.ORER to 0. Data
reception cannot be resumed while SSR.ORER is 1.
[4]
Reading receive data:
Read the receive data in RDR in the SCIn_RXI interrupt
request handling routine.
[5]
Serial transmission/reception continuation procedure:
To continue serial transmission and reception, before the
MSB (bit [7]) of the current frame is received, finish reading
the receive data in RDR by the SCIn_RXI interrupt. Also,
before the MSB (bit [7]) of the current frame is transmitted,
write data to TDR by the SCIn_TXI interrupt.
Transmit data can also be written to TDR by activating the
DMAC or DTC by a transmit data empty interrupt (SCIn_TXI)
request. Similarly, the RDR data can also be read by
activating the DMAC or DTC by a receive data full interrupt
(SCIn_RXI) request.
Start data transmission/reception
No
SCIn_TXI interrupt?
Yes
[2]
Write transmit data to TDR
Read the SSR.ORER flag
Yes
SSR.ORER = 1?
No
No
Error processing
SCIn_RXI interrupt?
Yes
Read receive data in RDR
[4]
All data received?
[5]
No
[3]
Yes
Clear SCR.TIE, RIE, TE, RE,
and TEIE to 0
End
Note:
When switching from transmit or receive operation to simultaneous transmit and receive operations, first set the TIE, RIE,
TE, RE, and TEIE bits in SCR to 0, then set TIE, RIE, TE, and RE bits to 1 simultaneously.
Figure 29.43
Example flow of simultaneous serial transmission and reception in clock synchronous mode with
non-FIFO selected
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(2)
29. Serial Communications Interface (SCI)
FIFO selected
Figure 29.44 shows an example flow of simultaneous serial transmit and receive operations in clock synchronous mode
with FIFO selected.
After initializing the SCI, use the following procedure for simultaneous serial data transmit and receive operations.
To switch from transmit mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the transmission by verifying that the TEND flag in SSR_FIFO is set to 1.
2. Initialize SCR, then set the TIE, RIE, TE, and RE bits in SCR to 1 simultaneously using a single instruction.
To switch from receive mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the reception.
2. Set the RIE and RE bits in SCR to 0 and then check that the receive error flag ORER in SSR_FIFO is 0.
3. Set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously using a single instruction.
[1]
Initialization
[1]
SCI initialization:
The TXDn pin can act as the output pin for transmitted data and
the RXDn pin can act as the input pin for received data at the
same time.
[2]
Transmit data write:
Write transmit data to FTDRL in the SCIn_TXI interrupt request
handling routine. The amount of transmission data that can be
written is 16 bits minus the amount of stored transmit data in the
FIFO.
[3]
Receive error processing:
If a receive error occurs, read the SSR_FIFO.ORER flag, perform
the relevant error processing, then set SSR_FIFO.ORER to 0.
Data reception cannot be resumed while SSR_FIFO.ORER is 1.
[4]
Reading receive data:
The received data stored in FRDRL register is read until the
amount of stored data is less than the FCR.RTRG value. Software
can check the readable data in FDR.R[4:0].
[5]
Serial transmission/reception continuation procedure:
To continue serial reception, before overrun error occurs, finish
reading the receive data in FRDRL and clear the SSR_FIFO.RDF
flag to 0. To continue serial transmission, before transmission of
the current transmit data is finished, write the next transmit data to
FTDRL in the SCIn_TXI interrupt handling routine and clear the
SSR_FIFO.TDFE flag to 0.
Transmit data can also be written to FTDRL by activating the
DMAC or DTC by a transmit FIFO data empty interrupt
(SCIn_TXI) request. Similarly, the FRDRL data can also be read
by activating the DMAC or DTC by a receive FIFO data full
interrupt (SCIn_RXI) request. The RDF and TDFE flags are
cleared automatically in this case.
Do not write to the RDF and TDFE flags.
Start data transmission/reception
No
SCIn_TXI interrupt?
Yes
[2]
Write transmit data to FTDRL
Read ORER*1 flag in SSR_FIFO
SSR_FIFO.ORER = 1?
No
No
Yes
Error processing
SCIn_RXI interrupt*2
Yes
Read receive data in FRDRL
[4]
All data received?
[5]
No
Yes
Clear SCR.TIE, RIE, TE, RE,
and TEIE to 0
[3]
End
Note 1.
Note 2.
ORER can also read from FRDRH.ORER. To clear the ORER flag, write 0 to SSR_FIFO.ORER.
The total receive data amount must be an integral multiple of the FIFO triggering number.
Figure 29.44
Example flow of simultaneous serial transmission and reception in clock synchronous mode with
FIFO selected
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29.6
29. Serial Communications Interface (SCI)
Operation in Smart Card Interface Mode
The SCI supports smart card (IC card) interfaces conforming to ISO/IEC 7816-3 (standard for Identification Cards), as
an extended function of the SCI.
Smart card interface mode can be selected using the appropriate register.
29.6.1
Example Connection
Figure 29.45 shows an example connection between a smart card (IC card) and the MCU.
Because the MCU communicates with an IC card using a single transmission line, interconnect the TXDn and RXDn
pins and pull up the data transmission line to VCC using a resistor, as shown in Figure 29.45.
Setting the TE and RE bits in SCR_SMCI to 1 with an IC card disconnected enables closed-loop transmission or
reception, allowing self-diagnosis. To supply an IC card with the clock pulses generated by the SCI, input the SCKn pin
output to the CLK pin of an IC card.
An output port of the MCU can be used to output a reset signal.
VCC
VCC
TXDn
RXDn
SCKn
Port
Data line
Clock line
Reset line
I/O
CLK
RST
IC card
Main unit of the device to
be connected
Figure 29.45
29.6.2
Example connection with a smart card (IC card)
Data Format (Except in Block Transfer Mode)
Figure 29.46 shows the data transfer formats in smart card interface mode.
The data transfer format is as follows:
One frame consists of 8-bit data and a parity bit in asynchronous mode
During transmission, a value of at least 2 ETUs (elementary time unit – the time required for transferring 1 bit) is set
as a guard time from the end of the parity bit until the start of the next frame
If a parity error is detected during reception, a low error signal is output for 1 ETU after a period of 10.5 ETUs
elapses from the start bit
If an error signal is sampled during transmission, the same data is automatically retransmitted after at least 2 ETUs.
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29. Serial Communications Interface (SCI)
In normal transmission/reception
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Output from the transmitting station
When a parity error occurs
Ds
D0
D1
D2
D3
D4
D5
DE
Output from the transmitting station
Ds:
D0 to D7:
Dp:
DE:
Figure 29.46
Output from the
receiving station
Start bit
Data bits
Parity bit
Error signal
Data formats in smart card interface mode
For communication with IC cards of the direct convention type and inverse convention type, follow the procedures in
this section.
(1)
Direct convention type
For the direct convention type, logic levels 1 and 0 indicate the Z and A states, respectively, and data is transferred with
LSB-first as the start character, as shown in Figure 29.47. Therefore, data in the start character in Figure 29.47 is 3Bh.
When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the PM bit in
SMR_SMCI to use even parity, which is recommended by the smart card standard.
(Z)
Figure 29.47
(2)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp
(Z) state
Direct convention with SDIR in SCMR = 0, SINV in SCMR = 0, and PM in SMR_SMCI = 0
Inverse convention type
For the inverse convention type, logic levels 1 and 0 indicate the A and Z states respectively, and data is transferred with
MSB-first as the start character, as shown in Figure 29.48. Therefore, data in the start character in Figure 29.48 is 3Fh.
When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is at logic level
0 to produce even parity, which is described by the smart card standard, and corresponds to the Z state. Because the
SINV bit only inverts data bits D7 to D0, write 1 to the PM bit in SMR_SMCI to invert the parity bit for both
transmission and reception.
(Z)
A
Z
Z
A
A
A
A
A
A
Z
(Z) state
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
Figure 29.48
29.6.3
Inverse convention with SDIR in SCMR = 1, SINV in SCMR = 1, and PM in SMR_SMCI = 1
Block Transfer Mode
Block transfer mode differs from non-block transfer mode of the smart card interface mode as follows:
If a parity error is detected during reception, no error signal is output. Because the PER bit in SSR_SMCI is set by
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29. Serial Communications Interface (SCI)
error detection, clear the PER flag before receiving the parity bit of the next frame.
During transmission, at least 1 ETU is set as a guard time from the end of the parity bit until the start of the next
frame
Because the same data is not retransmitted, the TEND flag in SSR_SMCI is set to 11.5 ETUs after transmission
starts
In block transfer mode, the ERS flag in SSR_SMCI indicates the error signal status as in non-block transfer mode of
the smart card interface mode, but the flag is read as 0 because no error signal is transferred.
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29.6.4
29. Serial Communications Interface (SCI)
Receive Data Sampling Timing and Reception Margin
Only the clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode.
In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit
rate set up in the BCP2 bit in SCMR and the BCP[1:0] bits in SMR_SMCI.
For data reception, the falling edge of the start bit is sampled with the base clock to perform synchronization.
Receive data is sampled on the 16th, 32nd, 186th, 128th, 46th, 64th, 93rd, and 256th rising edges of the base clock so that it
can be latched at the middle of each bit as shown in Figure 29.49. The reception margin is determined by the following
formula:
M = (0.5 -
1
) - (L - 0.5) F 2N
D - 0.5
N
(1 + F)
× 100 [%]
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Duty cycle of clock (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N = 372 in the specified formula, the reception margin is determined using the
following formula:
M = {0.5 - 1/(2 × 372)} × 100 [%] = 49.866%
372 clocks
372 clocks
186 clocks
0
186 clocks
185
371 0
185
371 0
Base clock
Receive data (RXDn)
Start bit
D0
D1
Synchronization sampling
timing
Data sampling timing
Figure 29.49
Receive data sampling timing in smart card interface mode for clock frequency 372 times the bit
rate
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29.6.5
29. Serial Communications Interface (SCI)
SCI Initialization
Before transmitting and receiving data, write the initial value 00h to SCR_SMCI and initialize the SCI as shown in the
example in Figure 29.50.
Be sure to set the initial value in the TIE, RIE, TE, RE, TEIE bits in SCR_SMCI before switching from transmission to
reception mode or from reception to transmission mode. When the RE bit in SCR_SMCI is set to 0, the RDR register is
not initialized.
To change from reception to transmission mode, first check that reception is complete, and then initialize the SCI. At the
end of initialization, set the TE bit to 1 and the RE bit to 0 in the SCR_SMCI register. Reception completion can be
verified by reading the SCIn_RXI request, or the ORER or PER flag in SSR_SMCI.
To change from transmission to reception mode, first check that transmission is complete, and then initialize the SCI. At
the end of initialization, set the TE bit to 0 and the RE bit to 1 in the SCR_SMCI register. Transmission completion can
be verified by reading the TEND flag in SSR_SMCI.
[1]
Stop the communication and initialize SKE[1:0].
[2]
Set to smart card interface mode.
[3]
Write to SSR_SMCI after reading SSR_SMCI.
[4]
Set the transmission or reception format in SPMR.
[5]
Set the operation mode and the transmission or reception format in
SMR_SMCI.
[6]
Set the transmission or reception format in SCMR.
[7]
Set SEMR.BRME and SEMR.RXDESEL to 0.
[8]
Write the value for the bit rate in BRR.
[9]
Set the I/O port functions for TXDn, RXDn, and SCKn.
Start initialization
Set SCR_SMCI.TIE, RIE, TE, RE, TEIE,
and CKE[1:0] to 0
[1]
Set SIMR1.IICM to 0
Set SCMR.SMIF to 1
[2]
Set SSR_SMCI.ORER, ERS, PER to 0
[3]
Set SPMR.CKPH, CKPOL
[4]
Set SMR_SMCI.GM, BLK, PM, BCP[1:0],
CKS[1:0], and set SMR_SMCI.PE to 1
[5]
Set SCMR.BCP2, SDIR, SINV
Set SEMR.BRME and SEMR.RXDESEL to 0
Set a value in BRR
Set the I/O port functions
Set a value in SCR_SMCI.CKE[1:0]
Set SCR_SCMI.TE or RE to 1, and
set SCR_SMCI.TIE, RIE
[6]
[7]
[8]
[9]
[ 10 ] Set the SCR_SMCI.CKE[1:0]. Although the function depends on
SMR_SMCI.GM, when the CKE[0] bit is set to 1, the clock is output
from the SCKn pin.
[ 11 ] Set the TE or RE bit in SCR_SMCI to 1, then set the TIE and RIE
bits in SCR_SMCI. Do not simultaneously set the TE and RE bits to
[ 10 ]
1 if self-diagnosis is not used.
[ 11 ]
Initialization completed
Figure 29.50
Example flow of SCI initialization in smart card interface mode
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29. Serial Communications Interface (SCI)
Figure 29.51 shows a timing diagram when data transmission is performed by transitioning to smart card interface mode
according to the flow in Figure 29.50. Figure 29.51 shows when the GM bit in SMR_SMCI is set to 0. The timing in
Figure 29.51 shows when the port is connected as SCKn and TXDn, the pins are Hi-Z because the CKE[0] bit in
SCR_SMCI is 0.
Start the clock output to the SCK pin by setting the CKE[0] bit in SCR_SMCI to 1, then start data transmission by
writing the transmit data after setting the TE bit in SCR_SMCI to 1. When the TE bit in SCR_SMCI changes from 0 to 1,
there is a preamble period for one frame before data transmission starts. In smart card interface mode, the TXDn pin is
Hi-Z when there is a preamble period. Pull-up or pull-down for the SCKn and TXDn pins is required outside the MCU.
In smart card interface mode, even when the TE and RE bits in SCR_SMCI are 0, the clock is continuously output if the
clock output setting is used.
Connect port SCKn starts when CKE[0] = 1
SCKn
Mode
Hi-Z
Smart card interface mode
SCR.TE
Preamble period
TXDn
Ds
Hi-Z
TE = 1
Figure 29.51
29.6.6
Data transfer
D0
D1
Write transfer data
Example timing of data transmission in smart card interface mode
Serial Data Transmission (Except in Block Transfer Mode)
Serial data transmission in smart card interface mode (except in block transfer mode) is different from that in non-smart
card interface mode, in that an error signal is sampled and data can be retransmitted in smart card mode. Figure 29.52
shows the data retransfer operation during transmission.
In Figure 29.52:
[1] indicates when an error signal from the receiver end is sampled after 1-frame data is transmitted, the ERS flag in
SSR_SMCI is set to 1. If the RIE bit is 1 in SCR_SMCI, an SCIn_ERI interrupt request is generated. Clear the ERS
flag to 0 before the next parity bit is sampled.
[2] indicates that for a frame in which an error signal is received, the TEND flag in SSR_SMCI is not set. Data is
retransferred from TDR to TSR, allowing automatic data retransmission.
[3] indicates that if no error signal is returned from the receiver, the ERS flag is not set to 1.
[4] indicates that SCI determines that the transmission of 1-frame data, including the retransfer, is complete, and the
TEND flag is set. If the TIE bit is 1 in SCR_SMCI, an SCIn_TXI interrupt request is generated. Write transmit data
to TDR to start transmission of the next data.
Figure 29.54 shows an example flow of serial transmission. All the processing steps are automatically performed using
an SCIn_TXI interrupt request to activate the DMAC or DTC.
When the TEND flag in SSR_SMCI is set to 1 in transmission and when the TIE bit in SCR_SMCI is 1, an SCIn_TXI
interrupt request is generated.
The DMAC or DTC is activated by an SCIn_TXI interrupt request if the SCIn_TXI interrupt request is previously
specified as a source of DMAC or DTC activation, allowing the transfer of transmit data. The TEND flag is
automatically set to 0 when the DMAC or DTC transfers data.
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29. Serial Communications Interface (SCI)
If an error occurs, the SCI automatically retransmits the same data. During this retransmission, the TEND flag is kept at
0 and the DMAC or DTC is not activated. Therefore, the SCI and DMAC or DTC automatically transmit the specified
number of bytes, including retransmission when an error occurs. Because the ERS flag is not automatically cleared, set
the RIE bit to 1 to enable an SCIn_ERI interrupt request generation when an error occurs, and clear the ERS flag to 0.
When transmitting or receiving data using the DMAC or DTC, always enable the DMAC or DTC before setting the SCI.
For DMAC or DTC settings, see section 17, DMA Controller (DMAC) and section 18, Data Transfer Controller (DTC).
nth transfer frame
(n + 1)th transfer
frame
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
SCIn_TXI interrupt signal
[2]
[4]
SSR_SMCI.ERS flag
[1]
Figure 29.52
Note:
[3]
Data retransfer operation in SCI transmission mode
The TEND flag in SSR_SMCI is set at different timings depending on the GM bit setting in SMR_SMCI.
Figure 29.53 shows the TEND flag generation timing.
I/O data
Ds
D0
D1
D2
D3
D4
D5
D6
D7
SSR_SMCI.TEND flag
(SCIn_TXI interrupt)
DE
Guard
time
When GM bit in SMR_SMCI = 0
When GM bit in SMR_SMCI = 1
Figure 29.53
Dp
Ds:
Start bit
D0 to D7:
Dp:
Data bits
Parity bit
DE:
Error signal
12.5 ETU (11.5 ETU in block transfer mode)
11.0 ETU
SSR.TEND flag generation timing during transmission
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29. Serial Communications Interface (SCI)
Start
Initialization
Start data transmission
SSR_SMCI.ERS flag = 0?
No
Yes
Error processing
No
SCIn_TXI interrupt?
Yes
Write transmit data to TDR
No
Write all transmit data?
Yes
SSR_SMCI.ERS flag = 0?
No
Yes
Error processing
No
SCIn_TXI interrupt?
Yes
Set SCR_SMCI.TIE, RIE,
and TE to 0
End
Figure 29.54
29.6.7
Example flow of smart card interface transmission
Serial Data Reception (Except in Block Transfer Mode)
Serial data reception in smart card interface mode is similar to that in non-smart card interface mode. Figure 29.55 shows
the data retransfer operation in reception mode.
[1] indicates that if a parity error is detected in the receive data, the PER flag in SSR_SMCI is set to 1. When the
RIE bit in SCR_SMCI is 1, an SCIn_ERI interrupt request is generated. Clear the PER flag to 0 before the next
parity bit is sampled.
[2] indicates that for a frame in which a parity error is detected, no SCIn_RXI interrupt is generated.
[3] indicates that when no parity error is detected, the PER flag in SSR_SMCI is not set to 1.
[4] indicates that the data is determined to be received successfully. When the RIE bit in SCR_SMCI is 1, an
SCIn_RXI interrupt request is generated.
Figure 29.56 shows an example flow of serial data reception. All the processing steps are automatically performed using
an SCIn_RXI interrupt request to activate the DMAC or DTC.
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29. Serial Communications Interface (SCI)
In reception, setting the RIE bit to 1 allows an SCIn_RXI interrupt request to be generated. The DMAC or DTC is
activated by an SCIn_RXI interrupt request if the SCIn_RXI interrupt request is previously specified as a source of
DMAC or DTC activation, allowing the transfer of receive data.
If an error occurs during reception and either the ORER or PER flag in SSR_SMCI is set to 1, a receive error interrupt
(SCIn_ERI) request is generated. Clear the error flag after the error occurrence. If an error occurs, the DMAC or DTC is
not activated and receive data is skipped. Therefore, the number of bytes of receive data specified in the DMAC or DTC
are transferred.
If a parity error occurs and the PER flag is set to 1 during reception, the receive data is transferred to RDR, therefore
allowing the data to be read.
When a reception is forced to terminate by setting the RE bit in SCR_SMCI to 0 during operation, read the RDR register
because the received data that is not yet read might be left in the RDR.
Note:
For operations in block transfer mode, see section 29.3.9, Serial Data Reception in Asynchronous Mode.
th
n transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(n + 1)th transfer
frame
Retransfer frame
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Ds D0 D1 D2 D3 D4
SCIn_RXI interrupt signal
[2]
[4]
[1]
[3]
SSR_SMCI.PER flag
Figure 29.55
Data retransfer operation in SCI reception mode with data retransfer operation during reception
Start
Initialization
Start data reception
SSR_SMCI.ORER = 0 and
SSR_SMCI.PER = 0?
No
Yes
No
Error processing
SCIn_RXI interrupt?
Yes
Read data from RDR
No
All data received?
Yes
Set SCR_SMCI.RIE and RE to 0
Figure 29.56
Example flow of smart card interface reception
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29.6.8
29. Serial Communications Interface (SCI)
Clock Output Control
When the GM bit in SMR_SMCI is set to 1, the clock output can be controlled by the CKE[1:0] bits in SCR_SMCI. For
details on the CKE[1:0] bits, see section 29.2.12, Serial Control Register for Smart Card Interface Mode (SCR_SMCI)
(SCMR.SMIF = 1). When setting the clock output, the base clock described in section 29.6.4, Receive Data Sampling
Timing and Reception Margin is output.
Figure 29.57 shows an example timing for the clock output control when the CKE[1] bit in SCR_SMCI is set to 0 and the
CKE[0] bit in SCR_SMCI is controlled.
When the GM bit in SMR_SMCI is 0, output control by the CKE[0] bit in SCR_SMCI is immediately reflected in the
SCK pin, so there is a possibility that pulses with an unintended width might be output from the SCK pin.
When the GM bit in SMR_SMCI is 1, the clock with the same pulse width as the base clock is output even if the CKE[0]
bit in SCR_SMCI is changed.
Base clock
CKE[0]
When GM = 0
SCK
When GM = 1
Figure 29.57
Clock output control
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29.7
29. Serial Communications Interface (SCI)
Operation in Simple IIC Mode
Simple IIC mode format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame
after a start condition or restart condition, a master device can specify a slave device as a partner for communications.
The currently specified slave device remains valid until a new slave device is specified or a stop condition is satisfied.
The 8 data bits in all frames are transmitted in the order from the MSB.
The I2C bus format and timing are shown in Figure 29.58 and Figure 29.59.
7-bit address format transmission
S
SLA (7 bits)
W#
A
DATA (8 bits)
A
A/A#
P
1
7
1
1
8
1
1
1
n: Number of transfer frames
n (n = 1 or larger)
: Master device Slave device
7-bit address format reception
S
SLA (7 bits)
R
A
DATA (8 bits)
A
A#
P
1
7
1
1
8
1
1
1
: Slave device Mater device
n (n = 1 or larger)
10-bit address format transmission
S
11110b + SLA
(2 bits)
W#
A
SLA (8 bits)
A
DATA (8 bits)
A
A/A#
P
1
7
1
1
8
1
8
1
1
1
n (n = 1 or larger)
10-bit address format reception
S
11110b + SLA
(2 bits)
W#
A
SLA (8 bits)
A
Sr
11110b + SLA
(2 bits)
R
A
DATA (8 bits)
A
A#
P
1
7
1
1
8
1
1
7
1
1
8
1
1
1
n (n = 1 or larger)
I2C bus format
Figure 29.58
MSB
LSB
SDAn
D7-D1
D0
SCLn
1-7
8
9
SLA
R/W#
A
S
Figure 29.59
D7-D1
D0
1-7
8
DATA
9
A
D7-D1
D0
1-7
8
DATA
9
A
P
I2C bus timing when SLA is 7 bits
S:
Indicates a start condition, when the master device changes the level on the SDAn line from high to low while
the SCLn line is high.
SLA:
Indicates a slave address, by which the master device selects a slave device.
R/W#: Indicates the direction of transfer (reception or transmission). The value 1 indicates transfer from the slave
device to the master device and 0 indicates transfer from the master device to the slave device.
A/A#: Indicates an acknowledge bit. This is returned by the slave device for master transmission and by the master
device for master reception. Return to low indicates ACK and return to high indicates NACK.
Sr:
Indicates a restart condition when the master device changes the level on the SDAn line from high to low while
the SCLn line is high and after the setup time elapses.
DATA:
Indicates the data being received or transmitted.
P:
Indicates a stop condition, when the master device changes the level on the SDAn line from low to high when
the SCLn line is high.
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29.7.1
29. Serial Communications Interface (SCI)
Generation of Start, Restart, and Stop Conditions
Writing 1 to the IICSTAREQ bit in SIMR3 causes the generation of a start condition. The generation of a start condition
proceeds through the following operations:
The level on the SDAn line falls (from high level to low level) and the SCLn line is kept in the released state
The hold time for the start condition is set as half of a bit period at the bit rate determined by the BRR setting
The level on the SCLn line falls (from high level to low level), the IICSTAREQ bit is set to 0, and a start-condition
generated interrupt is output.
Writing 1 to the IICRSTAREQ bit in SIMR3 causes the generation of a restart condition. The generation of a restart
condition proceeds through the following operations:
The SDAn line is released and the SCLn line is kept at a low level
The period at low level for the SCLn line is set as half of a bit period at the bit rate determined by the BRR setting
The SCLn line is released (transition from low to high level)
When the high level is detected on the SCLn line, the setup time for the restart condition is set as half of a bit period
at the bit rate determined by the BRR setting
The level on the SDAn line falls (from high level to low level)
The hold time for the restart condition is set as half of a bit period at the bit rate determined by the BRR setting
The level on the SCLn line falls (from high level to low level), the IICRSTAREQ bit in SIMR3 is set to 0, and a
restart-condition generated interrupt is output.
Writing 1 to the IICSTPREQ bit in SIMR3 causes the generation of a stop condition. The generation of a stop condition
proceeds through the following operations:
The level on the SDAn line falls (from high level to low level) and the SCLn line is kept at a low level
The period at low level for the SCLn line is set as half of a bit period at the bit rate determined by the BRR setting
The SCLn line is released (transition from low to high level)
When a high level on the SCLn line is detected, the setup time for the stop condition is set as half of a bit period at
the bit rate determined by the BRR setting
The SDAn is released (transition from low to high level), the IICSTPREQ bit in SIMR3 is set to 0, and a stopcondition generated interrupt is output.
Figure 29.60 shows the timing of operations in the generation of start, restart, and stop conditions.
SCLn
SDAn
SIMR3.IICSTAREQ
SIMR3.IICRSTAREQ
SIMR3.IICSTPREQ
SIMR3.IICSDAS[1:0]
11b 01b
SIMR3.IICSCLS[1:0]
Start-condition generated
interrupt request
Figure 29.60
00b
01b
00b
Restart-condition generated
interrupt request
01b
11b
Stop-condition generated
interrupt request
Timing of operations to generate start, restart, and stop conditions
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29.7.2
29. Serial Communications Interface (SCI)
Clock Synchronization
The SCLn line can be driven low if a wait is inserted by a slave device at the other side of the transfer. Setting the
IICCSC bit in SIMR2 to 1 allows clock synchronization control when a difference arises between the levels of the
internal SCLn clock signal and the level being input on the SCLn pin.
When the IICCSC bit is set to 1, the level of the internal SCLn clock signal changes from low to high. Counting to
determine the period at high level stops while the low level is input on the SCLn pin. Counting to determine the period at
high level starts after the input on the SCLn pin transitions to the high level.
The interval from the time until counting, to determine the period at high level that starts on the transition of the SCLn
pin to the high level, is the total of the delay of SCLn output, delay for noise filtering of the input on the SCLn pin (2 or
3 cycles of sampling clock for the noise filter), and delay for internal processing (1 or 2 PCLK cycles). The period at high
level of the internal SCLn clock is extended even if other devices do not place the low level on the SCLn line.
If the ICCSC bit in SIMR2 register is 1, synchronization is obtained for the transmission and reception of data by taking
the logical AND of the input on the SCLn pin and the internal SCLn clock. If the IICCSC bit in SIMR2 is 0,
synchronization with the internal SCLn clock is obtained for the transmission and reception of data.
If a slave device inserts a wait period into the interval until the transition of the internal SCLn clock signal from low to
high level after a request for the generation of a start, restart, or stop condition is issued, the time until generation is
prolonged by that period.
If a slave device inserts a wait period after the transition of the internal SCLn clock signal from the low to the high level,
although the generation-completed interrupt is issued without stopping the waiting period, generation of the condition
itself is not guaranteed. Figure 29.61 shows an example operation for synchronizing the clocks.
SCLn output from the
other device
SCLn line
Internal SCLn clock
Clock driving transfer
internally
Counting of the period
at low level starts
Counting of the period
at high level starts
Counting stops until the SCLn line is
at the high level
Figure 29.61
Counting of the period
at high level starts
Counting stops while the SCLn line
is at the low level
Example operation for clock synchronization
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29.7.3
29. Serial Communications Interface (SCI)
SDA Output Delay
The IICDL[4:0] bits in SIMR1 can be used to set a delay for output on the SDAn pin relative to the falling edges of
output on the SCLn pin. Delay settings from 0 to 31 are selectable. The delay settings represent periods of the associated
numbers of cycles of the clock signal from the on-chip baud rate generator (derived by frequency-dividing the base
clock, PCLK, by the divisor selected in the CKS[1:0] bit in the SMR register). A delay for output on the SDAn pin
applies to the start condition/restart condition/stop condition signal, 8-bit transmit data, and an acknowledge bit.
If the SDAn output delay is shorter than the time required for the level on the SCLn pin to fall, the change of the output
on the SDAn pin starts while the output level on the SCLn pin is falling, creating a possibility for erroneous operation of
slave devices. Ensure that the settings for the output delay on the SDAn pin specify a time period greater than the time
that the output on the SCLn pin takes to fall (300 ns for IIC in Standard mode and Fast mode).
Figure 29.62 shows the timing of delays in SDAn output.
Clock signal from the on-chip
baud rate generator (internal signal)
Output on the SCLn pin
Output on the SDAn pin
(IICDL[4:0] = 00000b)
Output on the SDAn pin
(IICDL[4:0] = 00001b)
Output on the SDAn pin
(IICDL[4:0] = 00010b)
Output on the SDAn pin
(IICDL[4:0] = 00111b)
Output on the SDAn pin
(IICDL[4:0] = 01000b)
Figure 29.62
Timing of delays in SDAn output
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29.7.4
29. Serial Communications Interface (SCI)
SCI Initialization in Simple IIC Mode
Before transferring data, write the initial value 00h to SCR and initialize the interface as shown in the example in Figure
29.63.
Before making any changes to the operating mode or transfer format, be sure to set SCR to its initial value.
In simple IIC mode, the open-drain setting for the communication ports should be made on the port side.
Start of initialization
[1]
Set the I/O ports to allow use (on N-channel open-drain
output pins) of the SCLn and SDAn pin functions.
Set SCR.TIE, RIE, TE, RE, TEIE
and CKE[1:0] to 0
[2]
Place the SCLn and SDAn pins in a high-impedance
state until a start condition is to be generated.
[3]
Set the format for transmission and reception in SMR
and SCMR.
In SMR, set CKS[1:0] to the target value and set the
other bits to 0.
In SCMR, set SDIR to 1 and set SINV and SMIF to 0.
[4]
Write the value for the target bit rate to BRR.
Set the I/O port functions
Set SIMR3.IICSDAS[1:0] and
SIMR3.IICSCLS[1:0] to 11b
[1]
[2]
Set up the transfer or reception format in
SMR and SCMR
[3]
[5]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not required if SEMR.BRME is set
to 0.
Set the value in BRR
[4]
[6]
Set a value in MDDR
[5]
Set the values in SEMR, SNFR, SIMR1,
SIMR2, and SPMR
[6]
Set the values in SEMR, SNFR, SIMR1, SIMR2, and
SPMR.
In SEMR, set NFEN and BRME.
In SNFR, set NFCS[2:0].
In SIMR1, set IICM to 1 and set IICDL[4:0] as required.
In SIMR2, set IICACKT and IICCSC to 1 and set
IICINTM as required.
In SPMR, set all the bits to 0.
Set SCR.RE and TE to 1 and
set SCR.TIE, RIE and TEIE
[7]
[7]
Set SCR.RE and TE to 1. Then, set SCR.TIE, RIE, and
TEIE (for transmission and when SIMR2.IICINTM is 1,
set RIE to 0).
Setting SCR.TE and RE to 1 makes the SCLn and
SDAn pin functions available.
Start of transmission or reception
Figure 29.63
Example flow of SCI initialization in simple IIC mode
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29.7.5
29. Serial Communications Interface (SCI)
Operation in Master Transmission in Simple IIC Mode
Figure 29.64 and Figure 29.65 show examples of master transmission and Figure 29.66 shows an example flow of data
transmission. The value of the IICINTM bit in the SIMR2 register is assumed to be 1 (use reception and transmission
interrupts) and the value of the RIE bit in the SCR register is assumed to be 0 (SCIn_RXI and SCIn_ERI interrupt
requests are disabled). See Table 29.28 for more information on the STI interrupt.
When 10-bit slave addresses are used, steps [3] and [4] in Figure 29.66 are repeated twice.
In simple IIC mode, the transmit data empty interrupt (SCIn_TXI) is generated when communication of one frame is
complete, unlike the timing of generation of the SCIn_TXI interrupt request during clock synchronous transmission.
Start condition
Slave address (7 bits)
Transmitted data
W#
Stop condition
SCLn
SDAn
D7
D6
D1
D0
ACK
D7
D6
D1
D0
ACK/NACK
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Acceptance of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
STI interrupt flag
(IELSRn.IR*1)
Generation of STI interrupt
Acceptance of request
Reception of ACK
SISR.IICACKR flag
Generation of request
Reception of NACK
Reception of ACK
Note 1.
Figure 29.64
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example 1 operation for master transmission in simple IIC mode with 7-bit slave addresses,
transmission interrupts, and reception interrupts
When the IICINTM bit in SIMR2 register is set to 0, using ACK/NACK interrupts during master transmission, the
DMAC or DTC is activated by the ACK interrupt as the trigger and the required number of data bytes are transmitted.
When a NACK is received, error processing such as transmission stop and retransmission is performed using the NACK
interrupt as the trigger.
Start condition
Slave address (7 bits)
Transmitted data
W#
Stop condition
SCLn
SDAn
D7
D6
D1
D0
ACK
D7
D6
D1
D0
NACK
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Generation of SCIn_TXI
interrupt request
SCIn_RXI interrupt flag
(IELSRn.IR*1)
Generation of SCIn_RXI
interrupt request
STI interrupt flag
(IELSRn.IR*1)
Generation of STI interrupt request
Note 1.
Figure 29.65
Acceptance of STI interrupt request
Acceptance of SCIn_TXI
interrupt request
Acceptance of SCIn_RXI
interrupt request
Generation of STI interrupt request
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example 2 operation for master transmission in simple IIC mode with 7-bit slave addresses, ACK
interrupts, and NACK interrupts
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29. Serial Communications Interface (SCI)
Initialization
[1]
[1] Initialization for simple IIC mode:
For transmission, set the SCR.RIE bit to 0.
(RXI and ERI interrupts requests are disabled.)
[2]
[2] Generate a start condition.
Start of transmission
Simultaneously set SIMR3.IICSTAREQ to 1 and
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 01b
STI interrupt?
No
[3] Writing to TDR:
Writing the slave address and value for the R/W bit to TDR.
Yes
Set SIMR3.IICSTIF to 0 and
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 00b
[3]
Write the slave address and value for the
R/W bit in TDR
SCIn_TXI interrupt?
No
If 10-bit slave addresses are in use,
processing of [3] and [4] is repeated twice.
Yes
SISR.IICACKR = 0?
No
[4]
Yes
[4] Confirming ACK response from the slave device:
Check the SISR.IICACKR bit. If its value is 0, it
indicates that the slave device responded with ACK
and operations proceed. If its value is 1,
it indicates that there was no response from
a slave device, so the next transition is to generate
the stop condition.
Write transmit data in TDR
SCIn_TXI interrupt?
No
Yes
No
All data transmitted?
[5]
[5] Steps for continuing with serial transmission:
When transmission is to continue, write additional
transmit data to TDR. Except for the first data to be
transmitted, an SCIn_TXI interrupt request can
activate the DMAC or DTC to handle writing of data
to TDR, but cannot confirm the status of ACK or NACK.
[6]
[6] Generation of a stop condition.
Yes
Simultaneously set SIMR3.IICSTPREQ to 1 and
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 01b
STI interrupt?
No
Yes
Set SIMR3.IICSTIF to 0 and
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 11b
Note: In simple IIC mode, the SCIn_TXI interrupt request is
generated when communication is complete.
End
Figure 29.66
Example flow of master transmission in simple IIC mode with transmission interrupts and
reception interrupts
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29.7.6
29. Serial Communications Interface (SCI)
Master Reception in Simple IIC Mode
Figure 29.67 shows an example of master reception operation in simple IIC mode and Figure 29.68 shows an example
flow of master reception.
The value of the IICINTM bit in SIMR2 register is assumed to be 1, using reception and transmission interrupts.
In simple IIC mode, the transmit data empty interrupt (SCIn_TXI) is generated when communication of one frame is
complete, unlike the SCIn_TXI interrupt request generation timing during clock synchronous transmission.
Start
condition
Slave address (7 bits)
Stop condition
Received data
R
SCLn
D7
SDAn
D6
D1
D0
ACK
D7
D6
D1
D0
NACK
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SCIn_RXI is assumed to have been disabled
by setting SCR.RIE = 0
Generation of SCIn_RXI interrupt request
Acceptance of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
STI interrupt flag
(IELSRn.IR*1)
Generation of SCIn_TXI interrupt request
Acceptance of STI interrupt request
Generation of STI interrupt request
Generation of STI interrupt request
Note 1.
Figure 29.67
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example operation for master reception in simple IIC mode with 7-bit slave addresses,
transmission interrupts, and reception interrupts
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29. Serial Communications Interface (SCI)
[1] [1] Initialization for simple IIC mode:
Set the RIE bit in SCR to 0.
Initialization
Start of reception
Simultaneously set SIMR3.IICSTAREQ to 1 and
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 01b
STI interrupt?
[2]
[2] Generate a start condition.
No
Yes
Set SIMR3.IICSTIF to 0 and set
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 00b
[3] [3] Writing to TDR:
Writing the slave address and value for the R/W bit to TDR.
Write the slave address and value for
the R/W bit to TDR
SCIn_TXI interrupt?
No
Yes
SISR.IICACKR = 0?
No
Yes
Set SIMR2.IICACKT to 0.
Set SCR.RIE to 1.
Next data is the last?
[4]
[4] Confirming ACK response from the slave device :
Check the SISR.IICACKR bit. If its value is 0, it indicates that the
slave device responded with ACK and operations proceed. If its value
is 1, it indicates that there was no response from a slave device so
the next transition is to generate the stop condition.
Yes
[5]
No
[6]
Set SIMR2.IICACKT to 1
Write FFh as dummy data to TDR
Write FFh as dummy data to TDR
SCIn_RXI interrupt?
No
No
SCIn_RXI interrupt?
Yes
Yes
Read received data from RDR
SCIn_TXI interrupt?
Read received data from RDR
No
Yes
[5] Step for continuing with reception:
To proceed with reception, write FFh as dummy transit data to TDR.
Other than in the first and last rounds of transmission, an SCIn_TXI
request can activate DMAC or DTC to handle writing of data to TDR.
Other than for the last data to be received, an SCIn_RXI
request can activate DMAC or DTC to handle reading of data from RDR.
[6] NACK is transmitted in response to the last data.
Yes
[7]
Simultaneously set SIMR3.IICSTPREQ to 1 and
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 01b
STI interrupt?
No
Yes
[7] Generation of a stop condition.
Note: In simple IIC mode, the SCIn_TXI interrupt request is
generated when communication is complete.
No
SCIn_TXI interrupt?
Set SIMR3.IICSTIF to 0 and set
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] to 11b
End
Figure 29.68
Example flow of master reception in simple IIC mode with transmission interrupts and reception
interrupts
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29.8
29. Serial Communications Interface (SCI)
Operation in Simple SPI Mode
As an extended function, the SCI supports a simple SPI mode that handles transfer between one or multiple master
devices and multiple slave devices.
To place the SCI in simple SPI mode, use the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0,
SMR.CM = 1) and set the SSE bit in SPMR register to 1. When the configuration only has a single master, the SSn pin
function is not required to connect the device used as the master in simple SPI mode. Therefore, in this case, set the SSE
bit in the SPMR register to 0.
Figure 29.69 shows an example of connections in simple SPI mode. Use a general port pin to produce the SSn output
signal from the master.
In simple SPI mode, data is transferred in synchronization with clock pulses in the same way as in clock synchronous
mode. One character of transfer data consists of 8 bits of data, and parity bits cannot be appended. The data can be
inverted by setting the SINV bit in SCMR to 1.
Because the receiver and transmitter are independent of each other within the SCI module, full-duplex communications
are possible, with a shared clock signal. Additionally, because both the transmitter and receiver have a buffered structure,
it is possible to both write the next transmit data while transmission is in progress and read previously received data
while reception is in progress. This enables continuous transfer.
Device 1 (master)
Device 2 (slave)
Port pin (output)
SSn (input)
Port pin (output)
SSn (input)
*1
SCKn (input)
SCKn (output)
MISOn (output)
MISOn (input)
MOSIn (input)
MOSIn (output)
Device 3 (slave)
SSn (input)
SCKn (input)
MISOn (output)
MOSIn (input)
Note 1.
Figure 29.69
The SSn input is not required in a single-master system
(the interface is used with the setting SPMR.SSE = 0).
Example connections using simple SPI mode in single master mode with SPMR.SSE bit = 0
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29.8.1
29. Serial Communications Interface (SCI)
States of Pins in Master and Slave Modes
The direction (input or output) of pins for the simple SPI mode interface differs according to whether the device is a
master (SCR.CKE[1:0] = 00b or 01b and SPMR.MSS = 0) or slave (SCR.CKE[1:0] = 10b or 11b and SPMR.MSS = 1).
Table 29.24 shows the relationship between the pin states, mode, and level on the SSn pin.
Table 29.24
Mode
Master
mode*1
Slave mode
Note 1.
Note 2.
Note 3.
29.8.2
Pin states by mode and input level on the SSn pin
Input on SSn pin
State of TXDn pin
State of RXDn pin
State of SCKn pin
High level
(transfer can proceed)
Output for data
transmission*2
Input for received data
Clock output*3
Low level
(transfer cannot proceed)
High-impedance
Input for received data
(but disabled)
High-impedance
High level
(transfer cannot proceed)
Input for received data
(but disabled)
High-impedance
Clock input
(but disabled)
Low level
(transfer can proceed)
Input for received data
Output for data
transmission
Clock input
When there is only a single master (SPMR.SSE = 0), transfer is possible regardless of the input level on the SSn pin. This is
equivalent to the input of a high level on the SSn pin. Because the SSn pin function is not required, the pin is available for other
purposes.
The MOSIn pin output is in the high-impedance state when serial transmission is disabled (SCR.TE bit = 0).
The SCKn pin output is in a high-impedance state when serial transmission is disabled (SCR.TE and RE bits = 00b) in a multimaster configuration (SPMR.SSE = 1).
SS Function in Master Mode
Setting the SCR.CKE[1:0] bits to 00b and the SPMR.MSS bit to 0 selects master operation. The SSn pin is not used in
single-master configurations (SPMR.SSE = 0) and so the transmission or reception can proceed regardless of the value of
the SSn pin.
In a multi-master configuration (SPMR.SSE = 1), when the level on the SSn pin is high, a master device outputs clock
signals from the SCKn pin before starting transmission or reception to indicate that there are no other masters or another
master is performing reception or transmission. When the level on the SSn pin is low in a multi-master configuration
(SPMR.SSE = 1), there are other masters, and a transmission or reception is in progress. The MOSIn output and SCKn
pins are placed in a high-impedance state and starting transmission or reception is not possible. In addition, the value of
the MFF bit in SPMR is 1, indicating a mode fault error. In a multi-master configuration, start the error processing by
reading the MFF flag in SPMR. If a mode fault error occurs while transmission or reception is in progress, transmission
or reception is not stopped, but the MOSIn and SCKn outputs are in the high-impedance state after the completion of the
transfer. Use a general port pin to produce the SS output signal from the master.
29.8.3
SS Function in Slave Mode
Setting the SCR.CKE[1:0] bits to 10b and the SPMR.MSS bit to 1 selects slave operation. When the level on the SSn pin
is high, the MISOn output pin is in a high-impedance state and clock input through the SCKn pin is ignored. When the
level on the SSn pin is low, clock input through the SCKn pin is valid and transmission or reception can proceed.
If the input on the SSn pin changes from low to high level during transmission or reception, the MISOn output pin is
placed in a high-impedance state. Meanwhile, the internal processing for transmission or reception continues at the rate
of the clock input through the SCKn pin until processing for the character currently being transmitted or received is
complete, after which it stops, and the appropriate interrupt (SCIn_TXI, SCIn_RXI, or SCIn_TEI) is generated.
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29.8.4
29. Serial Communications Interface (SCI)
Relationship between Clock and Transmit/Receive Data
The CKPOL and CKPH bits in SPMR can be used to set up the clock for use in transmission and reception in four
different ways. The relation between the clock signal and the transmission and reception of data is shown in Figure
29.70. The relation is the same for both master and slave operation. This is the same as when the level on the SSn pin is
high.
One unit of transfer data (character or frame)
(1) When CKPH = 0
SSn pin
(slave)
SCKn pin
(CKPOL = 0)
SCKn pin
(CKPOL = 1)
MOSIn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MISOn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CKPH = 1
SSn pin
(slave)
SCKn pin
(CKPOL = 0)
SCKn pin
(CKPOL = 1)
MOSIn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MISOn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 29.70
29.8.5
Relation between clock signal and transmit or receive data in simple SPI mode
SCI Initialization in Simple SPI Mode
Initialization in simple SPI mode is the same as in clock synchronous mode. See Figure 29.32 for an example
initialization flow. The CKPOL and CKPH bits in SPMR must be set to ensure that the selected clock signal
configuration is suitable for both master and slave devices.
Always initialize the SCR register before making any changes to the operating mode or transfer format.
Note:
Only the SCR.RE bit is set to 0. The SSR.ORER, FER, PER, and RDR flags are not initialized.
Changing the value of the TE bit in the SCR register from 1 to 0 or from 0 to 1, leads to the generation of a transmit data
empty interrupt (SCIn_TXI), if the TIE bit in the SCR register is 1.
29.8.6
Transmission and Reception of Serial Data in Simple SPI Mode
In master operation, ensure that the SSn pin of the slave device on the other side of the transfer is at a low level before
starting the transfer and at a high level on completion of the transfer. Otherwise, the procedures are the same as in clock
synchronous mode.
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29.9
29. Serial Communications Interface (SCI)
Bit Rate Modulation Function
Using the bit rate modulation function, the bit rate can be evenly corrected using the number specified in MDDR when
PCLK is selected using the CKS[1:0] bits in SMR/SMR_SMCI.
Figure 29.71 shows an example where PCLK is selected in the CKS[1:0] bits in SMR/SMR_SMC, and BRR and MDDR
are set to 0 and 160 respectively in asynchronous mode. In this example, the cycle of the base clock is evenly corrected
(256/160) and the bit rate is also corrected (160/256).
Note:
Enabling an internal clock causes bias, and expansion and contraction are generated in the pulse width of the internal base
clock.
Do not use this function in clock synchronous mode and in the highest speed settings in simple SPI mode
(SMR.CKS[1:0] = 00b, SCR.CKE[1] = 0, and BRR = 0).
Internal clock
(bit rate counter input)
Internal base clock
Transmit/receive data
1-bit interval is 16 cycles of the internal base clock
(a) When the bit modulation function is not used
160 clocks among 256 clocks are evenly enabled (96 clocks are disabled) by setting MDDR
Internal clock
(bit rate counter input)
Internal base clock
Transmit/receive data
1-bit interval is 16 cycles of the internal base clock
This figure shows an example when 1-bit interval is corrected to 52/32. (1-bit interval is evenly corrected to 256/160.)
(b) The bit rate is corrected (160/256) using the bit rate modulation function
Figure 29.71
Example internal base clock using bit rate modulation function
29.10 Interrupt Sources
29.10.1
Buffer Operations for SCIn_TXI and SCIn_RXI Interrupts (non-FIFO selected)
If the conditions for SCIn_TXI and SCIn_RXI interrupts are satisfied while the interrupt status flag in the ICU is 1, the
ICU does not output the interrupt request but saves it internally, with a capacity for saving one request per source.
When the interrupt status flag in the ICU becomes 0, the interrupt request retained within the ICU is output. The
internally retained interrupt request is automatically discarded when the actual interrupt is output. Clearing of the
associated interrupt enable bit (the TIE or RIE bit in the SCR/SCR_SMCI) can also be used to discard an internally
retained interrupt request.
29.10.2
Buffer Operation for SCIn_TXI and SCIn_RXI Interrupts (FIFO selected)
When an interrupt status flag in the ICU is set to 1, the SCIn_TXI and SCIn_RXI interrupts do not output interrupt
requests to the ICU. When an interrupt status flag of the ICU is cleared to 0, and if the conditions for SCIn_TXI and
SCIn_RXI interrupts are satisfied, an interrupt request is generated.
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29.10.3
(1)
29. Serial Communications Interface (SCI)
Interrupts in Asynchronous, Clock Synchronous, and Simple SPI Modes
Non-FIFO selected
Table 29.25 lists interrupt sources in asynchronous mode, clock synchronous mode, and simple SPI mode. A different
interrupt vector can be assigned to each interrupt source. Individual interrupt sources can be enabled or disabled with the
enable bits in SCR.
If the TIE bit in SCR register is 1, an SCIn_TXI interrupt request is generated when transmit data is transferred from
TDR or TDRHL*1 to the TSR. An SCIn_TXI interrupt request can also be generated using a single instruction to set the
TE and TIE bits to 1 in the SCR simultaneously. An SCIn_TXI interrupt request can activate the DMAC or DTC to
handle data transfer.
An SCIn_TXI interrupt request is not generated by setting TE to 1 when the TIE bit is 0 or by setting TIE to 1 when TE
is 1*2 in the SCR register.
When new data is not written by the time of transmission of the last bit of the current transmit data and the TEIE bit is 1
in SCR, the TEND flag in SSR sets to 1 and an SCIn_TEI interrupt request is generated. Additionally, when the TE bit is
1 in SCR, the TEND flag in SSR retains the value 1 until more transmit data are written to the TDR or TDRHL*1, and
setting the TEIE bit in SCR to 1 leads to the generation of an SCIn_TEI interrupt request.
Writing data to the TDR or TDRHL*1 leads to clearing of the TEND flag in SSR and, after a certain time, discarding of
the SCIn_TEI interrupt request.
If RIE is 1 in SCR, an SCIn_RXI interrupt request is generated when received data is stored in RDR. An SCIn_RXI
interrupt request can activate the DMAC or DTC to handle data transfer.
Setting any of the ORER, FER, and PER flags in SSR to 1 when the RIE bit in SCR is 1 leads to the generation of an
SCIn_ERI interrupt request. An SCIn_RXI interrupt request is not generated at this time. Clearing all three flags (ORER,
FER, and PER) leads to discarding of the SCIn_ERI interrupt request.
(2)
FIFO selected
Table 29.26 lists interrupt sources in FIFO selected mode.
If the TIE bit in the SCR register is 1, an SCIn_TXI interrupt request is generated when the amount of stored data in the
FTDRL register is equal to or less than the threshold value indicated in the TTRG bit in FCR register. An SCIn_TXI
interrupt request can also be generated by using a single instruction to set the TE and TIE bits in SCR to 1
simultaneously.
An SCIn_TXI interrupt request is not generated by setting the TE bit in the SCR register to 1 when TIE bit in the SCR
register is 0 or by setting TIE to 1 when TE is 1.
If the TEIE bit in SCR register is 1 and if the next data is not written to the FTDRL register by the time the last bit of the
transmit data is sent, the TEND flag in SSR_FIFO register is set to 1 and the SCIn_TEI interrupt request is generated.
If the RIE bit in the SCR register is 1, an SCIn_RXI interrupt request is generated when the amount of stored data in the
FRDRL becomes equal to or greater than the threshold value indicated in the RTRG bit in the FCR register. When RTRG
is 0, an SCIn_RXI interrupt does not occur even when the amount of data in the receive FIFO is equal to 0.
If the RIE bit in the SCR register is 1, when the ORER flag in the SSR_FIFO register is set to 1 or data with a framing
error or a parity error is stored in the FRDRL register, an SCIn_ERI interrupt request is generated. When the amount of
data stored in the FRDRL register is at or above the threshold value, an SCIn_RXI interrupt request is also generated.
The SCIn_ERI interrupt request can be canceled, in which case the ORER, FER, and PER flags in the SSR_FIFO
register are all cleared.
Note 1. When asynchronous mode and 9-bit data length are selected.
Note 2. To temporarily prohibit SCIn_TXI interrupts on transmission of the last of the data when a new round of
transmission is to be started, after handling the transmission-completed interrupt, control activation of the
interrupt using the interrupt request enable bit in the ICU rather than using the TIE bit in the SCR register. This
approach can prevent the suppression of SCIn_TXI interrupt requests in the transfer of new data.
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Table 29.25
29. Serial Communications Interface (SCI)
SCI interrupt sources with non-FIFO selected
Name
Interrupt source
Interrupt flag
Interrupt enable
DTC activation
DMAC activation
SCIn_ERI
Receive error*1
ORER, FER, PER,
DFER, DPER
RIE
Not possible
Not possible
SCIn_RXI
Receive data full
RDRF
RIE
Possible
Possible
Address match
DCMF
RIE
Possible
Possible
SCIn_AM
Address match
DCMF
-
Possible
Possible
SCIn_TXI
Transmit data empty
TDRE
TIE
Possible
Possible
SCIn_TEI
Transmit end
TEND
TEIE
Not possible
Not possible
Note 1. The interrupt flag is only ORER when in clock synchronous and simple SPI mode.
Table 29.26
SCI interrupt sources with FIFO selected
Name
Interrupt source
Interrupt flag
Interrupt enable
DTC activation
DMAC activation
SCIn_ERI
Receive error*1
ORER, FER, PER,
DFER, DPER
RIE
Not possible
Not possible
DR (when
FCR.DRES = 1)
RIE
Not possible
Not possible
SCIn_RXI
Receive data full
RDF
RIE
Possible
Possible
Receive data ready
DR (when
FCR.DRES = 0)
RIE
Possible
Possible
Address match
DCMF
RIE
Possible
Possible
SCIn_AM
Address match
DCMF
-
Possible
Possible
SCIn_TXI
Transmit data empty
TDFE
TIE
Possible
Possible
SCIn_TEI
Transmit end
TEND
TEIE
Not possible
Not possible
Note 1. The interrupt flag is only ORER when in clock synchronous and simple SPI mode.
29.10.4
Interrupts in Smart Card Interface Mode
Table 29.27 lists the interrupt sources in smart card interface mode. A transmit end interrupt (SCIn_TEI) request and an
address match (SCIn_AM) request cannot be used in this mode.
Table 29.27
SCI interrupt sources in smart card interface mode
Name
Interrupt source
Interrupt flag
Interrupt enable
DTC activation
DMAC activation
SCIn_ERI
Receive error or error
signal detection
ORER, FER, ERS
RIE
Not possible
Not possible
SCIn_RXI
Receive data full
RDRF
RIE
Possible
Possible
SCIn_TXI
Transmit end
TEND
TIE
Possible
Possible
Data transmission or reception using the DMAC or DTC is also possible in smart card interface mode. In transmission,
when the TEND flag in SSR_SMCI is set to 1, an SCIn_TXI interrupt request is generated. The SCIn_TXI interrupt
request activates the DMAC or DTC, allowing transfer of transmit data if the SCIn_TXI request is previously specified
as a source for DMAC or DTC activation. The TEND flag is automatically set to 0 when the DMAC or DTC transfers
data.
If an error occurs, the SCI automatically retransmits the same data. During the retransmission, the TEND flag is kept at 0
and the DMAC or DTC is not activated. Therefore, the SCI and DMAC or DTC automatically transmit the specified
number of bytes, including retransmission when an errors occur. However, the ERS flag in SSR_SMCI is not
automatically cleared to 0 at error occurrence. Therefore, the ERS flag must be cleared by setting the RIE bit in
SCR_SMCI to 1 to enable an SCIn_ERI interrupt request to be generated at error occurrence.
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29. Serial Communications Interface (SCI)
When transmitting or receiving data using the DMAC or DTC, always enable the DMAC or DTC before setting the SCI.
For DMAC or DTC settings, see section 17, DMA Controller (DMAC) and section 18, Data Transfer Controller (DTC).
In reception, an SCIn_RXI interrupt request is generated when receive data is set to RDR. This SCIn_RXI interrupt
request activates the DMAC or DTC, allowing transfer of receive data if the SCIn_RXI request is specified as a source of
DMAC or DTC activation. If an error occurs, the error flag is set. Therefore, the DMAC or DTC is not activated and an
SCIn_ERI interrupt request is issued to the CPU instead. The error flag must be cleared.
29.10.5
Interrupts in Simple IIC Mode
Table 29.28 lists the interrupt sources in simple IIC mode. The STI interrupt is allocated to the transmit end interrupt
(SCIn_TEI) request. The receive error interrupt (SCIn_ERI) and the address match (SCIn_AM) request cannot be used.
The DMAC or DTC can also be used to handle transfer in simple IIC mode.
When the IICINTM bit in SIMR2 register is 1:
An SCIn_RXI request is generated on the falling edge of the SCLn signal for the 8th bit. If SCIn_RXI is previously
set up as an activation source for the DMAC or DTC, the SCIn_RXI request activates the DMAC or DTC to handle
transfer of the received data.
An SCIn_TXI request is generated on the falling edge of the SCLn signal for the 9th bit (acknowledge bit). If
SCIn_TXI is previously set up as an activation source for the DMAC or DTC, the SCIn_TXI request activates the
DMAC or DTC to handle transfer of the transmit data.
When the IICINTM bit in SIMR2 register is 0:
An SCIn_RXI request (ACK detection) is generated if the input on the SDAn pin is low on the rising edge of the
SCLn signal for the 9th bit (acknowledge bit)
An SCIn_TXI request (NACK detection) is generated if the input on the SDAn pin is high on the rising edge of the
SCLn signal for the 9th bit (acknowledge bit)
If SCIn_RXI was previously set up as an activation source for the DMAC or DTC, the SCIn_RXI request activates
the DMAC or DTC to handle transfer of the received data.
If the DMAC or DTC is used for data transfer in reception or transmission, always set up and enable the DMAC or DTC
before setting up the SCI.
When the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits in SIMR3 are used to generate a start condition, restart
condition, or stop condition, the STI request is issued when generation is complete.
Table 29.28
SCI interrupt sources: simple IIC mode
Name
Interrupt source
Interrupt flag
Interrupt enable
DTC activation
DMAC activation
SCIn_RXI
Reception, ACK detection
-
RIE
Possible
Possible
SCIn_TXI
Transmission, NACK detection
-
TIE
Possible
Possible
STIn
Completion of generation of a
start, restart, or stop condition
IICSTIF
TEIE
Not possible
Not possible
Note:
Activation of the DTC is only possible when the SIMR2.IICINTM bit is 1 (use reception and transmission interrupts).
29.11 Event Linking
By using interrupt request signals as event signals, the SCI can provide linked operation through the Event Link
Controller (ELC) for modules selected in advance.
Event signals can be output regardless of the values of the associated interrupt request enable bits.
(1)
Error event output (receive error or error signal detected)
Indicates abnormal termination because of a parity error during reception in asynchronous mode
Indicates abnormal termination because of a framing error during reception in asynchronous mode
Indicates abnormal termination because of an overrun error during reception
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29. Serial Communications Interface (SCI)
Indicates detection of the error signal during transmission in smart card interface mode
Indicates that when the SSR_FIFO.FER and PER flags are 0, and receive data less than the receive FIFO data
trigger number is in the receive FIFO buffer, 15 ETUs elapse when FIFO is selected and FCR.DRES is 1.
(2)
Receive data full event output
Indicates that ACK is detected if the IICINTM bit in SIMR2 register is 0 in simple IIC mode
Indicates that the 8th-bit SCLn falling edge is detected if the IICINTM bit in SIMR2 register is 1 in simple IIC mode
When the IICINTM bit in SIMR2 register bit is 1 during master transmission in simple IIC mode, set the ELC so
that receive data full events are not used.
(a)
Non-FIFO selected
Indicates that received data is in the Receive Data Register (RDR or RDRHL).
(b)
FIFO selected
Using this event output is prohibited.
(3)
Transmit data empty event output
Indicates that the SCR/SCR_SMCI.TE bit changed from 0 to 1
Indicates that transmission is complete in smart card interface mode
Indicates that NACK is detected if the IICINTM bit in SIMR2 register is 0 in simple IIC mode
Indicates that the 9th-bit SCLn falling edge is detected if the IICINTM bit in SIMR2 register is 1 in simple IIC
mode.
(a)
Non-FIFO selected
Indicates that transmit data is transferred from the Transmit Data Register (TDR or TDRHL) to the Transmit Shift
Register (TSR).
(b)
(4)
FIFO selected
Using this event output is prohibited.
Transmit end event output
Indicates the completion of transmission
Indicates that the starting condition, restart condition, or stop condition is generated in simple IIC mode.
Note:
(5)
When FIFO is selected, using this event output is prohibited.
Address match event output
Indicates a match of the comparison data (CDR.CMPD) with one frame of receive data when DCCR.DCME is set
to 1 in asynchronous mode, including multi-processor mode.
29.12 Address Mismatch Event Output (SCI0_DCUF)
SCI0_DCUF indicates the mismatch of comparison data (CDR.CMPD) with receive data, that is one frame of data that is
received when DCCR.DCME is set to 1 in asynchronous mode, including multi-processor mode. This event can be used
for Snooze end request only.
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29. Serial Communications Interface (SCI)
29.13 Noise Cancellation Function
Figure 29.72 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of a 2-stage
flip-flop circuit and a match detection circuit. When the input signals of the noise filter and the output signals of the 2stage flip-flop circuits completely match, the matched level is conveyed as an internal signal. Unless a match occurs, the
previous value is retained. When the same level is retained for 3 cycles or longer on the sampling clock of the noise filter,
it is considered as a valid receive signal. A change in pulse for 3 cycles or shorter is considered as noise, not as a receive
signal.
When SEMR.ABCS = 0 and SEMR.ABCSE = 0, the cycle is 1/16 the period of 1 transfer bit.
When SEMR.ABCS = 1 and SEMR.ABCSE = 0, the cycle is 1/8 the period of 1 transfer bit.
When SEMR.ABCSE = 1, the cycle is 1/6 the period of 1 transfer bit.
In asynchronous mode, the noise cancellation function can be applied to the receive signal input on the RXDn pin. The
receive level of RXDn is sampled in the flip-flop circuit of the noise filter on the base clock of the asynchronous mode.
In simple IIC mode, this function can be used for each input on SDAn and SCLn. The sampling clock for the noise
cancellation function is selected in the SNFR.NFCS bit by dividing the baud rate generator source clock by 1, 2, 4, or 8.
If the base clock is stopped with the noise filter enabled and then the base clock input is restarted again, the noise filter
operation resumes from the state where the clock was stopped. When TE and RE in SCR are set to 0 during base clock
input, all of the noise filter flip-flop values are initialized to 1. Accordingly, if the input data is 1 when reception
operation resumes, the function determines that a level match is detected and the result is conveyed as an internal signal.
When the level being input corresponds to 0, the initial output of the noise filter is retained until the level matches in 3
consecutive sampling cycles.
TXDn/SDAn,
RXDn/SCLn
internal signal
Mismatch
Match
cmp
TXDn/SDAn,
RXDn/SCLn
inputs
Baud rate generator
clock source
Base clock of
asynchronous mode
D
1 div
2 div
4 div
8 div
Q
CLK
D
Q
CLK
Q
CLK
NFCS[2:0] bits
Figure 29.72
D
NFEN bit
Digital noise filter circuit block diagram
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29. Serial Communications Interface (SCI)
29.14 Usage Notes
29.14.1
Settings for the Module-Stop Function
The Module Stop Control Register B (MSTPCRB) can enable or disable SCI operation. The SCI is initially stopped after
reset. Releasing the module-stop state enables access to the registers. For details, see section 11, Low Power Modes.
29.14.2
(1)
SCI Operations during Low Power State
Transmission
When setting the module to the stopped state or in transition to Software Standby mode, stop operation (by setting the
TIE, TE, and TEIE bits in the SCR/SCR_SMCI to 0) after switching the TXDn pin to the general I/O port pin function.
When setting the I/O port as an SCI function, the SPTR register can control the state of the TXDn pin. Setting the TE bit
to 0 initializes TSR. The TEND bit in the SSR/SSR_SMCI is initialized to 1 with non-FIFO selected. The value is saved
with FIFO selected. Depending on the port settings and the SPTR register settings, output pins might output the level
before a transition to the low power state is made after release from the module-stopped state or Software Standby mode.
When transitions to these states are made during transmission, the transmitted data becomes indeterminate.
To transmit data in the same transmission mode after cancellation of the low power state:
1. Set the TE bit to 1.
2. Read SSR/SSR_FIFO/SSR_SMCI.
3. Write data to TDR sequentially to start data transmission.
To transmit data with a different transmission mode, initialize the SCI first.
Figure 29.73 shows an example flow of transition to Software Standby mode during transmission. Figure 29.74 and
Figure 29.75 show the port pin states during transition to Software Standby mode.
Before specifying the module-stop state or making a transition to Software Standby mode from the transmission mode
using DTC transfer, stop the transmit operations (TE = 0). To start transmission after cancellation using the DTC, set the
TE bit to 1. The SCIn_TXI interrupt flag is set to 1 and transmission starts using the DTC.
(2)
Reception
(a)
When address match function is not used as a wakeup condition
Before specifying the module-stop state or making a transition to Software Standby mode, stop the receive operations
(RE = 0 in SCR/SCR_SMCI). If transition is made during data reception, the received data is invalid.
Figure 29.76 shows an example flow of transition to Software Standby mode during reception.
(b)
When address match function is used as a wakeup condition
Before specifying the module-stop state or making a transition to Software Standby mode:
1. Set the operations after cancellation of the low power state.
2.
Set CDR.CMPD and DCCR.DCME = 1.
3. Set the receive operations (RE = 1 in SCR/SCR_SMCI).
4. Set the module-stop state or Software Standby mode.
When the SCI transfers to the low power mode, if the receive data pin (RXDn) is at the low level, set the RXDESEL bit
in SEMR to 0. If RXDESEL is set to 1, there is a possibility that a start bit (falling edge of RXDn pin) cannot be detected
on release of the low power mode.
Figure 29.77 shows an example flow of transition to Software Standby mode during reception with address match.
(c)
When using SCI0 in Snooze mode
When using SCI0 in Snooze mode, some restrictions, including the maximum bit rates, exist. For details, see section 11,
Low Power Modes.
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29. Serial Communications Interface (SCI)
Start of transmission
All data transmitted?
No
[1]
Data being transmitted is lost. Data can be normally
transmitted from the CPU by setting the TE bit in
SCR/SCR_SMCI to 1, reading SSR/SSR_FIFO/
SSR_SMCI, and writing in Software Standby mode.
However, it the DMAC or DTC is activated, the data
remaining in the DMAC or DTC is transmitted when
both the TE and TIE bits in SCR/SCR_SMCI are set
to 1.
[2]
Set the I/O port function and SPTR register settings
to switch the TXDn pin to operate as a general I/O
port.
[3]
Set SCR/SCR_SMCI.TE to 0. If SCR/
SCR_SMCI.TIE = 1 and SCR/SCR_SMCI.TEIE = 1,
these are set to 0 simultaneously with the SCR.TE
bit.
[4]
This includes the setting for the module-stop state.
[1]
Yes
Read TEND flag in SSR/SSR_FIFO/SSR_SMCI
SSR/SSR_FIFO/
SSR_SMCI.TEND = 1?
No
Yes
[2]
Set the I/O port function and the SPTR register
[3]
SCR/SCR_SMCI.TE bit = 0
Transition to Software Standby mode
[4]
Cancel Software Standby mode
Change operating mode?
Yes
No
Set the I/O port function
Initialization
SCR/SCR_SMCI.TE bit = 1
Start data transmission
Figure 29.73
Example flow of transition to Software Standby mode during transmission
Transition to
Software Standby
mode
Software Standby
mode canceled
PmnPFS.PMR bit setting
(TXDn pin function setting)
SPTR.SPB2IO bit
SCR/SCR_SMCI.TE bit
The level at transition to
software standby mode
is retained
SCKn output pin
TXDn output pin
Port input/output
Port
The TXDn output pin state
(low or high) after
PmnPFS.PMR bit is set, can
be set in the SPTR register
Figure 29.74
The level before
transition to software
standby mode is output
Stop
High output
SCI TXDn output
The TXDn pin status when
being TE = 0, can be
controlled by the SPTR
register
SPTR.SPB2DT bit set value
Port pin states during transition to Software Standby mode with internal clock and asynchronous
transmission
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29. Serial Communications Interface (SCI)
Transition to Software
Standby mode
Software Standby
mode canceled
PmnPFS.PMR bit setting
SCR/SCR_SMCI.TE bit
SCKn output pin
TXDn output pin
Port input/output
Last TXD bit retained
Marking output
SCI TXDn output
Port
Figure 29.75
Port input/output
The level before transition to Software
Standby mode is output
Port
SCI TXDn output
Port pin states during transition to Software Standby mode with internal clock and clock
synchronous transmission
Data reception
SCIn_RXI interrupt?
No
[1]
[ 1 ] Received data is invalid.
Yes
Read receive data in RDR
SCR/SCR_SMCI.RE = 0
Transition to Software Standby mode
[2]
[ 2 ] Setting for the module stop state is included.
Cancel Software Standby mode
Change operating mode?
No
Yes
Initialization
SCR/SCR_SMCI.RE = 1
Start data reception
Figure 29.76
Example flow of transition to Software Standby mode during reception
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29. Serial Communications Interface (SCI)
Data reception
SCIn_RXI interrupt?
No
[1]
[ 1 ] Received data is invalid.
Yes
Read receive data in RDR
SCR/SCR_SMCI.RE = 0
Set the operation mode to cancel software
standby
Set compare data to CDR
DCCR.DCME = 1
SCR/SCR_SMCI.RE = 1
[2]
Transition to Software Standby mode
[ 2 ] Setting for the module-stop state is included.
Cancel Software Standby mode
Change operating mode?
No
Yes
Initialization
Start/continue data reception
Figure 29.77
Example flow of transition to Software Standby mode during reception with address match
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29.14.3
(1)
29. Serial Communications Interface (SCI)
Break Detection and Processing
Non-FIFO selected
When a framing error is detected, a break can be detected by reading the RXDn pin value directly. In a break, the input
from the RXDn pin becomes all 0s, and the FER flag in SSR is set to 1 to indicate a framing error. The PER flag in SSR
might also be set to 1 to indicate a parity error. The SCI continues the receive operation even after a break is received.
Therefore, even if the FER flag is set to 0, indicating a no framing error, it is set to 1 again. When the RXDESEL bit in
SEMR is 1, the SCI sets the FER flag in SSR to 1 and stops receiving operations until a start bit of the next data frame is
detected. If the FER flag in SSR is 0, the FER flag in SSR retains 0 during the break.
When the RXDn pin is set to 1 and the break ends, detecting the beginning of the start bit at the first falling edge of the
RXDn pin allows the SCI to start the receiving operation.
(2)
FIFO selected
After a framing error is detected and when the SCI detects that continuous receive data is 0 for 1 frame, reception stops.
When a framing error is detected, a break can be detected by reading the RXDMON bit value in SPTR. After the RXD
signal is in the mark state and the break is finished, reception of data to FRDRHL resumes.
29.14.4
Mark State and Production of Breaks
When the TE bit is 0 in SCR/SCR_SMCI, disabling serial transmission, the state of the TXDn pin can be set using the
SPB2IO bit in SPTR and the SPB2DT bit in SPTR. With this approach, a TXDn pin can be placed in the mark state to
transmit a break.
Before setting the TE bit in SCR/SCR_SMCI to 1, enabling serial transmission, set the SPB2IO and SPB2DT bits to put
a communication line in the mark state (the state of 1), and change the TxDn pin using I/O port function. To output a
break on data transmission, after setting the TXDn pin to output 0 by setting the SPB2IO and SPB2DT bits, change the
TXDn pin using the I/O port function and set the TE bit in SCR/SCR_SMCI to 0. When the TE bit in SCR/SCR_SMCI
is set to 0, the transmitter is initialized regardless of the current state of transmission.
29.14.5
Receive Error Flags and Transmit Operation in Clock Synchronous Mode and
Simple SPI Mode
Transmission cannot start when a receive error flag (ORER) in SSR/SSR_FIFO is set to 1, even if data is written to the
TDR or FTDRL*1 registers. Be sure to set the receive error flags to 0 before starting transmission.
Note:
The receive error flags cannot be set to 0 if serial reception is disabled by setting the RE bit in SCR/SCR_SMCI
to 0.
Note 1. Do not use the FTDRH register in simple SPI mode.
29.14.6
Restrictions on Clock Synchronous Transmission in Clock Synchronous Mode
and Simple SPI Mode
When the external clock source is used as a synchronization clock, the following restrictions apply.
(1)
Start of transmission
Wait at least the following time from writing transmit data to TDR to the start of the external clock input:
1 PCLK cycle + data output delay time for the slave + setup time for the master (tSU). See Figure 29.78.
(2)
Continuous transmission
Write the next transmit data to TDR or TDRHL before the falling edge of the transmit clock for bit [7]. See Figure 29.78.
When updating TDR after bit [7] starts to transmit, update TDR while the synchronization clock is in the low-level
period, and set the high-level width of the transmit clock (bit [7]) to 4 PCLK cycles or longer. See Figure 29.78.
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29. Serial Communications Interface (SCI)
Set t 1 PCLK cycle + data output delay time for the slave (tDO) + setup time for the master (tSU)
before transmission is started when the external clock is used
Update TDR before bit [7] is started to transmit when continuous
transmission is performed on the external clock
Synchronous clock
(external clock)
t
Next frame of data
First frame of data
TDR
SCIn_TXI interrupt flag
(IELSRn.IR*1)
D0
Serial transmit data
D2
D1
D3
D4
D5
D6
D7
D0
D1
(1) Start of transmission and (2) Continuous transmission (a)
Set t 4 cycles of the PCLK if TDR is updated after bit [7] is started to transmit when continuous transmission is
performed on the external clock
t
Synchronous clock
(external clock)
Next frame of data
Previous frame of data
TDR
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Serial transmit data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
(2) Continuous transmission (b)
Note 1.
Figure 29.78
29.14.7
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Restrictions on the use of external clock in clock synchronous transmission
Restrictions on Using DMAC or DTC
During transmission or reception operations using the DMAC or DTC, do not set the transfer information for the DMAC
or DTC.
(1)
Writing data to TDR (FTDRHL)
(a)
Non-FIFO selected
Data can be written to TDR and TDRHL. However, if new data is written to TDR or TDRHL when transmit data remains
in TDR or TDRHL, the previous data in TDR and TDRHL is lost because it was not transferred to TSR yet. When using
DMAC or DTC, be sure to write transmit data to TDR or TDRHL in the SCIn_TXI interrupt request handling routine.
(b)
FIFO selected
It is possible to write data to the FTDRH and FTDRL registers when the TE bit is 1 in SCR register. Confirm the amount
of writable data using the FDR.T[4:0] bits.
(2)
Reading data from RDR (FRDRHL)
When using the DMAC or DTC to read RDR and RDRHL, be sure to set the receive data full interrupt (SCIn_RXI) as
the activation source of the relevant SCI channel.
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29.14.8
29. Serial Communications Interface (SCI)
Notes on Starting Transfer
When transfer starts after the Interrupt Status flag (IELSRn.IR flag) in the ICU is 1, follow the procedure in this section
to clear interrupt requests before permitting operations (by setting the SCR/SCR_SMCI.TE or SCR/SCR_SMCI.RE bit
to 1). For details on the interrupt status flag, see section 14, Interrupt Controller Unit (ICU).
1. Confirm that the transfer stopped (the SCR/SCR_SMCI.TE or SCR/SCR_SMCI.RE bit is 0).
2. Set the associated interrupt enable bit (SCR/SCR_SMCI.TIE or SCR/SCR_SMCI.RIE) to 0.
3. Read the associated interrupt enable bit (SCR/SCR_SMCI.TIE or SCR/SCR_SMCI.RIE bit) to check that it actually
becomes 0.
4. Set the Interrupt Status flag (IELSRn.IR flag) in the ICU to 0.
29.14.9
External Clock Input in Clock Synchronous Mode and Simple SPI Mode
In clock synchronous mode and simple SPI mode, the external clock (SCKn) must be input as follows:
High-pulse period, low-pulse period = 2 PCLK cycles or more, period = 6 PCLK cycles or more.
29.14.10
(1)
Limitations to Simple SPI Mode
Master mode
Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set by the
CKPH and CKPOL bits when the SSE bit is 1 in the SPMR register. This prevents the clock line from being placed
in the high-impedance state when the TE bit is set to 0 or unexpected edges from being generated on the clock line
when the TE bit is changed from 0 to 1 in the SCR register. When the SSE bit is 0 in single-master mode, pulling up
or pulling down the clock line is not required because the clock line is not placed in the high-impedance state even
when the TE bit is set to 0.
For the clock delay setting (SPMR.CKPH bit is 1), the receive data full interrupt (SCIn_RXI) is generated before
the final clock edge on the SCKn pin, as indicated in Figure 29.79. If the TE and RE bits in the SCR become 0
before the final edge of the clock signal on the SCKn pin, the SCKn pin is placed in the high-impedance state, so the
width of the last clock pulse of the transfer clock is shortened. Additionally, an SCIn_RXI interrupt might lead to
the input signal on the SSn pin of a connected slave going to the high level before the final edge of the clock signal
on the SCKn pin, leading to incorrect operation of the slave.
In a multi-master configuration, the SCKn pin output goes to high-impedance while the input on the SSn pin is at
the low level if a mode fault error occurs while the current character is being transferred, stopping supply of the
clock signal to the connected slave. Reset the connected slave to avoid misaligned bits when transfer is restarted.
SCKn
(CKPOL = 0)
SCKn
(CKPOL = 1)
RXDn
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
SCIn_RXI interrupt
source
Figure 29.79
Timing of SCIn_RXI interrupt in simple SPI mode with clock delay
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(2)
29. Serial Communications Interface (SCI)
Slave mode
Wait at least the following time from writing transmit data in the TDR register to the start of the external clock
input:
1 PCLK cycle + data output delay time for the slave (tDO) + setup time for the master (tSU).
Also, wait at least 5 PCLK cycles from the input of the low level on the SSn pin to the start of the external clock
input.
Provide an external clock signal to the master for the data length for transfer
Control the input on the SSn pin before the start and after the end of data transfer
When the input level on the SSn pin changes from low to high while a character is being transferred, set the TE and
RE bits in SCR to 0 and, after restoring the settings, restart transfer of the first byte.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.
I2C Bus Interface (IIC)
30.1
Overview
The MCU has a 3-channel I2C Bus Interface (IIC) module that conforms with and provides a subset of the NXP I2C bus
(Inter-Integrated Circuit bus) interface functions. Table 30.1 lists the IIC specifications, Figure 30.1 shows a block
diagram, and Figure 30.2 shows an example of I/O pin connections to external circuits, with an I2C bus configuration
example. Table 30.2 lists the I/O pins.
Table 30.1
IIC specifications (1 of 2)
Parameter
Description
Communications format
Transfer rate
Fast-mode supported, up to 400 kbps
SCL clock
For master operation, the duty cycle of the SCL clock is selectable in the range from 4% to 96%
Issuing and detecting
conditions
Start, restart, and stop conditions are automatically generated
Start conditions, including restart conditions, and stop conditions are detectable.
Slave address
Configurable for up to three different slave addresses
7-bit and 10-bit address formats supported, including simultaneous use
General call addresses, device ID addresses, and SMBus host addresses detectable.
Acknowledgment
For transmission, automatic loading of the acknowledge bit.
Transfer of the next transmit data can be automatically suspended on detection of a not-acknowledge
bit.
For reception, automatic transmission of the acknowledge bit.
If a wait between the 8th and 9th clock cycles is selected, software can control the value in the
acknowledge field in response to the received value.
Wait function
During reception, the following wait periods are available by holding the SCL clock low:
Waiting between the 8th and 9th clock cycles
Waiting between the 9th clock cycle and the 1st clock cycle of the next transfer.
SDA output delay function
Output timing of transmitted data, including the acknowledge bit, can be delayed
Arbitration
For multi-master operation:
- SCL clock synchronization is possible when conflict occurs with the SCL signal from another master
- When issuing the start condition creates conflict on the bus, loss of arbitration is detected by testing for
a mismatch between the internal signal for the SDA line and the level on the SDA line
- In master operation, loss of arbitration is detected by testing for a mismatch between the signal on the
SDA line and the internal signal for the SDA line.
Loss of arbitration because the start condition occurs while the bus is busy is detectable, to prevent the
issuing of double start conditions
Loss of arbitration is detectable on transfer of a not-acknowledge bit because the internal signal for the
SDA line and the level on the SDA line do not match
Loss of arbitration because a mismatch of internal and line levels for data is detectable in slave
transmission.
Timeout function
Internal detection of long-interval stops of the SCL clock
Noise cancellation
Digital noise filters for both the SCL and SDA signals
Programmable window for noise cancellation by the filters.
Interrupt sources
Transfer error or occurrence of events: arbitration detection, NACK, timeout, start or restart condition, or
stop condition
Receive data full, including matching with a slave address
Transmit data empty, including matching with a slave address
Transmit end.
Module-stop function
Module-stop state can be set to reduce power consumption
IIC operating modes
I2C bus format or SMBus format
Master or slave mode selectable
Automatic securing of the setup times, hold times, and bus-free times for the transfer rate.
Master transmit
Master receive
Slave transmit
Slave receive.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Table 30.1
IIC specifications (2 of 2)
Parameter
Description
Event link function (output)
Transfer error or occurrence of events: arbitration detection, NACK, timeout, start or restart condition, or
stop condition
Receive data full, including matching with a slave address
Transmit data empty, including matching with a slave address
Transmit end.
Wakeup function*1
CPU can return from Software Standby mode using a wakeup event
Note 1.
This function is only supported for IIC channel, IIC0.
PCLKB
PS
CKS[2:0]
ICMR1
BC[2:0]
IIC (PCLKB/1 to PCLKB/128)
Output
control
SCLn
ICBRH
Transfer clock
generator
CLO
Noise
canceller
ICBRL
SCLE
SCLI
ICCR1
SCLn, SDAn
NF[1:0]
NFE
Transmission/
reception control
circuit
PS
IICRST
SDAI
ST, RS, SP
DLCS
ICCR2
BBSY, MST, TRS
WAIT, RDRFS
ICFER
SDA output delay control
SDDL[2:0]
ICMR2
ICMR3
ACKBT
ACKBR
ACK output circuit
ICDRT
NACKE
Output
control
SDAn
ICDRS
NACK decision/ACK
reception circuit
SARL1
SARU2
SARL2
ICDRR
Arbitration decision
circuit
NFE
SARL0
SARU1
Address comparator
Noise
canceller
NF[1:0]
SARU0
Internal data bus
IIC, IIC/2
ICSR1
MALE, NALE, SALE
ICSER
Bus state decision
circuit
NACKF
TMOE
ICSR2
TMOS, TMOH, TMOL
Timeout circuit
TMOF
ICIER
Event output
Interrupt generator
Figure 30.1
Interrupt request
(IICn_TXI, IICn_TEI, IICn_RXI,
IICn_EEI, IIC0_WUI)
IIC block diagram
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Power supply for pull-up
SCLin
SCL
SCL
SDA
SDA
SCLout#
SDAin
SCLout#
SCLout#
SDAin
SDAin
SDAout#
SDAout#
SDA
SCLin
(Slave 1)
Figure 30.2
SCL
SCLin
SDA
(Master)
SCL
SDAout#
(Slave 2)
I/O pin connection to the external circuit (I2C bus configuration example)
The input level of the signals for IIC is CMOS when I2C bus is selected (ICMR3.SMBS = 0), or TTL when SMBus is
selected (ICMR3.SMBS = 1).
Table 30.2
Channel
IIC0
IIC1
IIC2
IIC I/O pins
Pin name
I/O
Function
SCL0
I/O
IIC0 serial clock I/O pin
SDA0
I/O
IIC0 serial data I/O pin
SCL1
I/O
IIC1 serial clock I/O pin
SDA1
I/O
IIC1 serial data I/O pin
SCL2
I/O
IIC2 serial clock I/O pin
SDA2
I/O
IIC2 serial data I/O pin
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.2
Register Descriptions
I2C Bus Control Register 1 (ICCR1)
30.2.1
Address(es): IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h, IIC2.ICCR1 4005 3200h
b7
b6
b5
ICE
IICRST
CLO
0
0
0
Value after reset:
b4
b3
SOWP SCLO
1
b2
b1
b0
SDAO
SCLI
SDAI
1
1
1
1
Bit
Symbol
Bit name
Description
R/W
b0
SDAI
SDA Line Monitor
0: SDAn line is low
1: SDAn line is high.
R
b1
SCLI
SCL Line Monitor
0: SCLn line is low
1: SCLn line is high.
R
b2
SDAO
SDA Output Control/Monitor
Read:
0: IIC drives the SDAn pin low
1: IIC releases the SDAn pin.
Write:
0: IIC drives SDAn pin low
1: IIC releases SDAn pin.
R/W
b3
SCLO
SCL Output Control/Monitor
Read:
0: IIC drives the SCLn pin low
1: IIC releases the SCLn pin.
Write:
0: IIC drives SCLn pin low
1: IIC releases SCLn pin.
Use an external pull-up resistor to drive the signal high.
R/W
b4
SOWP
SCLO/SDAO Write Protect
0: Write enable SCLO and SDAO bits
1: Write protect SCLO and SDAO bits.
This bit is read as 1.
R/W
b5
CLO
Extra SCL Clock Cycle Output
0: Do not output extra SCL clock cycle (default)
1: Output extra SCL clock cycle.
This bit clears automatically after 1 clock cycle is output.
R/W
b6
IICRST
IIC Bus Interface Internal Reset 0: Release IIC reset or internal reset
1: Initiate IIC reset or internal reset.
This setting clears the bit counter and the SCLn/SDAn output latch.
R/W
b7
ICE
IIC Bus Interface Enable
R/W
0: Disable (SCLn and SDAn pins in inactive state)
1: Enable (SCLn and SDAn pins in active state).
Used in combination with the IICRST bit to select either IIC or
internal reset.
SDAO bit (SDA Output Control/Monitor) and SCLO bit (SCL Output Control/Monitor)
The SDAO and SCLO bits directly control the SDAn and SCLn signals output from the IIC.
When writing to these bits, also write 0 to the SOWP bit. Setting these bits results in input to the IIC by the input buffer.
When slave mode is selected, a start condition might be detected and the bus might be released, depending on the bit
settings.
Do not rewrite these bits during a start condition, stop condition, restart condition, or during transmission, or reception.
Operation after rewriting under the specified conditions is not guaranteed. When reading these bits, the state of signals
output from the IIC can be read.
CLO bit (Extra SCL Clock Cycle Output)
The CLO bit allows the output of an extra SCL clock cycle for debugging or error processing.
Normally, set this bit to 0. Setting this bit to 1 in a normal communication state causes a communication error. For details
on this function, see section 30.12.2, Extra SCL Clock Cycle Output Function.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
IICRST bit (IIC Bus Interface Internal Reset)
The IICRST bit initiates an internal state reset of the IIC.
Setting this bit to 1 initiates an IIC reset or internal reset. Whether an IIC reset or internal reset is initiated is determined
by setting this bit in combination with the ICE bit. Table 30.3 lists the IIC resets.
The IIC reset initializes all registers except ICCR1.ICE and ICCR1.ICCRST bits and internal states of the IIC.
In addition to the internal states of the IIC, the internal reset initializes the following:
Bit counter (ICMR1.BC[2:0] bits)
I2C Bus Shift Register (ICDRS)
I2C Bus Status Registers (ICSR1 and ICSR2)
SDAO and SCLO Output Control/Monitor (ICCR1.SCLO and ICCR1.SDAO bits)
I2C Bus Control Register 2 (except ICCR2.BBSY bit).
For the reset conditions of each register, see section 30.15, Register States When Issuing Each Condition.
An internal reset initiated with the IICRST bit set to 1 during operation (with the ICE bit set to 1) resets the internal states
of the IIC without initializing the port settings and the control and setting registers of the IIC. If the IIC hangs in a lowlevel output state, resetting the internal states cancels the low-level output state and releases the bus with the SCLn pin
and SDAn pin at high impedance.
Note:
If an internal reset is initiated using the IICRST bit for a bus hang-up that occurs during communication with the
master device in slave mode, the slave device and the master device might enter different states, because the bit
counter information differs. For this reason, do not initiate an internal reset in slave mode. Initiate recovery
processing from the master device. If an internal reset is required because the IIC hangs with the SCLn line in a
low-level output state in slave mode, initiate an internal reset, and then issue a restart condition from the master
device or issue a stop condition and resume communication from the start condition. If communication is
restarted by initiating a reset solely in the slave device without issuing a start condition or restart condition from
the master device, synchronization is lost because the master and slave devices operate asynchronously.
Table 30.3
IIC resets
IICRST
ICE
State
Specifications
1
0
IIC reset
Resets all registers except ICCR1.ICE and ICCR1.ICCRST bits and internal states of the IIC
1
Internal reset
Resets the following:
ICMR1.BC[2:0] bits
ICSR1, ICSR2, and ICDRS registers
ICCR1.SCLO and ICCR1.SDAO bits
ICCR2 register (except ICCR2.BBSY bit)
Internal states of the IIC.
ICE bit (IIC Bus Interface Enable)
The ICE bit selects the active or inactive state of the SCLn and SDAn pins. It can also be combined with the IICRST bit
to initiate one of two types of resets. See Table 30.3 for the reset types.
Set the ICE bit to 1 when using the IIC. The SCLn and SDAn pins are placed in the active state when the ICE bit is set to
1. Set the ICE bit to 0 when the IIC is not used. The SCLn and SDAn pins are placed in the inactive state when the ICE
bit is set to 0. Do not assign the SCLn or SDAn pin to the IIC when setting up the pin function control. Slave address
comparison is performed if the pins are assigned to the IIC.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
I2C Bus Control Register 2 (ICCR2)
30.2.2
Address(es): IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h, IIC2.ICCR2 4005 3201h
b7
b6
b5
b4
b3
b2
b1
b0
BBSY
MST
TRS
—
SP
RS
ST
—
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b1
ST
Start Condition Issuance
Request
0: Do not issue a start condition request
1: Issue a start condition request.
R/W
b2
RS
Restart Condition Issuance
Request
0: Do not issue a restart condition request
1: Issue a restart condition request.
R/W
b3
SP
Stop Condition Issuance
Request
0: Do not issue a stop condition request
1: Issue a stop condition request.
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
TRS
Transmit/Receive Mode
0: Receive mode
1: Transmit mode.
R/W*1
b6
MST
Master/Slave Mode
0: Slave mode
1: Master mode.
R/W*1
b7
BBSY
Bus Busy Detection Flag
0: I2C bus released (bus free state)
1: I2C bus occupied (bus busy state).
R
Note 1.
The MST and TRS bits can be written to when the ICMR1.MTWP bit is set to 1.
ST bit (Start Condition Issuance Request)
The ST bit requests transition to master mode and issues a start condition.
When this bit is set to 1, a start condition is issued when the BBSY flag is set to 0 (bus free state). For details on issuing
a start condition, see section 30.11, Start, Restart, and Stop Condition Issuing Function.
[Setting condition]
When 1 is written to the ST bit.
[Clearing conditions]
When 0 is written to the ST bit
When a start condition is issued (a start condition is detected)
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
Note:
Set the ST bit to 1 (start condition request) when the BBSY flag is set to 0 (bus free state). Arbitration might be
lost if the ST bit is set to 1 (start condition request) when the BBSY flag is 1 (bus busy state).
RS bit (Restart Condition Issuance Request)
The RS bit requests that a restart condition be issued in master mode.
When this bit is set to 1 to request a restart condition, a restart condition is issued when the BBSY flag is set to 1 (bus
busy state) and the MST bit is set to 1 (master mode). For details on issuing a restart condition, see section 30.11, Start,
Restart, and Stop Condition Issuing Function.
[Setting condition]
When 1 is written to the RS bit with the BBSY flag in ICCR2 set to 1.
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30. I2C Bus Interface (IIC)
[Clearing conditions]
When 0 is written to the RS bit
When a restart condition is issued (a start condition is detected)
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
Note:
Note:
Do not set the RS bit to 1 while issuing a stop condition.
If 1 (restart condition request) is written to the RS bit in slave mode, the restart condition is not issued but the RS
bit remains set to 1. If the operating mode changes to master mode without the RS bit being cleared, the restart
condition might be issued.
SP bit (Stop Condition Issuance Request)
The SP bit requests that a stop condition be issued in master mode.
When this bit is set to 1, a stop condition is issued when the BBSY flag is set to 1 (bus busy state) and the MST bit is set
to 1 (master mode). For details on issuing a stop condition, see section 30.11, Start, Restart, and Stop Condition Issuing
Function.
[Setting condition]
When 1 is written to the SP bit with both the BBSY flag and the MST bit in ICCR2 set to 1.
[Clearing conditions]
When 0 is written to the SP bit
When a stop condition is issued (a stop condition is detected)
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When a start condition and a restart condition are detected
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
Note:
Note:
Writing to the SP bit is not possible while the BBSY flag is 0 (bus free state).
Do not set the SP bit to 1 while a restart condition is being issued.
TRS bit (Transmit/Receive Mode)
The TRS bit indicates transmit or receive mode.
The IIC is in receive mode when the TRS bit is set to 0 and in transmit mode when the TRS bit is set to 1. The
combination of the TRS bit and the MST bit indicates the operating mode of the IIC.
The value of the TRS bit automatically changes to 1 for transmit mode or 0 for receive mode when a start condition is
issued or detected and the R/W# bit is set. Although writing to the TRS bit is possible when the MTWP bit in ICMR1 is
set to 1, writing to the TRS bit is not required during normal usage.
[Setting conditions]
When a start condition is issued normally because of a start condition request (when a start condition is detected
with the ST bit set to 1)
When a restart condition is issued normally because of a restart condition request (when a restart condition is
detected with the RS bit set to 1)
When the R/W# bit appended to the slave address is set to 0 in master mode
When the address received in slave mode matches the address enabled in ICSER, with the R/W# bit set to 1
When 1 is written to the TRS bit with the MTWP bit in ICMR1 set to 1.
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30. I2C Bus Interface (IIC)
[Clearing conditions]
When a stop condition is detected
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When the R/W# bit appended to the slave address is set to 1 in master mode
In slave mode, on a match between the received address and the address enabled in ICSER when the value of the
received R/W# bit is 0, including when the received address is the general call address
In slave mode, when a restart condition is detected (a start condition is detected with ICCR2.BBSY = 1 and
ICCR2.MST = 0)
When 0 is written to the TRS bit with the MTWP bit in ICMR1 set to 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
MST bit (Master/Slave Mode)
The MST bit indicates master or slave mode.
The IIC is in slave mode when the MST bit is set to 0 and is in master mode when the MST bit is set to 1. The
combination of the MST bit and the TRS bit indicates the operating mode of the IIC.
The value of the MST bit automatically changes to 1 for master mode or 0 for slave mode when a start condition is issued
or when a stop condition is issued or detected. Although writing to the MST bit is possible when the MTWP bit in
ICMR1 is set to 1, writing to the MST bit is not required during normal usage.
[Setting conditions]
When a start condition is issued normally because of a start condition request (when a start condition is detected
with the ST bit set to 1)
When 1 is written to the MST bit with the MTWP bit in ICMR1 set to 1.
[Clearing conditions]
When a stop condition is detected
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When 0 is written to the MST bit with the MTWP bit in ICMR1 set to 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
BBSY flag (Bus Busy Detection Flag)
The BBSY flag indicates whether the I2C bus is occupied (bus busy state) or released (bus free state).
This flag is set to 1 when the SDAn line changes from high to low when the SCLn line is high, assuming that a start
condition was issued.
This flag is set to 0 when the SDAn line changes from low to high with the SCLn line high, if the bus free time (ICBRL
setting) start condition is not detected, assuming that a stop condition was issued.
[Setting condition]
When a start condition is detected.
[Clearing conditions]
When the bus free time (ICBRL setting) start condition is not detected after detecting a stop condition
When 1 is written to the IICRST bit in ICCR1 with the ICE bit in ICCR1 set to 0 (IIC reset).
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
I2C Bus Mode Register 1 (ICMR1)
30.2.3
Address(es): IIC0.ICMR1 4005 3002h, IIC1.ICMR1 4005 3102h, IIC2.ICMR1 4005 3202h
b7
b6
MTWP
Value after reset:
0
b5
b4
CKS[2:0]
0
0
b3
b2
BCWP
0
1
b1
b0
BC[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
BC[2:0]
Bit Counter
b2
R/W*1
b3
BCWP
BC Write Protect
0: Write enable BC[2:0] bits
1: Write protect BC[2:0] bits.
This bit is read as 1.
R/W*1
b6 to b4
CKS[2:0]
Internal Reference Clock Select
Select the internal reference clock source (IICΦ) for the IIC.
R/W
0
0
0
0
1
1
1
1
b6
0
0
0
0
1
1
1
1
b7
Note 1.
MTWP
MST/TRS Write Protect
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: 9 bits
1: 2 bits
0: 3 bits
1: 4 bits
0: 5 bits
1: 6 bits
0: 7 bits
1: 8 bits.
b4
0: PCLKB clock
1: PCLKB/2 clock
0: PCLKB/4 clock
1: PCLKB/8 clock
0: PCLKB/16 clock
1: PCLKB/32 clock
0: PCLKB/64 clock
1: PCLKB/128 clock.
0: Write protect MST and TRS bits in ICCR2
1: Write enable MST and TRS bits in ICCR2.
R/W
Rewrite the BC[2:0] bits and set the BCWP bit to 0 at the same time.
BC[2:0] bits (Bit Counter)
The BC[2:0] bits function as a counter that indicates the number of bits remaining to be transferred on detection of a
rising edge on the SCLn line. Although the BC[2:0] bits are read/write bits, it is not required to access these bits under
normal conditions.
To write to these bits, specify the number of bits to be transferred plus one, for an additional acknowledge bit, between
transferred frames when the SCLn line is at a low level.
The value in the BC[2:0] bits returns to 000b at the end of a data transfer, including the acknowledge bit, or when a start
or restart condition is detected.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
I2C Bus Mode Register 2 (ICMR2)
30.2.4
Address(es): IIC0.ICMR2 4005 3003h, IIC1.ICMR2 4005 3103h, IIC2.ICMR2 4005 3203h
b7
b6
DLCS
Value after reset:
0
b5
b4
SDDL[2:0]
0
0
b3
—
0
0
b2
b1
b0
TMOH TMOL
1
TMOS
1
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOS
Timeout Detection Time Select
0: Select long mode
1: Select short mode.
R/W
b1
TMOL
Timeout L Count Control
0: Disable count while the SCLn line is low
1: Enable count while the SCLn line is low.
R/W
b2
TMOH
Timeout H Count Control
0: Disable count while the SCLn line is high
1: Enable count while the SCLn line is high.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6 to b4
SDDL[2:0]
SDA Output Delay Counter
When ICMR2.DLCS = 0 (IICΦ)
R/W
b6
b4
0 0 0: No output delay
0 0 1: 1 IICΦ cycle
0 1 0: 2 IICΦ cycles
0 1 1: 3 IICΦ cycles
1 0 0: 4 IICΦ cycles
1 0 1: 5 IICΦ cycles
1 1 0: 6 IICΦ cycles
1 1 1: 7 IICΦ cycles.
When ICMR2.DLCS = 1 (IICΦ/2)
b6
0
0
0
0
1
1
1
1
b7
Note 1.
DLCS
SDA Output Delay Clock Source
Select
0
0
1
1
0
0
1
1
b4
0: No output delay
1: 1 or 2 IICΦ cycles
0: 3 or 4 IICΦ cycles
1: 5 or 6 IICΦ cycles
0: 7 or 8 IICΦ cycles
1: 9 or 10 IICΦ cycles
0: 11 or 12 IICΦ cycles
1: 13 or 14 IICΦ cycles.
0: Internal reference clock (IICΦ) selected as the clock source
for the SDA output delay counter
1: Internal reference clock divided by 2 (IICΦ/2) selected as the
clock source for the SDA output delay counter.*1
R/W
The DLCS = 1 (IICΦ/2) setting is only valid when SCL is low. When SCL is high, the DLCS = 1 setting becomes invalid and the
clock source becomes the internal reference clock (IICΦ).
TMOS bit (Timeout Detection Time Select)
The TMOS bit selects long or short mode for the timeout detection time when the timeout function is enabled
(ICFER.TMOE bit = 1).
When this bit is set to 0, long mode is selected. When the TMOS bit is set to 1, short mode is selected.
In long mode, the timeout detection internal counter functions as a 16-bit counter. In short mode, the counter functions as
a 14-bit counter. While the SCLn line is in the state that enables this counter as specified in the TMOH and TMOL bits,
the counter counts up in synchronization with the internal reference clock (IICΦ) as a count source.
For details on the timeout function, see section 30.12.1, Timeout Function.
TMOL bit (Timeout L Count Control)
The TMOL bit enables or disables up-counting on the internal counter of the timeout function while the SCLn line is
held low and the timeout function is enabled (ICFER.TMOE bit = 1).
TMOH bit (Timeout H Count Control)
The TMOH bit enables or disables up-counting on the internal counter of the timeout function while the SCLn line is
held high and the timeout function is enabled (ICFER.TMOE bit = 1).
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SDDL[2:0] bits (SDA Output Delay Counter)
The SDDL[2:0] bit can be used to delay the SDA output.
This counter works with the clock source selected in the DLCS bit. This function setting can be used for all types of SDA
output, including the transmission of the acknowledge bit.
Set the SDA output delay time to meet the I2C bus standard for the data enable time/acknowledge enable time*1, or the
SMBus standard, within [data hold time (300 ns or more + the SCL clock low-level period) - the data setup time (250
ns)]. If a value outside the standard is set, communication between devices might malfunction or falsely indicate a start
or stop condition, depending on the bus state.
For details on this function, see section 30.5, SDA Output Delay Function.
Note 1. Data enable time/acknowledge enable time
3450 ns for up to 100 kbps: Standard-mode (Sm)
900 ns for up to 400 kbps: Fast-mode (Fm).
I2C Bus Mode Register 3 (ICMR3)
30.2.5
Address(es): IIC0.ICMR3 4005 3004h, IIC1.ICMR3 4005 3104h, IIC2.ICMR3 4005 3204h
b7
SMBS
Value after reset:
0
b6
b5
b4
b3
b2
b1
WAIT RDRFS ACKW ACKBT ACKBR
P
0
0
0
0
0
b0
NF[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
NF[1:0]
Noise Filter Stage Select
b1 b0
R/W
b2
ACKBR
Receive Acknowledge
0: 0 received as the acknowledge bit (ACK reception)
1: 1 received as the acknowledge bit (NACK reception).
R
b3
ACKBT
Transmit Acknowledge
0: Send 0 as the acknowledge bit (ACK transmission)
1: Send 1 as the acknowledge bit (NACK transmission).
R/W*1
b4
ACKWP
ACKBT Write Protect
0: Write protect the ACKBT bit
1: Write enable the ACKBT bit.
R/W*1
b5
RDRFS
RDRF Flag Set Timing
Select
0: Set the RDRF flag on the rising edge of the 9th SCL clock cycle.
The SCLn line is not held low on the falling edge of the 8th clock cycle.
1: Set the RDRF flag on the rising edge of the 8th SCL clock cycle.
The SCLn line is held low on the falling edge of the 8th clock cycle.
Low-hold is released by writing to ACKBT.
R/W*2
b6
WAIT
WAIT
0: No wait.
SCLn is not held low during the period between 9th clock cycle and 1st
clock cycle.
1: Wait.
SCLn is held low during the period between 9th clock cycle and 1st clock
cycle.
Low-hold is released by reading ICDRR.
R/W*2
b7
SMBS
SMBus/I2C Bus Select
0: Select I2C bus
1: Select SMBus.
R/W
Note 1.
Note 2.
0 0: Filter out noise of up to 1 IIC cycle (single-stage filter)
0 1: Filter out noise of up to 2 IIC cycles (2-stage filter)
1 0: Filter out noise of up to 3 IIC cycles (3-stage filter)
1 1: Filter out noise of up to 4 IIC cycles (4-stage filter).
Write to the ACKBT bit only when the ACKWP bit is already 1. If the application writes 1 to both the ACKWP and ACKBT bits at
the same time, the ACKBT bit is not set to 1.
The WAIT and RDRFS bits are valid only in receive mode (invalid in transmit mode).
NF[1:0] bits (Noise Filter Stage Select)
The NF[1:0] bits select the number of stages in the digital noise filter.
For details on the digital noise filter function, see section 30.6, Digital Noise Filter Circuits.
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30. I2C Bus Interface (IIC)
Set the noise range to be filtered out by the noise filter within a range less than the SCLn line high-level period or
low-level period. If the noise range is set to a value of [SCL clock width: high-level period or low-level period,
whichever is shorter] - [1.5 internal reference clock (IICΦ) cycles + analog noise filter: 120 ns (reference values)]
or more, the SCL clock is regarded as noise by the noise filter function of the IIC, which might prevent the IIC
from operating normally.
ACKBR bit (Receive Acknowledge)
The ACKBR bit stores the acknowledge bit information received from the receive device in transmit mode.
[Setting condition]
When 1 is received as the acknowledge bit with the TRS bit in ICCR2 set to 1.
[Clearing conditions]
When 0 is received as the acknowledge bit with the TRS bit in ICCR2 set to 1
When 1 is written to the IICRST bit in ICCR1 while the ICE bit in ICCR1 is 0 (IIC reset).
ACKBT bit (Transmit Acknowledge)
The ACKBT bit sets the value of the acknowledge bit to be sent in receive mode.
[Setting condition]
When 1 is written to this bit with the ACKWP bit set to 1.
[Clearing conditions]
When 0 is written to this bit with the ACKWP bit set to 1
When stop condition issuance is detected with the SP bit in ICCR2 set to 1
When 1 is written to the IICRST bit in ICCR1 while the ICE bit in ICCR1 is 0 (IIC reset).
ACKWP bit (ACKBT Write Protect)
The ACKWP bit controls write enabling of the ACKBT bit.
RDRFS bit (RDRF Flag Set Timing Select)
The RDRFS bit selects the RDRF flag set timing in receive mode and also selects whether to hold the SCLn line low on
the falling edge of the 8th SCL clock cycle.
When the RDRFS bit is 0, the SCLn line is not held low on the falling edge of the 8th SCL clock cycle, and the RDRF
flag is set to 1 on the rising edge of the 9th SCL clock cycle.
When the RDRFS bit is 1, the SCLn line is held low on the falling edge of the 8th SCL clock cycle, and the RDRF flag is
set to 1 on the rising edge of the 8th SCL clock cycle. The low-hold of the SCLn line is released by a write to the ACKBT
bit.
After data is received with this setting, the SCLn line is automatically held low before the acknowledge bit is sent. This
enables processing to send ACK (ACKBT = 0) or NACK (ACKBT = 1), based on the receive data.
WAIT bit (WAIT)
The WAIT bit controls whether to hold the period between the 9th SCL clock cycle and the 1st SCL clock cycle low until
the receive data buffer (ICDRR) is completely read each time a single-byte of data is received in receive mode.
When the WAIT bit is 0, the receive operation continues without holding the period between the 9th and the 1st SCL
clock cycle low. When both the RDRFS and WAIT bits are 0, continuous receive operation is enabled with the double
buffer.
When the WAIT bit is 1, the SCLn line is held low from the falling edge of the 9th clock cycle until the ICDRR value is
read each time a single-byte of data is received. This enables receive operation in byte units.
Note:
When the WAIT bit value is to be read, be sure to first read the ICDRR.
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S3A1 User’s Manual
SMBS bit (SMBus/I2C Bus Select)
Setting the SMBS bit to 1 selects the SMBus and enables the HOAE bit in ICSER.
I2C Bus Function Enable Register (ICFER)
30.2.6
Address(es): IIC0.ICFER 4005 3005h, IIC1.ICFER 4005 3105h, IIC2.ICFER 4005 3205h
Value after reset:
b7
b6
b5
—
SCLE
NFE
0
1
1
b4
b3
NACKE SALE
1
0
b2
b1
b0
NALE
MALE
TMOE
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOE
Timeout Function Enable
0: Timeout function disabled
1: Timeout function enabled.
R/W
b1
MALE
Master Arbitration-Lost
Detection Enable
0: Master arbitration-lost detection disabled.
Also disables automatic clearing of the MST and TRS bits in ICCR2
when arbitration is lost.
1: Master arbitration-lost detection enabled.
Also enables automatic clearing of the MST and TRS bits in ICCR2
when arbitration is lost.
R/W
b2
NALE
NACK Transmission
Arbitration-Lost Detection
Enable
0: NACK transmission arbitration-lost detection disabled
1: NACK transmission arbitration-lost detection enabled.
R/W
b3
SALE
Slave Arbitration-Lost
Detection Enable
0: Slave arbitration-lost detection disabled
1: Slave arbitration-lost detection enabled.
R/W
b4
NACKE
NACK Reception Transfer
Suspension Enable
0: Transfer operation not suspended during NACK reception (transfer
suspension disabled)
1: Transfer operation suspended during NACK reception (transfer
suspension enabled).
R/W
b5
NFE
Digital Noise Filter Circuit
Enable
0: No digital noise filter circuit used
1: A digital noise filter circuit used.
R/W
b6
SCLE
SCL Synchronous Circuit
Enable
0: No SCL synchronous circuit used
1: An SCL synchronous circuit used.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
TMOE bit (Timeout Function Enable)
The TMOE bit enables or disables the timeout function. For details on the timeout function, see section 30.12.1, Timeout
Function.
MALE bit (Master Arbitration-Lost Detection Enable)
The MALE bit specifies whether to use the arbitration-lost detection function in master mode. For normal operation, set
this bit to 1.
NALE bit (NACK Transmission Arbitration-Lost Detection Enable)
The NALE bit specifies whether to cause loss of arbitration when ACK is detected during transmission of NACK in
receive mode, for example, when slaves with the same address exist on the bus, or when two or more masters select the
same slave device simultaneously with a different number of receive bytes.
SALE bit (Slave Arbitration-Lost Detection Enable)
The SALE bit specifies whether to cause loss of arbitration when a value different from the value being transmitted is
detected on the bus in slave transmit mode, for example, when slaves with the same address exist on the bus, or when a
mismatch with the transmit data occurs because of noise.
NACKE bit (NACK Reception Transfer Suspension Enable)
The NACKE bit specifies whether to continue or discontinue the transfer operation when NACK is received from the
slave device in transmit mode. For normal operation, set this bit to 1.
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30. I2C Bus Interface (IIC)
When NACK is received with the NACKE bit set to 1, the next transfer operation is suspended. When the NACKE bit is
0, the next transfer operation continues regardless of the received acknowledge content.
For details, see section 30.9.2, NACK Reception Transfer Suspension Function.
SCLE bit (SCL Synchronous Circuit Enable)
The SCLE bit specifies whether to synchronize the SCL clock with the SCL input clock. For normal operation, set this
bit to 1.
When the SCLE bit is set to 0 (no SCL synchronous circuit used), the IIC does not synchronize the SCL clock with the
SCL input clock. With this setting, the IIC outputs the SCL clock with the transfer rate set in ICBRH and ICBRL
regardless of the SCLn line state. For this reason, if the bus load of the I2C bus line is much larger than the specification
value, or if the SCL clock output overlaps in multiple masters, a short-cycle SCL clock that does not meet the
specification might be output. When no SCL synchronous circuit is used, it also affects the issuing of the start, restart,
and stop conditions, and the continuous output of extra SCL clock cycles.
Do not set this bit to 0 except when checking the output of the set transfer rate.
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S3A1 User’s Manual
I2C Bus Status Enable Register (ICSER)
30.2.7
Address(es): IIC0.ICSER 4005 3006h, IIC1.ICSER 4005 3106h, IIC2.ICSER 4005 3206h
b7
b6
b5
b4
HOAE
—
DIDE
—
0
0
0
0
Value after reset:
b3
b2
b1
b0
GCAE SAR2E SAR1E SAR0E
1
0
0
1
Bit
Symbol
Bit name
Description
R/W
b0
SAR0E
Slave Address Register 0 Enable
0: Slave address in SARL0 and SARU0 disabled
1: Slave address in SARL0 and SARU0 enabled.
R/W
b1
SAR1E
Slave Address Register 1 Enable
0: Slave address in SARL1 and SARU1 disabled
1: Slave address in SARL1 and SARU1 enabled.
R/W
b2
SAR2E
Slave Address Register 2 Enable
0: Slave address in SARL2 and SARU2 disabled
1: Slave address in SARL2 and SARU2 enabled.
R/W
b3
GCAE
General Call Address Enable
0: General call address detection disabled
1: General call address detection enabled.
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
DIDE
Device ID Address Detection
Enable
0: Device ID address detection disabled
1: Device ID address detection enabled.
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
HOAE
Host Address Enable
0: Host address detection disabled
1: Host address detection enabled.
R/W
SARyE bit (Slave Address Register y Enable) (y = 0 to 2)
The SARyE bit enables or disables the received slave address and the slave address set in SARLy and SARUy.
When the SARyE bit is set to 1, the slave address set in SARLy and SARUy is enabled and is compared with the received
slave address. When the SARyE bit is set to 0, the slave address set in SARLy and SARUy is disabled and is ignored
even if it matches the received slave address.
GCAE bit (General Call Address Enable)
The GCAE bit specifies whether to ignore the general call address (0000 000b + 0 [W]: All 0) when it is received.
When this bit is set to 1, if the received slave address matches the general call address, the IIC recognizes the received
slave address as the general call address independently of the slave addresses set in SARLy and SARUy (y = 0 to 2) and
performs the data receive operation. When this bit is set to 0, the received slave address is ignored even if it matches the
general call address.
DIDE bit (Device ID Address Detection Enable)
The DIDE bit specifies whether to recognize and execute the device ID address when a device ID (1111 100b) is received
in the first frame after a start condition or restart condition is detected.
When the DIDE bit is set to 1, if the received first frame matches the device ID, the IIC recognizes that the device ID
address was received. When the next R/W# bit is 0 (W), the IIC recognizes the second and the subsequent frames as
slave addresses and continues the receive operation. When the DIDE bit is set to 0, the IIC ignores the received first
frame even if it matches the device ID address, and recognizes the first frame as a normal slave address.
For details on the device ID address detection, see section 30.7.3, Device ID Address Detection.
HOAE bit (Host Address Enable)
The HOAE bit specifies whether to ignore the received host address (0001 000b) when the SMBS bit in ICMR3 is 1.
When this bit is set to 1 while the SMBS bit in ICMR3 is 1, if the received slave address matches the host address, the
IIC recognizes the received slave address as the host address independently of the slave addresses set in SARLy and
SARUy (y = 0 to 2), and performs the receive operation. When the SMBS bit in ICMR3 or the HOAE bit is set to 0, the
received slave address is ignored even if it matches the host address.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
I2C Bus Interrupt Enable Register (ICIER)
30.2.8
Address(es): IIC0.ICIER 4005 3007h, IIC1.ICIER 4005 3107h, IIC2.ICIER 4005 3207h
b7
b6
b5
b4
b3
b2
b1
b0
TIE
TEIE
RIE
NAKIE
SPIE
STIE
ALIE
TMOIE
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
TMOIE
Timeout Interrupt Request Enable
0: Timeout interrupt (TMOIn) request disabled
1: Timeout interrupt (TMOIn) request enabled.
R/W
b1
ALIE
Arbitration-Lost Interrupt Request
Enable
0: Arbitration-lost interrupt (ALIn) request disabled
1: Arbitration-lost interrupt (ALIn) request enabled.
R/W
b2
STIE
Start Condition Detection Interrupt
Request Enable
0: Start condition detection interrupt (STIn) request disabled
1: Start condition detection interrupt (STIn) request enabled.
R/W
b3
SPIE
Stop Condition Detection Interrupt
Request Enable
0: Stop condition detection interrupt (SPIn) request disabled
1: Stop condition detection interrupt (SPIn) request enabled.
R/W
b4
NAKIE
NACK Reception Interrupt Request
Enable
0: NACK reception interrupt (NAKIn) request disabled
1: NACK reception interrupt (NAKIn) request enabled.
R/W
b5
RIE
Receive Data Full Interrupt Request
Enable
0: Receive data full interrupt (IICn_RXI) request disabled
1: Receive data full interrupt (IICn_RXI) request enabled.
R/W
b6
TEIE
Transmit End Interrupt Request
Enable
0: Transmit end interrupt (IICn_TEI) request disabled
1: Transmit end interrupt (IICn_TEI) request enabled.
R/W
b7
TIE
Transmit Data Empty Interrupt
Request Enable
0: Transmit data empty interrupt (IICn_TXI) request disabled
1: Transmit data empty interrupt (IICn_TXI) request enabled.
R/W
TMOIE bit (Timeout Interrupt Request Enable)
The TMOIE bit enables or disables timeout interrupt (TMOIn) requests when the TMOF flag in ICSR2 is set to 1. To
cancel a TMOI interrupt request, set the TMOF flag or the TMOIE bit to 0.
ALIE bit (Arbitration-Lost Interrupt Request Enable)
The ALIE bit enables or disables arbitration-lost interrupt (ALIn) requests when the AL flag in ICSR2 is set to 1. To
cancel an ALI interrupt request, set the AL flag or the ALIE bit to 0.
STIE bit (Start Condition Detection Interrupt Request Enable)
The STIE bit enables or disables start condition detection interrupt (STIn) requests when the START flag in ICSR2 is set
to 1. To cancel an STI interrupt request, set the START flag or the STIE bit to 0.
SPIE bit (Stop Condition Detection Interrupt Request Enable)
The SPIE bit enables or disables stop condition detection interrupt (SPIn) requests when the STOP flag in ICSR2 is set to
1. To cancel an SPI interrupt request, set the STOP flag or the SPIE bit to 0.
NAKIE bit (NACK Reception Interrupt Request Enable)
The NAKIE bit enables or disables NACK reception interrupt (NAKIn) requests when the NACKF flag in ICSR2 is set
to 1. To cancel an NAKI interrupt request, set the NACKF flag or the NAKIE bit to 0.
RIE bit (Receive Data Full Interrupt Request Enable)
The RIE bit enables or disables receive data full interrupt (IICn_RXI) requests when the RDRF flag in ICSR2 is set to 1.
TEIE bit (Transmit End Interrupt Request Enable)
The TEIE bit enables or disables transmit end interrupt (IICn_TEI) requests when the TEND flag in ICSR2 is set to 1. To
cancel an IICn_TEI interrupt request, set the TEND flag or the TEIE bit to 0.
TIE bit (Transmit Data Empty Interrupt Request Enable)
The TIE bit enables or disables transmit data empty interrupt (IICn_TXI) requests when the TDRE flag in ICSR2 is set to
1.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
I2C Bus Status Register 1 (ICSR1)
30.2.9
Address(es): IIC0.ICSR1 4005 3008h, IIC1.ICSR1 4005 3108h, IIC2.ICSR1 4005 3208h
b7
b6
b5
b4
b3
b2
b1
b0
HOA
—
DID
—
GCA
AAS2
AAS1
AAS0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
AAS0
Slave Address 0 Detection Flag
0: Slave address 0 not detected
1: Slave address 0 detected.
R/(W)
*1
b1
AAS1
Slave Address 1 Detection Flag
0: Slave address 1 not detected
1: Slave address 1 detected.
R/(W)
*1
b2
AAS2
Slave Address 2 Detection Flag
0: Slave address 2 not detected
1: Slave address 2 detected.
R/(W)
*1
b3
GCA
General Call Address Detection
Flag
0: General call address not detected
1: General call address detected.
R/(W)
*1
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
DID
Device ID Address Detection Flag
0: Device ID command not detected
1: Device ID command detected.
This bit is set to 1 when the first frame received immediately after
a start condition is detected matches a value of (device ID (1111
100b) + 0[W]).
R/(W)
*1
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
HOA
Host Address Detection Flag
0: Host address not detected
1: Host address detected.
This bit is set to 1 when the received slave address matches the
host address (0001 000b).
R/(W)
*1
Note 1.
Only 0 can be written to clear the flag.
AASy flag (Slave Address y Detection Flag) (y = 0 to 2)
The AASy flag indicates whether slave address y was detected.
[Setting conditions]
For 7-bit address format (SARUy.FS = 0):
When the received slave address matches the SVA[6:0] value in SARLy, with the SARyE bit in ICSER set to 1
(slave address y detection enabled). This flag is set to 1 on the rising edge of the 9th SCL clock cycle in the frame.
For 10-bit address format (SARUy.FS = 1):
When the received slave address matches a value of 11110b + SVA[1:0] in SARUy and the subsequent address
matches the SARLy value with the SARyE bit in ICSER set to 1 (slave address y detection enabled). This flag is set
to 1 on the rising edge of the 9th SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the AASy flag after reading AASy = 1
When a stop condition is detected
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
For 7-bit address format (SARUy.FS = 0):
When the received slave address does not match the SVA[6:0] value in SARLy, with the SARyE bit in ICSER set to
1 (slave address y detection enabled). This flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
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30. I2C Bus Interface (IIC)
For 10-bit address format (SARUy.FS = 1):
When the received slave address does not match a value of 11110b + SVA[1:0] in SARUy, with the SARyE bit in
ICSER set to 1 (slave address y detection enabled). This flag is set to 0 on the rising edge of the 9th SCL clock cycle
in the frame.
When the received slave address matches a value of 11110b + SVA[1:0] in SARUy, and the subsequent address
does not match the SARLy value with the SARyE bit in ICSER set to 1 (slave address y detection enabled). This
flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
GCA flag (General Call Address Detection Flag)
The GCA flag indicates whether the general call address was detected.
[Setting condition]
When the received slave address matches the general call address (0000 000b + 0 [W]), with the GCAE bit in
ICSER set to 1 (general call address detection is enabled). This flag is set to 1 on the rising edge of the 9th SCL
clock cycle in the frame.
[Clearing conditions]
When 0 is written to the GCA bit after reading GCA = 1
When a stop condition is detected
When the received slave address does not match the general call address (0000 000b + 0 [W]), with the GCAE bit in
ICSER set to 1 (general call address detection is enabled). This flag is set to 0 on the rising edge of the 9th SCL
clock cycle in the frame.
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
DID flag (Device ID Address Detection Flag)
The DID flag indicates whether the device ID address was detected.
[Setting condition]
When the first frame received immediately after a start or restart condition is detected matches a value of (device ID
(1111 100b) + 0 [W]), with the DIDE bit in ICSER set to 1 (device ID address detection is enabled). This flag is set
to 1 on the rising edge of the 9th SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the DID bit after reading DID = 1
When a stop condition is detected
When the first frame received immediately after a start condition or restart condition is detected does not match the
value of device ID (1111 100b), with the DIDE bit in ICSER set to 1 (device ID address detection is enabled). This
flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
When the first frame received immediately after a start condition or restart condition is detected matches a value of
(device ID (1111 100b) + 0 [W]), and the second frame does not match any slave address from 0 to 2, with the
DIDE bit in ICSER set to 1 (device ID address detection enabled). This flag is set to 0 on the rising edge of the 9th
SCL clock cycle in the frame.
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
HOA flag (Host Address Detection Flag)
The HOA flag indicates whether the host address was detected.
[Setting condition]
When the received slave address matches the host address (0001 000b) with the HOAE bit in ICSER set to 1 (host
address detection is enabled). This flag is set to 1 on the rising edge of the 9th SCL clock cycle in the frame.
[Clearing conditions]
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S3A1 User’s Manual
When 0 is written to the HOA bit after reading HOA = 1
When a stop condition is detected
When the received slave address does not match the host address (0001 000b) with the HOAE bit in ICSER set to 1
(host address detection is enabled). The HOA flag is set to 0 on the rising edge of the 9th SCL clock cycle in the
frame.
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
I2C Bus Status Register 2 (ICSR2)
30.2.10
Address(es): IIC0.ICSR2 4005 3009h, IIC1.ICSR2 4005 3109h, IIC2.ICSR2 4005 3209h
b7
b6
TDRE
TEND
0
0
Value after reset:
b5
b4
b3
b2
RDRF NACKF STOP START
0
0
0
0
b1
b0
AL
TMOF
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOF
Timeout Detection Flag
0: Timeout not detected
1: Timeout detected.
R/(W)
*1
b1
AL
Arbitration-Lost Flag
0: Arbitration not lost
1: Arbitration lost.
R/(W)
*1
b2
START
Start Condition Detection Flag
0: Start condition not detected
1: Start condition detected.
R/(W)
*1
b3
STOP
Stop Condition Detection Flag
0: Stop condition not detected
1: Stop condition detected.
R/(W)
*1
b4
NACKF
NACK Detection Flag
0: NACK not detected
1: NACK detected.
R/(W)
*1
b5
RDRF
Receive Data Full Flag
0: ICDRR contains no receive data
1: ICDRR contains receive data.
R/(W)
*1
b6
TEND
Transmit End Flag
0: Data is being transmitted
1: Data transmission complete.
R/(W)
*1
b7
TDRE
Transmit Data Empty Flag
0: ICDRT contains transmit data
1: ICDRT contains no transmit data.
R
Note 1.
Only 0 can be written to clear the flag.
TMOF flag (Timeout Detection Flag)
The TMOF flag is set to 1 when the IIC detects a timeout after the SCLn line state remains unchanged for the set period.
[Setting condition]
When the SCLn line state remains unchanged for the period specified in the TMOH, TMOL, and TMOS bits in
ICMR2, while the TMOE bit in ICFER is 1 (the timeout function is enabled) in master mode or in slave mode, and
the received slave address matches.
[Clearing conditions]
When 0 is written to the TMOF flag after reading TMOF = 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
AL flag (Arbitration-Lost Flag)
The AL flag indicates that bus mastership is lost in arbitration because of a bus conflict or some other reason, when a
start condition is issued, or an address and data are transmitted. The IIC monitors the level on the SDAn line during
transmission. If the level on the line does not match the value of the bit being output, the IIC sets the AL flag to 1 to
indicate that the bus is occupied by another device. The IIC can also set the AL flag to indicate the detection of
arbitration loss during NACK transmission in master mode or during data transmission in slave mode.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
[Setting conditions]
When master arbitration-lost detection is enabled (ICFER.MALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of SCL clock, except for
the ACK period during data transmission in master transmit mode
When a start condition is detected while the ST bit in ICCR2 is 1 (start condition issue requested) or the internal
SDA output state does not match the SDAn line level
When the ST bit in ICCR2 is set to 1 (start condition issue requested), with the BBSY flag in ICCR2 set to 1.
When NACK arbitration-lost detection is enabled (ICFER.NALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of SCL clock in the ACK
period during NACK transmission in receive mode.
When slave arbitration-lost detection is enabled (ICFER.SALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of SCL clock, except for
the ACK period during data transmission in slave transmit mode.
[Clearing conditions]
When 0 is written to the AL flag after reading AL = 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
Table 30.4
Relationship between arbitration-lost generation sources and arbitration-lost enable functions
ICFER
ICSR2
MALE
NALE
SALE
AL
Error
Arbitration-lost generation source
1
×
×
1
Start condition
issuance error
When internal SDA output state does not match the SDAn line level when a
start condition is detected, while the ST bit in ICCR2 is 1
1
Transmit data
mismatch
When transmit data including slave address does not match the bus state in
master transmit mode
When ST in ICCR2 is set to 1 while BBSY in ICCR2 is 1
×
1
×
1
NACK
transmission
mismatch
When ACK is detected during transmission of NACK in master or slave
receive mode
×
×
1
1
Transmit data
mismatch
When transmit data does not match the bus state in slave transmit mode
×: Don’t care
START flag (Start Condition Detection Flag)
The START flag indicates whether a start or restart condition is detected.
[Setting condition]
When a start or restart condition is detected.
[Clearing conditions]
When 0 is written to the START flag after reading START = 1
When a stop condition is detected
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
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30. I2C Bus Interface (IIC)
STOP flag (Stop Condition Detection Flag)
The STOP flag indicates whether a stop condition is detected.
[Setting condition]
When a stop condition is detected.
[Clearing conditions]
When 0 is written to the STOP flag after reading STOP = 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
NACKF flag (NACK Detection Flag)
The NACKF flag indicates whether a NACK was detected.
[Setting condition]
When an acknowledge is not received (NACK is received) from the receive device in transmit mode, with the
NACKE bit in ICFER set to 1 (transfer suspension enabled).
[Clearing conditions]
When 0 is written to the NACKF flag after reading NACKF = 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
Note:
When the NACKF flag is set to 1, the IIC suspends data transmission or reception. Writing to ICDRT in transmit
mode or reading from ICDRR in receive mode with the NACKF flag set to 1 does not enable data transmit or
receive operation. To restart data transmission or reception, set the NACKF flag to 0.
RDRF flag (Receive Data Full Flag)
The RDRF flag indicates whether the IDCRR contains receive data.
[Setting conditions]
When receive data is transferred from ICDRS to ICDRR.
The RDRF flag is set to 1 on the rising edge of the 8th or 9th SCL clock cycle (selected in the RDRFS bit in ICMR3).
When the received slave address matches, after a start or restart condition is detected, with the TRS bit in ICCR2 set
to 0.
[Clearing conditions]
When 0 is written to the RDRF flag after reading RDRF = 1
When data is read from ICDRR
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
TEND flag (Transmit End Flag)
The TEND flag indicates whether data is still being transmitted.
[Setting condition]
On the rising edge of the 9th SCL clock cycle, while the TDRE flag is 1.
[Clearing conditions]
When 0 is written to the TEND flag after reading TEND = 1
When data is written to ICDRT
When a stop condition is detected
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
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30. I2C Bus Interface (IIC)
TDRE flag (Transmit Data Empty Flag)
The TDRE flag indicates whether the ICDRT contains transmit data.
[Setting conditions]
When data is transferred from ICDRT to ICDRS and ICDRT becomes empty
When the TRS bit in ICCR2 is set to 1
When the received slave address matches while the TRS bit is 1.
[Clearing conditions]
When data is written to ICDRT
When the TRS bit in ICCR2 is set to 0
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
Note:
When the NACKF flag is set to 1 while the NACKE bit in ICFER is 1, the IIC suspends data transmission or
reception. In this case, if the TDRE flag is 0 (next transmit data written), data is transferred to the ICDRS register
and the ICDRT register becomes empty on the rising edge of the 9th clock cycle, but the TDRE flag is not set to 1.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
I2C Bus Wakeup Unit Register (ICWUR)
30.2.11
Address(es): IIC0.ICWUR 4005 3016h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
WUE
WUIE
WUF
WUAC
K
—
—
—
WUAFA
0
0
0
1
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
WUAFA
Wakeup Analog Filter Additional Selection
0: Do not add the wakeup analog filter
1: Add the wakeup analog filter.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
WUACK
ACK Bit for Wakeup Mode
Choice of four response modes in combination with
ICCR1.IICRST and WUACK. See Table 30.5.
R/W
b5
WUF
Wakeup Event Occurrence Flag
0: Slave address not matching during wakeup
1: Slave address matching during wakeup.
R/W
b6
WUIE
Wakeup Interrupt Request Enable
0: Wakeup Interrupt Request (IIC0_WUI) disabled
1: Wakeup Interrupt Request (IIC0_WUI) enabled.
R/W
b7
WUE
Wakeup Function Enable
0: Wakeup function disabled
1: Wakeup function enabled.
R/W
Table 30.5
Wakeup mode
IICRST
WUACK
Operation mode
Description
0
0
Normal wakeup mode 1
ACK response at 9th SCL and SCL low-hold after 9th SCL
0
1
Normal wakeup mode 2
No ACK response immediately and SCL low-hold between 8th and 9th SCL.
SCL low-hold release and ACK response on 9th SCL.
1
0
Command recovery mode
ACK response on 9th SCL and no SCL low-hold
1
1
EEP response mode
NACK response on 9th SCL and no SCL low-hold
WUF flag (Wakeup Event Occurrence Flag)
The WUF flag indicates whether the slave address is matching during wakeup.
[Setting condition]
When PCLKB is supplied after a slave-address match in the first 8th SCL low during wakeup mode.
[Clearing conditions]
When 0 is written to the WUF bit after reading WUF = 1
When ICE = 0 and IICRST = 1.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
I2C Bus Wakeup Unit Register 2 (ICWUR2)
30.2.12
Address(es): IIC0.ICWUR2 4005 3017h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
1
1
1
1
1
b2
b1
b0
WUSY WUAS WUSE
F
YF
N
1
0
1
Bit
Symbol
Bit name
Description
R/W
b0
WUSEN
Wakeup Function Synchronous Enable
0: IIC asynchronous operation enabled
1: IIC synchronous operation enabled.
R/W
b1
WUASYF
Wakeup Function Asynchronous
Operation Status Flag
0: IIC synchronous operation enabled
1: IIC asynchronous operation enabled.
R
b2
WUSYF
Wakeup Function Synchronous Operation
Status Flag
0: IIC asynchronous operation enabled
1: IIC synchronous operation enabled.
R
b7 to b3
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
WUSEN bit (Wakeup Function Synchronous Enable)
The WUSEN bit is used in combination with the WUASYF flag (or WUSYF flag) to switch between PCLKB
synchronous and asynchronous operation, when a wakeup function is enabled (ICWUR.WUE = 1).
The PCLKB operation switches from synchronous to asynchronous operation:
When the BBSY flag in ICCR2 is 0, if the WUASYF flag at 0 writes 0 to the WUSEN bit. The reception occurs
independently of the operation of PCLKB (with PCLKB stopped) after it switches to the PCLKB asynchronous
operation, on wakeup event detection.
The PCLKB operation switches from asynchronous to synchronous operation:
When 1 is written to the WUSEN bit with the WUASYF flag at 1, when a wakeup event is detected. After writing 1,
the WUASYF flag immediately becomes 0.
When a stop condition is detected with a wakeup event undetected.
WUASYF flag (Wakeup Function Asynchronous Operation Status Flag)
The WUASYF flag can place the IIC in PCLKB asynchronous operation when wakeup function is enabled
(ICWUR.WUE = 1).
[Setting condition]
When the ICCR2.BBSY flag is 0, and the WUSEN bit is set to 0, with the ICWUR.WUE bit set to 1.
[Clearing conditions]
When 1 is written to the WUSEN bit, after detecting a wakeup event with the ICWUR.WUE bit set to 1
When a stop condition is detected with the WUSEN bit set to 1 before detecting the wakeup event, with WUASY
flag set to 1 and ICWUR.WUE bit set to 1
When 1 is written to the WUSEN bit with the WUASYF flag set to 1, and a wakeup event is detected with the
ICWUR.WUE bit set to 1
ICCR1.ICE = 0 and ICCRST = 1 (ICC reset)
ICWUR.WUE = 0.
WUSYF flag (Wakeup Function Synchronous Operation Status Flag)
The WUSYF flag can place the IIC in PCLKB synchronous operation when wakeup function is enabled (ICWUR.WUE
= 1). When this flag is used, the WUASYF flag is reserved.
[Setting conditions]
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S3A1 User’s Manual
When 1 is written to the WUSEN bit after detecting a wakeup event with the ICWUR.WUE bit set to 1 and the
WUSYF flag set to 0, with the ICWUR.WUE bit set to 1
When a stop condition is detected with the WUSEN bit set to 1, before detecting the wakeup event with the
WUSYF flag set to 0, with the ICWUR.WUE bit set to 1
ICCR1.ICE = 0 and ICCRST = 1 (ICC reset)
ICWUR.WUE = 0.
[Clearing condition]
When the ICCR2.BBSY flag is 0 with the ICWUR.WUE bit set to 1, after writing 0 to the WUSEN bit.
30.2.13
Slave Address Register Ly (SARLy) (y = 0 to 2)
Address(es): IIC0.SARL0 4005 300Ah, IIC1.SARL0 4005 310Ah, IIC2.SARL0 4005 320Ah,
IIC0.SARL1 4005 300Ch, IIC1.SARL1 4005 310Ch, IIC2.SARL1 4005 320Ch,
IIC0.SARL2 4005 300Eh, IIC1.SARL2 4005 310Eh, IIC2.SARL2 4005 320Eh
b7
b6
b5
b4
b3
b2
b1
SVA[6:0]
Value after reset:
0
0
0
0
b0
SVA0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SVA0
10-Bit Address LSB
Slave address setting
R/W
b7 to b1
SVA[6:0]
7-Bit Address/10-Bit Address Lower Bits
Slave address setting
R/W
SVA0 bit (10-Bit Address LSB)
When the 10-bit address format is selected (SARUy.FS = 1), the SVA0 bit functions as the LSB of a 10-bit address and is
combined with the SVA[6:0] bits to form the lower 8 bits of a 10-bit address.
This bit is valid when the SARyE bit in ICSER is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1.
When the SARUy.FS bit or SARyE bit is 0, the setting in this bit is ignored.
SVA[6:0] bits (7-Bit Address/10-Bit Address Lower Bits)
When the 7-bit address format is selected (SARUy.FS = 0), the SVA[6:0] bits function as a 7-bit address. When the 10bit address format is selected (SARUy.FS = 1), these bits are combined with the SVA0 bit to form the lower 8 bits of a
10-bit address. While the SARyE bit in ICSER is 0, the setting in these bits is ignored.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.2.14
Slave Address Register Uy (SARUy) (y = 0 to 2)
Address(es): IIC0.SARU0 4005 300Bh, IIC1.SARU0 4005 310Bh, IIC2.SARU0 4005 320Bh,
IIC0.SARU1 4005 300Dh, IIC1.SARU1 4005 310Dh, IIC2.SARU1 4005 320Dh,
IIC0.SARU2 4005 300Fh, IIC1.SARU2 4005 310Fh, IIC2.SARU2 4005 320Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
SVA[1:0]
0
0
0
0
0
0
b0
FS
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FS
7-Bit/10-Bit Address Format Select
0: Select 7-bit address format
1: Select 10-bit address format.
R/W
b2, b1
SVA[1:0]
10-Bit Address Upper Bits
Slave address setting
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
FS bit (7-Bit/10-Bit Address Format Select)
The FS bit selects a 7-bit or 10-bit address format for the slave address y (in SARLy and SARUy).
When the SARyE bit in ICSER is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 0, the 7-bit address
format is selected for slave address y, the SVA[6:0] setting in SARLy is valid, and the SVA[1:0] and SVA0 bit settings in
SARLy are ignored.
When the SARyE bit in ICSER is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1, the 10-bit address
format is selected for slave address y and the SVA[1:0] and SARLy settings are valid.
When the SARyE bit in ICSER is 0 (SARLy and SARUy disabled), the SARUy.FS bit setting is invalid.
SVA[1:0] bits (10-Bit Address Upper Bits)
When the 10-bit address format is selected (FS = 1), the SVA[1:0] bits function as the upper 2 bits of a 10-bit address.
When the SARyE bit in ICSER is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1, these bits are valid.
When the SARUy.FS or SARyE bit is 0, the setting in these bits is ignored.
I2C Bus Bit Rate Low-Level Register (ICBRL)
30.2.15
Address(es): IIC0.ICBRL 4005 3010h, IIC1.ICBRL 4005 3110h, IIC2.ICBRL 4005 3210h
Value after reset:
b7
b6
b5
—
—
—
1
1
1
b4
b3
b2
b1
b0
1
1
BRL[4:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
BRL[4:0]
Bit Rate Low-Level Period
Low-level period of SCL clock
R/W
b7 to b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
ICBRL is a 5-bit register that sets the low-level period of the SCL clock. ICBRL also works to generate the data setup
time for automatic SCL low-hold operation (see section 30.9, Automatic Low-Hold Function for SCL). When the IIC is
used only in slave mode, this register must be set to a value longer than the data setup time*1. ICBRL counts the lowlevel period with the internal reference clock source (IICΦ) specified in the CKS[2:0] bits in ICMR1.
If the digital noise filter is enabled (the NFE bit in ICFER is 1), set the ICBRL register to a value at least one greater than
the number of stages in the noise filter. For this number, see the description of the ICMR3.NF[1:0] bits.
Note 1. Data setup time (tSU: DAT)
250 ns for up to 100 kbps: Standard-mode (Sm)
100 ns for up to 400 kbps: Fast-mode (Fm).
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
I2C Bus Bit Rate High-Level Register (ICBRH)
30.2.16
Address(es): IIC0.ICBRH 4005 3011h, IIC1.ICBRH 4005 3111h, IIC2.ICBRH 4005 3211h
Value after reset:
b7
b6
b5
—
—
—
1
1
1
b4
b3
b2
b1
b0
1
1
BRH[4:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
BRH[4:0]
Bit Rate High-Level Period
High-level period of SCL clock
R/W
b7 to b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
ICBRH is a 5-bit register that sets the high-level period of the SCL clock. ICBRH is valid in master mode. If the IIC is
used only in slave mode, no setting is required in this register.
ICBRH counts the high-level period with the internal reference clock source (IICΦ) specified in the CKS[2:0] bits in
ICMR1.
If the digital noise filter is enabled (the NFE bit in ICFER is 1), set the ICBRH register to a value at least one greater than
the number of stages in the noise filter. For this number, see the description of the ICMR3.NF[1:0] bits.
The IIC transfer rate and the SCL clock duty are calculated using the following expressions (1) to (5):
1) ICFER.SCLE = 0
Transfer rate = 1/{[(BRH + 1) + (BRL + 1)]/IICφ*1 + tr*2 + tf*2}
Duty cycle = {tr + [(BRH + 1)/IICφ]}/{tr + tf + [(BRH + 1) + (BRL + 1)]/IICφ}.
2) ICFER.SCLE = 1 and ICFER.NFE = 0 and CKS[2:0] = 000b (IICφ = PCLKB)
Transfer rate = 1/{[(BRH + 3) + (BRL+ 3)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 3)/IICφ]}/{tr + tf + [(BRH + 3) + (BRL + 3)]/IICφ}.
3) ICFER.SCLE = 1 and ICFER.NFE = 1 and CKS[2:0] = 000b (IICφ = PCLKB)
Transfer rate = 1/{[(BRH + 3 + nf*3) + (BRL + 3 + nf)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 3 + nf)/IICφ]}/{tr + tf + [(BRH + 3 + nf) + (BRL + 3 + nf)]/IICφ}.
4) ICFER.SCLE = 1 and ICFER.NFE = 0 and CKS[2:0] ≠ 000b
Transfer rate = 1/{[(BRH + 2) + (BRL + 2)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 2)/IICφ]}/{tr + tf + [(BRH + 2) + (BRL + 2)]/IICφ}.
5) ICFER.SCLE = 1 and ICFER.NFE = 1 and CKS[2:0] ≠ 000b
Transfer rate = 1/{[(BRH + 2 + nf) + (BRL + 2 + nf)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 2 + nf)/IICφ]}/{tr + tf + [(BRH + 2 + nf) + (BRL + 2 + nf)]/IICφ}.
Note 1. IICφ = PCLKB × Division ratio.
Note 2. The SCLn line rising time (tr) and SCLn line falling time [tf] depend on the total bus line capacitance (Cb) and the
pull-up resistor (Rp). For details, see the I2C bus standard from NXP Semiconductors.
Note 3. nf = Number of digital noise filter stages selected in the ICMR3.NF[1:0] bits.
Table 30.6
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 0
Transfer rate (kbps)
CKS[2:0]
BRH[4:0]
(ICBRH)
BRL[4:0]
(ICBRL)
PCLKB (MHz)
NF[1:0]
Computation expression
100
011
15 (EFh)
18 (F2h)
32
-
(1)
400
001
9 (E9h)
20 (F4h)
32
-
(1)
Table 30.7
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 1 and NFE = 0 (1 of 2)
Transfer rate (kbps)
CKS[2:0]
BRH[4:0]
(ICBRH)
BRL[4:0]
(ICBRL)
PCLKB (MHz) NF[1:0]
Computation expression
100
011
14 (EEh)
17 (F1h)
32
(4)
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S3A1 User’s Manual
Table 30.7
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 1 and NFE = 0 (2 of 2)
Transfer rate (kbps)
CKS[2:0]
BRH[4:0]
(ICBRH)
BRL[4:0]
(ICBRL)
PCLKB (MHz) NF[1:0]
Computation expression
400
001
8 (E8h)
19 (F3h)
32
(4)
Table 30.8
-
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 1 and NFE = 1
BRH[4:0]
(ICBRH)
BRL[4:0]
(ICBRL)
Transfer rate (kbps)
CKS[2:0]
100
011
12 (ECh)
15 (EFh)
32
01b
(5)
400
001
6 (E6h)
17 (F1h)
32
01b
(5)
Note:
PCLKB (MHz) NF[1:0]
Computation expression
SCLn line rising time (tr): ≤ 100 kbps, Sm: 1000 ns, ≤ 400 kbps, Fm: ≤ 300 ns
SCLn line falling time (tf): ≤ 400 kbps, Sm/Fm: ≤ 300 ns
30.2.17
I2C Bus Transmit Data Register (ICDRT)
Address(es): IIC0.ICDRT 4005 3012h, IIC1.ICDRT 4005 3112h, IIC2.ICDRT 4005 3212h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
When ICDRT detects a space in the I2C Bus Shift Register (ICDRS), it transfers the transmit data that is written to
ICDRT to ICDRS and starts transmitting data in transmit mode.
The double-buffer structure of ICDRT and ICDRS allows continuous transmit operation if the next transmit data is
written to ICDRT while the ICDRS data is being transmitted.
ICDRT can always be read from and written to. Write transmit data to ICDRT when a transmit data empty interrupt
(IICn_TXI) request is generated.
30.2.18
I2C Bus Receive Data Register (ICDRR)
Address(es): IIC0.ICDRR 4005 3013h, IIC1.ICDRR 4005 3113h, IIC2.ICDRR 4005 3213h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
When 1 byte of data is received, the received data is transferred from the I2C bus Shift Register (ICDRS) to ICDRR to
enable the next data to be received.
The double-buffer structure of ICDRS and ICDRR allows continuous receive operation if the received data is read from
ICDRR while ICDRS is receiving data. ICDRR cannot be written to. Read data from ICDRR when a receive data full
interrupt (IICn_RXI) request is generated.
If ICDRR receives the next receive data before the current data is read from ICDRR while the RDRF flag in ICSR2 is 1,
the IIC automatically holds the SCL clock low for 1 cycle before the RDRF flag is set to 1 again.
30.2.19
Value after reset:
I2C Bus Shift Register (ICDRS)
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
ICDRS is an 8-bit shift register to transmit and receive data.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
During transmission, transmit data is transferred from ICDRT to ICDRS and is sent from the SDAn pin. During
reception, data is transferred from ICDRS to ICDRR after 1 byte of data is received. ICDRS cannot be accessed directly.
30.3
Operation
30.3.1
Communication Data Format
The I2C bus format consists of 8-bit data and 1-bit acknowledge. The frame following a start or restart condition is an
address frame that specifies a slave device with which the master device communicates. The specified slave is valid until
a new slave is specified or a stop condition is issued.
Figure 30.3 shows the I2C bus format, and Figure 30.4 shows the I2C bus timing.
[7-bit address format]
S
SLA (7 bits)
R/W#
A
1
7
1
1
DATA (8 bits)
8
A
A/A#
P
1
1
1
n (n = 1 or more)
[10-bit address format]
S
11110b +
SLA (2 bits)
W#
A
SLA (8 bits)
A
DATA (8 bits)
A
A/A#
P
1
7
1
1
8
1
8
1
1
1
n (n = 1 or more)
S
11110b +
SLA (2 bits)
W#
A
SLA (8 bits)
A
Sr
11110b +
SLA (2 bits)
R
A
DATA (8 bits)
A
A/A#
P
1
7
1
1
8
1
1
7
1
1
8
1
1
1
n (n = 1 or more)
n: Number of transfer frames
Figure 30.3
SCLn
I2C bus format
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDAn
S
Figure 30.4
SLA
R/W#
A
Data
A
Data
A
P
I2C bus timing with SLA = 7 bits
S:
Start condition. The master device drives the SDAn line low from high while the SCLn line is high.
SLA:
Slave address, by which the master device selects a slave device
R/W#:
Indicates the direction of data transfer: from the slave device to the master device when R/W# is 1, or from the master device
to the slave device when R/W# is 0
A:
Acknowledge. The receive device drives the SDAn line low. In master transmit mode, the slave device returns acknowledge.
In master receive mode, the master device returns acknowledge.
A#:
Not Acknowledge. The receive device drives the SDAn line high.
Sr:
Restart condition. The master device drives the SDAn line low from high after the setup time elapses with the SCLn line high.
DATA:
Transmitted or received data
P:
Stop condition. The master device drives the SDAn line high from low while the SCLn line is high.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.3.2
Initial Settings
Before starting data transmission or reception, initialize the IIC using the procedure shown in Figure 30.5.
1. Set the ICCR1.ICE bit to 0 to set the SCLn and SDAn pins to the inactive state.
2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset.
3. Set the ICCR1.ICE bit to 1 to initiate internal reset.
4. Set the SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL registers (y = 0 to 2), and set the other registers as
required. For initial settings of the IIC, see Figure 30.5.
5. When the required register settings are complete, set the ICCR1.IICRST bit to 0 to release the IIC reset.
Note:
This procedure is not required if the IIC initialization is already complete.
Initial settings
Set ICE in ICCR1 to 0
Set IICRST in ICCR1 to 1
Set ICE in ICCR1 to 1
Set SARLy and SARUy.
Set ICSER.
Set CKS[2:0] in ICMR1 and
ICBRL/ICBRH
SCLn, SDAn pins not driven
IIC reset
Internal reset, SCLn and SDAn pins in active state
Set slave address format and slave address
Set transfer bit rate*1
Set ICMR2 and ICMR3
*2
Set ICFER
Set ICIER
Set IICRST in ICCR1 to 0
Set interrupt enable
Release from the internal reset state
End
y = 0 to 2
Note 1.
Note 2.
Figure 30.5
When the IIC is used only in slave mode, set the ICBRL register to a value longer than the
data setup time.
Set these registers as required.
Example IIC initialization flow
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30.3.3
30. I2C Bus Interface (IIC)
Master Transmit Operation
In master transmit operation, the IIC outputs the SCL clock and transmit data signals as the master device, and the slave
device returns acknowledgments. Figure 30.6 shows an example of master transmission, and Figure 30.7 to Figure 30.9
show the timing of operations in master transmission.
To set up and perform master transmission:
1. Initialize the IIC using the procedure described in section 30.3.2, Initial Settings.
2. Read the BBSY flag in ICCR2 to check that the bus is open, and then set the ST bit in ICCR2 to 1 (start condition
request). On receiving the request, the IIC issues a start condition. At the same time, the BBSY and START flags in
ICSR2 automatically set to 1, and the ST bit is automatically set to 0. If the start condition is detected and the
internal levels for the SDA output state and the levels on the SDAn line match while the ST bit is 1, the IIC
recognizes that the start condition requested by the ST bit has successfully completed, and the MST and TRS bits in
ICCR2 automatically set to 1, placing the IIC in master transmit mode. The TDRE flag in ICSR2 also automatically
sets to 1 in response to the setting of the TRS bit to 1.
3. Check that the TDRE flag in ICSR2 is 1, and then write the value for transmission (the slave address and the R/W#
bit) to ICDRT. When the transmit data is written to ICDRT, the TDRE flag is automatically set to 0, the data is
transferred from ICDRT to ICDRS, and the TDRE flag again sets to 1. After the byte containing the slave address
and R/W# bit is transmitted, the value of the TRS bit automatically updates to select master transmit or master
receive mode based on the value of the transmitted R/W# bit. If the value of the R/W# bit is 0, the IIC continues in
master transmit mode.
If the ICSR2.NACKF flag is 1, indicating that no slave device recognized the address or there was an error in
communications, write 1 to the ICCR2.SP bit to issue a stop condition.
To transmit data with an address in the 10-bit format, start by writing 1111 0b, the 2 upper bits of the slave address,
and W to ICDRT as the first address transmission. Then, as the second address transmission, write the 8 lower bits
of the slave address to ICDRT.
4. After confirming that the TDRE flag in ICSR2 is 1, write the transmit data to the ICDRT register. The IIC
automatically holds the SCLn line low until the transmit data is ready or a stop condition is issued.
5. After all bytes of transmit data are written to the ICDRT register, wait until the value of the TEND flag in ICSR2
returns to 1, and then set the SP bit in ICCR2 to 1 (stop condition requested). On receiving a stop condition request,
the IIC issues the stop condition. Regarding issuing a stop condition, see section 30.11.3, Issuing a Stop Condition.
6. On detecting the stop condition, the IIC automatically sets the MST and TRS bits in ICCR2 to 00b and enters slave
receive mode. In addition, the IIC automatically sets the TDRE and TEND flags to 0, and sets the STOP flag in
ICSR2 to 1.
7. After checking that the ICSR2.STOP flag is 1, set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Master transmission
[1] Process initial settings.
Initial settings
No
ICCR2.BBSY = 0?
[2] Check I2C bus occupation and issue a
start condition.
Yes
ICCR2.ST = 1
ICSR2.NACKF = 0?
No
Yes
No
ICSR2.TDRE = 1?
Yes
[3] Transmit slave address and W (first byte).
[4] Check ACK and set transmit data.
Write data to ICDRT
No
All data transmitted?
Yes
No
ICSR2.TEND = 1?
Yes
ICSR2.STOP = 0
[5] Check end of last data transmission and
issue a stop condition.
ICCR2.SP = 1
No
ICSR2.STOP = 1?
[6] Check stop condition issuance.
Yes
ICSR2.NACKF = 0
ICSR2.STOP = 0
[7] Execute processing for the next transfer
operation.
End of master transmission
Figure 30.6
Example master transmission flow
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Automatic low-hold (to prevent wrong transmission)
S
1
2
b7
b6
3
4
5
6
7
8
b5
b4
b3
b2
b1
b0
9
1
2
3
4
5
6
7
8
9
b7
b6
b5
b4
b3
b2
b1
b0
ACK
1
2
3
4
b7
b6
b5
SCLn
SDAn
ACK
W
7-bit slave address
DATA 1
b4
DATA 2
BBSY
MST
TRS
Transmit data (7-bit address + W)
Transmit data (DATA 1)
Transmit data (DATA 2)
TDRE
TEND
RDRF
ICDRT
DATA 2
DATA 1
7-bit address + W
7-bit address + W
ICDRS
DATA 3
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
START
ST
Write data to
Write data to
Write 1
ICDRT
ICDRT
to ST (7-bit address + W)
(DATA 1)
[2]
[3]
Figure 30.7
Write data to
ICDRT
(DATA 2)
Write data to
ICDRT
(DATA 3)
[4]
[4]
[4]
Master transmit operation timing (1) with 7-bit address format
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
8
9
1
2
b0
ACK
b7
b6
3
4
5
6
7
8
9
1
2
3
4
b5
b4
b3
b2
b1
b0
ACK
b7
b6
b5
b4
SCLn
SDAn
Upper 10-bit addresses (11110b + 2 bits)
Lower 10-bit addresses
W
DATA 1
BBSY
MST
TRS
Transmit data (upper 10 bits + W)
Transmit data (DATA 1)
Transmit data (lower 10 bits)
TDRE
TEND
RDRF
ICDRT
Lower 10 bits
10-bit address + W
ICDRS
DATA 1
Lower 10 bits
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
ACKBR
DATA 2
DATA 1
Upper 10 bits + W
X (ACK/NACK)
0 (ACK)
0 (ACK)
START
ST
Write data to
Write data to
Write 1
ICDRT
ICDRT
to ST (11110b + 2
(lower 8 bits)
bits + W)
[2]
[3]
Figure 30.8
Write data to
ICDRT
(DATA 1)
Write data to
ICDRT
(DATA 2)
[4]
[4]
Master transmit operation timing (2) with 10-bit address format
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
7
8
9
1
2
3
ACK
b7
b6
b5
4
5
6
7
8
9
1
2
3
b4
b3
DATA n-1
b2
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
9
P
b4
b3
DATA n
b2
b1
b0
A/NA
SCLn
SDAn
b1
b0
DATA n-2
BBSY
MST
TRS
Transmit data (DATA n)
Transmit data (DATA n-1)
TDRE
TEND
RDRF
ICDRT
DATA n-1
ICDRS
DATA n-2
DATA n
DATA n-1
DATA n
XXXX (Initial value/final receive data)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
ACKBR
0 (ACK)
X (ACK/NACK)
STOP
SP
Figure 30.9
Write data to ICDRT
(Final transmit data [DATA n])
Write 1
to SP
Clear
STOP to 0
[4]
[5]
[7]
Master transmit operation timing (3)
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S3A1 User’s Manual
30.3.4
30. I2C Bus Interface (IIC)
Master Receive Operation
In master receive operation, the IIC as a master device outputs the SCL clock, receives data from the slave device, and
returns acknowledgments. Because the IIC must start by sending a slave address to the associated slave device, the slave
address phase of the procedure is performed in master transmit mode, and the subsequent steps are performed in master
receive mode.
Figure 30.10 and Figure 30.11 show examples of master reception (7-bit address format), and Figure 30.12 to Figure
30.14 show the timing of operations in master reception.
To set up and perform master reception:
1. Initialize the IIC using the procedure in section 30.3.2, Initial Settings.
2. Read the BBSY flag in ICCR2 to check that the bus is open, and then set the ST bit in ICCR2 to 1 to request issue of
a start condition. On receiving the request, the IIC issues a start condition. When the IIC detects the start condition,
the BBSY flag and the START flag in ICSR2 automatically set to 1 and the ST bit is automatically sets to 0. If the
start condition is detected and the levels for the SDA output and the levels on the SDAn line match while the ST bit
is 1, the IIC recognizes that the start condition issue is successful as requested by the ST bit, and the MST and TRS
bits in ICCR2 automatically set to 1, placing the IIC in master transmit mode. The TDRE flag in ICSR2 is also
automatically set to 1 in response to the setting of the TRS bit to 1.
3. Check that the TDRE flag in ICSR2 is 1, and then write the value for transmission (the first byte indicates the slave
address and value of the R/W# bit) to ICDRT. When the transmit data is written to ICDRT, the TDRE flag is
automatically set to 0, the data is transferred from ICDRT to ICDRS, and the TDRE flag is again set to 1. When the
byte containing the slave address and R/W# bit is transmitted, the value of the ICCR2.TRS bit automatically
updates to select transmit or receive mode based on the value of the transmitted R/W# bit. If the value of the R/W#
bit is 1, the TRS bit is set to 0 on the rising edge of the 9th cycle of the SCL clock, placing the IIC in master receive
mode. The TDRE flag is set to 0 and the ICSR2.RDRF flag is automatically set to 1.
If the ICSR2.NACKF flag is 1, indicating that no slave device recognized the address or that there is an error in
communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit
address, and then issue a restart condition. After that, transmit 1111 0b, the two upper bits of the slave address, and
the R bit to place the IIC in master receive mode.
4. Dummy read ICDRR after confirming that the RDRF flag in ICSR2 is 1. Doing so causes the IIC to start output of
the SCL clock and start data reception.
5. After 1 byte of data is received, the RDRF flag in ICSR2 is set to 1 on the rising edge of the 8th or 9th cycle of SCL
clock, as selected in the RDRFS bit in ICMR3. Reading the ICDRR register produces the received data and
automatically sets the RDRF flag to 0. The value of the acknowledgment field received during the 9th cycle of the
SCL clock is returned as the value set in the ICMR3.ACKBT bit. If the next byte to be received is the next-to-last
byte, set the ICMR3.WAIT bit to 1 for wait insertion before reading the ICDRR register, containing the next-to-last
byte. In addition to enabling NACK output, even when interrupts or other operations result in delays in setting the
ICMR3.ACKBT bit to 1 (NACK) in step (6), this fixes the SCLn line to low on the rising edge of the 9th clock cycle
in reception of the last byte, which enables the issue of a stop condition.
6. When the ICMR3.RDRFS bit is 0 and the slave device must be notified that it should end transfer for data reception
after transfer of the next and final byte, set the ICMR3.ACKBT bit to 1 (NACK).
7. After reading the second-to-last byte from the ICDRR register, if the value of the ICSR2.RDRF flag is 1, write 1 to
the SP bit in ICCR2 (to request stop condition), and then read the last byte from ICDRR. When ICDRR is read, the
IIC is released from the wait state and issues the stop condition after low-level output in the 9th clock cycle is
complete or the SCLn line is released from the low-hold state.
8. On detecting the stop condition, the IIC automatically sets the ICCR2.MST and ICCR2.TRS bits to 00b and enters
slave receive mode. Additionally, detection of the stop condition sets the ICSR2.STOP flag to 1.
9. Check that the ICSR2.STOP flag is 1, and then set the ICSR2.NACKF and ICSR2.STOP flags to 0 for the next
transfer operation.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
M a s te r re c e p tio n s ta rts
(1 ) P ro c e s s in itia l s e ttin g s .
In itia l s e ttin g s
No
IC C R 2 .B B S Y = 0 ?
(2 ) C h e c k I 2 C b u s o c c u p a tio n a n d is s u e a s ta rt c o n d itio n .
Yes
IC C R 2 .S T = 1
No
IC S R 2 .T D R E = 1 ?
Yes
W rite th e IC D R T re g is te r
No
(3 ) T ra n s m it th e s la v e a d d re s s fo llo w e d b y
R and check A C K .
IC S R 2 .R D R F = 1 ?
Yes
IC S R 2 .N A C K F = 0 ?
No
Yes
IC M R 3 .W A IT = 1
N e x t d a ta = la s t b y te ?
(4 ) S e t to W A IT .
Yes
No
D u m m y re a d th e IC D R R re g is te r
No
(5 ) S e t to N A C K .
W h e n re c e iv in g 2 b y te s , p e rfo rm d u m m y
re a d .
IC S R 2 .R D R F = 1 ?
Yes
S e t IC M R 3 .A C K B T
(6 ) R e a d re c e iv e d d a ta .
W h e n re c e iv in g 1 b y te , p e rfo rm
d u m m y re a d .
R e a d th e IC D R R re g is te r
No
IC S R 2 .R D R F = 1 ?
Yes
IC S R 2 .S T O P = 0
IC C R 2 .S P = 1
R e a d th e IC D R R re g is te r
IC S R 2 .S T O P = 0
IC C R 2 .S P = 1
D u m m y re a d th e IC D R R re g is te r
(7 ) R e a d th e la s t d a ta ,
re le a s e S C L b y th e A C K B T s e ttin g ,
a n d g e n e ra te a s to p c o n d itio n .
IC M R 3 .W A IT = 0
No
IC S R 2 .S T O P = 1 ?
(8 ) C o n firm th a t th e s to p c o n d itio n
h a s b e e n g e n e ra te d .
Yes
IC S R 2 .N A C K F = 0
IC S R 2 .S T O P = 0
(9 ) E x e c u te p ro c e s s in g fo r th e n e x t tra n s fe r o p e ra tio n .
M a s te r re c e p tio n e n d s
Figure 30.10
Example master reception flow with 7-bit address format and 1 or 2 bytes
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Master reception
[1] Process initial
settings.
Initial settings
No
ICCR2.BBSY = 0?
[2] Check I2C bus occupation and issue a start
condition.
Yes
ICCR2.ST = 1
No
ICSR2.TDRE = 1?
Yes
Write data to ICDRT
No
[3] Transmit the slave address followed by R and
check ACK.
ICSR2.RDRF = 1?
Yes
No
ICSR2.NACKF = 0?
Yes
[4] Perform dummy read.
Perform dummy read of ICDRR
No
ICSR2.RDRF = 1?
Yes
Next data = Final byte - 1?
No
Next data = Final byte - 2?
No
Yes
[5] Read received data and prepare for receiving
final data.
Yes
ICMR3.WAIT = 1
Read ICDRR
Set ICMR3.ACKBT
[6] Set the acknowledgment and read data of
(final byte – 1 byte).
Read ICDRR
No
ICSR2.RDRF = 1?
Yes
ICSR2.STOP = 0
ICSR2.STOP = 0
ICCR2.SP = 1
ICCR2.SP = 1
Read ICDRR
Perform dummy read of ICDRR
[7] Read final data and issue a stop
condition.
ICMR3.WAIT = 0
No
ICSR2.STOP = 1?
[8] Check stop condition issuance.
Yes
ICSR2.NACKF = 0
[9] Execute processing for the next transfer
operation.
ICSR2.STOP = 0
End of master reception
Figure 30.11
Example master reception flow with 7-bit address format and 3 or more bytes
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Automatic low hold
(to prevent wrong transmission)
S
Master transmit mode
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
Master receive mode
8
9
1
2
3
4
5
6
7
8
ACK
b7
b6
b5
b4
b3
b2
b1
b0
9
1
2
3
b7
b6
b5
4
SCLn
SDAn
7-bit slave address
b0
R
ACK
DATA 1
b4
DATA 2
BBSY
MST
TRS
Transmit data (7-bit address + R)
TDRE
Receive data (7-bit address + R)
TEND
Receive data (DATA 1)
RDRF
7-bit address + R
ICDRT
ICDRS
7-bit address + R
ICDRR
XXXX (Initial value/last data for reception)
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
DATA 1
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
START
ST
Write 1 Write data to ICDRT
to ST (7-bit address + R)
[2]
[3]
Figure 30.12
Read ICDRR
(Dummy read)
Read ICDRR
(DATA 1)
[4]
[5]
Master receive operation timing (1) with 7-bit address format, when RDRFS = 0
Master transmit mode
Automatic low hold (to prevent wrong transmission)
1 to 7
S
8
1 to 8
9
9
Sr
1
2
3
4
b6
b5
b4
5
6
7
b2
b1
Master receive mode
8
9
1
2
3
ACK
b7
b6
b5
4
SCLn
SDAn
b7
b1
Upper 10 bits
b0
W
ACK
b7
b0
ACK
Lower 10 bits
b7
b3
Upper 10-bit addresses (11110b + 2 bits)
b0
R
b4
DATA 1
BBSY
MST
TRS
Transmit data (upper 10 bits + W)Transmit data (lower 10 bits)
Transmit data (upper 10 bits + R)
TDRE
Transmit data (upper 10 bits + R)
TEND
RDRF
ICDRT
Upper 10 bits + W
ICDRS
Upper 10 bits + W
Lower 10 bits
Upper 10 bits + R
Lower 10 bits
Upper 10 bits + R
XXXX (Initial value/last data for reception)
ICDRR
DATA 1
XXXX (Initial value/last data for reception )
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
0 (ACK)
START
ST
RS
Write 1 Write data to ICDRT
to ST (11110b + 2 bits + W)
Write data to
ICDRT
(lower 8 bits)
[2]
Figure 30.13
Clear
START to 0
Write 1 Write data to ICDRT
to RS (11110b + 2 bits + R)
Read ICDRR
(Dummy read)
[3]
[4]
Master receive operation timing (2) with 10-bit address format, when RDRFS = 0
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Automatic low hold (WAIT)
7
8
9
1
2
3
b1
b0
ACK
b7
b6
b5
Automatic low hold (WAIT)
4
5
6
7
8
9
1
2
3
b4
b3
b2
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
9
b4
b3
b2
b1
b0
NACK
P
SCLn
SDAn
DATA n-2
DATA n-1
DATA n
BBSY
MST
TRS
TDRE
TEND
Receive data (DATA n-1)
Receive data (DATA n-2)
Receive data (DATA n)
RDRF
XXXX (last data for transmission
[7-bit addresses + R/Upper 10 bits + R])
ICDRT
ICDRS
ICDRR
DATA n-1
DATA n-2
DATA n-1
0 (ACK)
ACKBT
ACKBR
DATA n
DATA n-2
DATA n-3
0 (ACK)
DATA n
1 (NACK)
0 (ACK)
0
0 (ACK)
1 (NACK)
STOP
SP
WAIT
Write 1
to WAIT
Read ICDRR
(DATA n-2)
[5]
Figure 30.14
30.3.5
Write 1
Read ICDRR
to ACKBT (DATA n-1)
[6]
Write 1
to SP
Read ICDRR
Clear
Clear
(last data for reception
WAIT to 0 STOP to 0
[DATA n])
[7]
[9]
Master receive operation timing (3) when RDRFS = 0
Slave Transmit Operation
In slave transmit operation, the master device outputs the SCL clock, the IIC transmits data as a slave device, and the
master device returns acknowledgments.
Figure 30.15 shows an example of slave transmission, and Figure 30.16 and Figure 30.17 show the operation timing in
slave transmission.
To set up and perform slave transmission:
1. To initialize the IIC, follow the procedure in section 30.3.2, Initial Settings.
After initialization, the IIC stays in the standby state until it receives a slave address that matches.
2. After receiving a matching slave address, the IIC sets one of the associated bits ICSR1.HOA, GCA, and AASy (y =
0 to 2) flags to 1 on the rising edge of the 9th cycle of SCL clock and outputs the value set in the ICMR3.ACKBT bit
as the acknowledge bit on the 9th cycle of SCL clock. If the value of the received R/W# bit is 1, the IIC
automatically places itself in slave transmit mode by setting both the ICCR2.TRS bit and the ICSR2.TDRE flag to
1.
3. Check that the ICSR2.TEND flag is 1, and write the transmit data to the ICDRT register. If the IIC receives no
acknowledge from the master device (receives an NACK signal) while the ICFER.NACKE bit is 1, the IIC
suspends transfer of the next data.
4. Wait until the ICSR2.TEND flag is set to 1 while the ICSR2.TDRE flag is 1, after the ICSR2.NACKF flag is set to
1 or the last byte for transmission is written to the ICDRT register. When the ICSR2.NACKF flag or the TEND flag
is 1, the IIC drives the SCLn line low on the 9th falling edge of SCL clock.
5. When the ICSR2.NACKF flag or the ICSR2.TEND flag is 1, dummy read ICDRR to complete the processing. This
releases the SCLn line.
6. On detecting the stop condition, the IIC automatically sets the ICSR1.HOA, GCA, and AASy (y = 0 to 2) flags, the
ICSR2.TDRE and TEND flags, and the ICCR2.TRS bit to 0, and enters slave receive mode.
7. Check that the ICSR2.STOP flag is 1, and set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Slave transmission
[1] Process initial settings.
Initial settings
ICSR2.NACKF = 0?
No
Yes
No
ICSR2.TDRE = 1?
Yes
Write data to ICDRT
[2], [3] Check ACK and set transmit data. Checking of ACK is
not required immediately after the address is received.
No
All data transmitted?
Yes
No
ICSR2.TEND = 1?
Yes
No
Read ICDRR
[4] Dummy read to release SCLn.
ICSR2.STOP = 1?
[5] Check stop condition detection.
Yes
ICSR2.NACKF = 0
[6] Execute processing for the next transfer operation.
ICSR2.STOP = 0
End of slave transmission
Figure 30.15
Example slave transmission flow
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Slave receive mode
S
1
2
b7
b6
3
4
5
6
7
b5
b4
b3
b2
b1
Slave transmit mode
8
9
1
2
3
b7
b6
b5
Automatic low hold (to prevent wrong transmission)
4
5
6
7
8
b4
b3
b2
b1
b0
9
1
2
b7
b6
3
4
b5
b4
SCLn
SDAn
ACK
b0
7-bit slave address
R
ACK
DATA 1
DATA 2
BBSY
MST
TRS
Transmit data (DATA 2)
Transmit data (DATA 1)
TDRE
TEND
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
DATA 1
DATA 2
7-bit address + R
ICDRS
DATA 3
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
X (ACK/NACK)
ACKBR
0 (ACK)
0 (ACK)
START
NACKF
Write data to Write data to
ICDRT
ICDRT
(DATA 2)
(DATA 1)
[3]
Figure 30.16
Write data to
ICDRT
(DATA 3)
[3]
[3]
Slave transmit operation timing (1) with 7-bit address format
7
8
9
1
2
3
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
9
1
2
3
b4
b3
b2
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
b4
b3
b2
b1
b0
9
P
SCLn
SDAn
DATA n-2
DATA n-1
NACK
DATA n
BBSY
MST
TRS
Transmit data (DATA n-1)
Transmit data (DATA n)
TDRE
TEND
RDRF
AASy
ICDRT
ICDRS
DATA n-1
DATA n
DATA n-2
DATA n-1
ICDRR
DATA n
XXXX (Initial value/last data for reception)
0 (ACK)
ACKBT
0 (ACK)
ACKBR
0 (ACK)
1 (NACK)
STOP
NACKF
Write data to ICDRT
(last data for transmission
[DATA n])
[4]
Figure 30.17
Clear
Dummy read ICDRR
NACKF
(SCLn line is released)
to 0
[5]
Clear
STOP
to 0
[7]
Slave transmit operation timing (2)
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.3.6
Slave Receive Operation
In a slave receive operation, the master device outputs the SCL clock and transmit data, and the IIC returns
acknowledgments as a slave device.
Figure 30.18 shows an example of slave reception. Figure 30.19 and Figure 30.20 show the operation timing in slave
reception.
To set up and perform slave reception:
1. To initialize the IIC, follow the procedure in section 30.3.2, Initial Settings.
After initialization, the IIC stays in the standby state until it receives a slave address that matches.
2. After receiving a matching slave address, the IIC sets one of the associated ICSR1.HOA, GCA, and AASy
(y = 0 to 2) flags to 1 on the rising edge of the 9th cycle of the SCL clock and outputs the value set in the
ICMR3.ACKBT bit to the acknowledge bit on the 9th cycle of the SCL clock. If the value of the received R/W# bit
is 0, the IIC continues to place itself in slave receive mode and sets the RDRF flag in ICSR2 to 1.
3. Check that the ICSR2.STOP flag is 0 and the ICSR2.RDRF flag is 1, and then dummy read the ICDRR register. The
dummy value consists of the slave address and R/W# bit when the 7-bit address format is selected, or the lower 8
bits when the 10-bit address format is selected.
4. When ICDRR is read, the IIC automatically sets the ICSR2.RDRF flag to 0. If reading of ICDRR is delayed and the
next byte is received while the RDRF flag is still set to 1, the IIC holds the SCLn line low until 1 SCL cycle before
the point where RDRF must be set. In this case, reading the ICDRR register releases the SCLn line from being held
low.
When the ICSR2.STOP flag is 1 and the ICSR2.RDRF flag is also 1, read the ICDRR register until all the data is
completely received.
5. On detecting the stop condition, the IIC automatically clears the ICSR1.HOA, GCA, and AASy (y = 0 to 2) flags to
0.
6. Check that the ICSR2.STOP flag is 1, then set the ICSR2.STOP flag to 0 for the next transfer operation.
Slave reception
Initial settings
ICSR2.STOP = 0?
[1] Process initial settings.
No
Yes
No
ICSR2.RDRF = 1?
ICSR2.RDRF = 1?
Yes
Yes
Read ICDRR
No
Yes
No
[2], [3], [4] Read receive data
(dummy read first).
Read ICDRR (last data)
All data received?
Yes
No
ICSR2.STOP = 1?
[5] Check stop condition detection.
Yes
ICSR2.STOP = 0
[6] Execute processing for the next
transfer.
End of slave reception
Figure 30.18
Example slave reception flow
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Automatic low hold
(to prevent failure to receive data)
S
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
8
9
1
2
3
4
5
6
7
8
b7
b6
b5
b4
b3
b2
b1
b0
9
1
2
b7
b6
3
4
b5
b4
SCLn
SDAn
ACK
b0
7-bit slave address
W
ACK
DATA 1
DATA 2
BBSY
MST
TRS
TDRE
Receive data (7-bit address + W)
TEND
Receive data (DATA 1)
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
7-bit address + W
ICDRS
DATA 1
XXXX (Initial value/last data for reception)
ICDRR
DATA 2
DATA 1
7-bit address + W
0 (ACK)
ACKBT
X (ACK/NACK)
ACKBR
0 (ACK)
0 (ACK)
START
NACKF
Figure 30.19
Read ICDRR
(Dummy read
[7-bit address + W])
Read ICDRR
(DATA 1)
[3]
[3][4]
Slave receive operation timing (1) with 7-bit address format, when RDRFS = 0
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
b1
b0
ACK
b7
b6
b5
b4
b3
b2
b1
b0
ACK
b7
b6
b5
b4
b3
b2
b1
b0
ACK
P
SCLn
SDAn
DATA n-2
DATA n-1
DATA n
BBSY
MST
TRS
TDRE
TEND
Receive data (DATA n-2)
Receive data (DATA n-1)
Receive data (DATA n)
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
ICDRS
ICDRR
DATA n-2
DATA n
DATA n-1
DATA n-3
DATA n-2
DATA n-1
DATA n
0 (ACK)
ACKBT
0 (ACK)
0 (ACK)
ACKBR
0 (ACK)
STOP
NACKF
Figure 30.20
Read ICDRR
(DATA n-2)
Read ICDRR
(DATA n-1)
[3] [4]
[3] [4]
Read ICDRR
(DATA n)
[3] [4]
Clear
STOP to 0
[6]
Slave receive operation timing (2) when RDRFS = 0
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.4
SCL Synchronization Circuit
For generation of the SCL clock, the IIC starts counting the value for the high-level period specified in ICBRH when it
detects a rising edge on the SCLn line, and drives the SCLn line low when it completes counting. When the IIC detects
the falling edge of the SCLn line, it starts counting the value for the low-level period specified in ICBRL, and then stops
driving the SCLn line, releasing the line when it completes counting. The IIC repeats this process to generate the SCL
clock.
If multiple master devices are connected to the I2C bus, a collision of SCL signals might arise because of contention with
another master device. In such cases, the master devices must synchronize their SCL signals. Because this
synchronization of SCL signals must be bit-by-bit, the IIC is equipped with an SCL synchronization circuit to obtain bitby-bit synchronization of the SCL clock signals by monitoring the SCLn line while in master mode.
When the IIC detects a rising edge on the SCLn line and starts counting the high-level period specified in ICBRH, and
the level on the SCLn line falls because an SCL signal is being generated by another master device, the IIC performs the
following:
1. Stops counting when it detects the falling edge.
2. Drives the level on the SCLn line low.
3. Starts counting the low-level period specified in ICBRL.
When the IIC finishes counting the low-level period, it stops driving the SCLn line low. If the low-level period of the
SCL clock signal from the other master device is longer than the low-level period set in the IIC, the low-level period of
the SCL signal is extended. When the low-level period for the other master device ends, the SCL signal rises because the
SCLn line is released. When the IIC finishes outputting the low-level period of the SCL clock, the SCLn line is released
and the SCL clock rises. That is, when SCL signals from more than one master are contending, the high-level period of
the SCL signal is synchronized with that of the clock with the narrower period, and the low-level period of the SCL
signal is synchronized with that of the clock with the broader period. However, such synchronization of the SCL signal is
only enabled when the SCLE bit in ICFER is set to 1.
[SCL clock generation]
Rising of SCL detected
(High-level period count start)
Compare match
(Counter clear, low-drive start)
ICBRH
ICBRH
ICBRH
SCLn
ICBRL
ICBRL
Falling of SCLn detected
(Low-level period count start)
[SCL synchronization]
Compare match
(Counter clear, SCLn line released)
Counter clear
ICBRH
Counter clear
Low-level output of
other master device
Low-level output of
other master device
ICBRH
ICBRH
SCLn
ICBRL
ICBRL
ICBRL
ICBRH: I2C Bus Bit Rate High-Level Register (SCL clock high-level period counter)
ICBRL: I2C Bus Bit Rate Low-Level Register (SCL clock low-level period counter)
Figure 30.21
Generation and synchronization of SCL signal from IIC
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.5
SDA Output Delay Function
The IIC module provides a function for delaying output on the SDA line. The delay can be applied to all output on the
SDA line, including issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals.
With this function, SDA output is delayed from the detection of a falling edge of the SCL signal to ensure that the SDA
signal is output within the interval during which the SCL clock is low. This approach helps prevent erroneous operation
of communications devices, with the aim of satisfying the 300-ns minimum data-hold time requirement of the SMBus
specification. The output delay function is enabled by setting the SDDL[2:0] bits in ICMR2 to any value other than 000b,
and disabled by setting the same bits to 000b.
When the SDA output delay function is enabled, for example, the DLCS bit in ICMR2 selects the clock source for the
SDA output delay counter, either as the internal base clock (IICΦ) for the IIC module or as the internal base clock
divided by two (IICΦ/2). The counter counts the number of cycles set in the SDDL[2:0] bits in ICMR2. When the delay
count is reached, the IIC module places the required output (start, restart, or stop condition, data, or an ACK or NACK
signal) on the SDA line.
Analog noise filter delay time + PCLKB sampling error (1 PCLKB (max))
Digital noise filter delay time (NFE, NF[1:0] settings = 0.5 PCLKB (min), 1 IIC to 4 IIC (max))
Transmit mode
SDA output delay time (DLCS, SDDL[2:0] settings = 0 (min) to 14 IIC (max))
S
SDA output release timing
8
9
SCLn
b0
b7 to b1
SDAn
ACK/NACK
SDA output delay
Receive mode
SDA output release timing
1 to 7
8
9
P
SCLn
SDAn
b7 to b1
b0
ACK/NACK
SDA output delay
Master mode
ICBRH
SCLn
ST
ICBRL
ICBRH
1
b7
SDAn
ICBRL
ICBRL
2 to 8
b6 to b0
*1
9
ICBRH
RS
ICBRH
ICBRL
1 to 9
ICBRL
SP
ACK/NACK
*1
*1
BBSY
ST
SDA output delay
Note 1.
The output delay function is set by the DLCS and SDDL[2:0] bits when a start (ST), restart (RS), or stop (SP) condition
is issued.
Figure 30.22
SDA output delay function
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.6
Digital Noise Filter Circuits
The internal circuitry sees the states of the SCLn and SDAn pins through analog and digital noise-filter circuits. Figure
30.23 shows a block diagram of the digital noise-filter circuit.
The on-chip digital noise-filter circuit of the IIC consists of four flip-flop circuit stages connected in series, and a matchdetection circuit.
The number of valid stages in the digital noise filter is selected in the NF[1:0] bits in ICMR3. The selected number of
valid stages determines the noise-filtering capability as a period from 1 to 4 IICΦ cycles.
The input signal to the SCLn pin (or SDAn pin) is sampled on falling edges of the IICΦ signal. When the input signal
level matches the output level of the number of valid flip-flop circuit stages as selected in the NF[1:0] bits in ICMR3, the
signal level is seen in the subsequent stage. If the signal levels do not match, the previous value is saved.
If the ratio between the frequency of the internal operating clock (PCLKB) and the transfer rate is small, for example, for
data transfer at 400 kbps with PCLKB = 4 MHz, the digital noise filter might lead to the elimination of the required
signals as noise. In such cases, it is possible to disable the digital noise-filter circuit by setting the ICFER.NFE bit to 0,
and use only the analog noise filter circuit.
Mismatch
D
Match
Q
CLK
Comparator
Four-stage
digital
noise filter
D
Q
CLK
D
Q
CLK
D
Q
D
CLK
IIC
Q
CLK
D
PCLKB
Q
CLK
NF[1:0]
NFE
NFE:
Digital Noise Filter Circuit Enable bit
NF[1:0]: Noise Filter Stage Select bits
Figure 30.23
Digital noise filter circuit block diagram
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Oct 29, 2018
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.7
Address Match Detection
The IIC can set three unique slave addresses in addition to the general call address and host address. The slave addresses
can be 7-bit or 10-bit slave addresses.
30.7.1
Slave-Address Match Detection
The IIC can set three unique slave addresses and has a slave address detection function for each unique slave address.
When the SARyE bit (y = 0 to 2) in ICSER is set to 1, the slave addresses set in SARUy and SARLy (y = 0 to 2) can be
detected.
When the IIC detects a match of the set slave address, the associated AASy flag (y = 0 to 2) in ICSR1 is set to 1 on the
rising edge of the 9th SCL clock cycle, and the RDRF flag in ICSR2 or the TDRE flag in ICSR2 is set to 1 by the
subsequent R/W# bit. This causes a receive data full interrupt (IICn_RXI) or transmit data empty interrupt (IICn_TXI) to
be generated. The AASy flag identifies which slave address is specified.
Figure 30.24 to Figure 30.26 show the AASy flag set timing in three cases.
7-bit address format: slave reception
S
1
2
3
4
5
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
7-bit slave address
BBSY
Data (DATA 1)
Data (DATA 2)
ACK
Address match
AASy
Receive data (7-bit address)
TRS
Receive data (DATA 1)
TDRE
RDRF
Read ICDRR
(Dummy read [7-bit address])
Read ICDRR
(DATA 1)
7-bit address format: slave transmission
S
1
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
7-bit slave address
BBSY
Data (DATA 1)
Data (DATA 2)
ACK
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(DATA 1)
Figure 30.24
Write data to ICDRT
(DATA 2)
Write data to ICDRT
(DATA 3)
AASy flag set timing with 7-bit address format
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
10-bit address format: slave reception
S
1
2
3
4
5
1
1
1
1
0
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Upper 2 bits
10-bit slave address (lower 8 bits)
Data
ACK
BBSY
Address match
AASy
Receive data (lower addresses)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [lower addresses])
10-bit address format: slave transmission
S
1
2
3
4
5
1
1
1
1
0
6
7
8
9
1 to 8
9
Sr
1
2
3
4
5
1
1
1
1
0
6
7
8
9
R
ACK
SCLn
SDAn
Upper 2 bits
W
ACK Lower 8 bits ACK
BBSY
R
Upper 2 bits
Address match
AASy
Receive data (lower addresses)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [lower addresses])
Figure 30.25
AASy flag set timing with 10-bit address format
In the case of SAR0L: 7-bit address, SAR1L: 7-bit address, SAR2: 10-bit address (1)
S
1
2
3
4
5
6
7
8
9
1 to 8
9
DATA
ACK
Sr
1
2
3
4
5
6
7
8
9
SCLn
SDAn
R/W# ACK
7-bit slave address (SAR0L)
R/W# ACK
7-bit slave address (SAR1L)
BBSY
Address mismatch
AAS0
Address match
Address match
AAS1
AAS2
In the case of SAR0L: 7-bit address, SAR1L: 7-bit address, SAR2: 10-bit address (2)
S
1
2
3
4
5
6
7
8
9
1 to 8
9
DATA
ACK
Sr
1
2
3
4
5
1
1
1
1
0
6
7
8
9
W
ACK
SCLn
SDAn
R/W# ACK
7-bit slave address (SAR1L)
Upper 2 bits
BBSY
AAS0
AAS1
Address match
Address mismatch
AAS2
In the case of SAR0L: 7-bit address, SAR1L: 7-bit address, SAR2: 10-bit address (3)
S
1
2
3
4
5
1
1
1
1
0
6
7
8
9
1 to 8
9
Sr
1
2
3
4
5
6
7
8
9
SCLn
SDAn
Upper 2 bits
W
ACK Lower 8 bits ACK
7-bit slave address (SAR0L)
R/W# ACK
BBSY
Address match
AAS0
AAS1
AAS2
Figure 30.26
Address match
Address mismatch
AASy flag set and clear timing with 7-bit and 10-bit address formats mixed
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.7.2
Detection of General Call Address
The IIC provides detection of the general call address (0000 000b + 0 [W]). General call address detection is enabled by
setting the GCAE bit in ICSER to 1.
If the address received after a start or restart condition is issued is 0000 000b + 1[R] (start byte), the IIC recognizes this
as the address of a slave device with an all-zero address, but not as the general call address.
When the IIC detects the general call address, both the GCA flag in ICSR1 and the RDRF flag in ICSR2 set to 1 on the
rising edge of the 9th cycle of SCL clock. This leads to the generation of a receive data full interrupt (IICn_RXI). The
value of the GCA flag can be checked to confirm that the general call address is transmitted.
Operation after detection of the general call address is the same as normal slave receive operation.
General call address reception
S
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Data (DATA 1)
Data (DATA 2)
ACK
BBSY
AAS0
AAS1
Receive data (7-bit address)
Receive data (DATA 1)
AAS2
GCA
General call address match (0000 000b + W)
RDRF
Read ICDRR
(Dummy read [7-bit address])
Figure 30.27
30.7.3
Read ICDRR
(DATA 1)
Timing of GCA flag setting during reception of general call address
Device ID Address Detection
The IIC module provides detection of the device ID address in compliance with the I2C bus specification, revision 03.
When the IIC receives 1111 100b as the first byte after a start or restart condition is issued with the DIDE bit in ICSER
set to 1, the IIC recognizes the address as a device ID, sets the DID flag in ICSR1 to 1 on the rising edge of the 8th SCL
clock cycle when the subsequent R/W# bit is 0, and then compares the second and subsequent bytes with its own slave
address. If the address matches the value in the slave address register, the IIC sets the associated AASy flag (y = 0 to 2)
in ICSR1 to 1.
When the first byte received after the issue of a start or restart condition matches the device ID address (1111 100b) again
and the subsequent R/W# bit is 1, the IIC does not compare the second and subsequent bytes and sets the ICSR2.TDRE
flag to 1.
In the device ID address detection function, the IIC sets the DID flag to 0 if a match with the IIC slave address is not
obtained or a match with the device ID address is not obtained after a match with the IIC slave address, and a restart
condition is not detected. If the first byte after detection of a start or restart condition matches the device ID address
(1111 100b) and the R/W# bit is 0, the IIC sets the DID flag to 1 and compares the second and subsequent bytes with the
slave address of the IIC. If the R/W# bit is 1, the DID flag holds the previous value and the IIC does not compare the
second and subsequent bytes. Therefore, the reception of a device ID address can be checked by reading the DID flag
after confirming that TDRE = 1.
Additionally, prepare the device ID fields (3 bytes: 12 bits indicating the manufacturer + 9 bits identifying the part + 3
bits indicating the revision) that must be sent to the host after reception of a continuous device ID field as normal data for
transmission. For details on the information that must be included in device ID fields, contact NXP Semiconductors.
R01UM0010EU0120 Rev.1.20
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Device ID reception
S
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
W
ACK
1
to
8
9
Sr
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
R
ACK
SCLn
SDAn
Address
ACK
BBSY
Slave address match
AASy
Device ID match (1111 100b + R)
Device ID match (1111 100b + W)
DID
Receive data (7-bit address/lower 10 bits)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [7-bit address/lower 10 bits])
When address received after a restart condition is detected does not match the device ID
S
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
W
ACK
1
to
8
9
Sr
1
2
3
4
5
6
7
8
9
R/W#
ACK
SCLn
SDAn
Address
7-bit slave address (other station)
ACK
BBSY
Slave address match
Receive data (7-bit address/lower 10 bits)
Slave address mismatch
AASy
Device ID mismatch
Device ID match (1111 100b + W)
DID
RDRF
Read ICDRR
(Dummy read [7-bit address/lower 10 bits])
When address before the device ID + R does not match the slave address
S
1
2
3
4
5
6
7
8
1
1
1
1
1
0
0
R
9
1
to
8
9
Sr
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
R
NACK
SCLn
SDAn
NACK
NACK
Comparing the second and the following
bytes is stopped.
BBSY
AASy
DID
Device ID match (1111 100b + R)
Device ID match (1111 100b + R)
The previous value is retained
TDRE
RDRF
Figure 30.28
AASy/DID flag set/clear timing during reception of device ID
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.7.4
Host Address Detection
The IIC provides host address detection while the SMBus is operating. When the HOAE bit in ICSER is set to 1 while
the SMBS bit in ICMR3 is 1, the IIC can detect the host address (0001 000b) in slave receive mode (ICCR2.MST and
ICCR2.TRS bits = 00b).
When the IIC detects the host address, the HOA flag in the ICSR1 register is set to 1 on the rising edge of the 9th SCL
clock cycle. At the same time, the RDRF flag in the ICSR2 register is set to 1 if the R/W# bit is 0. This causes a receive
data full interrupt (IICn_RXI) to be generated. The HOA flag indicates that the host address was detected.
If the bit following the host address (0001 000b) is a read bit (R/W# bit = 1), the IIC can also detect the host address.
After the host address is detected, the IIC operates in the same manner as in normal slave operation.
Host address reception
S
1
2
3
4
5
6
7
8
9
0
0
0
1
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Data (DATA 1)
Data (DATA 2)
ACK
BBSY
AAS0
Receive data (7-bit address)
AAS1
Receive data (DATA 1)
AAS2
HOA
Host address match (0001 000b)
RDRF
Read ICDRR
(Dummy read [7-bit address])
Figure 30.29
30.8
Read ICDRR
(DATA 1)
HOA flag set timing during reception of host address
Wakeup Function
The IIC provides a wakeup function that causes the MCU to transition from Software Standby mode to normal operation.
The wakeup function enables the reception of data when the system clock is stopped, and generates a wakeup interrupt
signal on a match of the slave address of the received data. This wakeup interrupt signal triggers the return to normal
operation.
The wakeup function has four operation modes:
Normal wakeup mode 1
Normal wakeup mode 2
Command recovery mode
EEP response mode.
Table 30.9 describes the behavior in these modes.
Table 30.9
Wakeup operation modes
Operation mode
ACK response timing
ACK response before wakeup
SCL state during wakeup
Normal wakeup mode 1
Before wakeup
ACK
Fixed low
Normal wakeup mode 2
After wakeup
Before wakeup: no response
After wakeup: ACK response
Fixed low
Command recovery mode
Before wakeup
ACK
Open
EEP response mode
Before wakeup
NACK
Open
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Precautions on the use of the wakeup function
Disable the wakeup function (WUE = 0) after a wakeup interrupt triggers the transition from Software Standby
mode to normal operation
Do not change the content of the IIC registers while WUF = 0, even if the wakeup interrupt recovers the system
clock. Specify the register settings after confirming that WUF = 1.
Set WUE = WUIE = 1 and MST = TRS = 0 (slave reception mode) before entering Software Standby mode
Do not transition to Software Standby mode while BBSY = 1
The wakeup function supports the 7-bit slave address of slave address register SARL0, the general call address, and
the host address. 10-bit slave addresses, SARL1 and SARL2, are not supported.
When the wakeup function is enabled, disable the interrupts selectable in the TIE, TEIE, RIE, NAKIE, SPIE, STIE,
ALIE, and TMOIE bits in the ICIER register
When the wakeup function is enabled, do not use the timeout function
If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for example
IRQn, the WUF flag is not set to 1.
30.8.1
Normal Wakeup Mode 1
This section describes the behavior, timing, and an example operation in normal wakeup mode 1.
In normal wakeup mode 1, a wakeup interrupt triggered by the match of the slave address initiates the transition to
normal operation as follows:
Before wakeup:
ACK is sent in response to the data received with its own slave address of the IIC.
During wakeup:
After wakeup:
ACK response is made on the 9th clock cycle of SCL, after which SCL is held low.*1
Normal operation continues.
If the slave address does not match, the SCL line is not held low after the 9th clock cycle of SCL, and the slave
operation continues.
Figure 30.30 shows an operation example, and Figure 30.32 shows the detailed timing.
Note 1. Between the 9th clock cycle and 1st clock cycle during wakeup, WAIT = 1 is invalid.
If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for example the
IRQn, the WUF flag is not set to 1. Figure 30.31 shows an operation example.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
IIC normal operation
No
BBSY = 0
*1
[1] Wait until I2 C bus is free and stay in standby state.
Yes
MST = 0 & TRS = 0
(Slave receive)
No
Yes
IICRST = 0 (& ICE = 1)
[2] Negate internal reset (if asserted).
WUACK Setting, WUIE = 1
WUE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt.
[4] Enable wakeup function.
WUSEN = 0
[5] Set WUSEN to 0.
No
WUASYF = 1
Yes
ICIER = 00h
[6] Disable all interrupt requests except WUI.
WFI instruction
[7] Stop PCLKB to IIC. IIC continues to receive.
Wakeup interrupt
WUF = 1
No
WUSEN = 1
WUSYF = 1
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match).
[9] Wait for WUF = 1.
[10] Set WUSEN to 1.
No
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling.
WUF = 0
WUF = 0
No
Yes
WUIE = 0
[12] Disable wakeup interrupt.
WUE = 0
[13] Disable wakeup function.
TRS = 1
No
Slave receive processing
Yes
Slave transmit processing
Note 1. Do not issue start condition between BBSY = 0 and executing WFI instruction.
Figure 30.30
Note:
Example operation of normal wakeup mode 1 when wakeup is triggered by a wakeup interrupt on
match of the slave address
See Precautions on the use of the wakeup function.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
WUE = 1
WUSEN = 0
[1] Start PCLKB to IIC due to other return factor (IRQ).
No
WUASYF = 1
[2] Set WUSEN to 1.
Yes
[3] Disable wakeup interrupts.
ICIER = 00h
[4] Disable wakeup function.
WFI instruction
*1
[5] Reset IIC (ICE = 0 & IICRST = 1).
Start system clock due to
other return factor (IRQ)
WUSEN = 0
[1]
Yes
No
Continue
slave mode?
Yes
No
[2]
WUSEN = 1
WUSYF = 1
Wakeup Interrupt
WUSEN = 1
No
No
WUSYF = 1
Yes
From here, the sequence is the same as
step [9] onward, as in
Figure 30.30 for normal wakeup mode 1,
Figure 30.33 for normal wakeup mode 2.
Yes
WUIE = 0
[3]
WUIE = 0
WUE = 0
[4]
WUE = 0
ICE = 0 & IICRST = 1
[5]
ICE = IICRST = 1, initialize
[6]
ICE = 1 & IICRST = 0
[7]
[6] Reset IIC (internal reset: ICE = 1 & IICRST = 1).
Initial settings.
[7] Negate internal reset.
IIC Normal Operation
Note 1. Before this step, the flow is the same as Figure 30.30.
Figure 30.31
Note:
Example operation of normal wakeup modes 1 and 2 when wakeup is triggered by an interrupt
other than IIC wakeup interrupt, for example, IRQn
For details on the IIC initial settings, see section 30.3.2, Initial Settings.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Normal Wakeup Mode 1
As with the normal operation, ACK response when there is match with own slave address; SCL held low until return.
Before wakeup: Own slave ACK response. / During wakeup: SCL low hold after 9th SCL. / After wakeup: Continue normal operation.
Active
Software Standby Active
(During wakeup)
Software Standby (Before wakeup)
Active (After wakeup)
Continue to receive after returning (WAIT = 0)
WFI command
ST
1
SCL
WUACK = 0 (ACK Return)
2
3
4
5
6
7
SLAVE ADDRESS
SDA
8
W
ICDRR read
9
Low hold period
1
2
3
4
5
6
7
8
WUF 0 clear
(0 write after 1 read)
9
DATA
ACK
ICDRR read
SP
ACK
WUF
AAS0
RDRF
TRS
Continue to transmit after returning (WAIT = 0)
WUF 0 clear
ICDRT write
WUACK = 0 (ACK Return)
SCL
1
2
SDA
3
4
5
6
SLAVE ADDRESS
7
8
9
Low hold period
1
2
ICDRT write
3
R ACK
4
5
6
7
DATA
8
9
ACK
1
SP
2
3
4
5
DATA
6
7
8
9
NACK
WUF
AAS0
TDRE
TRS
Asynchronous Synchronous Switching period
Figure 30.32
30.8.2
Timing of normal wakeup mode 1
Normal Wakeup Mode 2
This section describes the behavior, timing, and an example operation in normal wakeup mode 2.
In normal wakeup mode 2, a wakeup interrupt triggered by a match of the slave address initiates the transition to normal
operation as follows:
Before wakeup:
No response to data received with its own slave address until the end of the 8th SCL cycle.
During wakeup:
SCL line held low during the 8th and 9th clock cycles.
After wakeup:
ACK returns on the 9th clock cycle of SCL and normal operation continues.
If the slave address does not match, the SCL line is not held low after the 8th SCL clock cycle, and the slave
operation continues.
Figure 30.33 shows an example operation in normal wakeup mode 2 and Figure 30.34 shows the detailed timing.
If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, such as the IRQ,
for example, the WUF flag is not set to 1. Follow the operation shown in Figure 30.31.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
IIC normal operation
No
BBSY = 0
*1
[1] Wait until I2C bus is free and stay in standby state.
Yes
MST = 0 & TRS = 0
(Slave receive)
No
Yes
IICRST = 0 (& ICE = 1)
[2] Negate internal reset (if asserted).
WUACK Setting, WUIE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt.
WUE = 1
[4] Enable wakeup function.
WUSEN = 0
[5] Set WUSEN to 0.
No
WUASYF = 1
Yes
ICIER = 00h
[6] Disable all interrupt requests except WUI.
WFI instruction
[7] Stop PCLKB to IIC. IIC continues to receive.
Wakeup interrupt
WUF = 1
No
[9] Wait for WUF = 1.
[10] Set WUSEN to 1.
WUSEN = 1
WUSYF = 1
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match).
No
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling.
WUF = 0
WUF = 0
No
Yes
WUIE = 0
[12] Disable wakeup interrupt.
WUE = 0
[13] Disable wakeup function.
TRS = 1
No
Slave receive processing
Yes
Slave transmit processing
Note 1.
Do not issue start condition between BBSY = 0 and executing WFI instruction.
Figure 30.33
Note:
Example operation of normal wakeup mode 2 when wakeup is triggered by a wakeup interrupt on
match of the slave address
See Precautions on the use of the wakeup function.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Normal Wakeup Mode 2
IIC holds SCL low until wakeup after its own slave match. ACK response after wakeup.
Before wakeup: Own slave – response. During wakeup: SCL low hold between 8th and 9th SCL. After wakeup: Continue normal operation after own slave ACK response.
Active
Software Standby Active
(during wakeup)
Software Standby (before wakeup)
Active (after wakeup)
Continue to receive after returning (WAIT = 0)
WFI command
ST
SCL
ICDRR read
WUF = 0 clear
1
2
3
4
5
6
7
SLAVE ADDRESS
SDA
8
W
Low hold period
NACK
9
1
2
3
4
5
ACK
6
7
8
ICDRR read
SP
9
DATA
ACK
WUF
AAS0
RDRF
TRS
WUF = 0 clear
Continue to transmit after returning (WAIT = 0)
1
SCL
2
SDA
3
4
5
6
SLAVE ADDRESS
ICDRT write
7
8
R
Low hold period
NACK
9
1
2
ICDRT write
3
ACK
4
5
DATA
6
7
8
9
1
SP
2
3
4
ACK
5
DATA
6
7
8
9
N ACK
WUF
AAS0
TDRE
TRS
Asynchronous Synchronous Switching period
Figure 30.34
30.8.3
Timing of normal wakeup mode 2
Command Recovery Mode and EEP Response Mode (Special Wakeup Modes)
This section describes the behavior, timing, and example operations of the command recovery and EEP response modes.
In the command recovery and EEP response modes, the SCL line is not held low during the wakeup period (after the rise
of the 9th clock cycle of SCL). Therefore, the other IIC devices can use the I2C bus during this period.
A wakeup interrupt triggered by the match of the slave address initiates the transition to normal operation as follows:
Before wakeup:
During wakeup:
After wakeup:
In response to the data received with its own slave address, the IIC returns ACK (command
recovery mode) or NACK (EEP response mode).
The SCL line is not held low.
Normal operation continues after IIC initialization.
If the slave address does not match, the slave operation continues.
For an example operation in command recovery mode and EEP response mode, see Figure 30.35.
Figure 30.37 provides the detailed timing.
Note:
Note:
Because the SCL line is not held low during wakeup, transmission or reception of the data that follows the slave
address is not possible.
The command recovery and EEP response modes are internal reset states (ICE = IICRST = 1). Therefore, the
match of the slave address does not set the flags HOA, GCA, AAS0, AAS1, and AAS2 in the ICSR1 register.
If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, such as the IRQn
for example, the WUF flag is not set to 1. Follow the operation shown in Figure 30.36.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
IIC normal operation
No
BBSY = 0?
*1
[1] Wait until I2C bus is free and stay in standby state.
Yes
MST = 0 & TRS = 0?
(Slave receive)
No
Yes
IICRST = 1 & ICE = 1
[2] Internal reset is asserted.
WUACK setting, WUIE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt.
WUE = 1
[4] Enable wakeup function.
[5] Set WUSEN to 0.
WUSEN = 0
WUASYF = 1?
No
Yes
ICIER = 00h
[6] Disable all interrupt requests except WUI.
WFI instruction
[7] Stop PCLKB to IIC. IIC continues to receive.
Wakeup interrupt
WUF = 1?
No
[9] Wait for WUF = 1.
[10] Set WUSEN = 1.
WUSEN = 1
WUSYF = 1?
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match).
No
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling.
WUF = 0
WUF = 0?
No
Yes
WUIE = 0
[12] Disable wakeup interrupt.
WUE = 0
[13] Disable wakeup function.
ICE = 0 & IICRST = 1
ICE = IICRST = 1; Initialize
ICE = 1 & IICRST = 0
[14] Reset IIC (ICE = 0 & IICRST = 1).
[15] Reset IIC (internal reset: ICE = 1 & IICRST = 1). Initial settings.
[16] Negate internal reset.
IIC Normal Operation
Note 1.
Figure 30.35
Note:
Do not issue start condition between BBSY = 0 and executing WFI instruction.
Example operation of command recovery and EEP response modes when wakeup is triggered by
a wakeup interrupt on a match of the slave address
See Precautions on the use of the wakeup function.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
WUE = 1
W USEN = 0
[1] Start PCLKB to IIC due to other return factor (IRQ).
W UASYF = 1?
[2] Set WUSEN to 1.
No
[3] Disable wakeup interrupts.
[4] Disable wakeup function.
Yes
ICIER = 00h
[5] Reset IIC (ICE = 0 & IICRST = 1).
W FI instruction
Start system clock supply by
other return factor (IRQ)
[1]
WUSEN = 0?
Yes
No
No
Continue slave mode
in Command recovery mode/
EEP response mode?
[2]
W USEN = 1
Yes
W USYF = 1?
No
W ake-Up Interrupt
From here, the sequence is same as step [9] onwards, as
in Figure 30.35.
Yes
W UIE = 0
[3]
WUE = 0
[4]
ICE = 0 & IICRST = 1
[5]
ICE = IICRST = 1, initialize
[6]
ICE = 1 & IICRST = 0
[7]
[6] Reset IIC (internal reset: ICE = 1 & IICRST = 1).
Initial settings.
[7] Negate internal reset.
IIC Normal Operation
Figure 30.36
Note:
Example operation of command recovery mode and EEP response mode when wakeup is
triggered by an interrupt other than IIC wakeup interrupt, for example, the IRQn
For details on the IIC initial settings, see section 30.3.2, Initial Settings.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
Command recovery mode/ EEP response mode
Reply ACK / NACK in response to own slave address.
Reply ACK in response to own slave again after IICRST release after wakeup.
Before wakeup: Own slave ACK/NACK response. During wakeup: No SCL low hold. After wakeup: Continue normal operation.
Active
Software Standby Active
(During wake-up)
Software Standby (Before wake-up)
Active (After wake-up)
WFI command
SCL
1
2
SDA
3
4
SLAVE ADDRESS
5
6
7
8
R/W#
9
1
2
A/NA
3
4
5
6
DATA
0
BC
0
BBSY
START
WUF
AAS0
TDRE/
RDRF
Asynchronous Synchronous Switching period
Figure 30.37
30.8.4
Timing of command recovery mode and EEP response mode
Precautions for WFI Instruction Execution
In the wakeup function examples shown in Figure 30.30, Figure 30.33, and Figure 30.35, make sure that the start
condition is not issued during the period from the setting of BBSY = 0 to the execution of the WFI instruction.
When a start condition is issued during this period, NACK is returned after the reception of the first byte of the first data
block. Detection of the start or restart condition then enables the wakeup function.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.9
Automatic Low-Hold Function for SCL
30.9.1
Function to Prevent Wrong Transmission of Transmit Data
If the I2C Bus Shift Register (ICDRS) is empty when data has not been written to the I2C Bus Transmit Data Register
(ICDRT) with the IIC in transmission mode (ICCR2.TRS = 1), the SCLn line is automatically held low over the
subsequent intervals. This low-hold period is extended until the transmit data is written, which prevents the unintended
transmission of erroneous data.
Master transmit mode:
Low-level interval after a start or restart condition is issued
Low-level interval between the 9th clock cycle of one transfer and the 1st clock cycle of the next.
Slave transmit mode:
Low-level interval between the 9th clock cycle of one transfer and the 1st clock cycle of the next.
Automatic low-hold
(to prevent wrong
transmission)
1
2
Master transmit mode
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
Automatic low-hold (to prevent wrong transmission)
8
9
W
ACK
1
2
3
4
5
6
7
8
9
SCLn
SDAn
7-bit slave address
Data (DATA 1)
ACK
BBSY
Transmit data (7-bit address + W)
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(7-bit address + W)
Write data to ICDRT
(DATA 1)
Slave transmit mode
S
1
Write data to ICDRT
(DATA 2)
Automatic low-hold (to prevent wrong transmission)
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
Automatic low-hold
(to prevent wrong
transmission)
1
2
3
SCLn
SDAn
7-bit slave address
BBSY
Data (DATA 1)
ACK
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(DATA 1)
Figure 30.38
30.9.2
Write data to ICDRT
(DATA 2)
Automatic low-hold operation in transmit mode
NACK Reception Transfer Suspension Function
This function suspends transfer operation when NACK is received in transmit mode (the ICCR2.TRS bit is 1). This
function is enabled when the NACKE bit in ICFER is set to 1 (transfer suspension enabled). If the next transmit data is
written (ICSR2.TDRE flag is 0) when the NACK is received, the next data transmission on the falling edge of the 9th
SCL clock cycle is automatically suspended. This prevents the SDAn line output level from being held low when the
MSB of the next transmit data is 0.
If the transfer operation is suspended by this function (ICSR2.NACKF flag is 1), transmit and receive operations are
discontinued. To restore transmit and receive operations, set the NACKF flag to 0. In master transmit mode, after a
restart or stop condition is issued, set the NACKF flag to 0, and then issue a start condition again.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
[Master transmit mode]
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
Bus free time (ICBRL)
8
9
P
S
1
2
3
4
5
6
7
8
9
W
ACK
SCLn
SDAn
W
7-bit slave address
BBSY
Transmit data
(7-bit address + W)
AASy
NACK
Transfer suspended
7-bit slave address
Transmit data
(7-bit address + W)
Transmit data (DATA 1)
Transmit data (DATA 1)
TRS
TDRE
NACKF
Write data to ICDRT register Write data to ICDRT
(7-bit address + W)
register (DATA 1)
Write 1
to SP bit
[Slave transmit mode]
S
1
Clear
NACKF flag
Write data to ICDRT
register
(7-bit address + W)
Write data to ICDRT
register (DATA 1)
Automatic low-hold (to prevent wrong transmission)
2
3
4
5
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
P
Bus free time
(ICBRL)
SCLn
SDAn
7-bit slave address
Data (DATA 1)
Transfer suspended
BBSY
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
NACKF
Write data to ICDRT
register (DATA 1)
Figure 30.39
30.9.3
Write data to ICDRT
register (DATA 2)
Write 1 to SP bit
Clear NACKF flag
Suspension of data transfer when NACK is received, when NACKE = 1
Function to Prevent Failure to Receive Data
If response processing is delayed when receive data (ICDRR) read is delayed for a period of one transfer frame or more
with receive data full (ICSR2.RDRF = 1) in receive mode (ICCR2.TRS = 0), the IIC holds the SCLn line low
automatically immediately before the next data is received to prevent failure to receive data.
This function is also enabled even if the read processing of the final receive data is delayed and, in the meantime, the IIC
slave address is designated after a stop condition is issued. This function does not interfere with other communication
because the IIC does not hold the SCLn line low when a mismatch with its own slave address occurs after a stop
condition is issued.
Periods in which the SCLn line is held low can be selected with a combination of the WAIT and RDRFS bits in the
ICMR3 register.
(1)
1-byte receive operation and automatic low-hold function using the WAIT bit
When the WAIT bit in the ICMR3 register is set to 1, the IIC performs a 1-byte receive operation using the WAIT bit
function. Additionally, when the ICMR3.RDRFS bit is 0, the IIC automatically sends the ICMR3.ACKBT bit value for
the acknowledge bit in the period from the falling edge of the 8th SCL clock cycle to the falling edge of the 9th SCL clock
cycle, and automatically holds the SCLn line low on the falling edge of the 9th SCL clock cycle using the WAIT bit
function. This low-hold is released by reading data from the ICDRR register, which enables byte-wise receive operation.
The WAIT bit function is enabled for receive frames after a match with the IIC slave address, including the general call
address and host address, is obtained in master or slave receive mode.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
(2)
1-byte receive operation (ACK/NACK transmission control) and automatic low-hold function
using the RDRFS bit
When the RDRFS bit in the ICMR3 register is set to 1, the IIC performs a 1-byte receive operation using the RDRFS bit
function. When the RDRFS bit is set to 1, the RDRF (receive data full) flag in ICSR2 is set to 1 on the rising edge of the
8th SCL clock cycle, and the SCLn line is automatically held low on the falling edge of the 8th SCL clock cycle. This
low-hold is released by writing to the ACKBT bit in ICMR3, but cannot be released by reading data from ICDRR, which
enables receive operation through the ACK or NACK transmission control based on the data received in byte units.
The RDRFS bit function is enabled for receive frames after a match with the IIC slave address, including the general call
address and host address, is obtained in master receive mode or slave receive mode.
Automatic low-hold
(to prevent failure to receive data)
[RDRFS = 0, WAIT = 0]
9
SCLn
SDAn
1
2
3
4
ACK
5
6
7
8
9
1
2
3
4
ACK
Data
5
6
7
8
9
1
ACK
Data
2
3
4
Data
RDRF
Read ICDRR
[RDRFS = 0, WAIT = 1]
9
Read ICDRR
Automatic low-hold (WAIT)
1
2
3
4
5
Read ICDRR
Automatic low-hold (WAIT)
6
7
8
9
1
2
3
4
5
6
7
8
9
Automatic lowhold (WAIT)
1
SCLn
SDAn
ACK
ACK
Data
ACK
Data
RDRF
Read ICDRR
Read ICDRR
[RDRFS = 1, WAIT = 0]
2
3
Read ICDRR
Automatic low-hold
(to prevent failure to
receive data)
8
Automatic low-hold (RDRFS)
4
5
6
7
8
9
1
2
3
4
5
6
7
Automatic lowhold (RDRFS)
9
1
SCLn
SDAn
ACK
Data
Data
ACK
RDRF
ACKBT
Write 0 to ACKBT
[RDRFS = 1, WAIT = 1]
2
3
4
5
Automatic low-hold
(RDRFS)
6
7
8
Read ICDRR Read ICDRR
Automatic low-hold (WAIT)
9
1
2
3
4
5
6
7
Write 0 to ACKBT
Automatic low-hold
(RDRFS)
9
1
8
SCLn
SDAn
Data
ACK
Data
ACK
RDRF
ACKBT
Write 0 to ACKBT
Figure 30.40
Read ICDRR
Read ICDRR Write 0 to ACKBT
Automatic low-hold operation in receive mode using RDRFS and WAIT bits
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S3A1 User’s Manual
30. I2C Bus Interface (IIC)
30.10 Arbitration-Lost Detection Functions
In addition to the normal arbitration-lost detection function defined by the I2C bus standard, the IIC has functions to
prevent double-issue of a start condition, detect arbitration-lost during transmission of NACK, and detect arbitration-lost
in slave transmit mode.
30.10.1
Master Arbitration-Lost Detection (MALE Bit)
IIC drives the SDAn line low to issue a start condition. However, if the SDAn line was already driven low by another
master device issuing a start condition, the IIC regards its own start condition issue as an error and considers this a loss in
arbitration. Priority is given to transfer by the other master device. Similarly, if a request to issue a start condition is made
by setting the ST bit in ICCR2 to 1 while the bus is busy (BBSY flag = 1 in ICCR2), the IIC regards this as a doubleissuing-of-start-condition error and considers itself to have lost the arbitration. This prevents a failure of transfer
resulting from a start condition issued while transfer is in progress.
When a start condition is issued successfully, if the transmit data including the address bits (internal SDA output level)
and the level on the SDAn line do not match, the IIC loses the arbitration.
After a loss in arbitration of mastership, the IIC immediately enters slave receive mode. If a slave address, including the
general call address, matches its own address at this time, the IIC continues in slave operation.
A loss in arbitration of mastership is detected when the following conditions are met while the MALE bit in ICFER
register is 1 (master arbitration-lost detection enabled).
[Master arbitration-lost conditions]
Mismatching of the internal level for output on SDA and the level on the SDAn line after a start condition was
issued by setting the ST bit in ICCR2 to 1 while the ICCR2.BBSY flag is set to 0 (erroneous issuing of a start
condition)
Setting of the ICCR2.ST bit to 1 (start condition double-issue error) while the BBSY flag is 1
When the transmit data excluding acknowledge (internal SDA output level) does not match the level on the SDAn
line in master transmit mode (MST and TRS bits = 11b in ICCR2).
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
[When slave addresses conflict]
1
S
2
3
4
5
6
Transmit data mismatch
(arbitration lost)
Release SCL/SDA
SCLn
SDAn
1
S
1
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
0
ACK
Data
BBSY
Data
Address match
Address mismatch
MST
TRS
AL
AASy
TDRE
Clear AL to 0
[When data transmission conflicts after general call address is sent ]
S
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
Transmit data mismatch
(arbitration lost)
5
Release SCL/SDA
SCLn
SDAn
S
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
ACK
0
Data
BBSY
MST
Receive data
TRS
AL
GCA
General call address match (0000 000b + W)
Clear AL to 0
RDRF
Read ICDRR
Figure 30.41
Examples of master arbitration-lost detection when MALE = 1
Bus free (BBSY = 0) start condition issuance (ST = 1) error
Bus busy (BBSY =1) start condition issuance (ST = 1) error
SDA mismatch
PCLKB
SCLn
PCLKB
PCLKB
SCLn
SCLn
SDAn
SDAn
SDAn
S
1
S
1
2
S
SCLn
SCLn
SCLn
SDAn
SDAn
SDAn
ST = 1, BBSY = 1
ST = 1, BBSY = 1
BBSY
BBSY
BBSY
MST
MST
MST
TRS
TRS
TRS
AASy
AASy
AASy
ST
ST
ST
AL
AL
AL
Write 1 to ST
Figure 30.42
Write 1 to ST
1
2
6
7
8
9
7-bit/10-bit slave address
R
ACK
1
ST = 1,
BBSY = 1
Write 1 to ST
Arbitration-lost when start condition is issued when MALE = 1
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.10.2
Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit)
This function causes arbitration to be lost if the internal SDA output level does not match the level on the SDAn line
during transmission of NACK in receive mode. Arbitration is lost because of a conflict between NACK and ACK
transmissions when two or more master devices receive data from the same slave device simultaneously in a multimaster system. Such a conflict occurs when multiple master devices send or receive the same information through a
single slave device. Figure 30.43 shows an example of arbitration-lost detection during the transmission of NACK.
NACK transmission mismatch
(arbitration lost)
[Conflict during transmission of NACK (ACK received)]
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
Release SCL/SDA
8
9
SCLn
SDAn
ACK
Data
2
3
4
5
6
7
8
9
Data
1
2
3
4
5
NACK
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Data
ACK
ACK
Data
Data
BBSY
MST
Receive data
TRS
Receive data
AL
RDRFS
RDRF
ACKBT
Write 1 to RDRFS
Figure 30.43
Read ICDRR
Read ICDRR
Write 1 to ACKBT
Clear AL to 0
Example of arbitration-lost detection during transmission of NACK when NALE = 1
The following description explains arbitration-lost detection using an example in which two master devices (master A
and master B) and a single slave device are connected through the bus. In this example, master A receives 2 bytes of data
from the slave device, and master B receives 4 bytes of data from the slave device.
If master A and master B access the slave device simultaneously, because the slave address is identical, arbitration is not
lost in either master A or master B during access to the slave device. Therefore, both master A and master B recognize
that they have obtained the bus mastership and operate as such. Master A sends NACK when it has received 2 final bytes
of data from the slave device. Meanwhile, master B sends ACK because it has not received the required 4 bytes of data.
The NACK transmission from master A and the ACK transmission from master B conflict. In general, if a conflict like
this occurs, master A cannot detect the ACK transmitted by master B and issues a stop condition. The stop condition
issue conflicts with the SCL clock output of master B, which disrupts communication.
When the IIC receives ACK during transmission of NACK, it detects a defeat in conflict with other master devices and
causes arbitration to be lost. If arbitration is lost during transmission of NACK, IIC immediately cancels the slave match
condition and enters slave receive mode. This prevents a stop condition from being issued, preventing a communication
failure on the bus.
Similarly, in the ARP command processing of SMBus, the function to detect loss of arbitration during transmission of
NACK is also available for eliminating the extra clock cycle processing, such as FFh transmission processing, which is
required if the UDID (Unique Device Identifier) of the assigned address does not match in the Get UDID general
processing after the Assign Address command.
The IIC detects arbitration-lost during transmission of NACK when the following condition is met with the NALE bit in
ICFER set to 1 (arbitration-lost detection during NACK transmission enabled).
[Condition for arbitration-lost during NACK transmission]
When the internal SDA output level does not match the SDAn line (ACK is received) during transmission of NACK
(ICMR3.ACKBT = 1).
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S3A1 User’s Manual
30.10.3
Slave Arbitration-Lost Detection (SALE Bit)
This function causes arbitration to be lost if the transmit data and the level on the SDAn line do not match in slave
transmit mode. This arbitration-lost detection function is mainly used when transmitting a UDID (Unique Device
Identifier) over an SMBus.
When the IIC loses slave arbitration, the IIC is immediately released from the slave-matched state and enters slave
receive mode. This function can detect conflicts of data during transmission of UDIDs over an SMBus and eliminates
subsequent redundant processing, or processing for the transmission of FFh.
IIC detects slave arbitration-lost when the following condition is met with the SALE bit in ICFER set to 1 (slave
arbitration-lost detection enabled).
[Condition for slave arbitration-lost]
When transmit data excluding acknowledge (internal SDA output level) does not match the SDAn line in slave
transmit mode (MST and TRS bits = 01b in ICCR2).
Transmit data mismatch
(arbitration lost)
[Conflict during data transmission]
2
3
4
5
6
7
8
9
1
2
3
4
Release SCL/SDA
5
SCLn
SDAn
ACK
Data
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
SCLn
SDAn
Data
ACK
ACK
0
Data
BBSY
MST
TRS
AL
TDRE
Write data to ICDRT
Figure 30.44
Clear AL to 0
Example of slave arbitration-lost detection when SALE = 1
30.11 Start, Restart, and Stop Condition Issuing Function
30.11.1
Issuing a Start Condition
The IIC issues a start condition when the ST bit in ICCR2 is set to 1. When the ST bit is set to 1, a start condition request
is made and the IIC issues a start condition when the BBSY flag in ICCR2 is 0 (bus free state). When a start condition is
issued normally, the IIC automatically shifts to the master transmit mode.
To issue a start condition:
1. Drive the SDAn line low (high level to low level).
2. Ensure that the time set in ICBRH and the start condition hold time elapse.
3. Drive the SCLn line low (high level to low level).
4. Detect low level on the SCLn line and ensure that the low-level period of the SCLn line set in ICBRL elapses.
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S3A1 User’s Manual
30.11.2
Issuing a Restart Condition
The IIC issues a restart condition when the RS bit in ICCR2 is set to 1.
When the RS bit is set to 1, a restart condition request is made, and the IIC issues a restart condition when the BBSY flag
in ICCR2 is 1 (bus busy state) and the MST bit in ICCR2 is 1 (master mode).
To issue a restart condition:
1. Release the SDAn line.
2. Ensure that the low-level period of the SCLn line set in ICBRL elapses.
3. Release the SCLn line (low level to high level).
4. Detect a high level on the SCLn line and ensure that the time set in ICBRL and the restart condition setup time
elapse.
5. Drive the SDAn line low (high level to low level).
6. Ensure that the time set in ICBRH and the restart condition hold time elapse.
7. Drive the SCLn line low (high level to low level).
8. Detect a low level of the SCLn line and ensure that the low-level period of the SCLn line set in ICBRL elapses.
Note:
When issuing restart condition requests, write the slave address to ICDRT after confirming that ICCR2.RS is 0.
Data written while ICCR2.RS is 1 is not forwarded because of the retransmission condition before the
occurrence.
Restart condition issuing operation
Start condition issuing operation
ICBRH
SCLn
SDAn
Hold time
ICBRL
ICBRH
SCLn
S Issue start
condition
SDAn
IIC
IIC
BBSY
BBSY
MST
MST
TRS
TRS
TDRE
TDRE
7 bits address +R/W#
ICDRT
Setup time
ICBRL
ICBRL
ICBRH
Hold time
ICBRL
Sr
Issue restart
condition
9
ACK/NACK
7 bits address +R/W#
ICDRT
START
START
RS
ST
Write 1 to ST bit
Write to ICDRT (7 bits address +R/W#)
Write 1 to RS bit
Accept start condition issuance
Figure 30.45
Write to ICDRT (7 bits address +R/W#)
Accept restart condition issuance
Start or restart condition issue timing using ST and RS bits
Figure 30.46 shows the operation timing when a restart condition is issued after the master transmission.
To issue a restart condition after the master transmission:
1. Initialize the IIC using the details provided in section 30.3.2, Initial Settings.
2. Read the IICR2.BBSY flag to check that the bus is free, and then set the ICCR2.ST bit to 1 (start condition request).
On receiving the request, the IIC issues a start condition. At the same time, the ICSR2.BBSY flag and
ICSR2.START flag are automatically set to 1 and the ST bit automatically sets to 0. If the start condition is detected
and the internal levels for the SDA output state and the levels on the SDAn line match while the ST bit is 1, the IIC
recognizes that a start condition is successfully issued as requested by the ST bit. The MST and TRS bits in ICCR2
automatically set to 1, placing the IIC in master transmit mode. The TDRE flag in ICSR2 also automatically sets to
1 when the TRS bit is set to 1.
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3. Check that the ICSR2.TDRE flag is 1, and then write the value for transmission (the slave address and the R/W# bit)
to ICDRT. After the transmit data is written to ICDRT, the TDRE flag automatically sets to 0, data is transferred
from ICDRT to ICDRS, and the TDRE flag again sets to 1. After the byte containing the slave address and R/W# bit
has been transmitted, the value of the TRS bit is automatically updated to select master transmit or master receive
mode according to the value of the transmitted R/W# bit. If the value in the R/W# bit is 0, the IIC continues in
master transmit mode. If the ICSR2.NACKF flag is 1 at this time, indicating that no slave device recognized the
address or that there was an error in communications, write 1 to ICCR2.SP bit to issue a stop condition. To transmit
data with an address in the 10-bit format, start by writing 1111 0b, the 2 upper bits of the slave address, and W to
ICDRT as the first address transmission. Then, as the second address transmission, write the 8 lower bits of the
slave address to the ICDRT register.
4. After confirming that the TDRE flag in ICSR2 is 1, write data for transmission to the ICDRT register. IIC
automatically holds the SCLn line low until data for transmission is ready, and a restart or a stop condition is issued.
5. After all bytes of data for transmission are written to the ICDRT register, wait until the value of the ICSR2.TEND
flag returns to 1. Then, after checking that the ICSR2.START flag is 1, set the ICSR2.START to 0.
6. Set the ICCR2.RS bit to 1 (restart condition issue request). On receiving the request, IIC issues a restart condition.
7. After checking that the ICSR2.START flag is 1, write the value for transmission (the slave address and the R/W#
bit) to the ICDRT register.
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
8
9
1
2
3
b0
ACK
b7
b6
b5
4
5
6
7
8
9
b4
b3
b2
b1
b0
ACK
Sr
1
SCL0
SDA0
7-bit slave address
W
b7
Data (DATA 1)
7-bit slave address
BBSY
MST
TRS
Transmit data (7-bit address + W)
Transmit data (DATA 1)
Transmit data (7-bit address + R)
TDRE
TEND
RDRF
Data (DATA 1)
7-bit address + W
ICDRT
7-bit address + W
ICDRS
7-bit address + R
Data (DATA 1)
7-bit address + R
XXXX (Initial value/Last data for reception)
ICDRR
“0”(ACK)
ACKBT
“X”(ACK/NACK)
ACKBR
“0”(ACK)
“0”(ACK)
START
ST
RS
Write data to
Write data to
ICDRT
Write 1
ICDRT
to ST (7-bit address + W) (DATA 1)
(2)
Figure 30.46
(3)
(4)
Clear
Write data to
Write 1
START
ICDRT
to RS
to 0
(7-bit address + R)
(5)
(6)
(7)
Restart condition issue timing after master transmission
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.11.3
Issuing a Stop Condition
The IIC issues a stop condition when the SP bit in ICCR2 is set to 1.
When the SP bit is set to 1, a stop condition request is made and IIC issues a stop condition when the ICCR2.BBSY flag
is 1 (bus busy state) and the ICCR2.MST bit is 1 (master mode).
To issue a stop condition:
1. Drive the SDAn line low (high level to low level).
2. Ensure that the low-level period of SCLn line set in ICBRL elapses.
3. Release the SCLn line (low level to high level).
4. Detect a high level on the SCLn line and ensure that the time set in ICBRH and the stop condition setup time elapse.
5. Release the SDAn line (low level to high level).
6. Ensure that the time set in ICBRL and the bus free time elapse.
7. Clear the BBSY flag to 0 to release the bus mastership.
ICBRL
ICBRH
SCLn
SDAn
ICBRL
ICBRH
8
b0
ICBRL
9
ICBRH
Issue stop
condition
ACK/NACK
Setup time
ICBRL
Bus free time
P
IIC
BBSY
MST
TRS
TDRE
STOP
SP
Write 1 to SP
Figure 30.47
Accept stop condition issuance
Clear STOP to 0
Stop condition issue timing using the SP bit
30.12 Bus Hanging
If the clock signals from the master and slave devices are out of synchronization because of noise or other factors, the I2C
bus might hang with a fixed level on the SCLn line or SDAn line.
To manage bus hanging, the IIC has the following:
A timeout function to detect hanging by monitoring the SCLn line
A function for the output of an extra SCL clock cycle to release the bus from a hung state because of clock signals
being out of synchronization
An IIC reset function
An internal reset function.
By checking the SCLO, SDAO, SCLI, and SDAI bits in ICCR1, it is possible to determine whether the IIC or its
communicating partner is placing the low level on the SCLn or SDAn lines.
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S3A1 User’s Manual
30.12.1
Timeout Function
The timeout function can detect when the SCLn line is stuck longer than the predetermined time. IIC can detect an
abnormal bus state by monitoring that the SCLn line is stuck low or high for a predetermined time.
The timeout function monitors the SCLn line state and counts the low-level period or high-level period using the internal
counter. The timeout function resets the internal counter each time the SCLn line changes (rising or falling), but
continues to count unless the SCLn line changes. If the internal counter overflows because no SCLn line changes, the IIC
can detect the timeout and report the bus hung state.
This timeout function is enabled when the ICFER.TMOE bit is 1. It detects a hung state when the SCLn line is stuck low
or high during the following conditions:
The bus is busy (ICCR2.BBSY flag is 1) in master mode (ICCR2.MST bit is 1)
The IIC slave address is detected (ICSR1 register is not 00h) and the bus is busy (ICCR2.BBSY flag is 1) in slave
mode (ICCR2.MST bit is 0)
The bus is free (ICCR2.BBSY flag is 0) while a start condition is requested (ICCR2.ST bit is 1).
The internal counter of the timeout function uses the internal reference clock (IICΦ) set in the CKS[2:0] bits in ICMR1
as a count source. It functions as a 16-bit counter when long mode is selected (ICMR2.TMOS = 0) or a 14-bit counter
when short mode is selected (ICMR2.TMOS = 1).
The SCLn line level (low, high, or both levels) during which this counter is activated can be selected in the TMOH and
TMOL bits in ICMR2. If both TMOL and TMOH bits are set to 0, the internal counter is disabled.
[Timeout function]
Start internal
counter
Start internal
counter
Clear internal
counter
Start internal
counter
Clear internal
counter
Clear internal
counter
Start internal
counter
Start internal
counter
Start internal
counter
Clear internal
counter
Clear internal
counter
Clear internal
counter
Clear internal
counter
IIC
BBSY
TMOE
TMOH
TMOL
Write 1 to TMOH
[Example of operation when TMOH = 1 and TMOL = 1]
Clear internal counter
7
8
9
When a stat condition is issued
S
Bus free time
1
TMOS = 1
TMOS = 0
2
7
7-bit slave address
Write 0 to TMOE
In the slave-address matched state
Start internal counter
P
A/NA
Write 1 to TMOL
Write 0 to TMOL
8
9
R/W# ACK
1
14-bit counter
overflows
16-bit counter
overflows
2
Data
BBSY
ST
TMOE
TMOF
Figure 30.48
Timeout function using the TMOE, TMOS, TMOH, and TMOL bits
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S3A1 User’s Manual
30.12.2
Extra SCL Clock Cycle Output Function
In master mode, this function outputs extra clock cycles to release the SDAn line of the slave device from being held low
because the master is out of synchronization with the slave device.
This function uses single cycles of the SCL clock for a bus error when the IIC cannot issue a stop condition because the
slave device is holding the SDAn line low. Do not use this function in normal situations. Using it when communications
are proceeding correctly leads to malfunctioning.
When the CLO bit in the ICCR1 register is set to 1 in master mode, a single cycle of the SCL clock at the transfer rate
specified in the ICMR1.CKS[2:0] bits, and in the ICBRH and ICBRL registers, is output as an extra clock cycle. After
output of this single cycle of the SCL clock, the CLO bit is automatically set to 0. Therefore, additional extra clock
cycles can be output consecutively by writing 1 to the CLO bit after having read CLO = 0.
When the IIC module is in master mode and the slave device is holding the SDAn line low because synchronization with
the slave device is lost because of effects like noise, the output of a stop condition is not possible. This function can be
used to output extra cycles of SCL one by one to make the slave device release the SDAn line from being held low, and
recover the bus from an unusable state. Release of the SDAn line by the slave device can be monitored by reading the
SDAI bit in ICCR1. After confirming the release of the SDAn line by the slave device, complete communications by
reissuing the stop condition.
Use this function with the MALE bit in the ICFER register set to 0 (master arbitration-lost detection disabled). If the
MALE bit is set to 1 (enabled), arbitration is lost when the value of the ICCR1.SDAO bit does not match the state of the
SDAn line.
[Output conditions for using the CLO bit in ICCR1]
When the bus is free (ICCR2.BBSY = 0) or in master mode (ICCR2.MST = 1 and ICCR2.BBSY = 1)
When the communication device does not hold the SCLn line low.
Figure 30.49 shows the operation timing of the extra SCL clock cycle output function (CLO bit).
SDAn line is held low because of irregular bits
ICBRH
SCLn
ICBRL
ICBRH
9
ACK or Data 0
SDAn
Release SDAn line
ICBRL
Extra clock cycle
output
ICBRH
MSB or Next Data
ICBRL
Extra clock cycle
output
Data 1
IIC
BBSY
MST
TRS
CLO
Accept CLO output
Figure 30.49
30.12.3
Write 1 to CLO
Write 1 to CLO
Extra SCL clock cycle output function using the CLO bit
IIC Reset and Internal Reset
The IIC module has two types of resets:
IIC reset, which initializes all registers including the BBSY flag in ICCR2
Internal reset, which releases the IIC from the slave-address matched state and initializes the internal counter while
saving other settings.
After issuing a reset, always set the ICCR1.IICRST bit to 0. Both types of resets are valid for release from bus-hung
states, because both restore the output state of the SCLn and SDAn pins to the high-impedance state.
Issuing a reset during slave operation might lead to a loss of synchronization between the master device clock and the
slave device clock, so avoid this when possible. In addition, monitoring the bus state, such as for the presence of a start
condition, is not possible during an IIC reset (ICE and IICRST bits = 01b in ICCR1).
For a detailed description of the IIC and internal resets, see section 30.15, Register States When Issuing Each Condition.
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30. I2C Bus Interface (IIC)
30.13 SMBus Operation
The IIC supports data communication conforming to the SMBus Specification, version 2.0. To perform SMBus
communication, set the SMBS bit in ICMR3 to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the
SMBus standard, set the ICMR1.CKS[2:0] bits, and the ICBRH, ICBRL registers. In addition, specify the values of the
ICMR2.DLCS and ICMR2.SDDL[2:0] bits to meet the data hold time specification of 300 ns or more. When the IIC is
used only as a slave device, the transfer rate setting is not required, but ICBRL must be set to a value longer than the data
setup time (250 ns).
For the SMBus device default address (1100 001b), use one of the slave address registers L0 to L2 (SARL0, SARL1, and
SARL2), and set the associated FS bit (7-bit/10-bit address format select) in SARUy (y = 0 to 2) to 0 (7-bit address
format).
When transmitting the UDID (Unique Device Identifier), set the ICFER.SALE bit to 1 to enable the slave arbitration-lost
detection function.
30.13.1
(1)
SMBus Timeout Measurement
Measuring slave device timeout
The following period (timeout interval: TLOW: SEXT) must be measured for slave devices in SMBus communication:
From start condition to stop condition
To measure timeout for slave devices, measure the period from start condition detection to stop condition detection with
the GPT using the IIC start condition detection interrupt (STIn) and stop condition detection interrupt (SPIn). The
measured timeout period must be within the total clock low-level period [slave device] TLOW: SEXT: 25 ms (maximum)
of the SMBus standard.
If the time measured with the GPT exceeds the clock low-level detection timeout TTIMEOUT: 25 ms (minimum) of the
SMBus standard, the slave device must release the bus by writing 1 to the ICCR1.IICRST to issue an internal reset of the
IIC. When an internal reset is issued, the IIC stops driving the bus for the SCLn and SDAn pins and makes the SCLn/
SDAn pin output high-impedance, which releases the bus.
(2)
Measuring master device timeout
The following periods (timeout interval: TLOW: MEXT) must be measured for master devices in SMBus communication:
From start condition to acknowledge bit
Between acknowledge bits
From acknowledge bit to stop condition.
To measure timeout for master devices, measure these periods with the GPT using the IIC start condition detection
interrupt (STIn), stop condition detection interrupt (SPIn), transmit end interrupt (IICn_TEI) or receive data full interrupt
(IICn_RXI). The measured timeout period must be within the total clock low-level extended period (master device)
TLOW: MEXT: 10 ms (maximum) of the SMBus standard, and the total of all TLOW: MEXT from start condition to stop
condition must be within TLOW: SEXT: 25 ms (maximum).
For the ACK receive timing (rising edge of the 9th SCL clock cycle), monitor the ICSR2.TEND flag in master transmit
mode (master transmitter) and the ICSR2.RDRF flag in master receive mode (master receiver). Perform byte-wise
transmit operations in master transmit mode, and hold the ICMR3.RDRFS bit at 0 until the byte immediately before
reception of the final byte in master receive mode. While the RDRFS bit is 0, the RDRF flag is set to 1 on the rising edge
of the 9th SCL clock cycle.
If the period measured with the GPT exceeds the total clock low-level extended period (master device) TLOW: MEXT: 10
ms (maximum) of the SMBus standard or if the total of measured periods exceeds the clock low-level detection timeout
TTIMEOUT: 25 ms (minimum) of the SMBus standard, the master device must stop the transaction by issuing a stop
condition. In master transmit mode, immediately stop the transmit operation (stop writing data to the ICDRT register).
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SMBus standard
Start
Stop
TLOW:SEXT
Clk ACK
TLOW:MEXT
S
TLOW:SEXT: Total clock low-level extended period (slave device)
TLOW:MEXT: Total clock low-level extended period (master device)
1
2
7
8
9
Clk ACK
TLOW:MEXT
1
2
7
8
9
Clk ACK
TLOW:MEXT
1
2
7
8
TLOW:MEXT
9
P
SCLn
SDAn
7-bit slave address
R/W# ACK
Data
ACK
Data
A/NA
BBSY
TDRE
TEND
RDRF
RDRFS
START
STOP
Measured with the GPT
Figure 30.50
30.13.2
SMBus timeout measurement
Packet Error Code (PEC)
The MCU provides a CRC calculator that enables transmission of a packet error code (PEC) or allows checking the
received data in SMBus data communication. For the CRC generating polynomials of the CRC calculator, see section 34,
Cyclic Redundancy Check (CRC) Calculator.
In master transmit mode, the PEC data can be generated by writing all transmit data to the CRC Data Input Register
(CRCDIR) in the CRC calculator.
In master receive mode, the PEC data can be checked by writing all receive data to the CRCDIR register in the CRC
calculator and comparing the obtained value in the CRC Data Output Register (CRCDOR) with the received PEC data.
To send ACK or NACK based on the match or mismatch result when the final byte is received as a result of the PEC code
check, set the ICMR3.RDRFS to 1 before the rising edge of the 8th SCL clock cycle during reception of the final byte,
and hold the SCLn line low on the falling edge of the 8th clock cycle.
30.13.3
SMBus Host Notification Protocol (Notify ARP Master Command)
In communications over an SMBus, a slave device can temporarily act as a master device to notify the SMBus host (or
ARP master) of its own slave address or to request its own slave address from the SMBus host.
For a product using the MCU to operate as an SMBus host or ARP master, the host address (0001 000b) sent from the
slave device must be detected as a slave address, and so the IIC has a function for detecting the host address. To detect
the host address as a slave address, set the ICMR3.SMBS bit and the ICSER.HOAE bit to 1. Operation after the host
address is detected is the same as normal slave operation.
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30. I2C Bus Interface (IIC)
S3A1 User’s Manual
30.14 Interrupt Sources
The IIC issues four types of interrupt requests:
Transfer error or event generation (detection of arbitration-lost, NACK, timeout, start condition, or stop condition)
Receive data full
Transmit data empty
Transmit end.
Table 30.10 lists details on the interrupt requests. The receive data full and transmit data empty interrupts can activate
data transfer by the DTC or DMAC.
Table 30.10
Interrupt sources
Symbol
Interrupt source
Interrupt flag
DTC activation
DMAC
activation
Interrupt condition
IICn_EEI*5
Transfer error or event
generation
AL
Not possible
Not possible
AL = 1, ALIE = 1
NACKF
NACKF = 1, NAKIE = 1
TMOF
TMOF = 1, TMOIE = 1
START
START = 1, STIE = 1
STOP
STOP = 1, SPIE = 1
IICn_RXI*2, *5
Receive data full
RDRF
Possible
Possible
RDRF = 1, RIE = 1
IICn_TXI*1, *5
Transmit data empty
TDRE
Possible
Possible
TDRE = 1, TIE = 1
IICn_TEI*3, *5
Transmit end
TEND
Not possible
Not possible
TEND = 1, TEIE = 1
IIC0_WUI*4
Slave address match
during wakeup function
WUF
Not possible
Not possible
Slave address match
Slave receive complete
RWAK operation ASY0 = 1
WUIE = 1
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
There is a delay between the execution of a write instruction for a peripheral module by the CPU and actual writing to the
module. When an interrupt flag is cleared or masked, read the relevant flag again to check whether clearing or masking is
complete, and then return from interrupt handling. Not doing so creates the possibility of repeated processing of the same
interrupt.
Because IICn_TXI is an edge-detected interrupt, it does not require clearing. Additionally, the ICSR2.TDRE flag (a condition for
IICn_TXI) is automatically set to 0 when transmit data is written to the ICDRT register or a stop condition is detected
(ICSR2.STOP = 1).
Because IICn_RXI is an edge-detected interrupt, it does not require clearing. Additionally, the ICSR2.RDRF flag (a condition for
IICn_RXI) is automatically set to 0 when data is read from ICDRR.
When using the IICn_TEI interrupt, clear the ICSR2.TEND flag in the IICn_TEI interrupt handling.
The ICSR2.TEND is automatically set to 0 when transmit data is written to ICDRT or a stop condition is detected (ICSR2.STOP
= 1).
Only channel 0 has a wakeup function, therefore IIC0_WUI is for channel 0 only.
Channel number (n = 0 to 2).
Clear or mask each flag during interrupt handling.
30.14.1
Buffer Operation for IICn_TXI and IICn_RXI Interrupts
If the conditions for generating an IICn_TXI and IICn_RXI interrupt are satisfied while the associated IR flag is 1, the
interrupt request is not output for the ICU but is saved internally. One request per source can be saved internally.
An interrupt request that is saved within the ICU is output when the value of the ICU.IELSRn.IR flag becomes 0.
Internally saved interrupt requests are automatically cleared under normal usage conditions. They can also be cleared by
writing 0 to the interrupt enable bit within the associated peripheral module.
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30. I2C Bus Interface (IIC)
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30.15 Register States When Issuing Each Condition
The IIC has 2 dedicated resets, IIC reset and internal reset. Table 30.11 lists the register states when issuing each
condition.
Table 30.11
Register states when issuing each condition
Reset
IIC reset
(ICE = 0, IICRST = 1)
Internal reset
(ICE = 1, IICRST = 1)
Start or restart
condition detection
Stop condition
detection
Reset
Saved
Saved
Saved
Saved
Reset
Reset
Reset
Saved
Set
Saved
Reset
Saved
Saved
TRS, MST
Set or saved
Reset
Others
Reset
Reset or saved
Reset
Reset
Saved
Saved
Saved
Registers
ICCR1
ICE, IICRST
SCLO, SDAO
Others
ICCR2
BBSY
Saved
Reset
ST
ICMR1
BC[2:0]
Reset
Reset
Others
ICMR2
Reset
Reset
Saved
Saved
Saved
ICMR3
Reset
Reset
Saved
Saved
Saved
ICFER
Reset
Reset
Saved
Saved
Saved
ICSER
Reset
Reset
Saved
Saved
Saved
ICIER
Reset
Reset
Saved
Saved
Saved
ICSR1
Reset
Reset
Reset
Saved
Reset
Reset
Reset
Reset
Saved
Reset
ICSR2
TDRE, TEND
START
Set
STOP
Saved
Others
ICWUR
ICWUR2
WUSEN
Set
Saved
Reset
Reset
Saved
Saved
Saved
Reset
Reset
Saved
Saved
Saved
Others
Saved or Set or
Reset
SARL0, SARL1, SARL2
SARU0, SARU1, SARU2
Reset
Reset
Saved
Saved
Saved
ICBRH, ICBRL
Reset
Reset
Saved
Saved
Saved
ICDRT
Reset
Reset
Saved
Saved
Saved
ICDRR
Reset
Reset
Saved
Saved
Saved
ICDRS
Reset
Reset
Reset
Saved
Saved
Timeout function
Reset
Reset
Operation
Operation
Operation
Bus free time
measurement
Reset
Reset
Operation
Operation
Operation
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30. I2C Bus Interface (IIC)
30.16 Output to the Event Link Controller (ELC)
IIC0 to IIC2 modules handle the event output for the Event Link Controller (ELC) for the following sources:
(1)
Transfer error event
When a transfer error event occurs, the associated event signal can be output to another module by the ELC.
(2)
Receive data full
When a receive data register becomes full, the associated event signal can be output to another module by the ELC.
(3)
Transmit data empty
When a transmit data register becomes empty, the associated event signal can be output to another module by the ELC.
(4)
Transmit end
On completion of the transfer, the associated event signal can be output to another module by the ELC.
30.16.1
Interrupt Handling and Event Linking
Each of the IIC interrupt types (see Table 30.10) has an enable bit to control enabling and disabling of the associated
interrupt signal. An interrupt request signal is output to the CPU when an interrupt source condition is satisfied while the
associated enable bit is set.
The associated event link output signals are sent to other modules as event signals by the ELC when the interrupt source
conditions are satisfied, regardless of the interrupt enable bit settings. For details on interrupt sources, see Table 30.10.
30.17 Usage Notes
30.17.1
Settings for the Module-Stop Function
The Module Stop Control Register B (MSTPCRB) can enable or disable IIC operation. IIC is initially stopped after a
reset. Releasing the module-stop state enables access to the registers.
For details on the Module Stop Control Register B, see section 11, Low Power Modes.
30.17.2
Notes on Starting Transfer
If the IR flag associated with the IIC interrupt is 1 when transfer is started (ICCR1.ICE = 1), follow the procedure to
clear interrupts before enabling operations. Starting transfer with the IR flag set to 1 while the ICCR1.ICE bit is 1 leads
to an interrupt request being internally saved after transfer starts, and this can lead to unanticipated behavior of the IR
flag.
To clear the IR flag before starting transfer operation:
1. Confirm that the ICCR1.ICE bit is 0.
2. Set the relevant interrupt enable bits, such as ICIER.TIE to 0.
3. Read the relevant interrupt enable bits, such as ICIER.TIE, and confirm that the value is 0.
4. Set the IR flag to 0.
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31. Controller Area Network (CAN) Module
31.
Controller Area Network (CAN) Module
31.1
Overview
The Controller Area Network (CAN) module uses a message-based protocol to receive and transmit data between
multiple slaves and masters in electromagnetically noisy applications. The module complies with the ISO 11898-1 (CAN
2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in
normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The
CAN module requires an additional external CAN transceiver.
Table 31.1 lists the CAN module specifications and Figure 31.1 shows a block diagram.
Table 31.1
CAN module specifications (1 of 2)
Item
Description
Data transfer rate
ISO11898-1 compliant for standard and extended frames
Bit rate
Programmable up to 1 Mbps (fCAN ≥ 8 MHz)
fCAN: CAN clock source
Message box
32 mailboxes, with two selectable mailbox modes:
Normal mode: 32 mailboxes independently configurable for transmission or reception
FIFO mode: 24 mailboxes independently configurable for transmission or reception, with remaining
mailboxes used for receive and transmit 4-stage FIFOs.
Reception
Support for data frame and remote frame reception
Reception ID format selectable to only standard ID, only extended ID, or mixed IDs
Programmable one-shot reception function
Selectable between overwrite mode (unread message overwritten) and overrun mode (unread
message saved)
Reception complete interrupt independently enabled or disabled for each mailbox.
Acceptance filter
Eight acceptance masks (one mask for every four mailboxes)
Masks independently enabled or disabled for each mailbox.
Transmission
Mode transition for bus-off
recovery
Mode transition for the recovery from the bus-off state selectable to:
ISO11898-1 specification compliant
Automatic invoking of CAN halt mode on bus-off entry
Automatic invoking of CAN halt mode on bus-off end
Invoking of CAN halt mode through software
Transition to error-active state through software.
Error status monitoring
Monitoring of CAN bus errors, including stuff error, form error, ACK error, 15-bit CRC error, bit error,
and ACK delimiter error
Detection of transition to error states, including error-warning, error-passive, bus-off entry, and bus-off
recovery
Support for reading of error counters.
Time stamping
Time stamp function using a 16-bit counter
Reference clock selectable to 1-bit, 2-bit, 4-bit and 8-bit time periods.
Interrupt function
Support for five interrupt sources:
Reception complete
Transmission complete
Receive FIFO
Transmit FIFO
Error interrupts.
CAN sleep mode
CAN clock stopped to reduce power consumption
Support for data frame and remote frame transmission
Transmission ID format selectable to only standard ID, only extended ID, or mixed IDs
Programmable one-shot transmission function
Broadcast messaging function
Priority mode selectable based on message ID or mailbox number
Support for transmission request abort, with abort completion confirmable in status flag
Transmission complete interrupt independently enabled or disabled for each mailbox.
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Table 31.1
31. Controller Area Network (CAN) Module
CAN module specifications (2 of 2)
Item
Description
Software support unit
Three software support units:
Acceptance filter support
Mailbox search support, including receive mailbox search, transmit mailbox search, and message lost
search
Channel search support.
CAN clock source
PCLKB or CANMCLK
Test mode
Three test modes available for evaluation purposes:
Listen-only mode
Self-test mode 0 (external loopback)
Self-test mode 1 (internal loopback).
Module-stop function
Module-stop state can be set to reduce power consumption
Internal peripheral bus
CAN control registers
CRX0
Protocol
controller
CTX0
fCANCLK
Baud rate
prescaler
(BRP)
Acceptance
filter
ID priority
transmission
controller
Timer
Peripheral module clock
(PCLKB)
CCLKS
EXTAL
BRP:
CCLKS:
fCANCLK:
fCAN:
Figure 31.1
System clock
(PCLKA)
fCAN
CANMCLK
Bit in the BCR register
Bit in the BCR register
CAN communication clock
CAN system clock
MailBoxes
CAN0 reception complete interrupt
CAN0 transmission complete interrupt
Interrupt
generator
CAN0 receive FIFO interrupt
CAN0 transmit FIFO interrupt
CAN0 error interrupt
CAN module block diagram
The CAN module includes the following blocks:
CAN input and output pins
CRX0 and CTX0
Protocol controller
Handles CAN protocol processing such as bus arbitration, bit timing at transmission and reception, stuffing, and
error handling.
Mailboxes
Consists of 32 mailboxes, which can be configured as either transmit or receive. Each mailbox has an individual ID,
data length code (DLC), a data field (8 bytes), and a time stamp.
Acceptance filter
Performs filtering of received messages. MKR0 to MKR7 registers are used for the filtering process.
Timer
Used for the time stamp function. The timer value when a message is stored in the mailbox is written as the time
stamp value.
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31. Controller Area Network (CAN) Module
Interrupt generator
Generates five types of interrupts:
CAN0 reception complete interrupt
CAN0 transmission complete interrupt
CAN0 receive FIFO interrupt
CAN0 transmit FIFO interrupt
CAN0 error interrupt.
Table 31.2 lists the CAN module pins. These pins are multiplexed with other signals on the MCU. For details, see section
20, I/O Ports.
Table 31.2
CAN module I/O pins
Pin name
I/O
CRX0
Input
Data receive pin
CTX0
Output
Data transmit pin
31.2
Function
Register Descriptions
31.2.1
Control Register (CTLR)
Address(es): CAN0.CTLR 4005 0840h
Value after reset:
b15
b14
b13
—
—
RBOC
0
0
0
b12
b11
BOM[1:0]
0
b10
SLPM
0
1
b9
b8
b7
b6
CANM[1:0]
TSPS[1:0]
0
0
1
0
b5
b4
b3
TSRC
TPM
MLM
0
0
0
b2
b1
IDFM[1:0]
0
0
b0
MBM
0
Bit
Symbol
Bit name
Description
R/W
b0
MBM
CAN Mailbox Mode
Select*1
0: Normal mailbox mode
1: FIFO mailbox mode.
R/W
b2, b1
IDFM[1:0]
ID Format Mode Select
*1
b2 b1
R/W
b3
MLM
Message Lost Mode
Select*1
0: Overwrite mode
1: Overrun mode.
R/W
b4
TPM
Transmission Priority
Mode Select*1
0: ID priority transmit mode
1: Mailbox number priority transmit mode.
R/W
b5
TSRC
Time Stamp Counter
Reset Command*4
0: Do not reset time stamp counter
1: Reset time stamp counter.*3
R/W
b7, b6
TSPS[1:0]
Time Stamp Prescaler
Select*1
b7 b6
R/W
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0 0: Standard ID mode
All mailboxes, including FIFO mailboxes, handle only standard IDs
0 1: Extended ID mode
All mailboxes, including FIFO mailboxes, handle only extended IDs
1 0: Mixed ID mode
All mailboxes, including FIFO mailboxes, handle both standard IDs
and extended IDs. In normal mailbox mode, use the associated IDE
bit to differentiate between standard and extended IDs. In FIFO
mailbox mode, the associated IDE bits are used for mailboxes 0 to
23, the IDE bits in FIDCR0 and FIDCR1 are used for the receive
FIFO, and the IDE bit associated with mailbox 24 is used for the
transmit FIFO.
1 1: Setting prohibited.
0
0
1
1
0: Every 1-bit time
1: Every 2-bit time
0: Every 4-bit time
1: Every 8-bit time.
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31. Controller Area Network (CAN) Module
Bit
Symbol
Bit name
Description
R/W
b9, b8
CANM[1:0]
CAN Operating Mode
Select*5
b9 b8
R/W
b10
SLPM
CAN Sleep Mode*5, *6
0: Exit CAN sleep mode
1: Enter CAN sleep mode.
R/W
b12, b11
BOM[1:0]
Bus-Off Recovery
Mode*1
b12 b11
R/W
b13
RBOC
Forcible Return from
Bus-Off*2
0: No return occurred
1: Forced return from bus-off state.*3
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
0
0
1
1
0: CAN operation mode
1: CAN reset mode
0: CAN halt mode
1: CAN reset mode (forced transition).
0 0: Normal mode (ISO11898-1 specification compliant)
0 1: Enter CAN halt mode automatically on entering bus-off state
1 0: Enter CAN halt mode automatically at the end of bus-off state
1 1: Enter CAN halt mode during bus-off recovery period through
a software request.
Write to the BOM[1:0], TSPS[1:0], TPM, MLM, IDFM[1:0], and MBM bits in CAN reset mode.
Set the RBOC bit to 1 in the bus-off state.
This bit automatically clears to 0 after being set to 1. It should be read as 0.
Set the TSRC bit to 1 in CAN operation mode.
When the CANM[1:0] and SLPM bits are changed, check STR to ensure that the mode is switched. Do not change the
CANM[1:0] bits or the SLPM bit until the mode is switched.
Write to the SLPM bit in CAN reset mode or CAN halt mode. When changing the SLPM bit, write 0 or 1 only to the SLPM bit.
MBM bit (CAN Mailbox Mode Select)
When the MBM bit is 0 (normal mailbox mode), mailboxes 0 to 31 are configured as transmit or receive mailboxes.
When the MBM bit is 1 (FIFO mailbox mode) the mailboxes are configured as follows:
Mailboxes 0 to 23 are configured as transmit or receive mailboxes
Mailboxes 24 to 27 are configured as transmit FIFO
Mailboxes 28 to 31 are configured as receive FIFO
Transmit data is written into mailbox 24, a window mailbox for the transmit FIFO. Receive data is read from mailbox 28,
a window mailbox for the receive FIFO.
Table 31.3 lists the mailbox configuration.
IDFM[1:0] bits (ID Format Mode Select)
The IDFM[1:0] bits specify the ID format.
MLM bit (Message Lost Mode Select)
The MLM bit specifies the operation when a new message is captured in an unread mailbox. Overwrite mode or overrun
mode can be selected. All mailboxes including the receive FIFO are set to either overwrite mode or overrun mode.
When the MLM bit is 0, all mailboxes are set to overwrite mode. Any new message received overwrites the pre-existing
message.
When the MLM bit is 1, all mailboxes are set to overrun mode. Any new message received does not overwrite the preexisting message, and it is discarded.
TPM bit (Transmission Priority Mode Select)
The TPM bit specifies the priority when transmitting messages.
The ID priority transmit mode or mailbox number transmit mode can be selected. All mailboxes are set for either ID
priority transmission or mailbox number priority transmission.
When the TPM bit is 0, ID priority transmit mode is selected and transmission priority is arbitrated, as defined in the
CAN specification (ISO11898-1). In ID priority transmit mode, mailboxes 0 to 31 (in normal mailbox mode), mailboxes
0 to 23 (in FIFO mailbox mode), and the transmit FIFO are compared for the IDs of mailboxes configured for
transmission. If two or more mailbox IDs are the same, the mailbox with the smaller number has higher priority.
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31. Controller Area Network (CAN) Module
Only the next message to be transmitted from the transmit FIFO is included in the transmission arbitration. If a FIFO
message is currently being transmitted, the next pending message within the transmit FIFO is included in the
transmission arbitration.
When the TPM bit is 1, mailbox number transmit mode is selected and the transmit mailbox with the smallest mailbox
number has the highest priority. In FIFO mailbox mode, the transmit FIFO has lower priority than normal mailboxes (0
to 23).
TSRC bit (Time Stamp Counter Reset Command)
The TSRC bit resets the time stamp counter. When this bit is set to 1, the TSR register is set to 0000h. This bit
automatically sets to 0.
TSPS[1:0] bits (Time Stamp Prescaler Select)
The TSPS[1:0] bits select the prescaler for the time stamp. The reference clock for the time stamp can be selected to
1-bit, 2-bit, 4-bit, or 8-bit time periods.
CANM[1:0] bits (CAN Operating Mode Select)
The CANM[1:0] bits select one of the following modes for the CAN module:
CAN operation mode
CAN reset mode
CAN halt mode.
The CAN sleep mode is set in the SLPM bit. For details, see section 31.3, Modes of Operation.
When the CAN module enters CAN halt mode based on the BOM[1:0] bits setting, the CANM[1:0] bits are
automatically set to 10b.
SLPM bit (CAN Sleep Mode)
When the SLPM bit is set to 1, the CAN module enters CAN sleep mode. When the SLPM bit is set to 0, the CAN
module exits CAN sleep mode. For details, see section 31.3, Modes of Operation.
BOM[1:0] bits (Bus-Off Recovery Mode)
The BOM[1:0] bits select bus-off recovery mode for the CAN module.
When the BOM[1:0] bits are 00b, the recovery from bus-off is compliant with the CAN specification (ISO11898-1). The
CAN module recovers CAN communication (error-active state) after detecting 11 consecutive recessive bits 128 times.
A bus-off recovery interrupt request occurs when recovering from bus-off.
When the BOM[1:0] bits are 01b and the CAN module reaches the bus-off state, the CANM[1:0] bits in the CTLR
register are set to 10b to enter the CAN halt mode. No bus-off recovery interrupt request occurs when recovering from
bus-off, and the TECR and RECR registers are set to 00h.
When the BOM[1:0] bits are 10b, the CANM[1:0] bits are set to 10b as soon as the CAN module reaches the bus-off
state. The CAN module enters CAN halt mode after the recovery from the bus-off state, after detecting 11 consecutive
recessive bits 128 times. A bus-off recovery interrupt request occurs when recovering from bus-off, and the TECR and
RECR registers are set to 00h.
When the BOM[1:0] bits are 11b, the CAN module enters CAN halt mode by setting the CANM[1:0] bits to 10b while
the CAN module is still in the bus-off state. No bus-off recovery interrupt request is generated when recovering from
bus-off, and TECR and RECR are set to 00h. However, a bus-off recovery interrupt request is generated if the CAN
module recovers from bus-off after detecting 11 consecutive recessive bits 128 times before the CANM[1:0] bits are set
to 10b.
If the CPU requests an entry to the CAN reset mode at the same time as the CAN module attempts to enter CAN halt
mode (at bus-off entry when the BOM[1:0] bits are 01b, or at bus-off end when the BOM[1:0] bits are 10b), then the
CPU request has higher priority.
RBOC bit (Forcible Return from Bus-Off)
When the RBOC bit is set to 1 in the bus-off state, the CAN module forcibly exits the bus-off state. This bit is
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31. Controller Area Network (CAN) Module
automatically set to 0, and the error state changes from bus-off to error-active. When the RBOC bit is set to 1, the RECR
and TECR registers are set to 00h and the BOST bit in the STR register is set to 0, indicating that the CAN module is not
in bus-off state. The other registers remain unchanged even when the RBOC bit is set to 1. No bus-off recovery interrupt
request is generated by this recovery from the bus-off state. Use the RBOC bit only when the BOM[1:0] bits are 00b
(normal mode).
Table 31.3
Mailbox configuration
Mailbox
MBM bit = 0 (normal mailbox mode)
MBM bit = 1*1 to *5 (FIFO mailbox mode)
Mailboxes 0 to 23
Normal mailbox
Normal mailbox
Mailboxes 24 to 27
Transmit FIFO
Mailboxes 28 to 31
Receive FIFO
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The transmit FIFO is controlled by the TFCR register. The MCTL_TXj registers associated with mailboxes 24 to 27 are
disabled. MCTL_TX24 to MCTL_TX27 cannot be used by the transmit FIFO.
The receive FIFO is controlled by the RFCR register. The MCTL_RXj registers associated with mailboxes 28 to 31 are
disabled. MCTL_RX28 to MCTL_RX31 cannot be used by the receive FIFO.
See the MIER_FIFO register for information on the FIFO interrupts.
The MKIVLR register bits associated with mailboxes 24 to 31 are disabled. Set these bits to 0.
The transmit and receive FIFOs can be used for both data frames and remote frames.
31.2.2
Bit Configuration Register (BCR)
Address(es): CAN0.BCR 4005 0844h
b31
b30
b29
b28
TSEG1[3:0]
b27
b26
—
—
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BRP[9:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
SJW[1:0]
—
—
—
—
—
—
—
—
CCLKS
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
0
TSEG2[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CCLKS
CAN Clock Source Selection
0: PCLKB (generated by the PLL clock)
1: CANMCLK (generated by the main clock).
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b10 to b8
TSEG2[2:0]
Time Segment 2 Control
b10
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b13, b12
SJW[1:0]
Synchronization Jump Width
Control
b13 b12
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25 to b16
BRP[9:0]
Baud Rate Prescaler select*1
These bits set the frequency of the CAN communication clock
(fCANCLK)
R/W
b27, b26
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b8
0: Setting prohibited
1: 2 Tq
0: 3 Tq
1: 4 Tq
0: 5 Tq
1: 6 Tq
0: 7 Tq
1: 8 Tq.
0: 1 Tq
1: 2 Tq
0: 3 Tq
1: 4 Tq.
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31. Controller Area Network (CAN) Module
Bit
Symbol
Bit name
Description
R/W
b31 to b28
TSEG1[3:0]
Time Segment 1 Control
b31
R/W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b28
0: Setting prohibited
1: Setting prohibited
0: Setting prohibited
1: 4 Tq
0: 5 Tq
1: 6 Tq
0: 7 Tq
1: 8 Tq
0: 9 Tq
1: 10 Tq
0: 11 Tq
1: 12 Tq
0: 13 Tq
1: 14 Tq
0: 15 Tq
1: 16 Tq.
Tq: Time Quantum
Note 1.
Do not select a value less than 1 when the SCKSCR.CKSEL[2:0] bits are 011b (selecting the main clock oscillator).
For details about setting the bit timing, see section 31.4, Data Transfer Rate Configuration. Set the BCR register before
entering CAN halt mode or CAN operation mode from CAN reset mode. After the setting is made once, this register can
be written to in CAN reset mode or CAN halt mode. 32-bit read/write accesses must be performed carefully so as not to
change bits [7:0].
CCLKS bit (CAN Clock Source Selection)
When the CCLKS bit is 0, the peripheral module clock (PCLKB) produced by the PLL frequency synthesizer is used as
the CAN clock source (fCAN). When the CCLKS bit is 1, CANMCLK produced externally by the EXTAL pins is used
as the CAN clock source (fCAN).
TSEG2[2:0] bits (Time Segment 2 Control)
The TSEG2[2:0] bits specify the length of the phase buffer segment 2 (PHASE_SEG2) with a Tq value. A value from 2
to 8 Tq can be set. Set a value smaller than that in the TSEG1[3:0] bits.
SJW[1:0] bits (Synchronization Jump Width Control)
The SJW[1:0] bits specify the synchronization jump width with a Tq value. A value from 1 to 4 Tq can be set. Set a value
smaller than or equal to that in the TSEG2[2:0] bits.
BRP[9:0] bits (Baud Rate Prescaler select)
The BRP[9:0] bits set the frequency of the CAN communication clock (fCANCLK). The fCANCLK cycle is 1 Tq. If the
setting is P (0 to 1023), the baud rate prescaler divides fCAN by P + 1.
TSEG1[3:0] bits (Time Segment 1 Control)
The TSEG1[3:0] bits specify the total length of the propagation time segment (PROP_SEG) and phase buffer segment 1
(PHASE_SEG1) with a time quantum (Tq) value. A value from 4 to 16 Tq can be set.
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31.2.3
31. Controller Area Network (CAN) Module
Mask Register k (MKRk) (k = 0 to 7)
Address(es): CAN0.MKR0 4005 0400h to CAN0.MKR7 4005 041Ch
b31
b30
b29
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
SID[10:0]
b17
b16
EID[17:0]
EID[17:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b17 to b0
EID[17:0]
Extended ID
0: Do not compare associated EID[17:0] bit
1: Compare associated EID[17:0] bit.
R/W
b28 to b18
SID[10:0]
Standard ID
0: Do not compare associated SID[10:0] bit
1: Compare associated SID[10:0] bit.
R/W
b31 to b29
—
Reserved
The read value is undefined. The write value should be 0.
R/W
For the mask function in FIFO mailbox mode, see section 31.6, Acceptance Filtering and Masking Functions. Write to
MKR0 to MKR7 registers in CAN reset mode or CAN halt mode.
EID[17:0] bits (Extended ID)
The EID[17:0] bits are the filter mask bits associated with the CAN extended ID bits. These bits are used to receive
extended ID messages.
When an EID[17:0] bit is set to 0, the received ID is not compared with the associated mailbox ID. When an EID[17:0]
bit is set to 1, the received ID is compared with the associated mailbox ID.
SID[10:0] bits (Standard ID)
The SID[10:0] bits are the filter mask bits associated with the CAN standard ID bits. These bits are used to receive both
standard ID and extended ID messages.
When an SID[10:0] bit is set to 0, the respective received ID is not compared with the associated mailbox ID bit. When
an SID[10:0] bit is set to 1, the respective received ID is compared with the associated mailbox ID.
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31.2.4
31. Controller Area Network (CAN) Module
FIFO Received ID Compare Registers 0 and 1 (FIDCR0 and FIDCR1)
Address(es): CAN0.FIDCR0 4005 0420h, CAN0.FIDCR1 4005 0424h
b31
b30
b29
IDE
RTR
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
SID[10:0]
b16
EID[17:0]
EID[17:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b17 to b0
EID[17:0]
Extended ID
Extended ID of data and remote frames
R/W
b28 to b18
SID[10:0]
Standard ID
Standard ID of data and remote frames
R/W
b29
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b30
RTR
Remote Transmission
Request
0: Data frame
1: Remote frame.
R/W
b31
IDE
ID Extension *1
0: Standard ID
1: Extended ID.
R/W
Note 1.
When the CTLR.IDFM[1:0] bits are any value other than 10b, the IDE bit should be written with 0 and is read as 0.
The FIDCR0 and FIDCR1 registers are enabled when the MBM bit in the CTLR register is set to 1 (FIFO mailbox
mode). In FIFO mailbox mode, the EID[17:0], SID[10:0], RTR, and IDE bits in the mailbox 28 to mailbox 31 registers
are disabled. Write to the FIDCR0 and FIDCR1 registers in CAN reset mode or CAN halt mode. For information on
using the FIDCR0 and FIDCR1 registers, see section 31.6, Acceptance Filtering and Masking Functions.
EID[17:0] bits (Extended ID)
The EID[17:0] bits set the extended ID of data and remote frames. These bits are used to receive extended ID messages.
SID[10:0] bits (Standard ID)
The SID[10:0] bits set the standard ID of data frames and remote frames. These bits are used to receive both standard ID
and extended ID messages.
RTR bit (Remote Transmission Request)
The RTR bit sets the specified frame format of data frames or remote frames:
When the RTR bits in both FIDCR0 and FIDCR1 registers are set to 0, only data frames are received
When the RTR bits in both FIDCR0 and FIDCR1 registers are set to 1, only remote frames are received
When the RTR bits in both FIDCR0 and FIDCR1 registers are set to different values, both data frames and remote
frames are received.
IDE bit (ID Extension)
The IDE bit sets the ID format to standard ID or extended ID. The IDE bit is enabled when the IDFM[1:0] bits in CTLR
are 10b (mixed ID mode):
When the IDE bits in both the FIDCR0 and FIDCR1 registers are set to 0, only standard ID frames are received
When the IDE bits in both the FIDCR0 and FIDCR1 registers are set to 1, only extended ID frames are received
When the IDE bits in both the FIDCR0 and FIDCR1 registers are set to different values, both standard ID and
extended ID frames are received.
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31.2.5
31. Controller Area Network (CAN) Module
Mask Invalid Register (MKIVLR)
Address(es): CAN0.MKIVLR 4005 0428h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MB31
MB30
MB29
MB28
MB27
MB26
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MB31 to MB0
Mask Invalid
0: Mask valid
1: Mask invalid.
R/W
Note 1.
Set bits [31:24] to 0 in FIFO mailbox mode.
Each bit in the MKIVLR register is associated with a mailbox of the same number. Bit [0] in the MKIVLR register
corresponds to mailbox 0 (MB0) and bit [31] corresponds to mailbox 31 (MB31).*1
When an MBn bit is set to 1, the associated acceptance mask register becomes invalid for the associated mailbox. When
an MBn bit is set to 1, a message is received by the associated mailbox only if the receive message ID matches the
mailbox ID exactly. Write to the MKIVLR register in CAN reset mode or halt mode.
31.2.6
Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31, m = 0 to 7)
Table 31.4 lists the CAN0 mailbox memory mapping, and Table 31.5 lists the CAN data frame configuration. The value
of the CAN0 mailbox after reset is undefined.
Write to the MBj_ID, MBj_DL, MBj_Dm, and MBj_TS registers only when the related MCTL_TXj or MCTL_RXj (j =
0 to 31) register is 00h and the associated mailbox is not processing an abort request.
See Table 31.4 for details on register addresses.
Table 31.4
CAN0 mailbox memory mapping (1 of 2)
Address
Message content
CAN0
Memory mapping
4005 0200h + 16 × j + 0
IDE, RTR, SID10 to SID6
4005 0200h + 16 × j + 1
SID5 to SID0, EID17, EID16
4005 0200h + 16 × j + 2
EID15 to EID8
4005 0200h + 16 × j + 3
EID7 to EID0
4005 0200h + 16 × j + 4
-
4005 0200h + 16 × j + 5
Data length code (DLC[3:0])
4005 0200h + 16 × j + 6
Data byte 0
4005 0200h + 16 × j + 7
Data byte 1
4005 0200h + 16 × j + 8
Data byte 2
4005 0200h + 16 × j + 9
Data byte 3
4005 0200h + 16 × j + 10
Data byte 4
4005 0200h + 16 × j + 11
Data byte 5
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Table 31.4
31. Controller Area Network (CAN) Module
CAN0 mailbox memory mapping (2 of 2)
Address
Message content
CAN0
Memory mapping
4005 0200h + 16 × j + 12
Data byte 6
4005 0200h + 16 × j + 13
Data byte 7
4005 0200h + 16 × j + 14
Time stamp upper byte
4005 0200h + 16 × j + 15
Time stamp lower byte
Table 31.5
CAN data frame configuration
SID10 to SID6
SID5 to SID0
EID17 to EID16
EID15 to EID8
EID7 to EID0
DLC3 to DLC1
DATA0
DATA1
...
DATA7
The previous value of each mailbox is saved unless a new message is received.
Address(es): CAN0.MB0_ID 4005 0200h to CAN0.MB31_ID 4005 03F0h
b31
b30
b29
IDE
RTR
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
SID[10:0]
b17
b16
EID[17:0]
EID[17:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b17 to b0
EID[17:0]
Extended ID *1
Extended ID of data and remote frames
R/W
b28 to b18
SID[10:0]
Standard ID
Standard ID of data and remote frames
R/W
b29
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b30
RTR
Remote Transmission Request
0: Data frame
1: Remote frame.
R/W
b31
IDE
ID Extension *2
0: Standard ID
1: Extended ID.
R/W
Note 1.
Note 2.
If the mailbox receives a standard ID message, the EID bits in the mailbox are undefined.
The IDE bit is enabled when the IDFM[1:0] bits in the CTLR register are 10b (mixed ID mode). When the IDFM[1:0] bits are any
value other than 10b, the IDE bit should be written with 0 and is read as 0.
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31. Controller Area Network (CAN) Module
Address(es): CAN0.MB0_DL 4005 0204h to CAN0.MB31_DL 4005 03F4h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
b3
b2
b1
b0
DLC[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit Name
Description
R/W
b3 to b0
DLC[3:0]
Data Length Code *1
b3
R/W
b15 to b4
—
Reserved
The read value is undefined. The write value should be 0.
b0
0 0 0 0: Data length = 0 byte
0 0 0 1: Data length = 1 byte
0 0 1 0: Data length = 2 bytes
0 0 1 1: Data length = 3 bytes
0 1 0 0: Data length = 4 bytes
0 1 0 1: Data length = 5 bytes
0 1 1 0: Data length = 6 bytes
0 1 1 1: Data length = 7 bytes
1 x x x: Data length = 8 bytes.
R/W
x: Don’t care
Note 1.
If the mailbox receives a message with data length (set in DLC[3:0]) of n bytes, where n is less than 8, the data in the DATAn to
DATA7 registers in the mailbox is undefined. Here, DATA0 to DATA7 are data registers for this mailbox. For example, if data
length is 6 bytes (DLC[3:0] = 6h), the data in DATA6 and DATA7 registers is undefined.
Address(es): CAN0.MB0_D0 4005 0206h to CAN0.MB31_D0 4005 03F6h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA0
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D1 4005 0207h to CAN0.MB31_D1 4005 03F7h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA1
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D2 4005 0208h to CAN0.MB31_D2 4005 03F8h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA2
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D3 4005 0209h to CAN0.MB31_D3 4005 03F9h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA3
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D4 4005 020Ah to CAN0.MB31_D4 4005 03FAh
b7
b6
b5
b4
b3
b2
b1
b0
DATA4
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Value after reset:
x
31. Controller Area Network (CAN) Module
x
x
x
x
x
x
x
Address(es): CAN0.MB0_D5 4005 020Bh to CAN0.MB31_D5 4005 03FBh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA5
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D6 4005 020Ch to CAN0.MB31_D6 4005 03FCh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA6
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D7 4005 020Dh to CAN0.MB31_D7 4005 03FDh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA7
Value after reset:
x
x
x
x
x
x: Undefined
Bit
Symbol
b7 to b0
Note 1.
Note 2.
Bit name
DATA0 to
DATA7
Data Bytes 0 to
7*1, *2
Description
R/W
DATA0 to DATA7 store the transmitted or received CAN message data.
Transmission or reception starts from DATA0. The bit order on the CAN
bus is MSB-first, and transmission or reception starts from bit [7].
R/W
If the mailbox receives a message with n bytes, where n is less than 8 bytes, the DATAn to DATA7 values in the mailbox are
undefined. For example, if the received data length is 6 bytes, the values of DATA6 and DATA7 are undefined.
If the mailbox receives a remote frame, the previous values of DATA0 to DATA7 in the mailbox are saved.
Address(es): CAN0.MB0_TS 4005 020Eh to CAN0.MB31_TS 4005 03FEh
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
TSH[7:0]
Value after reset:
x
x
x
x
x
b4
b3
b2
b1
b0
x
x
x
TSL[7:0]
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b7 to b0
TSL[7:0]
Time Stamp Lower Byte
R/W
b15 to b8
TSH[7:0]
Time Stamp Higher Byte
The TSH[7:0] and TSL[7:0] bits store the counter value of the time
stamp when received messages are stored in the mailbox.
R/W
EID[17:0] bits (Extended ID)
The EID[17:0] bits set the extended ID for data and remote frames. These bits transmit or receive extended ID messages.
SID[10:0] bits (Standard ID)
The SID[10:0] bits set the standard ID of data and remote frames. These bits transmit or receive both standard ID and
extended ID messages.
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31. Controller Area Network (CAN) Module
RTR bit (Remote Transmission Request)
The RTR bit sets the frame format to data frames or remote frames:
The receive mailbox only receives frames with the format specified in the RTR bit
The transmit mailbox only transmits frames with the format specified in the RTR bit
The receive FIFO mailbox receives the data frame, remote frame, or both frames specified in the RTR bit in the
FIDCR0 and FIDCR1 registers
The transmit FIFO mailbox transmits the data frame or remote frame as specified in the RTR bit in the relevant
transmit message.
IDE bit (ID Extension)
The IDE bit sets the ID format to standard ID or extended ID. The IDE bit is enabled when the IDFM[1:0] bits in the
CTLR register are 10b (mixed ID mode):
The receive mailbox receives only the ID format specified in the IDE bit
The transmit mailbox transmits with the ID format specified in the IDE bit
The receive FIFO mailbox receives messages with the standard ID and extended ID settings specified in the IDE bit
in the FIDCR0 and FIDCR1 registers
The transmit FIFO mailbox transmits messages with the standard ID or extended ID settings specified in the IDE bit
in the transmit message.
DLC[3:0] bits (Data Length Code)
The DLC[3:0] bits specify the data length to be transmitted in data frames. When a remote frame is used to request data,
this field specifies the requested data length.
When a data frame is received, the received data length is stored in this field. When a remote frame is received, this field
stores the requested data length.
31.2.7
Mailbox Interrupt Enable Register (MIER)
Address(es): CAN0.MIER 4005 042Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MB31
MB30
MB29
MB28
MB27
MB26
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MB31 to MB0
Interrupt Enable
0: Disable interrupt
1: Enable Interrupt.
Bit [31] is associated with mailbox 31 (MB31), and bit [0] with
mailbox 0 (MB0).
R/W
The MIER register can enable interrupts for each mailbox independently. This register is available in normal mailbox
mode. Do not access this register in FIFO mailbox mode.
Each bit is associated with a mailbox with the same number. These bits enable or disable transmission and reception
complete interrupts for the associated mailboxes as follows:
Bit [0] in MIER is associated with mailbox 0 (MB0)
Bit [31] in MIER is associated with mailbox 31 (MB31).
Write to MIER only when the associated MCTL_TXj or MCTL_RXj (j = 0 to 31) register is 00h and the associated
mailbox is not processing a transmission or reception abort request.
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31.2.8
31. Controller Area Network (CAN) Module
Mailbox Interrupt Enable Register for FIFO Mailbox Mode (MIER_FIFO)
Address(es): CAN0.MIER_FIFO 4005 042Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
MB29
MB28
—
—
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b23 to b0
MB23 to MB0
Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
Bit [23] is associated with mailbox 23 (MB23), and bit [0] is
associated with mailbox 0 (MB0).
R/W
b24
MB24
Transmit FIFO Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b25
MB25
Transmit FIFO Interrupt
Generation Timing Control
0: Generated every time transmission completes
1: Generated when the transmit FIFO empties on transmission
completion.
R/W
b27, b26
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b28
MB28
Receive FIFO Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b29
MB29
Receive FIFO Interrupt
Generation Timing Control*1
0: Generated every time reception completes
1: Generated when the receive FIFO becomes a buffer warning*2
on reception completion.
R/W
b31, b30
—
Reserved
The read value is undefined. The write value should be 0.
R/W
Note 1.
Note 2.
No interrupt request is generated when the receive FIFO becomes a buffer warning because it is full.
Buffer warning indicates a state in which the third message is stored in the receive FIFO.
The MIER_FIFO register allows independent enabling of interrupts for each mailbox and FIFO. This register is available
in FIFO mailbox mode. Do not access this register in normal mailbox mode.
MB0 to MB23 bits are associated with the mailbox with the same number. These bits enable or disable transmission and
reception complete interrupts for the associated mailboxes:
Bit [0] in MIER_FIFO is associated with mailbox 0 (MB0)
Bit [23] in MIER_FIFO is associated with mailbox 23 (MB23).
MB24, MB25, MB28 and MB29 bits specify whether the transmit and receive FIFO interrupts are enabled or disabled,
and the timing of interrupt requests.
Write to the MIER_FIFO register only when the associated MCTL_TXj or MCTL_RXj (j = 0 to 31) register is 00h and
the associated mailbox does not process a transmission or reception abort request. In addition, change the bits in
MIER_FIFO for the associated FIFO only when all the following conditions are true:
The TFE bit in TFCR is 0 and the TFEST bit is 1
The RFE bit in RFCR is 0 and the RFEST flag in RFCR is 1.
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31.2.9
31. Controller Area Network (CAN) Module
Message Control Registers for Transmit (MCTL_TXj) (j = 0 to 31)
Transmit mode (when the TRMREQ bit is 1 and the RECREQ bit is 0)
Address(es): CAN0.MCTL_TX0 4005 0820h to CAN0.MCTL_TX31 4005 083Fh
b7
b6
TRMRE RECRE
Q
Q
Value after reset:
0
0
b5
b4
b3
—
ONESH
OT
—
0
0
0
b2
b1
b0
TRMAB TRMAC SENTD
T
TIVE
ATA
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SENTDATA
Transmission Complete
Flag*1, *2
0: Transmission not complete
1: Transmission complete.
R/W
b1
TRMACTIVE
Transmission-in-Progress
Status Flag
0: Transmission pending or transmission not requested
1: Transmission in progress.
R
b2
TRMABT
Transmission Abort Complete
Flag*1, *2
0: Transmission started, transmission abort failed because
transmission completed, or transmission abort not requested
1: Transmission abort complete.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
0: Disable one-shot transmission
1: Enable one-shot transmission.
R/W
Enable*2, *3
b4
ONESHOT
One-Shot
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
RECREQ
Receive Mailbox Request*2,
*3, *4, *5
0: Do not configure for reception
1: Configure for reception.
R/W
b7
TRMREQ
Transmit Mailbox Request*2,
*4
0: Do not configure for transmission
1: Configure for transmission.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Write 0 only. Writing 1 has no effect.
When writing to the bits in this register, write 1 to the SENTDATA and TRMABT flags if these bits are not the write target.
To enter one-shot transmit mode, write 1 to the ONESHOT bit at the same time as setting the TRMREQ bit to 1.
To exit one-shot transmit mode, write 0 to the ONESHOT bit after the message is transmitted or aborted.
Do not set both the RECREQ and TRMREQ bits to 1.
When setting the RECREQ bit to 0, set the SENDDATA, TRMACTIVE, and TRMABT flags to 0 simultaneously.
The MCTL_TXj register sets the mailbox j to transmit mode or receive mode. In transmit mode, MCTL_TXj also
controls and indicates the transmission status. Do not access the MCTL_TXj register if the mailbox j is in receive mode.
Only write to the MCTL_TXj register in CAN operation mode or halt mode. Do not use the MCTL_TX24 to
MCTL_TX31 registers in FIFO mailbox mode.
SENTDATA flag (Transmission Complete Flag*1, *2)
The SENTDATA flag is set to 1 when data transmission from the associated mailbox is complete. This flag is set to 0
through a software write. To set this flag to 0, first set the TRMREQ bit to 0. The SENTDATA and TRMREQ bits cannot
be set to 0 simultaneously. To transmit a new message from the associated mailbox, set the SENTDATA flag to 0.
TRMACTIVE flag (Transmission-in-Progress Status Flag)
The TRMACTIVE flag is set to 1 when the associated mailbox of the CAN module begins to transmit a message. It is set
to 0 when the CAN module loses the CAN bus arbitration, when a CAN bus error occurs, or when data transmission
completes.
TRMABT flag (Transmission Abort Complete Flag*1, *2)
The TRMABT flag is set to 1 in the following cases:
Following a transmission abort request, when the transmission abort completes before starting transmission
Following a transmission abort request, when the CAN module detects CAN bus arbitration-lost or CAN bus error
In one-shot transmission mode (RECREQ = 0, TRMREQ = 1, and ONESHOT = 1), when the CAN module detects
CAN bus arbitration-lost or CAN bus error.
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31. Controller Area Network (CAN) Module
The TRMABT flag does not set to 1 when data transmission is complete. The SENTDATA flag is set to 1 and the
TRMABT flag is set to 0 through a software write.
ONESHOT bit (One-Shot Enable*2, *3)
When the ONESHOT bit is set to 1 in transmit mode (RECREQ = 0 and TRMREQ = 1), the CAN module transmits a
message only one time. The CAN module does not transmit the message again if a CAN bus error or CAN bus
arbitration-lost occurs. When transmission is complete, the SENTDATA flag is set to 1. If transmission does not
complete because of a CAN bus error or CAN bus arbitration-lost error, the TRMABT flag is set to 1. Set the ONESHOT
bit to 0 after the SENTDATA or TRMABT flag is set to 1.
RECREQ bit (Receive Mailbox Request*2, *3, *4, *5)
The RECREQ bit selects the receive modes listed in Table 31.10.
When the RECREQ bit is set to 1, the associated mailbox is configured for reception of a data frame or remote frame.
When the RECREQ bit is set to 0, the associated mailbox is not configured for reception of a data frame or remote frame.
Due to hardware protection, the RECREQ bit cannot be set to 0 through a software write during the following period:
Hardware protection is started from acceptance filter processing (the beginning of the CRC field)
Hardware protection is released:
For the mailbox that is specified to receive the incoming message, after the received data is stored in the mailbox
or a CAN bus error occurs. This means that the maximum period of hardware protection is from the beginning of
the CRC field to the end of the 7th bit of EOF.
For the other mailboxes, after acceptance filter processing
If no mailbox is specified to receive the message, after acceptance filter processing.
When setting the RECREQ bit to 1, do not set the TRMREQ bit to 1. To change the configuration of a mailbox from
transmission to reception, first abort the transmission, then set the SENTDATA and TRMABT flags to 0 before changing
to reception.
Note:
MCTL_TXj.RECREQ is the mirror bit of MCTL_RXj.RECREQ.
TRMREQ bit (Transmit Mailbox Request*2, *4)
The TRMREQ bit selects the transmit modes listed in Table 31.10.
When the TRMREQ bit is set to 1, the associated mailbox is configured for transmission of a data frame or remote frame.
When the TRMREQ bit is set to 0, the associated mailbox is not configured for transmission of a data frame or remote
frame.
If the TRMREQ bit is changed from 1 to 0 to cancel the associated transmission request, either the TRMABT or
SENTDATA flag is set to 1. When setting the TRMREQ bit to 1, do not set the RECREQ bit to 1. To change the
configuration of a mailbox from reception to transmission, first abort the reception, then set the NEWDATA and
MSGLOST flags to 0 before changing to transmission.
Note:
MCTL_TXj.TRMREQ is the mirror bit of MCTL_RXj.TRMREQ.
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31.2.10
31. Controller Area Network (CAN) Module
Message Control Register for Receive (MCTL_RXj) (j = 0 to 31)
Receive mode (when the TRMREQ bit is 0 and the RECREQ bit is 1)
Address(es): CAN0.MCTL_RX0 4005 0820h to CAN0.MCTL_RX31 4005 083Fh
b7
b6
TRMRE RECRE
Q
Q
Value after reset:
Bit
0
0
Symbol
b5
b4
b3
—
ONESH
OT
—
0
0
0
b2
b1
b0
MSGL INVALD NEWD
OST
ATA
ATA
0
Bit name
Flag*1, *2
0
0
Description
R/W
0: No data received, or 0 was written to the bit
1: New message is being stored or was stored in the mailbox.
R/W
b0
NEWDATA
Reception Complete
b1
INVALDATA
Reception-in-Progress Status
Flag
0: Message valid
1: Message being updated.
R
b2
MSGLOST
Message Lost Flag*1, *2
0: Message not overwritten or overrun
1: Message overwritten or overrun.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
ONESHOT
One-Shot Enable*2, *3
0: Disable one-shot reception
1: Enable one-shot reception.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
0: Do not configure for reception
1: Configure for reception.
R/W
0: Do not configure for transmission
1: Configure for transmission.
R/W
Request*2,
b6
RECREQ
Receive Mailbox
*3, *4, *5
b7
TRMREQ
Transmit Mailbox Request*2,
*4
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Write 0 only. Writing 1 has no effect.
When writing to bits in this register, write 1 to the NEWDATA and MSGLOST flags if these bits are not the write target.
To enter one-shot receive mode, write 1 to the ONESHOT bit at the same time as setting the RECREQ bit to 1.
To exit one-shot receive mode, write 0 to the ONESHOT bit after writing 0 to the RECREQ bit and confirming that it is 0.
Do not set both the RECREQ and TRMREQ bits to 1.
When setting the RECREQ bit to 0, set MSGLOST, NEWDATA, and RECREQ to 0 simultaneously.
The MCTL_RXj register sets mailbox j to transmit mode or receive mode. In receive mode, MCTL_RXj also controls
and indicates the reception status. Do not access the MCTL_RXj register if mailbox j is in transmit mode. Only write to
the MCTL_RXj register in CAN operation mode or halt mode. Do not use the MCTL_RX24 to MCTL_RX31 registers
in FIFO mailbox mode.
NEWDATA flag (Reception Complete Flag*1, *2)
The NEWDATA flag is set to 1 when a new message is being stored or was stored in the mailbox. Always set this bit to 1
simultaneously with the INVALDATA flag. The NEWDATA flag is cleared to 0 through a software write. The
NEWDATA flag cannot be cleared to 0 through a software write while the associated INVALDATA flag is 1.
INVALDATA flag (Reception-in-Progress Status Flag)
After the completion of a message reception, the INVALDATA flag is set to 1 while the received message is updated in
the associated mailbox. The INVALDATA flag is set to 0 immediately after the message is stored. If the mailbox is read
while the INVALDATA flag is 1, the data is undefined.
MSGLOST flag (Message Lost Flag*1, *2)
The MSGLOST flag is set to 1 when the mailbox is overwritten or overrun by a new received message while the
NEWDATA flag is 1. The MSGLOST flag is set to 1 at the end of the 6th bit of EOF. The MSGLOST flag is set to 0
through a software write.
In both overwrite and overrun modes, the MSGLOST flag cannot be set to 0 through a software write during the 5
PCLKB cycles following the 6th bit of EOF.
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31. Controller Area Network (CAN) Module
ONESHOT bit (One-Shot Enable*2, *3)
When the ONESHOT bit is set to 1 in receive mode (RECREQ = 1 and TRMREQ = 0), the mailbox receives a message
only one time. The mailbox does not behave as a receive mailbox after it receives the message. The behavior of the
NEWDATA and INVALDATA flags is the same as in normal receive mode. In one-shot receive mode, the MSGLOST
flag does not set to 1. To set the ONESHOT bit to 0, first write 0 to the RECREQ bit and ensure that it is 0.
RECREQ bit (Receive Mailbox Request*2, *3, *4, *5)
The RECREQ bit selects the receive modes listed in Table 31.10.
When the RECREQ bit is set to 1, the associated mailbox is configured for reception of a data frame or remote frame.
When the RECREQ bit is set to 0, the associated mailbox is not configured for reception of a data frame or remote frame.
Due to hardware protection, the RECREQ bit cannot be set to 0 through a software write during the following period:
Hardware protection is started from the acceptance filter processing (the beginning of the CRC field)
Hardware protection is released:
For the mailbox that is specified to receive the incoming message, after the received data is stored in the
mailbox, or a CAN bus error occurs. The maximum period of hardware protection is from the beginning of the
CRC field to the end of the 7th bit of EOF.
For the other mailboxes, after acceptance filter processing
If no mailbox is specified to receive the message, after acceptance filter processing.
When setting the RECREQ bit to 1, do not set the TRMREQ bit to 1. To change the configuration of a mailbox from
transmission to reception, first abort the transmission, then set the SENTDATA and TRMABT flags to 0 before changing
to reception.
Note:
MCTL_RXj.RECREQ is the mirror bit of MCTL_TXj.REQREQ.
TRMREQ bit (Transmit Mailbox Request*2, *4)
The TRMREQ bit selects the transmit modes listed in Table 31.10.
When the TRMREQ bit is set to 1, the associated mailbox is configured for transmission of a data frame or a remote
frame. When the TRMREQ bit is set to 0, the associated mailbox is not configured for transmission of a data frame or
remote frame.
If the TRMREQ bit is changed from 1 to 0 to cancel the associated transmission request, either the TRMABT flag or the
SENTDATA flag is set to 1. When setting the TRMREQ bit to 1, do not set the RECREQ bit to 1. To change the
configuration of a mailbox from reception to transmission, first abort the reception, and then set the NEWDATA and
MSGLOST flags to 0 before changing to transmission.
Note:
MCTL_RXj.TRMREQ is the mirror bit of MCTL_TXj.TRMREQ.
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31.2.11
31. Controller Area Network (CAN) Module
Receive FIFO Control Register (RFCR)
Address(es): CAN0.RFCR 4005 0848h
b7
b6
b5
b4
b3
RFEST RFWST RFFST RFMLF
Value after reset:
1
0
0
0
b2
b1
b0
RFUST[2:0]
0
0
RFE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RFE
Receive FIFO Enable
0: Disable receive FIFO
1: Enable receive FIFO.
R/W
b3 to b1
RFUST[2:0]
Receive FIFO Unread Message
Number Status
b3
R
b4
RFMLF
Receive FIFO Message Lost Flag
0: Receive FIFO message not lost
1: Receive FIFO message lost.
R/W
b5
RFFST
Receive FIFO Full Status Flag
0: Receive FIFO not full
1: Receive FIFO full (4 unread messages).
R
b6
RFWST
Receive FIFO Buffer Warning
Status Flag
0: Receive FIFO has no buffer warning
1: Receive FIFO has buffer warning (3 unread messages).
R
b7
RFEST
Receive FIFO Empty Status Flag
0: Unread message in receive FIFO
1: No unread message in receive FIFO.
R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b1
0: No unread message
1: 1 unread message
0: 2 unread messages
1: 3 unread messages
0: 4 unread messages
1: Reserved
0: Reserved
1: Reserved.
Write to the RFCR register in CAN operation or halt mode.
RFE bit (Receive FIFO Enable)
When the RFE bit is set to 1, the receive FIFO is enabled. When the RFE bit is set to 0, the receive FIFO is disabled for
reception and becomes empty (RFEST = 1). Write 0 to the RFE bit simultaneously with the RFMLF flag setting.
Do not set this bit to 1 in normal mailbox mode (MBM = 0). Due to hardware protection, the RFE bit cannot be set to 0
through a software write during the following period:
Hardware protection is started from the acceptance filter processing (the beginning of the CRC field)
Hardware protection is released:
If the receive FIFO is specified to receive the incoming message, after the received data is stored into the receive
FIFO or a CAN bus error occurs. The maximum period of hardware protection is from the beginning of the CRC
field to the end of 7th bit of EOF.
If the receive FIFO is not specified to receive the message, after acceptance filter processing.
RFUST[2:0] bits (Receive FIFO Unread Message Number Status)
The RFUST[2:0] bits indicate the number of unread messages in the receive FIFO. The value of the RFUST[2:0] bits is
initialized to 000b when the RFE bit is set to 0.
RFMLF flag (Receive FIFO Message Lost Flag)
The RFMLF flag is set to 1 (receive FIFO message lost) when the receive FIFO receives a new message and is full. This
flag is set to 1 at the end of the 6th bit of EOF.
The RFMLF flag is set to 0 through a software write. Writing 1 has no effect. In both overwrite and overrun modes, if the
receive FIFO is full and determined to have received a message, the RFMLF flag cannot be set to 0 (no receive FIFO
message lost) through a software write because of hardware protection during 5 PCLKB cycles following the 6th bit of
EOF.
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31. Controller Area Network (CAN) Module
RFFST flag (Receive FIFO Full Status Flag)
The RFFST flag is set to 1 (receive FIFO is full) when the number of unread messages in the receive FIFO is 4. The
RFFST flag is 0 (receive FIFO is not full) when the number of unread messages in the receive FIFO is less than 4. The
RFFST flag is set to 0 when the RFE bit is 0.
RFWST flag (Receive FIFO Buffer Warning Status Flag)
The RFWST flag is set to 1 (receive FIFO buffer warning) when the number of unread messages in the receive FIFO is 3.
The RFWST flag is 0 (no receive FIFO buffer warning) when the number of unread messages in the receive FIFO is less
than 3 or equal to 4. The RFWST flag is set to 0 when the RFE bit is 0.
RFEST flag (Receive FIFO Empty Status Flag)
The RFEST flag is set to 1 (no unread message in receive FIFO) when the number of unread messages in the receive
FIFO is 0. The RFEST flag is set to 1 when the RFE bit is set to 0. The RFEST flag is set to 0 (unread message in receive
FIFO) when the number of unread messages in the receive FIFO is one or more.
Figure 31.2 shows the receive FIFO mailbox operation.
Receive FIFO mailbox
Frame 1
Frame 2
Frame 3
Frame 4
CAN bus
Internal bus
Frame 1 Frame 2 Frame 3 Frame 4
Frame 1 Frame 2 Frame 3 Frame 4
RFCR.RFEST flag
RFCR.RFWST flag
RFCR.RFFST flag
CAN0 receive FIFO interrupt
Bit [29] and bit [28] in MIER_FIFO = 01b
CAN0 receive FIFO interrupt
Bit [29] and bit [28] in MIER_FIFO = 11b
RFPCR
Figure 31.2
Receive FIFO mailbox operation with bit [29] and bit [28] in MIER_FIFO = 01b or 11b
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31.2.12
31. Controller Area Network (CAN) Module
Receive FIFO Pointer Control Register (RFPCR)
Address(es): CAN0.RFPCR 4005 0849h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
Value after reset:
x: Undefined
Bit
Description
R/W
b7 to b0
The CPU pointer for the receive FIFO is incremented by writing FFh to RFPCR
W
When the receive FIFO is not empty, write FFh to the RFPCR register through software to increment the CPU pointer to
the next mailbox location. Do not write to the RFPCR register when the RFE bit in RFCR is 0 (receive FIFO disabled).
Both the CAN and CPU pointers are incremented when a new message is received and the RFFST flag is 1 (receive
FIFO is full) in overwrite mode. When the RFMLF flag is 1 in this state, the CPU pointer does not increment on a
software write to RFPCR.
31.2.13
Transmit FIFO Control Register (TFCR)
Address(es): CAN0.TFCR 4005 084Ah
b7
b6
TFEST TFFST
Value after reset:
1
0
b5
b4
—
—
0
0
b3
b2
b1
b0
TFUST[2:0]
0
0
TFE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TFE
Transmit FIFO Enable
0: Disable transmit FIFO
1: Enable transmit FIFO.
R/W
b3 to b1
TFUST[2:0]
Transmit FIFO Unsent Message
Number Status
b3
R
b5, b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
TFFST
Transmit FIFO Full Status
0: Transmit FIFO not full
1: Transmit FIFO full (4 unsent messages).
R
b7
TFEST
Transmit FIFO Empty Status
0: Unsent message in transmit FIFO
1: No unsent message in transmit FIFO.
R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b1
0: 0 unsent messages
1: 1 unsent message
0: 2 unsent messages
1: 3 unsent messages
0: 4 unsent messages
1: Reserved
0: Reserved
1: Reserved.
Write to TFCR in CAN operation mode or halt mode.
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31. Controller Area Network (CAN) Module
TFE bit (Transmit FIFO Enable)
When the TFE bit is set to 1, the transmit FIFO is enabled.
When the TFE bit is set to 0, the transmit FIFO becomes empty (TFEST bit = 1), and unsent messages from the transmit
FIFO are lost as follows:
Immediately if a message from the transmit FIFO is not scheduled for the next transmission or is already in
transmission
On completion of transmission, on a CAN bus error, CAN bus arbitration-lost, or entry to CAN halt mode, if a
message from the transmit FIFO is scheduled for the next transmission or is already in transmission.
Before setting the TFE bit to 1 again, ensure that the TFEST bit is set to 1. After setting the TFE bit to 1, write transmit
data to mailbox 24.
Do not set the TFE bit to 1 in normal mailbox mode (MBM bit in CTLR = 0).
TFUST[2:0] bits (Transmit FIFO Unsent Message Number Status)
The TFUST[2:0] bits indicate the number of unsent messages in the transmit FIFO. These bits are set to 000b after the
TFE bit is set to 0 and transmission aborts or completes.
TFFST bit (Transmit FIFO Full Status)
The TFFST bit is set to 1 (transmit FIFO is full) when the number of unsent messages in the transmit FIFO is 4. The
TFFST bit is set to 0 (transmit FIFO is not full) when the number of unsent messages in the transmit FIFO is less than 4.
The TFFST bit is set to 0 when transmission from the transmit FIFO is aborted.
TFEST bit (Transmit FIFO Empty Status)
The TFEST bit is set to 1 (no message in transmit FIFO) when the number of unsent messages in the transmit FIFO is 0.
The TFEST bit is set to 1 when transmission from the transmit FIFO is aborted. The TFEST bit is set to 0 (message in
transmit FIFO) when the number of unsent messages in the transmit FIFO is not 0.
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31. Controller Area Network (CAN) Module
Figure 31.3 shows the transmit FIFO mailbox operation.
Transmit FIFO mailbox
Frame 1
Frame 2
Frame 3
Frame 4
CAN bus
Frame 1 Frame 2 Frame 3 Frame 4
Frame 1 Frame 2 Frame 3 Frame 4
Internal bus
TFCR.TFEST flag
TFCR.TFFST bit
CAN0 transmit FIFO interrupt
Bit [25] and bit [24] in MIER_FIFO = 01b
CAN0 transmit FIFO interrupt
Bit [25] and bit [24] in MIER_FIFO = 11b
TFPCR
Figure 31.3
31.2.14
Transmit FIFO mailbox operation when bit [25] and bit [24] in MIER_FIFO = 01b or 11b
Transmit FIFO Pointer Control Register (TFPCR)
Address(es): CAN0.TFPCR 4005 084Bh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b7 to b0
The CPU pointer for the transmit FIFO is incremented by writing FFh to TFPCR
W
When the transmit FIFO is not full, write FFh to the TFPCR register through software to increment the CPU pointer for
the transmit FIFO to the next mailbox location.
Do not write to the TFPCR register when the TFE bit in TFCR is 0 (transmit FIFO disabled).
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31.2.15
31. Controller Area Network (CAN) Module
Status Register (STR)
Address(es): CAN0.STR 4005 0842h
b15
—
Value after reset:
0
b14
b13
b12
RECST TRMST BOST
0
0
b11
b10
b9
b8
EPST SLPST HLTST RSTST
0
0
1
0
1
b7
EST
0
b6
b5
b4
b3
TABST FMLST NMLST TFST
0
0
0
0
b2
b1
b0
RFST
SDST
NDST
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
NDST
NEWDATA Status Flag
0: No mailbox with NEWDATA = 1
1: 1 or more mailboxes with NEWDATA = 1.
R
b1
SDST
SENTDATA Status Flag
0: No mailbox with SENTDATA = 1
1: 1 or more mailboxes with SENTDATA = 1.
R
b2
RFST
Receive FIFO Status Flag
0: Receive FIFO empty
1: Message in receive FIFO.
R
b3
TFST
Transmit FIFO Status Flag
0: Transmit FIFO full
1: Transmit FIFO not full.
R
b4
NMLST
Normal Mailbox Message Lost
Status Flag
0: No mailbox with MSGLOST = 1
1: 1 or more mailboxes with MSGLOST = 1.
R
b5
FMLST
FIFO Mailbox Message Lost Status
Flag
0: RFMLF = 0
1: RFMLF = 1.
R
b6
TABST
Transmission Abort Status Flag
0: No mailbox with TRMABT = 1
1: 1 or more mailboxes with TRMABT = 1.
R
b7
EST
Error Status Flag
0: No error occurred
1: Error occurred.
R
b8
RSTST
CAN Reset Status Flag
0: Not in CAN reset mode
1: In CAN reset mode.
R
b9
HLTST
CAN Halt Status Flag
0: Not in CAN halt mode
1: In CAN halt mode.
R
b10
SLPST
CAN Sleep Status Flag
0: Not in CAN sleep mode
1: In CAN sleep mode.
R
b11
EPST
Error-Passive Status Flag
0: Not in error-passive state
1: In error-passive state.
R
b12
BOST
Bus-Off Status Flag
0: Not in bus-off state
1: In bus-off state.
R
b13
TRMST
Transmit Status Flag
0: Bus idle or reception in progress
1: Transmission in progress or in bus-off state.
R
b14
RECST
Receive Status Flag
0: Bus idle or transmission in progress
1: Reception in progress.
R
b15
—
Reserved
The read value is 0
R
NDST flag (NEWDATA Status Flag)
The NDST flag is set to 1 when at least one NEWDATA flag in the MCTL_RXj (j = 0 to 31) registers is 1 regardless of
the value of the MIER or MIER_FIFO registers. The NDST flag is set to 0 when all the NEWDATA flags are 0.
SDST flag (SENTDATA Status Flag)
The SDST flag is set to 1 when at least one SENTDATA flag in the MCTL_TXj (j = 0 to 31) registers is 1 regardless of
the value of the MIER or MIER_FIFO registers. The SDST flag is set to 0 when all the SENTDATA flags are 0.
RFST flag (Receive FIFO Status Flag)
The RFST flag is set to 1 when the receive FIFO is not empty. The RFST flag is set to 0 when the receive FIFO is empty
or normal mailbox mode is selected.
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31. Controller Area Network (CAN) Module
TFST flag (Transmit FIFO Status Flag)
The TFST flag is set to 1 when the transmit FIFO is not full. The TFST flag is set to 0 when the transmit FIFO is full or
normal mailbox mode is selected.
NMLST flag (Normal Mailbox Message Lost Status Flag)
The NMLST flag is set to 1 when at least one MSGLOST flag in MCTL_RXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. The NMLST flag is set to 0 when all MSGLOST flags are 0.
FMLST flag (FIFO Mailbox Message Lost Status Flag)
The FMLST flag is set to 1 when the RFMLF flag in RFCR is 1, regardless of the value of MIER_FIFO. The FMLST
flag is set to 0 when the RFMLF flag is 0.
TABST flag (Transmission Abort Status Flag)
The TABST flag is set to 1 when at least one TRMABT flag in the MCTL_TXj (j = 0 to 31) registers is 1, regardless of
the value of the MIER or MIER_FIFO registers. The TABST flag is set to 0 when all TRMABT flags are 0.
EST flag (Error Status Flag)
The EST flag is set to 1 when at least one error is detected by the EIFR register regardless of the value of the EIER
register. The EST flag is set to 0 when no error is detected by EIFR.
RSTST flag (CAN Reset Status Flag)
The RSTST flag is set to 1 when the CAN module is in CAN reset mode. The RSTST flag is 0 when the CAN module is
not in CAN reset mode. The flag remains 1, even when the state changes from CAN reset to sleep mode.
HLTST flag (CAN Halt Status Flag)
The HLTST flag is set to 1 when the CAN module is in CAN halt mode. The HLTST flag is set to 0 when the CAN
module is not in CAN halt mode. The flag remains 1, even when the state changes from CAN halt to sleep mode.
SLPST flag (CAN Sleep Status Flag)
The SLPST flag is set to 1 when the CAN module is in CAN sleep mode. The SLPST flag is set to 0 when the CAN
module is not in CAN sleep mode.
EPST flag (Error-Passive Status Flag)
The EPST flag is set to 1 when the value in the TECR or RECR registers exceeds 127 and the CAN module is in an errorpassive state (128 ≤ TEC < 256 or 128 ≤ REC < 256). The EPST flag is set to 0 when the CAN module is not in the errorpassive state.
BOST flag (Bus-Off Status Flag)
The BOST flag is set to 1 when the value in the TECR register exceeds 255 and the CAN module is in the bus-off state
(TEC ≥ 256). The BOST flag is set to 0 when the CAN module is not in the bus-off state.
TRMST flag (Transmit Status Flag)
The TRMST flag is set to 1 when the CAN module performs as a transmitter node or is in the bus-off state. The TRMST
flag is set to 0 when the CAN module performs as a receiver node or is in the bus-idle state.
RECST flag (Receive Status Flag)
The RECST flag is set to 1 when the CAN module performs as a receiver node. The RECST flag is set to 0 when the
CAN module performs as a transmitter node or is in the bus-idle state.
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31.2.16
31. Controller Area Network (CAN) Module
Mailbox Search Mode Register (MSMR)
Address(es): CAN0.MSMR 4005 0853h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MBSM[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
MBSM[1:0]
Mailbox Search Mode Select
b1 b0
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: Receive mailbox search mode
1: Transmit mailbox search mode
0: Message lost search mode
1: Channel search mode.
Write to the MSMR register in CAN operation or halt mode.
MBSM[1:0] bits (Mailbox Search Mode Select)
The MBSM[1:0] bits select the search mode for the mailbox search function.
When the MBSM[1:0] bits are 00b, receive mailbox search mode is selected. In this mode, the search targets are the
NEWDATA flag in the MCTL_RXj (j = 0 to 31) registers for the normal mailbox, and the RFEST flag in the RFCR
register.
When the MBSM[1:0] bits are 01b, transmit mailbox search mode is selected. In this mode, the search target is the
SENTDATA flag in the MCTL_TXj register.
When the MBSM[1:0] bits are 10b, message lost search mode is selected. In this mode, the search targets are the
MSGLOST flag in the MCTL_RXj register for the normal mailbox, and the RFMLF flag in the RFCR register.
When the MBSM[1:0] bits are 11b, channel search mode is selected. In this mode, the search target is the CSSR register.
See section 31.2.18, Channel Search Support Register (CSSR).
31.2.17
Mailbox Search Status Register (MSSR)
Address(es): CAN0.MSSR 4005 0852h
Value after reset:
b7
b6
b5
SEST
—
—
1
0
0
b4
b3
b2
b1
b0
0
0
MBNST[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
MBNST[4:0]
Search Result Mailbox
Number Status
These bits output the smallest mailbox number that is found in each
search mode selected in the MSMR register
R
b6, b5
—
Reserved
These bits are read as 0
R
b7
SEST
Search Result Status
0: Search result found
1: No search result.
R
MBNST[4:0] bits (Search Result Mailbox Number Status)
In all mailbox search modes, the MBNST[4:0] bits output the smallest mailbox number. In receive mailbox search mode,
transmit mailbox search mode, and message lost search mode, the value of the mailbox (the search result to be output) is
updated under the following conditions:
When the associated NEWDATA, SENTDATA, or MSGLOST flag is set to 0 for a mailbox output by
MBNST[4:0]
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31. Controller Area Network (CAN) Module
When the associated NEWDATA, SENTDATA, or MSGLOST flag is set to 1 for a mailbox with a smaller number
than that in MBNST[4:0].
If the MBSM[1:0] bits are set to 00b (receive mailbox search mode) or 10b (message lost search mode), the receive FIFO
(mailbox 28) is output when it is not empty and there are no unread received messages or no lost messages in any of the
normal mailboxes 0 to 23. If the MBSM[1:0] bits are set to 01b (transmit mailbox search mode), the transmit FIFO
(mailbox 24) is not output. Table 31.6 shows the behavior of the MBNST[4:0] bits in FIFO mailbox mode.
In channel search mode, the MBNST[4:0] bits output the associated channel number. After the MSSR register is read by
software, the next target channel number is output.
SEST bit (Search Result Status)
The SEST bit is set to 1 (no search result) when no associated mailbox is found after searching all the mailboxes. For
example, in transmit mailbox search mode, the SEST bit is set to 1 when no SENTDATA flag is 1 for any mailbox. The
SEST bit is set to 0 when at least one SENTDATA flag is 1. When the SEST bit is 1, the value of the MBNST[4:0] bits is
undefined.
Table 31.6
Behavior of MBNST[4:0] bits in FIFO mailbox mode
MBSM[1:0] bits
Mailbox 24 (transmit FIFO)
Mailbox 28 (receive FIFO)
00b
Mailbox 24 is not output
Mailbox 28 is output when no MCTL_RXj.NEWDATA flag for the normal
mailboxes is set to 1 (no message is being stored or was stored to the mailbox)
and the receive FIFO is not empty
01b
Mailbox 28 is not output
10b
Mailbox 28 is output when no MCTL_RXj.MSGLOST flag for the normal
mailboxes is set to 1 (no message is overwritten or overrun) and the
RFCR.RFMLF flag is set to 1 (receive FIFO message was lost) in the receive
FIFO
11b
Mailbox 28 is not output
31.2.18
Channel Search Support Register (CSSR)
Address(es): CAN0.CSSR 4005 0851h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b7 to b0
When the value for the channel search is input, the channel number is output to the MSSR register
R/W
The bits that are set to 1 in the CSSR register are encoded by an 8/3 encoder (the LSB position has the higher priority)
and output to the MBNST[4:0] bits in the MSSR register. The MSSR register outputs the updated value whenever MSSR
is read by software.
Write to the CSSR register only when the MBSM[1:0] bits in the MSMR register are 11b (channel search mode). Write
to the CSSR register in CAN operation mode or CAN halt mode.
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31. Controller Area Network (CAN) Module
Figure 31.4 shows the write and read operations of the CSSR and MSSR registers.
Address
CSSR
b7
b6
0
1
b3
0
0
1
0
0
b0
CAN0
1
4005 0851h
8/3 encoder
CAN0
MSSR
b7
b0
(1st read)
0
0
0
0
0
0
0
0
(Search result: Channel number 0 read)
(2nd read)
0
0
0
0
0
0
1
1
(Search result: Channel number 3 read)
rd
0
0
0
0
0
1
1
0
(Search result: Channel number 6 read)
th
1
0
0
(3 read)
(4 read)
Figure 31.4
b2
4005 0852h
(Search result: No corresponding channel number )
Write and read operation of CSSR and MSSR Registers
The value of the CSSR register is also updated whenever the MSSR register is read. On this read, the value prior to
conversion by the 8/3 encoder can be read.
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31.2.19
31. Controller Area Network (CAN) Module
Acceptance Filter Support Register (AFSR)
Address(es): CAN0.AFSR 4005 0856h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b15 to b0
After the standard ID of a received message is written, the value converted for data table search can be read
R/W
Note:
Write to AFSR in CAN operation mode or halt mode.
The acceptance filter support unit (ASU) can be used for data table (8 bits × 256) searches. In the data table, all standard
IDs that you create are set to be valid or invalid in bit units. When the AFSR register is written with data in 16-bit units
including the SID[10:0] bits in the MBj_ID (j = 0 to 31) register, in which a received standard ID is stored, a decoded
row (byte offset) position and column (bit) position for data table search can be read. The ASU can be used for standard
(11-bit) IDs only.
The ASU is enabled in the following cases:
When the ID to be received cannot be masked by the acceptance filter.
For example, if the IDs to be received are 078h, 087h, and 111h.
When there are too many IDs to receive, and the software filtering time is expected to be shortened.
Note:
The AFSR register cannot be set in CAN reset mode.
Figure 31.5 shows the write and read operation in the AFSR register.
Address
b15
When writing*
b8
b7
b0
SID SID SID SID SID SID SID SID SID SID SID
10
9
8
7
6
5
4
3
2
1
0
1
CAN0
4005 0856h
3/8 decoder
b15
b8
When reading
Column (bit) position in data table
Note 1.
Figure 31.5
b7
b0
SID SID SID SID SID SID SID SID
10
9
8
7
6
5
4
3
CAN0
4005 0856h
Row (byte offset) position in data table
Write the same value as the 16-bit unit data including the SID[10:0] bits in MBj_ID (j = 0 to 31).
Write and read operations in the AFSR register
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31.2.20
31. Controller Area Network (CAN) Module
Error Interrupt Enable Register (EIER)
Address(es): CAN0.EIER 4005 084Ch
Value after reset:
b7
b6
b5
BLIE
OLIE
ORIE
0
0
0
b4
b3
BORIE BOEIE
0
b2
b1
b0
EPIE
EWIE
BEIE
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BEIE
Bus Error Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b1
EWIE
Error-Warning Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b2
EPIE
Error-Passive Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b3
BOEIE
Bus-Off Entry Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b4
BORIE
Bus-Off Recovery Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b5
ORIE
Overrun Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b6
OLIE
Overload Frame Transmit Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b7
BLIE
Bus Lock Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
The EIER register independently enables or disables the error interrupt for each error interrupt source. Write to the EIER
register in CAN reset mode.
BEIE bit (Bus Error Interrupt Enable)
When the BEIE bit is 0, no error interrupt request is generated even if the BEIF flag in the EIFR register is 1. When the
BEIE bit is 1, an error interrupt request is generated if the BEIF flag is set to 1.
EWIE bit (Error-Warning Interrupt Enable)
When the EWIE bit is 0, no error interrupt request is generated even if the EWIF flag in the EIFR register is 1. When the
EWIE bit is 1, an error interrupt request is generated if the EWIF flag is set to 1.
EPIE bit (Error-Passive Interrupt Enable)
When the EPIE bit is 0, no error interrupt request is generated even if the EPIF flag in the EIFR register is 1. When the
EPIE bit is 1, an error interrupt request is generated if the EPIF flag is set to 1.
BOEIE bit (Bus-Off Entry Interrupt Enable)
When the BOEIE bit is 0, no error interrupt request is generated even if the BOEIF flag in the EIFR register is 1. When
the BOEIE bit is 1, an error interrupt request is generated if the BOEIF flag is set to 1.
BORIE bit (Bus-Off Recovery Interrupt Enable)
When the BORIE bit is 0, no error interrupt request is generated even if the BORIF flag in the EIFR register is 1. When
the BORIE bit is set to 1, an error interrupt request is generated if the BORIF flag is set to 1.
ORIE bit (Overrun Interrupt Enable)
When the ORIE bit is 0, no error interrupt request is generated even if the ORIF flag in the EIFR register is 1. When the
ORIE bit is 1, an error interrupt request is generated if the ORIF flag is set to 1.
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31. Controller Area Network (CAN) Module
OLIE bit (Overload Frame Transmit Interrupt Enable)
When the OLIE bit is 0, no error interrupt request is generated even if the OLIF flag in the EIFR register is 1. When the
OLIE bit is 1, an error interrupt request is generated if the OLIF flag is set to 1.
BLIE bit (Bus Lock Interrupt Enable)
When the BLIE bit is 0, no error interrupt request is generated even if the BLIF flag in the EIFR register is 1. When the
BLIE bit is 1, an error interrupt request is generated if the BLIF flag is set to 1.
31.2.21
Error Interrupt Factor Judge Register (EIFR)
Address(es): CAN0.EIFR 4005 084Dh
Value after reset:
b7
b6
b5
BLIF
OLIF
ORIF
0
0
0
b4
b3
BORIF BOEIF
0
0
b2
b1
b0
EPIF
EWIF
BEIF
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BEIF
Bus Error Detect Flag
0: No bus error detected
1: Bus error detected.
R/W
b1
EWIF
Error-Warning Detect Flag
0: No error-warning detected
1: Error-warning detected.
R/W
b2
EPIF
Error-Passive Detect Flag
0: No error-passive detected
1: Error-passive detected.
R/W
b3
BOEIF
Bus-Off Entry Detect Flag
0: No bus-off entry detected
1: Bus-off entry detected.
R/W
b4
BORIF
Bus-Off Recovery Detect Flag
0: No bus-off recovery detected
1: Bus-off recovery detected.
R/W
b5
ORIF
Receive Overrun Detect Flag
0: No receive overrun detected
1: Receive overrun detected.
R/W
b6
OLIF
Overload Frame Transmission
Detect Flag
0: No overload frame transmission detected
1: Overload frame transmission detected.
R/W
b7
BLIF
Bus Lock Detect Flag
0: No bus lock detected
1: Bus lock detected.
R/W
If an event associated with an EIFR flag occurs, the associated bit in EIFR is set to 1 regardless of the setting of EIER.
Clear the bits to 0 through a software write. If a bit is set to 1 at the same time that software clears it, the bit becomes 1.
When setting a single bit to 0 in software, use the transfer instruction (MOV) to ensure that only the specified bit is set to
0 and the other bits are set to 1. Writing 1 has no effect on these bit values.
BEIF flag (Bus Error Detect Flag)
The BEIF flag is set to 1 when a bus error is detected.
EWIF flag (Error-Warning Detect Flag)
The EWIF flag is set to 1 when the value of the receive error counter (REC) or transmit error counter (TEC) exceeds 95.
This flag is set to 1 only when the REC or TEC value initially exceeds 95. If software writes 0 to this flag while the REC
or TEC value remains greater than 95, the EWIF flag is not set to 1 until REC or TEC values go below 95 and then
exceeds 95 again.
EPIF flag (Error-Passive Detect Flag)
The EPIF flag is set to 1 when the CAN error state becomes error-passive, when the REC or TEC value exceeds 127.
This flag is set to 1 only when the REC or TEC initially exceeds 127. If software writes 0 to this flag while the REC or
TEC value remains greater than 127, the EPIF flag is not set to 1 until the REC or TEC value goes below 127 and then
exceeds 127 again.
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31. Controller Area Network (CAN) Module
BOEIF flag (Bus-Off Entry Detect Flag)
The BOEIF flag is set to 1 when the CAN error state becomes bus-off, when the TEC value exceeds 255. This flag is also
set to 1 when the BOM[1:0] bits in CTLR are 01b (automatic entry to CAN halt mode on bus-off entry) and the CAN
module enters the bus-off state.
BORIF flag (Bus-Off Recovery Detect Flag)
The BORIF flag is set to 1 when the CAN module recovers from the bus-off state normally by detecting 11 consecutive
recessive bits 128 times in the following conditions:
When the BOM[1:0] bits in CTLR are 00b
When the BOM[1:0] bits in CTLR are 10b
When the BOM[1:0] bits in CTLR are 11b.
The BORIF flag is not set to 1 if the CAN module recovers from the bus-off state in the following conditions:
When the CANM[1:0] bits in CTLR are set to 01b or 11b (CAN reset mode)
When the RBOC bit in CTLR is set to 1 (forced return from bus-off)
When the BOM[1:0] bits in CTLR are set to 01b
When the BOM[1:0] bits in CTLR are set to 11b and the CANM[1:0] bits in CTLR are set to 10b (CAN halt mode)
before normal recovery occurs.
Table 31.7 shows the behavior of the BOEIF and BORIF flags for each CTLR.BOM[1:0] bit setting.
Table 31.7
Behavior of BOEIF and BORIF flags for each CTLR.BOM[1:0] bit setting
BOM[1:0] bits
BOEIF flag
BORIF flag
00b
Set to 1 on entry to the bus-off state
Set to 1 on exit from the bus-off state
01b
Do not set to 1
10b
Set to 1 on exit from the bus-off state
11b
Set to 1 if normal bus-off recovery occurs before the CANM[1:0] bits are
set to 10b (CAN halt mode)
ORIF flag (Receive Overrun Detect Flag)
The ORIF flag is set to 1 when a receive overrun occurs. This flag does not set to 1 in overwrite mode. In overwrite
mode, a reception complete interrupt request is generated if an overwrite condition occurs and the ORIF flag is not set to
1.
In overrun mode with normal mailbox mode, if an overrun occurs in any of the mailboxes 0 to 31, this flag is set to 1. In
overrun mode with FIFO mailbox mode, if an overrun occurs in any of the mailboxes 0 to 23, or the receive FIFO, this
flag is set to 1.
OLIF flag (Overload Frame Transmission Detect Flag)
The OLIF flag is set to 1 if the transmitting condition of an overload frame is detected when the CAN module is
transmitting or receiving.
BLIF flag (Bus Lock Detect Flag)
The BLIF flag is set to 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN
operation mode. After the BLIF flag is set to 1, 32 consecutive dominant bits are detected again under either of the
following conditions:
Recessive bits are detected after the BLIF flag changes from 0 to 1
The CAN module enters CAN reset mode or halt mode and then enters CAN operation mode again after the BLIF
flag changes from 0 to 1.
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31.2.22
31. Controller Area Network (CAN) Module
Receive Error Count Register (RECR)
Address(es): CAN0.RECR 4005 084Eh
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Description
R/W
b7 to b0
Receive error count function.
RECR increments or decrements the counter value according to the error status of the CAN module during
reception.
R
The RECR register indicates the value of the receive error counter. See the CAN specification (ISO11898-1) for
information on the increment or decrement conditions of the receive error counter. The value of the RECR register in the
bus-off state is undefined.
31.2.23
Transmit Error Count Register (TECR)
Address(es): CAN0.TECR 4005 084Fh
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Description
R/W
b7 to b0
Transmit error count function.
TECR increments or decrements the counter value based on the error status of the CAN module during
transmission.
R
The TECR register indicates the value of the transmit error counter. See the CAN specification (ISO11898-1) for the
increment and decrement conditions of the transmit error counter. The value of the TECR register in the bus-off state is
undefined.
31.2.24
Error Code Store Register (ECSR)
Address(es): CAN0.ECSR 4005 0850h
b7
b6
b5
b4
b3
b2
b1
b0
EDPM
ADEF
BE0F
BE1F
CEF
AEF
FEF
SEF
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
SEF
Stuff Error Flag*1, *2
0: No stuff error detected
1: Stuff error detected.
R/W
b1
FEF
Form Error Flag*1, *2
0: No form error detected
1: Form error detected.
R/W
b2
AEF
ACK Error Flag*1, *2
0: No ACK error detected
1: ACK error detected.
R/W
b3
CEF
CRC Error Flag*1, *2
0: No CRC error detected
1: CRC error detected.
R/W
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Bit
Symbol
31. Controller Area Network (CAN) Module
Bit name
Description
R/W
Flag*1, *2
0: No bit error (recessive) detected
1: Bit error (recessive) detected.
R/W
b4
BE1F
Bit Error (recessive)
b5
BE0F
Bit Error (dominant) Flag*1, *2
0: No bit error (dominant) detected
1: Bit error (dominant) detected.
R/W
b6
ADEF
ACK Delimiter Error Flag*1, *2
0: No ACK delimiter error detected
1: ACK delimiter error detected.
R/W
b7
EDPM
Error Display Mode Select*3, *4
0: Output first detected error code
1: Output accumulated error code.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Writing 1 has no effect on these bit values.
To write 0 to the SEF, FEF, AEF, CEF, BE1F, BE0F, and ADEF bits, use the transfer (MOV) instruction to ensure that only the
specified bit is set to 0 and the other bits are set to 1.
Write to the EDPM bit in CAN reset or CAN halt mode.
If more than one error condition is detected simultaneously, all the related bits are set to 1.
The ECSR register indicates whether an error occurs on the CAN bus. See the CAN specification (ISO11898-1) for the
conditions when each error occurs.
Clear all the bits except the EDPM bit to 0 through a software write. If an ECSR bit is set to 1 at that same time that
software writes 0 to it, the bit is set to 1.
SEF flag (Stuff Error Flag)
The SEF flag is set to 1 when a stuff error is detected.
FEF flag (Form Error Flag)
The FEF flag is set to 1 when a form error is detected.
AEF flag (ACK Error Flag)
The AEF flag is set to 1 when an ACK error is detected.
CEF flag (CRC Error Flag)
The CEF flag is set to 1 when a CRC error is detected.
BE1F flag (Bit Error (recessive) Flag)
The BE1F flag is set to 1 when a recessive bit error is detected.
BE0F flag (Bit Error (dominant) Flag)
The BE0F flag is set to 1 when a dominant bit error is detected.
ADEF flag (ACK Delimiter Error Flag)
The ADEF flag is set to 1 when a form error is detected with the ACK delimiter during transmission.
EDPM bit (Error Display Mode Select)
The EDPM bit selects the output mode of ECSR. When the EDPM bit is set to 0, the ECSR register outputs the first error
code. When the EDPM bit is set to 1, the ECSR register outputs the accumulated error code.
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31.2.25
31. Controller Area Network (CAN) Module
Time Stamp Register (TSR)
Address(es): CAN0.TSR 4005 0854h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
R/W
b15 to b0
Free-running counter value for the time stamp function
R
Note:
Read the TSR register in 16-bit units.
Reading the TSR register returns the current value of the 16-bit free-running time stamp counter. The time stamp counter
reference clock is configured in the TSPS[1:0] bits in CTLR. The counter stops in CAN sleep and halt modes, and is
initialized in CAN reset mode. The time stamp counter value is stored in the TSL[7:0] and TSH[7:0] bits in the MBj_TS
register when a received message is stored in a receive mailbox.
31.2.26
Test Control Register (TCR)
Address(es): CAN0.TCR 4005 0858h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
TSTM[1:0]
0
0
0
0
0
0
b0
TSTE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TSTE
CAN Test Mode Enable
0: Disable CAN test mode
1: Enable CAN test mode.
R/W
b2, b1
TSTM[1:0]
CAN Test Mode Select
b2 b1
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: Not CAN test mode
1: Listen-only mode
0: Self-test mode 0 (external loopback)
1: Self-test mode 1 (internal loopback).
The TCR register controls the CAN test mode. Write to the TCR register in CAN halt mode only.
(1)
Listen-only mode
The CAN specification (ISO11898-1) recommends an optional bus monitoring mode. In listen-only mode, valid data
frames and valid remote frames can be received. However, only the recessive bits can be sent on the CAN bus. The ACK
bit, overload flag, and active error flag cannot be sent. Listen-only mode can be used for baud rate detection. Do not
request transmission from any mailboxes in listen-only mode.
Figure 31.6 shows the connection when listen-only mode is selected.
CTX0
CRX0
Recessive level
CTX0
(internal)
Figure 31.6
CRX0
(internal)
Connection when listen-only mode is selected
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(2)
31. Controller Area Network (CAN) Module
Self-test mode 0 (external loopback)
Self-test mode 0 is provided for CAN transceiver tests. In this mode, the protocol module treats its own transmitted
messages as those received by the CAN transceiver and stores them into the receive mailbox. To be independent from
external stimulation, the protocol module generates the ACK bit. Connect the CTX0 and CRX0 pins to the transceiver.
Figure 31.7 shows the connection when self-test mode 0 is selected.
CAN transceiver
CTX0
CRX0
ACK
CTX0
(internal)
Figure 31.7
(3)
CRX0
(internal)
Connection when self-test mode 0 is selected
Self-test mode 1 (internal loopback)
Self-test mode 1 is provided for self-test functions. In this mode, the protocol controller treats its transmitted messages as
received messages and stores them into the receive mailbox. To be independent from external stimulation, the protocol
controller generates the ACK bit.
In self-test mode 1, the protocol controller performs an internal feedback from the internal CTX0 pin to the internal
CRX0 pin. The input value of the external CRX0 pin is ignored. The external CTX0 pin outputs only recessive bits. The
CTX0 and CRX0 pins are not required to be connected to the CAN bus or any external device.
Figure 31.8 shows the connection when self-test mode 1 is selected.
CTX0
CRX0
Recessive level
ACK
CTX0
(internal)
Figure 31.8
CRX0
(internal)
Connection when self-test mode 1 is selected
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31.3
31. Controller Area Network (CAN) Module
Modes of Operation
The CAN module operation modes include the following:
CAN reset mode
CAN halt mode
CAN operation mode
CAN sleep mode.
Figure 31.9 shows the transitions between different operation modes.
CPU reset
CANM[1:0] = 01b or 11b
when SLPM = 0
CAN sleep mode*2
CANM[1:0] = 00b
CAN reset mode
SLPM = 1
CANM[1:0] = 10b
when SLPM = 0
SLPM = 1
CAN operation mode
CANM[1:0]
= 01b, 11b
CANM[1:0]
= 10b
CANM[1:0]
= 00b
CANM[1:0]
= 01b, 11b
CAN halt mode
TEC > 255
CANM[1:0] = 10b
CANM[1:0]
= 01b, 11b
When BOM[1:0] = 00b or 11b
(no halt request) and 11
consecutive recessive bits are
detected 128 times or RBOC = 1
CAN operation mode
(bus-off state)
CANM[1:0] = 10b*1
CANM, SLPM, BOM, RBOC: Bits in CTLR
Note 1.
Note 2.
Figure 31.9
The transition timing from the bus-off state to CAN halt mode depends on the setting of the CTLR.BOM[1:0] bits.
When the CTLR.BOM[1:0] bits are 01b, the state transition occurs immediately after entering the bus-off state.
When the CTLR.BOM[1:0] bits are 10b, the state transition occurs at the end of the bus-off state.
When the CTLR.BOM[1:0] bits are 11b, the state transition occurs at the setting of the CTLR.CANM[1:0] bits to
10b (CAN halt mode).
Change the CTLR.SLPM bit to set or cancel CAN sleep mode.
Transition between different operation modes
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31.3.1
31. Controller Area Network (CAN) Module
CAN Reset Mode
CAN reset mode is provided for CAN communication configuration. When the CTLR.CANM[1:0] bits are set to 01b or
11b, the CAN module enters CAN reset mode. Then, the STR.RSTST flag is set to 1. Do not change the
CTLR.CANM[1:0] bits until the RSTST flag is set to 1. Set the BCR register before exiting CAN reset mode to enter any
other modes.
The following registers are initialized to their reset values after entering CAN reset mode, and their initial values are
retained during CAN reset mode:
MCTL_TXj and MCTL_RXj
STR (except for the SLPST and TFST bits)
EIFR
RECR
TECR
TSR
MSSR
MSMR
RFCR
TFCR
TCR
ECSR (except for the EDPM bit).
The following registers retain their previous values even after entering CAN reset mode:
CTLR
STR (only the SLPST and TFST bits)
MIER and MIER_FIFO
EIER
BCR
CSSR
ECSR (only the EDPM bit)
MBj_ID, MBj_DL, MBj_Dm, and MBj_TS
MKRk
FIDCR0 and FIDCR1
MKIVLR
AFSR
RFPCR
TFPCR.
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31.3.2
31. Controller Area Network (CAN) Module
CAN Halt Mode
CAN halt mode is used for mailbox configuration and test mode setting. When the CANM[1:0] bits in the CTLR register
are set to 10b, CAN halt mode is selected and the HLTST bit in the STR register is set to 1. Do not change the
CANM[1:0] bits in the CTLR register until the HLTST bit is 1. See Table 31.8 for the state transition conditions when
transmitting or receiving.
All registers except for the RSTST, HLTST, and SLPST bits in the STR register remain unchanged when the CAN enters
CAN halt mode.
Do not change the CTLR register (except for bits CANM[1:0] and SLPM) and the EIER register in CAN halt mode. The
BCR register can be changed in CAN halt mode only when listen-only mode is selected for automatic baud rate
detection.
Table 31.8
Operation in CAN reset and halt modes
Operation mode
Receiver
Transmitter
Bus-off
CAN reset mode
(forced transition)
CANM[1:0] = 11b
CAN module enters CAN reset
mode without waiting for the end
of message reception
CAN module enters CAN reset
mode without waiting for the end
of message transmission
CAN module enters CAN reset mode
without waiting for the end of bus-off
recovery
CAN reset mode
CANM[1:0] = 01b
CAN module enters CAN reset
mode without waiting for the end
of message reception
CAN module enters CAN reset
mode after waiting for the end of
message transmission*1, *4
CAN module enters CAN reset mode
without waiting for the end of bus-off
recovery
CAN halt mode
CAN module enters CAN halt
mode after waiting for the end of
message reception*2, *3
CAN module enters CAN halt
mode after waiting for the end of
message transmission*1, *4
When the BOM[1:0] bits are 00b:
A halt request from software is accepted
only after bus-off recovery
When the BOM[1:0] bits are 01b:
CAN module automatically enters CAN
halt mode without waiting for the end of
bus-off recovery, regardless of a halt
request from software
When the BOM[1:0] bits are 10b:
CAN module automatically enters CAN
halt mode after waiting for the end of
bus-off recovery, regardless of a halt
request from software
When the BOM[1:0] bits are 11b:
CAN module enters CAN halt mode
without waiting for the end of bus-off
recovery, if a halt is requested by
software during bus-off.
Note 1.
Note 2.
Note 3.
Note 4.
31.3.3
If transmission of several messages is requested, a mode transition occurs on completion of the first transmission. If the CAN
reset mode is being requested during suspend transmission, mode transition occurs when the bus is idle, the next transmission
ends, or the CAN module becomes a receiver.
If the CAN bus is locked at the dominant level, the program can detect this state by monitoring the BLIF flag in the EIFR
register.
If a CAN bus error occurs during reception after CAN halt mode is requested, the CAN module transitions to CAN halt mode.
If a CAN bus error or arbitration-lost occurs during transmission after CAN reset mode or CAN halt mode is requested, the CAN
module transitions to the requested CAN mode.
CAN Sleep Mode
CAN sleep mode reduces current consumption by stopping the clock supply to the CAN module. After a reset from an
MCU pin or a software reset, the CAN module starts from CAN sleep mode.
When the SLPM bit in the CTLR register is set to 1, the CAN module enters CAN sleep mode and the SLPST bit in STR
is set to 1. Do not change the value of the SLPM bit until the SLPST bit is 1. The other registers remain unchanged when
the CAN module enters CAN sleep mode.
Write to the SLPM bit in CAN reset mode and CAN halt mode. Do not change any registers (except for the SLPM bit)
during CAN sleep mode. Read operation is still allowed.
When the SLPM bit is set to 0, the CAN module is released from CAN sleep mode. When the CAN module exits CAN
sleep mode, the other registers remain unchanged.
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31.3.4
31. Controller Area Network (CAN) Module
CAN Operation Mode (Excluding Bus-Off State)
CAN operation mode is used for CAN communication.
When the CANM[1:0] bits in the CTLR register are set to 00b, the CAN module enters CAN operation mode. The
RSTST and HLTST bits in STR are set to 0. Do not change the value of the CANM[1:0] bits until the RSTST and
HLTST bits are set to 0.
If 11 consecutive recessive bits are detected after entering CAN operation mode, the following occurs:
The CAN module becomes an active node on the network, which enables transmission and reception of CAN
messages
Error monitoring of the CAN bus, such as receive and transmit error counters, is performed.
During CAN operation mode, the CAN module may be in one of the following three sub-modes, depending on the status
of the CAN bus:
Idle mode: No transmission or reception occurs
Receive mode: A CAN message sent by another node is being received
Transmit mode: A CAN message is being transmitted. The CAN module receives a message transmitted by the
local node simultaneously when self-test mode 0 (TSTM[1:0] bits in TCR = 10b) or self-test mode 1 (TSTM[1:0]
bits = 11b) is selected.
Figure 31.10 shows the sub-modes in CAN operation mode.
Idle mode
STR.TRMST = 0
STR.RECST = 0
Transmission
starts
SOF
detected
Transmission
completed
Transmit mode
STR.TRMST = 1
STR.RECST = 0
Figure 31.10
Reception
completed
Lost in arbitration
Receive mode
STR.TRMST = 0
STR.RECST = 1
Sub-modes of CAN operation mode
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31.3.5
31. Controller Area Network (CAN) Module
CAN Operation Mode (Bus-Off State)
The CAN module enters the bus-off state based on the incrementing/decrementing conditions for the transmit or receive
error counters as defined in the CAN specifications.
The following cases apply when the CAN module is recovering from the bus-off state. When the CAN module is in the
bus-off state, the values of the CAN module registers remain unchanged, except for those in STR, EIFR, RECR, TECR,
and TSR.
(1)
When BOM[1:0] bits in CTLR are 00b (normal mode)
The CAN module enters the error-active state after it completes recovery from the bus-off state and CAN communication
is enabled. The BORIF flag in the EIFR register is set to 1 (bus-off recovery detected) at this time.
(2)
When RBOC bit in CTLR is set to 1 (forced return from bus-off)
The CAN module enters the error-active state when it is in the bus-off state and the RBOC bit is set to 1. CAN
communication is enabled again after 11b consecutive recessive bits are detected. The BORIF flag does not set to 1 at
this time.
(3)
When BOM[1:0] bits are 01b (automatic transition to CAN halt mode on bus-off entry)
The CAN module enters CAN halt mode when it reaches the bus-off state. The BORIF flag does not set to 1 at this time.
(4)
When BOM[1:0] bits are 10b (automatic transition to CAN halt mode at bus-off end)
The CAN module enters CAN halt mode when it completes the recovery from bus-off. The BORIF flag is set to 1 at this
time.
(5)
When BOM[1:0] bits are 11b (automatic transition to CAN halt mode through software) and
CANM[1:0] bits in CTLR are set to 10b (CAN halt mode) during bus-off state
The CAN module enters CAN halt mode when it is in the bus-off state and the CANM[1:0] bits are set to 10b (CAN halt
mode). The BORIF flag does not set to 1 at this time. If the CANM[1:0] bits are not set to 10b during bus-off, the same
behavior as (1) applies.
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31.4
31. Controller Area Network (CAN) Module
Data Transfer Rate Configuration
This section describes how to configure the data transfer rate.
31.4.1
Clock Setting
The CAN module provides a CAN clock generator, as shown in Figure 31.11. The CAN clock can be set by the CCLKS
bit and the BRP[9:0] bits in the BCR register.
CCLKS*1
Peripheral module clock
(PCLKB)*1
0
1
Baud rate
prescaler
1/(P + 1)
fCAN
fCANCLK
P = 0 to 1023
EXTAL
CCLKS:
fCAN:
P:
fCANCLK:
Note 1.
Figure 31.11
31.4.2
Bit in the BCR register
CAN system clock
Value selected in BRP[9:0] bits in BCR (P = 0 to 1023)
CAN communication clock (fCANCLK = fCAN/(P + 1))
See section 9, Clock Generation Circuit. When using the CAN module while the CCLKS bit is cleared to
0, the PLL must be selected as the source of the peripheral module clock.
CAN clock generator block digram
Bit Timing Setting
The bit timing consists of three segments as shown in Figure 31.12.
Bit time
SS
TSEG1
TSEG2
Sample point
The range of each segment:
Bit time = 8 Tq to 25 Tq
SS = 1 Tq
TSEG1 = 4 Tq to 16 Tq
TSEG2 = 2 Tq to 8 Tq
SJW = 1 Tq to 4 Tq
Setting of TSEG1 and TSEG2: TSEG1 > TSEG2 SJW
Figure 31.12
Bit timing
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31.4.3
31. Controller Area Network (CAN) Module
Data Transfer Rate
The data transfer rate depends on the division value of fCAN (CAN system clock), the division value of the baud rate
prescaler, and the Tq count for 1 bit time.
Data transfer rate
(bps)
=
fCAN
Baud rate prescaler division
value*1
x Tq count for 1 bit time
=
fCANCLK
Tq count for 1 bit time
Note 1. Division value of baud rate prescaler = P + 1 (P: 0 to 1023), where P is the BRP[9:0] setting in the BCR register.
Table 31.9 lists data transfer rate examples.
Table 31.9
Data transfer rate examples
fCAN
32 MHz
Data transfer rate
Tq count
P+1
1 Mbps
8Tq
16Tq
4
2
500 kbps
8Tq
16Tq
8
4
250 kbps
8Tq
16Tq
16
8
125 kbps
8Tq
16Tq
32
16
83.3 kbps
8Tq
16Tq
48
24
33.3 kbps
8Tq
10Tq
16Tq
20Tq
120
96
60
48
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31.5
31. Controller Area Network (CAN) Module
Mailbox and Mask Register Structure
Figure 31.13 shows the structure of the 32 mailbox registers: MBj_ID, MBj_DL, MBj_Dm, and MBj_TS.
Address
b7
b0
IDE
RTR
SID5
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0200h + 16 j + 0
4005 0200h + 16 j + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0200h + 16 j + 2
EID7
EID0
4005 0200h + 16 j + 3
EID6
EID5
EID4
EID3
EID2
EID1
4005 0200h + 16 j + 4
DLC3 DLC2 DLC1 DLC0
Figure 31.13
4005 0200h + 16 j + 5
DATA0
4005 0200h + 16 j + 6
DATA1
4005 0200h + 16 j + 7
DATA7
4005 0200h + 16 j + 13
TSH
4005 0200h + 16 j + 14
TSL
4005 0200h + 16 j + 15
Structure of the mailbox registers (j = 0 to 31)
Figure 31.14 shows the structure of the eight mask registers, MKRk.
Address
b7
SID5
b0
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0400h + 4 k + 0
4005 0400h + 4 k + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0400h + 4 k + 2
EID7
EID0
4005 0400h + 4 k + 3
EID6
EID5
EID4
EID3
EID2
EID1
MKRk register
Figure 31.14
Structure of the MKRk registers (k = 0 to 7)
Figure 31.15 shows the structure of the two FIFO received ID compare registers, FIDCR0 and FIDCR1.
Address
b7
b0
IDE
RTR
SID5
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0420h + 4 n + 0
4005 0420h + 4 n + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0420h + 4 n + 2
EID7
EID0
4005 0420h + 4 n + 3
EID6
EID5
EID4
EID3
EID2
EID1
FIDCRn register
Figure 31.15
Structure of the FIDCRn registers (n = 0, 1)
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31.6
31. Controller Area Network (CAN) Module
Acceptance Filtering and Masking Functions
The acceptance filtering and masking functions allow you to select and receive messages with multiple IDs for
mailboxes within a specified range.
The MKRk registers can mask the standard ID and the extended ID of 29 bits:
MKR0 is the mask register for mailboxes 0 to 3
MKR1 is the mask register for mailboxes 4 to 7
MKR2 is the mask register for mailboxes 8 to 11
MKR3 is the mask register for mailboxes 12 to 15
MKR4 is the mask register for mailboxes 16 to 19
MKR5 is the mask register for mailboxes 20 to 23
MKR6 is the mask register for mailboxes 24 to 27 in normal mailbox mode and receive FIFO mailboxes 28 to 31 in
FIFO mailbox mode
MKR7 is the mask register for mailboxes 28 to 31 in normal mailbox mode and receive FIFO mailboxes 28 to 31 in
FIFO mailbox mode.
MKIVLR disables acceptance filtering independently for each mailbox.
The IDE bit in the MBj_ID register is valid when the IDFM[1:0] bits in the CTLR register are 10b (mixed ID mode).
The RTR bit in the MBj_ID register selects a data frame or remote frame.
In FIFO mailbox mode, the normal mailboxes 0 to 23 use an associated register from MKR0 to MKR5 for acceptance
filtering. The receive FIFO mailboxes 28 to 31 use two registers, MKR6 and MKR7, for acceptance filtering. The receive
FIFO also uses two registers, FIDCR0 and FIDCR1, for ID comparison. The EID[17:0], SID[10:0], RTR, and IDE bits in
mailbox 28 to mailbox 31 for the receive FIFO are disabled. As acceptance filtering depends on the result of two logic
OR operations, two ranges of IDs can be received into the receive FIFO. The MKIVLR register is disabled for the
receive FIFO.
If different standard ID and extended ID values are set in the IDE bits in the FIDCR0 and FIDCR1 registers, both ID
formats are received. If different data frame and remote frame values are set in the RTR bits in the FIDCR0 and FIDCR1
registers, both data and remote frames are received. When a combination of two ranges of IDs is not required, set the
same mask value and the same ID in both the FIFO ID and mask registers.
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31. Controller Area Network (CAN) Module
Figure 31.16 shows the association between mask registers and mailboxes. Figure 31.17 shows acceptance filtering.
Normal mailbox mode
FIFO mailbox mode
Mailbox 0
Mailbox 0
MKR0 register
MKR0 register
Mailbox 3
Mailbox 3
Mailbox 4
Mailbox 4
MKR1 register
MKR1 register
Mailbox 7
Mailbox 7
Mailbox 8
Mailbox 8
MKR2 register
MKR2 register
Mailbox 11
Mailbox 11
Mailbox 12
Mailbox 12
MKR3 register
MKR3 register
Mailbox 15
Mailbox 15
Mailbox 16
Mailbox 16
MKR4 register
MKR4 register
Mailbox 19
Mailbox 19
Mailbox 20
Mailbox 20
MKR5 register
MKR5 register
Mailbox 23
Mailbox 23
Mailbox 24
Transmit FIFO
FIDCR0 register
Mailbox 27
Mailbox 28
Mailbox 27
Mailbox 28
MKR7 register
MKR7 register
Receive FIFO
FIDCR1 register
Mailbox 31
Figure 31.16
Mailbox 24
MKR6 register
MKR6 register
Mailbox 31
Association between mask registers and mailboxes
ID setting of MBj_ID
(j = 0 to 31)*1
ID value of received
message
Setting of MKIVLR*2
Setting of MKRk
(k = 0 to 7)
Mask bit values
0: IDs not compared
1: IDs compared
Acceptance judge signal
(internal signal)
Acceptance judge signal
0: Receiving message is ignored
(not stored in any mailbox)
1: Receiving message is stored in a mailbox
which matches the ID
Note 1.
Note 2.
The settings of FIDCR0 and FIDCR1 are used in FIFO mailbox mode.
Invalid in FIFO mailboxes.
Figure 31.17
Acceptance filtering
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31.7
31. Controller Area Network (CAN) Module
Reception and Transmission
Table 31.10 lists the CAN communication mode settings.
Table 31.10
Settings for CAN receive and transmit modes
MCTL_TXj.TRMREQ
and
MCTL_RXj.TRMREQ
MCTL_TXj.RECREQ
and
MCTL_RXj.RECREQ
MCTL_TXj.ONESHOT
and
MCTL_RX.ONESHOT
Mailbox communication mode
0
0
0
Mailbox disabled or transmission being aborted
0
0
1
Can be configured only when transmission or reception
from a mailbox programmed in one-shot mode is aborted
0
1
0
Configured as a receive mailbox for a data frame or remote
frame
0
1
1
Configured as a one-shot receive mailbox for a data frame
or remote frame
1
0
0
Configured as a transmit mailbox for a data frame or
remote frame
1
0
1
Configured as a one-shot transmit mailbox for a data frame
or remote frame
1
1
0
Do not set
1
1
1
Do not set
j = 0 to 31
When a mailbox is configured as a receive mailbox or a one-shot receive mailbox, the following restrictions apply:
Before configuring a mailbox, set the MCTL_RXj register to 00h
A received message is stored in the first mailbox that matches the condition resulting from the receive mode settings
and acceptance filtering. The matching mailbox with the smaller number takes priority for storing the received
message.
In CAN operation mode, the CAN module does not receive its own transmitted data even if the ID is a match. In
self-test mode, however, the CAN module receives its own transmitted data and returns ACK.
When configuring a mailbox as a transmit mailbox or a one-shot transmit mailbox, the following restriction applies:
Before configuring a mailbox, ensure that the MCTL_TXj register is 00h and that there is no pending abort process.
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31.7.1
31. Controller Area Network (CAN) Module
Reception
Figure 31.18 shows an operation example of data frame reception in overwrite mode. This example shows the
overwriting of the first message when the CAN module receives two consecutive CAN messages that match the
receiving conditions in the MCTL_RXj (j = 0 to 31) register.
Receive message in mailbox j
SOF
CRC
ACK
Receive message in mailbox j
EOF
IFS SOF
CRC
ACK
EOF
IFS
CAN bus
Acceptance filtering
Acceptance filtering
MCTL_RXj.RECREQ
MCTL_RXj.INVALDATA
MCTL_RXj.NEWDATA
MCTL_RXj.MSGLOST
CAN0 reception complete interrupt
STR.RECST
CAN0 error interrupt
j = 0 to 31
Figure 31.18
Operation example of data frame reception in overwrite mode
1. When an SOF is detected on the CAN bus, the RECST bit in the STR register is set to 1 (reception in progress) if the
CAN module has no message ready to start transmission.
2. Acceptance filtering starts at the beginning of the CRC field to select the receive mailbox.
3. After a message is received, MCTL_RXj.NEWDATA for the receive mailbox is set to 1 (new message is being
stored or was stored in the mailbox). The INVALDATA flag in the MCTL_RXj register is set to 1 (message is
being updated) at the same time. The INVALDATA flag is set to 0 (message valid) again after the complete
message is transferred to the mailbox.
4. When the interrupt enable bit in the MIER register for the receive mailbox is 1 (interrupt enabled), the
INVALDATA flag is set to 0, triggering a CAN0 reception complete interrupt request.
5. After reading the message from the mailbox, the NEWDATA flag must be set to 0 by software.
6. In overwrite mode, if the next CAN message is received while the NEWDATA bit in MCTL_RXj is set to 1, the
MSGLOST flag in MCTL_RXj is set to 1 (message was overwritten). The new received message is transferred to
the mailbox. The CAN0 reception complete interrupt request is generated in the same way as in step 4.
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31. Controller Area Network (CAN) Module
Figure 31.19 shows an operation example of data frame reception in overrun mode. The example shows the overrunning
of the second message when the CAN module receives two consecutive CAN messages that match the receiving
conditions of MCTL_RXj (j = 0 to 31).
Receive message in mailbox j
SOF
CRC
ACK
EOF
Receive message in mailbox j
IFS SOF
CRC
ACK
EOF
IFS
CAN bus
Acceptance filtering
Acceptance filtering
MCTL_RXj.RECREQ
MCTL_RXj.INVALDATA
MCTL_RXj.NEWDATA
MCTL_RXj.MSGLOST
CAN0 reception
complete interrupt
STR.RECST
CAN0 error interrupt
j = 0 to 31
Figure 31.19
Operation example of data frame reception in overrun mode
Steps 1. to 5. are the same as in overwrite mode.
6. In overrun mode, if the next CAN message is received before the NEWDATA flag in MCTL_RXj is set to 0, the
MSGLOST flag in MCTL_RXj is set to 1 (message overrun). The new received message is discarded and a CAN0
error interrupt request is generated if the associated interrupt enable bit in the EIER register is set to 1 (interrupt
enabled).
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31.7.2
31. Controller Area Network (CAN) Module
Transmission
Figure 31.20 shows an example operation of data frame transmission.
SOF
Transmission message in mailbox j
Transmission message in mailbox k
CRC
CRC
CRC
IFS
SOF
CRC
EOF
delimiter
delimiter EOF IFS
CAN bus
Next transmission scan
Next transmission scan
Next transmission scan
Mailbox j
MCTL_TXj.TRMREQ
MCTL_TXj.TRMACTIVE
MCTL_TXj.SENTDATA
Mailbox k
MCTL_TXk.TRMREQ
MCTL_TXk.TRMACTIVE
MCTL_TXk.SENTDATA
CAN0 transmission
complete interrupt
STR.TRMST
j, k = 0 to 31, j k
Figure 31.20
Operation example of data frame transmission
1. When a TRMREQ bit in MCTL_TXj (j = 0 to 31) is set to 1 (transmit mailbox) in the bus-idle state, the mailbox
scanning starts to decide the highest-priority mailbox for transmission. When the transmit mailbox is determined,
the TRMACTIVE flag in MCTL_TXj is set to 1 (from acceptance of transmission request to completion of
transmission, or error/arbitration-lost), the TRMST bit in STR is set to 1 (transmission in progress), and the CAN
module starts transmission.*1
2. If other TRMREQ bits are set, the transmission scanning starts with the CRC delimiter for the next transmission.
3. If transmission is completed without losing arbitration, the SENTDATA flag in MCTL_TXj is set to 1
(transmission complete) and the TRMACTIVE flag is set to 0 (transmission is pending or transmission is not
requested). If the interrupt enable bit in the MIER register is 1 (interrupt enabled), the CAN0 transmission complete
interrupt request is generated.
4. When requesting the next transmission from the same mailbox, set the SENTDATA and TRMREQ flag to 0, and
then set the TRMREQ bit to 1 after checking that the SENTDATA and TRMREQ bits are set to 0.
Note 1. If arbitration is lost after the CAN module starts transmission, the TRMACTIVE flag is set to 0. Transmission
scanning is performed again to search for the highest-priority transmit mailbox from the beginning of the CRC
delimiter. If an error occurs either during transmission or following arbitration-lost, transmission scanning is
performed again to search for the highest-priority transmit mailbox from the start of the CRC delimiter.
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31.8
31. Controller Area Network (CAN) Module
Interrupts
The CAN module provides the following interrupts for each channel:
CAN0 reception complete interrupt for mailboxes 0 to 31 (CAN0_RXM)
CAN0 transmission complete interrupt for mailboxes 0 to 31 (CAN0_TXM)
CAN0 receive FIFO interrupt (CAN0_RXF)
CAN0 transmit FIFO interrupt (CAN0_TXF)
CAN0 error interrupt (CAN0_ERS).
Eight interrupt sources are available for the CAN0 error interrupts. Check the EIFR register to determine whether these
sources were triggered:
Bus error
Error-warning
Error-passive
Bus-off entry
Bus-off recovery
Receive overrun
Overload frame transmission
Bus lock.
Table 31.11 lists the CAN interrupts.
Table 31.11
CAN interrupts
Module
Interrupt
name
Interrupt source
Source flag
CAN0
CAN0_ERS
Bus lock detected
EIFR.BLIF
Overload frame transmission detected
EIFR.OLIF
CAN0_RXF
Overrun detected
EIFR.ORIF
Bus-off recovery detected
EIFR.BORIF
Bus-off entry detected
EIFR.BOEIF
Error-passive detected
EIFR.EPIF
Error-warning detected
EIFR.EWIF
Bus error detected
EIFR.BEIF
Receive FIFO message received (MIER_FIFO.MB29 = 0)
RFCR.RFUST[2:0]
Receive FIFO warning (MIER_FIFO.MB29 = 1)
CAN0_TXF
Transmit FIFO message transmission completed (MIER_FIFO.MB25 = 0)
TFCR.TFUST[2:0]
FIFO last message transmission completed (MIER_FIFO.MB25 = 1)
CAN0_RXM
Mailbox 0 to 31 message received
MCTL_RX0.NEWDATA to
MCTL_RX31.NEWDATA
CAN0_TXM
Mailbox 0 to 31 message transmission completed
MCTL_TX0.SENTDATA to
MCTL_TX31.SENTDATA
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31.9
31.9.1
31. Controller Area Network (CAN) Module
Usage Notes
Settings for the Module-Stop Function
The Module Stop Control Register B (MSTPCRB) can enable or disable CAN module operation. The CAN module is
initially stopped after a reset. Releasing the module-stop state enables access to the registers. For details, see section 11,
Low Power Modes.
31.9.2
Settings for the Operating Clock
The settings for the operating clock can be made as follows:
The following clock constraint must be satisfied for the CAN module when the CCLKS bit is 1:
fPCLKB ≥ fCANMCLK
The source of the peripheral module clocks must be PLL for the CAN module when the CCLKS bit is 0
The clock frequency ratio of PCLKA and PCLKB must be 2:1 when using the CAN module. Operation is not
guaranteed for other settings.
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32. Serial Peripheral Interface (SPI)
32.
Serial Peripheral Interface (SPI)
32.1
Overview
The MCU provides two independent channels for the Serial Peripheral Interface (SPI). The SPI channels are capable of
high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices. Table 32.1
lists the SPI specifications, Figure 32.1 shows a block diagram, and Table 32.2 lists the I/O pins.
In this section, PCLK is used to refer to PCLKA. Additionally, n indicates A or B, and i indicates 0 or 1. A lower-case
letter i in pin and signal names indicates a value from 0 to 3, and a lower-case letter m in SPI Command Register m
(SPCMDm) indicates a value from 0 to 7.
Table 32.1
SPI specifications (1 of 2)
Item
Description
Number of channels
Two channels
SPI transfer functions
Use of MOSI (master out/slave in), MISO (master in/slave out), SSL (slave select), and RSPCK (SPI
clock) signals allows serial communications through SPI operation (4-wire method) or clock
synchronous operation (3-wire method)
Transmit-only operation available
Communication mode selectable to full-duplex or transmit-only
RSPCK polarity switching
RSPCK phase switching.
Data format
MSB-first or LSB-first selectable
Transfer bit length selectable to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits
SPI0: 128-bit transmit and receive buffers, with capability to transfer up to four frames in one round of
transmission or reception (each frame consisting of up to 32 bits)
SPI1: 32-bit transmit and receive buffers, with capability to transfer one frame in one round of
transmission or reception.
Bit rate
In master mode, the on-chip baud rate generator generates RSPCK by frequency-dividing PCLK (the
division ratio ranges from divided by 2 to divided by 4096)
In slave mode, the minimum PCLK clock divided by 6 can be input as RSPCK (PCLK divided by 6 is the
maximum RSPCK frequency).
Width at high level: 3 PCLK cycles; width at low level: 3 PCLK cycles.
Buffer configuration
Double buffer configuration for the transmit and receive buffers
SPI0: 128 bits for the transmit and receive buffers
SPI1: 32 bits for the transmit and receive buffers.
Error detection
SSL control function
Control in master transfer
Transfers of up to eight commands (for SPI0) each can be executed sequentially in looped execution
For each command, the following can be set:
- SPI0: SSL signal value, bit rate, RSPCK polarity and phase, transfer data length, MSB- or LSB-first,
burst, RSPCK delay, SSL negation delay, and next-access delay
- SPI1: SSL signal value, bit rate, RSPCK polarity/phase, transfer data length, MSB- or LSB-first,
RSPCK delay, SSL negation delay, and next-access delay
Transfers can be initiated by writing to the transmit buffer
MOSI signal value specifiable in SSL negation
RSPCK auto-stop function.
Mode-fault error detection
Underrun error detection
Overrun error detection*1
Parity error detection.
Four SSL pins (SSLn0 to SSLn3) for each channel
In single-master mode, SSLn0 to SSLn3 pins are output
In multi-master mode, SSLn0 pin for input, and SSLn1 to SSLn3 pins either for output or unused
In slave mode, SSLn0 pin for input, and SSLn1 to SSLn3 pins unused
Controllable delay from SSL output assertion to RSPCK operation (RSPCK delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable delay from RSPCK stop to SSL output negation (SSL negation delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable wait for next-access SSL output assertion (next-access delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Function for changing SSL polarity.
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Table 32.1
32. Serial Peripheral Interface (SPI)
SPI specifications (2 of 2)
Item
Description
Interrupt sources
Event link function (output)
The following events can be output to the Event Link Controller (ELC):
Receive buffer full signal
Transmit buffer empty signal
Mode-fault, underrun, overrun, or parity error signal
SPI idle signal
Transmission-complete signal.
Other functions
SPI initialization function
Loopback mode.
Module-stop function
Module-stop state can be set to reduce power consumption
Note 1.
Receive buffer full interrupt
Transmit buffer empty interrupt
SPI error interrupt (mode-fault, overrun, parity error)
SPI idle interrupt (SPI idle)
Transmission-complete interrupt.
In master reception, when the RSPCK auto-stop function is enabled, an overrun error does not occur because the transfer
clock is stopped on overrun error detection.
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32. Serial Peripheral Interface (SPI)
Bus interface
S3A1 User’s Manual
Module data bus
SPTX
SPRX
Parity circuit
Shift register
Selector
Normal
SPCR
SSLP
SPPCR
SPSR
SPDR/SPDR_HA
SPSCR*1
SPSSR*1
SPDCR
SPCKD
SSLND
SPND
SPCR2
SPCMD
Normal
MISOn
Loopback
Loopback 2
Normal
Loopback
Loopback 2
Master
Figure 32.1
PCLK
Event output
Loopback 2
Slave
Master
SPIn_SPTI
SPIn_SPRI
SPIn_SPII
SPIn_SPEI
SPIn_SPTEND
Slave
SPCR:
SPI Control Register
SPCR2:
SPI Control Register 2
SSLP:
SPI Slave Select Polarity Register
SPPCR:
SPI Pin Control Register
SPSR:
SPI Status Register
SPDR/SPDR_HA:SPI Data Register
SPSCR*1: SPI Sequence Control Register
SPSSR*1: SPI Sequence Status Register
SPDCR:
SPI Data Control Register
SPCKD:
SPI Clock Delay Register
SPI0 only
Baud rate
generator
Clock
SSLn0
SSLn1 to SSLn3
RSPCKn
Note 1.
SPBR
Transmission/
reception
controller
Loopback
MOSIn
Internal
peripheral bus
SSLND:
SPND:
SPCMD:
SPI Slave Select Negation Delay Register
SPI Next-Access Delay Register
SPI Command Registers
SPI0: 0 to 7 (eight registers)
SPI1: 0 (one register)
SPBR:
SPI Bit Rate Register
SPTX:
SPI Transmit Buffer
SPRX:
SPI Receive Buffer
SPIn_SPTI:SPI Transmit Buffer Empty Interrupt
SPIn_SPRI:SPI Receive Buffer Full Interrupt
SPIn_SPII: SPI Idle Interrupt
SPIn_SPEI:SPI Error Interrupt
SPIn_SPTEND:SPI Transmission Completed Event
SPI block diagram
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32. Serial Peripheral Interface (SPI)
The SPI automatically switches the I/O direction of the SSLn0 pin. SSLn0 is set as an output when the SPI is a singlemaster and as an input when the SPI is a multi-master or a slave. The RSPCKn, MOSIn, and MISOn pins are
automatically set as inputs or outputs based on the master or slave setting and the level input on the SSLn0 pin. For
details, see section 32.3.2, Controlling SPI Pins.
Table 32.2
SPI I/O pins
Channel
Pin name
I/O
Function
SPI0
RSPCKA
I/O
Clock input/output
MOSIA
I/O
Master transmit data input/output
SPI1
32.2
MISOA
I/O
Slave transmit data input/output
SSLA0
I/O
Slave selection input/output
SSLA1
Output
Slave selection output
SSLA2
Output
Slave selection output
SSLA3
Output
Slave selection output
RSPCKB
I/O
Clock input/output
MOSIB
I/O
Master transmit data input/output
MISOB
I/O
Slave transmit data input/output
SSLB0
I/O
Slave selection input/output
SSLB1
Output
Slave selection output
SSLB2
Output
Slave selection output
SSLB3
Output
Slave selection output
Register Descriptions
32.2.1
SPI Control Register (SPCR)
Address(es): SPI0.SPCR 4007 2000h, SPI1.SPCR 4007 2100h
b7
Value after reset:
b6
SPRIE
SPE
0
0
b5
b4
b3
b2
b1
SPTIE SPEIE MSTR MODF TXMD
EN
0
0
0
0
0
b0
SPMS
0
Bit
Symbol
Bit name
Description
R/W
b0
SPMS
SPI Mode Select
0: Select SPI operation (4-wire method)
1: Select clock synchronous operation (3-wire method).
R/W
b1
TXMD
Communications Operating Mode
Select
0: Select full-duplex synchronous serial communications
1: Select serial communications with transmit-only.
R/W
b2
MODFEN Mode-Fault Error Detection Enable
0: Disable detection of mode-fault errors
1: Enable detection of mode-fault errors.
R/W
b3
MSTR
SPI Master/Slave Mode Select
0: Select slave mode
1: Select master mode.
R/W
b4
SPEIE
SPI Error Interrupt Enable
0: Disable SPI error interrupt requests
1: Enable SPI error interrupt requests.
R/W
b5
SPTIE
Transmit Buffer Empty Interrupt
Enable
0: Disable transmit buffer empty interrupt requests
1: Enable transmit buffer empty interrupt requests.
R/W
b6
SPE
SPI Function Enable
0: Disable SPI function
1: Enable SPI function.
R/W
b7
SPRIE
SPI Receive Buffer Full Interrupt
Enable
0: Disable SPI receive buffer full interrupt requests
1: Enable SPI receive buffer full interrupt requests.
R/W
If the SPCR.MSTR, SPCR.MODFEN, or SPCR.TXMD bit is changed while the SPCR.SPE bit is 1, do not perform
subsequent operations.
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32. Serial Peripheral Interface (SPI)
SPMS bit (SPI Mode Select)
The SPMS bit selects SPI operation (4-wire method) or clock synchronous operation (3-wire method).
The SSLn0 to SSLn3 pins are not used in clock synchronous operation. The RSPCKn, MOSIn, and MISOn pins handle
communications. For clock synchronous operation in master mode (SPCR.MSTR = 1), the SPCMDm.CPHA bit can be
set to either 0 or 1. For clock synchronous operation in slave mode (SPCR.MSTR = 0), always set the CPHA bit to 1. Do
not perform the operations if the CPHA bit is set to 0 for clock synchronous operation in slave mode (SPCR.MSTR = 0).
TXMD bit (Communications Operating Mode Select)
The TXMD bit selects full-duplex synchronous serial communications or transmit-only operations. When this bit is set to
1, the SPI only performs transmit operations but not receive operations (see section 32.3.6, Data Transfer Modes), and
the receive buffer full interrupt requests cannot be used.
MODFEN bit (Mode-Fault Error Detection Enable)
The MODFEN bit enables or disables the detection of mode-fault errors (see section 32.3.8, Error Detection). In
addition, the SPI determines the I/O direction of the SSLn0 to SSLn3 pins based on combinations of the MODFEN and
MSTR bit settings (see section 32.3.2, Controlling SPI Pins).
MSTR bit (SPI Master/Slave Mode Select)
The MSTR bit selects master or slave mode for the SPI. Based on the MSTR bit settings, the SPI determines the direction
of the RSPCKn, MOSIn, MISOn, and SSLn0 to SSLn3 pins.
SPEIE bit (SPI Error Interrupt Enable)
The SPEIE bit enables or disables the generation of SPI error interrupt requests when one of the following occurs:
The SPI detects a mode-fault error or underrun error and sets the SPSR.MODF flag to 1
The SPI detects an overrun error and sets the SPSR.OVRF flag to 1
The SPI detects a parity error and sets the SPSR.PERF flag to 1.
For details, see section 32.3.8, Error Detection.
SPTIE bit (Transmit Buffer Empty Interrupt Enable)
The SPTIE bit enables or disables the generation of transmit buffer empty interrupt requests when the SPI detects that the
transmit buffer is empty. To generate a transmit buffer empty interrupt request when transmission starts, set the SPE and
SPTIE bits to 1 at the same time or set the SPE bit to 1 after setting the SPTIE bit to 1.
When the SPTIE bit is 1, transmit buffer interrupts are generated even when the SPI function is disabled (when the SPE
bit is changed to 0).
SPE bit (SPI Function Enable)
The SPE bit enables or disables the SPI function. The SPE bit cannot be set to 1 when the SPSR.MODF flag is 1. For
details, see section 32.3.8, Error Detection.
Setting the SPE bit to 0 disables the SPI function and initializes a part of the module function. For details, see section
32.3.9, Initializing the SPI. In addition, a transmit buffer empty interrupt request is generated when the SPE bit is
changed from 0 to 1 or 1 to 0.
SPRIE bit (SPI Receive Buffer Full Interrupt Enable)
The SPRIE bit enables or disables the generation of an SPI receive buffer interrupt request when the SPI detects a receive
buffer full write after completion of a serial transfer.
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32.2.2
32. Serial Peripheral Interface (SPI)
SPI Slave Select Polarity Register (SSLP)
Address(es): SPI0.SSLP 4007 2001h, SPI1.SSLP 4007 2101h
Value after reset:
b7
b6
b5
b4
—
—
—
—
0
0
0
0
b3
b2
b1
b0
SSL3P SSL2P SSL1P SSL0P
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSL0P
SSL0 Signal Polarity Setting
0: Set SSL0 signal to active-low
1: Set SSL0 signal to active-high.
R/W
b1
SSL1P
SSL1 Signal Polarity Setting
0: Set SSL1 signal to active-low
1: Set SSL1 signal to active-high.
R/W
b2
SSL2P
SSL2 Signal Polarity Setting
0: Set SSL2 signal to active-low
1: Set SSL2 signal to active-high.
R/W
b3
SSL3P
SSL3 Signal Polarity Setting
0: Set SSL3 signal to active-low
1: Set SSL3 signal to active-high.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the contents of SSLP are changed while the SPCR.SPE bit is 1, do not perform subsequent operations.
32.2.3
SPI Pin Control Register (SPPCR)
Address(es): SPI0.SPPCR 4007 2002h, SPI1.SPPCR 4007 2102h
Value after reset:
b7
b6
—
—
0
0
b5
b4
MOIFE MOIFV
0
b3
b2
b1
b0
—
—
SPLP2
SPLP
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SPLP
SPI Loopback
0: Normal mode
1: Loopback mode, with data inverted for transmission.
R/W
b1
SPLP2
SPI Loopback 2
0: Normal mode
1: Loopback mode, with data not inverted for transmission.
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
MOIFV
MOSI Idle Fixed Value
0: Set level output on the MOSIn pin during MOSI idling to low
1: Set level output on the MOSIn pin during MOSI idling to high.
R/W
b5
MOIFE
MOSI Idle Value Fixing
Enable
0: Set MOSI output value to equal the final data from previous transfer R/W
1: Set MOSI output value to equal the value set in the MOIFV bit.
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the contents of the SPPCR register are changed while the SPCR.SPE bit is 1, do not perform subsequent operations.
SPLP bit (SPI Loopback)
The SPLP bit selects the mode of the SPI pins. When this bit is set to 1, the SPI shuts off the path between the MISOn pin
and the shift register if the SPCR.MSTR bit is 1, and between the MOSIn pin and the shift register if the SPCR.MSTR bit
is 0. The SPI then connects the input path and output path for the shift register, establishing loopback mode.
SPLP2 bit (SPI Loopback 2)
The SPLP2 bit selects the mode of the SPI pins. When this bit is set to 1, the SPI shuts off the path between the MISOn
pin and the shift register if the SPCR.MSTR bit is 1, and between the MOSIn pin and the shift register if the
SPCR.MSTR bit is 0. The SPI then connects the input path and output path for the shift register, establishing loopback
mode.
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32. Serial Peripheral Interface (SPI)
MOIFV bit (MOSI Idle Fixed Value)
If the MOIFE bit is 1 in master mode, the MOIFV bit determines the MOSIn pin output value during the SSL negation
period for both SPI0 and SPI1, including the SSL retention period during a burst transfer for the SPI0.
MOIFE bit (MOSI Idle Value Fixing Enable)
The MOIFE bit fixes the MOSIn output value when SPI is in master mode and in an SSL negation period for both SPI0
and SPI1, including the SSL retention period during a burst transfer for the SPI0. When the MOIFE bit is 0, the SPI
outputs the last data from the previous serial transfer during the SSL negation period to the MOSIn pin. When the
MOIFE bit is 1, the SPI outputs the fixed value set in the MOIFV bit to the MOSIn pin.
32.2.4
SPI Status Register (SPSR)
Address(es): SPI0.SPSR 4007 2003h, SPI1.SPSR 4007 2103h
b7
b6
SPRF
—
0
0
Value after reset:
b5
b4
SPTEF UDRF
1
b3
PERF
0
b2
b1
MODF IDLNF
0
0
0
b0
OVRF
0
Bit
Symbol
Bit name
Description
R/W
b0
OVRF
Overrun Error Flag
0: No overrun error occurred
1: Overrun error occurred.
R/(W)*1
b1
IDLNF
SPI Idle Flag
0: SPI is in idle state
1: SPI is in transfer state.
R
b2
MODF
Mode Fault Error Flag
0: No mode-fault error or underrun error occurred
1: Mode-fault error or an underrun error occurred.
R/(W)*1
b3
PERF
Parity Error Flag
0: No parity error occurred
1: Parity error occurred.
R/(W)*1
b4
UDRF
Underrun Error Flag
0: Mode-fault error occurs (MODF = 1)
1: Underrun error occurs (MODF = 1).
This bit is invalid when MODF flag is 0.
R/W*1, *2
b5
SPTEF
SPI Transmit Buffer Empty Flag
0: Data is in the transmit buffer
1: No data is in the transmit buffer.
R/(W)*3
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
SPRF
SPI Receive Buffer Full Flag
0: No valid data is in SPDR/SPDR_HA
1: Valid data is in SPDR/SPDR_HA.
R/(W)*3
Note 1.
Note 2.
Note 3.
Only 0 can be written to clear the flag after reading 1.
Clear the UDRF flag at the same time as the MODF flag.
The write value should be 1.
OVRF flag (Overrun Error Flag)
The OVRF flag indicates the occurrence of an overrun error. In master mode (SPCR.MSTR = 1), when the RSPCK clock
auto-stop function is enabled (SPCR2.SCKASE = 1), an overrun error does not occur and this flag does not set to 1. For
details, see section 32.3.8.1, Overrun errors.
[Setting condition]
When the next serial transfer ends while the SPCR.TXMD bit is 0 and the receive buffer is full.
[Clearing condition]
When 0 is written to the OVRF flag after the OVRF flag is confirmed to be 1 by a read of SPSR.
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32. Serial Peripheral Interface (SPI)
IDLNF flag (SPI Idle Flag)
The IDLNF flag indicates the transfer status of the SPI.
[Setting condition]
Master mode
When conditions 1. and 2. in the master mode, in the clearing conditions, are not satisfied.
Slave mode
When the SPCR.SPE bit is 1, enabling the SPI function.
[Clearing condition]
Master mode
When condition 1. or conditions 2., 3., and 4. are satisfied for SPI0, and
when condition 1. or conditions 2. and 4. are satisfied for SPI1.
1. The SPCR.SPE bit is 0, indicating that the SPI is initialized.
2. The transmit buffer (SPTX) is empty, indicating that data for the next transfer is not set.
3. The SPSSR.SPCP[2:0] bits are 000b, indicating the beginning of sequence control.
4. The SPI internal sequencer enters the idle state, indicating that operations up to the next-access delay are complete.
Slave mode
When condition 1. is satisfied.
MODF flag (Mode Fault Error Flag)
The MODF flag indicates the occurrence of a mode-fault error or an underrun error. The UDRF flag indicates which
error occurred.
[Setting conditions]
Multi-master mode
When the input level of the SSLni pin changes to an active level while the SPCR.MSTR bit is 1 (master mode) and
the SPCR.MODFEN bit is 1 (mode-fault error detection is enabled), triggering a mode-fault error.
Slave mode
When condition 1. or 2. is satisfied.
1. The SSLni pin is negated before the RSPCK cycle required for data transfer ends while the SPCR.MSTR bit is 0
(slave mode) and the SPCR.MODFEN bit is 1 (mode-fault error detection is enabled), triggering a mode-fault
error.
2. The serial transfer begins with the SPCR.MSTR bit set to 0 (slave mode), SPCR.SPE bit set to 1, and the
transmission data not prepared, triggering an underrun error.
The active level of the SSLni signal is determined by the SSLP.SSLiP bit (SSLi signal polarity setting).
[Clearing condition]
When 0 is written to the MODF flag after the MODF flag is confirmed to be 1 by a read of SPSR.
PERF flag (Parity Error Flag)
The PERF flag indicates the occurrence of a parity error.
[Setting condition]
When a serial transfer ends while the SPCR.TXMD bit is 0 and the SPCR2.SPPE bit is 1, triggering a parity error.
[Clearing condition]
When 0 is written to the PERF flag after the PERF flag is confirmed to be 1 by a read of SPSR.
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32. Serial Peripheral Interface (SPI)
UDRF flag (Underrun Error Flag)
The UDRF flag indicates the occurrence of an underrun error.
[Setting condition]
When the serial transfer begins with the SPCR.MSTR bit set to 0 (slave mode), the SPCR.SPE bit set to 1, and the
transmission data not prepared, triggering an underrun error.
[Clearing condition]
When 0 is written to the UDRF flag after the UDRF flag is confirmed to be 1 by a read of SPSR.
SPTEF flag (SPI Transmit Buffer Empty Flag)
The SPTEF flag indicates the status of the transmit buffer for the SPI Data Register (SPDR/SPDR_HA).
[Setting conditions]
When condition 1. or condition 2. is satisfied.
1. The SPCR.SPE bit is 0 for SPI initialization.
2. Transmit data is transferred from the transmit buffer to the shift register.
[Clearing condition]
SPI0: When data written to the SPDR/SPDR_HA register equals the number of frames set in the number of frames
specification bits in the SPI Data Control Register (SPDCR.SPFC[1:0]).
SPI1: When data written is to SPDR/SPDR_HA.
Data can only be written to SPDR/SPDR_HA when the SPTEF bit is 1. If data is written to the transmit buffer of SPDR/
SPDR_HA when the SPTEF bit is 0, data in the transmit buffer is not updated.
SPRF flag (SPI Receive Buffer Full Flag)
The SPRF flag indicates the status of the receive buffer for the SPI Data Register (SPDR/SPDR_HA).
[Setting conditions]
SPI0: When receive data with the number of frames specified in the SPDCR.SPFC[1:0] bits is transferred from the
shift register to SPDR/SPDR_HA, while the SPCR.TXMD bit is 0, and the SPRF flag is 0. When the OVRF flag is
1, however, this flag is not changed from 0 to 1.
SPI1: When receive data is transferred from the shift register to SPDR/SPDR_HA, while the SPCR.TXMD bit is 0,
and the SPRF flag is 0. When the OVRF flag is 1, however, this flag is not changed from 0 to 1.
[Clearing condition]
When received data is read from SPDR/SPDR_HA.
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32.2.5
32. Serial Peripheral Interface (SPI)
SPI Data Register (SPDR/SPDR_HA)
Address(es): SPI0.SPDR 4007 2004h, SPI1.SPDR 4007 2104h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address(es): SPI0.SPDR_HA 4007 2004h, SPI1.SPDR_HA 4007 2104h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The SPDR/SPDR_HA register is the interface with the buffers that hold data for transmission and reception by the SPI.
When accessing this register in words (the SPLW bit is 1), access the SPDR register. When accessing it in halfwords (the
SPLW bit is 0), access the SPDR_HA register. The transmit buffer (SPTX) and receive buffer (SPRX) are independent
but are both mapped to SPDR/SPDR_HA. Figure 32.2 and Figure 32.3 show the configuration of the SPDR/SPDR_HA
register for SPI0 and SPI1 channels, respectively.
SPI Data Register
Note 1.
Figure 32.2
*1
SPDR/SPDR_HA
Internal peripheral bus
Transmit buffer
SPTX0
SPTX1
SPTX2
SPTX3
*1
Shift
register
Receive buffer
*1
SPRX0
SPRX1
SPRX2
SPRX3
Transmit data
Receive data
*1
The destination buffer and stage for access is automatically switched by hardware.
Configuration of SPDR/SPDR_HA (SPI0)
SPI Data register
Figure 32.3
SPDR/SPDR_HA
Internal peripheral bus
Transmit buffer
SPTX0
Shift
register
Transmit data
Receive data
Receive buffer
SPRX0
Configuration of SPDR/SPDR_HA (SPI1)
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32. Serial Peripheral Interface (SPI)
The transmit and receive buffers each have four stages for SPI0 and one stage for SPI1. The number of stages used for
SPI0 is selectable in the number of frames specification bits in the SPDCR register (SPDCR.SPFC[1:0]). These stages of
the buffer are all mapped to the single address of the SPDR/SPDR_HA register.
Data written to the SPDR/SPDR_HA register is written to a transmit-buffer stage (SPTXn) (n = 0 to 3 for SPI0, n = 0 for
SPI1), and then transmitted from the buffer. The receive buffer holds the received data on completion of reception. The
receive buffer is not updated if an overrun is generated.
If the data length is not 32 bits, the bits not referred to in SPTXn (n = 0 to 3 for SPI0, n = 0 for SPI1) are stored in the
associated bits in SPRXn (n = 0 to 3 for SPI0, n = 0 for SPI1). For example, if the data length is 9 bits, the received data
is stored in the SPRXn[8:0] bits and the SPTXn[31:9] bits are stored in the SPRXn[31:9] bits.
(1)
Bus interface
SPDR/SPDR_HA is an interface with 32-bit wide transmit and receive buffers, each of which has four stages for SPI0
and one stage for SPI1, for a total of 32 bytes. The 32 bytes are mapped to the 4-byte address space for SPDR/
SPDR_HA. The unit of access for SPDR/SPDR_HA is selected in the SPI Word Access/Halfword Access Specification
bit in the SPI Data Control Register (SPDCR.SPLW).
Flush the transmission data at the LSB end of the register, and store the received data at the LSB end.
The following sections describe the operations involved in writing to and reading from the SPDR/SPDR_HA register.
(a)
Writing
Data written to SPDR/SPDR_HA is written to a transmit buffer SPTXn (n = 0 to 3 for SPI0, n = 0 for SPI1). This is not
affected by the value of the SPDCR.SPRDTD bit, unlike when reading from SPDR/SPDR_HA.
The transmit buffer includes a write pointer that is automatically updated to reference the next stage each time data is
written to SPDR/SPDR_HA.
Figure 32.4 and Figure 32.5 show the configuration of the bus interface with the transmit buffer, for writes to SPDR/
SPDR_HA, for SPI0 and SPI1 respectively.
SPDR/SPDR_HA
SPTX0
SPTX1
SPTX2
SPTX3
Write access + Setting of the SPFC[1:0] bits
Configuration of SPDR/SPDR_HA for write access (SPI0)
SPDR/SPDR_HA
Figure 32.4
Figure 32.5
SPTX0
Configuration of SPDR/SPDR_HA for write access (SPI1)
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32. Serial Peripheral Interface (SPI)
For SPI0, the sequence for switching the transmit buffer write pointer changes with the setting of the number of frames
specification bits in the SPDCR register (SPDCR.SPFC[1:0]).
The relationship of the SPFC[1:0] setting and the sequence of pointer switching among SPTX0 to SPTX3 is as follows:
When the SPFC[1:0] bits are 00b: SPTX0 → SPTX0 → SPTX0 → …
When the SPFC[1:0] bits are 01b: SPTX0 → SPTX1 → SPTX0 → SPTX1 → …
When the SPFC[1:0] bits are 10b: SPTX0 → SPTX1 → SPTX2 → SPTX0 → SPTX1 → …
When the SPFC[1:0] bits are 11b: SPTX0 → SPTX1 → SPTX2 → SPTX3 → SPTX0 → SPTX1 → …
When 1 is written to the SPI Function Enable bit in the SPI Control Register (SPCR.SPE) while the bit is 0, SPTX0 is the
destination for the next write.
When writing to the transmit buffer SPTXn (n = 0 to 3 for SPI0, n = 0 for SPI1) after generation of the transmit buffer
empty interrupt (when SPSR.SPTEF is 1), write the number of frames set in SPFC[1:0] in the SPI Data Control Register
(SPDCR). Even when the specified number of frames is written to the transmit buffer (SPTXn), the value of the buffer is
not updated after completion of the writing and before the next transmit buffer empty interrupt is generated (when
SPTEF is 0).
(b)
Reading
SPDR/SPDR_HA can be accessed to read the value of a receive buffer SPRXn (n = 0 to 3 for SPI0, n = 0 for SPI1) or a
transmit buffer SPTXn (n = 0 to 3 for SPI0, n = 0 for SPI1). The setting in the SPI Receive/Transmit Data Select bit in the
SPDCR register (SPDCR.SPRDTD) selects whether reading is from the receive or transmit buffer.
The sequence of reading the SPDR/SPDR_HA register is controlled by the independent receive buffer read and transmit
buffer read pointers.
Figure 32.6 and Figure 32.7 show the configuration of a bus interface with the receive and transmit buffers for reading
from SPDR/SPDR_HA for SPI0 and SPI1, respectively.
SPI0
SPRX0
SPRX1
0
SPDR/SPDR_HA
SPRX2
SPRX3
Read access to receive buffer +
setting in the SPFC[1:0] bits
SPTX0
SPTX1
1
SPTX2
SPTX3
SPRDTD
Figure 32.6
Read access to transmit buffer +
setting in the SPFC[1:0] bits
Configuration of SPDR/SPDR_HA for read access (SPI0)
Reading the receive buffer switches the receive buffer read pointer to the next buffer automatically. The switching
sequence for the receive buffer read pointer is the same as that for the transmit buffer write pointer. However, when 1 is
written to the SPI Function Enable bit in the SPI Control Register (SPCR.SPE) while the bit is 1, SPRX0 is referenced by
the buffer read pointer for the next read.
The transmit buffer read pointer is updated when writing to SPDR/SPDR_HA, but is not updated when reading from the
transmit buffer. When reading from the transmit buffer, the value most recently written to SPDR/SPDR_HA is read.
However, after a transmit buffer empty interrupt is generated, and when the transmit buffer becomes full again (the
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32. Serial Peripheral Interface (SPI)
number of frames of data specified in the number of frames specification bits, SPDCR.SPFC[1:0], are written to the
transmit buffer), reading from the transmit buffer returns all 0s until the next transmit buffer empty interrupt is generated.
SPDR/SPDR_HA
SPI1.
0
SPRX0
1
SPTX0
SPRDTD
Figure 32.7
Configuration of SPDR/SPDR_HA for read access (SPI1)
The transmit buffer read pointer is updated when writing to SPDR/SPDR_HA, but is not updated when reading from the
transmit buffer. When reading from the transmit buffer, the value most recently written to SPDR/SPDR_HA is read.
However, after a transmit buffer empty interrupt is generated, and when the transmit buffer becomes full again, reading
from the transmit buffer returns all 0s until the next transmit buffer empty interrupt is generated (when SPTEF is 0).
32.2.6
SPI Sequence Control Register (SPSCR)
Address(es): SPI0.SPSCR 4007 2008h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SPSLN[2:0]
0
0
Bit
Symbol
Bit name
Description
b2 to b0
SPSLN[2:0]
SPI Sequence Length
Specification
b2
b7 to b3
—
Reserved
0
b0 Sequence Length
R/W
Referenced SPCMD0 to SPCMD7 (Number)
0 0 0: 1
0→0→…
0 0 1: 2
0→1→0→…
0 1 0: 3
0→1→2→0→…
0 1 1: 4
0→1→2→3→0→…
1 0 0: 5
0→1→2→3→4→0→…
1 0 1: 6
0→1→2→3→4→5→0→…
1 1 0: 7
0→1→2→3→4→5→6→0→…
1 1 1: 8
0→1→2→3→4→5→6→7→0→…
The sequence length that is set in these bits determines the order in
which the SPCMD0 to SPCMD07 registers are referenced. The setting
defines the relationship between the sequence length and the
SPCMD0 to SPCMD7 registers referenced by the SPI. In slave mode,
the SPI references SPCMD0.
These bits are read as 0. The write value should be 0.
R/W
R/W
The SPSCR register specifies the sequence length when the SPI operates in master mode. When changing the
SPSCR.SPSLN[2:0] bits while both the SPCR.MSTR and SPCR.SPE bits are 1, always check that the SPSR.IDLNF flag
is 0.
SPSLN[2:0] bits (SPI Sequence Length Specification)
The SPSLN[2:0] bits specify a sequence length when the SPI in master mode performs sequential operations. The SPI in
master mode changes the SPCMD0 to SPCMD7 registers to be referenced, and the order in which they are referenced is
based on this sequence length setting. In slave mode, SPCMD0 is referenced.
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32.2.7
32. Serial Peripheral Interface (SPI)
SPI Sequence Status Register (SPSSR)
Address(es): SPI0.SPSSR 4007 2009h
b7
b6
—
Value after reset:
0
b5
b4
SPECM[2:0]
0
0
b3
b2
—
0
0
b1
b0
SPCP[2:0]
0
0
0
Bit
Symbol
Bit name
Description
b2 to b0
SPCP[2:0]
SPI Command Pointer
b3
—
Reserved
This bit is read as 0
R
b6 to b4
SPECM[2:0]
SPI Error Command
b6
R
b7
—
Reserved
This bit is read as 0
b2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
R
b0
0: SPCMD0
1: SPCMD1
0: SPCMD2
1: SPCMD3
0: SPCMD4
1: SPCMD5
0: SPCMD6
1: SPCMD7.
b4
0: SPCMD0
1: SPCMD1
0: SPCMD2
1: SPCMD3
0: SPCMD4
1: SPCMD5
0: SPCMD6
1: SPCMD7.
R
The SPSSR register indicates the sequence control status when the SPI operates in master mode. Any writes to SPSSR
are ignored.
SPCP[2:0] bits (SPI Command Pointer)
The SPCP[2:0] bits indicate the SPCMDm register that is referenced to by the pointer during sequence control by the
SPI. For the SPI sequence control, see section 32.3.10.1, Master mode operation.
SPECM[2:0] bits (SPI Error Command)
The SPECM[2:0] bits indicate the SPCMDm register that is specified in the SPCP[2:0] bits when an error is detected
during sequence control by the SPI. The SPI updates the SPECM[2:0] bits only when an error is detected. If both the
SPSR.OVRF and SPSR.MODF flags are 0 and there is no error, the values of the SPECM[2:0] bits have no meaning.
For the SPI error detection function, see section 32.3.8, Error Detection. For the SPI sequence control, see section
32.3.10.1, Master mode operation.
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32.2.8
32. Serial Peripheral Interface (SPI)
SPI Bit Rate Register (SPBR)
Address(es): SPI0.SPBR 4007 200Ah, SPI1.SPBR 4007 210Ah
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
Value after reset:
The SPBR register sets the bit rate in master mode. If the contents of the SPBR register are changed while both the
SPCR.MSTR and SPCR.SPE bits are 1, do not perform subsequent operations.
When the SPI is in slave mode, the bit rate depends on the bit rate of the input clock regardless of the settings in SPBR
and the SPCMDm.BRDV[1:0] bits (bit rate division setting). Use bit rates that satisfy the electrical characteristics.
The bit rate is determined by combination of the SPBR and the BRDV[1:0] bit settings in the SPI Command Register,
SPCMDm (SPCMD0 to SPCMD7 for SPI0, SPCMD0 for SPI1). The equation for calculating the bit rate is as follows:
Bit rate =
f (PCLK)
2 × (n + 1) × 2N
In the equation, n denotes an SPBR setting (0, 1, 2, …, 255), and N denotes a BRDV[1:0] setting (0, 1, 2, 3).
Table 32.3 lists examples of the relationship between the SPBR settings, the BRDV[1:0] settings, and bit rates.
Table 32.3
Relationship between SPBR settings, BRDV[1:0] settings, and bit rates
Bit rate
SPBR (n)
BRDV[1:0] bits (N) Division ratio
PCLK = 32 MHz
PCLK = 48 MHz
0
0
2
16.0 Mbps
-
1
0
4
8.00 Mbps
12.0 Mbps
2
0
6
5.33 Mbps
8.00 Mbps
3
0
8
4.00 Mbps
6.00 Mbps
4
0
10
3.20 Mbps
4.80 Mbps
5
0
12
2.67 Mbps
4.00 Mbps
5
1
24
1.33 Mbps
2.00 Mbps
5
2
48
667 kbps
1.00 Mbps
5
3
96
333 kbps
500 kbps
255
3
4096
7.81 kbps
11.7 kbps
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32.2.9
32. Serial Peripheral Interface (SPI)
SPI Data Control Register (SPDCR)
Address(es): SPI0.SPDCR 4007 200Bh
b7
b6
(SPI0)
—
—
Value after reset:
0
0
b5
b4
b3
b2
b1
—
—
SPFC[1:0]
0
0
0
0
0
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
SPLW SPRDT
D
0
b0
Address(es): SPI1.SPDCR 4007 210Bh
b7
b6
(SPI1)
—
—
Value after reset:
0
0
b5
SPLW SPRDT
D
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
SPFC[1:0]
Number of Frames
Specification
• SPI0:
R/W
—
Reserved
• SPI1:
These bits are read as 0. The write value should be 0.
R/W
b1 b0
0
0
1
1
0: 1 frame
1: 2 frames
0: 3 frames
1: 4 frames.
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
SPRDTD
SPI Receive/Transmit Data
Select
0: Read SPDR/SPDR_HA values from the receive buffer
1: Read SPDR/SPDR_HA values from the transmit buffer, but
only if the transmit buffer is empty.
R/W
b5
SPLW
SPI Word Access/Halfword
Access Specification
0: Set SPDR_HA to valid for halfword access
1: Set SPDR to valid for word access.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Up to four frames for SPI0 and one frame for SPI1 can be transmitted or received in one round of transmission or
reception. The amount of data in each transfer for SPI0 is controlled by the combination of the SPCMDm.SPB[3:0] bits,
the SPSCR.SPSLN[2:0] bits, and the SPDCR.SPFC[1:0] bits. The amount of data in each transfer for SPI1 is controlled
by the combination of the SPCMD0.SPB[3:0] bits.
When changing the SPDCR.SPFC[1:0] bits while the SPCR.SPE bit is 1, always check that the SPSR.IDLNF flag is 0.
SPFC[1:0] bits (Number of Frames Specification)
The SPFC[1:0] bits specify the number of frames that can be stored in SPDR/SPDR_HA per transfer activation. Up to
four frames can be transmitted or received in one round of transmission or reception.
When the number of transmission data frames specified in the SPFC[1:0] bits is written to the SPDR/SPDR_HA register,
the SPI clears the SPSR.SPTEF flag to 0 and begins transmitting. After that, when the number of transmission data
frames specified in the SPFC[1:0] bits is transmitted to the shift register, the SPI generates the transmit buffer empty
interrupt (SPSR.SPTEF is set to 1).
When the number of data frames specified in the SPFC[1:0] bits is received, the SPI generates a receive buffer full
interrupt (SPSR.SPRF is set to 1).
The SPFC[1:0] bits are reserved for SPI1.
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Table 32.4
32. Serial Peripheral Interface (SPI)
Settable combinations of the SPSLN[2:0] and SPFC[1:0] bits
Setting
SPSLN[2:0]
SPFC[1:0]
Number of frames in
a single sequence
Number of frames at which transmit or receive buffer is
filled
1-1
000b
00b
1
1
1-2
000b
01b
2
2
1-3
000b
10b
3
3
1-4
000b
11b
4
4
2-1
001b
01b
2
2
2-2
001b
11b
4
4
3
010b
10b
3
3
4
011b
11b
4
4
5
100b
00b
5
1
6
101b
00b
6
1
7
110b
00b
7
1
8
111b
00b
8
1
SPRDTD bit (SPI Receive/Transmit Data Select)
The SPRDTD bit selects whether the SPDR/SPDR_HA register reads values from the receive buffer or from the transmit
buffer. If reading the transmit buffer, the value written to the SPDR/SPDR_HA register immediately beforehand is read.
Read the transmit buffer before the writing of the number of frames set in the SPFC[1:0] bits is finished and after
generation of the transmit buffer empty interrupt (SPSR.SPTEF = 1). For SPI1, read the transmit buffer after the
generation of the transmit buffer empty interrupt (SPSR.SPTEF = 1).
For details, see section 32.2.5, SPI Data Register (SPDR/SPDR_HA).
SPLW bit (SPI Word Access/Halfword Access Specification)
The SPLW bit specifies the access width for the SPDR register. Access to the SPDR_HA register in halfwords is valid
when the SPLW bit is 0 and access to the SPDR register in words is valid when the SPLW bit is 1. Also, when this bit is
0, set the SPI Data Length Setting bits, SPCMDm.SPB[3:0], from 8 to 16 bits. Do not perform any operations when a
data length of 20, 24, or 32 bits is specified.
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32.2.10
32. Serial Peripheral Interface (SPI)
SPI Clock Delay Register (SPCKD)
Address(es): SPI0.SPCKD 4007 200Ch, SPI1.SPCKD 4007 210Ch
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SCKDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SCKDL[2:0]
RSPCK Delay Setting
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK
1: 2 RSPCK
0: 3 RSPCK
1: 4 RSPCK
0: 5 RSPCK
1: 6 RSPCK
0: 7 RSPCK
1: 8 RSPCK.
R/W
The SPCKD register specifies the RSPCK delay, the period from the beginning of SSLni signal assertion to RSPCK
oscillation, when the SPCMDm.SCKDEN bit is 1. If the contents of the SPCKD register are changed while both the
SPCR.MSTR and SPCR.SPE bits are 1, do not perform subsequent operations.
SCKDL[2:0] bits (RSPCK Delay Setting)
The SCKDL[2:0] bits specify an RSPCK delay value when the SPCMDm.SCKDEN bit is 1. When using the SPI in slave
mode, set the SCKDL[2:0] bits to 000b.
32.2.11
SPI Slave Select Negation Delay Register (SSLND)
Address(es): SPI0.SSLND 4007 200Dh, SPI1.SSLND 4007 210Dh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SLNDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SLNDL[2:0]
SSL Negation Delay Setting
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK
1: 2 RSPCK
0: 3 RSPCK
1: 4 RSPCK
0: 5 RSPCK
1: 6 RSPCK
0: 7 RSPCK
1: 8 RSPCK.
R/W
The SSLND specifies the SSL negation delay, the period (SSL negation delay) from the transmission of a final RSPCK
edge to the negation of the SSLni signal during a serial transfer by the SPI in master mode. If the contents of the SSLND
register are changed while both the SPCR.MSTR and SPCR.SPE bits are 1, do not perform subsequent operations.
SLNDL[2:0] bits (SSL Negation Delay Setting)
The SLNDL[2:0] bits set an SSL negation delay value when the SPI is in master mode. When using the SPI in slave
mode, set the SLNDL[2:0] bits to 000b.
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32.2.12
32. Serial Peripheral Interface (SPI)
SPI Next-Access Delay Register (SPND)
Address(es): SPI0.SPND 4007 200Eh, SPI1.SPND 4007 210Eh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SPNDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SPNDL[2:0]
SPI Next-Access Delay Setting
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK + 2 PCLK
1: 2 RSPCK + 2 PCLK
0: 3 RSPCK + 2 PCLK
1: 4 RSPCK + 2 PCLK
0: 5 RSPCK + 2 PCLK
1: 6 RSPCK + 2 PCLK
0: 7 RSPCK + 2 PCLK
1: 8 RSPCK + 2 PCLK.
R/W
The SPND register specifies next-access delay, the non-active period of the SSLni signal after termination of a serial
transfer, when the SPCMDm.SPNDEN bit is 1. If the contents of the SPND register are changed while both the
SPCR.MSTR and SPCR.SPE bits are 1, do not perform subsequent operations.
SPNDL[2:0] bits (SPI Next-Access Delay Setting)
The SPNDL[2:0] bits specify a next-access delay when the SPCMDm.SPNDEN bit is 1. When using the SPI in slave
mode, set the SPNDL[2:0] bits to 000b.
32.2.13
SPI Control Register 2 (SPCR2)
Address(es): SPI0.SPCR2 4007 200Fh, SPI1.SPCR2 4007 210Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
SCKAS
E
PTE
SPIIE
SPOE
SPPE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SPPE
Parity Enable
0: Do not add parity bit to transmit data and do not check parity bit of
receive data
1: When SPCR.TXMD = 0: Add parity bit to transmit data and check
parity bit of receive data.
When SPCR.TXMD = 1: Add parity bit to transmit data but do not
check parity bit of receive data.
R/W
b1
SPOE
Parity Mode
0: Select even parity for transmission and reception
1: Select odd parity for transmission and reception.
R/W
b2
SPIIE
SPI Idle Interrupt Enable
0: Disable idle interrupt requests
1: Enable idle interrupt requests.
R/W
b3
PTE
Parity Self-Testing
0: Disable self-diagnosis function of the parity circuit
1: Enable self-diagnosis function of the parity circuit.
R/W
b4
SCKASE
RSPCK Auto-Stop Function
Enable
0: Disable RSPCK auto-stop function
1: Enable RSPCK auto-stop function.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the SPPE, SPOE, or SCKASE bit in SPCR2 is changed while the SPE bit in the SPCR register is 1, do not perform
subsequent operations.
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32. Serial Peripheral Interface (SPI)
SPPE bit (Parity Enable)
The SPPE bit enables or disables the parity function.
When the SPCR.TXMD bit is 0 and the SPCR2.SPPE bit is 1, the parity bit is added to transmit data and parity checking
is performed for receive data.
When the SPCR.TXMD bit is 1 and the SPCR2.SPPE bit is 1, the parity bit is added to transmit data but parity checking
is not performed for receive data.
SPOE bit (Parity Mode)
The SPOE bit specifies odd or even parity.
When even parity is set, parity bit addition is performed so that the total number of bits whose value is 1 in the transmit
or receive character plus the parity bit is even. Similarly, when an odd parity is set, parity bit addition is performed so that
the total number of bits whose value is 1 in the transmit or receive character plus the parity bit is odd.
The SPOE bit is valid only when the SPPE bit is 1.
SPIIE bit (SPI Idle Interrupt Enable)
The SPIIE bit enables or disables the generation of SPI idle interrupt requests when an idle state is detected in the SPI
and the SPSR.IDLNF flag is set to 0.
PTE bit (Parity Self-Testing)
The PTE bit enables self-diagnosis of the parity circuit in order to check whether the parity function is operating
correctly.
SCKASE bit (RSPCK Auto-Stop Function Enable)
The SCKASE bit enables or disables the RSPCK auto-stop function. When this function is enabled, the RSPCK clock is
stopped before an overrun error occurs, when data is received in master mode. For details, see section 32.3.8.1, Overrun
errors.
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32.2.14
32. Serial Peripheral Interface (SPI)
SPI Command Registers (SPCMDm) (m =0 to 7 for SPI0; m = 0 for SPI1)
Address(es): SPI0.SPCMD0 4007 2010h, SPI0.SPCMD1 4007 2012h, SPI0.SPCMD2 4007 2014h, SPI0.SPCMD3 4007 2016h,
SPI0.SPCMD4 4007 2018h, SPI0.SPCMD5 4007 201Ah, SPI0.SPCMD6 4007 201Ch, SPI0.SPCMD7 4007 201Eh
b15
b14
b13
b12
b11
b10
SCKDE SLNDE SPNDE LSBF
N
N
N
(SPI0)
0
Value after reset:
0
0
b9
b8
SPB[3:0]
b7
b6
SSLKP
b5
b4
SSLA[2:0]
b3
b2
BRDV[1:0]
b1
b0
CPOL
CPHA
0
0
1
1
1
0
0
0
0
1
1
0
1
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
CPOL
CPHA
0
1
Address(es): SPI1.SPCMD0 4007 2110h
b15
b14
b13
SCKDE SLNDE SPNDE LSBF
N
N
N
(SPI1)
Value after reset:
0
0
0
0
SPB[3:0]
0
1
—
1
1
0
SSLA[2:0]
0
0
BRDV[1:0]
0
1
1
Bit
Symbol
Bit name
Description
R/W
b0
CPHA
RSPCK Phase Setting
0: Select data sampling on leading edge, data change on trailing
edge
1: Select data change on leading edge, data sampling on trailing
edge.
R/W
b1
CPOL
RSPCK Polarity Setting
0: Set RSPCK low when idle
1: Set RSPCK high when idle.
R/W
b3, b2
BRDV[1:0]
Bit Rate Division Setting
b3 b2
R/W
b6 to b4
SSLA[2:0]
SSL Signal Assertion Setting
b6
b7
SSLKP
SSL Signal Level Keeping
• SPI0
0: Negate all SSL signals on completion of transfer
1: Keep the SSL signal level from the end of transfer until the
beginning of the next access.
R/W
—
Reserved
• SPI1
This bit is read as 0. The write value should be 0.
R/W
b11 to b8
SPB[3:0]
SPI Data Length Setting
b11
R/W
b12
LSBF
SPI LSB First
0: MSB first
1: LSB first.
R/W
b13
SPNDEN
SPI Next-Access Delay
Enable
0: Select next-access delay of 1 RSPCK + 2 PCLK
1: Select next-access delay equal to the setting of the SPI NextAccess Delay Register (SPND).
R/W
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0
0
1
1
0: Select the base bit rate
1: Select the base bit rate divided by 2
0: Select the base bit rate divided by 4
1: Select the base bit rate divided by 8.
R/W
b4
0 0 0: SSL0
0 0 1: SSL1
0 1 0: SSL2
0 1 1: SSL3
1 x x: Setting prohibited
x: Don’t care.
b8
0100 to 0111: 8 bits
1 0 0 0: 9 bits
1 0 0 1: 10 bits
1 0 1 0: 11 bits
1 0 1 1: 12 bits
1 1 0 0: 13 bits
1 1 0 1: 14 bits
1 1 1 0: 15 bits
1 1 1 1: 16 bits
0 0 0 0: 20 bits
0 0 0 1: 24 bits
0010, 0011: 32 bits.
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32. Serial Peripheral Interface (SPI)
Bit
Symbol
Bit name
Description
R/W
b14
SLNDEN
SSL Negation Delay Setting
Enable
0: Select SSL negation delay of 1 RSPCK
1: Select SSL negation delay equal to the setting in the SPI Slave
Select Negation Delay Register (SSLND).
R/W
b15
SCKDEN
RSPCK Delay Setting Enable
0: Select RSPCK delay of 1 RSPCK
1: Select RSPCK delay equal to the setting in the SPI Clock Delay
Register (SPCKD).
R/W
SPI0
SPI0 has eight SPI command registers, SPCMD0 to SPCMD7. The SPCMDm (m = 0 to 7) registers specify the transfer
format for the SPI in master mode. Some of the bits in the SPCMD0 register are used to set the transfer mode for the SPI
in slave mode. The SPI in master mode sequentially references the SPCMDm register based on the settings in the
SPSCR.SPSLN[2:0] bits and executes the serial transfer that is set in the referenced SPCMDm register.
Set the SPCMDm register while the transmit buffer is empty (SPSR.SPTEF is 1 and data for the next transfer is not set),
and before the setting of data to be transmitted when that SPCMDm register is referenced.
The SPCMDm register referenced by the SPI in master mode can be checked with the SPSSR.SPCP[2:0] bits. If the
contents of SPCMDm are changed while the SPCR.MSTR bit is 0 and the SPCR.SPE bit is 1, do not perform subsequent
operations.
SPI1
SPI1 has one SPI Command Register (SPCMD). The SPI Command Register (SPCMD) specifies the transfer format in
master mode. Some of the bits in the SPCMD0 register are used to set the transfer mode for the SPI in slave mode. If the
SPCMD register is rewritten while the SPE bit of the SPCR register is 1, subsequent operation cannot be guaranteed.
CPHA bit (RSPCK Phase Setting)
The CPHA bit selects the RSPCK phase of the SPI in master mode or slave mode. Data communications between SPI
modules require the same RSPCK phase setting between the modules.
CPOL bit (RSPCK Polarity Setting)
The CPOL bit selects the RSPCK polarity of the SPI in master mode or slave mode. Data communications between SPI
modules require the same RSPCK polarity setting between the modules.
BRDV[1:0] bits (Bit Rate Division Setting)
The BRDV[1:0] bits determine the bit rate. The bit rate is determined by combination of the settings in the BRDV[1:0]
bits and the SPBR register. See section 32.2.8, SPI Bit Rate Register (SPBR). The SPBR settings determine the base bit
rate. The BRDV[1:0] settings select a bit rate that is obtained by dividing the base bit rate by 1, 2, 4, or 8. Different
BRDV[1:0] bit settings can be specified in the SPCMDm registers for SPI0. This enables execution of serial transfers at
a different bit rate for each command.
SSLA[2:0] bits (SSL Signal Assertion Setting)
The SSLA[2:0] bits control the SSLni signal assertion when the SPI performs serial transfers in master mode. When an
SSLni signal is asserted, its polarity is determined by the value set in the associated SSLP. When the SSLA[2:0] bits are
set to 000b in multi-master mode, serial transfers are performed with all the SSL signals in the negated state, as the
SSLn0 pin acts as input.
When using the SPI in slave mode, set the SSLA[2:0] bits to 000b.
SSLKP bit (SSL Signal Level Keeping)
When the SPI in master mode performs a serial transfer, the SSLKP bit specifies whether the SSLni signal level for the
current command is to be kept or negated between the SSL negation timing associated with the current command and the
SSL assertion timing associated with the next command.
Setting the SSLKP bit to 1 enables a burst transfer. For details, see (4) Burst transfer in section 32.3.10.1, Master mode
operation. When using the SPI in slave mode, set the SSLKP bit to 0.
The SSLKP bit is reserved for SPI1.
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32. Serial Peripheral Interface (SPI)
SPB[3:0] bits (SPI Data Length Setting)
The SPB[3:0] bits specify the transfer data length for the SPI in master or slave mode. When the SPLW bit is 0, set these
bits from 8 to 16 bits.
LSBF bit (SPI LSB First)
The LSBF bit specifies the data format of the SPI in master or slave mode to MSB-first or LSB-first.
SPNDEN bit (SPI Next-Access Delay Enable)
The SPNDEN bit specifies the next-access delay, the period from the time the SPI in master mode terminates a serial
transfer and sets the SSLni signal inactive until the SPI enables the SSLni signal assertion for the next access. If the
SPNDEN bit is 0, the SPI sets the next-access delay to 1 RSPCK + 2 PCLK. If the SPNDEN bit is 1, the SPI inserts a
next-access delay in accordance with the SPND setting.
When using the SPI in slave mode, set the SPNDEN bit to 0.
SLNDEN bit (SSL Negation Delay Setting Enable)
The SLNDEN bit specifies the SSL negation delay, the period from the time the SPI in master mode stops RSPCK
oscillation until the SPI sets the SSLni signal to inactive. If the SLNDEN bit is 0, the SPI sets the SSL negation delay to
1 RSPCK. If the SLNDEN bit is 1, the SPI negates the SSL signal at an SSL negation delay determined by the SSLND
setting.
When using the SPI in slave mode, set the SLNDEN bit to 0.
SCKDEN bit (RSPCK Delay Setting Enable)
The SCKDEN bit specifies the SPI clock delay, the period between when the SPI in master mode asserts the SSLni signal
until the RSPCK starts oscillation. If the SCKDEN bit is 0, the SPI sets the RSPCK delay to 1 RSPCK. If the SCKDEN
bit is 1, the SPI starts the oscillation of RSPCK at an RSPCK delay determined by the SPCKD setting.
When using the SPI in slave mode, set the SCKDEN bit to 0.
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32.3
32. Serial Peripheral Interface (SPI)
Operation
In this section, the serial transfer period refers to a period from the beginning of driving valid data to the fetching of the
final valid data.
32.3.1
Overview of SPI Operations
The SPI is capable of synchronous serial transfers in the following modes:
Slave mode (SPI operation)
Single-master mode (SPI operation)
Multi-master mode (SPI operation)
Slave mode (clock synchronous operation)
Master mode (clock synchronous operation).
The SPI mode can be selected using the MSTR, MODFEN, and SPMS bits in SPCR. Table 32.5 lists the relationship
between the SPI modes and SPCR settings, and provides a description for each mode.
Table 32.5
Relationship between SPCR settings and SPI modes (1 of 2)
Mode
Slave
(SPI operation)
MSTR bit setting
MODFEN bit setting
Single-master
(SPI operation)
Multi-master
(SPI operation)
Slave
(clock
synchronous
operation)
Master
(clock
synchronous
operation)
0
1
1
0
1
0 or 1
0
1
0
0
SPMS bit setting
0
0
0
1
1
RSPCKn signal
Input
Output
Output/Hi-Z
Input
Output
MOSIn signal
Input
Output
Output/Hi-Z
Input
Output
MISOn signal
Output/Hi-Z
Input
Input
Output
Input
SSLn0 signal
Input
Output
Input
Hi-Z*1
Hi-Z*1
SSLn1 to SSLn3 signals
Hi-Z*1
Output
Output/Hi-Z
Hi-Z*1
Hi-Z*1
Supported
Supported
Supported
-
-
Transfer rate
Up to PCLK/6
Up to PCLK/2
Up to PCLK/2
Up to PCLK/6
Up to PCLK/2
Clock source
RSPCKn input
On-chip baud rate
generator
On-chip baud rate
generator
RSPCKn input
On-chip baud rate
generator
Two
Two
One (CPHA = 1)
Two
SSL polarity change
function
Clock polarity
Clock phase
Two
First transfer bit
MSB/LSB
Transfer data length
Burst transfer
Two
8 to 16, 20, 24, 32 bits
Supported in SPI0
Supported in SPI0
Supported in SPI0
-
-
RSPCK delay control
Not supported
Supported
Supported
Not supported
Supported
SSL negation delay
control
Not supported
Supported
Supported
Not supported
Supported
Next-access delay
control
Not supported
Supported
Supported
Not supported
Supported
Transfer activation
method
SSL input active or
RSPCK oscillation
RSPCK oscillation
Write to transmit
buffer on generation of a transmit
buffer empty interrupt request
(SPTEF is 1)
Sequence control
Not supported
Not supported
Supported in SPI0
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Write to transmit buf- Write to transmit buffer on generation of
fer on generation of
a transmit buffer
a transmit buffer
empty interrupt
empty interrupt
request (SPTEF is 1) request (SPTEF is 1)
Supported in SPI0
Supported in SPI0
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Table 32.5
32. Serial Peripheral Interface (SPI)
Relationship between SPCR settings and SPI modes (2 of 2)
Slave
(SPI operation)
Mode
Single-master
(SPI operation)
Multi-master
(SPI operation)
Transmit buffer empty
detection
Supported*2
Supported*2
Supported*2, *4
Supported*2
Supported*2
Supported
(MODFEN = 1)
Not supported
Supported
Not supported
Not supported
Supported
Not supported
Not supported
Supported
Not supported
Underrun error detection
Note 1.
Note 2.
Note 3.
Note 4.
Supported*2, *4
Supported*2, *3
Parity error detection
Mode-fault error
detection
Master
(clock
synchronous
operation)
Supported
Receive buffer full
detection
Overrun error detection
Slave
(clock
synchronous
operation)
This function is not supported in this mode.
When the SPCR.TXMD bit is 1, detection of receiver buffer full, overrun error, and parity error is not performed.
When the SPCR2.SPPE bit is 0, parity error detection is not performed.
When the SPCR2.SCKASE bit is 1, overrun error detection is not performed.
32.3.2
Controlling SPI Pins
The SPI can switch pin states based on the MSTR, MODFEN, and SPMS bit settings in the SPCR register and the
PmnPFS.NCODR bit for the I/O ports. Table 32.6 lists the relationship between pin states and bit settings. Setting the
PmnPFS.NCODR bit for an I/O port to 0 selects the CMOS output. Setting it to 1 selects the open-drain output. The I/O
port settings must follow this relationship.
Table 32.6
Relationship between pin states and bit settings
Pin state*2
PmnPFS.NCODR bit for I/O
ports = 0
PmnPFS.NCODR bit for I/O
ports = 1
Mode
Pin
Single-master mode (SPI operation)
(MSTR = 1, MODFEN = 0, SPMS = 0)
RSPCKn
CMOS output
Open-drain output
SSLn0 to SSLn3
CMOS output
Open-drain output
MOSIn
CMOS output
Open-drain output
MISOn
Input
Input
RSPCKn*3
CMOS output/Hi-Z
Open-drain output/Hi-Z
SSLn0
Input
Input
Multi-master mode (SPI operation)
(MSTR = 1, MODFEN = 1, SPMS = 0)
CMOS output/Hi-Z
Open-drain output/Hi-Z
MOSIn*3
CMOS output/Hi-Z
Open-drain output/Hi-Z
MISOn
Input
Input
SSLn1 to
Slave mode (SPI operation)
(MSTR = 0, SPMS = 0)
Master mode
(Clock synchronous operation)
(MSTR = 1, MODFEN = 0, SPMS = 1)
Slave mode
(Clock synchronous operation)
(MSTR = 0, SPMS = 1)
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SSLn3*3
RSPCKn
Input
Input
SSLn0
Input
Input
SSLn1 to SSLn3*5
Hi-Z*1
Hi-Z*1
MOSIn
Input
Input
MISOn*4
CMOS output/Hi-Z
Open-drain output/Hi-Z
RSPCKn
CMOS output
Open-drain output
SSLn0 to SSLn3*5
Hi-Z*1
Hi-Z*1
MOSIn
CMOS output
Open-drain output
MISOn
Input
Input
RSPCKn
Input
Input
SSLn0 to SSLn3*5
Hi-Z*1
Hi-Z*1
MOSIn
Input
Input
MISOn
CMOS output
Open-drain output
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Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
32. Serial Peripheral Interface (SPI)
This function is not supported in this mode.
SPI settings are not reflected in multiplexed pins for which the SPI function is not selected.
When SSLn0 is at the active level, the pin state is Hi-Z.
When SSLn0 is at the non-active level or the SPCR.SPE bit is 0, the pin state is Hi-Z.
These pins are available for use as I/O port pins.
The SPI in single-master or multi-master mode (SPI operation) determines MOSI signal values during the SSL negation
period (including the SSL retention period during a burst transfer for SPI0) based on the MOIFE and MOIFV bit settings
in SPPCR, as listed in Table 32.7.
Table 32.7
MOSI signal value determination during SSL negation period
MOIFE bit
MOIFV bit
MOSIn signal value during SSL negation period
0
0, 1
Final data from previous transfer
1
0
Low
1
1
High
32.3.3
32.3.3.1
SPI System Configuration Examples
Single-master/single-slave with the MCU as master
Figure 32.8 shows a single-master/single-slave SPI system configuration example where the MCU is used as a master. In
the single-master/single-slave configuration, the SSLn0 to SSLn3 outputs of the MCU (master) are not used. The SSL
input of the SPI slave is fixed to the low level, and the SPI slave is maintained in the selected state.*1
The MCU (master) drives the RSPCKn and MOSIn signals. The SPI slave drives the MISO signal.
Note 1. In the transfer format used when the SPCMDm.CPHA is 0, the SSL signal cannot be fixed to an active level for
some slave devices. In this case, always connect the SSLni output of the MCU to the SSL input of the slave
device.
M C U (m a s te r)
RRSPCKn
SPCK
MOSIn
M
OSI
M
IS O
MISOn
S S L0
SSLn0
S S L1
SSLn1
S
SL2
S
SL3
SSLn2
S P I s la v e
SPCK
MOSI
M IS O
SSL
SSLn3
Figure 32.8
Single-master/single-slave configuration example with the MCU as the master
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32.3.3.2
32. Serial Peripheral Interface (SPI)
Single-master/single-slave with the MCU as slave
Figure 32.9 shows a single-master/single-slave SPI system configuration example where the MCU is used as a slave.
When the MCU is to operate as a slave, the SSLn0 pin is used as SSL input. The SPI master drives the RSPCK and
MOSI signals. The MCU (slave) drives the MISOn signal.*1
In the single-slave configuration when the SPCMDm.CPHA bit is set to 1, the SSLn0 input of the MCU (slave) is fixed
to the low level, and the MCU (slave) is maintained in the selected state. This enables serial transfer execution (Figure
32.10).
Note 1. When SSLn0 is at a non-active level, the pin state is Hi-Z.
MCU (slave)
SPI master
SPCK
RSPCKn
RSPCK
MOSI
MOSI
MOSIn
MISO
MISO
MISOn
SSL
SSL0
SSLn0
SSL1
SSLn1
SSL2
SSLn2
SSL3
SSLn3
Figure 32.9
Single-master/single-slave configuration example with the MCU as a slave and CPHA = 0
MCU (slave, CPHA = 1)
SPI master
SPCK
MOSI
MISO
SSL
RSPCKn
RSPCK
MOSIn
MOSI
MISO
MISOn
SSL0
SSLn0
SSL1
SSLn1
SSL2
SSL3
SSLn2
SSLn3
Figure 32.10
Single-master/single-slave configuration example with the MCU as a slave and CPHA = 1
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32.3.3.3
32. Serial Peripheral Interface (SPI)
Single-master/multi-slave with the MCU as master
Figure 32.11 shows a single-master/multi-slave SPI system configuration example where the MCU is a master. In this
example, the SPI system includes the MCU (master) and four slaves (SPI slave 0 to SPI slave 3).
The RSPCKn and MOSIn outputs of the MCU (master) are connected to the RSPCK and MOSI inputs of SPI slave 0 to
SPI slave 3. The MISO outputs of SPI slave 0 to SPI slave 3 are all connected to the MISOn input of the MCU (master).
The SSLn0 to SSLn3 outputs of the MCU (master) are connected to the SSL inputs of SPI slave 0 to SPI slave 3,
respectively.
The MCU (master) drives the RSPCKn, MOSIn signals, and SSLn0 to SSLn3 pins. Among SPI slave 0 to SPI slave 3,
the slave that receives low-level input into the SSL input drives the MISO signal.
MCU (master)
SPI slave 0
RSPCK
RSPCKn
SPCK
MOSIn
MOSI
MOSI
MISO
MISOn
MISO
SSLn0
SSL0
SSL
SSLn1
SSL1
SSL2
SSLn2
SSL3
SSLn3
SPI slave 1
SPCK
MOSI
MISO
SSL
SPI slave 2
SPCK
MOSI
MISO
SSL
SPI slave 3
SPCK
MOSI
MISO
SSL
Figure 32.11
Single-master/multi-slave configuration example with the MCU as master
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32.3.3.4
32. Serial Peripheral Interface (SPI)
Single-master/multi-slave with the MCU configured as a slave
Figure 32.12 shows a single-master/multi-slave SPI system configuration example where the MCU is a slave. In this
example, the SPI system includes an SPI master and two MCUs (slave X and slave Y).
The SPCK and MOSI outputs of the SPI master are connected to the RSPCKn and MOSIn inputs of the MCUs (slave X
and slave Y). The MISOn outputs of the MCUs (slave X and slave Y) are all connected to the MISO input of the SPI
master. SSLX and SSLY outputs of the SPI master are connected to the SSLn0 inputs of the MCUs (slave X and slave
Y), respectively.
The SPI master drives the SPCK, MOSI, SSLX, and SSLY signals. The MCUs (slaves X and Y) that receives low-level
input into the SSLn0 input drives MISOn.
SPI master
SPCK
MOSI
MISO
SSLX
SSLY
MCU (slave X)
RSPCKn
RSPCK
MOSIn
MOSI
MISO
MISOn
SSL0
SSLn0
SSL1
SSLn1
SSL2
SSLn2
SSL3
SSLn3
MCU (slave Y)
RSPCKn
RSPCK
MOSI
MOSIn
MISO
MISOn
SSL0
SSLn0
SSL1
SSLn1
SSL2
SSL3
SSLn2
SSLn3
Figure 32.12
Single-master/multi-slave configuration example with the MCU as slave
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32.3.3.5
32. Serial Peripheral Interface (SPI)
Multi-master/multi-slave with the MCU as master
Figure 32.13 shows a multi-master and multi-slave SPI system configuration example where the MCU is a master. In the
example shown in Figure 32.13, the SPI system comprises two MCUs (master X and master Y) and two SPI slaves (SPI
slave 1 and SPI slave 2).
The RSPCKn and MOSIn outputs of the MCUs (master X and master Y) are connected to the RSPCK and MOSI inputs
of SPI slaves 1 and 2. The MISO outputs of SPI slaves 1 and 2 are connected to the MISOn inputs of the MCUs (master
X and master Y). Any generic port Y output from the MCU (master X) is connected to the SSLn0 input of the MCU
(master Y). Any generic port X output of the MCU (master Y) is connected to the SSLn0 input of the MCU (master X).
The SSLn1 and SSLn2 outputs of the MCUs (master X and master Y) are connected to the SSL inputs of the SPI slaves
1 and 2. In this configuration example, because the system can be comprised solely of SSLn0 input, and SSLn1 and
SSLn2 outputs for slave connections, the SSLn3 output of the MCU is not required.
The MCU drives the RSPCKn, MOSIn, SSLn1, and SSLn2 signals when the SSLn0 input level is high. When the SSLn0
input level is low, the MCU detects a mode-fault error, sets RSPCKn, MOSIn, SSLn1, and SSLn2 to Hi-Z, and releases
the SPI bus directly to the other master. Of the SPI slaves 1 and 2, the slave that receives low-level input into the SSL
input drives the MISO signal.
MCU (master X)
RSPCKn
RSPCK
MOSIn
MOSI
MISOn
MISO
SSLn0
SSL0
SSL1
SSLn1
SSL2
SSLn2
SSL3
SSLn3
Port Y
MCU (master Y)
RSPCKn
MOSIn
RSPCK
MISOn
MOSI
SSLn0
MISO
SSLn1
SSL0
SSL1
SSLn2
SSL2
SSLn3
SSL3
Port X
SPI slave 1
SPCK
MOSI
MISO
SSL
SPI slave 2
SPCK
MOSI
MISO
SSL
Figure 32.13
Multi-master/multi-slave configuration example with the MCU as master
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32.3.3.6
32. Serial Peripheral Interface (SPI)
Clock synchronous master/slave configuration with the MCU as master
Figure 32.14 shows a master/slave clock synchronous mode configuration where the MCU is a master. In the master and
slave clock synchronous mode configuration, SSLn0 to SSLn3 of the MCU (master) are not used.
The MCU (master) drives the RSPCKn and MOSIn signals. The SPI slave drives the MISO signal.
MCU (master)
RSPCKn
RSPCK
MOSIn
MOSI
MISO
MISOn
SSL0
SSLn0
SSL1
SSLn1
SSL2
SSLn2
SSL3
SSLn3
SPI slave
SPCK
MOSI
MISO
SSL
Figure 32.14
Clock synchronous master/slave configuration example with the MCU as master
32.3.3.7
Clock synchronous master/slave configuration with the MCU as slave
Figure 32.15 shows a master/slave in clock synchronous mode configuration example where the MCU is a slave. When
the MCU is to operate as a slave in clock synchronous operation, the MCU (slave) drives the MISOn signal and the SPI
master drives the SPCK and MOSI signals. The SSLn0 to SSLn3 of the MCU (slave) are not used.
The MCU (slave) can only execute serial transfer in the single-slave configuration when the SPCMDm.CPHA is set to 1.
SPI master
MCU (slave)
SPCK
MOSI
MISO
SSL
Figure 32.15
RSPCKn
RSPCK
MOSIn
MOSI
MISO
MISOn
SSL0
SSLn0
SSL1
SSLn1
SSL2
SSLn2
SSL3
SSLn3
Clock synchronous master/slave configuration example with the MCU as slave and CPHA = 1
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32.3.4
32. Serial Peripheral Interface (SPI)
Data Format
The data format of the SPI depends on the settings in the SPI Command Register m (SPCMDm) (m = 0 to 7) and the
Parity Enable bit in SPI Control Register 2 (SPCR2.SPPE). Regardless of whether the ordering is MSB- or LSB-first, the
SPI treats the range from the LSB bit in the SPI Data Register (SPDR/SPDR_HA) to the bit associated with the selected
data length as transfer data.
This section shows the format of one frame of data before or after transfer.
(a)
With parity disabled
When parity is disabled, transmission or reception of data proceeds with the bit-length selected in the SPI Data Length
Setting bits in the SPI Command Register m (SPCMDm.SPB[3:0] for SPI0, SPCMD0.SPB[3:0] for SPI1).
(b)
With parity enabled
When parity is enabled, transmission or reception of data proceeds with the bit-length selected in the SPI data length
setting bits in SPI Command Register m (SPCMDm.SPB[3:0] for SPI0, SPCMD0.SPB[3:0] for SPI1). In this case,
however, the last bit is a parity bit.
SPI0
With parity
disabled
D0
D1
D2
Dn-2
Dn-1
Dn
SPCMDm.SPB[3:0] (m = SPSSR.SPCP[2:0])
With parity
enabled
D0
D1
D2
Dn-2
Dn-1
P
SPCMDm.SPB[3:0] (m = SPSSR.SPCP[2:0])
Figure 32.16
Data format with parity disabled and enabled (SPI0)
SPI1
Figure 32.17
With parity
disabled
D0
With parity
enabled
D0
D1
D2
D n-2 D n-1 D n
SPCMD0.SPB[3:0]
D1
D2
D n-2 D n-1
P
SPCMD0.SPB[3:0]
Data format with parity disabled and enabled (SPI1)
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32.3.4.1
32. Serial Peripheral Interface (SPI)
Operation when parity is disabled (SPCR2.SPPE = 0)
When parity is disabled, data for transmission is copied to the shift register with no pre-processing. This section
describes the connection between the SPI Data Register (SPDR/SPDR_HA) and the shift register in terms of the
combination of MSB- or LSB-first order and data length.
(1)
MSB-first transfer with 32-bit data
Figure 32.18 shows the transfer operations of the SPI Data Register (SPDR) and the shift register in a transfer with parity
disabled, a SPI data length of 32 bits, and MSB-first selected.
In transmission, bits T31 to T00 from the current stage of the transmit buffer are copied to the shift register. Data for
transmission is shifted out from the shift register from T31 to T30, and continuing to T00 in that order.
In reception, received data is shifted in bit by bit through bit [0] of the shift register. When the R31 to R00 bits are
collected after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive
buffer.
Transfer start
Bit 31
Transmit buffer
T31 T30 T29 T28 T27 T26 T25 T24 T23
Bit 0
T08 T07 T06 T05 T04 T03 T02 T01 T00
Copy
Output
T31 T30 T29 T28 T27 T26 T25 T24 T23
Bit 31
T08 T07 T06 T05 T04 T03 T02
Shift register
T01 T00
Bit 0
Transfer end
Bit 31
Shift register
Bit 0
R08 R07 R06 R05 R04 R03 R02 R01 R00
R31 R30 R29 R28 R27 R26 R25 R24 R23
Input
Copy
R31 R30 R29 R28 R27 R26 R25 R24 R23
Bit 31
Note:
R08 R07 R06 R05 R04 R03 R02 R01 R00
Receive buffer
Bit 0
Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 32.18
MSB-first transfer with 32-bit data and parity disabled
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32. Serial Peripheral Interface (SPI)
MSB-first transfer with 24-bit data
Figure 32.19 shows the operation of the SPI Data Register (SPDR) and the shift register in a transfer with parity disabled,
a SPI data length of 24 bits for an example that is not 32 bits, and MSB-first selected.
In transmission, the lower 24 bits (T23 to T00) from the current stage of the transmit buffer are copied to the shift
register. Data for transmission is shifted out from the shift register from T23 to T22, continuing to T00 in that order.
In reception, received data is shifted in bit by bit through bit [0] of the shift register. When the R23 to R00 bits are
collected after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive
buffer. The upper 8 bits of the transmit buffer are stored in the upper 8 bits of the receive buffer. Writing 0 to the T31 to
T24 bits at the time of transmission leads to 0 being inserted in the upper 8 bits of the receive buffer.
Transfer start
Transmit buffer
Bit 23
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T08
T07
T06
T05
T04
T03
T02
T01
T00
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 23
Shift register
Bit 31
T00
Bit 0
Transfer end
Bit 24
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
Shift register
Bit 23
R23
Bit 0
R08
R07
R06
R05
R04
R03
R02
R01
R00
R08
R07
R06
R05
R04
R03
R02
R01
R00
Input
Copy
T31
T30
T29
T28
Bit 31
Note:
T27
T26
T25
T24
Bit 24
R23
Bit 23
Receive buffer
Bit 0
Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 32.19
MSB-first transfer with 24-bit data and parity disabled
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32. Serial Peripheral Interface (SPI)
LSB-first transfer with 32-bit data
Figure 32.20 shows the operation of the SPI Data Register (SPDR) and the shift register in a transfer with parity disabled,
a SPI data length of 32 bits, and LSB-first selected.
In transmission, bits T31 to T00 from the current stage of the transmit buffer are reordered bit by bit to obtain the order
T00 to T31 for copying to the shift register. Data for transmission is shifted out from the shift register from T00 to T01,
and continuing to T31 in that order.
In reception, received data is shifted in bit by bit through bit [0] of the shift register. When the R00 to R31 bits are
collected after input of the required number RSPCK cycles, the value in the shift register is copied to the receive buffer.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T23
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
R23
R24
R25
R26
R27
R28
R29
R30
R31
R08
R07
R06
R05
R04
R03
R02
R01
R00
Input
Copy
R31
R30
R29
R28
Bit 31
Note:
R27
R26
R25
R24
R23
Receive buffer
Bit 0
Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 32.20
LSB-first transfer with 32-bit data and parity disabled
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32. Serial Peripheral Interface (SPI)
LSB-first transfer with 24-bit data
Figure 32.21 shows the operation of the SPI Data Register (SPDR) and the shift register in a transfer with parity disabled,
a SPI data length of 24 bits for an example that is not 32 bits, and LSB-first selected.
In transmission, the lower 24 bits (T23 to T00) from the current stage of the transmit buffer are reordered bit by bit to
obtain the order T00 to T23 for copying to the shift register. Data for transmission is shifted out from the shift register
from T00 to T01, and continuing to T23 in that order.
In reception, received data is shifted in bit by bit through bit [8] of the shift register. When the R00 to R23 bits are
collected after input of the required number RSPCK cycles, the value in the shift register is copied to the receive buffer.
The upper 8 bits of the transmit buffer are stored in the upper 8 bits of the receive buffer. Writing 0 to the T31 to T24 bits
at the time of transmission leads to 0 being inserted in the upper 8 bits of the receive buffer.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T23
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Input
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
R23
T24
T25
T26
T27
T28
T29
T30
T31
R08
R07
R06
R05
R04
R03
R02
R01
R00
Copy
T31
T30
T29
T28
Bit 31
Note:
Figure 32.21
T27
T26
T25
T24
R23
Receive buffer
Bit 0
Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
LSB-first transfer with 24-bit data and parity disabled
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32.3.4.2
32. Serial Peripheral Interface (SPI)
Operation when parity is enabled (SPCR2.SPPE = 1)
When parity is enabled, the lowest-order bit of the data for transmission becomes a parity bit. Hardware calculates the
value of the parity bit.
(1)
MSB-first transfer with 32-bit data
Figure 32.22 shows the operation of the SPI Data Register (SPDR) and the shift register in a transfer with parity enabled,
a SPI data length of 32 bits, and MSB-first selected.
In transmission, the value of the parity bit (P) is calculated from bits T31 to T01. This replaces the final bit, T00, and the
whole value is copied to the shift register. Data is transmitted in the order T31, T30, …, T01, and P.
In reception, received data is shifted in bit by bit through bit [0] of the shift register. When the R31 to P bits are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On
copying of data to the shift register, the data from R31 to P is checked for parity.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T08
T23
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
T31
T30
T29
T28
T27
T26
T25
T24
T23
Parity added
T08
T07
T06
T05
T04
T03
T02
T01
P
T08
T07
T06
T05
T04
T03
T02
T01
P
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
Bit 31
T23
Bit 0
Shift register
Transfer end
Shift register
Bit 31
R31
R30
R29
R28
R27
R26
R25
R24
R23
Bit 0
R08
R07
R06
R05
R04
R03
R02
R01
P
R08
R07
R06
R05
R04
R03
R02
R01
P
Input
Copy
R31
R30
R29
R28
R27
Bit 31
Note:
R26
R25
R24
R23
Receive buffer
Bit 0
Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 32.22
MSB-first transfer with 32-bit data and parity enabled
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32. Serial Peripheral Interface (SPI)
MSB-first transfer with 24-bit data
Figure 32.23 shows the operation of the SPI Data Register (SPDR) and the shift register in a transfer with parity enabled,
a SPI data length of 24 bits for an example that is not 32 bits, and MSB-first selected.
In transmission, the value of the parity bit (P) is calculated from bits T23 to T01. This replaces the final bit, T00, and the
whole value is copied to the shift register. Data is transmitted in the order T23, T22, …, T01, and P.
In reception, received data is shifted in bit by bit through bit [0] of the shift register. When the R23 to P bits are collected
after input of the required number RSPCK cycles, the value in the shift register is copied to the receive buffer. After data
is copied to the shift register, the data from R23 to P is checked for parity. The upper 8 bits of the transmit buffer are
stored in the upper 8 bits of the receive buffer. Writing 0 to the T31 to T24 bits at the time of transmission leads to 0
being inserted in the upper 8 bits of the receive buffer.
Transfer start
Transmit buffer
Bit 23
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
T08
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity added
T31
T30
T29
T28
T27
T26
T25
T24
T23
T08
T07
T06
T05
T04
T03
T02
T01
P
T08
T07
T06
T05
T04
T03
T02
T01
P
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 23
Shift register
Bit 31
Bit 0
Transfer end
Bit 24
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
Shift register
Bit 23
R23
Bit 0
R08
R07
R06
R05
R04
R03
R02
R01
R08
R07
R06
R05
R04
R03
R02
R01
P
Input
Copy
T31
T30
T29
T28
T27
Bit 31
Note:
T26
T25
T24
Bit 24
R23
Bit 23
Receive buffer
P
Bit 0
Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 32.23
MSB-first transfer with 24-bit data and parity enabled
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32. Serial Peripheral Interface (SPI)
LSB-first transfer with 32-bit data
Figure 32.24 shows the operation of the SPI Data Register (SPDR) and the shift register in a transfer with parity enabled,
a SPI data length of 32 bits, and LSB-first selected.
In transmission, the value of the parity bit (P) is calculated from the T30 to T00 bits. This replaces the final bit, T31, and
the whole value is copied to the shift register. Data is transmitted in the order T00, T01, …, T30, and P.
In reception, received data is shifted in bit by bit through bit [0] of the shift register. When bits R00 to P are collected
after input of the required number RSPCK cycles, the value in the shift register is copied to the receive buffer. On
copying of data to the shift register, the data from R00 to P is checked for parity.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T08
T23
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
Parity added
Bit 31
P
T30
Bit 0
T29
T28
T27
T26
T25
T24
T23
T08
T07
T06
T05
T04
T03
T02
T01
T00
T23
T24
T25
T26
T27
T28
T29
T30
P
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
R23
R24
R25
R26
R27
R28
R29
R30
P
R08
R07
R06
R05
R04
R03
R02
R01
R00
Input
Copy
P
R30
R29
R28
R27
Bit 31
Note:
R26
R25
R24
R23
Receive buffer
Bit 0
Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 32.24
LSB-first transfer with 32-bit data and parity enabled
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32. Serial Peripheral Interface (SPI)
LSB-first transfer with 24-bit data
Figure 32.25 shows the operation of the SPI Data Register (SPDR) and the shift register in a transfer with parity enabled,
a SPI data length of 24 bits for an example that is not 32 bits, and LSB-first selected.
In transmission, the value of the parity bit (P) is calculated from the T22 to T00 bits. This replaces the final bit, T23, and
the whole value is copied to the shift register. Data is transmitted in the order T00, T01, …, T22, and P.
In reception, received data is shifted in bit by bit through bit [8] of the shift register. When bits R00 to P are collected
after input of the required number RSPCK cycles, the value in the shift register is copied to the receive buffer. On
copying of data to the shift register, the data from R00 to P is checked for parity. The upper 8 bits of the transmit buffer
are stored in the upper 8 bits of the receive buffer. Writing 0 to the T31 to T24 bits at transmission leads to 0 being
inserted in the upper 8 bits of the receive buffer.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
T08
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
Parity added
Bit 0
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
P
T08
T07
T06
T05
T04
T03
T02
T01
T00
P
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Input
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
P
T24
T25
T26
T27
T28
T29
T30
T31
R08
R07
R06
R05
R04
R03
R02
R01
R00
Copy
T31
T30
T29
T28
T27
Bit 31
Note:
T26
T25
T24
P
Receive buffer
Bit 0
Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 32.25
LSB-first transfer with 24-bit data and parity enabled
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32.3.5
32. Serial Peripheral Interface (SPI)
Transfer Formats
32.3.5.1
Transfer format when CPHA = 0
Figure 32.26 shows an example transfer format for the serial transfer of 8-bit data when SPCMDm.CPHA is 0. Do not
perform clock synchronous operation (SPCR.SPMS = 1) when the SPI operates in slave mode (SPCR.MSTR = 0) and
the CPHA bit is 0. In Figure 32.26, RSPCKn (CPOL = 0) indicates the RSPCKn signal waveform when
SPCMDm.CPOL is 0, and RSPCKn (CPOL = 1) indicates the RSPCKn signal waveform when the CPOL bit is 1. The
sampling timing represents the timing at which the SPI fetches serial transfer data into the shift register. The I/O
directions of the signals depend on the SPI settings. For details, see section 32.3.2, Controlling SPI Pins.
When SPCMDm.CPHA is 0, the driving of valid data to the MOSIn and MISOn signals begins at an SSLni signal
assertion. The first RSPCKn signal change that occurs after the SSLni signal assertion becomes the first transfer data
fetch. After this, data is sampled every 1 RSPCK cycle. The change timing for the MOSIn and MISOn signals is 1/2
RSPCK cycles after the transfer data fetch timing. The CPOL bit setting does not affect the RSPCK signal operation
timing as it only affects the signal polarity.
t1 denotes the RSPCK delay, the period from an SSLni signal assertion to RSPCKn oscillation. t2 denotes the SSL
negation delay, the period from the termination of RSPCKn oscillation to an SSLni signal negation. t3 denotes the nextaccess delay, the period in which SSLni signal assertion is suppressed for the next transfer after the end of serial transfer.
t1, t2, and t3 are controlled by a master device running on the SPI system. For a description of t1, t2, and t3 when the SPI
is in master mode, see section 32.3.10.1, Master mode operation.
Start
End
Serial transfer period
RSPCK
cycle
1
2
3
4
5
6
7
8
RSPCK
RSPCKn
(CPOL
= 0)
(CPOL
= 0)
RSPCKn
RSPCK
(CPOL
= 1)
(CPOL
= 1)
Sampling
timing
MOSIn
MOSI
MISOn
MISO
SSLni
SSLi
t1
Figure 32.26
t2
t3
SPI transfer format when CPHA = 0
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32.3.5.2
32. Serial Peripheral Interface (SPI)
When CPHA = 1
Figure 32.27 shows an example transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 1.
However, when the SPCR.SPMS bit is 1, the SSLni signals are not used, and only the three signals RSPCKn, MOSIn,
and MISOn handle communications. In Figure 32.27, RSPCK (CPOL = 0) indicates the RSPCKn signal waveform when
the SPCMDm.CPOL bit is 0, and RSPCK indicates the RSPCKn signal waveform when the CPOL bit is 1. The sampling
timing represents the timing at which the SPI fetches serial transfer data into the shift register. The I/O directions of the
signals depend on the SPI mode (master or slave). For details, see section 32.3.2, Controlling SPI Pins.
When the SPCMDm.CPHA bit is 1, the driving of invalid data to the MISOn signal begins at an SSLni signal assertion.
The output of valid data to the MOSIn and MISOn signals begins at the first RSPCKn signal change that occurs after the
SSLni signal assertion. After this, data is updated every 1 RSPCK cycle. The transfer data fetch timing is 1/2 RSPCK
cycles after the data update timing. The SPCMDm.CPOL bit setting does not affect the RSPCKn signal operation timing.
It only affects the signal polarity.
t1, t2, and t3 are the same as those when CPHA = 0. For a description of t1, t2, and t3 when the MCU SPI is in master
mode, see section 32.3.10.1, Master mode operation.
Start
RSPCK
cycle
1
End
Serial transfer period
2
3
4
5
6
7
8
RSPCKn
(CPOL = 0)
RSPCKn
(CPOL = 1)
Sampling
timing
MOSIn
MISOn
SSLni
t1
Figure 32.27
t2
t3
SPI transfer format when CPHA = 1
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32.3.6
32. Serial Peripheral Interface (SPI)
Data Transfer Modes
Full-duplex synchronous serial communications or transmit operations can only be selected in the Communications
Operating Mode Select bit (SPCR.TXMD). The register accesses shown in Figure 32.28 and Figure 32.29 indicate the
condition of access to the SPDR/SPDR_HA register, where W denotes a write cycle.
32.3.6.1
Full-duplex synchronous serial communications (SPCR.TXMD = 0)
Figure 32.28 shows an example of operation where the Communications Operating Mode Select bit (SPCR.TXMD) is
set to 0. In this example, the SPI performs an 8-bit serial transfer in which the SPDCR.SPFC[1:0] bits are 00b, the
SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0 for SPI0, and in which the SPCMD0.CPHA bit is 1 and the
SPCMD0.CPOL bit is 0 for SPI1. The numbers given for RSPCKn in the waveform represent the number of RSPCK
cycles, such as the number of transferred bits.
SPDR_HA access
RSPCKn
(CPHA = 1, CPOL = 0)
Receive buffer state
W
W
1
2
3
4
5
6
7
8
1
Empty
2
3
4
5
6
7
8
Full
SPIn_SPRI
(1)
SPRF
OVRF
(2)
Figure 32.28
Operation example when SPCR.TXMD = 0
The operation of the flags at timings (1) and (2) in the Figure 32.28 is as follows:
1. When a serial transfer ends with the SPDR_HA receive buffer empty, the SPI generates a receive buffer full
interrupt request (SPIn_SPRI), the SPI sets the SPSR.SPRF flag to 1 and copies the received data in the shift
register to the receive buffer.
2. When a serial transfer ends with the receive buffer of SPDR_HA holding data that was received in the previous
serial transfer, the SPI sets the SPSR.OVRF flag to 1 and discards the received data in the shift register.
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32.3.6.2
32. Serial Peripheral Interface (SPI)
Transmit only operations (SPCR.TXMD = 1)
Figure 32.29 shows an example of operation where the Communications Operating Mode Select bit (SPCR.TXMD) is
set to 1. In the example, the SPI performs an 8-bit serial transfer in which the SPDCR.SPFC[1:0] bits are 00b, the
SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0 for SPI0, and in which the SPCMD0.CPHA bit is 1 and the
SPCMD0.CPOL bit is 0 for SPI1. The numbers given for RSPCKn in the waveform represent the number of RSPCK
cycles, such as the number of transferred bits.
W
SPDR_HA access
RSPCKn
(CPHA = 1, CPOL = 0)
TXMD
(TXMD = 1)
W
1
2
3
4
5
6
7
1
8
2
3
4
5
6
7
8
(1)
Receive buffer state
Empty
SPIn_SPRI
SPRF
(2)
OVRF
(3)
Figure 32.29
Operation example when SPCR.TXMD = 1
The operation of the flags at timings (1) to (3) in the Figure 32.29 is as follows:
1. Make sure that there is no data left in the receive buffer (SPSR.SPRF = 0) and the SPSR.OVRF flag is 0 before
entering the transmit-only mode (SPCR.TXMD = 1).
2. When a serial transfer ends with the receive buffer of SPDR_HA empty, if the transmit-only mode is selected
(SPCR.TXMD = 1), the SPSR.SPRF flag remains 0, and the SPI does not copy the data in the shift register to the
receive buffer.
3. Because the receive buffer of SPDR_HA does not hold data that was received in the previous serial transfer, even
when a serial transfer ends, the SPSR.OVRF flag remains 0, and the data in the shift register is not copied to the
receive buffer.
In transmit-only mode (SPCR.TXMD = 1), the SPI transmits data but does not receive data. Therefore, the SPSR.SPRF
and SPSR.OVRF flags remain 0 at timings (1) to (3).
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32.3.7
32. Serial Peripheral Interface (SPI)
Transmit Buffer Empty and Receive Buffer Full Interrupts
Figure 32.30 and Figure 32.31 show operation examples of the transmit buffer empty interrupt (SPIn_SPTI) and the
receive buffer full interrupt (SPIn_SPRI). The register accesses shown in these figures indicate the conditions of access
to the SPDR_HA register, where W denotes a write cycle, and R denotes a read cycle. In Figure 32.26, the SPI performs
an 8-bit serial transfer when the SPCR.TXMD bit is 0, the SPDCR.SPFC[1:0] bits are 00b, the SPCMDm.CPHA bit is 0,
and the SPCMDm.CPOL bit is 0 for SPI0, and in which the SPCR.TXMD bit is 0, the SPCMD0.CPHA bit is 0, and the
SPCMD0.CPOL bit is 0 for SPI1.
In Figure 32.27, the SPI performs an 8-bit serial transfer when SPCR.TXMD bit is 0, the SPDCR.SPFC[1:0] bits are 00b,
the SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0 for SPI0, and in which the SPCR.TXMD bit is 0, the
SPCMD0.CPHA bit is 1, and the SPCMD0.CPOL bit is 0 for SPI1. The numbers for RSPCKn in the waveform represent
the number of RSPCK cycles, such as the number of transferred bits.
SPDR_HA access
W
RSPCKn
1
(CPHA = 0, CPOL = 0)
Transmit buffer state Empty Full
(1) (2)
SPIn_SPTI
W
2
3
Empty
4
R
5
6
7
Full
(3)
8
1
2
3
4
5
Empty
6
7
8
(4)
SPTEF
Receive buffer state
Empty
Full
Empty
(4)
Full
(5)
SPIn_SPRI
SPRF
Figure 32.30
Operation example of the SPIn_SPTI and SPIn_SPRI interrupts when CPHA = 0 and CPOL = 0
SPDR_HA access
W
W
RSPCKn
1
2
3
(CPHA = 1, CPOL = 0)
Transmit buffer state Empty Full
Empty
(1) (2)
SPIn_SPTI
4
R
5
6
7
Full
8
(3)
1
2
3
4
5
Empty
6
7
8
(4)
SPTEF
Receive buffer state
Empty
Full
(4)
Empty
Full
(5)
SPIn_SPRI
SPRF
Figure 32.31
Operation example of the SPIn_SPTI and SPIn_SPRI interrupts when CPHA = 1 and CPOL = 0
The operation of the SPI at timings (1) to (5) in the figure is as follows:
1. When transmit data is written to the SPDR_HA register with the transmit buffer of SPDR_HA empty and data for
the next transfer not set, the SPI writes data to the transmit buffer and clears the SPSR.SPTEF flag to 0.
2. If the shift register is empty, the SPI copies the data in the transmit buffer to the shift register, generates a transmit
buffer empty interrupt request (SPIn_SPTI), and sets the SPSR.SPTEF flag to 1. How a serial transfer is started
depends on the mode of the SPI. For details, see section 32.3.10, SPI Operation, and section 32.3.11, Clock
Synchronous Operation.
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32. Serial Peripheral Interface (SPI)
3. When transmit data is written to the SPDR_HA register either by the transmit buffer empty interrupt routine, or by
the processing of transmit buffer empty using the SPTEF flag, the SPI writes data to the transmit buffer and clears
the SPTEF flag to 0. Because the data being transferred serially is stored in the shift register, the SPI does not copy
the data in the transmit buffer to the shift register.
4. When the serial transfer ends with the receive buffer of SPDR_HA empty, the SPI copies the receive data in the
shift register to the receive buffer, generates a receive buffer full interrupt request (SPIn_SPRI), and sets the SPRF
flag to 1. Because the shift register is empty on completion of the serial transfer, if the transmit buffer was full
before the serial transfer ended, the SPI sets the SPTEF flag to 1 and copies the data in the transmit buffer to the
shift register. Even when received data is not copied from the shift register to the receive buffer in an overrun error
status, on completion of the serial transfer, the SPI determines that the shift register is empty, and data transfer from
the transmit buffer to the shift register is enabled.
5. When SPDR_HA is read either by the receive buffer full interrupt routine or by the processing of the receive buffer
full interrupt using the SPRF flag, the receive data can be read.
If SPDR_HA is written to when the transmit buffer holds untransmitted data (SPTEF flag is 0), the SPI does not update
the data in the transmit buffer. When writing to SPDR_HA, make sure to either use a transmit buffer empty interrupt
request or to process a transmit buffer empty interrupt using the SPTEF flag. To use a transmit buffer empty interrupt, set
the SPTIE bit in SPCR to 1. If the SPI function is disabled (the SPCR.SPE bit is 0), set the SPTIE bit to 0.
When serial transfer ends with the receive buffer full (SPRF = 1), the SPI does not copy data from the shift register to the
receive buffer, and detects an overrun error (see section 32.3.8, Error Detection). To prevent a receive data overrun error,
read the received data using a receive buffer full interrupt request before the next serial transfer ends. To use an SPI
receive buffer full interrupt, set the SPCR.SPRIE bit to 1.
Transmission and reception interrupts or the associated IELSRj.IR flags (where j is the interrupt vector number) in the
ICU can be used to confirm the states of the transmit and receive buffers. Similarly, the SPTEF and SPRF flags can be
used to confirm the states of the transmit and receive buffers. See section 14, Interrupt Controller Unit (ICU), for the
interrupt vector numbers.
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32.3.8
32. Serial Peripheral Interface (SPI)
Error Detection
In the normal SPI serial transfer, data written to the SPDR/SPDR_HA transmit buffer is transmitted, and the received
data can be read from the SPDR/SPDR_HA receive buffer. If access is made to SPDR/SPDR_HA, a non-normal transfer
might occur depending on the status of the transmit or receive buffer, or the status of the SPI at the beginning or end of
the serial transfer.
If a non-normal transfer occurs, the SPI detects the event as an underrun error, overrun error, parity error, or mode-fault
error. Table 32.8 shows the relationship between a non-normal transfer operation and the SPI error detection function.
Table 32.8
Operation
Relationship between non-normal transfer operations and SPI error detection function
Occurrence condition
SPI operation
Error detection
1
SPDR/SPDR_HA is written when the transmit
buffer is full
The contents of the transmit buffer are kept
Write data is missing.
None
2
SPDR/SPDR_HA is read when the receive buffer
is empty
The contents of the receive buffer and
previously received data are output
None
3
Serial transfer is started in slave mode when the
SPI is not able to transmit data
Serial transfer is suspended
Transmit or receive data is missing
Driving of the MISOA output signal is
stopped
SPI function is disabled.
Underrun error
4
Serial transfer terminates when the receive buffer
is full
The contents of the receive buffer are kept
Receive data is missing.
Overrun error
5
An incorrect parity bit is received during full-duplex
synchronous serial communications with the parity
function enabled
The parity error flag is asserted
Parity error
6
The SSLn0 input signal is asserted when the serial
transfer is idle in multi-master mode
Driving of the RSPCKn, MOSIn, SSLn1 to
SSLn3 output signals is stopped
SPI function is disabled.
Mode-fault error
7
The SSLn0 input signal is asserted during serial
transfer in multi-master mode
Serial transfer is suspended
Transmit or receive data is missing
Driving of the RSPCKn, MOSIn, SSLn1 to
SSLn3 output signals is stopped
SPI function is disabled.
Mode-fault error
8
The SSLn0 input signal is negated during serial
transfer in slave mode
Serial transfer is suspended
Missing transmit/receive data
Driving of the MISOn output signal is
stopped
SPI function is disabled.
Mode-fault error
In operation 1 described in Table 32.8, the SPI does not detect an error. To prevent data omission during writes to SPDR/
SPDR_HA, writes to SPDR/SPDR_HA must be executed using a transmit buffer empty interrupt request (when the
SPSR.SPTEF flag is 1).
Similarly, the SPI does not detect an error in operation 2. To prevent extraneous data from being read, SPDR/SPDR_HA
reads must be executed using a SPI receive buffer full interrupt request (when SPSR.SPRF flag is 1).
For information on the other errors, see the following sections:
Underrun errors, indicated in operation 3, see section 32.3.8.4, Underrun errors
Overrun errors, indicated in operation 4, see section 32.3.8.1, Overrun errors
Parity errors, indicated in operation 5, see section 32.3.8.2, Parity errors
Mode-fault errors, indicated in operations 6 to 8, see section 32.3.8.3, Mode-fault errors.
For the transmit and receive interrupts, see section 32.3.7, Transmit Buffer Empty and Receive Buffer Full Interrupts.
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32.3.8.1
32. Serial Peripheral Interface (SPI)
Overrun errors
If a serial transfer ends when the receive buffer of SPDR/SPDR_HA is full, the SPI detects an overrun error and sets the
SPSR.OVRF flag to 1. When the OVRF flag is 1, the SPI does not copy data from the shift register to the receive buffer,
so the data prior to the occurrence of the error is saved in the receive buffer. To set the OVRF flag to 0, write 0 to the
OVRF flag after the CPU reads SPSR with the OVRF flag set to 1.
Figure 32.32 shows an example operation of OVRF and SPRF flags. The SPSR and SPDR_HA accesses shown in Figure
32.32 indicate the condition of accesses to the SPSR and SPDR_HA respectively, where W denotes a write cycle, and R
denotes a read cycle. In Figure 32.32, the SPI performs an 8-bit serial transfer in which the SPCMDm.CPHA bit is 1 and
the SPCMDm.CPOL bit is 0. The numbers given for RSPCKn in the waveform represent the number of RSPCK cycles,
such as the number of transferred bits.
R
SPSR access
SPDR_HA access
RSPCKn
(CPHA = 1, CPOL = 0)
Receive buffer state
R
1
2
3
4
5
6
7
8
1
Figure 32.32
2
3
4
5
6
7
Full
8
Empty
SPRF
OVRF
W
(2)
(1)
(3)
(4)
Operation example of OVRF flag and SPRF flag
The operation of the flags at the timing shown in (1) to (4) in Figure 32.32 is as follows:
1. If a serial transfer terminates with the SPRF flag set to 1 (receive buffer full), the SPI detects an overrun error and
sets the OVRF flag to 1. The SPI does not copy the data in the shift register to the receive buffer. Even when the
SPPE bit is 1, parity errors are not detected. In master mode for SPI0, the SPI copies the value of the SPCMDm
pointer to the SPSSR.SPECM[2:0] bits.
2. When SPDR_HA is read, the SPI outputs the data in the receive buffer. The SPRF flag is then set to 0. The receive
buffer becoming empty does not set the OVRF flag to 0.
3. If the serial transfer ends with the OVRF flag set to 1 (an overrun error occurs), the SPI does not copy data in the
shift register to the receive buffer (the SPRF flag does not set to 1). A receive buffer full interrupt is not generated.
Even when the SPPE bit is 1, parity errors are not detected. When in master mode for SPI0, the SPI does not update
the SPSSR.SPECM[2:0] bits. When an overrun error occurs and the SPI does not copy the received data from the
shift register to the receive buffer, on termination of the serial transfer, the SPI determines that the shift register is
empty. This enables the data transfer from the transmit buffer to the shift register.
4. If 0 is written to the OVRF flag after SPSR is read when the OVRF flag is 1, the OVRF flag clears to 0.
The occurrence of an overrun can be checked either by reading SPSR or by using an SPI error interrupt and reading
SPSR. When executing a serial transfer, make sure that overrun errors are detected early, for instance, by reading SPSR
immediately after SPDR_HA is read. When the SPI is in master mode for SPI0, the value of the SPCMDm pointer on the
error occurrence can be checked by reading the SPSSR.SPECM[2:0] bits.
If an overrun error occurs and the OVRF flag is set to 1, normal reception operations cannot be performed until the
OVRF flag is cleared to 0.
When the RSPCK auto-stop function is enabled in master mode, an overrun error does not occur. Figure 32.33 and
Figure 32.34 show the clock stop waveform when a serial transfer continues while the receive buffer is full in master
mode.
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32. Serial Peripheral Interface (SPI)
Serial transfer
period
Start
Start
End
End
Serial transfer period
R
SPDR_HA access
RSPCK
cycle
1
2
3
4
5
6
7
RSPCK
cycle
8
1
2
3
4
5
6
RSPCKn
(CPOL = 0)
7
8
Clock is stopped
(2)
RSPCKn
(CPOL = 1)
Sampling timing
MOSIn
MISOn
SSLni
t2
t1
Receive buffer state
t3
t2
t1
Empty
Em
pty
Full
SPRF
(Receive Buffer Full Flag)
OVRF
Low
(Overrun Error Flag)
Receive
buffer read
(1)
Output: Undefined (0 or 1)
Input: Don’t care
SPI transfer format (CPHA = 1) t1: SPI Clock Delay Register (SPCKD)
t2: SPI Slave Select Negation Delay Register (SSLND)
t3: SPI Next-Access Delay Register (SPND)
Figure 32.33
Full
Clock stop waveform when serial transfer continues while receive buffer is full in master mode
with CPHA = 1
Start
Start
End
Serial transfer period
End
Serial transfer period
SPDR_HA access
R
RSPCK
cycle
1
2
3
4
5
6
7
RSPCK
cycle
8
1
2
3
RSPCKn
(CPOL = 0)
4
5
6
7
8
Clock is stopped
(2)
RSPCKn
(CPOL = 1)
Sampling timing
MOSIn
MISOn
SSLni
t2
t1
Receive buffer state
t3
t2
t1
Empty
Em
pty
Full
SPRF
(Receive Buffer Full Flag)
OVRF
Low
(Overrun Error Flag)
SPI transfer format (CPHA = 0) t1: SPI Clock Delay Register (SPCKD)
t2: SPI Slave Select Negation Delay Register (SSLND)
t3: SPI Next-Access Delay Register (SPND)
Figure 32.34
Full
Receive buffer
read
(1)
Output: Undefined (0 or 1)
Input: don’t care
Clock stop waveform when serial transfer continues while receive buffer is full in master mode
with CPHA = 0
The operation of the flags at the timings (1) and (2) in Figure 32.33 and Figure 32.34 is as follows:
1. When the receive buffer is full, an overrun error does not occur because the RSPCK clock is stopped.
2. If SPDR_HA is read while the clock is stopped, data in the receive buffer can be read. The RSPCK clock restarts
after reading the receive buffer (after the SPSR.SPRF flag clears to 0).
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32.3.8.2
32. Serial Peripheral Interface (SPI)
Parity errors
If full-duplex synchronous serial communication is performed with the SPCR.TXMD bit set to 0 and the SPCR2.SPPE
bit set to 1, the SPI checks for parity errors when serial transfer ends. On detecting a parity error in the received data, the
SPI sets the SPSR.PERF flag to 1. Because the SPI does not copy data in the shift register to the receive buffer when the
SPSR.OVRF flag is set to 1, parity error detection is not performed for the received data. To set the PERF flag to 0, write
0 to the PERF flag after the SPSR register is read with the PERF flag set to 1.
Figure 32.35 shows an example operation of the OVRF and PERF flags. In the SPSR access shown in Figure 32.35, W
denotes a write cycle, and R denotes a read cycle. In this example, full-duplex synchronous serial communication is
performed while the SPCR.TXMD bit is 0 and the SPCR2.SPPE bit is 1. The SPI performs an 8-bit serial transfer when
the SPCMDm.CPHA bit is 1 and the SPCMDm.CPOL bit is 0. The numbers given for RSPCKn in the waveform
represent the number of RSPCK cycles, such as the number of transferred bits.
SPSR access
RSPCKn
(CPHA = 1, CPOL = 0)
R
1 2
3
4
5
6
PERF
7
8
1 2
W
3
4
(1)
OVRF
Figure 32.35
5
6
7
8
(2)
(3)
Operation example of the PERF flag
The operation of the flags at the timings (1) to (3) in Figure 32.35 is as follows:
1. If a serial transfer terminates with the SPI not detecting an overrun error, the SPI copies the data in the shift register
to the receive buffer. The SPI checks the received data at this time and sets the PERF flag to 1 if a parity error is
detected. In master mode for SPI0, the SPI copies the value of the SPCMDm pointer to the SPSSR.SPECM[2:0]
bits.
2. If 0 is written to the PERF flag after the SPSR register is read when the PERF flag is 1, the PERF flag sets to 0.
3. When the SPI detects an overrun error and serial transfer is terminated, the data in the shift register is not copied to
the receive buffer. The SPI does not perform parity error detection at this time.
Parity errors can be checked for either by reading the SPSR register or using an SPI error interrupt and reading the SPSR
register. When executing a serial transfer, make sure that parity errors are detected early, for instance by reading SPSR
errors. When the SPI is in master mode for SPI0, the pointer value to the SPCMDm register at the error occurrence can
be checked by reading the SPSSR.SPECM[2:0] bits.
32.3.8.3
Mode-fault errors
The SPI operates in multi-master mode when the SPCR.MSTR bit is 1, the SPCR.SPMS bit is 0, and the
SPCR.MODFEN bit is 1. If an active level is input for the SSLn0 input signal of the SPI in multi-master mode, the SPI
detects a mode-fault error regardless of the status of the serial transfer, and sets the SPSR.MODF flag to 1. On detecting
the mode-fault error for SPI0, the SPI copies the value of the SPCMDm pointer to the SPSSR.SPECM[2:0] bits. The
active level of the SSLn0 signal is determined by the SSLP.SSL0P bit.
When the MSTR bit is 0, the SPI operates in slave mode. The SPI detects a mode-fault error if the MODFEN bit of the
SPI in slave mode is 1, and the SPMS bit is 0, and if the SSLn0 input signal is negated during the serial transfer period
(from the time the driving of valid data is started to the time the final valid data is fetched).
On detecting a mode-fault error, the SPI stops driving of the output signals and clears the SPCR.SPE bit to 0 (see section
32.3.9, Initializing the SPI). For multi-master configuration, detection of a mode-fault error is used to stop the driving of
output signals and the SPI function, which allows the master to be released.
The occurrence of a mode-fault error can be checked either by reading SPSR or by using an SPI error interrupt and
reading SPSR. Detecting mode-fault errors without using the SPI error interrupt requires polling of SPSR. When using
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32. Serial Peripheral Interface (SPI)
the SPI in master mode for SPI0, the value of the SPCMDm pointer at the error occurrence can be checked by reading the
SPSSR.SPECM[2:0] bits.
When the MODF flag is 1, writing 1 to the SPE bit is ignored by the SPI. To enable the SPI function after the detection of
a mode-fault error, the MODF flag must be set to 0.
32.3.8.4
Underrun errors
When the serial transfer begins with the SPCR.MSTR bit set to 0 (slave mode), the SPCR.SPE bit set to 1, and the
transmission data not prepared, the SPI detects an underrun error. Then, SPI sets the SPSR.MODF and SPSR.UDRF
flags to 1.
On detecting an underrun error, the SPI stops driving the output signals and clears the SPCR.SPE bit to 0 (see section
32.3.9, Initializing the SPI).
The occurrence of an underrun error can be checked either by reading the SPSR register or by using an SPI error interrupt
and reading the SPSR register. Detecting underrun errors without using the SPI error interrupt requires polling of SPSR.
When the MODF flag is 1, writing 1 to the SPE bit is ignored by the SPI. To enable the SPI function after the detection of
an underrun error, the MODF flag must be cleared to 0.
32.3.9
Initializing the SPI
If 0 is written to the SPCR.SPE bit or if the SPI sets the SPE bit to 0 because it detected a mode-fault error or an underrun
error, the SPI disables the SPI function and initializes some of the module functions. When a system reset is generated,
the SPI initializes all of the module functions. This section describes initialization by clearing the SPCR.SPE bit, and by
a system reset.
32.3.9.1
Initialization by clearing of the SPE bit
When the SPCR.SPE bit is set to 0, the SPI initializes by performing the following actions:
Suspending any serial transfer that is being executed
Stopping the driving of output signals (Hi-Z) in slave mode
Initializing the internal state of the SPI
Initializing the transmit buffer of the SPI (SPSR.SPTEF flag is set to 1).
Initialization by clearing of the SPE bit does not initialize the control bits of the SPI. For this reason, the SPI can be
started in the same transfer mode that is in use prior to initialization when the SPE bit is set to 1 again.
The SPRF, OVRF, MODF, PERF and UDRF flags in the SPSR register are not initialized, and the SPI Sequence Status
Register (SPSSR) is not initialized for SPI0. Therefore, even after the SPI is initialized, data from the receive buffer can
be read to check the error status during a SPI transfer.
The transmit buffer is initialized to an empty state (SPSR.SPTEF flag is set to 1). Therefore, if the SPCR.SPTIE bit is set
to 1 after SPI initialization, a transmit buffer empty interrupt is generated. When the SPI is initialized, to disable any
transmit buffer empty interrupts, write 0 to the SPTIE bit simultaneously while writing 0 to the SPE bit.
32.3.9.2
Initialization by system reset
A system reset completely initializes the SPI by initializing all bits that control the SPI, the status bits, and the data
registers, in addition to meeting the requirements described in section 32.3.9.1, Initialization by clearing of the SPE bit.
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32.3.10
32. Serial Peripheral Interface (SPI)
SPI Operation
32.3.10.1
Master mode operation
The only difference between single-master and multi-master mode operation is the use of mode-fault error detection (see
section 32.3.8, Error Detection). In single-master mode, the SPI does not detect mode-fault errors whereas in multimaster mode, it does. This section explains operations that are common to both single-master and multi-master modes.
(1)
Starting serial transfer
The SPI updates the data in the transmit buffer (SPTX) when data is written to the SPI Data Register (SPDR/SPDR_HA)
with the SPI transmit buffer empty, and data for the next transfer is not set (SPSR.SPTEF is 1). When the shift register is
empty after the number of frames set in the SPDCR.SPFC[1:0] bits are written to the SPDR/SPDR_HA for SPI0, and the
shift register is empty for SPI1, the SPI copies data from the transmit buffer to the shift register and starts serial transfer.
On copying transmit data to the shift register, the SPI changes the status of the shift register to full, and on termination of
serial transfer, it changes the status of the shift register to empty. The status of the shift register cannot be referenced.
The polarity of the SSLni output pins depends on the SSLP register settings. For details on the SPI transfer format, see
section 32.3.5, Transfer Formats.
(2)
Terminating serial transfer
Regardless of the SPCMDm.CPHA bit setting, the SPI terminates a serial transfer after transmitting an RSPCKn edge
associated with the final sampling timing. If free space is available in the receive buffer (SPRX) (SPSR.SPRF = 0), on
termination of serial transfer, the SPI copies data from the shift register to the receive buffer of the SPDR/SPDR_HA
register.
The final sampling timing varies depending on the bit length of transfer data. In master mode, the SPI data length
depends on the SPCMDm.SPB[3:0] bit setting. The polarity of the SSLni output pin depends on the SSLP register
settings. For details on the SPI transfer format, see section 32.3.5, Transfer Formats.
(3)
Sequence control
(a)
SPI0
The transfer format used in master mode is determined by the SPSCR, SPCMDm, SPBR, SPCKD, SSLND, and SPND
registers.
The SPSCR register determines the sequence configuration for serial transfers that the SPI executes in master mode. The
following items are set in the SPCMDm register:
SSLni pin output signal value
MSB- or LSB-first
Data length
Some of the bit rate settings
RSPCK polarity/phase
Whether SPCKD is to be referenced
Whether SSLND is to be referenced
Whether SPND is to be referenced.
The SPBR register holds some of the bit rate settings, including SPCKD (SPI clock delay), SSLND (SSL negation
delay), and SPND (next-access delay).
Based on the sequence length assigned in the SPSCR register, the SPI makes up a sequence comprised of a part or all of
the SPCMDm register. The SPI contains a pointer to the SPCMDm register that makes up the sequence. The value of this
pointer can be checked by reading the SPSSR.SPCP[2:0] bits. When the SPCR.SPE bit is set to 1 and the SPI function is
enabled, the SPI loads the pointer to the commands in the SPCMD0 register, and incorporates the SPCMD0 settings into
the transfer format at the beginning of serial transfer. The SPI increments the pointer each time the next-access delay
period for a data transfer ends. On completion of the serial transfer that corresponds to the final command in the
sequence, the SPI sets the pointer to SPCMD0 to execute the sequence repeatedly.
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Sequence length setting
32. Serial Peripheral Interface (SPI)
Determining reference command
Loading transfer format settings
SPSCR
Command pointer
control
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
SPCMD6
SPCMD7
CPHA
CPOL
BRDV[1:0]
SSLA[2:0]
SSLKP
SPB[3:0]
LSBF
SLNDEN
SCKDEN
SPCKD
SSLND
SPNDEN
SPND
Transfer format determiner
Figure 32.36
Procedure for determining serial transfer format in master mode (SPI0)
In this section, a frame is the combination of the SPDR/SPDR_HA data and the SPCMDm settings.
Data
(SPDR/SPDR_HA)
+
Frame
Data
Settings
Settings
(SPCMD)
Figure 32.37
Conceptual diagram of frames (SPI0)
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32. Serial Peripheral Interface (SPI)
Figure 32.38 shows the relationship between the commands and the transmit and receive buffers in the sequence of
operations specified by the settings in Table 32.4.
Setting 1-1
SPTX0/SPRX0
SPCMD0
Only 1 frame
Setting 1-2
SPTX0/SPRX0
SPCMD0
1st frame
SPTX0/SPRX0
Setting 1-3
SPCMD0
SPTX1/SPRX1
SPCMD0
2nd frame
SPTX1/SPRX1
SPCMD0
SPTX2/SPRX2
SPCMD0
1st frame
2nd frame
3rd frame
Setting 1-4
SPTX0/SPRX0
SPCMD0
SPTX1/SPRX1
SPCMD0
SPTX2/SPRX2
SPCMD0
SPTX3/SPRX3
SPCMD0
1st frame
2nd frame
3rd frame
4th frame
Setting 2-1
SPTX0/SPRX0
SPCMD0
SPTX1/SPRX1
SPCMD1
1st frame
2nd frame
Setting 2-2
SPTX0/SPRX0
SPCMD0
SPTX1/SPRX1
SPCMD1
SPTX2/SPRX2
SPCMD0
SPTX3/SPRX3
SPCMD1
1st frame
2nd frame
3rd frame
4th frame
Setting 3
SPTX0/SPRX0
SPCMD0
SPTX1/SPRX1
SPCMD1
SPTX2/SPRX2
SPCMD2
1st frame
2nd frame
3rd frame
Setting 4
SPTX0/SPRX0
SPCMD0
SPTX1/SPRX1
SPCMD1
SPTX2/SPRX2
SPCMD2
1st frame
2nd frame
3rd frame
4th frame
Setting 5
SPTX0/SPRX0
SPCMD0
SPTX0/SPRX0
SPCMD1
SPTX0/SPRX0
SPCMD2
SPTX0/SPRX0
SPCMD3
1st frame
2nd frame
3rd frame
4th frame
5th frame
Setting 6
SPTX0/SPRX0
SPCMD0
SPTX0/SPRX0
SPCMD1
SPTX0/SPRX0
SPCMD2
SPTX0/SPRX0
SPCMD3
SPTX0/SPRX0
SPCMD4
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
Setting 7
SPTX0/SPRX0
SPCMD0
SPTX0/SPRX0
SPCMD1
SPTX0/SPRX0
SPCMD2
SPTX0/SPRX0
SPCMD3
SPTX0/SPRX0
SPCMD4
SPTX0/SPRX0
SPCMD5
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
7th frame
Setting 8
SPTX0/SPRX0
SPCMD0
SPTX0/SPRX0
SPCMD1
SPTX0/SPRX0
SPCMD2
SPTX0/SPRX0
SPCMD3
SPTX0/SPRX0
SPCMD4
SPTX0/SPRX0
SPCMD5
SPTX0/SPRX0
SPCMD6
SPTX0/SPRX0
SPCMD7
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
7th frame
8th frame
Figure 32.38
(b)
SPTX3/SPRX3
SPCMD3
SPTX0/SPRX0
SPCMD4
SPTX0/SPRX0
SPCMD5
SPTX0/SPRX0
SPCMD6
Relationship between SPI Command Register (SPCMDm) and transmit and receive buffers in
sequence operations (SPI0)
SPI1
The transfer format in master mode is determined by the SPSCR, SPCMD0, SPBR, SPCKD, SSLND, and SPND
registers.
The SPSCR register determines the sequence configuration for serial transfers that are executed by the SPI in master
mode. The following parameters set in the SPCMD0 register:
SSLni pin output signal value
MSB- or LSB-first
Data length
Some of the bit rate settings
RSPCK polarity/phase
Whether SPCKD is to be referenced
Whether SSLND is to be referenced
Whether SPND is to be referenced.
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32. Serial Peripheral Interface (SPI)
The SPBR register holds some of the bit rate settings such as the SPI clock delay value (SPCKD), the SSL negation delay
(SSLND), and the next-access delay value (SPND).
When the SPI function is enabled (SPCR.SPE = 1), the SPI loads the pointer to the commands in SPCMD0 and
incorporates the SPCMD0 settings into the transfer format at the beginning of serial transfer.
Reference command
SPCMD0
Loading transfer format settings
SLNDEN
SPNDEN
SCKDEN
SSLND
SPND
SPCKD
CPHA
CPOL
BRDV[1:0]
SSLA[2:0]
SPB[3:0]
LSBF
Transfer format determiner
Figure 32.39
Procedure for determining form of serial transfer in master mode (SPI1)
In this section, a frame is the combination of the SPDR/SPDR_HA data and the SPCMD0 settings.
Data
(SPDR/
SPDR_HA)
Frame
Data
Settings
+
Settings
(SPCMD)
Figure 32.40
Conceptual diagram of frames (SPI1)
Figure 32.41 shows the relationship between the command and the transmit and receive buffers in the sequence of
operations.
SPTX0/SPRX0
SPCMD0
Only 1 frame
Figure 32.41
(4)
Relationship between the SPI Command Register and the transmit and receive buffers in
sequence operations (SPI1)
Burst transfer
SPI0
If the SPCMDm.SSLKP bit that the SPI references during the current serial transfer is 1, the SPI maintains the SSLni
signal level during the serial transfer until the beginning of the SSLni signal assertion for the next serial transfer. If the
SSLni signal level for the next serial transfer is the same as the SSLni signal level for the current serial transfer, the SPI
can execute continuous serial transfers while keeping the SSLni signal assertion status (burst transfer).
Figure 32.42 shows an example of an SSLni signal operation for a burst transfer that is implemented using the SPCMD0
and SPCMD1 register settings. This section explains the SPI operations (1) to (7) as shown in Figure 32.42.
Note:
The polarity of the SSLni output signal depends on the SSLP register settings.
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32. Serial Peripheral Interface (SPI)
RSPCKn
(CPHA = 1, CPOL = 0)
SSLni
(1)
Figure 32.42
(2)
(3) (4) (5)
(6)
(7)
Example of burst transfer operation using the SSLKP bit (SPI0)
1. Based on the SPCMD0 settings, the SPI asserts the SSLni signal and inserts RSPCK delays.
2. The SPI executes serial transfers according to the SPCMD0 settings.
3. The SPI inserts SSL negation delays.
4. Because the SPCMD0.SSLKP bit is 1, the SPI keeps the SSLni signal value specified in SPCMD0. This period is
sustained at a minimum for a period equal to the next-access delay in SPCMD0. If the shift register is empty after
the minimum period has passed, this period is sustained until the transmit data is stored in the shift register for the
next transfer.
5. Based on the SPCMD1 settings, the SPI asserts the SSLni signal and inserts RSPCK delays.
6. The SPI executes serial transfers according to the SPCMD1 settings.
7. Because the SPCMD1.SSLKP bit is 0, the SPI negates the SSLni signal. In addition, a next-access delay is inserted
according to SPCMD1.
If the SSLni signal output settings in the SPCMDm register, where 1 is assigned to the SSLKP bit, are different from the
SSLni signal output settings in the SPCMDm register to be used in the next transfer, the SPI switches the SSLni signal
status to SSLni signal assertion as shown in (5) in Figure 32.42. This corresponds to the command for the next transfer.
Note:
If such an SSLni signal switching occurs, the slaves that drive the MISOn signal compete, and collision of signal
levels might occur.
In master mode, the SPI references the SSLni signal operation within the module when the SSLKP bit is not used. Even
when the SPCMDm.CPHA bit is 0, the SPI can accurately start serial transfers using the SSLni signal assertion for the
next transfer that is detected internally.
SPI1
SPI does not support continuous serial transfer (burst transfer), keeping the SSL signal asserted. However, burst transfer
can be implemented by controlling the SSL signal output in general-purpose ports.
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(5)
32. Serial Peripheral Interface (SPI)
RSPCK delay (t1)
The RSPCK delay value of the SPI in master mode depends on the SPCMDm.SCKDEN bit setting and the SPCKD
register setting. For SPI0, the SPI determines the SPCMDm register to be referenced by pointer control during a serial
transfer, and determines an RSPCK delay using the SPCMDm.SCKDEN bit and SPCKD, as listed in Table 32.9. For
SPI1, the SPI determines an RSPCK delay using the SPCMD0.SCKDEN bit and SPCKD, as listed in Table 32.9. For a
definition of RSPCK delay, see section 32.3.5, Transfer Formats.
Table 32.9
Relationship between the SCKDEN bit, SPCKD, and RSPCK delay
SPCMDm.SCKDEN bit
SPCKD.SCKDL[2:0] bits
RSPCK delay
0
000b to 111b
1 RSPCK
1
000b
1 RSPCK
001b
2 RSPCK
010b
3 RSPCK
011b
4 RSPCK
100b
5 RSPCK
101b
6 RSPCK
(6)
110b
7 RSPCK
111b
8 RSPCK
SSL negation delay (t2)
The SSL negation delay value of the SPI in master mode depends on the SPCMDm.SLNDEN bit setting and the SSLND
register setting. For SPI0, the SPI determines the SPCMDm register to be referenced by pointer control during serial
transfer, and determines an SSL negation delay using the SPCMDm.SLNDEN bit and SSLND, as listed in Table 32.10.
For SPI1, the SPI determines an SSL negation delay using the SPCMD0.SLNDEN bit and SSLND, as listed in Table
32.10. For a definition of SSL negation delay, see section 32.3.5, Transfer Formats.
Table 32.10
Relationship between the SLNDEN bit, SSLND, and SSL negation delay
SPCMDm.SLNDEN bit
SSLND.SLNDL[2:0] bits
SSL negation delay
0
000b to 111b
1 RSPCK
1
000b
1 RSPCK
001b
2 RSPCK
010b
3 RSPCK
011b
4 RSPCK
100b
5 RSPCK
101b
6 RSPCK
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7 RSPCK
111b
8 RSPCK
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(7)
32. Serial Peripheral Interface (SPI)
Next-access delay (t3)
The next-access delay value of the SPI in master mode depends on the SPCMDm.SPNDEN bit setting and the SPND
setting. For SPI0, the SPI determines the SPCMDm register to be referenced by pointer control during serial transfer, and
determines a next-access delay during serial transfer by using the SPCMDm.SPNDEN bit and SPND, as listed in Table
32.11. For SPI1, the SPI determines a next-access delay during serial transfer using the SPCMD0.SPNDEN bit and
SPND, as listed in Table 32.11. For a definition of next-access delay, see section 32.3.5, Transfer Formats.
Table 32.11
Relationship between SPNDEN bit, SPND, and next-access delay
SPCMDm.SPNDEN bit
SPND.SPNDL[2:0] bits
Next-access delay
0
000b to 111b
1 RSPCK + 2 PCLK
1
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000b
1 RSPCK + 2 PCLK
001b
2 RSPCK + 2 PCLK
010b
3 RSPCK + 2 PCLK
011b
4 RSPCK + 2 PCLK
100b
5 RSPCK + 2 PCLK
101b
6 RSPCK + 2 PCLK
110b
7 RSPCK + 2 PCLK
111b
8 RSPCK + 2 PCLK
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(8)
32. Serial Peripheral Interface (SPI)
Initialization flow
Figure 32.43 shows an example of SPI initialization flow when the SPI is in master mode. For information on how to set
up the ICU, DMAC, and I/O ports, see the descriptions given in the individual blocks.
Start of initialization in
master mode
Set SPI Slave Select Polarity
Register (SSLP)
• Sets polarity of SSL signal.
Set SPI Pin Control Register
(SPPCR)
• Sets output mode (CMOS/open-drain).
• Sets MOSI signal value when transfer is in idle state.
Set SPI Bit Rate Register (SPBR)
• Sets transfer bit rate.
Set SPI Data Control Register
(SPDCR)
• Sets number of frames to be used for SPI0.
Set SPI Clock Delay Register
(SPCKD)
• Sets RSPCK delay value.
Set SPI Slave Select Negation
Delay Register (SSLND)
• Sets SSL negation delay value.
Set SPI Next-access Delay Register
(SPND)
• Sets next-access delay value.
Set SPI Control Register 2 (SPCR2)
• Sets parity function.
• Sets interrupt mask.
SPI Sequence Control Register*1
(SPSCR)
Set SPI Command Registers
(SPCMDm)
(m = 0 to 7 for SPI0; m = 0 for SPI1)
• Sets sequence length.
• Sets SSL signal level for SCI0.
• Sets RSPCK delay enable.
• Sets SSL negation delay enable.
• Sets next-access delay enable.
• Sets MSB or LSB first.
• Sets data length.
• Sets transfer bit rate.
• Sets clock phase.
• Sets clock polarity.
• Sets SSL assertion signal.
Set interrupt controller
(when using an interrupt)
Set DMAC
(when using the DMAC)
Set I/O ports
Set SPI Control Register (SPCR)
• Sets master mode.
• Sets interrupt mask.
• Sets SPI mode.
Read SPI Control Register (SPCR)
End of initialization in
master mode
Note 1.
Figure 32.43
SPI0 only
Example of initialization flow in master mode for SPI operation
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32. Serial Peripheral Interface (SPI)
Software processing flow
Figure 32.44 to Figure 32.46 show examples of the software processing flow.
(a)
Transmit processing flow
When transmitting data, with the SPIn_SPII interrupt enabled, the CPU is notified of the completion of data transmission
after the last data write for transmission.
Processing for transmission
Start processing
for transmission
Pre-transfer processing
End of initial settings
Clear the SPSR.MODF, OVRF,
PERF, and UDRF flags
[1] Clear error sources.
Transmit buffer empty
interrupt (SPIn_SPTI)?
or
*1
SPSR.SPTEF = 1?
No
Yes
[2] Disable idle interrupts.
Set SPCR2.SPIIE = 0
Set SPCR.SPE = 1
Set SPTIE, SPRIE and SPEIE
Proceed to
processing for
transmission
[3] Set the SPE bit to “enabled”.
Enable the required interrupts at the
same time.
Using the interrupt is prohibited if
the user uses the flag for polling.
Proceed to
processing for
reception
Proceed to
error
processing
Write data for transmission to
SPDR/SPDR_HA
Have the last of the
data been written?
[4] [4] Access when the interrupt
handling routine is executed once
is to the number of frames set in
No
SPDCR.SPFC[1:0] for SPI0.
Yes
SPCR.SPTIE = 0,
SPCR2.SPIIE
=1
Yes
or
SPCR.SPTIE = 0,
*2
SPCR2.SPIIE = 0
SPIn_SPII
or
*3
SPSR.IDLNF = 0?
No
Yes
SPCR.SPE = 0,
SPCR2.SPIIE = 0
End of
processing for
transmission
Note 1.
Note 2.
Note 3.
Before writing data for transmission to SPDR/SPDR_HA, check that the transmit buffer is empty by reading the SPSR.SPTEF flag, if the
flag for polling is used.
Setting the idle interrupt is prohibited (SPCR2.SPIIE = 0) if the flag for polling is used.
Wait more than 1 PCLK after writing data for transmission to SPDE and before starting to poll PSR.IDLNF if the flag for polling is used.
Figure 32.44
Transmission flow in master mode transmission
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(b)
32. Serial Peripheral Interface (SPI)
Receive processing flow
The SPI does not handle receive-only operations, so processing for transmission is required.
Pre-transfer processing
Processing for reception
Start
processing for
reception
End of initial
settings
Clear the SPSR.MODF,
OVRF, PERF, and UDRF flags
Set SPCR2.SPIIE = 0
[2] Disable idle interrupts.
Set SPCR.SPE = 1.
Set SPTIE, SPRIE and SPEIE.
Proceed to
processing for
transmission
[1] Clear error sources.
[3] Set the SPE bit to enabled.
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the user uses the flag for polling.
Proceed to
processing
for reception
Proceed to
error
processing
Receive buffer
No
full interrupt (SPIn_SPRI)
or
SPSR.SPRF = 1?
Yes
Read receive data from
SPDR/SPDR_HA
Have the last of the
data been read?
[4]
[4] Access when the routine is
executed once is to the number of
frames set in SPDCR.SPFC[1:0]
for SPI0.
No
Yes
SPCR.SPRIE = 0
End of
processing for
reception
Figure 32.45
(c)
[5] Prohibition of operation is handled
by processing for transmission.
Reception flow in master mode
Error processing flow
The SPI detects mode-fault errors, underrun errors, overrun errors, and parity errors. When a mode-fault error is
generated, the SPCR.SPE bit is automatically cleared, stopping operations for transmission and reception. For errors
from other sources, the SPCR.SPE bit is not cleared and operations for transmission and reception continue. Therefore,
Renesas recommends clearing the SPCR.SPE bit to stop operations for errors other than mode-fault errors. Not doing so
leads to updating of the SPSSR.SPECM[2:0] bits for SPI0.
When an error is detected by using an interrupt, clear the ICU.IELSRj.IR flag in the error processing routine. If this is not
done, the ICU.IELSRj.IR flag might continue to indicate a transmit buffer empty or a receive buffer full interrupt
request. If an SPIn_SPRI interrupt request is indicated, read the receive buffer and initialize the sequencer in the SPI.
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32. Serial Peripheral Interface (SPI)
Error processing
Start error
processing
Pre-transfer processing
End of initial
settings
Clear the SPSR.MODF,
OVRF, PERF, and UDRF flags
[1] Clear error sources.
Error interrupt (SPIn_SPEI)
or
SPSR.MODF/OVRF/PERF/UDRF
= 1?
No
Yes
Set SPCR2.SPIIE = 0
[2] Disable idle interrupts.
Set SPCR.SPE = 1
Set SPTIE, SPRIE and SPEIE
Proceed to
processing for
transmission
[3] Set the SPE bit to “enabled”.
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the user uses the flag for polling.
Proceed to
processing
for reception
Proceed to
error
processing
SPSR.MODF = 0
No
Yes
SSLn0 = inactive?
SPCR.SPE = 0
[4]
[4] Read the port register and
confirm that the SSLn0 pin is at
the inactive level.
Set SPCR.SPTIE = 0,
SPRIE = 0, SPEIE = 0,
and SPCR2.SPIIE = 0
Error processing
No
[5]
[5] Clear the ICU.IELSRj.IR flag
corresponding to SPIn_SPTI,
SPIn_SPRI, and so on.
Clear the SPSR.MODF, OVRF,
PERF, and UDRF flags
Repeat the transfer
processing
End of error
processing
Figure 32.46
[6] Run the initialization processing
again.
Processing order can be changed.
Error processing flow in master mode
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32.3.10.2
(1)
32. Serial Peripheral Interface (SPI)
Slave mode operation
Starting serial transfer
When the SPCMD0.CPHA bit is 0, if the SPI detects an SSLn0 input signal assertion, it must drive valid data to the
MISOn output signal. For this reason, when the CPHA bit is 0, the assertion of the SSLn0 input signal triggers the start of
a serial transfer.
When the CPHA bit is 1, if the SPI detects the first RSPCKn edge in an SSLn0 signal asserted condition, it must drive
valid data to the MISOn output signal. For this reason, when the CPHA bit is 1, the first RSPCKn edge in an SSLn0
signal asserted condition triggers the start of a serial transfer.
Regardless of the CPHA bit setting, the SPI drives the MISOn output signal on SSLn0 signal assertion. The data that is
output by the SPI is either valid or invalid, depending on the CPHA bit setting.
The polarity of the SSLn0 input signal depends on the setting of the SSLP.SSL0P bit. For details on the SPI transfer
format, see section 32.3.5, Transfer Formats.
(2)
Terminating serial transfer
Regardless of the SPCMD0.CPHA bit setting, the SPI terminates the serial transfer after detecting an RSPCKn edge
associated with the final sampling timing. When free space is available in the receive buffer (the SPSR.SPRF flag is 0),
on termination of serial transfer, the SPI copies received data from the shift register to the receive buffer of the SPDR/
SPDR_HA register. On termination of a serial transfer, the SPI changes the status of the shift register to empty, regardless
of the receive buffer state. A mode-fault error occurs if the SPI detects an SSLn0 input signal negation from the
beginning of the serial transfer to the end of the serial transfer (see section 32.3.8, Error Detection).
The final sampling timing changes depending on the bit length of the transfer data. In slave mode, the SPI data length is
determined by the SPCMD0.SPB[3:0] bit setting. The polarity of the SSLn0 input signal is determined by the
SSLP.SSL0P bit setting. For details on the SPI transfer format, see section 32.3.5, Transfer Formats.
(3)
Notes on single-slave operations
If the SPCMD0.CPHA bit is 0, the SPI starts serial transfers when it detects the assertion edge for an SSLn0 input signal.
In the configuration example shown in Figure 32.10, if the SPI is in single-slave mode, the SSLn0 signal is fixed at an
active state. Therefore, when the CPHA bit is set to 0, the SPI cannot correctly start a serial transfer. For the SPI to
correctly execute transmit and receive operations in slave mode when the SSLn0 input signal is fixed at an active state,
the CPHA bit must be set to 1. Do not fix the SSLn0 input signal if there is a requirement for setting the CPHA bit to 0.
(4)
Burst transfer
If the SPCMD0.CPHA bit is 1, continuous serial transfer (burst transfer) can be executed while retaining the assertion
state for the SSLn0 input signal. If the CPHA bit is 1, the serial transfer period is the period from the first RSPCKn edge
to the sampling timing for the reception of the final bit in an SSLn0 signal active state. Even when the SSLn0 input signal
remains at an active level, the SPI can accommodate burst transfers because it can detect the start of an access.
When the CPHA bit is 0, the second and subsequent serial transfers during burst transfer cannot be executed correctly.
Burst transfer cannot be executed for SPI1.
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32. Serial Peripheral Interface (SPI)
Initialization flow
Figure 32.47 shows an example of initialization flow for SPI operation where the SPI is in slave mode. For information
on how to set up the ICU, DMAC, and I/O ports, see the descriptions given in the individual blocks.
Start of initialization in
slave mode
Set SPI Slave Select Polarity
Register (SSLP)
Set SPI Data Control
Register (SPDCR)
Set SPI Control Register 2 (SPCR2)
Set SPI Command Register 0
(SPCMD0)
• Sets polarity of SSLn0 input signal
• Sets number of frames to be used for SPI0
• Sets parity function
• Sets interrupt mask.
• Sets MSB or LSB first
• Sets data length
• Sets clock phase
• Sets clock polarity.
Set interrupt controller
(when using an interrupt)
Set DMAC
(when using the DMAC)
Set I/O ports
Set SPI Control Register
(SPCR)
• Sets slave mode
• Sets mode fault error detection
• Sets interrupt mask
• Sets SPI mode.
Read SPI Control Register (SPCR)
End of initialization in
slave mode
Figure 32.47
Example initialization flow in slave mode for SPI operation
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32. Serial Peripheral Interface (SPI)
Software processing flow
Figure 32.48 to Figure 32.50 show examples of the software processing flow.
(a)
Transmit processing flow
Pre-transfer processing
Processing for transmission
Start processing
for transmission
End of initial
settings
Clear the SPSR.MODF, OVRF,
UDRF, and PERF flags
[1] Clear error sources.
Transmit buffer empty
interrupt (SPIn_SPTI)
or
SPSR.SPTEF = 1? *1
[2] Disable idle interrupts.
Set SPCR2.SPIIE = 0
Set SPCR.SPE = 1
Set SPTIE, SPRIE and SPEIE
[3] Set the SPE bit to enabled.
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the user uses the flag for polling.
Yes
Write data for transmission
to SPDR/SPDR_HA
Have the last of the
data been written?
Proceed to
processing for
transmission
No
Proceed to
processing for
reception
Proceed to
error
processing
[4]
[4] Access when the routine is
executed once is to the number of
frames set in SPDCR.SPFC[1:0]
for SPI0.
No
Yes
End of processing
for transmission
Note 1.
Proceed to processing writing data for transmission to SPDR/SPDR_HA after checking that the transmit buffer is empty by reading
SPSR.SPTEF flag, if the flag for polling is used.
Figure 32.48
(b)
Transmission flow in slave mode
Receive processing flow
The SPI does not handle receive-only operation, so processing for transmission is required.
Pre-transfer processing
Processing for reception
Start processing
for reception
End of initial
settings
Clear the SPSR.MODF, OVRF,
UDRF, and PERF flags
Set SPCR2.SPIIE = 0
[2] Disable idle interrupts.
Set SPCR.SPE = 1.
Set SPTIE, SPRIE and SPEIE.
Proceed to
processing for
transmission
[1] Clear error sources.
[3] Set the SPE bit to “enabled”.
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the user uses the flag for polling.
Proceed to
processing for
reception
Receive buffer full
interrupt (SPIn_SPRI)
or
SPSR.SPRF = 1?
No
Yes
Read receive data from
SPDR/SPDR_HA
[4]
Have the last of the
data been read?
No
[4] Access when the routine is
executed once is to the number of
frames set in SPDCR.SPFC[1:0] for SPI0.
Yes
Proceed to error
processing
SPCR.SPRIE = 0
End of processing
for reception
Figure 32.49
Reception flow in slave mode
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(c)
32. Serial Peripheral Interface (SPI)
Error processing flow
In slave operation, even when a mode-fault error is generated, the SPSR.MODF flag can be cleared regardless of the
state of the SSLn0 pin.
When an error is detected using an interrupt, clear the ICU.IELSRj.IR flag in the error processing routine. If this is not
done, the ICU.IELSRj.IR flag might continue to indicate a transmit buffer empty or receive buffer full interrupt request.
If a receive buffer full request is indicated, read the receive buffer and initialize the sequencer in the SPI.
Error processing
Start error
processing
Pre-transfer processing
End of initial
settings
Clear the SPSR.MODF, OVRF,
UDRF, and PERF flags
[1] Clear error sources.
Error interrupt
(SPIn_SPEI)
or
SPSR.MODF/OVRF/PERF
= 1?
No
Yes
Set SPCR2.SPIIE = 0
[2] Disable idle interrupts.
Set SPCR.SPE = 1.
Set SPTIE, SPRIE and SPEIE.
Proceed to
processing for
transmission
[3] Set the SPE bit to enabled.
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the user uses the flag for polling.
Proceed to
processing for
reception
Proceed to error
processing
SPSR.MODF = 0
No
Yes
SPCR.SPE = 0
Set SPCR.SPTIE = 0,
SPRIE = 0, SPEIE = 0,
and SPCR2.SPIIE = 0
Error processing
[4]
[4] Clear the ICU.IELSRj.IR flag
corresponding to SPIn_SPTI,
SPIn_SPRI, and so on.
Clear the SPSR.MODF, UDRF,
OVRF, and PERF flags
Repeat the trans
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