User’s Manual
Cover
S5D5 Microcontroller Group
User’s Manual
Renesas Synergy™ Platform
Synergy Microcontrollers
S5 Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.30 Aug 2019
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorporation or any
other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims
any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits,
software, or information.
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involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas
Electronics products or technical information described in this document, including but not limited to, the product data,
drawings, charts, programs, algorithms, and application examples.
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(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be
used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for
printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a
finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from
the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product
that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the
power reaches the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes
in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during
power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input
pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit
state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows
internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is
generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only
released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an
external resonator or by an external oscillator while program execution is in progress, wait until the target clock
signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take
care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition
period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating
margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number,
implement a system-evaluation test for the given product.
Preface
1.
About this Document
This manual describes the functions and electrical characteristics of the Renesas Synergy™ Microcontroller.
This manual is generally organized into an overview of the product, descriptions of the CPU, system control functions,
peripheral functions, electrical characteristics, and usage notes. This manual describes the product specification of the
microcontroller (MCU) superset. Depending on your product, some pins, registers, or functions might not exist. Address
space that store unavailable registers are reserved.
2.
Audience
This manual is written for system designers who are designing and programming applications using the Renesas Synergy
Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU.
3.
Renesas Publications
Renesas provides the following documents for the Renesas Synergy Microcontroller. Before using any of these
documents, visit renesassynergy.com/docs for the most up-to-date version of the document.
Component
Microcontrollers
Software
Tools & Kits,
Solutions
Document type
Description
Datasheet
Features, overview, and electrical characteristics of the MCU
User’s Manual: Microcontrollers
MCU specifications such as pin assignments, memory maps, peripheral
functions, electrical characteristics, timing diagrams, and operation
descriptions
Application Notes
Technical notes, board design guidelines, and software migration information
Technical Update (TU)
Preliminary reports on product specifications such as restriction and errata
Datasheet
Functional descriptions and specific performance data for software modules
that are included in Renesas Synergy Software Package (SSP)
User’s Manual: Software
API reference including SSP architecture and programming information
Application Notes
Project files, guidelines for software programming, and application examples
to develop embedded software applications
User’s Manual: Development Tools
User’s manual and quick start guide for developing embedded software
applications with Development Kit (DK), Starter Kit (SK), Promotion Kit (PK),
Target Board Kit (TB), Product Examples (PE), and Application Examples (AE)
User’s Manual: Software
Quick Start Guide
Application Notes
Project files, guidelines for software programming, and application examples
to develop embedded software applications
4.
Numbering Notation
The following numbering notation is used throughout this manual:
Example
Description
011b
Binary number. For example, the binary equivalent of the number 3 is 011b.
1Fh
Hexadecimal number. For example, the hexadecimal equivalent of the number 31 is described 1Fh. In
some cases, a hexadecimal number is shown with the prefix 0x, based on C/C++ formatting.
1234
Decimal number. Decimal numbers are generally shown without a suffix.
5.
Typographic Notation
The following typographic notation is used throughout this manual:
Example
Description
ICU.NMICR.NMIMD
Periods separate a function module symbol (ICU), register symbol (NMICR), and bit field symbol
(NMIMD)
ICU.NMICR
A period separates a function module symbol (ICU) and register symbol (NMICR)
NMICR.NMIMD
A period separates a register symbol (NMICR) and bit field symbol (NMIMD)
NFCLKSEL[1:0]
In a register bit name, the bit range enclosed in square brackets indicates the number of bits in the field
at this location. In this example, NFCLKSEL[1:0] represents a 2-bit field at the specified location in the
NMI Pin Interrupt Control Register (NMICR).
6.
Unit Prefix
The following unit prefixes are sometimes misleading. Those unit prefixes are described throughout this manual with the
following meaning:
Prefix
Description
b
Bit
B
Byte. This unit prefix is generally used for memory specification of the MCU and address space.
k
1000 = 103. k is also used to denote 1024 (210) but this unit prefix is used to denote 1000 (103)
throughout this manual.
K
1024 = 210. This unit prefix is used to denote 1024 (210) not 1000 (103) throughout this manual.
7.
Special Terms
The following terms have special meanings:
Term
Description
NC
Not connected pin. NC means the pin is not connected to the MCU.
Hi-Z
High impedance
8.
Register Description
Each register description includes both a register diagram that shows the bit assignments and a register bit table that
describes the content of each bit. The example of symbols used in these tables are described in the sections that follow.
The following is an example of a register description and associated bit field definition.
X.X.X
NMI Pin Interrupt Control Register (NMICR)
Address(es):
Value after reset:
(1)
ICU.NMICR 4000 6100h
b7
b6
NFLTE
N
—
0
0
b5
b4
NFCLKSEL[1:0]
0
0
b3
b2
b1
b0
—
—
—
NMIMD
0
0
0
0
(4)
(2)
(3)
(6)
(5)
Bit
Symbol
Bit name
Description
R/W
b0
NMIMD
NMI Detection Set
0: Falling edge
1: Rising edge.
R/W
b3 to b1 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5, b4
NFCLKSEL[1:0]
NMI Digital Filter Sampling Clock
Select
b5 b4
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
NFLTEN
NMI Digital Filter Enable
0: Disable the digital filter
1: Enable the digital filter.
R/W
0
0
1
1
0: PCLKB
1: PCLKB/8
0: PCLKB/32
1: PCLKB/64.
(1) Function module symbol, register symbol, and address assignment
Function module symbol, register symbol, and address assignment of this register are generally expressed. ICU.NMICR
4000 6100h means NMI Pin Interrupt Control Register (NMICR) of Interrupt Controller Unit (ICU) is assigned to
address 4000 6100h.
(2) Bit number
This number indicates the bit number. These bits are shown in order from b31 to b0 for a 32-bit register, from b15 to b0
for a 16-bit register, and from b7 to b0 for an 8-bit register.
(3) Value after reset
This symbol or number indicates the value of each bit after a reset. The value is shown in binary unless specified
otherwise.
0: Indicates that the value is 0 after a reset.
1: Indicates that the value is 1 after a reset.
x: Indicates that the value is undefined after a reset.
(4) Bit symbol
Bit symbol indicates the short name of the bit field. Reserved bit is expressed with a —.
(5) Bit name
Bit name indicates the full name of the bit field.
(6) R/W
The R/W column indicates access type: whether the bit field is read or write.
R/W: The bit field is read and write.
R/(W): The bit field is read and write. But writing to this bit field has some limitations. For details on the limitations,
see the description or notes of respective registers.
R: The bit field is read-only. Writing to this bit field has no effect.
W: The bit field is write-only. The read value is undefined.
9.
Abbreviations
Abbreviations used in this manual are shown in the following table:
Abbreviation
AES
Description
Advanced Encryption Standard
AHB
Advanced High-Performance Bus
AHB-AP
AHB Access Port
APB
Advanced Peripheral Bus
ARC
Alleged RC
ATB
Advanced Trace Bus
BCD
Binary Coded Decimal
BSDL
Boundary Scan Description Language
DES
Data Encryption Standard
DSA
Digital Signature Algorithm
ECC
Elliptic Curve Cryptography
ETB
Embedded Trace Buffer
ETM
Embedded Trace Macrocell
FLL
Frequency Locked Loop
FPU
Floating-Point Unit
GSM
Global System for Mobile communications
HMI
Human Machine Interface
IrDA
Infrared Data Association
LSB
Least Significant Bit
MSB
Most Significant Bit
NVIC
Nested Vector Interrupt Controller
PC
Program Counter
PFS
Port Function Select
PLL
Phase Locked Loop
POR
Power-On Reset
PWM
Pulse Width Modulation
RSA
Rivest Shamir Adleman
SHA
Secure Hash Algorithm
S/H
Sample and Hold
SP
Stack Pointer
SWD
Serial Wire Debug
SW-DP
Serial Wire-Debug Port
TRNG
True Random Number Generator
UART
Universal Asynchronous Receiver/Transmitter
10. Proprietary Notice
All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained
in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and
trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein,
no part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded,
translated, transmitted or distributed in any other medium for publication or distribution or for any commercial
enterprise, without prior written consent from Renesas.
Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.
CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium.
Magic Packet™ is a trademark of Advanced Micro Devices, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective
holders.
11. Website and Support
Visit the following vanity URLs to learn about key elements of the Synergy Platform, download components and related
documentation, and get support.
Synergy Software
www.renesas.com/synergy/software
Synergy Software Package
www.renesas.com/synergy/ssp
Software add-ons
www.renesas.com/synergy/addons
Software glossary
www.renesas.com/synergy/softwareglossary
Development tools
www.renesas.com/synergy/tools
Synergy Hardware
www.renesas.com/synergy/hardware
Microcontrollers
www.renesas.com/synergy/mcus
MCU glossary
www.renesas.com/synergy/mcuglossary
Parametric search
www.renesas.com/synergy/parametric
Kits
www.renesas.com/synergy/kits
Synergy Solutions Gallery
www.renesas.com/synergy/solutionsgallery
Partner projects
www.renesas.com/synergy/partnerprojects
Application projects
www.renesas.com/synergy/applicationprojects
Self-service support resources:
Documentation
www.renesas.com/synergy/docs
Knowledgebase
www.renesas.com/synergy/knowledgebase
Forums
www.renesas.com/synergy/forum
Training
www.renesas.com/synergy/training
Videos
www.renesas.com/synergy/videos
Chat and web ticket
www.renesas.com/synergy/resourcelibrary
12. Feedback on the Product
If you have any comments or suggestions about this product, go to renesassynergy.com/support.
13. Feedback on Content
If you have any comments on the document such as general suggestions for improvements, go to
renesassynergy.com/support, and provide:
- The title of the Renesas Synergy document
- The document number
- If applicable, the page number(s) to which your comments refer
- A detailed explanation of your comments.
Contents
Features ................................................................................................................................................... 58
1.
2.
Overview ........................................................................................................................................ 59
1.1
Function Outline ................................................................................................................... 59
1.2
Block Diagram ..................................................................................................................... 65
1.3
Part Numbering .................................................................................................................... 66
1.4
Function Comparison ........................................................................................................... 67
1.5
Pin Functions ....................................................................................................................... 68
1.6
Pin Assignments .................................................................................................................. 73
1.7
Pin Lists ............................................................................................................................... 76
CPU ............................................................................................................................................... 80
2.1
Overview .............................................................................................................................. 80
2.1.1
CPU ............................................................................................................................. 80
2.1.2
Debug .......................................................................................................................... 80
2.1.3
Operating Frequency ................................................................................................... 81
2.2
MCU Implementation Options .............................................................................................. 82
2.3
Trace Interface ..................................................................................................................... 82
2.4
JTAG/SWD Interface ........................................................................................................... 82
2.5
Debug Mode ........................................................................................................................ 83
2.5.1
Debug Mode Definition ................................................................................................ 83
2.5.2
Debug Mode Effects .................................................................................................... 83
2.5.2.1
Low power mode ................................................................................................. 83
2.5.2.2
Reset ................................................................................................................... 83
2.6
Programmers Model ............................................................................................................ 84
2.6.1
Address Spaces .......................................................................................................... 84
2.6.2
Cortex-M4 Peripheral Address Map ............................................................................ 84
2.6.3
CoreSight ROM Table ................................................................................................. 85
2.6.3.1
ROM entries ........................................................................................................ 85
2.6.3.2
CoreSight component registers ........................................................................... 85
2.6.4
DBGREG Module ........................................................................................................ 86
2.6.4.1
Debug Status Register (DBGSTR) ...................................................................... 86
2.6.4.2
Debug Stop Control Register (DBGSTOPCR) .................................................... 87
2.6.4.3
Trace Control Register (TRACECTR) ................................................................. 87
2.6.4.4
DBGREG CoreSight component registers .......................................................... 88
2.6.5
2.7
OCDREG Module ........................................................................................................ 88
2.6.5.1
ID Authentication Code Register (IAUTH0 to 3) .................................................. 88
2.6.5.2
MCU Status Register (MCUSTAT) ....................................................................... 89
2.6.5.3
MCU Control Register (MCUCTRL) .................................................................... 90
2.6.5.4
OCDREG CoreSight component registers .......................................................... 90
CoreSight ATB Funnel ......................................................................................................... 90
2.8
Flash Patch and Break Unit ................................................................................................. 91
2.9
SysTick System Timer ......................................................................................................... 91
2.10
CoreSight Time Stamp Generator ....................................................................................... 91
2.11
OCD Emulator Connection .................................................................................................. 91
2.11.1
DBGEN ........................................................................................................................ 92
2.11.2
Unlock ID Code ........................................................................................................... 92
2.11.3
Restrictions on Connecting an OCD Emulator ............................................................ 92
2.11.3.1
Starting connection while in low power mode ..................................................... 92
2.11.3.2
Changing low power mode while in OCD mode .................................................. 92
2.11.3.3
Modifying the unlock ID code in OSIS ................................................................. 93
2.11.3.4
Connecting sequence and JTAG/SWD authentication ........................................ 93
2.12
3.
Operating Modes ........................................................................................................................... 95
3.1
Overview .............................................................................................................................. 95
3.2
Details of Operating Modes ................................................................................................. 95
3.2.1
Single-Chip Mode ........................................................................................................ 95
3.2.2
SCI Boot Mode ............................................................................................................ 95
3.2.3
USB Boot Mode ........................................................................................................... 95
3.3
Operating Mode Transitions ................................................................................................ 95
3.3.1
4.
5.
Operating Mode Transitions as Determined by the Mode-Setting Pin ........................ 95
Address Space ............................................................................................................................... 96
4.1
Overview .............................................................................................................................. 96
4.2
External Address Space ...................................................................................................... 97
Memory Mirror Function (MMF) ..................................................................................................... 98
5.1
Overview .............................................................................................................................. 98
5.2
Register Descriptions ........................................................................................................... 98
5.2.1
MemMirror Special Function Register (MMSFR) ......................................................... 98
5.2.2
MemMirror Enable Register (MMEN) .......................................................................... 99
5.3
6.
References .......................................................................................................................... 94
Operation ............................................................................................................................. 99
5.3.1
MMF Operation ............................................................................................................ 99
5.3.2
Setting Example ........................................................................................................ 102
Resets .......................................................................................................................................... 104
6.1
Overview ............................................................................................................................ 104
6.2
Register Descriptions ......................................................................................................... 108
6.2.1
Reset Status Register 0 (RSTSR0) ........................................................................... 108
6.2.2
Reset Status Register 1 (RSTSR1) ........................................................................... 109
6.2.3
Reset Status Register 2 (RSTSR2) ........................................................................... 111
6.3
Operation ........................................................................................................................... 112
6.3.1
RES Pin Reset ........................................................................................................... 112
6.3.2
Power-On Reset ........................................................................................................ 112
6.3.3
Voltage Monitor Reset ............................................................................................... 113
7.
6.3.4
Deep Software Standby Reset .................................................................................. 114
6.3.5
Independent Watchdog Timer Reset ......................................................................... 114
6.3.6
Watchdog Timer Reset .............................................................................................. 115
6.3.7
Software Reset .......................................................................................................... 115
6.3.8
Determination of Cold/Warm Start ............................................................................. 115
6.3.9
Determination of Reset Generation Source ............................................................... 115
Option-Setting Memory ................................................................................................................ 117
7.1
Overview ............................................................................................................................ 117
7.2
Register Descriptions ......................................................................................................... 117
7.2.1
Option Function Select Register 0 (OFS0) ................................................................ 117
7.2.2
Option Function Select Register 1 (OFS1) ................................................................ 120
7.2.3
Access Window Setting Register (AWS) ................................................................... 121
7.2.4
OCD/Serial Programmer ID Setting Register (OSIS) ................................................ 123
7.3
Setting the Option-Setting Memory .................................................................................... 124
7.3.1
Allocation of Data in the Option-Setting Memory ....................................................... 124
7.3.2
Setting Data for Programming the Option-Setting Memory ....................................... 124
7.4
Usage Notes ...................................................................................................................... 124
7.4.1
8.
Low Voltage Detection (LVD) ....................................................................................................... 125
8.1
Overview ............................................................................................................................ 125
8.2
Register Descriptions ......................................................................................................... 127
8.2.1
Voltage Monitor 1 Circuit Control Register 1 (LVD1CR1) .......................................... 127
8.2.2
Voltage Monitor 1 Circuit Status Register (LVD1SR) ................................................. 128
8.2.3
Voltage Monitor 2 Circuit Control Register 1 (LVD2CR1) .......................................... 128
8.2.4
Voltage Monitor 2 Circuit Status Register (LVD2SR) ................................................. 129
8.2.5
Voltage Monitor Circuit Control Register (LVCMPCR) ............................................... 129
8.2.6
Voltage Detection Level Select Register (LVDLVLR) ................................................. 130
8.2.7
Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0) .......................................... 130
8.2.8
Voltage Monitor 2 Circuit Control Register 0 (LVD2CR0) .......................................... 131
8.3
VCC Input Voltage Monitor ................................................................................................ 132
8.3.1
Monitoring Vdet0 ....................................................................................................... 132
8.3.2
Monitoring Vdet1 ....................................................................................................... 132
8.3.3
Monitoring Vdet2 ....................................................................................................... 133
8.4
Reset from Voltage Monitor 0 ............................................................................................ 133
8.5
Interrupt and Reset from Voltage Monitor 1 ....................................................................... 134
8.6
Interrupt and Reset from Voltage Monitor 2 ....................................................................... 137
8.7
Event Link Output .............................................................................................................. 139
8.7.1
9.
Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory
................................................................................................................................... 124
Interrupt Handling and Event Linking ........................................................................ 140
Clock Generation Circuit .............................................................................................................. 141
9.1
Overview ............................................................................................................................ 141
9.2
Register Descriptions ......................................................................................................... 145
9.2.1
System Clock Division Control Register (SCKDIVCR) .............................................. 145
9.2.2
System Clock Division Control Register 2 (SCKDIVCR2) ......................................... 149
9.2.3
System Clock Source Control Register (SCKSCR) ................................................... 149
9.2.4
PLL Clock Control Register (PLLCCR) ...................................................................... 152
9.2.5
PLL Control Register (PLLCR) .................................................................................. 153
9.2.6
External Bus Clock Control Register (BCKCR) ......................................................... 153
9.2.7
Main Clock Oscillator Control Register (MOSCCR) .................................................. 154
9.2.8
Subclock Oscillator Control Register (SOSCCR) ...................................................... 155
9.2.9
Low-Speed On-Chip Oscillator Control Register (LOCOCR) .................................... 155
9.2.10
High-Speed On-Chip Oscillator Control Register (HOCOCR) ................................... 156
9.2.11
High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR) ..................... 157
9.2.12
Middle-Speed On-Chip Oscillator Control Register (MOCOCR) ............................... 157
9.2.13
FLL Control Register 1 (FLLCR1) .............................................................................. 158
9.2.14
FLL Control Register 2 (FLLCR2) .............................................................................. 160
9.2.15
Oscillation Stabilization Flag Register (OSCSF) ........................................................ 160
9.2.16
Oscillation Stop Detection Control Register (OSTDCR) ............................................ 161
9.2.17
Oscillation Stop Detection Status Register (OSTDSR) .............................................. 162
9.2.18
Main Clock Oscillator Wait Control Register (MOSCWTCR) ..................................... 163
9.2.19
Main Clock Oscillator Mode Oscillation Control Register (MOMCR) ......................... 164
9.2.20
Subclock Oscillator Mode Control Register (SOMCR) .............................................. 165
9.2.21
Clock Out Control Register (CKOCR) ....................................................................... 165
9.2.22
External Bus Clock Output Control Register (EBCKOCR) ........................................ 166
9.2.23
SDRAM Clock Output Control Register (SDCKOCR) ............................................... 166
9.2.24
LOCO User Trimming Control Register (LOCOUTCR) ............................................. 167
9.2.25
MOCO User Trimming Control Register (MOCOUTCR) ........................................... 167
9.2.26
HOCO User Trimming Control Register (HOCOUTCR) ............................................ 168
9.2.27
Trace Clock Control Register (TRCKCR) .................................................................. 168
9.3
Main Clock Oscillator ......................................................................................................... 168
9.3.1
Connecting the Crystal Resonator ............................................................................. 169
9.3.2
External Clock Input .................................................................................................. 169
9.3.3
Notes on External Clock Input ................................................................................... 169
9.4
Sub-Clock Oscillator .......................................................................................................... 170
9.4.1
Connecting a 32.768-kHz Crystal Resonator ............................................................ 170
9.4.2
Handling of Pins When the Sub-Clock Oscillator Is Not Used ................................... 170
9.5
Oscillation Stop Detection Function ................................................................................... 171
9.5.1
Oscillation Stop Detection and Operation after Detection ......................................... 171
9.5.2
Oscillation Stop Detection Interrupts ......................................................................... 172
9.6
PLL Circuit ......................................................................................................................... 173
9.7
Internal Clock ..................................................................................................................... 173
9.7.1
System Clock (ICLK) ................................................................................................. 173
9.7.2
Peripheral Module Clock (PCLKA, PCLKB, PCLKC, PCLKD) .................................. 174
9.7.3
Flash Interface Clock (FCLK) .................................................................................... 175
9.7.4
External Bus Clock (BCLK) ....................................................................................... 175
9.7.5
SDRAM Clock (SDCLK) ............................................................................................ 175
9.7.6
USB Clock (UCLK) .................................................................................................... 175
9.7.7
CAN Clock (CANMCLK) ............................................................................................ 176
9.7.8
CAC Clock (CACCLK) ............................................................................................... 176
9.7.9
RTC-Dedicated Clock (RTCSCLK, RTCLCLK) ......................................................... 176
9.7.10
IWDT-Dedicated Clock (IWDTCLK) .......................................................................... 176
9.7.11
AGT-Dedicated Clock (AGTSCLK, AGTLCLK) ......................................................... 176
9.7.12
SysTick Timer-Dedicated Clock (SYSTICCLK) ......................................................... 176
9.7.13
Clock/Buzzer Output Clock (CLKOUT) ...................................................................... 176
9.7.14
JTAG Clock (JTAGTCK) ............................................................................................ 176
9.8
10.
Usage Notes ...................................................................................................................... 176
9.8.1
Notes on Clock Generation Circuit ............................................................................ 176
9.8.2
Notes on the Resonator ............................................................................................. 177
9.8.3
Notes on Board Design ............................................................................................. 177
9.8.4
Notes on the Resonator Connect Pin ........................................................................ 177
9.8.5
Notes on Using Sub-Clock Oscillator for LGA Packages .......................................... 177
9.8.6
Notes on the Main Clock Oscillator Drive Capability Auto Switching Function .......... 177
Clock Frequency Accuracy Measurement Circuit (CAC) ............................................................. 179
10.1
Overview ............................................................................................................................ 179
10.2
Register Descriptions ......................................................................................................... 180
10.2.1
CAC Control Register 0 (CACR0) ............................................................................. 180
10.2.2
CAC Control Register 1 (CACR1) ............................................................................. 181
10.2.3
CAC Control Register 2 (CACR2) ............................................................................. 182
10.2.4
CAC Interrupt Control Register (CAICR) ................................................................... 183
10.2.5
CAC Status Register (CASTR) .................................................................................. 184
10.2.6
CAC Upper-Limit Value Setting Register (CAULVR) ................................................. 185
10.2.7
CAC Lower-Limit Value Setting Register (CALLVR) .................................................. 185
10.2.8
CAC Counter Buffer Register (CACNTBR) ............................................................... 185
10.3
Operation ........................................................................................................................... 185
10.3.1
Measuring Clock Frequency ...................................................................................... 185
10.3.2
Digital Filtering of Signals on CACREF Pin ............................................................... 187
10.4
Interrupt Requests ............................................................................................................. 187
10.5
Usage Notes ...................................................................................................................... 187
10.5.1
11.
Settings for the Module-Stop Function ...................................................................... 187
Low Power Modes ....................................................................................................................... 188
11.1
Overview ............................................................................................................................ 188
11.2
Register Descriptions ......................................................................................................... 192
11.2.1
Standby Control Register (SBYCR) ........................................................................... 192
11.2.2
Module Stop Control Register A (MSTPCRA) ........................................................... 193
11.2.3
Module Stop Control Register B (MSTPCRB) ........................................................... 194
11.2.4
Module Stop Control Register C (MSTPCRC) ........................................................... 195
11.2.5
Module Stop Control Register D (MSTPCRD) ........................................................... 196
11.2.6
Operating Power Control Register (OPCCR) ............................................................ 198
11.2.7
Sub Operating Power Control Register (SOPCCR) .................................................. 199
11.2.8
Snooze Control Register (SNZCR) ............................................................................ 200
11.2.9
Snooze End Control Register (SNZEDCR) ............................................................... 201
11.2.10
Snooze Request Control Register (SNZREQCR) ..................................................... 202
11.2.11
Deep Software Standby Control Register (DPSBYCR) ............................................. 204
11.2.12
Deep Software Standby Interrupt Enable Register 0 (DPSIER0) .............................. 205
11.2.13
Deep Software Standby Interrupt Enable Register 1 (DPSIER1) .............................. 206
11.2.14
Deep Software Standby Interrupt Enable Register 2 (DPSIER2) .............................. 206
11.2.15
Deep Software Standby Interrupt Enable Register 3 (DPSIER3) .............................. 207
11.2.16
Deep Software Standby Interrupt Flag Register 0 (DPSIFR0) .................................. 208
11.2.17
Deep Software Standby Interrupt Flag Register 1 (DPSIFR1) .................................. 209
11.2.18
Deep Software Standby Interrupt Flag Register 2 (DPSIFR2) .................................. 210
11.2.19
Deep Software Standby Interrupt Flag Register 3 (DPSIFR3) .................................. 211
11.2.20
Deep Software Standby Interrupt Edge Register 0 (DPSIEGR0) .............................. 212
11.2.21
Deep Software Standby Interrupt Edge Register 1 (DPSIEGR1) .............................. 212
11.2.22
Deep Software Standby Interrupt Edge Register 2 (DPSIEGR2) .............................. 213
11.2.23
System Control OCD Control Register (SYOCDCR) ................................................. 213
11.2.24
Standby Condition Register (STCONR) .................................................................... 214
11.3
Reducing Power Consumption by Switching Clock Signals .............................................. 214
11.4
Module-Stop Function ........................................................................................................ 215
11.5
Function for Lower Operating Power Consumption ........................................................... 215
11.5.1
11.6
Setting the Operating Power Control Mode ............................................................... 215
Sleep Mode ........................................................................................................................ 216
11.6.1
Transition to Sleep Mode ........................................................................................... 216
11.6.2
Canceling Sleep Mode .............................................................................................. 217
11.7
Software Standby Mode .................................................................................................... 218
11.7.1
Transition to Software Standby Mode ....................................................................... 218
11.7.2
Canceling Software Standby Mode ........................................................................... 219
11.7.3
Example of Software Standby Mode Application ....................................................... 221
11.8
Snooze Mode ..................................................................................................................... 222
11.8.1
Transition to Snooze Mode ........................................................................................ 222
11.8.2
Canceling Snooze Mode ........................................................................................... 223
11.8.3
Return to Software Standby Mode ............................................................................ 223
11.8.4
Snooze Operation Example ....................................................................................... 225
11.9
Deep Software Standby Mode ........................................................................................... 229
11.9.1
Transition to Deep Software Standby Mode .............................................................. 229
11.9.2
Canceling Deep Software Standby Mode .................................................................. 229
11.9.3
Pin States when Deep Software Standby Mode is Canceled .................................... 230
11.9.4
Example of Deep Software Standby Mode Application ............................................. 230
11.9.5
Usage Flow for Deep Software Standby Mode ......................................................... 231
11.10
Usage Notes ...................................................................................................................... 232
11.10.1
Register Access ......................................................................................................... 232
11.10.2
I/O Port States ........................................................................................................... 234
11.10.3
Module-Stop State of DMAC and DTC ...................................................................... 234
11.10.4
Internal Interrupt Sources .......................................................................................... 234
11.10.5
Input Buffer Control by the DIRQnE Bit (n = 0 to 13) ................................................ 234
11.10.6
Transition to Low Power Modes ................................................................................ 234
11.10.7
Timing of WFI Instruction ........................................................................................... 234
11.10.8
Writing to the WDT and IWDT Registers by the DMAC or DTC in Sleep or Snooze Mode
................................................................................................................................... 234
11.10.9
Oscillators in Snooze Mode ....................................................................................... 235
11.10.10 Snooze Mode Entry by RXD0 Falling Edge ............................................................... 235
11.10.11 Using SCI0 in Snooze Mode ..................................................................................... 235
11.10.12 Conditions of A/D Conversion Start in Snooze Mode ................................................ 235
11.10.13 ELC Events in Snooze Mode ..................................................................................... 235
11.10.14 Conditions of CTSU in Snooze Mode ........................................................................ 235
12.
Battery Backup Function .............................................................................................................. 236
12.1
12.1.1
Features of Battery Backup Function ........................................................................ 236
12.1.2
Battery Power Supply Switch .................................................................................... 236
12.1.3
Backup Registers ...................................................................................................... 236
12.1.4
Time Capture Pin Detection ...................................................................................... 236
12.2
Register Descriptions ......................................................................................................... 237
12.2.1
VBATT Backup Register (VBTBKRn) (n = 0 to 511) .................................................. 237
12.2.2
VBATT Input Control Register (VBTICTLR) .............................................................. 238
12.3
Operation ........................................................................................................................... 238
12.3.1
Battery Backup Function ........................................................................................... 238
12.3.2
VBATT Battery Power Supply Switch Usage ............................................................ 240
12.3.3
VBATT Backup Register Usage ................................................................................ 240
12.4
13.
Overview ............................................................................................................................ 236
Usage Notes ...................................................................................................................... 240
Register Write Protection ............................................................................................................. 241
13.1
Overview ............................................................................................................................ 241
13.2
Register Descriptions ......................................................................................................... 241
13.2.1
14.
Protect Register (PRCR) ........................................................................................... 241
Interrupt Controller Unit (ICU) ...................................................................................................... 242
14.1
Overview ............................................................................................................................ 242
14.2
Register Descriptions ......................................................................................................... 244
14.2.1
IRQ Control Register i (IRQCRi) (i = 0 to 15) ............................................................ 244
14.2.2
Non-Maskable Interrupt Status Register (NMISR) ..................................................... 245
14.2.3
Non-Maskable Interrupt Enable Register (NMIER) ................................................... 247
14.2.4
Non-Maskable Interrupt Status Clear Register (NMICLR) ......................................... 249
14.2.5
NMI Pin Interrupt Control Register (NMICR) ............................................................. 250
14.2.6
ICU Event Link Setting Register n (IELSRn) (n = 0 to 95) ......................................... 251
14.2.7
DMAC Event Link Setting Register n (DELSRn) (n = 0 to 7) ..................................... 252
14.2.8
SYS Event Link Setting Register (SELSR0) .............................................................. 253
14.2.9
Wake Up Interrupt Enable Register (WUPEN) .......................................................... 253
14.3
14.3.1
Interrupt Vector Table ................................................................................................ 255
14.3.2
Event Numbers .......................................................................................................... 258
14.4
15.
Vector Table ...................................................................................................................... 255
Interrupt Operation ............................................................................................................. 265
14.4.1
Detecting Interrupts ................................................................................................... 266
14.4.2
Selecting Interrupt Request Destinations .................................................................. 267
14.4.2.1
CPU interrupt request ........................................................................................ 267
14.4.2.2
DTC activation ................................................................................................... 267
14.4.2.3
DMAC activation ................................................................................................ 268
14.4.3
Digital Filter ................................................................................................................ 268
14.4.4
External Pin Interrupts ............................................................................................... 269
14.5
Non-Maskable Interrupt Operation .................................................................................... 269
14.6
Return from Low Power Modes ......................................................................................... 270
14.6.1
Return from Sleep Mode ........................................................................................... 270
14.6.2
Return from Software Standby Mode ........................................................................ 270
14.6.3
Return from Snooze Mode ........................................................................................ 270
14.7
Using the WFI Instruction with Non-Maskable Interrupts ................................................... 271
14.8
Reference .......................................................................................................................... 271
Buses ........................................................................................................................................... 272
15.1
Overview ............................................................................................................................ 272
15.2
Description of Buses .......................................................................................................... 273
15.2.1
Main Buses ................................................................................................................ 273
15.2.2
Slave Interface ........................................................................................................... 274
15.2.3
External Bus .............................................................................................................. 274
15.2.4
Parallel Operations .................................................................................................... 276
15.2.5
Bus Settings .............................................................................................................. 277
15.2.6
Restrictions ................................................................................................................ 277
15.3
Register Descriptions ......................................................................................................... 277
15.3.1
CSn Control Register (CSnCR) (n = 0 to 7) .............................................................. 277
15.3.2
CSn Recovery Cycle Register (CSnREC) (n = 0 to 7) .............................................. 279
15.3.3
CS Recovery Cycle Insertion Enable Register (CSRECEN) ..................................... 280
15.3.4
CSn Mode Register (CSnMOD) (n = 0 to 7) .............................................................. 282
15.3.5
CSn Wait Control Register 1 (CSnWCR1) (n = 0 to 7) .............................................. 283
15.3.6
CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 7) .............................................. 285
15.3.7
SDC Control Register (SDCCR) ................................................................................ 288
15.3.8
SDC Mode Register (SDCMOD) ............................................................................... 288
15.3.9
SDRAM Self-Refresh Control Register (SDSELF) .................................................... 289
15.3.10
SDRAM Refresh Control Register (SDRFCR) ........................................................... 289
15.3.10.1
Auto-refresh request interval and RFC set value .............................................. 290
15.3.11
SDRAM Auto-Refresh Control Register (SDRFEN) .................................................. 290
15.3.12
SDRAM Initialization Sequence Control Register (SDICR) ....................................... 291
15.3.13
SDRAM Initialization Register (SDIR) ....................................................................... 291
15.3.14
SDRAM Address Register (SDADR) ......................................................................... 292
15.3.15
SDRAM Timing Register (SDTR) .............................................................................. 293
15.3.16
SDRAM Mode Register (SDMOD) ............................................................................ 294
15.3.17
SDRAM Status Register (SDSR) ............................................................................... 295
15.3.18
Master Bus Control Register (BUSMCNT) ................................................. 296
15.3.19
Slave Bus Control Register (BUSSCNT) ...................................................... 297
15.3.20
Bus Error Address Register (BUSnERRADD) (n = 1 to 5) ........................................ 298
15.3.21
Bus Error Status Register (BUSnERRSTAT) (n = 1 to 5) .......................................... 299
15.4
Endianness and Data Alignment ....................................................................................... 299
15.4.1
Data Alignment Control for the CS Areas .................................................................. 300
15.4.2
Data Alignment Control for the SDRAM Area ............................................................ 303
15.5
Operation of CS Area Controller ........................................................................................ 304
15.5.1
Separate Bus ............................................................................................................. 304
15.5.2
Address/Data Multiplexed Bus .................................................................................. 315
15.5.3
External Wait Function .............................................................................................. 317
15.5.4
Insertion of Recovery Cycles ..................................................................................... 320
15.5.5
No Access State ........................................................................................................ 323
15.5.6
Write Buffer Function (External Bus) ......................................................................... 323
15.5.7
Constraints ................................................................................................................ 324
15.6
SDRAM Area Controller Operation .................................................................................... 325
15.6.1
Enabling/Disabling SDRAM Access and Setting the SDRAM Bus Width .................. 325
15.6.2
No Access State ........................................................................................................ 325
15.6.3
Insertion of Recovery Cycles ..................................................................................... 325
15.6.4
Write Buffer Function ................................................................................................. 326
15.6.5
SDRAM Commands .................................................................................................. 326
15.6.6
Conditions for Setting the SDRAMC Registers ......................................................... 326
15.6.7
Self-Refresh ............................................................................................................... 327
15.6.8
Auto-Refresh ............................................................................................................. 329
15.6.9
Initialization Sequencer ............................................................................................. 330
15.6.10
Setting the Mode Register ......................................................................................... 331
15.6.11
SDRAMC Setting Examples ...................................................................................... 331
15.6.11.1
SDRAMC access procedure ............................................................................. 331
15.6.11.2
Procedure for transitioning to and recovering from self-refresh mode .............. 332
15.6.11.3
Timing register settings and access timing ....................................................... 334
15.6.12
Address Multiplexing ................................................................................................. 340
15.6.13
Example SDRAM Connections .................................................................................. 341
15.6.13.1
15.6.14
15.7
16.
16-bit bus space ................................................................................................ 341
Constraints ................................................................................................................ 344
Bus Error Monitoring Section ............................................................................................ 344
15.7.1
Bus Error Types ......................................................................................................... 345
15.7.2
Operation When a Bus Error Occurs ......................................................................... 345
15.7.3
Conditions Leading to Illegal Address Access Errors ................................................ 345
15.7.4
Timeout ...................................................................................................................... 346
15.8
Notes on using Flash Cache .............................................................................................. 346
15.9
References ........................................................................................................................ 346
Memory Protection Unit (MPU) .................................................................................................... 347
16.1
Overview ............................................................................................................................ 347
16.2
CPU Stack Pointer Monitor ................................................................................................ 348
16.2.1
Register Descriptions ................................................................................................ 350
16.2.1.1
Main Stack Pointer Monitor Start Address Register (MSPMPUSA) .................. 350
16.2.1.2
Main Stack Pointer Monitor End Address Register (MSPMPUEA) ................... 351
16.2.1.3
Process Stack Pointer Monitor Start Address Register (PSPMPUSA) .............. 351
16.2.1.4
Process Stack Pointer Monitor End Address Register (PSPMPUEA) ............... 352
16.2.1.5
Stack Pointer Monitor Operation After Detection Register (MSPMPUOAD, PSPMPUOAD) ............................................................................................................ 352
16.2.1.6
Stack Pointer Monitor Access Control Register (MSPMPUCTL, PSPMPUCTL)
........................................................................................................................... 353
16.2.1.7
Stack Pointer Monitor Protection Register (MSPMPUPT, PSPMPUPT) ........... 354
16.2.2
Operation ................................................................................................................... 354
16.2.2.1
Protecting the registers ..................................................................................... 354
16.2.2.2
Overflow and underflow errors .......................................................................... 354
16.3
Arm MPU ........................................................................................................................... 355
16.4
Bus Master MPU ................................................................................................................ 355
16.4.1
Register Descriptions ................................................................................................ 357
16.4.1.1
Group m Region n Start Address Register (MMPUSmn) (m = A or B; n = 0 to 31)
........................................................................................................................... 357
16.4.1.2
Group m Region n End Address Register (MMPUEmn) (m = A or B; n = 0 to 31)
........................................................................................................................... 357
16.4.1.3
Group m Region n Access Control Register (MMPUACmn) (m = A or B; n = 0 to 31)
.......................................................................................................................... 358
16.4.1.4
Bus Master MPU Control Register (MMPUCTLm) (m = A or B) ........................ 359
16.4.1.5
Group m Protection of Register (MMPUPTm) (m = A or B) .............................. 360
16.4.2
Operation ................................................................................................................... 361
16.4.2.1
Memory protection ............................................................................................. 361
16.5
16.4.2.2
Protecting the registers ..................................................................................... 363
16.4.2.3
Memory protection error .................................................................................... 363
Bus Slave MPU .................................................................................................................. 363
16.5.1
16.5.1.1
Access Control Register for Memory Bus 3 (SMPUMBIU) ................................ 364
16.5.1.2
Access Control Register for Internal Peripheral Bus 9 (SMPUFBIU) ................ 365
16.5.1.3
Access Control Register for Memory Bus 4 (SMPUSRAM0) ............................ 366
16.5.1.4
Access Control Register for Memory Bus 5 (SMPUSRAM1) ............................ 367
16.5.1.5
Access Control Register for Internal Peripheral Bus 1 (SMPUP0BIU) .............. 368
16.5.1.6
Access Control Register for Internal Peripheral Bus 3 (SMPUP2BIU) .............. 369
16.5.1.7
Access Control Register for Internal Peripheral Bus 7 (SMPUP6BIU) .............. 370
16.5.1.8
Access Control Register for CS Area and SDRAM Area (SMPUEXBIU) .......... 371
16.5.1.9
Access Control Register for QSPI Area (SMPUEXBIU2) .................................. 372
16.5.1.10
Slave MPU Control Register (SMPUCTL) ......................................................... 373
16.5.2
16.6
Register Descriptions ................................................................................................ 364
Operation ................................................................................................................... 373
16.5.2.1
Memory protection ............................................................................................. 373
16.5.2.2
Protecting the registers ..................................................................................... 374
16.5.2.3
Memory protection error .................................................................................... 374
Security MPU ..................................................................................................................... 374
16.6.1
Register Descriptions (Option-Setting memory) ........................................................ 375
16.6.1.1
Security MPU Program Counter Start Address Register (SECMPUPCSn)
(n = 0, 1) ............................................................................................................ 375
16.6.1.2
Security MPU Program Counter End Address Register (SECMPUPCEn)
(n = 0, 1) ............................................................................................................ 376
16.6.1.3
Security MPU Region 0 Start Address Register (SECMPUS0) ......................... 376
16.6.1.4
Security MPU Region 0 End Address Register (SECMPUE0) .......................... 377
16.6.1.5
Security MPU Region 1 Start Address Register (SECMPUS1) ......................... 378
16.6.1.6
Security MPU Region 1 End Address Register (SECMPUE1) .......................... 378
16.6.1.7
Security MPU Region 2 Start Address Register (SECMPUS2) ......................... 379
16.6.1.8
Security MPU Region 2 End Address Register (SECMPUE2) .......................... 379
16.6.1.9
Security MPU Region 3 Start Address Register (SECMPUS3) ......................... 380
16.6.1.10
Security MPU Region 3 End Address Register (SECMPUE3) .......................... 381
16.6.1.11
Security MPU Access Control Register (SECMPUAC) ..................................... 381
16.6.2
Memory Protection .................................................................................................... 382
16.6.2.1
16.7
17.
Notes on debug ................................................................................................. 383
References ........................................................................................................................ 383
DMA Controller (DMAC) .............................................................................................................. 384
17.1
Overview ............................................................................................................................ 384
17.2
Register Descriptions ........................................................................................................ 386
17.2.1
DMA Source Address Register (DMSAR) ................................................................. 386
17.2.2
DMA Destination Address Register (DMDAR) .......................................................... 386
17.2.3
DMA Transfer Count Register (DMCRA) ................................................................... 387
17.2.4
DMA Block Transfer Count Register (DMCRB) ......................................................... 388
17.2.5
DMA Transfer Mode Register (DMTMD) ................................................................... 388
17.2.6
DMA Interrupt Setting Register (DMINT) ................................................................... 389
17.2.7
DMA Address Mode Register (DMAMD) ................................................................... 390
17.2.8
DMA Offset Register (DMOFR) ................................................................................. 392
17.2.9
DMA Transfer Enable Register (DMCNT) ................................................................. 392
17.2.10
DMA Software Start Register (DMREQ) .................................................................... 393
17.2.11
DMA Status Register (DMSTS) ................................................................................. 394
17.2.12
DMAC Module Activation Register (DMAST) ............................................................ 395
17.3
17.3.1
Transfer Mode ........................................................................................................... 395
17.3.2
Extended Repeat Area Function ............................................................................... 398
17.3.3
Address Update Function Using Offset ..................................................................... 400
17.3.4
Activation Sources ..................................................................................................... 403
17.3.5
Operation Timing ....................................................................................................... 404
17.3.6
Execution Cycles of DMAC ....................................................................................... 405
17.3.7
Activating the DMAC ................................................................................................. 405
17.3.8
Starting DMA Transfer ............................................................................................... 407
17.3.9
Registers during DMA Transfer ................................................................................. 407
17.3.10
Channel Priority ......................................................................................................... 408
17.4
18.
Operation ........................................................................................................................... 395
Ending DMA Transfer ........................................................................................................ 408
17.4.1
Transfer End by Completion of Specified Total Number of Transfer Operations ...... 408
17.4.2
Transfer End by Repeat Size End Interrupt ............................................................... 408
17.4.3
Transfer End by Interrupt on Extended Repeat Area Overflow ................................. 408
17.4.4
Precautions for the End of DMA Transfer .................................................................. 409
17.5
Interrupts ............................................................................................................................ 409
17.6
Event Link .......................................................................................................................... 410
17.7
Low Power Consumption Function .................................................................................... 410
17.8
Usage Notes ...................................................................................................................... 411
17.8.1
DMA Transfer to External Devices ............................................................................ 411
17.8.2
Access to Registers during DMA Transfer ................................................................ 411
17.8.3
DMA Transfer to Reserved Areas ............................................................................. 411
17.8.4
Setting the DMAC Event Link Setting Register of the Interrupt Controller Unit (ICU.DELSRn) .......................................................................................................................... 411
17.8.5
Suspending or Restarting DMA Activation ................................................................ 411
Data Transfer Controller (DTC) .................................................................................................... 412
18.1
Overview ............................................................................................................................ 412
18.2
Register Descriptions ......................................................................................................... 413
18.2.1
DTC Mode Register A (MRA) .................................................................................... 414
18.2.2
DTC Mode Register B (MRB) .................................................................................... 414
18.2.3
DTC Transfer Source Register (SAR) ....................................................................... 415
18.2.4
DTC Transfer Destination Register (DAR) ................................................................ 416
18.2.5
DTC Transfer Count Register A (CRA) ..................................................................... 416
18.2.6
DTC Transfer Count Register B (CRB) .................................................................... 417
18.2.7
DTC Control Register (DTCCR) ................................................................................ 417
18.2.8
DTC Vector Base Register (DTCVBR) ...................................................................... 418
18.2.9
DTC Module Start Register (DTCST) ........................................................................ 418
18.2.10
DTC Status Register (DTCSTS) ................................................................................ 419
18.3
Activation Sources ............................................................................................................. 419
18.3.1
18.4
Operation ........................................................................................................................... 421
18.4.1
Transfer Information Read Skip Function .................................................................. 424
18.4.2
Transfer Information Write-Back Skip Function ......................................................... 424
18.4.3
Normal Transfer Mode ............................................................................................... 425
18.4.4
Repeat Transfer Mode ............................................................................................... 426
18.4.5
Block Transfer Mode ................................................................................................. 427
18.4.6
Chain Transfer ........................................................................................................... 428
18.4.7
Operation Timing ....................................................................................................... 429
18.4.8
Execution Cycles of DTC ........................................................................................... 430
18.4.9
DTC Bus Mastership Release Timing ....................................................................... 431
18.5
DTC Setting Procedure ...................................................................................................... 431
18.6
Examples of DTC Usage ................................................................................................... 432
18.6.1
Normal Transfer ......................................................................................................... 432
18.6.2
Chain Transfer ........................................................................................................... 433
18.6.3
Chain Transfer when Counter = 0 ............................................................................. 434
18.7
Interrupt Sources ............................................................................................................... 436
18.8
Event Link .......................................................................................................................... 436
18.9
Snooze Control Interface ................................................................................................... 436
18.10
Module-Stop Function ........................................................................................................ 436
18.11
Usage Notes ...................................................................................................................... 437
18.11.1
19.
Allocating Transfer Information and the DTC Vector Table ....................................... 420
Transfer information Start Address ............................................................................ 437
Event Link Controller (ELC) ......................................................................................................... 438
19.1
Overview ............................................................................................................................ 438
19.2
Register Descriptions ......................................................................................................... 439
19.2.1
Event Link Controller Register (ELCR) ...................................................................... 439
19.2.2
Event Link Software Event Generation Register n (ELSEGRn) (n = 0, 1) ................. 439
19.2.3
Event Link Setting Register n (ELSRn) (n = 0 to 18) ................................................. 440
19.3
Operation ........................................................................................................................... 447
19.3.1
Relation between Interrupt Handling and Event Linking ............................................ 447
19.3.2
Linking Events ........................................................................................................... 447
19.3.3
Example Procedure for Linking Events ..................................................................... 447
19.4
Usage Notes ...................................................................................................................... 447
20.
19.4.1
Linking DMAC or DTC Transfer End Signals as Events ............................................ 447
19.4.2
Setting Clocks ............................................................................................................ 448
19.4.3
Settings for the Module-Stop Function ...................................................................... 448
19.4.4
ELC Delay Time ........................................................................................................ 448
I/O Ports ....................................................................................................................................... 449
20.1
Overview ............................................................................................................................ 449
20.2
Register Descriptions ......................................................................................................... 451
20.2.1
Port Control Register 1 (PCNTR1/PODR/PDR) ........................................................ 451
20.2.2
Port Control Register 2 (PCNTR2/EIDR/PIDR) ......................................................... 452
20.2.3
Port Control Register 3 (PCNTR3/PORR/POSR) ...................................................... 453
20.2.4
Port Control Register 4 (PCNTR4/EORR/EOSR) ...................................................... 454
20.2.5
Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY)
(m = 0 to 8; n = 00 to 15) ........................................................................................... 455
20.2.6
Write-Protect Register (PWPR) ................................................................................. 457
20.2.7
Ethernet Control Register (PFENET) ........................................................................ 457
20.3
21.
Operation ........................................................................................................................... 457
20.3.1
General I/O Ports ....................................................................................................... 457
20.3.2
Port Function Select .................................................................................................. 458
20.3.3
Port Group Function for the ELC ............................................................................... 458
20.3.3.1
Behavior when ELC_PORT1, 2, 3, or 4 is input from the ELC .......................... 458
20.3.3.2
Behavior when an event pulse is output to the ELC .......................................... 459
20.4
Handling of Unused Pins ................................................................................................... 460
20.5
Usage Notes ...................................................................................................................... 461
20.5.1
Procedure for Specifying the Pin Functions .............................................................. 461
20.5.2
Procedure for Using Port Group Input ....................................................................... 461
20.5.3
Port Output Data Register (PODR) Summary ........................................................... 461
20.5.4
Notes on Using Analog Functions ............................................................................. 461
20.5.5
I/O Buffer Specification .............................................................................................. 461
20.6
Peripheral Select Settings for each Product ...................................................................... 463
20.7
Notes on the PmnPFS Register Setting ............................................................................ 463
Key Interrupt Function (KINT) ...................................................................................................... 477
21.1
Overview ............................................................................................................................ 477
21.2
Register Descriptions ......................................................................................................... 479
21.2.1
Key Return Control Register (KRCTL) ...................................................................... 479
21.2.2
Key Return Flag Register (KRF) ................................................................................ 479
21.2.3
Key Return Mode Register (KRM) ............................................................................. 479
21.3
Operation ........................................................................................................................... 480
21.3.1
Operation When Not Using Key Interrupt Flag (KRMD = 0) ...................................... 480
21.3.2
Operation When Using the Key Interrupt Flags (KRMD = 1) ..................................... 480
21.4
Usage Notes ...................................................................................................................... 482
22.
Port Output Enable for GPT (POEG) ........................................................................................... 483
22.1
Overview ............................................................................................................................ 483
22.2
Register Descriptions ......................................................................................................... 485
22.2.1
22.3
POEG Group n Setting Register (POEGGn) (n = A to D) ......................................... 485
Output-Disable Control Operation ..................................................................................... 486
22.3.1
Pin Input Level Detection Operation .......................................................................... 486
22.3.1.1
23.
Digital filter ......................................................................................................... 486
22.3.2
Output-Disable Requests from the GPT .................................................................... 487
22.3.3
Comparator Interrupt Detection ................................................................................. 487
22.3.4
Output-Disable Control Using Detection of Stopped Oscillation ................................ 487
22.3.5
Output-Disable Control Using Registers .................................................................... 487
22.3.6
Release from Output-Disable .................................................................................... 487
22.4
Interrupt Sources ............................................................................................................... 488
22.5
External Trigger Output to the GPT ................................................................................... 489
22.6
Usage Notes ...................................................................................................................... 489
22.6.1
Transition to Software Standby Mode ....................................................................... 489
22.6.2
Specifying Pins Associated with the GPT .................................................................. 489
General PWM Timer (GPT) ......................................................................................................... 490
23.1
Overview ............................................................................................................................ 490
23.2
Register Descriptions ......................................................................................................... 494
23.2.1
General PWM Timer Write-Protection Register (GTWP) .......................................... 496
23.2.2
General PWM Timer Software Start Register (GTSTR) ............................................ 496
23.2.3
General PWM Timer Software Stop Register (GTSTP) ............................................ 497
23.2.4
General PWM Timer Software Clear Register (GTCLR) ........................................... 497
23.2.5
General PWM Timer Start Source Select Register (GTSSR) .................................... 498
23.2.6
General PWM Timer Stop Source Select Register (GTPSR) .................................... 501
23.2.7
General PWM Timer Clear Source Select Register (GTCSR) .................................. 504
23.2.8
General PWM Timer Up Count Source Select Register (GTUPSR) ......................... 507
23.2.9
General PWM Timer Down Count Source Select Register (GTDNSR) ..................... 510
23.2.10
General PWM Timer Input Capture Source Select Register A (GTICASR) .............. 513
23.2.11
General PWM Timer Input Capture Source Select Register B (GTICBSR) .............. 516
23.2.12
General PWM Timer Control Register (GTCR) ......................................................... 519
23.2.13
General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC) ....... 520
23.2.14
General PWM Timer I/O Control Register (GTIOR) .................................................. 523
23.2.15
General PWM Timer Interrupt Output Setting Register (GTINTAD) .......................... 527
23.2.16
General PWM Timer Status Register (GTST) ........................................................... 529
23.2.17
General PWM Timer Buffer Enable Register (GTBER) ............................................. 534
23.2.18
General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register (GTITC) ................................................................................................................ 537
23.2.19
General PWM Timer Counter (GTCNT) .................................................................... 539
23.2.20
General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F) .............. 539
23.2.21
General PWM Timer Cycle Setting Register (GTPR) ................................................ 540
23.2.22
General PWM Timer Cycle Setting Buffer Register (GTPBR) ................................... 540
23.2.23
General PWM Timer Cycle Setting Double-Buffer Register (GTPDBR) .................... 540
23.2.24
A/D Converter Start Request Timing Register n (GTADTRn) (n = A, B) ................... 541
23.2.25
A/D Converter Start Request Timing Buffer Register n (GTADTBRn)
(n = A, B) .................................................................................................................. 541
23.2.26
A/D Converter Start Request Timing Double-Buffer Register n (GTADTDBRn)
(n = A, B) ................................................................................................................... 542
23.2.27
General PWM Timer Dead Time Control Register (GTDTCR) .................................. 542
23.2.28
General PWM Timer Dead Time Value Register n (GTDVn) (n = U, D) .................... 544
23.2.29
General PWM Timer Dead Time Buffer Register n (GTDBn) (n = U, D) ................... 544
23.2.30
General PWM Timer Output Protection Function Status Register (GTSOS) ............ 545
23.2.31
General PWM Timer Output Protection Function Temporary Release Register (GTSOTR) ....................................................................................................................... 545
23.2.32
Output Phase Switching Control Register (OPSCR) ................................................. 546
23.3
Operation ........................................................................................................................... 548
23.3.1
Basic Operation ......................................................................................................... 548
23.3.1.1
Counter operation .............................................................................................. 548
23.3.1.2
Waveform output by compare match ................................................................ 553
23.3.1.3
Input capture function ........................................................................................ 556
23.3.2
Buffer Operation ........................................................................................................ 558
23.3.2.1
GTPR register buffer operation ......................................................................... 558
23.3.2.2
Buffer operation for GTCCRA and GTCCRB .................................................... 561
23.3.2.3
Buffer operation for GTADTRA and GTADTRB ................................................ 566
23.3.3
PWM Output Operating Mode ................................................................................... 569
23.3.3.1
Saw-wave PWM mode ...................................................................................... 569
23.3.3.2
Saw-wave one-shot pulse mode ....................................................................... 572
23.3.3.3
Triangle-wave PWM mode 1 (32-bit transfer at trough) .................................... 575
23.3.3.4
Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) .................... 577
23.3.3.5
Triangle-wave PWM mode 3 (64-bit transfer at trough) .................................... 579
23.3.4
Automatic Dead Time Setting Function ..................................................................... 581
23.3.5
Count Direction Changing Function ........................................................................... 587
23.3.6
Function of Output Duty 0% and 100% ..................................................................... 587
23.3.7
Hardware Count Start/Count Stop and Clear Operation ........................................... 589
23.3.7.1
Hardware start operation ................................................................................... 589
23.3.7.2
Hardware stop operation ................................................................................... 590
23.3.7.3
Hardware clear operation .................................................................................. 593
23.3.8
Synchronized Operation ............................................................................................ 595
23.3.8.1
Synchronized operation by software ................................................................. 595
23.3.8.2
Synchronized operation by hardware ................................................................ 597
23.3.9
PWM Output Operation Examples ............................................................................ 599
23.3.10
Phase Counting Function .......................................................................................... 605
23.3.11
Output Phase Switching (GPT_OPS) ........................................................................ 612
23.4
Input selection and synchronization of external input signal ............................. 615
23.3.11.2
Input sampling ................................................................................................... 616
23.3.11.3
Input phase decode ........................................................................................... 616
23.3.11.4
Output selection control ..................................................................................... 616
23.3.11.5
Output selection control (group output disable function) ................................... 617
23.3.11.6
Event Link Controller (ELC) output .................................................................... 618
23.3.11.7
GPT_OPS start operation setting flow .............................................................. 619
Interrupt Sources ............................................................................................................... 619
23.4.1
Overview .................................................................................................................... 619
23.4.2
DMAC/DTC Activation ............................................................................................... 625
23.4.3
Interrupt and A/D Conversion Request Skipping Function ........................................ 625
23.5
A/D Converter Start Request ............................................................................................. 629
23.6
Operations Linked by the ELC ........................................................................................... 632
23.6.1
Event Signal Output to the ELC ................................................................................. 632
23.6.2
Event Signal Inputs from the ELC ............................................................................. 632
23.7
Noise Filter Function .......................................................................................................... 632
23.8
Protection Function ............................................................................................................ 633
23.8.1
Write-Protection for Registers ................................................................................... 633
23.8.2
Disabling of Buffer Operation .................................................................................... 633
23.8.3
GTIOC Pin Output Negate Control ............................................................................ 634
23.8.4
Output Protection Function for GTIOC Pin Output .................................................... 635
23.9
23.8.4.1
Output protection function when the GTCCRA register is set to 0 during buffer transfer ...................................................................................................................... 636
23.8.4.2
Output protection function when GTCCRA ≥ GTPR is set during buffer transfer at
troughs .............................................................................................................. 638
23.8.4.3
Output protection function when GTCCRA ≥ GTPR is set during buffer transfer at
crests ................................................................................................................. 640
23.8.4.4
Restricted specification of output protection function ........................................ 641
23.8.4.5
Temporary cancellation of output protection function ........................................ 641
Initialization Method of Output Pins ................................................................................... 642
23.9.1
Pin Settings after Reset ............................................................................................. 642
23.9.2
Pin Initialization Caused by Error during Operation ................................................... 643
23.10
24.
23.3.11.1
Usage Notes ...................................................................................................................... 643
23.10.1
Module-Stop Function Setting ................................................................................... 643
23.10.2
GTCCRn Settings during Compare Match Operation (n = A to F) ............................ 643
23.10.3
Setting Range for the GTCNT Counter ..................................................................... 644
23.10.4
Starting and Stopping the GTCNT Counter ............................................................... 644
23.10.5
Priority Order of Each Event ...................................................................................... 645
PWM Delay Generation Circuit .................................................................................................... 646
24.1
Overview ............................................................................................................................ 646
24.2
Register Descriptions ......................................................................................................... 647
24.2.1
PWM Output Delay Control Register (GTDLYCR) .................................................... 647
24.2.2
PWM Output Delay Control Register 2 (GTDLYCR2) ............................................... 647
24.2.3
GTIOCnA Rising Output Delay Register (GTDLYRnA) (n = 0 to 3) .......................... 649
24.2.4
GTIOCnA Falling Output Delay Register (GTDLYFnA) (n = 0 to 3) .......................... 650
24.2.5
GTIOCnB Rising Output Delay Register (GTDLYRnB) (n = 0 to 3) .......................... 651
24.2.6
GTIOCnB Falling Output Delay Register (GTDLYFnB) (n = 0 to 3) .......................... 652
24.3
24.3.1
Adjustments to the Timing of Rising and Falling Edges in PWM Waveforms ........... 652
24.3.2
Timing for Transfer of GTDLYRnA, GTLDYRnB, GTDLYFnA, and GTDLYFnB Register
Settings ...................................................................................................................... 654
24.4
25.
Operation ........................................................................................................................... 652
Usage Notes ...................................................................................................................... 655
24.4.1
Module-Stop Function Settings ................................................................................. 655
24.4.2
Notes on Delay Settings for PWM Delay Generation Circuit ..................................... 655
Asynchronous General-Purpose Timer (AGT) ............................................................................. 657
25.1
Overview ............................................................................................................................ 657
25.2
Register Descriptions ......................................................................................................... 659
25.2.1
AGT Counter Register (AGT) .................................................................................... 659
25.2.2
AGT Compare Match A Register (AGTCMA) ............................................................ 659
25.2.3
AGT Compare Match B Register (AGTCMB) ............................................................ 660
25.2.4
AGT Control Register (AGTCR) ................................................................................ 660
25.2.5
AGT Mode Register 1 (AGTMR1) ............................................................................. 662
25.2.6
AGT Mode Register 2 (AGTMR2) ............................................................................. 663
25.2.7
AGT I/O Control Register (AGTIOC) ......................................................................... 663
25.2.8
AGT Event Pin Select Register (AGTISR) ................................................................. 664
25.2.9
AGT Compare Match Function Select Register (AGTCMSR) ................................... 665
25.2.10
AGT Pin Select Register (AGTIOSEL) ...................................................................... 665
25.3
Operation ........................................................................................................................... 666
25.3.1
Reload Register and Counter Rewrite Operation ...................................................... 666
25.3.2
Reload Register and Compare Register A/B Rewrite Operation ............................... 668
25.3.3
Timer Mode ............................................................................................................... 669
25.3.4
Pulse Output Mode .................................................................................................... 670
25.3.5
Event Counter Mode .................................................................................................. 671
25.3.6
Pulse Width Measurement Mode .............................................................................. 672
25.3.7
Pulse Period Measurement Mode ............................................................................. 673
25.3.8
Compare Match Function .......................................................................................... 674
25.3.9
Output Settings for Each Mode ................................................................................. 675
25.3.10
Standby Mode ........................................................................................................... 677
25.3.11
Interrupt Sources ....................................................................................................... 677
25.3.12
Event Signal Output to ELC ....................................................................................... 678
25.4
Usage Notes ...................................................................................................................... 678
25.4.1
Count Operation Start and Stop Control .................................................................... 678
25.4.2
Access to Counter Register ....................................................................................... 679
26.
25.4.3
When Changing Mode ............................................................................................... 679
25.4.4
Digital Filter ................................................................................................................ 679
25.4.5
How to Calculate Event Number, Pulse Width, and Pulse Period ............................. 679
25.4.6
When Count Is Forcibly Stopped by TSTOP Bit ........................................................ 679
25.4.7
When Selecting AGT0 Underflow as the Count Source ............................................ 679
25.4.8
Reset of I/O Register ................................................................................................. 680
25.4.9
When Selecting PCLKB, PCLKB/8, or PCLKB/2 as the Count Source ..................... 680
25.4.10
When Selecting AGTSCLK or AGTLCLK as the Count Source ................................ 680
25.4.11
When Switching Source Clock .................................................................................. 680
Realtime Clock (RTC) .................................................................................................................. 681
26.1
Overview ............................................................................................................................ 681
26.2
Register Descriptions ......................................................................................................... 683
26.2.1
64-Hz Counter (R64CNT) .......................................................................................... 683
26.2.2
Second Counter (RSECCNT)/Binary Counter 0 (BCNT0) ......................................... 683
26.2.3
Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1) ........................................... 684
26.2.4
Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2) ............................................... 685
26.2.5
Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3) .................................. 686
26.2.6
Day Counter (RDAYCNT) .......................................................................................... 687
26.2.7
Month Counter (RMONCNT) ..................................................................................... 687
26.2.8
Year Counter (RYRCNT) ........................................................................................... 688
26.2.9
Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register (BCNT0AR) .. 688
26.2.10
Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR) .... 689
26.2.11
Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register (BCNT2AR) ......... 690
26.2.12
Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register (BCNT3AR)
................................................................................................................................... 691
26.2.13
Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register (BCNT0AER)
................................................................................................................................... 692
26.2.14
Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register
(BCNT1AER) ............................................................................................................. 693
26.2.15
Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register (BCNT2AER)
................................................................................................................................... 694
26.2.16
Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable Register
(BCNT3AER) ............................................................................................................. 695
26.2.17
RTC Control Register 1 (RCR1) ................................................................................ 696
26.2.18
RTC Control Register 2 (RCR2) ................................................................................ 697
26.2.19
RTC Control Register 4 (RCR4) ................................................................................ 700
26.2.20
Frequency Register (RFRH/RFRL) ........................................................................... 701
26.2.21
Time Error Adjustment Register (RADJ) .................................................................... 702
26.2.22
Time Capture Control Register y (RTCCRy) (y = 0 to 2) ........................................... 702
26.2.23
Second Capture Register y (RSECCPy) (y = 0 to 2)/BCNT0 Capture Register y
(BCNT0CPy) (y = 0 to 2) ........................................................................................... 704
26.2.24
Minute Capture Register y (RMINCPy) (y = 0 to 2)/BCNT1 Capture Register y
(BCNT1CPy) (y = 0 to 2) ........................................................................................... 704
26.2.25
Hour Capture Register y (RHRCPy) (y = 0 to 2)/BCNT2 Capture Register y (BCNT2CPy)
(y = 0 to 2) ................................................................................................................. 705
26.2.26
Date Capture Register y (RDAYCPy) (y = 0 to 2)/BCNT3 Capture Register y
(BCNT3CPy) (y = 0 to 2) ........................................................................................... 706
26.2.27
Month Capture Register y (RMONCPy) (y = 0 to 2) .................................................. 707
26.3
Operation ........................................................................................................................... 707
26.3.1
Outline of Initial Settings of Registers after Power On .............................................. 707
26.3.2
Clock and Count Mode Setting Procedure ................................................................ 708
26.3.3
Setting the Time ........................................................................................................ 708
26.3.4
30-Second Adjustment .............................................................................................. 709
26.3.5
Reading 64-Hz Counter and Time ............................................................................. 710
26.3.6
Alarm Function .......................................................................................................... 711
26.3.7
Procedure for Disabling Alarm Interrupt .................................................................... 712
26.3.8
Time Error Adjustment Function ................................................................................ 712
26.3.8.1
Automatic adjustment ........................................................................................ 712
26.3.8.2
Adjustment by software ..................................................................................... 713
26.3.8.3
Procedure for changing the mode of adjustment .............................................. 713
26.3.8.4
Procedure for stopping adjustment ................................................................... 714
26.3.8.5
Capturing the time ............................................................................................. 714
26.4
Interrupt Sources ............................................................................................................... 715
26.5
Event Link Output .............................................................................................................. 716
26.5.1
26.6
27.
Interrupt Handling and Event Linking ........................................................................ 717
Usage Notes ...................................................................................................................... 717
26.6.1
Register Writing during Counting ............................................................................... 717
26.6.2
Use of Periodic Interrupts .......................................................................................... 717
26.6.3
RTCOUT (1-Hz/64-Hz) Clock Output ........................................................................ 718
26.6.4
Transitions to Low Power Modes after Setting Registers .......................................... 718
26.6.5
Notes on Writing to and Reading from Registers ...................................................... 718
26.6.6
Changing the Count Mode ......................................................................................... 718
26.6.7
Initialization Procedure when the Realtime Clock Is Not To Be Used ....................... 718
26.6.8
When Switching Source Clock .................................................................................. 719
Watchdog Timer (WDT) ............................................................................................................... 720
27.1
Overview ............................................................................................................................ 720
27.2
Register Descriptions ......................................................................................................... 721
27.2.1
WDT Refresh Register (WDTRR) .............................................................................. 721
27.2.2
WDT Control Register (WDTCR) ............................................................................... 722
27.2.3
WDT Status Register (WDTSR) ................................................................................ 724
27.2.4
WDT Reset Control Register (WDTRCR) .................................................................. 725
27.2.5
WDT Count Stop Control Register (WDTCSTPR) ..................................................... 726
27.2.6
Option Function Select Register 0 (OFS0) ................................................................ 726
27.3
Operation ........................................................................................................................... 726
27.3.1
Count Operation in Each Start Mode ......................................................................... 726
27.3.1.1
Register start mode ........................................................................................... 726
27.3.1.2
Auto start mode ................................................................................................. 728
27.3.2
Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers .............. 729
27.3.3
Refresh Operation ..................................................................................................... 730
27.3.4
Reset Output ............................................................................................................. 731
27.3.5
Interrupt Sources ....................................................................................................... 731
27.3.6
Reading the Down-Counter Value ............................................................................. 731
27.3.7
Association between Option Function Select Register 0 (OFS0) and WDT Registers
.................................................................................................................................... 732
27.4
Link Operation by ELC ....................................................................................................... 732
27.5
Usage Notes ...................................................................................................................... 732
27.5.1
28.
Independent Watchdog Timer (IWDT) ......................................................................................... 733
28.1
Overview ............................................................................................................................ 733
28.2
Register Descriptions ......................................................................................................... 734
28.2.1
IWDT Refresh Register (IWDTRR) ............................................................................ 734
28.2.2
IWDT Status Register (IWDTSR) .............................................................................. 735
28.2.3
Option Function Select Register 0 (OFS0) ................................................................ 736
28.3
29.
ICU Event Link Setting Register n (IELSRn) Setting ................................................. 732
Operation ........................................................................................................................... 738
28.3.1
Auto Start Mode ......................................................................................................... 738
28.3.2
Refresh Operation ..................................................................................................... 739
28.3.3
Status Flags ............................................................................................................... 740
28.3.4
Reset Output ............................................................................................................. 741
28.3.5
Interrupt Sources ....................................................................................................... 741
28.3.6
Reading the Down-Counter Value ............................................................................. 741
28.4
Output to the Event Link Controller (ELC) ......................................................................... 741
28.5
Usage Notes ...................................................................................................................... 742
28.5.1
Refresh Operations ................................................................................................... 742
28.5.2
Constraints on the Clock Division Ratio Setting ........................................................ 742
Ethernet MAC Controller (ETHERC) ............................................................................................ 743
29.1
Overview ............................................................................................................................ 743
29.2
Register Descriptions ......................................................................................................... 747
29.2.1
ETHERC Mode Register (ECMR) ............................................................................. 747
29.2.2
Receive Frame Maximum Length Register (RFLR) .................................................. 749
29.2.3
ETHERC Status Register (ECSR) ............................................................................. 750
29.2.4
ETHERC Interrupt Enable Register (ECSIPR) .......................................................... 751
29.2.5
PHY Interface Register (PIR) .................................................................................... 752
29.2.6
PHY Status Register (PSR) ....................................................................................... 752
29.2.7
Random Number Generation Counter Upper Limit Setting Register (RDMLR) ........ 753
29.2.8
Interpacket Gap Register (IPGR) .............................................................................. 753
29.2.9
Automatic PAUSE Frame Register (APR) ................................................................. 754
29.2.10
Manual PAUSE Frame Register (MPR) ..................................................................... 754
29.2.11
Received PAUSE Frame Counter (RFCF) ................................................................ 755
29.2.12
PAUSE Frame Retransmit Count Setting Register (TPAUSER) ................................ 755
29.2.13
PAUSE Frame Retransmit Counter (TPAUSECR) .................................................... 756
29.2.14
Broadcast Frame Receive Count Setting Register (BCFRR) .................................... 756
29.2.15
MAC Address Upper Bit Register (MAHR) ................................................................ 757
29.2.16
MAC Address Lower Bit Register (MALR) ................................................................. 757
29.2.17
Transmit Retry Over Counter Register (TROCR) ...................................................... 758
29.2.18
Late Collision Detect Counter Register (CDCR) ........................................................ 758
29.2.19
Lost Carrier Counter Register (LCCR) ...................................................................... 759
29.2.20
Carrier Not Detect Counter Register (CNDCR) ......................................................... 759
29.2.21
CRC Error Frame Receive Counter Register (CEFCR) ............................................ 760
29.2.22
Frame Receive Error Counter Register (FRECR) ..................................................... 760
29.2.23
Too-Short Frame Receive Counter Register (TSFRCR) ........................................... 761
29.2.24
Too-Long Frame Receive Counter Register (TLFRCR) ............................................ 761
29.2.25
Received Alignment Error Frame Counter Register (RFCR) ..................................... 762
29.2.26
Multicast Address Frame Receive Counter Register (MAFCR) ................................ 762
29.3
Operation ........................................................................................................................... 763
29.3.1
Transmission ............................................................................................................. 763
29.3.2
Reception .................................................................................................................. 764
29.3.3
Frame Timing ............................................................................................................ 765
29.3.3.1
MII frame timing ................................................................................................. 765
29.3.3.2
RMII frame timing .............................................................................................. 767
29.3.4
Accessing the MII and RMII Registers ...................................................................... 768
29.3.4.1
MII and RMII management frame format .......................................................... 768
29.3.4.2
MII and RMII register access procedure ........................................................... 768
29.3.5
Magic Packet Detection ............................................................................................. 770
29.3.5.1
29.3.6
Adjusting Transmission Efficiency by Changing the IPG ........................................... 770
29.3.7
Flow Control .............................................................................................................. 771
29.3.7.1
Automatic PAUSE frame transmission .............................................................. 771
29.3.7.2
Manual PAUSE frame transmission .................................................................. 772
29.3.7.3
PAUSE frame reception .................................................................................... 772
29.3.8
30.
Constraints on Magic Packet detection ............................................................. 770
MAC Filter .................................................................................................................. 772
29.4
Interrupts ............................................................................................................................ 772
29.5
Usage Notes ...................................................................................................................... 772
29.5.1
Preventing the LCHNG Flag from Erroneously Setting to 1 ...................................... 772
29.5.2
Input to RMII0_RX_ER Pin While RMII Is Selected .................................................. 772
29.5.3
Collision Occurrence in Half-Duplex Mode ................................................................ 772
Ethernet DMA Controller (EDMAC) ............................................................................................. 773
30.1
Overview ............................................................................................................................ 773
30.2
Register Descriptions ......................................................................................................... 775
30.2.1
EDMAC Mode Register (EDMR) ............................................................................... 775
30.2.2
EDMAC Transmit Request Register (EDTRR) .......................................................... 776
30.2.3
EDMAC Receive Request Register (EDRRR) ........................................................... 776
30.2.4
Transmit Descriptor List Start Address Register (TDLAR) ......................................... 777
30.2.5
Receive Descriptor List Start Address Register (RDLAR) ......................................... 777
30.2.6
ETHERC/EDMAC Status Register (EESR) ............................................................... 778
30.2.7
ETHERC/EDMAC Status Interrupt Enable Register (EESIPR) ................................. 781
30.2.8
ETHERC/EDMAC Transmit/Receive Status Copy Enable Register (TRSCER) ........ 782
30.2.9
Missed-Frame Counter Register (RMFCR) ............................................................... 783
30.2.10
Transmit FIFO Threshold Register (TFTR) ................................................................ 784
30.2.11
FIFO Depth Register (FDR) ....................................................................................... 785
30.2.12
Receive Method Control Register (RMCR) ............................................................... 785
30.2.13
Transmit FIFO Underflow Counter (TFUCR) ............................................................. 786
30.2.14
Receive FIFO Overflow Counter (RFOCR) ............................................................... 786
30.2.15
Independent Output Signal Setting Register (IOSR) ................................................. 787
30.2.16
Flow Control Start FIFO Threshold Setting Register (FCFTR) .................................. 788
30.2.17
Receive Data Padding Insert Register (RPADIR) ...................................................... 789
30.2.18
Transmit Interrupt Setting Register (TRIMD) ............................................................. 790
30.2.19
Receive Buffer Write Address Register (RBWAR) .................................................... 790
30.2.20
Receive Descriptor Fetch Address Register (RDFAR) .............................................. 791
30.2.21
Transmit Buffer Read Address Register (TBRAR) .................................................... 791
30.2.22
Transmit Descriptor Fetch Address Register (TDFAR) .............................................. 792
30.3
Operation ........................................................................................................................... 792
30.3.1
31.
Descriptor Lists and Data Buffers .............................................................................. 792
30.3.1.1
Transmit descriptor ............................................................................................ 792
30.3.1.2
Receive descriptor ............................................................................................. 794
30.3.2
Transmission ............................................................................................................. 796
30.3.3
Reception .................................................................................................................. 797
30.3.4
Multi-Buffer Frame Transmission .............................................................................. 798
30.3.4.1
Error processing while transmitting multi-buffer frame ...................................... 798
30.3.4.2
Error processing while receiving multi-buffer frame .......................................... 799
30.4
Interrupts ............................................................................................................................ 800
30.5
Usage Notes ...................................................................................................................... 800
30.5.1
Settings for the Module-Stop Function ...................................................................... 800
30.5.2
Stopping the EDMAC during Operation ..................................................................... 800
USB 2.0 Full-Speed Module (USBFS) ......................................................................................... 801
31.1
Overview ............................................................................................................................ 801
31.2
Register Descriptions ......................................................................................................... 803
31.2.1
System Configuration Control Register (SYSCFG) ................................................... 803
31.2.2
System Configuration Status Register 0 (SYSSTS0) ................................................ 804
31.2.3
Device State Control Register 0 (DVSTCTR0) .......................................................... 805
31.2.4
CFIFO Port Register (CFIFO/CFIFOL)
D0FIFO Port Register (D0FIFO/D0FIFOL)
D1FIFO Port Register (D1FIFO/D1FIFOL) ................................................................ 807
31.2.5
CFIFO Port Select Register (CFIFOSEL)
D0FIFO Port Select Register (D0FIFOSEL)
D1FIFO Port Select Register (D1FIFOSEL) .............................................................. 809
31.2.6
CFIFO Port Control Register (CFIFOCTR)
D0FIFO Port Control Register (D0FIFOCTR)
D1FIFO Port Control Register (D1FIFOCTR) ............................................................ 812
31.2.7
Interrupt Enable Register 0 (INTENB0) ..................................................................... 814
31.2.8
Interrupt Enable Register 1 (INTENB1) ..................................................................... 815
31.2.9
BRDY Interrupt Enable Register (BRDYENB) ........................................................... 815
31.2.10
NRDY Interrupt Enable Register (NRDYENB) .......................................................... 816
31.2.11
BEMP Interrupt Enable Register (BEMPENB) .......................................................... 817
31.2.12
SOF Output Configuration Register (SOFCFG) ........................................................ 818
31.2.13
Interrupt Status Register 0 (INTSTS0) ....................................................................... 818
31.2.14
Interrupt Status Register 1 (INTSTS1) ....................................................................... 821
31.2.15
BRDY Interrupt Status Register (BRDYSTS) ............................................................ 823
31.2.16
NRDY Interrupt Status Register (NRDYSTS) ............................................................ 824
31.2.17
BEMP Interrupt Status Register (BEMPSTS) ............................................................ 824
31.2.18
Frame Number Register (FRMNUM) ......................................................................... 825
31.2.19
Device State Change Register (DVCHGR) ............................................................... 826
31.2.20
USB Address Register (USBADDR) .......................................................................... 826
31.2.21
USB Request Type Register (USBREQ) ................................................................... 827
31.2.22
USB Request Value Register (USBVAL) ................................................................... 828
31.2.23
USB Request Index Register (USBINDX) ................................................................. 828
31.2.24
USB Request Length Register (USBLENG) .............................................................. 829
31.2.25
DCP Configuration Register (DCPCFG) .................................................................... 829
31.2.26
DCP Maximum Packet Size Register (DCPMAXP) ................................................... 830
31.2.27
DCP Control Register (DCPCTR) .............................................................................. 831
31.2.28
Pipe Window Select Register (PIPESEL) .................................................................. 834
31.2.29
Pipe Configuration Register (PIPECFG) ................................................................... 834
31.2.30
Pipe Maximum Packet Size Register (PIPEMAXP) ................................................... 836
31.2.31
Pipe Cycle Control Register (PIPEPERI) .................................................................. 837
31.2.32
PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) .................................................... 838
31.2.33
PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 1 to 5) ..................... 844
31.2.34
PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5) ................................. 845
31.2.35
Device Address n Configuration Register (DEVADDn) (n = 0 to 5) ........................... 846
31.2.36
PHY Cross Point Adjustment Register (PHYSLEW) ................................................. 846
31.2.37
Deep Software Standby USB Transceiver Control/Pin Monitor Register (DPUSR0R)
.................................................................................................................................... 847
31.2.38
Deep Software Standby USB Suspend/Resume Interrupt Register (DPUSR1R) .... 848
31.3
Operation ........................................................................................................................... 850
31.3.1
System Control .......................................................................................................... 850
31.3.1.1
Setting data to the USBFS registers ................................................................. 850
31.3.1.2
Selecting the controller function ........................................................................ 850
31.3.1.3
Controlling the USB data bus using resistors .................................................... 850
31.3.1.4
Example external connection circuits ................................................................ 850
31.3.1.5
Release from deep software standby mode because of USB suspend/resume interrupts .................................................................................................................. 855
31.3.2
Interrupts ................................................................................................................... 858
31.3.3
Interrupt Descriptions ................................................................................................ 861
31.3.3.1
BRDY interrupt .................................................................................................. 861
31.3.3.2
NRDY interrupt .................................................................................................. 864
31.3.3.3
BEMP interrupt .................................................................................................. 866
31.3.3.4
Device state transition interrupt (device controller mode) ................................. 867
31.3.3.5
Control transfer stage transition interrupt (device controller mode) .................. 868
31.3.3.6
Frame update interrupt ...................................................................................... 869
31.3.3.7
VBUS interrupt .................................................................................................. 869
31.3.3.8
Resume interrupt ............................................................................................... 869
31.3.3.9
OVRCR interrupt ............................................................................................... 869
31.3.3.10
BCHG interrupt .................................................................................................. 869
31.3.3.11
DTCH interrupt .................................................................................................. 869
31.3.3.12
SACK interrupt .................................................................................................. 869
31.3.3.13
SIGN interrupt ................................................................................................... 869
31.3.3.14
ATTCH interrupt ................................................................................................ 870
31.3.3.15
EOFERR interrupt ............................................................................................. 870
31.3.4
Pipe Control ............................................................................................................... 870
31.3.4.1
Pipe control register switching procedures ........................................................ 872
31.3.4.2
Transfer types ................................................................................................... 872
31.3.4.3
Endpoint number ............................................................................................... 872
31.3.4.4
Maximum packet size setting ............................................................................ 873
31.3.4.5
Transaction counter for pipes 1 to 5 in the receiving direction .......................... 873
31.3.4.6
Response PID ................................................................................................... 873
31.3.4.7
Data PID sequence bit ...................................................................................... 874
31.3.4.8
Response PID = NAK function .......................................................................... 874
31.3.4.9
Auto response mode ......................................................................................... 875
31.3.4.10
OUT-NAK mode ................................................................................................ 875
31.3.4.11
Null auto response mode .................................................................................. 875
31.3.5
FIFO Buffer ................................................................................................................ 875
31.3.6
FIFO Buffer Clearing ................................................................................................. 876
31.3.7
FIFO Port Functions .................................................................................................. 876
31.3.8
DMA Transfers (D0FIFO and D1FIFO Ports) ............................................................ 877
31.3.9
Control Transfers Using the DCP .............................................................................. 878
31.3.9.1
Control transfers in host controller mode .......................................................... 878
31.3.9.2
Control transfers in device controller mode ....................................................... 879
31.3.10
Bulk Transfers (Pipes 1 to 5) ..................................................................................... 880
31.3.11
Interrupt Transfers (Pipes 6 to 9) ............................................................................... 880
31.3.11.1
31.3.12
Isochronous Transfers (Pipes 1 and 2) ..................................................................... 880
31.3.12.1
Error detection in isochronous transfers ............................................................ 881
31.3.12.2
DATA-PID .......................................................................................................... 882
31.3.12.3
Interval counter .................................................................................................. 882
31.3.13
SOF Interpolation Function ........................................................................................ 887
31.3.14
Pipe Schedule ........................................................................................................... 888
31.4
32.
Interval counter for interrupt transfers in host controller mode .......................... 880
31.3.14.1
Conditions for generating transactions .............................................................. 888
31.3.14.2
Transfer schedule .............................................................................................. 888
31.3.14.3
Enabling USB communication ........................................................................... 889
Usage Notes ...................................................................................................................... 889
31.4.1
Settings for the Module-Stop State ............................................................................ 889
31.4.2
Clearing the Interrupt Status Register on Exiting Software Standby Mode ............... 889
31.4.3
Clearing the Interrupt Status Register after Setting Up the Port Function ................. 889
Serial Communications Interface (SCI) ........................................................................................ 890
32.1
Overview ............................................................................................................................ 890
32.2
Register Descriptions ......................................................................................................... 894
32.2.1
Receive Shift Register (RSR) .................................................................................... 894
32.2.2
Receive Data Register (RDR) ................................................................................... 894
32.2.3
Receive 9-Bit Data Register (RDRHL) ...................................................................... 895
32.2.4
Receive FIFO Data Register H, L, HL (FRDRH, FRDRL, FRDRHL) ......................... 896
32.2.5
Transmit Data Register (TDR) ................................................................................... 897
32.2.6
Transmit 9-Bit Data Register (TDRHL) ...................................................................... 897
32.2.7
Transmit FIFO Data Register H, L, HL (FTDRH, FTDRL, FTDRHL) ......................... 898
32.2.8
Transmit Shift Register (TSR) ................................................................................... 899
32.2.9
Serial Mode Register (SMR) for Non-Smart Card Interface Mode
(SCMR.SMIF = 0) ..................................................................................................... 899
32.2.10
Serial Mode Register for Smart Card Interface Mode (SMR_SMCI) (SCMR.SMIF = 1)
.................................................................................................................................... 900
32.2.11
Serial Control Register (SCR) for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
.................................................................................................................................... 902
32.2.12
Serial Control Register for Smart Card Interface Mode (SCR_SMCI) (SCMR.SMIF = 1)
................................................................................................................................... 904
32.2.13
Serial Status Register (SSR) for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) ................................................................................ 905
32.2.14
Serial Status Register for Non-Smart Card Interface and FIFO Mode (SSR_FIFO) (SCMR.SMIF = 0 and FCR.FM = 1) ................................................................................ 908
32.2.15
Serial Status Register for Smart Card Interface Mode (SSR_SMCI) (SCMR.SMIF = 1) .
911
32.2.16
Smart Card Mode Register (SCMR) .......................................................................... 913
32.2.17
Bit Rate Register (BRR) ............................................................................................ 914
32.2.18
Modulation Duty Register (MDDR) ............................................................................ 924
32.2.19
Serial Extended Mode Register (SEMR) ................................................................... 926
32.2.20
Noise Filter Setting Register (SNFR) ......................................................................... 928
32.2.21
IIC Mode Register 1 (SIMR1) .................................................................................... 928
32.2.22
IIC Mode Register 2 (SIMR2) .................................................................................... 929
32.2.23
IIC Mode Register 3 (SIMR3) .................................................................................... 930
32.2.24
IIC Status Register (SISR) ......................................................................................... 932
32.2.25
SPI Mode Register (SPMR) ....................................................................................... 932
32.2.26
FIFO Control Register (FCR) ..................................................................................... 934
32.2.27
FIFO Data Count Register (FDR) .............................................................................. 935
32.2.28
Line Status Register (LSR) ........................................................................................ 936
32.2.29
Compare Match Data Register (CDR) ....................................................................... 936
32.2.30
Data Compare Match Control Register (DCCR) ........................................................ 937
32.2.31
Serial Port Register (SPTR) ...................................................................................... 938
32.3
Operation in Asynchronous Mode ..................................................................................... 939
32.3.1
Serial Data Transfer Format ...................................................................................... 939
32.3.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ....... 941
32.3.3
Clock .......................................................................................................................... 942
32.3.4
Double-Speed Operation and Frequency of 6 Times the Bit Rate ............................ 942
32.3.5
CTS and RTS Functions ............................................................................................ 943
32.3.6
Address Match (Receive Data Match Detection) Function ........................................ 943
32.3.7
SCI Initialization in Asynchronous Mode ................................................................... 947
32.3.8
Serial Data Transmission in Asynchronous Mode ..................................................... 948
32.3.9
Serial Data Reception in Asynchronous Mode .......................................................... 953
32.4
Multi-Processor Communication Function ......................................................................... 960
32.4.1
Multi-Processor Serial Data Transmission ................................................................ 961
32.4.2
Multi-Processor Serial Data Reception ...................................................................... 964
32.5
Operation in Clock Synchronous Mode ............................................................................. 968
32.5.1
Clock .......................................................................................................................... 969
32.5.2
CTS and RTS Functions ............................................................................................ 969
32.5.3
SCI Initialization in Clock Synchronous Mode ........................................................... 970
32.5.4
Serial Data Transmission in Clock Synchronous Mode ............................................. 972
32.5.5
Serial Data Reception in Clock Synchronous Mode .................................................. 976
32.5.6
Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode
.................................................................................................................................... 981
32.6
Operation in Smart Card Interface Mode ........................................................................... 983
32.6.1
Example Connection ................................................................................................. 983
32.6.2
Data Format (Except in Block Transfer Mode) .......................................................... 984
32.6.3
Block Transfer Mode ................................................................................................. 985
32.6.4
Receive Data Sampling Timing and Reception Margin ............................................. 985
32.6.5
Initialization of the SCI ............................................................................................... 986
32.6.6
Serial Data Transmission (Except in Block Transfer Mode) ...................................... 988
32.6.7
Serial Data Reception (Except in Block Transfer Mode) ........................................... 990
32.6.8
Clock Output Control ................................................................................................. 992
32.7
Operation in Simple IIC Mode ............................................................................................ 992
32.7.1
Generation of Start, Restart, and Stop Conditions .................................................... 993
32.7.2
Clock Synchronization ............................................................................................... 994
32.7.3
SDA Output Delay ..................................................................................................... 995
32.7.4
SCI Initialization in Simple IIC Mode ......................................................................... 996
32.7.5
Operation in Master Transmission in Simple IIC Mode ............................................. 997
32.7.6
Master Reception in Simple IIC Mode ..................................................................... 1000
32.8
Operation in Simple SPI Mode ........................................................................................ 1002
32.8.1
States of Pins in Master and Slave Modes .............................................................. 1002
32.8.2
SS Function in Master Mode ................................................................................... 1003
32.8.3
SS Function in Slave Mode ..................................................................................... 1003
32.8.4
Relationship between Clock and Transmit/Receive Data ........................................ 1003
32.8.5
SCI Initialization in Simple SPI Mode ...................................................................... 1004
32.8.6
Transmission and Reception of Serial Data in Simple SPI Mode ............................ 1004
32.9
Bit Rate Modulation Function ........................................................................................... 1004
32.10
Interrupt Sources ............................................................................................................. 1005
32.10.1
Buffer Operation for SCIn_TXI and SCIn_RXI Interrupts (non-FIFO selected) ....... 1005
32.10.2
Buffer Operation for SCIn_TXI and SCIn_RXI Interrupts (FIFO selected) .............. 1005
32.10.3
Interrupts in Asynchronous, Clock Synchronous, and Simple SPI Modes .............. 1005
32.10.4
Interrupts in Smart Card Interface Mode ................................................................. 1007
32.10.5
Interrupts in Simple IIC Mode .................................................................................. 1007
32.11
Event Linking ................................................................................................................... 1008
32.12
Address mismatch event output (SCI0_DCUF) ............................................................... 1009
32.13
Noise Cancellation Function ............................................................................................ 1009
32.14
Usage Notes .................................................................................................................... 1010
32.14.1
Settings for the Module-Stop Function .................................................................... 1010
32.14.2
SCI Operation during Low Power State ................................................................... 1010
32.14.3
Break Detection and Processing ............................................................................. 1014
32.14.4
Mark State and Production of Breaks ...................................................................... 1015
32.14.5
Receive Error Flags and Transmit Operation in Clock Synchronous and Simple SPI
Modes ...................................................................................................................... 1015
32.14.6
Restrictions on Clock Synchronous Transmission in Clock Synchronous and Simple SPI
Modes ...................................................................................................................... 1015
32.14.7
Restrictions on Using DMAC or DTC ...................................................................... 1016
32.14.8
Notes on Starting Transfer ...................................................................................... 1017
32.14.9
External Clock Input in Clock Synchronous and Simple SPI Modes ....................... 1017
32.14.10 Limitations on Simple SPI Mode .............................................................................. 1017
33.
IrDA Interface ............................................................................................................................. 1019
33.1
Overview .......................................................................................................................... 1019
33.2
Register Descriptions ....................................................................................................... 1020
33.2.1
33.3
Operation ......................................................................................................................... 1021
33.3.1
IrDA Interface Setup Procedure .............................................................................. 1021
33.3.2
Transmission ........................................................................................................... 1021
33.3.3
Reception ................................................................................................................ 1021
33.4
34.
IrDA Control Register (IRCR) .................................................................................. 1020
Usage Notes .................................................................................................................... 1022
33.4.1
Settings for the Module-Stop Function .................................................................... 1022
33.4.2
Asynchronous Reference Clock for SCI1 ................................................................ 1022
I2C Bus Interface (IIC) ................................................................................................................ 1023
34.1
Overview .......................................................................................................................... 1023
34.2
Register Descriptions ....................................................................................................... 1026
34.2.1
I2C Bus Control Register 1 (ICCR1) ........................................................................ 1026
34.2.2
I2C Bus Control Register 2 (ICCR2) ........................................................................ 1028
34.2.3
I2C Bus Mode Register 1 (ICMR1) .......................................................................... 1031
34.2.4
I2C Bus Mode Register 2 (ICMR2) .......................................................................... 1032
34.2.5
I2C Bus Mode Register 3 (ICMR3) .......................................................................... 1033
34.2.6
I2C Bus Function Enable Register (ICFER) ............................................................. 1035
34.2.7
I2C Bus Status Enable Register (ICSER) ................................................................ 1036
34.2.8
I2C Bus Interrupt Enable Register (ICIER) .............................................................. 1037
34.2.9
I2C Bus Status Register 1 (ICSR1) .......................................................................... 1038
34.2.10
I2C Bus Status Register 2 (ICSR2) .......................................................................... 1041
34.2.11
I2C Bus Wakeup Unit Register (ICWUR) ................................................................. 1044
34.2.12
I2C-Bus Wakeup Unit Register 2 (ICWUR2) ............................................................ 1045
34.2.13
Slave Address Register L y (SARLy) (y = 0 to 2) .................................................... 1046
34.2.14
Slave Address Register U y (SARUy) (y = 0 to 2) ................................................... 1046
34.2.15
I2C Bus Bit Rate Low-Level Register (ICBRL) ......................................................... 1047
34.2.16
I2C Bus Bit Rate High-Level Register (ICBRH) ....................................................... 1047
34.2.17
I2C Bus Transmit Data Register (ICDRT) ................................................................ 1049
34.2.18
I2C Bus Receive Data Register (ICDRR) ................................................................ 1049
34.2.19
I2C Bus Shift Register (ICDRS) ............................................................................... 1049
34.3
Operation ......................................................................................................................... 1049
34.3.1
Communication Data Format ................................................................................... 1049
34.3.2
Initial Settings .......................................................................................................... 1050
34.3.3
Master Transmit Operation ...................................................................................... 1051
34.3.4
Master Receive Operation ....................................................................................... 1055
34.3.5
Slave Transmit Operation ........................................................................................ 1060
34.3.6
Slave Receive Operation ......................................................................................... 1063
34.4
SCL Synchronization Circuit ............................................................................................ 1065
34.5
SDA Output Delay Function ............................................................................................. 1066
34.6
Digital Noise Filter Circuits ............................................................................................... 1067
34.7
Address Match Detection ................................................................................................. 1067
34.7.1
Slave-Address Match Detection .............................................................................. 1067
34.7.2
Detection of General Call Address .......................................................................... 1069
34.7.3
Device ID Address Detection ................................................................................... 1070
34.7.4
Host Address Detection ........................................................................................... 1071
34.8
Wakeup Function ............................................................................................................. 1071
34.8.1
Normal Wakeup Mode 1 .......................................................................................... 1072
34.8.2
Normal Wakeup Mode 2 .......................................................................................... 1075
34.8.3
Command Recovery Mode and EEP Response Mode (Special Wakeup Modes) .. 1077
34.8.4
Precautions for WFI Instruction Execution .............................................................. 1080
34.9
Automatic Low-Hold Function for SCL ............................................................................. 1080
34.9.1
Function to Prevent Wrong Transmission of Transmit Data .................................... 1080
34.9.2
NACK Reception Transfer Suspension Function .................................................... 1081
34.9.3
Function to Prevent Failure to Receive Data ........................................................... 1082
34.10
Arbitration-Lost Detection Functions ................................................................................ 1084
34.10.1
Master Arbitration-Lost Detection (MALE Bit) .......................................................... 1084
34.10.2
Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) ....... 1086
34.10.3
Slave Arbitration-Lost Detection (SALE Bit) ............................................................ 1087
34.11
Start, Restart, and Stop Condition Issuing Function ........................................................ 1087
34.11.1
Issuing a Start Condition ......................................................................................... 1087
34.11.2
Issuing a Restart Condition ..................................................................................... 1088
34.11.3
Issuing a Stop Condition .......................................................................................... 1089
34.12
Bus Hanging .................................................................................................................... 1090
34.12.1
Timeout Function ..................................................................................................... 1090
34.12.2
Extra SCL Clock Cycle Output Function .................................................................. 1091
34.12.3
IIC Reset and Internal Reset ................................................................................... 1092
34.13
SMBus Operation ............................................................................................................ 1092
34.13.1
SMBus Timeout Measurement ................................................................................ 1093
34.13.2
Packet Error Code (PEC) ........................................................................................ 1094
34.13.3
SMBus Host Notification Protocol (Notify ARP Master Command) ......................... 1094
34.14
Interrupt Sources ............................................................................................................. 1094
34.14.1
Buffer Operation for IICn_TXI and IICn_RXI Interrupts ........................................... 1095
34.15
State of Registers when Issuing each Condition ............................................................. 1095
34.16
Output to the Event Link Controller (ELC) ....................................................................... 1097
34.16.1
34.17
Interrupt Handling and Event Linking ...................................................................... 1097
Usage Notes .................................................................................................................... 1097
34.17.1
Settings for the Module-Stop Function .................................................................... 1097
34.17.2
Starting Transfer after an Interrupt Occurrence ....................................................... 1097
35.
Controller Area Network (CAN) Module ..................................................................................... 1098
35.1
Overview .......................................................................................................................... 1098
35.2
Register Descriptions ....................................................................................................... 1100
35.2.1
Control Register (CTLR) .......................................................................................... 1100
35.2.2
Bit Configuration Register (BCR) ............................................................................. 1103
35.2.3
Mask Register k (MKRk) (k = 0 to 7) ....................................................................... 1104
35.2.4
FIFO Received ID Compare Registers 0 and 1 (FIDCR0 and FIDCR1) ................. 1105
35.2.5
Mask Invalid Register (MKIVLR) ............................................................................. 1106
35.2.6
Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31; m = 0 to 7) .. 1106
35.2.7
Mailbox Interrupt Enable Register (MIER) ............................................................... 1110
35.2.8
Mailbox Interrupt Enable Register for FIFO Mailbox Mode (MIER_FIFO) ............... 1111
35.2.9
Message Control Register for Transmit (MCTL_TXj) (j = 0 to 31) ........................... 1112
35.2.10
Message Control Register for Receive (MCTL_RXj) (j = 0 to 31) ............................ 1114
35.2.11
Receive FIFO Control Register (RFCR) .................................................................. 1115
35.2.12
Receive FIFO Pointer Control Register (RFPCR) ................................................... 1117
35.2.13
Transmit FIFO Control Register (TFCR) .................................................................. 1118
35.2.14
Transmit FIFO Pointer Control Register (TFPCR) ................................................... 1119
35.2.15
Status Register (STR) .............................................................................................. 1120
35.2.16
Mailbox Search Mode Register (MSMR) ................................................................. 1122
35.2.17
Mailbox Search Status Register (MSSR) ................................................................. 1122
35.2.18
Channel Search Support Register (CSSR) ............................................................. 1123
35.2.19
Acceptance Filter Support Register (AFSR) ............................................................ 1124
35.2.20
Error Interrupt Enable Register (EIER) .................................................................... 1125
35.2.21
Error Interrupt Factor Judge Register (EIFR) .......................................................... 1126
35.2.22
Receive Error Count Register (RECR) .................................................................... 1128
35.2.23
Transmit Error Count Register (TECR) .................................................................... 1128
35.2.24
Error Code Store Register (ECSR) .......................................................................... 1129
35.2.25
Time Stamp Register (TSR) ..................................................................................... 1130
35.2.26
Test Control Register (TCR) .................................................................................... 1130
35.3
Operation Modes ............................................................................................................. 1132
35.3.1
CAN Reset Mode ..................................................................................................... 1132
35.3.2
CAN Halt Mode ........................................................................................................ 1133
35.3.3
CAN Sleep Mode ..................................................................................................... 1134
35.3.4
CAN Operation Mode (Excluding Bus-Off State) ..................................................... 1134
35.3.5
CAN Operation Mode (Bus-Off State) ..................................................................... 1135
35.4
Data Transfer Rate Configuration .................................................................................... 1136
35.4.1
Clock Setting ........................................................................................................... 1136
35.4.2
Bit Timing Setting .................................................................................................... 1136
35.4.3
Data Transfer Rate .................................................................................................. 1136
35.5
Mailbox and Mask Register Structure .............................................................................. 1137
35.6
Acceptance Filtering and Masking Functions .................................................................. 1138
35.7
36.
Reception and Transmission ........................................................................................... 1140
35.7.1
Reception ................................................................................................................ 1141
35.7.2
Transmission ........................................................................................................... 1143
35.8
Interrupts .......................................................................................................................... 1143
35.9
Usage Notes .................................................................................................................... 1144
35.9.1
Settings for the Module-Stop Function .................................................................... 1144
35.9.2
Settings for the Operating Clock .............................................................................. 1144
Serial Peripheral Interface (SPI) ................................................................................................ 1145
36.1
Overview .......................................................................................................................... 1145
36.2
Register Descriptions ....................................................................................................... 1147
36.2.1
SPI Control Register (SPCR) .................................................................................. 1147
36.2.2
SPI Slave Select Polarity Register (SSLP) .............................................................. 1149
36.2.3
SPI Pin Control Register (SPPCR) .......................................................................... 1149
36.2.4
SPI Status Register (SPSR) .................................................................................... 1150
36.2.5
SPI Data Register (SPDR/SPDR_HA) .................................................................... 1152
36.2.6
SPI Sequence Control Register (SPSCR) ............................................................... 1155
36.2.7
SPI Sequence Status Register (SPSSR) ................................................................. 1156
36.2.8
SPI Bit Rate Register (SPBR) ................................................................................. 1157
36.2.9
SPI Data Control Register (SPDCR) ....................................................................... 1158
36.2.10
SPI Clock Delay Register (SPCKD) ........................................................................ 1159
36.2.11
SPI Slave Select Negation Delay Register (SSLND) .............................................. 1160
36.2.12
SPI Next-Access Delay Register (SPND) ................................................................ 1160
36.2.13
SPI Control Register 2 (SPCR2) ............................................................................. 1161
36.2.14
SPI Command Registers 0 to 7 (SPCMD0 to SPCMD7) ......................................... 1162
36.2.15
SPI Data Control Register 2 (SPDCR2) .................................................................. 1164
36.3
Operation ......................................................................................................................... 1165
36.3.1
Overview of SPI Operation ...................................................................................... 1165
36.3.2
Controlling the SPI Pins ........................................................................................... 1166
36.3.3
SPI System Configuration Examples ....................................................................... 1167
36.3.3.1
Single master and single slave with the MCU as a master ............................. 1167
36.3.3.2
Single master and single slave with the MCU as a slave ................................ 1168
36.3.3.3
Single master and multi slave with the MCU as a master ............................... 1169
36.3.3.4
Single master and multi-slave with the MCU as a slave ................................. 1170
36.3.3.5
Multi master and multi slave with the MCU as a master ................................. 1170
36.3.3.6
Master and slave in clock synchronous mode with the MCU as a master ...... 1171
36.3.3.7
Master and slave in clock synchronous mode with the MCU as a slave ......... 1172
36.3.4
Data Formats ........................................................................................................... 1172
36.3.4.1
Operation when parity is disabled (SPCR2.SPPE = 0) ................................... 1173
36.3.4.2
Operation when parity is enabled (SPCR2.SPPE = 1) .................................... 1177
36.3.5
Transfer Formats ..................................................................................................... 1181
36.3.5.1
Transfer format when CPHA = 0 ..................................................................... 1181
36.3.5.2
36.3.6
Data Transfer Modes ............................................................................................... 1183
36.3.6.1
Full-duplex synchronous serial communications (SPCR.TXMD = 0) .............. 1183
36.3.6.2
Transmit operations only (SPCR.TXMD = 1) .................................................. 1184
36.3.7
Transmit Buffer Empty and Receive Buffer Full Interrupts ...................................... 1185
36.3.8
Error Detection ........................................................................................................ 1186
36.3.8.1
Overrun errors ................................................................................................. 1188
36.3.8.2
Parity errors ..................................................................................................... 1190
36.3.8.3
Mode fault errors ............................................................................................. 1190
36.3.8.4
Underrun errors ............................................................................................... 1191
36.3.9
Initializing the SPI .................................................................................................... 1191
36.3.9.1
Initialization by clearing of the SPE bit ............................................................ 1191
36.3.9.2
System reset ................................................................................................... 1191
36.3.10
SPI Operation .......................................................................................................... 1191
36.3.10.1
Master mode operation ................................................................................... 1191
36.3.10.2
Slave mode operation ..................................................................................... 1202
36.3.11
Clock Synchronous Operation ................................................................................. 1205
36.3.11.1
Master mode operation ................................................................................... 1206
36.3.11.2
Slave mode operation ..................................................................................... 1210
36.3.12
Loopback Mode ....................................................................................................... 1212
36.3.13
Self-Diagnosis of Parity Bit Function ....................................................................... 1212
36.3.14
Interrupt Sources ..................................................................................................... 1214
36.4
Output to the Event Link Controller (ELC) ....................................................................... 1214
36.4.1
Receive Buffer Full Event Output ............................................................................ 1215
36.4.2
Transmit Buffer Empty Event Output ....................................................................... 1215
36.4.3
Mode-Fault, Underrun, Overrun, or Parity Error Event Output ................................ 1215
36.4.4
SPI Idle Event Output .............................................................................................. 1215
36.4.5
Transmission-Completed Event Output ................................................................... 1215
36.5
37.
When CPHA = 1 .............................................................................................. 1182
Usage Notes .................................................................................................................... 1216
36.5.1
Settings for the Module-Stop Function .................................................................... 1216
36.5.2
Constraint on Low Power Functions ........................................................................ 1216
36.5.3
Constraints on Starting Transfer .............................................................................. 1216
36.5.4
Constraints on Mode-Fault, Underrun, Overrun, or Parity Error Event Output ........ 1216
36.5.5
Constraints on the SPRF and SPTEF Flags ........................................................... 1216
Quad Serial Peripheral Interface (QSPI) .................................................................................... 1217
37.1
Overview .......................................................................................................................... 1217
37.2
Register Descriptions ....................................................................................................... 1218
37.2.1
Transfer Mode Control Register (SFMSMD) ........................................................... 1218
37.2.2
Chip Selection Control Register (SFMSSC) ............................................................ 1219
37.2.3
Clock Control Register (SFMSKC) .......................................................................... 1220
37.2.4
Status Register (SFMSST) ...................................................................................... 1221
37.2.5
Communication Port Register (SFMCOM) .............................................................. 1222
37.2.6
Communication Mode Control Register (SFMCMD) ............................................... 1222
37.2.7
Communication Status Register (SFMCST) ............................................................ 1223
37.2.8
Instruction Code Register (SFMSIC) ....................................................................... 1223
37.2.9
Address Mode Control Register (SFMSAC) ............................................................ 1224
37.2.10
Dummy Cycle Control Register (SFMSDC) ............................................................. 1225
37.2.11
SPI Protocol Control Register (SFMSPC) ............................................................... 1226
37.2.12
Port Control Register (SFMPMD) ............................................................................ 1226
37.2.13
External QSPI Address Register (SFMCNT1) ......................................................... 1227
37.3
Memory Map .................................................................................................................... 1227
37.3.1
Internal Bus Space .................................................................................................. 1227
37.3.2
Address Width of the SPI Space and SPI Bus ........................................................ 1228
37.4
SPI Bus ............................................................................................................................ 1229
37.4.1
SPI Protocol ............................................................................................................. 1229
37.4.2
SPI Mode ................................................................................................................. 1231
37.5
SPI Bus Timing Adjustment ............................................................................................ 1231
37.5.1
SPI Bus Reference Cycles ...................................................................................... 1231
37.5.2
QSPCLK Signal Duty Ratio ..................................................................................... 1232
37.5.3
Minimum High-Level Width for the QSSL Signal ..................................................... 1233
37.5.4
QSSL Signal Setup Time ......................................................................................... 1233
37.5.5
QSSL Signal Hold Time ........................................................................................... 1233
37.5.6
Hold Time of the Serial Data Output Enable ........................................................... 1234
37.5.7
Setup Time for Serial Data Output .......................................................................... 1234
37.5.8
Hold Time for Serial Data Output ............................................................................ 1235
37.5.9
Serial Data Receiving Latency ................................................................................ 1235
37.6
SPI Instruction Set Used for Flash Access ...................................................................... 1236
37.6.1
SPI Instructions That Are Automatically Generated ................................................ 1236
37.6.2
Standard Read Instruction ....................................................................................... 1237
37.6.3
Fast Read Instruction .............................................................................................. 1238
37.6.4
Fast Read Dual Output Instruction .......................................................................... 1239
37.6.5
Fast Read Dual I/O Instruction ................................................................................ 1240
37.6.6
Fast Read Quad Output Instruction ......................................................................... 1241
37.6.7
Fast Read Quad I/O Instruction ............................................................................... 1241
37.6.8
Enter 4-Byte Mode Instruction ................................................................................. 1243
37.6.9
Exit 4-Byte Mode Instruction .................................................................................... 1243
37.6.10
Write Enable Instruction .......................................................................................... 1244
37.7
SPI Bus Cycle Arrangement ............................................................................................ 1244
37.7.1
Flash Read Based on Individual Conversion ........................................................... 1244
37.7.2
Flash Read Using the Prefetch Function ................................................................. 1245
37.7.3
Halt of Prefetching ................................................................................................... 1245
37.7.4
Direct Specification of Prefetch Destination ............................................................ 1245
37.7.5
Prefetch State Polling .............................................................................................. 1246
37.7.6
Flash Read Using the SPI Bus Cycle Extension Function ...................................... 1246
37.8
XIP Control ...................................................................................................................... 1247
37.8.1
Selecting the XIP Mode ........................................................................................... 1247
37.8.2
Releasing the XIP Mode .......................................................................................... 1247
37.9
QIO2 and QIO3 Pin States .............................................................................................. 1248
37.10
Direct Communication Mode ........................................................................................... 1248
37.10.1
About Direct Communication ................................................................................... 1248
37.10.2
Using Direct Communication Mode ......................................................................... 1248
37.10.3
Generating the SPI Bus Cycle during Direct Communication ................................. 1249
37.11
Operation ......................................................................................................................... 1250
37.11.1
37.12
Interrupts .......................................................................................................................... 1250
37.13
Usage Notes .................................................................................................................... 1251
37.13.1
38.
Settings for the Module-Stop Function .................................................................... 1251
Cyclic Redundancy Check (CRC) Calculator ............................................................................. 1252
38.1
Overview .......................................................................................................................... 1252
38.2
Register Descriptions ....................................................................................................... 1253
38.2.1
CRC Control Register 0 (CRCCR0) ........................................................................ 1253
38.2.2
CRC Control Register 1 (CRCCR1) ........................................................................ 1254
38.2.3
CRC Data Input Register (CRCDIR/CRCDIR_BY) .................................................. 1254
38.2.4
CRC Data Output Register (CRCDOR/CRCDOR_HA/CRCDOR_BY) ................... 1255
38.2.5
Snoop Address Register (CRCSAR) ....................................................................... 1255
38.3
Operation ......................................................................................................................... 1257
38.3.1
Basic Operation ....................................................................................................... 1257
38.3.2
CRC Snoop ............................................................................................................. 1261
38.4
39.
Procedure for Changing Settings in Multiple Control Registers .............................. 1250
Usage Notes .................................................................................................................... 1261
38.4.1
Settings for the Module-Stop Function .................................................................... 1261
38.4.2
Note on Transmission .............................................................................................. 1261
Serial Sound Interface Enhanced (SSIE) ................................................................................... 1263
39.1
Overview .......................................................................................................................... 1263
39.2
Features ........................................................................................................................... 1263
39.3
Block Diagram ................................................................................................................. 1265
39.4
Register Descriptions ....................................................................................................... 1267
39.4.1
Control Register (SSICR) ........................................................................................ 1267
39.4.2
Status Register (SSISR) .......................................................................................... 1276
39.4.3
FIFO Control Register (SSIFCR) ............................................................................. 1286
39.4.4
FIFO Status Register (SSIFSR) ............................................................................... 1292
39.4.5
Transmit FIFO Data Register (SSIFTDR) ................................................................ 1294
39.4.6
Receive FIFO Data Register (SSIFRDR) ................................................................ 1297
39.4.7
Audio Format Register (SSIOFR) ........................................................................... 1299
39.4.8
39.5
Status Control Register (SSISCR) .......................................................................... 1303
Communication Formats .................................................................................................. 1304
39.5.1
I2S Format ............................................................................................................... 1305
39.5.2
Monaural Format ..................................................................................................... 1305
39.5.2.1
Short frame ...................................................................................................... 1306
39.5.2.2
Long frame ...................................................................................................... 1306
39.5.3
39.6
TDM Format ............................................................................................................ 1307
Communication Modes .................................................................................................... 1308
39.6.1
Slave-mode Communication ................................................................................... 1308
39.6.2
Master-mode Communication ................................................................................. 1308
39.6.3
Transmission ........................................................................................................... 1309
39.6.4
Reception ................................................................................................................ 1309
39.6.5
Transmission and Reception ................................................................................... 1309
39.7
Operation ......................................................................................................................... 1309
39.7.1
Idle State ................................................................................................................. 1310
39.7.2
Communication States ............................................................................................ 1312
39.8
39.7.2.1
Data communication state ............................................................................... 1313
39.7.2.2
Padding communication .................................................................................. 1315
Communication Operation ............................................................................................... 1315
39.8.1
Start Communication ............................................................................................... 1316
39.8.2
Transmission ........................................................................................................... 1317
39.8.3
Reception ................................................................................................................ 1318
39.8.4
Transmission and Reception ................................................................................... 1318
39.8.5
Halt Communication ................................................................................................ 1319
39.8.6
Error Handling ......................................................................................................... 1320
39.8.7
Resume Communication ......................................................................................... 1321
39.9
Interrupts .......................................................................................................................... 1322
39.9.1
SSIE0_SSIF Interrupt .............................................................................................. 1322
39.9.2
SSIE0_SSITXI Interrupt [Full-duplex communication] ............................................. 1323
39.9.3
SSIE0_SSIRXI Interrupt .......................................................................................... 1323
39.10
Software Resets .............................................................................................................. 1323
39.10.1
39.11
Software Reset Procedure ...................................................................................... 1323
Notes ............................................................................................................................... 1324
39.11.1
Notes for Slave-mode Communication .................................................................... 1324
39.11.1.1
ADCKE control ................................................................................................ 1324
39.11.1.2
SSILRCK/SSIFS pin ........................................................................................ 1324
39.11.2
Notes for Master-mode Communication .................................................................. 1325
39.11.2.1
ADCKE control ................................................................................................ 1325
39.11.2.2
LRCONT control .............................................................................................. 1325
39.11.2.3
BCKASTP control ............................................................................................ 1325
39.11.3
Notes for Communication Flow ............................................................................... 1325
39.11.3.1
When an error interrupt is generated .............................................................. 1325
39.11.3.2
Transmit data empty interrupt ......................................................................... 1326
39.11.3.3
Receive data full interrupt ................................................................................ 1326
39.11.3.4
Switching transfer modes ................................................................................ 1326
39.11.3.5
Resume communication after halting SSIE ..................................................... 1326
39.11.4
40.
39.11.4.1
SSICR register ................................................................................................ 1326
39.11.4.2
SSISR register ................................................................................................. 1326
39.11.4.3
Communication state ....................................................................................... 1327
Sampling Rate Converter (SRC) ................................................................................................ 1328
40.1
Overview .......................................................................................................................... 1328
40.2
Register Descriptions ....................................................................................................... 1329
40.2.1
Input Data Register (SRCID) ................................................................................... 1329
40.2.2
Output Data Register (SRCOD) .............................................................................. 1329
40.2.3
Input Data Control Register (SRCIDCTRL) ............................................................. 1330
40.2.4
Output Data Control Register (SRCODCTRL) ........................................................ 1331
40.2.5
Control Register (SRCCTRL) .................................................................................. 1332
40.2.6
Status Register (SRCSTAT) ..................................................................................... 1335
40.2.7
Filter Coefficient Table n (SRCFCTRn) (n = 0 to 5551) ........................................... 1337
40.3
41.
Write Access Restriction .......................................................................................... 1326
Operation ......................................................................................................................... 1337
40.3.1
Initial Settings .......................................................................................................... 1337
40.3.2
Data Input ................................................................................................................ 1338
40.3.3
Data Output ............................................................................................................. 1339
40.4
Interrupts .......................................................................................................................... 1340
40.5
Usage Notes .................................................................................................................... 1341
40.5.1
Notes on Accessing Registers ................................................................................. 1341
40.5.2
Notes on Flush Processing ...................................................................................... 1341
40.5.3
Notes on DMAC or DTC Transfer ............................................................................ 1341
40.5.4
Notes on SRC Operation ......................................................................................... 1341
40.5.5
Settings for the Module-Stop Function .................................................................... 1341
SD/MMC Host Interface (SDHI) ................................................................................................. 1342
41.1
Overview .......................................................................................................................... 1342
41.2
Register Descriptions ....................................................................................................... 1344
41.2.1
Command Type Register (SD_CMD) ...................................................................... 1344
41.2.2
SD Command Argument Register (SD_ARG) ......................................................... 1345
41.2.3
SD Command Argument Register 1 (SD_ARG1) .................................................... 1345
41.2.4
Data Stop Register (SD_STOP) .............................................................................. 1346
41.2.5
Block Count Register (SD_SECCNT) ...................................................................... 1347
41.2.6
SD Card Response Register 10 (SD_RSP10), SD Card Response Register 32 (SD_RSP32), SD Card Response Register 54 (SD_RSP54) ............................................ 1347
41.2.7
SD Card Response Register 1 (SD_RSP1), SD Card Response Register 3 (SD_RSP3),
SD Card Response Register 5 (SD_RSP5) ............................................................ 1347
41.2.8
SD Card Response Register 76 (SD_RSP76) ........................................................ 1348
41.2.9
SD Card Response Register 7 (SD_RSP7) ............................................................ 1348
41.2.10
SD Card Interrupt Flag Register 1 (SD_INFO1) ...................................................... 1349
41.2.11
SD Card Interrupt Flag Register 2 (SD_INFO2) ...................................................... 1352
41.2.12
SD INFO1 Interrupt Mask Register (SD_INFO1_MASK) ........................................ 1356
41.2.13
SD INFO2 Interrupt Mask Register (SD_INFO2_MASK) ........................................ 1357
41.2.14
SD Clock Control Register (SD_CLK_CTRL) .......................................................... 1358
41.2.15
Transfer Data Length Register (SD_SIZE) .............................................................. 1359
41.2.16
SD Card Access Control Option Register (SD_OPTION) ....................................... 1359
41.2.17
SD Error Status Register 1 (SD_ERR_STS1) ......................................................... 1360
41.2.18
SD Error Status Register 2 (SD_ERR_STS2) ......................................................... 1361
41.2.19
SD Buffer Register (SD_BUF0) ............................................................................... 1362
41.2.20
SDIO Mode Control Register (SDIO_MODE) .......................................................... 1363
41.2.21
SDIO Interrupt Flag Register (SDIO_INFO1) .......................................................... 1364
41.2.22
SDIO INFO1 Interrupt Mask Register (SDIO_INFO1_MASK) ................................. 1365
41.2.23
DMA Mode Enable Register (SD_DMAEN) ............................................................. 1366
41.2.24
Software Reset Register (SOFT_RST) ................................................................... 1367
41.2.25
SD Interface Mode Setting Register (SDIF_MODE) ................................................ 1368
41.2.26
Swap Control Register (EXT_SWAP) ...................................................................... 1368
41.3
Operation ......................................................................................................................... 1369
41.3.1
SD/MMC Interface ................................................................................................... 1369
41.3.2
Card Detect/Write Protect ........................................................................................ 1371
41.3.2.1
Card detect ...................................................................................................... 1371
41.3.2.2
Write protect .................................................................................................... 1372
41.3.3
Interrupt Request and DMA Transfer Request ........................................................ 1372
41.3.3.1
Interrupts ......................................................................................................... 1372
41.3.3.2
DMA transfer requests (SDHI_MMCn_ODMSDBREQ, n = 0 to 1) ................. 1373
41.3.4
Communication Errors and Timeouts ...................................................................... 1374
41.3.5
Command without Data Transfer (SD/MMC) ........................................................... 1376
41.3.5.1
41.3.6
Single Block Read (SD/MMC) ................................................................................. 1378
41.3.6.1
41.3.7
Multiple block write operation using internal timer ........................................... 1385
Multiple Block Write (MMC using external timer) ..................................................... 1386
41.3.10.1
41.3.11
Multiple block read operation .......................................................................... 1383
Multiple Block Write (SD/MMC Using Internal Timer) .............................................. 1384
41.3.9.1
41.3.10
Single block write operation ............................................................................ 1381
Multiple Block Read (SD/MMC) ............................................................................... 1382
41.3.8.1
41.3.9
Single block read operation ............................................................................. 1379
Single Block Write (SD/MMC) ................................................................................. 1380
41.3.7.1
41.3.8
Operation for command without data transfer ................................................. 1377
Multiple block write operation using external timer .......................................... 1387
IO_RW_DIRECT Command (SD: CMD52) ............................................................. 1388
41.3.12
IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Read) ...................... 1388
41.3.13
IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Write) ...................... 1390
41.3.14
DMA Transfer (SD/MMC) ........................................................................................ 1392
41.3.14.1
41.3.15
41.4
Example of SD_CMD Register Setting .................................................................... 1394
Usage Notes .................................................................................................................... 1396
41.4.1
SD_BUF Illegal Write Access (SD/MMC) ................................................................ 1396
41.4.2
Block Number Constraint for Multiple Block Read (SD)] ......................................... 1396
41.4.2.1
42.
SD_BUF DMA transfer .................................................................................... 1392
Mechanism of incorrect reading ...................................................................... 1396
41.4.3
Automatic Control of SD/MMC Clock Output (SD/MMC) ......................................... 1397
41.4.4
Control of the C52PUB Setting for Multiple Block Write (SD) .................................. 1397
41.4.5
Notes on SD_CLK_CTRL Register Settings (SD/MMC) ......................................... 1397
41.4.6
Specification Limitations .......................................................................................... 1398
41.4.7
STP Bit Setting during Multiple Block Read (SD/MMC) .......................................... 1398
41.4.8
Register Setting Notes ............................................................................................. 1398
Parallel Data Capture Unit (PDC) .............................................................................................. 1399
42.1
Overview .......................................................................................................................... 1399
42.2
Register Descriptions ....................................................................................................... 1401
42.2.1
PDC Control Register 0 (PCCR0) ........................................................................... 1401
42.2.2
PDC Control Register 1 (PCCR1) ........................................................................... 1403
42.2.3
PDC Status Register (PCSR) .................................................................................. 1404
42.2.4
PDC Pin Monitor Register (PCMONR) .................................................................... 1406
42.2.5
PDC Receive Data Register (PCDR) ...................................................................... 1406
42.2.6
Vertical Capture Register (VCR) .............................................................................. 1408
42.2.7
Horizontal Capture Register (HCR) ......................................................................... 1409
42.3
Operation ......................................................................................................................... 1410
42.3.1
Transfer Formats ..................................................................................................... 1410
42.3.2
Transfer Timing ....................................................................................................... 1411
42.3.3
VCR and HCR Register Settings and the Capture Range ...................................... 1412
42.3.4
Reception Operation ................................................................................................ 1414
42.3.5
Operation during Horizontal Blanking Period .......................................................... 1415
42.3.6
Continued Reception Operations at Frame End ...................................................... 1415
42.3.7
Error Detection ........................................................................................................ 1416
42.3.8
Initial Settings .......................................................................................................... 1418
42.3.9
Operation Flows ...................................................................................................... 1420
42.3.10
Interrupt Sources ..................................................................................................... 1422
42.3.11
Reset State .............................................................................................................. 1423
42.4
Usage Notes .................................................................................................................... 1424
42.4.1
Settings for the Module-Stop Function .................................................................... 1424
42.4.2
Constraints on the Low Power Function .................................................................. 1424
42.4.3
Constraints on Error Interrupts ................................................................................ 1424
43.
42.4.4
Constraints on Using the DTC ................................................................................. 1424
42.4.5
Constraints on Using the DMAC .............................................................................. 1424
Boundary Scan .......................................................................................................................... 1425
43.1
Overview .......................................................................................................................... 1425
43.2
Register Descriptions ....................................................................................................... 1426
43.2.1
Instruction Register (JTIR) ....................................................................................... 1426
43.2.2
ID Code Register (JTIDR) ....................................................................................... 1427
43.2.3
Bypass Register (JTBPR) ........................................................................................ 1427
43.2.4
Boundary Scan Register (JTBSR) ........................................................................... 1427
43.3
43.3.1
TAP Controller ......................................................................................................... 1427
43.3.2
Commands .............................................................................................................. 1428
43.4
44.
Usage Notes .................................................................................................................... 1429
Secure Cryptographic Engine (SCE7) ....................................................................................... 1431
44.1
Overview .......................................................................................................................... 1431
44.2
Operation ......................................................................................................................... 1433
44.2.1
Encryption Engine ................................................................................................... 1433
44.2.2
Encryption and Decryption ...................................................................................... 1434
44.3
45.
Operation ......................................................................................................................... 1427
Usage Notes .................................................................................................................... 1434
44.3.1
Software Standby Mode .......................................................................................... 1434
44.3.2
Settings for the Module-Stop Function .................................................................... 1434
12-Bit A/D Converter (ADC12) ................................................................................................... 1435
45.1
Overview .......................................................................................................................... 1435
45.2
Register Descriptions ....................................................................................................... 1440
45.2.1
A/D Data Registers y (ADDRy), A/D Data Duplexing Register (ADDBLDR),
A/D Data Duplexing Register A (ADDBLDRA), A/D Data Duplexing Register B
(ADDBLDRB), A/D Temperature Sensor Data Register (ADTSDR),
A/D Internal Reference Voltage Data Register (ADOCDR) ..................................... 1440
45.2.2
A/D Self-Diagnosis Data Register (ADRD) .............................................................. 1444
45.2.3
A/D Control Register (ADCSR) .......................................................................................... 1447
45.2.4
A/D Channel Select Register A0 (ADANSA0) ......................................................... 1451
45.2.5
A/D Channel Select Register A1 (ADANSA1) ......................................................... 1451
45.2.6
A/D Channel Select Register B0 (ADANSB0) ......................................................... 1452
45.2.7
A/D Channel Select Register B1 (ADANSB1) ......................................................... 1452
45.2.8
A/D-Converted Value Addition/Average Channel Select Register 0 (ADADS0) ...... 1453
45.2.9
A/D-Converted Value Addition/Average Channel Select Register 1 (ADADS1) ...... 1453
45.2.10
A/D-Converted Value Addition/Average Count Select Register (ADADC) ............... 1454
45.2.11
A/D Control Extended Register (ADCER) ............................................................... 1455
45.2.12
A/D Conversion Start Trigger Select Register (ADSTRGR) .......................................... 1456
45.2.13
A/D Conversion Extended Input Control Register (ADEXICR) ................................ 1458
45.2.14
A/D Sampling State Register n (ADSSTRn) (n = 00 to 07, L, T, O) ........................ 1459
45.2.15
A/D Sample and Hold Circuit Control Register (ADSHCR) ..................................... 1460
45.2.16
A/D Sample and Hold Operation Mode Selection Register (ADSHMSR) ................ 1461
45.2.17
A/D Disconnection Detection Control Register (ADDISCR) .................................... 1461
45.2.18
A/D Group Scan Priority Control Register (ADGSPCR) .......................................... 1462
45.2.19
A/D Compare Function Control Register (ADCMPCR) ........................................... 1463
45.2.20
A/D Compare Function Window A Channel Select Register 0 (ADCMPANSR0) .... 1464
45.2.21
A/D Compare Function Window A Channel Select Register 1 (ADCMPANSR1) .... 1465
45.2.22
A/D Compare Function Window A Extended Input Select Register (ADCMPANSER)
.................................................................................................................................. 1465
45.2.23
A/D Compare Function Window A Comparison Condition Setting Register 0 (ADCMPLR0) ...................................................................................................................... 1466
45.2.24
A/D Compare Function Window A Comparison Condition Setting Register 1 (ADCMPLR1) ...................................................................................................................... 1468
45.2.25
A/D Compare Function Window A Extended Input Comparison Condition Setting Register (ADCMPLER) ..................................................................................................... 1468
45.2.26
A/D Compare Function Window A Lower-Side Level Setting Register (ADCMPDR0), A/D
Compare Function Window A Upper-Side Level Setting Register (ADCMPDR1), A/D
Compare Function Window B Lower-Side Level Setting Register (ADWINLLB), A/D
Compare Function Window B Upper-Side Level Setting Register (ADWINULB) .... 1469
45.2.27
A/D Compare Function Window A Channel Status Register 0 (ADCMPSR0) ......... 1471
45.2.28
A/D Compare Function Window A Channel Status Register1 (ADCMPSR1) .......... 1471
45.2.29
A/D Compare Function Window A Extended Input Channel Status Register (ADCMPSER) .......................................................................................................................... 1472
45.2.30
A/D Compare Function Window B Channel Select Register (ADCMPBNSR) ......... 1473
45.2.31
A/D Compare Function Window B Status Register (ADCMPBSR) .......................... 1475
45.2.32
A/D Compare Function Window A/B Status Monitor Register (ADWINMON) ......... 1475
45.3
Operation ......................................................................................................................... 1476
45.3.1
Scanning Operation ................................................................................................. 1476
45.3.2
Single Scan Mode ................................................................................................... 1477
45.3.2.1
Basic operation without channel-dedicated sample-and-hold circuits ............. 1477
45.3.2.2
Basic operation with channel-dedicated sample-and-hold circuits and continuous
sampling disabled ............................................................................................ 1478
45.3.2.3
Basic operation with channel-dedicated sample-and-hold circuits and continuous
sampling enabled ............................................................................................ 1479
45.3.2.4
Channel selection and self-diagnosis without channel-dedicated sample-and-hold
circuits ............................................................................................................. 1480
45.3.2.5
Channel selection and self-diagnosis with channel-dedicated sample-and-hold circuits and continuous sampling disabled .......................................................... 1481
45.3.2.6
Channel selection and self-diagnosis with channel-dedicated sample-and-hold circuits and continuous sampling enabled .......................................................... 1482
45.3.2.7
A/D conversion of temperature sensor output or internal reference voltage ... 1483
45.3.2.8
A/D conversion in double-trigger mode ........................................................... 1484
45.3.2.9
Extended operations when double-trigger mode is selected ........................... 1485
45.3.3
Continuous Scan Mode ........................................................................................... 1486
45.3.3.1
Basic operation without channel-dedicated sample-and-hold circuits ............. 1486
45.3.3.2
Basic operation with channel-dedicated sample-and-hold circuits and continuous
sampling disabled ............................................................................................ 1487
45.3.3.3
Basic operation with channel-dedicated sample-and-hold circuits and continuous
sampling enabled ............................................................................................ 1488
45.3.3.4
Channel selection and self-diagnosis without channel-dedicated sample-and-hold
circuits ............................................................................................................. 1489
45.3.3.5
Channel selection and self-diagnosis with channel-dedicated sample-and-hold circuits and continuous sampling disabled .......................................................... 1490
45.3.3.6
Channel selection and self-diagnosis with channel-dedicated sample-and-hold circuits and continuous sampling enabled .......................................................... 1491
45.3.3.7
A/D conversion of temperature sensor output or internal reference voltage ... 1492
45.3.4
Group Scan Mode ................................................................................................... 1493
45.3.4.1
Basic operation ................................................................................................ 1493
45.3.4.2
A/D conversion in double-trigger mode ........................................................... 1494
45.3.4.3
Operation with group A priority control ............................................................ 1495
45.3.5
Compare Function for Windows A and B ................................................................ 1502
45.3.5.1
Compare function ............................................................................................ 1502
45.3.5.2
Event output of compare function .................................................................... 1504
45.3.5.3
Restrictions on the compare function .............................................................. 1505
45.3.6
Analog Input Sampling and Scan Conversion Time ................................................ 1506
45.3.7
Usage Example of A/D Data Register Automatic Clearing Function ....................... 1508
45.3.8
A/D-Converted Value Addition/Average Mode ........................................................ 1509
45.3.9
Disconnection Detection Assist Function ................................................................ 1509
45.3.10
Starting A/D Conversion with an Asynchronous Trigger ......................................... 1511
45.3.11
Starting A/D Conversion with a Synchronous Trigger from a Peripheral Module .... 1511
45.4
Interrupt Sources and DTC/DMAC Transfer Requests .................................................... 1511
45.4.1
45.5
Interrupt Requests ................................................................................................... 1511
Event Link Function ......................................................................................................... 1513
45.5.1
Event Output to the ELC .......................................................................................... 1513
45.5.2
ADC12 Operation through an Event from the ELC .................................................. 1513
45.6
Usage Notes .................................................................................................................... 1514
45.6.1
Constraints on Reading the Data Registers ............................................................ 1514
45.6.2
Constraints on Stopping A/D Conversion ................................................................ 1514
45.6.3
A/D Conversion Restart and Termination Timing .................................................... 1515
45.6.4
Constraints on Scan End Interrupt Handling ........................................................... 1515
45.6.5
Settings for the Module-Stop Function .................................................................... 1515
45.6.6
Notes on Entering the Low-Power States ................................................................ 1516
45.6.7
Error in Absolute Accuracy When Disconnection Detection Assistance Is in Use .. 1516
45.6.8
Constraints on Operating Modes and Status Bits .................................................... 1516
45.6.9
Notes on Board Design ........................................................................................... 1516
45.6.10
Constraints on Noise Prevention ............................................................................. 1516
45.6.11
Port Settings When Using the ADC12 Input ............................................................ 1517
45.6.12
Relationship between ADC12 Units 0 and 1 and the ACMPHS .............................. 1517
46.
12-Bit D/A Converter (DAC12) ................................................................................................... 1519
46.1
Overview .......................................................................................................................... 1519
46.2
Register Descriptions ....................................................................................................... 1520
46.2.1
D/A Data Register m (DADRm) (m = 0, 1) .............................................................. 1520
46.2.2
D/A Control Register (DACR) .................................................................................. 1520
46.2.3
DADRm Format Select Register (DADPR) .............................................................. 1522
46.2.4
D/A A/D Synchronous Start Control Register (DAADSCR) ..................................... 1522
46.2.5
D/A Output Amplifier Control Register (DAAMPCR) ............................................... 1523
46.2.6
D/A Amplifier Stabilization Wait Control Register (DAASWCR) ............................... 1523
46.2.7
D/A A/D Synchronous Unit Select Register (DAADUSR) ........................................ 1524
46.3
Operation ......................................................................................................................... 1524
46.3.1
46.4
47.
Event Link Operation Setting Procedure ......................................................................... 1527
46.4.1
DA0 Event Link Operation Setting Procedure ......................................................... 1527
46.4.2
DA1 Event Link Operation Setting Procedure ......................................................... 1527
46.5
Usage Notes on Event Link Operation ............................................................................ 1527
46.6
Usage Notes .................................................................................................................... 1527
46.6.1
Settings for the Module-Stop Function .................................................................... 1527
46.6.2
DAC12 Operation in the Module-Stop State ............................................................ 1527
46.6.3
DAC12 Operation in Software Standby Mode ......................................................... 1528
46.6.4
Constraint on Entering Deep Software Standby Mode ............................................ 1528
46.6.5
Initialization Procedure with the Output Amplifier .................................................... 1528
46.6.6
Restrictions on Usage When Interference Reduction between D/A and A/D Conversion
Is Enabled ................................................................................................................ 1528
Temperature Sensor (TSN) ........................................................................................................ 1529
47.1
Overview .......................................................................................................................... 1529
47.2
Register Descriptions ....................................................................................................... 1530
47.2.1
Temperature Sensor Control Register (TSCR) ........................................................ 1530
47.2.2
Temperature Sensor Calibration Data Register (TSCDR) ....................................... 1530
47.3
Using the Temperature Sensor ........................................................................................ 1530
47.3.1
Preparation for Using the Temperature Sensor ....................................................... 1530
47.3.2
Procedures for Using the Temperature Sensor ....................................................... 1531
47.4
48.
Reducing Interference between D/A and A/D Conversion ...................................... 1525
Usage Notes .................................................................................................................... 1533
47.4.1
Settings for the Module-Stop Function .................................................................... 1533
47.4.2
Constraints .............................................................................................................. 1533
High-Speed Analog Comparator (ACMPHS) ............................................................................. 1534
48.1
Overview .......................................................................................................................... 1534
48.2
Register Descriptions ....................................................................................................... 1535
48.2.1
Comparator Control Register (CMPCTL) ................................................................ 1535
48.2.2
Comparator Input Select Register (CMPSEL0) ...................................................... 1536
48.2.3
Comparator Reference Voltage Select Register (CMPSEL1) ................................. 1537
48.2.4
Comparator Output Monitor Register (CMPMON) ................................................... 1537
48.2.5
49.
Comparator Output Control Register (CPIOC) ........................................................ 1538
48.3
Operation ......................................................................................................................... 1538
48.4
Noise Filter ....................................................................................................................... 1540
48.5
ACMPHS Interrupts ......................................................................................................... 1540
48.6
ACMPHS Output to the Event Link Controller (ELC) ....................................................... 1541
48.7
ACMPHS Pin Output ....................................................................................................... 1541
48.8
Usage Notes .................................................................................................................... 1541
48.8.1
Settings for the Module-Stop Function .................................................................... 1541
48.8.2
Relationship with the ADC12 ................................................................................... 1541
Capacitive Touch Sensing Unit (CTSU) ..................................................................................... 1542
49.1
Overview .......................................................................................................................... 1542
49.2
Register Descriptions ....................................................................................................... 1544
49.2.1
CTSU Control Register 0 (CTSUCR0) .................................................................... 1544
49.2.2
CTSU Control Register 1 (CTSUCR1) .................................................................... 1546
49.2.3
CTSU Synchronous Noise Reduction Setting Register (CTSUSDPRS) ................. 1547
49.2.4
CTSU Sensor Stabilization Wait Control Register (CTSUSST) ............................... 1548
49.2.5
CTSU Measurement Channel Register 0 (CTSUMCH0) ......................................... 1549
49.2.6
CTSU Measurement Channel Register 1 (CTSUMCH1) ......................................... 1550
49.2.7
CTSU Channel Enable Control Register 0 (CTSUCHAC0) ..................................... 1550
49.2.8
CTSU Channel Enable Control Register 1 (CTSUCHAC1) ..................................... 1551
49.2.9
CTSU Channel Enable Control Register 2 (CTSUCHAC2) ..................................... 1551
49.2.10
CTSU Channel Transmit/Receive Control Register 0 (CTSUCHTRC0) .................. 1552
49.2.11
CTSU Channel Transmit/Receive Control Register 1 (CTSUCHTRC1) .................. 1552
49.2.12
CTSU Channel Transmit/Receive Control Register 2 (CTSUCHTRC2) .................. 1553
49.2.13
CTSU High-Pass Noise Reduction Control Register (CTSUDCLKC) ..................... 1553
49.2.14
CTSU Status Register (CTSUST) ............................................................................ 1554
49.2.15
CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register (CTSUSSC)
.................................................................................................................................. 1555
49.2.16
CTSU Sensor Offset Register 0 (CTSUSO0) .......................................................... 1556
49.2.17
CTSU Sensor Offset Register 1 (CTSUSO1) .......................................................... 1557
49.2.18
CTSU Sensor Counter (CTSUSC) .......................................................................... 1558
49.2.19
CTSU Reference Counter (CTSURC) ..................................................................... 1558
49.2.20
CTSU Error Status Register (CTSUERRS) ............................................................. 1559
49.3
Operation ......................................................................................................................... 1560
49.3.1
Principles of Measurement Operation ..................................................................... 1560
49.3.2
Measurement Modes ............................................................................................... 1561
49.3.2.1
Initial settings flow ........................................................................................... 1562
49.3.2.2
Status counter ................................................................................................. 1563
49.3.2.3
Self-capacitance single scan mode operation ................................................. 1564
49.3.2.4
Self-capacitance multi-scan mode operation .................................................. 1565
49.3.2.5
Mutual capacitance full scan mode operation ................................................. 1568
49.3.3
Parameters Common to Multiple Modes ................................................................. 1570
49.4
50.
49.3.3.1
Sensor stabilization wait time and measurement time .................................... 1570
49.3.3.2
Interrupts ......................................................................................................... 1571
Usage Notes .................................................................................................................... 1572
49.4.1
Measurement Result Data (CTSUSC and CTSURC Counters) .............................. 1572
49.4.2
Constraint on Software Trigger ................................................................................ 1572
49.4.3
Constraints on External Triggers ............................................................................. 1573
49.4.4
Constraints on Forced Stops ................................................................................... 1573
49.4.5
TSCAP Pin .............................................................................................................. 1573
49.4.6
Constraints on Measurement Operation (CTSUCR0.CTSUSTRT Bit = 1) .............. 1573
Data Operation Circuit (DOC) .................................................................................................... 1574
50.1
Overview .......................................................................................................................... 1574
50.2
Register Descriptions ....................................................................................................... 1575
50.2.1
DOC Control Register (DOCR) ................................................................................ 1575
50.2.2
DOC Data Input Register (DODIR) .......................................................................... 1576
50.2.3
DOC Data Setting Register (DODSR) ..................................................................... 1576
50.3
Operation ......................................................................................................................... 1576
50.3.1
Data Comparison Mode ........................................................................................... 1576
50.3.2
Data Addition Mode ................................................................................................. 1577
50.3.3
Data Subtraction Mode ............................................................................................ 1577
50.4
Interrupt Request and Output to the Event Link Controller (ELC) ................................... 1578
50.5
Usage Notes .................................................................................................................... 1578
50.5.1
51.
Settings for the Module-Stop Function .................................................................... 1578
SRAM ......................................................................................................................................... 1579
51.1
Overview .......................................................................................................................... 1579
51.2
Register Descriptions ...................................................................................................... 1579
51.2.1
SRAM Parity Error Operation After Detection Register (PARIOAD) ........................ 1579
51.2.2
SRAM Protection Register (SRAMPRCR) ............................................................... 1580
51.2.3
SRAM Wait State Control Register (SRAMWTSC) .................................................. 1580
51.2.4
ECC Operating Mode Control Register (ECCMODE) ............................................. 1581
51.2.5
ECC 2-Bit Error Status Register (ECC2STS) .......................................................... 1581
51.2.6
ECC 1-Bit Error Information Update Enable Register (ECC1STSEN) .................... 1582
51.2.7
ECC 1-Bit Error Status Register (ECC1STS) .......................................................... 1582
51.2.8
ECC Protection Register (ECCPRCR) .................................................................... 1583
51.2.9
ECC Test Control Register (ECCETST) .................................................................. 1583
51.2.10
SRAM ECC Error Operation After Detection Register (ECCOAD) .......................... 1584
51.3
Operation ......................................................................................................................... 1584
51.3.1
Low-Power Functions .............................................................................................. 1584
51.3.2
ECC Function .......................................................................................................... 1584
51.3.3
ECC Error Generation ............................................................................................. 1585
51.3.4
ECC Decoder Testing .............................................................................................. 1585
51.3.5
Parity Calculation Function ...................................................................................... 1586
51.3.6
SRAM Error Sources ............................................................................................... 1588
51.3.7
Access Cycles ......................................................................................................... 1588
51.4
52.
Usage Notes .................................................................................................................... 1589
51.4.1
Wait State Insertion ................................................................................................. 1589
51.4.2
Instruction Fetch from the SRAM Area .................................................................... 1589
51.4.3
Store Buffer of SRAM .............................................................................................. 1589
Standby SRAM ........................................................................................................................... 1590
52.1
Overview .......................................................................................................................... 1590
52.2
Operation ......................................................................................................................... 1590
52.2.1
Data Retention ......................................................................................................... 1590
52.2.2
Low Power Function ................................................................................................ 1590
52.2.3
Parity Calculation Function ...................................................................................... 1590
52.2.4
Access Cycle ........................................................................................................... 1590
52.3
Usage Notes .................................................................................................................... 1591
52.3.1
53.
Instruction Fetch from the Standby SRAM area ...................................................... 1591
Flash Memory ............................................................................................................................ 1592
53.1
Overview .......................................................................................................................... 1592
53.2
Structure of Memory ........................................................................................................ 1593
53.3
Flash Cache ..................................................................................................................... 1594
53.3.1
Overview .................................................................................................................. 1594
53.3.2
Register Descriptions .............................................................................................. 1595
53.4
53.3.2.1
Flash Cache Enable Register (FCACHEE) ..................................................... 1595
53.3.2.2
Flash Cache Invalidate Register (FCACHEIV) ................................................ 1596
53.3.2.3
Flash Wait Cycle Register (FLWT) .................................................................. 1596
Operation ......................................................................................................................... 1596
53.4.1
53.5
Operating Modes Associated with the Flash Memory ..................................................... 1597
53.5.1
53.6
Notice to use Flash Cache ...................................................................................... 1597
ID Code Protection .................................................................................................. 1597
Overview of Functions ..................................................................................................... 1598
53.6.1
Configuration Area Bit Map ..................................................................................... 1600
53.6.2
Startup Area Select ................................................................................................. 1601
53.6.3
Protection by Access Window ................................................................................. 1601
53.7
Programming Commands ................................................................................................ 1603
53.8
Suspend Operation .......................................................................................................... 1603
53.9
Protection ......................................................................................................................... 1604
53.10
Serial Programming Mode ............................................................................................... 1604
53.10.1
SCI Boot Mode ........................................................................................................ 1604
53.10.2
USB Boot Mode ....................................................................................................... 1605
53.11
Using a Serial Programmer for Programming .................................................................. 1605
53.11.1
Serial Programming ................................................................................................. 1606
53.11.2
Programming Environments .................................................................................... 1606
53.12
53.12.1
Overview .................................................................................................................. 1606
53.12.2
Background Operation ............................................................................................. 1607
53.13
55.
Reading the Flash Memory .............................................................................................. 1607
53.13.1
Reading the Code Flash Memory ............................................................................ 1607
53.13.2
Reading the Data Flash Memory ............................................................................. 1607
53.14
54.
Programming through Self-Programming ........................................................................ 1606
Usage Notes .................................................................................................................... 1607
53.14.1
Reading Areas Where Programming or Erasure Was Interrupted .......................... 1607
53.14.2
Constraint on Additional Writes ............................................................................... 1607
53.14.3
Resets during Programming and Erasure ............................................................... 1608
53.14.4
Allocation of Vectors for Interrupts and Other Exceptions during Programming and Erasure .......................................................................................................................... 1608
53.14.5
Constraints during Programming and Erasure ........................................................ 1608
53.14.6
Abnormal Termination of Programming and Erasure .............................................. 1608
Internal Voltage Regulator ......................................................................................................... 1609
54.1
Overview .......................................................................................................................... 1609
54.2
Operation ......................................................................................................................... 1609
Electrical Characteristics ............................................................................................................ 1610
55.1
Absolute Maximum Ratings ............................................................................................. 1610
55.2
DC Characteristics ........................................................................................................... 1611
55.2.1
Tj/Ta Definition ......................................................................................................... 1611
55.2.2
I/O VIH, VIL ............................................................................................................... 1611
55.2.3
I/O IOH, IOL ............................................................................................................... 1613
55.2.4
I/O VOH, VOL, and Other Characteristics ................................................................. 1614
55.2.5
Operating and Standby Current ............................................................................... 1615
55.2.6
VCC Rise and Fall Gradient and Ripple Frequency ................................................ 1618
55.3
AC Characteristics ........................................................................................................... 1619
55.3.1
Frequency ................................................................................................................ 1619
55.3.2
Clock Timing ............................................................................................................ 1620
55.3.3
Reset Timing ........................................................................................................... 1623
55.3.4
Wakeup Timing ........................................................................................................ 1624
55.3.5
NMI and IRQ Noise Filter ........................................................................................ 1626
55.3.6
Bus Timing ............................................................................................................... 1627
55.3.7
I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing ........................ 1637
55.3.8
PWM Delay Generation Circuit Timing .................................................................... 1640
55.3.9
CAC Timing ............................................................................................................. 1640
55.3.10
SCI Timing ............................................................................................................... 1641
55.3.11
SPI Timing ............................................................................................................... 1646
55.3.12
QSPI Timing ............................................................................................................ 1650
55.3.13
IIC Timing ................................................................................................................ 1651
55.3.14
SSIE Timing ............................................................................................................. 1654
55.3.15
SD/MMC Host Interface Timing ............................................................................... 1656
55.3.16
ETHERC Timing ...................................................................................................... 1657
55.3.17
PDC Timing ............................................................................................................. 1661
55.4
USB Characteristics ......................................................................................................... 1662
55.4.1
USBFS Timing ......................................................................................................... 1662
55.5
ADC12 Characteristics .................................................................................................... 1663
55.6
DAC12 Characteristics .................................................................................................... 1667
55.7
TSN Characteristics ......................................................................................................... 1668
55.8
OSC Stop Detect Characteristics .................................................................................... 1668
55.9
POR and LVD Characteristics ......................................................................................... 1668
55.10
VBATT Characteristics .................................................................................................... 1671
55.11
CTSU Characteristics ...................................................................................................... 1671
55.12
ACMPHS Characteristics ................................................................................................. 1671
55.13
Flash Memory Characteristics ......................................................................................... 1672
55.13.1
Code Flash Memory Characteristics ....................................................................... 1672
55.13.2
Data Flash Memory Characteristics ........................................................................ 1674
55.14
Boundary Scan ................................................................................................................ 1674
55.15
Joint Test Action Group (JTAG) ....................................................................................... 1676
55.16
Serial Wire Debug (SWD) ................................................................................................ 1677
55.17
Embedded Trace Macro Interface (ETM) ........................................................................ 1678
Appendix 1. Port States in Each Processing Mode ............................................................................ 1679
Appendix 2. Package Dimensions ....................................................................................................... 1684
Appendix 3. I/O Registers ................................................................................................................... 1687
3.1
Peripheral Base Addresses ............................................................................................. 1687
3.2
Access Cycles ................................................................................................................. 1689
3.3
Register Descriptions ....................................................................................................... 1691
Appendix 4. Revised Mask Set of the Ethernet Peripheral Interface .................................................. 1727
Revision History ................................................................................................................................... 1728
S5D5 Microcontroller Group
User’s Manual
Leading performance 120-MHz Arm® Cortex®-M4 core, up to 1-MB code flash memory, 384-KB SRAM, Capacitive
Touch Sensing Unit, Ethernet MAC Controller, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and
advanced analog.
Features
■ Arm Cortex-M4 Core with Floating Point Unit (FPU)
Armv7E-M architecture with DSP instruction set
Maximum operating frequency: 120 MHz
Support for 4-GB address space
On-chip debugging system: JTAG, SWD, and ETM
Boundary scan and Arm Memory Protection Unit (Arm MPU)
■ Memory
Up to 1-MB code flash memory (40 MHz zero wait states)
32-KB data flash memory (125,000 erase/write cycles)
Up to 384-KB SRAM
Flash Cache (FCACHE)
Memory Protection Units (MPU)
Memory Mirror Function (MMF)
128-bit unique ID
■ Connectivity
Ethernet MAC Controller (ETHERC)
Ethernet DMA Controller (EDMAC)
USB 2.0 Full-Speed (USBFS) module
- On-chip transceiver
Serial Communications Interface (SCI) with FIFO × 10
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 3
Controller Area Network (CAN) × 2
Serial Sound Interface Enhanced (SSIE)
SD/MMC Host Interface (SDHI) × 2
Quad Serial Peripheral Interface (QSPI)
IrDA interface
Sampling Rate Converter (SRC)
External address space
- 8-bit or 16-bit bus space is selectable per area
- SDRAM support
■ Analog
12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits
each × 2
12-bit D/A Converter (DAC12) × 2
High-Speed Analog Comparator (ACMPHS) × 6
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-bit Enhanced High Resolution
(GPT32EH) × 4
General PWM Timer 32-bit Enhanced (GPT32E) × 4
General PWM Timer 32-bit (GPT32) × 6
Asynchronous General-Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
■ System and Power Management
Low power modes
Realtime Clock (RTC) with calendar and VBATT support
Event Link Controller (ELC)
DMA Controller (DMAC) × 8
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
■ Security and Encryption
AES128/192/256
3DES/ARC4
SHA1/SHA224/SHA256/MD5
GHASH
RSA/DSA/ECC
True Random Number Generator (TRNG)
■ Human Machine Interface (HMI)
Capacitive Touch Sensing Unit (CTSU)
Parallel Data Capture Unit (PDC)
■ Multiple Clock Sources
Main clock oscillator (MOSC) (8 to 24 MHz)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
■ General-Purpose I/O Ports
Up to 110 input/output pins
- Up to 1 CMOS input
- Up to 109 CMOS input/output
- Up to 21 input/output 5 V tolerant
- Up to 18 high current (20 mA)
■ Operating Voltage
VCC: 2.7 to 3.6 V
■ Operating Temperature and Packages
Ta = -40°C to +85°C
- 145-pin LGA (7 mm × 7 mm, 0.5 mm pitch)
Ta = -40°C to +105°C
- 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
■ Safety
Error Correction Code (ECC) in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
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1.
1. Overview
Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex®-M4 core running up to 120 MHz with the
following features:
Up to 1-MB code flash memory
384-KB SRAM
Capacitive Touch Sensing Unit (CTSU)
Ethernet MAC Controller (ETHERC), USBFS, SD/MMC Host Interface
Quad Serial Peripheral Interface (QSPI)
Security and safety features
12-bit A/D Converter (ADC12)
12-bit D/A Converter (DAC12)
Analog peripherals.
1.1
Function Outline
Table 1.1
Arm core
Feature
Functional description
Arm Cortex-M4 core
Maximum operating frequency: up to 120 MHz
Arm Cortex-M4 core:
- Revision: r0p1-01rel0
- ARMv7E-M architecture profile
- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.
Arm Memory Protection Unit (Arm MPU):
- Armv7 Protected Memory System Architecture
- 8 protect regions.
SysTick timer:
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2
Memory
Feature
Functional description
Code flash memory
Maximum 1-MB code flash memory. See section 53, Flash Memory.
Data flash memory
32-KB data flash memory. See section 53, Flash Memory.
Memory Mirror Function (MMF)
The Memory Mirror Function (MMF) can be configured to mirror the target application image
load address in code flash memory to the application image link address in the 23-bit unused
memory space (memory mirror space addresses). Your application code is developed and
linked to run from this MMF destination address. The application code does not need to know
the load location where it is stored in code flash memory. See section 5, Memory Mirror
Function (MMF).
Option-setting memory
The option-setting memory determines the state of the MCU after a reset. See section 7,
Option-Setting Memory.
SRAM
On-chip high-speed SRAM with either parity-bit or Error Correction Code (ECC). The first 32
KB of SRAM0 error correction capability using ECC. Parity check is performed for other areas.
See section 51, SRAM.
Standby SRAM
On-chip SRAM that can retain data in Deep Software Standby mode. See section 52, Standby
SRAM.
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Table 1.3
1. Overview
System (1 of 2)
Feature
Functional description
Operating modes
Two operating modes:
Single-chip mode
SCI or USB boot mode.
See section 3, Operating Modes.
Resets
14 resets:
RES pin reset
Power-on reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Independent watchdog timer reset
Watchdog timer reset
Deep Software Standby reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
Stack pointer error reset
Software reset.
See section 6, Resets.
Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and
the detection level can be selected using a software program. See section 8, Low Voltage
Detection (LVD).
Clocks
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
PLL frequency synthesizer
IWDT-dedicated on-chip oscillator
Clock out support.
See section 9, Clock Generation Circuit.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock to be used as a
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.
When measurement is complete or the number of pulses within the time generated by the
measurement reference clock is not within the allowable range, an interrupt request is
generated.
See section 10, Clock Frequency Accuracy Measurement Circuit (CAC).
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt
Controller Unit (ICU).
Key Interrupt Function (KINT)
A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function
(KINT).
Low power modes
Power consumption can be reduced in multiple ways, such as by setting clock dividers,
controlling EBCLK output, controlling SDCLK output, stopping modules, selecting power
control mode in normal operation, and transitioning to low power modes. See section 11, Low
Power Modes.
Battery backup function
A battery backup function is provided for partial powering by a battery. The battery powered
area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See
section 12, Battery Backup Function.
Register write protection
The register write protection function protects important registers from being overwritten
because of software errors. See section 13, Register Write Protection.
Memory Protection Unit (MPU)
Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided
for memory protection. See section 16, Memory Protection Unit (MPU).
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Table 1.3
1. Overview
System (2 of 2)
Feature
Functional description
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow.
A refresh-permitted period can be set to refresh the counter and be used as the condition for
detecting when the system runs out of control. See section 27, Watchdog Timer (WDT).
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt or interrupt for a timer underflow. Because
the timer operates with an independent, dedicated clock source, it is particularly useful in
returning the MCU to a known state as a fail-safe mechanism when the system runs out of
control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by
a refresh of the count value in the registers. See section 28, Independent Watchdog Timer
(IWDT).
Table 1.4
Event link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 19, Event Link Controller (ELC).
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request. See section 18, Data Transfer Controller (DTC).
DMA Controller (DMAC)
An 8-channel DMAC module is provided for transferring data without the CPU. When a DMA
transfer request is generated, the DMAC transfers data stored at the transfer source address
to the transfer destination address. See section 17, DMA Controller (DMAC).
Table 1.6
External bus interface
Feature
Functional description
External buses
CS area (EXBIU): Connected to the external devices (external memory interface)
SDRAM area (EXBIU): Connected to the SDRAM (external memory interface)
QSPI area (EXBIUT2): Connected to the QSPI (external device interface).
Table 1.7
Timers
Feature
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with 14 channels. PWM waveforms can be
generated by controlling the up-counter, down-counter, or up- and down-counter. In addition,
PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be
used as a general-purpose timer. See section 23, General PWM Timer (GPT).
Port Output Enable for GPT (POEG)
Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG).
Asynchronous General-Purpose
Timer (AGT)
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
output, external pulse width or period measurement, and counting of external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and can be accessed with the AGT register.
See section 25, Asynchronous General-Purpose Timer (AGT).
Realtime Clock (RTC)
The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 26, Realtime Clock (RTC).
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Table 1.8
1. Overview
Communication interfaces (1 of 2)
Feature
Functional description
Serial Communications Interface
(SCI)
The Serial Communications Interface (SCI) is configurable to five asynchronous and
synchronous serial interfaces:
Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 32, Serial Communications Interface (SCI).
IrDA Interface (IrDA)
The IrDA interface sends and receives IrDA data communication waveforms in cooperation
with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 33,
IrDA Interface.
I2C bus interface (IIC)
The 3-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C
(Inter-Integrated Circuit) bus interface functions. See section 34, I2C Bus Interface (IIC).
Serial Peripheral Interface (SPI)
Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, fullduplex synchronous serial communications with multiple processors and peripheral devices.
See section 36, Serial Peripheral Interface (SPI).
Serial Sound Interface Enhanced
(SSIE)
The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
digital audio devices for transmitting I2S (Inter-Integrated Sound) 2ch, 4ch, 6ch, 8ch, Word
Select (WS) Continue/Monaural/TDM audio data over a serial bus. The SSIE supports an
audio clock frequency of up to 50 MHz, and can be operated as a slave or master receiver,
transmitter, or transceiver to suit various applications. The SSIE includes 32-stage FIFO
buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception
and transmission. See section 39, Serial Sound Interface Enhanced (SSIE).
Quad Serial Peripheral Interface
(QSPI)
The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial
ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM)
that has an SPI-compatible interface. See section 37, Quad Serial Peripheral Interface (QSPI).
Controller Area Network (CAN)
module
The Controller Area Network (CAN) module provides functionality to receive and transmit data
using a message-based protocol between multiple slaves and masters in electromagneticallynoisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 35, Controller Area Network (CAN) Module.
USB 2.0 Full-Speed (USBFS) module
The USB 2.0 Full-Speed (USBFS) module can operate as a host controller or device controller.
The module supports full-speed and low-speed (host controller only) transfer as defined in
Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in Universal Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9
can be assigned any endpoint number based on the peripheral devices used for
communication or based on your system. See section 31, USB 2.0 Full-Speed Module
(USBFS).
Ethernet MAC (ETHERC)
One-channel Ethernet MAC Controller (ETHERC) compliant with the Ethernet/IEEE802.3
Media Access Control (MAC) layer protocol. An ETHERC channel provides one channel of the
MAC layer interface, connecting the MCU to the physical layer LSI (PHY-LSI) that allows
transmission and reception of frames compliant with the Ethernet and IEEE802.3 standards.
The ETHERC is connected to the Ethernet DMA Controller (EDMAC) so data can be
transferred without using the CPU.
See section 29, Ethernet MAC Controller (ETHERC).
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Table 1.8
1. Overview
Communication interfaces (2 of 2)
Feature
Functional description
SD/MMC Host Interface (SDHI)
The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to
connect a variety of external memory cards to the MCU. The SDHI supports both 1- and 4-bit
buses for connecting memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD Specifications, you must comply with
the SD Host/Ancillary Product License Agreement (SD HALA).
The MMC interface supports 1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51
(JEDEC Standard JESD 84-B451) device access. This interface also provides backward
compatibility and supports high-speed SDR transfer modes. See section 41, SD/MMC Host
Interface (SDHI).
Table 1.9
Analog
Feature
Functional description
12-bit A/D Converter (ADC12)
Up to two successive approximation 12-bit A/D Converters (ADC12) are provided. In unit 0, up
to 13 analog input channels are selectable. In unit 1, up to nine analog input channels, the
temperature sensor output, and an internal reference voltage are selectable for conversion.
The A/D conversion accuracy is selectable from 12-bit, 10-bit, and 8-bit conversion, making it
possible to optimize the tradeoff between speed and resolution in generating a digital value.
See section 45, 12-Bit A/D Converter (ADC12).
12-bit D/A Converter (DAC12)
The12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section
46, 12-Bit D/A Converter (DAC12).
Temperature sensor (TSN)
The on-chip temperature sensor can determine and monitor the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC12 for conversion and can also be used by the end
application. See section 47, Temperature Sensor (TSN).
High-Speed Analog Comparator
(ACMPHS)
The High-Speed Analog Comparator (ACMPHS) compares a test voltage with a reference
voltage and provides a digital output based on the conversion result.
Both the test and reference voltages can be provided to the comparator from internal sources
such as the DAC12 output and internal reference voltage, and an external source.
Such flexibility is useful in applications that require go/no-go comparisons to be performed
between analog signals without necessarily requiring A/D conversion. See section 48, HighSpeed Analog Comparator (ACMPHS).
Table 1.10
Human machine interfaces
Feature
Functional description
Capacitive Touch Sensing Unit
(CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed with an electrical insulator so that fingers do
not come into direct contact with the electrodes. See section 49, Capacitive Touch Sensing
Unit (CTSU).
Table 1.11
Graphics
Feature
Functional description
Parallel Data Capture (PDC) unit
One Parallel Data Capture (PDC) unit is provided to communicate with external I/O devices,
including image sensors, and to transfer parallel data such as an image output from the
external I/O device through the DTC or DMAC to the on-chip SRAM and external address
spaces (the CS and SDRAM areas). See section 42, Parallel Data Capture Unit (PDC).
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Table 1.12
1. Overview
Data processing
Feature
Functional description
Cyclic Redundancy Check (CRC)
calculator
The CRC calculator generates CRC codes to detect errors in the data. The bit order of CRC
calculation results can be switched for LSB-first or MSB-first communication. Additionally,
various CRC-generating polynomials are available. The snoop function allows monitoring
reads from and writes to specific addresses. This function is useful in applications that require
CRC code to be generated automatically in certain events, such as monitoring writes to the
serial transmit buffer and reads from the serial receive buffer. See section 38, Cyclic
Redundancy Check (CRC) Calculator.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 50,
Data Operation Circuit (DOC).
Sampling Rate Converter (SRC)
The Sampling Rate Converter (SRC) converts the sampling rate of data produced by various
audio decoders, such as the WMA, MP3, and AAC. Both 16-bit stereo and monaural data are
supported.
See section 40, Sampling Rate Converter (SRC).
Table 1.13
Security
Feature
Functional description
Secure Crypto Engine 7 (SCE7)
Security algorithms:
- Symmetric algorithms: AES, 3DES, and ARC4
- Asymmetric algorithms: RSA, DSA, and ECC.
Other support features:
- TRNG (True Random Number Generator)
- Hash-value generation: SHA1, SHA224, SHA256, GHASH, and MD5
- 128-bit unique ID.
See section 44, Secure Cryptographic Engine (SCE7).
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1.2
1. Overview
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the
features.
Memory
Bus
1 MB code flash
External
32 KB data flash
CSC
Arm Cortex-M4
DSP
System
FPU
POR/LVD
MOSC/SOSC
MPU
384 KB SRAM
SDRAM
8 KB Standby
SRAM
MPU
Clocks
Reset
(H/M/L) OCO
NVIC
Mode control
PLL
Power control
CAC
ICU
Battery backup
KINT
Register write
protection
System timer
DMA
Test and DBG interface
DTC
DMAC × 8
Timers
GPT32EH x 4
GPT32E x 4
GPT32 x 6
Communication interfaces
SCI × 10
QSPI
Human machine interfaces
ETHERC
CTSU
IrDA × 1
AGT × 2
RTC
Graphics
PDC
IIC × 3
SDHI × 2
SPI × 2
CAN × 2
SSIE
USBFS
WDT/IWDT
Event link
Data processing
ELC
CRC
Security
DOC
SRC
Analog
ADC12 × 2
TSN
DAC12
ACMPHS × 6
SCE7
Figure 1.1
Block diagram
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 65 of 1734
S5D5 User’s Manual
1.3
1. Overview
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.14 shows a
list of products.
R 7 F S 5 D 5 7C 3 A 0 1 C F B # A A 0
Production identification code
Packaging, Terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
FB: LQFP 144 pins
FP: LQFP 100 pins
LK: LGA 145 pins
Quality ID
Software ID
Operating temperature
2: -40°C to 85°C
3: -40°C to 105°C
Code flash memory size
A: 512 KB
C: 1 MB
Feature set
7: Superset
Group name
D5: S5D5 Group, Arm Cortex-M4, 120 MHz
Series name
5: High integration
Renesas Synergy family
Flash memory
Renesas microcontroller unit
Renesas
Figure 1.2
Table 1.14
Part numbering scheme
Product list
Product part number
Orderable part number
Package
Code
flash
Data
flash
SRAM
Operating
temperature
R7FS5D57C2A01CLK
R7FS5D57C2A01CLK#AC1
PTLG0145KA-A
1 MB
32 KB
384 KB
-40 to +85°C
R7FS5D57C3A01CFB
R7FS5D57C3A01CFB#AA1
PLQP0144KA-B
-40 to +105°C
R7FS5D57C3A01CFP
R7FS5D57C3A01CFP#AA1
PLQP0100KB-B
-40 to +105°C
R7FS5D57A2A01CLK
R7FS5D57A2A01CLK#AC1
PTLG0145KA-A
R7FS5D57A3A01CFB
R7FS5D57A3A01CFB#AA1
PLQP0144KA-B
-40 to +105°C
R7FS5D57A3A01CFP
R7FS5D57A3A01CFP#AA1
PLQP0100KB-B
-40 to +105°C
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
512 KB
-40 to +85°C
Page 66 of 1734
S5D5 User’s Manual
1.4
1. Overview
Function Comparison
Table 1.15
Functional comparison
Part numbers
R7FS5D57C2A01CLK/
R7FS5D57A2A01CLK
Function
R7FS5D57C3A01CFB/
R7FS5D57A3A01CFB
R7FS5D57C3A01CFP/
R7FS5D57A3A01CFP
Pin count
145
144
100
Package
LGA
LQFP
LQFP
Code flash memory
1 MB/512 KB
Data flash memory
32 KB
SRAM
384 KB
Parity
352 KB
ECC
32 KB
Standby SRAM
System
8 KB
CPU clock
120 MHz
Backup registers
512 B
ICU
Yes
KINT
8
Event link
ELC
Yes
DMA
DTC
Yes
BUS
External bus
DMAC
8
16-bit bus
SDRAM
Timers
Communication
4
4
4
GPT32E
4
4
4
GPT32
6
6
5
AGT
2
2
2
RTC
Yes
WDT/IWDT
Yes
SCI
10
3
2
SSIE
1
QSPI
1
SDHI
2
CAN
2
Yes
ETHERC
ADC12
1
22
DAC12
6
TSN
CTSU
Data processing
19
2
ACMPHS
Graphics
2
SPI
USBFS
HMI
No
GPT32EH
IIC
Analog
8-bit bus
Yes
Yes
18
12
PDC
Yes
CRC
Yes
DOC
Yes
SRC
Security
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Yes
SCE7
Page 67 of 1734
S5D5 User’s Manual
1.5
1. Overview
Pin Functions
Table 1.16
Pin functions (1 of 5)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. This is used as the digital power supply for the respective
modules and internal voltage regulator, and used to monitor the voltage of
the POR/LVD. Connect it to the system power supply. Connect this pin to
VSS by a 0.1-μF capacitor. Place the capacitor close to the pin.
Clock
VCL0
-
VCL
-
Connect to VSS through a 0.1-μF smoothing capacitor close to each VCL
pin. Stabilize the internal power supply.
VSS
Input
Ground pin. Connect to the system power supply (0 V).
VBATT
Input
Backup power pin
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input through the
EXTAL pin.
XCIN
Input
XCOUT
Output
Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
EBCLK
Output
Outputs the external bus clock for external devices
SDCLK
Output
Outputs the SDRAM-dedicated clock
CLKOUT
Output
Clock output pin
Operating mode
control
MD
Input
Pin for setting the operating mode. The signal level on this pin must not be
changed during operation mode transition on release from the reset state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this signal goes
low.
CAC
CACREF
Input
Measurement reference clock input pin
Interrupt
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ15
Input
Maskable interrupt request pins
KINT
KR00 to KR07
Input
A key interrupt can be generated by inputting a falling edge to the key
interrupt input pins
On-chip emulator
TMS
I/O
On-chip emulator or boundary scan pins
TDI
Input
TCK
Input
TDO
Output
External bus
interface
TCLK
Output
TDATA0 to TDATA3
Output
Trace data output
SWDIO
I/O
Serial wire debug data input/output pin
SWCLK
Input
Serial wire clock pin
SWO
Output
Serial wire trace output pin
RD
Output
Strobe signal indicating that reading from the external bus interface space is
in progress, active-low
WR
Output
Strobe signal indicating that writing to the external bus interface space is in
progress, in 1-write strobe mode, active-low
WR0 to WR1
Output
Strobe signals indicating that either group of data bus pins (D07 to D00 or
D15 to D08) is valid in writing to the external bus interface space, in byte
strobe mode, active-low
BC0 to BC1
Output
Strobe signals indicating that either group of data bus pins (D07 to D00 or
D15 to D08) is valid in access to the external bus interface space, in 1-write
strobe mode, active-low
ALE
Output
Address latch signal when address/data multiplexed bus is selected
WAIT
Input
Input pin for wait request signals in access to the external space, active-low
CS0 to CS7
Output
Select signals for CS areas, active-low
A00 to A20
Output
Address bus
D00 to D15
I/O
Data bus
A00/D00 to A15/D15
I/O
Address/data multiplexed bus
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
This pin outputs the clock for synchronization with the trace data
Page 68 of 1734
S5D5 User’s Manual
Table 1.16
1. Overview
Pin functions (2 of 5)
Function
Signal
I/O
Description
SDRAM interface
CKE
Output
SDRAM clock enable signal
GPT
AGT
RTC
SCI
IIC
SSIE
SDCS
Output
SDRAM chip select signal, active-low
RAS
Output
SDRAM low address strobe signal, active-low
CAS
Output
SDRAM column address strobe signal, active-low
WE
Output
SDRAM write enable signal, active-low
DQM0
Output
SDRAM I/O data mask enable signal for DQ07 to DQ00
DQM1
Output
SDRAM I/O data mask enable signal for DQ15 to DQ08
A00 to A15
Output
Address bus
DQ00 to DQ15
I/O
Data bus
GTETRGA,
GTETRGB,
GTETRGC,
GTETRGD
Input
External trigger input pins
GTIOC0A to
GTIOC13A,
GTIOC0B to
GTIOC13B
I/O
Input capture, output compare, or PWM output pins
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U phase)
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W phase)
AGTEE0, AGTEE1
Input
External event input enable signals
AGTIO0, AGTIO1
I/O
External event input and pulse output pins
AGTO0, AGTO1
Output
Pulse output pins
AGTOA0, AGTOA1
Output
Output compare match A output pins
AGTOB0, AGTOB1
Output
Output compare match B output pins
RTCOUT
Output
Output pin for 1-Hz or 64-Hz clock
RTCIC0 to RTCIC2
Input
Time capture event input pins
SCK0 to SCK9
I/O
Input/output pins for the clock (clock synchronous mode)
RXD0 to RXD9
Input
Input pins for received data (asynchronous mode/clock synchronous mode)
TXD0 to TXD9
Output
Output pins for transmitted data (asynchronous mode/clock synchronous
mode)
CTS0_RTS0 to
CTS9_RTS9
I/O
Input/output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active-low
SCL0 to SCL9
I/O
Input/output pins for the IIC clock (simple IIC mode)
SDA0 to SDA9
I/O
Input/output pins for the IIC data (simple IIC mode)
SCK0 to SCK9
I/O
Input/output pins for the clock (simple SPI mode)
MISO0 to MISO9
I/O
Input/output pins for slave transmission of data (simple SPI mode)
MOSI0 to MOSI9
I/O
Input/output pins for master transmission of data (simple SPI mode)
SS0 to SS9
Input
Chip-select input pins (simple SPI mode), active-low
SCL0 to SCL2
I/O
Input/output pins for the clock
SDA0 to SDA2
I/O
Input/output pins for data
SSIBCK0
I/O
SSIE serial bit clock pins
SSILRCK0/SSIFS0
I/O
LR clock/frame synchronization pins
SSITXD0
Output
Serial data output pins
SSIRXD0
Input
Serial data input pins
SSIDATA0
I/O
Serial data input/output pins
AUDIO_CLK
Input
External clock pin for audio (input oversampling clock)
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Aug 30, 2019
Page 69 of 1734
S5D5 User’s Manual
Table 1.16
1. Overview
Pin functions (3 of 5)
Function
Signal
I/O
SPI
RSPCKA, RSPCKB
I/O
Clock input/output pin
MOSIA, MOSIB
I/O
Input or output pins for data output from the master
QSPI
CAN
USBFS
Description
MISOA, MISOB
I/O
Input or output pins for data output from the slave
SSLA0, SSLB0
I/O
Input or output pin for slave selection
SSLA1 to SSLA3,
SSLB1 to SSLB3
Output
Output pins for slave selection
QSPCLK
Output
QSPI clock output pin
QSSL
Output
QSPI slave output pin
QIO0 to QIO3
I/O
Data0 to Data3
CRX0, CRX1
Input
Receive data
CTX0, CTX1
Output
Transmit data
VCC_USB
Input
Power supply pins
VSS_USB
Input
Ground pins
USB_DP
I/O
D+ I/O pin of the USB on-chip transceiver. Connect this pin to the D+ pin of
the USB bus
USB_DM
I/O
D- I/O pin of the USB on-chip transceiver. Connect this pin to the D- pin of
the USB bus
USB_VBUS
Input
USB cable connection monitor pin. Connect this pin to VBUS of the USB
bus. The VBUS pin status (connected or disconnected) can be detected
when the USB module is operating as a device controller.
USB_EXICEN
Output
Low-power control signal for external power supply (OTG) chip
USB_VBUSEN
Output
VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA,
USB_OVRCURB
Input
Connect the external overcurrent detection signals to these pins. Connect
the VBUS comparator signals to these pins when the OTG power supply
chip is connected.
USB_ID
Input
Connect the MicroAB connector ID input signal to this pin during operation in
OTG mode
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Page 70 of 1734
S5D5 User’s Manual
Table 1.16
1. Overview
Pin functions (4 of 5)
Function
Signal
I/O
Description
ETHERC
REF50CK0
Input
50-MHz reference clock. This pin inputs reference signal for
transmission/reception timing in RMII mode.
RMII0_CRS_DV
Input
Indicates carrier detection signals and valid receive data on RMII0_RXD1
and RMII0_RXD0 in RMII mode
RMII0_TXD0,
RMII0_TXD1
Output
2-bit transmit data in RMII mode
RMII0_RXD0,
RMII0_RXD1
Input
2-bit receive data in RMII mode
SDHI
Analog power
supply
RMII0_TXD_EN
Output
Output pin for data transmit enable signal in RMII mode
RMII0_RX_ER
Input
Indicates an error occurred during reception of data in RMII mode
ET0_CRS
Input
Carrier detection/data reception enable signal
ET0_RX_DV
Input
Indicates valid receive data on ET0_ERXD3 to ET0_ERXD0
ET0_EXOUT
Output
General-purpose external output pin
ET0_LINKSTA
Input
Input link status from the PHY-LSI
ET0_ETXD0 to
ET0_ETXD3
Output
4 bits of MII transmit data
ET0_ERXD0 to
ET0_ERXD3
Input
4 bits of MII receive data
ET0_TX_EN
Output
Transmit enable signal. Functions as signal indicating that transmit data is
ready on ET0_ETXD3 to ET0_ETXD0
ET0_TX_ER
Output
Transmit error pin. Functions as signal notifying the PHY_LSI of an error
during transmission
ET0_RX_ER
Input
Receive error pin. Functions as signal to recognize an error during reception
ET0_TX_CLK
Input
Transmit clock pin. This pin inputs reference signal for output timing from
ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0, and ET0_TX_ER
ET0_RX_CLK
Input
Receive clock pin. This pin inputs reference signal for input timing to
ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and ET0_RX_ER
ET0_COL
Input
Input collision detection signal
ET0_WOL
Output
Receive Magic packets
ET0_MDC
Output
Output reference clock signal for information transfer through ET0_MDIO
ET0_MDIO
I/O
Input or output bidirectional signal for exchange of management data with
PHY-LSI
SD0CLK, SD1CLK
Output
SD clock output pins
SD0CMD, SD1CMD
I/O
Command output pin and response input signal pins
SD0DAT0 to
SD0DAT7,
SD1DAT0 to
SD1DAT7
I/O
SD and MMC data bus pins
SD0CD, SD1CD
Input
SD card detection pins
SD0WP
Input
SD write-protect signals
AVCC0
Input
Analog voltage supply pin. This is used as the analog power supply for the
respective modules. Supply this pin with the same voltage as the VCC pin.
AVSS0
Input
Analog ground pin. This is used as the analog ground for the respective
modules. Supply this pin with the same voltage as the VSS pin.
VREFH0
Input
Analog reference voltage supply pin for the ADC12 (unit 0). Connect this pin
to VCC when not using the ADC12 (unit 0) and sample-and-hold circuit for
AN000 to AN002.
VREFL0
Input
Analog reference ground pin for the ADC12. Connect this pin to VSS when
not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to
AN002
VREFH
Input
Analog reference voltage supply pin for the ADC12 (unit 1) and D/A
Converter. Connect this pin to VCC when not using the ADC12 (unit 1),
sample-and-hold circuit for AN100 to AN102, and D/A Converter.
VREFL
Input
Analog reference ground pin for the ADC12 and D/A Converter. Connect this
pin to VSS when not using the ADC12 (unit 1), sample-and-hold circuit for
AN100 to AN102, and D/A Converter.
R01UM0009EU0130 Rev.1.30
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Page 71 of 1734
S5D5 User’s Manual
Table 1.16
1. Overview
Pin functions (5 of 5)
Function
Signal
I/O
Description
ADC12
AN000 to AN007,
AN016 to AN020
Input
Input pins for the analog signals to be processed by the ADC12
AN100 to AN102,
AN105 to AN107,
AN116 to AN118
Input
ADTRG0
Input
ADTRG1
Input
Input pins for the external trigger signals that start the A/D conversion
DAC12
DA0, DA1
Output
Output pins for the analog signals processed by the D/A converter
ACMPHS
VCOUT
Output
Comparator output pin
CTSU
I/O ports
PDC
IVREF0 to IVREF3
Input
Reference voltage input pins for comparator
IVCMP0 to IVCMP2
Input
Analog voltage input pins for comparator
TS00 to TS17
Input
Capacitive touch detection pins (touch pins)
TSCAP
-
Secondary power supply pin for the touch driver
P000 to P009,
P014, P015
I/O
General-purpose input/output pins
P100 to P115
I/O
General-purpose input/output pins
P200
Input
General-purpose input pin
P201 to P214
I/O
General-purpose input/output pins
P300 to P313
I/O
General-purpose input/output pins
P400 to P415
I/O
General-purpose input/output pins
P500 to P506,
P508, P511, P512
I/O
General-purpose input/output pins
P600 to P605,
P608 to P614
I/O
General-purpose input/output pins
P700 to P705,
P708 to P713
I/O
General-purpose input/output pins
General-purpose input/output pins
P800, P801
I/O
PIXCLK
Input
Image transfer clock pin
VSYNC
Input
Vertical synchronization signal pin
HSYNC
Input
Horizontal synchronization signal pin
PIXD0 to PIXD7
Input
8-bit image data pins
PCKO
Output
Output pin for dot clock
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 72 of 1734
S5D5 User’s Manual
1.6
1. Overview
Pin Assignments
Figure 1.3 to Figure 1.5 show the pin assignments.
R7FS5D57XXA01CLK
13
A
B
C
D
E
F
G
H
J
K
L
M
N
P407
P409
P412
P708
P711
VCC
P212
/EXTAL
XCIN
VCL0
P702
P405
P402
P400
13
P410
P414
P710
VSS
P213
/XTAL
XCOUT
VBATT
P701
P404
P511
VCC
12
12 USB_DM USB_DP
11
VCC_
USB
VSS_
USB
P207
P411
P415
P712
P705
P704
P703
P403
P401
P512
VSS
11
10
P205
P206
P204
P408
P413
P709
P713
P700
P406
P003
P000
P002
P001
10
9
P203
P313
P202
VSS
P004
P006
P009
P008
9
8
P214
P211
P200
VCC
P005
AVSS0
VREFL0
VREFH0
8
7
P210
P209
RES
P310
P007
AVCC0
VREFL
VREFH
7
6
P208
P201/MD
P312
P305
P505
P506
P015
P014
6
5
P309
P311
P308
P303
NC
P503
P504
VSS
VCC
5
4
P307
P306
P304
P109/TDO
P114
P608
P604
P600
P105
P500
P502
P501
P508
4
3
VSS
VCC
P301
P112
P115
P610
P614
P603
P107
P106
P104
VSS
VCC
3
2
P302
P300/TCK
/SWCLK
P111
VCC
P609
P612
VSS
P605
P601
VCC
P800
P101
P801
2
P108/TMS
P110/TDI
/SWDIO
P113
VSS
P611
P613
VCC
VCL
P602
VSS
P103
P102
P100
1
C
D
E
F
G
H
J
K
L
M
N
1
A
Figure 1.3
B
Pin assignment for 145-pin LGA (top view)
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 73 of 1734
VSS
VCC
P614
P613
P612
P611
P610
P609
P608
VSS
VCC
P115
P114
P113
P112
P111
P110/TDI
P109/TDO
P108/TMS/SWDIO
91
90
89
88
87
85
83
81
79
76
75
74
73
VCL
92
77
P604
P605
94
78
P602
P603
96
80
P601
97
82
VCC
P600
99
84
VSS
100
86
P107
101
93
P106
102
95
P104
P105
104
98
P102
P103
103
P101
106
105
P100
107
1. Overview
108
S5D5 User’s Manual
P800
109
72
P300/TCK/SWCLK
P801
110
71
P301
VCC
111
70
P302
VSS
112
69
P303
P500
113
68
P501
114
67
VCC
VSS
P502
P503
115
66
P304
116
65
P305
P504
117
64
P306
P505
118
63
P307
P506
119
62
P308
P508
120
61
P309
VCC
121
60
P310
VSS
122
59
P015
123
58
P311
P312
P014
124
57
VREFL
VREFH
125
56
P200
P201/MD
55
RES
AVCC0
127
54
P208
AVSS0
128
53
P209
VREFL0
129
52
P210
VREFH0
130
51
P211
P009
P008
131
50
P214
132
49
VCC
P007
133
48
P006
134
47
VSS
P313
P005
135
46
P004
136
45
P202
P203
P003
137
44
P204
P002
138
43
P205
P001
P000
139
42
P206
140
41
P207
VSS
VCC
P512
141
40
142
39
143
38
VCC_USB
USB_DP
USB_DM
P511
144
37
VSS_USB
Figure 1.4
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
P705
VBATT
VCL0
XCIN
XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P713
P712
P711
P710
P709
P708
P415
P414
P413
P412
P411
P410
P409
P408
P407
32
12
P704
14
11
10
9
P701
P702
5
P404
P405
8
4
P403
7
3
P402
P406
P700
2
P401
6
1
P400
P703
R7FS5D57XXA01CFB
126
Pin assignment for 144-pin LQFP (top view)
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 74 of 1734
Figure 1.5
P100
P101
P102
P103
P104
P105
P106
P107
P600
P601
P602
VCL
VSS
VCC
P610
P609
P608
P115
P114
P113
P112
P111
P110/TDI
P109/TDO
P108/TMS/SWDIO
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1. Overview
75
S5D5 User’s Manual
P500
76
50
P501
77
49
P300/TCK/SWCLK
P301
P502
78
48
P302
P503
79
47
P303
P504
80
46
VCC
P508
81
45
VSS
VCC
82
44
P304
VSS
83
43
P305
P015
84
42
P306
P014
85
41
P307
VREFL
86
40
P200
VREFH
87
39
P201/MD
AVCC0
88
38
RES
AVSS0
89
37
P208
VREFL0
90
36
P209
VREFH0
91
35
P210
P008
92
34
P211
P007
93
33
P214
P006
94
32
P205
P005
95
31
P206
P004
96
30
P207
P003
97
29
VCC_USB
P002
98
28
USB_DP
P001
99
27
USB_DM
P000
100
26
VSS_USB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P400
P401
P402
P403
P404
P405
P406
VBATT
VCL0
XCIN
XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P708
P415
P414
P413
P412
P411
P410
P409
P408
P407
R7FS5D57XXA01CFP
Pin assignment for 100-pin LQFP (top view)
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 75 of 1734
S5D5 User’s Manual
Pin Lists
N13
1
1
-
IRQ0
P400 -
-
AGTIO1 -
L11
2
2
-
IRQ5- P401 DS
-
-
GTIOC 6A
M13 3
3
CACREF IRQ4- P402 DS
-
AGTIO0/ AGTIO1
-
K11
4
4
-
-
P403 -
-
AGTIO0/ AGTIO1
GTIOC RTCI 3A
C1
L12
5
5
-
-
P404 -
-
-
-
L13
6
6
-
-
P405 -
-
-
-
GTETRGA GTIOC 6B
-
SCK4
SCK7
SCL0 _A
CTX0 CTS4_R TXD7/M SDA0 TS4/SS4 OSI7/SD _A
A7
RTCI CRX0 C0
HMI
PDC
CTSU
DAC12,
ACMPHS
ADC12
SDHI
ETHERC (RMII)
(50 MHz)
ETHERC (MII)
(25 MHz)
SSIE
SPI, QSPI
Analog
IIC
SCI1,3,5,7,9
(30 MHz)
SCI0,2,4,6,8
(30 MHz)
GPT
AGT
Communication interfaces
RTC
USBFS,
CAN
Timers
GPT
External bus
I/O port
Interrupt
LQFP144
LGA145
Extbus
LQFP100
Power, System,
Clock, Debug,
CAC
Pin number
SDRAM
1.7
1. Overview
AUDIO ET0_WOL ET0_WOL _CLK
ADTRG 1
-
-
-
ET0_MDC ET0_MDC -
-
-
-
-
RXD7/MI SO7/SC
L7
-
AUDIO ET0_MDI ET0_MDI _CLK O
O
-
-
-
VSYNC
-
CTS7_R TS7/SS7
-
SSIBC ET0_LINK ET0_LINK SD1DA K0_A STA
STA
T7_B
-
-
PIXD7
GTIOC RTCI 3B
C2
-
-
-
-
SSILR ET0_EXO ET0_EXO SD1DA UT
T6_B
CK0/S UT
SIFS0
_A
-
-
PIXD6
GTIOC 1A
-
-
-
-
SSITX ET0_TX_ RMII0_TX SD1DA D0_A EN
D_EN_B T5_B
-
-
PIXD5
-
J10
7
7
-
-
P406 -
-
-
-
GTIOC 1B
-
-
-
-
SSLB3 SSIRX ET0_RX_ RMII0_TX SD1DA _C
D0_A ER
D1_B
T4_B
-
-
PIXD4
H10
8
-
-
-
P700 -
-
-
-
GTIOC 5A
-
-
-
-
MISOB _C
ET0_ETX RMII0_TX SD1DA D1
D0_B
T3_B
-
-
PIXD3
K12
9
-
-
-
P701 -
-
-
-
GTIOC 5B
-
-
-
-
MOSIB _C
ET0_ETX REF50CK SD1DA D0
0_B
T2_B
-
-
PIXD2
K13
10
-
-
-
P702 -
-
-
-
GTIOC 6A
-
-
-
-
RSPC KB_C
ET0_ERX RMII0_RX SD1DA D1
D0_B
T1_B
-
-
PIXD1
J11
11
-
-
-
P703 -
-
-
-
GTIOC 6B
-
-
-
-
SSLB0 _C
ET0_ERX RMII0_RX SD1DA D0
D1_B
T0_B
VCOUT -
PIXD0
H11
12
-
-
-
P704 -
-
AGTO0
-
-
-
CTX0 -
-
-
SSLB1 _C
ET0_RX_ RMII0_RX SD1CL CLK
_ER_B
K_B
-
-
HSYNC
G11
13
-
-
-
P705 -
-
AGTIO0 -
-
-
CRX0 -
-
-
SSLB2 _C
ET0_CRS RMII0_CR SD1CM S_DV_B D_B
-
-
PIXCLK
J12
14
8
VBATT
-
-
-
-
-
-
J13
15
9
VCL0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H13
16
10
XCIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H12
17
11
XCOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F12
18
12
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G12 19
13
XTAL
IRQ2
P213 -
-
-
GTETRGC GTIOC 0A
-
-
TXD1/M OSI1/SD
A1
-
-
-
-
-
ADTRG 1
-
-
G13 20
14
EXTAL
IRQ3
P212 -
-
AGTEE1 GTETRGD GTIOC 0B
-
-
RXD1/MI SO1/SC
L1
-
-
-
-
-
-
-
-
-
F13
15
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P713 -
-
AGTOA0 -
GTIOC 2A
-
-
-
-
-
-
-
-
-
-
-
TS17
-
21
G10 22
-
-
F11
23
-
-
-
P712 -
-
AGTOB0 -
GTIOC 2B
-
-
-
-
-
-
-
-
-
-
-
TS16
-
E13
24
-
-
-
P711 -
-
AGTEE0 -
-
-
-
-
CTS1_R TS1/SS1
-
-
ET0_TX_ CLK
-
-
-
TS15
-
E12
25
-
-
-
P710 -
-
-
-
-
-
-
-
SCK1
-
-
-
ET0_TX_ ER
-
-
-
TS14
-
F10
26
-
-
IRQ10 P709 -
-
-
-
-
-
-
-
TXD1/M OSI1/SD
A1
-
-
ET0_ETX D2
-
-
-
TS13
-
D13
27
16
CACREF IRQ11 P708 -
-
-
-
-
-
-
-
RXD1/MI SO1/SC
L1
SSLA3 AUDIO ET0_ETX _B
_CLK D3
-
-
-
TS12
PCKO
E11
28
17
-
IRQ8
P415 -
-
-
-
GTIOC 0A
USB_ VBUS
EN
-
SSLA2 _B
ET0_TX_ RMII0_TX SD0CD EN
D_EN_A
-
TS11
PIXD5
-
D12
29
18
-
IRQ9
P414 -
-
-
-
GTIOC 0B
-
-
-
-
SSLA1 _B
ET0_RX_ RMII0_TX SD0WP ER
D1_A
-
TS10
PIXD4
E10
30
19
-
-
P413 -
-
-
GTOUUP
-
-
-
CTS0_R TS0/SS0
-
SSLA0 _B
ET0_ETX RMII0_TX SD0CL D1
D0_A
K_A
-
TS09
PIXD3
C13
31
20
-
-
P412 -
-
AGTEE1 GTOULO
-
-
-
SCK0
-
RSPC KA_B
ET0_ETX REF50CK SD0CM D0
0_A
D_A
-
TS08
PIX02
D11
32
21
-
IRQ4
P411 -
-
AGTOA1 GTOVUP
GTIOC 9A
-
TXD0/M CTS3_R OSI0/SD TS3/SS3
A0
MOSIA _B
ET0_ERX RMII0_RX SD0DA D1
D0_A
T0_A
-
TS07
PIX01
C12
33
22
-
IRQ5
P410 -
-
AGTOB1 GTOVLO
GTIOC 9B
-
RXD0/MI SCK3
SO0/SC
L0
MISOA _B
ET0_ERX RMII0_RX SD0DA D0
D1_A
T1_A
-
TS06
PIXD0
B13
34
23
-
IRQ6
P409 -
-
-
GTOWUP GTIOC 10A
USB_ EXICE
N
TXD3/M OSI3/SD
A3
-
-
ET0_RX_ RMII0_RX CLK
_ER_A
-
-
TS05
HSYNC
D10
35
24
-
IRQ7
P408 -
-
-
GTOWLO GTIOC 10B
USB_I D
RXD3/MI SCL0 SO3/SC _B
L3
-
ET0_CRS RMII0_CR S_DV_A
-
-
TS04
PIXCLK
A13
36
25
-
-
P407 -
-
AGTIO0 -
-
RTC USB_ CTS4_R OUT VBUS TS4/SS4
B11
37
26
VSS_US B
-
-
-
-
-
-
-
-
-
-
SDA0 SSLB3 _B
_A
ET0_EXO ET0_EXO UT
UT
ADTRG 0
TS03
-
-
-
-
-
-
-
-
-
-
-
-
-
A12
38
27
-
-
-
-
-
-
-
-
-
USB_ DM
-
-
-
-
-
-
-
-
-
-
B12
39
28
-
-
-
-
-
-
-
-
-
USB_ DP
-
-
-
-
-
-
-
-
-
-
-
A11
40
29
VCC_US B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
-
Page 76 of 1734
S5D5 User’s Manual
1. Overview
P207 A17
-
-
C11
41
30
-
-
-
-
-
-
-
-
B10
42
31
-
IRQ0- P206 WAI DS
T
-
GTIU
-
-
USB_ RXD4/MI VBUS SO4/SC
EN
L4
A10
43
32
CLKOUT IRQ1- P205 A16
DS
-
AGTO1
GTIV
GTIOC 4A
USB_ TXD4/M CTS9_R SCL1 SSLB0
_A
OVRC OSI4/SD TS9/SS9 _A
URA- A4
DS
C10
44
-
CACREF -
P204 A18
-
AGTIO1 GTIW
GTIOC 4B
USB_ SCK4
OVRC
URBDS
A9
45
-
-
IRQ2- P203 A19
DS
-
-
-
GTIOC 5A
CTX0 CTS2_R TXD9/M TS2/SS2 OSI9/SD
A9
MOSIB _A
C9
46
-
-
IRQ3- P202 WR1 DS
/BC1
-
-
GTIOC 5B
CRX0 SCK2
MISOB
_A
SCK9
-
SSLB2 _A/QS
SL
-
-
PDC
CTSU
-
-
TS02
-
SDA1 SSLB1 SSIDA ET0_LINK ET0_LINK SD0DA _A
_A
TA0_C STA
STA
T2_A
-
TS01
-
SSILR ET0_WOL ET0_WOL SD0DA T3_A
CK0/S
SIFS0
_C
-
TSCA
P
-
SD0DA T4_A
-
TS00
-
ET0_COL -
SD0DA T5_A
-
TSCA
P
-
ET0_ERX D2
SD0DA T6_A
-
-
-
SCL0 RSPC SSIBC ET0_RX_ _B
KB_A K0_C DV
RXD9/MI SO9/SC
L9
-
HMI
DAC12,
ACMPHS
ADC12
SDHI
ETHERC (RMII)
(50 MHz)
ETHERC (MII)
(25 MHz)
SSIE
SPI, QSPI
Analog
IIC
SCI1,3,5,7,9
(30 MHz)
SCI0,2,4,6,8
(30 MHz)
GPT
GPT
AGT
Communication interfaces
RTC
USBFS,
CAN
Timers
SDRAM
I/O port
Interrupt
External bus
Extbus
LQFP100
Power, System,
Clock, Debug,
CAC
LQFP144
LGA145
Pin number
B9
47
-
-
-
P313 A20
-
-
-
-
-
-
-
-
-
-
-
ET0_ERX D3
SD0DA T7_A
-
-
-
D9
48
-
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D8
49
-
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A8
50
33
TRCLK
-
P214 -
-
-
GTIU
-
-
-
-
-
-
QSPC LK
ET0_MDC ET0_MDC SD0CL K_B
-
-
-
B8
51
34
TRDATA 0
P211 CS7 -
-
GTIV
-
-
-
-
-
-
QIO0
ET0_MDI ET0_MDI SD0CM O
O
D_B
-
-
-
A7
52
35
TRDATA 1
P210 CS6 -
-
GTIW
-
-
-
-
-
-
QIO1
-
ET0_WOL ET0_WOL SD0CD -
-
-
-
B7
53
36
TRDATA 2
P209 CS5 -
-
GTOVUP
-
-
-
-
-
-
QIO2
-
ET0_EXO ET0_EXO SD0WP UT
UT
-
-
-
-
A6
54
37
TRDATA 3
P208 CS4 -
-
GTOVLO
-
-
-
-
-
-
QIO3
-
ET0_LINK ET0_LINK SD0DA STA
STA
T0_B
-
-
-
C7
55
38
RES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B6
56
39
MD
-
P201 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C8
57
40
-
NMI
P200 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C6
58
-
-
-
P312 CS3 CAS
AGTOA1 -
-
-
-
-
CTS3_R TS3/SS3
-
-
-
-
-
-
-
-
-
B5
59
-
-
-
P311 CS2 RAS
AGTOB1 -
-
-
-
-
SCK3
-
-
-
-
-
-
-
-
-
-
D7
60
-
-
-
P310 A15
A15
AGTEE1 -
-
-
-
-
TXD3
-
QIO3
-
-
-
-
-
-
-
-
A5
61
-
-
-
P309 A14
A14
-
-
-
-
-
-
RXD3
-
QIO2
-
-
-
-
-
-
-
-
C5
62
-
-
-
P308 A13
A13
-
-
-
-
-
-
-
-
QIO1
-
-
-
-
-
-
-
-
A4
63
41
-
-
P307 A12
A12
-
GTOUUP
-
-
-
CTS6
-
-
QIO0
-
-
-
-
-
-
-
-
B4
64
42
-
-
P306 A11
A11
-
GTOULO
-
-
-
SCK6
-
-
QSSL
-
-
-
-
-
-
-
-
D6
65
43
-
IRQ8
P305 A10
A10
-
GTOWUP -
-
-
TXD6/M OSI6/SD
A6
-
QSPC LK
-
-
-
-
-
-
-
C4
66
44
-
IRQ9
P304 A09
A09
-
GTOWLO GTIOC 7A
-
RXD6/MI SO6/SC
L6
-
-
-
-
-
-
-
-
-
A3
67
45
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B3
68
46
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D5
69
47
-
-
P303 A08
A08
-
-
GTIOC 7B
-
-
-
-
-
-
-
-
-
-
-
-
-
A2
70
48
-
IRQ5
P302 A07
A07
-
GTOUUP
GTIOC 4A
-
TXD2/M OSI2/SD
A2
-
SSLB3 _B
-
-
-
-
-
-
-
C3
71
49
-
IRQ6
P301 A06
A06
AGTIO0 GTOULO
GTIOC 4B
-
RXD2/MI CTS9_R SO2/SC TS9/SS9
L2
SSLB2 _B
-
-
-
-
-
-
-
B2
72
50
TCK/SW CLK
P300 -
-
-
GTOUUP
GTIOC 0A_A
-
-
-
-
SSLB1 _B
-
-
-
-
-
-
-
A1
73
51
TMS/SW DIO
P108 -
-
-
GTOULO
GTIOC 0B_A
-
-
CTS9_R TS9/SS9
SSLB0 _B
-
-
-
-
-
-
-
D4
74
52
CLKOUT /TDO/S
WO
P109 -
-
-
GTOVUP
GTIOC 1A_A
CTX1 -
TXD9/M OSI9/SD
A9
MOSIB _B
-
-
-
-
-
-
-
B1
75
53
TDI
IRQ3
P110 -
-
-
GTOVLO
GTIOC 1B_A
CRX1 CTS2_R RXD9/MI TS2/SS2 SO9/SC
L9
MISOB _B
-
-
-
-
VCOUT -
-
C2
76
54
-
IRQ4
P111 A05
A05
-
-
GTIOC 3A_A
-
SCK2
SCK9
-
RSPC KB_B
-
-
-
-
-
-
-
D3
77
55
-
-
P112 A04
A04
-
-
GTIOC 3B_A
-
TXD2/M SCK1
OSI2/SD
A2
-
SSLB0 SSIBC _B
K0_B
-
-
-
-
-
-
C1
78
56
-
-
P113 A03
A03
-
-
GTIOC 2A
-
RXD2/MI SO2/SC
L2
-
-
SSILR CK0/S
SIFS0
_B
-
-
-
-
-
-
E4
79
57
-
-
P114 A02
A02
-
-
GTIOC 2B
-
-
-
-
-
SSIRX D0_B
-
-
-
-
-
-
E3
80
58
-
-
P115 A01
A01
-
-
GTIOC 4A
-
-
-
-
-
SSITX D0_B
-
-
-
-
-
-
D2
81
-
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D1
82
-
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F4
83
59
-
-
P608 A00/ A00/D BC0 QM1
-
GTIOC 4B
-
-
-
-
-
-
-
-
-
-
-
-
-
E2
84
60
-
-
P609 CS1 CKE
-
-
GTIOC 5A
CTX1 -
-
-
-
-
-
-
-
-
-
-
-
F3
85
61
-
-
P610 CS0 WE
-
-
GTIOC 5B
CRX1 -
-
-
-
-
-
-
-
-
-
-
-
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Aug 30, 2019
Page 77 of 1734
S5D5 User’s Manual
1. Overview
HMI
PDC
CTSU
DAC12,
ACMPHS
ADC12
SDHI
ETHERC (RMII)
(50 MHz)
ETHERC (MII)
(25 MHz)
SSIE
SPI, QSPI
Analog
IIC
SCI1,3,5,7,9
(30 MHz)
SCI0,2,4,6,8
(30 MHz)
GPT
GPT
AGT
Communication interfaces
RTC
USBFS,
CAN
Timers
SDRAM
I/O port
Interrupt
External bus
Extbus
LQFP100
Power, System,
Clock, Debug,
CAC
LQFP144
LGA145
Pin number
E1
86
-
CLKOUT /CACRE
F
P611 -
SDCS -
-
-
-
-
-
CTS7_R TS7/SS7
-
-
-
-
-
-
-
-
-
F2
87
-
-
-
P612 D08[ DQ08 A08/
D08]
-
-
-
-
-
SCK7
-
-
-
-
-
-
-
-
-
-
F1
88
-
-
-
P613 D09[ DQ09 A09/
D09]
-
-
-
-
-
TXD7
-
-
-
-
-
-
-
-
-
-
G3
89
-
-
-
P614 D10[ DQ10 A10/
D10]
-
-
-
-
-
RXD7
-
-
-
-
-
-
-
-
-
-
G1
90
62
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G2
91
63
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H1
92
64
VCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H2
93
-
-
-
P605 D11[ DQ11 A11/
D11]
-
GTIOC 8A
-
-
-
-
-
-
-
-
-
-
-
-
-
G4
94
-
-
-
P604 D12[ DQ12 A12/
D12]
-
GTIOC 8B
-
-
-
-
-
-
-
-
-
-
-
-
-
H3
95
-
-
-
P603 D13[ DQ13 A13/
D13]
-
GTIOC 7A
-
-
CTS9_R TS9/SS9
-
-
-
-
-
-
-
-
-
J1
96
65
-
-
P602 EBC SDCL LK
K
-
GTIOC 7B
-
-
TXD9
-
-
-
-
-
-
-
-
-
-
-
J2
97
66
-
P601 WR/ DQM0 WR0
-
GTIOC 6A
-
-
RXD9
-
-
-
-
-
-
-
-
-
-
H4
98
67
CLKOUT /CACRE
F
P600 RD
-
-
-
GTIOC 6B
-
-
SCK9
-
-
-
-
-
-
-
-
-
-
K2
99
-
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K1
100
-
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J3
101
68
-
KR07 P107 D07[ DQ07 AGTOA0 A07/
D07]
GTIOC 8A
-
CTS8_R TS8/SS8
-
-
-
-
-
-
-
-
-
-
K3
102
69
-
KR06 P106 D06[ DQ06 AGTOB0 A06/
D06]
GTIOC 8B
-
SCK8
-
-
SSLA3 _A
-
-
-
-
-
-
-
J4
103
70
-
IRQ0/ P105 D05[ DQ05 KR05
A05/
D05]
GTETRGA GTIOC 1A
-
TXD8/M OSI8/SD
A8
-
SSLA2 _A
-
-
-
-
-
-
-
L3
104
71
-
IRQ1/ P104 D04[ DQ04 KR04
A04/
D04]
GTETRGB GTIOC 1B
-
RXD8/MI SO8/SC
L8
-
SSLA1 _A
-
-
-
-
-
-
-
L1
105
72
-
KR03 P103 D03[ DQ03 A03/
D03]
GTOWUP GTIOC 2A_A
CTX0 CTS0_R TS0/SS0
-
SSLA0 _A
-
-
-
-
-
-
-
M1
106
73
-
KR02 P102 D02[ DQ02 AGTO0
A02/
D02]
GTOWLO GTIOC 2B_A
CRX0 SCK0
-
RSPC KA_A
-
-
-
ADTRG 0
-
-
M2
107
74
-
IRQ1/ P101 D01[ DQ01 AGTEE0 GTETRGB GTIOC KR01
A01/
5A
D01]
-
TXD0/M CTS1_R SDA1 MOSIA OSI0/SD TS1/SS1 _B
_A
A0
-
-
-
-
-
-
-
N1
108
75
-
IRQ2/ P100 D00[ DQ00 AGTIO0 GTETRGA GTIOC KR00
A00/
5B
D00]
-
RXD0/MI SCK1
SO0/SC
L0
SCL1 MISOA _B
_A
-
-
-
-
-
-
-
L2
109
-
-
-
P800 D14[ DQ14 A14/
D14]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N2
110
-
-
-
P801 D15[ DQ15 A15/
D15]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N3
111
-
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M3
112
-
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K4
113
76
-
-
P500 -
-
AGTOA0 GTIU
GTIOC 11A
USB_ VBUS
EN
-
-
QSPC LK
-
-
SD1CL AN016
K_A
IVREF0 -
-
M4
114
77
-
IRQ11 P501 -
-
AGTOB0 GTIV
GTIOC 11B
USB_ OVRC
URA
TXD5/M OSI5/SD
A5
QSSL
-
-
-
SD1CM AN116
D_A
IVREF1 -
-
L4
115
78
-
IRQ12 P502 -
-
-
GTIW
GTIOC 12A
USB_ OVRC
URB
RXD5/MI SO5/SC
L5
QIO0
-
-
-
SD1DA AN017
T0_A
IVCMP0 -
-
K5
116
79
-
-
P503 -
-
-
GTETRGC GTIOC 12B
QIO1
-
-
-
SD1DA AN117
T1_A
-
-
-
P504 ALE -
-
USB_ CTS6_R SCK5
EXICE TS6/SS6
N
-
L5
117
80
-
-
-
GTETRGD GTIOC 13A
USB_I SCK6
D
QIO2
-
-
-
SD1DA AN018
T2_A
-
-
-
K6
118
-
-
IRQ14 P505 -
-
-
-
GTIOC 13B
-
RXD6/MI SO6/SC
L6
-
QIO3
-
-
-
SD1DA AN118
T3_A
-
-
-
L6
119
-
-
IRQ15 P506 -
-
-
-
-
-
-
TXD6/M OSI6/SD
A6
-
-
-
-
-
SD1CD AN019
-
-
-
N4
120
81
-
-
P508 -
-
-
-
-
-
-
SCK6
SCK5
-
-
-
-
-
SD1DA AN020
T3_A
-
-
-
N5
121
82
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M5
122
83
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M6
123
84
-
IRQ13 P015 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN006/ DA1/
AN106 IVCMP1
-
N6
124
85
-
-
P014 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN005/ DA0/
AN105 IVREF3
-
M7
125
86
VREFL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
CTS5_R TS5/SS5
-
-
Page 78 of 1734
S5D5 User’s Manual
1. Overview
HMI
PDC
CTSU
DAC12,
ACMPHS
ADC12
SDHI
ETHERC (RMII)
(50 MHz)
ETHERC (MII)
(25 MHz)
SSIE
SPI, QSPI
Analog
IIC
SCI1,3,5,7,9
(30 MHz)
SCI0,2,4,6,8
(30 MHz)
GPT
GPT
AGT
Communication interfaces
RTC
USBFS,
CAN
Timers
SDRAM
External bus
I/O port
Interrupt
LQFP144
LGA145
Extbus
LQFP100
Power, System,
Clock, Debug,
CAC
Pin number
N7
126
87
VREFH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L7
127
88
AVCC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L8
128
89
AVSS0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M8
129
90
VREFL0 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N8
130
91
VREFH0 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M9
131
-
-
IRQ13 P009 -DS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN004
-
-
-
N9
132
92
-
IRQ12 P008 -DS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN003
-
-
-
K7
133
93
-
-
P007 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN107
-
-
-
L9
134
94
-
IRQ11 P006 -DS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN102
IVCMP2 -
-
K8
135
95
-
IRQ10 P005 -DS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN101
IVCMP2 -
-
K9
136
96
-
IRQ9- P004 DS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN100
IVCMP2 -
-
K10
137
97
-
-
P003 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN007
-
-
-
M10 138
98
-
IRQ8- P002 DS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN002
IVCMP2 -
-
N10
99
-
IRQ7- P001 DS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN001
IVCMP2 -
-
139
L10
140
100
-
IRQ6- P000 DS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN000
IVCMP2 -
N11
141
-
VSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N12
142
-
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M11 143
-
-
IRQ14 P512 -
-
-
-
GTIOC 0A
CTX1 TXD4/M OSI4/SD
A4
SCL2 -
-
-
-
-
-
-
-
VSYNC
M12 144
-
-
IRQ15 P511 -
-
-
-
GTIOC 0B
CRX1 RXD4/MI SO4/SC
L4
SDA2 -
-
-
-
-
-
-
-
PCKO
Note:
Some pin names have the added suffix of _A, _B, and _C. When assigning the GPT, IIC, SPI, SSIE, ETHERC (RMII), and
SDHI functionality, select the functional pins with the same suffix.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 79 of 1734
S5D5 User’s Manual
2.
2. CPU
CPU
The MCU is based on the Arm® Cortex®-M4 core.
2.1
Overview
2.1.1
CPU
Arm Cortex-M4
Revision: r0p1-01rel0
ARMv7E-M architecture profile
Single Precision Floating Point Unit compliant with the ANSI/IEEE Std 754-2008.
Memory Protection Unit (MPU)
ARMv7 Protected Memory System Architecture
8 protected regions.
SysTick timer
Driven by SYSTICCLK (LOCO) or ICLK.
See reference 1. and reference 2. for details.
2.1.2
Debug
Arm CoreSight™ ETM-M4
Revision: r0p1-00rel0
Arm ETM architecture version 3.5.
CoreSight Instrumentation Trace Macrocell (ITM)
Data Watchpoint and Trace Unit (DWT)
4 comparators for watchpoints and triggers.
Flash Patch and Breakpoint Unit (FPB)
Flash Patch (remap) function is not available, only Breakpoint function is available
6 instruction comparators
2 literal comparators.
CoreSight Time Stamp Generator (TSG)
Time stamp for ETM and ITM
Driven by CPU clock.
Debug Register Module (DBGREG)
Reset control
Halt control.
CoreSight Debug Access Port (DAP)
JTAG Debug Port (JTAG-DP)
Serial Wire Debug Port (SW-DP).
Cortex-M4 Trace Port Interface Unit (TPIU)
4-bit TPIU formatter output
Serial Wire Output.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 80 of 1734
S5D5 User’s Manual
2. CPU
CoreSight Embedded Trace Buffer (ETB)
CoreSight Trace Memory Controller with ETB configuration
Buffer size: 2 KB.
See reference 1. and reference 2. for details.
2.1.3
Operating Frequency
The operating frequencies for the MCU are as follows:
CPU: maximum 120 MHz
4-bit TPIU trace interface: maximum 60 MHz
Serial Write Output (SWO) trace interface: maximum 60 MHz
Joint Test Action Group (JTAG) interface: maximum 25 MHz
SWD interface: maximum 25 MHz.
Figure 2.1 shows a block diagram of the Cortex-M4 CPU.
OCD access
Trace/debug data
From: OCD emulator (JTAG/SWD)
From: System bus
Cortex®-M4 integration
SWJ-DP
TS Gen
Cortex-M4
Cortex-M4 core
(DPU)
DAP IC
NVIC
APB-AP
DWT
ETM
DBGREG
To: System control
MPU
OCDREG
ITM
AHB-AP
FPB
Bus matrix
Funnel
ETB
M4-TPIU
AHB2APB
To: System bus
Figure 2.1
ROM table
To: Trace pin
(4-pin trace, SWO)
Cortex-M4 CPU block diagram
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 81 of 1734
S5D5 User’s Manual
2.2
2. CPU
MCU Implementation Options
Table 2.1 shows the implementation options of the MCU and is based on the configurable options in reference 2.
Table 2.1
Implementation options
Option
Implementation
MPU
Included, 8 protect regions
FPB
Flash Patch (remap) function is not available, only Breakpoint function is available
FPU
Included
Number of interrupts
96
Number of priority bits
4
Number of Wakeup Interrupt Controllers
(WIC*1)
Not included
Sleep mode power saving
Sleep mode and other low power modes are supported. For more details, see section
11, Low Power Modes.
Note:
SCB.SCR.SLEEPDEEP is ignored.
Endianness
Little-endian
SysTick SYST_CALIB register
SYST_CALIB = 4000 0147h
Bit [31] = 0
Reference clock provided
Bit [30] = 1
TERMS value is inexact
Bits [29:24] = 00h
Reserved
Bits [23:0] = 000147h TERM: (32768 × 10 ms) - 1 / 32.768 kHz
= 326.66 decimal
= 327 with skew
= 000147h
Event input/output
Not implemented
System reset request output
The SYSRESETREQ bit in the Application Interrupt and Reset Control Register causes
a CPU reset
Auxiliary fault inputs (AUXFAULT)
Not implemented
Note 1.
The ICU can wake up the CPU instead of the Wakeup Interrupt Controller (WIC). For details, see section 14, Interrupt
Controller Unit (ICU).
2.3
Trace Interface
A Trace Port Interface Unit (TPIU) and Serial Wire Output (SWO) provide trace output. Table 2.2 shows the MCU pins
for the function. These pins are multiplexed with other functions.
Table 2.2
Trace function pins
Name
I/O
Width
Function
TCLK
Output
1 bit
Trace clock
TDATA0
Output
1 bit
Trace data output 0
TDATA1
Output
1 bit
Trace data output 1
TDATA2
Output
1 bit
Trace data output 2
TDATA3
Output
1 bit
Trace data output 3
TDO/SWO
Output
1 bit
Serial wire output
Multiplexed with JTAG TDO pin
2.4
JTAG/SWD Interface
Table 2.3 shows the JTAG/SWD pins.
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Page 82 of 1734
S5D5 User’s Manual
Table 2.3
2. CPU
JTAG/SWD pins
Name
I/O
P/N
Width
Function
When not in use
TCK/SWCLK
Input
Pos.
1 bit
JTAG clock pin
Pull-up
TMS/SWDIO
I/O
Neg.
1 bit
JTAG TMS pin
SWD I/O pin
Pull-up
TDI
Input
Pos.
1 bit
JTAG TDI pin
Pull-up
TDO/SWO
Output
Neg.
1 bit
JTAG TDO pin
Multiplexed with serial wire output
Open
2.5
Debug Mode
2.5.1
Debug Mode Definition
In single chip mode, the debugger state of connection is defined as OCD mode, the debugger state of disconnection is
defined as User mode. Table 2.4 shows the two CPU debug modes and usage conditions.
Table 2.4
CPU debug mode and conditions
Conditions
Mode
OCD connect
JTAG/SWD authentication
Debug mode
Debug authentication
Not connected
—
User mode
Disabled
Connected
Failed
User mode
Disabled
Connected
Passed
OCD mode
Enabled
Note 1.
Note 2.
OCD connect is determined by the CDBGPWRUPREQ bit output in the SWJ-DP register. The bit can only be written by the
OCD. However, the level of the bit can be confirmed by reading the DBGSTR.CDBGPWRUPREQ bit.
Debug Authentication is defined by the ARMv7-M architecture. Enabled means that both invasive and non-invasive CPU
debugging are permitted. Disabled means that both are not permitted.
2.5.2
Debug Mode Effects
This section describes the effects of debug mode, which occur both internally and externally to the CPU.
2.5.2.1
Low power mode
All CoreSight debug components can store the register settings even when the CPU enters Software Standby, Snooze, or
Deep Software Standby mode. However, AHB-AP cannot respond to On-Chip Debug (OCD) access in these low power
modes. The OCD must wait for cancellation of the low power mode to access the CoreSight debug components. To
request low power mode cancellation, the OCD can set the DBIRQ bit in the MCUCTRL register. For details, see section
2.6.5.3, MCU Control Register (MCUCTRL).
2.5.2.2
Reset
In OCD mode, some resets depend on the CPU status and the DBGSTOPCR setting.
Table 2.5
Reset or interrupt and mode setting (1 of 2)
Control in On-Chip Debug (OCD) mode
Reset or interrupt name
OCD break mode
RES pin reset
Same as user mode
Power-on reset
Same as user mode
Independent watchdog timer reset/interrupt
Does not occur*1
Depends on DBGSTOPCR setting*2
Watchdog timer reset/interrupt
Does not occur*1
Depends on DBGSTOPCR setting*2
Voltage monitor 0 reset
Depends on DBGSTOPCR setting*3
Voltage monitor 1 reset/interrupt
Depends on DBGSTOPCR setting*3
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Table 2.5
2. CPU
Reset or interrupt and mode setting (2 of 2)
Control in On-Chip Debug (OCD) mode
Reset or interrupt name
OCD break mode
Voltage monitor 2 reset/interrupt
Depends on DBGSTOPCR setting*3
SRAM parity error reset/interrupt
Depends on DBGSTOPCR setting*3
SRAM ECC error reset/interrupt
Depends on DBGSTOPCR setting*3
MPU bus master reset/interrupt
Same as user mode
MPU bus slave reset/interrupt
Same as user mode
Stack pointer error reset/interrupt
Same as user mode
Deep software standby reset
Same as user mode
Software reset
Same as user mode
Note:
Note 1.
Note 2.
Note 3.
2.6
OCD run mode
In OCD break mode, the CPU is halted. In OCD run mode, the CPU is in OCD mode and the CPU is not halted.
The IWDT and WDT always stop in this mode.
The IWDT and WDT operation depends on the DBGSTOPCR setting.
Reset or interrupt masking depends on the DBGSTOPCR setting.
Programmers Model
2.6.1
Address Spaces
The MCU debug system includes two CoreSight Access Ports (AP):
AHB-AP, which is connected to the CPU bus matrix and has the same access to the system address space as the
CPU
APB-AP, which has a dedicated address space (OCD address space) and is connected to the OCD register.
Figure 2.2 shows a block diagram of the AP connection and address spaces.
JTAG/SWD
Port 0
SWJ-DP
AHB-AP
System address space
(through CPU bus matrix)
DBGREG
DAP
IC
Port 1
OCD address space
APB-AP
OCDREG
Figure 2.2
JTAG/SWD authentication block diagram
For debugging purposes, there are two register modules, DBGREG and OCDREG. DBGREG is located in the system
address space and can be accessed from the OCD emulator, the CPU, and other bus masters in the MCU. OCDREG is
located in the OCD address space and can only be accessed from the OCD tool. The CPU and other bus masters cannot
access the OCD registers.
2.6.2
Cortex-M4 Peripheral Address Map
In the system address space, the Cortex-M4 core has a Private Peripheral Bus (PPB) that can only be accessed from the
CPU and OCD emulator. The PPB is expanded from the Cortex-M4 original implementation for the MCU. Table 2.6
shows the address map of the MCU.
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Table 2.6
2. CPU
Cortex-M4 peripheral address map
Component name
Start address
End address
Note
ITM
E000 0000h
E000 0FFFh
See reference 2.
DWT
E000 1000h
E000 1FFFh
See reference 2.
FPB
E000 2000h
E000 2FFFh
See reference 2.
SCS
E000 E000h
E000 EFFFh
See reference 2.
TPIU
E004 0000h
E004 0FFFh
See reference 2.
ETM
E004 1000h
E004 1FFFh
See reference 5.
ATB funnel
E004 2000h
E004 2FFFh
See section 2.7
and reference 4.
ETB
E004 3000h
E004 3FFFh
See reference 6.
Time Stamp Generator
E004 4000h
E004 4FFFh
See section 2.10
and reference 4.
ROM Table
E00F F000h
E00F FFFFh
See section 2.6.3
and reference 7.
2.6.3
CoreSight ROM Table
The MCU contains one CoreSight ROM Table, which lists the Arm components.
2.6.3.1
ROM entries
Table 2.7 shows the ROM entries in the CoreSight ROM Table. The OCD emulator can use the ROM entries to
determine which components are implemented in a system. See reference 7. for details.
Table 2.7
CoreSight ROM Table
#
Address
Access size
R/W
Value
Component
0
E00F F000h
32 bits
R
FFF0F003
NVIC
1
E00F F004h
32 bits
R
FFF02003
SWT
2
E00F F008h
32 bits
R
FFF03003
FPB
3
E00F F00Ch
32 bits
R
FFF01003
ITM
4
E00F F010h
32 bits
R
FFF41003
TPIU
5
E00F F014h
32 bits
R
FFF42003
ETM
6
E00F F018h
32 bits
R
FFF43003
Funnel
7
E00F F01Ch
32 bits
R
FFF44003
ETB
8
E00F F020h
32 bits
R
FFF45003
TSG
9
E00F F024h
32 bits
R
00000000
(End of entries)
2.6.3.2
CoreSight component registers
The CoreSight ROM Table lists the CoreSight component registers defined in the Arm CoreSight architecture.
Table 2.8 shows the registers. See reference 7. for details of each register.
Table 2.8
CoreSight component registers in the CoreSight ROM Table (1 of 2)
Name
Address
Access size
R/W
Initial value
DEVTYPE
E00F FFCCh
32 bits
R
00000001h
PID4
E00F FFD0h
32 bits
R
00000004h
PID5
E00F FFD4h
32 bits
R
00000000h
PID6
E00F FFD8h
32 bits
R
00000000h
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Table 2.8
2. CPU
CoreSight component registers in the CoreSight ROM Table (2 of 2)
Name
Address
Access size
R/W
Initial value
PID7
E00F FFDCh
32 bits
R
00000000h
PID0
E00F FFE0h
32 bits
R
00000015h
PID1
E00F FFE4h
32 bits
R
00000030h
PID2
E00F FFE8h
32 bits
R
0000000Ah
PID3
E00F FFECh
32 bits
R
00000000h
CID0
E00F FFF0h
32 bits
R
0000000Dh
CID1
E00F FFF4h
32 bits
R
00000010h
CID2
E00F FFF8h
32 bits
R
00000005h
CID3
E00F FFFCh
32 bits
R
000000B1h
2.6.4
DBGREG Module
The DBGREG register module controls the debug functionalities and is implemented as a CoreSight-compliant
component.
Table 2.9 shows the DBGREG registers other than the CoreSight component registers.
Table 2.9
Non-CoreSight DBGREG registers
Name
DAP port
Address
Access size
R/W
Debug Status Register
DBGSTR
Port 0
4001 B000h
32 bits
R
Debug Stop Control Register
DBGSTOPCR
Port 0
4001 B010h
32 bits
R/W
Trace Control Register
TRACECTR
Port 0
4001 B020h
32 bits
R/W
2.6.4.1
Debug Status Register (DBGSTR)
Address(es): DBG.DBGSTR 4001 B000h
b31
b30
—
—
0
0
0
b15
b14
—
0
Value after reset:
Value after reset:
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CDBGP CDBGP
WRUP WRUP
ACK
REQ
Bit
Symbol
Bit name
Description
R/W
b27 to b0
—
Reserved
These bits are read as 0
R
b28
CDBGPWRUPREQ
Debug power-up request
0: OCD is not requesting debug power-up
1: OCD is requesting debug power-up.
R
b29
CDBGPWRUPACK
Debug power-up
acknowledge
0: Debug power-up request is not acknowledged
1: Debug power-up request is acknowledged.
R
b31, b30
—
Reserved
These bits are read as 0
R
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2.6.4.2
2. CPU
Debug Stop Control Register (DBGSTOPCR)
Address(es): DBG.DBGSTOPCR 4001 B010h
b31
b30
b29
b28
b27
b26
—
—
—
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
Value after reset:
b25
b24
b23
b22
b21
b20
b19
—
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
DBGST DBGST
OP_RE OP_RP
CCR
ER
b18
b16
DBGSTOP_LVD[2:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
b17
0
0
b1
b0
DBGST DBGST
OP_W OP_IW
DT
DT
1
1
Bit
Symbol
Bit name
Description
R/W
b0
DBGSTOP_IWDT
Mask bit for IWDT reset or
interrupt
0: Enable IWDT reset or interrupt
1: Mask IWDT reset or interrupt and stop WDT count
when CPU is in OCD break mode.
R/W
b1
DBGSTOP_WDT
Mask bit for WDT reset or
interrupt
0: Enable WDT reset or interrupt
1: Mask WDT reset or interrupt and stop WDT count
when CPU is in OCD break mode.
R/W
b15 to b2
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b16
DBGSTOP_LVD[2:0]
Mask bit for LVD0 reset
0: Enable LVD0 reset
1: Mask LVD0 reset.
R/W
b17
Mask bit for LVD1 reset or
interrupt
0: Enable LVD1 reset or interrupt
1: Mask LVD1 reset or interrupt.
R/W
b18
Mask bit for LVD2 reset or
interrupt
0: Enable LVD2 reset or interrupt
1: Mask LVD2 reset or interrupt.
R/W
b23 to b19
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b24
DBGSTOP_RPER
Mask bit for SRAM parity error
reset or interrupt
0: Enable SRAM parity error reset or interrupt
1: Mask SRAM parity error reset or interrupt.
R/W
b25
DBGSTOP_RECCR
Mask bit for SRAM ECC error
reset or interrupt
0: Enable SRAM ECC error reset or interrupt
1: Mask SRAM ECC error reset or interrupt.
R/W
b31 to b26
—
Reserved
These bits are read as 0. The write value should be 0. R/W
The Debug Stop Control Register (DBGSTOPCR) specifies the functional stop in OCD mode. All bits in the register are
regarded as 0 when the MCU is not in OCD mode.
2.6.4.3
Trace Control Register (TRACECTR)
Address(es): DBG.TRACECTR 4001 B020h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
ENETB
FULL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b30 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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Bit
Symbol
Bit name
Description
R/W
b31
ENETBFULL
Enable bit for halt request on
ETB full
0: ETB full does not cause a CPU halt
1: ETB full causes a CPU halt.
R/W
2.6.4.4
DBGREG CoreSight component registers
The DBGREG module provides the CoreSight component registers defined in the Arm CoreSight architecture.
Table 2.10 shows these registers. See reference 7. for details of each register.
Table 2.10
DBGREG CoreSight component registers
Name
Address
Access size
R/W
Initial value
PID4
4001 BFD0h
32 bits
R
00000004h
PID5
4001 BFD4h
32 bits
R
00000000h
PID6
4001 BFD8h
32 bits
R
00000000h
PID7
4001 BFDCh
32 bits
R
00000000h
PID0
4001 BFE0h
32 bits
R
00000005h
PID1
4001 BFE4h
32 bits
R
00000030h
PID2
4001 BFE8h
32 bits
R
0000001Ah
PID3
4001 BFECh
32 bits
R
00000000h
CID0
4001 BFF0h
32 bits
R
0000000Dh
CID1
4001 BFF4h
32 bits
R
000000F0h
CID2
4001 BFF8h
32 bits
R
00000005h
CID3
4001 BFFCh
32 bits
R
000000B1h
2.6.5
OCDREG Module
The OCDREG register module controls the On-Chip Debug (OCD) emulator functionalities and is implemented as a
CoreSight-compliant component.
Table 2.11 shows the OCDREG registers other than the CoreSight component registers.
Table 2.11
Non-CoreSight OCDREG registers
Name
DAP port
Address
Access size
R/W
ID Authentication Code Register 0
IAUTH0
Port 1
8000_0000
32 bits
W
ID Authentication Code Register 1
IAUTH1
Port 1
8000_0100
32 bits
W
ID Authentication Code Register 2
IAUTH2
Port 1
8000_0200
32 bits
W
ID Authentication Code Register 3
IAUTH3
Port 1
8000_0300
32 bits
W
MCU Status Register
MCUSTAT
Port 1
8000 0400h
32 bits
R
MCU Control Register
MCUCTRL
Port 1
8000 0410h
32 bits
R/W
Note:
OCDREG is located in the dedicated OCD address space. This address map is independent from the system address map.
See section 2.6.2, Cortex-M4 Peripheral Address Map.
2.6.5.1
ID Authentication Code Register (IAUTH0 to 3)
Four authentication registers are provided for writing the 128-bit key. These registers must be written in sequential order
from IAUTH0 to IAUTH3. If the set of register writes is not compliant with this order, the result is unpredictable.
Only 32-bit writes are permitted. The initial value of the registers is all 1s. This means that JTAG/SWD access is initially
permitted when the ID code in the OSIS register has the initial value. See section 2.11.2, Unlock ID Code.
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2. CPU
Address(es): IAUTH0 8000 0000h
b31
b0
IAUTH0: AID 31-0 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH1 8000 0100h
b31
b0
IAUTH1: AID 63-32 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH2 8000 0200h
b31
b0
IAUTH2: AID 95-64 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH3 8000 0300h
b31
b0
IAUTH3: AID 127-96 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.6.5.2
MCU Status Register (MCUSTAT)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): MCUSTAT 8000 0400h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
CPUST CPUSL AUTH
OPCLK EEP
1/0*1
1/0*1
0
Bit
Symbol
Bit name
Description
R/W
b0
AUTH
Authentication status
0: Authentication failed
1: Authentication succeeded.
R
b1
CPUSLEEP
0: CPU is not in Sleep mode
1: CPU is in Sleep mode.
R
b2
CPUSTOPCLK
0: CPU clock is not stopped. This indicates that the MCU is in
Normal or Sleep mode
1: CPU clock is stopped. This indicates that the MCU is in
Snooze or Software Standby mode.
R
b31 to b3
—
These bits are read as 0.
R
Note 1.
Reserved
Depends on the MCU status.
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2.6.5.3
2. CPU
MCU Control Register (MCUCTRL)
Address(es): MCUCTRL 8000 0410h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DBIRQ
—
—
—
—
—
—
—
EDBGR
Q
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
EDBGRQ
External Debug
Request
Writing 1 to the bit causes a CPU halt or debug monitor
exception:
0: Debug event not requested
1: Debug event requested.
When the EDBGRQ bit is set to 0 or the CPU is halted, the
EDBCRQ bit is cleared.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
DBIRQ
Debug Interrupt
Request
Writing 1 to the bit wakes up the MCU from low power mode:
0: Debug interrupt not requested
1: Debug interrupt requested.
The condition can be cleared by writing 0 to the DBIRQ bit.
R/W
b31 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Set DBIRQ and EDBGRQ to the same value.
2.6.5.4
OCDREG CoreSight component registers
The OCDREG module provides the CoreSight component registers defined in the Arm CoreSight architecture.
Table 2.12 shows these registers. See reference 7. for details of each register.
Table 2.12
OCDREG CoreSight component registers
Name
Address
Access size
R/W
Initial value
PID4
8000 0FD0h
32 bits
Read-only
00000004h
PID5
8000 0FD4h
32 bits
Read-only
00000000h
PID6
8000 0FD8h
32 bits
Read-only
00000000h
PID7
8000 0FDCh
32 bits
Read-only
00000000h
PID0
8000 0FE0h
32 bits
Read-only
00000004h
PID1
8000 0FE4h
32 bits
Read-only
00000030h
PID2
8000 0FE8h
32 bits
Read-only
0000000Ah
PID3
8000 0FECh
32 bits
Read-only
00000000h
CID0
8000 0FF0h
32 bits
Read-only
0000000Dh
CID1
8000 0FF4h
32 bits
Read-only
000000F0h
CID2
8000 0FF8h
32 bits
Read-only
00000005h
CID3
8000 0FFCh
32 bits
Read-only
000000B1h
2.7
CoreSight ATB Funnel
There is one CoreSight ATB funnel in the MCU. The funnel has two ATB slaves and one ATB master, and it selects the
debug trace source from ETM and ITM to ETB. Figure 2.3 shows the CoreSight ATB connection in the MCU.
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2. CPU
ITM
ETM
ATB
replicator
ATB
replicator
ATB
funnel
ETB
Figure 2.3
TPIU
CoreSight ATB connection
Table 2.13 shows the ATB slave connection for the funnel.
Table 2.13
ATB slave connection
ATB slave number
Connected trace source
#0
ITM
#1
ETM
For details of the ATB and funnel, see reference 4.
2.8
Flash Patch and Break Unit
The MCU has a flash patch and break unit. Breakpoint function is available, but flash patch (remap) function is not
available. Therefore, do not set the REPLACE bits [31:30] in the FP_COMPn register to 0. Bit [28] of FP_REMAP
register is always set to 1. When writing to this register, write 1 to bit [28]. When reading this register, bit [28] is always
read as 1. See reference 1.*1 for details.
Note 1.
2.9
In the reference, SYSTICCLK (LOCO) is the IMPLEMENTATION DEFINED external reference clock and ICLK is the processor
clock.
SysTick System Timer
The SysTick system timer provides a simple 24-bit down counter. The reference clock for the timer can be selected as the
CPU clock (ICLK) or SysTick Timer clock (SYSTICCLK). See reference 1. for details.
2.10
CoreSight Time Stamp Generator
A CoreSight Time Stamp Generator provides a CPU clock-based timestamp to ITM and ETM. The 48 LSB bits of the
64-bit counter are used for the two components. See reference 4. for details.
2.11
OCD Emulator Connection
A JTAG/SWD authentication mechanism checks access permission for debug and MCU resources. To obtain full debug
functionality, a pass result of the authentication mechanism is required.
Figure 2.4 shows a block diagram of the authentication mechanism.
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2. CPU
Emulator host
PC
MCU
OCD emulator
SWJ-DP
AHB-AP
To: CPU debug
To: CPU bus
JTAG/SWD
APB-AP
OCDREG
ID
comparator
Option-setting memory
IAUTH output
Unlock ID
Figure 2.4
Compare result
(debug enable)
Authentication mechanism block diagram
An ID comparator is available in the MCU for authentication. The comparator compares the 128-bit IAUTH output from
OCDREG and the 128-bit unlock ID code from the option-setting memory. When the two outputs are identical, the CPU
debug functions and system bus access from the OCD emulator are permitted.
2.11.1
DBGEN
After the OCD emulator gets access permission, the OCD emulator must set the DBGEN bit in the System Control OCD
Control Register (SYOCDCR). In addition, the OCD emulator must clear the DBGEN bit before disconnecting it. See
section 11, Low Power Modes for details.
2.11.2
Unlock ID Code
The unlock ID code is used for checking permissions for debug and access to on-chip resources. If the unlock ID code
matches the 128-bit data written in ID Authentication Registers 0 to 3, the JTAG/SWD debugger obtains access
permission. Unlock ID code is written in the OCD/Serial Programmer ID Setting Register (OSIS) in the option-setting
memory. The initial value of the unlock ID code is all 1s (FFFFFFFF_FFFFFFFF_FFFFFFFFh). See section 7, OptionSetting Memory for details.
2.11.3
Restrictions on Connecting an OCD Emulator
This section describes the restrictions on emulator access.
2.11.3.1
Starting connection while in low power mode
When starting a JTAG/SWD connection from an OCD emulator, the MCU must be in Normal or Sleep mode. If the
MCU is in Software Standby, Snooze, or Deep Software Standby mode, the OCD emulator can cause the MCU to hang.
2.11.3.2
Changing low power mode while in OCD mode
When the MCU is in OCD mode, the low power mode can be changed. However, system bus access from AHB-AP is
prohibited in Software Standby, Snooze, or Deep Software Standby mode. Only SWJ-DP, APB-AP, and OCDREG can
be accessed from the OCD emulator in these modes. Table 2.14 shows the restrictions.
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Table 2.14
2. CPU
Restrictions by mode
Start OCD emulator
connection
Active mode
Change low power
mode
Access AHB-AP and
system bus
Access APB-AP and
OCDREG
Normal
Yes
Yes
Yes
Yes
Sleep
Yes
Yes
Yes
Yes
Software Standby
No
Yes
No
Yes
Snooze
No
Yes
No
Yes
Deep Software Standby
No
Yes
No
Yes
If system bus access is required in Software Standby, Snooze, or Deep Software Standby mode, set the
OCUCTRL.DBIRG bit in OCDREG to wake up the MCU from the low power modes. Simultaneously, using the
OCUCTRL.EDBGRQ bit in OCDREG, the OCD emulator can wake up the MCU without starting CPU execution by
using a CPU break.
2.11.3.3
Modifying the unlock ID code in OSIS
After modifying the unlock ID code in the OSIS, the OCD emulator must reset the MCU by asserting the RES pin or
setting the SYSRESETREQ bit of the Application Interrupt and Reset Control Register in the system control block to 1.
The modified unlock ID code is reflected after reset.
2.11.3.4
Connecting sequence and JTAG/SWD authentication
Because the OCD emulator is protected by the JTAG/SWD authentication mechanism, the OCD might be required to
input the ID code to the authentication registers. The OSIS value in the option-setting memory determines whether the
code is required.
After the negation of the reset, a 5 μs wait time is required before comparing the OSIS value at cold start.
(1)
When MSB of OSIS is 0 (bit [127] = 0)
The ID code is always mismatching and connection to the OCD is prohibited.
(2)
When OSIS is all 1s (default)
OCD authentication is not required and the OCD can use the AHB-AP without the authentication.
1. Connect the OCD emulator to the MCU through the JTAG or SWD interface.
2. Set up SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in the SWJDP Control Status Register, then wait until CSDBGPWRUPACK in the same register is asserted.
3. Set up the AHB-AP to access the system address space. The AHB-AP is connected to the DAP bus port 0.
4. Start accessing the CPU debug resources using the AHB-AP.
(3)
When OSIS[127:126] = 2’b10
OCD authentication is required and the OCD must write the unlock ID code to the IAUTH registers 0 to 3 in the
OCDREG before using the AHB-AP.
1. Connect the OCD debugger to the MCU through the JTAG or SWD interface.
2. Set up SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in the SWJDP Control Status Register, and wait until CSDBGPWRUPACK in the same register is asserted.
3. Set up the APB-AP to access OCDREG. The APB-AP is connected to the DAP bus port 1.
4. Write the 128-bit ID code to IAUTH registers 0 to 3 in the OCDREG register using the APB-AP.
5. If the 128-bit ID code matches the OSIS value, the AHB-AP is authorized to issue an AHB transaction. The
authorization result can be confirmed in the AUTH bit in the MCUSTAT Register or the DbgStatus bit in the AHBAP Control Status Word Register.
When the DbgStatus bit is 1, the 128-bit ID code is a match with the OSIS value. AHB transfers are permitted.
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2. CPU
When the DbgStatus bit is 0, the 128-bit ID code is not a match with the OSIS value. AHB transfers are not
permitted.
6. Set up the AHB-AP to access the system address space. The AHB-AP is connected to the DAP bus port 0.
7. Start accessing the CPU debug resources using the AHB-AP.
(4)
When OSIS[127:126] is 2’b11
OCD authentication is required and the OCD must write the unlock ID code to IAUTH registers 0 to 3 in the OCDREG
register. The connection sequence is the same when OSIS[127:126] is 2’b10 except for ALeRASE capability.
When IATUH0-3 are ALeRASE in ASCII code, the contents of the code flash, data flash, and configuration area are
erased at once. See section 53, Flash Memory for details.
ALeRASE sequence:
1. Connect the OCD debugger to the MCU through the JTAG or SWD interface.
2. Set up SWJ-DP to access DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in the SWJDP
Control Status Register, and then wait until CSDBGPWRUPACK in the same register is asserted.
3. Set the APB-AP to access OCDREG. This APB-AP is connected to the DAP bus port 1.
4. Write the 128-bit ID code to IAUTH registers 0 to 3 in the OCDREG register using the APB-AP.
5. If the 128-bit ID code is ALeRASE in ASCII code (414C_6552_4153_45FF_FFFF_FFFF_FFFF_FFFFh), the
contents of the code flash, data flash, and configuration area are erased. After that, the MCU transitions to Sleep
mode.
2.12
References
1. ARM®v7-M Architecture Reference Manual (ARM DDI 0403D).
2. ARM® Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D).
3. ARM® Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).
4. ARM® CoreSight™ SoC-400 Technical Reference Manual (ARM DDI 0480F).
5. ARM® CoreSight™ ETM-M4 Technical Reference Manual (ARM DDI 0440C).
6. ARM® CoreSight™ Trace Memory Controller Technical Reference Manual (ARM DDI 0461B).
7. ARM® CoreSight™ Architecture Specification (ARM IHI 0029D).
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3. Operating Modes
3.
Operating Modes
3.1
Overview
Table 3.1 shows the selection of operating modes by the mode-setting pin. For details, see section 3.2, Details of
Operating Modes. Operation starts with the on-chip flash memory enabled, regardless of the mode in which operation
started.
Table 3.1
Selection of operating modes by the mode-setting pin
Mode-setting pin
MD
Operating mode
On-chip flash memory
External bus
1
Single-chip mode
Enable
Disable
0
SCI/USB boot mode
Enable
Disable
3.2
Details of Operating Modes
3.2.1
Single-Chip Mode
In single-chip mode, all I/O pins are available for use as input or output port, inputs or outputs for peripheral functions, or
as interrupt inputs. When a reset is released while the MD pin is high, the MCU starts in single-chip mode and the onchip flash is enabled.
3.2.2
SCI Boot Mode
In this mode, the on-chip flash memory programming routine (SCI boot program), stored in a dedicated area within the
MCU, is used. The on-chip flash, including the code flash memory and data flash memory, can be modified from outside
the MCU by using a universal asynchronous receiver/transmitter (UART) SCI. For details, see section 53, Flash
Memory. The MCU starts in SCI boot mode if the MD pin is held low on release from the reset state.
3.2.3
USB Boot Mode
In this mode, the on-chip flash memory programming routine (USB boot program), stored in the boot area within the
MCU, is used. The on-chip flash, including the code flash memory and data flash memory, can be modified from outside
the MCU by using the USB. For details, see section 53, Flash Memory. The MCU starts in USB boot mode if the MD pin
is held low on release from the reset state.
3.3
Operating Mode Transitions
3.3.1
Operating Mode Transitions as Determined by the Mode-Setting Pin
Figure 3.1 shows operating mode transitions determined by the settings of the MD pin.
Reset
MD = 1 and release RES pin
Release POR
RES pin or POR occurs
RES pin or POR occurs
MD = 0 and release RES pin
Single-chip mode
Figure 3.1
SCI boot mode
USB boot mode
Mode-setting pin level and operating mode
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4. Address Space
4.
Address Space
4.1
Overview
The MCU supports a 4-GB linear address space ranging from 0000 0000h to FFFF FFFFh that can contain both program
and data. Figure 4.1 shows the memory map.
FFFF FFFFh
System for Cortex®-M4
E000 0000h
Reserved area*2
9800 0000h
External address space
(SDRAM area)
9000 0000h
Reserved area*2
8720 0000h
External address space
(CS area)
8000 0000h
Reserved area*2
6800 0000h
6000 0000h
4080 0000h
407F C000h
407F B1A0h
407F B17Ch
407F 0000h
407E 0000h
External address space
(SPI area)
Reserved area*2
Flash I/O registers
Reserved area*2
On-chip flash (option-setting memory)*4
Reserved area*2
Flash I/O registers
Reserved area*2
4010 8000h
On-chip flash (data flash)
4010 0000h
Peripheral I/O registers
4000 0000h
Reserved area*2
2010 0000h
200F E000h
Standby SRAM
Reserved area*2
SRAM0
2004 0000h
2000 0000h
1FFE 0000h
0280 0000h
0200 0000h
0100 A168h
0100 A150h
SRAMHS
Reserved area*2
Memory mapping area
Reserved area*2
On-chip flash (option-setting memory)
Reserved area*2
0100 8000h
On-chip flash
(option-setting memory)
0100 7000h
Reserved area*2
0010 0000h
On-chip flash (program flash)
(read only)*1, *3
0000 0000h
Note 1.
The capacity of the flash differs depending on the product.
Code flash
memory
capacity
Note 2.
Note 3.
Note 4.
Figure 4.1
Address
Data flash
memory
capacity
Address
RAM
capacity
Address
1 Mbytes
0000 0000h - 000F FFFFh
32 Kbytes
4010 0000h - 4010 7FFFh
384 Kbyte
1FFE 0000h - 2003 FFFFh
512 Kbytes
0000 0000h - 0007 FFFFh
Do not access reserved areas.
Some regions are reserved for the option-setting memory. For details, see section 7, Option-Setting Memory.
Do not access from 407F B180h to 407F B19Bh.
Memory map
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4.2
4. Address Space
External Address Space
The external address space is divided into CS areas (CS0 to CS7), SDRAM area (SDCS), and SPI area. The eight CS
areas (CS0 to CS7) each correspond to the CSn signal output from a CSn (n = 0 to 7) pin. The SPI area is divided into
two areas, QSPI I/O registers and external SPI device space.
Figure 4.2 shows the address ranges associated with the individual CS areas (CS0 to CS7), SDRAM area (SDCS), and
SPI area.
871F FFFFh
FFFF FFFFh
CS7 (2 MB)
System for Cortex-M4
8700 0000h
E000 0000h
Reserved area*1
Reserved area*1
9800 0000h
External address space
(SDRAM area)
9000 0000h
861F FFFFh
CS6 (2 MB)
8600 0000h
Reserved area*1
8720 0000h
External address space
(CS area)
8000 0000h
Reserved area*1
6800 0000h
6000 0000h
4080 0000h
407F C000h
407F B1A0h
407F B17Ch
407F 0000h
407E 0000h
Reserved area*1
851F FFFFh
CS5 (2 MB)
8500 0000h
Reserved area*1
External address space
(SPI area)
Reserved area*1
Flash I/O registers
Reserved area*1
841F FFFFh
CS4 (2 MB)
8400 0000h
Reserved area*1
On-chip flash (option-setting memory)*2
Reserved area*1
Flash I/O registers
831F FFFFh
CS3 (2 MB)
8300 0000h
Reserved area*1
4010 8000h
On-chip flash (data flash)
4010 0000h
Peripheral I/O registers
Reserved area*1
821F FFFFh
CS2 (2 MB)
8200 0000h
Reserved area*1
4000 0000h
2010 0000h
200F E000h
2004 0000h
2000 0000h
1FFE 0000h
0280 0000h
0200 0000h
0100 A168h
0100 A150h
0100 8000h
0100 7000h
0010 0000h
Reserved area*1
811F FFFFh
Standby-SRAM
Reserved area*1
8100 0000h
CS1 (2 MB)
Reserved area*1
SRAM0
SRAMHS
Reserved area*1
Memory mapping area
Reserved area*1
801F FFFFh
CS0 (2 MB)
8000 0000h
On-chip flash (option-setting memory)
Reserved area*1
On-chip flash
(option-setting memory)
Reserved area*1
67FF FFFFh
QSPI I/O registers
6400 0000h
63FF FFFFh
External SPI device
On-chip flash (program flash)
(read only)
0000 0000h
Note 1.
Note 2.
Figure 4.2
6000 0000h
Do not access reserved areas.
Do not access from 407F B180h to 407F B19Bh.
Association between external address spaces and CS areas
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5. Memory Mirror Function (MMF)
5.
Memory Mirror Function (MMF)
5.1
Overview
The MCU provides a Memory Mirror Function (MMF). You can configure the MMF to map an application image load
address in the code flash memory to the application image link address in the unused 23-bit memory mirror space
addresses. Your application code must be developed and linked to run from this MMF destination address. The
application code is not required to know the load location where it is stored in the code flash memory.
Table 5.1 lists the MMF specifications.
Table 5.1
MMF specifications
Parameter
Description
Memory mirror space
8 MB (0200 0000h to 027F FFFFh)
Memory mirror boundary
128 bytes
5.2
Register Descriptions
5.2.1
MemMirror Special Function Register (MMSFR)
Address(es): MMF.MMSFR 4000 1000h
b31
b30
b29
b28
b27
b26
b25
b24
KEY[7:0]
b23
b22
b21
—
b20
b19
b18
b17
b16
MEMMIRADDR[15:9]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
0
0
0
0
0
0
0
Value after reset:
MEMMIRADDR[8:0]
0
Value after reset:
0
0
0
0
0
0
0
0
Bits
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b22 to b7
MEMMIRADDR[15:0]
Memory Mirror Address
0000h to FFFFh (8 MB)
R/W
b23
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b31 to b24
KEY[7:0]
MMSFR Key Code
These bits enable or disable rewriting of the
MEMMIRADDR bits
R/W
MEMMIRADDR[15:0] bits (Memory Mirror Address)
The MEMMIRADDR bits specify bits [22:7] of the memory mirror address. They define where the start address of the
memory mirror space addresses (0200 0000h) is linked to. Writing to these bits is enabled only when this register is
accessed in 32-bit words and the value DBh is written to the KEY[7:0] bits.
KEY[7:0] bits (MMSFR Key Code)
The KEY[7:0] bits enable or disable rewriting of the MEMMIRADDR bits. Data written to the KEY bits is not saved.
These bits are read as 0. The KEY code and MEMMIRADDR must be written to in the same cycle.
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5.2.2
5. Memory Mirror Function (MMF)
MemMirror Enable Register (MMEN)
Address(es): MMF.MMEN 4000 1004h
b31
b30
b29
b28
b27
b26
b25
b24
KEY[7:0]
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bits
Symbol
Bit name
Description
R/W
b0
EN
Memory Mirror Function
Enable
0: Disable MMF
1: Enable MMF.
R/W
b23 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24
KEY[7:0]
MMEN Key Code
These bits enable or disable rewriting of the EN bit.
R/W
EN bit (Memory Mirror Function Enable)
Writing to the EN bit is enabled only when the MemMirror Enable Register is accessed in 32-bit words and the value
DBh is written to the KEY[7:0] bits.
KEY[7:0] bits (MMEN Key Code)
The KEY[7:0] bits enable or disable rewriting of the EN bit. Data written to the KEY[7:0] bits is not saved. These bits
are read as 0. The KEY code and the EN bit must be written to in the same cycle.
5.3
5.3.1
Operation
MMF Operation
The MMF links the memory mirror space (0200 0000h to 027F FFFFh) to the code flash area. If MMEN.EN = 1, the
CPU can access code flash using both normal addresses (starting at 0000 0000h) and memory mirror space addresses
(starting at 0200 0000h). Figure 5.1 shows an overview of the MMF. The MMSFR.MEMMIRADDR bits specify where
the start address of the memory mirror space addresses (0200 0000h) is linked to. Figure 5.2, Figure 5.3, and Figure 5.4
show the MMF operation. Figure 5.5 shows the setting procedure of the MMF.
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5. Memory Mirror Function (MMF)
b31
Address bus
b24 b23
b16
b15
b8
b7
0
0
0
0
0
0
1
0
0
MemMirror SFR —
—
—
—
—
—
—
—
—
MEMMIRADDR[15:0]
0
0
0
0
0
0
0
0
0
Address bus [22:0] + MEMMIRADDR[22:0]
Code flash address
0
0
0
0
0
0
0
0
0
MEMMIRADDR - 1
0042 237Fh
027F FFFFh
Address bus + MemMir SFR
Memory mirror space
addresses
027F FFFFh - MEMMIRADDR + 1
027F FFFFh - MEMMIRADDR
8 MB code flash MAT
addresses
Example: MemMirrorSFR = 0042 2380h
Read from 0200 1000h = Code flash 0042 3380h
Read from 023E 8123h = Code flash 0000 A4A3h
0000 0000h
007F FFFFh
MEMMIRADDR
0042 2380h
0200 0000h
Figure 5.1
b0
Memory mirror space [0200 0000h to 027F FFFFh]
MMF operation
MemMirror SFR
CPU
Hex
0 0 4 2 2 3 8 0
32 bits
128-byte boundary
Memory mirror space (fixed value)
- : don’t care
bin
0000 0010 0 - - -
Fixed value is acceptable
- - - - - - - - - - - - - - - - - - - -
Fixed mirror area
In this case, 0200 0000h to 027F FFFFh
Address bus
9 bits
Comp
Adder*1
32 bits
9 bits
32 bits
Selector
32 bits
Code
flash
Note 1. For details, see Figure 5.4.
Figure 5.2
MMF block diagram
Figure 5.3 shows the addresses handled by each module. The Arm® MPU uses the original address of the CPU. The
security MPU and code flash memory each uses an address after conversion through the Memory Mirror Function.
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5. Memory Mirror Function (MMF)
CPU
Original address of CPU
ARM MPU
Memory Mirror Function
Code flash memory
Figure 5.3
Conversion address by
Memory Mirror Function
MMF address handling
Start
MMEN.EN = 1
Yes
Address bus [31:23] =
000000100b
Yes
No
Compare the address bus and the memory
mirror space (0200 0000h to 027F FFFFh)
No
Add the MEMMIRADDR to the address
bus
Code flash address [6:0] = Address bus [6:0]
Code flash address [22:7] = Address bus [22:7] +
MMSFR.MEMMIRADDR[15:0]
Code flash address [31:23] = 000000000b
Code flash address [31:0] = Address bus [31:0]
End
Figure 5.4
MMF operation flow
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5. Memory Mirror Function (MMF)
Start
Set
MMSFR.MEMMIRADDR[15:0]
(start address of the application
in code flash area)
Set MMEN.EN = 1
End
Figure 5.5
5.3.2
MMF setup flow
Setting Example
The target application code on the code flash can be accessed from the address 0200 0000h on the memory mirror space
by setting up the code flash start address in MMSFR.MEMMIRADDR and setting MMEN.EN = 1.
Figure 5.6 shows an example of how to use the MMF.
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5. Memory Mirror Function (MMF)
027F FFFFh
Memory mirror space
0201 0000h
Application code
0200 0000h
003F FFFFh
Code flash
You can choose any version of application code in the MMSFR
register
Application code ver3
0012 0000h
Application code ver2
0011 0000h
Application code ver1
0010 0000h
0001 0000h
Shared start up code
Jump to application code after initialization
- Always the same address
0000 0000h
Figure 5.6
MMF setting example
Setting the MMSFR register to DB10 0000h to use the application code ver1.
Setting the MMSFR register to DB11 0000h to use the application code ver2.
Setting the MMSFR register to DB12 0000h to use the application code ver3.
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6.
Resets
6.1
Overview
6. Resets
The MCU provides 14 resets:
RES pin reset
Power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
Stack pointer error reset
Deep Software Standby reset
Software reset.
Table 6.1 lists the reset names and sources.
Table 6.1
Reset names and sources
Reset name
Source
RES pin reset
Voltage input to the RES pin is driven low
Power-on reset
VCC rise (voltage detection VPOR)*1
Independent watchdog timer reset
IWDT underflow or refresh error
Watchdog timer reset
WDT underflow or refresh error
Voltage monitor 0 reset
VCC fall (voltage detection Vdet0)*1
Voltage monitor 1 reset
VCC fall (voltage detection Vdet1)*1
Voltage monitor 2 reset
VCC fall (voltage detection Vdet2)*1
SRAM parity error reset
SRAM parity error detection
SRAM ECC error reset
SRAM ECC error detection
Bus master MPU error reset
Bus master MPU error detection
Bus slave MPU error reset
Bus slave MPU error detection
Stack pointer error reset
Stack pointer error detection
Deep software standby reset
Canceling of Deep Software Standby mode by an interrupt
Software reset
Register setting (use the Arm® software reset bit AIRCR.SYSRESETREQ)
Note 1.
For details on the voltages to be monitored (VPOR, Vdet0, Vdet1, and Vdet2), see section 8, Low Voltage Detection (LVD) and
section 55, Electrical Characteristics.
The internal state and pins are initialized by a reset. Table 6.2 and Table 6.3 list the targets initialized by resets.
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Table 6.2
6. Resets
Reset detect flags initialized by each reset source
Reset source
Flag to be initialized
RES pin
reset
Power-on
reset
Voltage
monitor 0
reset
Independent
watchdog
timer reset
Watchdog
timer reset
Voltage
monitor 1
reset
Voltage
monitor 2
reset
Power-On Reset Detect Flag (RSTSR0.PORF)
×
×
×
×
×
×
×
Voltage Monitor 0 Reset Detect Flag
(RSTSR0.LVD0RF)
×
×
×
×
×
×
Independent Watchdog Timer Reset Detect Flag
(RSTSR1.IWDTRF)
×
×
×
×
×
Watchdog Timer Reset Detect Flag
(RSTSR1.WDTRF)
×
×
×
×
×
Voltage Monitor 1 Reset Detect Flag
(RSTSR0.LVD1RF)
×
×
×
×
×
Voltage Monitor 2 Reset Detect Flag
(RSTSR0.LVD2RF)
×
×
×
×
×
Software Reset Detect Flag (RSTSR1.SWRF)
×
×
×
×
×
SRAM Parity Error Reset Detect Flag
(RSTSR1.RPERF)
×
×
×
×
×
SRAM ECC Error Reset Detect Flag
(RSTSR1.REERF)
×
×
×
×
×
Bus Slave MPU Error Reset Detect Flag
(RSTSR1.BUSSRF)
×
×
×
×
×
Bus Master MPU Error Reset Detect Flag
(RSTSR1.BUSMRF)
×
×
×
×
×
Stack Pointer Error Reset Detect Flag
(RSTSR1.SPERF)
×
×
×
×
×
Deep Software Standby Reset Detect Flag
(RSTSR0.DPSRSTF)
×
×
×
×
×
Cold Start/Warm Start Determination Flag
(RSTSR2.CWSF)
×
×
×
×
×
×
×
SRAM ECC
error reset
Bus master
MPU error
reset
Bus slave
MPU error
reset
Stack
pointer
error reset
Deep Software Standby reset
Flag to be initialized
SRAM
parity error
reset
DEEPCUT[0] = 0
DEEPCUT[0] = 1
Power-On Reset Detect Flag (RSTSR0.PORF)
×
×
×
×
×
×
×
Voltage Monitor 0 Reset Detect Flag
(RSTSR0.LVD0RF)
×
×
×
×
×
×
×
Independent Watchdog Timer Reset Detect Flag
(RSTSR1.IWDTRF)
×
×
×
×
×
Watchdog Timer Reset Detect Flag
(RSTSR1.WDTRF)
×
×
×
×
×
Voltage Monitor 1 Reset Detect Flag
(RSTSR0.LVD1RF)
×
×
×
×
×
×
×
Voltage Monitor 2 Reset Detect Flag
(RSTSR0.LVD2RF)
×
×
×
×
×
×
×
Software Reset Detect Flag (RSTSR1.SWRF)
×
×
×
×
×
SRAM Parity Error Reset Detect Flag
(RSTSR1.RPERF)
×
×
×
×
×
SRAM ECC Error Reset Detect Flag
(RSTSR1.REERF)
×
×
×
×
×
Bus Slave MPU Error Reset Detect Flag
(RSTSR1.BUSSRF)
×
×
×
×
×
Bus Master MPU Error Reset Detect Flag
(RSTSR1.BUSMRF)
×
×
×
×
×
Stack Pointer Error Reset Detect Flag
(RSTSR1.SPERF)
×
×
×
×
×
Deep Software Standby Reset Detect Flag
(RSTSR0.DPSRSTF)
×
×
×
×
×
×
×
Cold Start/Warm Start Determination Flag
(RSTSR2.CWSF)
×
×
×
×
×
×
×
Software
reset
Reset source
: Initialized to 0
×: Not initialized
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Table 6.3
6. Resets
Module-related registers initialized by each reset source
Reset source
Registers to be initialized
RES pin
reset
Power-on
reset
Voltage
monitor 0
reset
Independent
watchdog
timer reset
Watchdog
timer
reset
Voltage
monitor 1
reset
Voltage
monitor 2
reset
Software
reset
Watchdog timer registers
WDTRR, WDTCR, WDTSR,
WDTRCR, WDTCSTPR
Voltage monitor function 1
registers
LVD1CR0, LVCMPCR.LVD1E,
LVDLVLR.LVD1LVL
×
×
×
LVD1CR1/LVD1SR
×
×
×
LVD2CR0, LVCMPCR.LVD2E,
LVDLVLR.LVD2LVL
×
×
×
LVD2CR1/LVD2SR
×
×
×
SOSCCR
×
*1
×
×
×
×
×
×
SOMCR
×
×
×
×
×
×
×
×
LOCOCR
LOCOUTCR
×
×
×
×
MOMCR
×
×
×
×
×
×
×
×
Voltage monitor function 2
registers
SOSC register
LOCO registers
MOSC register
Realtime Clock (RTC) register*2
×
×
×
×
Except DPUSR0R, DPUSR1R
DPUSR0R, DPUSR1R
MPU register
Pin states (except XCIN/XCOUT pin)
Pin states (XCIN/XCOUT pin)
×
×
×
×
×
×
×
×
Battery backup register
×
×
×
×
×
×
×
×
Registers other than those shown, CPU, and internal state
AGT registers
USBFS registers
Low-power function registers
DPSBYCR, DPSIER0 to
DPSIER3, DPSIFR0 to
DPSIFR3, DPSIEGR0 to
DPSIEGR2
Reset source
Registers to be initialized
SRAM
parity
error
reset
SRAM
ECC error
reset
Bus
master
MPU error
reset
Bus slave
MPU error
reset
Stack
pointer
error reset
Deep Software Standby reset
DEEPCUT[0] = 0
DEEPCUT[0] = 1
Watchdog timer registers
WDTRR, WDTCR, WDTSR,
WDTRCR, WDTCSTPR
Voltage monitor function 1
registers
LVD1CR0, LVCMPCR.LVD1E,
LVDLVLR.LVD1LVL
×
×
×
×
×
×
×
LVD1CR1/LVD1SR
×
×
×
×
×
LVD2CR0, LVCMPCR.LVD2E,
LVDLVLR.LVD2LVL
×
×
×
×
×
×
×
Voltage monitor function 2
registers
LVD2CR1/LVD2SR
×
×
×
×
×
SOSC register
SOSCCR
×
×
×
×
×
×
×
SOMCR
×
×
×
×
×
×
×
LOCO register
LOCOCR
LOCOUTCR
×
×
×
×
×
×
MOMCR
×
×
Realtime Clock (RTC) register*2
×
×
×
×
×
×
×
AGT register
×
×
×
×
×
×
Except DPUSR0R, DPUSR1R
DPUSR0R, DPUSR1R
×
MPU register
×
×
×
Pin states (except XCIN/XCOUT pin)
*3
*3
Pin states (XCIN/XCOUT pin)
×
×
×
×
×
×
×
×
×
Battery backup register
×
×
×
×
×
×
×
Registers other than those shown, CPU, and internal state
MOSC registers
USBFS registers
Low-power function registers
DPSBYCR, DPSIER0 to
DPSIER3, DPSIFR0 to
DPSIFR3, DPSIEGR0 to
DPSIEGR2
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6. Resets
: Initialized
×: Not initialized
Note 1.
Note 2.
Note 3.
For the initial value of each register, see section 9, Clock Generation Circuit.
The RTC has a software reset. RCR1.RTCOS, RCR1.CIE, RCR2.RTCOE, RCR2.ADJ30, and RCR2.RESET are initialized by
all types of resets. For details on the target bits, see section 26, Realtime Clock (RTC).
Depends on the setting of DPSBYCR.IOKEEP.
The RTC is not initialized by any reset source. SOSC and LOCO can be selected as the clock sources of RTC. Table 6.4
and Table 6.5 show the states of SOSC and LOCO when a reset occurs.
Table 6.4
States of SOSC when a reset occurs
Reset source
SOSC
Table 6.5
POR
Other
Enable or disable
Initialized to enable
Continue with the state that was selected before the
reset occurred
Drive capability
Continue with the state that was selected before the reset occurred
States of LOCO when a reset occurs
Reset source
POR, LVD0, LVD1, LVD2/
Deep Software Standby
(DEEPCUT[0] = 1)
LOCO
Note 1.
Enable or disable
Initialized to enable
Oscillation accuracy*1
Initialized to accuracy before trimming
by LOCOUTCR (accuracy: ± 15%)
Other
Continue with the accuracy that was trimmed by
LOCOUTCR
The LOCO User Trimming Control Register (LOCOUTCR) is reset by POR, LVD0, LVD1, LVD2, and Deep Software Standby
(DEEPCUT[0] = 1) resets, returning the LOCO to the default oscillation accuracy. This can affect RTC accuracy if the RTC uses
the LOCO (with a user trimming value in LOCOUTCR) as the RTC source clock. To restore the pre-reset LOCO oscillation
accuracy, reload the required trimming value into LOCOUTCR after any of these resets.
Table 6.6 lists the pin related to the reset function.
Table 6.6
Reset I/O pin
Pin name
I/O
Function
RES
Input
Reset pin
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6.2
6. Resets
Register Descriptions
6.2.1
Reset Status Register 0 (RSTSR0)
Address(es): SYSTEM.RSTSR0 4001 E410h
b7
b6
b5
b4
DPSRS
TF
—
—
—
x*1
0
0
0
Value after reset:
b3
b2
b1
b0
LVD2R LVD1R LVD0R PORF
F
F
F
x*1
x*1
x*1
x*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
PORF
Power-On Reset Detect Flag
0: Power-on reset not detected
1: Power-on reset detected.
R(/W)*2
b1
LVD0RF
Voltage Monitor 0 Reset Detect Flag
0: Voltage monitor 0 reset not detected
1: Voltage monitor 0 reset detected.
R(/W)*2
b2
LVD1RF
Voltage Monitor 1 Reset Detect Flag
0: Voltage monitor 1 reset not detected
1: Voltage monitor 1 reset detected.
R(/W)*2
b3
LVD2RF
Voltage Monitor 2 Reset Detect Flag
0: Voltage monitor 2 reset not detected
1: Voltage monitor 2 reset detected.
R(/W)*2
b6 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
DPSRSTF
Deep Software Standby Reset Flag
0: Deep Software Standby mode cancellation not
requested by an interrupt
1: Deep Software Standby mode cancellation
requested by an interrupt.
R(/W)*2
Note 1.
Note 2.
The value after reset depends on the reset source.
Only 0 can be written to clear the flag. The flag must be cleared by writing 0 after 1 is read.
PORF flag (Power-On Reset Detect Flag)
The PORF flag indicates that a power-on reset occurred.
[Setting condition]
When a power-on reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to PORF.
LVD0RF flag (Voltage Monitor 0 Reset Detect Flag)
The LVD0RF flag indicates that the VCC voltage fell below Vdet0.
[Setting condition]
When a voltage monitor 0 reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to LVD0RF.
LVD1RF flag (Voltage Monitor 1 Reset Detect Flag)
The LVD1RF flag indicates that the VCC voltage fell below Vdet1.
[Setting condition]
When a voltage monitor 1 reset occurs.
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6. Resets
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to LVD1RF.
LVD2RF flag (Voltage Monitor 2 Reset Detect Flag)
The LVD2RF flag indicates that the VCC voltage fell below Vdet2.
[Setting condition]
When a voltage monitor 2 reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to LVD2RF.
DPSRSTF flag (Deep Software Standby Reset Flag)
The DPSRSTF flag indicates that Deep Software Standby mode is canceled by an external or internal interrupt, and that
an internal reset (Deep Software Standby reset) occurs when an exception from Deep Software Standby mode occurs.
[Setting condition]
When Deep Software Standby mode is canceled by an external or internal interrupt. For details, see section 11, Low
Power Modes.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to DPSRSTF.
6.2.2
Reset Status Register 1 (RSTSR1)
Address(es): SYSTEM.RSTSR1 4001 E0C0h
b15
b14
b13
—
—
—
0
0
0
Value after reset:
b12
b11
b10
b9
b8
b7
SPERF BUSM BUSSR REERF RPERF
RF
F
x*1
x*1
x*1
x*1
x*1
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SWRF WDTR IWDTR
F
F
x*1
x*1
x*1
Bit
Symbol
Bit name
Description
R/W
b0
IWDTRF
Independent Watchdog Timer Reset
Detect Flag
0: Independent watchdog timer reset not detected
1: Independent watchdog timer reset detected.
R(/W)
*2
b1
WDTRF
Watchdog Timer Reset Detect Flag
0: Watchdog timer reset not detected
1: Watchdog timer reset detected.
R(/W)
*2
b2
SWRF
Software Reset Detect Flag
0: Software reset not detected
1: Software reset detected.
R(/W)
*2
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b8
RPERF
SRAM Parity Error Reset Detect Flag
0: SRAM parity error reset not detected
1: SRAM parity error reset detected.
R(/W)
*2
b9
REERF
SRAM ECC Error Reset Detect Flag
0: SRAM ECC error reset not detected
1: SRAM ECC error reset detected.
R(/W)
*2
b10
BUSSRF
Bus Slave MPU Error Reset Detect Flag
0: Bus slave MPU error reset not detected
1: Bus slave MPU error reset detected.
R(/W)
*2
b11
BUSMRF
Bus Master MPU Error Reset Detect Flag
0: Bus master MPU error reset not detected
1: Bus master MPU error reset detected.
R(/W)
*2
b12
SPERF
SP Error Reset Detect Flag
0: SP error reset not detected
1: SP error reset detected.
R(/W)
*2
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6. Resets
Bit
Symbol
Bit name
Description
b15 to b13
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note 1.
Note 2.
R/W
The value after reset depends on the reset source.
Only 0 can be written to clear the flag. The flag must be cleared by writing 0 after 1 is read.
IWDTRF flag (Independent Watchdog Timer Reset Detect Flag)
The IWDTRF flag indicates that an independent watchdog timer reset occurred.
[Setting condition]
When an independent watchdog timer reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to IWDTRF.
WDTRF flag (Watchdog Timer Reset Detect Flag)
The WDTRF flag indicates that a watchdog timer reset occurred.
[Setting condition]
When a watchdog timer reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to WDTRF.
SWRF flag (Software Reset Detect Flag)
The SWRF flag indicates that a software reset occurred.
[Setting condition]
When a software reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to SWRF.
RPERF flag (SRAM Parity Error Reset Detect Flag)
The RPERF flag indicates that a SRAM parity error reset occurred.
[Setting condition]
When a SRAM parity error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to RPERF.
REERF flag (SRAM ECC Error Reset Detect Flag)
The REERF flag indicates that a SRAM ECC error reset occurred.
[Setting condition]
When a SRAM ECC error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
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6. Resets
When 1 is read from and then 0 is written to REERF.
BUSSRF flag (Bus Slave MPU Error Reset Detect Flag)
The BUSSRF flag indicates that a bus slave MPU error reset occurred.
[Setting condition]
When a bus slave MPU error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to BUSSRF.
BUSMRF flag (Bus Master MPU Error Reset Detect Flag)
The BUSMRF flag indicates that a bus master MPU error reset occurred.
[Setting condition]
When a bus master MPU error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to BUSMRF.
SPERF flag (SP Error Reset Detect Flag)
The SPERF flag indicates that a stack pointer error reset occurred.
[Setting condition]
When a stack pointer error reset occurs.
[Clearing conditions]
When a reset listed in Table 6.2 occurs
When 1 is read from and then 0 is written to SPERF.
6.2.3
Reset Status Register 2 (RSTSR2)
Address(es): SYSTEM.RSTSR2 4001 E411h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
CWSF
0
0
0
0
0
0
0
x*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
CWSF
Cold/Warm Start Determination Flag
0: Cold start
1: Warm start.
R(/W)
*2
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
The value after reset depends on the reset source.
Only 1 can be written to set the flag.
RSTSR2 determines whether a power-on reset caused the reset processing (cold start) or a reset signal input during
operation caused the reset processing (warm start).
CWSF flag (Cold/Warm Start Determination Flag)
The CWSF flag indicates the type of reset processing, either cold start or warm start. The CWSF flag is initialized by a
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6. Resets
power-on reset. It is not initialized by a reset signal generated by the RES pin.
[Setting condition]
When 1 is written by software. Writing 0 to CWSF does not set it to 0.
[Clearing condition]
When a reset listed in Table 6.2 occurs.
6.3
6.3.1
Operation
RES Pin Reset
The RES pin generates this reset. When the RES pin is driven low, all the processing in progress is aborted and the MCU
enters a reset state. To successfully reset the MCU, the RES pin must be held low for the power supply stabilization time
specified at power-on.
When the RES pin is driven high from low, the internal reset is canceled after the post-RES cancellation wait time
(tRESWT) elapses. The CPU then starts the reset exception handling.
For details, see section 55, Electrical Characteristics.
6.3.2
Power-On Reset
The power-on reset (POR) is an internal reset generated by the power-on reset circuit. If the RES pin is in a high-level
state when power is supplied, a power-on reset is generated. After VCC exceeds VPOR and the specified power-on reset
time elapses, the internal reset is canceled and the CPU starts the reset exception handling. The power-on reset time is the
stabilization period for the external power supply and the MCU circuit. After a power-on reset is generated, the PORF
flag in the RSTSR0 is set to 1. The PORF flag is initialized by the RES pin reset.
The voltage monitor 0 reset is an internal reset generated by the voltage monitor circuit. If the Voltage Detection 0
Circuit Start bit (LVDAS) in Option Function Select Register 1 (OFS1) is 0 (voltage monitor 0 reset is enabled after a
reset) and VCC falls below Vdet0, the RSTSR0.LVD0RF flag is set to 1 and the voltage detection circuit generates
voltage monitor 0 reset. Clear the OFS1.LVDAS bit to 0 if the voltage monitor 0 reset is to be used.
After VCC exceeds Vdet0 and the voltage monitor 0 reset time (tLVD0) elapses, the internal reset is canceled and the
CPU starts the reset exception handling. The Vdet0 voltage detection level can be changed by the setting in the
VDSEL[1:0] bits in Option Function Select Register 1 (OFS1).
Figure 6.1 shows example of operations during a power-on reset and voltage monitor 0 reset.
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6. Resets
Vdet0*1
*3
VCCmin.
VPOR
VCC
Power-on reset state
Voltage monitor 0 reset state
Voltage monitor 0 reset state
RES pin
POR Monitor
(active-low)
LVD0 enable/disable signal
(active-low)
Set by OFS1.LVDAS
Voltage detection 0 signal
(active-low)
Internal reset signal
(active-low)
RSTSR0.PORF
tLVD0*2
tLVD0*2
Cleared by user
programming
RES pin reset
RSTSR0.LVD0RF
Note:
Note 1.
Note 2.
Note 3.
Figure 6.1
6.3.3
For details on the electrical characteristics, see section 55, Electrical Characteristics.
Vdet0 shows a voltage monitor 0 reset detection level, VPOR shows a power-on reset detection level, and VCCmin shows
minimum guaranteed voltage of MCU.
tLVD0 shows a time for voltage monitor 0 reset.
At power-on, VCC should have risen to the minimum guaranteed voltage before the POR reset is released.
Example of operations during power-on and voltage monitor 0 resets
Voltage Monitor Reset
The voltage monitor 0 reset is an internal reset generated by the voltage monitor circuit. If the Voltage Detection 0
Circuit Start (LVDAS) bit in Option Function Select Register 1 (OFS1) is 0 (voltage monitor 0 reset is enabled after a
reset) and VCC falls below Vdet0, the RSTSR0.LVD0RF flag is set to 1 and the voltage detection circuit generates a
voltage monitor 0 reset. Clear the OFS1.LVDAS bit to 0 if the voltage monitor 0 reset is to be used. After VCC exceeds
Vdet0 and the voltage monitor 0 reset time (tLVD0) elapses, the internal reset is canceled and the CPU starts the reset
exception handling.
When the Voltage Monitor 1 Interrupt/Reset Enable bit (RIE) is set to 1 (enabling generation of a reset or interrupt by the
voltage detection circuit) and the Voltage Monitor 1 Circuit Mode Select bit (LVD1CR0.RI) is set to 1 (selecting
generation of a reset in response to detection of a low voltage) in the Voltage Monitor 1 Circuit Control Register 0
(LVD1CR0), the RSTSR0.LVD1RF flag is set to 1 and the voltage detection circuit generates a voltage monitor 1 reset if
VCC falls to or below Vdet1.
Likewise, when the Voltage Monitor 2 Interrupt/Reset Enable bit (RIE) is set to 1 (enabling generation of a reset or
interrupt by the voltage detection circuit) and the Voltage Monitor 2 Circuit Mode Select bit (LVD2CR0.RI) is set to 1
(selecting generation of a reset in response to detection of a low voltage) in Voltage Monitor 2 Circuit Control Register 0
(LVD2CR0), the RSTSR0.LVD2RF flag is set to 1 and the voltage detection circuit generates a voltage monitor 2 reset if
VCC falls to or below Vdet2.
Similarly, timing for release from the voltage monitor 1 reset state is selectable in the Voltage Monitor 1 Reset Negate
Select bit (RN) in the LVD1CR0. When the LVD1CR0.RN bit is 0 and VCC falls to or below Vdet1, the CPU is released
from the internal reset state and starts reset exception handling when the LVD1 reset time (tLVD1) elapses after VCC
rises above Vdet1. When the LVD1CR0.RN bit is 1 and VCC falls to or below Vdet1, the CPU is released from the
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6. Resets
internal reset state and starts reset exception handling when the LVD1 reset time (tLVD1) elapses.
Likewise, timing for release from the voltage monitor 2 reset state is selectable in the Voltage Monitor 2 Reset Negate
Select bit (RN) in the LDV2CR0 register.
Detection levels Vdet1 and Vdet2 can be changed in the Voltage Detection Level Select Register (LDVLVLR).
Figure 6.2 shows example of operations during voltage monitor 1 and 2 resets. For details on the voltage monitor 1 reset
and voltage monitor 2 reset, see section 8, Low Voltage Detection (LVD).
Vdeti*1
VCC
RES pin
LVDi valid setting
LVCMPCR.LVDiE
Voltage detection i signal
(active-low)
LVDiCR0.RN = 0
RES pin reset
RSTSR0.LVDiRF
tLVDi*2
Internal reset signal
LVDiCR0.RN = 1
RES pin reset
RSTSR0.LVDiRF
Internal reset signal
Note:
Note 1.
Note 2.
Figure 6.2
6.3.4
tLVDi*2
For details on the electrical characteristics, see section 55, Electrical Characteristics.
Vdeti indicates the detection level of a voltage monitor 1 reset and voltage monitor 2 reset. (i = 1, 2)
tLVDi indicates the time for a voltage monitor 1 reset and voltage monitor 2 reset. (i = 1, 2)
Example of operations during voltage monitor 1 and voltage monitor 2 resets
Deep Software Standby Reset
The deep software standby reset is an internal reset generated when Deep Software Standby mode is canceled by an
associated interrupt. The deep software standby reset is canceled after tDSBY (return time after Deep Software Standby
mode cancellation) elapses.
When tDSBYWT (wait time after Deep Software Standby mode cancellation) elapses after Deep Software Standby
mode is canceled, the internal reset is canceled and the CPU starts the reset exception handling.
For details on the deep software standby reset, see section 11, Low Power Modes.
6.3.5
Independent Watchdog Timer Reset
The independent watchdog timer reset is an internal reset generated from the Independent Watchdog Timer (IWDT).
Output of the reset from the IWDT can be selected in the Option Function Select Register 0 (OFS0).
When output of the independent watchdog timer reset is selected, the reset is generated if the IWDT underflows, or if
data is written when refresh operation is disabled. When the internal reset time (tRESW2) elapses after the independent
watchdog timer reset is generated, the internal reset is canceled and the CPU starts the reset exception handling.
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6. Resets
For details on the independent watchdog timer reset, see section 28, Independent Watchdog Timer (IWDT).
6.3.6
Watchdog Timer Reset
The watchdog timer reset is an internal reset generated from the Watchdog Timer (WDT). Output of the reset from the
WDT can be selected in the WDT Reset Control Register (WDTRCR) or Option Function Select Register 0 (OFS0).
When output of the watchdog timer reset is selected, the reset is generated if the WDT underflows, or if data is written
when refresh operation is disabled. When the internal reset time (tRESW2) elapses after the watchdog timer reset is
generated, the internal reset is canceled and the CPU starts the reset exception handling.
For details on the watchdog timer reset, see section 27, Watchdog Timer (WDT).
6.3.7
Software Reset
Software reset is an internal reset generated by a software setting of the SYSRESETREQ bit in the AIRCR register in the
Arm core. When the SYSRESETREQ bit is set to 1, a software reset is generated. When the internal reset time
(tRESW2) elapses after a software reset is generated, the internal reset is canceled and the CPU starts the reset exception
handling.
For details on the SYSRESETREQ bit, see the ARM® Cortex®-M4 Technical Reference Manual.
6.3.8
Determination of Cold/Warm Start
Read the CWSF flag in RSTSR2 to determine the cause of reset processing. The flag indicates whether a power-on reset
caused the reset processing (cold start) or a reset signal input during operation caused the reset processing (warm start).
The CWSF flag is set to 0 when a power-on reset occurs (cold start). Otherwise, the flag is not set to 0. The flag is set to
1 when 1 is written to it through software. It is not set to 0 even on writing 0 to it.
Figure 6.3 shows an example of a cold/warm start determination operation.
VPOR
VCC
RES pin
POR signal (active-low)
Not driven to 0 when a
low level is applied to
the RES pin
RSTSR2.CWSF flag
Set to 1 through programming
Figure 6.3
6.3.9
Example of a cold/warm start determination operation
Determination of Reset Generation Source
Read RSTSR0 and RSTSR1 to determine which reset executes the reset exception handling. Figure 6.4 shows an
example of the flow to identify a reset generation source. The reset flag must be written with 0 after it is read as 1.
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6. Resets
Reset exception
handling
RSTSR1 00h
or
RSTSR0.LVD1RF = 1
or
RSTSR0.LVD2RF = 1
Yes
No
RSTSR0.DPSRSTF
=1
Yes
No
RSTSR0.
LVD0RF = 1
Yes
No
RSTSR0.
PORF = 1
No
Yes
Reset corresponding to
each bit of RSTSR1,
RSTSR0.LVD1RF, or
RSTSR0.LVD2RF*1
Note 1.
Figure 6.4
Deep software
standby reset
Voltage
monitor 0
reset
Power-on
reset
RES pin reset
If two or more resets associated with the RSTSR1, RSTSR0.LVD1RF, or RSTSR0.LVD2RF bits occur at the
same time, all reset flags are set to 1.
Example of reset generation source determination flow
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7. Option-Setting Memory
7.
Option-Setting Memory
7.1
Overview
The option-setting memory determines the state of the MCU after a reset. The option-setting memory is allocated to the
configuration setting area and the program flash area of the flash memory, and the available methods of setting are
different for the two areas.
Figure 7.1 shows the option-setting memory area.
Address*1
0100 A164h to 0100 A167h
Access Window Setting Register
(AWS)
0100 A150h to 0100 A15Ch
OCD/Serial Programmer ID
Setting Register (OSIS)
0000 0408h to 0000 043Bh
SECMPUxxx
0000 0404h to 0000 0407h
Option Function Select Register 1
(OFS1)
0000 0400h to 0000 0403h
Option Function Select Register 0
(OFS0)
Configuration setting area
Program flash area
Note 1. The option-setting memory must be allocated to the flash user area.
Figure 7.1
7.2
Option-setting memory area
Register Descriptions
7.2.1
Option Function Select Register 0 (OFS0)
Address(es): OFS0 0000 0400h
b31
b30
b29
—
WDTST
PCTL
—
b28
b27
b26
b25
b24
b23
WDTRS WDTRPSS[1:0] WDTRPES[1:0]
TIRQS
b22
b21
b20
b19
b18
b17
b16
WDTTOPS[1:0] WDTST
RT
WDTCKS[3:0]
—
User setting*1
Value after reset:
b15
b14
—
IWDTS
TPCTL
b13
—
b12
b11
b10
b9
b8
b7
IWDTRS
TIRQS IWDTRPSS[1:0] IWDTRPES[1:0]
b6
b5
IWDTCKS[3:0]
b4
b3
b2
b1
b0
IWDTTOPS[1:0] IWDTS
TRT
—
User setting*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
b1
IWDTSTRT
IWDT Start Mode Select
0: Automatically activate IWDT after a reset (auto start
mode)
1: Disable IWDT.
R
b3, b2
IWDTTOPS[1:0]
IWDT Timeout Period Select
b3 b2
R
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0
0
1
1
0: 128 cycles (007Fh)
1: 512 cycles (01FFh)
0: 1024 cycles (03FFh)
1: 2048 cycles (07FFh).
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7. Option-Setting Memory
Bit
Symbol
Bit name
Description
R/W
b7 to b4
IWDTCKS[3:0]
IWDT-Dedicated Clock
Frequency Division Ratio
Select
b7
R
b9, b8
IWDTRPES[1:0]
IWDT Window End Position
Select
b9 b8
R
b11, b10
IWDTRPSS[1:0]
IWDT Window Start Position
Select
b11 b10
R
b12
IWDTRSTIRQS
IWDT Reset Interrupt
Request Select
0: Enable non-maskable interrupt request or interrupt
request
1: Enable reset.
R
b13
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
b14
IWDTSTPCTL
IWDT Stop Control
0: Continue counting
1: Stop counting when in Sleep, Snooze, or Software
Standby mode.
R
b16, b15
—
Reserved
When read, these bits return the written value. The write
value should be 1.
R
b17
WDTSTRT
WDT Start Mode Select
0: Automatically activate WDT after a reset (auto start
mode)
1: Stop WDT after a reset (register start mode).
R
b19, b18
WDTTOPS[1:0]
WDT Timeout Period Select
b19 b18
R
b23 to b20
WDTCKS[3:0]
WDT Clock Frequency
Division Ratio Select
b23
b25, b24
WDTRPES[1:0]
WDT Window End Position
Select
b25 b24
R
b27, b26
WDTRPSS[1:0]
WDT Window Start Position
Select
b27 b26
R
b28
WDTRSTIRQS
WDT Reset Interrupt Request
Select
WDT Behavior Select
0: NMI
1: Reset.
R
b29
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
b30
WDTSTPCTL
WDT Stop Control
0: Continue counting
1: Stop counting when entering Sleep mode.
R
b31
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
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b4
0 0 0 0: × 1
0 0 1 0: × 1/16
0 0 1 1: × 1/32
0 1 0 0: × 1/64
1 1 1 1: × 1/128
0 1 0 1: × 1/256.
Other settings are prohibited.
0
0
1
1
0
0
1
1
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (no window end position setting).
0: 25%
1: 50%
0: 75%
1: 100% (no window start position setting).
0: 1024 cycles (03FFh)
1: 4096 cycles (0FFFh)
0: 8192 cycles (1FFFh)
1: 16384 cycles (3FFFh).
R
b20
0 0 0 1: PCLKB divided by 4
0 1 0 0: PCLKB divided by 64
1 1 1 1: PCLKB divided by 128
0 1 1 0: PCLKB divided by 512
0 1 1 1: PCLKB divided by 2048
1 0 0 0: PCLKB divided by 8192.
Other settings are prohibited.
0
0
1
1
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (No window end position setting).
0: 25%
1: 50%
0: 75%
1: 100% (No window start position setting).
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Note 1.
7. Option-Setting Memory
The value in a blank product is FFFF FFFFh. It is set to the value written by your application.
IWDTSTRT bit (IWDT Start Mode Select)
The IWDTSTRT bit selects the mode in which the IWDT is activated after a reset (stopped state or activated state).
IWDTTOPS[1:0] bits (IWDT Timeout Period Select)
The IWDTTOPS[1:0] bits select the timeout period, the time it takes for the down counter to underflow, as 128, 512,
1024, or 2048 cycles of the frequency-divided clock set in the IWDTCKS[3:0] bits. The number of clock cycles that the
counter takes to underflow after a refresh operation is determined by the combination of the IWDTCKS[3:0] and
IWDTTOPS[1:0] bits.
For details, see section 28, Independent Watchdog Timer (IWDT).
IWDTCKS[3:0] bits (IWDT-Dedicated Clock Frequency Division Ratio Select)
The IWDTCKS[3:0] bits select the division ratio of the prescaler for dividing the frequency of the clock for the IWDT as
1/1, 1/16, 1/32, 1/64, 1/128, or 1/256. Using this setting combined with the IWDTTOPS[1:0] bit setting, the IWDT
counting period can be set from 128 to 524,288 IWDT clock cycles.
For details, see section 28, Independent Watchdog Timer (IWDT).
IWDTRPES[1:0] bits (IWDT Window End Position Select)
The IWDTRPES[1:0] bits select the position where the window for the down counter ends as 0%, 25%, 50%, or 75% of
the count value. The value of the window end position must be smaller than the value of the window start position.
Otherwise, only the value for the window start position is valid.
The counter values associated with the settings for the start and end positions of the window, in the IWDTRPSS[1:0] and
IWDTRPES[1:0] bits vary with the setting in the IWDTTOPS[1:0] bits.
For details, see section 28, Independent Watchdog Timer (IWDT).
IWDTRPSS[1:0] bits (IWDT Window Start Position Select)
The IWDTRPSS[1:0] bits select the position where the window for the down counter starts as 25%, 50%, 75%, or 100%
of the counted value. The point at which counting starts is 100% and the point at which an underflow occurs is 0%. The
interval between the positions where the window starts and ends becomes the period in which a refresh is possible.
However, refresh is not possible outside this period.
For details, see section 28, Independent Watchdog Timer (IWDT).
IWDTRSTIRQS bit (IWDT Reset Interrupt Request Select)
The IWDTRSTIRQS bit selects the operation on an underflow of the down counter or generation of a refresh error. The
selected operation can be an independent watchdog timer reset, non-maskable interrupt request, or interrupt request.
For details, see section 28, Independent Watchdog Timer (IWDT).
IWDTSTPCTL bit (IWDT Stop Control)
The IWDTSTPCTL bit specifies whether to stop counting when entering Sleep, Snooze, or Software Standby mode.
For details, see section 28, Independent Watchdog Timer (IWDT).
WDTSTRT bit (WDT Start Mode Select)
The WDTSTRT bit selects the mode in which the WDT is activated after a reset (stopped state or activated state). When
the WDT is activated in auto start mode, the OFS0 register setting for the WDT is valid.
WDTTOPS[1:0] bits (WDT Timeout Period Select)
The WDTTOPS[1:0] bits select the timeout period, the time it takes for the down counter to underflow, as 1024, 4096,
8192, or 16384 cycles of the frequency-divided clock set in the WDTCKS[3:0] bits. The number of PCLKB cycles that
the counter takes to underflow after a refresh operation is determined by the combination of the WDTCKS[3:0] and
WDTTOPS[1:0] bits.
For details, see section 27, Watchdog Timer (WDT).
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7. Option-Setting Memory
WDTCKS[3:0] bits (WDT Clock Frequency Division Ratio Select)
The WDTCKS[3:0] bits select the division ratio of the prescaler to divide the PCLKB frequency as 1/4, 1/64, 1/128,
1/512, 1/2048, or 1/8192. Using this setting combined with the WDTTOPS[1:0] bit setting, the WDT counting period
can be set from 4,096 to 134,217,728 PCLKB cycles.
For details, see section 27, Watchdog Timer (WDT).
WDTRPES[1:0] bits (WDT Window End Position Select)
The WDTRPES[1:0] bits select the position where the window for the down counter ends as 0%, 25%, 50%, or 75% of
the counted value. The value of the window end position must be smaller than the value of the window start position.
Otherwise, only the value for the window start position is valid.
The counter values associated with the settings for the start and end positions of the window, in the WDTRPSS[1:0] and
WDTRPES[1:0] bits, vary with the setting of the WDTTOPS[1:0] bits.
For details, see section 27, Watchdog Timer (WDT).
WDTRPSS[1:0] bits (WDT Window Start Position Select)
The WDTRPSS[1:0] bits select the position where the window for the down counter starts as 25%, 50%, 75%, or 100%
of the counted value. The point at which counting starts is 100% and the point at which an underflow occurs is 0%. The
interval between the positions where the window starts and ends becomes the period in which a refresh is possible.
However, refresh is not possible outside this period.
For details, see section 27, Watchdog Timer (WDT).
WDTRSTIRQS bit (WDT Reset Interrupt Request Select)
The WDTRSTIRQS bit selects the operation on an underflow of the down counter or generation of a refresh error. The
selected operation can be a watchdog timer reset, non-maskable interrupt request, or interrupt request.
For details, see section 27, Watchdog Timer (WDT).
WDTSTPCTL bit (WDT Stop Control)
The WDTSTPCTL bit specifies whether to stop counting when entering Sleep mode. For details, see section 27,
Watchdog Timer (WDT).
7.2.2
Option Function Select Register 1 (OFS1)
Address(es): OFS1 0000 0404h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
LVDAS
User setting*1
Value after reset:
b15
b14
b13
b12
b11
—
—
—
—
—
b10
b9
b8
HOCOFRQ0[1:0 HOCO
]
EN
VDSEL0[1:0]
User setting*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b1, b0
VDSEL0[1:0]
Voltage Detection 0
Level Select
b1 b0
R
b2
LVDAS
Voltage Detection 0
Circuit Start
0: Enable voltage monitor 0 reset after a reset
1: Disable voltage monitor 0 reset after a reset.
R
b7 to b3
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
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0
0
1
1
0: Setting prohibited
1: Select 2.94 V
0: Select 2.87 V
1: Select 2.80 V.
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7. Option-Setting Memory
Bit
Symbol
Bit name
Description
R/W
b8
HOCOEN
HOCO Oscillation
Enable
0: Enable HOCO oscillation after a reset
1: Disable HOCO oscillation after a reset.
R
b10, b9
HOCOFRQ0[1:0]
HOCO Frequency
Setting 0
b10 b9
R
b31 to b11
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
Note 1.
0
0
1
1
0: 16 MHz
1: 18 MHz
0: 20 MHz
1: Setting prohibited.
The value in a blank product is FFFF FFFFh. It is set to the value written by your application.
VDSEL0[1:0] bits (Voltage Detection 0 Level Select)
The VDSEL0[1:0] bits select the voltage detection level of the voltage detection 0 circuit.
LVDAS bit (Voltage Detection 0 Circuit Start)
The LVDAS bit selects whether the voltage monitor 0 reset is enabled or disabled after a reset.
HOCOEN bit (HOCO Oscillation Enable)
The HOCOEN bit selects whether the HOCO oscillation is enabled or disabled after a reset. Setting this bit to 0 allows
the HOCO oscillation to start before the CPU starts operation, which reduces the wait time for oscillation stabilization.
Note:
When the HOCOEN bit is set to 0, the system clock source is not switched to HOCO. The system clock source is
only switched to HOCO by setting the Clock Source Select bits (SCKSCR.CKSEL[2:0]). To use the HOCO clock,
you must set the OFS1.HOCOFRQ0 bit to an optimum value.
HOCOFRQ0[1:0] bits (HOCO Frequency Setting 0)
The HOCOFRQ0[1:0] bits specify the HOCO frequency after a reset as 16, 18, or 20 MHz.
7.2.3
Access Window Setting Register (AWS)
Address(es): AWS 0100 A164h
b31
b30
b29
b28
b27
BTFLG
—
—
—
—
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b4
b3
b2
b1
b0
FAWE[10:0]
User setting
Value after reset:
b15
b14
b13
b12
b11
FSPR
—
—
—
—
b10
b9
b8
b7
b6
b5
FAWS[10:0]
User setting
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b10 to b0
FAWS[10:0]
Access Window Start Block
Address
These bits specify the start block address for the access window.
They do not represent the block number of the access window.
The access window is only valid in the program flash area. The
block address specifies the first address of the block and consists
of address bits [23:13].
R
b14 to b11
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
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7. Option-Setting Memory
Bit
Symbol
Bit name
Description
R/W
b15
FSPR
Protection of Access
Window and Startup Area
Select Function
This bit controls the programming of the write/erase protection for
the access window, the Startup Area Select flag (AWS.BTFLG),
and the temporary boot swap control. When this bit is set to 0, it
cannot be changed to 1.
0: Executing the configuration setting command for programming
the access window (FAWE[10:0], FAWS[10:0]) and the Startup
Area Select flag (AWS.BTFLG) is invalid
1: Executing the configuration setting command for programming
the access window (FAWE[10:0], FAWS[10:0]) and the Startup
Area Select flag (AWS.BTFLG) is valid.
R
b26 to b16
FAWE[10:0]
Access Window End Block
Address
These bits specify the end block address for the access window.
They do not represent the block number of the access window.
The access window is only valid in the program flash area. The
end block address for the access window is the next block to the
region acceptable for programming and erasure defined by the
access window. The block address specifies the first address of
the block and consists of the address bits [23:13].
R
b30 to b27
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b31
BTFLG
Startup Area Select Flag
This bit specifies whether the address of the startup area is
exchanged for the boot swap function or not:
0: First 8-KB area (0000 0000h to 0000 1FFFh) and second 8-KB
area (0000 2000h to 0000 3FFFh) are exchanged
1: First 8-KB area (0000 0000h to 0000 1FFFh) and second 8-KB
area (0000 2000h to 0000 3FFFh) are not exchanged.
R
Issuing the program or erase (P/E) command to an area outside the access window causes a command-locked state. The
access window is only valid in the program flash area. The access window provides protection in self-programming
mode, serial programming mode, and on-chip debug mode. The access window can be locked by the FSPR bit.
The access window is specified in both the FAWS[10:0] and FAWE[10:0] bits: The following describes how to set the
FAWS[10:0] and FAWE[10:0] bits:
FAWE[10:0] = FAWS[10:0]: The P/E command is allowed to execute in the full program flash area
FAWE[10:0] > FAWS[10:0]: The P/E command is only allowed to execute in the window from the block pointed to
by the FAWS[10:0] bits to the block one lower than the block pointed to by the FAWE[10:0] bits
FAWE[10:0] < FAWS[10:0]: The P/E command is not allowed to execute in the program flash area.
P/E
Address
…
Block 7
(FAWE[10:0] = 007h)
Protected
area
Block 6
Access
window
Block 5
Non-protected
area
Block 4
(FAWS[10:0] = 004h)
Block 3
Block 2
Block 1
Protected
area
Block 0
Figure 7.2
Access window overview
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7.2.4
7. Option-Setting Memory
OCD/Serial Programmer ID Setting Register (OSIS)
The OSIS register stores the ID for ID code protection of the OCD/serial programmer. When connecting the OCD/serial
programmer, write values so that the MCU can determine whether to permit the connection. Use this register to check
whether a code transmitted from the OCD/serial programmer matches the ID code in the option-setting memory.
When the ID codes match, connection of the OCD/serial programmer is permitted, if not, connection with the
OCD/serial programmer is not possible. The OSIS register must be set in 32-bit words.
Address(es): OSIS 0100 A150h, OSIS 0100 A154h, OSIS 0100 A158h, OSIS 0100 A15Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
User setting
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
User setting
Value after reset:
These fields hold the ID for use in ID authentication for the OCD/serial programmer.
ID code bits [127] and [126] determine whether ID code protection is enabled and the method of authentication to use
with the host. Table 7.1 shows how the ID code determines the method of authentication.
Setting bit [127] to 0 prevents Renesas from accessing the test mode. Therefore, Renesas cannot perform failure analysis
unless provided with bits [126:0]. To process any warranty claim, Renesas must be able to perform failure analysis.
Table 7.1
Specifications for ID code protection
Operating mode on boot
up
ID code
State of protection
Serial programming mode
(SCI/USB boot mode)
FFh, …, FFh
(all bytes are FFh)
Protection disabled
The ID code is not checked, the ID code always
matches, and the connection to programmer or onchip debugger is permitted
Bit [127] = 1 and bit [126] =
1, and at least one of the
16 bytes is not FFh.
Protection enabled
Matching ID code = authentication is complete and
connection to the programmer or the on-chip
debugger is permitted.
Mismatching ID code = transition to the ID code
protection wait state.
When the ID code sent from the programmer or
the on-chip debugger is ALeRASE in ASCII code
(414C_6552_4153_45FF_FFFF_FFFF_FFFF_FF
FFh), the contents of the user flash (code and
data) area and the configuration area are erased.
However, forced erasure is not executed when the
FSPR bit is 0.
Bit [127] = 1 and bit [126] =
0
Protection enabled
Matching ID code = authentication is complete and
connection to the programmer or the on-chip
debugger is permitted.
Mismatching ID code = transition to the ID code
protection wait state.
Bit [127] = 0
Protection enabled
The ID code is not checked, the ID code is always
mismatching, and the connection to the
programmer or the on-chip debugger is prohibited
On-chip debug mode
(JTAG/SWD boot mode)
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7.3
7. Option-Setting Memory
Setting the Option-Setting Memory
7.3.1
Allocation of Data in the Option-Setting Memory
Programming data is allocated to the addresses in the option-setting memory shown in Figure 7.1. The allocated data is
used by tools such as a flash programming software or an on-chip debugger.
Note:
Programming formats vary depending on the compiler. See the compiler manual for details.
7.3.2
Setting Data for Programming the Option-Setting Memory
Allocating data as described in section 7.3.1, Allocation of Data in the Option-Setting Memory, alone does not actually
write the data to the option-setting memory. You must also follow one of the actions described in this section.
(1)
Changing the option-setting memory by self-programming
To write data to the program flash area, use the programming command. To write data to the option-setting memory in
the configuration setting area, use the configuration setting command. In addition, use the startup area select function to
safely update the boot program that includes the option-setting memory.
For details on the programming command, the configuration setting command, and the startup area select function, see
section 53, Flash Memory.
Note:
While programming the configuration setting area, the following restrictions apply:
The code must not access addresses that satisfy the ranges described by the expression defined in Expression 1
from all bus masters
The code must not execute on addresses that satisfy the ranges described by the expression defined in Expression
1.
Expression 1
If (((address & 0x0101F800) = = 0x01010000) || ((address & 0x0101FC00) = = 0x01012000))
For example, the ranges of addresses 0x1FFF0000 to 0x1FFF07FF or 0x1FFF2000 to 0x1FFF23FF are associated with
the SRAMHS area that is tagged as restricted. Also, interrupts are allowed, however, the ISR has these specified
restrictions. Therefore, it is highly recommended that you disable all interrupts, and bus masters except the CPU while
programming the configuration setting area because the interrupts and these modules might access prohibited area in
Expression 1.
(2)
Debugging through an OCD or programming by a flash writer
This procedure depends on the tool in use, see the tool manual for details.
The MCU provides two setting procedures:
Read the data allocated as described in section 7.3.1, Allocation of Data in the Option-Setting Memory, from an
object file or Motorola S-format file generated by the compiler, and write the data to the MCU
Use the GUI interface of the tool to program the same data allocated as described in section 7.3.1, Allocation of
Data in the Option-Setting Memory.
Note:
While programming the OSIS or AWS registers, the following restrictions apply:
The code must not access addresses that satisfy the ranges described by the expression defined in Expression 1
from all bus masters
The code must not execute on addresses that satisfy the ranges described by the expression defined in Expression
1.
7.4
7.4.1
Usage Notes
Data for Programming Reserved Areas and Reserved Bits in the Option-Setting
Memory
When reserved areas and reserved bits in the option-setting memory are within the scope of programming, write 1 to all
bits in reserved areas and all reserved bits. Operation is not guaranteed if 0 is written to these bits.
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8. Low Voltage Detection (LVD)
8.
Low Voltage Detection (LVD)
8.1
Overview
The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin, and the detection level can
be selected using a software program. The LVD module consists of three separate voltage level detectors, 0, 1, and 2,
which measure the voltage level input to the VCC pin. LVD voltage detection registers allow your application to
configure detection of VCC changes at various voltage thresholds.
Each voltage level detector has a voltage monitor associated with it, for example voltage monitors 0, 1, and 2. Voltage
monitor registers are used to configure the LVD to trigger an interrupt, event link output, or reset when the thresholds are
crossed.
Table 8.1 lists the LVD specifications. Figure 8.1 shows a block diagram of voltage detectors 0, 1, and 2, Figure 8.2
shows a block diagram of the voltage monitor 1 interrupt and reset circuit, and Figure 8.3 shows a block diagram of the
voltage monitor 2 interrupt and reset circuit.
Table 8.1
LVD specifications
Voltage monitor 0
specifications
Voltage monitor 1 specifications Voltage monitor 2 specifications
Monitored
voltage
Vdet0
Vdet1
Vdet2
Detected
event
Voltage falls past Vdet0
Voltage rises or falls past Vdet1
Voltage rises or falls past Vdet2
Detection
voltage
Selectable from three
different levels in the
OFS1.VDSEL0[1:0] bits
Selectable from three different
levels in the
LVDLVLR.LVD1LVL[4:0] bits
Selectable from three different
levels in the
LVDLVLR.LVD2LVL[2:0] bits
Monitor flag
None
LVD1SR.MON flag: Monitors
whether voltage is higher or lower
than Vdet1
LVD2SR.MON flag: Monitors
whether voltage is higher or lower
than Vdet2
LVD1SR.DET flag: Vdet1 passage
detection
LVD2SR.DET flag: Vdet2 passage
detection
Parameter
VCC
monitoring
Process on
voltage
detection
Reset
Interrupt
Digital filter
Event linking
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Reset when Vdet0 > VCC
CPU restart after specified
time with VCC > Vdet0
Reset when Vdet1 > VCC
CPU restart timing selectable:
after specified time with VCC >
Vdet1 or Vdet1 > VCC
Reset when Vdet2 > VCC
CPU restart timing selectable:
after specified time with VCC >
Vdet2 or Vdet2 > VCC
No interrupt
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Non-maskable or maskable
interrupt selectable
Non-maskable or maskable
interrupt selectable
Interrupt request issued when
Vdet1 > VCC or VCC > Vdet1
Interrupt request issued when
Vdet2 > VCC or VCC > Vdet2
Enable/
Disable
switching
Digital filter function not
available
Available
Available
Sampling
time
—
1/n LOCO frequency 2
(n: 2, 4, 8, 16)
1/n LOCO frequency 2
(n: 2, 4, 8, 16)
None
Available
Output of event signals on
detection of Vdet1 crossings
Available
Output of event signals on
detection of Vdet2 crossings
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8. Low Voltage Detection (LVD)
OFS1.LVDAS
VCC
Voltage detection 0 reset signal
+
-
Level selection
circuit
Internal reference voltage
(for detecting Vdet0)
Vdet0
OFS1.VDSEL[1:0]
LVCMPCR.LVD1E
LVD1CR0.CMPE
Voltage detection 1 signal
+
Internal reference voltage
(for detecting Vdet1)
Level selection
circuit
- Vdet1
LVDLVLR.LVD1LVL[4:0]
LVCMPCR.LVD2E
LVD2CR0.CMPE
Voltage detection 2 signal
+
Internal reference voltage
(for detecting Vdet2)
- Vdet2
Level selection
circuit
LVDLVLR.LVD2LVL[2:0]
Note 1. See section 7, Option-Setting Memory.
Figure 8.1
Voltage detection 0, 1, and 2 block diagram
Voltage monitor 1
Voltage detection 1
LVD1CR0.FSAMP[1:0]
The LVD1SR.DET bit is 0 if 0
(undetected) is written in the program
LVD1SR.MON
VCC
LVCMPCR.LVD1E
b1
LVD1CR0.CMPE
+
Internal reference
voltage
(for detection of
Vdet1)
Level
selection
Digital filter
Voltage
detection 1
signal
LVD1CR0.DFDIS
=0
LVD1CR0.DFDIS
=1
Fixed
period
negation
Edge
selection
circuit
LVDLVLR.LVD1LVL[4:0]
Voltage detection 1 signal is high when
the LVCMPCR.LVD1E bit is 0
(disabled)
LVD1CR0.RIE
LVD1CR0.RI
LVD1CR0.RN = 0
LVD1CR1.IDTSEL[1:0]
LVD1CR0.
RN = 1
LVD1SR.
DET
Voltage monitor 1
reset signal
(active-low)
Voltage monitor 1
non-maskable interrupt
signal
LVD1CR1.IRQSEL
Voltage monitor 1
interrupt signal
Event
Figure 8.2
Voltage monitor 1 interrupt and reset circuit block diagram
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8. Low Voltage Detection (LVD)
Voltage monitor 2
The LVD2SR.DET bit is 0 if 0
(undetected) is written by the program
Voltage detection 2
LVD2CR0.FSAMP[1:0]
LVD2SR.MON
VCC
LVCMPCR.LVD2E
b1
LVD2CR0.CMPE
+
Digital filter
Voltage
detection 2
signal
-
Internal reference
voltage
Level
(for detection of
selection
Vdet2)
LVD2CR0.DFDIS
=0
LVD2CR0.DFDIS
=1
LVD2CR0.RIE
LVD2CR0.RI
LVD2CR0.RN = 0
Fixed
period
negation
Edge
selection
circuit
LVDLVLR.LVD2LVL[2:0]
Voltage detection 2 signal is high when the
LVCMPCR.LVD2E bit is 0 (disabled)
LVD2CR0.
RN = 1
LVD2SR.
DET
LVD2CR1.IDTSEL[1:0]
Voltage monitor 2
reset signal
(active-low)
Voltage monitor 2
non-maskable
interrupt signal
LVD2CR1.IRQSEL
Voltage monitor 2
interrupt signal
Event
Figure 8.3
8.2
Voltage monitor 2 interrupt and reset circuit block diagram
Register Descriptions
8.2.1
Voltage Monitor 1 Circuit Control Register 1 (LVD1CR1)
Address(es): SYSTEM.LVD1CR1 4001 E0E0h
b7
Value after reset:
b6
b5
b4
b3
b2
—
—
—
—
—
IRQSE
L
0
0
0
0
0
0
b1
b0
IDTSEL[1:0]
0
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
IDTSEL[1:0]
Voltage Monitor 1 Interrupt
Generation Condition Select
b1 b0
R/W
b2
IRQSEL
Voltage Monitor 1 Interrupt Type
Select
0: Non-maskable interrupt
1: Maskable interrupt.*1
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Note 1.
0
0
1
1
0: When VCC Vdet1 (rise) is detected
1: When VCC < Vdet1 (fall) is detected
0: When fall and rise are detected
1: Settings prohibited.
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
When enabling maskable interrupts, do not change the value of the NMIER.LVD1EN bit in the ICU from the reset state.
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8.2.2
8. Low Voltage Detection (LVD)
Voltage Monitor 1 Circuit Status Register (LVD1SR)
Address(es): SYSTEM.LVD1SR 4001 E0E1h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MON
DET
0
0
0
0
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
DET
Voltage Monitor 1 Voltage Change
Detection Flag
0: Not detected
1: Vdet1 passage detected.
*1
R(/W)
b1
MON
Voltage Monitor 1 Signal Monitor Flag
0: VCC < Vdet1
1: VCC Vdet1 or MON is disabled.
R
b7 to b2
—
Reserved
These bits are read as 0. The write value should be
0.
R/W
Note 1.
Only 0 can be written to this bit. After writing 0 to this bit, 2 system clock cycles are required for the bit to be read as 0.
DET flag (Voltage Monitor 1 Voltage Change Detection Flag)
The DET flag is enabled when the LVCMPCR.LVD1E bit is 1 (voltage detection 1 circuit enabled) and the
LVD1CR0.CMPE bit is 1 (voltage monitor 1 circuit comparison result output enabled).
Set the DET flag to 0 after LVD1CR0.RIE is set to 0 (disabled). LVD1CR0.RIE can be set to 1 (enabled) after 2 or more
PCLKB cycles have elapsed.
MON flag (Voltage Monitor 1 Signal Monitor Flag)
The MON flag is enabled when the LVCMPCR.LVD1E bit is 1 (voltage detection 1 circuit enabled) and the
LVD1CR0.CMPE bit is 1 (voltage monitor 1 circuit comparison result output enabled).
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
8.2.3
Voltage Monitor 2 Circuit Control Register 1 (LVD2CR1)
Address(es): SYSTEM.LVD2CR1 4001 E0E2h
Value after reset:
b7
b6
b5
b4
b3
b2
—
—
—
—
—
IRQSE
L
0
0
0
0
0
0
b1
b0
IDTSEL[1:0]
0
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
IDTSEL[1:0]
Voltage Monitor 2 Interrupt
Generation Condition Select
b1 b0
R/W
b2
IRQSEL
Voltage Monitor 2 Interrupt Type
Select
0: Non-maskable interrupt
1: Maskable interrupt.*1
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Note 1.
0
0
1
1
0: When VCC Vdet2 (rise) is detected
1: When VCC < Vdet2 (fall) is detected
0: When fall and rise are detected
1: Settings prohibited.
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
When enabling maskable interrupts, do not change the value of the NMIER.LVD1EN bit in the ICU from the reset state.
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8.2.4
8. Low Voltage Detection (LVD)
Voltage Monitor 2 Circuit Status Register (LVD2SR)
Address(es): SYSTEM.LVD2SR 4001 E0E3h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MON
DET
0
0
0
0
0
0
1
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
DET
Voltage Monitor 2 Voltage Change
Detection Flag
0: Not detected
1: Vdet2 passage detected.
*1
R(/W)
b1
MON
Voltage Monitor 2 Signal Monitor
Flag
0: VCC < Vdet2
1: VCC Vdet2 or MON is disabled.
R
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Only 0 can be written to this bit. After writing 0 to this bit, it takes two system clock cycles for the bit to be read as 0.
DET flag (Voltage Monitor 2 Voltage Change Detection Flag)
The DET flag is enabled when the LVCMPCR.LVD2E bit is 1 (voltage detection 2 circuit enabled) and the
LVD2CR0.CMPE bit is 1 (voltage monitor 2 circuit comparison result output enabled).
Set the DET flag to 0 after LVD2CR0.RIE is set to 0 (disabled). LVD2CR0.RIE can be set to 1 (enabled) after 2 or more
PCLKB cycles have elapsed.
MON flag (Voltage Monitor 2 Signal Monitor Flag)
The MON flag is enabled when the LVCMPCR.LVD2E bit is 1 (voltage detection 2 circuit enabled) and the
LVD2CR0.CMPE bit is 1 (voltage monitor 2 circuit comparison result output enabled).
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
8.2.5
Voltage Monitor Circuit Control Register (LVCMPCR)
Address(es): SYSTEM.LVCMPCR 4001 E417h
b7
—
b6
LVD2E LVD1E
0
Value after reset:
b5
0
0
b4
b3
b2
b1
b0
—
—
—
—
—
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
LVD1E
Voltage Detection 1 Enable
0: Voltage detection 1 circuit disabled
1: Voltage detection 1 circuit enabled.
R/W
b6
LVD2E
Voltage Detection 2 Enable
0: Voltage detection 2 circuit disabled
1: Voltage detection 2 circuit enabled.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
LVD1E bit (Voltage Detection 1 Enable)
When using voltage detection 1 interrupt/reset or the LVD1SR.MON bit, set the LVD1E bit to 1. The voltage detection 1
circuit starts when td(E-A) elapses after the LVD1E bit value is changed from 0 to 1. When using the voltage detection 1
circuit in Deep Software Standby mode, do not set the DPSBYCR.DEEPCUT[1:0] bits to 11b.
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8. Low Voltage Detection (LVD)
LVD2E bit (Voltage Detection 2 Enable)
When using voltage detection 2 interrupt/reset or the LVD2SR.MON bit, set the LVD2E bit to 1. The voltage detection 2
circuit starts when td(E-A) elapses after the LVD2E bit value is changed from 0 to 1. When using the voltage detection 2
circuit in Deep Software Standby mode, do not set the DPSBYCR.DEEPCUT[1:0] bits to 11b.
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
8.2.6
Voltage Detection Level Select Register (LVDLVLR)
Address(es): SYSTEM.LVDLVLR 4001 E418h
b7
b6
b5
b4
b3
LVD2LVL[2:0]
1
Value after reset
1
b2
b1
b0
1
1
LVD1LVL[4:0]
1
1
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
LVD1LVL[4:0]
Voltage Detection 1 Level Select
(standard voltage during fall in voltage)
b4
R/W
b7 to b5
LVD2LVL[2:0]
Voltage Detection 2 Level Select
(standard voltage during fall in voltage)
b0
1 0 0 0 1: 2.99 V (Vdet1_1)
1 0 0 1 0: 2.92 V (Vdet1_2)
1 0 0 1 1: 2.85 V (Vdet1_3).
Other settings are prohibited.
b7
R/W
b5
1 0 1: 2.99 V (Vdet2_1)
1 1 0: 2.92 V (Vdet2_2)
1 1 1: 2.85 V (Vdet2_3).
Other settings are prohibited.
The contents of the LVDLVLR register can only be changed if the LVCMPCR.LVD1E and LVCMPCR.LVD2E bits
(voltage detection n circuit disable, n = 1, 2) are both 0. Do not set LVD detectors 1 and 2 to the same voltage detection
level.
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
8.2.7
Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0)
Address(es): SYSTEM.LVD1CR0 4001 E41Ah
b7
b6
b5
b4
b3
RN
RI
FSAMP[1:0]
—
1
0
Value after reset:
0
0
b2
b1
CMPE DFDIS
x
0
1
b0
RIE
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RIE
Voltage Monitor 1
Interrupt/Reset Enable
0: Disable
1: Enable.
R/W
b1
DFDIS
Voltage Monitor 1 Digital
Filter Disable Mode Select
0: Enable digital filter
1: Disable digital filter.
R/W
b2
CMPE
Voltage Monitor 1 Circuit
Comparison Result Output
Enable
0: Disable voltage monitor 1 circuit comparison result output
1: Enable voltage monitor 1 circuit comparison result output.
R/W
b3
—
Reserved
The read value is undefined. The write value should be 1.
R/W
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8. Low Voltage Detection (LVD)
Bit
Symbol
Bit name
Description
R/W
b5, b4
FSAMP[1:0]
Sampling Clock Select
b5 b4
R/W
b6
RI
Voltage Monitor 1 Circuit
Mode Select
0: Generate voltage monitor 1 interrupt on Vdet1 passage
1: Enable voltage monitor 1 reset when the voltage falls to and
below Vdet1.
R/W
b7
RN
Voltage Monitor 1 Reset
Negate Select
0: Negate after a stabilization time (tLVD1) when VCC > Vdet1 is
detected
1: Negate after a stabilization time (tLVD1) on assertion of the
LVD1 reset.
R/W
0
0
1
1
0: 1/2 LOCO frequency
1: 1/4 LOCO frequency
0: 1/8 LOCO frequency
1: 1/16 LOCO frequency.
RIE bit (Voltage Monitor 1 Interrupt/Reset Enable)
The RIE bit enables or disables the voltage monitor 1 interrupt/reset. Set this bit to ensure that neither a voltage monitor
1 interrupt nor a voltage monitor 1 reset is generated during programming or erasure of the flash memory.
DFDIS bit (Voltage Monitor 1 Digital Filter Disable Mode Select)
The DFDIS bit enables the digital filter circuit. Set the LOCOCR.LCSTP bit to 0 (the LOCO operates) if this bit is 0
(enabled). Set the bit to 1 (disabled) when using the voltage monitor 1 circuit in Software Standby or Deep Software
Standby mode.
FSAMP[1:0] bits (Sampling Clock Select)
Only change the FSAMP[1:0] bits when the LVD1CR0.DFDIS bit is 1 (digital filter circuit disabled) but not when
LVD1CR0.DFDIS is 0 (digital filter circuit enabled).
RI bit (Voltage Monitor 1 Circuit Mode Select)
When the RI bit is 1 (voltage monitor 1 reset selected) or when the LVD2CR0.RI bit is 1 (voltage monitor 2 reset
selected), transition to Software Standby mode can be made but not to Deep Software Standby mode. To enter Deep
Software Standby mode, set the RI bit to 0 (voltage monitor 1 interrupt selected) and the LVD2CR0.RI bit to 0 (voltage
monitor 2 interrupt selected).
RN bit (Voltage Monitor 1 Reset Negate Select)
If the RN bit is to be set to 1 (negation follows a stabilization time on assertion of the LVD1 reset signal), set the
LOCOCR.LCSTP bit to 0 (the LOCO operates). In addition, for a transition to Software Standby or Deep Software
Standby, the only possible value for the RN bit is 0 (negation follows a stabilization time when VCC > Vdet1 is detected).
Do not set the RN bit to 1 when this is the case.
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
8.2.8
Voltage Monitor 2 Circuit Control Register 0 (LVD2CR0)
Address(es): SYSTEM.LVD2CR0 4001 E41Bh
b7
b6
b5
b4
b3
RN
RI
FSAMP[1:0]
—
1
0
Value after reset:
0
0
x
b2
b1
CMPE DFDIS
0
1
b0
RIE
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RIE
Voltage Monitor 2 Interrupt/Reset
Enable
0: Disable
1: Enable.
R/W
b1
DFDIS
Voltage Monitor 2 Digital Filter
Disable Mode Select
0: Enable digital filter
1: Disable digital filter.
R/W
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8. Low Voltage Detection (LVD)
Bit
Symbol
Bit name
Description
R/W
b2
CMPE
Voltage Monitor 2 Circuit
Comparison Result Output Enable
0: Disable voltage monitor 2 circuit comparison result
output
1: Enable voltage monitor 2 circuit comparison result
output.
R/W
b3
—
Reserved
The read value is undefined. The write value should be 1.
R/W
b5, b4
FSAMP[1:0]
Sampling Clock Select
b5 b4
R/W
b6
RI
Voltage Monitor 2 Circuit Mode
Select
0: Generate voltage monitor 2 interrupt on Vdet2 passage
1: Enable voltage monitor 2 reset when the voltage falls to
and below Vdet2.
R/W
b7
RN
Voltage Monitor 2 Reset Negate
Select
0: Negate after a stabilization time (tLVD2) when VCC >
Vdet2 is detected
1: Negate after a stabilization time (tLVD2) on assertion of
the LVD2 reset.
R/W
0
0
1
1
0: 1/2 LOCO frequency
1: 1/4 LOCO frequency
0: 1/8 LOCO frequency
1: 1/16 LOCO frequency.
RIE bit (Voltage Monitor 2 Interrupt/Reset Enable)
The RIE bit enables or disables voltage monitor 2 interrupt/reset. Set this bit to ensure that neither a voltage monitor 2
interrupt nor a voltage monitor 2 reset is generated during programming or erasure of the flash memory.
DFDIS bit (Voltage Monitor 2 Digital Filter Disable Mode Select)
The DFDIS bit enables the digital filter circuit. Set the LOCOCR.LCSTP bit to 0 (the LOCO operates) if this bit is 0
(enabled). Set the bit to 1 (disabled) when using the voltage monitor 2 circuit in Software Standby or Deep Software
Standby mode.
FSAMP[1:0] bits (Sampling Clock Select)
Only change the FSAMP[1:0] bits when the LVD2CR0.DFDIS bit is 1 (digital filter circuit disabled), but not when
LVD2CR0.DFDIS is 0 (digital filter circuit enabled).
RI bit (Voltage Monitor 2 Circuit Mode Select)
When the RI bit is 1 (voltage monitor 2 reset selected) or when the LVD1CR0.RI bit is 1 (voltage monitor 1 reset
selected), transition to Software Standby mode can be made but not to Deep Software Standby mode. To enter Deep
Software Standby mode, set the RI bit to 0 (voltage monitor 2 interrupt selected) and the LVD1CR0.RI bit to 0 (voltage
monitor 1 interrupt selected).
RN bit (Voltage Monitor 2 Reset Negate Select)
If the RN bit is set to 1 (negation follows a stabilization time on assertion of the LVD2 reset signal), set the
LOCOCR.LCSTP bit to 0 (the LOCO operates). Additionally, for a transition to Software Standby or Deep Software
Standby mode, the only possible value for the RN bit is 0 (negation follows a stabilization time when VCC > Vdet2 is
detected). Do not set the RN bit to 1 (negation follows a stabilization time after assertion of the LVD2 reset signal) when
this is the case.
Note:
8.3
8.3.1
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
VCC Input Voltage Monitor
Monitoring Vdet0
The comparison results from voltage monitor 0 are not available for reading.
8.3.2
Monitoring Vdet1
Table 8.2 shows the procedure to set up monitoring against Vdet1. After the settings are complete, the comparison results
from voltage monitor 1 can be monitored with the LVD1SR.MON flag.
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Table 8.2
8. Low Voltage Detection (LVD)
Procedure to set up monitoring against Vdet1
Step
Monitoring the comparison results from voltage monitor 1
Setting the voltage
detection 1 circuit
Setting the digital
filter*2
Enabling output
Note 1.
Note 2.
1
Set LVCMPCR.LVD1E = 0 to disable voltage detection 1 before writing to LVDLVLR register.
2
Select the detection voltage in the LVDLVLR.LVD1LVL[4:0] bits.
3
Set LVCMPCR.LVD1E = 1 to enable voltage detection 1.
4
Wait for at least td(E-A) for the LVD operation stabilization time after LVD is enabled.*1
5
Select the sampling clock for the digital filter in the LVD1CR0.FSAMP[1:0] bits.
6
Set LVD1CR0.DFDIS = 0 to enable the digital filter.
7
Wait for at least 2n + 3 cycles of the LOCO, where n = 2, 4, 8, 16 and the sampling clock for the digital
filter is the LOCO frequency-divided by n.
8
Set LVD1CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 1.
Steps 5 to 7 can be performed during the wait time in step 4. For details on td(E-A), see section 55, Electrical Characteristics.
Steps 5 to 7 are not required if the digital filter is not in use.
8.3.3
Monitoring Vdet2
Table 8.3 shows the procedure to set up monitoring against Vdet2. After the settings are complete, the comparison results
from voltage monitor 2 can be monitored with the LVD2SR.MON flag.
Table 8.3
Procedure to set up monitoring against Vdet2
Step
Monitoring the comparison results by voltage monitor 2
Setting up the voltage
detection 2 circuit
Setting up the digital
filter*2
Enabling output
Note 1.
Note 2.
8.4
1
Set LVCMPCR.LVD2E = 0 to disable voltage detection 2 before writing to the LVDLVLR register.
2
Select the detection voltage in the LVDLVLR.LVD2LVL[2:0] bits.
3
Set LVCMPCR.LVD2E = 1 to enable the voltage detection 2 circuit.
4
Wait for at least td(E-A) for the LVD operation stabilization time after LVD is enabled.*1
5
Select the sampling clock for the digital filter in the LVD2CR0.FSAMP[1:0] bits.
6
Set LVD2CR0.DFDIS = 0 to enable the digital filter.
7
Wait for at least 2n + 3 LOCO cycles, where n = 2, 4, 8, 16 and the sampling clock for the digital filter is
the LOCO frequency-divided by n.
8
Set LVD2CR0.CMPE = 1 to enable output of the comparison results by voltage monitor 2.
Steps 5 to 7 can be performed during the wait time in step 4. For details on td(E-A), see section 55, Electrical Characteristics.
Steps 5 to 7 are not required if the digital filter is not in use.
Reset from Voltage Monitor 0
When using the reset from voltage monitor 0, clear the OFS1.LVDAS bit to 0 to enable the voltage monitor 0 reset after
a reset. However, at boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Figure 8.4 shows an example of operations for a voltage monitor 0 reset.
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8. Low Voltage Detection (LVD)
*3
Vdet0*1
VPOR*1
External voltage VCC
Power-on reset state
Voltage-monitor 0 reset state
RES pin
POR detection signal
(active-low)
Set by OFS1.LVDAS
LVD0 enable/disable
signal (active-low)
Voltage detection 0
signal (active-low)
Internal reset signal
(active-low)
tPOR*2
RSTSR0.PORF
tLVD0*2
RES pin reset
RSTSR0.LVD0RF
Note:
Note 1.
For details of the electrical characteristics, see section 55, Electrical Characteristics.
VPOR indicates the detection level for a power-on reset and Vdet0 indicates the detection level for a voltage monitor 0
reset.
tPOR indicates the period of a power-on reset and tLVD0 indicates the period of a voltage monitor 0 reset.
At power-on, raise VCC to the minimum guaranteed voltage before releasing the POR reset.
Note 2.
Note 3.
Figure 8.4
8.5
Example of voltage monitor 0 reset operation
Interrupt and Reset from Voltage Monitor 1
An interrupt or reset can be generated in response to the comparison results from the voltage monitor 1 circuit.
Table 8.4 shows the procedure for setting bits related to the voltage monitor 1 interrupt and reset so that voltage
monitoring operates. Table 8.5 shows the procedure for setting bits related to the voltage monitor 1 interrupt and reset so
that voltage monitoring stops. Figure 8.5 shows an example of operations for a voltage monitor 1 interrupt. For the
operation of the voltage monitor 1 reset, see Figure 6.2 in section 6, Resets.
When using the voltage monitor 1 circuit in Software Standby or Deep Software Standby, set the circuit with the
following procedures.
(1)
Settings in Software Standby mode
Disable the digital filter (LVD1CR0.DFDIS = 1)
When VCC > Vdet1 is detected, negate the voltage monitor 1 reset signal (LVD1CR0.RN = 0) following a
stabilization time.
(2)
Settings in Deep Software Standby mode
Disable the digital filter (LVD1CR0.DFDIS = 1)
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8. Low Voltage Detection (LVD)
Enable voltage monitor 1 interrupts (LVD1CR0.RI = 0). If the voltage monitor 1 reset is enabled (LVD1CR0.RI =
1), a transition to Deep Software Standby mode is not possible, and the operation transitions to Software Standby
mode instead
When the DPSBYCR.DEEPCUT[1:0] bits are 11b, the voltage monitor 1 circuit stops. To use the voltage monitor 1
circuit in Deep Software Standby mode, set the DPSBYCR.DEEPCUT[1:0] bits to a value other than 11b.
Table 8.4
Procedure to set bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so that
voltage monitoring operates
Voltage monitor 1 interrupt
(voltage monitor 1 ELC event output)
Step
Setting up the voltage
detection 1 circuit
Setting up the digital
filter *2
Setting up the voltage
monitor 1 interrupt or
reset
Enabling output
Note 1.
Note 2.
Note 3.
Note 4.
Voltage monitor 1 reset
1
Set LVCMPCR.LVD1E = 0 to disable voltage detection 1 before writing to the LVDLVLR register.
2
Select the detection voltage in the LVDLVLR.LVD1LVL[3:0] bits.
3
Set LVCMPCR.LVD1E = 1 to enable the voltage detection 1 circuit.
4
Wait for at least td(E-A) for the LVD operation stabilization time after LVD is enabled.*1
5
Select the sampling clock for the digital filter in the LVD1CR0.FSAMP[1:0] bits.
6
Set LVD1CR0.DFDIS = 0 to enable the digital filter.
7
Wait for at least 2n + 3 LOCO cycles, where n = 2, 4, 8, 16 and the sampling clock for the digital filter is
the LOCO frequency-divided by n.*4
8
Set LVD1CR0.RI = 0 to select the voltage monitor
1 interrupt.
Set LVD1CR0.RI = 1 to select the voltage
monitor 1 reset
Select the type of reset negation in the
LVD1CR0.RN bit.
9
Select the interrupt request timing in the
LVD1CR1.IDTSEL[1:0] bits
Select the interrupt type in the
LVD1CR1.IRQSEL bit.
—
10
Set LVD1SR.DET = 0.
11
Set LVD1CR0.RIE = 1 to enable the voltage monitor 1 interrupt or reset.*3
12
Set LVD1CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 1.
Steps 5 to 11 can be performed during the wait time in step 4. For details on td(E-A), see section 55, Electrical Characteristics.
Steps 5 to 7 are not required if the digital filter is not in use.
Step 11 is not required if only the ELC event signal is to be output.
Steps 8 to 11 can be performed during the wait time in step 7.
Table 8.5
Procedure to set bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so that
voltage monitoring stops
Step
Voltage monitor 1 interrupt (voltage monitor 1 ELC event output), voltage monitor 1 reset
Settings to stop
enabling output
1
Set LVD1CR0.CMPE = 0 to disable output of the comparison results by voltage monitor 1.
2
Wait for at least 2n + 3 LOCO cycles, where n = 2, 4, 8, 16 and the sampling clock for the digital filter is
the LOCO frequency-divided by n.*1
3
Set LVD1CR0.RIE = 0 to disable the voltage monitor 1 interrupt or reset.*2
Stopping the digital
filter
4
Set LVD1CR0.DFDIS = 1 to disable the digital filter.*1, *3
Stopping the voltage
detection 1 circuit
5
Set LVCMPCR.LVD1E = 0 to disable the voltage detection 1 circuit.
Note 1.
Note 2.
Note 3.
Steps 2 and 4 are not required if the digital filter is not in use.
Step 3 is not required if only the ELC event signal is to be output.
To disable the digital filter from its enabled state and then re-enable it, disable it and wait for at least 2 LOCO clock cycles
before re-enabling it.
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8. Low Voltage Detection (LVD)
If the voltage monitor 1 interrupt or reset setting is to be made again after it is used and stopped once, omit the following
steps in the procedures for stopping and setting, depending on the conditions:
Setting or stopping the voltage detection 1 circuit is not required if the settings for the circuit do not change
Setting or stopping the digital filter is not required if the settings for the digital filter do not change
Setting the voltage monitor 1 interrupt or reset is not required if the settings for the voltage monitor 1 interrupt or
reset do not change.
VCC
Vdet1
Lower limit on VCC voltage (VCCmin)*1
LVD1SR.MON bit when LVD1CR0.DFDIS bit is
set to 0 (digital filter enabled)
1n+2 to 2n+3 cycles of
the LOCO
LVD1CR0.DFDIS bit is set to 0
(digital filter enabled) and
LVD1CR1.IDTSEL[1:0] bits are set to
10b (when fall and rise are detected)
1n+2 to 2n+3 cycles of
the LOCO
LVD1SR.DET bit
Set to 0 by software
Voltage monitor 1
interrupt request
Set to 0 by software
LVD1CR0.DFDIS bit is set to 0
(digital filter enabled),
LVD1CR1.IDTSEL[1:0] bits are set to
00b (when rise is detected)
LVD1SR.DET bit
LVD1CR0.DFDIS bit is set to 0
(digital filter enabled),
LVD1CR1.IDTSEL[1:0] bits are set
to 01b (when fall is detected)
LVD1SR.DET bit
Voltage monitor 1
interrupt request
Set to 0 by software
Voltage monitor 1
interrupt request
LVD1SR.MON bit when LVD1CR0.DFDIS bit is
set to 1 (digital filter disabled)
Set to 0 by software
LVD1CR0.DFDIS bit is set to 1
(digital filter disabled) and
LVD1CR1.IDTSEL[1:0] bits are set
to 10b (when fall and rise are
detected)
LVD1SR.DET bit
Voltage monitor 1
interrupt request
Set to 0 by software
LVD1CR0.DFDIS bit is set to 1
(digital filter disabled),
LVD1CR1.IDTSEL[1:0] bits are set
to 00b (when rise is detected)
LVD1SR.DET bit
LVD1CR0.DFDIS bit is set to 1
(digital filter disabled),
LVD1CR1.IDTSEL[1:0] bits are set
to 01b (when fall is detected)
LVD1SR.DET bit
Voltage monitor 1
interrupt request
Set to 0 by software
Voltage monitor 1
interrupt request
n: Frequency of the sampling clock for the digital filter is the LOCO frequency divided by n
Note 1. When the voltage monitor 0 reset is not in use, VCC VCCmin.
Figure 8.5
Voltage monitor 1 interrupt operation example
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8.6
8. Low Voltage Detection (LVD)
Interrupt and Reset from Voltage Monitor 2
An interrupt or reset can be generated in response to the comparison results from the voltage monitor 2 circuit.
Table 8.6 shows the procedure for setting bits related to the voltage monitor 2 interrupt and reset so that voltage
monitoring operates. Table 8.7 shows the procedure for setting bits related to the voltage monitor 2 interrupt and reset so
that voltage monitoring stops. Figure 8.6 shows an example of operations for a voltage monitor 2 interrupt. For the
operation of the voltage monitor 2 reset, see Figure 6.2 in section 6, Resets.
When using the voltage monitor 2 circuit in Software Standby or Deep Software Standby, set the circuit with the
following procedures.
(1)
Settings in Software Standby mode
Disable the digital filter (LVD2CR0.DFDIS = 1)
When VCC > Vdet2 is detected, negate the voltage monitor 2 reset signal (LVD2CR0.RN = 0) following the
stabilization time.
(2)
Settings in Deep Software Standby mode
Disable the digital filter (LVD2CR0.DFDIS = 1)
Enable voltage monitor 2 interrupts (LVD2CR0.RI = 0). If the voltage monitor 2 reset is enabled (LVD2CR0.RI =
1), a transition to Deep Software Standby mode is not possible, and the operation transitions to Software Standby
mode instead.
When the DPSBYCR.DEEPCUT[1:0] bits are 11b, the voltage monitor 2 circuit stops. To use the voltage monitor 2
circuit in Deep Software Standby mode, set the DPSBYCR.DEEPCUT[1:0] bits to a value other than 11b.
Table 8.6
Procedures to set bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that
voltage monitoring operates
Voltage monitor 2 interrupt
(voltage monitor 2 ELC event output)
Step
Setting up the voltage
detection 2 circuit
Setting up the digital
filter *2
Setting up the voltage
monitor 2 interrupt or
reset
Enabling output
Note 1.
Note 2.
Note 3.
Note 4.
Voltage monitor 2 reset
1
Set LVCMPCR.LVD2E = 0 to disable voltage detection 2 before writing to the LVDLVLR register.
2
Select the detection voltage in the LVDLVLR.LVD2LVL[2:0] bits.
3
Set LVCMPCR.LVD2E = 1 to enable the voltage detection 2 circuit.
4
Wait for at least td(E-A) for the LVD operation stabilization time after LVD is enabled.*1
5
Select the sampling clock for the digital filter in the LVD2CR0.FSAMP[1:0] bits.
6
Set LVD2CR0.DFDIS = 0 to enable the digital filter.
7
Wait for at least 2n + 3 LOCO cycles, where n = 2, 4, 8, 16, and the sampling clock for the digital filter is
the LOCO frequency-divided by n.*4
8
Set LVD2CR0.RI = 0 to select the voltage monitor
2 interrupt.
Set LVD2CR0.RI = 1 to select the voltage
monitor 2 reset
Select the type of reset negation in the
LVD2CR0.RN bit.
9
Select the interrupt request timing in the
LVD2CR1.IDTSEL[1:0] bits
Select the interrupt type in the
LVD2CR1.IRQSEL bit.
—
10
Set LVD2SR.DET = 0.
11
Set LVD2CR0.RIE = 1 to enable the voltage monitor 2 interrupt or reset.*3
12
Set LVD2CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 2.
Steps 5 to 11 can be performed during the wait time in step 4. For details on td(E-A), see section 55, Electrical Characteristics.
Steps 5 to 7 are not required if the digital filter is not in use.
Step 11 is not required if only the ELC event signal is to be output.
Steps 8 to 10 can be performed during the wait time in step 7.
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Table 8.7
8. Low Voltage Detection (LVD)
Procedure to set bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that
voltage monitoring stops
Step
Voltage monitor 2 interrupt (voltage monitor 2 ELC event output), voltage monitor 2 reset
Settings to stop
enabling output
1
Set LVD2CR0.CMPE = 0 to disable output of the comparison results by voltage monitor 2.
2
Wait for at least 2n + 3 LOCO cycles, where n = 2, 4, 8, 16, and the sampling clock for the digital filter is
the LOCO frequency-divided by n.*1
3
Set LVD2CR0.RIE = 0 to disable the voltage monitor 2 interrupt or reset.*2
Stopping the digital
filter
4
Set LVD2CR0.DFDIS = 1 to disable the digital filter.*1, *3
Stopping the voltage
detection 1 circuit
5
Set LVCMPCR.LVD2E = 0 to disable the voltage detection 2 circuit.
Note 1.
Note 2.
Note 3.
Steps 2 and 4 are not required if the digital filter is not in use.
Step 3 is not required if only the ELC event signal is to be output.
To disable the digital filter from its enabled state and then re-enable it, disable it and wait for at least 2 LOCO cycles before reenabling it.
If the voltage monitor 2 interrupt or reset setting is to be made again after it is used and stopped once, omit the following
steps in the procedures for stopping and setting, depending on the conditions:
Setting or stopping the voltage detection 2 circuit is not required if the settings for the circuit do not change
Setting or stopping the digital filter is not required if the settings for the digital filter do not change
Setting the voltage monitor 2 interrupt or reset is not required if the settings for the voltage monitor 2 interrupt or
voltage monitor 2 reset do not change.
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8. Low Voltage Detection (LVD)
VCC
Vdet2
Lower limit on VCC voltage
(VCCmin)*1
LVD2SR.MON bit when LVD2CR0.DFDIS bit is
set to 0 (digital filter enabled)
1n+2 to 2n+3 cycles of
the LOCO
1n+2 to 2n+3 cycles of
the LOCO
LVD2CR0.DFDIS bit is set to 0
(digital filter enabled) and
LVD2CR1.IDTSEL[1:0] bits are set to
10b (when fall and rise are detected)
LVD2SR.DET bit
Set to 0 by software
Voltage monitor 2
interrupt request
Set to 0 by software
LVD2CR0.DFDIS bit is set to 0
(digital filter enabled),
LVD2CR1.IDTSEL[1:0] bits are set
to 00b (when rise is detected)
LVD2SR.DET bit
LVD2CR0.DFDIS bit is set to 0
(digital filter enabled),
LVD2CR1.IDTSEL[1:0] bits are set
to 01b (when fall is detected)
LVD2SR.DET bit
Voltage monitor 2
interrupt request
Set to 0 by software
Voltage monitor 2
interrupt request
LVD2SR.MON bit when LVD2CR0.DFDIS bit is
set to 1 (digital filter disabled)
Set to 0 by software
LVD2CR0.DFDIS bit is set to 1,
LVD2CR1.IDTSEL[1:0] bits are set
to 10b (when fall and rise are
detected)
LVD2SR.DET bit
Voltage monitor 2
interrupt request
Set to 0 by software
LVD2CR0.DFDIS bit is set to 1
(digital filter disabled),
LVD2CR1.IDTSEL[1:0] bits are set
to 00b (when rise is detected)
LVD2SR.DET bit
LVD2CR0.DFDIS bit is set to 1
(digital filter disabled),
LVD2CR1.IDTSEL[1:0] bits are set
to 01b (when fall is detected)
LVD2SR.DET bit
Voltage monitor 2
interrupt request
Set to 0 by software
Voltage monitor 2
interrupt request
n: Frequency of the sampling clock for the digital filter is the LOCO frequency divided by n
Note 1. When the voltage monitor 0 reset is not in use, VCC VCCmin.
Figure 8.6
8.7
Example of voltage monitor 2 interrupt operation
Event Link Output
The LVD can output the event signals to the Event Link Controller (ELC).
(1)
Vdet1 Crossing Detection Event
The LVD outputs the event signal when it detects that the voltage has passed the Vdet1 voltage while both the voltage
detection 1 circuit and the voltage monitor 1 circuit comparison result output are enabled.
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(2)
8. Low Voltage Detection (LVD)
Vdet2 Crossing Detection Event
The LVD outputs the event signal when it detects that the voltage has passed the Vdet2 voltage while both the voltage
detection 2 circuit and the voltage monitor 2 circuit comparison result output are enabled.
When enabling the event link output function of the LVD, you must enable the LVD before enabling the LVD event link
function of the ELC. To stop the event link output function of the LVD, you must stop the LVD before disabling the LVD
event link function of the ELC.
8.7.1
Interrupt Handling and Event Linking
The LVD provides bits to separately enable or disable the voltage monitor 1 and 2 interrupts. When an interrupt source is
generated and the interrupt is enabled by the interrupt enable bit, the interrupt signal (LVD1CR0.RIE or LVD2CR0.RIE)
is output to the CPU.
On the other hand, as soon as an interrupt source is generated, an event link signal is output as the event signal to the
other module through the ELC, regardless of the state of the interrupt enable bit.
It is possible to output voltage monitor 1 and 2 interrupts in Software Standby and Deep Software Standby modes. The
event signals for the ELC in Software Standby and Deep Software Standby modes are output as follows:
When a Vdet1 or Vdet2 passage event is detected in Software Standby mode, event signals are not generated for the
ELC because the clock is not supplied in Software Standby mode. Because the Vdet1 and Vdet2 passage detection
flags are saved, when the clock supply resumes after returning from Software Standby mode, the event signals for
the ELC are output based on the state of the Vdet1 and Vdet2 detection flags.
When a Vdet1 or Vdet2 passage events is detected in Deep Software Standby mode, event signals are not generated
for the ELC.
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9. Clock Generation Circuit
9.
Clock Generation Circuit
9.1
Overview
The MCU provides a clock generation circuit. Table 9.1 and Table 9.2 list the clock generation circuit specifications,
Figure 9.1 shows a block diagram, and Table 9.3 lists the I/O pins.
Table 9.1
Clock generation circuit specifications for the clock sources
Clock source
Parameter
Specifications
Main clock oscillator
(MOSC)
Resonator frequency
8 to 24 MHz
USB boot mode: 8, 10, 12, 15, 16, 20, 24
MHz
External clock input frequency
Up to 24 MHz
External resonator or additional circuit: ceramic resonator, crystal
Available
Connection pins EXTAL, XTAL
Drive capability switching
Oscillation stop detection function
Sub-clock oscillator
(SOSC)
Resonator frequency
32.768 kHz
External resonator or additional circuit: crystal resonator
Available
Connection pins: XCIN, XCOUT
Drive capability switching
PLL circuit
Input clock source
MOSC, HOCO
Input pulse frequency division ratio
Selectable from 1, 2, and 3
Input frequency
8 to 24 MHz
Frequency multiplication ratio
Selectable from 10 to 30 (0.5 steps)
PLL output frequency
120 to 240 MHz
High-speed on-chip
oscillator (HOCO)
Oscillation frequency
16, 18, 20 MHz
User trimming
Available
Middle-speed
on-chip oscillator
(MOCO)
Oscillation frequency
8 MHz
User trimming
Available
Low-speed on-chip
oscillator (LOCO)
Oscillation frequency
32.768 kHz
User trimming
Available
IWDT-dedicated onchip oscillator
(IWDTLOCO)
Oscillation frequency
15 kHz
External clock input
for JTAG (TCK)
Input clock frequency
Up to 25 MHz
External clock input
for SWD (SWCLK)
Input clock frequency
Up to 25 MHz
Table 9.2
Clock generation circuit specifications for the internal clocks (1 of 2)
Parameter
Clock sources
Clock supply
System clock (ICLK)
MOSC, SOSC, HOCO,
MOCO, LOCO, PLL
CPU, DTC, DMAC, Flash, SRAM Up to 120 MHz
Division ratios: 1, 2, 4, 8, 16, 32,
64
Peripheral module clock A
(PCLKA)
MOSC, SOSC, HOCO,
MOCO, LOCO, PLL
Peripheral modules (ETHERC,
EDMAC, QSPI, SPI, SCI, SCE7,
SDHI, CRC, IrDA, GPT busclock)
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Specifications
Up to 120 MHz*2
Division ratios: 1, 2, 4, 8, 16, 32,
64
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Table 9.2
9. Clock Generation Circuit
Clock generation circuit specifications for the internal clocks (2 of 2)
Parameter
Clock sources
Clock supply
Specifications
Peripheral module clock B
(PCLKB)
MOSC, SOSC, HOCO,
MOCO, LOCO, PLL
Peripheral modules (IIC, SSIE,
SRC, DOC, CAC, CAN, DAC12,
POEG, CTSU, AGT, Standby
SRAM, ELC, I/O ports, RTC,
WDT, IWDT, ADC12, KINT,
USBFS, ACMPHS, TSN, PDC)
Up to 60 MHz
Division ratios: 1, 2, 4, 8, 16, 32,
64
Peripheral module clock C
(PCLKC)
MOSC, SOSC, HOCO,
MOCO, LOCO, PLL
Peripheral module (ADC12
conversion clock)
Up to 60 MHz
Division ratios: 1, 2, 4, 8, 16, 32,
64
Peripheral module clock D
(PCLKD)
MOSC, SOSC, HOCO,
MOCO, LOCO, PLL
Peripheral module (GPT countclock)
Up to 120 MHz
Division ratios: 1, 2, 4, 8, 16, 32,
64
Flash interface clock (FCLK)
MOSC, SOSC, HOCO,
MOCO, LOCO, PLL
Flash interface
4 to 60 MHz (P/E)
Up to 60 MHz (read) *1
Division ratios: 1, 2, 4, 8, 16, 32,
64
External bus clock (BCLK)
MOSC, SOSC, HOCO,
MOCO, LOCO, PLL
External bus
Up to 120 MHz
Division ratios: 1, 2, 4, 8, 16, 32,
64
EBCLK pin output (EBCLK)
BCLK or 1/2 BCLK
EBCLK pin
Up to 60 MHz
Division ratios: 1, 2
SDCLK pin output (SDCLK)
BCLK
SDCLK pin
Up to 120 MHz
USB clock (UCLK)
PLL
USB
48 MHz
Division ratios: 3, 4, 5
CAN clock (CANMCLK)
MOSC
CAN
8 to 24 MHz
AGT clock (AGTSCLK,
AGTLCLK)
SOSC, LOCO
AGT
32.768 kHz
CAC main clock (CACMCLK)
MOSC
CAC
Up to 24 MHz
CAC sub-clock (CACSCLK)
SOSC
CAC
32.768 kHz
CAC LOCO clock (CACLCLK)
LOCO
CAC
32.768 kHz
CAC MOCO clock
(CACMOCLK)
MOCO
CAC
8 MHz
CAC HOCO clock
(CACHCLK)
HOCO
CAC
16, 18, 20 MHz
CAC IWDTLOCO clock
(CACILCLK)
IWDTLOCO
CAC
15 kHz
RTC clock (RTCSCLK,
RTCLCLK)
SOSC, LOCO
RTC
32.768 kHz
IWDT clock (IWDTCLK)
IWDTLOCO
IWDT
15 kHz
SysTick timer clock
(SYSTICCLK)
LOCO
SysTick timer
32.768 kHz
JTAG clock (JTAGTCK)
TCK pin
JTAG
Up to 25 MHz
Clock and buzzer output
(CLKOUT)
MOSC, SOSC, LOCO,
MOCO, HOCO
CLKOUT pin
Up to 24 MHz
Division ratios: 1, 2, 4, 8, 16, 32,
64, 128
Serial wire clock (SWCLK)
SWCLK pin
OCD
Up to 25 MHz
Trace clock (TRCLK)
MOSC, SOSC, HOCO,
MOCO, LOCO, PLL
CPU-OCD
Up to 60 MHz
Division ratios: 1, 2, 4
TCLK pin output (TCLK)
1/2 TRCLK
TCLK pin
Up to 30 MHz
Note:
Restrictions on the clock frequency settings: ICLK ≥ PCLKA ≥ PCLKB, PCLKD ≥ PCLKA ≥ PCLKB
Restrictions on the clock frequency ratio (N: integer, and up to 64):
ICLK:FCLK = N:1, ICLK:BCLK = N:1, ICLK:PCLKA = N:1, ICLK:PCLKB = N:1
ICLK:PCLKC = N:1 or 1:N, ICLK:PCLKD = N:1 or 1:N
If the A/D converter is enabled, the clock frequency ratio is constrained as follows:
PCLKB:PCLKC = 1:1 or 1:2 or 1:4 or 2:1 or 4:1 or 8:1.
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Note:
Note:
Note 1.
Note 2.
9. Clock Generation Circuit
Clocks have a permissible frequency range. See Table 9.2.
Flash memory and SRAM also have a permissible operating frequency range in each wait cycle setting. See section 51, SRAM,
and section 53, Flash Memory.
Those clock frequency ranges must be satisfied even when the HOCO has its maximum or minimum frequency. See section
55, Electrical Characteristics.
If the PLL reference clock source is HOCO, the PLL multiplication setting must be set to 120 - 240 MHz in consideration of
HOCO frequency (minimum/maximum).
The minimum FCLK frequency is 4 MHz in Programming/Erasure (P/E) mode.
When using ETHERC, the PCLKA frequency is in the range 12.5 MHz ≤ PCLKA ≤ 120 MHz.
When using ETHERC and PCLKA = ICLK.
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9. Clock Generation Circuit
Frequency
divider
PLL
Circuit
Selector
SCKSCR
Oscillation
stop detection
circuit
Main clock
Oscillator
EXTAL
XCIN
Sub-clock
oscillator
XCOUT
Oscillation
wait control
Main clock
Selector
XTAL
CKSEL[2:0]
Frequency
divider
1/1
1/2
1/4
1/8
1/16
1/32
1/64
Oscillation
wait control
Sub-clock
SCKDIVCR
Selector
PLLCCR
SCKDIVCR
1/3
1/5
Selector
Selector
Selector
PLLMUL[5:0]
PLLCCR
Selector
PLIDIV[1:0]
PLLCCR
Selector
SCKDIVCR
PLSRCSEL
FCK[2:0]
Flash interface clock (FCLK)
To flash interface
ICK[2:0]
System clock(ICLK)
To CPU, DMAC, Flash, and
SRAM
PCKA[2:0]
PCKB[2:0]
PCKC[2:0]
PCKD[2:0]
Peripheral module clock
PCLKA (high-speed peripheral bus)
PCLKB (peripheral bus)
PCLKC (ADC)
PCLKD (GPT)
To FLL
BCKCR BCLKDIV
Selector
1/2
1
High-speed on-chip
oscillator
16, 18, 20 MHz
Middle-speed
on-chip
oscillator
8 MHz
High-speed
clock
Oscillation
wait control
TRCKCR
Middle-speed
clock
Selector
*
Selector
SCKDIVCR BCK[2:0]
EBCLK pin
External bus clock (BCLK)
To external bus controller
SDRAM clock (SDCLK)
To SDRAM pin
TRCK[3:0]
Trace clock (TRCLK)
To Cortex-M4 debugger
Selector
SCKDIVCR2 UCLK[2:0]
USB clock (UCLK)
To USB
Systic timer (SYSTICCLK)
Low-speed on-chip
oscillator
Low-speed
clock
AGT clock (AGTSCLK)
To AGT (AGTLCLK)
32.768 kHz
CKODIV[2:0]
CKOCR
CKOSEL[2:0]
Selector
CKOCR
IWDT dedicated
on-chip oscillator
15 kHz
IWDT
low-speed clock
Frequency
divider
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Clock/buzzer output (CLKOUT)
To CLKOUT pin
CAN clock (CANMCLK)
To CAN
IWDT clock (IWDTCLK)
To IWDT
(CACILCLK)
(CACLCLK)
CAC clock (CACMOCLK)
(CACHCLK)
To CAC
(CACSCLK)
(CACMCLK)
RTC clock (RTCLCLK)
To RTC (RTCSCLK)
JTAG clock (JTAGTCK)
To TAP controller
Serial wire clock (SWCLK)
To TAP controller
TCK/SWCLK pin
Note 1. HOCO has FLL.
Figure 9.1
Clock generation circuit block diagram
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Table 9.3
9. Clock Generation Circuit
Clock Generation Circuit I/O pins
Pin name
I/O
Description
XTAL
Output
EXTAL
Input
Crystal resonator connections
The EXTAL pin can also be used to input an external clock. For details, see section
9.3.2, External Clock Input.
XCIN
Input
XCOUT
Output
TCK/SWCLK
Input
JTAG clock input
EBCLK
Output
External bus clock (EBCLK) supply for external devices
SDCLK
Output
SDRAM clock (SDCLK) supply for external devices
CLKOUT
Output
CLKOUT and BUZZER clock output
9.2
32.768-kHz crystal resonator connection
Register Descriptions
9.2.1
System Clock Division Control Register (SCKDIVCR)
Address(es): SYSTEM.SCKDIVCR 4001 E020h
b31
b30
—
Value after reset:
b28
FCK[2:0]
b27
b26
—
b25
b24
ICK[2:0]
b23
b22
b21
b20
b19
—
—
—
—
—
b18
b17
b16
BCK[2:0]
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
Value after reset:
b29
0
PCKA[2:0]
0
1
—
0
0
PCKB[2:0]
0
1
Bit
Symbol
Bit name
b2 to b0
PCKD[2:0]
Peripheral Module Clock D
(PCLKD) Select*4
b3
—
Reserved
b6 to b4
PCKC[2:0]
Peripheral Module Clock C
(PCLKC) Select*4
b7
—
Reserved
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—
0
PCKC[2:0]
0
0
1
—
0
0
PCKD[2:0]
0
Description
b2
0
R/W
R/W
b0
0 0 0: ×1/1
0 0 1: ×1/2
0 1 0: ×1/4
0 1 1: ×1/8
1 0 0: ×1/16
1 0 1: ×1/32
1 1 0: ×1/64.
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
b6
1
R/W
R/W
b4
0 0 0: ×1/1
0 0 1: ×1/2
0 1 0: ×1/4
0 1 1: ×1/8
1 0 0: ×1/16
1 0 1: ×1/32
1 1 0: ×1/64.
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
R/W
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9. Clock Generation Circuit
Bit
Symbol
Bit name
Description
R/W
b10 to b8
PCKB[2:0]
Peripheral Module Clock B
(PCLKB) Select*3
b10
R/W
b8
0 0 0: ×1/1
0 0 1: ×1/2
0 1 0: ×1/4
0 1 1: ×1/8
1 0 0: ×1/16
1 0 1: ×1/32
1 1 0: ×1/64.
Other settings are prohibited.
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b14 to b12
PCKA[2:0]
Peripheral Module Clock A
(PCLKA) Select*3
b14
R/W
b15
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b18 to b16
BCK[2:0]
External Bus Clock (BCLK)
Select*2
b18
R/W
b23 to b19
—
Reserved
These bits are read as 0. The write value should be
0.
R/W
b26 to b24
ICK[2:0]
System Clock (ICLK)
Select*1*2*3*4*5
b26
R/W
b12
0 0 0: ×1/1
0 0 1: ×1/2
0 1 0: ×1/4
0 1 1: ×1/8
1 0 0: ×1/16
1 0 1: ×1/32
1 1 0: ×1/64.
Other settings are prohibited.
b16
0 0 0: ×1/1
0 0 1: ×1/2
0 1 0: ×1/4
0 1 1: ×1/8
1 0 0: ×1/16
1 0 1: ×1/32
1 1 0: ×1/64.
Other settings are prohibited.
b24
0 0 0: ×1/1
0 0 1: ×1/2
0 1 0: ×1/4
0 1 1: ×1/8
1 0 0: ×1/16
1 0 1: ×1/32
1 1 0: ×1/64.
Other settings are prohibited.
b27
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b30 to b28
FCK[2:0]
Flash Interface Clock (FCLK)
Select*1
b30
R/W
b31
—
Reserved
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
b28
0 0 0: ×1/1
0 0 1: ×1/2
0 1 0: ×1/4
0 1 1: ×1/8
1 0 0: ×1/16
1 0 1: ×1/32
1 1 0: ×1/64.
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
R/W
The following association is required between the frequencies of the system clock (ICLK) and the flash interface clock (FCLK):
ICLK:FCLK = N:1 (N: integer)
If a setting is made where ICLK < FCLK, then that setting is ignored.
The following association is required between the frequencies of the system clock (ICLK) and the external bus clock (BCLK):
ICLK:BCLK = N:1 (N: integer)
If a setting is made where ICLK < BCLK, then that setting is ignored.
The following association is required between the frequencies of the system clock (ICLK) and the peripheral module clocks
(PCLKA, PCLKB): ICLK:PCLKA = N:1, ICLK:PCLKB = N:1 (N: integer)
If a setting is made where ICLK < PCLKA or ICLK < PCLKB, then that setting is ignored.
The following association is required between the frequencies of the system clock (ICLK) and the peripheral module clocks
(PCLKC, PCLKD): ICLK:PCLKC, PCLKD = N:1 or 1:N (N: integer).
The frequency of the system clock (ICLK) is limited to the flash wait cycle register (FLWT). See section 53, Flash Memory.
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9. Clock Generation Circuit
The SCKDIVCR register selects the frequencies of the system clock (ICLK), the peripheral module clocks (PCLKA,
PCLKB, PCLKC, PCLKD), flash interface clock (FCLK), external bus clock (BCLK), and SDRAM clock (SDCLK).
When the PLL is selected as the clock source, set the following modules to the module-stop state before changing the
value of SCKDIVCR:
ETHERC
EDMAC
SCE7
GPT32EH
GPT32E.
In addition, when changing any value in SCKDIVCR from a lower division ratio to a higher division ratio, wait at least
750 ns before changing the value. When changing any value from a higher division ratio to a lower division ratio, wait at
least 250 ns after changing the value, before starting subsequent processing.
The recommended method to measure the wait time is through software. Be sure to consider the worst-case conditions to
ensure that the required wait time elapses.
Figure 9.2 shows an example flow for changing the value of SCKDIVCR.
PCKD[2:0] bits (Peripheral Module Clock D (PCLKD) Select*4)
The PCKD[2:0] bits select the frequency for peripheral module clock D (PCLKD).
PCKC[2:0] bits (Peripheral Module Clock C (PCLKC) Select*4)
The PCKC[2:0] bits select the frequency for peripheral module clock C (PCLKC).
PCKB[2:0] bits (Peripheral Module Clock B (PCLKB) Select*3)
The PCKB[2:0] bits select the frequency for peripheral module clock B (PCLKB).
PCKA[2:0] bits (Peripheral Module Clock A (PCLKA) Select*3)
The PCKA[2:0] bits select the frequency for peripheral module clock A (PCLKA).
BCK[2:0] bits (External Bus Clock (BCLK) Select*2)
The BCK[2:0] bits select the frequency for the external bus clock (BCLK) and the SDRAM clock (SDCLK).
ICK[2:0] bits (System Clock (ICLK) Select*1*2*3*4*5)
The ICK[2:0] bits select the frequency for the system clock for the CPU, DMAC, and DTC.
FCK[2:0] bits (Flash Interface Clock (FCLK) Select*1)
The FCK[2:0] bits select the frequency for the flash interface clock (FCLK).
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9. Clock Generation Circuit
Start
No
SCKSCR.CKSEL = 101b?
Yes
No
MSTPB15, MSTPC31,
or MSTPD5 = 0?
Yes
MSTPB15 = 0?
Repeat for MSTPB15 to MSTPD5
No
Yes
Set ETHERC0 and EDMAC0 to the
module-stop state
Wait for 250 ns
Change any division ratio in
SCKCIVCR from low to high?
No
Yes
Wait for 750 ns
Change the value of SCKDIVCR
Change the value of SCKDIVCR
Change any division ratio in
SCKCIVCR from high to low?
No
Yes
Wait for 250 ns
Repeat for MSTPB15 to MSTPD5
Need to cancel
module-stop state of ETHERC0 and
EDMAC0?
No
Yes
Cancel module-stop state of ETHERC0 and
EDMAC0?
Wait for 250 ns
End
Figure 9.2
Example flow for changing the value of SCKDIVCR
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9.2.2
9. Clock Generation Circuit
System Clock Division Control Register 2 (SCKDIVCR2)
Address(es): SYSTEM.SCKDIVCR2 4001 E024h
b7
b6
—
0
Value after reset:
b5
b4
UCK[2:0]
1
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6 to b4
UCK[2:0]
USB Clock (UCLK) Select
b6
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
Note:
b4
0 1 0: ×1/3
0 1 1: ×1/4
1 0 0: ×1/5.
Other settings are prohibited.
R/W
Do not write to SCKDIVCR2 and SCKSCR at the same time by 32-bit access.
The SCKDIVCR2 register selects the frequency of the USB clock (UCLK).
UCK[2:0] bits (USB Clock (UCLK) Select)
The UCK[2:0] bits select the frequency of the USB clock (UCLK). The duty ratio is 2:1 when ×1/3 is selected or 3:2
when ×1/5 is selected.
9.2.3
System Clock Source Control Register (SCKSCR)
Address(es): SYSTEM.SCKSCR 4001 E026h
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
b2 to b0
CKSEL[2:0]
Clock Source Select
b7 to b3
—
Reserved
Note:
b2
b1
b0
CKSEL[2:0]
0
0
1
Description
b2
R/W
R/W
b0
0 0 0: HOCO
0 0 1: MOCO
0 1 0: LOCO
0 1 1: Main clock oscillator
1 0 0: Sub-clock oscillator
1 0 1: PLL.
Other settings are prohibited.
These bits are read as 0. The write value should be 0.
R/W
Do not write to SCKDIVCR2 and SCKSCR at the same time by 32-bit access.
The SCKSCR register selects the clock source for the system clock.
When changing the value of SCKSCR to either select or deselect the PLL, set the following modules to the module-stop
state before changing the SCKSCR value:
ETHERC
EDMAC
SCE7
GPT32EH
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9. Clock Generation Circuit
GPT32E.
In addition, when changing the value of SCKSCR from the PLL to a different clock source, wait at least 750 ns before
changing the value. When changing the value from a non-PLL clock source to the PLL, wait at least 250 ns after
changing the value, before starting subsequent processing.
The recommended method to measure the wait time is through software. Be sure to consider the worst-case conditions to
ensure that the required wait time elapses.
Figure 9.3 shows an example flow for changing the value of SCKSCR.
CKSEL[2:0] bits (Clock Source Select)
The CKSEL[2:0] bits select the clock source for the following modules:
System clock (ICLK)
Peripheral module clocks (PCLKA, PCLKB, PCLKC, and PCLKD)
Flash interface clock (FCLK)
External bus clock (BCLK)
SDRAM clock (SDCLK)
USBFS clock (UCLK).
The bits select from one of the following sources:
Low-speed on-chip oscillator (LOCO)
Middle-speed on-chip oscillator (MOCO)
High-speed on-chip oscillator (HOCO)
Main clock oscillator
Sub-clock oscillator
PLL circuit.
The clock sources should be switched when there are no occurring internal asynchronous interrupt.
Transitions to clock sources that are not in operation are prohibited.
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9. Clock Generation Circuit
Start
Change the value
from PLL to non-PLL or
from non-PLL to PLL?
No
Yes
No
MSTPB15, MSTPC31,
or MSTPD5 = 0?
Repeat for MSTPB15 to MSTPD5
Yes
MSTPB15 = 0?
No
Yes
Set ETHERC0 and EDMAC0 to the
module-stop state
Wait for 250 ns
Change the value
from non-PLL to PLL?
No
Yes
Wait for 750 ns
Change the value of SCKSCR
Change the value of SCKSCR
Changed the value
from PLL to non-PLL?
No
Yes
Wait for 250 ns
Repeat for MSTPB15 to MSTPD5
Need to cancel
module-stop state of ETHERC0 and
EDMAC0?
No
Yes
Cancel module-stop state of ETHERC0 and
EDMAC0?
Wait for 250 ns
End
Figure 9.3
Example flow for changing the value of SCKSCR
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9.2.4
9. Clock Generation Circuit
PLL Clock Control Register (PLLCCR)
Address(es): SYSTEM.PLLCCR 4001 E028h
b15
b14
—
—
0
0
Value after reset:
b13
b12
b11
b10
b9
b8
PLLMUL[5:0]
0
1
0
0
1
Bit
Symbol
Bit name
b1, b0
PLIDIV[1:0]
PLL Input Frequency Division
Ratio Select*1
1
b7
b6
b5
b4
b3
b2
b1
—
—
—
PLSRC
SEL
—
—
PLIDIV[1:0]
0
0
0
0
0
0
0
Description
b1 b0
0
0
1
1
0:
1:
0:
1:
b0
0
R/W
R/W
×1
× 1/2
× 1/3
Setting prohibited.
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
PLSRCSEL
PLL Clock Source Select
0: Main clock oscillator*3
1: HOCO.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13 to b8
PLLMUL[5:0]
PLL Frequency Multiplication
Factor Select*2
b13
R/W
b15, b14
—
Reserved
Note 1.
Note 2.
Note 3.
b8
0 1 0 0 1 1: × 10.0
0 1 0 1 0 0: × 10.5
0 1 0 1 0 1: × 11.0
…
0 1 1 1 0 0: × 14.5
0 1 1 1 0 1: × 15.0
0 1 1 1 1 0: × 15.5
…
1 1 1 0 1 0: × 29.5
1 1 1 0 1 1: × 30.0.
Other settings are prohibited.
These bits are read as 0. The write value should be 0.
R/W
PLIDIV[1:0] must be set so that the frequency of the PLL input signal is within the range listed in Table 9.1.
PLLMUL[5:0] must be set so that the frequency of the PLL output signal is within the range listed in Table 9.1.
PLSRCSEL must be set to 0 when using UCLK.
The PLLCCR register sets up the operation of the PLL circuit. Writing to the PLLCCR is prohibited when the PLL is
operating (when the PLLCR.PLLSTP bit is 0).
PLIDIV[1:0] bits (PLL Input Frequency Division Ratio Select*1)
The PLIDIV[1:0] bits select the frequency division ratio for the PLL clock source.
PLSRCSEL bit (PLL Clock Source Select)
The PLSRCSEL bit selects the clock source for the PLL.
PLLMUL[5:0] bits (PLL Frequency Multiplication Factor Select*2)
The PLLMUL[5:0] bits select the frequency multiplication factor for the PLL circuit.
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9.2.5
9. Clock Generation Circuit
PLL Control Register (PLLCR)
Address(es): SYSTEM.PLLCR 4001 E02Ah
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
PLLST
P
0
0
0
0
0
0
0
1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
PLLSTP
PLL Stop Control
0: Operate the PLL
1: Stop the PLL.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The PLLCR register controls the operation of the PLL circuit.
PLLSTP bit (PLL Stop Control)
The PLLSTP bit starts or stops the PLL circuit. When selecting the main clock oscillator as the clock source for the PLL
in the PLLCCR.PLSRCSEL bit, you must also set the Main Clock Oscillator Wait Control Register (MOSCWTCR).
After setting the PLLSTP bit to 0, confirm that the OSCSF.PLLSF bit is set to 1 before using the PLL clock. A fixed
stabilization wait is required after setting the PLL to start operation. A fixed wait for the oscillation to stop is also
required.
The following restrictions apply when starting and stopping the PLL operation:
After stopping the PLL, confirm that the OSCSF.PLLSF bit is 0 before restarting the PLL
Confirm that the PLL operates and that the OSCSF.PLLSF bit is 1 before stopping the PLL
Regardless of whether the PLL clock is selected as the system clock, after setting the PLL to start operation, confirm
that the OSCSF.PLLSF is set to 1 before executing a WFI instruction to place the MCU in Software Standby or
Deep Software Standby mode
When a transition to Software Standby or Deep Software Standby mode is to follow the setting to stop the PLL,
confirm that the OSCSF.PLLSF bit is set to 0 before executing the WFI instruction.
Writing 1 to PLLSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 101b (system clock source = PLL).
Make sure the following conditions apply before writing 0 to PLLSTP:
When PLL source clock = MOSC, OSCSF.MOSCSF bit = 1
When PLL source clock = HOCO, OSCSF.HOCOSF bit = 1.
9.2.6
External Bus Clock Control Register (BCKCR)
Address(es): SYSTEM.BCKCR 4001 E030h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
BCLKD
IV
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
BCLKDIV
EBCLK Pin Output Select
0: BCLK
1: BCLK/2.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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9. Clock Generation Circuit
The BCKCR register controls the external bus clock pin.
BCLKDIV bit (EBCLK Pin Output Select)
The BCLKDIV bit selects the clock signal for output from the EBCLK pin. The signal can be selected from either the
BCLK clock with the frequency selected in the BCK[2:0] bits in SCKDIVCR or the BCLK clock divided by 2.
9.2.7
Main Clock Oscillator Control Register (MOSCCR)
Address(es): SYSTEM.MOSCCR 4001 E032h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
MOSTP
0
0
0
0
0
0
0
1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
oscillator*1
b0
MOSTP
Main Clock Oscillator Stop
0: Operate the main clock
1: Stop the main clock oscillator.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
The MOMCR register must be set before setting MOSTP to 0.
The MOSCCR register controls the main clock oscillator.
MOSTP bit (Main Clock Oscillator Stop)
The MOSTP bit starts or stops the main clock oscillator. To start the main clock oscillator, set this bit to 0. When
changing the value of the bit, only execute subsequent instructions after reading the bit to check that the value was
updated. When using the main clock oscillator, you must set the Main Clock Oscillator Mode Oscillation Control
Register (MOMCR) and the Main Clock Oscillator Wait Control Register (MOSCWTCR) before setting MOSTP to 0.
After setting the MOSTP bit to 0, confirm that the OSCSF.MOSCSF bit is set to 1 before using the main clock oscillator.
A fixed stabilization wait is required after setting the main clock oscillator to start operation. A fixed wait for the
oscillation to stop is also required.
The following restrictions apply when starting and stopping the main clock oscillator operation:
After stopping the main clock oscillator, ensure that the OSCSF.MOSCSF bit is 0 before restarting the main clock
oscillator
Confirm that the main clock oscillator operates and that the OSCSF.MOSCSF bit is 1 before stopping the main
clock oscillator
Regardless of whether the main clock oscillator is selected as the system clock, confirm that the OSCSF.MOSCSF
bit is set to 1 before executing a WFI instruction to place the MCU in Software Standby or Deep Software Standby
mode
When a transition to Software Standby or Deep Software Standby mode is to follow the setting to stop the main
clock oscillator, confirm that the OSCSF.MOSCSF bit is set to 0 before executing the WFI instruction.
Writing 1 to MOSTP is prohibited under the following conditions:
SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC)
PLLCCR.PLSRCSEL = 0 (PLL source clock = MOSC) and SCKSCR.CKSEL[2:0] = 101b (system clock source =
PLL)
PLLCCR.PLSRCSEL = 0 (PLL source clock = MOSC) and PLLCR.PLLSTP = 0 (PLL is operating).
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9.2.8
9. Clock Generation Circuit
Subclock Oscillator Control Register (SOSCCR)
Address(es): SYSTEM.SOSCCR 4001 E480h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
SOSTP
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
oscillator*1
b0
SOSTP
Sub-Clock Oscillator Stop
0: Operate the sub-clock
1: Stop the sub-clock oscillator.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
The SOMCR register must be set before setting SOSTP to 0.
The SOSCCR register controls the sub-clock oscillator.
SOSTP bit (Sub-Clock Oscillator Stop)
The SOSTP bit starts or stops the sub-clock oscillator.
When changing the value of the SOSTP bit, only execute subsequent instructions after reading the bit and checking that
its value is updated. Use the SOSTP bit when using the sub-clock oscillator as the source for a peripheral module, for
example the RTC. When using the sub-clock oscillator, you must set the Sub-Clock Oscillator Mode Control Register
(SOMCR) before setting SOSTP to 0.
After setting SOSTP to 0, only use the sub-clock oscillator after the sub-clock oscillation stabilization wait time
(tSUBOSCOWT) elapses. A fixed stabilization wait is required after setting the sub-clock oscillator to start operation. A
fixed wait for the oscillation to stop is also required.
The following restrictions apply when starting and stopping operation:
After stopping the sub-clock oscillator, allow a stop interval of at least 5 SOSC clock cycles before restarting it
Confirm that sub-clock oscillation is stable before stopping the sub-clock oscillator
Regardless of whether the sub-clock oscillator is selected as the system clock, confirm that sub-clock oscillation is
stable before executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting to stop the sub-clock oscillator, wait for at least
3 SOSC clock cycles before executing the WFI instruction.
Writing 1 to SOSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 100b (system clock source = SOSC).
9.2.9
Low-Speed On-Chip Oscillator Control Register (LOCOCR)
Address(es): SYSTEM.LOCOCR 4001 E490h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
LCSTP
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
LCSTP
LOCO Stop
0: Operate the LOCO clock
1: Stop the LOCO clock.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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The LOCOCR register controls the LOCO clock.
LCSTP bit (LOCO Stop)
The LCSTP bit starts or stops the LOCO clock.
After setting the LCSTP bit to 0 to start the LOCO clock, only use the clock after the LOCO clock oscillation
stabilization wait time (tLOCOWT) elapses. A fixed stabilization wait is required after setting the LOCO clock to start
operation. A fixed wait for the oscillation to stop is also required.
The following restrictions apply when starting and stopping operation:
After stopping the LOCO clock, allow a stop interval of at least 5 LOCO clock cycles before restarting it
Confirm that LOCO oscillation is stable before stopping the LOCO clock
Regardless of whether the LOCO clock is selected as the system clock, confirm that LOCO oscillation is stable
before executing a WFI instruction to place the MCU in Software Standby or Deep Software Standby mode
When a transition to Software Standby or Deep Software Standby mode is to follow the setting to stop the LOCO
clock, wait for at least 3 LOCO clock cycles before executing the WFI instruction.
Writing 1 to LOSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 010b (system clock source = LOCO).
Because the LOCO clock measures the wait time for other oscillators, it continues to oscillate while measuring this time,
regardless of the setting in LOCOCR.LCSTP. As a result, the LOCO clock might be unintentionally supplied even when
the LCSTP is set to stop.
9.2.10
High-Speed On-Chip Oscillator Control Register (HOCOCR)
Address(es): SYSTEM.HOCOCR 4001 E036h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
HCSTP
0
0
0
0
0
0
0
0/1*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
HCSTP
HOCO Stop
0: Operate the HOCO clock*2
1: Stop the HOCO clock.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
The HCSTP bit value after a reset is 0 when the OFS1.HOCOEN bit is 0. It is 1 when the OFS1.HOCOEN bit is 1.
If you use the HOCO (HCSTP = 0), you must set the OFS1.HOCOFRQ1 bit to an optimum value.
The HOCOCR register controls the HOCO clock.
HCSTP bit (HOCO Stop)
The HCSTP bit starts or stops the HOCO clock.
After setting the HCSTP bit to 0 to start the HOCO clock, confirm that the OSCSF.HOSCSF bit is set to 1 before using
the clock. When OFS1.HOCOEN is set to 1, confirm that the OSCSF.HOCOSF is also set to 1 before using the HOCO
clock. A fixed stabilization wait is required after setting the HOCO clock to start operation. A fixed wait for oscillation to
stop is also required. For the HOCO to operate, the HOCO Wait Control Register (HOCOWTCR) must also be set.
The following restrictions apply when starting and stopping operation:
After stopping the HOCO, confirm that the OSCSF.HOCOSF bit is 0 before restarting the HOCO clock
Confirm that the HOCO clock operates and that the OSCSF.HOCOSF bit is 1 before stopping the HOCO clock
Regardless of whether the HOCO clock is selected as the system clock, confirm that the OSCSF.HOSCSF bit is set
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9. Clock Generation Circuit
to 1 before executing a WFI instruction to place the MCU in Software Standby or Deep Software Standby mode
When a transition to Software Standby or Deep Software Standby mode is to follow the setting to stop the HOCO
clock, confirm that the OSCSF.MOSCSF bit is set to 0, before executing the WFI instruction.
Writing 1 to HCSTP is prohibited under the following conditions:
SCKSCR.CKSEL[2:0] = 000b (system clock source = HOCO)
PLLCCR.PLSRCSEL = 1 (PLL source clock = HOCO) and SCKSCR.CKSEL[2:0] = 101b (system clock source =
PLL)
PLLCCR.PLSRCSEL = 1 (PLL source clock = HOCO) and PLLCR.PLLSTP = 0 (PLL is operating).
9.2.11
High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR)
Address(es): SYSTEM.HOCOWTCR 4001 E0A5h
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
Value after reset:
Bit
Symbol
b2
b1
b0
HSTS[2:0]
0
Bit name
1
0
Description
R/W
b2 to b0
HSTS[2:0]
HOCO Wait Time Setting
Wait time (s) = (HSTS[2:0] setting +3) / fLOCO
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R
HSTS[2:0] bits (HOCO Wait Time Setting)
The HOCOWTCR.HSTS[2:0] bits must be set to 110b, except when using SCI0 in Snooze mode. When using SCI0 in
Snooze mode, the HOCOWTCR.HSTS[2:0] bits must be set to 010b.
9.2.12
Middle-Speed On-Chip Oscillator Control Register (MOCOCR)
Address(es): SYSTEM.MOCOCR 4001 E038h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
MCSTP
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
MCSTP
MOCO Stop
0: Operate the MOCO clock
1: Stop the MOCO clock.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The MOCOCR register controls the MOCO clock.
MCSTP bit (MOCO Stop)
The MCSTP bit starts or stops the MOCO clock.
After setting the MCSTP bit to 0 to start the MOCO clock, only use the clock after the MOCO clock oscillation
stabilization time (tMOCOWT) elapses. A fixed stabilization wait is required after setting the MOCO clock to start
operation. A fixed wait for oscillation to stop is also required.
The following restrictions apply when starting and stopping operation:
After stopping the MOCO clock, allow a stop interval of at least 5 MOCO clock cycles before restarting it
Confirm that MOCO oscillation is stable before stopping the MOCO clock
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Regardless of whether the MOCO clock is selected as the system clock, confirm that MOCO oscillation is stable
before executing a WFI instruction to place the MCU in Software Standby or Deep Software Standby mode
When a transition to Software Standby or Deep Software Standby mode is to follow the setting to stop the MOCO
clock, wait for at least 3 MOCO clock cycles before executing the WFI instruction.
Writing 1 to MCSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 001b (system clock source = MOCO).
Writing 1 to the MCSTP bit (stopping the MOCO) is prohibited if oscillation stop detection is enabled in the Oscillation
Stop Detection Control Register (OSTDCR.OSTDE).
9.2.13
FLL Control Register 1 (FLLCR1)
Address(es): SYSTEM.FLLCR1 4001 E039h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
FLLEN
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FLLEN
FLL Enable
0: FLL function is disabled
1: FLL function is enabled.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
HOCO must be stopped (HOCOCR.HCSTP = 1) before FLLCR1.FLLEN is changed.
SOSC must operate with stabilization while FLL is enabled (FLLCR1.FLLEN = 1).
The FLLCR1 register controls the FLL function of the HOCO. The FLL function uses SOSC when available for better
accuracy in HOCO.
FLLEN bit (FLL Enable)
The FLLEN bit enables or disables the FLL function of the HOCO.
If the FLL function is enabled, the frequency accuracy is guaranteed after the FLL is stabilized. The FLL stabilization
can be checked by the frequency measurement of the Clock Frequency Accuracy Measurement Circuit (CAC) after the
HOCO is stabilized.
The FLL function must be disabled before the transition to Software Standby mode. Therefore, this bit must be set to 0
before the transition to Software Standby mode.
Figure 9.4 and Figure 9.5 show an example flow of the FLL setting in each case.
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9. Clock Generation Circuit
Start
(After reset release/Deep Software Standby cancellation)
FLL setting (FLLCR2.FLLCNTL)
Enable FLL (FLLCR1.FLLEN = 1)*1
Enable HOCO (HOCOCR.HCSTP = 0)
Wait for the FLL stabilization (tFLLWT)
Check the HOCO stabilization (OSCSR.HOCOSF = 1)
End (HOCO can be used.)
Note 1.
Figure 9.4
SOSC must be running with the oscillation stabilized.
FLL setting flow after reset release/Deep Software Standby cancellation
Start (FLL is used)
Stop HOCO (HOCOCR1.HCSTP = 1)*1
Disable FLL (FLLCR1.FLLEN = 0)
WFI instruction
Software Standby mode
Software Standby cancellation
Enable FLL (FLLCR1.FLLEN = 1)
Enable HOCO (HOCOCR.HCSTP = 0)
Wait for the FLL stabilization (tFLLWT)
Check the HOCO stabilization (OSCSR.HOCOSF = 1)
End (HOCO can be used)
Note 1.
Figure 9.5
If HOCO is used as the system clock or the PLL reference clock, these clock
sources must be changed to another clock before HOCO is stopped.
Software Standby transition/cancellation flow
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9.2.14
9. Clock Generation Circuit
FLL Control Register 2 (FLLCR2)
Address(es): SYSTEM.FLLCR2.4001 E03Ah
Value after reset:
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
FLLCNTL[10:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
FLLCNTL[10:0]
FLL Multiplication Control
When OFS1.HOCOFRQ0[1:0] is 00b (16 MHz), these
bits must be set to 1E9h
When OFS1.HOCOFRQ0[1:0] is 01b (18 MHz), these
bits must be set to 226h
When OFS1.HOCOFRQ0[1:0] is 10b (20 MHz), these
bits must be set to 263h.
Other settings are prohibited.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The FLLCR2 register controls the FLL function of the HOCO.
FLLCNTL[10:0] bits (FLL Multiplication Control)
The FLLCNTL[10:0] bits select the multiplication ratio of the FLL reference clock.
These bits must be set before FLL is enabled (FLLCR1.FLLEN = 1).
9.2.15
Oscillation Stabilization Flag Register (OSCSF)
Address(es): SYSTEM.OSCSF 4001 E03Ch
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
PLLSF
—
MOSC
SF
—
—
HOCO
SF
0
0
0
0
0
0
0
0/1*1
Bit
Symbol
Bit name
Description
R/W
b0
HOCOSF
HOCO Clock Oscillation
Stabilization Flag
0: The HOCO clock is stopped or is not yet stable
1: The HOCO clock is stable, and is available for use as
the system clock.
R
b2, b1
—
Reserved
These bits are read as 0.
R
b3
MOSCSF
Main Clock Oscillation
Stabilization Flag
0: The main clock oscillator is stopped (MOSTP = 1) or is
not yet stable*2
1: The main clock oscillator is stable, and is available for
use as the system clock.
R
b4
—
Reserved
This bit is read as 0.
R
b5
PLLSF
PLL Clock Oscillation Stabilization
Flag
0: The PLL clock is stopped or is not yet stable
1: The PLL clock is stable, and is available for use as the
system clock.
R
b7, b6
—
Reserved
These bits are read as 0
R
Note 1.
Note 2.
The value after reset depends on the OFS1.HOCOEN setting.
When OFS1.HOCOEN = 1, the value after reset of HOCOSF is 0.
When OFS1.HOCOEN = 0, the HOCOSF value becomes 0 after reset is released, and HOCOSF is set to 1 after the HOCO
oscillation stabilization wait time elapses.
An appropriate value is set in the Wait Control Register for the given oscillator. If the wait time value is not sufficient, the
oscillation stabilization flag is set to 1 and supply of the clock signal to the internal circuits starts before oscillation is stable.
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The OSCSF register contains flags to indicate the operating status of the counters in the oscillation stabilization wait
circuits for the individual oscillators. After oscillation starts, these counters measure the wait time until each oscillator
output clock is supplied to the internal circuits. An overflow of a counter indicates that the clock supply is stable and
available for the associated circuit.
HOCOSF flag (HOCO Clock Oscillation Stabilization Flag)
The HOCOSF flag indicates the operating status of the counter that measures the wait time for the high-speed clock
oscillator (HOCO). When OFS1.HOCOEN is set to 1, confirm that the OSCSF.HOCOSF is also set to 1 before using the
HOCO clock.
[Setting condition]
After the HOCO clock stops and the HOCOCR.HCSTP bit is set to 0, supply of the MCU clock starts after the
number of LOCO cycles associated with the setting of the HOCOWTCR register elapses.
[Clearing condition]
When the HOCO clock is operating and then is deactivated because the HOCOCR.HCSTP bit is set to 1.
MOSCSF flag (Main Clock Oscillation Stabilization Flag)
The MOSCSF flag indicates the operating status of the counter that measures the wait time for the main clock oscillator.
[Setting condition]
After the main clock oscillator stops and the MOSCCR.MOSTP bit is set to 0, supply of the MCU clock starts after
the number of LOCO cycles associated with the setting of the MOSCWTCR register elapses.
[Clearing condition]
When the main clock oscillator is operating and then is deactivated because the MOSCCR.MOSTP bit is set to 1.
PLLSF flag (PLL Clock Oscillation Stabilization Flag)
The PLLSF flag indicates the operating status of the counter that measures the wait time for the PLL.
[Setting condition]
After the PLL stops and the PLLCR.PLLSTP bit is set to 0, supply of the MCU clock starts after 31 LOCO cycles.
If oscillation by the PLL clock source selected in the PLLCCR.PLSRCSEL bit is not stable when the PLLSTP bit is
set to 0, counting of the LOCO cycles continues after the PLL clock source oscillation is stabilized. Wait time is
calculated as:
1 cycle = LOCO (32.768 kHz) x 8 (3.81 μs typical).
[Clearing condition]
When the PLL is operating and then is deactivated because the PLLCCR.PLLSTP bit is set to 1.
9.2.16
Oscillation Stop Detection Control Register (OSTDCR)
Address(es): SYSTEM.OSTDCR 4001 E040h
b7
b6
b5
b4
b3
b2
b1
b0
OSTDE
—
—
—
—
—
—
OSTDI
E
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
OSTDIE
Oscillation Stop Detection
Interrupt Enable
0: Disable oscillation stop detection interrupt (do not notify
the POEG)
1: Enable oscillation stop detection interrupt (notify the
POEG).
R/W
b6 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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Bit
Symbol
Bit name
Description
R/W
b7
OSTDE
Oscillation Stop Detection
Function Enable
0: Disable oscillation stop detection function
1: Enable oscillation stop detection function.
R/W
The OSTDCR register controls the oscillation stop detection function.
OSTDIE bit (Oscillation Stop Detection Interrupt Enable)
The OSTDIE bit enables the oscillation stop detection function interrupt. It also controls whether oscillation stop
detection is reported to the POEG.
If the Oscillation Stop Detection flag in the Oscillation Stop Detection Status Register (OSTDSR.OSTDF) requires
clearing, set the OSTDIE bit to 0 before clearing OSTDF. Wait for at least 2 PCLKB cycles before setting the OSTDIE
bit to 1. A longer PCLKB wait time might be required, depending on the number of cycles required to read a given I/O
register.
OSTDE bit (Oscillation Stop Detection Function Enable)
The OSTDE bit enables the oscillation stop detection function.
When OSTDE is 1 (enabled), the MOCO stop bit (MOCOCR.MCSTP) is set to 0 and MOCO operation starts. The
MOCO clock cannot be stopped while the oscillation stop detection function is enabled. Writing 1 to the
MOCOCR.MCSTP bit (MOCO stopped) is invalid.
When the Oscillation Stop Detection flag in the Oscillation Stop Detection Status Register (OSTDSR.OSTDF) is 1 (main
clock oscillation stop detected), writing 0 to the OSTDE bit is invalid.
The OSTDE bit must be set to 0 before transitioning to Software Standby or Deep Software Standby mode. To transition
to either of these modes, first set the OSTDE bit to 0, then execute the WFI instruction.
The following restrictions apply when using the oscillation stop detection function:
In low-speed mode, selecting division by 1, 2, 4, 8 for ICLK, FCLK, BCLK, PCLKA, PCLKB, PCLKC, PCLKD is
prohibited.
9.2.17
Oscillation Stop Detection Status Register (OSTDSR)
Address(es): SYSTEM.OSTDSR 4001 E041h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
OSTDF
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
OSTDF
Oscillation Stop Detection Flag
0: Main clock oscillation stop not detected
1: Main clock oscillation stop detected.
R(/W)*1
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R
Note 1.
This bit can only be set to 0.
The OSTDSR register indicates the stop detection status of the main clock oscillator.
OSTDF flag (Oscillation Stop Detection Flag)
The OSTDF flag indicates the main clock oscillator status. When OSTDF is 1, it indicates that the main clock oscillation
stop was detected. After this stop is detected, the OSTDF flag is not set to 0 even when oscillation is restarted. The
OSTDF flag is set to 0 by writing 0 after reading it as 1.
At least 3 ICLK cycles of wait time are required between writing 0 to OSTDF and reading OSTDF as 0. If the OSTDF
flag is set to 0 when the main clock oscillation is stopped, the OSTDF flag becomes 0 then returns to 1.
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OSTDSR.OSTDF cannot be set to 0 under the following conditions:
SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC)
PLLCCR.PLSRCSEL = 0 (PLL source clock = MOSC) and SCKSCR.CKSEL[2:0] = 101b (system clock source =
PLL).
The OSTDF flag must be set to 0 after switching the clock source to sources other than the main clock oscillator and
PLL.
[Setting condition]
The main clock oscillator is stopped when OSTDCR.OSTDE = 1 (oscillation stop detection function enabled).
[Clearing condition]
1 is read and then 0 is written when the SCKSCR.CKSEL[2:0] bits are neither 011b (system clock = MOSC) nor
101b (system clock = PLL), and the PLLCCR.PLSRCSEL bit is not 0 (PLL source clock = MOSC).
9.2.18
Main Clock Oscillator Wait Control Register (MOSCWTCR)
Address(es): SYSTEM.MOSCWTCR 4001 E0A2h
b7
b6
b5
b4
—
—
—
—
0
0
0
0
Value after reset:
b3
b2
b1
b0
MSTS[3:0]
0
1
0
1
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MSTS[3:0]
Main Clock Oscillator Wait
Time Setting
When drive capability automatic switching function is disabled
(MOMCR.AUTODRVEN = 0 [default]):
R/W
b3
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
b0
1: Wait time = 35 cycles (133.5 μs)
0: Wait time = 67 cycles (255.6 μs)
1: Wait time = 131 cycles (499.7 μs)
0: Wait time = 259 cycles (988.0 μs)
1: Wait time = 547 cycles (2086.6 μs) (value after reset)
0: Wait time = 1059 cycles (4039.8 μs)
1: Wait time = 2147 cycles (8190.2 μs)
0: Wait time = 4291 cycles (16368.9 μs)
1: Wait time = 8163 cycles (31139.4 μs).
When drive capability automatic switching function is enabled
(MOMCR.AUTODRVEN = 1):
b3
b0
0 0 0 1: Wait time = 36 cycles (137.3 μs)
0 0 1 0: Wait time = 68 cycles (259.4 μs)
0 0 1 1: Wait time = 132 cycles (503.5 μs)
0 1 0 0: Wait time = 260 cycles (991.8 μs)
0 1 0 1: Wait time = 548 cycles (2090.5 μs) (value after reset)
0 1 1 0: Wait time = 1060 cycles (4043.6 μs)
0 1 1 1: Wait time = 2148 cycles (8194.0 μs)
1 0 0 0: Wait time = 4292 cycles (16372.7 μs)
1 0 0 1: Wait time = 8164 cycles (31143.2 μs).
Other settings are prohibited.
Wait time is calculated as:
1 cycle (μs) = 1 / (f_LOCO [MHz] × 8) = 1 / (0.032768 × 8) = 3.81 μs
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R
MSTS[3:0] bits (Main Clock Oscillator Wait Time Setting)
Set the MSTS[3:0] bits to select the oscillation stabilization wait time for the main clock oscillator.
Specify a time period longer than or equal to the stabilization time recommended by the oscillator manufacturer. When
the main clock is input externally, set these bits to 0001b, because the oscillation stabilization time is not required.
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9. Clock Generation Circuit
The wait time set in the MSTS[3:0] bits is counted using:
1 cycle (μs) = 1 / (f_ LOCO [MHz] × 8) = 1 / (0.032768 × 8) = 3.81 (μs).
The LOCO clock automatically oscillates when necessary, regardless of the value of the LOCOCR.LOSTP bit. After the
specified wait time elapses, supply of the main clock oscillator starts internally in the MCU, and the OSCSF.MOSCSF
flag is set to 1. If the specified wait time is short, supply of the main clock oscillator starts before oscillation of the clock
becomes stable.
Only rewrite the MOSCWTCR register when the MOSCCR.MOSTP bit is 1 and the OSCSF.MOSCSF flag is 0. Do not
rewrite this register under any other conditions.
9.2.19
Main Clock Oscillator Mode Oscillation Control Register (MOMCR)
Address(es): SYSTEM.MOMCR 4001 E413h
b7
b6
b5
b4
AUTOD MOSEL MODRV0[1:0]
RVEN
Value after reset:
0
0
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
b5, b4
MODRV0[1:0]
Main Clock Oscillator Drive
Capability 0 Switching
b6
MOSEL
Main Clock Oscillator Switching
b7
AUTODRVEN
Main Clock Oscillator Drive
0: Disable
Capability Auto Switching Enable 1: Enable.
Note:
Note:
b5 b4
0
0
1
1
0:
1:
0:
1:
20 to 24 MHz
16 to 20 MHz
8 to 16 MHz
8 MHz.
0: Resonator
1: External clock input.
R/W
R/W
R/W
R/W
R/W
The EXTAL/XTAL pin is also used as a port. In the initial state, the port function is selected.
The MOSTP bit must be 1 (MOSC = stopped) before changing this register.
MODRV0[1:0] bits (Main Clock Oscillator Drive Capability 0 Switching)
The MODRV0[1:0] bits switch the drive capability of the main clock oscillator.
MOSEL bit (Main Clock Oscillator Switching)
The MOSEL bit switches the source for the main clock oscillator.
AUTODRVEN bit (Main Clock Oscillator Drive Capability Auto Switching Enable)
The AUTODRVEN bit controls the drive capability auto switching of the main clock oscillator.
When AUTODRVEN = 1, after the time set in the MSTS bits in the Main Clock Oscillator Wait Control Register elapses,
the effective main clock oscillator drive capability is automatically set to the lowest, regardless of the
MOMCR.MODRV0[1:0] setting. The main clock oscillator restarts oscillation with MOMCR.MODRV0 specified drive
capability after the oscillation stops by the MOSCCR.MOSTP setting or by entering Software Standby mode.
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9.2.20
9. Clock Generation Circuit
Subclock Oscillator Mode Control Register (SOMCR)
Address(es): SYSTEM.SOMCR 4001 E481h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
SODRV
1
—
0
0
0
0
0
0
x
0
Value after reset:
x: Undefined
Bit
Symbol
Bit name
b0
—
b1
SODRV1
b7 to b2
—
Note:
Description
R/W
Reserved
This bit is read as 0. The write value should be 0.
R/W
Sub-Clock Oscillator Drive
Capability Switching
0: Standard
1: Low.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SOSCCR.SOSTP bit must be 1 (SOSC = stopped) before changing this register.
SODRV1 bit (Sub-Clock Oscillator Drive Capability Switching)
The SODRV1 bit switches the drive capability of the sub-clock oscillator. This bit is undefined at the first power on, but
the value after reset of SOSCCR.SOSTP is 0 (SOSC = operating). Set up the SOSC as follows at the first power on:
1. Set the SOSCCR.SOSTP bit to 1 (SOSC = stopped).
2. Set the SODRV1 bit to the correct value for the current capacitor.
3. Set the SOSCCR.SOSTP bit to 0 (SOSC = operating).
9.2.21
Clock Out Control Register (CKOCR)
Address(es): SYSTEM.CKOCR 4001 E03Eh
b7
b6
CKOEN
0
Value after reset:
b5
b4
CKODIV[2:0]
0
0
b3
b2
—
0
0
b1
CKOSEL[2:0]
0
Bit
Symbol
Bit name
b2 to b0
CKOSEL[2:0]
Clock Out Source Select
b3
—
Reserved
b6 to b4
CKODIV[2:0]
Clock Out Input Frequency
Division Select
b7
CKOEN
Clock Out Enable
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b0
0
0
Description
b2
R/W
R/W
b0
0 0 0: HOCO
0 0 1: MOCO
0 1 0: LOCO
0 1 1: MOSC
1 0 0: SOSC.
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
b6
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b4
0:
1:
0:
1:
0:
1:
0:
1:
×1
/2
/4
/8
/16
/32
/64
/128.
0: Disable clock out
1: Enable clock out.
R/W
R/W
R/W
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9. Clock Generation Circuit
CKOSEL[2:0] bits (Clock Out Source Select)
The CKOSEL[2:0] bits specify the HOCO, MOCO, LOCO, MOSC, or SOSC clock as the source of the clock to be
output from the CLKOUT pin. When changing the CLKOUT source clock, set the CKOEN bit to 0.
CKODIV[2:0] bits (Clock Out Input Frequency Division Select)
The CKODIV[2:0] bits specify the clock division ratio. Set the CKOEN bit to 0 when changing the division ratio. The
division ratio of the output clock frequency must be set to a value no higher than the characteristics of the CLKOUT pin
output frequency. For details on the characteristics of the CLKOUT pin, see section 55, Electrical Characteristics.
CKOEN bit (Clock Out Enable)
The CKOEN bit enables output from the CLKOUT pin. When CKOEN is set to 1, the selected clock is output. When
CKOEN is set to 0, low is output. When changing this bit, confirm that the clock out source clock selected in the
CKOSEL[2:0] bits is stable. Otherwise, a glitch might be generated in the output.
The CKOEN bit must be cleared before entering Software Standby or Deep Software Standby mode if the selected clock
out source clock is stopped in that mode.
9.2.22
External Bus Clock Output Control Register (EBCKOCR)
Address(es): SYSTEM.EBCKOCR 4001 E052h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
EBCKO
EN
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
EBCKOEN
EBCLK Pin Output Control
0: Disable EBCLK pin output (fixed high)
1: Enable EBCLK pin output.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
9.2.23
SDRAM Clock Output Control Register (SDCKOCR)
Address(es): SYSTEM.SDCKOCR 4001 E053h
b7
Value after reset:
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
SDCKO
EN
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SDCKOEN
SDCLK Pin Output Control
0: Disable SDCLK pin output (fixed high)
1: Enable SDCLK pin output.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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9.2.24
9. Clock Generation Circuit
LOCO User Trimming Control Register (LOCOUTCR)
Address(es): SYSTEM.LOCOUTCR 4001 E492h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
LOCOUTRM[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
LOCOUTRM[7:0]
LOCO User Trimming
b7
R/W
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127.
These bits are added to the original LOCO trimming bits.
Note:
Note:
MCU operation is not guaranteed when LOCOUTCR is set to a value that causes the LOCO frequency to be outside of the
specification range.
When LOCOUTCR is changed, the time that the frequency is stabilized corresponds to the frequency stabilization time at the
start of the MCU operation.
9.2.25
MOCO User Trimming Control Register (MOCOUTCR)
Address(es): SYSTEM.MOCOUTCR 4001 E061h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
MOCOUTRM[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
MOCOUTRM[7:0]
MOCO User Trimming
b7
R/W
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127.
These bits are added to the original MOCO trimming bits.
Note:
Note:
MCU operation is not guaranteed when MOCOUTCR is set to a value that causes the MOCO frequency to be outside of the
specification range.
When MOCOUTCR is changed, the time that the frequency is stabilized corresponds to the frequency stabilization time at the
start of the MCU operation.
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9.2.26
9. Clock Generation Circuit
HOCO User Trimming Control Register (HOCOUTCR)
Address(es): SYSTEM.HOCOUTCR 4001 E062h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
HOCOUTRM[7:0]
0
Value after reset:
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
HOCOUTRM[7:0]
HOCO User Trimming
b7
R/W
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127.
These bits are added to the original HOCO trimming bits.
Note:
Note:
Note:
MCU operation is not guaranteed when HOCOUTCR is set to a value that causes the HOCO frequency to be outside of the
specification range.
When HOCOUTCR is changed, the time that the frequency is stabilized corresponds to the frequency stabilization time at the
start of the MCU operation.
These bits must be 00000000b when FLL is enabled (FLLCR1.FLLEN = 1).
9.2.27
Trace Clock Control Register (TRCKCR)
Address(es): SYSTEM.TRCKCR 4001 E03Fh
b7
b6
b5
b4
TRCKE
N
—
—
—
0
0
0
0
Value after reset:
b3
b2
b1
b0
TRCK[3:0]
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b3 to b0
TRCK[3:0]
Trace Clock Operating
Frequency Select
b3
R/W
b6 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
TRCKEN
Trace Clock Operation
Enable
0: Disable operation
1: Enable operation.
R/W
b0
0 0 0 0: /1
0 0 0 1: /2 (value after reset)
0 0 1 0: /4.
Other settings are prohibited.
The Trace Clock Control Register controls the switching of the trace clock. Before changing the TRCLK frequency, set
the TRCKEN bit to 0. The TRCKCR register is initialized by all reset sources.
9.3
Main Clock Oscillator
Use one of the following ways to supply the clock signal to the main clock oscillator:
Connect an oscillator
Connect the input of an external clock signal.
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9.3.1
9. Clock Generation Circuit
Connecting the Crystal Resonator
Figure 9.6 shows an example connection to a crystal resonator. A damping resistor (Rd) can be added, if required.
Because the resistor values vary according to the resonator and the oscillation drive capability, use values recommended
by the resonator manufacturer. If the manufacturer recommends using an external feedback resistor (Rf), insert an Rf
between EXTAL and XTAL by following the instructions.
When connecting a resonator to supply the clock, the frequency of the resonator must be in the frequency range of the
resonator for the main clock oscillator as described in Table 9.1.
CL1
EXTAL
Rf
XTAL
CL2
Rd
Figure 9.6
Example of crystal resonator connection
Figure 9.7 shows an equivalent circuit of the crystal resonator.
CL
RS
L
XTAL
EXTAL
C0
Figure 9.7
9.3.2
Equivalent circuit of the crystal resonator
External Clock Input
Figure 9.8 shows an example connection to an external clock input. To operate the oscillator with an external clock
signal, set the MOMCR.MOSEL bit to 1. The XTAL pin is the function that is set in PFS.P213PFS.
External clock input
EXTAL
P213 (XTAL)
Figure 9.8
9.3.3
Port
Equivalent circuit for external clock
Notes on External Clock Input
The frequency of the external clock input can only be changed when the main clock oscillator is stopped. Do not change
the frequency of the external clock input when the Main Clock Oscillator Stop bit (MOSCCR.MOSTP) is 0.
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9.4
9. Clock Generation Circuit
Sub-Clock Oscillator
The only way of supplying a clock signal to the sub-clock oscillator is by connecting a crystal oscillator.
9.4.1
Connecting a 32.768-kHz Crystal Resonator
To supply a clock to the sub-clock oscillator, connect a 32.768-kHz crystal resonator as shown in Figure 9.9. A damping
resistor (Rd) can be added, if required. Because the resistor values vary according to the resonator and the oscillation
drive capability, use values recommended by the resonator manufacturer. If the manufacturer recommends using an
external feedback resistor (Rf), insert an Rf between XCIN and XCOUT by following the instructions.
When connecting a resonator to supply the clock, the frequency of the resonator must be in the frequency range of the
resonator for the sub-clock oscillator as described in Table 9.1.
C1
XCIN
Rf
XCOUT
Rd
Figure 9.9
C2
Connection example of 32.768-kHz crystal resonator
Figure 9.10 shows an equivalent circuit for the 32.768-kHz crystal resonator.
CS
RS
LS
XCIN
XCOUT
C0
Figure 9.10
9.4.2
Equivalent circuit for the 32.768-kHz crystal resonator
Handling of Pins When the Sub-Clock Oscillator Is Not Used
When the sub-clock oscillator is not in use, connect the XCIN pin to VSS through a resistor (to pull VSS down) and
leave the XCOUT pin open as shown in Figure 9.11. In addition, if an oscillator is not connected, set the Sub-clock
Oscillator Stop bit (SOSCCR.SOSTP) to 1 to stop the oscillator.
XCIN
XCOUT
Figure 9.11
Open
Pin handling when the sub-clock oscillator is not used
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9.5
9. Clock Generation Circuit
Oscillation Stop Detection Function
9.5.1
Oscillation Stop Detection and Operation after Detection
The oscillation stop detection function detects the main clock oscillator stop. When an oscillation stop is detected, the
system clock switches as follows:
If an oscillation stop is detected with SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC), the system
clock source switches to the MOCO clock.
If an oscillation stop is detected with PLLCCR.PLSRCSEL = 0 (PLL source clock = MOSC) and
SCKSCR.CKSEL[2:0] = 101b (system clock source = PLL), the PLL clock remains as the system clock source. The
frequency becomes a free-running oscillation frequency, and the setting of SCKSCR.CKSEL[2:0] bits does not
change.
An oscillation stop detection interrupt request can be generated when an oscillation stop is detected. In addition, the
General PWM Timer (GPT) output can be forced to a high-impedance state on detection.
The main clock oscillation stop is detected when the input clock remains at 0 or 1 for a certain period, for example, when
a malfunction occurs in the main clock oscillator. See section 55, Electrical Characteristics.
Switching between the main clock oscillator and the MOCO clock or between the PLL clock and the PLL free-running
clock is controlled by the Oscillation Stop Detection flag (OSTDSR.OSTDF).
The OSTDF flag controls the switched clock as follows:
When SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC):
When OSTDF changes from 0 to 1, the clock source switches to the MOCO clock.
When OSTDF changes from 1 to 0, the clock source switches to MOSC again.
When PLLCCR.PLSRCSEL = 0 (PLL source clock = MOSC) and SCKSCR.CKSEL[2:0] = 101b (system clock
source = PLL)
When OSTDF changes from 0 to 1, the clock source switches to the PLL free-running oscillation clock.
When OSTDF changes from 1 to 0, the clock source switches to PLL again.
To switch the clock source to the main clock oscillator or PLL clock again after oscillation stop detection, set the
CKSEL[2:0] bits to a clock source other than the main clock oscillator or PLL clock, and clear the OSTDF flag to 0.
Also, check that the OSTDF flag is not 1, and then set the CKSEL[2:0] bits to the main clock oscillator or PLL clock
after the specified oscillation stabilization time elapses.
After a reset release, the main clock oscillator is stopped and the oscillation stop detection function is disabled. To enable
the oscillation stop detection function, activate the main clock oscillator and write 1 to the Oscillation Stop Detection
Function Enable bit (OSTDCR.OSTDE) after the specified oscillation stabilization time elapses.
The oscillation stop detection function detects when the main clock oscillator is stopped by an external cause. This
means that the oscillation stop detection function must be disabled before the main clock oscillator is stopped by
software or before entering Software Standby or Deep Software Standby mode.
The oscillation stop detection function switches the following clocks to the MOCO clock (when the system clock is
MOSC) or the PLL free-running clock (when the system clock is PLL):
All clocks that can be selected as the MOSC clock or PLL except CLKOUT
The system clock (ICLK) frequency during MOCO operation (when the system clock is MOSC) or PLL freerunning operation (when the system clock is PLL) is specified in the MOCO oscillation frequency and the division
ratio set in the System Clock Select bits (SCKDIVCR.ICK[2:0]).
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9. Clock Generation Circuit
Example of returning from oscillation stop detection when CKSEL[2:0] =
011b (selecting the main clock oscillator)
Start (oscillation stop is detected)
Switch to clock source other than MOSC or
PLL
Example: Switch to SCKSCR.CKSEL[2:0] =
001b (selecting MOCO)
Set OSTDCR.OSTDIE = 0
Read OSTDSR.OSTDF = 1
Yes
Set OSTDSR.OSTDF = 0
OSTDSR.OSTDF = 0?
No
Try again?
Yes
Wait for the specified oscillation stabilization
time
Switch to SCKSCR.CKSEL[2:0] = 011b
(selecting the main clock oscillator)
End
Note:
Figure 9.12
9.5.2
No
On returning from the oscillation-stopped state, the factor responsible for stopping the main clock oscillator
must be removed from the system to allow oscillation to resume.
Flow of recovery on detection of oscillator stop
Oscillation Stop Detection Interrupts
An oscillation stop detection interrupt (MOSC_STOP) is generated when the Oscillation Stop Detection flag
(OSTDSR.OSTDF) is 1 and the Oscillation Stop Detection Interrupt Enable bit in the Oscillation Stop Detection Control
Register (OSTDCR.OSTDIE) is 1 (enabled). The Port Output Enable for GPT (POEG) is notified of the main clock
oscillator stop. On receiving the notification, the POEG sets the Oscillation Stop Detection Flag in the POEG Group n
Setting Register (POEGGn.OSTPF) to 1 (n = A, B).
After the oscillation stop is detected, wait at least 10 PCLKB cycles before writing to the POEGGn.OSTPF flag. When
the OSTDSR.OSTDF flag requires clearing, do so after clearing the Oscillation Stop Detection Interrupt Enable bit in the
Oscillation Stop Detection Control Register (OSTDCR.OSTDIE). Wait for at least 2 PCLKB clock cycles before setting
the OSTDCR.OSTDIE bit to 1 again. Depending on the number of cycles required to read a given I/O register, a longer
PCLKB wait time might be required.
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9. Clock Generation Circuit
The oscillation stop detection interrupt is a non-maskable interrupt. Because non-maskable interrupts are disabled in the
initial state after a reset release, enable non-maskable interrupts through software before using oscillation stop detection
interrupts. For details, see section 14, Interrupt Controller Unit (ICU).
9.6
PLL Circuit
The PLL circuit provides a function for multiplying the frequency from the oscillator.
9.7
Internal Clock
Clock sources for the internal clock signals include:
Main clock oscillator
Sub-clock oscillator
HOCO clock
MOCO clock
LOCO clock
PLL clock
Dedicated clock for the IWDT
External clock for JTAG.
The following internal clocks are produced from these sources:
Operating clock for the CPU, DMAC, DTC, flash memory, and SRAM — system clock (ICLK)
Operating clocks for peripheral modules — PCLKA, PCLKB, PCLKC, and PCLKD
Operating clock for the flash interface — FCLK
Clock for the external bus controller and external pin output — EBCLK
Clock for the external bus controller and external pin output for the SDRAM — SDCLK
Operating clock for the USBFS — UCLK
Operating clock for the CAN — CANMCLK
Operating clock for the CAC — CACCLK
Operating clock for the RTC LOCO clock — RTCLCLK
Operating clock for the RTC sub-clock — RTCSCLK
Operating clock for the IWDT — IWDTCLK
Operating clock for the AGT LOCO clock — AGTLCLK
Operating clock for the AGT sub-clock — AGTSCLK
Operating clock for the SysTick timer — SYSTICCLK
Clock for external pin output — CLKOUT
Operating clock for the JTAG — JTAGTCK.
For details on the registers used to set the frequencies of the internal clocks, see section 9.7.1, System Clock (ICLK) to
section 9.7.14, JTAG Clock (JTAGTCK). If the value of any of these bits is changed, subsequent operation is at the
frequency determined by the new value.
9.7.1
System Clock (ICLK)
The system clock, ICLK, is the operating clock for the CPU, DMAC, DTC, flash memory, and SRAM. Specify the
frequency in the following bits:
ICK[2:0] bits in SCKDIVCR
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9. Clock Generation Circuit
CKSEL[2:0] bits in SCKSCR
PLLMUL[5:0] and PLIDIV[1:0] bits in PLLCCR
HOCOFRQ[1:0] bits in OFS1.
When the ICLK clock source is switched, the duration of the ICLK clock cycle becomes longer during the clock source
transition period. See Figure 9.13 and Figure 9.14.
SCKSCR.CKSEL[2:0]
Main clock oscillator
Sub-clock oscillator
Selected clock
1/1
1/2
1/4
1/8
1/16
1/32
1/64
Selector
LOCO
Selector
HOCO
MOCO
SCKDIVCR.ICK[2:0]
Frequency
divider
System clock (ICLK)
PLL
Selector
SCKDIVCR.PCKx[2:0]
Figure 9.13
Peripheral module clock (PCLKx)
Clock source selector block diagram
SCKCR.CKSEL[2:0]
Source A
Source B
ta
ICLK
(SCKDIVCR.ICK[2:0] = 000b)
Clock source A
Clock source B
tb
Selected clock
PCLKB
(SCKDIVCR.PCKB[2:0] = 001b)
ta (maximum):
tb (maximum):
Source A:
Source B:
Figure 9.14
9.7.2
2 ICLK and 3 clock cycles of source A
3.5 clock cycles of source B
Clock source before the switch
Clock source after the switch
Clock source switching timing diagram
Peripheral Module Clock (PCLKA, PCLKB, PCLKC, PCLKD)
The peripheral module clocks, PCLKA, PCLKB, PCLKC, and PCLKD, are the operating clocks for the peripheral
modules. Specify the frequency in the following bits:
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PCKA[2:0], PCKB[2:0], PCKC[2:0], and PCKD[2:0] bits in SCKDIVCR
CKSEL[2:0] bits in SCKSCR
PLLMUL[5:0] and PLIDIV[1:0] bits in PLLCCR
HOCOFRQ[1:0] bits in OFS1.
When the clock source of the peripheral module clock is switched, the duration of the peripheral module clock cycle
becomes longer during the clock source transition period. See Figure 9.13 and Figure 9.14.
9.7.3
Flash Interface Clock (FCLK)
The flash interface clock, FCLK, is the operating clock for the flash memory interface. In addition to reading from the
data flash, it is used for the programming and erasure of the code flash and data flash. Specify the frequency in the
following bits:
FCK[2:0] bits in SCKDIVCR
CKSEL[2:0] bits in SCKSCR
PLLMUL[5:0] and PLIDIV[1:0] bits in PLLCCR
HOCOFRQ[1:0] bits in OFS1.
9.7.4
External Bus Clock (BCLK)
The external bus clock, BCLK, is an operating clock for the external bus controller. It is also output externally from the
EBCLK pin for the external connection bus. To output BCLK from the EBCLK pin, set the EBCKOCR.EBCKOEN bit
to 1 and set the PmnPFS.PSEL[4:0] bits to 01011b. Only change the PmnPFS.PSEL[4:0] bits to 01011b when the
EBCKOCR.EBCKOEN bit is 0. When the BCKCR.BCLKDIV bit is 1, the BCLK clock divided by 2 is output from the
EBCLK pin. Specify the frequency in the following bits:
BCK[2:0] bits in SCKDIVCR
CKSEL[2:0] bits in SCKSCR
PLLMUL[5:0] and PLIDIV[1:0] bits in PLLCCR
HOCOFRQ[1:0] bits in OFS1.
Do not set BCLK to a frequency higher than that of the system clock (ICLK).
9.7.5
SDRAM Clock (SDCLK)
The SDRAM clock, SDCLK, is an operating clock for the external bus controller. It is output externally from the
SDCLK pin for the SDRAM that is connected to the external bus. To output SDCLK on the SDCLK pin, set the
SDCKOCR.SDCKOEN bit to 1 and set the PmnPFS.PSEL[4:0] bits to 01011b (enabling SDCLK output). Only change
the value in the PmnPFS.PSEL[4:0] bits when the SDCKOCR.SDCKOEN bit is 0. Specify the frequency in the
following bits:
SCKDIVCR.BCK[2:0], SCKSCR.CKSEL[2:0], PLLMUL[5:0], and PLIDIV[1:0] bits in PLLCCR
HOCOFRQ[1:0] bits in OFS1.
Do not set SDCLK to a frequency higher than that of the system clock (ICLK).
9.7.6
USB Clock (UCLK)
The USB clock, UCLK, is the operating clock for the USBFS module. A 48-MHz clock must be supplied to the USBFS
module. When the module is used, the UCLK clock must be specified as 48 MHz. Specify the frequency in the following
bits:
UCK[2:0] bits in SCKDIVCR2
CKSEL[2:0] bits in SCKSCR
PLLMUL[5:0] and PLIDIV[1:0] bits in PLLCCR.
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9.7.7
9. Clock Generation Circuit
CAN Clock (CANMCLK)
The CAN clock, CANMCLK, is the operating clock for the CAN module. CANMCLK is generated by the main clock
oscillator.
9.7.8
CAC Clock (CACCLK)
The CAC clock, CACCLK, is the operating clock for the CAC. CACCLK is generated by the following oscillators:
Main clock oscillator
Sub-clock oscillator
High-speed clock oscillator (HOCO)
Middle-speed clock oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator.
9.7.9
RTC-Dedicated Clock (RTCSCLK, RTCLCLK)
The RTC-dedicated clocks, RTCSCLK and RTCLCLK, are the operating clocks for the RTC. RTCSCLK is generated by
the sub-clock oscillator and RTCLCLK by the LOCO clock.
9.7.10
IWDT-Dedicated Clock (IWDTCLK)
The IWDT-dedicated clock, IWDTCLK, is the operating clock for the IWDT. IWDTCLK is internally generated by the
IWDT-dedicated on-chip oscillator.
9.7.11
AGT-Dedicated Clock (AGTSCLK, AGTLCLK)
The AGT-dedicated clocks, AGTSCLK and AGTLCLK, are the operating clocks for the AGT. AGTSCLK is generated
by the sub-clock oscillator and AGTLCLK is generated by the LOCO clock.
9.7.12
SysTick Timer-Dedicated Clock (SYSTICCLK)
The SysTick timer-dedicated clock, SYSTICCLK, is the operating clock for the SYSTICCLK. SYSTICCLK is
generated by the LOCO clock.
9.7.13
Clock/Buzzer Output Clock (CLKOUT)
The CLKOUT is output externally from the CLKOUT pin for the clock or buzzer output. CLKOUT is output to the
CLKOUT pin when CKOCR.CKOEN is set to 1. Only change the value in the CKODIV[2:0] or CKOSEL[2:0] bits in
CKOCR when the CKOCR.CKOEN bit is 0. Specify the frequency in the following bits:
CKODIV[2:0] or CKOSEL[2:0] bits in CKOCR
HOCOFRQ[1:0] bits in OFS1.
9.7.14
JTAG Clock (JTAGTCK)
The JTAG-dedicated clock, JTAGTCK, is the operating clock for the JTAG. JTAGTCK is generated by the external clock
for JTAG (TCK).
9.8
9.8.1
Usage Notes
Notes on Clock Generation Circuit
The frequencies of the system clock (ICLK), peripheral module clock (PCLKA to PCLKD), flash interface clock
(FCLK), external bus clock (BCLK), and SDRAM clock (SDCLK) supplied to each module change according to the
settings in SCKDIVCR. Each frequency must meet the following conditions:
Each frequency must be selected within the operation-guaranteed range of the clock cycle time (tcyc) specified in
the AC electrical characteristics, see section 55, Electrical Characteristics
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The frequencies must not exceed the ranges listed in Table 9.2
The peripheral modules operate on PCLKB and PCLKA. As a result, the operating speed of modules such as the
timer and SCI is different before and after the frequency is changed.
The system clock (ICLK), peripheral module clock (PCLKA to PCLKD), flash interface clock (FCLK), and
external bus clock (BCLK) must be set as shown in Table 9.2.
Do not change the clock frequency during external bus access. Additionally, when access by the external bus starts after
a change to the clock frequency, only access by the bus after confirming that the change to the frequencies is complete.
To ensure correct processing after the clock frequency changes, first write to the relevant Clock Control Register to
change the frequency, then read the value from the register, and finally perform the subsequent processing.
9.8.2
Notes on the Resonator
Because the resonator characteristics relate closely to your board design, adequate evaluation is required before use. See
the resonator connection example in Figure 9.9. The circuit constants for the resonator depend on the resonator to be used
and the stray capacitance of the mounting circuit. Always consult the resonator manufacturer when determining the
circuit constants. The voltage to be applied between the resonator pins must be within the absolute maximum rating.
9.8.3
Notes on Board Design
When using a crystal resonator, place the resonator and its load capacitors as close to the XTAL and EXTAL pins as
possible. Route other signal lines away from the oscillation circuit, as shown in Figure 9.15, to prevent electromagnetic
induction from interfering with correct oscillation.
Prohibited
Signal A
Signal B
Prohibited
MCU
CL2
XTAL
EXTAL
CL1
Figure 9.15
9.8.4
Notes on board design for oscillation circuit (applies to the sub-clock oscillator for the main
clock oscillator)
Notes on the Resonator Connect Pin
When the main clock oscillator is not used, the EXTAL and XTAL pins can be used as general ports P212 and P213.
When these pins are used as general ports, the main clock oscillator must be stopped (MOSCCR.MOSTP must be set to
1).
9.8.5
Notes on Using Sub-Clock Oscillator for LGA Packages
The output of the P212 (EXTAL), P213 (XTAL), and P704 pins may affect the oscillation by the sub-clock oscillator.
If the sub-clock oscillator is used, implement the board design so as not to affect the oscillation. Renesas strongly
recommends setting the DSCR[1:0] bits to 00b or 01b when using P212 (EXTAL), P213 (XTAL), and P704 as output
pins and using the sub-clock oscillator.
In addition, when using the sub-clock oscillator in middle drive capability (SOMCR.SODRV1 = 1), Renesas
recommends not to use two or more ports of P212 (EXTAL), P213 (XTAL), and P704 simultaneously as output pins to
avoid affecting the oscillation.
9.8.6
Notes on the Main Clock Oscillator Drive Capability Auto Switching Function
The drive capability auto switching function lowers the main clock oscillator drive capability automatically after the
main clock oscillator starts and suppresses the EMI associated with the main clock oscillator.
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To enable drive capability auto switching, set MOMCR.AUTODRVEN to 1 when the main clock oscillator is stopped
(MOSCCR.MOSTP = 1). Regardless of the MOMCR.AUTODRVEN setting, the Drive Capability Switching register
(MOMCR.MODRV0[1:0]) must be set properly according to the selected oscillator. Next, enable the main clock
oscillator (MOSCCR.MOSTP = 0). After the Oscillation Stabilization flag (OSCSF.MOSCSF) becomes 1, the main
clock can be used.
EMI suppression is gained in return for an extension in the oscillation stabilization wait time. For more information, see
section 9.2.18, Main Clock Oscillator Wait Control Register (MOSCWTCR).
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10. Clock Frequency Accuracy Measurement Circuit (CAC)
10.
Clock Frequency Accuracy Measurement Circuit (CAC)
10.1
Overview
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement
target clock) within the time generated by the clock selected as a measurement reference (measurement reference clock),
and determines the accuracy depending on whether the number of pulses is within the allowable range.
The reference clock can be provided externally through an I/O port pin or internally from various on-chip oscillators.
Interrupt signals can be generated when the clock does not match or measurement ends. This feature is useful in
implementing a fail-safe mechanism for home and industrial automation applications.
Table 10.1 lists the CAC specifications, Figure 10.1 shows a block diagram, and Table 10.2 describes the I/O pin.
Table 10.1
CAC specifications
Parameter
Specifications
Measurement target clocks
Frequency can be measured for:
Main clock oscillator
Sub-clock oscillator
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B (PCLKB).
Measurement reference clocks
Frequency can be referenced to:
External clock input to the CACREF pin
Main clock oscillator
Sub-clock oscillator
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B (PCLKB).
Selectable function
Digital filter
Interrupt sources
Measurement end
Frequency error
Overflow.
Module-stop function
Module-stop state can be set to reduce power consumption
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10. Clock Frequency Accuracy Measurement Circuit (CAC)
DFS[1:0]
CACREFE
CACREF pin
DFS[1:0]
Digital filter
RSCS[2:0]
RCDS[1:0]
EDGES[1:0]
Frequency
dividing circuit
1/32
Reference
signal
generation
clock select
circuit
FMCS[2:0]
Main clock
Sub clock
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B
(PCLKB)
1/128
1/8192
Valid edge signal
TCSS[1:0]
Frequency
measurement
clock
Frequency
dividing circuit
Frequency
measurement
clock select
circuit
1/4
1/8
Table 10.2
CFME
Count source
clock
16-bit counter
Overflow interrupt request
1/32
CACNTBR
CAULVR
CALLVR
Measurement end interrupt
request
Frequency error interrupt
request
CAICR
CASTR
Internal peripheral bus
CAC block diagram
CAC I/O pin
Pin name
I/O
Function
CACREF
Input
Measurement reference clock input pin
10.2
Interrupt control
circuit
Comparator
CFME: Bit in CACR0
CACREFE, FMCS[2:0], TCSS[1:0], EDGES[1:0]: Bits in CACR1
RPS, RSCS[2:0], RCDS[1:0], DFS[1:0]: Bits in CACR2
CAICR: CAC Interrupt Control Register
CASTR: CAC Status Register
CAULVR: CAC Upper-Limit Value Setting Register
CALLVR: CAC Lower-Limit Value Setting Register
CACNTBR: CAC Counter Buffer Register
Figure 10.1
Edge detection
circuit
RPS
1/1024
Register Descriptions
10.2.1
CAC Control Register 0 (CACR0)
Address(es): CAC.CACR0 4004 4600h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
CFME
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CFME
Clock Frequency Measurement Enable
0: Disable
1: Enable.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CFME bit (Clock Frequency Measurement Enable)
The CFME bit enables the clock frequency measurement. Read the CFME bit to confirm that the bit value has changed.
Additional write accesses are ignored before the change is complete.
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10.2.2
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Control Register 1 (CACR1)
Address(es): CAC.CACR1 4004 4601h
b7
b6
EDGES[1:0]
Value after reset:
0
0
b5
b4
b3
TCSS[1:0]
0
0
b2
b1
b0
CACRE
FE
FMCS[2:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CACREFE
CACREF Pin Input Enable
0: Disable
1: Enable.
R/W
b3 to b1
FMCS[2:0]
Measurement Target Clock Select
b3
R/W
b5, b4
TCSS[1:0]
Measurement Target Clock
Frequency Division Ratio Select
b5 b4
R/W
b7, b6
EDGES[1:0]
Valid Edge Select
b7 b6
R/W
Note:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b1
0: Main clock oscillator
1: Sub-clock oscillator
0: HOCO clock
1: MOCO clock
0: LOCO clock
1: Peripheral module clock (PCLKB)
0: IWDTCLK clock
1: Setting prohibited.
0: No division
1: ×1/4 clock
0: ×1/8 clock
1: ×1/32 clock.
0: Rising edge
1: Falling edge
0: Both rising and falling edges
1: Setting prohibited.
Set the CACR1 register when the CACR0.CFME bit is 0.
CACREFE bit (CACREF Pin Input Enable)
The CACREFE bit enables the CACREF pin input.
FMCS[2:0] bits (Measurement Target Clock Select)
The FMCS[2:0] bits select the clock for which the frequency is to be measured.
TCSS[1:0] bits (Measurement Target Clock Frequency Division Ratio Select)
The TCSS[1:0] bits select the division ratio of the measurement target clock.
EDGES[1:0] bits (Valid Edge Select)
The EDGES[1:0] bits select the valid edge for the reference signal.
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10.2.3
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Control Register 2 (CACR2)
Address(es): CAC.CACR2 4004 4602h
b7
Value after reset:
b6
b5
b4
DFS[1:0]
RCDS[1:0]
0
0
0
0
b3
b2
b1
b0
RSCS[2:0]
0
0
RPS
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPS
Reference Signal Select
0: CACREF pin input
1: Internal clock (internally generated signal).
R/W
b3 to b1
RSCS[2:0]
Measurement Reference Clock
Select
b3
R/W
b5, b4
RCDS[1:0]
Measurement Reference Clock
Frequency Division Ratio Select
b5 b4
R/W
b7, b6
DFS[1:0]
Digital Filter Select
b7 b6
R/W
Note:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b1
0: Main clock oscillator
1: Sub-clock oscillator
0: HOCO clock
1: MOCO clock
0: LOCO clock
1: Peripheral module clock (PCLKB)
0: IWDTCLK clock
1: Setting prohibited.
0: ×1/32 clock
1: ×1/128 clock
0: ×1/1024 clock
1: ×1/8192 clock.
0 0: Disable digital filtering
0 1: Use sampling clock for the digital filter as the frequency
measuring clock
1 0: Use sampling clock for the digital filter as the frequency
measuring clock divided by 4
1 1: Use sampling clock for the digital filter as the frequency
measuring clock divided by 16.
Set the CACR2 register when the CACR0.CFME bit is 0.
RPS bit (Reference Signal Select)
The RPS bit selects whether to use the CACREF pin input or an internal clock (internally generated signal) as the
reference signal.
RSCS[2:0] bits (Measurement Reference Clock Select)
The RSCS[2:0] bits select the clock source for generating the measurement reference clock.
RCDS[1:0] bits (Measurement Reference Clock Frequency Division Ratio Select)
The RCDS[1:0] bits select the frequency division ratio of the measurement reference clock when an internal reference
clock is selected (RPS = 1). When RPS = 0 (CACREF pin is used as the reference clock source), the reference clock is
not divided.
DFS[1:0] bits (Digital Filter Select)
The setting of the DFS[1:0] bits enables or disables the digital filter and selects its sampling clock.
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10.2.4
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Interrupt Control Register (CAICR)
Address(es): CAC.CAICR 4004 4603h
b7
—
Value after reset:
b6
b5
b4
OVFFC MENDF FERRF
L
CL
CL
0
0
0
0
b3
—
0
b2
b1
b0
OVFIE MENDI FERRI
E
E
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FERRIE
Frequency Error Interrupt Request
Enable
0: Disable
1: Enable.
R/W
b1
MENDIE
Measurement End Interrupt
Request Enable
0: Disable
1: Enable.
R/W
b2
OVFIE
Overflow Interrupt Request Enable 0: Disable
1: Enable.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
FERRFCL
FERRF Clear
When 1 is written to this bit, the CASTR.FERRF flag is
cleared. This bit is read as 0.
R/W
b5
MENDFCL
MENDF Clear
When 1 is written to this bit, the CASTR.MENDF flag is
cleared. This bit is read as 0.
R/W
b6
OVFFCL
OVFF Clear
When 1 is written to this bit, the CASTR.OVFF flag is cleared.
This bit is read as 0.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
FERRIE bit (Frequency Error Interrupt Request Enable)
The FERRIE bit enables the frequency error interrupt request.
MENDIE bit (Measurement End Interrupt Request Enable)
The MENDIE bit enables the measurement end interrupt request.
OVFIE bit (Overflow Interrupt Request Enable)
The OVFIE bit enables the overflow interrupt request.
FERRFCL bit (FERRF Clear)
Setting the FERRFCL bit to 1 clears the CASTR.FERRF flag.
MENDFCL bit (MENDF Clear)
Setting the MENDFCL bit to 1 clears the CASTR.MENDF flag.
OVFFCL bit (OVFF Clear)
Setting the OVFFCL bit to 1 clears the CASTR.OVFF flag.
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10.2.5
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Status Register (CASTR)
Address(es): CAC.CASTR 4004 4604h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
OVFF MENDF FERRF
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FERRF
Frequency Error Flag
0: Clock frequency is within the allowable range
1: Clock frequency has deviated beyond the allowable range
(frequency error).
R
b1
MENDF
Measurement End Flag
0: Measurement is in progress
1: Measurement ended.
R
b2
OVFF
Overflow Flag
0: Counter has not overflowed
1: Counter overflowed.
R
b7 to b3
—
Reserved
These bits are read as 0
R
FERRF flag (Frequency Error Flag)
The FERRF flag indicates a deviation of the clock frequency from the set value (frequency error).
[Setting condition]
The clock frequency is outside the allowable range defined in the CAULVR and CALLVR registers.
[Clearing condition]
1 is written to the FERRFCL bit.
MENDF flag (Measurement End Flag)
The MENDF flag indicates the end of measurement.
[Setting condition]
Measurement completes.
[Clearing condition]
1 is written to the MENDFCL bit.
OVFF flag (Overflow Flag)
The OVFF flag indicates that the counter overflowed.
[Setting condition]
The counter overflows.
[Clearing condition]
1 is written to the OVFFCL bit.
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10.2.6
10. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Upper-Limit Value Setting Register (CAULVR)
Address(es): CAC.CAULVR 4004 4606h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CAULVR is a 16-bit read/write register that specifies the upper value of the allowable range. When the counter value
exceeds the value specified in this register, a frequency error is detected. Write to this register when the CACR0.CFME
bit is 0.
The counter value stored in CACNTBR can vary depending on the difference between the phases of the digital filter and
edge-detection circuit, and the signal on the CACREF pin. Ensure that this setting allows an adequate margin.
10.2.7
CAC Lower-Limit Value Setting Register (CALLVR)
Address(es): CAC.CALLVR 4004 4608h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CALLVR is a 16-bit read/write register that specifies the lower value of the allowable range. When the counter value
falls below the value specified in this register, a frequency error is detected. Write to this register when the
CACR0.CFME bit is 0.
The counter value stored in CACNTBR can vary depending on the difference between the phases of the digital filter and
edge-detection circuit, and the signal on the CACREF pin. Ensure that this setting allows an adequate margin.
10.2.8
CAC Counter Buffer Register (CACNTBR)
Address(es): CAC.CACNTBR 4004 460Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CACNTBR is a 16-bit read-only register that stores the measurement result.
10.3
10.3.1
Operation
Measuring Clock Frequency
The CAC measures the clock frequency using the CACREF pin input or the internal clock as a reference. Figure 10.2
shows an operating example of the CAC.
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CACREF pin or
internal clock
1
0
CFME bit in CACR0
1
0
10. Clock Frequency Accuracy Measurement Circuit (CAC)
0 is written to
CFME bit.
1 is written to
CFME bit.
Counter value
FFFFh
Counter is
cleared by writing
0 to CFME bit.
After 1 is written to CFME bit, counting
starts on the first valid edge.
CAULVR
CALLVR
0000h
Time
CACNTBR
FERRF flag in CASTR
(frequency error flag)
1
0
MENDF flag in CASTR
(measurement end flag)
1
0
0000h
7FFFh
BFFFh
1 is written to MENDFCL
bit in CAICR.
(1)
(2)
(3)
(4)
3FFFh
1 is written to FERRFCL
bit in CAICR.
1 is written to FERRFCL
bit in CAICR.
1 is written to MENDFCL
bit in CAICR.
1 is written to MENDFCL
bit in CAICR.
(5)
(6)
When the CACREF pin input is used as a reference:
In CACR1: CACREFE bit = 1, EDGES[1:0] bits = 00b
CAULVR register = AAAAh, CALLVR register = 5555h
When the internal clock is used as a reference:
In CACR1: CACREFE bit = 0, EDGES[1:0] bits = 00b
CAULVR register = AAAAh, CALLVR register = 5555h
Figure 10.2
CAC operating example
The events in Figure 10.2 are:
1. Before writing 1 to CACR0.CFME, set CACR1 and CACR2 to define the measurement target clock and
measurement reference clock. Writing 1 to the CACR0.CFME bit enables clock frequency measurement.
2. The timer starts counting up if the valid edge selected in the CACR1.EDGES[1:0] bits is input from the
measurement reference clock. In Figure 10.2, the valid edge is a rising edge (CACR1.EDGES[1:0] = 00b).
3. When the next valid edge is input, the counter value is transferred to CACNTBR and compared with the values in
CAULVR and CALLVR. If both CACNTBR ≤ CAULVR and CACNTBR ≥ CALLVR are true, only the MENDF
flag in CASTR is set to 1, because the clock frequency is correct. If the MENDIE bit in CAICR is 1, a measurement
end interrupt is generated.
4. When the next valid edge is input, the counter value is transferred to CACNTBR and compared with the values in
CAULVR and CALLVR. If CACNTBR > CAULVR, the FERRF flag in CASTR is set to 1, because the clock
frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. The MENDF flag
in CASTR is set to 1 at the end of measurement. If the MENDIE bit in CAICR is 1, a measurement end interrupt is
generated.
5. When the next valid edge is input, the counter value is transferred to CACNTBR and compared with the values in
CAULVR and CALLVR. If CACNTBR < CALLVR, the FERRF flag in CASTR is set to 1, because the clock
frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. The MENDF flag
in CASTR is set to 1 at the end of measurement. If the MENDIE bit in CAICR is 1, a measurement end interrupt is
generated.
6. When the CFME bit in CACR0 is 1, the counter value is transferred to CACNTBR and compared with the values in
CAULVR and CALLVR every time a valid edge is input. Writing 0 to the CFME bit in CACR0 clears the counter
and stops up-counting.
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10.3.2
10. Clock Frequency Accuracy Measurement Circuit (CAC)
Digital Filtering of Signals on CACREF Pin
The CACREF pin has a digital filter, and levels on the CACREF pin are transmitted to the internal circuitry after three
consecutive matches in the selected sampling interval. The same level continues to be transmitted internally until the
level on the pin has three consecutive matches again. Enabling or disabling of the digital filter and its sampling clock are
selectable.
The counter value transferred to CACNTBR might be in error by up to 1 cycle of the sampling clock because of the
difference between the phases of the digital filter and the signal input to the CACREF pin. When a frequency dividing
clock is selected as a count source clock, the counter value error is obtained using the following formula:
Counter value error = (1 cycle of the count source clock) / (1 cycle of the sampling clock)
10.4
Interrupt Requests
The CAC generates three types of interrupt requests:
Frequency error interrupt
Measurement end interrupt
Overflow interrupt.
When an interrupt source is generated, the associated status flag becomes 1. Table 10.3 provides information on the CAC
interrupt requests.
Table 10.3
CAC interrupt requests
Interrupt request
Interrupt enable bit
Status flag
Interrupt sources
Frequency error
interrupt
CAICR.FERRIE
CASTR.FERRF
The result of comparing CACNTBR with CAULVR and CALLVR
is either CACNTBR > CAULVR or CACNTBR < CALLVR
Measurement end
interrupt
CAICR.MENDIE
CASTR.MENDF
Valid edge is input from the CACREF pin or internal clock
Measurement end interrupt does not occur at the first valid
edge after writing 1 to the CACR0.CFME bit.
Overflow interrupt
CAICR.OVFIE
CASTR.OVFF
The counter overflows
10.5
10.5.1
Usage Notes
Settings for the Module-Stop Function
The Module Stop Control Register C (MSTPCRC) can enable or disable CAC operation. The CAC module is initially
stopped after reset. Releasing the module-stop state enables access to the registers. For details, see section 11, Low
Power Modes.
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11. Low Power Modes
11.
Low Power Modes
11.1
Overview
The MCU provides several functions for reducing power consumption, such as setting clock dividers, controlling
EBCLK output, controlling SDCLK output, stopping modules, selecting power control mode in normal mode, and
transitioning to low power modes.
Table 11.1 lists the specifications of the low power mode functions. Table 11.2 lists the conditions to transition to low
power modes, the states of the CPU and peripheral modules, and the method for canceling each mode. After a reset, the
MCU enters the program execution state, but only the DMAC, DTC, and SRAM operate.
Table 11.1
Specifications of the low power mode functions
Parameter
Specifications
Reducing power consumption by
switching clock signals
Frequency division ratio independently selectable for the system clock (ICLK), peripheral module
clocks (PCLKA, PCLKB, PCLKC, PCLKD), external bus clock (BCLK), and flash interface clock
(FCLK)*1
EBCLK output control
Selectable to BCLK output or high-level output
SDCLK output control
Selectable to SDCLK output or high-level output
Module-stop state
Peripheral module functions can be stopped independently
Low power modes
Power control modes
Power consumption can be reduced in Normal, Sleep, and Snooze modes by selecting an
appropriate operating power control mode according to the operating frequency and voltage.
Available operating power control modes:
High-speed mode
Low-speed mode
Subosc-speed mode.
Note 1.
Sleep mode
Software Standby mode
Snooze mode
Deep Software Standby mode.
For details, see section 9, Clock Generation Circuit.
Table 11.2
Operating conditions of each low power mode (1 of 3)
Software Standby
mode
Snooze mode*1
Deep Software
Standby mode
Parameter
Sleep mode
Transition condition
WFI instruction while
SBYCR.SSBY = 0
WFI instruction while
SBYCR.SSBY = 1 and
DPSBYCR.DPSBY = 0
Snooze request trigger
in Software Standby
mode.
SNZCR.SNZE = 1
WFI instruction while
SBYCR.SSBY = 1 and
DPSBYCR.DPSBY = 1
Canceling method
All interrupts.
Any reset available in the
mode.
Interrupts shown in Table
11.3. Any reset available
in the mode.
Interrupts shown in Table
11.3. Any reset available
in the mode.
Interrupts shown in Table
11.3. Any reset available
in the mode.
State after cancellation
by an interrupt
Program execution state
(interrupt processing)
Program execution state
(interrupt processing)
Program execution state
(interrupt processing)
Reset state
State after cancellation
by a reset
Reset state
Reset state
Reset state
Reset state
Main clock oscillator
Selectable
Stop
Selectable*2
Stop
Sub-clock oscillator
Selectable
Selectable
Selectable
Selectable
High-speed on-chip
oscillator
Selectable
Stop
Selectable
Stop
Middle-speed on-chip
oscillator
Selectable
Stop
Selectable
Stop
Low-speed on-chip
oscillator
Selectable
Selectable
Selectable
Selectable*3
IWDT-dedicated on-chip
oscillator
Selectable*7
Selectable*7
Selectable*7
Stop
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Table 11.2
11. Low Power Modes
Operating conditions of each low power mode (2 of 3)
Parameter
Sleep mode
Software Standby
mode
Snooze mode*1
Deep Software
Standby mode
PLL
Selectable
Stop
Selectable*2
Stop
Oscillation stop detection
function
Selectable
Operation prohibited
Operation prohibited
Operation prohibited
Clock/buzzer output
function
Selectable
Selectable*4
Selectable
Stop (Undefined)
External Bus (EBCLK)
Selectable
Stop (Retained)
Operation prohibited
Stop (Retained)
CPU
Stop (Retained)
Stop (Retained)
Stop (Retained)
Stop (Undefined)
SRAM0, SRAMHS,
ECC SRAM
Selectable
Stop (Retained)
Selectable
Stop (Undefined)
Standby SRAM
Selectable
Stop (Retained)
Selectable
Stop
(Retained/Undefined)*5
Flash memory
Operating
Stop (Retained)
Stop (Retained)
Stop (Retained)
DMA Controller (DMAC)
Selectable
Stop (Retained)
Operation prohibited
Stop (Undefined)
Data Transfer Controller
(DTC)
Selectable
Stop (Retained)
Selectable
Stop (Undefined)
USB 2.0 Full-Speed
Module (USBFS)
Selectable
Stop (Retained).
Detection of USB
resumption is possible.
Operation prohibited.
Detection of USB
resumption is possible.
Stop
(Retained/Undefined)
Detection of USB
resumption is possible.*6
Watchdog Timer (WDT)
Selectable*7
Stop (Retained)
Stop (Retained)
Stop (Undefined)
Independent Watchdog
Timer (IWDT)
Selectable*7
Selectable*7
Selectable *7
Stop (Undefined)
Realtime clock (RTC)
Selectable
Selectable
Selectable
Selectable*8
Asynchronous General
Purpose Timer (AGTn, n
= 0, 1)
Selectable
Selectable*9
Selectable*9
Selectable*9
12-bit A/D Converter
(ADC12)
Selectable
Stop (Retained)
Selectable*18
Stop (Undefined)
12-bit D/A Converter
(DAC12)
Selectable
Stop (Retained)
Selectable
Stop (Undefined)
Capacitive Touch
Sensing Unit (CTSU)
Selectable
Stop (Retained)
Selectable
Stop (Undefined)
Data Operation Circuit
(DOC)
Selectable
Stop (Retained)
Selectable
Stop (Undefined)
Serial Communications
Interface (SCI0)
Selectable
Stop (Retained)
Selectable
(RXD0 falling edge is
available, to enter
Snooze mode) (only in
asynchronous mode).*14
Stop (Undefined)
Serial Communications
Interface (SCIn, n = 1 to
9)
Selectable
Stop (Retained)
Operation prohibited
Stop (Undefined)
I2C Bus Interface (IIC0)
Selectable
Selectable*13
Selectable*13
Stop (Undefined)
I2C Bus Interface (IICn, n
= 1, 2)
Selectable
Stop (Retained)
Operation prohibited
Stop (Undefined)
Event Link Controller
(ELC)
Selectable
Stop (Retained)
Selectable*10
Stop (Undefined)
High-Speed Analog
Comparator (ACMPHS0)
Selectable
Selectable*12
Selectable.
VCOUT function only.*12
Stop (Undefined)
High-Speed Analog
Comparator (ACMPHSn,
n = 1 to 5)
Selectable
Selectable*11
Selectable.
VCOUT function only.*11
Stop (Undefined)
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Table 11.2
11. Low Power Modes
Operating conditions of each low power mode (3 of 3)
Parameter
Sleep mode
Software Standby
mode
Snooze mode*1
Deep Software
Standby mode
IRQn (n = 0 to 15) pin
interrupt
Selectable
Selectable
Selectable
Stop (Undefined)
NMI, IRQn-DS (n = 0 to
13) pin interrupt
Selectable
Selectable
Selectable
Selectable
Key Interrupt Function
(KINT)
Selectable
Selectable
Selectable
Stop (Undefined)
Low voltage detection
(LVD)
Selectable
Selectable
Selectable
Selectable*15
Power-on reset circuit
Operating
Operating
Operating
Operating*16
Other peripheral
modules
Selectable
Stop (Retained)
Operation prohibited
Stop (Undefined)
I/O ports
Operating
Retained*17
Operating
Retained*17
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
Note 10.
Note 11.
Note 12.
Note 13.
Note 14.
Note 15.
Note 16.
Note 17.
Note 18.
Selectable means that operating or not operating can be selected in the control registers.
Stop (Retained) means that the contents of the internal registers are retained but the operations are suspended.
Operation prohibited means that the function must be stopped before entering Software Standby mode.
Stop (Undefined) means that the contents of the internal registers are undefined and power to the internal circuit is cut off.
All modules whose module-stop bits are 0 start as soon as PCLKs are supplied after entering Snooze mode. To avoid an
increase in power consumption in Snooze mode, set the module-stop bit of modules that are not required in Snooze mode to 1
before entering Software Standby mode.
When using SCI0 in Snooze mode, the MOSCCR.MOSTP and PLLCR.PLLSTP bits must be 1.
If the DPSBYCR.DEEPCUT[1:0] bits are 00b, the oscillator status is the same as before entering Deep Software Standby
mode. When the DPSBYCR.DEEPCUT[1:0] bits are not 00b, the oscillator stops when the MCU enters Deep Software Standby
mode.
Stopped when the clock output source select bits (CKOCR.CKOSEL[2:0]) are set to a value other than 010b (LOCO) and 100b
(SOSC).
If the DPSBYCR.DEEPCUT[1:0] bits are 00b, data in the Standby SRAM is retained in Deep Software Standby mode. When
the DPSBYCR.DEEPCUT[1:0] bits are not 00b, data in the Standby SRAM is undefined in Deep Software Standby mode.
If the DPSBYCR.DEEPCUT[1:0] bits are 00b, the values of the USB resume detection circuit registers are retained and
detection of USB resumption is enabled, and the values of other registers are undefined in Deep Software Standby mode.
When the DPSBYCR.DEEPCUT[1:0] bits are not 00b, the values of all registers are undefined in Deep Software Standby
mode.
In IWDT-dedicated on-chip oscillator and IWDT, operating or stopping is selected by setting the IWDT Stop Control bit
(IWDTSTPCTL) in Option Function Select register 0 (OFS0) in IWDT auto start mode. In WDT, operating or stopping is
selected by setting the WDT Stop Control bit (WDTSTPCTL) in Option Function Select Register 0 (OFS0) in WDT auto start
mode.
When the RCR4.RCKSEL bit set to 1 (LOCO), the DPSBYCR.DEEPCUT[1:0] bits must set to 00b before entering Deep
Software Standby mode.
AGT0 operation is possible when 100b (AGTLCLK) or 110b (AGTSCLK) is selected in the AGT0.AGTMR1.TCK[2:0] bits.
AGT1 operation is possible when 100b (AGTLCLK), 110b (AGTSCLK) or 101 (underflow event signal from AGT0) is selected in
the AGT1.AGTMR1.TCK[2:0] bits.
When 100b (AGTLCLK) is selected in AGTn.AGTMR1.TCK[2:0] bits (n = 0, 1), the DPSBYCR.DEEPCUT[1:0] bits must set to
00b before entering Deep Software Standby mode.
Event lists the restrictions described in section 11.10.13, ELC Events in Snooze Mode.
Only VCOUT function is permitted. The VCOUT pin operates when ACMPHS uses no digital filter.
For details on digital filter, see section 48, High-Speed Analog Comparator (ACMPHS).
When CMPCTL0.CSTEN bit is 1, canceling Software Standby Mode or entering Snooze mode by the comparator detection is
available.
IIC0 wakeup interrupt is available.
Serial communication mode of SCI0 is asynchronous mode.
When using LVD in Deep Software Standby mode, DPSBYCR.DEEPCUT[1:0] bits must be 00b or 01b before entering Deep
Software Standby mode.
When the MCU enters Deep Software Standby mode with the DPSBYCR.DEEPCUT[1:0] bits set to 11b, the LVD circuit stops
and the low power function of the power-on reset circuit is enabled.
For the address bus and bus control signals (For SRAM: [CS0 to CS7, RD, WR0 to WR1, WR, BC0 to BC1, and ALE], and for
SDRAM: [SDCS, RAS, CAS and WE]), keeping the output state or changing to the high-impedance state can be selected in the
SBYCR.OPE bit.
When using the 12-bit A/D Converter in Snooze mode, the ADCMPCR.CMPAE and ADCMPCR.CMPBE bits must be 1.
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Table 11.3
11. Low Power Modes
Interrupt sources for canceling Snooze, Software Standby, and Deep Software Standby modes
Name
Software Standby
mode
Yes
Yes
Yes
Port
PORT_IRQn (n = 0 to 15)
Yes
Yes
No
PORT_IRQn-DS (n = 0 to 13)
Yes
Yes
Yes
LVD
LVD_LVD1
Yes
Yes
Yes
LVD_LVD2
Yes
Yes
Yes
Interrupt source
NMI
Snooze mode
Deep Software Standby
mode
IWDT
IWDT_NMIUNDF
Yes
Yes
No
USBFS
USBFS_USBR
Yes
Yes
Yes
RTC
RTC_ALM
Yes
Yes
Yes
RTC_PRD
Yes
Yes
Yes
KINT
KEY_INTKR
Yes
Yes
No
AGT1
AGT1_AGTI
Yes
Yes*3
Yes
AGT1_AGTCMAI
Yes
Yes
No
AGT1_AGTCMBI
Yes
Yes
No
ACMP_HS0
Yes
Yes
No
IIC0
IIC0_WUI
Yes
Yes
No
ADC12n
(n = 0, 1)
ADC12n_WCMPM
No
Yes with SELSR0*1,*3
No
No
Yes with
SELSR0*1,*3
No
SELSR0*1,*2
No
ACMPHS
SCI0
DTC
ADC12n_WCMPUM
SCI0_AM
No
Yes with
SCI0_RXI_OR_ERI
No
Yes with SELSR0*1,*2
No
No
Yes with
SELSR0*1,*3
No
SELSR0*1
No
No
DTC_COMPLETE
DOC
DOC_DOPCI
No
Yes with
CTSU
CTSU_CTSUFN
No
Yes with SELSR0*1
Note 1.
Note 2.
Note 3.
To use the interrupt request as a trigger for exiting Snooze mode, the request must be selected in SELSR0. See section 14,
Interrupt Controller Unit (ICU). When a trigger selected in SELSR0 occurs after executing a WFI instruction and during the
transition from Normal to Software Standby mode, whether the request can be accepted depends on the timing of the
occurrence.
Only one of either SCI0_AM or SCI0_RXI_OR_ERI can be set.
The event that is enabled by the SNZEDCR register must not be used.
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11. Low Power Modes
SBYCR.SSBY = 0
Reset state
Sleep mode
WFI instruction*1
RES pin = high*2
SNZCR.SNZE = 1
All interrupts
Snooze mode
Interrupt shown in Table 11.3
Normal mode
(program execution state)*3
Snooze end condition
shown in Table 11.9
Snooze requests
shown in Table 11.7
WFI instruction*1
DPSBYCR.DPSBY = 0
SBYCR.SSBY = 1
Software Standby mode
Interrupt shown in Table 11.3
DPSBYCR.DPSBY = 1
Internal reset state*4
Deep Software Standby mode
Interrupt shown in Table 11.3
Low power mode (program stopped state)
Note 1.
Note 2.
Note 3.
Note 4.
When an interrupt that acts as a trigger for cancel is received during a transition to the program stopped state after the execution of a WFI
instruction, the MCU executes interrupt exception handling instead of transitioning to low power mode.
The MOCO clock is the source of the operating clock following a transition from the reset state to Normal mode.
The transition to Normal mode is made because of an interrupt from Sleep, Snooze, or Software Standby mode. The clock source is the
same as before entering the low power mode.
When an available interrupt request is generated, an internal reset (Deep Software Standby reset) is generated over a fixed period.
Canceling of Deep Software Standby mode accompanies release from the internal reset state, and then the MCU transitions to Normal
mode and execute a reset exception processing with the MOCO clock as the source of the operating clock.
Figure 11.1
11.2
Mode transitions
Register Descriptions
11.2.1
Standby Control Register (SBYCR)
Address(es): SYSTEM.SBYCR 4001 E00Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
SSBY
OPE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
OPE
Output Port Enable
0: In Software Standby or Deep Software Standby mode, set the
address bus and bus control signals to the high-impedance state. In
Snooze mode, the status of the address bus and bus control signals
are the same as before entering Software Standby mode.
1: In Software Standby or Deep Software Standby mode, retain the
output state of the address bus and bus control signals.
R/W
b15
SSBY
Software Standby
0: Sleep mode
1: Software Standby mode when DPSBYCR.DPSBY = 0 and Deep
Software Standby mode when DPSBYCR.DPSBY = 1.
R/W
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11. Low Power Modes
OPE bit (Output Port Enable)
The OPE bit specifies whether to set to the high-impedance state or to retain the output of the address bus and bus control
signals (for SRAM: CS0 to CS7, RD, WR0 to WR1, WR, BC0 to BC1, and ALE, and for SDRAM: SDCS, RAS, CAS,
and WE) in Software Standby mode or Deep Software Standby mode.
SSBY bit (Software Standby)
The SSBY bit specifies the target transition after a WFI instruction is executed. When the SSBY bit is set to 1, the MCU
enters Software Standby mode after executing the WFI instruction. When the MCU cancels Software Standby mode by
an interrupt, the SSBY bit remains 1. The SSBY bit can be cleared by writing 0 to it.
When the OSTDCR.OSTDE bit is 1, the SSBY bit is ignored. Even if the SSBY bit is 1, the MCU enters Sleep mode on
execution of a WFI instruction.
When the FENTRYR.FENTRYi bit (i = 0 to 3) is 1 or the FENTRYR.FENTRYD bit is 1, the setting of SSBY is ignored.
Even if the SSBY bit is 1, the MCU enters Sleep mode on execution of a WFI instruction. See Table 11.6 for details.
When using the HOCO clock to enter Software Standby mode, STCONR.STCON[1:0] must be set to 00b and
HOCOWTCR.HSTS[2:0] must be set to 110b. However, when using SCI0 in Snooze mode, HOCOWTCR.HSTS[2:0]
must be set to 010b.
11.2.2
Module Stop Control Register A (MSTPCRA)
Address(es): SYSTEM.MSTPCRA 4001 E01Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
MSTPA
22
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
MSTPA
0
1
1
1
1
1
1
1
1
1
1
1
1
0
MSTPA MSTPA MSTPA
7
6
5
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MSTPA0
SRAM0 Module Stop*1
Target module: SRAM0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b4 to b1
—
Reserved
These bits are read as 1. The write value should be 1. R/W
b5
MSTPA5
High-Speed SRAM Module
Stop
Target module: high-speed SRAM
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b6
MSTPA6
ECC SRAM Module Stop*1
Target module: ECC SRAM
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b7
MSTPA7
Standby SRAM Module
Stop
Target module: Standby SRAM
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b21 to b8
—
Reserved
These bits are read as 1. The write value should be 1. R/W
b22
MSTPA22
DMA Controller/Data
Transfer Controller Module
Stop*2
Target modules: DMAC, DTC
0: Cancel the module-stop state
1: Enter the module-stop state.
b31 to b23
—
Reserved
These bits are read as 1. The write value should be 1. R/W
Note 1.
Note 2.
R/W
The MSTPA0 and MSTPA6 bit settings must be the same.
When rewriting the MSTPA22 bit from 0 to 1, disable the DMAC and DTC before setting the MSTPA22 bit.
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11.2.3
11. Low Power Modes
Module Stop Control Register B (MSTPCRB)
Address(es): MSTP.MSTPCRB 4004 7000h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
MSTPB MSTPB MSTPB MSTPB MSTPB MSTPB MSTPB MSTPB MSTPB MSTPB
31
30
29
28
27
26
25
24
23
22
Value after reset:
Value after reset:
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
—
1
MSTPB
15
—
—
—
MSTPB
11
1
1
1
1
1
b21
b20
—
—
b19
1
1
1
1
1
1
b9
b8
b7
b6
b5
b4
b3
1
1
1
1
—
—
1
1
1
b17
b16
—
—
1
1
1
b2
b1
b0
MSTPB MSTPB
19
18
1
MSTPB MSTPB MSTPB MSTPB MSTPB
9
8
7
6
5
b18
MSTPB MSTPB
2
1
1
1
—
1
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b1
MSTPB1
Controller Area Network 1 Module
Stop*1
Target module: CAN1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b2
MSTPB2
Controller Area Network 0 Module
Stop*1
Target module: CAN0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b4, b3
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b5
MSTPB5
IrDA Module Stop
Target module: IrDA
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b6
MSTPB6
Quad Serial Peripheral Interface
Module Stop
Target module: QSPI
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b7
MSTPB7
I2C Bus Interface 2 Module Stop
Target module: IIC2
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b8
MSTPB8
I2C Bus Interface 1 Module Stop
Target module: IIC1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b9
MSTPB9
I2C Bus Interface 0 Module Stop
Target module: IIC0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b10
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b11
MSTPB11
Universal Serial Bus 2.0 FS
Interface Module Stop*2
Target module: USBFS
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b14 to b12
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b15
MSTPB15
ETHERC0 and EDMAC0 Controller
Module Stop
Target modules: ETHERC0, EDMAC0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b17, b16
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b18
MSTPB18
Serial Peripheral Interface 1 Module
Stop
Target module: SPI1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b19
MSTPB19
Serial Peripheral Interface 0 Module
Stop
Target module: SPI0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b21, b20
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
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Bit
Symbol
Bit name
Description
R/W
b22
MSTPB22
Serial Communication Interface 9
Module Stop
Target module: SCI9
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b23
MSTPB23
Serial Communication Interface 8
Module Stop
Target module: SCI8
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b24
MSTPB24
Serial Communication Interface 7
Module Stop
Target module: SCI7
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b25
MSTPB25
Serial Communication Interface 6
Module Stop
Target module: SCI6
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b26
MSTPB26
Serial Communication Interface 5
Module Stop
Target module: SCI5
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b27
MSTPB27
Serial Communication Interface 4
Module Stop
Target module: SCI4
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b28
MSTPB28
Serial Communication Interface 3
Module Stop
Target module: SCI3
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b29
MSTPB29
Serial Communication Interface 2
Module Stop
Target module: SCI2
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b30
MSTPB30
Serial Communication Interface 1
Module Stop
Target module: SCI1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b31
MSTPB31
Serial Communication Interface 0
Module Stop
Target module: SCI0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
Note 1.
Note 2.
The MSTPBi bit must be written to while the oscillation of the clock controlled by this bit is stable. To enter Software Standby
mode after writing to this bit, wait for 2 CAN clock (CANMCLK) cycles after writing, then execute a WFI instruction (i = 1, 2).
To enter Software Standby mode after writing to the MSTPB11 bit, wait for 2 USB clock (UCLK) cycles after writing, then
execute a WFI instruction.
11.2.4
Module Stop Control Register C (MSTPCRC)
Address(es): MSTP.MSTPCRC 4004 7004h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MSTPC
31
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b15
—
Value after reset:
MSTPC MSTPC MSTPC MSTPC
14
13
12
11
1
1
1
1
—
1
1
MSTPC MSTPC
9
8
1
1
—
—
—
—
1
1
1
1
MSTPC MSTPC MSTPC MSTPC
3
2
1
0
1
1
1
1
Bit
Symbol
Bit name
Description
R/W
b0
MSTPC0*1
Clock Frequency
Accuracy Measurement
Circuit Module Stop
Target module: CAC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b1
MSTPC1
Cyclic Redundancy
Check Calculator Module
Stop
Target module: CRC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
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Bit
Symbol
Bit name
Description
R/W
b2
MSTPC2
Parallel Data Capture
Module Stop
Target module: PDC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b3
MSTPC3
Capacitive Touch
Target module: CTSU
Sensing Unit Module Stop 0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b7 to b4
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b8
MSTPC8
Serial Sound Interface
Enhanced (channel 0)
Module Stop
Target module: SSIE0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b9
MSTPC9
Sampling Rate Converter
Module Stop
Target module: SRC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b10
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b11
MSTPC11
Secure Digital Host IF/
MultiMediaCard 1 Module
Stop
Target module: SDHI/MMC1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b12
MSTPC12
Secure Digital Host IF/
MultiMediaCard 0 Module
Stop
Target module: SDHI/MMC0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b13
MSTPC13
Data Operation Circuit
Module Stop
Target module: DOC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b14
MSTPC14
Event Link Controller
Module Stop
Target module: ELC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b30 to b15
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b31
MSTPC31
SCE7 Module Stop
Target module: SCE7
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
Note 1.
The MSTPC0 bit must be written to while the oscillation of the clock controlled by this bit is stable. To enter Software Standby
mode after writing to this bit, wait for 2 cycles of the slowest clock from the clocks output by the oscillators, then execute a WFI
instruction.
11.2.5
Module Stop Control Register D (MSTPCRD)
Address(es): MSTP.MSTPCRD 4004 7008h
Value after reset:
b31
b30
b29
—
—
—
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
MSTPD MSTPD
15
14
Value after reset:
1
1
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
MSTPD
20
—
—
—
MSTPD
16
1
1
1
1
1
1
1
b6
b5
b4
b3
b2
b1
b0
—
—
1
1
MSTPD MSTPD MSTPD MSTPD MSTPD MSTPD MSTPD
28
27
26
25
24
23
22
—
—
—
—
—
—
—
1
1
1
1
1
1
1
MSTPD MSTPD
6
5
1
1
—
1
MSTPD MSTPD
3
2
1
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b2
MSTPD2
Asynchronous General
Purpose Timer 1 Module
Stop*1
Target module: AGT1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b3
MSTPD3
Asynchronous General
Purpose Timer 0 Module
Stop*2
Target module: AGT0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
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Bit
Symbol
Bit name
Description
R/W
b4
—
b5
MSTPD5
Reserved
This bit is read as 1. The write value should be 1.
R/W
General PWM Timer 32EH0 to
32EH3 and 32E4 to 32E7 and
PWM Delay Generation Circuit
Module Stop
Target modules: GPT32EHx (x = 0 to 3), GPT32Ey (y = 4 to
7), and PWM Delay Generation Circuit
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b6
MSTPD6
General PWM Timer 328 to
3213 Module Stop
Target modules: GPT32x (x = 8 to 13)
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b13 to b7
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b14
MSTPD14
Port Output Enable for GPT
Module Stop
Target module: POEG
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b15
MSTPD15
12-Bit A/D Converter 1 Module
Stop
Target module: ADC121
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b16
MSTPD16
12-Bit A/D Converter 0 Module
Stop
Target module: ADC120
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b19 to b17
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b20
MSTPD20
12-Bit D/A Converter Module
Stop
Target module: DAC12
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b21
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b22
MSTPD22
Temperature Sensor Module
Stop
Target module: TSN
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b23
MSTPD23
High-Speed Analog
Comparator 5 Module Stop
Target module: ACMPHS5
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b24
MSTPD24
High-Speed Analog
Comparator 4 Module Stop
Target module: ACMPHS4
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b25
MSTPD25
High-Speed Analog
Comparator 3 Module Stop
Target module: ACMPHS3
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b26
MSTPD26
High-Speed Analog
Comparator 2 Module Stop
Target module: ACMPHS2
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b27
MSTPD27
High-Speed Analog
Comparator 1 Module Stop
Target module: ACMPHS1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b28
MSTPD28
High-Speed Analog
Comparator 0 Module Stop
Target module: ACMPHS0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b31 to b29
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
Note 1.
Note 2.
When the count source is sub-clock oscillator or LOCO, AGT1 counting does not stop even if MSTPD2 is set to 1. If the count
source is the sub-clock oscillator or LOCO, this bit must be set to 1 except when accessing the AGT1 registers.
When the count source is sub-clock oscillator or LOCO, AGT0 counting does not stop even if MSTPD3 is set to 1. If the count
source is the sub-clock oscillator or LOCO, this bit must be set to 1 except when accessing the AGT0 registers.
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11.2.6
11. Low Power Modes
Operating Power Control Register (OPCCR)
Address(es): SYSTEM.OPCCR 4001 E0A0h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
OPCM
TSF
—
—
OPCM[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
OPCM[1:0]
Operating Power Control
Mode Select
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
OPCMTSF
Operating Power Control
Mode Transition Status
Flag
Read
0: Transition completed
1: Transition in progress.
R
0 0: High-speed mode
1 1: Low-speed mode.
Other settings are prohibited.
Write
The write value should be 0.
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The OPCCR register is used to reduce power consumption in Normal and Sleep modes by specifying a lower operating
frequency and operating voltage. For the procedure to change the operating power control modes, see section 11.5,
Function for Lower Operating Power Consumption.
When transitioning from Software Standby mode to Normal or Snooze mode, the settings in the OPCCR.OPCM[1:0] and
SOPCCR.SOPCM bits are as follows, regardless of their settings before entering Software Standby mode:
OPCCR.OPCM[1:0] = 00b (High-speed mode)
SOPCCR.SOPCM = 0b (not Subosc-speed mode).
If Software Standby mode is canceled before the transition to Software Standby completes, the OPCCR.OPCM[1:0] and
SOPCCR.SOPCM bits retain their settings from before the WFI instruction is executed. If this causes any problem, set
the MCU to High-speed mode during the exception handling procedure when canceling Software Standby mode.
OPCM[1:0] bits (Operating Power Control Mode Select)
The OPCM[1:0] bits select the operating power control mode in Normal and Sleep modes. Table 11.4 shows the
relationship between the operating power control modes and the OPCM[1:0] and SOPCM settings.
OPCMTSF flag (Operating Power Control Mode Transition Status Flag)
The OPCMTSF flag indicates the switching control state when the operating power control mode is switched. This flag
becomes 1 when the OPCM[1:0] bits are written, and 0 when the mode transition completed. Read this flag and confirm
that it is 0 before proceeding.
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11. Low Power Modes
Sub Operating Power Control Register (SOPCCR)
Address(es): SYSTEM.SOPCCR 4001 E0AAh
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
SOPC
MTSF
—
—
—
SOPC
M
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
SOPCM
Sub Operating Power Control
Mode Select
0: Not Subosc-speed mode
1: Subosc-speed mode.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
SOPCMTSF
Sub Operating Power Control
Mode Transition Status Flag
0: Transition completed
1: Transition in progress.
R
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SOPCCR register is used to reduce power consumption in Normal and Sleep modes by initiating entry to and exit
from Subosc-speed mode. Subosc-speed mode is only available when using the sub-clock oscillator or LOCO without
dividing the frequency.
The flash cache function should be set to disabled by setting FCACHEE.FCACHEEN to 0 before switching the
operating power control mode. For details, see section 53, Flash Memory.
For the procedure to change operating power control modes, see section 11.5, Function for Lower Operating Power
Consumption.
SOPCM bit (Sub Operating Power Control Mode Select)
The SOPCM bit selects the operating power control mode in Normal and Sleep modes. Setting this bit to 1 allows
transition to Subosc-speed mode. Setting this bit to 0 allows a return to the operating mode (operating mode set by
OPCCR.OPCM[1:0]) that was active before the transition to Subosc-speed mode.
When transitioning from Software Standby mode to Normal mode or Snooze mode, the OPCCR.OPCM[1:0] and
SOPCCR.SOPCM settings are as follows, regardless of their settings before entering Software Standby mode:
OPCCR.OPCM[1:0] = 00b (High-speed mode)
SOPCCR.SOPCM = 0b (not Subosc-speed mode).
If Software Standby mode is canceled before the transition to Software Standby completes, the OPCCR.OPCM[1:0] and
SOPCCR.SOPCM bits retain their settings from before the WFI instruction is executed. If this causes any problem, set
the MCU to High-speed mode during the exception handling procedure when canceling Software Standby mode.
Table 11.4 shows the relationship between the operating power control modes and the OPCM[1:0] and SOPCM settings.
SOPCMTSF flag (Sub Operating Power Control Mode Transition Status Flag)
The SOPCMTSF flag indicates the switching control state when the operating power control mode is switched to
Subosc-speed mode or from Subosc-speed mode. The flag is set to 1 on a write access to the SOPCM bit, and to 0 when
the mode transition completes. Confirm that the flag is 0 before next proceeding.
Table 11.4
Relationship between the operating power control modes and the OPCM[1:0] and SOPCM settings
Operating power control mode
High-speed mode
Low-speed mode
Subosc-speed mode
Note:
OPCM[1:0] bits
SOPCM bit
00b
0
11b
0
00b, 11b
1
Power consumption
High
Low
See section 55, Electrical Characteristics, for the operating frequency range and voltage range.
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11. Low Power Modes
High-speed operating mode
After a reset cancellation, the MCU is activated in this mode.
Low-speed mode
The following constraints apply in low-speed mode:
Programming and erasure operations for the flash memory are prohibited
Using the PLL is prohibited. See section 11.10.1, Register Access.
In this mode, lower power consumption is possible than in High-speed mode when the same operation is performed
under the same conditions, such as operating frequency and operating voltage.
Subosc-speed mode
The following constraints apply in Subosc-speed mode:
Programming and erasure operations for the flash memory are prohibited
Reading of the data flash is prohibited
Using MOSC, PLL, MOCO, or HOCO is prohibited. See section 11.10.1, Register Access
Using the divided clock for ICK or FCK is prohibited. See section 11.10.1, Register Access
Using the oscillation stop detection function of the main clock oscillator is prohibited.
11.2.8
Snooze Control Register (SNZCR)
Address(es): SYSTEM.SNZCR 4001 E092h
b7
b6
b5
b4
b3
b2
SNZE
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b1
b0
SNZDT RXDRE
CEN
QEN
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RXDREQEN
RXD0 Snooze Request Enable
0: Ignore the RXD0 falling edge in Software Standby mode
1: Detect the RXD0 falling edge in Software Standby mode.
R/W
b1
SNZDTCEN
DTC Enable in Snooze mode
0: Disable DTC operation in Snooze mode
1: Enable DTC operation in Snooze mode.
R/W
b6 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
SNZE
Snooze Mode Enable
0: Disable Snooze mode
1: Enable Snooze mode.
R/W
RXDREQEN bit (RXD0 Snooze Request Enable)
The RXDREQEN bit specifies whether to detect a falling edge of the RXD0 pin in Software Standby mode. This bit is
only available when SCI0 operates in asynchronous mode. To detect a falling edge of the RXD0 pin, set this bit before
entering Software Standby mode. When this bit is set to 1, a falling edge of the RXD0 pin in Software Standby mode
causes the MCU to enter Snooze mode.
SNZDTCEN bit (DTC Enable in Snooze mode)
The SNZDTCEN bit specifies whether to use the DTC and SRAM in Snooze mode. To use the DTC and SRAM in
Snooze mode, set this bit to 1 before entering Software Standby mode. When this bit is set to 1, the DTC can be activated
by setting IELSRn (ICU Event Link Setting Register n).
SNZE bit (Snooze Mode Enable)
The SNZE bit enables or disables a transition from Software Standby to Snooze mode. To use Snooze mode, set this bit
to 1 before entering Software Standby mode. When this bit is set to 1, one of the event triggers shown in Table 11.7
occurring in Software Standby mode causes the MCU to enter Snooze mode. After the MCU transitions from Software
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Standby or Snooze mode to Normal mode, clear the SNZE bit once and then set it before re-entering Software Standby
mode. For details, see section 11.8, Snooze Mode.
11.2.9
Snooze End Control Register (SNZEDCR)
Address(es): SYSTEM.SNZEDCR 4001 E094h
b7
b6
b5
b4
b3
b2
b1
b0
SCI0U AD1UM AD1MA AD0UM AD0MA DTCNZ DTCZR AGTUN
MTED TED
TED
TED
TED
RED
ED
FED
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
AGTUNFED
AGT1 Underflow Snooze End Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b1
DTCZRED
Last DTC Transmission Completion
Snooze End Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b2
DTCNZRED
Not Last DTC Transmission Completion
Snooze End Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b3
AD0MATED
AD Compare Match 0 Snooze End
Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b4
AD0UMTED
AD Compare Mismatch 0 Snooze End
Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b5
AD1MATED
AD Compare Match 1 Snooze End
Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b6
AD1UMTED
AD Compare Mismatch 1 Snooze End
Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
b7
SCI0UMTED
SCI0 Address Mismatch Snooze End
Enable
0: Disable the Snooze end request
1: Enable the Snooze end request.
R/W
To use one of the triggers shown in Table 11.8 as a condition to switch from Snooze to Software Standby mode, set the
associated bit in the SNZEDCR register to 1.
The event that is used for returning to Normal mode from Snooze mode as listed in Table 11.3 must not be enabled in the
SNZEDCR register.
AGTUNFED bit (AGT1 Underflow Snooze End Enable)
The AGTUNFED bit enables or disables a transition from Snooze to Software Standby mode on an AGT1 underflow.
For details on the trigger conditions, see section 25, Asynchronous General-Purpose Timer (AGT).
DTCZRED bit (Last DTC Transmission Completion Snooze End Enable)
The DTCZRED bit enables or disables a transition from Snooze to Software Standby mode on completion of the last
DTC transmission, signaled when the CRA or CRB register in the DTC is 0. For details on the trigger conditions, see
section 18, Data Transfer Controller (DTC).
DTCNZRED bit (Not Last DTC Transmission Completion Snooze End Enable)
The DTCNZRED bit enables or disables a transition from Snooze to Software Standby mode on completion of each DTC
transmission, signaled when the CRA or CRB register in the DTC is not 0. For details on the trigger conditions, see
section 18, Data Transfer Controller (DTC).
AD0MATED bit (AD Compare Match 0 Snooze End Enable)
The AD0MATED bit enables or disables a transition from Snooze to Software Standby mode on an AD0 event when a
conversion result matches the expected data. For details on the trigger conditions, see section 45, 12-Bit A/D Converter
(ADC12).
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AD0UMTED bit (AD Compare Mismatch 0 Snooze End Enable)
The AD0UMTED bit enables or disables a transition from Snooze to Software Standby mode on an AD0 event when the
conversion result does not match the expected data. For details on the trigger conditions, see section 45, 12-Bit A/D
Converter (ADC12).
AD1MATED bit (AD Compare Match 1 Snooze End Enable)
The AD1MATED bit enables or disables a transition from Snooze to Software Standby mode on an AD1 event when the
conversion result matches the expected data. For details on the trigger conditions, see section 45, 12-Bit A/D Converter
(ADC12).
AD1UMTED bit (AD Compare Mismatch 1 Snooze End Enable)
The AD1UMTED bit enables or disables a transition from Snooze to Software Standby mode on an AD1 event when the
conversion result does not match the expected data. For details on the trigger conditions, see section 45, 12-Bit A/D
Converter (ADC12).
SCI0UMTED bit (SCI0 Address Mismatch Snooze End Enable)
The SCI0UMTED bit enables or disables a transition from Snooze to Software Standby mode on an SCI0 event when an
address received in Software Standby mode does not match the expected data. For details on the trigger conditions, see
section 32, Serial Communications Interface (SCI). Only set this bit to 1 when SCI0 is operating in asynchronous mode.
11.2.10
Snooze Request Control Register (SNZREQCR)
Address(es): SYSTEM.SNZREQCR 4001 E098h
b31
—
Value after reset:
b30
b29
b28
SNZRE SNZRE SNZRE
QEN30 QEN29 QEN28
b27
b26
—
—
b25
b24
SNZRE SNZRE
QEN25 QEN24
b23
b22
b21
b20
b19
b18
b17
b16
—
SNZRE
QEN22
—
—
—
—
SNZRE
QEN17
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE
QEN15 QEN14 QEN13 QEN12 QEN11 QEN10 QEN9 QEN8 QEN7 QEN6 QEN5 QEN4 QEN3 QEN2 QEN1 QEN0
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SNZREQEN0
Snooze Request Enable 0
Enables the IRQ0 pin snooze request:
0: Disable
1: Enable.
R/W
b1
SNZREQEN1
Snooze Request Enable 1
Enables the IRQ1 pin snooze request:
0: Disable
1: Enable.
R/W
b2
SNZREQEN2
Snooze Request Enable 2
Enables the IRQ2 pin snooze request:
0: Disable
1: Enable.
R/W
b3
SNZREQEN3
Snooze Request Enable 3
Enables the IRQ3 pin snooze request:
0: Disable
1: Enable.
R/W
b4
SNZREQEN4
Snooze Request Enable 4
Enables the IRQ4 pin snooze request:
0: Disable
1: Enable.
R/W
b5
SNZREQEN5
Snooze Request Enable 5
Enables the IRQ5 pin snooze request:
0: Disable
1: Enable.
R/W
b6
SNZREQEN6
Snooze Request Enable 6
Enables the IRQ6 pin snooze request:
0: Disable
1: Enable.
R/W
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Bit
Symbol
Bit name
Description
R/W
b7
SNZREQEN7
Snooze Request Enable 7
Enables the IRQ7 pin snooze request:
0: Disable
1: Enable.
R/W
b8
SNZREQEN8
Snooze Request Enable 8
Enables the IRQ8 pin snooze request:
0: Disable
1: Enable.
R/W
b9
SNZREQEN9
Snooze Request Enable 9
Enables the IRQ9 pin snooze request:
0: Disable
1: Enable.
R/W
b10
SNZREQEN10
Snooze Request Enable 10
Enables the IRQ10 pin snooze request:
0: Disable
1: Enable.
R/W
b11
SNZREQEN11
Snooze Request Enable 11
Enables the IRQ11 pin snooze request:
0: Disable
1: Enable.
R/W
b12
SNZREQEN12
Snooze Request Enable 12
Enables the IRQ12 pin snooze request:
0: Disable
1: Enable.
R/W
b13
SNZREQEN13
Snooze Request Enable 13
Enables the IRQ13 pin snooze request:
0: Disable
1: Enable.
R/W
b14
SNZREQEN14
Snooze Request Enable 14
Enables the IRQ14 pin snooze request:
0: Disable
1: Enable.
R/W
b15
SNZREQEN15
Snooze Request Enable 15
Enables the IRQ15 pin snooze request:
0: Disable
1: Enable.
R/W
b16
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b17
SNZREQEN17
Snooze Request Enable 17
Enables the Key Interrupt snooze request:
0: Disable
1: Enable.
R/W
b21 to b18
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b22
SNZREQEN22
Snooze Request Enable 22
Enables the ACMPHS0 snooze request:
0: Disable
1: Enable.
R/W
b23
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b24
SNZREQEN24
Snooze Request Enable 24
Enables the RTC alarm snooze request:
0: Disable
1: Enable.
R/W
b25
SNZREQEN25
Snooze Request Enable 25
Enables the RTC period snooze request:
0: Disable
1: Enable.
R/W
b27, b26
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28
SNZREQEN28
Snooze Request Enable 28
Enables the AGT1 underflow snooze request:
0: Disable
1: Enable.
R/W
b29
SNZREQEN29
Snooze Request Enable 29
Enables the AGT1 compare match A snooze request:
0: Disable
1: Enable.
R/W
b30
SNZREQEN30
Snooze Request Enable 30
Enables the AGT1 compare match B snooze request:
0: Disable
1: Enable.
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
The SNZREQCR register controls which trigger causes the MCU to switch from Software Standby to Snooze mode. If a
trigger is selected as a request to cancel Software Standby mode in the WUPEN register (see section 14, Interrupt
Controller Unit (ICU)), the MCU enters Normal mode when the trigger is generated even when the associated bit of the
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SNZREQCR is 1. The setting of the WUPEN register always has a higher priority than the SNZREQCR register settings.
For details, see section 11.8, Snooze Mode, and section 14, Interrupt Controller Unit (ICU).
11.2.11
Deep Software Standby Control Register (DPSBYCR)
Address(es): SYSTEM.DPSBYCR 4001 E400h
b7
b6
DPSBY IOKEE
P
Value after reset:
0
0
b5
b4
b3
b2
—
—
—
—
0
0
0
0
b1
b0
DEEPCUT[1:0]
0
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
DEEPCUT
[1:0]
Power-Supply
Control
b1
R/W
0
0
1
1
b0
0: Supply power to the Standby SRAM, low-speed on-chip oscillator, AGTn,
and USBFS resume detecting unit in Deep Software Standby mode
1: Do not supply power to the Standby SRAM, low-speed on-chip oscillator,
AGTn, and USBFS resume detecting unit in Deep Software Standby mode
0: Setting prohibited
1: Do not supply power to the Standby SRAM, low-speed on-chip oscillator,
AGTn, and USBFS resume detecting unit in Deep Software Standby mode.
In addition, disable the LVD and enable the low power function of the poweron reset circuit.
b5 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
IOKEEP
I/O Port
Retention
0: When Deep Software Standby mode is canceled, clear the I/O ports to the reset
state
1: When Deep Software Standby mode is canceled, keep the I/O ports in the same
state as in Deep Software Standby mode.
R/W
b7
DPSBY
Deep Software
Standby
0: Sleep mode (SBYCR.SSBY = 0) or Software Standby mode (SBYCR.SSBY = 1) R/W
1: Sleep mode (SBYCR.SSBY = 0) or Deep Software Standby mode
(SBYCR.SSBY = 1).
The DPSBYCR register is not initialized by the internal reset signal that cancels Deep Software Standby mode. For
details, see Table 6.2, Reset detect flags initialized by each reset source.
DEEPCUT[1:0] bits (Power-Supply Control)
The DEEPCUT[1:0] bits control the internal power supply to the Standby SRAM, low-speed on-chip oscillator, AGTn,
and USBFS resume detecting unit in Deep Software Standby mode. In addition, these bits control the state of the LVD
and power-on reset circuit in Deep Software Standby mode. When a USBFS suspend/resume interrupt is used as a
canceling source for Deep Software Standby mode, the DEEPCUT[1:0] bits must be set to 00b. When an LVD interrupt
is used in Deep Software Standby mode, the DEEPCUT[1:0] bits must be set to 00b or 01b.
For lower power consumption, set the DEEPCUT[1:0] bits to 11b so that the LVD is stopped and the low power mode
function of the power-on reset circuit is enabled. The internal power supply of the SRAM stops in Deep Software
Standby mode regardless of the DEEPCUT[1:0] bit settings.
IOKEEP bit (I/O Port Retention)
In Deep Software Standby mode, the I/O ports keep the same states as in Software Standby mode. The IOKEEP bit
specifies whether to reset the state of the I/O ports when Deep Software Standby mode is canceled.
DPSBY bit (Deep Software Standby)
The DPSBY bit controls transitions to Deep Software Standby mode. See Table 11.6 for details.
When the WFI instruction is executed while the SBYCR.SSBY and DPSBYCR.DPSBY bits are both 1, the MCU enters
Deep Software Standby mode through Software Standby mode.
The DPSBY bit remains 1 when Deep Software Standby mode is canceled by certain pins that are the sources of external
pin interrupts (NMI and IRQ0-DS to IRQ13-DS) or by a peripheral interrupt (RTC alarm, RTC interval, USB
suspend/resume, voltage monitor 1, or voltage monitor 2). Write 0 to this bit to clear it.
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The DPSBY setting is invalid when the OFS0.IWDTSTPCTL bit is 0 (counting continues), regardless of the setting in
the OFS0.IWDTSTRT bit. When the SBYCR.SSBY and DPSBY bits are 1, the MCU transitions to Software Standby
mode on execution of a WFI instruction.
The DPSBY setting is invalid when the voltage monitor 1 reset is enabled (LVD1CR0.RI = 1) or when the voltage
monitor 2 reset is enabled (LVD2CR0.RI = 1). When the SBYCR.SSBY and the DPSBY bits are 1, the MCU transitions
to Software Standby mode on execution of a WFI instruction.
11.2.12
Deep Software Standby Interrupt Enable Register 0 (DPSIER0)
Address(es): SYSTEM.DPSIER0 4001 E402h
b7
b6
b5
b4
b3
b2
b1
b0
DIRQ7 DIRQ6 DIRQ5 DIRQ4 DIRQ3 DIRQ2 DIRQ1 DIRQ0
E
E
E
E
E
E
E
E
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DIRQ0E
IRQ0-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ0-DS pin:
0: Disable
1: Enable.
R/W
b1
DIRQ1E
IRQ1-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ1-DS pin:
0: Disable
1: Enable.
R/W
b2
DIRQ2E
IRQ2-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ2-DS pin:
0: Disable
1: Enable.
R/W
b3
DIRQ3E
IRQ3-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ3-DS pin:
0: Disable
1: Enable.
R/W
b4
DIRQ4E
IRQ4-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ4-DS pin:
0: Disable
1: Enable.
R/W
b5
DIRQ5E
IRQ5-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ5-DS pin:
0: Disable
1: Enable.
R/W
b6
DIRQ6E
IRQ6-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ6-DS pin:
0: Disable
1: Enable.
R/W
b7
DIRQ7E
IRQ7-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ7-DS pin:
0: Disable
1: Enable.
R/W
The DPSIER0 register is not initialized by the internal reset signal that cancels Deep Software Standby mode. For details,
see Table 6.2, Reset detect flags initialized by each reset source. After a setting in DPSIER0 is changed, an edge can be
internally generated depending on the associated pin state, resulting in the associated DPSIFR0 bit being set to 1. Clear
DPSIFR0 to 0 before entering Deep Software Standby mode.
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11. Low Power Modes
Deep Software Standby Interrupt Enable Register 1 (DPSIER1)
Address(es): SYSTEM.DPSIER1 4001 E403h
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
DIRQ1 DIRQ1 DIRQ11 DIRQ1 DIRQ9 DIRQ8
3E
2E
E
0E
E
E
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DIRQ8E
IRQ8-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ8-DS pin:
0: Disable
1: Enable.
R/W
b1
DIRQ9E
IRQ9-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ9-DS pin:
0: Disable
1: Enable.
R/W
b2
DIRQ10E
IRQ10-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ10-DS pin:
0: Disable
1: Enable.
R/W
b3
DIRQ11E
IRQ11-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ11-DS pin:
0: Disable
1: Enable.
R/W
b4
DIRQ12E
IRQ12-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ12-DS pin:
0: Disable
1: Enable.
R/W
b5
DIRQ13E
IRQ13-DS Pin Enable
Enables canceling of Deep Software Standby mode by the IRQ13-DS pin:
0: Disable
1: Enable.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The DPSIER1 register is not initialized by the internal reset signal that cancels Deep Software Standby mode. For details,
see Table 6.2, Reset detect flags initialized by each reset source. After a setting in DPSIER1 is changed, an edge can be
internally generated depending on the associated pin state, resulting in the associated DPSIFR1 bit being set to 1. Clear
DPSIFR1 to 0 before entering Deep Software Standby mode.
11.2.14
Deep Software Standby Interrupt Enable Register 2 (DPSIER2)
Address(es): SYSTEM.DPSIER2 4001 E404h
b7
Value after reset:
b6
b5
—
—
—
0
0
0
b4
b3
b2
b1
b0
DNMIE DRTCA DRTCII DLVD2I DLVD1I
IE
E
E
E
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DLVD1IE
LVD1 Deep Software Standby
Cancel Signal Enable
Enables canceling of Deep Software Standby mode by the
voltage monitor 1 signal:
0: Disable
1: Enable.
R/W
b1
DLVD2IE
LVD2 Deep Software Standby
Cancel Signal Enable
Enables canceling of Deep Software Standby mode by the
voltage monitor 2 signal:
0: Disable
1: Enable.
R/W
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Bit
Symbol
Bit name
Description
R/W
b2
DRTCIIE
RTC Interval Interrupt Deep
Software Standby Cancel Signal
Enable
Enables canceling of Deep Software Standby mode by the
RTC interval interrupt signal:
0: Disable
1: Enable.
R/W
b3
DRTCAIE
RTC Alarm Interrupt Deep
Software Standby Cancel Signal
Enable
Enables canceling of Deep Software Standby mode by the
RTC alarm interrupt signal:
0: Disable
1: Enable.
R/W
b4
DNMIE
NMI Pin Enable
Enables canceling of Deep Software Standby mode by the
NMI pin:
0: Disable
1: Enable.
R/W*1
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. 1 can be written only once. After 1 is written to this bit, subsequent write accesses are disabled.
The DPSIER2 register is not initialized by the internal reset signal that cancels Deep Software Standby mode. For details,
see Table 6.2, Reset detect flags initialized by each reset source. After a setting in DPSIER2 is changed, an edge can be
internally generated depending on the associated pin state, resulting in the associated DPSIFR2 bit being set to 1. Clear
DPSIFR2 to 0 before entering Deep Software Standby mode.
11.2.15
Deep Software Standby Interrupt Enable Register 3 (DPSIER3)
Address(es): SYSTEM.DPSIER3 4001 E405h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
DAGT1
IE
—
DUSBF
SIE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DUSBFSIE
USBFS Suspend/Resume Deep Software
Standby Cancel Signal Enable
Enables canceling of Deep Software Standby mode by a
USBFS suspend/resume:
0: Disable
1: Enable.
R/W
b1
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2
DAGT1IE
AGT1 Underflow Deep Software Standby
Cancel Signal Enable
Enables canceling of Deep Software Standby mode by
an AGT1 underflow:
0: Disable
1: Enable.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The DPSIER3 register is not initialized by the internal reset signal that cancels Deep Software Standby mode. For details,
see Table 6.2, Reset detect flags initialized by each reset source. After a setting in DPSIER3 is changed, an edge can be
internally generated depending on the associated pin state, resulting in the associated DPSIFR3 bit setting to 1. Clear
DPSIFR3 to 0 before entering Deep Software Standby mode.
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11. Low Power Modes
Deep Software Standby Interrupt Flag Register 0 (DPSIFR0)
Address(es): SYSTEM.DPSIFR0 4001 E406h
b7
b6
b5
b4
b3
b2
b1
b0
DIRQ7 DIRQ6 DIRQ5 DIRQ4 DIRQ3 DIRQ2 DIRQ1 DIRQ0
F
F
F
F
F
F
F
F
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DIRQ0F
IRQ0-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ0-DS pin:
0: No request generated
1: Request generated.
R(/W)
*1
b1
DIRQ1F
IRQ1-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ1-DS pin:
0: No request generated
1: Request generated.
R(/W)
*1
b2
DIRQ2F
IRQ2-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ2-DS pin:
0: No request generated
1: Request generated.
R(/W)
*1
b3
DIRQ3F
IRQ3-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ3-DS pin:
0: No request generated
1: Request generated.
R(/W)
*1
b4
DIRQ4F
IRQ4-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ4-DS pin:
0: No request generated
1: Request generated.
R(/W)
*1
b5
DIRQ5F
IRQ5-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ5-DS pin:
0: No request generated
1: Request generated.
R(/W)
*1
b6
DIRQ6F
IRQ6-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ6-DS pin:
0: No request generated
1: Request generated.
R(/W)
*1
b7
DIRQ7F
IRQ7-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ7-DS pin:
0: No request generated
1: Request generated.
R(/W)
*1
Note 1.
Only 0 can be written to clear the flag.
The flags in the DPSIFR0 register is set to 1 when the associated cancel request specified in DPSIEGR0 is generated.
Each flag can be set to 1 when a cancel request is generated in any mode, not only in Deep Software Standby mode, or
when the setting in DPSIER0 is changed. Clear DPSIFR0 to 00h before entering Deep Software Standby mode.
To clear DPSIFR0 to 00h after modifying DPSIER0, wait for at least 6 PCLKB cycles, read DPSIFR0, and then write 0
to DPSIFR0. Six or more PCLKB cycles can be secured, for example, by reading DPSIER0. DPSIFR0 is not initialized
by the internal reset signal that cancels Deep Software Standby mode. For details, see Table 6.2, Reset detect flags
initialized by each reset source.
DIRQnF flags (IRQn-DS Deep Software Standby Cancel Flag) (n = 0 to 7)
The DIRQnF flag indicates that a cancel request is generated by the IRQn-DS pin.
[Setting condition]
A cancel request generated by an IRQn-DS pin specified in DPSIEGR0.
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[Clearing condition]
Writing 0 to the flag after reading it as 1.
11.2.17
Deep Software Standby Interrupt Flag Register 1 (DPSIFR1)
Address(es): SYSTEM.DPSIFR1 4001 E407h
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
DIRQ1 DIRQ1 DIRQ11 DIRQ1 DIRQ9 DIRQ8
3F
2F
F
0F
F
F
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DIRQ8F
IRQ8-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ8-DS pin:
0: No request generated
1: Request generated.
R(/W)*1
b1
DIRQ9F
IRQ9-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ9-DS pin:
0: No request generated
1: Request generated.
R(/W)*1
b2
DIRQ10F
IRQ10-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ10-DS pin:
0: No request generated
1: Request generated.
R(/W)*1
b3
DIRQ11F
IRQ11-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ11-DS pin:
0: No request generated
1: Request generated.
R(/W)*1
b4
DIRQ12F
IRQ12-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ12-DS pin:
0: No request generated
1: Request generated.
R(/W)*1
b5
DIRQ13F
IRQ13-DS Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the
IRQ13-DS pin:
0: No request generated
1: Request generated.
R(/W)*1
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R(/W)*1
Note 1.
Only 0 can be written to clear the flag.
The flags in the DPSIFR1 register are set to 1 when the associated cancel request specified in DPSIEGR1 is generated.
Each flag can be set to 1 when a cancel request is generated in any mode, not only in Deep Software Standby mode, or
when the setting in DPSIER1 is changed. Clear DPSIFR1 to 00h before entering Deep Software Standby mode.
To clear DPSIFR1 to 00h after modifying DPSIER1, wait for at least 6 PCLKB cycles, read DPSIFR1, and then write 0
to DPSIFR1. Six or more PCLKB cycles can be secured, for example, by reading DPSIER1. DPSIFR1 is not initialized
by the internal reset signal that cancels Deep Software Standby mode. For details, see Table 6.2, Reset detect flags
initialized by each reset source.
DIRQnF flags (IRQn-DS Deep Software Standby Cancel Flag) (n = 8 to 13)
The DIRQnF flag indicates that a cancel request is generated by the IRQn-DS pin.
[Setting condition]
A cancel request generated by the IRQn-DS pin specified in DPSIEGR1.
[Clearing condition]
Writing 0 to the flag after reading it as 1.
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11. Low Power Modes
Deep Software Standby Interrupt Flag Register 2 (DPSIFR2)
Address(es): SYSTEM.DPSIFR2 4001 E408h
Value after reset:
b7
b6
b5
—
—
—
0
0
0
b4
b3
b2
b1
b0
DNMIF DRTCA DRTCII DLVD2I DLVD1I
IF
F
F
F
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DLVD1IF
LVD1 Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the voltage
monitor 1 signal:
0: No request generated
1: Request generated.
R(/W)*1
b1
DLVD2IF
LVD2 Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the voltage
monitor 2 signal:
0: No request generated
1: Request generated.
R(/W)*1
b2
DRTCIIF
RTC Interval Interrupt Deep
Software Standby Cancel Flag
Indicates Deep Software Standby cancel request by the RTC
interval interrupt signal:
0: No request generated
1: Request generated.
R(/W)*1
b3
DRTCAIF RTC Alarm Interrupt Deep
Software Standby Cancel Flag
Indicates Deep Software Standby cancel request by the RTC alarm
interrupt signal:
0: No request generated
1: Request generated.
R(/W)*1
b4
DNMIF
NMI Deep Software Standby
Cancel Flag
Indicates Deep Software Standby cancel request by the NMI pin:
0: No request generated
1: Request generated.
R(/W)*1
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b5 —
Note 1.
Only 0 can be written to clear the flag.
The flags in the DPSIFR2 register are set to 1 when the associated cancel request specified in DPSIEGR2 is generated.
Each flag can be set to 1 when a cancel request is generated in any mode, not only in Deep Software Standby mode, or
when the setting in DPSIER2 is changed. Clear DPSIFR2 to 00h before entering Deep Software Standby mode.
To clear DPSIFR2 to 00h after modifying DPSIER2, wait for at least 6 PCLKB cycles, read DPSIFR2, and then write 0
to DPSIFR2. Six or more PCLKB cycles can be secured, for example, by reading DPSIER2. DPSIFR2 is not initialized
by the internal reset signal that cancels Deep Software Standby mode. For details, see Table 6.2, Reset detect flags
initialized by each reset source.
DLVDmIF flag (LVDm Deep Software Standby Cancel Flag) (m = 1 or 2)
The DLVDmIF flag indicates that a cancel request is generated by the voltage monitor m signal.
[Setting condition]
A cancel request generated by the voltage monitor m signal specified in DPSIEGR2.
[Clearing condition]
Writing 0 to the flag after reading it as 1.
DRTCIIF flag (RTC Interval Interrupt Deep Software Standby Cancel Flag)
The DRTCIIF flag indicates that a cancel request is generated by the RTC interval interrupt signal.
[Setting condition]
A cancel request generated by the RTC interval interrupt signal.
[Clearing condition]
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Writing 0 to the flag after reading it as 1.
DRTCAIF flag (RTC Alarm Interrupt Deep Software Standby Cancel Flag)
The DRTCAIF flag indicates that a cancel request is generated by the RTC alarm interrupt signal.
[Setting condition]
A cancel request generated by the RTC alarm interrupt signal.
[Clearing condition]
Writing 0 to the flag after reading it as 1.
DNMIF flag (NMI Deep Software Standby Cancel Flag)
The DNMIF flag indicates that a cancel request is generated by the NMI pin.
[Setting condition]
A cancel request generated by the NMI pin specified in DPSIEGR2.
[Clearing condition]
Writing 0 to the flag after reading it as 1.
11.2.19
Deep Software Standby Interrupt Flag Register 3 (DPSIFR3)
Address(es): SYSTEM.DPSIFR3 4001 E409h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
DAGT1
IF
—
DUSBF
SIF
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DUSBFSIF
USBFS Suspend/Resume Deep
Software Standby Cancel Flag
Indicates Deep Software Standby cancel request by a
USBFS suspend/resume:
0: No request generated
1: Request generated.
R(/W)*1
b1
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2
DAGT1IF
AGT1 Underflow Deep Software
Standby Cancel Flag
Indicates Deep Software Standby cancel request by an
AGT1 underflow:
0: No request generated
1: Request generated.
R(/W)*1
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Only 0 can be written to clear the flag.
The flags in the DPSIFR3 register are set to 1 when the associated cancel request is generated. Each flag can be set to 1
when a cancel request is generated in any mode, not only in Deep Software Standby mode, or when the setting in
DPSIER3 is changed. Clear DPSIFR3 to 00h before entering Deep Software Standby mode.
To clear DPSIFR3 to 00h after modifying DPSIER3, wait for at least 6 PCLKB cycles, read DPSIFR3, and then write 0
to DPSIFR3. Six or more PCLKB cycles can be secured, for example, by reading DPSIER3. DPSIFR3 is not initialized
by the internal reset signal that cancels Deep Software Standby mode. For details, see section 6, Resets.
DUSBFSIF flag (USBFS Suspend/Resume Deep Software Standby Cancel Flag)
The DUSBFSIF flag indicates that a cancel request is generated by a USBFS suspend/resume.
[Setting condition]
A cancel request generated by the USBFS suspend/resume.
[Clearing condition]
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Writing 0 to the flag after reading it as 1.
DAGT1IF flag (AGT1 Underflow Deep Software Standby Cancel Flag)
The DAGT1IF flag indicates that a cancel request is generated by an AGT1 underflow.
[Setting condition]
A cancel request generated by the AGT1 underflow.
[Clearing condition]
Writing 0 to the flag after reading it as 1.
11.2.20
Deep Software Standby Interrupt Edge Register 0 (DPSIEGR0)
Address(es): SYSTEM.DPSIEGR0 4001 E40Ah
b7
b6
b5
b4
b3
b2
b1
b0
DIRQ7 DIRQ6 DIRQ5 DIRQ4 DIRQ3 DIRQ2 DIRQ1 DIRQ0
EG
EG
EG
EG
EG
EG
EG
EG
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DIRQ0EG
IRQ0-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b1
DIRQ1EG
IRQ1-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b2
DIRQ2EG
IRQ2-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b3
DIRQ3EG
IRQ3-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b4
DIRQ4EG
IRQ4-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b5
DIRQ5EG
IRQ5-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b6
DIRQ6EG
IRQ6-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b7
DIRQ7EG
IRQ7-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
The DPSIEGR0 register is not initialized by the internal reset signal that cancels Deep Software Standby mode. For
details, see Table 6.2, Reset detect flags initialized by each reset source.
11.2.21
Deep Software Standby Interrupt Edge Register 1 (DPSIEGR1)
Address(es): SYSTEM.DPSIEGR1 4001 E40Bh
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
DIRQ1 DIRQ1 DIRQ11 DIRQ1 DIRQ9 DIRQ8
3EG
2EG
EG
0EG
EG
EG
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DIRQ8EG
IRQ8-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b1
DIRQ9EG
IRQ9-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
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Bit
Symbol
Bit name
Description
R/W
b2
DIRQ10EG
IRQ10-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b3
DIRQ11EG
IRQ11-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b4
DIRQ12EG
IRQ12-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b5
DIRQ13EG
IRQ13-DS Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The DPSIEGR1 register is not initialized by the internal reset signal that cancels Deep Software Standby mode. For
details, see Table 6.2, Reset detect flags initialized by each reset source.
11.2.22
Deep Software Standby Interrupt Edge Register 2 (DPSIEGR2)
Address(es): SYSTEM.DPSIEGR2 4001 E40Ch
b7
Value after reset:
b6
b5
b4
—
—
0
0
—
—
—
DNMIE
G
0
0
0
0
b3
b2
b1
b0
DLVD2 DLVD1
EG
EG
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DLVD1EG
LVD1 Edge Select
0: Generate cancel request when VCC < Vdet1 (fall) is detected
1: Generate cancel request when VCC Vdet1 (rise) is detected.
R/W
b1
DLVD2EG
LVD2 Edge Select
0: Generate cancel request when VCC < Vdet2 (fall) is detected
1: Generate cancel request when VCC Vdet2 (rise) is detected.
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
DNMIEG
NMI Pin Edge Select
0: Generate cancel request on falling edge
1: Generate cancel request on rising edge.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The DPSIEGR2 register is not initialized by the internal reset signal that cancels Deep Software Standby mode. For
details, see Table 6.2, Reset detect flags initialized by each reset source.
11.2.23
System Control OCD Control Register (SYOCDCR)
Address(es): SYSTEM.SYOCDCR 4001 E40Eh
b7
b6
b5
b4
b3
b2
b1
b0
DBGEN
—
—
—
—
—
—
DOCDF
0
0
0
0
0
0
0
x
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
DOCDF
Deep Software Standby OCD Flag
Indicates cancel request by the DBIRQ:
0: DBIRQ is not generated
1: DBIRQ is generated.
R/(W)*1
b6 to b1
—
Reserved
These bits are read as 0. The write value must be 0.
R/W
b7
DBGEN
Debugger Enable Bit
0: Disable on-chip debugger
1: Enable on-chip debugger.
Set to 1 first in On-Chip Debug (OCD) mode.
R/W
Note 1.
Writing 0 clears the flag. Writing 1 is ignored.
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SYOCDCR is not initialized by the internal reset signal that cancels Deep Software Standby mode.
DOCDF flag (Deep Software Standby OCD Flag)
The DOCDF flag indicates that a Deep Software Standby cancel request is generated by the MCUCTRL.DBIRQ bit. The
flag is set to 1 when the cancel request is generated. The flag can be set to 1 when a cancel request is generated in any
mode, not only in Deep Software Standby mode. Clear the DOCDF flag to 0 before entering Deep Software Standby
mode.
[Setting condition]
A cancel request generated by the MCUCTRL.DBIRQ bit.
[Clearing condition]
Writing 0 to the flag after reading it as 1
When the DBGEN bit is 0.
DBGEN bit (Debugger Enable Bit)
The DBGEN bit enables the OCD mode. This bit must be set to 1 first in the OCD mode.
[Setting condition]
Writing 1 to the bit when the debugger is connected.
[Clearing condition]
Power-on reset is generated
Writing 0 to the bit.
11.2.24
Standby Condition Register (STCONR)
Address(es): SYSTEM.STCONR 4001 E40Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
—
STCON[1:0]
1
1
0
0
0
0
Bit
Symbol
Bit name
b1 to b0
STCON[1:0]
SSTBY Condition Bit
1
b0
1
Description
b1 b0
0
1
R/W
0: Set this value to transition to Software Standby mode when
using HOCO
1: Set this value to transition to Software Standby mode when
not using HOCO.
R/W
b5 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b6
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
STCON[1:0] bits (SSTBY Condition Bit)
The STCON[1:0] bits must always be set to 00b when using HOCO to enter Software Standby mode.
11.3
Reducing Power Consumption by Switching Clock Signals
When the SCKDIVCR.FCK[2:0], ICK[2:0], BCK[2:0], PCKA[2:0], PCKB[2:0], PCKC[2:0], and PCKD[2:0] bits are
set, the clock frequency changes. The module and clock associations are as follows:
The CPU, DMAC, DTC, flash, and SRAM use the operating clock specified in the ICK[2:0] bits
Peripheral modules use the operating clocks specified in the PCKA[2:0], PCKB[2:0], PCKC[2:0], and PCKD[2:0]
bits
The flash memory interface uses the operating clock specified in the FCK[2:0] bits
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The external bus uses the operating clock specified in the BCK[2:0] bits.
For details, see section 9, Clock Generation Circuit.
11.4
Module-Stop Function
The module-stop function can be set for each on-chip peripheral module. When the MSTPmi bit (m = A to D, i = 31 to 0)
in MSTPCRA to MSTPCRD is set to 1, the specified module stops operating and enters the module-stop state, but the
CPU continues to operate independently. Clearing the MSTPmi bit to 0 cancels the module-stop state, allowing the
module to resume operation at the end of the bus cycle. The internal states of the modules are retained in the module-stop
state.
After a reset is canceled, all modules other than the DMAC, DTC, and SRAM modules are placed in the module-stop
state. Do not access the module while the associated MSTPmi bit is 1. Otherwise, the read/write data and the operation of
the module is not guaranteed. Do not set the MSTPmi bit to 1 while the associated module is being accessed.
When the PLL is selected as the clock source, MSTPmi bits must be changed only one bit at a time. In this case, wait at
least 250 ns after changing each MSTPmi bit before starting subsequent processing if you change any of the following
bits:
MSTPA22 (DMAC, DTC)
MSTPB15 (ETHERC0, EDMAC0)
MSTPC31 (SCE7)
MSTPD5 (GPT32EH, GPT32E).
The recommended method to measure the wait time is through software. Be sure to consider the worst-case conditions to
ensure that the required wait time elapses.
11.5
Function for Lower Operating Power Consumption
Power consumption can be reduced in Normal, Sleep, and Snooze modes by selecting an appropriate operating power
mode for the given operating frequency and operating voltage.
11.5.1
Setting the Operating Power Control Mode
Make sure that the operating conditions, such as the voltage and frequency ranges, are always within the specified ranges
before and after switching the operating power control modes. This section provides example procedures for switching
operating power control modes.
Table 11.5
Available oscillators in each mode
Oscillator
Mode
PLL
High-speed
on-chip
oscillator
High-speed
Available
Available
Low-speed
N/A
Available
Available
Available
Available
Available
Available
Subosc-speed
N/A
N/A
N/A
Available
N/A
Available
Available
(1)
Middle-speed
on-chip
oscillator
Low-speed
on-chip
oscillator
Main clock
oscillator
Sub-clock
oscillator
IWDT-dedicated
on-chip
oscillator
Available
Available
Available
Available
Available
Switching from a higher to a lower power mode
Example 1: From High-speed mode to Low-speed mode
Operation begins in High-speed mode.
1. Change the oscillator to that used in Low-speed mode. Set the frequency of each clock lower than the maximum
operating frequency in Low-speed mode.
2. Turn off the oscillator that is not required in Low-speed mode.
3. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed).
4. Set the OPCCR.OPCM[1:0] bits to 11b (Low-speed mode).
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5. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed).
Operation is now in Low-speed mode.
Example 2: From High-speed mode to Subosc-speed mode
Operation begins in High-speed mode.
1. Change the clock source to the sub-clock oscillator.
2. Turn off HOCO, MOCO, LOCO, main oscillator, and PLL.
3. Confirm that all clock sources except the sub-clock oscillator are stopped.
4. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed).
5. Set the SOPCCR.SOPCM bit to 1 (Subosc-speed mode).
6. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed).
Operation is now in Subosc-speed mode.
(2)
Switching from a lower to a higher power mode
Example 1: From Subosc-speed mode to High-speed mode
Operation begins in Subosc-speed mode.
1. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed).
2. Set the SOPCCR.SOPCM bit to 0 (High-speed mode).
3. Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed).
4. Turn on the desired oscillator in High-speed mode.
5. Set the frequency of each clock lower than the maximum operating frequency for High-speed mode.
Operation is now in High-speed mode.
Example 2: From Low-speed mode to High-speed mode
Operation begins in Low-speed mode.
1. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed).
2. Set the OPCCR.OPCM[1:0] bits to 00b (High-speed mode).
3. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed).
4. Turn on any desired oscillator in High-speed mode.
5. Set the frequency of each clock lower than the maximum operating frequency for High-speed mode.
Operation is now in High-speed mode.
11.6
11.6.1
Sleep Mode
Transition to Sleep Mode
When a WFI instruction is executed while the SBYCR.SSBY bit is 0, the MCU enters Sleep mode. In Sleep mode, the
CPU stops operating, but the contents of its internal registers are retained. Other peripheral functions do not stop.
Available resets or interrupts in Sleep mode cause the MCU to cancel Sleep mode. All interrupt sources are available. If
using an interrupt to cancel Sleep mode, you must set the associated IELSRn register before executing a WFI instruction.
For details, see section 14, Interrupt Controller Unit (ICU).
Counting by the IWDT stops when the MCU enters Sleep mode while the IWDT is in auto start mode and the
OFS0.IWDTSTPCTL bit is 1 (IWDT stops in Sleep, Software Standby, or Snooze mode).
Counting by the IWDT continues when the MCU enters Sleep mode while the IWDT is in auto start mode and the
OFS0.IWDTSTPCTL bit is 0 (IWDT does not stop in Sleep, Software Standby, or Snooze mode).
Counting by the WDT stops when the MCU enters Sleep mode while the WDT is in auto start mode and the
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OFS0.WDTSTPCTL bit is 1 (WDT stops in Sleep mode). In the same way, counting by the WDT stops when the MCU
enters Sleep mode while the WDT is in register start mode and the WDTCSTPR.SLCSTP bit is 1 (WDT stops in Sleep
mode).
Counting by the WDT continues when the MCU enters Sleep mode while the WDT is in auto start mode and the OFS0.
WDTSTPCTL bit is 0 (WDT does not stop in Sleep mode). In the same way, counting by the WDT continues when the
MCU enters Sleep mode while the WDT is in register start mode and the WDTCSTPR.SLCSTP bit is 0 (WDT does not
stop in Sleep mode).
11.6.2
Canceling Sleep Mode
Sleep mode is canceled by:
An interrupt
RES pin reset
A power-on reset
A voltage monitor reset
An SRAM parity error reset
An SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
A reset caused by an IWDT
A WDT underflow.
The operations are as follows:
Canceling by an interrupt
When an available interrupt request (see Table 11.3) is generated, Sleep mode is canceled and the MCU starts the
interrupt handling.
Canceling by RES pin reset
When the RES pin is driven low, the MCU enters the reset state. You must keep the RES pin low for the time period
specified in section 55, Electrical Characteristics. When the RES pin is driven high after the specified time period,
the CPU starts the reset exception handling.
Canceling by IWDT reset
Sleep mode is canceled by an internal reset generated by an IWDT underflow, and the MCU starts the reset
exception handling. However, IWDT stops in Sleep mode and an internal reset for canceling Sleep mode is not
generated in the following conditions:
OFS0.IWDTSTRT = 0 and OFS0.IWDTSTPCTL = 1.
Canceling by WDT reset
Sleep mode is canceled by an internal reset generated by an WDT underflow and the MCU starts the reset exception
handling. However, WDT stops in Sleep mode even when counting in Normal mode and an internal reset for
canceling Sleep mode is not generated in the following conditions:
OFS0.WDTSTRT = 0 (auto start mode) and OFS0.WDTSTPCTL = 1
OFS0.WDTSTRT = 1 (register start mode) and WDTCSTPR.SLCSTP = 1.
Canceling by other resets available in Sleep mode
Sleep mode is canceled by the associated resets, and the MCU starts the reset exception handling.
Note:
For details on proper setting of the interrupts, see section 14, Interrupt Controller Unit (ICU).
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11.7
11. Low Power Modes
Software Standby Mode
11.7.1
Transition to Software Standby Mode
When a WFI instruction is executed while the SBYCR.SSBY bit is 1 and the DPSBYCR.DPSBY bit is 0, the MCU
enters Software Standby mode. In this mode, the CPU, most of the on-chip peripheral functions, and the oscillators stop.
However, the contents of the CPU internal registers and the SRAM data, the states of the on-chip peripheral functions,
and the I/O port states are retained. Software Standby mode allows a significant reduction in power consumption because
most of the oscillators stop in this mode. Table 11.2 shows the status of the on-chip peripheral functions and oscillators.
Available resets or interrupts in Software Standby mode cause the MCU to cancel Software Standby mode. See Table
11.3 for available interrupt sources and section 14.2.9, Wake Up Interrupt Enable Register (WUPEN) for information on
waking up the MCU from Software Standby mode. If using an interrupt to cancel Software Standby mode, you must set
the associated IELSRn register before executing a WFI instruction. For details, see section 14, Interrupt Controller Unit
(ICU).
The status of the address bus and bus control signals in Software Standby mode can be selected with the SBYCR.OPE
bit.
Clear the DMAST.DMST and DTCST.DTCST bits to 0 before executing a WFI instruction, except when using the DTC
in Snooze mode. If the DTC is required in Snooze mode, set the DTCST.DTCST bit to 1 before executing a WFI
instruction.
Counting by the IWDT stops when the MCU enters Software Standby mode while the IWDT is in auto start mode and
the OFS0.IWDTSTPCTL bit is 1 (IWDT stops in Sleep, Software Standby, or Snooze mode).
Counting by the IWDT continues when the MCU enters Software Standby mode while the IWDT is in auto start mode
and the OFS0.IWDTSTPCTL bit is 0 (IWDT does not stop in Sleep mode, Software Standby, or Snooze mode). The
WDT stops counting when the MCU enters Software Standby mode.
Do not enter Software Standby mode while OSTDCR.OSTDE is 1 (oscillation stop detection function enabled). To enter
Software Standby mode, execute a WFI instruction after disabling the oscillation stop detection function
(OSTDCR.OSTDE is 0). If software executes a WFI instruction while OSTDCR.OSTDE is 1, the MCU enters Sleep
mode even when SBYCR.SSBY is 1. Do not enter Software Standby mode while the flash memory is performing a
programming or erasing procedure. To enter Software Standby mode, execute a WFI instruction after the programming
or erasing procedure completes.
When the PLL is selected as the clock source, set the following modules to the module-stop state before executing a WFI
instruction:
ETHERC
EDMAC
SCE7
GPT32EH
GPT32E.
In this case, you must also insert a wait time of at least 750 ns before executing the WFI instruction. The recommended
method to measure the wait time is through software. Be sure to consider the worst-case conditions to ensure that the
required wait time elapses.
Table 11.6 shows the setting of the related control bits and the modes entered on execution of a WFI instruction.
Figure 11.2 shows an example flow for transitioning to Software Standby or Deep Software Standby mode.
Table 11.6
Bit settings that affect modes on WFI instruction execution (1 of 2)
SBYCR.SSBY and DPSBYCR.DPSBY bit settings
Other bit settings
OSTDCR.OSTDE
0
SSBY = 0, DPSBY = 0
SSBY = 0, DPSBY = 1
SSBY = 1, DPSBY = 0
SSBY = 1, DPSBY = 1
Sleep mode
Sleep mode
Software Standby
mode
Deep Software Standby
mode
Sleep mode
Sleep mode
1
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Table 11.6
11. Low Power Modes
Bit settings that affect modes on WFI instruction execution (2 of 2)
SBYCR.SSBY and DPSBYCR.DPSBY bit settings
Other bit settings
FENTRYR.FENTRYi
0
OFS0.IWDTSTPCTL
0
SSBY = 0, DPSBY = 0
SSBY = 0, DPSBY = 1
SSBY = 1, DPSBY = 0
SSBY = 1, DPSBY = 1
Sleep mode
Sleep mode
Software Standby
mode
Deep Software Standby
mode
Sleep mode
Sleep mode
Sleep mode
Sleep mode
Software Standby
mode
Software Standby mode
Software Standby
mode
Deep Software Standby
mode
1
1
LVD1CR0.RI
0
Sleep mode
Sleep mode
1
LVD2CR0.RI
0
Deep Software Standby
mode
Software Standby mode
Sleep mode
Sleep mode
Software Standby
mode
1
Deep Software Standby
mode
Software Standby mode
Start
No
SCKSCR.CKSEL = 101b?
Yes
No
MSTPB15, MSTPC31,
or MSTPD5 = 0?
Yes
Repeat for MSTPB15 to MSTPD5
MSTPB15 = 0?
No
Yes
Set ETHERC0 and EDMAC0 to the
module-stop state
Wait for 250 ns
Wait for 750 ns
Execute WFI instruction
Software Standby or
Deep Software Standby mode
Figure 11.2
11.7.2
Example flow for transition to Software Standby or Deep Software Standby mode
Canceling Software Standby Mode
Software Standby mode is canceled by:
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11. Low Power Modes
An available interrupt shown in Table 11.3
RES pin reset
A power-on reset
A voltage monitor reset
A reset caused by an IWDT underflow.
On exiting Software Standby mode, the oscillators that operate before transitioning to the mode restart. After all the
oscillators are stabilized, the MCU returns to Normal mode from Software Standby mode. See section 14.2.9, Wake Up
Interrupt Enable Register (WUPEN), for information on waking up the MCU from Software Standby mode.
You can cancel Software Standby mode in any of the following ways:
Canceling by an interrupt
When an available interrupt request (see Table 11.3) is generated, all oscillators that operate before the transition to
Software Standby mode restart. After all the oscillators are stabilized, the MCU cancels Software Standby mode and
starts the interrupt handling. When the PLL is selected as the clock source, you must insert a wait time of at least
250 ns at the beginning of the interrupt handling. The recommended method to measure the wait time is through
software. Be sure to consider the worst-case conditions to ensure that the required wait time elapses. Figure 11.3
shows an example flow for canceling Software Standby by an interrupt.
Canceling by RES pin reset
When the RES pin is driven low, the MCU enters the reset state and the oscillators start to operate in their default
status. Make sure to keep the RES pin low for the time period specified in section 55, Electrical Characteristics.
When the RES pin is driven high after the specified time period, the CPU starts the reset exception handling.
Canceling by a power-on reset
Software Standby mode is canceled by a power-on reset and the MCU starts the reset exception handling.
Canceling by a voltage monitor reset
Software Standby mode is canceled by a voltage monitor reset from the voltage detection circuit and the MCU starts
the reset exception handling.
Canceling by IWDT reset
Software Standby mode is canceled by an internal reset generated by an IWDT underflow, and the MCU starts reset
exception handling. However, IWDT stops in Software Standby mode and an internal reset for canceling Software
Standby mode is not generated in the following conditions:
OFS0.IWDTSTRT = 0 and OFS0.IWDTSTPCTL = 1.
Canceling by other resets available in Software Standby mode
Software Standby mode is canceled by the associated resets, and the MCU starts the reset exception handling.
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11. Low Power Modes
Start
SCKSCR.CKSEL = 101b?
No
Yes
Wait for 250 ns
Repeat for MSTPB15 to MSTPD5
Need to cancel
module-stop state of ETHERC0 and
EDMAC0?
No
Yes
Cancel module-stop state of ETHERC0 and
EDMAC0?
Wait for 250 ns
Start subsequent processing
Figure 11.3
11.7.3
Example flow for canceling Software Standby mode
Example of Software Standby Mode Application
Figure 11.4 shows an example of entry to Software Standby mode on detection of a falling edge of the IRQn pin, and exit
from Software Standby mode on a rising edge of the IRQn pin. In this example, an IRQn pin interrupt is accepted when
the IRQCRi.IRQMD[1:0] bits of the ICU are set to 01b (falling edge) in Normal mode, and then set to 10b (rising edge).
Next, the SBYCR.SSBY bit is set to 1 and a WFI instruction is executed. As a result, entry to Software Standby mode
completes, and exit from Software Standby mode is initiated by a rising edge of the IRQn pin.
Setting the ICU is also required to exit Software Standby mode. For details, see section 14, Interrupt Controller Unit
(ICU). The oscillation stabilization time in Figure 11.4 is specified in section 55, Electrical Characteristics.
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11. Low Power Modes
Oscillator
ICLK
IRQn pin
IRQMD[1:0]
01b
10b
SBYCR.SSBY
IRQ exception handling
IRQMD[1:0] = 10b
SBYCR.SSBY = 1
Oscillation
settling time
WFI instruction
Figure 11.4
11.8
IRQ exception handling
Software Standby mode
Example of Software Standby mode application
Snooze Mode
11.8.1
Transition to Snooze Mode
Figure 11.5 shows snooze mode entry configuration. When the snooze control circuit receives a snooze request in
Software Standby mode, the MCU transitions to Snooze mode. In this mode, some peripheral modules operate without
waking up the CPU. Table 11.2 shows the peripheral modules that can operate in Snooze mode. Also, DTC operation can
be selected in Snooze mode by setting the SNZCR.SNZDTCEN bit.
ICU
Snooze Control Circuit
WUPEN.bn
1
Wakeup request
Interrupt request
0
PAD (RXD0)
n = 0-15, 17, 22, 24, 25,
28-30
ELC
SNZCR.b7
SNZREQCR.bn
Control
SYSTEM_SNZREQ
(Snooze entry)
ELSRx
Event control
Snooze request
SNZCR.b0
Noise filter
+
Edge detect
SCI0
rxd
Figure 11.5
Snooze entry configuration
Table 11.7 shows the snooze requests to switch the MCU from Software Standby mode to Snooze mode. To use a listed
snooze requests as a trigger to switch to Snooze mode, you must set the associated SNZREQENn bit of the SNZREQCR
register or RXDREQEN bit of the SNZCR register before entering Software Standby mode.
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Table 11.7
11. Low Power Modes
Available snooze requests to switch to Snooze mode
Control Register
Snooze request
Bit*1
Register
PORT_IRQn (n = 0 to 15)
SNZREQCR
SNZREQENn (n = 0 to 15)
KEY_INTKR
SNZREQCR
SNZREQEN17
ACMP_HS0
SNZREQCR
SNZREQEN22
RTC_ALM
SNZREQCR
SNZREQEN24
RTC_PRD
SNZREQCR
SNZREQEN25
AGT1_AGTI
SNZREQCR
SNZREQEN28
AGT1_AGTCMAI
SNZREQCR
SNZREQEN29
AGT1_AGTCMBI
SNZREQCR
SNZREQEN30
RXD0 falling edge
SNZCR
RXDREQEN*2
Note 1.
Note 2.
Do not enable multiple snooze requests at the same time.
Do not set the RXDREQEN bit to 1 except in asynchronous mode.
11.8.2
Canceling Snooze Mode
Snooze mode is canceled by an interrupt request that is available in Software Standby mode or a reset. Table 11.3 shows
the requests that can be used to exit each mode. After canceling the Snooze mode, the MCU enters Normal mode and
proceeds with exception processing for the given interrupt or reset. The action triggered by the interrupt requests that is
selected in SELSR0, cancels Snooze mode. Interrupt canceling Snooze mode must be selected in IELSRn (n = 0 to 96) to
link to the NVIC for the corresponding interrupt handling. See section 14, Interrupt Controller Unit (ICU), for the setting
of SELSR0 and IELSRn registers.
WFI
instruction
Trigger
detection
Interrupt
request
High
Standby cancel
signal
Low
Snooze end
signal
Low
Low power mode
Normal
mode*3
Software
Standby
mode
Oscillator
for system clock
Oscillates
Oscillation
stopped
*1
Snooze mode
*2
Normal mode*4
Oscillates
Wait for oscillation accuracy stabilization
Note 1.
Note 2.
Note 3.
Note 4.
Figure 11.6
11.8.3
Transition time from Software Standby to Snooze mode.
Transition time from Snooze mode to Normal mode.
Enable Snooze mode (SNZCR.SNZE = 1) immediately before entering Software Standby mode.
You must disable Snooze mode (SNZCR.SNZE = 0) immediately after canceling Snooze mode.
Canceling of Snooze mode when an interrupt request signal is generated
Return to Software Standby Mode
Table 11.8 shows the snooze end requests that can be used as triggers to return to Software Standby mode. The snooze
end requests are available only in Snooze mode. If the requests are generated when the MCU is not in Snooze mode, they
are ignored. When multiple requests are selected, each one of the requests invokes transition to Software Standby mode
from Snooze mode.
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11. Low Power Modes
Table 11.9 shows the snooze end conditions that consist of the snooze end requests and the conditions of the peripheral
modules. The CTSU, SCI0, ADC120, ADC121, and DTC modules can keep the MCU in Snooze mode until they
complete their operation.
An AGT1 underflow as a trigger to return to Software Standby mode cancels Snooze mode without waiting for the
completion of the SCI0 operation.
Figure 11.7 shows the timing diagram for the transition from Snooze mode to Software Standby mode. This mode
transition occurs according to which snooze end requests are set in the SNZEDCR register. A snooze request is cleared
automatically after it is returned to Software Standby mode.
Table 11.8
Available snooze end requests (triggers to return to Software Standby mode)
Enable/disable control
Snooze end request
Register
Bit
AGT1 unterflow or measurement complete (AGT1_AGTI)
SNZEDCR
b0
DTC transfer completion (DTC_COMPLETE)
SNZEDCR
b1
Not DTC transfer completion (DTC_TRANSFER)
SNZEDCR
b2
ADC120 window A/B compare match (ADC120_WCMPM)
SNZEDCR
b3
ADC120 window A/B compare mismatch (ADC120_WCMPUM)
SNZEDCR
b4
ADC121 window A/B compare match (ADC121_WCMPM)
SNZEDCR
b5
ADC121 window A/B compare mismatch (ADC121_WCMPUM)
SNZEDCR
b6
SCI0 address mismatch (SCI0_DCUF)
SNZEDCR
b7
Table 11.9
Snooze end conditions
Operating module when a
Snooze end request occurs
DTC
ADC120
Snooze end request
AGT1 underflow
All except AGT1 underflow
The MCU transitions to Software Standby mode
after all of the modules listed to the left of this
column complete operation
The MCU transitions to Software Standby mode
after all of the modules complete operation
ADC121
CTSU
SCI0
The MCU transitions to Software Standby mode
immediately after a snooze end request is
generated
All other modules
The MCU transitions to Software Standby mode immediately after a snooze end request is generated
Note:
If the DTC is used to activate the ADC120, ADC121, CTSU, or SCI, the MCU transitions to Software Standby mode
immediately after a Snooze end request is generated.
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11. Low Power Modes
WFI
instruction
Trigger
detection
Standby cancel
signal
Low
Snooze end signal
Low power mode
Oscillator
for system clock
Normal
mode*2
Software
Standby
mode
Oscillates
Oscillation
stopped
*1
Snooze mode
Oscillates
Software Standby mode
Oscillation stopped
Wait for oscillation accuracy stabilization
Note 1.
Note 2.
Figure 11.7
11.8.4
Transition time from Software Standby to Snooze mode.
Enable Snooze mode (SNZCR.SNZE = 1) immediately before entering Software Standby mode.
Canceling of Snooze mode when interrupt request signal is not generated
Snooze Operation Example
Figure 11.8 shows an example setting for using ELC in Snooze mode.
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11. Low Power Modes
Start Snooze mode setting
Setting for ELC in Snooze mode
MSTPCRC.MSTPC14 = 0
Cancel ELC module-stop state
Snooze entry (SYSTEM_SNZREQ)
signal is linked to modules
ELSRx.ELS = 03Ch
ELCR.ELCON = 1
ELC function enabled
Setting for Snooze cancel
SELSR0.SELS = 0xxh
Select event number in Table 14.4 as
the source for canceling Snooze mode
IELSRy.DTCE = 0
IELSRy.IELS = 02Dh
Select canceling Snooze mode as the
interrupt request
Setting for snooze end
SNZEDCR.bm = 1
Enable snooze end request m
Setting for snooze request
WUPEN.bn = 0
SNZREQCR.bn = 1
Disable wakeup request n
Enable snooze request n
SNZCR.b7 = 1
(SNZE = 1)
Enable Snooze mode
Complete Snooze mode
setting
WFI instruction
Enter Software Standby mode
Software Standby mode
Snooze request?
No
Yes
Snooze mode
SYSTEM_SNZREQ
By way of ELC
Operating module
SELS event or
snooze end request?
SELS event
Snooze end request
Snooze end
Interrupt for
canceling Snooze mode
Normal mode
Figure 11.8
Setting example of using ELC in Snooze mode
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11. Low Power Modes
The MCU can transmit and receive data in SCI0 asynchronous mode without CPU intervention. When using the SCI0 in
Snooze mode, use either High-speed mode or Low-speed mode.
Do not use Subosc-speed mode. Table 11.10 shows the maximum transfer rate of SCI0 in Snooze mode.
Table 11.10
HOCO: ± 1.4% (Ta = -20 to 105°C)
Maximum division ratio
of ICLK, PCLKA,
PCLKB, PCLKC,
PCLKD, FCLK, BCLK,
and TRCLK
(Unit: bps)
HOCO frequency
LOCO is not operating
16 MHz
1
18 MHz
LOCO is operating
20 MHz
16 MHz
18 MHz
2400
4800
1200
2400
20 MHz
2
4
8
16
32
64
Figure 11.9 shows an example setting for using SCI0 in Snooze mode entry.
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Start Snooze mode setting
Setting for SCI0 in Snooze mode
MSTPCRB.MSTPB31 = 0
Cancel SCI0 module-stop state
Set SCI0
Set as asynchronous UART receive mode
SCKSCR.CKSEL = 0h
The clock source must be HOCO
MOCOCR.MCSTP = 1
MOSCCR.MOSTP = 1
PLLCR.PLLSTP = 1
Stop MOCO, the main clock oscillator, and
the PLL
MSTPCRC.MSTPC0 = 1
Enter CAC module-stop state
Hold the communications line in the mark
state before entering Software Standby
mode
RXD0 = 1
Setting for Snooze cancel
Select SCI0_RXI_OR_ERI event as the
source of canceling Snooze mode
SELSR0.SELS = 179h
IELSRy.DTCE = 0
IELSRy.IELS = 02Dh
Select canceling Snooze mode as the
interrupt request
Setting for Snooze end
SNZEDCR.b7 = 1
(SCI0UMTED = 1)
Enable snooze end request by SCI0
address mismatch
Setting for AGT1 to avoid Snooze mode by
a noise on the RXD0 pin
MSTPCRD.MSTPD2 = 0
Cancel AGT1 module-stop state
Set as a timer to avoid Snooze mode by a
noise on the RXD0 pin
Set AGT1
SNZEDCR.b0 = 1
(AGTUNFED = 1)
Enable snooze end request by
AGT1 underflow
Setting for snooze request
Detect RXD0 falling edge in Software
Standby mode as a request to transition to
Snooze mode
SNZCR.b0 = 1
(RXDREQEN) = 1
SNZCR.b7 = 1
(SNZE = 1)
Enable Snooze mode
Complete Snooze mode setting
WFI instruction
Enter Software Standby mode
Software Standby mode
Snooze request?
No
Yes
Snooze mode
SCI0 receive data
completed before
AGT1 underflow?
Yes
SELS event or
Snooze end request?
No
AGT1 underflow
SELS event
(receive data full or receive error)
Snooze end request
(address mismatch)
Snooze end
Interrupt for
canceling Snooze mode
Normal mode
Figure 11.9
Setting example of using SCI0 in Snooze mode entry
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11.9
11. Low Power Modes
Deep Software Standby Mode
11.9.1
Transition to Deep Software Standby Mode
The MCU enters Deep Software Standby mode when a WFI instruction is executed with the SBYCR.SSBY bit set to 1
and the DPSBYCR.DPSBY bit set to 1. See Table 11.6 for the settings of the related control bits.
In Deep Software Standby mode, the CPU, on-chip peripheral functions except for the RTC alarm, RTC interval, and
USB suspend/resume detecting unit, SRAM (not the Standby SRAM), and all oscillators except for the sub-clock
oscillator and low-speed on-chip oscillator are stopped. Power consumption is reduced because the internal power supply
to these modules is stopped. The contents of all of the CPU registers and internal peripheral modules, except for the RTC
alarm, RTC interval, and USB suspend/resume detecting unit, become undefined.
Data in the Standby SRAM is saved if the setting in the DEEPCUT[1:0] bits is 00b. If the setting in the DEEPCUT[1:0]
bits is 01b, the internal power supply to the Standby SRAM and the USB resume detecting unit is cut off, and power
consumption is reduced. Data in the Standby SRAM becomes undefined at this time.
If the setting in the DEEPCUT[1:0] bits is 11b, the internal power supply to the Standby SRAM and the USB resume
detecting unit is cut off, the LVD is stopped, and the low power mode function of the power-on reset circuit is enabled.
Therefore, power consumption is further reduced. For details, see section 55, Electrical Characteristics.
When the MCU enters Deep Software Standby mode while the IWDT is in auto start mode and the OFS0.IWDTSTPCTL
bit is 1, power supply to the IWDT-dedicated clock and the IWDT is cut off. Counting by the IWDT also stops.
When the OFS0.IWDTSTPCTL bit is 0, the MCU enters Software Standby mode instead of Deep Software Standby
mode, regardless of the setting in the OFS0.IWDTSTRT or DPSBYCR.DPSBY bit. When the OFS0.IWDTSTPCTL bit
is 0 while the OFS0.IWDTSTRT bit is 0 (auto start mode), the IWDT-dedicated clock and IWDT continue operation.
When the LVD1CR0.RI bit is 1 (selecting the voltage monitor 1 reset) or the LVD2CR0.RI bit is 1 (selecting the voltage
monitor 2 reset), the MCU enters Software Standby mode instead of Deep Software Standby mode. The I/O port states
are the same as in Software Standby mode.
When the PLL is selected as the clock source, set the following modules to the module-stop state before executing a WFI
instruction:
ETHERC
EDMAC
SCE7
GPT32EH
GPT32E.
In this case, you must also insert a wait time of at least 750 ns before executing the WFI instruction. The recommended
method to measure the wait time is through software. Be sure to consider the worst-case conditions to ensure that the
required wait time elapses.
Figure 11.2 shows an example flow for transitioning to Software Standby or Deep Software Standby mode.
Note 1. Conditions on the DTC, DMAC, and IWDT for transition to Software Standby mode must be met before the WFI
instruction is executed. For details, see section 11.7, Software Standby Mode.
11.9.2
Canceling Deep Software Standby Mode
Deep Software Standby mode is canceled by the interrupts shown in Table 11.3, a RES pin reset, a power-on reset, or a
voltage monitor 0 reset. The operations are as follows:
1. Canceling by an interrupt
Canceling by interrupts is controlled by DPSIERn (n = 0 to 3) and DPSIFRn (n = 0 to 3). When an available
interrupt request is generated, the associated flag in DPSIFRn is set to 1. If the interrupt is enabled in DPSIERn,
Deep Software Standby mode is canceled. Rising or falling edge detection can be selected in DPSIEGRn (n = 0 to
2). The detection edge can be selected for the NMI, IRQ0-DS to IRQ13-DS, voltage monitor 1, and voltage monitor
2 interrupts. When a Deep Software Standby mode canceling request occurs, internal power is supplied, the MOCO
clock starts to oscillate, and then an internal reset (Deep Software Standby reset) is generated for the entire MCU.
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The stable MOCO clock is supplied to the entire MCU and Deep Software Standby reset is canceled. The MCU
starts reset exception handling.
When Deep Software Standby mode is canceled by an external interrupt pin or internal interrupt signal, the
RSTSR0.DPSRSTF flag is set to 1.
2. Canceling by RES pin reset
When the RES pin is driven low, the MCU cancels Deep Software Standby mode and enters a reset state. Make sure
to keep the RES pin low for the time period specified in section 55, Electrical Characteristics. When the RES pin is
driven high after the specified time period, the CPU starts reset exception handling.
3. Canceling by power-on reset
Deep Software Standby mode is canceled by a power-on reset, and the MCU starts reset exception handling.
4. Canceling by voltage monitor 0 reset
Deep Software Standby mode is canceled by a voltage monitor 0 reset from the voltage detection circuit, and the
MCU starts reset exception handling.
11.9.3
Pin States when Deep Software Standby Mode is Canceled
In Deep Software Standby mode, the I/O ports retain the same states from Software Standby mode. The MCU is
initialized by an internal reset generated when Deep Software Standby mode is canceled, and reset exception handling
starts immediately. The DPSBYCR.IOKEEP bit setting determines whether to initialize the I/O ports or to retain the I/O
ports states for Software Standby mode. The following is the state of the I/O ports for each bit setting:
When the DPSBYCR.IOKEEP bit = 0
The I/O ports are initialized by an internal reset generated when Deep Software Standby mode is canceled.
When the DPSBYCR.IOKEEP bit = 1
Although the MCU is initialized by an internal reset generated when Deep Software Standby mode is canceled, the
I/O ports retain their states from Software Standby mode regardless of the MCU internal state. The I/O ports states
remain unchanged from Software Standby mode even when settings are made to the I/O ports or peripheral
modules. The retained I/O ports states are released by clearing the DPSBYCR.IOKEEP bit to 0, and the MCU
operates according to the internal state. The DPSBYCR.IOKEEP bit is not initialized by any internal reset generated
when Deep Software Standby mode is canceled.
11.9.4
(1)
Example of Deep Software Standby Mode Application
Entering and exiting Deep Software Standby mode
Figure 11.10 shows an example transition to Deep Software Standby mode on the falling edge of the IRQn-DS pin, and
an exit from Deep Software Standby mode on the rising edge of the IRQn-DS pin. In this example, an IRQn interrupt is
accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge). After the DPSIEGRy.DIRQnEG bit (y
= 0, 1 and n = 0 to 13) is set to 1 (rising edge) and the SBYCR.SSBY and DPSBYCR.DPSBY bits are both set to 1, the
WFI instruction is executed. As a result, the MCU transitions to Deep Software Standby mode. Deep Software Standby
mode is then canceled on the rising edge of the IRQn-DS pin.
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11. Low Power Modes
Oscillator
ICLK
IRQn-DS pin
IRQn interrupt
Disabled by an internal reset
Set
DIRQnF set request
Set
DIRQnEG bit
Set
DPSBY bit
Set
Clear
When IOKEEP = H
IOKEEP bit
I/O ports
Clear
Set
Active
Retained
Active
Active
Retained
Active
When IOKEEP = L
IOKEEP bit
I/O ports
DPSRSTF flag
Internal reset
IRQn exception
handling
DIRQnEG = 1
SSBY = 1
DPSBY = 1
Figure 11.10
11.9.5
Deep Software Standby mode
(power-down state)
Oscillation
stabilization
time
Reset exception
handling
WFI instruction
Example of Deep Software Standby mode application
Usage Flow for Deep Software Standby Mode
Figure 11.11 shows an example flow for using Deep Software Standby mode. In this example, the RSTSR0.DPSRSTF
flag of the reset function is read after reset exception handling to determine whether the reset is generated by the RES pin
or by the cancellation of Deep Software Standby mode. For a reset by the RES pin, the MCU transitions to Deep
Software Standby mode after the required register settings are made. For a reset by cancellation of Deep Software
Standby mode, the DPSBYCR.IOKEEP bit is set to 0 after the I/O port settings are made.
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11. Low Power Modes
After reset
Reset exception handling
Program start
No
RSTSR0.DPSRSTF =
0
Yes
Set the following:
• SBYCR.SSBY = 1
• DPSBYCR.DPSBY = 1
• DPSBYCR.DEEPCUT[1:0]
Select Deep Software
Standby mode
Read DPSIFRy
Set PCNTR1.PDRn and
PCNTR1.PODRn
Set PCNT1.PDR and
PCNT1.PODR
Set SBYCR.OPE
Set pin states during
and after Deep
Software Standby
mode
Set DPSBYCR.IOKEEP = 1
Set DPSBYCR.IOKEEP = 0
Identify Deep Software
Standby mode
canceling source -- (1)
Set pin states after
clearing IOKEEP to 0
Release pin states that
are retained after
transition to Deep
Software Standby mode
Execute program for
canceling source identified in
(1)
Set DPSIEGRy
Set DPSIERy
Set an interrupt for exiting Deep
Software Standby mode
Confirm DPSIERy setting
Clear DPSIFRy
Read I/O register
Confirm the last register setting
that was written
Read CS/SDRAM area
Execute WFI instruction
Deep Software Standby
mode
Figure 11.11
Example flow for using Deep Software Standby mode
11.10 Usage Notes
11.10.1
(1)
Register Access
Invalid register write accesses during specific modes or transitions
Do not write to registers under any of the listed conditions in this section.
[Registers]
All registers with a peripheral name of SYSTEM.
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11. Low Power Modes
[Conditions]
OPCCR.OPCMTSF = 1 or SOPCCR.SOPCMTSF = 1 (during transition of the operating power control mode)
During the time period from executing a WFI instruction to returning to Normal mode
When FENTRYR.FENTRYi = 1 (i = 0 to 3) (flash P/E mode) or FENTRYR.FENTRYD = 1 (data flash P/E mode).
(2)
Valid settings for the clock-related registers
Table 11.11 and Table 11.12 show the valid settings of the clock-related registers in each operating power control mode.
Do not write any value other than the valid setting. Any other written value is ignored. Each register has certain
prohibited settings under conditions other than those related to the operating power control modes. See section 9, Clock
Generation Circuit, for these other conditions for each register.
Table 11.11
Valid settings for the clock-related registers (1)
Valid settings
SCKSCR.CKSEL[2:0],
CKOCR.CKOSEL[2:0]
SCKDIVCR.FCK[2:0],
ICK[2:0]
High-speed
000b (HOCO)
001b (MOCO)
010b (LOCO)
011b (Main clock)
100b (Sub-clock)
101b (PLL)*1
0 (operating)
1 (stopped)
Low-speed
000b (HOCO)
001b (MOCO)
010b (LOCO)
011b (Main clock)
100b (Sub-clock)
000b (1/1)
001b (1/2)
010b (1/4)
011b (1/8)
100b (1/16)
101b (1/32)
110b (1/64)
Suboscspeed
010b (LOCO)
100b (Sub-clock)
000b (1/1)
1 (stopped)
Mode
Note 1.
PLLCR.PLLSTP
HOCOCR.
HCSTP
MOCOCR.
MCSTP
LOCOCR.
LCSTP
MOSCCR.
MOSTP
SOSCCR.
SOSTP
0
(operating)
1 (stopped)
0
(operating)
1 (stopped)
0
(operating)
1 (stopped)
0
(operating)
1
(stopped)
0
(operating)
1 (stopped)
1 (stopped)
1 (stopped)
0
(operating)
1 (stopped)
1
(stopped)
0
(operating)
1 (stopped)
1 (stopped)
SCKSCR.CKSEL[2:0] only.
Table 11.12
Valid settings for the clock related registers (2)
Valid settings
Operating oscillator
OPCCR.OPCM[1:0]
SOPCCR.SOPCM
PLL
00b
0
High-speed on-chip oscillator
00b, 11b
0
00b, 11b
0, 1
Middle-speed on-chip oscillator
Main clock oscillator
Low-speed on-chip oscillator
Sub-clock oscillator
IWDT-dedicated on-chip oscillator
(3)
Invalid register write accesses in subosc-speed mode
Do not write to registers under the listed condition in this section.
[Registers]
SCKSCR, OPCCR.
[Condition]
SOPCCR.SOPCM = 1 (Subosc-speed mode).
(4)
Invalid register write accesses by the DTC or DMAC
Do not write to registers listed in this section by the DTC or DMAC.
[Registers]
MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD.
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(5)
11. Low Power Modes
Invalid register write accesses in Snooze mode
Do not write to registers listed in this section in Snooze mode. They must be set before entering Software Standby mode.
[Registers]
SNZCR, SNZEDCR, SNZREQCR.
(6)
Invalid write access to FLWT.FLWT[2:0]
Do not write any value other than 000b to the FLWT.FLWT[2:0] bits under the listed condition.
[Condition]
SOPCCR.SOPCM = 1 (Subosc-speed mode)
(7)
Invalid write access when PRCR.PRC1 is 0
Do not write to registers listed in this section when the PRCR.PRC1 bit is 0.
[Registers]
SBYCR, SNZCR, SNZEDCR, SNZREQCR, OPCCR, SOPCCR, DPSBYCR, DPSIERn (n = 0 to 3), DPSIFRn (n =
0 to 3), DPSIEGRn (n = 0 to 2), and SYOCDCR.
11.10.2
I/O Port States
The I/O port states in Software Standby, Deep Software Standby, and Snooze modes (except when modifying in Snooze
mode) are the same before entering the modes. Therefore, power consumption is not reduced while the output signals are
held high.
11.10.3
Module-Stop State of DMAC and DTC
Before writing 1 to MSTPCRA.MSTPA22, clear the DMAST.DMST bit of the DMAC and the DTCST.DTCST bit of the
DTC to 0.
11.10.4
Internal Interrupt Sources
Interrupts do not operate in the module-stop state. If the module-stop bit is set when an interrupt request is generated, a
CPU interrupt source or a DMAC or DTC startup source cannot be cleared. Always disable the associated interrupts
before setting the module-stop bits.
11.10.5
Input Buffer Control by the DIRQnE Bit (n = 0 to 13)
Setting the DPSIERy.DIRQnE bit (y = 0, 1 and n = 0 to 13) to 1 enables the associated input buffer of the IRQ0-DS to
IRQ13-DS pins. Although inputs to these pins are sent to the DPSIFRy.DIRQnF bits (y = 0, 1 and n = 0 to 13), they are
not sent to the ICU, peripheral modules, or I/O ports.
11.10.6
Transition to Low Power Modes
Because the MCU does not support wakeup by events, do not enter the low power modes (Sleep, Software Standby, or
Deep Software Standby mode) by executing a WFE instruction. Also, do not set the SLEEPDEEP bit of the System
Control Register in the Cortex®-M4 core, because the MCU does not support low power modes by SLEEPDEEP.
11.10.7
Timing of WFI Instruction
It is possible for the WFI instruction to be executed before I/O register and CS/SDRAM area writes are complete, in
which case operation might not proceed as intended. This can happen if the WFI is placed immediately after a write to an
I/O register or CS/SDRAM area. To avoid this problem, read back the register or CS/SDRAM area that was written to
confirm that the write completed.
11.10.8
Writing to the WDT and IWDT Registers by the DMAC or DTC in Sleep or
Snooze Mode
Do not write to the WDT or IWDT registers by the DMAC or DTC while the WDT or IWDT is stopped after entering
Sleep or Snooze mode.
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11.10.9
11. Low Power Modes
Oscillators in Snooze Mode
Oscillators that stop on entering Software Standby mode automatically restart when a trigger for switching to Snooze
mode is generated. The MCU does not enter Snooze mode until all of the oscillators stabilize. In Snooze mode, you must
disable oscillators that are not required in Snooze mode before entering Software Standby mode. Otherwise, the
transition from Software Standby to Snooze mode takes longer.
11.10.10
Snooze Mode Entry by RXD0 Falling Edge
When the SNZCR.RXDREQEN bit is 1, noise on the RXD0 pin might cause the MCU transition from Software Standby
to Snooze mode. Any subsequent RXD0 data can be received in Snooze mode by noise on the RXD0 pin. If the MCU
does not receive any RXD0 data after the noise, interrupts such as SCI0_ERI or SCI0_RXI, and address mismatch events
are not generated, the MCU stays in Snooze mode. To avoid this, an AGT1 underflow interrupt must be used to return to
Software Standby or Normal mode when using SCI0 in Snooze mode. However, do not use the AGT1 underflow as a
source to return to Software Standby mode during an SCI communication. This makes the SCI0 stop the operation in a
half-finished state.
11.10.11
Using SCI0 in Snooze Mode
When using SCI0 in Snooze mode, the AGT1 underflow must be used for the interrupt request or Snooze end request. Do
not use any other trigger.
When using SCI0 in Snooze mode, the following conditions must be satisfied:
The clock source must be HOCO
MOCO, the main clock oscillator, and the PLL must be stopped before entering Software Standby mode
The RXD0 pin must be kept at the high level before entering Software Standby mode
A transition to Software Standby mode must not occur during an SCI communication
The MSTPCRC.MSTPC0 bit must be 1 before entering Software Standby mode.
11.10.12
Conditions of A/D Conversion Start in Snooze Mode
The ADC12 can only be triggered by the ELC in Snooze mode. Do not use a software trigger or ADTRGn pin.
11.10.13
ELC Events in Snooze Mode
Only the ELC events listed in this section are available in Snooze mode. Do not use any other events. If starting
peripheral modules for the first time after entering Snooze mode, the Event Link Setting Register (ELSRn) must set a
Snooze mode entry event (SYSTEM_SNZREQ) as the trigger.
Snooze mode entry (SYSTEM_SNZREQ)
DTC transfer end (DTC_DTCEND)
ADC12n Window A/B compare match (ADC12n_WCMPM) (n = 0, 1)
ADC12n Window A/B compare mismatch (ADC12n_WCMPUM) (n = 0, 1)
Data operation circuit interrupt (DOC_DOPCI).
11.10.14
Conditions of CTSU in Snooze Mode
The CTSU can only be started by the ELC in Snooze mode.
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12.
Battery Backup Function
12.1
Overview
12. Battery Backup Function
The MCU provides a battery backup function that maintains partial battery powering in the event of a power loss.
Switching between VCC and VBATT, the battery-powered area includes RTC, SOSC, and backup memory.
During normal operation, the battery-powered area is powered by the main power supply, the VCC pin. When a VCC
voltage drop is detected, the power source switches to the dedicated battery backup power pin, the VBATT pin. When the
voltage rises again, the power source switches back from VBATT to VCC.
12.1.1
Features of Battery Backup Function
The features include:
Battery power supply switch
Backup registers
Time capture pin detection.
12.1.2
Battery Power Supply Switch
When the voltage applied to the VCC pin drops, this feature switches the power supply from the VCC pin to the VBATT
pin. When the voltage rises, it switches the power supply from the VBATT pin back to the VCC pin.
12.1.3
Backup Registers
The battery-powered area provides 512 one-byte backup registers. These registers retain data only when VBATT is
supplied and VCC is powered off.
12.1.4
Time Capture Pin Detection
The RTC detects input level changes on the time capture pin. For more information, see section 26, Realtime Clock
(RTC).
Note:
Note:
When VCC is < VDETBATT and > (VBATT + 0.6 V), the injected current flows from the VCC to the VBATT pin
through an internal diode. If the power supply battery connected to the VBATT pin cannot support this current
injection, for example if the battery is not rechargeable, Renesas strongly recommends that you connect through
a low-voltage threshold diode between the power supply battery and the VBATT pin.
You must enable voltage monitor 0 resets to use the battery backup function. The voltage monitor 0 level must be
higher than the VBATT switch level.
Figure 12.1 shows the configuration of the battery backup function.
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12. Battery Backup Function
Voltage drop
detection
VCC
VBATT
Switch
control
XCIN
Sub-clock
oscillator
XCOUT
VBATT backup register
RTC
RTCIC0 to
RTCIC2
pins
Backup power area
VCC:
VBATT:
XCIN/XCOUT:
RTCICn (n = 0 to 2):
Figure 12.1
12.2
Main power supply pin
Battery backup power supply pin
SOSC input/output
Input port for battery backup function
Configuration of the battery backup function
Register Descriptions
12.2.1
VBATT Backup Register (VBTBKRn) (n = 0 to 511)
Address(es): SYSTEM.VBTBKR[0] 4001 E500h to SYSTEM.VBTBKR[511] 4001 E6FFh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
VBTBKR[7:0]
Value after reset:
x
x
x
x
x
x: Undefined
VBTBKRn is an 8-bit access read/write register to store data powered by VBATT. The value of this register is retained
when VCC is not powered and VBATT is powered. This register is not initialized by any reset.
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12.2.2
12. Battery Backup Function
VBATT Input Control Register (VBTICTLR)
Address(es): SYSTEM.VBTICTLR 4001 E4BBh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
VCH2I VCH1I VCH0I
NEN
NEN
NEN
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
VCH0INEN
VBATT CH0 Input Enable
0: Disable
1: Enable.
R/W
b1
VCH1INEN
VBATT CH1 Input Enable
0: Disable
1: Enable.
R/W
b2
VCH2INEN
VBATT CH2 Input Enable
0: Disable
1: Enable.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The VBTICTLR register selects the VBATT I/O direction as input.
VCHnINEN bit (VBATT CHn Input Enable Bit) (n = 0 to 2)
The VCHnINEN bit enables the input direction on the associated VBATT channel.
For more information on CH0 to CH2 associated function, see section 20.5.5, I/O Buffer Specification.
12.3
Operation
12.3.1
Battery Backup Function
When the voltage on the VCC pin drops, power can be supplied to the RTC and sub-clock oscillator from the VBATT
pin. When a power supply drop from the VCC pin is detected, the power connection switches from the power supply to
the VBATT pin. The power supply from the VCC pin is resumed when the voltage on the VCC pin exceeds VDETBATT.
This power supply change does not affect the RTC operation.
You must enable voltage monitor 0 resets to use the battery backup function. The RTC supports time capture detection,
triggered by a change to the time capture pin input level.
The VBATT pin supplies power to the following modules:
RTC
Sub-clock oscillator (including XCIN and XCOUT pins)
VBATT Backup Register.
Table 12.1 shows the operating states in VBATT mode.
Table 12.1
Operating states in VBATT mode (1 of 2)
Operating state
VBATT mode
Transition condition
Detection of VCC voltage drop
Canceling method other than reset
Detection of VCC voltage rise
State after cancellation by an interrupt
—
State after cancellation by a reset
—
Main clock oscillator
Stopped
Sub-clock oscillator
Operating
High-speed on-chip oscillator
Stopped
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Table 12.1
12. Battery Backup Function
Operating states in VBATT mode (2 of 2)
Operating state
VBATT mode
Middle-speed on-chip oscillator
Stopped
Low-speed on-chip oscillator
Stopped
IWDT-dedicated on-chip oscillator
Stopped
PLL
Stopped
CPU
Stopped (undefined)
SRAM (ECC SRAM included)
Stopped (undefined)
Standby SRAM
Stopped (undefined)
VBATT Backup Register
Stopped (retained)
Flash memory
Stopped (retained)
Realtime Clock (RTC)
Selectable when selecting clock that serves as the count source
AGTn (n = 0, 1)
Stopped (undefined)
Low Voltage Detection (LVD)
Stopped
Power-on reset circuit
Stopped
Other peripheral modules
Stopped (undefined)
I/O ports
RTCICn ports (n = 0 to 2): Operating
Other than the specified ports: Undefined.
Note:
Note:
Note:
Selectable means that operating or stopped is selectable in the control registers. Some modules are also controlled by the
associated module-stop bit.
Stopped (retained) means that the contents of the internal registers are retained but the operations are suspended.
Stop (undefined) means that the contents of the internal registers are undefined and power to the internal circuit is cut off.
Figure 12.2 shows the switching sequence of the battery backup function.
Power supply from VCC pin is halted
LVD0 detection level
VCC
VCC pin voltage
VBATT pin voltage
VDETBATT*1
VBATT
Reset by LVD0
VCC
Automatically switched
Voltage of backup
power area
VBATT
Power supply from
VCC pin
Note:
Note 1.
Figure 12.2
Power supply from
VBATT pin
Power supply from
VCC pin
For details on electrical characteristics, see section 55, Electrical Characteristics.
VDETBATT indicates the threshold level of the power supply change between the VCC pin and the VBATT pin.
Switching sequence for the battery backup function
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12.3.2
12. Battery Backup Function
VBATT Battery Power Supply Switch Usage
The battery power supply switch can switch the power supply from the VCC pin to the VBATT pin when the voltage
applied to the VCC pin drops. When the voltage rises, this switch changes the power supply from the VBATT pin to the
VCC pin.
Note:
12.3.3
You must enable voltage monitor 0 resets to use the battery backup function. Voltage monitor 0 level must be
higher than the VBATT switch level.
VBATT Backup Register Usage
Use the VBATT backup registers VBTBKRn, where n = 0 to 511, to store or restore data with an 8-bit read or write
operation.
12.4
Usage Notes
1. When the voltage level on VBATT is lower than the guaranteed operation range, operation of the sub-clock
oscillator and RTC cannot be guaranteed. The RTC must be initialized to restart the power supply after the VBATT
pin falls below the guaranteed operating voltage.
2. If a reset is generated while writing to the registers described in this section, the register values might be lost.
3. When VCC is higher than VDETBATT, the VCC and VBATT pins are separated. When VCC is lower than
VDETBATT and the switch is connected to the VBATT pin, and if the voltage on VBATT drops lower than (VCC 0.6 V), current might flow into the VBATT pin through the parasitic diode between the VCC and VBATT pins.
4. During RTC operation using the voltage from the VBATT pin and the I/O ports (P402, P403 and P404) within the
backup, the power supply area can only be used as time capture event input pins for the RTC.
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13. Register Write Protection
13.
Register Write Protection
13.1
Overview
The register write protection function protects important registers from being overwritten because of software errors. The
registers to be protected are set with the Protect Register (PRCR).
Table 13.1 lists the association between the PRCR bits and the registers to be protected.
Table 13.1
Association between PRCR bits and registers to be protected
PRCR bit
Registers to be protected
PRC0
Registers related to the clock generation circuit:
SCKDIVCR, SCKDIVCR2, SCKSCR, PLLCCR, PLLCR, BCKCR, MOSCCR, HOCOCR, MOCOCR, CKOCR,
TRCKCR, OSTDCR, OSTDSR, EBCKOCR, SDCKOCR, MOCOUTCR, HOCOUTCR, MOSCWTCR, MOMCR,
SOSCCR, SOMCR, LOCOCR, LOCOUTCR, HOCOWTCR, FLLCR1, FLLCR2
PRC1
Registers related to the low power modes:
SBYCR, SNZCR, SNZEDCR, SNZREQCR, OPCCR, SOPCCR, DPSBYCR, DPSIER0-3, DPSIFR0-3,
DPSIEGR0-2, SYOCDCR, STCONR
Registers related to the battery backup function:
VBTBKRn (n = 0 to 511), VBTICTLR
PRC3
Registers related to the LVD:
LVD1CR1, LVD1SR, LVD2CR1, LVD2SR, LVCMPCR, LVDLVLR, LVD1CR0, LVD2CR0
13.2
Register Descriptions
13.2.1
Protect Register (PRCR)
Address(es): SYSTEM.PRCR 4001 E3FEh
b15
b14
b13
b12
b11
b10
b9
b8
PRKEY[7:0]
Value after reset:
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
PRC3
—
PRC1
PRC0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Function
R/W
b0
PRC0
Protect Bit 0
Enables writing to the registers related to the clock generation circuit:
0: Disable writes
1: Enable writes.
R/W
b1
PRC1
Protect Bit 1
Enables writing to the registers related to the low power modes and the
battery backup function:
0: Disable writes
1: Enable writes.
R/W
b2
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b3
PRC3
Protect Bit 3
Enables writing to the registers related to the LVD:
0: Disable writes
1: Enable writes.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
PRKEY[7:0]
PRC Key Code
These bits control write access to the PRCR register. To modify the
PRCR register, write A5h to the upper 8 bits and the target value to the
lower 8 bits as a 16-bit unit.
W*1
Note 1.
Write data is not retained. Always reads 00h.
PRCn bits (Protect Bit n) (n = 0, 1, 3)
The PRCn bits enable or disable writing to the protected registers listed in Table 13.1. Setting PRCn to 1 or 0 enables or
disables writing, respectively.
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14. Interrupt Controller Unit (ICU)
14.
Interrupt Controller Unit (ICU)
14.1
Overview
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC, DTC, and DMAC modules.
The ICU also controls non-maskable interrupts. Table 14.1 lists the ICU specifications, Figure 14.1 shows a block
diagram, and Table 14.2 lists the I/O pins.
Table 14.1
ICU specifications
Parameter
Interrupts
Non-maskable
interrupts*2
Specifications
Peripheral function interrupts
Interrupts from peripheral modules
Number of sources: 301 (select factors within event list numbers 64 to 511)
External pin interrupts
Interrupt detection on low level, falling edge, rising edge, rising and falling edges
One of these detection methods can be set for each source.
Digital filter function supported
16 sources, with interrupts from IRQ0 to IRQ15 pins.
DTC and DMAC control
The DTC and DMAC can be activated using interrupt sources*1
Interrupt sources for NVIC
96 sources
NMI pin interrupt
Interrupt from the NMI pin
Interrupt detection on falling edge or rising edge
Digital filter function supported.
Oscillation stop detection
interrupt*3
Interrupt on detecting that the main oscillator has stopped
WDT underflow/refresh error*3
Interrupt on an underflow of the down-counter or occurrence of a refresh error
IWDT underflow/refresh
error*3
Interrupt on an underflow of the down-counter or occurrence of a refresh error
Voltage monitor 1 interrupt*3
Voltage monitor interrupt of low voltage detection detector 1 (LVD1)
Voltage monitor 2 interrupt*3
Voltage monitor interrupt of low voltage detection detector 2 (LVD2)
RPEST
Interrupt on SRAM parity error
RECCST
Interrupt on SRAM ECC error
BUSSST
Interrupt on MPU bus slave error
BUSMST
Interrupt on MPU bus master error
SPEST
Interrupt on CPU stack pointer monitor
Return from low power mode*4
Note 1.
Note 2.
Note 3.
Note 4.
Sleep mode: return is initiated by non-maskable interrupts or any other interrupt
source
Software Standby mode: return is initiated by non-maskable interrupts
Interrupts can be selected in the WUPEN register.
Snooze mode: return is initiated by non-maskable interrupts
Interrupts can be selected in the SELSR0 and WUPEN registers.
See section 14.2.8, SYS Event Link Setting Register (SELSR0), and section
14.2.9, Wake Up Interrupt Enable Register (WUPEN).
For the DTC and DMAC activation sources, see Table 14.4.
Non-maskable interrupts can be enabled only once after a reset release.
These non-maskable interrupts can also be used as event signals. When used as interrupts, do not change the value of the
NMIER register from the reset state. To enable voltage monitor 1 and voltage monitor 2 interrupts, set the LVD1CR1.IRQSEL
and LVD2CR1.IRQSEL bits to 1.
For return from Deep Software Standby mode, see section 11.9, Deep Software Standby Mode.
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14. Interrupt Controller Unit (ICU)
Interrupt Controller
CPU stack pointer monitor error
MPU bus master error
MPU bus slave error
SRAM ECC error
SRAM parity error
IWDT underflow/refresh error
WDT underflow/refresh error
Oscillation stop detection interrupt
Clock recovery request
NMI
SR
Voltage monitor 2 interrupt
Voltage monitor 1 interrupt
Low voltage detection
Digital
filter
NMI pin
Clock recovery
determination
Detection
NFCL NFLT
KSEL EN
NMI
MD
NMI
CLR
Clock recovery enable level
NMI
ER
Clock
generation
circuit
CPU
WUPEN
Non-maskable interrupt request
Module data bus
IRQ
MD
Digital
filter
Detection
IRQ0
IRQ15
DTCE
Wakeup signal
Snooze Mode cancellation
(Generated from the output of SELSR0)
NVIC
FCLK FLT
SEL EN
SELSR0
Peripheral
modules
Interrupt request
IELSRn
Control
Interrupt
source
[95:0]
DMAC
DTC
Destination switchover
to CPU
DTC activation
request
IR
DTC
activation
control
DMAC activation
request
DMAC activation request[7:0]
Figure 14.1
DTC response
Interrupt status and transfer destination switching
DELSRm
NMISR:
NMIER:
NMICLR:
NMIMD:
NFCLKSEL:
NFLTEN:
IRQMD:
FCLKSEL:
FLTEN:
SELSR0:
WUPEN:
IELSRn:
IR:
DTCE:
DELSRm:
DTC
DMAC
activation
control
DMAC
DMAC response
Non-Maskable Interrupt Status Register
Non-Maskable Interrupt Enable Register
Non-Maskable Interrupt Status Clear Register
NMI Detection Set (NMICR.NMIMD)
NMI Digital Filter Sampling Clock Select (NMICR.NFCLKSEL)
NMI Digital Filter Enable (NMICR.NFLTEN)
IRQi Detection Sense Select (IRQCRi.IRQMD (i = 0 to 15))
IRQi Digital Filter Sampling Clock Select (IRQCRi.FCLKSEL (i = 0 to 15))
IRQi Digital Filter Enable (IRQCRi.FLTEN (i = 0 to 15))
SYS Event Link Setting Register 0
Wake Up Interrupt Enable Register
ICU Event Link Setting Register (n = 0 to 95)
Interrupt Status Flag (IELSRn.IR)
DTC Activation Enable (IELSRn.DTCE)
DMAC Event Link Setting Register (m = 0 to 7)
ICU block diagram
Table 14.2 lists the ICU input/output pins.
Table 14.2
ICU I/O pins
Pin name
I/O
Description
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ15
Input
External interrupt request pins
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14.2
14. Interrupt Controller Unit (ICU)
Register Descriptions
This chapter does not describe the Arm® NVIC internal registers. For information on these registers, see the ARM®
Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D).
14.2.1
IRQ Control Register i (IRQCRi) (i = 0 to 15)
Address(es): ICU.IRQCR0 4000 6000h, ICU.IRQCR1 4000 6001h, ICU.IRQCR2 4000 6002h, ICU.IRQCR3 4000 6003h,
ICU.IRQCR4 4000 6004h, ICU.IRQCR5 4000 6005h, ICU.IRQCR6 4000 6006h, ICU.IRQCR7 4000 6007h
ICU.IRQCR8 4000 6008h, ICU.IRQCR9 4000 6009h, ICU.IRQCR10 4000 600Ah, ICU.IRQCR11 4000 600Bh,
ICU.IRQCR12 4000 600Ch, ICU.IRQCR13 4000 600Dh, ICU.IRQCR14 4000 600Eh, ICU.IRQCR15 4000 600Fh
b7
b6
FLTEN
—
0
0
Value after reset:
b5
b4
FCLKSEL[1:0]
0
0
b3
b2
b1
—
—
IRQMD[1:0]
0
0
0
b0
0
Bit
Symbol
Bit name
b1, b0
IRQMD[1:0]
IRQi Detection Sense Select
Description
b3, b2
—
Reserved
b5, b4
FCLKSEL[1:0]
IRQi Digital Filter Sampling Clock
Select
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
FLTEN
IRQi Digital Filter Enable
0: Disable
1: Enable.
R/W
b1 b0
0
0
1
1
0:
1:
0:
1:
R/W
R/W
Falling edge
Rising edge
Rising and falling edges
Low level.
These bits are read as 0. The write value should be 0.
b5 b4
0
0
1
1
0:
1:
0:
1:
R/W
R/W
PCLKB
PCLKB/8
PCLKB/32
PCLKB/64.
IRQCRi register changes must satisfy the following conditions:
For a CPU interrupt or DTC trigger:
Change the IRQCRi register setting before setting the target IELSRn register (n = 0 to 95).
You can change the register values only when the IELSRn.IELS[8:0] bits are 000h.
For a DMAC trigger:
Change the IRQCRi register setting before setting the target DELSRn register (n = 0 to 7).
You can change the register values only when the DELSRn.DELR[8:0] bits are 000h.
For a wakeup enable signal:
Change the IRQCRi register setting before setting the target WUPEN.IRQWUPEN[n] (n = 0 to 15).
You can only change the register values when the target WUPEN.IRQWUPEN[n] is 0.
IRQMD[1:0] bits (IRQi Detection Sense Select)
The IRQMD[1:0] bits set the detection sensing method for the IRQi external pin interrupt sources. For more information
on the settings, see section 14.4.4, External Pin Interrupts.
FCLKSEL[1:0] bits (IRQi Digital Filter Sampling Clock Select)
The FCLKSEL[1:0] bits select the digital filter sampling clock for the IRQi external pin interrupt requests, selectable to:
PCLKB (every cycle)
PCLKB/8 (once every 8 cycles)
PCLKB/32 (once every 32 cycles)
PCLKB/64 (once every 64 cycles).
For details on the digital filter, see section 14.4.3, Digital Filter.
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14. Interrupt Controller Unit (ICU)
FLTEN bit (IRQi Digital Filter Enable)
The FLTEN bit enables the digital filter used for the IRQi external pin interrupt sources. The filter is enabled when
FLTEN is 1 and disabled when FLTEN is 0. The IRQi pin level is sampled at the cycle specified in FCLKSEL[1:0].
When the sampled level matches three times, the output level from the digital filter changes. For details on the digital
filter, see section 14.4.3, Digital Filter.
14.2.2
Non-Maskable Interrupt Status Register (NMISR)
Address(es): ICU.NMISR 4000 6140h
Value after reset:
b15
b14
b13
—
—
—
0
0
0
b12
b11
b10
b9
b8
b7
b6
SPEST BUSMS BUSSS RECCS RPEST NMIST OSTST
T
T
T
0
0
0
0
0
0
0
b5
b4
—
—
0
0
b3
b2
b1
b0
LVD2S LVD1S WDTST IWDTS
T
T
T
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IWDTST
IWDT Underflow/Refresh Error Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b1
WDTST
WDT Underflow/Refresh Error Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b2
LVD1ST
Voltage Monitor 1 Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b3
LVD2ST
Voltage Monitor 2 Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b5, b4
—
Reserved
These bits are read as 0.
R
b6
OSTST
Main Oscillation Stop Detection Interrupt
Status Flag
0: Interrupt not requested for main oscillation stop
1: Interrupt requested for main oscillation stop.
R
b7
NMIST
NMI Status Flag
0: NMI pin interrupt not requested
1: NMI pin interrupt requested.
R
b8
RPEST
SRAM Parity Error Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b9
RECCST
SRAM ECC Error Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b10
BUSSST
MPU Bus Slave Error Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b11
BUSMST
MPU Bus Master Error Interrupt Status Flag 0: Interrupt not requested
1: Interrupt requested.
R
b12
SPEST
CPU Stack Pointer Monitor Interrupt Status
Flag
0: Interrupt not requested
1: Interrupt requested.
R
Reserved
These bits are read as 0.
R
b15 to b13 —
The NMISR register monitors the status of non-maskable interrupt sources. Writes to the NMISR register are ignored.
The setting in the Non-Maskable Interrupt Enable Register (NMIER) does not affect the status flags in this register.
Before the end of the non-maskable interrupt handler, check that all of the bits in this register are set to 0 to confirm that
no other NMI requests have occurred during handler processing.
IWDTST flag (IWDT Underflow/Refresh Error Status Flag)
The IWDTST flag indicates an IWDT underflow/refresh error interrupt request. It is read-only and cleared by the
NMICLR.IWDTCLR bit.
[Setting condition]
When an IWDT underflow/refresh error interrupt occurs and this interrupt source is enabled.
[Clearing condition]
When 1 is written to the NMICLR.IWDTCLR bit.
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WDTST flag (WDT Underflow/Refresh Error Status Flag)
The WDTST flag indicates a WDT underflow/refresh error interrupt request. It is read-only and cleared by the
NMICLR.WDTCLR bit.
[Setting condition]
When a WDT underflow/refresh error interrupt occurs.
[Clearing condition]
When 1 is written to the NMICLR.WDTCLR bit.
LVD1ST flag (Voltage Monitor 1 Interrupt Status Flag)
The LVD1ST flag indicates a request for voltage monitor 1 interrupt. It is read-only and cleared by the
NMICLR.LVD1CLR bit.
[Setting condition]
When a voltage monitor 1 interrupt occurs and this interrupt source is enabled.
[Clearing condition]
When 1 is written to the NMICLR.LVD1CLR bit.
LVD2ST flag (Voltage Monitor 2 Interrupt Status Flag)
The LVD2ST flag indicates a request for voltage monitor 2 interrupt. It is read-only and cleared by the
NMICLR.LVD2CLR bit.
[Setting condition]
When a voltage monitor 2 interrupt occurs and this interrupt source is enabled.
[Clearing condition]
When 1 is written to the NMICLR.LVD2CLR bit.
OSTST flag (Main Oscillation Stop Detection Interrupt Status Flag)
The OSTST flag indicates a main oscillation stop detection interrupt request. It is read-only and cleared by the
NMICLR.OSTCLR bit.
[Setting condition]
When an oscillation stop detection interrupt occurs.
[Clearing condition]
When 1 is written to the NMICLR.OSTCLR bit.
NMIST flag (NMI Status Flag)
The NMIST flag indicates an NMI pin interrupt request. It is read-only and cleared by the NMICLR.NMICLR bit.
[Setting condition]
When an edge specified in the NMICR.NMIMD bit is input to the NMI pin.
[Clearing condition]
When 1 is written to the NMICLR.NMICLR bit.
RPEST flag (SRAM Parity Error Interrupt Status Flag)
The RPEST flag indicates an SRAM parity error interrupt request.
[Setting condition]
When an interrupt occurs in response to an SRAM parity error.
[Clearing condition]
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When 1 is written to the NMICLR.RPECLR bit.
RECCST flag (SRAM ECC Error Interrupt Status Flag)
The RECCST flag indicates an SRAM ECC error interrupt request.
[Setting condition]
When an interrupt occurs in response to an SRAM ECC error.
[Clearing condition]
When 1 is written to the NMICLR.RECCCLR bit.
BUSSST flag (MPU Bus Slave Error Interrupt Status Flag)
The BUSSST flag indicates a bus slave error interrupt request.
[Setting condition]
When an interrupt occurs in response to a bus slave error.
[Clearing condition]
When 1 is written to the NMICLR.BUSSCLR bit.
BUSMST flag (MPU Bus Master Error Interrupt Status Flag)
The BUSMST flag indicates a bus master error interrupt request.
[Setting condition]
When an interrupt occurs in response to a bus master error.
[Clearing condition]
When 1 is written to the NMICLR.BUSMCLR bit.
SPEST flag (CPU Stack Pointer Monitor Interrupt Status Flag)
The SPEST flag indicates a CPU stack pointer monitor interrupt request.
[Setting condition]
When an interrupt occurs in response to a CPU stack pointer monitor error.
[Clearing condition]
When 1 is written to the NMICLR.SPECLR bit.
14.2.3
Non-Maskable Interrupt Enable Register (NMIER)
Address(es): ICU.NMIER 4000 6120h
Value after reset:
b15
b14
b13
—
—
—
0
0
0
b12
b11
b10
b9
b8
b7
b6
SPEEN BUSME BUSSE RECCE RPEEN NMIEN OSTEN
N
N
N
0
0
0
0
0
0
0
b5
b4
—
—
0
0
b3
b2
b1
b0
LVD2E LVD1E WDTE IWDTE
N
N
N
N
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IWDTEN
IWDT Underflow/Refresh Error Interrupt
Enable
0: Disable
1: Enable.
*1, *2
WDT Underflow/Refresh Error Interrupt
Enable
0: Disable
1: Enable.
*1, *2
Voltage Monitor 1 Interrupt Enable
0: Disable
1: Enable.
*1, *2
b1
b2
WDTEN
LVD1EN
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14. Interrupt Controller Unit (ICU)
Bit
Symbol
Bit name
Description
R/W
b3
LVD2EN
Voltage Monitor 2 Interrupt Enable
0: Disable
1: Enable.
*1, *2
R/(W)
b5 to b4
―
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
OSTEN
Oscillation Stop Detection Interrupt
Enable
0: Disable
1: Enable.
*1, *2
NMI Pin Interrupt Enable
0: Disable
1: Enable.
*1
0: Disable
1: Enable.
*1, *2
0: Disable
1: Enable.
*1, *2
0: Disable
1: Enable.
*1, *2
0: Disable
1: Enable.
*1, *2
CPU Stack Pointer Monitor Interrupt
Enable
0: Disable
1: Enable.
*1, *2
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
b8
b9
b10
b11
b12
NMIEN
RPEEN
RECCEN
BUSSEN
BUSMEN
SPEEN
b15 to b13 ―
Note 1.
Note 2.
SRAM Parity Error Interrupt Enable
SRAM ECC Error Interrupt Enable
MPU Bus Slave Error Interrupt Enable
MPU Bus Master Error Interrupt Enable
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
You can write 1 to this bit only once after reset. Subsequent write accesses are invalid. Writing 0 to this bit is invalid.
Do not write 1 to this bit when the source is used as an event signal.
IWDTEN bit (IWDT Underflow/Refresh Error Interrupt Enable)
The IWDTEN bit enables IWDT underflow/refresh error interrupts as an NMI trigger.
WDTEN bit (WDT Underflow/Refresh Error Interrupt Enable)
The WDTEN bit enables WDT underflow/refresh error interrupts as an NMI trigger.
LVD1EN bit (Voltage Monitor 1 Interrupt Enable)
The LVD1EN bit enables voltage monitor 1 interrupts as an NMI trigger.
LVD2EN bit (Voltage Monitor 2 Interrupt Enable)
The LVD2EN bit enables voltage monitor 2 interrupts as an NMI trigger.
OSTEN bit (Oscillation Stop Detection Interrupt Enable)
The OSTEN bit enables main oscillation stop detection interrupts as an NMI trigger.
NMIEN bit (NMI Pin Interrupt Enable)
The NMIEN bit enables NMI pin interrupts as an NMI trigger.
RPEEN bit (SRAM Parity Error Interrupt Enable)
The RPEEN bit enables SRAM parity error interrupts as an NMI trigger.
RECCEN bit (SRAM ECC Error Interrupt Enable)
The RECCEN bit enables SRAM ECC error interrupts as an NMI trigger.
BUSSEN bit (MPU Bus Slave Error Interrupt Enable)
The BUSSEN bit enables bus slave error interrupts as an NMI trigger.
BUSMEN bit (MPU Bus Master Error Interrupt Enable)
The BUSMEN bit enables bus master error interrupts as an NMI trigger.
SPEEN bit (CPU Stack Pointer Monitor Interrupt Enable)
The SPEEN bit enables CPU stack pointer monitor interrupts as an NMI trigger.
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14.2.4
14. Interrupt Controller Unit (ICU)
Non-Maskable Interrupt Status Clear Register (NMICLR)
Address(es): ICU.NMICLR 4000 6130h
b15
b14
b13
—
—
—
0
0
0
Value after reset:
b12
b11
b10
b9
b8
b7
b6
SPECL BUSM BUSSC RECCC RPECL NMICL OSTCL
R
CLR
LR
LR
R
R
R
0
0
0
0
0
0
0
b5
b4
—
—
0
0
b3
b2
b1
b0
LVD2C LVD1C WDTCL IWDTC
LR
LR
R
LR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IWDTCLR
IWDT Clear
0: No effect
1: Clear the NMISR.IWDTST flag.
R/(W)*1
b1
WDTCLR
WDT Clear
0: No effect
1: Clear the NMISR.WDTST flag.
R/(W)*1
b2
LVD1CLR
LVD1 Clear
0: No effect
1: Clear the NMISR.LVD1ST flag.
R/(W)*1
b3
LVD2CLR
LVD2 Clear
0: No effect
1: Clear the NMISR.LVD2ST flag.
R/(W)*1
b5 to b4
—
Reserved
The write value should be 0.
R/(W)*1
b6
OSTCLR
OST Clear
0: No effect
1: Clear the NMISR.OSTST flag.
R/(W)*1
b7
NMICLR
NMI Clear
0: No effect
1: Clear the NMISR.NMIST flag.
R/(W)*1
b8
RPECLR
SRAM Parity Error Clear
0: No effect
1: Clear the NMISR.RPEST flag.
R/(W)*1
b9
RECCCLR
SRAM ECC Error Clear
0: No effect
1: Clear the NMISR.RECCST flag.
R/(W)*1
b10
BUSSCLR
Bus Slave Error Clear
0: No effect
1: Clear the NMISR.BUSSST flag.
R/(W)*1
b11
BUSMCLR
Bus Master Error Clear
0: No effect
1: Clear the NMISR.BUSMST flag.
R/(W)*1
b12
SPECLR
SPEST Clear
0: No effect
1: Clear the NMISR.SPEST flag.
R/(W)*1
b15 to b13
—
Reserved
These bits are read as 0. The write value should be 0.
R/(W)*1
Note 1.
Only write 1 to this bit.
IWDTCLR bit (IWDT Clear)
Writing 1 to the IWDTCLR bit clears the NMISR.IWDTST flag. This bit is read as 0.
WDTCLR bit (WDT Clear)
Writing 1 to the WDTCLR bit clears the NMISR.WDTST flag. This bit is read as 0.
LVD1CLR bit (LVD1 Clear)
Writing 1 to the LVD1CLR bit clears the NMISR.LVD1ST flag. This bit is read as 0.
LVD2CLR bit (LVD2 Clear)
Writing 1 to the LVD2CLR bit clears the NMISR.LVD2ST flag. This bit is read as 0.
OSTCLR bit (OST Clear)
Writing 1 to the OSTCLR bit clears the NMISR.OSTST flag. This bit is read as 0.
NMICLR bit (NMI Clear)
Writing 1 to the NMICLR bit clears the NMISR.NMIST flag. This bit is read as 0.
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14. Interrupt Controller Unit (ICU)
RPECLR bit (SRAM Parity Error Clear)
Writing 1 to the RPECLR bit clears the NMISR.RPEST flag. This bit is read as 0.
RECCCLR bit (SRAM ECC Error Clear)
Writing 1 to the RECCCLR bit clears the NMISR.RECCST flag. This bit is read as 0.
BUSSCLR bit (Bus Slave Error Clear)
Writing 1 to the BUSSCLR bit clears the NMISR.BUSSST flag. This bit is read as 0.
BUSMCLR bit (Bus Master Error Clear)
Writing 1 to the BUSMCLR bit clears the NMISR.BUSMSST flag. This bit is read as 0.
SPECLR bit (SPEST Clear)
Writing 1 to the SPECLR bit clears the NMISR.SPEST flag. This bit is read as 0.
14.2.5
NMI Pin Interrupt Control Register (NMICR)
Address(es): ICU.NMICR 4000 6100h
b7
b6
NFLTE
N
—
0
0
Value after reset:
b5
b4
NFCLKSEL[1:0]
0
0
b3
b2
b1
b0
—
—
—
NMIMD
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
NMIMD
NMI Detection Set
0: Falling edge
1: Rising edge.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b5, b4
NFCLKSEL[1:0]
NMI Digital Filter Sampling Clock
Select
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
NFLTEN
NMI Digital Filter Enable
0: Disable
1: Enable.
R/W
b5 b4
0
0
1
1
0:
1:
0:
1:
R/W
PCLKB
PCLKB/8
PCLKB/32
PCLKB/64.
Change the NMICR register settings before enabling NMI pin interrupts (before setting NMIER.NMIEN to 1).
NMIMD bit (NMI Detection Set)
The NMIMD bit selects the detection sensing method for the NMI pin interrupts.
NFCLKSEL[1:0] bits (NMI Digital Filter Sampling Clock Select)
The NFCLKSEL[1:0] bits select the digital filter sampling clock for the NMI pin interrupts, selectable to:
PCLKB (every cycle)
PCLKB/8 (once every 8 cycles)
PCLKB/32 (once every 32 cycles)
PCLKB/64 (once every 64 cycles).
For details of the digital filter, see section 14.4.3, Digital Filter.
NFLTEN bit (NMI Digital Filter Enable)
The NFLTEN bit enables the digital filter used for NMI pin interrupts. The filter is enabled when NFLTEN is 1 and
disabled when NFLTEN is 0. The NMI pin level is sampled at the cycle specified in NMIFLTC.NFCLKSEL[1:0]. When
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14. Interrupt Controller Unit (ICU)
the sampled level matches three times, the output level from the digital filter changes. For details of the digital filter, see
section 14.4.3, Digital Filter.
14.2.6
ICU Event Link Setting Register n (IELSRn) (n = 0 to 95)
Address(es): ICU.IELSR0 4000 6300h, ICU.IELSR1 4000 6304h, ICU.IELSR2 4000 6308h, ICU.IELSR3 4000 630Ch……
……ICU.IELSR92 4000 6470h, ICU.IELSR93 4000 6474h, ICU.IELSR94 4000 6478h, ICU.IELSR95 4000 647Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
DTCE
—
—
—
—
—
—
—
IR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
IELS[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
IELS[8:0]
ICU Event Link Select
b8
R/W*1
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
IR
Interrupt Status Flag
0: No interrupt request occurred
1: Interrupt request occurred.
R/(W)*2
b23 to b17 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b24
DTC Activation Enable
0: Disable
1: Enable.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
DTCE
b31 to b25 —
Note 1.
Note 2.
b0
000000000: Disable interrupts to the associated NVIC or DTC module
000000001 to 111111111: Event signal number to be linked.
For details, see Table 14.4.
This register requires halfword or word access.
Writing 1 to the IR flag is prohibited.
The IELSRn register selects the IRQ source used by the NVIC. For details, see Table 14.4. IELSRn, where n = 0 to 95,
corresponds to the NVIC IRQ input source numbers 0 to 95.
IELS[8:0] bits (ICU Event Link Select)
The IELS[8:0] bits link an event signal to the associated NVIC or DTC module. All IELS[8:0] bits must be written to
simultaneously.
IR flag (Interrupt Status Flag)
The IR flag indicates an individual interrupt request from the event specified in IELS[8:0].
[Setting condition]
When an interrupt request is received from the associated peripheral module or IRQi pin.
[Clearing conditions]
When 0 is written to the bit. DTCE must be set to 0 before writing 0 to the IR flag.
To clear the IR flag:
1. Negate the input interrupt signal.
2. Read access the peripheral once and wait for 2 clock cycles of the target module clock.
3. Clear the IR flag by writing 0.
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14. Interrupt Controller Unit (ICU)
DTCE bit (DTC Activation Enable)
When the DTCE bit is set to 1, the associated event is selected as the source for DTC activation.
[Setting condition]
When 1 is written to the DTCE bit.
[Clearing conditions]
When the specified number of transfers is complete. For chain transfers, when the specified number of transfers for
the last chain transfer is complete.
When 0 is written to the bit.
14.2.7
DMAC Event Link Setting Register n (DELSRn) (n = 0 to 7)
Address(es): ICU.DELSR0 4000 6280h, ICU.DELSR1 4000 6284h, ICU.DELSR2 4000 6288h, ICU.DELSR3 4000 628Ch,
ICU.DELSR4 4000 6290h, ICU.DELSR5 4000 6294h, ICU.DELSR6 4000 6298h, ICU.DELSR7 4000 629Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
DELS[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
DELS[8:0]
DMAC Event Link Select
b8
R/W*1
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
IR
Interrupt Status Flag for DMAC
0: No interrupt request is generated
1: An interrupt request is generated.
R/(W)*2
b31 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
b0
000000000: Disable DMA start requests to the associated
DMAC module
000000001 to 111111111: Event signal number to be linked.
For details, see Table 14.4.
This register requires halfword or word access.
Writing 1 to the IR flag is prohibited.
DELS[8:0] bits (DMAC Event Link Select)
The DELS[8:0] bits link an event signal to the DMAC module. All DELS[8:0] bits must be written to simultaneously.
IR flag (Interrupt Status Flag for DMAC)
The IR flag is the status flag of an individual DMA transfer request. This flag corresponds to DELS[8:0] bits of the same
register.
[Setting condition]
The flag is set to 1 when a DMA transfer request is generated from the corresponding peripheral module or IRQi pin.
[Clearing conditions]
When 0 is written to the flag.
At the start of the DMA transfer after the DMA transfer request is issued.
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14.2.8
14. Interrupt Controller Unit (ICU)
SYS Event Link Setting Register (SELSR0)
Address(es): ICU.SELSR0 4000 6200h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
SELS[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
SELS[8:0]
SYS Event Link Select
b8
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
Note:
b0
000000000: Disable event output to the associated low-power
mode module
000000001 to 111111111: Event signal number to be linked.
For details, see Table 14.4.
R/W
This register requires halfword access.
The SELSR0 register selects the events that wake the CPU from Snooze mode. You can only use the events listed in
Table 14.4 checked under “Canceling Snooze using SELSR0”. Events specified in this register are defined as
ICU_SNZCANCEL (02Dh) in Table 14.4. When 02Dh is set in IELSRn.IELS, the SELSR0 event interrupt occurs.
SELS[8:0] bits (SYS Event Link Select)
All SELS[8:0] bits must be written to simultaneously.
14.2.9
Wake Up Interrupt Enable Register (WUPEN)
Address(es): ICU.WUPEN 4000 61A0h
b31
b30
b29
b28
b27
IIC0WU AGT1C AGT1C AGT1U USBFS
PEN BWUP AWUP DWUP WUPE
EN
EN
EN
N
Value after reset:
b26
—
b25
b24
RTCPR RTCAL
DWUP MWUP
EN
EN
b23
b22
b21
b20
—
ACMP
HS0W
UPEN
—
—
b19
b18
b17
b16
LVD2W LVD1W KEYW IWDTW
UPEN UPEN UPEN UPEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
IRQWUPEN[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
IRQWUPEN[15:0]
IRQ Interrupt Software
Standby Returns Enable
0: Disable Software Standby returns by IRQ interrupts
1: Enable Software Standby returns by IRQ interrupts.
R/W
b16
IWDTWUPEN
IWDT Interrupt Software
Standby Returns Enable
0: Disable Software Standby returns by IWDT interrupts
1: Enable Software Standby returns by IWDT interrupts.
R/W
b17
KEYWUPEN
Key Interrupt Software
Standby Returns Enable
0: Disable Software Standby returns by KEY interrupts
1: Enable Software Standby returns by KEY interrupts.
R/W
b18
LVD1WUPEN
LVD1 Interrupt Software
Standby Returns Enable
0: Disable Software Standby returns by LVD1 interrupts
1: Enable Software Standby returns by LVD1 interrupts.
R/W
b19
LVD2WUPEN
LVD2 Interrupt Software
Standby Returns Enable
0: Disable Software Standby returns by LVD2 interrupts
1: Enable Software Standby returns by LVD2 interrupts.
R/W
b21 to b20
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b22
ACMPHS0WUPEN
ACMPHS0 Interrupt
Software Standby Returns
Enable
0: Disable Software Standby returns by ACMPHS0
interrupts
1: Enable Software Standby returns by ACMPHS0
interrupts.
R/W
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14. Interrupt Controller Unit (ICU)
Bit
Symbol
Bit name
Description
R/W
b23
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b24
RTCALMWUPEN
RTC Alarm Interrupt
Software Standby Returns
Enable
0: Disable Software Standby returns by RTC alarm
interrupts
1: Enable Software Standby returns by RTC alarm
interrupts.
R/W
b25
RTCPRDWUPEN
RTC Period Interrupt
Software Standby Returns
Enable
0: Disable Software Standby returns by RTC period
interrupts
1: Enable Software Standby returns by RTC period
interrupts.
R/W
b26
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b27
USBFSWUPEN
USBFS Interrupt Software
Standby Returns Enable
0: Disable Software Standby returns by USBFS
interrupts
1: Enable Software Standby returns by USBFS
interrupts.
R/W
b28
AGT1UDWUPEN
AGT1 Underflow Interrupt
Software Standby Returns
Enable
0: Disable Software Standby returns by AGT1 underflow
interrupts
1: Enable Software Standby returns by AGT1 underflow
interrupts.
R/W
b29
AGT1CAWUPEN
AGT1 Compare Match A
Interrupt Software Standby
Returns Enable
0: Disable Software Standby returns by AGT1 compare
match A interrupts
1: Enable Software Standby returns by AGT1 compare
match A interrupts.
R/W
b30
AGT1CBWUPEN
AGT1 Compare Match B
Interrupt Software Standby
Returns Enable
0: Disable Software Standby returns by AGT1 compare
match B interrupts
1: Enable Software Standby returns by AGT1 compare
match B interrupts.
R/W
b31
IIC0WUPEN
IIC0 Address Match
Interrupt Software Standby
Returns Enable
0: Disable Software Standby returns by IIC0 address
match interrupts
1: Enable Software Standby returns by IIC0 address
match interrupts.
R/W
The bits in this register control whether the associated interrupt can wake up the CPU from Software Standby mode.
IRQWUPEN[15:0] bits (IRQ Interrupt Software Standby Returns Enable)
The IRQWUPEN[15:0] bits enable the use of IRQn interrupts to cancel Software Standby mode.
IWDTWUPEN bit (IWDT Interrupt Software Standby Returns Enable)
The IWDTWUPEN bit enables the use of IWDT interrupts to cancel Software Standby mode.
KEYWUPEN bit (Key Interrupt Software Standby Returns Enable)
The KEYWUPEN bit enables the use of key interrupts to cancel Software Standby mode.
LVD1WUPEN bit (LVD1 Interrupt Software Standby Returns Enable)
The LVD1WUPEN bit enables the use of LVD1 interrupts to cancel Software Standby mode.
LVD2WUPEN bit (LVD2 Interrupt Software Standby Returns Enable)
The LVD2WUPEN bit enables the use of LVD2 interrupts to cancel Software Standby mode.
ACMPHS0WUPEN bit (ACMPHS0 Interrupt Software Standby Returns Enable)
The ACMPHS0WUPEN bit enables the use of ACMPHS0 interrupts to cancel Software Standby mode.
RTCALMWUPEN bit (RTC Alarm Interrupt Software Standby Returns Enable)
The RTCALMWUPEN bit enables the use of RTC alarm interrupts to cancel Software Standby mode.
RTCPRDWUPEN bit (RTC Period Interrupt Software Standby Returns Enable)
The RTCPRDWUPEN bit enables the use of RTC period interrupts to cancel Software Standby mode.
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14. Interrupt Controller Unit (ICU)
USBFSWUPEN bit (USBFS Interrupt Software Standby Returns Enable)
The USBFSWUPEN bit enables the use of USBFS interrupts to cancel Software Standby mode.
AGT1UDWUPEN bit (AGT1 Underflow Interrupt Software Standby Returns Enable)
The AGT1UDWUPEN bit enables the use of AGT1 underflow interrupts to cancel Software Standby mode.
AGT1CAWUPEN bit (AGT1 Compare Match A Interrupt Software Standby Returns Enable)
The AGT1CAWUPEN bit enables the use of AGT1 compare match A interrupts to cancel Software Standby mode.
AGT1CBWUPEN bit (AGT1 Compare Match B Interrupt Software Standby Returns Enable)
The AGT1CBWUPEN bit enables the use of AGT1 compare match B interrupts to cancel Software Standby mode.
IIC0WUPEN bit (IIC0 Address Match Interrupt Software Standby Returns Enable)
The IIC0WUPEN bit enables the use of IIC0 interrupts to cancel Software Standby mode.
14.3
Vector Table
The ICU detects two types of interrupts, maskable and non-maskable. Interrupt priorities are set up in the Arm NVIC.
See the NVIC chapter of the ARM® Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D).
14.3.1
Interrupt Vector Table
Table 14.3 describes the interrupt vectors. The addresses conform to the NVIC specifications.
Table 14.3
Interrupt vector table (1 of 3)
Exception
number
IRQ number
Vector offset Source
Description
0
-
000h
Arm
Initial stack pointer
1
-
004h
Arm
Initial program counter (reset vector)
2
-
008h
Arm
Non-maskable interrupt (NMI)
3
-
00Ch
Arm
Hard fault
4
-
010h
Arm
MemManage fault
5
-
014h
Arm
Bus fault
6
-
018h
Arm
Usage fault
7
-
01Ch
Arm
Reserved
8
-
020h
Arm
Reserved
9
-
024h
Arm
Reserved
10
-
028h
Arm
Reserved
11
-
02Ch
Arm
Supervisor call (SVCall)
12
-
030h
Arm
Debug Monitor
13
-
034h
Arm
Reserved
14
-
038h
Arm
Pendable request for system service (PendableSrvReq)
15
-
03Ch
Arm
System tick timer (SysTick)
16
0
040h
ICU.IELSR0
Event selected in the ICU.IELSR0 register
17
1
044h
ICU.IELSR1
Event selected in the ICU.IELSR1 register
18
2
048h
ICU.IELSR2
Event selected in the ICU.IELSR2 register
19
3
04Ch
ICU.IELSR3
Event selected in the ICU.IELSR3 register
20
4
050h
ICU.IELSR4
Event selected in the ICU.IELSR4 register
21
5
054h
ICU.IELSR5
Event selected in the ICU.IELSR5 register
22
6
058h
ICU.IELSR6
Event selected in the ICU.IELSR6 register
23
7
05Ch
ICU.IELSR7
Event selected in the ICU.IELSR7 register
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Table 14.3
14. Interrupt Controller Unit (ICU)
Interrupt vector table (2 of 3)
Exception
number
IRQ number
Vector offset Source
Description
24
8
060h
ICU.IELSR8
Event selected in the ICU.IELSR8 register
25
9
064h
ICU.IELSR9
Event selected in the ICU.IELSR9 register
26
10
068h
ICU.IELSR10
Event selected in the ICU.IELSR10 register
27
11
06Ch
ICU.IELSR11
Event selected in the ICU.IELSR11 register
28
12
070h
ICU.IELSR12
Event selected in the ICU.IELSR12 register
29
13
074h
ICU.IELSR13
Event selected in the ICU.IELSR13 register
30
14
078h
ICU.IELSR14
Event selected in the ICU.IELSR14 register
31
15
07Ch
ICU.IELSR15
Event selected in the ICU.IELSR15 register
32
16
080h
ICU.IELSR16
Event selected in the ICU.IELSR16 register
33
17
084h
ICU.IELSR17
Event selected in the ICU.IELSR17 register
34
18
088h
ICU.IELSR18
Event selected in the ICU.IELSR18 register
35
19
08Ch
ICU.IELSR19
Event selected in the ICU.IELSR19 register
36
20
090h
ICU.IELSR20
Event selected in the ICU.IELSR20 register
37
21
094h
ICU.IELSR21
Event selected in the ICU.IELSR21 register
38
22
098h
ICU.IELSR22
Event selected in the ICU.IELSR22 register
39
23
09Ch
ICU.IELSR23
Event selected in the ICU.IELSR23 register
40
24
0A0h
ICU.IELSR24
Event selected in the ICU.IELSR24 register
41
25
0A4h
ICU.IELSR25
Event selected in the ICU.IELSR25 register
42
26
0A8h
ICU.IELSR26
Event selected in the ICU.IELSR26 register
43
27
0ACh
ICU.IELSR27
Event selected in the ICU.IELSR27 register
44
28
0B0h
ICU.IELSR28
Event selected in the ICU.IELSR28 register
45
29
0B4h
ICU.IELSR29
Event selected in the ICU.IELSR29 register
46
30
0B8h
ICU.IELSR30
Event selected in the ICU.IELSR30 register
47
31
0BCh
ICU.IELSR31
Event selected in the ICU.IELSR31 register
48
32
0C0h
ICU.IELSR32
Event selected in the ICU.IELSR32 register
49
33
0C4h
ICU.IELSR33
Event selected in the ICU.IELSR33 register
50
34
0C8h
ICU.IELSR34
Event selected in the ICU.IELSR34 register
51
35
0CCh
ICU.IELSR35
Event selected in the ICU.IELSR35 register
52
36
0D0h
ICU.IELSR36
Event selected in the ICU.IELSR36 register
53
37
0D4h
ICU.IELSR37
Event selected in the ICU.IELSR37 register
54
38
0D8h
ICU.IELSR38
Event selected in the ICU.IELSR38 register
55
39
0DCh
ICU.IELSR39
Event selected in the ICU.IELSR39 register
56
40
0E0h
ICU.IELSR40
Event selected in the ICU.IELSR40 register
57
41
0E4h
ICU.IELSR41
Event selected in the ICU.IELSR41 register
58
42
0E8h
ICU.IELSR42
Event selected in the ICU.IELSR42 register
59
43
0ECh
ICU.IELSR43
Event selected in the ICU.IELSR43 register
60
44
0F0h
ICU.IELSR44
Event selected in the ICU.IELSR44 register
61
45
0F4h
ICU.IELSR45
Event selected in the ICU.IELSR45 register
62
46
0F8h
ICU.IELSR46
Event selected in the ICU.IELSR46 register
63
47
0FCh
ICU.IELSR47
Event selected in the ICU.IELSR47 register
64
48
100h
ICU.IELSR48
Event selected in the ICU.IELSR48 register
65
49
104h
ICU.IELSR49
Event selected in the ICU.IELSR49 register
66
50
108h
ICU.IELSR50
Event selected in the ICU.IELSR50 register
67
51
10Ch
ICU.IELSR51
Event selected in the ICU.IELSR51 register
68
52
110h
ICU.IELSR52
Event selected in the ICU.IELSR52 register
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Table 14.3
14. Interrupt Controller Unit (ICU)
Interrupt vector table (3 of 3)
Exception
number
IRQ number
Vector offset Source
Description
69
53
114h
ICU.IELSR53
Event selected in the ICU.IELSR53 register
70
54
118h
ICU.IELSR54
Event selected in the ICU.IELSR54 register
71
55
11Ch
ICU.IELSR55
Event selected in the ICU.IELSR55 register
72
56
120h
ICU.IELSR56
Event selected in the ICU.IELSR56 register
73
57
124h
ICU.IELSR57
Event selected in the ICU.IELSR57 register
74
58
128h
ICU.IELSR58
Event selected in the ICU.IELSR58 register
75
59
12Ch
ICU.IELSR59
Event selected in the ICU.IELSR59 register
76
60
130h
ICU.IELSR60
Event selected in the ICU.IELSR60 register
77
61
134h
ICU.IELSR61
Event selected in the ICU.IELSR61 register
78
62
138h
ICU.IELSR62
Event selected in the ICU.IELSR62 register
79
63
13Ch
ICU.IELSR63
Event selected in the ICU.IELSR63 register
80
64
140h
ICU.IELSR64
Event selected in the ICU.IELSR64 register
81
65
144h
ICU.IELSR65
Event selected in the ICU.IELSR65 register
82
66
148h
ICU.IELSR66
Event selected in the ICU.IELSR66 register
83
67
14Ch
ICU.IELSR67
Event selected in the ICU.IELSR67 register
84
68
150h
ICU.IELSR68
Event selected in the ICU.IELSR68 register
85
69
154h
ICU.IELSR69
Event selected in the ICU.IELSR69 register
86
70
158h
ICU.IELSR70
Event selected in the ICU.IELSR70 register
87
71
15Ch
ICU.IELSR71
Event selected in the ICU.IELSR71 register
88
72
160h
ICU.IELSR72
Event selected in the ICU.IELSR72 register
89
73
164h
ICU.IELSR73
Event selected in the ICU.IELSR73 register
90
74
168h
ICU.IELSR74
Event selected in the ICU.IELSR74 register
91
75
16Ch
ICU.IELSR75
Event selected in the ICU.IELSR75 register
92
76
170h
ICU.IELSR76
Event selected in the ICU.IELSR76 register
93
77
174h
ICU.IELSR77
Event selected in the ICU.IELSR77 register
94
78
178h
ICU.IELSR78
Event selected in the ICU.IELSR78 register
95
79
17Ch
ICU.IELSR79
Event selected in the ICU.IELSR79 register
96
80
180h
ICU.IELSR80
Event selected in the ICU.IELSR80 register
97
81
184h
ICU.IELSR81
Event selected in the ICU.IELSR81 register
98
82
188h
ICU.IELSR82
Event selected in the ICU.IELSR82 register
99
83
18Ch
ICU.IELSR83
Event selected in the ICU.IELSR83 register
100
84
190h
ICU.IELSR84
Event selected in the ICU.IELSR84 register
101
85
194h
ICU.IELSR85
Event selected in the ICU.IELSR85 register
102
86
198h
ICU.IELSR86
Event selected in the ICU.IELSR86 register
103
87
19Ch
ICU.IELSR87
Event selected in the ICU.IELSR87 register
104
88
1A0h
ICU.IELSR88
Event selected in the ICU.IELSR88 register
105
89
1A4h
ICU.IELSR89
Event selected in the ICU.IELSR89 register
106
90
1A8h
ICU.IELSR90
Event selected in the ICU.IELSR90 register
107
91
1ACh
ICU.IELSR91
Event selected in the ICU.IELSR91 register
108
92
1B0h
ICU.IELSR92
Event selected in the ICU.IELSR92 register
109
93
1B4h
ICU.IELSR93
Event selected in the ICU.IELSR93 register
110
94
1B8h
ICU.IELSR94
Event selected in the ICU.IELSR94 register
111
95
1BCh
ICU.IELSR95
Event selected in the ICU.IELSR95 register
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Aug 30, 2019
Page 257 of 1734
S5D5 User’s Manual
14.3.2
14. Interrupt Controller Unit (ICU)
Event Numbers
The following table lists heading details for Table 14.4, which describes each event number.
Heading
Description
Interrupt request source
Name of the source generating the interrupt request
Name
Name of the interrupt
Connect to NVIC
“” indicates the interrupt can be used as a CPU interrupt (IELSRn setting)
Invoke DTC
“” indicates the interrupt can be used to request DTC activation (IELSRn setting)
Invoke DMAC
“” indicates the interrupt can be used to request DMAC activation (DELSRn setting)
Canceling Snooze mode
“” indicates the interrupt can be used to request a return from Snooze mode using
SELSR0. Otherwise, “” indicates it can be used directly
Canceling Software Standby mode
“” indicates the interrupt can be used to request a return from Software Standby mode
Canceling Deep Software Standby mode
“” indicates the interrupt can be used to request a return from Deep Software Standby
mode
Table 14.4
Event table (1 of 8)
IELSRn
DELSRn
Canceling
Deep
Software
Standby
mode
Name
Connect
to NVIC
Invoke
DTC
Invoke
DMAC
Canceling
Snooze
mode
Canceling
Software
Standby
mode
PORT_IRQ0
002h
PORT_IRQ1
003h
PORT_IRQ2
004h
PORT_IRQ3
005h
PORT_IRQ4
006h
PORT_IRQ5
007h
PORT_IRQ6
008h
PORT_IRQ7
009h
PORT_IRQ8
00Ah
PORT_IRQ9
00Bh
PORT_IRQ10
00Ch
PORT_IRQ11
00Dh
PORT_IRQ12
00Eh
PORT_IRQ13
00Fh
PORT_IRQ14
010h
PORT_IRQ15
-
Event
number
Interrupt request
source
001h
Port
020h
DMAC0
DMAC0_INT
-
-
-
-
021h
DMAC1
DMAC1_INT
-
-
-
-
022h
DMAC2
DMAC2_INT
-
-
-
-
023h
DMAC3
DMAC3_INT
-
-
-
-
024h
DMAC4
DMAC4_INT
-
-
-
-
025h
DMAC5
DMAC5_INT
-
-
-
-
026h
DMAC6
DMAC6_INT
-
-
-
-
027h
DMAC7
DMAC7_INT
-
-
-
-
029h
DTC
DTC_COMPLETE
-
-
*5
-
-
02Dh
ICU
ICU_SNZCANCEL
-
-
-
-
030h
FCU
FCU_FIFERR
-
-
-
-
-
FCU_FRDYI
-
-
-
-
-
031h
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Page 258 of 1734
S5D5 User’s Manual
Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (2 of 8)
IELSRn
Event
number
Interrupt request
source
038h
LVD
DELSRn
Name
Connect
to NVIC
Invoke
DTC
Invoke
DMAC
Canceling
Snooze
mode
Canceling
Software
Standby
mode
Canceling
Deep
Software
Standby
mode
LVD_LVD1
-
-
LVD_LVD2
-
-
MOSC
MOSC_STOP
-
-
-
-
-
03Ch
Low power mode
SYSTEM_SNZREQ
-
-
-
-
-
040h
AGT0
AGT0_AGTI
-
-
-
041h
AGT0_AGTCMAI
-
-
-
042h
AGT0_AGTCMBI
-
-
-
AGT1_AGTI
044h
AGT1_AGTCMAI
-
045h
AGT1_AGTCMBI
-
039h
03Bh
043h
AGT1
046h
IWDT
IWDT_NMIUNDF
-
-
-
047h
WDT
WDT_NMIUNDF
-
-
-
-
-
048h
RTC
RTC_ALM
-
-
049h
RTC_PRD
-
-
04Ah
RTC_CUP
-
-
-
-
-
ADC120_ADI
-
-
04Ch
04Bh
ADC120
ADC120_GBADI
-
-
-
04Dh
ADC120_CMPAI
-
-
-
-
-
04Eh
ADC120_CMPBI
-
-
-
-
-
04Fh
ADC120_WCMPM
-
*5
-
-
ADC120_WCMPUM
-
*5
-
-
ADC121_ADI
-
-
-
ADC121_GBADI
-
-
-
053h
ADC121_CMPAI
-
-
-
-
-
054h
ADC121_CMPBI
-
-
-
-
-
050h
051h
ADC121
052h
055h
ADC121_WCMPM
-
*5
-
-
056h
ADC121_WCMPUM
-
*5
-
-
ACMP_HS0
-
-
*1
*1
-
058h
ACMP_HS1
-
-
-
-
-
059h
ACMP_HS2
-
-
-
-
-
05Ah
ACMP_HS3
-
-
-
-
-
05Bh
ACMP_HS4
-
-
-
-
-
05Ch
ACMP_HS5
-
-
-
-
-
057h
05Fh
ACMPHS
USBFS_D0FIFO
-
-
-
060h
USBFS_D1FIFO
-
-
-
061h
USBFS_USBI
-
-
-
-
-
062h
USBFS_USBR
-
-
IIC0_RXI
-
-
-
064h
IIC0_TXI
-
-
-
065h
IIC0_TEI
-
-
-
-
-
066h
IIC0_EEI
-
-
-
-
-
067h
IIC0_WUI
-
-
-
IIC1_RXI
-
-
-
069h
IIC1_TXI
-
-
-
06Ah
IIC1_TEI
-
-
-
-
-
06Bh
IIC1_EEI
-
-
-
-
-
063h
068h
USBFS
IIC0
IIC1
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Aug 30, 2019
Page 259 of 1734
S5D5 User’s Manual
Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (3 of 8)
IELSRn
Event
number
Interrupt request
source
06Dh
IIC2
DELSRn
Name
Connect
to NVIC
Invoke
DTC
Invoke
DMAC
Canceling
Snooze
mode
Canceling
Software
Standby
mode
Canceling
Deep
Software
Standby
mode
-
IIC2_RXI
-
-
06Eh
IIC2_TXI
-
-
-
06Fh
IIC2_TEI
-
-
-
-
-
070h
IIC2_EEI
-
-
-
-
-
SSIE0_SSITXI
-
-
-
073h
SSIE0_SSIRXI
-
-
-
075h
SSIE0_SSIF
-
-
-
-
-
SRC_IDEI
-
-
-
07Bh
SRC_ODFI
-
-
-
07Ch
SRC_OVFI
-
-
-
-
-
07Dh
SRC_UDFI
-
-
-
-
-
07Eh
SRC_CEFI
-
-
-
-
-
PDC_PCDFI
-
-
-
080h
PDC_PCFEI
-
-
-
-
-
081h
PDC_PCERI
-
-
-
-
-
072h
07Ah
07Fh
082h
SSIE0
SRC
PDC
CTSU_CTSUWR
-
-
-
083h
CTSU
CTSU_CTSURD
-
-
-
084h
CTSU_CTSUFN
-
-
*5
-
-
*2
-
085h
KINT
KEY_INTKR
-
-
*2
086h
DOC
DOC_DOPCI
-
-
*5
-
-
087h
CAC
CAC_FERRI
-
-
-
-
-
088h
CAC_MENDI
-
-
-
-
-
089h
CAC_OVFI
-
-
-
-
-
08Ah
CAN0_ERS
-
-
-
-
-
08Bh
CAN0_RXF
-
-
-
-
-
08Ch
CAN0_TXF
-
-
-
-
-
08Dh
CAN0_RXM
-
-
-
-
-
08Eh
CAN0_TXM
-
-
-
-
-
08Fh
CAN0
CAN1_ERS
-
-
-
-
-
090h
CAN1_RXF
-
-
-
-
-
091h
CAN1_TXF
-
-
-
-
-
092h
CAN1_RXM
-
-
-
-
-
093h
CAN1_TXM
-
-
-
-
-
IOPORT_GROUP1
*3
*3
-
-
-
IOPORT_GROUP2
*3
*3
-
-
-
*3
-
094h
CAN1
I/O port
095h
096h
IOPORT_GROUP3
*3
-
-
097h
IOPORT_GROUP4
*3
*3
-
-
-
ELC_SWEVT0
*4
-
-
-
-
ELC_SWEVT1
*4
-
-
-
-
POEG_GROUP0
-
-
-
-
-
09Bh
POEG_GROUP1
-
-
-
-
-
09Ch
POEG_GROUP2
-
-
-
-
-
09Dh
POEG_GROUP3
-
-
-
-
-
098h
ELC
099h
09Ah
POEG
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Aug 30, 2019
Page 260 of 1734
S5D5 User’s Manual
Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (4 of 8)
IELSRn
Event
number
Interrupt request
source
0B0h
GPT32EH0
DELSRn
Name
Connect
to NVIC
Invoke
DTC
Invoke
DMAC
Canceling
Snooze
mode
Canceling
Software
Standby
mode
Canceling
Deep
Software
Standby
mode
GPT0_CCMPA
-
-
-
0B1h
GPT0_CCMPB
-
-
-
0B2h
GPT0_CMPC
-
-
-
0B3h
GPT0_CMPD
-
-
-
0B4h
GPT0_CMPE
-
-
-
0B5h
GPT0_CMPF
-
-
-
0B6h
GPT0_OVF
-
-
-
0B7h
GPT0_UDF
-
-
-
0B8h
GPT0_ADTRGA
-
-
-
0B9h
GPT0_ADTRGB
-
-
-
0BAh
GPT1_CCMPA
-
-
-
0BBh
GPT1_CCMPB
-
-
-
0BCh
GPT1_CMPC
-
-
-
0BDh
GPT1_CMPD
-
-
-
0BEh
GPT1_CMPE
-
-
-
0BFh
GPT1_CMPF
-
-
-
0C0h
GPT1_OVF
-
-
-
0C1h
GPT1_UDF
-
-
-
0C2h
GPT1_ADTRGA
-
-
-
0C3h
GPT1_ADTRGB
-
-
-
0C4h
GPT32EH1
GPT2_CCMPA
-
-
-
0C5h
GPT2_CCMPB
-
-
-
0C6h
GPT2_CMPC
-
-
-
0C7h
GPT2_CMPD
-
-
-
0C8h
GPT2_CMPE
-
-
-
0C9h
GPT2_CMPF
-
-
-
0CAh
GPT2_OVF
-
-
-
0CBh
GPT2_UDF
-
-
-
0CCh
GPT2_ADTRGA
-
-
-
0CDh
GPT2_ADTRGB
-
-
-
0CEh
GPT32EH2
GPT3_CCMPA
-
-
-
0CFh
GPT32EH3
GPT3_CCMPB
-
-
-
0D0h
GPT3_CMPC
-
-
-
0D1h
GPT3_CMPD
-
-
-
0D2h
GPT3_CMPE
-
-
-
0D3h
GPT3_CMPF
-
-
-
0D4h
GPT3_OVF
-
-
-
0D5h
GPT3_UDF
-
-
-
0D6h
GPT3_ADTRGA
-
-
-
0D7h
GPT3_ADTRGB
-
-
-
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 261 of 1734
S5D5 User’s Manual
Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (5 of 8)
IELSRn
Event
number
Interrupt request
source
0D8h
GPT32E4
DELSRn
Name
Connect
to NVIC
Invoke
DTC
Invoke
DMAC
Canceling
Snooze
mode
Canceling
Software
Standby
mode
Canceling
Deep
Software
Standby
mode
GPT4_CCMPA
-
-
-
0D9h
GPT4_CCMPB
-
-
-
0DAh
GPT4_CMPC
-
-
-
0DBh
GPT4_CMPD
-
-
-
0DCh
GPT4_CMPE
-
-
-
0DDh
GPT4_CMPF
-
-
-
0DEh
GPT4_OVF
-
-
-
0DFh
GPT4_UDF
-
-
-
0E0h
GPT4_ADTRGA
-
-
-
0E1h
GPT4_ADTRGB
-
-
-
0E2h
GPT5_CCMPA
-
-
-
0E3h
GPT5_CCMPB
-
-
-
0E4h
GPT5_CMPC
-
-
-
0E5h
GPT5_CMPD
-
-
-
0E6h
GPT5_CMPE
-
-
-
0E7h
GPT5_CMPF
-
-
-
0E8h
GPT5_OVF
-
-
-
0E9h
GPT5_UDF
-
-
-
0EAh
GPT5_ADTRGA
-
-
-
0EBh
GPT5_ADTRGB
-
-
-
0ECh
GPT32E5
GPT6_CCMPA
-
-
-
0EDh
GPT6_CCMPB
-
-
-
0EEh
GPT6_CMPC
-
-
-
0EFh
GPT6_CMPD
-
-
-
0F0h
GPT6_CMPE
-
-
-
0F1h
GPT6_CMPF
-
-
-
0F2h
GPT6_OVF
-
-
-
0F3h
GPT6_UDF
-
-
-
0F4h
GPT6_ADTRGA
-
-
-
0F5h
GPT6_ADTRGB
-
-
-
0F6h
GPT32E6
GPT7_CCMPA
-
-
-
0F7h
GPT32E7
GPT7_CCMPB
-
-
-
0F8h
GPT7_CMPC
-
-
-
0F9h
GPT7_CMPD
-
-
-
0FAh
GPT7_CMPE
-
-
-
0FBh
GPT7_CMPF
-
-
-
0FCh
GPT7_OVF
-
-
-
0FDh
GPT7_UDF
-
-
-
0FEh
GPT7_ADTRGA
-
-
-
0FFh
GPT7_ADTRGB
-
-
-
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 262 of 1734
S5D5 User’s Manual
Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (6 of 8)
IELSRn
Event
number
Interrupt request
source
100h
GPT328
DELSRn
Name
Connect
to NVIC
Invoke
DTC
Invoke
DMAC
Canceling
Snooze
mode
Canceling
Software
Standby
mode
Canceling
Deep
Software
Standby
mode
GPT8_CCMPA
-
-
-
101h
GPT8_CCMPB
-
-
-
102h
GPT8_CMPC
-
-
-
103h
GPT8_CMPD
-
-
-
104h
GPT8_CMPE
-
-
-
105h
GPT8_CMPF
-
-
-
106h
GPT8_OVF
-
-
-
107h
GPT8_UDF
-
-
-
GPT9_CCMPA
-
-
-
GPT9_CCMPB
-
-
-
10Ch
GPT9_CMPC
-
-
-
10Dh
GPT9_CMPD
-
-
-
10Eh
GPT9_CMPE
-
-
-
10Fh
GPT9_CMPF
-
-
-
110h
GPT9_OVF
-
-
-
10Ah
GPT329
10Bh
111h
GPT9_UDF
-
-
-
GPT10_CCMPA
-
-
-
GPT10_CCMPB
-
-
-
116h
GPT10_CMPC
-
-
-
117h
GPT10_CMPD
-
-
-
118h
GPT10_CMPE
-
-
-
119h
GPT10_CMPF
-
-
-
11Ah
GPT10_OVF
-
-
-
GPT10_UDF
-
-
-
GPT11_CCMPA
-
-
-
11Fh
GPT11_CCMPB
-
-
-
120h
GPT11_CMPC
-
-
-
121h
GPT11_CMPD
-
-
-
122h
GPT11_CMPE
-
-
-
123h
GPT11_CMPF
-
-
-
124h
GPT11_OVF
-
-
-
125h
GPT11_UDF
-
-
-
GPT12_CCMPA
-
-
-
129h
GPT12_CCMPB
-
-
-
12Ah
GPT12_CMPC
-
-
-
12Bh
GPT12_CMPD
-
-
-
12Ch
GPT12_CMPE
-
-
-
12Dh
GPT12_CMPF
-
-
-
12Eh
GPT12_OVF
-
-
-
12Fh
GPT12_UDF
-
-
-
114h
GPT3210
115h
11Bh
11Eh
128h
GPT3211
GPT3212
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Aug 30, 2019
Page 263 of 1734
S5D5 User’s Manual
Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (7 of 8)
IELSRn
Event
number
Interrupt request
source
132h
GPT3213
DELSRn
Name
Connect
to NVIC
Invoke
DTC
Invoke
DMAC
Canceling
Snooze
mode
Canceling
Software
Standby
mode
Canceling
Deep
Software
Standby
mode
GPT13_CCMPA
-
-
-
133h
GPT13_CCMPB
-
-
-
134h
GPT13_CMPC
-
-
-
135h
GPT13_CMPD
-
-
-
136h
GPT13_CMPE
-
-
-
137h
GPT13_CMPF
-
-
-
138h
GPT13_OVF
-
-
-
139h
GPT13_UDF
-
-
-
150h
GPT
GPT_UVWEDGE
-
-
-
163h
Ethernet Controller
ETHER_EINT0
-
-
-
-
-
174h
SCI0
-
SCI0_RXI
-
-
175h
SCI0_TXI
-
-
-
176h
SCI0_TEI
-
-
-
-
-
177h
SCI0_ERI
-
-
-
-
-
178h
SCI0_AM
-
-
*5
-
-
SCI0_RXI_OR_ERI
-
-
-
*5
-
-
SCI1_RXI
-
-
-
17Bh
SCI1_TXI
-
-
-
17Ch
SCI1_TEI
-
-
-
-
-
17Dh
SCI1_ERI
-
-
-
-
-
179h
17Ah
SCI1
17Eh
SCI1_AM
-
-
-
-
-
SCI2_RXI
-
-
-
SCI2_TXI
-
-
-
182h
SCI2_TEI
-
-
-
-
-
183h
SCI2_ERI
-
-
-
-
-
180h
SCI2
181h
184h
SCI2_AM
-
-
-
-
-
SCI3_RXI
-
-
-
SCI3_TXI
-
-
-
188h
SCI3_TEI
-
-
-
-
-
189h
SCI3_ERI
-
-
-
-
-
SCI3_AM
-
-
-
-
-
SCI4_RXI
-
-
-
18Dh
SCI4_TXI
-
-
-
18Eh
SCI4_TEI
-
-
-
-
-
18Fh
SCI4_ERI
-
-
-
-
-
186h
SCI3
187h
18Ah
18Ch
SCI4
190h
SCI4_AM
-
-
-
-
-
SCI5_RXI
-
-
-
SCI5_TXI
-
-
-
194h
SCI5_TEI
-
-
-
-
-
195h
SCI5_ERI
-
-
-
-
-
192h
SCI5
193h
196h
SCI5_AM
-
-
-
-
-
SCI6_RXI
-
-
-
SCI6_TXI
-
-
-
19Ah
SCI6_TEI
-
-
-
-
-
19Bh
SCI6_ERI
-
-
-
-
-
19Ch
SCI6_AM
-
-
-
-
-
198h
199h
SCI6
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Table 14.4
14. Interrupt Controller Unit (ICU)
Event table (8 of 8)
IELSRn
Event
number
Interrupt request
source
19Eh
SCI7
DELSRn
Name
Connect
to NVIC
Invoke
DTC
Invoke
DMAC
Canceling
Snooze
mode
Canceling
Software
Standby
mode
Canceling
Deep
Software
Standby
mode
-
SCI7_RXI
-
-
19Fh
SCI7_TXI
-
-
-
1A0h
SCI7_TEI
-
-
-
-
-
1A1h
SCI7_ERI
-
-
-
-
-
1A2h
SCI7_AM
-
-
-
-
-
SCI8_RXI
-
-
1A5h
1A4h
SCI8_TXI
-
-
-
1A6h
SCI8_TEI
-
-
-
-
-
1A7h
SCI8_ERI
-
-
-
-
-
1A8h
SCI8_AM
-
-
-
-
-
1AAh
SCI8
SCI9_RXI
-
-
1ABh
SCI9_TXI
-
-
-
1ACh
SCI9_TEI
-
-
-
-
-
1ADh
SCI9_ERI
-
-
-
-
-
1AEh
SCI9_AM
-
-
-
-
-
1BCh
SCI9
SPI0_SPRI
-
-
1BDh
SPI0_SPTI
-
-
-
1BEh
SPI0_SPII
-
-
-
-
-
1BFh
SPI0_SPEI
-
-
-
-
-
1C0h
SPI0_SPTEND
-
-
-
-
-
1C1h
SPI0
SPI1_SPRI
-
-
1C2h
SPI1
SPI1_SPTI
-
-
-
1C3h
SPI1_SPII
-
-
-
-
-
1C4h
SPI1_SPEI
-
-
-
-
-
1C5h
SPI1_SPTEND
-
-
-
-
-
1C6h
QSPI
QSPI_INTR
-
-
-
-
-
1C7h
SDHI0
SDHI_MMC0_ACCS
-
-
-
-
-
1C8h
SDHI_MMC0_SDIO
-
-
-
-
-
1C9h
SDHI_MMC0_CARD
-
-
-
-
-
1CAh
SDHI_MMC0_ODMSDBREQ
-
-
-
-
1CBh
SDHI_MMC1_ACCS
-
-
-
-
-
1CCh
SDHI_MMC1_SDIO
-
-
-
-
-
1CDh
SDHI_MMC1_CARD
-
-
-
-
-
1CEh
SDHI_MMC1_ODMSDBREQ
-
-
-
-
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
14.4
SDHI1
Only supported when CMPCTL0.CSTEN = 1.
Only supported when KRCTL.KRMD = 1.
Only the first edge detection is valid.
Only interrupts after DTC transfer are supported.
Using SELSR0.
Interrupt Operation
The ICU performs the following functions:
Detecting interrupts
Enabling and disabling interrupts
Selecting interrupt request destinations such as CPU interrupt, DTC activation, or DMAC activation.
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14.4.1
14. Interrupt Controller Unit (ICU)
Detecting Interrupts
External pin interrupt requests are detected by either the edge or level (falling edge, rising edge, rising and falling edges,
or low level) of the interrupt signal. Set the IRQMD[1:0] bits in the IRQCRi register to select the detection mode for the
IRQi pins. For interrupt sources associated with peripheral modules, see section 14.3.2, Event Numbers. Events must be
accepted by the NVIC before an interrupt occurs and is accepted by the CPU.
ICU
CPU: NVIC
IELSR
Set through software interrupt
Event select
Event
IR
Interrupt
source
Pending
Set
Set
Reset
Reset
Enable register
Clear through software
Figure 14.2
Automatically cleared by
the interrupt completion
Interrupt path of the ICU and CPU: NVIC
Use the procedures in this section to detect interrupts:
General operations during an interrupt
When a non-software interrupt occurs:
The IELSRn.IR flag and Interrupt Set/Clear-Pending register (NVIC) are set.
When a software interrupt occurs:
Set the Interrupt Set-Pending register.
When an interrupt is complete:
Clear the IELSRn.IR flag in the software.
The Interrupt Set/Clear-Pending register clears automatically.
When interrupts are enabled
a. Set the Interrupt Set-Enable register (NVIC).
b. Set the IELSRn.IELS bits as the interrupt source.
c. Specify the operation settings for the event source.
When interrupts are disabled
d. Disable the settings for the event source.
e. Clear the IELSRn.IELS bits (IELSRn.IELS = 0000h). Clear the IELSRn.IR flag as required.
f. Clear the Interrupt Clear-Enable register. Clear the Interrupt Clear-Pending register as required.
When polling for interrupts
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14. Interrupt Controller Unit (ICU)
g. Set the Interrupt Clear-Enable register (disabling interrupts).
h. Set the IELSRn.IELS bits (selecting the source).
i. Specify the operation settings for the event source.
j. Poll the Interrupt Set-Pending register.
k. When polling is no longer required, follow the procedure for clearing an interrupt when it is complete. Clear the
IELSRn.IR flag through software.
14.4.2
Selecting Interrupt Request Destinations
The interrupt output destination, CPU, DTC, or DMAC, can be independently selected for each interrupt source. The
available destinations are fixed for each interrupt, as described in Table 14.4.
Note:
Do not use an interrupt request destination setting that is not indicated by a “” in the event list (Table 14.4).
If you select the CPU or DTC in one IELSRn register, setting the same interrupt factor in any other IELSRn register is
prohibited. Similarly, if you select the DMAC in one DELSRn register, setting the same interrupt factor in any other
DELSRn register is prohibited.
Note:
Setting the same interrupt factor for IELSRn and DELSRn is prohibited.
If the DMAC or DTC is selected as the destination for requests from an IRQi pin, you must set the IRQMD[1:0] bits in
IRQCRi for that interrupt to select edge detection.
14.4.2.1
CPU interrupt request
When IELSRn.DTCE = 0, the event specified in the IELSRn register is output to the NVIC. Set the IELSRn.IELS bits to
the target event and the IELSRn.DTCE bit to 0.
14.4.2.2
DTC activation
When IELSRn.DTCE = 1, the event specified in the IELSRn register is output to the DTC. After DTC transmission
completes, the associated interrupt occurs. Use the following procedure:
1. Set the IELSRn.IELS bits to the target event and the IELSRn.DTCE bit to 1.
2. Set the DTC module start bit (DTCST.DTCST) to 1.
Table 14.5 shows operation when the DTC is the request destination.
Table 14.5
Operations when the DTC is activated
Interrupt
request
destination
DISEL*1
Remaining
transfer
operations
DTC*3
1
0
Note 1.
Note 2.
Note 3.
Operations per
request
IR*2
≠0
DTC transfer CPU
interrupt
Cleared on interrupt acceptance
by the CPU
DTC
=0
DTC transfer CPU
interrupt
Cleared on interrupt acceptance
by the CPU
The IELSRn.DTCE bit is cleared
and the CPU becomes the
destination
≠0
DTC transfer
Cleared at the start of DTC data
transfer after DTC transfer data
is read
DTC
=0
DTC transfer CPU
interrupt
Cleared on interrupt acceptance
by the CPU
The IELSRn.DTCE bit is cleared
and the CPU becomes the
destination
Interrupt request destination
after transfer
Set the interrupt request mode for the DTC in the DTC.MRB.DISEL bit.
When the IELSRn.IR flag is 1, an interrupt request (DTC activation request) that occurs again is ignored.
For chain transfers, DTC transfer continues until the last chain transfer ends. At this point, the DISEL bit state and the
remaining transfer count determine whether a CPU interrupt occurs, the IELSRn.IR flag clear timing, and the interrupt request
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14. Interrupt Controller Unit (ICU)
destination after transfer. See Table 18.3, Chain transfer conditions, in section 18, Data Transfer Controller (DTC).
14.4.2.3
DMAC activation
Events specified in the DELSRn registers are output to the DMAC. When using interrupts, you must select the DMAC as
the interrupt source in the IELSRn.IELS[8:0] bits and enable DMAC output by setting IELSRn.DTCE to 1. When
IELSRn.DTCE is 0, the events specified in the IELSRn registers are output to the NVIC. Use the following procedure:
1. Set the DELSRn.DELS[8:0] bits to the target event.
2. When using interrupts, set the IELSRn.IELS bit to DMAC interrupts as the source, and set the IELSRn.DTCE bit to
1.
3. Set the activation source for the target DMAC channel (DMACm.DMTMD.DCTG[1:0]) to 01b (interrupt module
detection).
4. Set the DMAC transfer enable bit for the target DMAC channel (DMACm.DMCNT.DTE) to 1.
5. Set the DMAC operation enable bit (DMACm.DMAST.DMST) to 1.
ICU
IELSR
Event
numbers
32 to 39
Interrupt
sources
CPU
Interrupt requests
IR
N
V
I
C
IR
IR
IR
IR
DELSR
DMAC activation
request
DMAC activation request
DMAC
activation
control
DMAC
DMAC response
DMAC interrupt
Figure 14.3
14.4.3
DMAC request trigger and interrupt path
Digital Filter
A digital filter function is provided for the external interrupt request pins (IRQi, i = 0 to 15) and NMI pin interrupt. It
samples input signals on the filter PCLKB sampling clock and removes any signal with a pulse width less than 3
sampling cycles.
To use the digital filter for an IRQi pin:
1. Set the sampling clock cycle to PCLKB, PCLKB/8, PCLKB/32, or PCLKB/64 in the IRQCRi.FCLKSEL[1:0] bits.
2. Set the IRQCRi.FLTEN bit to 1 (digital filter enabled).
To use the digital filter for the NMI pin:
1. Set the sampling clock cycle to PCLKB, PCLKB/8, PCLKB/32, or PCLKB/64 in the NMICR.NFCLKSEL[1:0]
bits.
2. Set the NMICR.NFLTEN bit to 1 (digital filter enabled).
Figure 14.4 shows an example of digital filter operation.
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14. Interrupt Controller Unit (ICU)
Sampling clock
for digital filter
IRQCRi.FLTEN bit
Pulses removed
The level matches
three times
IRQi pin
The level matches
three times
IRQi_d
(internal flip-flop)
Digital filter enabled
Disabled
Enabled
Operation example with IRQCRi.IRQMD[1:0] = 11b (low-level detection)
Figure 14.4
Digital filter operation example
Before entering Software Standby mode, disable the digital filters by clearing the IRQCRi.FLTEN and NMICR.NFLTEN
bits. The clock for the ICU stops in Software Standby mode. On exiting Software Standby, the circuit detects the edge by
comparing the state before standby to the state after standby release. If the input changes during Software Standby, an
incorrect edge might be detected. You can enable the digital filters again after exiting Software Standby mode.
14.4.4
External Pin Interrupts
To use external pin interrupts:
1. Clear the IRQCRi.FLTEN bit (i = 0 to 15) to 0 (digital filter disabled).
2. Set or confirm the I/O port settings.
3. Set the IRQMD[1:0] bits, FCLKSEL[1:0] bits, and FLTEN bit of the IRQCRi register.
4. Select the IRQ pin as follows:
If the IRQ pin is to be used for CPU interrupt requests, set the IELSRn.IELS bits and set the IELSRn.DTCE bit
to 0
If the IRQ pin is to be used for DTC activation, set the IELSRn.IELS bits and set the IELSRn.DTCE bit to 1
If the IRQ pin is to be used for DMAC activation, set the DELSRn.DELS bits.
14.5
Non-Maskable Interrupt Operation
The following sources can trigger a non-maskable interrupt:
NMI pin interrupt
Oscillation stop detection interrupt
WDT underflow/refresh error interrupt
IWDT underflow/refresh error interrupt
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
SRAM parity error interrupt
SRAM ECC error interrupt
MPU bus master error interrupt
MPU bus slave error interrupt
CPU stack pointer monitor interrupt.
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14. Interrupt Controller Unit (ICU)
Non-maskable interrupts can only be used with the CPU, not to activate the DTC or DMAC. Non-maskable interrupts
take precedence over all other interrupts. The non-maskable interrupt states can be verified in the Non-Maskable
Interrupt Status Register (NMISR). Confirm that all bits in the NMISR are 0 before returning from the NMI handler.
Non-maskable interrupts are disabled by default. To use non-maskable interrupts, you must:
1. Clear the NMICR.NFLTEN bit to 0 (digital filter disabled) to use the NMI pin.
2. Set the NMIMD bit, NFCLKSEL[1:0] bits, and NFLTEN bit of NMICR register to use the NMI pin.
3. Write 1 to the NMICLR.NMICLR bit to clear the NMISR.NMIST flag to 0 to use the NMI pin.
4. Enable the non-maskable interrupt by writing 1 to the associated bit in the Non-Maskable Interrupt Enable Register
(NMIER).
After 1 is written to the NMIER register, subsequent write access to the NMIEN bit in NMIER is ignored. An NMI
interrupt cannot be disabled when enabled, except by a reset.
14.6
Return from Low Power Modes
Table 14.4 lists the interrupt sources you can use to exit Sleep or Software Standby mode. For more information, see
section 11, Low Power Modes. Sections 14.6.1 to 14.6.3 describe how to use interrupts to return from Sleep, Software
Standby, and Snooze modes. For Deep Software Standby, see section 11.9, Deep Software Standby Mode.
14.6.1
Return from Sleep Mode
To return from Sleep mode in response to an interrupt:
1. Select the CPU as the interrupt request destination.
2. Enable the interrupt in the NVIC.
To return from Sleep mode in response to a non-maskable interrupt, use the NMIER register to enable the target interrupt
request.
14.6.2
Return from Software Standby Mode
The ICU can return from Software Standby mode using a non-maskable interrupt or an interrupt selected in the WUPEN
register. See section 14.2.9, Wake Up Interrupt Enable Register (WUPEN).
To return from Software Standby mode:
1. Select the interrupt source that enables return from Software Standby.
For non-maskable interrupts, use the NMIER register to enable the target interrupt request
For maskable interrupts, use the WUPEN register to enable the target interrupt request.
2. Select the CPU as the interrupt request destination.
3. Enable the interrupt in the NVIC.
Interrupt requests through the IRQ pins that do not satisfy these conditions are not detected while the clock is stopped in
Software Standby mode.
14.6.3
Return from Snooze Mode
The ICU can return from Snooze mode using the interrupts provided for this mode.
To return to Normal mode from Snooze mode:
1. Use either of the following methods to select the event that you want to trigger a return to Normal mode from
Snooze mode:
Set the event that you want to trigger a return to Normal mode from Snooze mode in SELSR0.SEL and set the
value 02Dh (ICU_SNZCANCEL) in IELSRn.IELS.
Set the event that you want to trigger a return to Normal mode from Snooze mode in IELSRn.IELS.
2. Select the CPU as the interrupt request destination.
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14. Interrupt Controller Unit (ICU)
3. Enable the interrupt in the NVIC.
Note:
14.7
In Snooze mode, a clock is supplied to the ICU. If an event selected in IELSRn is detected, the CPU can
acknowledge the interrupt after returning to Normal mode from Software Standby mode. If an event selected in
DELSRn is detected, the DMAC can acknowledge the interrupt after returning to Normal mode from Software
Standby mode.
Using the WFI Instruction with Non-Maskable Interrupts
Whenever a WFI instruction is executed, confirm that all status flags in the NMISR register are 0.
14.8
Reference
ARM® Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D).
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15.
Buses
15.1
Overview
15. Buses
Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses
assigned for each bus.
This bus interface can also apply to connect LCD Intel 8080 and Motorola 6800 interfaces.
Table 15.1
Bus specifications
Bus type
Main bus
Slave
interface
External bus
Specifications
ICode bus (CPU)
Connected to the CPU
Connected to the on-chip memory (code flash memory, SRAMHS).
DCode bus (CPU)
Connected to the CPU
Connected to the on-chip memory (code flash memory, SRAMHS).
System bus (CPU)
Connected to the CPU
Connected to the on-chip memory, internal peripheral buses, and external bus.
DMA bus
Connected to the DMAC and DTC
Connected to the on-chip memory, internal peripheral buses, and external bus.
ETHER bus
Connected to the EDMAC
Connected to the on-chip memory, internal peripheral buses, and external bus.
Memory bus 1
Connected to code flash memory
Memory bus 2
Connected to SRAMHS
Memory bus 3
Connected to code flash memory and SRAMHS through the DMA bus and ETHER
bus
Memory bus 4
Connected to SRAM0
Memory bus 5
Connected to Standby SRAM
Internal peripheral bus 1
Connected to system control related to peripheral modules
Internal peripheral bus 3
Connected to peripheral modules (CAC, ELC, I/O ports, POEG, RTC, WDT, IWDT,
IIC, CAN, SSIE, SRC, ADC12, DAC12, TSN, and DOC)
Internal peripheral bus 4
Connected to peripheral modules (GPT, ETHERC, EDMAC, SCI, IrDA, SPI, CRC,
and SDHI)
Internal peripheral bus 5
Connected to peripheral modules (KINT, AGT, USBFS, PDC, ACMPHS, and CTSU)
Internal peripheral bus 7
Connected to Secure IPs (SCE7)
Internal peripheral bus 9
Connected to flash memory (in P/E)*1, data flash memory, and TSN
CS area
Connected to the external devices
SDRAM area
Connected to SDRAM
QSPI area
Connected to the external SPI devices
Note 1. P/E: Programming and erasure.
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15. Buses
DMAC/
DTC
CM4
EDMAC
ICode bus
DCode bus
System bus
DMA bus
ETHER bus
SRAM0
Data flash
memory
Internal
peripherals
External bus
controller
Standby
SRAM
Code flash
memory
Figure 15.1
Table 15.2
SRAMHS
Bus configuration
Addresses assigned for each bus
Addresses
Bus
Area
0000 0000h to 01FF FFFFh
Memory bus 1, 3
Code flash memory
1FFE 0000h to 1FFF FFFFh
Memory bus 2, 3
SRAMHS
2000 0000h to 2003 FFFFh
Memory bus 4
SRAM0
2004 0000h to 200F FFFFh
Memory bus 5
Standby SRAM
4000 0000h to 4001 FFFFh
Internal peripheral bus 1
Peripheral I/O registers
4004 0000h to 4005 FFFFh
Internal peripheral bus 3
4006 0000h to 4007 FFFFh
Internal peripheral bus 4
4008 0000h to 4009 FFFFh
Internal peripheral bus 5
400C 0000h to 400D FFFFh
Internal peripheral bus 7
Secure IPs
4010 0000h to 407F FFFFh
Internal peripheral bus 9
Flash memory (in P/E*1), data flash memory, and TSN
6000 0000h to 67FF FFFFh
External bus
QSPI area
8000 0000h to 97FF FFFFh
External bus
CS area and SDRAM area
Note 1.
15.2
15.2.1
P/E: Programming and erasure.
Description of Buses
Main Buses
The main buses for the CPU constitute the ICode bus, DCode bus, and system bus:
The ICode and DCode buses are connected to the code flash memory and SRAMHS. The ICode bus is used for
instruction access to the CPU, and the DCode bus is used for data access to the CPU.
The system bus is connected to the SRAM0, Standby SRAM, data flash memory, internal peripheral buses, and
external bus. It is used for instruction and data accesses to the CPU.
The main bus for modules other than the CPU consists of the DMA bus, and ETHER bus:
The DMA bus is connected to the code flash memory, SRAMHS, SRAM0, Standby SRAM, data flash memory, and
external bus
The ETHER bus is connected to the code flash memory, SRAMHS, SRAM0, Standby SRAM, data flash memory,
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15. Buses
and external bus.
Different master and slave transfer combinations can proceed simultaneously.
Arbitration between the DMAC and DTC for the mastership of the DMA bus occurs in the DMAC and DTC. The
following fixed-priority order is used:
DMAC0 > DMAC1 > DMAC2 > DMAC3 > DMAC4 > DMAC5 > DMAC6 > DMAC7 > DTC.
Only one DTC and DMAC channels that have accepted the activation requests can issue the bus mastership request. In
addition, requests for bus access from masters other than the DTC are not accepted during reads of transfer control
information for the DTC.
The arbitration protocol is selectable as either fixed-priority or round-robin. For more information, see section 15.3.19,
Slave Bus Control Register (BUSSCNT).
15.2.2
Slave Interface
Products using the Cortex®-M4 core contain ICode and DCode bus areas and a system bus area.
To create the ICode and DCode bus areas, a bus matrix connects the ICode bus, DCode bus, and memory bus 3 from the
main bus to the slave interfaces of the code flash memory and SRAMHS. Bus access to the slave interfaces is arbitrated
between the three buses. The arbitration protocol is selectable as either fixed-priority or round-robin. For more
information, see section 15.3.19, Slave Bus Control Register (BUSSCNT).
To create the system bus area, a bus matrix connects the system bus, DMA bus, and ETHER bus from the main bus to the
slave interfaces of the SRAM0, Standby SRAM, data flash memory, internal peripherals, and external bus. Bus access to
the slave interfaces is arbitrated between the three buses. The arbitration protocol is selectable as either fixed-priority or
round-robin. For more information, see section 15.3.19, Slave Bus Control Register (BUSSCNT).
For connections from the main bus to the slave interfaces, see the slave interfaces in Table 15.1. For a description of the
external bus, see section 15.2.3, External Bus.
Different master and slave transfer combinations can proceed simultaneously.
15.2.3
External Bus
The external bus controller arbitrates requests for bus access on the external address space from the CPU system bus,
DMAC bus, and ETHER bus. The priority order can be set using the external bus priority control bits
(BUSSCNT.ARBMET[1:0]). For more information, see section 15.3.19, Slave Bus Control Register
(BUSSCNT).
The bus system provides an external space for the QSPI. See section 37, Quad Serial Peripheral Interface (QSPI).
Table 15.3 lists the external bus specifications and Table 15.4 lists the I/O pins.
Table 15.3
External bus specifications (1 of 2)
Parameter
Specifications
External address space
The external address space is divided into 8 CS areas (CS0 to CS7) and the SDRAM area (SDCS) for
management
Chip select signals can be output for each area
The bus width can be set for each area:
- Separate bus: Selectable to 8-bit or 16-bit bus space
- Address/data multiplexed bus: Selectable to 8-bit or 16-bit bus space
Endian mode can be specified for each area.
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Table 15.3
15. Buses
External bus specifications (2 of 2)
Parameter
Specifications
CS area controller
Recovery cycles can be inserted:
- Read recovery: Up to 15 cycles
- Write recovery: Up to 15 cycles
Cycle wait function: Wait for up to 31 cycles (for page access, up to 7 cycles)
Use wait control to set up:
- Assertion and negation timing of chip select signals (CS0 to CS7)
- Assertion timing of the read signal (RD) and write signals (WR0/WR and WR1)
- Timing of data output starts and ends
Write access modes:
- Single-write strobe mode and byte strobe mode
Separate bus or address/data multiplexed bus can be set for each area.
SDRAM area controller
Multiplexed output of row address and column address (8, 9, 10, or 11 bits)
Self-refresh and auto-refresh selectable
CAS latency can be specified from 1 to 3 cycles.
Write buffer function
When write data from the bus master is written to the write buffer, write access by the bus master is
complete
Frequency
The CS area controller (CSC) operates in synchronization with the external bus clock (BCLK)*1
The frequency of the EBCLK pin output is the same as BCLK by default. Half of the BCLK cycles can be
supplied by setting the EBCLK Pin Output Select bit, BCKCR.BCLKDIV, in the External Bus Clock Control
Register. For more information, see section 9, Clock Generation Circuit.
The SDRAM area controller (SDRAMC) operates in synchronization with the SDRAM clock (SDCLK).
Note 1.
BCLK and SDCLK must operate at the same frequency when the SDRAM is in use.
Table 15.4
External bus I/O pins (1 of 2)
Pin name
I/O
EBCLK,
SDCLK*1
Output
CSC,
SDRAMC
Description
Clock output pin
A20 to A00*2
Output
CSC,
SDRAMC
Address output pins
D15 to D00
DQ15 to DQ00
I/O
CSC,
SDRAMC
D15 to D00 are CSC data input/output pins
DQ15 to DQ00 are SDRAMC data input/output pins
D015 to D00, DQ15 to DQ00 pins are enabled when the 16-bit bus space is specified
D07 to D00, DQ07 to DQ00 pins are enabled when the 8-bit bus space is specified.
BC0
Output
CSC
Strobe signal that indicates (when low) that D07 to D00 are valid during access to an
external address space in single-write strobe mode, active-low
When an 8-bit bus space is specified, this output pin is always held low regardless of
the write access mode.
BC1
Output
CSC
Strobe signal that indicates (when low) that D15 to D08 are valid during access to an
external address space in single-write strobe mode, active-low
This pin is not used when the 8-bit bus space is specified.
CS0*3
Output
CSC
Chip select signal for area 0 (CS0), active-low
CS1*3
Output
CSC
Chip select signal for area 1 (CS1), active-low
CS2*3
Output
CSC
Chip select signal for area 2 (CS2), active-low
CS3*3
Output
CSC
Chip select signal for area 3 (CS3), active-low
CS4
Output
CSC
Chip select signal for area 4 (CS4), active-low
CS5
Output
CSC
Chip select signal for area 5 (CS5), active-low
CS6
Output
CSC
Chip select signal for area 6 (CS6), active-low
CS7
Output
CSC
Chip select signal for area 7 (CS7), active-low
RD
Output
CSC
Strobe signal that indicates that a read from an external address space (CS0 to CS7) is
in progress, active-low
WR0/WR*4
Output
CSC
WR0 signal is a strobe signal that indicates that a write to an external address space
is in progress in byte strobe mode, and D07 to D00 are valid, active-low
WR signal is a strobe signal that indicates that a write to an external address space is
in progress in single-write strobe mode, active-low
When an 8-bit bus space is specified, this output pin is held low during a write access
regardless of the write access mode.
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Table 15.4
15. Buses
External bus I/O pins (2 of 2)
Pin name
I/O
WR1
Output
CSC
Strobe signal that indicates that D15 to D08 are valid during a write to an external
address space in byte strobe mode, active-low
This signal is invalid in single-write strobe mode
This pin is not used when the 8-bit bus space is specified.
ALE
Output
CSC
Address latch signal when address/data multiplexed bus is selected
WAIT
Input
CSC
Wait request signal used when accessing the external address space (CS0 to CS7),
active-low
CKE
Output
SDRAMC
Clock enable signal
SDCS
Output
SDRAMC
Chip select signal, active-low
RAS
Output
SDRAMC
Row address strobe signal, active-low
CAS
Output
SDRAMC
Column address strobe signal, active-low
WE
Output
SDRAMC
Write enable signal, active-low
DQM0
Output
SDRAMC
I/O data mask enable signal for DQ07 to DQ00
DQM1
Output
SDRAMC
I/O data mask enable signal for DQ15 to DQ08
Note 1.
Note 2.
Note 3.
Note 4.
15.2.4
Description
The EBCLK and the SDCLK pin functions are shared by the CS area controller (CSC) and the SDRAM area controller
(SDRAMC).
When using the CSC and the SDRAMC simultaneously, the SDCLK pin function is valid.
The A20 to A00 pin functions are shared by the CSC and the SDRAMC.
When using the CSC only:
The A00 and BC0 pin functions share the same pin, and either becomes valid according to the area, with the function being
A00 in byte strobe mode and BC0 in single-write strobe mode. Setting the 8-bit external bus width is prohibited in single-write
strobe mode.
When using the SDRAMC only:
The A15 to A00 pin functions are valid.
The A00 and DQM1 pin functions share the same pin, and either becomes valid according to the external bus width.
When selecting 8-bit bus width, the pin function is A00. When selecting 16-bit bus width, the pin function is DQM1.
When using the CSC and the SDRAMC simultaneously:
The A20 to A16 pin functions are valid for CSC. The A15 to A00 pin functions are shared by the CSC and the SDRAMC.
In the SDRAMC functions, the A00 and the DQM1 pin function works as described.
In the CSC functions, the A00 and the BC0 pin function works as described.
The CS0 to CS3 (CSC) and SDRAMC pin functions share the same pin. When using the CSC and the SDRAMC
simultaneously, the CS0 to CS3 pin functions are invalid.
The WR0 signal and WR signal are identical. The WR0 signal is referred to as WR in single-write strobe mode.
Parallel Operations
Parallel operations are possible when different bus masters request access to different slave modules. For example, if the
CPU fetches an instruction from the flash and an operand from the SRAM, the DMAC can handle transfers between a
peripheral bus and the external bus at the same time.
An example of parallel operations is shown in Figure 15.2. In this example, the CPU uses the instruction and operand
buses for simultaneous access to the flash and SRAM, respectively. Additionally, the DMAC/DTC, and EDMAC
simultaneously use the DMA bus (DMAC/DTC), and ETHER bus (EDMAC) for access to a peripheral bus or external
bus during access to the flash memory and SRAM by the CPU.
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15. Buses
Flash access
CPU instruction fetching
Flash
Flash
Flash
CPU operand
SRAM
SRAM
SRAM
Flash
Flash
Flash
Flash
SRAM
SRAM
SRAM access
DMAC
Figure 15.2
15.2.5
SRAM
SRAM
Peripheral bus access
External bus access
Peripheral bus
External bus
Example of parallel operations
Bus Settings
Set up the external bus with the following registers:
Mode settings:
CSn Mode Register (CSnMOD), CSn Wait Control Register 1 (CSnWCR1), CSn Wait Control Register 2
(CSnWCR2), CSn Control Register (CSnCR), CSn Recovery Cycle Setting Register (CSnREC), CS Recovery
Cycle Insertion Enable Register (CSRECEN), and Bus Priority Control Register (BUSSCNT)
I/O port assignments:
PmnPFS.PMR = 1 and PmnPFS.PSEL[4:0] = 0Bh
Frequency of the external bus clock (BCLK) and SDRAM clock (SDCLK):
SCKDIVCR register.
See section 20, I/O Ports, for information on PmnPFS and section 9, Clock Generation Circuit for information on
SCKDIVCR.
15.2.6
(1)
Restrictions
Endianness constraint
Memory space must be little-endian to execute code on the Cortex®-M4 core.
15.3
Register Descriptions
15.3.1
CSn Control Register (CSnCR) (n = 0 to 7)
Address(es): BUS.CS0CR 4000 3802h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
MPXEN
—
—
—
EMOD
E
—
—
BSIZE[1:0]
—
—
—
EXENB
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
Address(es): BUS.CS1CR 4000 3812h, BUS.CS2CR 4000 3822h, BUS.CS3CR 4000 3832h, BUS.CS4CR 4000 3842h,
BUS.CS5CR 4000 3852h, BUS.CS6CR 4000 3862h, BUS.CS7CR 4000 3872h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
BSIZE[1:0]
—
—
—
EXENB
0
0
0
0
0
0
0
—
—
—
MPXEN
—
—
—
EMOD
E
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
EXENB
Operation Enable
0: Disable operation
1: Enable operation.
R/W
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15. Buses
Bit
Symbol
Bit name
Description
R/W
b3 to b1
—
b5, b4
BSIZE[1:0]
Reserved
These bits are read as 0. The write value should be 0.
R/W
External Bus Width Select
b5 b4
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
EMODE
Endian Mode
0: Little-endian
1: Big-endian.
R/W
b11 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b12
MPXEN
Address/Data Multiplexed I/O
Interface Select
0: Separate bus interface is selected for area n
1: Address/data multiplexed I/O interface is selected for
area n. (n = 0 to 7).
b15 to b13
—
Reserved
These bits are read as 0. The write value should be 0.
0 0: 16-bit bus space
0 1: Setting prohibited
1 0: 8-bit bus space
1 1: Setting prohibited.
R/W
Do not attempt to write to the CSnCR register while the external bus is being accessed.
EXENB bit (Operation Enable)
The EXENB bit enables operation of the associated CS area. On MCU reset, operation is enabled (EXENB = 1) only for
area 0. Operation in other areas is disabled (EXENB = 0). Attempts to access disabled areas have no effect.
When the CSC and SDRAMC are in use at the same time, BCLK and SDCLK must operate at the same frequency.
BSIZE[1:0] bits (External Bus Width Select)
The BSIZE[1:0] bits specify the data bus width for the associated area.
EMODE bit (Endian Mode)
The EMODE bit specifies the endianness for the associated area. The Cortex®-M4 core is fixed at little-endian order, so
instruction code can only be allocated to external spaces with little-endian specified. If an area is specified as big-endian,
no instruction code can be allocated to it.
MPXEN bit (Address/Data Multiplexed I/O Interface Select)
Th MPXEN bit specifies separate bus interface or address/data multiplexed I/O interface of each area.
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15.3.2
15. Buses
CSn Recovery Cycle Register (CSnREC) (n = 0 to 7)
Address(es): BUS.CS0REC 4000 380Ah, BUS.CS1REC 4000 381Ah, BUS.CS2REC 4000 382Ah, BUS.CS3REC 4000 383Ah,
BUS.CS4REC 4000 384Ah, BUS.CS5REC 4000 385Ah, BUS.CS6REC 4000 386Ah, BUS.CS7REC 4000 387Ah
b15
b14
b13
b12
—
—
—
—
0
0
0
0
Value after reset:
b11
b10
b9
b8
WRCV[3:0]
0
0
0
0
b7
b6
b5
b4
—
—
—
—
0
0
0
0
b3
b2
b1
b0
RRCV[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
RRCV[3:0]
Read Recovery
b3
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b11 to b8
WRCV[3:0]
Write Recovery
b11
b15 to b12
—
Reserved
These bits are read as 0. The write value should be 0. R/W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: Do not insert any recovery cycles
1: Insert 1 recovery cycle
0: Insert 2 recovery cycles
1: Insert 3 recovery cycles
0: Insert 4 recovery cycles
1: Insert 5 recovery cycles
0: Insert 6 recovery cycles
1: Insert 7 recovery cycles
0: Insert 8 recovery cycles
1: Insert 9 recovery cycles
0: Insert 10 recovery cycles
1: Insert 11 recovery cycles
0: Insert 12 recovery cycles
1: Insert 13 recovery cycles
0: Insert 14 recovery cycles
1: Insert 15 recovery cycles.
b8
0: Do not insert any recovery cycles
1: Insert 1 recovery cycle
0: Insert 2 recovery cycles
1: Insert 3 recovery cycles
0: Insert 4 recovery cycles
1: Insert 5 recovery cycles
0: Insert 6 recovery cycles
1: Insert 7 recovery cycles
0: Insert 8 recovery cycles
1: Insert 9 recovery cycles
0: Insert 10 recovery cycles
1: Insert 11 recovery cycles
0: Insert 12 recovery cycles
1: Insert 13 recovery cycles
0: Insert 14 recovery cycles
1: Insert 15 recovery cycles.
R/W
Do not attempt to write to the CSnREC register while the external bus is being accessed.
When the preceding bus access is from a separate bus, CSnREC is valid when the recovery cycle insertion is enabled in
the Separate Bus Recovery Cycle Insertion Enable bit (RCVENi (i = 0 to 7)) in CSRECEN. When the preceding bus
access is an address/data multiplexed bus access, CSnREC is valid when the recovery cycle insertion is enabled with the
Multiplexed Bus Recovery Cycle Insertion Enable bit (RCVENMj (j = 0 to 7)) in CSRECEN. For more information, see
section 15.5.4, Insertion of Recovery Cycles.
RRCV[3:0] bits (Read Recovery)
The RRCV[3:0] bits specify the number of recovery cycles inserted after a read access on the external bus for CSn (n = 0
to 7). When recovery cycle insertion is enabled and a value other than 0000b is set, 1 to 15 recovery cycles are inserted
when:
After a read access to the external bus, a read access is made to the external bus in the same area
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15. Buses
After a read access to the external bus, a read access is made to the external bus in a different area
After a read access to the external bus, a write access is made to the external bus in the same area
After a read access to the external bus, a write access is made to the external bus in a different area.
WRCV[3:0] bits (Write Recovery)
The WRCV[3:0] bits specify the number of recovery cycles inserted after a write access on the external bus for CSn (n =
0 to 7). When recovery cycle insertion is enabled and a value other than 0000b is set, 1 to 15 recovery cycles are inserted
when:
After a write access to the external bus, a read access is made to the external bus in the same area
After a write access to the external bus, a read access is made to the external bus in a different area
After a write access to the external bus, a write access is made to the external bus in the same area
After a write access to the external bus, a write access is made to the external bus in a different area.
15.3.3
CS Recovery Cycle Insertion Enable Register (CSRECEN)
Address(es): BUS.CSRECEN 4000 3880h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN
M7
M6
M5
M4
M3
M2
M1
M0
7
6
5
4
3
2
1
0
Value after reset:
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
Bit
Symbol
Bit name
Description
R/W
b0
RCVEN0
Separate Bus Recovery Cycle Insertion
Enable 0
0: Disable
1: Enable.
R/W
b1
RCVEN1
Separate Bus Recovery Cycle Insertion
Enable 1
0: Disable
1: Enable.
R/W
b2
RCVEN2
Separate Bus Recovery Cycle Insertion
Enable 2
0: Disable
1: Enable.
R/W
b3
RCVEN3
Separate Bus Recovery Cycle Insertion
Enable 3
0: Disable
1: Enable.
R/W
b4
RCVEN4
Separate Bus Recovery Cycle Insertion
Enable 4
0: Disable
1: Enable.
R/W
b5
RCVEN5
Separate Bus Recovery Cycle Insertion
Enable 5
0: Disable
1: Enable.
R/W
b6
RCVEN6
Separate Bus Recovery Cycle Insertion
Enable 6
0: Disable
1: Enable.
R/W
b7
RCVEN7
Separate Bus Recovery Cycle Insertion
Enable 7
0: Disable
1: Enable.
R/W
b8
RCVENM0
Multiplexed Bus Recovery Cycle Insertion
Enable 0
0: Disable
1: Enable.
R/W
b9
RCVENM1
Multiplexed Bus Recovery Cycle Insertion
Enable 1
0: Disable
1: Enable.
R/W
b10
RCVENM2
Multiplexed Bus Recovery Cycle Insertion
Enable 2
0: Disable
1: Enable.
R/W
b11
RCVENM3
Multiplexed Bus Recovery Cycle Insertion
Enable 3
0: Disable
1: Enable.
R/W
b12
RCVENM4
Multiplexed Bus Recovery Cycle Insertion
Enable 4
0: Disable
1: Enable.
R/W
b13
RCVENM5
Multiplexed Bus Recovery Cycle Insertion
Enable 5
0: Disable
1: Enable.
R/W
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15. Buses
Bit
Symbol
Bit name
Description
R/W
b14
RCVENM6
Multiplexed Bus Recovery Cycle Insertion
Enable 6
0: Disable
1: Enable.
R/W
b15
RCVENM7
Multiplexed Bus Recovery Cycle Insertion
Enable 7
0: Disable
1: Enable.
R/W
Do not attempt to write to the CSRECEN register while the external bus is being accessed. For more information on
insertion recovery cycles, see 15.5.4 Insertion of Recovery Cycles.
RCVENi bit (Separate Bus Recovery Cycle Insertion Enable i) (i = 0 to 7)
The RCVENi bit enables the insertion of read or write recovery cycles when, after a read or write access on the external
bus, a read or write access is made on the external bus to the same or different area.
RCVENMj bit (Multiplexed Bus Recovery Cycle Insertion Enable j) (j = 0 to 7)
The RCVENMj bit enables the insertion of read or write recovery cycles when, after a read or write access on the
external bus, a read or write access is made on the external bus to the same or different area.
Table 15.5
Insertion of recovery cycles
Access type
External address
space
Read access after read access
Same area
Recovery cycles specified in the
RRCV[3:0] bits are inserted for the
priority access area
RCVEN0/RCVENM0
Different area
Recovery cycles specified in the
RRCV[3:0] bits are inserted for the
priority access area
RCVEN1/RCVENM1
Same area
Recovery cycles specified in the
RRCV[3:0] bits are inserted for the
priority access area
RCVEN2/RCVENM2
Different area
Recovery cycles specified in the
RRCV[3:0] bits are inserted for the
priority access area
RCVEN3/RCVENM3
Same area
Recovery cycles specified in the
WRCV[3:0] bits are inserted for the
priority access area
RCVEN4/RCVENM4
Different area
Recovery cycles specified in the
WRCV[3:0] bits are inserted for the
priority access area
RCVEN5/RCVENM5
Same area
Recovery cycles specified in the
WRCV[3:0] bits are inserted for the
priority access area
RCVEN6/RCVENM6
Different area
Recovery cycles specified in the
WRCV[3:0] bits are inserted for the
priority access area
RCVEN7/RCVENM7
Write access after read access
Read access after write access
Write access after write access
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Associated bits
(Separate/Multiplexed)
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15.3.4
15. Buses
CSn Mode Register (CSnMOD) (n = 0 to 7)
Address(es): BUS.CS0MOD 4000 3002h, BUS.CS1MOD 4000 3012h, BUS.CS2MOD 4000 3022h, BUS.CS3MOD 4000 3032h,
BUS.CS4MOD 4000 3042h, BUS.CS5MOD 4000 3052h, BUS.CS6MOD 4000 3062h, BUS.CS7MOD 4000 3072h
b15
Value after reset:
b14
b13
b12
b11
b10
PRMO
D
—
—
—
—
—
0
0
0
0
0
0
b9
b8
PWEN PRENB
B
0
0
b7
b6
b5
b4
b3
—
—
—
—
EWEN
B
0
0
0
0
0
b2
b1
b0
—
—
WRMO
D
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
WRMOD
Write Access Mode Select
0: Byte strobe mode
1: Single-write strobe mode.
R/W
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
EWENB
External Wait Enable
0: Disable
1: Enable.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
PRENB
Page Read Access Enable
0: Disable
1: Enable.
R/W
b9
PWENB
Page Write Access Enable
0: Disable
1: Enable.
R/W
b14 to b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
PRMOD
Page Read Access Mode Select
0: Normal access compatible mode
1: External data read continuous assertion mode.
R/W
Do not write to the CSnMOD register while access to the CSn area is in progress.
WRMOD bit (Write Access Mode Select)
The WRMOD bit selects the write access operating mode. Writing 0 selects byte strobe mode, in which data writes are
controlled by the WRn signals (n = 0 to 1) associated with the respective byte positions. Writing 1 selects single-write
strobe mode, in which data writes are controlled by the BCn (n = 0 to 1) and WR signals associated with the respective
byte positions.
Note:
Setting the external bus width to 8 bits is prohibited in single-write strobe mode.
Table 15.6
Control signals for write access modes
Pin name
Write access mode
WR1
WR0/WR
BC1
BC0
Byte strobe mode
(WR0)
×
×
Single-write strobe mode
×
(WR)
: Enabled, ×: Disabled
EWENB bit (External Wait Enable)
The EWENB bit enables external waits. Writing 0 disables the WAIT signal. Writing 1 selects external wait and allows
the WAIT signal to control the number of waits per cycle. In this state, wait cycles are inserted when the WAIT signal is
low.
PRENB bit (Page Read Access Enable)
The PRENB bit enables page read accesses.
Note:
When the address/data multiplexed I/O interface is selected with the CSnCR.MPXEN bit, PRENB should not be
set to enable page read accesses. Page read accesses are not supported in the address/data multiplexed I/O
interface.
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15. Buses
PWENB bit (Page Write Access Enable)
The PWENB bit enables page write accesses.
Note:
When the address/data multiplexed I/O interface is selected with the CSnCR.MPXEN bit, PWENB should not be
set to enable page write accesses. Page write accesses are not supported in the address/data multiplexed I/O
interface.
PRMOD bit (Page Read Access Mode Select)
The PRMOD bit selects the operating mode for page read accesses. Writing 0 selects normal access compatible mode, in
which the RD signal is negated and an RD assert wait is inserted each time a unit of data is read. When there is no RD
assert wait, the RD signal is negated only in the final transfer of the external bus access.
Writing 1 selects external data read continuous assertion mode, in which an RD assert wait is inserted and the RD signal
is continuously asserted during the wait.
15.3.5
CSn Wait Control Register 1 (CSnWCR1) (n = 0 to 7)
Address(es): BUS.CS0WCR1 4000 3004h, BUS.CS1WCR1 4000 3014h, BUS.CS2WCR1 4000 3024h, BUS.CS3WCR1 4000 3034h,
BUS.CS4WCR1 4000 3044h, BUS.CS5WCR1 4000 3054h, BUS.CS6WCR1 4000 3064h, BUS.CS7WCR1 4000 3074h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
—
—
—
0
0
0
0
0
1
1
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
0
0
0
0
0
b24
b23
b22
b21
—
—
—
1
0
0
0
0
0
1
1
1
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
0
0
0
0
0
CSRWAIT[4:0]
CSPRWAIT[2:0]
1
1
1
b20
b19
b18
b17
b16
CSWWAIT[4:0]
CSPWWAIT[2:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CSPWWAIT[2:0]
Page Write Cycle Wait Select*1
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b10 to b8
CSPRWAIT[2:0]
Page Read Cycle Wait Select*2
b10
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
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0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
b8
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
R/W
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Bit
Symbol
b20 to b16 CSWWAIT[4:0]
15. Buses
Bit name
Description
R/W
Normal Write Cycle Wait Select
b20
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
b16
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
...
1 1 1 0 1: Insert wait of 29 clock cycles
1 1 1 1 0: Insert wait of 30 clock cycles
1 1 1 1 1: Insert wait of 31 clock cycles.
b23 to b21 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28 to b24 CSRWAIT[4:0]
Normal Read Cycle Wait Select
b28
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
b24
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles.
...
1 1 1 0 1: Insert wait of 29 clock cycles
1 1 1 1 0: Insert wait of 30 clock cycles
1 1 1 1 1: Insert wait of 31 clock cycles.
b31 to b29 —
Note 1.
Note 2.
Reserved
These bits are read as 0. The write value should be 0.
R/W
The CSPWWAIT[2:0] value is only valid when the CSnMOD.PWENB bit is set to 1.
The CSPRWAIT[2:0] value is only valid when the CSnMOD.PRENB bit is set to 1.
Do not attempt to write to the CSnWCR1 register while the external bus is being accessed. Set each of these bits within a
range of the restrictions described in section 15.5.7, Constraints, (1) Constraints on using a separate bus interface or
section 15.5.7, Constraints, (2) Constraints on using address/data multiplexed bus interface, according to the bus
interface used.
CSPWWAIT[2:0] bits (Page Write Cycle Wait Select)
The CSPWWAIT[2:0] bits specify the number of wait cycles to be inserted into the second and subsequent accesses
during a page write cycle. The setting is enabled when the CSnMOD.PWENB bit is set to 1.
Note:
The settings must satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value, and CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value.
CSPRWAIT[2:0] bits (Page Read Cycle Wait Select)
The CSPRWAIT[2:0] bits specify the number of wait cycles to be inserted into the second and subsequent accesses
during a page read cycle. The setting is enabled when the CSnMOD.PRENB bit is set to 1.
Note:
The settings must satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSPRWAIT[2:0] value.
CSWWAIT[4:0] bits (Normal Write Cycle Wait Select)
The CSWWAIT[4:0] bits specify the number of wait cycles to be inserted into the first access during a normal write cycle
or page write cycle.
Note:
The settings must satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value, and CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
CSRWAIT[4:0] bits (Normal Read Cycle Wait Select)
The CSRWAIT[4:0] bits specify the number of wait cycles to be inserted into the first access during a normal read cycle
or page read cycle.
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Note:
15. Buses
The settings must satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSRWAIT[4:0] value.
15.3.6
CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 7)
Address(es): BUS.CS0WCR2 4000 3008h, BUS.CS1WCR2 4000 3018h, BUS.CS2WCR2 4000 3028h, BUS.CS3WCR2 4000 3038h,
BUS.CS4WCR2 4000 3048h, BUS.CS5WCR2 4000 3058h, BUS.CS6WCR2 4000 3068h, BUS.CS7WCR2 4000 3078h
b31
b30
—
b29
b28
CSON[2:0]
b27
b26
—
b25
b24
b23
WDON[2:0]
b22
—
b21
b20
WRON[2:0]
b19
b18
—
b17
b16
RDON[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
AWAIT[1:0]
—
0
0
Value after reset:
Value after reset:
0
0
0
WDOFF[2:0]
0
—
0
0
0
CSWOFF[2:0]
0
0
—
0
0
CSROFF[2:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CSROFF[2:0]
Read-Access CS Extension Cycle
Select
b2
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6 to b4
CSWOFF[2:0]
Write-Access CS Extension Cycle
Select
b6
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10 to b8
WDOFF[2:0]
Write Data Output Extension Cycle
Select
b10
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b13, b12
AWAIT[1:0]
Address Cycle Wait Select
b13 b12
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
b4
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
b8
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles.
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Bit
Symbol
Bit name
Description
R/W
b18 to b16
RDON[2:0]
RD Assert Wait Select
b18
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b16
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
b19
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b22 to b20
WRON[2:0]
WR Assert Wait Select
b22
R/W
b23
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b26 to b24
WDON[2:0]
Write Data Output Wait Select
b26
R/W
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b20
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
b24
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
b27
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b30 to b28
CSON[2:0]
CS Assert Wait Select
b30
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b28
0: Do not insert wait
1: Insert wait of 1 clock cycle
0: Insert wait of 2 clock cycles
1: Insert wait of 3 clock cycles
0: Insert wait of 4 clock cycles
1: Insert wait of 5 clock cycles
0: Insert wait of 6 clock cycles
1: Insert wait of 7 clock cycles.
R/W
Do not attempt to write to the CSnWCR2 register while the external bus is being accessed. Set each of these bits within a
range of the restrictions described in section 15.5.7, Constraints, (1) Constraints on using a separate bus interface. or
section 15.5.7, Constraints, (2) Constraints on using address/data multiplexed bus interface, according to the bus
interface used.
CSROFF[2:0] bits (Read-Access CS Extension Cycle Select)
The CSROFF[2:0] bits specify the number of wait cycles to be inserted during the period from the end of a wait cycle
(RD signal negated) until the CSn signal (n = 0 to 7) is negated in read access mode.
CSWOFF[2:0] bits (Write-Access CS Extension Cycle Select)
The CSWOFF[2:0] bits specify the number of wait cycles to be inserted during the period from the end of a wait cycle
(WRn signal (n = 0, 1) negated) until the CSn signal (n = 0 to 7) is negated in write access mode.
Note:
The settings must satisfy CSnWCR2.WDOFF[2:0] value ≤ CSnWCR2.CSWOFF[2:0] value.
WDOFF[2:0] bits (Write Data Output Extension Cycle Select)
The WDOFF[2:0] bits specify the number of wait cycles to be inserted during the period from the end of a wait cycle
(WRn signal (n = 0, 1) negated) until the write-data output is complete in write access mode.
Note:
The settings must satisfy CSnWCR2.WDOFF[2:0] value ≤ CSnWCR2.CSWOFF[2:0] value.
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15. Buses
AWAIT[1:0] bits (Address Cycle Wait Select)
The AWAIT[1:0] bits specify the number of wait cycles to be inserted into an address output cycle with the address/data
multiplexed I/O interface.
Note:
CSnWCR2.CSON[2:0] value ≤ CSnWCR2.AWAIT[1:0] value.
For read access, satisfy CSnWCR2.AWAIT[1:0] value + 2 ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSRWAIT[4:0] value.
For write access, satisfy CSnWCR2.AWAIT[1:0] value + 2 ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value and CSnWCR2.AWAIT[1:0] value + 2 ≤ CSnWCR2.WDON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
RDON[2:0] bits (RD Assert Wait Select)
The RDON[2:0] bits specify the number of wait cycles to be inserted before the RD signal is asserted.
Note:
For normal read access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSRWAIT[4:0] value.
For page read access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSPRWAIT[2:0] value.
When the address/data multiplexed I/O interface is selected, satisfy CSnWCR2.AWAIT[1:0] value + 2 ≤
CSnWCR2.RDON[2:0] value ≤ CSnWCR1.CSRWAIT[4:0] value.
WRON[2:0] bits (WR Assert Wait Select)
The WRON[2:0] bits specify the number of wait cycles to be inserted before the WRn signal (n = 0, 1) is asserted.
Note:
For normal write access, satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value, and CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
For page write access, satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value, and CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value.
When the address/data multiplexed I/O interface is selected, satisfy CSnWCR2.AWAIT[1:0] value + 2 ≤
CSnWCR2.WRON[2:0] value ≤ CSnWCR1.CSWWAIT[4:0] value.
WDON[2:0] bits (Write Data Output Wait Select)
The WDON[2:0] bits specify the number of wait cycles to be inserted before the write data is output.
Note:
For normal write access, satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
For page write access, satisfy 1 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value.
When the address/data multiplexed I/O interface is selected, satisfy CSnWCR2.AWAIT[1:0] value + 2 ≤
CSnWCR2.WDON[2:0] value ≤ CSnWCR1.CSWWAIT[4:0] value.
CSON[2:0] bits (CS Assert Wait Select)
The CSON[2:0] bits specify the number of wait cycles to be inserted before the CSn signal (n = 0 to 7) is asserted.
Note:
For normal read access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSRWAIT[4:0] value.
For page read access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.RDON[2:0] value ≤
CSnWCR1.CSPRWAIT[2:0] value.
For normal write access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSWWAIT[4:0] value.
For page write access, satisfy CSnWCR2.CSON[2:0] value ≤ CSnWCR2.WRON[2:0] value ≤
CSnWCR1.CSPWWAIT[2:0] value.
When the address/data multiplexed I/O interface is selected, satisfy CSnWCR2.CSON[2:0] value ≤
CSnWCR2.AWAIT[1:0] value.
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15.3.7
15. Buses
SDC Control Register (SDCCR)
Address(es): BUS.SDCCR 4000 3C00h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
BSIZE[1:0]
—
—
—
EXENB
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
EXENB
Operation Enable
0: Disable
1: Enable.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b5, b4
BSIZE[1:0]
SDRAM Bus Width Select
b5 b4
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0. R/W
R/W
0 0: 16-bit bus space
0 1: Setting prohibited
1 0: 8-bit bus space
1 1: Setting prohibited.
EXENB bit (Operation Enable)
The EXENB bit enables the operation of the SDRAM address space. On reset, operation is disabled (EXENB = 0).
Attempts to access disabled areas have no effect.
When CSC and SDRAMC are in use at the same time, BCLK and SDCLK must operate at the same frequency.
15.3.8
SDC Mode Register (SDCMOD)
Address(es): BUS.SDCMOD 4000 3C01h
b7
Value after reset:
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
EMOD
E
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
EMODE
Endian Mode
0: Endian order of SDRAM address space is the same
as the endian order of the operating mode
1: Endian order of SDRAM address space is not the
endian order of the operating mode.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Writing to this register is possible only once after release from reset. Operation is not guaranteed if more than one write
access is attempted.
EMODE bit (Endian Mode)
The EMODE bit specifies the endianness for the SDRAM address space. The Cortex®-M4 core is fixed at little-endian
order, so instruction code can only be allocated to external spaces with little-endian specified. If an area is specified as
big-endian, no instruction code can be allocated to it.
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15.3.9
15. Buses
SDRAM Self-Refresh Control Register (SDSELF)
Address(es): BUS.SDSELF 4000 3C10h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
SFEN
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SFEN
SDRAM Self-Refresh Enable
0: Disable
1: Enable.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Set the SDSELF register only when the conditions in Table 15.14 are satisfied. Otherwise, operation is not guaranteed.
SFEN bit (SDRAM Self-Refresh Enable)
The SFEN bit controls the self-refresh operation. Setting this bit to 1 initiates an auto-refresh cycle, after which selfrefresh begins. Clearing this bit to 0 ends the self-refresh, and auto-refresh resumes. When the bit is set to 1, the write
value takes effect when the self-refresh operation starts. When it is cleared to 0, the write value has already taken effect
when auto-refresh starts after the end of the self-refresh.
15.3.10
SDRAM Refresh Control Register (SDRFCR)
Address(es): BUS.SDRFCR 4000 3C14h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
REFW[3:0]
Value after reset:
0
0
0
b5
b4
b3
b2
b1
b0
0
0
0
0
1
RFC[11:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b11 to b0
RFC[11:0]
Auto-Refresh Request Interval Setting
b11
b15 to b12
REFW[3:0]
Auto-Refresh Cycle/Self-Refresh
Clearing Cycle Count Setting
b15
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
:
1 1 1 1 1 1 1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b12
0
R/W
b0
0 0 0 0 0: Setting prohibited
0 0 0 0 1: 2 cycles
0 0 0 1 0: 3 cycles
R/W
1 1 1 1 1: 4096 cycles.
0: 1 cycle
1: 2 cycles
0: 3 cycles
1: 4 cycles
0: 5 cycles
1: 6 cycles
0: 7 cycles
1: 8 cycles
0: 9 cycles
1: 10 cycles
0: 11 cycles
1: 12 cycles
0: 13 cycles
1: 14 cycles
0: 15 cycles
1: 16 cycles.
R/W
RFC[11:0] bits (Auto-Refresh Request Interval Setting)
The RFC[11:0] bits specify the auto-refresh request interval. They can be written to at any time, regardless of the state of
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15. Buses
the Auto-Refresh Operation Enable bit (RFEN) in SDRFEN. If auto-refresh is enabled, the write value takes effect after
the end of the auto-refresh cycles. The refresh counter uses SDCLK.
REFW[3:0] bits (Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting)
The REFW[3:0] bits specify the number of auto-refresh cycles and the number of self-refresh clearing cycles. They can
be written to at any time, regardless of the state of the Auto-Refresh Operation Enable bit (RFEN) in SDRFEN. If an
auto-refresh cycle is in progress, the value written to the bits while auto-refresh is enabled takes effect after the cycle
completes.
Note:
Auto-refresh requests are not accepted while the SDRAM is being accessed. This means they must sometimes
wait until the access completes for the auto-refresh interval to be extended. Set the RFC[11:0] bits to an autorefresh request interval value that meets the specifications of the SDRAM being used. Additionally, make sure to
set the auto-refresh request interval to a duration longer than the auto-refresh cycle. The auto-refresh interval
cannot be automatically adjusted when the frequency is changed during operation. In this case, perform a selfrefresh operation and set the auto-refresh interval to an appropriate value for the frequency again.
15.3.10.1
Auto-refresh request interval and RFC set value
The SDRAMC (SDRAM area controller) includes a 12-bit refresh counter that generates auto-refresh requests at fixed
intervals. Use the following equation to calculate the set value for the RFC[11:0] bits from the auto-refresh request
interval:
RFC = (Auto-refresh request interval / SDCLK cycle) - 1
Note:
Auto-refresh requests are not accepted while the SDRAM is being accessed. They must wait until the access
completes. However, the counter value is updated regardless of whether or not the request was accepted. If two
or more auto-refresh requests are generated while the SDRAM is being accessed, the second and subsequent
requests are ignored.
15.3.11
SDRAM Auto-Refresh Control Register (SDRFEN)
Address(es): BUS.SDRFEN 4000 3C16h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
RFEN
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RFEN
Auto-Refresh Operation Enable
0: Disable
1: Enable.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
RFEN bit (Auto-Refresh Operation Enable)
The RFEN bit enables auto-refresh operation. When auto-refresh is required, set the RFEN bit to 1 before SDRAM
access.
Clearing this bit to 0 while auto-refreshing is enabled causes RFEN to be cleared to 0 and auto-refresh operation to halt
after the end of the auto-refresh cycle.The interval at which refresh requests are generated is determined by the value in
the Auto-Refresh Request Interval Setting bits (RFC[11:0]) in the SDRAM Refresh Control Register (SDRFCR).
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15.3.12
15. Buses
SDRAM Initialization Sequence Control Register (SDICR)
Address(es): BUS.SDICR 4000 3C20h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
INIRQ
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
INIRQ
Initialization Sequence Start
0: Invalid
1: Start initialization sequence.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Writing to this register is possible only once after release from reset. Operation is not guaranteed if more than one write
access is attempted.
INIRQ bit (Initialization Sequence Start)
Setting the INIRQ bit to 1 starts the SDRAM initialization sequence and automatically sets the Initialization Status bit
(INIST) in the SDRAM Status Register (SDSR) to 1. The INIST bit clears automatically after the initialization sequence
ends. The value written to the INIRQ bit is not retained.
Note:
Set the INIRQ bit to start the SDRAM initialization sequence only when the conditions in Table 15.14 are
satisfied. Otherwise, operation is not guaranteed.
15.3.13
SDRAM Initialization Register (SDIR)
Address(es): BUS.SDIR 4000 3C24h
Value after reset:
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
b10
b9
b8
b7
b6
PRC[2:0]
0
0
b5
b4
b3
ARFC[3:0]
0
0
0
0
b2
b1
b0
ARFI[3:0]
1
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
ARFI[3:0]
Initialization Auto-Refresh Interval
b3
R/W
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0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: 3 cycles
1: 4 cycles
0: 5 cycles
1: 6 cycles
0: 7 cycles
1: 8 cycles
0: 9 cycles
1: 10 cycles
0: 11 cycles
1: 12 cycles
0: 13 cycles
1: 14 cycles
0: 15 cycles
1: 16 cycles
0: 17 cycles
1: 18 cycles.
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Bit
Symbol
Bit name
Description
R/W
b7 to b4
ARFC[3:0]
Initialization Auto-Refresh Count
b7
R/W
b10 to b8
PRC[2:0]
Initialization Precharge Cycle Count
b10
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b4
0: Setting prohibited
1: 1 time
0: 2 times
1: 3 times
0: 4 times
1: 5 times
0: 6 times
1: 7 times
0: 8 times
1: 9 times
0: 10 times
1: 11 times
0: 12 times
1: 13 times
0: 14 times
1: 15 times.
R/W
b8
0: 3 cycles
1: 4 cycles
0: 5 cycles
1: 6 cycles
0: 7 cycles
1: 8 cycles
0: 9 cycles
1: 10 cycles.
Writing to this register is possible only once after release from reset. Operation is not guaranteed if more than one write
access is attempted.
ARFI[3:0] bits (Initialization Auto-Refresh Interval)
The ARFI[3:0] bits specify the interval at which the auto-refresh commands are issued in the SDRAM initialization
sequence.
ARFC[3:0] bits (Initialization Auto-Refresh Count)
The ARFC[3:0] bits specify the number of times auto-refresh is to be performed in the SDRAM initialization sequence.
PRC[2:0] bits (Initialization Precharge Cycle Count)
The PRC[2:0] bits specify the number of precharged cycles in the SDRAM initialization sequence.
Note:
Implement settings that satisfy the specifications of the connected SDRAM before starting the initialization
sequence.
15.3.14
SDRAM Address Register (SDADR)
Address(es): BUS.SDADR 4000 3C40h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MXC[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
MXC[1:0]
Address Multiplex Select
b1 b0
R/W
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0 1: 9-bit shift
1 0: 10-bit shift
1 1: 11-bit shift.
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Bit
Symbol
Bit name
Description
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Set SDADR only when the conditions in Table 15.14 are satisfied. Otherwise, operation is not guaranteed.
MXC[1:0] bits (Address Multiplex Select)
The MXC[1:0] bits select the size of the shift towards the lower half of the row address in row address/column address
multiplexing. For details, see Table 15.17.
15.3.15
SDRAM Timing Register (SDTR)
Address(es): BUS.SDTR 4000 3C44h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
RCD[1:0]
WR
—
—
—
—
—
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
0
RP[2:0]
0
0
0
b18
b17
b16
RAS[2:0]
CL[2:0]
0
1
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CL[2:0]
SDRAMC Column Latency
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b8
WR
Write Recovery Interval
0: 1 cycle
1: 2 cycles.
R/W
b11 to b9
RP[2:0]
Row Precharge Interval
b11
R/W
b13, b12
RCD[1:0]
Row Column Latency
b13 b12
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b18 to b16
RAS[2:0]
Row Active Interval
b18
b31 to b19
—
Reserved
These bits are read as 0. The write value should be 0. R/W
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0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: Setting prohibited
1: 1 cycle
0: 2 cycles
1: 3 cycles
0: Setting prohibited
1: Setting prohibited
0: Setting prohibited
1: Setting prohibited.
b9
0: 1 cycle
1: 2 cycles
0: 3 cycles
1: 4 cycles
0: 5 cycles
1: 6 cycles
0: 7 cycles
1: 8 cycles.
0: 1 cycle
1: 2 cycles
0: 3 cycles
1: 4 cycles.
0
0
1
1
0
0
1
1
b16
0: 1 cycle
1: 2 cycles
0: 3 cycles
1: 4 cycles
0: 5 cycles
1: 6 cycles
0: 7 cycles
1: Setting prohibited.
R/W
R/W
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15. Buses
The SDTR register specifies the timing for read and write accesses to the SDRAM. For more information, see section
15.6.11.3, Timing register settings and access timing.
Set the SDTR register only when the conditions in Table 15.14 are satisfied. Otherwise, operation is not guaranteed.
Writing to this register is possible only once after release from reset. Operation is not guaranteed if more than one write
access is attempted.
CL[2:0] bits (SDRAMC Column Latency)
The CL[2:0] bits specify the column latency of the SDRAM controller. This setting only affects the latency setting on the
SDRAM controller side. To specify the column latency for externally connected SDRAM, use the SDRAM mode
register (SDMOD).
WR bit (Write Recovery Interval)
The WR bit specifies the interval that must elapse between the SDRAM write command (WRIT) and deactivation
(PALL).
RP[2:0] bits (Row Precharge Interval)
The RP[2:0] bits specify the minimum number of cycles that must elapse between the SDRAM deactivation command
(PALL) and the next valid command.
RAS[2:0] bits (Row Active Interval)
The RAS[2:0] bits specify the minimum interval that must elapse between the SDRAM row activation command
(ACTV) and deactivation (PALL). The value specified in these bits must be less than or equal to the sum of the row
column latency (RCD[1:0]) and column latency (CL[2:0]) settings.
15.3.16
SDRAM Mode Register (SDMOD)
Address(es): BUS.SDMOD 4000 3C48h
b15
b14
b13
b12
b11
b10
b9
b8
—
Value after reset:
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
MR[14:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b14 to b0
MR[14:0]
Mode Register Setting
Writing to these bits triggers a mode register set
command
R/W
b15
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
The SDMOD register specifies the value to be written to the SDRAM mode register. Writing to SDMOD causes a mode
register set command to be issued automatically to the SDRAM. Set SDMOD only when the conditions in Table 15.14
are satisfied. Otherwise, operation is not guaranteed.
Writing to this register is possible only once after release from reset. Operation is not guaranteed if more than one write
access is attempted.
MR[14:0] bits (Mode Register Setting)
Writing to the MR[14:0] bits causes a mode register set command to be issued to the SDRAM, and the setting in the
MR[14:0] bits is output to the lower bits of the address. For more information, see section 15.6.10, Setting the Mode
Register.
Note:
Note:
Note:
Set a burst length of 1 for the SDRAM. Operation is not guaranteed with any other burst length setting.
The SDRAM column latency must match the setting in the SDRAMC Column Latency setting (CL[2:0]) in the
SDRAM Timing Register (SDTR). Operation is not guaranteed if the latency settings do not agree.
Make sure the SRFST, INIST, and MRSST status bits in the SDRAM Status Register (SDSR) are all 0.
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15.3.17
15. Buses
SDRAM Status Register (SDSR)
Address(es): BUS.SDSR 4000 3C50h
Value after reset:
b7
b6
b5
—
—
—
0
0
0
b4
b3
SRFST INIST
0
0
b2
b1
b0
—
—
MRSST
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MRSST
Mode Register Setting Status
0: Mode register setting not in progress
1: Mode register setting in progress.
R
b2, b1
—
Reserved
These bits are read as 0
R
b3
INIST
Initialization Status
0: Initialization sequence not in progress
1: Initialization sequence in progress.
R
b4
SRFST
Self-Refresh Transition/Recovery Status
0: Transition/recovery not in progress
1: Transition/recovery in progress.
R
b7 to b5
—
Reserved
These bits are read as 0
R
MRSST bit (Mode Register Setting Status)
When set to 1, the MRSST bit indicates that SDRAM mode register setting is in progress.
INIST bit (Initialization Status)
When set to 1, the INIST bit indicates that the SDRAM initialization sequence is in progress.
SRFST bit (Self-Refresh Transition/Recovery Status)
When set to 1, the SRFST bit indicates that a transition to or recovery from a self-refresh operation is in progress for the
SDRAM. The in progress interval begins when the bits in Table 15.7 are written to and lasts until the associated
commands are issued.
Note:
Execution of a self-refresh, initialization sequence, or mode register setting can only be performed when all the
status bits are 0. Do not rewrite the registers and bits in Table 15.7 when any of the SRFST, INIST, or MRSST
status bits is set to 1.
Table 15.7
Registers and bits requiring status bit checking
Function
Register
Bits
Self-refresh
SDSELF
SFEN
Initialization sequence
SDICR
INIRQ
Mode register setting
SDMOD
MR[14:0]
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15.3.18
15. Buses
Master Bus Control Register (BUSMCNT)
Address(es): BUS.BUSMCNTM4I 4000 4000h, BUS.BUSMCNTM4D 4000 4004h, BUS.BUSMCNTSYS 4000 4008h,
BUS.BUSMCNTDMA 4000 400Ch, BUS.BUSMCNTEDM 4000 4010h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
IERES
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
b14 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b15
IERES
Ignore Error Responses
0: Report bus errors
1: Do not report bus errors.
Note:
R/W
R/W
Changing reserved bits from the initial value of 0 is prohibited. Operation during the change is not guaranteed.
Table 15.8 shows the registers associated with each bus type.
Table 15.8
Associations between bus types and registers
Bus type
Master Bus
Control Register
Slave Bus Control Register
Bus Error Address
Register
Bus Error Status
Register
ICode bus (CPU)
BUSMCNTM4I
-
BUS1ERRADD
BUS1ERRSTAT
DCode bus (CPU)
BUSMCNTM4D
-
BUS2ERRADD
BUS2ERRSTAT
System bus (CPU)
BUSMCNTSYS
-
BUS3ERRADD
BUS3ERRSTAT
DMA bus
BUSMCNTDMA
-
BUS4ERRADD
BUS4ERRSTAT
EDMAC bus
BUSMCNTEDM
-
BUS5ERRADD
BUS5ERRSTAT
Memory bus 1
-
BUSSCNTFLI
-
-
Memory bus 2
-
BUSSCNTRAMH
-
-
Memory bus 3
-
BUSSCNTMBIU
-
-
Memory bus 4
-
BUSSCNTRAM0
-
-
Memory bus 5
-
BUSSCNTRAM1
-
-
Internal peripheral bus 1,
3, 4, 5, 7
-
BUSSCNTPnB (n = 0, 2, 3, 4, 6)
-
-
Internal peripheral bus 9
-
BUSSCNTFBU
-
-
External bus (CS and
SDRAM areas)
-
BUSSCNTEXT
-
-
External bus (QSPI area)
-
BUSSCNTEXT2
-
-
IERES bit (Ignore Error Responses)
The IERES bit, when set, disables the AHB-Lite protocol error response.
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15.3.19
15. Buses
Slave Bus Control Register (BUSSCNT)
Address(es): BUS.BUSSCNTFLI 4000 4100h, BUS.BUSSCNTRAMH 4000 4104h, BUS.BUSSCNTMBIU 4000 4108h,
BUS.BUSSCNTRAM0 4000 410Ch, BUS.BUSSCNTRAM1 4000 4110h, BUS.BUSSCNTP0B 4000 4114h,
BUS.BUSSCNTP2B 4000 4118h, BUS.BUSSCNTP3B 4000 411Ch, BUS.BUSSCNTP4B 4000 4120h,
BUS.BUSSCNTP6B 4000 4128h, BUS.BUSSCNTFBU 4000 4130h, BUS.BUSSCNTEXT 4000 4134h,
BUS.BUSSCNTEXT2 4000 4138h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
EWRE
S
—
—
0
0
0
0
0
0
0
0
0
0
Value after reset:
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
ARBMET[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b5, b4
ARBMET[1:0]
Arbitration Method
R/W
Specifies the group priorities.
b5 b4
0 0: Fixed priority
0 1: Round-robin
1 0: Setting prohibited
1 1: Setting prohibited.
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b8
EWRES
Early Write Response
0: Disable early write response
1: Enable early write response.
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note:
R/W
Changing reserved bits from the initial value of 0 is prohibited. Operation during the change is not guaranteed.
Table 15.8 lists the registers associated with each bus type.
ARBMET[1:0] bits (Arbitration Method)
The ARBMET[1:0] bits specify the arbitration protocol, with priority defined for all bus masters. For fixed priority, see
Table 15.9. For round-robin, see Table 15.10.
EWRES bit (Early Write Response)
The EWRES bit indicates whether the next write request is accepted before the response for the current write transaction
occurs. When the value is 1, the next write request is accepted and high-speed transfer is possible, but AHB-Lite error
responses are not detected. Bus errors are returned to the requesting master IP using the error response protocol for AHBLite. For details on errors that occur on each bus, see section 15.7, Bus Error Monitoring Section. Only use the
BUSSCNTMBIU, BUSSCNTP0B, and BUSSCNTEXT registers.
Table 15.9
Bus priorities with fixed-priority arbitration (ARBMET[1:0] = 00b)
Slave Bus Control Register
Slave interface
Priority order
BUSSCNTFLI
Memory bus 1
Memory bus 3 > DCode bus (CPU) > ICode bus (CPU)
BUSSCNTRAMH
Memory bus 2
Memory bus 3 > DCode bus (CPU) > ICode bus (CPU)
BUSSCNTMBIU
Memory bus 3
ETHER bus > DMA bus
BUSSCNTRAM0
Memory bus 4
ETHER bus > DMA bus > system bus (CPU)
BUSSCNTRAM1
Memory bus 5
ETHER bus > DMA bus > system bus (CPU)
BUSSCNTPnB (n = 0, 2, 3, 4, 6)
Internal peripheral bus 1, 3, 4, 5, 7
DMA bus > system bus (CPU)
BUSSCNTFBU
Internal peripheral bus 9
ETHER bus > DMA bus > system bus (CPU)
BUSSCNTEXT
External bus (CS and SDRAM
areas)
ETHER bus > DMA bus > system bus (CPU)
BUSSCNTEXT2
External bus (QSPI area)
ETHER bus > DMA bus > system bus (CPU)
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Table 15.10
15. Buses
Bus priorities with round-robin priority arbitration (ARBMET[1:0] = 01b)
Slave Bus Control Register
Slave interface
Priority order*1
BUSSCNTFLI
Memory bus 1
Memory bus 3 DCode bus (CPU) ICode bus
(CPU)
BUSSCNTRAMH
Memory bus 2
Memory bus 3 DCode bus (CPU) ICode bus
(CPU)
BUSSCNTMBIU
Memory bus 3
ETHER bus DMA bus
BUSSCNTRAM0
Memory bus 4
ETHER bus DMA bus system bus (CPU)
BUSSCNTRAM1
Memory bus 5
ETHER bus DMA bus system bus (CPU)
BUSSCNTPnB (n = 0, 2, 3, 4, 6)
Internal peripheral bus 1, 3, 4, 5, 7
DMA bus system bus (CPU)
BUSSCNTFBU
Internal peripheral bus 9
ETHER bus DMA bus system bus (CPU)
BUSSCNTEXT
External bus (CS and SDRAM
areas)
ETHER bus DMA bus system bus (CPU)
BUSSCNTEXT2
External bus (QSPI area)
ETHER bus DMA bus system bus (CPU)
Note 1.
Round-robin priority is denoted by .
15.3.20
Bus Error Address Register (BUSnERRADD) (n = 1 to 5)
Address(es): BUS.BUS1ERRADD 4000 4800h, BUS.BUS2ERRADD 4000 4810h, BUS.BUS3ERRADD 4000 4820h,
BUS.BUS4ERRADD 4000 4830h, BUS.BUS5ERRADD 4000 4840h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BERAD[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
BERAD[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
BERAD[31:0]
Bus Error Address
When a bus error occurs, these bits store the error
address
R
Note:
This register is cleared only by reset other than MPU related reset. For more information, see section 6, Resets, and section 16,
Memory Protection Unit (MPU).
Table 15.8 lists the registers associated with each bus type.
BERAD[31:0] bits (Bus Error Address)
When a bus error occurs, the BERAD[31:0] bits store the access address. For more information, see the
BUSnERRSTAT.ERRSTAT bit description and section 15.7, Bus Error Monitoring Section.
A value of BUSnERRADD.BERAD[31:0] (n = 1 to 5) is only valid when BUSnERRSTAT.ERRSTAT (n = 1 to 5) is set
to 1.
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15.3.21
15. Buses
Bus Error Status Register (BUSnERRSTAT) (n = 1 to 5)
Address(es): BUS.BUS1ERRSTAT 4000 4804h, BUS.BUS2ERRSTAT 4000 4814h, BUS.BUS3ERRSTAT 4000 4824h,
BUS.BUS4ERRSTAT 4000 4834h, BUS.BUS5ERRSTAT 4000 4844h
b7
b6
b5
b4
b3
ERRST
AT
—
—
—
—
0
0
0
0
0
Value after reset:
b2
b1
b0
—
—
ACCST
AT
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
ACCSTAT
Error Access Status
Access status when the error occurred:
1: Write access
0: Read access.
R
b6 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
ERRSTAT
Bus Error Status
0: No bus error occurred
1: Bus error occurred.
Note:
R
This register is cleared only by reset other than MPU related reset. For more information, see section 6, Resets, and section 16,
Memory Protection Unit (MPU).
Table 15.8 lists the registers associated with each bus type.
ACCSTAT bit (Error Access Status)
The ACCSTAT bit indicates the access status, write access or read access, when an error occurs on the associated bus.
For more information, see the BUSnERRSTAT.ERRSTAT bit description and section 15.7, Bus Error Monitoring
Section.
The value is only valid when BUSnERRSTAT.ERRSTAT (n = 1 to 5) is set to 1.
ERRSTAT bit (Bus Error Status)
The ERRSTAT bit indicates whether a bus error occurred. When an error occurs on the associated bus, the access address
and status of write or read access are stored. BUSnERRSTATn.ERRSTAT (n = 1 to 5) is set to 1.
The following types of errors can occur on each bus:
Illegal address access
Bus master MPU error
Bus slave MPU error
Time out.
When detecting bus master MPU errors or bus slave MPU errors, and reset is selected in the respective OAD bit,
BUSnERRSTAT.ERRSTAT (n = 1 to 5) is not set to 1 if the bus access that caused the MPU error completes later than
the internal reset signal being generated, which may occur depending on the wait setting.
When detecting bus master MPU errors or bus slave MPU errors, and NMI is selected in the respective OAD bit,
BUSnERRSTAT.ERRSTAT (n = 1 to 5) is set to 1 when the bus access that caused the MPU error completes.
For more information on errors that occur on each bus, see section 15.7, Bus Error Monitoring Section, and section 16,
Memory Protection Unit (MPU).
15.4
Endianness and Data Alignment
The external bus has a data alignment function to control which byte of the data bus (D15 to D08, D07 to D00) is used
when accessing the external address space (the CS and SDRAM areas). Alignment is based on the bus specifications of
the area to be accessed (8-bit or 16-bit bus space), the data size, and the endian order.
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15. Buses
Data Alignment Control for the CS Areas
16-bit bus space
When a 16-bit bus space is selected in the BSIZE[1:0] bits in CSnCR, address buses A20 to A01 are enabled to output
address signals in 16-bit units, and the address bus A00 is disabled (always outputs low).
When byte strobe mode is selected (WRMOD = 0 in CSnMOD), the WR0 and WR1 pins are enabled. The BC0 and BC1
pins are not used.
When single-write strobe mode is selected (WRMOD = 1 in CSnMOD), only the WR0 pin is enabled, and it always
outputs low during write access, regardless of the data size. The WR1 pin is invalid (always outputs high). The valid byte
position is indicated by the BC0 and BC1 pins.
The valid positions of control signals and data external to the chip differ depending on the endian order. See Figure 15.3
and Figure 15.4.
Page access can occur for accesses to data in 32-bit units. Page access can only occur when an access does not extend
over a 32-bit boundary and causes no change in the BC0 and BC1 signals. The situations in which page access occurs are
indicated by the letter (p) in Figure 15.3 and Figure 15.4.
WR1/BC1
WR0/BC0
RD
Data size
8 bits
16 bits
32 bits
Accessed
address
Number of
accesses
Bus cycle
Unit of
data
Address
4n
One
First
8 bits
4n
4n+1
One
First
8 bits
4n
4n+2
One
First
8 bits
4n+2
4n+3
One
First
8 bits
4n+2
4n
One
First
16 bits
4n+2
One
First
First
Second
4n
Two
D15
Data bus
D08 D07
D00
7
0
7
0
7
0
4n
15
8 7
0
16 bits
4n+2
15
8 7
0
16 bits
4n
15
8 7
0
16 bits
4n+2
31
24 23
7
(p)
0
16
(p): Page access (only when page access is enabled in the PRENB and PWENB bits in CSnMOD).
Figure 15.3
Data alignment in 16-bit bus space with little-endian order for CS areas
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15. Buses
WR1/BC1
WR0/BC0
RD
Data size
8 bits
16 bits
32 bits
Accessed
address
Number of
accesses
Bus cycle
Unit of
data
Address
4n
One
First
8 bits
4n
4n+1
One
First
8 bits
4n
4n+2
One
First
8 bits
4n+2
4n+3
One
First
8 bits
4n+2
4n
One
First
16 bits
4n
15
8 7
0
4n+2
One
First
16 bits
4n+2
15
8 7
0
4n
Two
First
16 bits
4n
31
24 23
16
Second
16 bits
4n+2
15
87
0
D15
7
7
(p)
Data bus
D08 D07
D00
0
7
0
7
0
0
(p): Page access (only when page access is enabled in the PRENB and PWENB bits in CSnMOD).
Figure 15.4
(2)
Data alignment in 16-bit bus space with big-endian order for CS areas
8-bit bus space
When an 8-bit bus space is selected in the BSIZE[1:0] bits in CSnCR, the address buses A20 to A00 are enabled to
output address signals in byte units.
In 8-bit bus space, only the WR0 pin is valid, regardless of the write access mode, and it always outputs low during write
access. The WR1 and BC0 pins are not used.
The valid positions of data external to the chip are D07 to D00, and WR0 is used as the control signal, regardless of the
endian mode. See Figure 15.5 and Figure 15.6.
Page access can occur for accesses to data in 16-bit or 32-bit units. Page access can only occur when an access does not
extend over a 32-bit boundary. The situations in which page access occurs are indicated by the letter (p) in Figure 15.5
and Figure 15.6.
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WR1/BC1
WR0/BC0
RD
Data size
8 bits
Accessed
address
Number of
accesses
Unit of
data
Address
D15
Data bus
D08 D07
D00
4n
One
First
8 bits
4n
7
0
4n+1
One
First
8 bits
4n+1
7
0
4n+2
One
First
8 bits
4n+2
7
0
4n+3
One
First
8 bits
4n+3
7
0
4n
Two
4n+2
Two
16 bits
32 bits
Bus cycle
4n
Four
First
8 bits
4n
Second
8 bits
4n+1
First
8 bits
4n+2
Second
8 bits
4n+3
7
0
15
8
7
0
(p)
15
8
(p)
First
8 bits
4n
7
0
Second
8 bits
4n+1
(p)
15
8
Third
8 bits
4n+2
(p)
23
16
Fourth
8 bits
4n+3
(p)
31
24
(p): Page access (only when page access is enabled
in the PRENB and PWENB bits in CSnMOD)
Figure 15.5
Data alignment in 8-bit bus space with little-endian order for CS areas
WR1/BC1
WR0/BC0
RD
Data size
8 bits
Accessed
address
Number of
accesses
Bus cycle
Unit of
data
Address
4n
One
First
8 bits
4n
7
0
4n+1
One
First
8 bits
4n+1
7
0
4n+2
One
First
8 bits
4n+2
7
0
4n+3
One
4n
Two
16 bits
4n+2
32 bits
4n
Two
Four
D15
Data bus
D08 D07
D00
First
8 bits
4n+3
7
0
First
8 bits
4n
15
8
Second
8 bits
4n+1
First
8 bits
4n+2
Second
8 bits
4n+3
First
8 bits
4n
Second
8 bits
4n+1
Third
8 bits
Fourth
8 bits
(p)
(p)
7
0
15
8
7
0
31
24
(p)
23
16
4n+2
(p)
15
8
4n+3
(p)
7
0
(p): Page access (only when page access is enabled
in the PRENB and PWENB bits in CSnMOD)
Figure 15.6
Data alignment in 8-bit bus space with big-endian order for CS areas
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15. Buses
Data Alignment Control for the SDRAM Area
16-bit bus space
When a 16-bit bus space is selected in the BSIZE[1:0] bits in SDCCR, address buses A26 to A01 are enabled to output
address signals in 16-bit units, and the address bus A00 is disabled (always outputs low). The valid byte position is
indicated by the DQM0 and DQM1 signals.
External data is accessed using the DQ15 to DQ08 and DQ07 to DQ00 pins and DQM0 and DQM1 control signals. Data
can be accessed in either 8-bit or 16-bit units at a time.
The valid positions of control signals and data external to the chip differ depending on the endian order. See Figure 15.7
and Figure 15.8.
DQM1
DQM0
WE
Data size
8 bits
16 bit
32 bits
Figure 15.7
Accessed
address
Number of
accesses
Bus cycle
4n
One
First
8 bits
4n
4n+1
One
First
8 bits
4n
4n+2
One
First
8 bits
4n+2
4n+3
One
First
8 bits
4n+2
4n
One
First
16 bits
4n+2
One
First
16 bits
4n
Two
Unit of
data
Address
Data bus
DQ08 DQ07
DQ15
DQ00
7
0
7
0
7
0
4n
15
8 7
0
4n+2
15
8 7
0
8 7
0
24 23
7
First
16 bits
4n
15
Second
16 bits
4n+2
31
0
16
Data alignment in 16-bit bus space with little-endian order for SDRAM area
DQM1
DQM0
WE
Data size
8 bits
16 bits
32 bits
Figure 15.8
(2)
Accessed
address
Number of
accesses
Bus cycle
Unit of
data
Address
4n
One
First
8 bits
4n
4n+1
One
First
8 bits
4n
4n+2
One
First
8 bits
4n+2
4n+3
One
First
8 bits
4n+2
DQ15
Data bus
DQ08 DQ07
7
7
DQ00
0
7
0
7
0
0
4n
One
First
16 bits
4n
15
8 7
0
4n+2
One
First
16 bits
4n+2
15
8 7
0
4n
Two
First
16 bits
4n
31
24 23
4n+2
15
87
Second
16 bits
16
0
Data alignment in 16-bit bus space with big-endian order for SDRAM area
8-bit bus space
When an 8-bit width is selected in the BSIZE[1:0] bits in SDCCR, address buses A26 to A00 are enabled to output
address signals in 8-bit units.
External data is accessed using the DQ07 to DQ00 pins and DQM0 control signal. 8-bit data is accessed in single 8-bit
accesses, 16-bit data with two 8-bit accesses, and 32-bit data with four 8-bit accesses.
The valid positions of control signals and data external to the chip differ depending on the endian order. See Figure 15.9
and Figure 15.10.
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DQM1
DQM0
WE
Data size
8 bits
Accessed
address
Number of
accesses
Figure 15.9
Unit of
data
Address
DQ15
Data bus
DQ08 DQ07
DQ00
4n
One
First
8 bits
4n
7
0
4n+1
One
First
8 bits
4n+1
7
0
4n+2
One
First
8 bits
4n+2
7
0
4n+3
One
First
8 bits
4n+3
7
0
4n
Two
4n+2
Two
16 bits
32 bits
Bus cycle
4n
Four
First
8 bits
4n
7
0
Second
8 bits
4n+1
15
8
First
8 bits
4n+2
7
0
Second
8 bits
4n+3
15
8
First
8 bits
4n
7
0
Second
8 bits
4n+1
15
8
Third
8 bits
4n+2
23
16
Fourth
8 bits
4n+3
31
24
Data alignment in 8-bit bus space with little-endian order for SDRAM area
DQM1
DQM0
WE
Data size
8 bits
Accessed
address
Number of
accesses
Figure 15.10
15.5
15.5.1
Address
DQ15
Data bus
DQ08 DQ07
DQ00
4n
One
First
8 bits
4n
7
0
4n+1
One
First
8 bits
4n+1
7
0
4n+2
One
First
8 bits
4n+2
7
0
4n+3
One
0
4n
Two
4n+2
Two
16 bits
32 bits
Bus cycle
Unit of
data
4n
Four
First
8 bits
4n+3
7
First
8 bits
4n
15
8
0
Second
8 bits
4n+1
7
First
8 bits
4n+2
15
8
0
Second
8 bits
4n+3
7
First
8 bits
4n
31
24
16
Second
8 bits
4n+1
23
Third
8 bits
4n+2
15
8
Fourth
8 bits
4n+3
7
0
Data alignment in 8-bit bus space with big-endian order for SDRAM area
Operation of CS Area Controller
Separate Bus
This section describes the periods shown in the timing diagrams. The CS area controller (CSC) operates in
synchronization with the external bus clock, BCLK. Operation cycles, such as wait cycles, specified in the CSC register,
are counted on BCLK. In the following description, the frequencies of BCLK and EBCLK pin output are the same,
unless otherwise noted. Access through the external bus starts at the same point as the output of a rising edge on the
EBCLK pin. However, if the external bus clock, BCLK, and the output on the EBCLK pin are at different frequencies,
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15. Buses
the wait settings can cause the start of access for the second and subsequent rounds to coincide with the falling edge of
the output on the EBCLK pin. See Figure 15.16 to Figure 15.20. If recovery cycles are inserted for bus access, the setting
for the number of recovery cycles can also cause the start of access for the second and subsequent rounds to coincide
with the falling edge of the output on the EBCLK pin. See Figure 15.38.
(a)
Tw1 to Twn (clock cycles for waiting for a normal read cycle or normal write cycle)
The period from Tw1 to Twn is the number of clock cycles from the start of access through the external bus clock to 1
cycle before the strobe signal is valid. The number of cycles is selectable from 0 to 31. Within this period, the timing of
CSn, RD, and WRn assertion (driving the signals low) is determined by the respective wait settings. The wait periods are
controlled by the CS Assert Wait Select bits (CSON), the RD Assert Wait Select bits (RDON), the WR Assert Wait
Select bits (WRON), and the Write-Data Output Wait Select bits (WDON) in CSn Wait Control Register 2 (CSnWCR2).
The number of clock cycles for each of these wait periods is selectable as a value from 0 to 7, counted from the start of
external bus access. The selectable number of cycles is also within the overall number of clock cycles required for
waiting to read or write.
(b)
Tend (clock cycle where the strobe signal is valid)
Tend is the next clock cycle after completion of the wait period for a normal cycle of read or write, or for a cycle of page
reading or page writing. If the wait select bit for these cycles is 0, bus access starts on the clock cycle where the strobe
signal is valid. The RD and WRn signals are negated in the next clock cycle. For a read access, the clock cycle where the
strobe signal is valid is where the data to be read is sampled. If an external wait is enabled, the wait signal is sampled on
the cycle where the strobe signal is valid. The bus cycle is extended if the wait signal is low. The bus cycle completes in
the next clock cycle if the wait signal is high. Tend indicates the cycle where sampling of the wait signal starts.
After the first cycle where the strobe signal is valid during page access, second and subsequent page access operations
(see section (e), Tpw1 to Tpwn (page read cycle wait or page write cycle wait)) start in the next cycle, except during
write access with a setting other than 0 for write-data output extension clock cycles (see section (d), Tdw1 to Tdwn
(clock cycles for write-data output extension)). If the setting for the RD or WR assertion wait is any value other than 0,
the RD and WRn signals are negated in the next clock cycle. If the setting is 0, assertion continues. Additionally, the CSn
signal continues to be asserted rather than negated.
(c)
Tn1 to Tnm (clock cycles for CS extension)
For normal access, Tn1 to Tnm represent the clock cycles of the period following the cycle where the strobe signal is
valid (Tend) up to negation of the CSn signal. For read or write access, the negation timing can be controlled by the readaccess CS Extension Cycle Select bits (CSROFF) and the write-access CS Extension Cycle Select bits (CSWOFF) in the
CSn Wait Control Register 2 (CSnWCR2). The number of cycles is counted from the cycle following the cycle where the
strobe signal is valid.
For page access, Tn1 to Tnm represent the clock cycles of the period following the last cycle where the strobe signal is
valid up to negation of the CSn signal.
For write access, setting the Write Data Output Extension Cycle Select bits (WDOFF) controls extension of the period
where the address and output data is valid.
(d)
Tdw1 to Tdwn (clock cycles for write-data output extension)
For write access, if the wait setting for the write-data output extension is any value other than 0, the specified clock
cycles are inserted from the cycle following the cycle where the strobe signal is valid (Tend).
For normal access, this period is inserted within the clock cycle period for CS extension (Tn1 to Tnm).
For page access, this period is inserted within the clock cycle period where the strobe signal is valid and subsequent page
accesses, or within the clock cycle period for the CS extension (Tn1 to Tnm). Valid address and data output are extended
over this period, and the WRn signal is negated.
(e)
Tpw1 to Tpwn (page read cycle wait or page write cycle wait)
For the second and subsequent bus cycles during page access, the values for a page read cycle wait or page write cycle
wait are used instead of the settings for a normal read or write cycle wait. The settings in the WR Assert Wait Select bits
become enabled in the same way as for the first access. The RD assertion control operation depends on the page read
access mode setting (the PRMOD bit in CSnMOD) as follows:
CSnMOD.PRMOD = 0: A wait for RD assertion is inserted in the same way as for the first access, and the RD
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signal is negated
CSnMOD.PRMOD = 1: Although a wait for RD assertion is inserted in the same way as for normal-access
compatibility mode, the RD signal continues to be asserted over this period.
(f)
Tr1 to Trn (recovery cycles)
Recovery cycles can be inserted from the point where a bus cycle is complete (CSn signal negation). The number of
recovery cycles can be controlled by setting the Read Recovery (RRCV) or Write Recovery (WRCV) bits in the CSn
Recovery Cycle Register (CSnREC). Both numbers of recovery cycles are counted from the end of a bus cycle (CSn
negation) and can be selected from 0 to 15 cycles. For more information, see section 15.5.4, Insertion of Recovery
Cycles.
(1)
Normal access
When the PRENB and PWENB bits in CSnMOD are set to 0 to disable page read and page write access, all bus accesses
take the form of normal read and write operations. Even when these bits are set to 1 to enable page read and page write
access, bus access other than page access takes the form of normal read and write operations. Figure 15.11 to Figure
15.13 show the normal access operations.
Next bus access can be started*1
Tw1
External bus clock
(BCLK)
Tw2
...
Twn
Tn1
...
Tnm
Read-access CS extension cycle (CSROFF)
Normal read cycle wait (CSRWAIT)
Address
(A20 to A00)
Tend
A
CS assert wait (CSON)
Chip select
(CSn)
Byte control
(BCm)
RD assert wait (RDON)
Data read
(RD)
D
Data bus
(D15 to D00)
Note 1: When CSnWCR2.CSROFF[2:0] = 000b, the next round of bus access can start 1 cycle later.
Figure 15.11
: Indicates sampling point
Bus timing for normal read operation (n = 0 to 7, m = 0, 1)
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Next bus access can be started
Tw1
External bus clock
(BCLK)
Tw2
...
Twn
Tn1
...
Tnm
Write-access CS extension cycle (CSWOFF)
Normal write cycle wait (CSWWAIT)
Address
(A20 to A00)
Tend
A
CS assert wait (CSON)
Chip select
(CSn)
Byte control
(BCm)
WR assert wait (WRON)
Data write
(WR)
Write data output wait (WDON)
Write data output extension cycle (WDOFF)
Data bus
(D15 to D00)
Figure 15.12
D
Bus timing for normal write operation in single-write strobe mode (n = 0 to 7, m = 0, 1)
Tw1
Tw2
Tend
Tn1
Tw1
Tw2
Tend
Tn1
External bus clock
(BCLK)
Address
(A20 to A00)
A1
A2
Normal write cycle wait (CSWWAIT): 2
Normal read cycle wait (CSRWAIT): 2
Chip select/byte
control
(CSn/BCm)
Read-access CS extension
cycle (CSROFF): 1
CS assert wait (CSON): 0
Write-access CS extension cycle
(CSWOFF): 1
RD assert wait (RDON): 1
Data read
(RD)
Data write
(WR)
WR assert wait (WRON): 1
Write data output extension cycle (WDOFF): 1
Write data output wait (WDON): 1
Data bus
(D15 to D00)
D1
D2
: Indicates sampling point
Figure 15.13
Example of normal access operation for read and write (n = 0 to 7, m = 0, 1)
When two or more rounds of external bus access are required in response to a single request for transfer from a bus
master, normal access operations are repeated. See section (a), Tw1 to Twn (clock cycles for waiting for a normal read
cycle or normal write cycle) to section (d), Tdw1 to Tdwn (clock cycles for write-data output extension). Figure 15.14
and Figure 15.15 show examples of operations when two rounds of bus access are generated in response to a single
transfer request. If the recovery cycle insertion condition is satisfied, recovery cycles (section (f), Tr1 to Trn (recovery
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15. Buses
cycles)) are also inserted in the second and subsequent external bus accesses. See Figure 15.36.
The values in the wait control registers shown in the figures are example settings. In your application, set the registers
appropriately for the specifications of connected devices.
Tw1
Tw2
Tend
Tn1
Tw1
Tw2
Tend
Tn1
External bus clock
(BCLK)
Normal read cycle wait (CSRWAIT): 2
Address
(A20 to A00)
A2
A1
Read-access CS extension
cycle (CSROFF): 1
Chip select
(CSn)
CSRWAIT: 2
CSROFF: 1
Byte control
(BCm)
RD assert wait (RDON): 1
RDON: 1
Data read
(RD)
Data bus
(D15 to D00)
D2
D1
CS assert wait (CSON): 0
: Indicates sampling point
Figure 15.14
Example of normal read operation when two rounds of bus access are generated in response to a
single transfer request (n = 0 to 7, m = 0, 1)
Tw1
Tw2
Tend
Tn1
Tw1
Tw2
Tend
Tn1
External bus clock
(BCLK)
CSWWAIT: 2
Normal write cycle wait (CSWWAIT): 2
Address
(A20 to A00)
A1
A2
Write-access CS extension cycle (CSWOFF): 1
Chip select
(CSn)
CSWOFF: 1
Byte control
(BCm)
WR assert wait (WRON): 1
WRON: 1
Write data output wait (WDON): 1
WDON: 1
Data write
(WR)
Data bus
(D15 to D00)
D1
WDOFF: 1
D2
Write data output extension cycle (WDOFF): 1
CS assert wait (CSON): 0
Figure 15.15
Example of normal write operation when two rounds of bus access are generated in response to
a single transfer request in single-write strobe mode (n = 0 to 7, m = 0, 1)
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Figure 15.16 to Figure 15.20 show examples of normal accesses made when BCLK/2 is selected as the frequency
division in the EBCLK Pin Output Select bit.
Tw1
Tw2
Tend
Tn1
Tn2
Tw1
Tw2
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A20 to A00)
Chip select
(CSn)
A1
Normal read cycle wait
(CSRWAIT): 2
A2
Read-access CS extension Normal write cycle wait Write-access CS extension cycle
(CSWOFF): 1
(CSWWAIT): 2
cycle (CSROFF): 2
Byte control
(BCm)
RD assert wait (RDON): 1
Data read
(RD)
Data write
(WR)
WR assert wait (WRON): 1
Write data output extension cycle
(WDOFF): 1
Write data output wait
(WDON): 1
Data bus
(D15 to D00)
D1
D2
CS assert wait (CSON): 0
: Indicates sampling point
Figure 15.16
Example of normal access when BCLK/2 is selected in the EBCLK Pin Output Select bit (n = 0 to
7, m = 0, 1)
Tw1
Tw2
Tw3
Tend
Tn1
Tw1
Tw2
Tw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A20 to A00)
A1
Normal read cycle wait (CSRWAIT): 3
A2
Read-access CS extension
cycle (CSROFF): 1
CSRWAIT: 3
CSROFF: 1
Chip select
(CSn)
CS assert wait (CSON): 1
CSON: 1
Byte control
(BCm)
RD assert wait (RDON): 2
RDON: 2
Data
read
(RD)
Data bus
(D15 to D00)
D1
D2
: Indicates sampling point
Figure 15.17
Example of normal read operation when BCLK/2 is selected in the EBCLK Pin Output Select bit (n
= 0 to 7, m = 0, 1)
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Tw1
Tw2
Tw3
Tend
Tn1
Tw1
Tw2
Tw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A20 to A00)
A1
Normal write cycle wait (CSWWAIT): 3
Chip select
(CSn)
A2
Write-access CS extension
cycle (CSWOFF): 1
CS assert wait (CSON): 1
CSWWAIT: 3
CSWOFF : 1
CSON: 1
Byte control
(BCm)
WR assert wait (WRON): 2
WRON: 2
Data write
(WR)
Write data output extension
cycle (WDOFF): 1
Write data output wait (WDON): 2
Data bus
(D15 to D00)
Figure 15.18
WDOFF: 1
WDON: 2
D2
D1
Example of normal write operation when BCLK/2 is selected in the EBCLK Pin Output Select bit
(n = 0 to 7, m = 0, 1)
Tw1
Tw2
Tw3
Tend
Tn1
Tw1
Tw2
Tw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A20 to A00)
A1
Normal read cycle wait
(CSRWAIT): 3
A2
Read-access CS
extension cycle
(CSROFF): 1
CSRWAIT: 3
CSROFF: 1
Chip select
(CSn)
CSON: 1
CS assert wait (CSON): 1
Byte control
(BCm)
RD assert wait (RDON): 2
RDON: 2
Data read
(RD)
Data bus
(D15 to D00)
D1
D2
: Indicates sampling point
Figure 15.19
Example of normal read operation when BCLK/2 is selected in the EBCLK Pin Output Select bit
and two rounds of bus access are generated in response to a single transfer request (n = 0 to 7, m
= 0, 1)
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Tw1
Tw2
Tw3
Tend
Tn1
Tw1
Tw2
Tw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A20 to A00)
A2
A1
Write-access CS
Normal write cycle wait extension cycle
(CSWWAIT): 3 (CSWOFF): 1
CSWWAIT: 3
CSWOFF: 1
Chip select
(CSn)
CS assert wait (CSON): 1
CSON: 1
Byte control
(BCm)
WR assert wait (WRON): 2
WRON: 2
Data write
(WR)
Write data output wait (WDON): 2
Data bus
(D15 to D00)
Figure 15.20
(2)
Write data output extension
WDON: 2
cycle (WDOFF): 1
D1
WDOFF: 1
D2
Example of normal write operation when BCLK/2 is selected in the EBCLK Pin Output Select bit
and two rounds of bus access are generated in response to a single transfer request (n = 0 to 7, m
= 0, 1)
Page access
When the PRENB and PWENB bits in CSnMOD are set to 1 to enable page read and page write access, the bus access
for page access operations becomes page reading and writing. Page access can only occur when two or more rounds of
external bus access are required for a single transfer request from the bus master. However, normal access is made when
split accesses are not aligned or access extends across the 32-bit boundary. See Figure 15.3 to Figure 15.6 for the
conditions under which page access occurs.
Figure 15.21 and Figure 15.22 show examples of page access operations.
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Next bus access can be started
Tw1
...
Tw2
Twn
Tend
Tpw1
...
Tpwn
Tn1
Tend
Tnm
External bus clock
(BCLK)
Normal read cycle wait (CSRWAIT)
Address
(A20 to A00)
Read-access CS extension cycle
(CSROFF)
Page read cycle wait (CSPRWAIT)
A0
A1
CS assert wait (CSON)
Chip select
(CSn)
Byte control
(BCm)
RD assert wait (RDON)
Data read
(RD)
RD assert wait (RDON)*1
Data bus
(D15 to D00)
D0
D1
Note 1. The RD assert wait operation in the second and subsequent bus accesses depends
on the page read access mode setting.
Figure 15.21
: Indicates sampling point
Page read access timing (n = 0 to 7, m = 0, 1)
Next bus access can be started
Tw1
Tw2
...
Twn
Tend
Tdw1 Tdwn Tpw1 Tpwn
Tend
Tn1
...
Tnm
External bus clock
(BCLK)
Normal write cycle wait (CSWWAIT)
Address
(A20 to A00)
Write-access CS extension cycle
Page write cycle wait (CSPWWAIT) (CSWOFF)
A0
A1
CS assert wait (CSON)
Chip select
(CSn)
Byte control
(BCm)
WR assert wait (WRON)
WR assert wait (WRON)
Data write
(WR)
Write data output extension cycle (WDOFF)
Data bus
(D15 to D00)
Figure 15.22
Write data output wait (WDON)
Write data output extension cycle
(WDOFF)
Write data output wait (WDON)
Page write access timing (n = 0 to 7, m = 0, 1)
Figure 15.23 and Figure 15.24 show examples of operations for access to a 16-bit bus space in 32 bits. The values of the
wait control registers shown in the figures are example settings. In your application, set the registers appropriately for the
specifications of connected devices.
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CSRWAIT: 4
CSPRWAIT: 3
Tw1
Tend
Tpw1
Tend
Tn1
External bus clock
(BCLK)
Address
(A20 to A00)
A0
A1
Chip select
(CSn)
CSROFF: 1
Byte control
(BC1, BC0)
Data read
(RD)
RDON: 1
RDON: 1
Data bus
(D15 to D00)
D0
D1
: Indicates sampling point
Figure 15.23
Example page read access operation when 16-bit bus space is accessed in 32 bits (n = 0 to 7)
CSWWAIT: 4
CSPWWAIT: 4
Tw1
Tend
Tdw1
Tpw1
Tend
Tn1
External bus clock
(BCLK)
Address
(A20 to A00)
A1
A0
CSWOFF: 1
Chip select
(CSn)
Byte control
(BC1, BC0)
Data write
(WR)
WRON: 1
WRON: 1
WDON: 1
Data bus
(D15 to D00)
D0
WDON: 1
Figure 15.24
D1
WDOFF: 1
WDOFF: 1
Example page write access operation when 16-bit bus space is accessed in 32 bits in single-write
strobe mode (n = 0 to 7)
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Figure 15.25 and Figure 15.26 show examples of page access operations when BCLK/2 is selected as the frequency
division in the EBCLK Pin Output Select bit.
CSRWAIT: 3
CSRWAIT: 5
Tw1
Tw2
Tw3
Tw4
Tw5
Tend
Tpw1
Tpw2
Tpw3
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A20 to A00)
A0
A1
A1
CSROFF: 1
Chip select
(CSn)
Byte control
(BC1, BC0)
RDON: 1
RDON: 1
Data read
(RD)
Data bus
(D15 to D00)
D0
D1
: Indicates sampling point
Figure 15.25
Example page read access operation when BCLK/2 is selected in the EBCLK Pin Output Select bit
and two rounds of bus access are generated in response to a single transfer request (n = 0 to 7)
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CSPWWAIT: 4
CSWWAIT: 4
Tw1
Tw2
Tw3
Tw4
Tend
Tdw1
Tpw1
Tpw2
Tpw3
Tpw4
Tend
Tn1
EBCLK pin output
External bus clock
(BCLK)
Address
(A20 to A00)
A1
A0
CSWOFF: 1
Chip select
(CSn)
Byte control
(BC1, BC0)
WRON: 1
WRON: 1
WDON: 1
WDON: 1
Data write
(WR)
Data bus
(D15 to D00)
D1
D0
WDOFF: 1
Figure 15.26
15.5.2
WDOFF: 1
Example page write access operation when BCLK/2 is selected in the EBCLK Pin Output Select
bit and two rounds of bus access are generated in response to a single transfer request, in
single-write strobe mode (n = 0 to 7)
Address/Data Multiplexed Bus
When the address/data Multiplexed I/O Interface Select bit (MPXEN) in CSnCR is set to 1, addresses and data can be
multiplexing input/output to/from the D15 to D00 pins in the corresponding area. Using this function enables direct
connection of this LSI to peripheral LSIs requiring address/data multiplexing. When 8-bit width is selected with the
BSIZE[1:0] bits in CSnCR, D7 to D00 are multiplexed with A07 to A00. When 16-bit width is selected, D15 to D00 are
multiplexed with A15 to A00. In the address/data multiplexed I/O space, accesses are controlled with the ALE, RD,
WRn, and BCn signals.
Byte strobe mode or single-write strobe mode is selectable in the same way as for a separate bus. However, with regard
to the BCn signals within the address cycle, the byte-control signal is output for the data being read or written.
During the address/data multiplexed I/O space access, after the number of wait cycles specified by the address cycle wait
select bits (AWAIT[1:0]) in CSnWCR2 is inserted in the address output cycle, data access is performed.
Ta1 to Tan (Address Cycle Wait)
The period Ta1 to Tan is valid only when the address/data multiplexed I/O space is specified. This period is made up of
the number of clock cycles between the start of external bus access and 1 cycle before the address latch (ALE) signal is
negated. The number of cycles are selectable within the range from zero to three. Addresses are output until the next
cycle of ALE signal negation (address cycle). The timing of ALE signal is the same as that of CS assertion. After the
address cycle, a data cycle is started. CSnWCR1 and CSnWCR2 should be set so that an address cycle and a data cycle
do not overlap.
Page access to the address/data multiplexed I/O space is invalid. When the PRENB or PWENB bit in CSnMOD is set to
1 to enable page-read or page-write access, these settings are ignored and normal read or write operation is performed.
Figure 15.27 to Figure 15.29 show examples of operations with the address/data multiplexed I/O interface
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Ta1
...
Tw1
...
Address cycle
Tan
Data cycle
Twn
Tend
Tn1
Tnm
External bus clock
(BCLK)
A
Address
Address cycle wait (AWAIT)
A
Address/data bus
D
1 cycle fixed
Address latch
(ALE)
RD assert wait (RDON)
Data read
(RD)
Read-access CS extension cycle (CSROFF)
Normal read cycle wait (CSRWAIT)
Chip select
(CSn)
CS assert wait (CSON)
: Indicates the sampling point.
Figure 15.27
Example of read access operation with address/data multiplexed I/O interface (n = 0 to 7)
Address cycle
Ta1
...
Tw1
...
Data cycle
Tan
Twn
Tend
Tn1
External bus clock
(BCLK)
Write data output wait (WDON)
Address
A
Data output extension cycle (WDOFF)
Address cycle wait (AWAIT)
D
A
Address/data bus
1 cycle fixed
\
Address latch
(ALE)
WR assert wait (WRON)
Data write
(WRm)
CS assert wait (CSON)
Write-access CS extension cycle (CSWOFF)
Chip select
(CSn)
Normal write cycle wait (CSWWAIT)
Figure 15.28
Example of write access operation with address/data multiplexed I/O interface (m = 0, 1)
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Address cycle
Tw1
Data cycle
Address cycle
Twn Tend Tn1
...
Tw1
Data cycle
Twn Tend Tn1
...
EBCLK output
pin
External bus
clock
(BCLK)
A
Address
A
Write data output wait (WDON): 4
Address cycle wait (AWAIT): 1
Address/data
bus
Data output extension cycle
(WDOFF): 1
D
A
1 cycle fixed
Address latch
(ALE)
Address cycle wait (AWAIT): 1
D
A
1 cycle fixed
WR assert wait (WRON): 5
Data write
(WRm)
RD assert wait (RDON): 4
CS assert wait (CSON):0
Data read
(RD)
Normal write cycle wait (CSWWAIT): 6
Normal read cycle wait (CSRWAIT): 5
Read-access CS extension
cycle (CSROFF): 1
Chip select
(CSn)
Write-access CS extension cycle (CSWOFF): 1
Figure 15.29
15.5.3
Example of bus timing with address/data multiplexed I/O interface (m = 0, 1)
External Wait Function
Wait cycles can be extended by the WAIT signal beyond the length of the normal access cycle wait specified in the
CSRWAIT[4:0] and CSWWAIT[4:0] bits in CSnWCR1, and the page access cycle wait specified in the CSPRWAIT[2:0]
and CSPWWAIT[2:0] bits in CSnWCR1.
When external wait is enabled (EWENB = 1 in CSnMOD), wait cycles are inserted while the WAIT signal is held low.
When external wait is disabled (EWENB = 0 in CSnMOD), the WAIT signal has no effect. All wait cycles specified in
CSnWCR1 are inserted independently of the WAIT signal.
(1)
Normal access
Sampling of the WAIT signal begins on completion of the wait cycle (Tend) specified in CSnWCR1. The bus cycle is
extended while the WAIT signal is held low. The wait cycle ends (Tend) at the next cycle after the WAIT signal goes
high.
(2)
Page access
The first access operation is the same as the normal access operation. Sampling of the WAIT signal begins on completion
of the wait cycle (Tend) specified in the CSnWCR1 register. The bus cycle is extended while the WAIT signal is held
low. The wait cycle (Tend) ends at the next cycle after the WAIT signal goes high.
For the second and subsequent accesses, sampling of the WAIT signal begins on completion of the page access wait
cycle (Tend). The page access wait cycle is extended while the WAIT signal is held low, and ends (Tend) at the next cycle
after the WAIT signal goes high.
Figure 15.30 to Figure 15.33 show examples of external wait insertion timing with the separate bus interface.
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Tw1
Tw2
…
Twn (Tend)
Tend Tpw1
…
Tpwn (Tend)
Tend
External bus clock
(BCLK)
Address
(A20 to A00)
A0
A1
Chip select/
byte control
(CSn/BC)
Data read
(RD)
Read cycle wait (CSRWAIT)
Page read cycle wait (CSPRWAIT)
Data bus
(D15 to D00)
D0
D1
External wait
(WAIT)
External wait
External wait
: Indicates sampling point
Figure 15.30
Example external wait timing for page read access to 16-bit bus space (when 1/1 BCLK is
selected with the BCLK Pin Output Select bit) (n = 0 to 7, m = 0, 1)
Tw1
Tw2
…
Twn (Tend)
Tend Tpw1
…
Tpwn (Tend)
Tend
BCLK pin
output
External bus clock
(BCLK)
Address
(A20 to A0)
A0
A1
Chip select/
Byte control
(CSn/BCm)
Data read
(RD)
Read cycle wait (CSRWAIT)
Page read cycle wait (CSPRWAIT)
Data bus
(D15 to D00)
D0
D1
External wait
(WAIT)
External wait
External wait
: Indicates the sampling point.
Figure 15.31
Example external wait timing for page read access to 16-bit bus space (when 1/2 BCLK is
Selected with the BCLK Pin Output Select bit) (n = 0 to 7, m = 0, 1)
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Tw1
Tw2
Twn (Tend)
…
Tend Tdw1 Tpw1
Tpwn (Tend)
…
Tend Tdw1
External bus clock
(BCLK)
Address
(A20 to A00)
A0
A1
Chip select
(CSn)
Data read
(RD)
WR assert wait (WRON)
WR assert wait (WRON)
Data write
(WR)
Page write cycle wait (CSPWWAIT)
Write cycle wait (CSWWAIT)
Data bus
(D15 to D00)
D0
Write data output wait (WDON)
D1
Write data output
extension cycle (WDOFF)
Write data output
extension cycle (WDOFF)
Write data output wait (WDON)
External wait
(WAIT)
External wait
External wait
: Indicates sampling point
Figure 15.32
Example external wait timing for page write access to 16-bit bus space in byte strobe mode (when
1/1 BCLK is selected with the BCLK Pin Output Select bit) (n = 0 to 7, m = 0, 1)
Tw1
Tw2
…
Twn (Tend)
Tend Tdw1 Tpw1
…
Tpwn (Tend)
Tend Tdw1
BCLK pin
output
External bus clock
(BCLK)
Address
(A20 to A0)
A0
A1
Chip select
(CSn)
Data read
(RD)
WR assert wait (WRON)
WR assert wait (WRON)
Data write
(WRm)
Page write cycle wait (CSPWWAIT)
Write cycle wait (CSWWAIT)
Data bus
(D15 to D00)
D0
Write data output wait (WDON)
D1
Write data output
extension cycle (WDOFF)
Write data output
extension cycle (WDOFF)
Write data output wait (WDON)
External wait
(WAIT)
External wait
External wait
: Indicates the sampling point.
Figure 15.33
(3)
Example external wait timing for page write access to 16-bit bus space in byte strobe mode (when
1/2 BCLK is selected with the BCLK Pin Output Select bit) (n = 0 to 7, m = 0, 1)
Address/data multiplexed I/O interface
In a data cycle with the address/data multiplexed I/O interface, programmed waits and pin waits using the WAIT pin can
be inserted in the same way as that with the separate bus interface.
Address cycles are not affected by the wait control settings. Figure 15.34 shows an example of external wait insertion
timing with the address/data multiplexed I/O interface.
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Address
cycle
Tw1 Tw2
Address
cycle
Tw1 Tw2
Data cycle
Tw3
Tw4 (Tend)
Tend
Data cycle
Tw3
Tw4 (Tend)
Tend
External bus clock
(BCLK)
A0
Address
Address/data bus
A1
D0
A0
D1
A1
Address latch
(ALE)
Chip select/
byte control
(CSn/BCm)
Data read
(RD)
Normal read cycle wait (CSRWAIT)
Normal read cycle wait (CSRWAIT)
External wait
(WAIT)
External wait
External wait
: Indicates the sampling point.
Figure 15.34
15.5.4
Example external wait Insertion timing with address/data multiplexed I/O interface (m = 0, 1)
Insertion of Recovery Cycles
Recovery cycles can be inserted between consecutive rounds of external bus access by setting the Recovery Cycle
Insertion Enable bit in CSRECEN to 1.
The number of recovery cycles to be inserted after read cycles and write cycles can be independently set for each area
using CSnREC. When the preceding bus cycle is a write access, the number of write recovery cycles must be set with the
WRCV[3:0] bits for the associated area. When the preceding bus cycle is a read access, the number of read recovery
cycles must be set with the RRCV[3:0] bits for the associated area. For example, when a CS1 read access occurs after a
CS0 read access, the number of recovery cycles to be inserted between them is set in the RRCV[3:0] bits in CS0REC.
Recovery cycle insertion can be enabled or disabled with RCVENi (i = 0 to 7) in CSRECEN when the preceding bus
access is a separate bus access, and with RCVENMj (j = 0 to 7) when the preceding bus access is an address/data
multiplexed bus access.
Recovery cycles can be inserted on any of the following conditions:
After a read access to the external bus, a read access is made to the external bus in the same area
After a read access to the external bus, a read access is made to the external bus in a different area
After a read access to the external bus, a write access is made to the external bus in the same area
After a read access to the external bus, a write access is made to the external bus in a different area
After a write access to the external bus, a read access is made to the external bus in the same area
After a write access to the external bus, a read access is made to the external bus in a different area
After a write access to the external bus, a write access is made to the external bus in the same area
After a write access to the external bus, a write access is made to the external bus in a different area.
The recovery cycle starts at the end of the preceding bus cycle, for example when the CSn signal (n = 0 to 7) is negated.
A high-level period of the CSn signal is inserted for the specified recovery cycle period starting from this point.
In the fastest case, the CSn signal for the next round of bus access is asserted immediately after the end of the recovery
cycles. Even if the next request for access to an external address space is generated during the recovery period, the next
access over the external bus starts immediately after the end of the recovery cycles.
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When two or more external bus access cycles are required for a single transfer request from a bus master, and the
recovery cycle insertion condition is satisfied, recovery cycles are also inserted between these bus access cycles.
However, when page read access is enabled (CSnMOD.PRENB = 1) or page write access is enabled (CSnMOD.PWENB
= 1), recovery cycles are not inserted except after the last bus access cycle of the transfer, even if the recovery cycle
insertion condition is satisfied. See Figure 15.37.
Similarly, during normal access with page access enabled, recovery cycles are not inserted between bus access cycles but
only after the last bus access cycle of the transfer. With the address/data multiplexed I/O interface, when the recovery
cycle insertion condition is satisfied, recovery cycles are inserted between bus access cycles regardless of the page access
enable setting.
Figure 15.35 to Figure 15.37 show examples of recovery cycle insertion with the separate bus interface.
CS0 write
External bus clock
(BCLK)
CS0 write recovery
(CS0REC.WRCV[3:0]): 4
Tw1 Tw2 Tw3 Tend Tr1
Address
(A20 to A00)
Tr2
Tr3
A0
CS0 read recovery
(CS0REC.RRCV[3:0]): 4
CS0 read
Tr4 Tw1 Tw2 Tend
Tn1
Tr1
Tr2
Tr3
Tr4
CS1 read
Tw1 Tw2 Tw3 Tend
A2
A1
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
Data bus
(D15 to D00)
D1
D0
D2
: Indicates sampling point
Figure 15.35
Example recovery cycle insertion with separate bus interface (m = 0, 1)
CS1 read recovery
CS0 write recovery
CS0 write recovery
(CS1REC.RRCV[3:0]): 1
(CS0REC.WRCV[3:0]): 2
(CS0REC.WRCV[3:0]): 2
CS1 read (1)
Write (2)
CS0 write (1)
Read (2)
External bus clock
(BCLK)
Address
(A20 to A00)
Tw1 Tw2 Tend Tr1
A0(1)
Tr2 Tw1 Tw2 Tend Tr1
A0(2)
Tr2 Tw1 Tend Tn1
A1(1)
Tr1
Tw1 Tend Tn1
Tr1
A1(2)
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
Data bus
(D15 to D00)
D0(1)
D0(2)
D1(1)
D1(2)
: Indicates sampling point
Figure 15.36
Example recovery cycle insertion when bus access is split, with separate bus interface and
normal access (m = 0, 1)
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CS0 write recovery
(CS0REC.WRCV[3:0]): 2
CS0 write (2)
CS1 read (1)
CS0 write (1)
External bus clock
(BCLK)
Tw1 Tw2 Tw3 Tend Tpw1 Tpw2 Tpw3 Tend Tr1
Address
(A20 to A00)
Data bus
(D15 to D00)
A0(1)
Tr2
A0(2)
D0(1)
CSWWAIT = 3
CS1 read recovery
(CS1REC.RRCV[3:0]): 2
CS1 read (2)
Tw1 Tw2 Tw3 Tend Tpw1 Tpw2 Tpw3 Tend Tr1
A1(1)
A1(2)
D0(2)
CSPWWAIT = 3
D1(2)
D1
Chip select 0
(CS0)
Tr2
CSRWAIT = 3
CSPRWAIT = 3
RDON = 3
RDON = 3
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
Figure 15.37
WRON = 2
WRON = 2
: Indicates sampling point
Example recovery cycle insertion when bus access is split, with separate bus interface and page
access (m = 0, 1)
Figure 15.38 shows an example operation when BCLK/2 is selected as the frequency division in the EBCLK Pin Output
Select bit.
CS0 write
CS0 write recovery
(CS0.WRCV) : 4
CS0 read recovery
(CS0.RRCV) : 4
CS0 read
CS1 read
EBCLK pin output
External bus clock
(BCLK)
Address
(A20 to A00)
Tw1
Tw2
A0
Tend
Tr1
Tr2
Tr3
Tr4
Tw1
Tw2
Tend
A1
Tn1
Tr1
Tr2
Tr3
Tr4
Tw1
Tw3
Tw2
Tend
A2
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
Data bus
(D15 to D00)
D0
D1
D2
: Indicates sampling point
Figure 15.38
Example operation for recovery cycles when BCLK/2 is selected in the EBCLK Pin Output Select
bit, with normal access through a separate bus interface (m = 0, 1)
With the address/data multiplexed I/O interface, recovery cycles are inserted in the same way as that with the separate
bus interface. Figure 15.39 and Figure 15.40 show examples of recovery cycle insertion with the address/data
multiplexed I/O interface.
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15. Buses
CS0 write recovery
(CS0REC.WRCV[3:0]): 3
CS0 write
External bus clock
(BCLK)
Tw1 Tw2 Tw3 Tw4 Tend Tr1
Address
Address/data bus
Tr2
Tr3
CS0 read recovery
(CS0REC.RRCV[3:0]): 2
Tw1 Tw2 Tw3 Tw4 Tend Tr1
A0
A0
CS0 read
CS1 read
Tr2 Tw1 Tw2 Tw3 Tw4 Tend
A2
A1
D1
A1
D0
D2
A2
Address latch
(ALE)
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
: Indicates the sampling point.
Figure 15.39
Example of recovery cycle insertion with address/data multiplexed I/O interface (m = 0, 1)
CS1 read recovery
(CS1REC.RRCV[3:0]): 1
CS0 write recovery
(CS0REC.WRCV[3:0]): 1
CS0 write (1)
External bus clock
(BCLK)
Tw1 Tw2 Tw3 Tend Tr1
Address
Address/data bus
Address latch
(ALE)
Tw1 Tw2 Tw3 Tend Tr1
A0 (1)
A0(1)
0(1)
CS1 read (1)
CS0 write (2)
Tw1 Tw2 Tw3 Tend Tr1
A0 (2)
D0(1)
A0(2)
CS1 read (2)
Tw1 Tw2 Tw3 Tend Tr1
A1 (1)
D0(2)
0(2)
A1(1)
1(1)
A1 (2)
D1
A1(2)
D1(2)
1(2)
Chip select 0
(CS0)
Chip select 1
(CS1)
Byte control
(BCm)
Data read
(RD)
Data write
(WR)
: Indicates the sampling point.
Figure 15.40
15.5.5
Example of recovery cycle insertion when a bus access is split with address/data multiplexed I/O
interface (m = 0, 1)
No Access State
When no external address space is accessed, the CSn, BCn, WRn, RD signals are high, ALE signal is low, and D15 to
D00 are in the high-impedance state.
15.5.6
Write Buffer Function (External Bus)
In write access, the main bus is released by writing data to the write buffer before the access is complete. This allows the
next round of bus access to start. However, if the next access is to an external address space or to a register of the external
bus controller, it is suspended until the external bus operations already in progress are complete.
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15. Buses
Figure 15.41 shows an example of operation when the write buffer function is in use. When this function is in use, if the
next operation after an external write is an internal access, the internal access is executed in parallel with the external
write, for example without waiting for completion of the latter operation.
External
memory
Main bus
Peripheral module
External write
External bus
Figure 15.41
15.5.7
(1)
External memory
Example operation when the write buffer function is in use
Constraints
Constraints on using a separate bus interface
Table 15.11 lists the constraints that apply to bits in the CSn Wait Control Register 1 (CSnWCR1) and CSn Wait Control
Register 2 (CSnWCR2) when normal and page accesses occur.
Even if the Page Read Access Enable bit or Page Write Access Enable bit in the CSn Mode Register is set to enable
(CSnMOD.PRENB = 1 or CSnMOD.PWENB = 1), the first page access or access that does not fall within the scope of a
page access is a normal access operation. Because of this, constraints on normal access must be satisfied.
Table 15.11
Constraints on normal access and page access
Constraints on normal access
Constraints on page access
Reading
Writing
Reading
Writing
CSON[2:0] CSRWAIT
RDON[2:0] CSRWAIT
CSON[2:0] RDON
1 WDON[2:0]
CSON[2:0] CSWWAIT
WRON[2:0] CSWWAIT
WDON[2:0] CSWWAIT
WDOFF[2:0] CSWOFF
WDON[2:0] WRON
CSON[2:0] WRON
CSON[2:0] CSPRWAIT
RDON[2:0] CSPRWAIT
CSON[2:0] RDON
1 WDON[2:0]
CSON[2:0] CSPWWAIT
WRON[2:0] CSPWWAIT
WDON[2:0] CSPWWAIT
WDOFF[2:0] CSWOFF
WDON[2:0] WRON
CSON[2:0] WRON
Note:
(2)
When two or more external bus access cycles are required for a single transfer request from a bus master, and
the recovery cycle insertion condition is satisfied, with page read access enabled (CSnMOD.PRENB = 1) or page
write access enabled (CSnMOD.PWENB = 1), recovery cycles are not inserted between bus access cycles and
are inserted only after the last bus access cycle of the transfer.
Constraints on using address/data multiplexed bus interface
In the address/data multiplexed I/O space, page accesses are invalid. If a page access setting is specified, the setting is
ignored and the normal read or write operation is performed.
Table 15.12
Constraints at the time of normal access
Constraints at the time of normal access
Reading
Writing
CSON[2:0] ≤ CSRWAIT
RDON[2:0] ≤ CSRWAIT
CSON[2:0] ≤ RDON
AWAIT[1:0] + 2 ≤ RDON
CSON[2:0] ≤ AWAIT
CSON[2:0] ≤ CSWWAIT
WRON[2:0] ≤ CSWWAIT
WDON[2:0] ≤ CSWWAIT
WDOFF[2:0] ≤ CSWOFF
WDON[2:0] ≤ WRON
CSON[2:0] ≤ WRON
AWAIT[1:0] + 2 ≤ WRON
AWAIT[1:0] + 2 ≤ WDON
CSON[2:0] ≤ AWAIT
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15. Buses
Constraint on pin multiplexing between the A00 and BC0 functions
Setting the single-write strobe mode is prohibited in the 8-bit bus space.
(4)
Constraints when BCLK/2 is selected in the EBCLK Pin Output Select bit
When 1/2 cycle of BCLK is selected in the EBCLK Pin Output Select bit, the external bus access cycle starts on the
rising edge of the EBCLK pin output. However, when 2 or more external bus access cycles are generated for a single
transfer request from a bus master, the second or subsequent external bus access cycle can start on the falling edge of the
EBCLK pin output, depending on the wait cycle settings. Set the registers appropriately for the specifications of
connected devices.
(5)
Instruction code constraint
You must fix the instruction code to little-endian order.
15.6
SDRAM Area Controller Operation
This section describes how the SDRAM area controller (SDRAMC) is enabled and the SDRAM bus width is set,
followed by a description of the SDRAMC operations, including read, write, auto-refresh, self-refresh, initialization
sequence, and mode register settings.
15.6.1
Enabling/Disabling SDRAM Access and Setting the SDRAM Bus Width
SDRAM access can be enabled or disabled using the SDC Control Register (SDCCR). The SDRAM bus width can also
be set using SDCCR. The refresh operation is available even when the operation of the SDRAM address space is
disabled, as long as self-refresh or auto-refresh is enabled.
15.6.2
No Access State
When no external address space is accessed, the SDCS, WE, RAS and CAS signals are high.
15.6.3
Insertion of Recovery Cycles
When access to the SDRAM area follows access to the CS area, data recovery cycles are inserted for the CS area
controller (CSC). If the number of recovery cycles for the CSC is 0, the ACT command for the next SDRAM access is
issued immediately after negation of CSn signal at the earliest. If the number of recovery cycles are not 0, the ACT
command is issued 2 cycles after the specified recovery cycle period elapsed after negation of CSn signal at the earliest.
Because no data conflicts can occur during access to the SDRAM area, there is no need to set data recovery cycles for the
SDRAM (fixed to 0 cycle).
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CS4 write recovery
(CS4.WRCV): 1
CS4 write
Tw1
External SDRAM clock
(SDLK)
Address
(A20 to A00)
Tw2
Tw1
Tend
A0
A1(r)
CS4 read recovery
(CS4.RRCV): 0
CS4 read
Tw2
A1
Tend
Tr1
A3(r)
A2
A3
Chip select (CS4)
Byte control (BCm)
Data read (RD)
Data write (WR0)
Data bus
(D15 to D00)
(DQ15 to DQ00)
ACT
SDRAM command
D2
D1
D0
RD
DSL
PRA
DSL
D3
ACT
RD
DSL
PRA
DSL
(r): Row address
: Indicates the sampling point.
Note:
When using SDRAM and CS Area access simultaneously.
- EBCLK cannot be used.
- CS0 to CS3 cannot be used.
Figure 15.42
15.6.4
Example of recovery timing for SDRAM access
Write Buffer Function
In write access, the main bus is released by writing data to the write buffer before access is complete. This allows the
next round of bus access to start. However, if the next access is to an external address space or to a register of the external
bus controller, it is suspended until the external bus operations already in progress are complete.
15.6.5
SDRAM Commands
To control the SDRAM, the SDRAMC issues a command for each bus cycle. Commands are defined by a combination of
the SDCS, RAS, CAS, WE, CKE, and other signals. Table 15.13 lists the commands issued by the SDRAMC.
Table 15.13
SDRAMC commands
CKE
Name
Abbreviation
Command
SDCS
RAS
CAS
WE
n-1
n
BA1
BA0
DESL
DSL
Device deselect
H
x
x
x
H
x
x
x
ACTV
ACT
Bank active
L
L
H
H
H
x
V
V
READ
RD
Read
L
H
L
H
H
x
V
V
WRIT
WRI
Write
L
H
L
L
H
x
V
V
PALL
PRA
All bank precharge
L
L
H
L
H
x
x
x
REF
RFA
Auto-refresh
L
L
L
H
H
x
x
x
MRS
MRS
Mode register set
L
L
L
L
H
x
L
L
SELF
RFS
Self-refresh entry
L
L
L
H
H
L
x
x
SELFX
RFX
Self-refresh end
H
x
x
x
L
H
x
x
Note:
15.6.6
H = high level, L = low level, V = valid, x = don’t care.
n = command issue cycle, n - 1 = 1 cycle before the command is issued.
Conditions for Setting the SDRAMC Registers
The SDRAMC registers must only be modified when all the conditions shown in Table 15.14 are satisfied.
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Table 15.14
15. Buses
Conditions for register modification
Function or operation
Registers
Conditions
Self-refresh
SDSELF*1
SDRAM access is disabled (SDCCR.EXENB = 0*2)
Auto-refresh operation is enabled (SDRFEN.RFEN = 1).
Auto-refresh
SDRFCR
Self-refresh operation is disabled (SDSELF.SFEN = 0)
SDRFEN
SDRAM access is disabled (SDCCR.EXENB = 0*2)
Self-refresh operation is disabled (SDSELF.SFEN = 0).
SDIR*1
SDICR is not set yet, and the same conditions as for SDICR modification
are satisfied
SDICR*1
SDRAM access is disabled (SDCCR.EXENB = 0*2)
Auto-refresh operation is disabled (SDRFEN.RFEN = 0)
Self-refresh operation is disabled (SDSELF.SFEN = 0).
Address register
SDADR
SDRAM access is disabled (SDCCR.EXENB = 0*2)
Auto-refresh operation is disabled (SDRFEN.RFEN = 0)
Self-refresh operation is disabled (SDSELF.SFEN = 0).
Timing register
SDTR
Self-refresh operation is in progress (SDSELF.SFEN = 1)
or
SDRAM access is disabled (SDCCR.EXENB = 0*2)
Auto-refresh operation is disabled (SDRFEN.RFEN = 0)
Self-refresh operation is disabled (SDSELF.SFEN = 0).
Mode register
SDMOD*1
SDRAM access is disabled (SDCCR.EXENB = 0*2)
Self-refresh operation is disabled (SDSELF.SFEN = 0).
Initialization sequence
Note 1.
Note 2.
Before modifying this register, confirm that all the status bits in SDSR are 0.
After writing 0 to the EXENB bit, confirm that it is cleared to 0.
15.6.7
Self-Refresh
Transition to or recovery from self-refresh mode is controlled with the SDRAM Self-Refresh Control Register
(SDSELF). Immediately before the transition to self-refresh mode, an auto-refresh operation is performed. In self-refresh
mode, the CKE signal is low. Immediately after recovery from self-refresh mode, the auto-refresh cycle starts.
Figure 15.43 and Figure 15.44 show timing examples of the transition to and recovery from self-refresh mode.
Auto-refresh cycle
Self-refresh mode (CKE = L)
SDCLK
CKE
SDRAM commands
RFA
DSL
DSL
RFS
DSL: Device deselect command
RFA: Auto-refresh command
RFS: Self-refresh entry command
REFW: 0010 = 3 cycles
Figure 15.43
Example timing for transition to self-refresh mode when SDRFCR.REFW[3:0] = 0010b (3 cycles)
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Self-refresh mode
(CKE = L)
Self-refresh
cancellation period
Auto-refresh cycle
SDCLK
CKE
RFX
SDRAM commands
DSL
DSL
REFW: 0010 = 3 cycles
RFA
DSL
DSL
REFW: 0010 = 3 cycles
DSL: Device deselect command
RFA: Auto-refresh command
RFX: Self-refresh end command
Figure 15.44
(1)
Example timing for recovery from self-refresh mode
Self-refresh in Software Standby mode
When invoking self-refresh in Software Standby mode, first follow the procedure shown in section 15.6.11.2, Procedure
for transitioning to and recovering from self-refresh mode. Next, set up the transition to Software Standby mode. In this
mode, set the Output Port Enable bit (OPE) in the Standby Control Register (SBYCR) to 1 to hold the output state of the
address bus and bus control signals.
After canceling Software Standby mode, follow the procedure shown in section 15.6.11.2, Procedure for transitioning to
and recovering from self-refresh mode. For details on invoking and canceling Software Standby mode, see section 11,
Low Power Modes.
(2)
Self-refresh in Deep Software Standby mode
Deep Software Standby mode is invoked from within Software Standby mode. On this transition, the pin states remain
unchanged. Therefore, invoking of self-refresh in Deep Software Standby mode can be handled the same as for Software
Standby mode with one additional setting. You must also set the I/O Port Keep bit (IOKEEP) in the Deep Software
Standby mode Control Register (DPSBYCR) to 1.
Because the SDRAMC is reset internally when Deep Software Standby mode is canceled, the SDRAM control registers
must be set again. After canceling Software Standby mode, follow the procedure in this section to cancel self-refresh.
Figure 15.45 shows self-refresh timing in Deep Software Standby mode. For details on invoking and canceling Deep
Software Standby mode, see section 11, Low Power Modes.
To cancel self-refresh mode:
1. Set DPSBYCR.IOKEEP to 1 to keep the CKE signal output low in Deep Software Standby mode.
2. Start the clock supply to the SDRAMC.
3. Set the SDRAM control registers (SDCMOD, SDADR, and SDTR) again. These registers were initialized by an
internal reset on entering Deep Software Standby mode.
4. Enable an auto-refresh operation by setting SDRFEN.RFEN to 1.
5. Check that all the status bits in SDSR are cleared to 0 and set SDSELF.SFEN to 1 to select self-refresh mode again.
6. Modify the port settings for the SDRAM interface.
7. Set SDCKOCR.SDCKOEN to 1 to start the clock supply to the SDRAM with the SDCLK pin.
8. Check that all the status bits in SDSR are cleared to 0 and set SDSELF.SFEN to 0 to cancel self-refresh mode.
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Deep Software
Standby mode
XTAL
Clock supply to
SDRAMC started
Internal reset
SDRAM
interface
SDCKOEN clear set again
IOKEEP SDCKO
cleared EN set
Clock supply to
SDRAM started
SDCLK
Self-refresh started
(Set SDSELF.SFEN to 1)
SDRAMC control
register set again
Self-refresh set again
(Set SDSELF.SFEN to 1)
Self-refresh cleared.
(Set SDSELF.SFEN to 0)
SDCS
RAS
CAS
WE
CKE
Pin state of SDRAM interface
Pin state retained in deep software
standby mode (IOKEEP = 1)
SDRAM
command
R
F
A
D
S
L
D
S
L
R
F
S
Pin state depending
on the I/O port
register
R
F
S
Auto-refresh
cycle
R
F
S
Self-refresh mode
R
F
X
D
S
L
D
S
L
Self-refresh
clearing period
R
F
A
D
S
L
D
S
L
Auto-refresh
cycle
DSL: Device deselect command
RFA: Auto-refresh command
RFX: Self-refresh end command
Figure 15.45
15.6.8
Example timing for self-refresh cycle in Deep Software Standby mode
Auto-Refresh
The auto-refresh cycle can be started by setting the Auto-Refresh Operation Enable bit (RFEN) in the SDRAM AutoRefresh Control Register (SDRFEN) to 1. After the cycle starts, refresh requests are generated at fixed intervals
determined by the refresh counter. However, because refresh requests are not accepted during read or write access, the
auto-refresh cycle might be suspended.
If an SDRAM access and a refresh request are generated at the same time, the refresh request takes precedence. A CS
area access and a refresh request can be made at the same if the SDCS, RAS, CAS, WE, and CKE signals, which are
required for issuing the refresh command, are exclusively provided for SDRAM access.
The refresh counter is halted during a self-refresh operation. After recovery from the self-refresh mode, the auto-refresh
cycle starts and the counter value is reset, resuming the counter operation.
Figure 15.46 shows a timing example of an auto-refresh cycle.
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Auto-refresh cycle
SDCLK
RFA
SDRAM commands
DSL
DSL
REFW: 0010 = 3 cycles
DSL : Device deselect command
RFA : Auto-refresh command
Figure 15.46
Example timing for auto-refresh cycle (1)
Figure 15.47 shows examples of operation when an auto-refresh request is generated during single access.
Auto-refresh
command is issued
REFW: 0000: 1 cycle
Single write (split in half)
Single write (split in half)
SDCLK
SDRAM
commands
Data bus
ACT
WRI
PRA
d0
ACT
WRI
PRA
RFA
ACT
WRI
d1
d2
PRA
ACT
WRI
PRA
d3
Suspended until completion of single
transfer processing
Auto-refresh request
ACT :
WRI :
PRA :
RFA :
Figure 15.47
15.6.9
Bank active command
Write command
All bank precharge command
Auto-refresh command
Example timing for auto-refresh cycle (2), when the auto-refresh request is made during single
access
Initialization Sequencer
The SDRAMC has a sequencer to issue SDRAM initialization commands. After a reset, the initialization sequencer must
be activated without fail. Operation is not guaranteed if the SDRAM is not initialized.
The SDRAM initialization sequencer issues an all-bank precharge command followed by auto-refresh commands n
times, where n = 1 to 15. The SDRAM initialization sequence timing can be set using the SDRAM Initialization Register
(SDIR). The SDRAM initialization sequence can be activated using the SDRAM Initialization Sequence Control
Register (SDICR). These registers must be set only when the conditions listed in Table 15.14 are satisfied.
Figure 15.48 shows a timing example of the SDRAM initialization sequence. When the ARFC[3:0] bits in SDIR are set
so that auto-refresh operation is performed two or more times, auto-refresh cycles are repeated in the initialization
sequence accordingly.
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Initialization precharge cycle
Initialization auto-refresh cycle
PRA
RFA
SDCLK
SDRAM commands
DSL
DSL
DSL
SDIR.PRC: 001 = 4 cycles
DSL
DSL
DSL
SDIR.ARFI: 001 = 4 cycles
SDIR.ARFC: 001 = 1 time
DSL : Device deselect command
RFA : Auto-refresh command
PRA : All bank precharge command
Figure 15.48
15.6.10
INIST bit in SDSTR is
cleared to 0.
Example timing for SDRAM initialization sequence
Setting the Mode Register
Setting the SDRAM Mode Register (SDMOD) allows the mode register set command to be issued to the SDRAM and
the value set in the MR[14:0] bits in SDMOD to be output to the lower bits of the address, specifically to A14 to A00 for
8-bit bus width or A15 to A01 for 16-bit bus width. Before setting the mode register, set the SDRAM Bus Width Select
bits in the SDC Control Register (SDCCR.BSIZE[1:0]) to determine the data bus width of the SDRAM.
Figure 15.49 shows the mode register setting timing.
Mode register
setting cycle
SDCLK
SDRAM commands
Address bus
MRS
DSL
DSL
A
3 cycles (fixed)
DSL: Device deselect command
MRS: Mode register setting command
Figure 15.49
15.6.11
Mode register setting timing
SDRAMC Setting Examples
This section describes the following:
SDRAMC setting procedure
Timing register setting examples
Procedure for transitioning to and recovering from self-refresh mode.
15.6.11.1
SDRAMC access procedure
Figure 15.50 shows the SDRAMC setting procedure.
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Reset
Initialization sequence
(1) SDIR
Set the PRC, ARFC, and ARFI bits.
(2) SDICR
Set the INIRQ bit to 1.*1
Settings for SDRAM
(1) SDSR
Confirm that all the status bits are cleared to 0.
(2) SDCCR
Set the BSIZE bits (SDRAM bus width).
(3) SDMOD
Set the mode register.
(4) SDTR
Set the RAS, RCD, RP, CL, and WR bits.
(5) SDADR
Set the MXC bits.
Auto-refresh start
SDRFCR Set the number of auto-refresh cycles.
Set the RFEN bit in SDRFEN to 1.
Enabling access
Enable operation in the SDRAM address space. (Set the EXENB bit in SDCCR to 1.)
Access to SDRAM is enabled.
Note 1.
When SDRAM bus width is 8-bit, before SDICR setting, set the BSIZE[1:0] bits in SDCCR to 10b.
Figure 15.50
SDRAMC setting procedure
15.6.11.2
Procedure for transitioning to and recovering from self-refresh mode
Figure 15.51 shows the procedure for transitioning to and recovering from self-refresh mode.
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Access enable state
Auto-refresh is enabled (the RFEN bit in SDRFEN is 1) and SDRAMC access is enabled (the
EXENB bit in SDCCR is 1).
Disabling access
(1) If an access to the SDRAM area is being requested, suspend it.
(2) Disable the SDRAMC access (clear the EXENB bit in SDCCR to 0) in the program located in
areas other than the SDRAM area .
(3) Confirm that the EXENB bit in SDCCR is cleared to 0.
Transition to self-refresh mode
(1) Confirm that all the status bits in SDSR are cleared to 0.
(2) Set the SFEN bit in SDSELF to 1 in the program located in areas other than the SDRAM area.
Self-refresh mode
Recovering from self-refresh mode
(1) Confirm that all the status bits in SDSR are cleared to 0.
(2) Clear the SFEN bit in SDSELF to 0 in the program located in areas other than the SDRAM
area.
Enabling access
Enable SDRAMC access (set the EXENB bit in SDCCR to 1) in the program located in areas other
than the SDRAM area.
Access enable state
The RFEN bit in SDRFEN and the EXENB bit in SDCCR are 1.
Figure 15.51
Note:
Procedure for transitioning to and recovering from self-refresh mode
Self-refresh mode cannot be invoked during SDRAM access. SDRAM access must be disabled during both
transition to and recovery from self-refresh mode. Follow the programming instructions shown in Figure 15.52.
Before transitioning to self-refresh mode, disable access to the SDRAM area.
During transition to self-refresh mode, self-refresh operation, and recovery from self-refresh mode, do not allow
any operand access or instruction fetch, including prefetch to the SDRAM area, to be generated.
Figure 15.52 shows the procedure for transitioning to and recovering from self-refresh mode in Deep Software Standby
mode.
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15. Buses
Access enable state
Auto-refresh is enabled (the RFEN bit in SDRFEN is 1) and SDRAMC access is enabled (the EXENB bit in
SDCCR is 1).
Disabling access
(1) If an access to the SDRAM area is being requested, suspend it.
(2) Disable SDRAMC access (clear the EXENB bit in SDCCR to 0) in the program located in the areas other
than the SDRAM area.
(3) Confirm that the EXENB bit in SDCCR is cleared to 0.
Transition to self-refresh mode
(1) Confirm that all the status bits in SDSR are cleared to 0.
(2) Set the SFEN bit in SDSELF to 1 in the program located in areas other than the SDRAM area.
Self-refresh mode
Deep Software Standby Mode
(The OPE bit in SBYCR and IOKEEP bit in DPSBYCR are 1.)
Internal reset
Starting clock supply to SDRAMC
Setting SDRAMC control registers again
(1) Reset the SDRAM control registers that were initialized by an internal reset in Deep Software Standby Mode
(SDCMOD, SDADR, SDTR, SDRFCR)
(2) Enable auto-refresh (set RFEN bit in SDRFEN to 1).
Setting self-refresh mode again
(1) Confirm that all the status bits in SDSR are cleared to 0.
(2) Set the SFEN bit in SDSELF to 1 in the program located in areas other than the SDRAM area.
Modifying port settings
Modify port settings for the SDRAM interface.
Starting clock supply to SDRAM
Recovering from self-refresh mode
(1) Confirm that all the status bits in SDSR are cleared to 0.
(2) Clear the SFEN bit in SDSELF to 0 in the program located in areas other than the SDRAM area.
Enabling access
Enable SDRAMC access (set the EXENB bit in SDCCR to 1) in the program located in areas other than the
SDRAM area.
Access enable state
The RFEN bit in SDRFEN and the EXENB bit in SDCCR are 1.
Figure 15.52
Procedure for transitioning to and recovering from self-refresh mode in Deep Software Standby
mode
15.6.11.3
Timing register settings and access timing
This section describes the relationship between read and write timing and the settings in the SDRAM Timing Register
(SDTR).
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(1)
15. Buses
Single read timing examples
Figure 15.53 to Figure 15.57 show the relationship between single read timing and the SDTR register settings. Table
15.15 shows the correspondence between the figures and the SDTR register settings.
During read access, the next bus access is enabled at the earliest 2 cycles after the read data becomes valid. However, if
two or more accesses occur for one transfer request, the next bus access is enabled at the earliest 1 cycle after the read
data becomes valid, as shown in Figure 15.57.
Table 15.15
Figure
number
Correspondence between timing figures and STDR register settings for single read timing
RAS[2:0]
settings
Number of
cycles
RCD[1:0]
settings
Number of
cycles
RP[2:0]
settings
Number of
cycles
CL[2:0]
settings
Number of
cycles
Figure 15.53
010
3
00
1
001
2
010
2
Figure 15.54
000
1
01
2
001
2
010
2
Figure 15.55
000
1
01
2
001
2
011
3
Figure 15.56,
Figure 15.57
010
3
00
1
000
1
010
2
Single read
Single read
SDCLK
SDRAM commands
ACT
RD
DSL
PRA
DSL
ACT
d0
Data bus
RCD: 1 cycle
CL: 2 cycles
RD
DSL
PRA
DSL
d1
RP: 2 cycles
RAS: 3 cycles
ACT:
RD:
PRA:
DSL:
Figure 15.53
Bank active command
Read command
All bank precharge command
Device deselect command
Example timing for single read (1)
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15. Buses
Single read
Single read
SDCLK
SDRAM commands
ACT
DSL
RD
PRA
DSL
ACT
DSL
RD
PRA
DSL
d0
Data bus
d1
RCD: 2 cycles CL: 2 cycles
RP: 2 cycles
RAS: 1 cycle
Note: When the period set in the RAS bits ends earlier than the
issue of the RD command, the PRA command is issued in
the next cycle of the RD command cycle.
Figure 15.54
ACT:
RD:
PRA:
DSL:
Bank active command
Read command
All bank precharge command
Device deselect command
Example timing for single read (2)
Single read
Single read
SDCLK
SDRAM commands
ACT
DSL
RD
PRA
DSL
Data bus
DSL
RD
PRA
DSL
d0
RCD: 2 cycles
RAS: 1 cycle
Figure 15.55
ACT
d1
CL: 3 cycles
RP: 2 cycles
ACT:
RD:
PRA:
DSL:
Bank active command
Read command
All bank precharge command
Device deselect command
Example timing for single read (3)
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15. Buses
Single read
Single read
SDCLK
ACT
SDRAM commands
RD
DSL
Data bus
PRA
DSL
RD
DSL
d0
RCD: 1 cycle
CL: 2 cycles
PRA
DSL
d1
RP: 1 cycle
RAS: 3 cycles
Figure 15.56
ACT
ACT:
RD:
PRA:
DSL:
Bank active command
Read command
All bank precharge command
Device deselect command
Example timing for single read (4)
Single read
(second access)
Single read
(first access)
SDCLK
ACT
SDRAM commands
RD
DSL
Data bus
PRA
ACT
PRA
DSL
d1
CL: 2 cycles RP: 1 cycle
ACT:
RD:
PRA:
DSL:
RAS: 3 cycles
(2)
DSL
d0
RCD: 1 cycle
Figure 15.57
RD
Bank active command
Read command
All bank precharge command
Device deselect command
Example timing for single read (5), when two bus accesses occur for one transfer request
Single write timing examples
Figure 15.58 to Figure 15.59 show the relationship between the single write timing and the SDTR register settings. Table
15.16 shows the association between the figures and the SDTR register settings. During write access, the next bus access
is enabled at the earliest 2 cycles after an all bank precharge command (PRA) is issued. However, if two or more accesses
occur for one transfer request, the next bus access is enabled at the earliest 1 cycle after the PRA is issued, as shown in
Figure 15.62.
Table 15.16
Figure
number
Association between timing figures and STDR register settings for single write timing
RAS[2:0]
settings
Number of
cycles
RCD[1:0]
settings
Number of
cycles
RP[2:0]
settings
Number of
cycles
WR
settings
Number of
cycles
Figure 15.58
010
3
00
1
001
2
0
1
Figure 15.59
000
1
01
2
001
2
0
1
Figure 15.60
000
1
01
2
001
2
1
2
Figure 15.61,
Figure 15.62
010
3
00
0
000
2
0
1
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15. Buses
Single write
Single write
SDCLK
SDRAM commands
ACT
Data bus
WRI
DSL
PRA
DSL
ACT
d0
RCD: 1 cycle
WRI
DSL
PRA
DSL
d1
WR: 1 cycle
RP: 2 cycles
RAS: 3 cycles
Note: When the period specified in the RAS bits is longer
than the period specified in WR bits, starting from
ACT:
WRI:
PRA:
DSL:
the issue of the WRI command, the RAS setting is
applied.
Figure 15.58
Bank active command
Write command
All bank precharge command
Device deselect command
Example timing for single write (1)
Single write
Single write
SDCLK
SDRAM commands
ACT
DSL
WRI
PRA
DSL
ACT
DSL
d0
Data bus
RCD: 2 cycles
WRI
PRA
DSL
d1
RP: 2 cycles
WR: 1 cycle
RAS: 1 cycle
Note: When the period specified in the RAS bits is shorter
than the period specified in WR bits, starting from
the issue of the WRI command, the WR setting is
applied.
Figure 15.59
ACT:
WRI:
PRA:
DSL:
Bank active command
Write command
All bank precharge command
Device deselect command
Example timing for single write (2)
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15. Buses
Single write
Single write
SDCLK
SDRAM commands
ACT
DSL
WRI
DSL
PRA
DSL
ACT
DSL
RCD: 2 cycles
DSL
PRA
DSL
d1
d0
Data bus
WRI
WR: 2 cycles
RP: 2 cycles
RAS: 1 cycle
ACT:
WRI:
PRA:
DSL:
Figure 15.60
Bank active command
Write command
All bank precharge command
Device deselect command
Example timing for single write (3)
Single write
Single write
SDCLK
SDRAM commands
Data bus
ACT
WRI
DSL
PRA
DSL
d0
RCD: 1 cycle WR: 1 cycle
ACT
WRI
DSL
PRA
DSL
d1
RP: 1 cycle
RAS: 3 cycles
Note: When the period specified in the RAS bits is longer than
the period specified in WR bits, starting from the issue of
the WRI command, the RAS setting is applied.
Figure 15.61
ACT:
WRI:
PRA:
DSL:
Bank active command
Write command
All bank precharge command
Device deselect command
Example timing for single write (4)
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15. Buses
Single write
(first access)
Single write
(second access)
SDCLK
SDRAM commands
ACT
WRI
Data bus
DSL
PRA
ACT
d0
WRI
DSL
PRA
d1
RCD: 1 cycle WR: 1 cycle
RP: 1 cycle
RAS: 3 cycles
Note:
Figure 15.62
15.6.12
ACT:
WRI:
PRA:
DSL:
When the period specified in the RAS bits is longer
than the period specified in WR bits, starting from the
issue of the WRI command, the RAS setting is
applied.
Bank active command
Write command
All bank precharge command
Device deselect command
Example timing for single write (5), when two bus accesses occur for one transfer request
Address Multiplexing
In the SDRAM space, row and column addresses are multiplexed. The size of the shift in a row address must be specified
in the Address Multiplex Select bits (SDADR.MXC[1:0]) in the SDRAM Address Register (SDADR). Additionally, in
the SDRAM space, the address precharge-select command (Precharge-sel) is output to the upper bits of column
addresses. Table 15.17 shows the relationship between the SDADR.MXC[1:0] settings and the shift amount.
Table 15.17
Address multiplexing
MXC
[1:0]
Shift
amount
Data
bus
width
00
8 bits
8 bits
Address
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
Row
A23
A22
A21
A20
A19
A18*
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
Column
A23
A22
A21
A20
A19
P
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
Row
A23
A22
A21
A20
A19*
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
Column
A23
A22
A21
A20
P
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
Row
A24
A23
A22
A21
A20
A20*
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
Column
A24
A23
A22
A21
A20
P
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
16 bits
Row
A24
A23
A22
A21
A20*
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
Column
A24
A23
A22
A21
P
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
8 bits
Row
A25
A24
A23
A22
A21
A20*
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
Column
A25
A24
A23
A22
A21
P
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
16 bits
01
10
9 bits
10 bits
8 bits
16 bits
11
11 bits
8 bits
16 bits
Note:
Address pins external to the MCU
Row
A25
A24
A23
A22
A21*
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
Column
A25
A24
A23
A22
P
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
Row
A26
A25
A24
A23
A22
A21*
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
Column
A26
A25
A24
A23
A10
P
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
Row
A26
A25
A24
A23
A22*
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
Column
A26
A25
A24
A11
P
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
P: Precharge-select command (Precharge-sel) is output.
*: When the PALL command is issued, Precharge-sel = 1 (high) is output. When the Active command is issued, the associated
address is output.
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15.6.13
15.6.13.1
15. Buses
Example SDRAM Connections
16-bit bus space
Figure 15.63 shows an example connection to two 512-Mb SDRAMs with a 13-bit row address, 11-bit column address,
and 8-bit bus.
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15. Buses
This MCU (shift amount: 11 bits)
No.
Pin name
Row
Column
1
2
RAS
CAS
RAS#
CAS#
3
4
WE
CKE
WE#
CKE
5
6
7
SDCS
SDCLK
DQM0
CS#
CLK
LDQM
8
9
A15
A14
A13
A26
A25
A26
A25
BA1(A14)
BA0(A13)
A12
A24
A23
A24
A11
A12
A11
12
13
A11
A10
A22
A21
P
A10
A10
A9
14
15
A09
A08
A20
A19
A9
A8
A8
A7
A8
A7
A8
A7
16
17
A07
A06
A18
A17
A7
A6
A6
A5
A6
A5
A6
A5
18
19
A05
A04
A16
A15
A5
A4
A4
A3
A4
A3
A4
A3
20
21
A03
A02
A14
A13
A3
A2
A2
A1
A2
A1
A2
A1
22
23
No.
A01
A12
A1
DQ07 to DQ00
A0
A0
A0
DQ[7:0]
SDRAM (512 Mb, with 8-bit bus)
(1)
(2)
RAS
CAS
RAS#
CAS#
(3)
(4)
WE
CKE
WE#
CKE
(5)
(6)
SDCS
SDCLK
CS#
CLK
24
(8)
DQM1
A15
A26
A26
LDQM
BA1(A14)
(9)
(10)
A14
A13
A25
A24
A25
A24
BA0(A13)
A12
(11)
(12)
A12
A11
A23
A22
A11
P
A11
A10
(13)
(14)
A10
A09
A21
A20
A10
A9
(15)
(16)
A08
A07
A19
A18
(17)
(18)
(19)
A06
A05
A04
(20)
(21)
(22)
25
10
11
Figure 15.63
SDRAM (512 Mb, with 8-bit bus)
Pin name
BA/AP
Row
Column
BA1
BA0
AP
–
–
A12
A11
A10
A9
–
–
–
A11
–
A9
BA1
–
–
BA0
–
A12
–
–
A11
A10
A11
–
A9
A8
A9
A8
A9
A8
A8
A7
A7
A6
A7
A6
A7
A6
A17
A16
A15
A6
A5
A4
A5
A4
A3
A5
A4
A5
A4
A3
A03
A02
A14
A13
A3
A2
A2
A1
A01
A12
A1
A0
DQ[7:0]
DQ15 to DQ08
AP
A3
A2
A1
A0
A2
A1
A0
SDRAM connection example with 512-Mb × 2 and 8-bit bus
Figure 15.64 shows an example connection to a 512-Mb SDRAMs with a 13-bit row address, 10-bit column address, and
16-bit bus.
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15. Buses
This MCU (shift amount: 10 bits)
No.
Pin name
Row
Column
SDRAM (512 Mb, with 16-bit bus)
Pin name
1
RAS
RAS#
2
CAS
CAS#
3
WE
WE#
4
CKE
CKE
5
SDCS
CS#
6
SDCLK
CLK
7
DQM1
UDQM
8
DQM0
LDQM
BA/AP
Row
Column
9
A15
A25
A25
BA1(A14)
BA1
–
–
10
A14
A24
A24
BA0(A13)
BA0
–
–
11
A13
A23
A23
A12
A12
–
12
A12
A22
A22
A11
A11
–
13
A11
A21
P
A10
A10
–
14
A10
A20
A10
A9
A9
A9
15
A09
A19
A9
A8
A8
A8
16
A08
A18
A8
A7
A7
A7
17
A07
A17
A7
A6
A6
A6
A5
AP
18
A06
A16
A6
A5
A5
19
A05
A15
A5
A4
A4
A4
20
A04
A14
A4
A3
A3
A3
21
A03
A13
A3
A2
A2
A2
22
A02
A12
A2
A1
A1
A1
23
A01
A11
A1
A0
A0
A0
24
DQ15 to DQ08
DQ[15:8]
25
DQ07 to DQ00
DQ[7:0]
Figure 15.64
SDRAM connection example with 512-Mb × 1 and 16-bit bus
Figure 15.65 shows an example connection to a 256-Mb SDRAMs with a 13-bit row address, 9-bit column address, and
16-bit bus.
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15. Buses
This MCU (shift amount: 9 bits)
No.
(1)
Row
Column
Pin name
1
RAS
RAS#
2
CAS
CAS#
3
WE
WE#
4
CKE
CKE
5
SDCS
CS#
6
SDCLK
CLK
7
DQM1
UDQM
8
DQM0
LDQM
BA/AP
Row
Column
9
A15
A24
A24
BA1(A14)
BA1
–
–
10
A14
A23
A23
BA0(A13)
BA0
–
–
11
A13
A22
A22
A12
A12
–
12
A12
A21
A21
A11
A11
–
13
A11
A20
P
A10
A10
–
14
A10
A19
A10
A9
A9
–
15
A09
A18
A9
A8
A8
A8
16
A08
A17
A8
A7
A7
A7
17
A07
A16
A7
A6
A6
A6
A5
AP
18
A06
A15
A6
A5
A5
19
A05
A14
A5
A4
A4
A4
20
A04
A13
A4
A3
A3
A3
21
A03
A12
A3
A2
A2
A2
22
A02
A11
A2
A1
A1
A1
23
A01
A10
A1
A0
A0
A0
24
DQ15 to DQ08
DQ[15:8]
25
DQ07 to DQ00
DQ[7:0]
Figure 15.65
15.6.14
Pin name
SDRAM (256 Mb, with 16-bit bus)
SDRAM connection example with 256-Mb × 1 and 16-bit bus
Constraints
Low-power states
In Software Standby and Deep Software Standby modes, auto-refresh operation is not available because the clock supply
to the SDRAMC is stopped. To retain the data in the SDRAM when the SDRAM is externally connected, use the selfrefresh function. For the procedure for transitioning to and recovering from self-refresh mode, see section 15.6.7, SelfRefresh.
(2)
Setting the SDRAM Timing Register
Set the RAS[2:0] bits in the SDRAM Timing Register (SDTR) to a value less than or equal to the sum of the row column
latency (SDTR.RCD[1:0]) and column latency (SDTR.CL[2:0]) settings. Operation is not guaranteed if this condition is
not satisfied.
(3)
Instruction code constraint
You must fix the instruction code to little-endian order.
15.7
Bus Error Monitoring Section
This monitoring system monitors each individual area, and whenever it detects an error, it returns the error to the
requesting master IP using the AHB-Lite error response protocol.
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15.7.1
15. Buses
Bus Error Types
The following types of errors can occur on each bus:
Illegal address access
Bus master MPU error
Bus slave MPU error
Timeout.
Table 15.18 lists the address ranges where access leads to illegal address access errors. The reserved area in the slave
does not trigger an illegal address access error. For more information on the bus master MPU and bus slave MPU, see
section 16, Memory Protection Unit (MPU).
15.7.2
Operation When a Bus Error Occurs
When a bus error occurs, operation is not guaranteed and the error is returned to the requesting master IP. The bus errors
that occur for each master are stored in the BUSnERRADD and BUSnERRSTAT registers. These registers must only be
cleared by a reset. For more information, see section 15.3.20, Bus Error Address Register (BUSnERRADD) (n = 1 to 5)
and section 15.3.21, Bus Error Status Register (BUSnERRSTAT) (n = 1 to 5).
Note:
The DMAC and DTC do not receive bus errors. If the DMAC or DTC accesses the bus, the transfer continues.
For other masters that receive bus errors, see section 30, Ethernet DMA Controller (EDMAC).
15.7.3
Conditions Leading to Illegal Address Access Errors
Table 15.18 lists the address spaces for each bus that trigger illegal address access errors.
Table 15.18
Conditions leading to illegal address access errors (1 of 2)
Master bus
CPU (ICode, DCode,
System)
Address
Slave bus name
DMA
ETHER
0000 0000h to 01FF FFFFh
Memory bus 1
Memory bus 3
—
—
—
0200 0000h to 027F FFFFh
Memory mapping area
*1
E
E
0280 0000h to 1FFD FFFFh
Reserved
E
E
E
1FFE 0000h to 1FFF FFFFh
Memory bus 2
Memory bus 3
—
—
—
2000 0000h to 2003 FFFFh
Memory bus 4
—
—
—
2004 0000h to 200F FFFFh
Memory bus 5
—
—
—
2010 0000h to 3FFF FFFFh
Reserved
E
E
E
4000 0000h to 4001 FFFFh
Peripheral bus 1
—
—
E
4002 0000h to 4003 FFFFh
Reserved
E
E
E
4004 0000h to 4005 FFFFh
Peripheral bus 3
—
—
E
4006 0000h to 4007 FFFFh
Peripheral bus 4
—
—
E
4008 0000h to 4009 FFFFh
Peripheral bus 5
—
—
E
400A 0000h to 400B FFFFh
Reserved
—
—
E
400C 0000h to 400D FFFFh
Peripheral bus 7
—
—
E
400E 0000h to 400F FFFFh
Reserved
E
E
E
4010 0000h to 407F FFFFh
Peripheral bus 9
—
—
—
4080 0000h to 5FFF FFFFh
Reserved
E
E
E
6000 0000h to 67FF FFFFh
QSPI area
—
—
—
6800 0000h to 7FFF FFFFh
Reserved
E
E
E
8000 0000h to 97FF FFFFh
CS/SDRAM area
—
—
—
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Table 15.18
15. Buses
Conditions leading to illegal address access errors (2 of 2)
Master bus
Address
Slave bus name
9800 0000h to DFFF FFFFh
Reserved
E000 0000h to FFFF FFFFh
System for
CPU (ICode, DCode,
System)
Cortex®-M4
DMA
ETHER
E
E
E
—
E
E
E: Path where an illegal address access error occurs.
Note 1. The bus module does not detect whether the MMF switched the address. Therefore, if the MMF is enabled and
the CPU accesses 0200 0000h, no error occurs. This depends on the switched address.
If the MMF is disabled and the CPU accesses 0200 0000h, the bus module can detect the error.
The bus module detects an access error resulting from access to a reserved area, for example if no area is assigned to the
slave.
0200 0000h to 1FFD FFFFh: access error detection
0000 0000h to 01FF FFFFh: memory bus 1 no access error detection.
15.7.4
Timeout
For some peripheral modules, a timeout error occurs with the module-stop function. When there is no response from the
slave for a certain period of time, a timeout error is detected. A timeout error is returned to the requesting master IP using
the AHB-Lite error response protocol.
15.8
Notes on using Flash Cache
When using flash cache through access from the CPU, the Arm MPU should also be set to cacheable. See references 1.
and 2. for more information.
15.9
References
1. ARM®v7-M Architecture Reference Manual (ARM DDI 0403D)
2. ARM® Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).
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16. Memory Protection Unit (MPU)
16.
Memory Protection Unit (MPU)
16.1
Overview
The MCU provides four Memory Protection Units (MPUs) and a CPU stack pointer monitor function. Table 16.1 lists the
MPU specifications and Table 16.2 shows the behavior on detection of each MPU error.
Table 16.1
MPU specifications
Classification
Module/Function
Description
Illegal memory
access
Arm® Cortex®-M4 CPU
Arm CPU has a default memory map. If the CPU makes an illegal access, an
exception interrupt occurs.
MPU can change a default memory map.
CPU stack pointer
monitor
2 regions:
Main Stack Pointer (MSP)
Process Stack Pointer (PSP).
Arm MPU
Memory protection function for the CPU:
8 MPU regions with subregions and background region.
Bus master MPU
Memory protection function for each bus master except for the CPU:
Bus master MPU group A: 32 regions
Bus master MPU group B: 8 regions.
Bus slave MPU
Memory protection function for each bus slave
Security MPU
Protects accesses from non-secure programs to the following secure regions:
2 regions (PC)
4 regions (code flash, SRAM, two secure functions).
Memory protection
Security
Table 16.2
Behavior on MPU error detection
MPU type
Notification type
Bus access on error detection
Storing of error access
information
CPU stack pointer monitor
Reset or non-maskable
interrupt
Don’t care
Not stored
Arm MPU
Hard fault
Does not correctly have write
access
Does not correctly have read
access.
Stored in the Cortex-M4 processor
Bus master MPU
Reset or non-maskable
interrupt
Write access to the protected
region
Read access to the protected
region.
Stored
Bus slave MPU
Reset or non-maskable
interrupt
Hard fault.
Write access ignored
Read access read as 0.
Stored
Security MPU
Not notified
Does not correctly have write
access
Does not correctly have read
access.
Do not hold
For information on error access for the Arm MPU, see section 16.7. For information on error access for other MPUs, see
section 15.3.20, Bus Error Address Register (BUSnERRADD) (n = 1 to 5) and section 15.3.21, Bus Error Status Register
(BUSnERRSTAT) (n = 1 to 5) in section 15, Buses.
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16.2
16. Memory Protection Unit (MPU)
CPU Stack Pointer Monitor
The CPU stack pointer monitor detects underflows and overflows of the stack pointer. Because the Arm CPU has two
stack pointers, a Main Stack Pointer (MSP) and Process Stack Pointer (PSP), it supports two CPU stack pointer monitors.
If a stack pointer underflow or overflow is detected, the CPU stack pointer monitor generates a reset or a non-maskable
interrupt.
The CPU stack pointer monitor is enabled by setting the Stack Pointer Monitor Enable bit in the Stack Pointer Monitor
Access Control Register (MSPMPUCTL, PSPMPUCTL) to 1.
Table 16.3 lists the specifications of the CPU stack pointer monitor, Figure 16.1 shows a block diagram, and Figure 16.2
shows the register setting flow.
Table 16.3
CPU stack pointer monitor specifications
Parameter
Description
Protected region
SRAM region
Number of regions
2 regions:
Main Stack Pointer
Process Stack Pointer.
Address specification for individual regions
Region start and end addresses configurable
Stack pointer monitor enable or disable setting for
individual regions
Stack pointer monitor for individual regions can be enabled or disabled
Operation on error detection
Reset or non-maskable interrupts can be generated
Register protection
Registers can be protected from illegal writes
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16. Memory Protection Unit (MPU)
CPU processor register set
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13 (SP)
R14 (LR)
R15 (PC)
xPSR
Process Stack
Pointer (PSP)
Main Stack
Pointer (MSP)
CPU stack pointer monitor
Main stack pointer monitor
Start
address
End
address
ENABLE
bit
OAD
bit
Reset
Compare
(within)
Non-maskable
interrupt
ERROR
flag
Process stack pointer monitor
Start
address
End
address
ENABLE
bit
OAD
bit
Compare
(within)
ERROR
flag
Figure 16.1
CPU stack pointer monitor block diagram
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16. Memory Protection Unit (MPU)
Start
Write to Main Stack Pointer Register
Write to Process Stack Pointer Register
Write to MSPMPUSA and MSPMPUEA registers
Write to PSPMPUSA and PSPMPUEA registers
Write to MSPMPUCTL and PSPMPUCTL registers
Write to MSPMPUOAD and PSPMPUOAD registers
Write to MSPMPUPT and PSPMPUPT registers
End
Figure 16.2
16.2.1
Note:
Register setting flow
Register Descriptions
Bus access must be stopped before writing to MPU registers.
16.2.1.1
Main Stack Pointer Monitor Start Address Register (MSPMPUSA)
Address(es): SPMON.MSPMPUSA 4000 0D08h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MSPMPUSA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
0
0
MSPMPUSA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MSPMPUSA[31:0]
Region Start Address
Address where the region starts, for use in region determination.
The lower 2 bits should be 0. The value range must be 1FF0
0000h to 200F FFFCh, excluding reserved areas.
R/W
The MSPMPUSA and MSPMPUEA registers specify the CPU stack region in the SRAM (1FF0 0000h to 200F FFFFh,
excluding reserved areas). For SRAM area to be covered, see Figure 4.1, Memory map.
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16.2.1.2
16. Memory Protection Unit (MPU)
Main Stack Pointer Monitor End Address Register (MSPMPUEA)
Address(es): SPMON.MSPMPUEA 4000 0D0Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MSPMPUEA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
1
1
MSPMPUEA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MSPMPUEA[31:0]
Region End Address
Address where the region ends, for use in region determination.
The lower 2 bits should be 1. The value range must be 1FF0
0003h to 200F FFFFh, excluding reserved areas.
R/W
16.2.1.3
Process Stack Pointer Monitor Start Address Register (PSPMPUSA)
Address(es): SPMON.PSPMPUSA 4000 0D18h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PSPMPUSA[31:16]
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
0
0
PSPMPUSA[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
PSPMPUSA[31:0]
Region Start Address
Address where the region starts, for use in region determination.
The lower 2 bits should be 0. The value range must be 1FF0
0000h to 200F FFFCh, excluding reserved areas.
R/W
The PSPMPUSA and PSPMPUEA registers specify the CPU stack region in the SRAM (1FF0 0000h to 200F FFFFh,
excluding reserved areas). For SRAM area to be covered, see Figure 4.1, Memory map.
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16.2.1.4
16. Memory Protection Unit (MPU)
Process Stack Pointer Monitor End Address Register (PSPMPUEA)
Address(es): SPMON.PSPMPUEA 4000 0D1Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PSPMPUEA[31:16]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
1
1
Value after reset:
PSPMPUEA[15:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
PSPMPUEA[31:0]
Region End Address
Address where the region ends, for use in region determination.
The lower 2 bits should be 1. The value range must be 1FF0
0003h to 200F FFFFh, excluding reserved areas.
R/W
16.2.1.5
Stack Pointer Monitor Operation After Detection Register (MSPMPUOAD,
PSPMPUOAD)
Address(es): SPMON.MSPMPUOAD 4000 0D00h, SPMON.PSPMPUOAD 4000 0D10h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
OAD
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
OAD
Operation after Detection
0: Non-maskable interrupt
1: Reset.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the OAD bit.
R/(W)*1
Note 1. Write data is not saved.
OAD bit (Operation after Detection)
The OAD bit selects either a reset or a non-maskable interrupt to occur when a stack pointer underflow or overflow is
detected by the CPU stack pointer monitor. The main and the process stack pointer monitors each use an OAD bit to
determine which signal is generated when a stack pointer underflow or overflow is detected. When writing to the OAD
bit, write A5h simultaneously to the KEY[7:0] bits using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writes to the OAD bit. When writing to the OAD bit, write A5h simultaneously to
the KEY[7:0] bits. When values other than A5h are written to the KEY[7:0] bits, the OAD bit is not updated. The
KEY[7:0] bits are always read as 00h.
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16.2.1.6
16. Memory Protection Unit (MPU)
Stack Pointer Monitor Access Control Register (MSPMPUCTL, PSPMPUCTL)
Address(es): SPMON.MSPMPUCTL 4000 0D04h, SPMON.PSPMPUCTL 4000 0D14h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
ERRO
R
—
—
—
—
—
—
—
ENABL
E
0
0
0
0
0
0
0
0/1*1
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
ENABLE
Stack Pointer Monitor
Enable
0: Disable stack pointer monitor
1: Enable stack pointer monitor.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
ERROR
Stack Pointer Monitor
Error Flag
0: No stack pointer overflow or underflow occurred
1: Stack pointer overflow or underflow occurred.
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. The initial value depends on the reset generation source.
ENABLE bit (Stack Pointer Monitor Enable)
The ENABLE bit enables or disables the stack pointer monitor function, independently set for the main stack pointer
monitor and the process stack pointer monitor.
When the MSPMPUCTL.ENABLE bit is set to 1, the following registers are available:
MSPMPUSA
MSPMPUEA
MSPMPUOAD.
When the PSPMPUCTL.ENABLE bit is set to 1, the following registers are available:
PSPMPUSA
PSPMPUEA
PSPMPUOAD.
ERROR bit (Stack Pointer Monitor Error Flag)
The ERROR bit indicates the status of the stack pointer monitor. Each stack pointer monitor has an independent ERROR
bit.
[Setting condition]
Overflow or underflow of the stack pointer.
[Clearing condition]
0 is written to this bit
A reset other than the bus master MPU error reset, bus slave MPU error reset, and stack pointer error reset.
Note:
Only 0 can be written to the ERROR bit.
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16.2.1.7
16. Memory Protection Unit (MPU)
Stack Pointer Monitor Protection Register (MSPMPUPT, PSPMPUPT)
Address(es): SPMON.MSPMPUPT 4000 0D06h, SPMON.PSPMPUPT 4000 0D16h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
PROTE
CT
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PROTECT
Protection of register
0: Stack pointer monitor register writes are permitted
1: Stack pointer monitor register writes are protected. Reads
are permitted.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the PROTECT bit.
R/(W)*1
Note 1. Write data is not saved.
PROTECT bit (Protection of register)
The PROTECT bit enables or disables writes to the associated registers to be protected, independently set for the Main
Stack Pointer monitor and the Process Stack Pointer monitor.
MSPMPUPT.PROTECT controls the following Main Stack Pointer protection registers:
MSPMPUCTL
MSPMPUSA
MSPMPUEA.
PSPMPUT.PROTECT controls the following Process Stack Pointer protection registers:
PSPMPUCTL
PSPMPUSA
PSPMPUEA.
When writing to the PROTECT bit, write A5h simultaneously to the KEY[7:0] bits, using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writing to the PROTECT bit. When writing to the PROTECT bit, write A5h
simultaneously to the KEY[7:0] bits. When other values are written, the PROTECT bit is not updated. The KEY[7:0] bits
are always read as 00h.
16.2.2
16.2.2.1
Operation
Protecting the registers
To protect registers related to the CPU stack pointer monitor, set the associated PROTECT bit.
16.2.2.2
Overflow and underflow errors
The CPU stack pointer monitor generates an error if an overflow or underflow error is detected. Set the OAD bit to select
whether the error is reported as a non-maskable interrupt or reset. The non-maskable interrupt status is indicated in
ICU.NMISR.SPEST, see section 14, Interrupt Controller Unit (ICU). Reset status is indicated in
SYSTEM.RSTSR1.SPERF, see section 6, Resets.
When ICU.NMISR.SPEST indicates that a CPU stack pointer monitor interrupt occurred, confirm it by checking the
ERROR bit in MSPMPUCTL and PSPMPUCTL to determine whether the error is a main stack pointer monitor error or
process stack pointer monitor error.
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16. Memory Protection Unit (MPU)
A non-maskable interrupt remains set when a stack pointer overflows or underflows. To clear the error, clear the nonmaskable interrupt flag by writing 1 to ICU.NMICLR.SPECLR. Write 0 to clear the ERROR bit in MSPMPUCTL and
PSPMPUCTL.
16.3
Arm MPU
The Arm MPU has eight region MPUs and provides full support for:
Protected regions
Overlapping protected regions, with ascending priority:
7 = highest priority
0 = lowest priority.
Access permissions
Export of memory attributes to the system.
Arm MPU mismatches and permission violations invoke the programmable-priority MemManage fault (HardFault)
handler. For details, see section 16.7.
16.4
Bus Master MPU
The bus master MPU monitors the addresses accessed by the bus masters in the entire address space (0000 0000h to
FFFF FFFFh). The access control information, consisting of read and write permissions, can be independently set for up
to 32 regions. The bus master MPU monitors access to each region based on these settings. If access to a protected region
is detected, the bus master MPU generates a reset or a non-maskable interrupt. For details on error access, see section
15.3.20 and section 15.3.21 in section 15, Buses.
Table 16.4 lists the specifications of the bus master MPU and Figure 16.3 shows a block diagram. Figure 16.4 shows bus
master MPU groups A and B.
Table 16.4
Bus master MPU specifications
Parameter
Specifications
Protected master groups
Bus master MPU group A: DMA bus
Bus master MPU group B: ETHER bus.
Protected region
0000 0000h to FFFF FFFFh
Number of regions
Bus master MPU group A: 32 regions
Bus master MPU group B: 8 regions.
Address specification for individual regions
Region start and end addresses configurable
Enable/disable setting for memory protection
in individual regions
Settings enabled or disabled for the associated region
Access-control settings for individual regions
Permission to read and write
Operation on error detection
Reset or non-maskable interrupt
Register protection
Register can be protected from illegal writes
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ICode
bus
Code
flash
memory
Figure 16.3
16. Memory Protection Unit (MPU)
CPU
DCode
bus
System
bus
DMAC/DTC
EDMAC
Bus master MPU
group A
DMA bus
Bus master
MPU group B
ETHER bus
Data
flash
memory
SRAMHS
SRAM0
Internal
peripheral
Bus master
MPU
External bus
cont.
Standby
SRAM
Bus master MPU block diagram
Bus master MPU group A
Start
address
End
address
Enable
Write
protect
Read
protect
Region
control
circuit
Compare
(within)
Enable
Master
control
circuit
Region 0
Region 1
Region 2
Region 31
Group A address
Error status
Group A write access
OAD
Reset
Group A read access
Non-maskable interrupt
Bus master MPU group B
Start
address
End
address
Compare
(within)
Enable
Write
protect
Read
protect
Region
control
circuit
Master
control
circuit
Region 0
Region 1
Region 2
Region 7
Group B address
Group B write access
Enable
Error status
OAD
Group B read access
Figure 16.4
Bus master MPU groups A and B
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16.4.1
Note:
16. Memory Protection Unit (MPU)
Register Descriptions
Bus access must be stopped before writing to MPU registers.
16.4.1.1
Group m Region n Start Address Register (MMPUSmn) (m = A or B; n = 0 to
31)
Address(es): MMPU.MMPUSA0 4000 0204h, MMPU.MMPUSA1 4000 0214h, MMPU.MMPUSA2 4000 0224h, MMPU.MMPUSA3 4000 0234h,
MMPU.MMPUSA4 4000 0244h, MMPU.MMPUSA5 4000 0254h, MMPU.MMPUSA6 4000 0264h, MMPU.MMPUSA7 4000 0274h,
MMPU.MMPUSA8 4000 0284h, MMPU.MMPUSA9 4000 0294h, MMPU.MMPUSA10 4000 02A4h, MMPU.MMPUSA11 4000 02B4h,
MMPU.MMPUSA12 4000 02C4h, MMPU.MMPUSA13 4000 02D4h, MMPU.MMPUSA14 4000 02E4h, MMPU.MMPUSA15 4000 02F4h,
MMPU.MMPUSA16 4000 0304h, MMPU.MMPUSA17 4000 0314h, MMPU.MMPUSA18 4000 0324h, MMPU.MMPUSA19 4000 0334h,
MMPU.MMPUSA20 4000 0344h, MMPU.MMPUSA21 4000 0354h, MMPU.MMPUSA22 4000 0364h, MMPU.MMPUSA23 4000 0374h,
MMPU.MMPUSA24 4000 0384h, MMPU.MMPUSA25 4000 0394h, MMPU.MMPUSA26 4000 03A4h, MMPU.MMPUSA27 4000 03B4h,
MMPU.MMPUSA28 4000 03C4h, MMPU.MMPUSA29 4000 03D4h, MMPU.MMPUSA30 4000 03E4h, MMPU.MMPUSA31 4000 03F4h,
MMPU.MMPUSB0 4000 0604h, MMPU.MMPUSB1 4000 0614h, MMPU.MMPUSB2 4000 0624h, MMPU.MMPUSB3 4000 0634h,
MMPU.MMPUSB4 4000 0644h, MMPU.MMPUSB5 4000 0654h, MMPU.MMPUSB6 4000 0664h, MMPU.MMPUSB7 4000 0674h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MMPUSm[31:16] (m = A or B)
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
0
0
MMPUSm[15:0] (m = A or B)
Value after reset:
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MMPUSm[31:0] (m = A or B)
Region Start Address
Address where the region starts, for use in
region determination. The lower 2 bits should
be 0.
R/W
16.4.1.2
Group m Region n End Address Register (MMPUEmn) (m = A or B; n = 0 to
31)
Address(es): MMPU.MMPUEA0 4000 0208h, MMPU.MMPUEA1 4000 0218h, MMPU.MMPUEA2 4000 0228h, MMPU.MMPUEA3 4000 0238h,
MMPU.MMPUEA4 4000 0248h, MMPU.MMPUEA5 4000 0258h, MMPU.MMPUEA6 4000 0268h, MMPU.MMPUEA7 4000 0278h,
MMPU.MMPUEA8 4000 0288h, MMPU.MMPUEA9 4000 0298h, MMPU.MMPUEA10 4000 02A8h, MMPU.MMPUEA11 4000 02B8h,
MMPU.MMPUEA12 4000 02C8h, MMPU.MMPUEA13 4000 02D8h, MMPU.MMPUEA14 4000 02E8h, MMPU.MMPUEA15 4000 02F8h,
MMPU.MMPUEA16 4000 0308h, MMPU.MMPUEA17 4000 0318h, MMPU.MMPUEA18 4000 0328h, MMPU.MMPUEA19 4000 0338h,
MMPU.MMPUEA20 4000 0348h, MMPU.MMPUEA21 4000 0358h, MMPU.MMPUEA22 4000 0368h, MMPU.MMPUEA23 4000 0378h,
MMPU.MMPUEA24 4000 0388h, MMPU.MMPUEA25 4000 0398h, MMPU.MMPUEA26 4000 03A8h, MMPU.MMPUEA27 4000 03B8h,
MMPU.MMPUEA28 4000 03C8h, MMPU.MMPUEA29 4000 03D8h, MMPU.MMPUEA30 4000 03E8h, MMPU.MMPUEA31 4000 03F8h,
MMPU.MMPUEB0 4000 0608h, MMPU.MMPUEB1 4000 0618h, MMPU.MMPUEB2 4000 0628h, MMPU.MMPUEB3 4000 0638h,
MMPU.MMPUEB4 4000 0648h, MMPU.MMPUEB5 4000 0658h, MMPU.MMPUEB6 4000 0668h, MMPU.MMPUEB7 4000 0678h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MMPUEm[31:16] (m = A or B)
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
1
1
MMPUEm[15:0] (m = A or B)
Value after reset:
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MMPUEm[31:0] (m = A or B)
Region End Address
Address where the region ends, for use in
region determination. The lower 2 bits should
be 1.
R/W
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16.4.1.3
16. Memory Protection Unit (MPU)
Group m Region n Access Control Register (MMPUACmn) (m = A or B; n = 0
to 31)
Address(es): MMPU.MMPUACA0 4000 0200h, MMPU.MMPUACA1 4000 0210h, MMPU.MMPUACA2 4000 0220h, MMPU.MMPUACA3 4000 0230h,
MMPU.MMPUACA4 4000 0240h, MMPU.MMPUACA5 4000 0250h, MMPU.MMPUACA6 4000 0260h, MMPU.MMPUACA7 4000 0270h,
MMPU.MMPUACA8 4000 0280h, MMPU.MMPUACA9 4000 0290h, MMPU.MMPUACA10 4000 02A0h,
MMPU.MMPUACA11 4000 02B0h, MMPU.MMPUACA12 4000 02C0h, MMPU.MMPUACA13 4000 02D0h,
MMPU.MMPUACA14 4000 02E0h, MMPU.MMPUACA15 4000 02F0h,
MMPU.MMPUACA16 4000 0300h, MMPU.MMPUACA17 4000 0310h, MMPU.MMPUACA18 4000 0320h,
MMPU.MMPUACA19 4000 0330h, MMPU.MMPUACA20 4000 0340h, MMPU.MMPUACA21 4000 0350h,
MMPU.MMPUACA22 4000 0360h, MMPU.MMPUACA23 4000 0370h, MMPU.MMPUACA24 4000 0380h,
MMPU.MMPUACA25 4000 0390h, MMPU.MMPUACA26 4000 03A0h, MMPU.MMPUACA27 4000 03B0h,
MMPU.MMPUACA28 4000 03C0h, MMPU.MMPUACA29 4000 03D0h, MMPU.MMPUACA30 4000 03E0h,
MMPU.MMPUACA31 4000 03F0h, MMPU.MMPUACB0 4000 0600h, MMPU.MMPUACB1 4000 0610h,
MMPU.MMPUACB2 4000 0620h, MMPU.MMPUACB3 4000 0630h, MMPU.MMPUACB4 4000 0640h,
MMPU.MMPUACB5 4000 0650h, MMPU.MMPUACB6 4000 0660h, MMPU.MMPUACB7 4000 0670h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
WP
RP
ENABL
E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
ENABLE
Region Enable
0: Group m region n unit disabled
1: Group m region n unit enabled.
R/W
b1
RP
Read Protection
0: Read access permitted
1: Read access protected.
R/W
b2
WP
Write Protection
0: Write access permitted
1: Write access protected.
R/W
b15 to b3
—
Reserved
These bits are read as 0. The write value should be 0. R/W
The ENABLE, RP, and WP bits are individually configurable for each group m region n unit.
ENABLE bit (Region Enable)
The ENABLE bit enables or disables the group m region n unit. When the ENABLE bit is set to 1, the RP and WP bits
can be set to permit or protect access to the region that is set in MMPUSmn and MMPUEmn. When the ENABLE bit is
set to 0, no region is specified for group m region n access.
RP bit (Read Protection)
The RP bit enables or disables read protection for group m region n. The RP bit is available when the ENABLE bit is set
to 1.
WP bit (Write Protection)
The WP bit enables or disables write protection for group m region n. The WP bit is available when the ENABLE bit is
set to 1.
Table 16.5
Function of region control circuit (1 of 2)
MMPUACmn.ENABLE*1
MMPUACmn.RP*1
MMPUACmn.WP*1
Access
Region
Output of group m region n unit*1
0
—
—
Read
—
Outside of region
Write
—
Outside of region
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Table 16.5
16. Memory Protection Unit (MPU)
Function of region control circuit (2 of 2)
MMPUACmn.ENABLE*1
MMPUACmn.RP*1
MMPUACmn.WP*1
Access
Region
Output of group m region n unit*1
1
0
0
Read
Inside
Permitted region
Outside
Outside of region
Inside
Permitted region
Outside
Outside of region
Write
0
1
1
Read
0
Inside
Permitted region
Outside
Outside of region
Write
Inside
Protected region
Outside
Outside of region
Read
Inside
Protected region
Outside
Outside of region
Write
1
1
Read
Write
Inside
Permitted region
Outside
Outside of region
Inside
Protected region
Outside
Outside of region
Inside
Protected region
Outside
Outside of region
Note 1. m = A or B,
In the case of m = A: n = 0 to 31
In the case of m = B: n = 0 to 7.
Table 16.6
Function of master control circuit
Output of group A
Region 2 to 31 unit,
Output of group B
Region 2 to 7 unit
MMPUCTLm.ENABLE*1
Output of group m
region 0 unit*1
Output of group m
region 1 unit*1
1
Protected region
Don’t care
Don’t care
Generate error
1
Don’t care
Protected region
Don’t care
Generate error
1
Don’t care
Don’t care
Protected region
Generate error
1
Outside of region
Outside of region
Outside of region
Generate error
Function of group m*1
Other case
No error
Note 1. m = A or B.
A master MPU error occurs on the following conditions:
MMPUCTLm.ENABLE = 1, and output of one or more region n units is to a protected region
MMPUCTLm.ENABLE = 1, and output of all region n units is outside of region.
Other cases are handled as permitted regions.
16.4.1.4
Bus Master MPU Control Register (MMPUCTLm) (m = A or B)
Address(es): MMPU.MMPUCTLA 4000 0000h, MMPU.MMPUCTLB 4000 0400h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
Value after reset:
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
OAD
ENABL
E
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ENABLE
Master Group Enable
0: Master group m disabled
1: Master group m enabled.
R/W
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16. Memory Protection Unit (MPU)
Bit
Symbol
Bit name
Description
R/W
b1
OAD
Operation After Detection
0: Non-maskable interrupt
1: Reset.
R/W
b7 to b2
—
Reserved
These bits are read as 0.The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the OAD and
ENABLE bits.
R/(W)*1
Note 1. Write data is not saved.
ENABLE bit (Master Group Enable)
The ENABLE bit enables or disables the bus master MPU function for each master group. When this bit is set to 1,
MMPUACmn is available. When this bit is set to 0, MMPUACmn is unavailable, including permission for all regions.
The bus master MPU function of each master group uses the ENABLE bit. When writing to the ENABLE bit, write A5h
to the KEY[7:0] bits simultaneously using halfword access.
OAD bit (Operation After Detection)
The OAD bit selects either a reset or a non-maskable interrupt to occur when access to the protected region is detected by
the bus master MPU. The bus master MPU function for each master group uses its OAD bit independently. When writing
to the OAD bit, write A5h to the KEY[7:0] bits simultaneously using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writing to the ENABLE and OAD bits. When writing to the ENABLE and OAD
bits, write A5h to the KEY[7:0] bits simultaneously. When other values are written, the ENABLE and OAD bits are not
updated. The KEY[7:0] bits are always read as 00h.
16.4.1.5
Group m Protection of Register (MMPUPTm) (m = A or B)
Address(es): MMPU.MMPUPTA 4000 0102h, MMPU.MMPUPTB 4000 0502h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
PROTE
CT
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PROTECT
Protection of register
0: All bus master MPU group m register writes are
permitted
1: All bus master MPU group m register writes are
protected. Read is possible.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the PROTECT bit
R/(W)*1
Note 1. Write data is not saved.
PROTECT bit (Protection of register)
The PROTECT bit enables or disables writes to the associated registers to be protected. MMPUTm.PROTECT controls
the following bus master MPU group m protection registers:
MMPUSmn
MMPUEmn
MMPUACmn
MMPUCTLm.
When writing to the PROTECT bit, write A5h to the KEY[7:0] bits simultaneously using halfword access.
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16. Memory Protection Unit (MPU)
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writing to the PROTECT bit. When writing to the PROTECT bit, write A5h to the
KEY[7:0] bits simultaneously. When other values are written, the PROTECT bit is not updated. The KEY[7:0] bits are
always read as 00h.
16.4.2
16.4.2.1
Operation
Memory protection
The bus master MPU monitors memory access using control settings made individually for the access control regions. If
access to a protected region is detected, the bus master MPU generates a memory protection error.
The bus master MPU can be configured for up to 32 protection regions. Protected regions include those with overlapping
permitted and protected regions, and those with two overlapping permitted regions.
The bus master MPU provides groups A and B. The memory protection function checks the address of the bus for a
unified master group, and all accesses by a master group are protected. The bus master MPU sets the permission for all of
the regions after reset. Setting MMPUCTLm.ENABLE to 1 protects all of the regions. A permitted region is set up
within the protected region for each region. If access to a protected region is detected, the bus master MPU generates an
error.
Figure 16.5 shows the use case of a bus master MPU.
MMPUCTLm.
ENABLE bit = 0
MMPUCTLm.
ENABLE bit = 1
Setting of all regions
Setting of
regions
All memory is
R/W
after reset
All memory is
protected
region
Clearing of
MMPUACmn.
ENABLE bit
Clearing of
MMPUCTLm.
ENABLE bit
Protected region
Region 0 R/W
Region 1 read only
Region 2 write only
Protected region
Region 3 R/W
Protected region
Figure 16.5
Use case of bus master MPU
Figure 16.6 shows the access permission or protection for overlapping bus master MPU regions. Access control for
overlapping regions is as follows:
The region is handled as protected when output of one or more region units is a protected region
The region is handled as protected when output of all region units is outside of the regions
Other cases are handled as permitted regions.
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16. Memory Protection Unit (MPU)
Protected region
Region 0 R/W
Read- and write-protected region
(Output of every single region unit is "region
where permission has not been set".)
Read- and write-permitted region
Region 1 read only
(write protection)
Region 2 write only
(read protection)
Read-permitted and
write-protected region
Read- and write-protected region
Read-protected and
write-permitted region
Region 3
(R/W protection)
Read- and write-protected region
Read- and write-permitted region
Read- and write-protected region
(Output of every single region unit is "region
where permission has not been set".)
Figure 16.6
Access permission or protection by overlap of the bus master MPU regions
Figure 16.7 shows the register setting flow after reset. During this register setting, stop all masters except the CPU.
Start
Write to MMPUCTLm.OAD flag
Set MMPUCTLm.ENABLE flag
All memory is protected region
Write to MMPUSmn and MMPUEmn registers
Write to MMPUACmn register
Set MMPUPTm.PROTECT flag
Regions selected in the MMPUACmn
registers are added
The register is protected
End
Figure 16.7
Register setting flow after reset
Figure 16.8 shows the register setting flow for adding regions. During this register setting, stop all masters except the
CPU.
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16. Memory Protection Unit (MPU)
Start
Clear MMPUPTm.PROTECT flag
Write to MMPUSmn and MMPUEmn registers
Write to MMPUACmn register
Set MMPUPTm.PROTECT flag
End
Figure 16.8
Register setting flow for region addition
16.4.2.2
Protecting the registers
To protect registers related to the bus master MPU, set the PROTECT bit in the associated MMPUPTm register.
16.4.2.3
Memory protection error
The bus master MPU generates an error if access to a protected region is detected. Set the OAD bit to select whether the
error is reported as a non-maskable interrupt or reset. The non-maskable interrupt or reset is shared between bus master
MPU groups A and B. The non-maskable interrupt status is indicated in ICU.NMISR.BUSMST, see section 14, Interrupt
Controller Unit (ICU). Reset status is indicated in SYSTEM.RSTSR1.BUSMRF, see section 6, Resets.
16.5
Bus Slave MPU
The bus slave MPU monitors access to the bus slave functions, such as flash or SRAM. The function can be accessed
from three bus masters, the CPU, and bus master MPU groups A and B. The bus slave MPU has a separate protection
register for each of the three bus masters, with individual access protection control, consisting of read and write
permissions. If access to a protected region is detected, the bus slave MPU generates a reset or a non-maskable interrupt,
and stores the bus error address, bus error status, and error access status. For details, see 15.3.20 and 15.3.21 in section
15, Buses.
Table 16.7 lists the specifications of the bus slave MPU and Figure 16.9 shows a block diagram.
Table 16.7
Bus slave MPU specifications (1 of 2)
Specifications
Description
Protected bus masters
Bus master MPU group A: DMA bus
Bus master MPU group B: ETHER bus.
Protected slave functions
Access-control settings for individual regions
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Memory bus 3: Code flash memory, SRAMHS
Internal peripheral bus 9: Flash memory (in P/E), data flash memory, and TSN
Memory bus 4: SRAM0
Memory bus 5: Standby SRAM
Internal peripheral bus 1: DTC, DMAC, interrupt controller, flash registers, MPU,
CSC, SDRAMC, SRAM registers, system controller and bus controller
Internal peripheral bus 3, 4, 5: Other peripherals
Internal peripheral bus 7: Secure IPs (SCE7)
EXBIU: External memory interface (SDRAM, CSC)
EXBIU2: External device interface (QSPI).
Permission to read and write
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Table 16.7
16. Memory Protection Unit (MPU)
Bus slave MPU specifications (2 of 2)
Specifications
Description
Operation on error detection
Reset, non-maskable interrupt, or exception
Register protection
Register can be protected from illegal writes
CPU
ICode bus
DCode bus
DMAC/DTC
System bus
EDMAC
Bus Slave MPU
Bus slave MPU
Code
flash
memory
Bus slave MPU
Bus slave MPU
Bus slave MPU
Bus slave MPU
Bus slave MPU
Bus slave MPU
SRAM0
Internal
peripheral
External bus
cont.
Data flash
memory
SRAMHS
Standby
SRAM
Figure 16.9
16.5.1
Note:
Bus slave MPU block diagram
Register Descriptions
Bus access must be stopped before writing to the MPU registers.
16.5.1.1
Access Control Register for Memory Bus 3 (SMPUMBIU)
Address(es): SMPU.SMPUMBIU 4000 0C10h
b15
b14
b13
b12
WPSR RPSRA WPFLI RPFLI
AMHS MHS
Value after reset:
0
0
1
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
0
0
0
0
0
0
0
b5
b4
b3
b2
WPGR RPGRP WPGR RPGRP
PB
B
PA
A
0
0
0
0
b1
b0
—
—
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
Protection
0: Memory protection for master group B reads disabled
1: Memory protection for master group B reads enabled.
R/W
b5
WPGRPB
Master Group B Write
Protection
0: Memory protection for master group B writes disabled
1: Memory protection for master group B writes enabled.
R/W
b11 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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16. Memory Protection Unit (MPU)
Bit
Symbol
Bit name
Description
R/W
b12
RPFLI
Code Flash Memory Read
Protection
0: Memory protection for code flash memory reads from
master group A and B disabled
1: Memory protection for code flash memory reads from
master group A and B enabled.
R/W
b13
WPFLI
Code Flash Memory Write
Protection
1: Memory protection for code flash memory writes from
master group A and B enabled.
This bit is read as 1. The write value should be 1.
R/W
b14
RPSRAMHS
SRAMHS Read Protection
0: Memory protection for SRAMHS reads from master
group A and B disabled
1: Memory protection for SRAMHS reads from master
group A and B enabled.
R/W
b15
WPSRAMHS
SRAMHS Write Protection
0: Memory protection for SRAMHS writes from master
group A and B disabled
1: Memory protection for SRAMHS writes from master
group A and B enabled.
R/W
The SMPUMBIU register enables memory protection for the specified master and slave for access from master group A
or B to code flash memory and SRAMHS.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for reads by master group A on memory bus 3.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for writes by master group A on memory bus 3.
RPGRPB bit (Master Group B Read Protection)
The RPGRPB bit enables or disables memory protection for reads by master group B on memory bus 3.
WPGRPB bit (Master Group B Write Protection)
The WPGRPB bit enables or disables memory protection for writes by master group B on memory bus 3.
RPFLI bit (Code Flash Memory Read Protection)
The RPFLI bit enables or disables memory protection for reads by master group A or B on the code flash memory.
WPFLI bit (Code Flash Memory Write Protection)
The WPFLI bit enables memory protection for writes by master group A or B on the code flash memory.
RPSRAMHS bit (SRAMHS Read Protection)
The RPSRAMHS bit enables or disables memory protection for reads by master group A or B on the SRAMHS.
WPSRAMHS bit (SRAMHS Write Protection)
The WPSRAMHS bit enables or disables memory protection for writes by master group A or B on the SRAMHS.
16.5.1.2
Access Control Register for Internal Peripheral Bus 9 (SMPUFBIU)
Address(es): SMPU.SMPUFBIU 4000 0C14h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
WPGR RPGRP WPGR RPGRP WPCP RPCPU
PB
B
PA
A
U
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU reads disabled
1: Memory protection for CPU reads enabled.
R/W
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16. Memory Protection Unit (MPU)
Bit
Symbol
Bit name
Description
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU writes disabled
1: Memory protection for CPU writes enabled.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
Protection
0: Memory protection for master group B reads disabled
1: Memory protection for master group B reads enabled.
R/W
b5
WPGRPB
Master Group B Write
Protection
0: Memory protection for master group B writes disabled
1: Memory protection for master group B writes enabled.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables memory protection for reads by the CPU on internal peripheral bus 9.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables memory protection for writes by the CPU on internal peripheral bus 9.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for reads by master group A on internal peripheral bus 9.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for writes by master group A on internal peripheral bus 9.
RPGRPB bit (Master Group B Read Protection)
The RPGRPB bit enables or disables memory protection for reads by master group B on internal peripheral bus 9.
WPGRPB bit (Master Group B Write Protection)
The WPGRPB bit enables or disables memory protection for writes by master group B on internal peripheral bus 9.
16.5.1.3
Access Control Register for Memory Bus 4 (SMPUSRAM0)
Address(es): SMPU.SMPUSRAM0 4000 0C18h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
WPGR RPGRP WPGR RPGRP WPCP RPCPU
PB
B
PA
A
U
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read protection
0: Memory protection for CPU reads disabled
1: Memory protection for CPU reads enabled.
R/W
b1
WPCPU
CPU Write protection
0: Memory protection for CPU writes disabled
1: Memory protection for CPU writes enabled.
R/W
b2
RPGRPA
Master Group A Read
protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
protection
0: Memory protection for master group B reads disabled
1: Memory protection for master group B reads enabled.
R/W
b5
WPGRPB
Master Group B Write
protection
0: Memory protection for master group B writes disabled
1: Memory protection for master group B writes enabled.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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16. Memory Protection Unit (MPU)
RPCPU bit (CPU Read protection)
The RPCPU bit enables or disables memory protection for reads by the CPU on memory bus 4.
WPCPU bit (CPU Write protection)
The WPCPU bit enables or disables memory protection for writes by the CPU on memory bus 4.
RPGRPA bit (Master Group A Read protection)
The RPGRPA bit enables or disables memory protection for reads by master group A on memory bus 4.
WPGRPA bit (Master Group A Write protection)
The WPGRPA bit enables or disables memory protection for writes by master group A on memory bus 4.
RPGRPB bit (Master Group B Read protection)
The RPGRPB bit enables or disables memory protection for reads by master group B on memory bus 4.
WPGRPB bit (Master Group B Write protection)
The WPGRPB bit enables or disables memory protection for writes by master group B on memory bus 4.
16.5.1.4
Access Control Register for Memory Bus 5 (SMPUSRAM1)
Address(es): SMPU.SMPUSRAM1 4000 0C1Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
WPGR RPGRP WPGR RPGRP WPCP RPCPU
PB
B
PA
A
U
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU reads disabled
1: Memory protection for CPU reads enabled.
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU writes disabled
1: Memory protection for CPU writes enabled.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
Protection
0: Memory protection for master group B reads disabled
1: Memory protection for master group B reads enabled.
R/W
b5
WPGRPB
Master Group B Write
Protection
0: Memory protection for master group B writes disabled
1: Memory protection for master group B writes enabled.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables memory protection for reads by the CPU on memory bus 5.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables memory protection for writes by the CPU on memory bus 5.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for reads by master group A on memory bus 5.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for writes by master group A on memory bus 5.
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16. Memory Protection Unit (MPU)
RPGRPB bit (Master Group B Read Protection)
The RPGRPB bit enables or disables memory protection for reads by master group B on memory bus 5.
WPGRPB bit (Master Group B Write Protection)
The WPGRPB bit enables or disables memory protection for writes by master group B on memory bus 5.
16.5.1.5
Access Control Register for Internal Peripheral Bus 1 (SMPUP0BIU)
Address(es): SMPU.SMPUP0BIU 4000 0C20h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
WPGR RPGRP WPGR RPGRP WPCP RPCPU
PB
B
PA
A
U
1
1
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU reads disabled
1: Memory protection for CPU reads enabled.
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU writes disabled
1: Memory protection for CPU writes enabled.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
Protection
1: Memory protection for master group B reads enabled.
Master group B is protected, and is not detected. This bit
is read as 1. The write value should be 1.
R/W
b5
WPGRPB
Master Group B Write
Protection
1: Memory protection for master group B writes enabled.
Master group B is protected, and is not detected. This bit
is read as 1. The write value should be 1.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables memory protection for reads by the CPU on internal peripheral bus 1.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables memory protection for writes by the CPU on internal peripheral bus 1.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for reads by master group A on internal peripheral bus 1.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for writes by master group A on internal peripheral bus 1.
RPGRPB bit (Master Group B Read Protection)
The RPGRPB bit enables memory protection for reads by master group B on internal peripheral bus 1. There is no
connection between master group B and internal peripheral bus 1. This bit is read as 1, and the write value should be 1.
WPGRPB bit (Master Group B Write Protection)
The WPGRPB bit enables memory protection for writes by master group B on internal peripheral bus 1. There is no
connection between master group B and internal peripheral bus 1. This bit is read as 1, and the write value should be 1.
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16.5.1.6
16. Memory Protection Unit (MPU)
Access Control Register for Internal Peripheral Bus 3 (SMPUP2BIU)
Address(es): SMPU.SMPUP2BIU 4000 0C24h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
WPGR RPGRP WPGR RPGRP WPCP RPCPU
PB
B
PA
A
U
1
1
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU reads disabled
1: Memory protection for CPU reads enabled.
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU writes disabled
1: Memory protection for CPU writes enabled.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
Protection
1: Memory protection for master group B reads enabled.
Master group B is protected, and is not detected. This bit
is read as 1. The write value should be 1.
R/W
b5
WPGRPB
Master Group B Write
Protection
1: Memory protection for master group B writes enabled.
Master group B is protected, and is not detected. This bit
is read as 1. The write value should be 1.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables memory protection for reads by the CPU on internal peripheral buses 3, 4, and 5.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables memory protection for writes by the CPU on internal peripheral buses 3, 4, and 5.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for reads by master group A on internal peripheral buses 3, 4,
and 5.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for writes by master group A on internal peripheral buses 3, 4,
and 5.
RPGRPB bit (Master Group B Read Protection)
The RPGRPB bit enables memory protection for reads by master group B on internal peripheral buses 3, 4, and 5. There
is no connection between master group B and internal peripheral buses 3, 4, and 5. This bit is read as 1, and the write
value should be 1.
WPGRPB bit (Master Group B Write Protection)
The WPGRPB bit enables memory protection for writes by master group B on internal peripheral buses 3, 4, and 5.
There is no connection between master group B and internal peripheral buses 3, 4, and 5. This bit is read as 1, and the
write value should be 1.
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16.5.1.7
16. Memory Protection Unit (MPU)
Access Control Register for Internal Peripheral Bus 7 (SMPUP6BIU)
Address(es): SMPU.SMPUP6BIU 4000 0C28h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
WPGR RPGRP WPGR RPGRP WPCP RPCPU
PB
B
PA
A
U
1
1
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU reads disabled
1: Memory protection for CPU reads enabled.
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU writes disabled
1: Memory protection for CPU writes enabled.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
Protection
1: Memory protection for master group B reads enabled.
Master group B is protected, and is not detected. This bit
is read as 1. The write value should be 1.
R/W
b5
WPGRPB
Master Group B Write
Protection
1: Memory protection for master group B writes enabled.
Master group B is protected, and is not detected. This bit
is read as 1. The write value should be 1.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables memory protection for reads by the CPU on internal peripheral bus 7.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables memory protection for writes by the CPU on internal peripheral bus 7.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for reads by master group A on internal peripheral bus 7.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for writes by master group A on internal peripheral bus 7.
RPGRPB bit (Master Group B Read Protection)
The RPGRPB bit enables memory protection for reads by master group B on internal peripheral bus 7. There is no
connection between master group B and internal peripheral bus 7. This bit is read as 1, and the write value should be 1.
WPGRPB bit (Master Group B Write Protection)
The WPGRPB bit enables memory protection for writes by master group B on internal peripheral bus 7. There is no
connection between master group B and internal peripheral bus 7. This bit is read as 1, and the write value should be 1.
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16.5.1.8
16. Memory Protection Unit (MPU)
Access Control Register for CS Area and SDRAM Area (SMPUEXBIU)
Address(es): SMPU.SMPUEXBIU 4000 0C30h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
WPGR RPGRP WPGR RPGRP WPCP RPCPU
PB
B
PA
A
U
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU reads disabled
1: Memory protection for CPU reads enabled.
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU writes disabled
1: Memory protection for CPU writes enabled.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
Protection
0: Memory protection for master group B reads disabled
1: Memory protection for master group B reads enabled.
R/W
b5
WPGRPB
Master Group B Write
Protection
0: Memory protection for master group B writes disabled
1: Memory protection for master group B writes enabled.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables memory protection for reads by the CPU in the CS and SDRAM areas.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables memory protection for writes by the CPU in the CS and SDRAM areas.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for reads by master group A in the CS and SDRAM areas.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for writes by master group A in the CS and SDRAM areas.
RPGRPB bit (Master Group B Read Protection)
The RPGRPB bit enables or disables memory protection for reads by master group B in the CS and SDRAM areas.
WPGRPB bit (Master Group B Write Protection)
The WPGRPB bit enables or disables memory protection for writes by master group B in the CS and SDRAM areas.
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16.5.1.9
16. Memory Protection Unit (MPU)
Access Control Register for QSPI Area (SMPUEXBIU2)
Address(es): SMPU.SMPUEXBIU2 4000 0C34h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
WPGR RPGRP WPGR RPGRP WPCP RPCPU
PB
B
PA
A
U
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPCPU
CPU Read Protection
0: Memory protection for CPU reads disabled
1: Memory protection for CPU reads enabled.
R/W
b1
WPCPU
CPU Write Protection
0: Memory protection for CPU writes disabled
1: Memory protection for CPU writes enabled.
R/W
b2
RPGRPA
Master Group A Read
Protection
0: Memory protection for master group A reads disabled
1: Memory protection for master group A reads enabled.
R/W
b3
WPGRPA
Master Group A Write
Protection
0: Memory protection for master group A writes disabled
1: Memory protection for master group A writes enabled.
R/W
b4
RPGRPB
Master Group B Read
Protection
0: Memory protection for master group B reads disabled
1: Memory protection for master group B reads enabled.
R/W
b5
WPGRPB
Master Group B Write
Protection
0: Memory protection for master group B writes disabled
1: Memory protection for master group B writes enabled.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RPCPU bit (CPU Read Protection)
The RPCPU bit enables or disables memory protection for reads by the CPU in the QSPI area.
WPCPU bit (CPU Write Protection)
The WPCPU bit enables or disables memory protection for writes by the CPU in the QSPI area.
RPGRPA bit (Master Group A Read Protection)
The RPGRPA bit enables or disables memory protection for reads by master group A in the QSPI area.
WPGRPA bit (Master Group A Write Protection)
The WPGRPA bit enables or disables memory protection for writes by master group A in the QSPI area.
RPGRPB bit (Master Group B Read Protection)
The RPGRPB bit enables or disables memory protection for reads by master group B in the QSPI area.
WPGRPB bit (Master Group B Write Protection)
The WPGRPB bit enables or disables memory protection for writes by master group B in the QSPI area.
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16.5.1.10
16. Memory Protection Unit (MPU)
Slave MPU Control Register (SMPUCTL)
Address(es): SMPU.SMPUCTL 4000 0C00h
b15
b14
b13
b12
b11
b10
b9
b8
KEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
PROTE
CT
OAD
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
OAD
Operation After
Detection
0: Non-maskable interrupt
1: Reset.
R/W
b1
PROTECT
Protection of Register
0: All bus slave MPU register writes are permitted
1: All bus slave MPU register writes are protected. Reads are
permitted.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
KEY[7:0]
Key Code
These bits enable or disable writes to the OAD and PROTECT
bits
R/(W)*1
Note 1. Write data is not saved.
OAD bit (Operation After Detection)
The OAD bit selects either a reset or non-maskable interrupt to occur when access to the protected region is detected by
the bus slave MPU. When writing to the OAD bit, write A5h to the KEY[7:0] bits simultaneously using halfword access.
PROTECT bit (Protection of Register)
The PROTECT bit enables or disables writes to the associated registers to be protected. SMPUCTL.PROTECT controls
the following registers:
SMPUMBIU
SMPUFBIU
SMPUSRAM0
SMPUSRAM1
SMPUP0BIU
SMPUP2BIU
SMPUP6BIU
SMPUEXBIU
SMPUEXBIU2.
When writing to the PROTECT bit, write A5h to the KEY[7:0] bits simultaneously using halfword access.
KEY[7:0] bits (Key Code)
The KEY[7:0] bits enable or disable writing to the OAD and PROTECT bits. When writing to the OAD and PROTECT
bits, write A5h to the KEY[7:0] bits simultaneously. When other values are written, the OAD and PROTECT bits are not
updated. The KEY[7:0] bits are always read as 00h.
16.5.2
16.5.2.1
Operation
Memory protection
The bus slave MPU monitoring functions with access control information that is set for the individual access control
registers. If access to a protected region is detected, the bus slave MPU generates a memory protection error.
The bus slave MPU is enabled by writing 1 to the Write Protect (WPCPU or WPGRPA) bit or the Read Protect (RPCPU
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16. Memory Protection Unit (MPU)
or RPGRPA) bit in the access control register (SMPUMBIU, SMPUFBIU, SMPUSRAM0, SMPUSRAM1,
SMPUP0BIU, SMPUP2BIU, SMPUP6BIU, SMPUEXBIU and SMPUEXBIU2).
16.5.2.2
Protecting the registers
Registers related to the bus slave MPU can be protected with the PROTECT bit in the SMPUCTL register.
16.5.2.3
Memory protection error
If access to a protected region is detected, the slave master MPU generates a memory protection error. Set the OAD bit to
select whether the error is reported as a non-maskable interrupt or reset.
The non-maskable interrupt status is indicated in ICU.NMISR.BUSSST. For details, see section 14, Interrupt Controller
Unit (ICU). The reset status is indicated in SYSTEM.RSTSR1.BUSSRF. For details, see section 6, Resets.
16.6
Security MPU
The MCU incorporates a security MPU with four secure regions that include the code flash, the SRAM, and two security
functions. The secure regions can be protected from non-secure program accesses. Access to a protected region from a
non-secure program is not permitted.
Table 16.8 lists the specifications of the security MPU and Figure 16.10 shows a block diagram of the security MPU.
Table 16.8
Security MPU specifications
Specifications
Description
Secure regions
Code flash, SRAM, two security functions
Protected regions
0000 0000h to FFFF FFFFh
Number of regions
Program Counter: 2 regions
Data access: 4 regions
Address specification for individual regions
Setting the address where regions start and end
Enable/disable setting for memory protection
in individual regions
Settings enabled or disabled for the associated region
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16. Memory Protection Unit (MPU)
Monitor of program counter
PC region 0
PC region 1
Program counter
Monitor of DCode bus
Region 0
Region 1
Bus of CPU
Mask of CPU access
Monitor of system bus
Region 1
Region 2
Region 3
Mask of CPU access
Monitor of master group A
Region 0
Region 1
Region 2
Region 3
Bus of
master group A
Mask of master
group A access
Monitor of master group B
Region 0
Region 1
Region 2
Region 3
Bus of
master group B
Figure 16.10
16.6.1
Mask of master
group B access
Security MPU block diagram
Register Descriptions (Option-Setting memory)
All security MPU registers are option-setting memory. Option-setting memory refers to a set of registers that are
provided for selecting the state of the microcontroller after a reset. The option-setting memory is allocated in the flash.
16.6.1.1
Security MPU Program Counter Start Address Register (SECMPUPCSn)
(n = 0, 1)
Address(es): SECMPUPCS0 0000 0408h, SECMPUPCS1 0000 0410h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
SECMPUPCS[15:2]
—
—
The value set by user
0
0
SECMPUPCS[31:16]
The value set by user
Value after reset:
b15
b14
b13
b12
b11
Value after reset:
b10
b9
b8
b7
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. When writing to flash, the
write value should always be 0.
R
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16. Memory Protection Unit (MPU)
Bit
Symbol
Bit name
Description
R/W
b31 to b2
SECMPUPCS[31:2]
Region Start Address
Address where the region starts, for use in region
determination
R
The SECMPUPCSn and SECMPUPCEn registers specify the security fetch region for the code flash or SRAM (0000
0000h to FFFF FFFFh). The secure program is executed in the memory space defined by the SECMPUPCSn and
SECMPUPCEn registers and can access the secure data specified in the SECMPUSm and SECMPUEm registers (m = 0
to 3).
The SECMPUPCSn register specifies the start address where the region starts. Setting of the memory mirror space (0200
0000h to 027F FFFFh) for MMF is prohibited.
An address space of greater than 12 bytes is required between the last instruction of the non-secure program and the first
instruction of the secure program.
16.6.1.2
Security MPU Program Counter End Address Register (SECMPUPCEn)
(n = 0, 1)
Address(es): SECMPUPCE0 0000 040Ch, SECMPUPCE1 0000 0414h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
SECMPUPCE[15:2]
—
—
The value set by user
1
1
SECMPUPCE[31:16]
The value set by user
Value after reset:
b15
b14
b13
b12
b11
b10
Value after reset:
b9
b8
b7
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. When writing to flash, the
write value should always be 1.
R
b31 to b2
SECMPUPCE[31:2]
Region End Address
Address where the region ends, for use in region
determination.
R
The SECMPUPCSn and SECMPUPCEn registers specify the security fetch region of the code flash or SRAM (0000
0000h to FFFF FFFFh).
The SECMPUPCEn register specifies the end address where the region ends.
16.6.1.3
Security MPU Region 0 Start Address Register (SECMPUS0)
Address(es): SECMPUS0 0000 0418h
b31
b30
b29
b28
b27
b26
b25
b24
—
—
—
—
—
—
—
—
SECMPUS0[23:16]
0
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
Value after reset:
Value after reset:
b23
b18
b17
b16
b2
b1
b0
SECMPUS0[15:2]
—
—
The value set by user
0
0
b7
b22
b6
b21
b5
b20
b4
b19
b3
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
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16. Memory Protection Unit (MPU)
Bit
Symbol
Bit name
Description
R/W
b23 to b2
SECMPUS0[23:2]
Region Start Address
Address where the region starts, for use in region
determination.
R
b31 to b24
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
The SECMPUS0 and SECMPUE0 registers specify the secure region of the flash (0000 0000 to 00FF FFFFh). The
memory space defined in the SECMPUS0 and SECMPUE0 registers can only be accessed from the secure program set
up in the SECMPUPCSn and SECMPUPCEn registers.
The SECMPUS0 register specifies the start address where the region starts.
Setting of the vector table area is prohibited.
16.6.1.4
Security MPU Region 0 End Address Register (SECMPUE0)
Address(es): SECMPUE0 0000 041Ch
b31
b30
b29
b28
b27
b26
b25
b24
—
—
—
—
—
—
—
—
SECMPUS0[23:16]
0
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
Value after reset:
Value after reset:
b23
b18
b17
b16
b2
b1
b0
SECMPUS0[15:2]
—
—
The value set by user
1
1
b7
b22
b6
b21
b5
b20
b4
b19
b3
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. When writing to flash, the write
value should always be 1.
R
b23 to b2
SECMPUE0[23:2]
Region End Address
Address where the region end, for use in region
determination.
R
b31 to b24
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
The SECMPUS0 and SECMPUE0 registers specify the secure region of the flash (0000 0000 to 00FF FFFFh). The
memory space defined in the SECMPUS0 and SECMPUE0 registers can only be accessed from the secure program set
up in the SECMPUPCSn and SECMPUPCEn registers.
The SECMPUE0 register specifies the end address where the region ends.
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16.6.1.5
16. Memory Protection Unit (MPU)
Security MPU Region 1 Start Address Register (SECMPUS1)
Address(es): SECMPUS1 0000 0420h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
SECMPUS1[15:2]
—
—
The value set by user
0
0
SECMPUS1[31:16]
The value set by user
Value after reset:
b15
b14
b13
b12
b11
b10
Value after reset:
b9
b8
b7
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
b19 to b2
SECMPUS1[19:2]
Region Start Address
Address where the region starts, for use in region
determination
R
b31 to b20
SECMPUS1[31:20]
Region Start Address
Address where the region starts, for use in region
determination.
The write value should always be 1FFh or 200h.
R
The SECMPUS1 and SECMPUE1 registers specify the secure region of the SRAM (1FF0 0000h to 200F FFFFh). The
memory space defined in the SECMPUS1 and SECMPUE1 registers can only be accessed from the secure program set
up in the SECMPUPCSn and SECMPUPCEn registers.
The SECMPUS1 register specifies the start address where the region starts.
Setting of the stack area and the vector table are prohibited.
16.6.1.6
Security MPU Region 1 End Address Register (SECMPUE1)
Address(es): SECMPUE1 0000 0424h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b6
b5
b4
b3
b2
b1
b0
SECMPUE1[15:2]
—
—
The value set by user
1
1
SECMPUE1[31:16]
The value set by user
Value after reset:
b15
b14
b13
b12
b11
Value after reset:
b10
b9
b8
b7
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. When writing to flash, the write
value should always be 1.
R
b19 to b2
SECMPUE1[19:2]
Region End Address
Address where the region ends, for use in region
determination
R
b31 to b20
SECMPUE1[31:20]
Region End Address
Address where the region end, for use in region
determination.
The write value should always be 1FFh or 200h.
R
The SECMPUS1 and SECMPUE1 registers specify the secure region of the SRAM (1FF0 0000h to 200F FFFFh). The
memory space defined in the SECMPUS1 and SECMPUE1 registers can only be accessed from the secure program set in
up the SECMPUPCSn and SECMPUPCEn registers.
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The SECMPUE1 register specifies the end address where the region ends.
16.6.1.7
Security MPU Region 2 Start Address Register (SECMPUS2)
Address(es): SECMPUS2 0000 0428h
b31
b30
b29
b28
b27
b26
b25
b24
b23
—
—
—
—
—
—
—
—
—
SECMPUS2[22:16]
0
1
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
b7
Value after reset:
Value after reset:
b22
b17
b16
b1
b0
SECMPUS2[15:2]
—
—
The value set by user
0
0
b6
b21
b5
b20
b4
b19
b18
b3
b2
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
b22 to b2
SECMPUS2[22:2]
Region Start Address
Address where the region starts, for use in region
determination
R
b29 to b23
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
b30
—
Reserved
This bit is read as 1. When writing to flash, the write value
should always be 1.
R
b31
—
Reserved
This bit is read as 0. When writing to flash, the write value
should always be 0.
R
The SECMPUS2 and SECMPUE2 registers specify the secure region for security function 1 (400C 0000 to 400D FFFFh
and 4010 0000 to 407F FFFFh). The memory space defined in the SECMPUS2 and SECMPUE2 registers can only be
accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
The SECMPUS2 register specifies the start address where the region starts.
16.6.1.8
Security MPU Region 2 End Address Register (SECMPUE2)
Address(es): SECMPUE2 0000 042Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
—
—
—
—
—
—
—
—
—
SECMPUE2[22:16]
0
1
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
b7
Value after reset:
Value after reset:
b22
b17
b16
b1
b0
SECMPUE2[15:2]
—
—
The value set by user
1
1
b6
b21
b5
b20
b4
b19
b3
b18
b2
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. When writing to flash, the write
value should always be 1.
R
b22 to b2
SECMPUE2[22:2]
Region End Address
Address where the region ends, for use in region
determination
R
b29 to b23
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
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16. Memory Protection Unit (MPU)
Bit
Symbol
Bit name
Description
R/W
b30
—
Reserved
This bit is read as 1. When writing to flash, the write value
should always be 1.
R
b31
—
Reserved
This bit is read as 0. When writing to flash, the write value
should always be 0.
R
The SECMPUS2 and SECMPUE2 registers specify the secure region for security function 1 (400C 0000 to 400D FFFFh
and 4010 0000 to 407F FFFFh). The memory space defined in the SECMPUS2 and SECMPUE2 registers can only be
accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
The SECMPUE2 register specifies the end address where the region ends.
16.6.1.9
Security MPU Region 3 Start Address Register (SECMPUS3)
Address(es): SECMPUS3 0000 0430h
b31
b30
b29
b28
b27
b26
b25
b24
b23
—
—
—
—
—
—
—
—
—
SECMPUS3[22:16]
0
1
0
0
0
0
0
0
0
The value set by user
b15
b14
b13
b12
b11
b10
b9
b8
b7
Value after reset:
Value after reset:
b22
b17
b16
b1
b0
SECMPUS3[15:2]
—
—
The value set by user
0
0
b6
b21
b5
b20
b4
b19
b18
b3
b2
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
b22 to b2
SECMPUS3[22:2]
Region Start Address
Address where the region starts, for use in region
determination.
R
b29 to b23
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
b30
—
Reserved
This bit is read as 1. When writing to flash, the write value
should always be 1.
R
b31
—
Reserved
This bit is read as 0. When writing to flash, the write value
should always be 0.
R
The SECMPUS3 and SECMPUE3 registers specify the secure region for security function 2 (400C 0000h to 400D
FFFFh and 4010 0000h to 407F FFFFh). The memory space defined in the SECMPUS3 and SECMPUE3 registers can
only be accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
The SECMPUS3 register specifies the start address where the region starts.
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16.6.1.10
16. Memory Protection Unit (MPU)
Security MPU Region 3 End Address Register (SECMPUE3)
Address(es): SECMPUE3 0000 0434h
b31
b30
b29
b28
b27
b26
b25
b24
b23
—
—
—
—
—
—
—
—
—
0
1
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
Value after reset:
Value after reset:
b22
b21
b20
b19
b18
b17
b16
b1
b0
SECMPUE3[15:2]
—
—
The value set by user
1
1
SECMPUE3[22:16]
The value set by user
b6
b5
b4
b3
b2
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. When writing to flash, the write
value should always be 1.
R
b22 to b2
SECMPUE3[22:2]
Region End Address
Address where the region ends, for use in region
determination.
R
b29 to b23
—
Reserved
These bits are read as 0. When writing to flash, the write
value should always be 0.
R
b30
—
Reserved
This bit is read as 1. When writing to flash, the write value
should always be 1.
R
b31
—
Reserved
This bit is read as 0. When writing to flash, the write value
should always be 0.
R
The SECMPUS3 and SECMPUE3 registers specify the secure region for security function 2 (400C 0000h to 400D
FFFFh and 4010 0000h to 407F FFFFh). The memory space defined in the SECMPUS3 and SECMPUE3 registers can
only be accessed from the secure program set up in the SECMPUPCSn and SECMPUPCEn registers.
The SECMPUE3 register specifies the end address where the region ends.
16.6.1.11
Security MPU Access Control Register (SECMPUAC)
Address(es): SECMPUAC 0000 0438h
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
DISPC DISPC
1
0
1
1
1
1
1
1
The value set by
user
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
DIS3
DIS2
DIS1
DIS0
1
1
1
1
The value set by user
Bit
Symbol
Bit name
Description
R/W
b0
DIS0
Region 0 Disable
0: Security MPU region 0 is enabled
1: Security MPU region 0 is disabled.
R
b1
DIS1
Region 1 Disable
0: Security MPU region 1 is enabled
1: Security MPU region 1 is disabled.
R
b2
DIS2
Region 2 Disable
0: Security MPU region 2 is enabled
1: Security MPU region 2 is disabled.
R
b3
DIS3
Region 3 Disable
0: Security MPU region 3 is enabled
1: Security MPU region 3 is disabled.
R
b7 to b4
—
Reserved
These bits are read as 1. When writing to flash, the write
value should always be 1.
R
b8
DISPC0
PC Region 0 Disable
0: Security MPU PC region 0 is enabled
1: Security MPU PC region 0 is disabled.
R
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Bit
Symbol
Bit name
Description
R/W
b9
DISPC1
PC Region 1 Disable
0: Security MPU PC region 1 is enabled
1: Security MPU PC region 1 is disabled.
R
b15 to b10
—
Reserved
These bits are read as 1. When writing to flash, the write
value should always be 1.
R
Note:
Note:
When flash memory is erased, the security MPU is disabled.
To enable or disable the security MPU, see section 16.6.2, Memory Protection.
DIS0 bit (Region 0 Disable)
The DIS0 bit enables or disables the security MPU region 0. If security MPU region 0 is enabled, the code flash region
within the limits set up by SECMPUS0 and SECMPUE0 is secure data.
DIS1 bit (Region 1 Disable)
The DIS1 bit enables or disables the security MPU region 1. If security MPU region 1 is enabled, the SRAM region
within the limits set up by SECMPUS1 and SECMPUE1 is secure data.
DIS2 bit (Region 2 Disable)
The DIS2 bit enables or disables the security MPU region 2. If security MPU region 2 is enabled, the region within the
limits set up by SECMPUS2 and SECMPUE2 is secure data.
DIS3 bit (Region 3 Disable)
The DIS3 bit enables or disables the security MPU region 3. If security MPU region 3 is enabled, the region within the
limits set up by SECMPUS3 and SECMPUE3 is secure data.
DISPC0 bit (PC Region 0 Disable)
The DISPC0 bit enables or disables the security MPU PC region 0. If security MPU PC region 0 is enabled, the code
flash or SRAM region within the limits set up by SECMPUPCS0 and SECMPUPCE0 contains a secure program.
DISPC1 bit (PC Region 1 Disable)
The DISPC1 bit enables or disables the security MPU PC region 1. If security MPU PC region 1 is enabled, the code
flash or SRAM region within the limits set up by SECMPUPCS1 and SECMPUPCE1 contains a secure program.
16.6.2
Memory Protection
The security MPU protects the regions (code flash, SRAM, two security function regions) from non-secure program
access. If access to the protected region is detected, access becomes invalid.
When the security MPU is enabled, DISPC0 or DISPC1 in the Security MPU Access Control Register (SECMPUAC)
must be cleared to 0 and DIS0, DIS1, DIS2, or DIS3 in the Security MPU Access Control Register (SECMPUAC) must
be cleared to 0.
When security MPU is disabled, all of bits DISPC0, DISPC1, DIS0, DIS1, DIS2, and DIS3 in the Security MPU Access
Control Register (SECMPUAC) must be set to 1.
Other settings of the Security MPU Access Control Register (SECMPUAC) are prohibited.
The security MPU provides protection of secure regions when:
Secure data is accessed from a non-secure program
Secure data is accessed from other than the CPU (DMAC, DTC, EDMAC)
Secure data is accessed from the debugger.
Secure data is accessible only from a secure program.
Note:
Secure program:
Code flash or SRAM region within the limits set up by SECMPUPCS0 and SECMPUPCE0.
Code flash or SRAM region within the limits set up by SECMPUPCS1 and SECMPUPCE1.
Non-secure program: All regions outside the secure program.
Secure data:
Code flash region within the limits set up by SECMPUS0 and SECMPUE0,
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16. Memory Protection Unit (MPU)
SRAM region within the limits set up by SECMPUS1 and SECMPUE1.
Security function region within the limits set up by SECMPUS2 and SECMPUE2.
Security Function region within the limits set up by SECMPUS3 and SECMPUE3.
Security MPU setting
Memory
Memory
Non-secure data
Secure function
Region 3
Secure data
Non-secure data
Secure function
Region 2
Secure data
Non-secure
program
Non-secure data
SRAM
Region 1
Secure data
Secure program
PC region 1
Code flash
Non-secure data
Region 0
Non-secure
program
Secure data
PC region 0
Secure program
Non-secure
program
Secure program in code flash (PC region 0) can access all data (secure data and non-secure data).
Secure program in SRAM (PC region 1) can access all data (secure data and non-secure data).
Non-secure program (not PC region 0 or PC region 1) cannot access secure data (region 0, region 1, region 2, region 3).
Non-secure program (not PC region 0 or PC region 1) can access non-secure data.
Figure 16.11
Use case of security MPU
16.6.2.1
Notes on debug
The protected memory cannot be debugged if the security MPU is enabled. Disable the security MPU when debugging a
secure program.
16.7
References
1. ARM®v7-M Architecture Reference Manual (ARM DDI 0403D).
2. ARM® Cortex®-M4 Processor Technical Reference Manual (ARM DDI 0439D).
3. ARM® Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).
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17. DMA Controller (DMAC)
17.
DMA Controller (DMAC)
17.1
Overview
The MCU includes an 8-channel DMA Controller (DMAC) that can transfer data without intervention from the CPU.
When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer
destination address.
Table 17.1 lists the DMAC specifications and Figure 17.1 shows a block diagram.
Table 17.1
DMAC specifications
Parameter
Specifications
Number of channels
8 channels (DMACm, m = 0 to 7)
Transfer space
4 GB (0000 0000h to FFFF FFFFh, excluding reserved areas)
Maximum transfer volume
64M data units (maximum number of transfers in block transfer mode: 1,024 data units ×
65,536 blocks)
DMA activation source
Selectable for each channel:
Software trigger
Interrupt requests from peripheral modules or trigger from external interrupt input pins.*1
Channel priority
Channel 0 > Channel 1 > Channel 2 > Channel 3... > Channel 7 (Channel 0: highest)
Transfer data
Single data
Bit length: 8, 16, 32 bits
Block size
Number of data: 1 to 1,024
Normal transfer mode
One data transfer by one DMA transfer request
Selectable free running mode (total number of data transfers is not specified).
Repeat transfer mode
One data transfer by one DMA transfer request
Program returns to the transfer start address on completion of the repeat size of data
transfer specified for the transfer source or destination
Maximum settable repeat size: 1,024.
Block transfer mode
One data block transfer by one DMA transfer request
Maximum settable block size: 1,024 data.
Selective
functions
Extended repeat area
function
Allows data to be transferred by repeating the address values in the specified range, with
the upper bit values in the transfer address register remaining fixed
Area of 2 bytes to 128 MB individually selectable as the extended repeat area for transfer
source and destination.
Interrupt
request
(DMACm_INT)
Transfer end interrupt
Generated on completion of transferring data volume specified in the transfer counter
Transfer escape end
interrupt
Generated when:
The repeat size of data transfer is complete
The source address of the extended repeat area overflows
The destination address of the extended repeat area overflows.
Transfer mode
Event link activation (DMACm_INT)
An event link request is generated after each data transfer (for block transfer, after each
block is transferred)
Module-stop function
Module-stop state can be set to reduce power consumption
Note 1.
For details on DMAC activation sources, see Table 14.3, Interrupt vector table, in section 14, Interrupt Controller Unit (ICU).
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17. DMA Controller (DMAC)
DMAC
DMAC registers
DMAC channels
(CH0 to CH7)
DMSAR
DMDAR
DMCRA
DMCRB
DMOFR
DMTMD
DMAMD
DMSTS
DMCNT
Activation control
8
Interrupt
controller
DMA
transfer
request
arbitration
DMA start
request
DMAC
response
DMAST
8
Interrupt
request for ICU
(DMACm_INT)
Register control
8
m = 0 to 7
Interrupt
request for ELC
(DMACm_INT)
ELC
DMAC response
control
8
m = 0 to 7
DMAC core
Source address
Destination address
Transfer counter
Block counter
Transfer mode
DMAC
control
circuit
Bus interface
Internal peripheral bus 1
DMA Bus
Code
flash
memory
Figure 17.1
SRAMHS
SRAM0
Standby
SRAM
Data
flash
memory
Internal
peripherals
External
bus controller
System bus
DMA bus
DMAC block diagram
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17.2
17. DMA Controller (DMAC)
Register Descriptions
17.2.1
DMA Source Address Register (DMSAR)
Address(es): DMAC0.DMSAR 4000 5000h, DMAC1.DMSAR 4000 5040h, DMAC2.DMSAR 4000 5080h, DMAC3.DMSAR 4000 50C0h,
DMAC4.DMSAR 4000 5100h, DMAC5.DMSAR 4000 5140h, DMAC6.DMSAR 4000 5180h, DMAC7.DMSAR 4000 51C0h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
Setting range
R/W
b31 to b0
Specifies the transfer source start address
0000 0000h to FFFF FFFFh (4 GB)
R/W
Set DMSAR while DMAC activation is disabled (the DMST bit in DMAST = 0) or DMA transfer is disabled (the DTE
bit in DMCNT = 0).
Note:
Address alignment in this register must match the transfer data size value selected in the SZ bit in DMTMD.
17.2.2
DMA Destination Address Register (DMDAR)
Address(es): DMAC0.DMDAR 4000 5004h, DMAC1.DMDAR 4000 5044h, DMAC2.DMDAR 4000 5084h, DMAC3.DMDAR 4000 50C4h,
DMAC4.DMDAR 4000 5104h, DMAC5.DMDAR 4000 5144h, DMAC6.DMDAR 4000 5184h, DMAC7.DMDAR 4000 51C4h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
Setting range
R/W
b31 to b0
Specifies the transfer destination start address
0000 0000h to FFFF FFFFh (4 GB)
R/W
Set DMDAR while DMAC activation is disabled (the DMST bit in DMAST = 0) or DMA transfer is disabled (the DTE
bit in DMCNT = 0).
Note:
Address alignment in this register must match the transfer data size value selected in the SZ bit in DMTMD.
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17.2.3
17. DMA Controller (DMAC)
DMA Transfer Count Register (DMCRA)
Address(es): DMAC0.DMCRA 4000 5008h, DMAC1.DMCRA 4000 5048h, DMAC2.DMCRA 4000 5088h, DMAC3.DMCRA 4000 50C8h
DMAC4.DMCRA 4000 5108h, DMAC5.DMCRA 4000 5148h, DMAC6.DMCRA 4000 5188h, DMAC7.DMCRA 4000 51C8h
Normal transfer mode
DMCRAH
Value after reset:
b31
b30
b29
b28
b27
b26
—
—
—
—
—
—
0
0
0
0
0
0
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
DMCRAL
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Repeat transfer mode, block transfer mode
DMCRAH
Value after reset:
b31
b30
b29
b28
b27
b26
—
—
—
—
—
—
0
0
0
0
0
0
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
DMCRAL
Value after reset:
b15
b14
b13
b12
b11
b10
0
0
0
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
Symbol
Bit name
Description
R/W
DMCRAL
Lower bits of transfer count
Specifies the number of transfer operations
R/W
DMCRAH
Upper bits of transfer count
Note:
(1)
R/W
In repeat and block transfer modes, set the same value for DMCRAH and DMCRAL.
Normal transfer mode (MD[1:0] bits in DMACm.DMTMD = 00b)
In normal transfer mode, DMCRAL functions as a 16-bit transfer counter. The number of transfer operations is one when
the setting is 0001h, and 65,535 when it is FFFFh. The value is decremented by one each time data is transferred. A
setting of 0000h indicates an unspecified number of transfer operations. Data transfer is performed with the transfer
counter stopped, that is, in free running mode.
Do not use DMCRAH in normal transfer mode. Write 0000h to DMCRAH.
(2)
Repeat transfer mode (MD[1:0] bits in DMACm.DMTMD = 01b)
In repeat transfer mode, DMCRAH specifies the repeat size and DMCRAL functions as a 10-bit transfer counter. The
number of transfer operations is one when the setting is 001h, 1,023 when it is 3FFh, and 1,024 when it is 000h. In this
mode, a value in the range of 000h to 3FFh (1 to 1,024) can be set for DMCRAH and DMCRAL.
Setting bits [15:10] in DMCRAL is invalid. Write 0 to these bits. The value in DMCRAL is decremented by 1 each time
data is transferred until it reaches 000h, at which time the value in DMCRAH is loaded into DMCRAL.
(3)
Block transfer mode (MD[1:0] bits in DMACm.DMTMD = 10b)
In block transfer mode, DMCRAH specifies the block size and DMCRAL functions as a 10-bit block size counter. The
block size is one when the setting is 001h, 1,023 when it is 3FFh, and 1,024 when it is 000h. In this mode, a value in the
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17. DMA Controller (DMAC)
range of 000h to 3FFh can be set for DMCRAH and DMCRAL.
Setting bits [15:10] in DMCRAL is invalid. Write 0 to these bits. The value in DMCRAL is decremented by 1 each time
data is transferred until it reaches 000h, at which time the value in DMCRAH is loaded into DMCRAL.
17.2.4
DMA Block Transfer Count Register (DMCRB)
Address(es): DMAC0.DMCRB 4000 500Ch, DMAC1.DMCRB 4000 504Ch, DMAC2.DMCRB 4000 508Ch, DMAC3.DMCRB 4000 50CCh,
DMAC4.DMCRB 4000 510Ch, DMAC5.DMCRB 4000 514Ch, DMAC6.DMCRB 4000 518Ch, DMAC7.DMCRB 4000 51CCh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
Setting range
R/W
b15 to b0
Specifies the number of block or repeat transfer
operations
0001h to FFFFh (1 to 65,535)
0000h (65,536).
R/W
DMCRB specifies the number of operations in block and repeat transfer modes. The number of transfer operations is one
when the setting is 0001h, 65,535 when it is FFFFh, and 65,536 when it is 0000h.
In repeat transfer mode, the value is decremented by 1 when the final data of one repeat size is transferred. In block
transfer mode, the value is decremented by 1 when the final data of one block size is transferred. Do not use DMCRB in
normal transfer mode as the setting is invalid.
17.2.5
DMA Transfer Mode Register (DMTMD)
Address(es): DMAC0.DMTMD 4000 5010h, DMAC1.DMTMD 4000 5050h, DMAC2.DMTMD 4000 5090h, DMAC3.DMTMD 4000 50D0h,
DMAC4.DMTMD 4000 5110h, DMAC5.DMTMD 4000 5150h, DMAC6.DMTMD 4000 5190h, DMAC7.DMTMD 4000 51D0h
b15
b14
MD[1:0]
Value after reset:
0
0
b13
b12
b11
b10
DTS[1:0]
—
—
0
0
0
0
b9
b8
SZ[1:0]
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
DCTG[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
DCTG[1:0]
Transfer Request
Source Select
b1 b0
R/W
0
0
1
1
0: Software
1: Interrupts*1 from peripheral modules or external interrupt input pins
0: Setting prohibited
1: Setting prohibited.
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b9, b8
SZ[1:0]
Transfer Data Size
Select
b9 b8
R/W
b11, b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13, b12
DTS[1:0]
Repeat Area Select
b13 b12
R/W
b15, b14
MD[1:0]
Transfer Mode Select
b15 b14
R/W
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0
0
1
1
0
0
1
1
0
0
1
1
0: 8 bits
1: 16 bits
0: 32 bits
1: Setting prohibited.
0: Specify destination as the repeat area or block area
1: Specify source as the repeat area or block area
0: Do not specify repeat area or block area
1: Setting prohibited.
0: Normal transfer
1: Repeat transfer
0: Block transfer
1: Setting prohibited.
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Note 1.
17. DMA Controller (DMAC)
To select the DMAC activation source, use the DELSRn registers of the ICU. For details on DMAC activation sources, see
Table 14.4, Event table in section 14, Interrupt Controller Unit (ICU).
DTS[1:0] bits (Repeat Area Select)
The DTS[1:0] bits select either the source or destination as the repeat area in repeat transfer mode and the block area in
block transfer mode. In normal transfer mode, these bit settings are invalid.
17.2.6
DMA Interrupt Setting Register (DMINT)
Address(es): DMAC0.DMINT 4000 5013h, DMAC1.DMINT 4000 5053h, DMAC2.DMINT 4000 5093h, DMAC3.DMINT 4000 50D3h,
DMAC4.DMINT 4000 5113h, DMAC5.DMINT 4000 5153h, DMAC6.DMINT 4000 5193h, DMAC7.DMINT 4000 51D3h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
DTIE
ESIE
0
0
0
0
0
b2
b1
b0
RPTIE SARIE DARIE
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DARIE
Destination Address Extended Repeat Area
Overflow Interrupt Enable
0: Disable
1: Enable.
R/W
b1
SARIE
Source Address Extended Repeat Area
Overflow Interrupt Enable
0: Disable
1: Enable.
R/W
b2
RPTIE
Repeat Size End Interrupt Enable
0: Disable
1: Enable.
R/W
b3
ESIE
Transfer Escape End Interrupt Enable
0: Disable
1: Enable.
R/W
b4
DTIE
Transfer End Interrupt Enable
0: Disable
1: Enable.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
DARIE bit (Destination Address Extended Repeat Area Overflow Interrupt Enable)
When an extended repeat area overflow occurs on the destination address when the DARIE bit is set to 1, the DTE bit in
DMCNT is set to 0. At the same time, the ESIF flag in DMSTS is set to 1 to indicate an interrupt request triggered by an
extended repeat area overflow on the destination address.
When block transfer mode is used with the extended repeat area function, an interrupt occurs after completion of a 1block size transfer. When the DTE bit is set to 1 in DMACm.DMCNT of the channel associated with the stopped
transfer, the transfer resumes from the state it was in when the transfer stopped. If the extended repeat area is not
specified for the destination address, this bit is ignored.
SARIE bit (Source Address Extended Repeat Area Overflow Interrupt Enable)
When an extended repeat area overflow occurs on the source address when the SARIE bit is set to 1, the DTE bit in
DMCNT clears to 0. At the same time, the ESIF flag in DMSTS is set to 1 to indicate an interrupt request triggered by an
extended repeat area overflow on the source address.
When block transfer mode is used with the extended repeat area function, an interrupt occurs after completion of a 1block size transfer. When the DTE bit is set to 1 in DMACm.DMCNT of the channel associated with the stopped
transfer, the transfer resumes from the state it was in when the transfer stopped.
When the extended repeat area is not specified for the source address, this bit is ignored.
RPTIE bit (Repeat Size End Interrupt Enable)
When the RPTIE bit is set to 1 in repeat transfer mode, the DTE bit in DMCNT clears to 0 after completion of a 1-repeat
size data transfer. At the same time, the ESIF flag in DMSTS is set to 1 to indicate that the repeat size end interrupt
request occurred. The repeat size end interrupt request can be generated even when the DTS[1:0] bits in DMTMD are
10b (repeat area or block area is not specified).
When the RPTIE bit is set to 1 in block transfer mode, the DTE bit in DMCNT clears to 0 after completion of a 1-block
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17. DMA Controller (DMAC)
data transfer in the same way as repeat transfer mode. At the same time, the ESIF flag in DMSTS is set to 1 to indicate
that the repeat size end interrupt request occurred. The repeat size end interrupt request can be generated even when the
DTS[1:0] bits in DMTMD are 10b (repeat area or block area is not specified).
ESIE bit (Transfer Escape End Interrupt Enable)
The ESIE bit enables the transfer escape end interrupt requests (repeat size end interrupt request and extended repeat area
overflow interrupt request) that occur during DMA transfer. The interrupt occurs when this bit is 1 and the ESIF flag in
DMSTS is set to 1. To clear the transfer escape end interrupt, clear this bit or the ESIF flag in DMSTS to 0.
DTIE bit (Transfer End Interrupt Enable)
The DTIE bit enables the transfer end interrupt request that occurs on completion of a specified number of data transfers.
The interrupt occurs when this bit is 1 and the DTIF flag in DMSTS is set to 1. To clear the transfer end interrupt, clear
this bit or the DTIF flag in DMSTS to 0.
17.2.7
DMA Address Mode Register (DMAMD)
Address(es): DMAC0.DMAMD 4000 5014h, DMAC1.DMAMD 4000 5054h, DMAC2.DMAMD 4000 5094h, DMAC3.DMAMD 4000 50D4h,
DMAC4.DMAMD 4000 5114h, DMAC5.DMAMD 4000 5154h, DMAC6.DMAMD 4000 5194h, DMAC7.DMAMD 4000 51D4h
b15
b14
SM[1:0]
Value after reset:
0
0
b13
b12
b11
—
0
b10
b9
b8
SARA[4:0]
0
0
0
b7
b6
DM[1:0]
0
0
0
0
b5
b4
b3
—
0
b2
b1
b0
0
0
DARA[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
DARA[4:0]
Destination Address Extended
Repeat Area
Specifies the extended repeat area on the destination address.
For details on the settings, see Table 17.2.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7, b6
DM[1:0]
Destination Address Update
Mode
b7
R/W
b12 to b8
SARA[4:0]
Source Address Extended
Repeat Area
Specifies the extended repeat area on the source address. For
details on the settings, see Table 17.2.
b13
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b15, b14
SM[1:0]
Source Address Update Mode
b15 b14
R/W
0
0
1
1
0
0
1
1
b6
0: Fixed address
1: Offset addition
0: Incremented address
1: Decremented address.
0: Fixed address
1: Offset addition
0: Incremented address
1: Decremented address.
R/W
DARA[4:0] bits (Destination Address Extended Repeat Area)
The DARA[4:0] bits specify the extended repeat area on the destination address. The extended repeat area function is
realized through an update of the specified lower address bits with the remaining upper address bits fixed. The size of the
extended repeat area can be any power of two between 2 bytes and 128 MB. The start address of the extended repeat area
is set when the lower address overflows the extended repeat area on an address increment. Similarly, the end address of
the extended repeat area is set when the lower address underflows the extended repeat area on an address decrement.
Do not specify the extended repeat area on the destination address when a repeat or block area is specified as the transfer
destination. When repeat or block transfer is selected, and when DMACm.DMTMD.DTS[1:0] = 00b (the transfer
destination is specified as the repeat or block area), write 00000b in the DARA[4:0] bits.
To request an interrupt when an overflow or underflow occurs in the extended repeat area, set the DARIE bit in DMINT
to 1. Table 17.2 lists the extended repeat areas associated with each setting.
DM[1:0] bits (Destination Address Update Mode)
The DM[1:0] bits select the update mode for the destination address.
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17. DMA Controller (DMAC)
When increment is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the destination address is
incremented by 1, 2, and 4, respectively
When decrement is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the destination address is
decremented by 1, 2, and 4, respectively
When offset addition is selected, the offset specified in the DMACm.DMOFR register is added to the address.
SARA[4:0] bits (Source Address Extended Repeat Area)
The SARA[4:0] bits specify the extended repeat area on the source address. The extended repeat area function is realized
through an update of the specified lower address bits with the remaining upper address bits fixed. The size of the
extended repeat area can be any power of two between 2 bytes and 128 MB. The start address of the extended repeat area
is set when the lower address overflows the extended repeat area on an address increment. Similarly, the end address of
the extended repeat area is set when the lower address underflows the extended repeat area on an address decrement.
Do not specify the extended repeat area on the source address when a repeat or block area is specified as the transfer
source. When repeat or block transfer is selected, and when DMACm.DMTMD.DTS[1:0] = 01b (the transfer source is
specified as the repeat or block area), write 00000b in the SARA[4:0] bits.
To request an interrupt when an overflow or underflow occurs in the extended repeat area, set the SARIE bit in DMINT
to 1. Table 17.2 lists the extended repeat areas associated with each setting.
SM[1:0] bits (Source Address Update Mode)
The SM[1:0] bits select the update mode for the source address:
When increment is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the source address is
incremented by 1, 2, and 4, respectively
When decrement is selected and the SZ[1:0] bits in DMTMD are set to 00b, 01b, and 10b, the source address is
decremented by 1, 2, and 4, respectively
When offset addition is selected, the offset specified in the DMACm.DMOFR register is added to the address.
.
Table 17.2
SARA[4:0] or DARA[4:0] settings and corresponding repeat areas (1 of 2)
SARA[4:0] or DARA[4:0]
Extended repeat area
00000b
Not specified
00001b
2 bytes specified as extended repeat area by the lower 1 bit of the address
00010b
4 bytes specified as extended repeat area by the lower 2 bits of the address
00011b
8 bytes specified as extended repeat area by the lower 3 bits of the address
00100b
16 bytes specified as extended repeat area by the lower 4 bits of the address
00101b
32 bytes specified as extended repeat area by the lower 5 bits of the address
00110b
64 bytes specified as extended repeat area by the lower 6 bits of the address
00111b
128 bytes specified as extended repeat area by the lower 7 bits of the address
01000b
256 bytes specified as extended repeat area by the lower 8 bits of the address
01001b
512 bytes specified as extended repeat area by the lower 9 bits of the address
01010b
1 KB specified as extended repeat area by the lower 10 bits of the address
01011b
2 KB specified as extended repeat area by the lower 11 bits of the address
01100b
4 KB specified as extended repeat area by the lower 12 bits of the address
01101b
8 KB specified as extended repeat area by the lower 13 bits of the address
01110b
16 KB specified as extended repeat area by the lower 14 bits of the address
01111b
32 KB specified as extended repeat area by the lower 15 bits of the address
10000b
64 KB specified as extended repeat area by the lower 16 bits of the address
10001b
128 KB specified as extended repeat area by the lower 17 bits of the address
10010b
256 KB specified as extended repeat area by the lower 18 bits of the address
10011b
512 KB specified as extended repeat area by the lower 19 bits of the address
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Table 17.2
17. DMA Controller (DMAC)
SARA[4:0] or DARA[4:0] settings and corresponding repeat areas (2 of 2)
SARA[4:0] or DARA[4:0]
Extended repeat area
10100b
1 MB specified as extended repeat area by the lower 20 bits of the address
10101b
2 MB specified as extended repeat area by the lower 21 bits of the address
10110b
4 MB specified as extended repeat area by the lower 22 bits of the address
10111b
8 MB specified as extended repeat area by the lower 23 bits of the address
11000b
16 MB specified as extended repeat area by the lower 24 bits of the address
11001b
32 MB specified as extended repeat area by the lower 25 bits of the address
11010b
64 MB specified as extended repeat area by the lower 26 bits of the address
11011b
128 MB specified as extended repeat area by the lower 27 bits of the address
11100b to 11111b
Setting prohibited
17.2.8
DMA Offset Register (DMOFR)
Address(es): DMAC0.DMOFR 4000 5018h, DMAC1.DMOFR 4000 5058h, DMAC2.DMOFR 4000 5098h, DMAC3.DMOFR 4000 50D8h,
DMAC4.DMOFR 4000 5118h, DMAC5.DMOFR 4000 5158h, DMAC6.DMOFR 4000 5198h, DMAC7.DMOFR 4000 51D8h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
Setting range
R/W
b31 to b0
Specifies the offset when offset addition is selected
as the address update mode for transfer source or
destination
0000 0000h to 00FF FFFFh (0 byte to (16 MB - 1 byte))
FF00 0000h to FFFF FFFFh (-16 MB to -1 byte)
R/W
Only write to this register while DMAC operation is stopped or DMA transfer is disabled, not during data transfer.
Setting bits [31:25] is invalid. The value in bit [24] is extended to bits [31:25]. Reading DMOFR returns the extended
value.
17.2.9
DMA Transfer Enable Register (DMCNT)
Address(es): DMAC0.DMCNT 4000 501Ch, DMAC1.DMCNT 4000 505Ch, DMAC2.DMCNT 4000 509Ch, DMAC3.DMCNT 4000 50DCh,
DMAC4.DMCNT 4000 511Ch, DMAC5.DMCNT 4000 515Ch, DMAC6.DMCNT 4000 519Ch, DMAC7.DMCNT 4000 51DCh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DTE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DTE
DMA Transfer Enable
0: Disable
1: Enable.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
DTE bit (DMA Transfer Enable)
The DTE bit enables DMA transfer. To enable DMA transfer, set the DMST bit in DMAST to 1 to enable DMAC
activation, then set the DTE bit to 1 to enable DMA transfer for the associated channel.
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17. DMA Controller (DMAC)
[Setting condition]
When 1 is written to this bit.
[Clearing conditions]
When 0 is written to this bit
When the specified volume of data transfer is complete
When DMA transfer is stopped by a repeat size end interrupt
When DMA transfer is stopped by an extended repeat area overflow interrupt.
17.2.10
DMA Software Start Register (DMREQ)
Address(es): DMAC0.DMREQ 4000 501Dh, DMAC1.DMREQ 4000 505Dh, DMAC2.DMREQ 4000 509Dh, DMAC3.DMREQ 4000 50DDh,
DMAC4.DMREQ 4000 511Dh, DMAC5.DMREQ 4000 515Dh, DMAC6.DMREQ 4000 519Dh, DMAC7.DMREQ 4000 51DDh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
CLRS
—
—
—
SWRE
Q
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SWREQ
DMA Software Start
0: DMA transfer is not requested
1: DMA transfer is requested.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
CLRS
DMA Software Start Bit Auto
Clear Select
0: SWREQ bit is cleared after DMA transfer is started by software
1: SWREQ bit is not cleared after DMA transfer is started by software.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
SWREQ bit (DMA Software Start)
Writing 1 to the SWREQ bit generates a DMA transfer request. After DMA transfer starts, SWREQ clears to 0 if the
CLRS bit is 0. SWREQ does not clear if CLRS bit is 1. The DMA transfer request can be issued again after the transfer
is complete.
Note:
Setting this bit is valid and DMA transfer by software is enabled only when the DCTG[1:0] bits in DMTMD are set
to 00b, specifying software as the DMA activation source. Setting this bit is invalid when the DCTG[1:0] bits in
DMTMD are set to any value other than 00b.
To start DMA transfer by software with the CLRS bit set to 0, ensure that the SWREQ bit is 0, then write 1 to the
SWREQ bit.
[Setting condition]
When 1 is written to this bit.
[Clearing conditions]
When a DMA transfer request by software is accepted and DMA transfer is started with the CLRS bit set to 0 (the
SWREQ bit is cleared after DMA transfer is started by software)
When 0 is written to this bit.
CLRS bit (DMA Software Start Bit Auto Clear Select)
When an SWREQ setting of 1 triggers a transfer request, the CLRS bit specifies whether to clear the SWREQ bit to 0
after DMA transfer starts. When the CLRS bit is set to 0, SWREQ clears to 0 after DMA transfer starts. When the CLRS
bit is set to 1, SWREQ does not clear to 0. A DMA transfer request can be issued again after the transfer is complete.
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17.2.11
17. DMA Controller (DMAC)
DMA Status Register (DMSTS)
Address(es): DMAC0.DMSTS 4000 501Eh, DMAC1.DMSTS 4000 505Eh, DMAC2.DMSTS 4000 509Eh, DMAC3.DMSTS 4000 50DEh,
DMAC4.DMSTS 4000 511Eh, DMAC5.DMSTS 4000 515Eh, DMAC6.DMSTS 4000 519Eh, DMAC7.DMSTS 4000 51DEh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
ACT
—
—
DTIF
—
—
—
ESIF
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ESIF
Transfer Escape End Interrupt
Flag
0: No interrupt occurred
1: Interrupt occurred.
R/W*1
b3 to b1
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
b4
DTIF
Transfer End Interrupt Flag
0: No interrupt occurred
1: Interrupt occurred.
R/W*1
b6, b5
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
b7
ACT
DMA Active Flag
0: DMAC operation suspended
1: DMAC operating.
R
Note 1.
Only 0 can be written to clear the flag.
ESIF flag (Transfer Escape End Interrupt Flag)
The ESIF flag indicates that a transfer escape end interrupt occurred.
[Setting conditions]
In repeat transfer mode, when one repeat size data transfer completes with the RPTIE bit in DMINT set to 1
In block transfer mode, when one block data transfer completes with the RPTIE bit in DMINT set to 1
When an extended repeat area overflow on the source address occurs with the SARIE bit in DMINT set to 1, and the
SARA[4:0] bits in DMAMD set to any value other than 00000b (extended repeat area is specified on the transfer
source address)
When an extended repeat area overflow on the destination address occurs with the DARIE bit in DMINT set to 1,
and the DARA[4:0] bits in DMAMD set to any value other than 00000b (extended repeat area is specified on the
transfer destination address).
[Clearing conditions]
When 0 is written to this flag
When 1 is written to the DTE bit in DMCNT.
DTIF flag (Transfer End Interrupt Flag)
The DTIF flag indicates that a transfer end interrupt occurred.
[Setting conditions]
In normal transfer mode, when the specified number of unit transfers completes (the value of DMCRAL becomes 0
on completion of transfer)
In repeat transfer mode, when the specified number of repeat transfer operations completes (the value of DMCRB
becomes 0 on completion of transfer)
In block transfer mode, when the specified number of blocks is transferred (the value of DMCRB becomes 0 on
completion of transfer).
[Clearing conditions]
When 0 is written to this flag
When 1 is written to the DTE bit in DMCNT.
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17. DMA Controller (DMAC)
ACT flag (DMA Active Flag)
The ACT flag indicates whether the DMAC is in the idle or active state.
[Setting condition]
When the DMAC starts a data transfer.
[Clearing condition]
When the data transfer in response to one transfer request completes.
17.2.12
DMAC Module Activation Register (DMAST)
Address(es): DMA.DMAST 4000 5200h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DMST
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DMST
DMAC Operation Enable
0: Disabled
1: Enabled.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
DMST bit (DMAC Operation Enable)
Setting the DMST bit to 1 enables DMAC activation for all channels. When the DMST bit is set to 1 (DMAC activation
is enabled), and 1 is written to the DMACm.DMCNT.DTE bit (DMA transfer is enabled) for multiple channels, all of the
associated channels can be placed in the transfer request ready state at the same time.
When the DMST bit clears to 0 during DMA transfer, DMA transfer is suspended after the current data transfer
associated with a single transfer request completes. To resume DMA transfer, set the DMST bit to 1 again.
[Setting condition]
When 1 is written to this bit.
[Clearing condition]
When 0 is written to this bit.
17.3
Operation
17.3.1
(1)
Transfer Mode
Normal transfer mode
In normal transfer mode, one data unit is transferred for one transfer request. You can specify the number of transfer
operations, up a maximum of 65,535, in DMACm.DMCRAL. When these bits are set to 0000h, no number of operations
is specified and data transfer is performed with the transfer counter stopped (free running mode). A transfer end interrupt
request can be generated after completion of the specified number of transfer operations, except when in free running
mode. Setting DMACm.DMCRB is invalid in normal transfer mode.
Table 17.3 summarizes the register update operation in normal transfer mode.
Table 17.3
Register update operation in normal transfer mode (1 of 2)
Register
Function
Update operation after completion of a transfer for one transfer request
DMACm.DMSAR
Transfer source address
Increment, decrement, fixed, or offset addition
DMACm.DMDAR
Transfer destination address
Increment, decrement, fixed, or offset addition
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Table 17.3
17. DMA Controller (DMAC)
Register update operation in normal transfer mode (2 of 2)
Register
Function
Update operation after completion of a transfer for one transfer request
DMACm.DMCRAL
Transfer count
Decremented by 1 or not updated (in free running mode)
DMACm.DMCRAH
-
Not updated (not used in normal transfer mode)
DMACm.DMCRB
-
Not updated (not used in normal transfer mode)
Figure 17.2 shows the operation in normal transfer mode.
Transfer source data area
Transfer destination data area
Data 1
Data 1
DMSAR
Transfer
Data 2
Figure 17.2
(2)
DMDAR
Data 2
Data 3
Data 3
Data 4
Data 4
Data 5
Data 5
Data 6
Data 6
Operation in normal transfer mode
Repeat transfer mode
In repeat transfer mode, one data unit is transferred for one transfer request. The repeat transfer size, up to a maximum of
1K data units, is set in DMACm.DMCRA. The number of repeat transfers, up to a maximum of 64K, is set in
DMACm.DMCRB. The total data transfer size can be set to a maximum of 64M data units (1K data units × 64K repeat
transfer operations).
You can specify either the transfer source or destination as a repeat area. When transfer of the repeat size data is
complete, the address of the specified repeat area (DMSAR or DMDAR in DMACm) returns to the transfer start address.
In this mode, when all data of the specified repeat size is transferred, DMA transfer can be stopped and a repeat size end
interrupt can be requested. To resume DMA transfer, write 1 to the DTE bit in DMACm.DMCNT during repeat size end
interrupt handling.
A transfer end interrupt request can be generated after completion of the specified number of repeat transfers.
Table 17.4 summarizes the register update operation in repeat transfer mode, and Figure 17.3 shows the operation in
repeat transfer mode.
Table 17.4
Register update operation in repeat transfer mode (1 of 2)
Update operation after completion of a transfer for one transfer request
Register
Function
When DMACm.DMCRAL is not 1
DMACm.DMSAR
Transfer source
address
Increment, decrement, fixed, or offset
addition
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When DMACm.DMCRAL is 1
(transfer of the last repeat size data unit)
DMACm.DMTMD.DTS[1:0] = 00b
Increment, decrement, fixed, or offset addition
DMACm.DMTMD.DTS[1:0] = 01b
Initial value of DMACm.DMSAR
DMACm.DMTMD.DTS[1:0] = 10b
Increment, decrement, fixed, or offset
addition.
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Table 17.4
17. DMA Controller (DMAC)
Register update operation in repeat transfer mode (2 of 2)
Update operation after completion of a transfer for one transfer request
When DMACm.DMCRAL is 1
(transfer of the last repeat size data unit)
Register
Function
When DMACm.DMCRAL is not 1
DMACm.DMDAR
Transfer
destination
address
Increment, decrement, fixed, or offset
addition
DMACm.DMCRAH
Repeat size
Not updated
Not updated
DMACm.DMCRAL
Transfer count
Decremented by one
DMACm.DMCRAH
DMACm.DMCRB
Count of repeat
transfer operations
Not updated
Decremented by 1
DMACm.DMTMD.DTS[1:0] = 00b
Initial value of DMACm.DMDAR
DMACm.DMTMD.DTS[1:0] = 01b
Increment, decrement, fixed, or offset addition
DMACm.DMTMD.DTS[1:0] = 10b
Increment, decrement, fixed, or offset
addition.
Transfer source data area
(Specified as repeat area)
Transfer destination data area
Data 1
Data 1
DMSAR
Data 2
Transfer
DMDAR
Data 2
Data 3
Data 3
Data 4
Data 4
Data 1
Data 2
Data 3
Data 4
Figure 17.3
(3)
Operation in repeat transfer mode
Block transfer mode
In block transfer mode, a single data block is transferred for one transfer request. The block size, up to a maximum of 1K
data units, is set in DMACm.DMCRA. The number of block transfers, up to a maximum of 64K, is set in
DMACm.DMCRB. A total data transfer size up to a maximum of 64M data units (1K data units × 64K block transfer
operations) can be set.
You can specify either the transfer source or destination as a block area. When transfer of a single data block is complete,
the address of the specified block area (DMSAR or DMDAR in DMACm) returns to the transfer start address. In this
mode, when all data in a single block is transferred, DMA transfer can be stopped and a repeat size end interrupt can be
requested. To resume DMA transfer, write 1 to the DTE bit in DMACm.DMCNT during repeat size end interrupt
handling.
A transfer end interrupt request can be generated after completion of the specified number of block transfers.
Table 17.5 summarizes the register update operation in block transfer mode, and Figure 17.4 shows the operation in
block transfer mode.
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Table 17.5
17. DMA Controller (DMAC)
Register update operation in block transfer mode
Update operation after completion of single-block transfer for one
transfer request
Register
Function
DMACm.DMSAR
Transfer source address
DMACm.DMTMD.DTS[1:0] = 00b
Increment, decrement, fixed, or offset addition
DMACm.DMTMD.DTS[1:0] = 01b
Initial value of DMACm.DMSAR
DMACm.DMTMD.DTS[1:0] = 10b
Increment, decrement, fixed, or offset addition.
DMACm.DMDAR
Transfer destination address
DMACm.DMTMD.DTS[1:0] = 00b
Initial value of DMACm.DMDAR
DMACm.DMTMD.DTS[1:0] = 01b
Increment, decrement, fixed, or offset addition
DMACm.DMTMD.DTS[1:0] = 10b
Increment, decrement, fixed, or offset addition.
DMACm.DMCRAH
Block size
Not updated
DMACm.DMCRAL
Transfer count
DMACm.DMCRAH
DMACm.DMCRB
Count of block transfer operations
Decremented by 1
Transfer source data area
DMSAR
First block
Transfer destination data area
(Specified as block area)
Transfer
Block area
DMDAR
Nth block
Figure 17.4
17.3.2
Operation in block transfer mode
Extended Repeat Area Function
The DMAC supports extended repeat areas on the transfer source and destination addresses, specified separately in the
transfer source address register (DMSAR) and transfer destination address register (DMDAR) of DMACm. When this
function is set, the address registers repeatedly indicate the addresses of the specified extended repeat areas.
The extended repeat area on the source address is specified in the SARA[4:0] bits in DMACm.DMAMD. The extended
repeat area on the destination address is specified in the DARA[4:0] bits in DMACm.DMAMD. You can specify
different sizes for the source and destination. However, you must not specify a transfer source or destination that is set as
the repeat or block area as the extended repeat area.
When the address register value reaches the end address of the extended repeat area and the extended repeat area
overflows, DMA transfer is stopped and an extended repeat area overflow interrupt can be requested. When an overflow
occurs in the extended repeat area on the transfer source while the SARIE bit in DMACm.DMINT is set to 1, the ESIF
flag in DMACm.DMSTS is set to 1 and the DTE bit in DMACm.DMCNT clears to 0 to stop DMA transfer. At this point,
if the ESIE bit in DMACm.DMINT is set to 1, an extended repeat area overflow interrupt is requested. When the DARIE
bit in DMACm.DMINT is set to 1, the destination address register becomes a target for the function. To resume DMA
transfer, write 1 to the DTE bit in DMACm.DMCNT during interrupt handling.
Figure 17.5 shows an example of the extended repeat area operation.
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17. DMA Controller (DMAC)
Example:
8 bytes are specified as an extended repeat area in the lower 3 bits of DMACm.DMSAR (SARA[4:0] bits in
DMACm.DMAMD = 00011b)
The data size is 8 bits (SZ[1:0] bits in DMACm.DMTMD = 00b)
Memory area
00013FFEh
DMSAR value
range
00013FFFh
00014000h
00014000h
00014001h
00014001h
00014002h
00014002h
00014003h
00014003h
00014004h
00014004h
00014005h
00014005h
00014006h
00014006h
00014007h
00014007h
00014008h
Repeat
An extended repeat area overflow interrupt
request can be generated
00014009h
Figure 17.5
Example of extended repeat area operation
When using extended repeat area overflow interrupts in block transfer mode, consider the following points:
When a transfer is stopped by an extended repeat area overflow interrupt, the address register must be set so that the
block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an
overflow on the extended repeat area occurs during a transfer of one block, the overflow interrupt is suspended until
transfer of the block is complete, and the transfer overruns.
Figure 17.6 shows an example of using the extended repeat area function in block transfer mode.
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17. DMA Controller (DMAC)
Example:
8 bytes are specified as an extended repeat area in the lower 3 bits of DMACm.DMSAR (SARA[4:0] bits in DMACm.DMAMD
= 00011b)
Block transfer mode with block size 5 is set (DMACm.DMCRA = 00050005h)
The transfer source address is not specified as a block area
The data size is 8 bits (SZ[1:0] bits in DMACm.DMTMD = 00b)
Memory area
Repeated
DMSAR value
range
First block transfer
Second block
transfer
00014000h
00014000h
00014000h
00014000h
00014001h
00014001h
00014001h
00014001h
00014002h
00014002h
00014002h
00014003h
00014003h
00014003h
00014004h
00014004h
00014004h
00014005h
00014005h
00014005h
00014006h
00014006h
00014006h
00014007h
00014007h
00014007h
00013FFEh
00013FFFh
Interrupt request
generated
00014008h
Block transfer
continued
00014009h
Figure 17.6
17.3.3
Example of extended repeat area function in block transfer mode
Address Update Function Using Offset
The source and destination addresses can be updated by fixing, incrementing, decrementing, or adding an offset. When
offset addition is selected, the offset specified in the DMA Offset Register (DMACm.DMOFR) is added to the address
every time the DMAC performs one data transfer. You can also subtract an offset by setting a negative value in
DMACm.DMOFR. The negative value must be in two’s complement.
Table 17.6 shows the address update method in each address update mode.
Table 17.6
Address update method in each address update mode
Address update
mode
Settings of
DMACm.DMAMD.SM[1:0] and
DMACm.DMAMD.DM[1:0] for
address update modes
Address update method for different SZ[1:0] settings in
DMACm.DMTMD
SZ[1:0] = 00b
SZ[1:0] = 01b
SZ[1:0] = 10b
Address fixed
00b
Fixed
Offset addition
01b
+DMACm.DMOFR*1
Increment
10b
+1
+2
+4
Decrement
11b
-1
-2
-4
Note 1.
(1)
When setting a negative value in the DMA Offset Register, the value must be in two’s complement, obtained by the following
formula:
two’s complement of a negative offset value = ~ (offset) + 1 (~ = bit inversion)
Basic transfer using offset addition
Figure 17.7 shows an example of address updating using offset addition.
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17. DMA Controller (DMAC)
Transfer
Data 1
Address A1
Offset value
Data 2
Address A2
= address A1 + offset value
Data 3
Address A3
= address A2 + offset value
Data 4
Address A4
= address A3 + offset value
Data 1
Address B1
Data 2
Address B2 = address B1 + 4
Data 3
Address B3 = address B2 + 4
Data 4
Address B4 = address B3 + 4
Data 5
Address B5 = address B4 + 4
Offset value
Offset value
Offset value
Data 5
Figure 17.7
Address A5
= address A4 + offset value
Transfer source: Offset addition
Transfer destination: Increment
Data size: 32 bits
Example of address updating through offset addition
In Figure 17.7:
The transfer data is 32 bits long
Offset addition is set as the transfer source address update mode
Increment is set as the transfer destination address update mode.
The second and subsequent data units are each read from the source address obtained by adding the offset value to the
previous address. The data read from the addresses at the specified intervals is written to continuous locations on the
destination.
(2)
Example of XY conversion using offset addition
Figure 17.8 shows XY conversion using offset addition in repeat transfer mode. The settings are as follows:
DMAC0.DMAMD — Transfer source address update mode: offset addition
DMAC0.DMAMD — Transfer destination address update mode: destination address is incremented
DMAC0.DMTMD — Transfer data size select: 32 bits
DMAC0.DMTMD — Transfer mode select: repeat transfer
DMAC0.DMTMD — Repeat area select: the source is specified as the repeat area
DMAC0.DMOFR — Offset address: 10h
DMAC0.DMCRA — Repeat size: 4h
DMAC0.DMINT — The repeat size end interrupt is enabled.
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Offset value
Offset value
Offset value
S5D5 User’s Manual
17. DMA Controller (DMAC)
Data 5
Data 9
Data 13
Data 1
Data 2
Data 3
Data 2
Data 6
Data 10
Data 14
Second cycle
Data 5
Data 6
Data 7
Data 8
Data 3
Data 7
Data 11
Data 15
Third cycle
Data 9
Data 10
Data 11
Data 12
Data 4
Data 8
Data 12
Data 16
Fourth cycle
Data 13
Data 14
Data 15
Data 16
Transfer
Data 4
Transfer
source
Third cycle
address written
by CPU
First cycle
Second cycle
Data 1
Data 1
Data 1
Data 5
Data 5
Data 2
Data 9
Data 3
Data 5
Address
returned
Address
returned
Transfer
Data 1
Data 9
Data 9
Data 13
Data 13
Data 13
Data 2
Data 2
Data 2
Data 6
Data 6
Data 6
Data 6
Data 10
Data 10
Data 10
Data 7
Data 14
Data 14
Data 14
Data 8
Data 3
Data 3
Data 3
Data 9
Transfer source
address written by
CPU
Data 5
Data 7
Data 7
Data 7
Data 10
Data 11
Data 11
Data 11
Data 15
Data 15
Data 15
Data 12
Data 4
Data 4
Data 4
Data 13
Data 8
Data 8
Data 14
Data 12
Data 15
Data 12
Interrupt
request
generated
Data 16
Data 12
Data 16
Interrupt
request
generated
Data 16
Interrupt
request
generated
First
cycle
Data 4
Data 11
Data 8
Figure 17.8
First
cycle
Data 1
Second
cycle
Third
cycle
Fourth
cycle
Data 16
XY conversion operation using offset addition in repeat transfer mode
When a transfer starts, the offset value is added to the transfer source address every time data is transferred. The transfer
data is written to continuous destination addresses. When data 4 is transferred:
The repeat size of the transfers is complete
The transfer source address returns to the transfer start address (the address of data 1 on the transfer source)
A repeat size end interrupt is requested.
During the time this interrupt pauses the transfer, perform the following:
DMAC0.DMSAR — Rewrite the DMA transfer source address to the address of data 5
(in this example, the data 1 address + 4)
DMAC0.DMCNT — Set the DTE bit to 1.
The DMA transfer resumes from the state when the DMA transfer was stopped. The same operations are repeated until
the transfer source data is transposed to the destination area (XY conversion).
Figure 17.9 shows a flow of the XY conversion.
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17. DMA Controller (DMAC)
Start
Set the address, repeat size, and number of repeat
operations
Set repeat transfer mode
Enable repeat size end interrupts
Write 1 to the DTE bit in DMAC0.DMCNT
Receive transfer request
Transfer data
Decrement repeat size and number of repeat operations
No
Number of repeat operations = 0?
Yes
Repeat size = 0?
No
Yes
Return to transfer source address
Generate repeat size end interrupt
Set “transfer source address + 4”
(When transfer data size = 32 bits)
End
: User processing
: DMAC processing
Figure 17.9
17.3.4
XY conversion flow using offset addition in repeat transfer mode
Activation Sources
Software, interrupt requests from the peripheral modules, and external interrupt requests can all be specified as DMAC
activation sources. Set the DCTG[1:0] bits in DMACm.DMTMD to select the activation source.
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(1)
17. DMA Controller (DMAC)
DMAC activation through software
To start DMA transfer through software:
1. Set the DCTG[1:0] bits in DMACm.DMTMD to 00b.
2. Set the DTE bit in DMACm.DMCNT to 1 (enable DMA transfer).
3. Set the DMST bit in DMAST to 1 (enable DMAC activation).
4. Set the SWREQ bit in DMACm.DMREQ to 1 (request DMA).
When the DMAC is activated by software while the CLRS bit in DMACm.DMREQ is 0, the SWREQ bit in
DMACm.DMREQ clears to 0 after data transfer starts in response to a DMA transfer request.
When the DMAC is activated by software while the CLRS bit is 1, SWREQ does not clear to 0 after data transfer starts.
A DMA transfer request is issued again after completion of a transfer.
(2)
DMAC activation through interrupt requests from on-chip peripheral modules or external
interrupt requests
You can specify interrupt requests from on-chip peripheral modules and external interrupt requests as DMAC activation
sources. The activation source can be individually selected for each channel in ICU.DELSRn.DELS[8:0] (n = 0 to 7).
To start DMAC transfer through an interrupt request from an on-chip peripheral module or an external interrupt request:
1. Set the DCTG[1:0] bits in DMACm.DMTMD to 01b (select interrupts from the peripheral modules and the external
interrupt pins).
2. Set the DTE bit in DMACm.DMCNT to 1 (enable DMA transfer).
3. Set ICU.DELSRn.DSEL to the event number (select the DMAC event link).
4. Set the DMST bit in DMAST to 1 (enable DMAC activation).
For interrupt requests specified as DMAC activation sources, see Table 14.3, Interrupt vector table in section 14,
Interrupt Controller Unit (ICU).
17.3.5
Operation Timing
The following timing diagrams show the minimum number of execution cycles.
System clock
Peripheral module or
external pin interrupts
DMAC activation
request
DMAC access
R
W
Data transfer
Figure 17.10
R
W
Data transfer
DMAC operation timing example 1 with DMA activation by interrupt from peripheral module or
external interrupt input pin, in normal transfer mode or repeat transfer mode
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17. DMA Controller (DMAC)
System clock
Peripheral module or
external pin interrupt
DMAC activation
request
DMAC access
Data transfer
Figure 17.11
17.3.6
DMAC operation timing example 2 with DMA activation by interrupt from peripheral module or
external interrupt input pin, in block transfer mode with block size = 4
Execution Cycles of DMAC
Table 17.7 lists the execution cycles in one DMAC data transfer operation.
Table 17.7
DMAC execution cycles
Transfer mode
Data transfer (read)
Data transfer (write)
Normal
Cr+Cs+1
Cw+Cs
Repeat
Cr+Cs+1
Cw+Cs
Block*1
P × (Cr+Cs)
P × (Cw+Cs)
Note:
Note 1.
P = Block size (DMCRAH register setting).
Cr = Read destination access cycle.
Cw = Data write destination access cycle.
Cs = When accessing SRAMHS and peripheral modules related to system control: 2 cycles.
When accessing elsewhere: 0 cycles.
When a slave bus changes by a read/write data transfer, add 1 more cycle.
This is the case when the block size is 2 or more. When the block size is 1, normal transfer cycle applies.
Cr and Cw depend on the access destination. For the number of cycles of each access destination, see section 51, SRAM,
section 53, Flash Memory, and section 15.2.3, External Bus. The frequency ratio of the system clock and the peripheral
clock is also taken into consideration.
The unit for +1 in the data transfer (read) column is 1 system clock cycle, ICLK. For the operation example, see section
17.3.5, Operation Timing.
The DMAC response time is the time from when the DMAC activation source is detected until the DMAC transfer starts.
Table 17.7 does not include the time until the DMAC data transfer starts after the DMAC activation source becomes
active.
17.3.7
Activating the DMAC
Figure 17.12 shows the register setting procedure.
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17. DMA Controller (DMAC)
Initial settings
To use peripheral function
interrupts as DMA activation
sources
Disable the peripheral function as the DMACm
request source
To use external pin interrupts as
DMA activation sources
Disable the IRQ pin as the DMACm request
source
Set the DMACm Event Link Select
(ICU.DELSRm.DELS[8:0]) to 0
Disable the DMACm request
Clear the DTE bit in DMACm.DMCNT to 0.
Disable DMACm transfers
The interrupt must be enabled in NVIC.
To use on-chip peripheral or
external pin interrupts as DMA
activation sources
Disable the control register for the peripheral function
Set the interrupt request as a DMACm request
source in the DMACm Event Link Setting Register
(ICU.DELSRm) using the ICU.
Enable the interrupt bit for the activation source
Set the DMACm activation source
To use peripheral module
interrupts as DMA activation
sources
Set the peripheral module as a DMACm request
source
Set the control register for the peripheral function without
starting it
To use external pin interrupts as
DMA activation sources
Set the IRQ pin function using the ICU
Set the IRQ pin function without enabling it
DM[1:0] bits in DMACm.DMAMD
SM[1:0] bits in DMACm.DMAMD
DARA[4:0] bits in DMACm.DMAMD
SARA[4:0] bits in DMACm.DMAMD
Transfer destination address update mode bits
Transfer source address update mode bits
Destination address extended repeat area bits
Source address extended repeat area bits
DCTG[1:0] bits in DMACm.DMTMD
SZ[1:0] bits in DMACm.DMTMD
DTS[1:0] bits in DMACm.DMTMD
MD[1:0] bits in DMACm.DMTMD
Transfer request select bits
Data transfer size bits
Repeat area select bits
Transfer mode select bits
DMACm.DMSAR
Set the transfer source start address
DMACm.DMDAR
Set the transfer destination start address
DMACm.DMCRA
Set the number of transfer operations
(To use block transfer mode or repeat transfer mode)
Set the number of block transfer operations
DMACm.DMCRB
(To use the address update function with offset)
DMACm.DMOFR
Set the offset value
(To use DMA transfer end interrupts)
Set 1 to DTIE bit in DMACm.DMINT
Enable DMACm transfer end interrupts
(To use DMA transfer escape interrupts)
RPTIE bit in DMACm.DMINT
SARIE bit in DMACm.DMINT
DARIE bit in DMACm.DMINT
Set the ESIE bit in DMACm.DMINT to 1
Set repeat size end interrupts.
Set the DTE bit in DMACm.DMCNT to 1
Enable DMACm transfers
Set the DMST bit in DMAST to 1
Enable DMAC operation*1
To use peripheral function
interrupts as DMA activation
sources
Start the peripheral function as a DMACm request
source
To use external pin interrupts as
DMA activation sources
Enable the IRQ pin as a DMACm request source
End
m: DMAC channel (m = 0 to 7)
Note 1.
Set transfer source address extended repeat area overflow interrupts .
Set transfer destination address extended repeat area overflow interrupts .
Enable DMA transfer escape end interrupts.
Common settings for DMAC
For activation by software
On completion of the initial settings, write 1 to the DMA software start
bit (DMACm.DMREQ.SWREQ) to start DMA transfer
Setting of the DMAST.DMST bit does not necessarily have to follow the settings for the individual activation sources.
Figure 17.12
Register setting procedure
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17.3.8
17. DMA Controller (DMAC)
Starting DMA Transfer
To enable a DMA transfer of channel m, set the DTE bit in DMACm.DMCNT to 1 (DMA transfer enabled) and set the
DMST bit in DMAST to 1 (DMAC activation enabled). New activation requests are not accepted during the transfer of
another DMAC channel or DTC. When the proceeding transfer is complete, channel arbitration selects the DMA transfer
request of the highest priority channel, and DMA transfer of that channel starts. When DMA transfer starts, the ACT flag
in DMACm.DMSTS is set to 1 (the DMAC is in the active state).
17.3.9
Registers during DMA Transfer
The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and
the transfer state. The registers that are updated are DMSAR, DMDAR, DMCRA, DMCRB, DMCNT, and
DMACm.DMSTS, described in the following sections. For details on register update operations in each transfer mode,
see Table 17.3 to Table 17.5.
(1)
DMA Source Address Register (DMACm.DMSAR)
After the data for one transfer request is transferred, the contents of DMSAR are updated to the address to be accessed by
the next transfer request.
(2)
DMA Destination Address Register (DMACm.DMDAR)
After the data for one transfer request is transferred, the contents of DMDAR are updated to the address to be accessed
by the next transfer request.
(3)
DMA Transfer Count Register (DMACm.DMCRA)
After the data for one transfer request is transferred, the count value is updated. The update operation depends on the
transfer mode selected.
(4)
DMA Block Transfer Count Register (DMACm.DMCRB)
After the data for one transfer request is transferred, the count value is updated. The update operation depends on the
transfer mode selected.
(5)
DMA Transfer Enable bit (DMACm.DMCNT.DTE)
The DMACm.DMCNT.DTE bit enables or disables data transfer through register write access. It is automatically cleared
to 0 by the DMAC based on the DMA transfer state.
The conditions for clearing this bit by the DMAC are as follows:
When the specified total volume of data transfer is complete
When DMA transfer is stopped by a repeat size end interrupt
When DMA transfer is stopped by an extended repeat area overflow interrupt.
Writing to the registers for channels whose associated DMACm.DMCNT.DTE bit is set to 1 is prohibited except for
DMACm.DMCNT. Writes are only possible after the bit clears to 0.
(6)
DMA Active flag (DMACm.DMSTS.ACT)
The ACT flag in DMSTS of DMACm indicates whether the DMACm is in the idle or active state. This flag is set to 1
when the DMAC starts data transfer, and clears to 0 when data transfer for one transfer request is complete. Even when
DMA transfer is stopped by write of 0 to the DTE bit in DMACm.DMCNT, this flag remains 1 until DMA transfer is
complete.
(7)
Transfer End Interrupt Flag (DMACm.DMSTS.DTIF)
The DTIF flag in DMACm.DMSTS is set to 1 after DMA transfer of the total transfer size is complete. When both this
flag and the DTIE bit in DMACm.DMINT are 1, a transfer end interrupt is requested. This flag is set to 1 when the DMA
transfer bus cycle is complete and the ACT flag in DMACm.DMSTS clears to 0, indicating the DMA transfer end. The
flag automatically clears to 0 when the DTE bit in DMACm.DMCNT is set to 1 during interrupt handling.
(8)
Transfer Escape End Interrupt Flag (DMACm.DMSTS.ESIF)
The ESIF flag in DMACm.DMSTS is set to 1 when a repeat size end interrupt or extended repeat area overflow interrupt
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17. DMA Controller (DMAC)
is requested. When this bit and the ESIE bit in DMACm.DMINT are 1, a transfer escape end interrupt is requested. This
flag is set to 1 when the bus cycle of the DMA transfer that caused the interrupt request is complete and the ACT flag in
DMACm.DMSTS clears to 0, indicating the DMA transfer end. The flag automatically clears to 0 when the DTE bit in
DMACm.DMCNT is set to 1 during interrupt handling.
You must set the interrupt control register before sending an interrupt request from the DMAC to the CPU or the DTC.
For more information, see section 14, Interrupt Controller Unit (ICU).
17.3.10
Channel Priority
When multiple DMA transfer requests occur, the DMAC determines the priority of channels that have DMA transfer
requests.
The priority is fixed as channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7.
(channel 0 is the highest.)
When a DMA transfer request occurs during data transfer, channel arbitration starts after the final data unit is transferred,
and DMA transfer of the highest-priority channel starts.
17.4
Ending DMA Transfer
The operation for ending a DMA transfer depends on the transfer end conditions. When a DMA transfer ends, the DTE
bit in DMCNT and the ACT flag in DMACm.DMSTS change from 1 to 0.
17.4.1
(1)
Transfer End by Completion of Specified Total Number of Transfer Operations
In normal transfer mode (DMACm.DMTMD.MD[1:0] = 00b)
When the value of DMACm.DMCRAL changes from 1 to 0, DMA transfer ends on the associated channel, the DTE bit
in DMACm.DMCNT clears to 0, and the DTIF flag in DMACm.DMSTS is set to 1. If the DTIE bit in DMACm.DMINT
is 1 at this time, a transfer end interrupt request is sent to the CPU or the DTC.
(2)
In repeat transfer mode (DMACm.DMTMD.MD[1:0] = 01b)
When the value of DMACm.DMCRB changes from 1 to 0, DMA transfer ends on the associated channel, the DTE bit in
DMACm.DMCNT clears to 0, and the DTIF flag in DMACm.DMSTS is set to 1. If the DTIE bit in DMACm.DMINT is
1 at this time, an interrupt request is sent to the CPU or the DTC.
(3)
In block transfer mode (DMACm.DMTMD.MD[1:0] = 10b)
When the value of DMACm.DMCRB changes from 1 to 0, DMA transfer ends on the associated channel, the DTE bit in
DMACm.DMCNT clears to 0, and the DTIF flag in DMACm.DMSTS is set to 1. If the DTIE bit in DMACm.DMINT is
1 at this time, an interrupt request is sent to the CPU or the DTC.
You must set the interrupt control register before sending an interrupt request from the DMAC to the CPU or the DTC.
For more information, see section 14, Interrupt Controller Unit (ICU).
17.4.2
Transfer End by Repeat Size End Interrupt
In repeat transfer mode, if the RPTIE bit in DMACm.DMINT is 1, a repeat size end interrupt is requested when transfer
of a single repeat size of data is complete. The DTE bit in DMACm.DMCNT clears to 0 and the ESIF flag in
DMACm.DMSTS is set to 1. If the ESIE bit in DMACm.DMINT is 1 at this time, an interrupt request is sent to the CPU
or the DTC. To resume the transfer, write 1 to the DTE bit in DMACm.DMCNT.
A repeat size end interrupt can also be requested in block transfer mode. When transfer of a single block size of data is
complete, the interrupt is requested in the same way as in repeat transfer mode.
You must set the interrupt control register before sending an interrupt request from the DMAC to the CPU or the DTC.
For more information, see section 14, Interrupt Controller Unit (ICU).
17.4.3
Transfer End by Interrupt on Extended Repeat Area Overflow
When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or
DARIE bit in DMACm.DMINT is 1, an extended repeat area overflow interrupt is requested. The DMA transfer is
terminated, the DTE bit in DMACm.DMCNT clears to 0, and the ESIF flag in DMACm.DMSTS is set to 1. If the ESIE
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17. DMA Controller (DMAC)
bit in DMACm.DMINT is 1 at this time, an interrupt request is sent to the CPU or the DTC.
If this interrupt is requested during a read cycle, the subsequent write cycle is performed. In block transfer mode, if the
interrupt is requested during a 1-block transfer, the remaining data in the block is transferred before transfer stops.
Before sending an interrupt request from the DMAC to the CPU or the DTC, the interrupt control register must be set.
For more information, see section 14, Interrupt Controller Unit (ICU).
17.4.4
Precautions for the End of DMA Transfer
A DMA activation request source might occur in the next request after a DMA transfer completes. If this happens, the
DMA transfer starts and the DMA activation request is held in DMAC. To prevent this, stop the DMA activation requests
by clearing the DELSRn.DSELS[8:0] bits in the ICU to 0.
When the DMA activation request occurs after the last round of the DMA transfer is generated, clear the DMA activation
request by setting ICU.DELSRm.IR bit to 0.
17.5
Interrupts
Each DMAC channel can output an interrupt request (DMACm_INT) to the CPU or DTC after transfer for one request is
complete. When the transfer destination is the external bus, an interrupt request is generated after completion of a data
write to the write buffer, and not to the actual transfer destination.
Table 17.8 lists the interrupt sources and their associated status flags and enable bits. Figure 17.13 shows the schematic
logic diagram of the interrupt outputs (DMAC0 to DMAC7). Figure 17.14 shows the DMAC interrupt handling routine
for resuming and terminating DMA transfers.
Table 17.8
Association between interrupt sources, interrupt status flags, and interrupt enable bits
Interrupt sources
Interrupt enable bits
Interrupt status flags
Request output enable bits
Transfer end
—
DMACm.DMSTS.DTIF
DMACm.DMINT.DTIE
Repeat size end
DMACm.DMINT.RPTIE
DMACm.DMSTS.ESIF
DMACm.DMINT.ESIE
Source address extended repeat
area overflow
DMACm.DMINT.SARIE
Destination address extended
repeat area overflow
DMACm.DMINT.DARIE
Escape
transfer end
DTIE
DTIF
When the specified number of data
transfer operations are complete
1-setting condition
DMACm interrupt request
RPTIE
ESIE
When the specified repeat (or block)
size of data transfer is complete
ESIF
SARIE
1-setting condition
When a source address extended
repeat area overflow occurs
DARIE
When a destination address extended
repeat area overflow occurs
Figure 17.13
Interrupt output logic diagram for DMAC channel m (DMACm)
m = 0 to 7
Schematic logic diagram of interrupt outputs for DMAC0 to DMAC7
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17. DMA Controller (DMAC)
Different procedures are used for canceling an interrupt to restart a DMA transfer in the following cases:
When terminating a DMA transfer
When continuing a DMA transfer.
(1)
When terminating a DMA transfer
Write 0 to the DTIF flag in DMACm.DMSTS to clear a transfer end interrupt, and to the ESIF flag in DMACm.DMSTS
to clear a repeat size interrupt or an extended repeat area overflow interrupt. DMACm remains in the stopped state. When
starting another DMA transfer, set the appropriate registers and set the DTE bit in DMACm.DMCNT to 1 (DMA transfer
enabled).
(2)
When continuing a DMA transfer
Write 1 to the DTE bit in DMACm.DMCNT. The ESIF flag in DMSTS of DMACm automatically clears to 0 (interrupt
source cleared), and the DMA transfer resumes.
Start of DMAC interrupt handling
Continue
Terminate
Continue suspended transfer?
Change register settings if necessary
Write 1 to DTE bit in DMACm.DMCNT
Write 0 to ESIF or DTIF bit in DMACm.DMSTS
(interrupt source cleared)
Discontinue
Perform another data transfer?
End
Start another transfer
ESIF bit in DMACm.DMSTS clears automatically
(interrupt source cleared)
Change register settings
Transfer resumed
Write 1 to DTE bit in DMACm.DMCNT
DMA transfer restarted
(start of another DMA transfer)
Figure 17.14
17.6
DMAC interrupt handling routine to resume or terminate a DMA transfer
Event Link
Each DMAC channel outputs an event link request signal (DMACm_INT) every time it completes a data transfer, or a
block transfer in block transfer mode. When the transfer destination is the external bus, the signal is generated when
writing to the write buffer is accepted. For more information, see section 19, Event Link Controller (ELC).
17.7
Low Power Consumption Function
Before entering the module-stop state, Software Standby mode, or Deep Software Standby mode, you must first clear the
DMST bit in DMAST to 0 (DMAC suspended) and use the settings in the sections that follow.
(1)
Module-stop function
Writing 1 to the MSTPA22 bit in MSTPCRA enables the module-stop function of the DMAC. If a DMA transfer is in
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17. DMA Controller (DMAC)
progress when 1 is written to MSTPA22, the transition to the module-stop state continues after DMA transfer ends.
Access to the DMAC registers is prohibited while MSTPA22 is 1. Writing 0 to the MSTPA22 bit releases the DMAC
from the module-stop state.
(2)
Software Standby and Deep Software Standby modes
Use the settings described in section 11.7.1, Transition to Software Standby Mode and section 11.9.1, Transition to Deep
Software Standby Mode.
If DMA transfer operations are in progress when the WFI instruction is executed, the DMA transfer completes before the
transition to Software Standby mode or Deep Software Standby mode.
(3)
Notes on the low power consumption function
For information on the WFI instruction and register settings, see section 11.10.7, Timing of WFI Instruction.
To perform a DMA transfer after returning from a low power consumption mode, set the DMST bit in DMAST to 1
again. To use a request that is generated in Software Standby mode as an interrupt request to the CPU but not as a DMAC
startup request, specify the CPU as the interrupt request destination, as described in section 14.4.2, Selecting Interrupt
Request Destinations, then execute the WFI instruction.
17.8
Usage Notes
17.8.1
DMA Transfer to External Devices
In a DMA transfer to an external device, the ACT flag in DMACm.DMSTS may be set to 0 (DMAC transfer suspended)
from the beginning of the final data write to the end of the external bus access.
17.8.2
Access to Registers during DMA Transfer
Do not write to the following registers of DMACm while the ACT flag in DMSTS of the associated channel is set to 1
(DMAC active state) or the DTE bit in DMCNT of the associated channel is set to 1 (DMA transfer enabled):
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
DMAMD
DMOFR.
17.8.3
DMA Transfer to Reserved Areas
DMA transfer to reserved areas is prohibited. If such an access is made, transfer results are not guaranteed. For details on
reserved areas, see section 4, Address Space.
17.8.4
Setting the DMAC Event Link Setting Register of the Interrupt Controller Unit
(ICU.DELSRn)
Before setting the DMAC Event Link Setting Register (ICU.DELSRn), make sure the DMA Transfer Enable bit
(DMACm.DMCNT.DTE) is set to 0, disabling DMA transfer. Additionally, ensure that the DTC activation enable
register (ICU.IELSRn.DTCE) associated with the event number set in the ICU.DELSRn register is not set to 1. For
details on ICU.IELSRn.DTCE and ICU.DELSRn, see section 14, Interrupt Controller Unit (ICU).
17.8.5
Suspending or Restarting DMA Activation
To suspend a DMA activation request, write 0 to the DMAC Event Link Select bits (ICU.DELSRn.DELS[8:0]). To
restart the DMA transfer, write the event number to the ICU.DELSRn.DELS[8:0] bit with the settings shown in section
17.3.7, Activating the DMAC.
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18. Data Transfer Controller (DTC)
18.
Data Transfer Controller (DTC)
18.1
Overview
The MCU includes a Data Transfer Controller (DTC) that performs data transfers when activated by an interrupt request.
Table 18.1 lists the DTC specifications and Figure 18.1 shows a block diagram.
Table 18.1
DTC specifications
Parameter
Specifications
Transfer modes
Normal transfer mode
A single activation leads to a single data transfer.
Repeat transfer mode
A single activation leads to a single data transfer.
The transfer address returns to the start address after the number of data transfers reaches the
specified repeat size.
The maximum number of repeat transfers is 256 and the maximum data transfer size is 256 ×
32 bits (1024 bytes).
Block transfer mode
A single activation leads to a transfer of a single block.
The maximum block size is 256 × 32 bits = 1024 bytes.
Transfer channel
Channel transfer can be associated with the interrupt source (transferred by a DTC activation
request from the ICU)
Multiple data units can be transferred on a single activation source (chain transfer)
Chain transfers can be set to either execute when the counter is 0 or always execute
Transfer space
4 GB (0000 0000h to FFFF FFFFh, excluding reserved areas)
Data transfer units
Single data unit: 1 byte (8 bits), 1 halfword (16 bits), or 1 word (32 bits)
Single block size: 1 to 256 data units
CPU interrupt source
An interrupt request can be generated to the CPU on a DTC activation interrupt
An interrupt request can be generated to the CPU after a single data transfer
An interrupt request can be generated to the CPU after a data transfer of a specified volume.
Event link function
An event link request is generated after one data transfer (for block, after one block transfer)
Read skip
Read of transfer information can be skipped
Write-back skip
When the transfer source or destination address is specified as fixed, a write-back of transfer
information can be skipped
Module-stop function
Module-stop state can be set to reduce power consumption
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18. Data Transfer Controller (DTC)
CPU
Non-maskable interrupt request
Interrupt request
NVIC
Activation request
DMAC response
DMAC
Snooze control signals
System
DTC_DTCEND
ELC
Interrupt
controller
DTC
MRA
MRB
Vector number
CRA
CRB
SAR
DAR
Activation request
Activation
control
DTC internal bus
Register
control
DTC response
DTCCR
DTCVBR
DTCST
Bus interface
DTC
response
control
DTCSTS
Internal peripheral bus 1
System bus
DMA bus
MRA:
MRB:
CRA:
CRB:
SAR:
DAR:
DTCCR:
DTCVBR:
DTCST:
DTCSTS:
Figure 18.1
DMA bus
Code FCU
flash data
flash
SRAMHS
Transfer
information
SRAM0
Transfer
information
Internal
Standby SRAM
peripheral buses
Transfer
information
External
memory
interface
External device
interface
DTC Mode Register A
DTC Mode Register B
DTC Transfer Count Register A
DTC Transfer Count Register B
DTC Transfer Source Register
DTC Transfer Destination Register
DTC Control Register
DTC Vector Base Register
DTC Module Start Register
DTC Status Register
DTC block diagram
See 14.1 Overview, in section 14, Interrupt Controller Unit (ICU), for the connections between the DTC and NVIC in the
CPU.
18.2
Register Descriptions
MRA, MRB, SAR, DAR, CRA, and CRB are all DTC internal registers that cannot be directly accessed from the CPU.
Values to be set in these DTC internal registers are placed in the SRAM area as transfer information. When an activation
request is generated, the DTC reads the transfer information from the SRAM area and sets it in its internal registers. After
the data transfer ends, the internal register contents are written back to the SRAM area as transfer information.
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18.2.1
18. Data Transfer Controller (DTC)
DTC Mode Register A (MRA)
Address(es): (Inaccessible directly from the CPU. See section 18.3.1.)
b7
b6
b5
MD[1:0]
x
Value after reset:
x
b4
SZ[1:0]
x
b3
b2
SM[1:0]
x
x
x
b1
b0
—
—
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as undefined. The write value should be 0. —
b3, b2
SM[1:0]
Transfer Source Address Addressing
Mode
b3 b2
—
b5, b4
SZ[1:0]
DTC Data Transfer Size
b5 b4
—
b7, b6
MD[1:0]
DTC Transfer Mode Select
b7 b6
—
0 0: Address in the SAR register is fixed
(write-back to SAR) is skipped
0 1: Address in the SAR register is fixed
(write-back to SAR is skipped)
1 0: SAR value is incremented after data transfer:
+1 when SZ[1:0] = 00b
+2 when SZ[1:0] = 01b
+4 when SZ[1:0] = 10b.
1 1: SAR value is decremented after data transfer:
-1 when SZ[1:0] = 00b
-2 when SZ[1:0] = 01b
-4 when SZ[1:0] = 10b.
0
0
1
1
0
0
1
1
0: Byte (8-bit) transfer
1: Halfword (16-bit) transfer
0: Word (32-bit) transfer
1: Setting prohibited.
0: Normal transfer mode
1: Repeat transfer mode
0: Block transfer mode
1: Setting prohibited.
The MRA register cannot be accessed directly from the CPU, however the CPU can access the SRAM area (transfer
information (n) start address + 03h) and the DTC automatically transfers the MRA transfer information to and from the
MRA register. See section 18.3.1, Allocating Transfer Information and the DTC Vector Table.
18.2.2
DTC Mode Register B (MRB)
Address(es): (Inaccessible directly from the CPU. See section 18.3.1.)
b7
CHNE
x
Value after reset:
b6
b5
CHNS DISEL
x
x
b4
DTS
x
b3
b2
DM[1:0]
x
x
b1
b0
—
—
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as undefined. The write value should be 0.
—
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Bit
Symbol
Bit name
Description
R/W
b3, b2
DM[1:0]
Transfer Destination Address
Addressing Mode
b3 b2
—
b4
DTS
DTC Transfer Mode Select
0: Select transfer destination as repeat or block area
1: Select transfer source as repeat or block area.
—
b5
DISEL
DTC Interrupt Select
0: Generate an interrupt request to CPU when specified data transfer
is complete
1: Generate an interrupt request to CPU each time DTC data transfer
is performed.
—
b6
CHNS
DTC Chain Transfer Select
0: Select continuous chain transfer
1: Select chain transfer to occur only when the transfer counter is
changed from 1 to 0 or 1 to CRAH.
—
b7
CHNE
DTC Chain Transfer Enable
0: Chain transfer disabled
1: Chain transfer enabled.
—
0 0: Address in the DAR register is fixed
(write-back to DAR is skipped)
0 1: Address in the DAR register is fixed
(write-back to DAR is skipped)
1 0: DAR value is incremented after data transfer:
+1 when MRA.SZ[1:0] = 00b
+2 when MRA.SZ[1:0] = 01b
+4 when MRA.SZ[1:0] = 10b.
1 1: DAR value is decremented after data transfer:
-1 when MRA.SZ[1:0] = 00b
-2 when MRA.SZ[1:0] = 01b
-4 when MRA.SZ[1:0] = 10b.
The MRB register cannot be accessed directly from the CPU, however the CPU can access the SRAM area (transfer
information (n) start address + 02h) and the DTC automatically transfers the MRB transfer information to and from the
MRB register. See section 18.3.1, Allocating Transfer Information and the DTC Vector Table.
DTS bit (DTC Transfer Mode Select)
The DTS bit selects either the transfer source or transfer destination as the repeat area or block area in repeat or block
transfer mode.
CHNS bit (DTC Chain Transfer Select)
The CHNS bit selects the chain transfer condition. When CHNE is 0, the CHNS setting is ignored. For details on the
conditions for chain transfer, see Table 18.3, Chain transfer conditions.
When the next transfer is a chain transfer, completion of the specified number of transfers is not determined, the
activation source flag is not cleared, and an interrupt request to the CPU is not generated.
CHNE bit (DTC Chain Transfer Enable)
The CHNE bit enables chain transfer. The chain transfer condition is selected in the CHNS bit. For details on chain
transfer, see section 18.4.6, Chain Transfer.
18.2.3
DTC Transfer Source Register (SAR)
Address(es): (Inaccessible directly from the CPU. See section 18.3.1.)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The SAR register sets the transfer source start address and cannot be accessed directly from the CPU. However, the CPU
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18. Data Transfer Controller (DTC)
can access the SRAM area (transfer information (n) start address + 04h) and the DTC automatically transfers the SAR
transfer information to and from the SAR register. See section 18.3.1, Allocating Transfer Information and the DTC
Vector Table.
Note:
Misalignment is prohibited for DTC transfers. Bit [0] must be 0 when MRA.SZ[1:0] = 01b.
Bits [1] and [0] must be 0 when MRA.SZ[1:0] = 10b.
18.2.4
DTC Transfer Destination Register (DAR)
Address(es): (Inaccessible directly from the CPU. See section 18.3.1.)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The DAR register sets the transfer destination start address and cannot be accessed directly from the CPU. However, the
CPU can access the SRAM area (transfer information (n) start address + 08h) and the DTC automatically transfers the
DAR transfer information to and from the DAR register. See section 18.3.1, Allocating Transfer Information and the
DTC Vector Table.
Note:
Misalignment is prohibited for DTC transfers. Bit [0] must be 0 when MRA.SZ[1:0] = 01b.
Bits [1] and [0] must be 0 when MRA.SZ[1:0] = 10b.
18.2.5
DTC Transfer Count Register A (CRA)
Address(es): (Inaccessible directly from the CPU. See section 18.3.1.)
Normal transfer mode
CRA
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Repeat transfer mode/block transfer mode
CRAH
Value after reset:
CRAL
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Symbol
Register name
Description
CRAL
Transfer Counter A Lower Register
Specify the transfer count
CRAH
Transfer Counter A Upper Register
Note:
Note:
R/W
—
—
The function depends on the transfer mode.
Set CRAH and CRAL to the same value in repeat transfer mode and block transfer mode.
The CRA register cannot be accessed directly from the CPU, however the CPU can access the SRAM area (transfer
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18. Data Transfer Controller (DTC)
information (n) start address + 0Eh) and the DTC automatically transfers the CRA transfer information to and from the
CRA register. See section 18.3.1, Allocating Transfer Information and the DTC Vector Table.
(1)
Normal transfer mode (MRA.MD[1:0] = 00b)
In normal transfer mode, CRA functions as a 16-bit transfer counter. The transfer count is 1, 65,535, and 65,536 when the
set value is 0001h, FFFFh, and 0000h, respectively. The CRA value is decremented (-1) on each data transfer.
(2)
Repeat transfer mode (MRA.MD[1:0] = 01b)
In repeat transfer mode, the CRAH register holds the transfer count and the CRAL register functions as an 8-bit transfer
counter. The transfer count is 1, 255, and 256 when the set value is 01h, FFh, and 00h, respectively. The CRAL value is
decremented (-1) on each data transfer. When it reaches 00h, the CRAH value is transferred to CRAL.
(3)
Block transfer mode (MRA.MD[1:0] = 10b)
In block transfer mode, the CRAH register holds the transfer count and the CRAL register functions as an 8-bit block
size counter. The transfer count is 1, 255, and 256 when the set value is 01h, FFh, and 00h, respectively. The CRAL value
is decremented (-1) at each data transfer. When it reaches 00h, the CRAH value is transferred to CRAL.
18.2.6
DTC Transfer Count Register B (CRB)
Address(es): (Inaccessible directly from the CPU. See section 18.3.1.)
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The CRB register sets the block transfer count for block transfer mode. The transfer count is 1, 65,535, and 65,536 when
the set value is 0001h, FFFFh, and 0000h, respectively. The CRB value is decremented (-1) when the final data of a
single block size is transferred. When normal transfer mode or repeat transfer mode is selected, this register is not used
and the set value is ignored.
CRB cannot be accessed directly from the CPU, however the CPU can access the SRAM area (transfer information (n)
start address + 0Ch) and the DTC automatically transfers the CRB transfer information to and from the CRB register. See
section 18.3.1, Allocating Transfer Information and the DTC Vector Table.
18.2.7
DTC Control Register (DTCCR)
Address(es): DTC.DTCCR 4000 5400h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
RRS
—
—
—
—
0
0
0
0
1
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b4
RRS
DTC Transfer Information
Read Skip Enable
0: Transfer information read is not skipped
1: Transfer information read is skipped when vector numbers match.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RRS bit (DTC Transfer Information Read Skip Enable)
The RRS bit enables skipping of transfer information reads when vector numbers match. The DTC vector number is
compared with the vector number in the previous activation process. When these vector numbers match and the RRS bit
is set to 1, DTC data transfer is performed without reading the transfer information. However, when the previous transfer
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18. Data Transfer Controller (DTC)
is a chain transfer, the transfer information is read regardless of the value in the RRS bit.
When the transfer counter (CRA register) becomes 0 during the previous normal transfer and when the transfer counter
(CRB register) becomes 0 during the previous block transfer, the transfer information is read regardless of the RRS bit
value.
18.2.8
DTC Vector Base Register (DTCVBR)
Address(es): DTC.DTCVBR 4000 5404h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Bit name
Description
R/W
b31 to b0
DTC Vector Base Address
Set the DTC vector base address. The lower 10 bits should be 0.
R/W
The DTCVBR register sets the base address for calculating the DTC vector table address, which can be set in the range
of 0000 0000h to FFFF FFFFh (4 GB) in 1-KB units.
18.2.9
DTC Module Start Register (DTCST)
Address(es): DTC.DTCST 4000 540Ch
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DTCST
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DTCST
DTC Module Start
0: DTC module stopped
1: DTC module started.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
DTCST bit (DTC Module Start)
Set the DTCST bit to 1 to enable the DTC to accept transfer requests. When DTCST is set to 0, transfer requests are no
longer accepted. If DTCST is set to 0 during a data transfer, the accepted transfer request is active until processing is
complete.
DTCST must be set to 0 before transitioning to any of the following state or mode:
Module-stop state
Software Standby mode without Snooze mode transition
Deep Software Standby mode.
For details on these transitions, see section 18.10, Module-Stop Function, and section 11, Low Power Modes.
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18.2.10
18. Data Transfer Controller (DTC)
DTC Status Register (DTCSTS)
Address(es): DTC.DTCSTS 4000 540Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
ACT
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
VECN[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
VECN[7:0]
DTC-Activating Vector
Number Monitoring
These bits indicate the vector number for the activation source
when a DTC transfer is in progress.
The value is only valid if a DTC transfer is in progress (ACT flag is
1).
R
b14 to b8
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
b15
ACT
DTC Active Flag
0: DTC transfer operation is not in progress
1: DTC transfer operation is in progress.
R
VECN[7:0] bits (DTC-Activating Vector Number Monitoring)
While transfer by the DTC is in progress, the VECN[7:0] bits indicate the vector number associated with the activation
source for the transfer. The value read from the VECN[7:0] bits is valid if the ACT flag is 1, indicating that a DTC
transfer is in progress, and invalid if the ACT flag is 0, indicating that no DTC transfer is in progress.
ACT flag (DTC Active Flag)
The ACT flag indicates the state of the DTC transfer operation.
[Setting condition]
When the DTC is activated by a transfer request.
[Clearing condition]
When transfer by the DTC, in response to a transfer request, is complete.
18.3
Activation Sources
The DTC is activated by an interrupt request. Setting the ICU.IELSRn.DTCE bit to 1 enables activation of the DTC by
the associated interrupt. The selector output n number set in ICU.IELSRn is defined as the interrupt vector number,
where n = 0 to 95. For an enabled interrupt, the specific DTC interrupt source associated with each interrupt vector
number n is selected in ICU.IELSRn.IELS[8:0] where n = 0 to 95, as listed in Table 14.4, Event table, in section 14,
Interrupt Controller Unit (ICU). For activation by software, see section 19.2.2, Event Link Software Event Generation
Register n (ELSEGRn) (n = 0, 1).
The interrupt vector number is equivalent to the DTC vector table number. After the DTC accepted an activation request,
it does not accept another activation request until transfer for that single request is complete, regardless of the priority of
the requests. When multiple activation requests are generated during a DMAC or DTC transfer, a highest priority request
is accepted on completion of the transfer. When multiple activation requests are generated while the DTC Module Start
bit (DTCST.DTCST) is 0, the DTC accepts the highest-priority request when DTCST.DTCST is subsequently set to 1.
The smaller interrupt vector number has higher priority.
The DTC performs the following operations at the start of a single data transfer or for a chain transfer, after the last of the
consecutive transfers:
On completion of a specified round of data transfer, the ICU.IELSRn.DTCE bit is set to 0, and an interrupt request
is sent to the CPU
If the MRB.DISEL bit is 1, an interrupt request is sent to the CPU on completion of a data transfer
For other transfers, the ICU.IELSRn.IR bit of the activation source is set to 0 at the start of the data transfer.
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18.3.1
18. Data Transfer Controller (DTC)
Allocating Transfer Information and the DTC Vector Table
The DTC reads the start address of the transfer information associated with each activation source from the vector table
and reads the transfer information starting at that address.
The vector table must be located so that the lower 10 bits of the base address (start address) are 0. Use the DTC Vector
Base Register (DTCVBR) to set the base address of the DTC vector table. Transfer information is allocated in the SRAM
area. In the SRAM area, the start address of the transfer information n with vector number n must be 4n added to the base
address in the vector table.
Figure 18.2 shows the relationship between the DTC vector table and transfer information. Figure 18.3 shows the
allocation of transfer information in the SRAM area.
Upper: DTCVBR
Lower: vector number 4
DTC vector table
Transfer information (1)
DTC vector address
Transfer information (1)
start address
+4
Transfer information (2)
start address
Transfer information (2)
:
:
:
+4(n-1)
Transfer information (n)
start address
:
:
:
4 bytes
Transfer information (n)
4 bytes
Figure 18.2
DTC vector table and transfer information
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18. Data Transfer Controller (DTC)
Allocation of transfer information
Lower address
Start address
3
2
MRA
MRB
0
1
Reserved (0)
Transfer information
per transfer
(4 words (16 bytes))
SAR
DAR
CRA
Chain
transfer
MRA
CRB
MRB
Reserved (0)
Transfer information for
the second transfer in
chain transfer mode
(4 words (16 bytes))
SAR
DAR
CRA
CRB
4 bytes
Figure 18.3
18.4
Allocation of transfer information in the SRAM area
Operation
The DTC transfers data according to the transfer information. Storage of the transfer information in the SRAM area is
required before a DTC operation. When the DTC is activated, it reads the DTC vector associated with the vector number.
The DTC then reads the transfer information from the transfer information store address referenced by the DTC vector
and transfers the data. After the data transfer, the DTC writes back the transfer information. Storing the transfer
information in the SRAM area allows data transfer of any number of channels.
The transfer modes include:
Normal transfer mode
Repeat transfer mode
Block transfer mode.
The DTC specifies a transfer source address in the SAR register and a transfer destination address in the DAR register.
The values in these registers are incremented, decremented, or address-fixed independently after the data transfer.
Table 18.2 describes the DTC transfer modes.
Table 18.2
DTC transfer modes
Data size transferred on single transfer
request
Increment or decrement of
memory address
Settable transfer
count
Normal transfer mode
1 byte (8 bits), 1 halfword (16 bits), or 1 word (32
bits)
Incremented or decremented by
1, 2, or 4 or address fixed
1 to 65,536
Repeat transfer mode*1
1 byte (8 bits), 1 halfword (16 bits), or 1 word (32
bits)
Incremented or decremented by
1, 2, or 4 or address fixed
1 to 256*3
Block transfer mode*2
Block size specified in CRAH
(1 to 256 bytes, 1 to 256 halfwords (2 to 512
bytes), or 1 to 256 words (4 to 1024 bytes))
Incremented or decremented by
1, 2, or 4 or address fixed
1 to 65,536
Transfer mode
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Note 1.
Note 2.
Note 3.
18. Data Transfer Controller (DTC)
Set the transfer source or destination as the repeat area.
Set the transfer source or destination as the block area.
After a data transfer of the specified count, the initial state is restored and operation restarts.
Setting the MRB.CHNE bit to 1 allows multiple transfers or a chain transfer on a single activation source. It also enables
a chain transfer when the specified data transfer is complete.
Figure 18.4 shows the operation flow of the DTC. Table 18.3 lists the chain transfer conditions. The combination of
control information for the second and subsequent transfers are omitted in this table.
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18. Data Transfer Controller (DTC)
Start
Match and
RRS bit = 1
Compare vector
numbers. Match?
Mismatch or RRS bit = 0
Read DTC vector
Next transfer
Read transfer
information
Update transfer
information start address
Yes
CHNE bit = 1?
Yes
No
CHNS bit = 0
No
MD[1:0] bits = 01b?
(repeat transfer mode?)
Yes
No
Last data transfer?
(transfer counter = 1?)*1
Yes
Last data transfer?
(transfer counter = 1?)*1
No
Yes
No
Yes
DISEL bit = 1?
No
Clear the ICU.IELSRn.IR
bit
Transfer data
Transfer data
Transfer data
Transfer data
Write transfer information
Write transfer information
Write transfer information
Write transfer information
Clear the ICU.IELSRn.DTCE
bit. An interrupt to the CPU is
generated.
An interrupt to the CPU
is generated
End
Figure 18.4
Note 1. Counter value before starting data transfer.
DTC operation flow
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Table 18.3
18. Data Transfer Controller (DTC)
Chain transfer conditions
Second transfer*3
First transfer
CHNE
bit
CHNS
bit
DISEL
bit
Transfer
counter*1,*2
CHNE
bit
CHNS
bit
DISEL
bit
Transfer
counter*1,*2
0
—
0
Other than (1 → 0)
—
—
—
—
Ends after the first
transfer
0
—
0
(1 → 0)
—
—
—
—
0
—
1
—
—
—
—
—
Ends after the first
transfer with an interrupt
request to the CPU
1
0
—
—
0
—
0
Other than (1 → 0)
Ends after the second
transfer
0
—
0
(1 → 0)
0
—
1
—
Ends after the second
transfer with an interrupt
request to the CPU
DTC transfer
1
1
0
Other than (1 → *)
—
—
—
—
Ends after the first
transfer
1
1
—
(1 → *)
0
—
0
Other than (1 → 0)
Ends after the second
transfer
0
—
0
(1 → 0)
0
—
1
—
Ends after the second
transfer with an interrupt
request to the CPU
—
—
—
—
1
Note 1.
Note 2.
Note 3.
18.4.1
1
1
Other than (1 → *)
Ends after the first
transfer with an interrupt
request to the CPU
The transfer counter used depends on the transfer modes as follows:
Normal transfer mode — CRA register
Repeat transfer mode — CRAL register
Block transfer mode — CRB register
On completion of a data transfer, the counters operate as follows:
1 → 0 in normal and block transfer modes
1 → CRAH in repeat transfer mode
(1 → *) in the table indicates both of these two operations, depending on the mode.
Chain transfer can be selected for the second or subsequent transfers. The conditions for the combination of the second
transfer and CHNE bit = 1 is omitted.
Transfer Information Read Skip Function
Reading of vector addresses and transfer information can be skipped by setting the DTCCR.RRS bit. When a DTC
activation request is generated, the current DTC vector number is compared to the DTC vector number in the previous
activation process. When these vector numbers match and the RRS bit is set to 1, the DTC data transfer is performed
without reading the vector address and transfer information. However, when the previous transfer is a chain transfer, the
vector address and transfer information are read. Additionally, when the transfer counter (CRA register) becomes 0
during the previous normal transfer, or when the transfer counter (CRB register) becomes 0 during the previous block
transfer, transfer information is read regardless of the RRS bit. Figure 18.12 shows an example of a transfer information
read skip.
To update the vector table and transfer information, set the RRS bit to 0, update the vector table and transfer information,
and then set the RRS bit to 1. The stored vector number is discarded by setting the RRS bit to 0. The updated DTC vector
table and transfer information are read in the next activation process.
18.4.2
Transfer Information Write-Back Skip Function
When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to address fixed, a part of the transfer information is not
written back. Table 18.4 lists the transfer information write-back skip conditions and the associated registers. The CRA
and CRB registers are written back, and the write-back of the MRA and MRB registers is skipped.
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Table 18.4
18. Data Transfer Controller (DTC)
Transfer information write-back skip conditions and applicable registers
MRA.SM[1:0] bits
MRB.DM[1:0] bits
b3
b2
b3
b2
SAR register
DAR register
0
0
0
0
Skip
Skip
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
Skip
Write-back
0
0
1
1
0
1
1
0
0
1
1
1
1
0
0
0
Write-back
Skip
1
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
Write-back
Write-back
1
0
1
1
1
1
1
0
1
1
1
1
18.4.3
Normal Transfer Mode
Normal transfer mode allows a 1-byte (8-bit), 1-halfword (16-bit), or 1-word (32-bit) data transfer on a single activation
source. The transfer count can be set from 1 to 65536. Transfer source and destination addresses can be independently set
to increment, decrement, or remain fixed. This mode enables an interrupt request to the CPU to be generated at the end of
a specified-count transfer.
Table 18.5 lists register functions in normal transfer mode, and Figure 18.5 shows the memory map of normal transfer
mode.
Table 18.5
Register functions in normal transfer mode
Register
Description
Value written back by writing transfer information
SAR
Transfer source address
Increment, decrement, or fixed*1
DAR
Transfer destination address
Increment, decrement, or fixed*1
CRA
Transfer counter A
CRA - 1
CRB
Transfer counter B
Not updated
Note 1.
Write-back operation is skipped in address-fixed mode.
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18. Data Transfer Controller (DTC)
Transfer destination data area
Transfer source data area
SAR
Data 1
Data 2
Figure 18.5
18.4.4
Transfer 6
times
(transfer 1 data
unit per event)
DAR
Data 1
Data 2
Data 3
Data 3
Data 4
Data 4
Data 5
Data 5
Data 6
Data 6
Memory map of normal transfer mode (MRA.SM[1:0] = 10b, MRB.DM[1:0] = 10b, CRA = 0006h)
Repeat Transfer Mode
Repeat transfer mode allows a 1-byte (8-bit), 1-halfword (16-bit), or 1-word (32-bit) data transfer on a single activation
source. Specify either transfer source or transfer destination for the repeat area in the MRB.DTS bit. The transfer count
can be set from 1 to 256. When the specified-count transfer is complete, the initial value of the address register specified
in the repeat area is restored, the initial value of the transfer counter is restored, and transfer is repeated. The other
address register is incremented or decremented continuously or remains unchanged.
When the transfer counter CRAL decrements to 00h in repeat transfer mode, the CRAL value is updated to the value set
in the CRAH register. As a result, the transfer counter does not become 00h, which disables interrupt requests to the CPU
when the MRB.DISEL bit is set to 0. An interrupt request to the CPU is generated when the specified data transfer is
complete.
Table 18.6 lists the register functions in repeat transfer mode, and Figure 18.6 shows the memory map of repeat transfer
mode.
Table 18.6
Register functions in repeat transfer mode
Value written back by writing transfer information
Register
Description
When CRAL is not 1
When CRAL is 1
fixed*1
When the MRB.DTS bit is 0
Increment, decrement, or fixed*1
When the MRB.DTS bit is 1
SAR register initial value.
SAR
Transfer source
address
Increment, decrement, or
DAR
Transfer destination
address
Increment, decrement, or fixed*1
When the MRB.DTS bit is 0
DAR register initial value
When the MRB.DTS bit is 1
Increment, decrement, or fixed.*1
CRAH
Holds transfer
counter
CRAH
CRAH
CRAL
Transfer counter A
CRAL - 1
CRAH
CRB
Transfer counter B
Not updated
Not updated
Note 1.
Write-back is skipped in address-fixed mode.
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18. Data Transfer Controller (DTC)
Transfer destination data area
Transfer source data area
(set to repeat area)
SAR
Data 1
Data 2
Transfer 8
times
(transfer 1 data
unit per event)
Data 1
DAR
Data 2
Data 3
Data 3
Data 4
Data 4
Data 1
Data 2
Data 3
Data 4
Figure 18.6
18.4.5
Memory map of repeat transfer mode when the transfer source is a repeat area (MRA.SM[1:0] =
10b, MRB.DM[1:0] = 10b, CRAH = 04h)
Block Transfer Mode
Block transfer mode allows single-block data transfer on a single activation source. Transfer source or transfer
destination for the block area must be specified in the MRB.DTS bit. The block size can be set from 1 to 256 bytes, 1 to
256 halfwords (2 to 512 bytes), or 1 to 256 words (4 to 1024 bytes). When transfer of the specified block completes, the
initial values of the block size counter CRAL and the address register (the SAR register when the MRB.DTS bit = 1 or
the DAR register when the DTS bit = 0) specified in the block area are restored. The other address register is incremented
or decremented continuously or remains unchanged.
The transfer count (block count) can be set from 1 to 65,536. This mode enables an interrupt request to the CPU to be
generated at the end of the specified-count block transfer.
Table 18.7 lists register functions in block transfer mode, and Figure 18.7 shows the memory map for block transfer
mode.
Table 18.7
Register functions in block transfer mode
Register
Description
Value written back by writing transfer information
SAR
Transfer source address
When MRB.DTS bit is 0
Increment, decrement, or fixed*1
When MRB.DTS bit is 1
SAR register initial value.
DAR
Transfer destination address
When MRB.DTS bit is 0
DAR register initial value
When MRB.DTS bit is 1
Increment, decrement, or fixed.*1
CRAH
Holds the block size
CRAH
CRAL
Block size counter
CRAH
CRB
Block transfer counter
CRB - 1
Note 1.
Write-back is skipped in address-fixed mode.
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18. Data Transfer Controller (DTC)
Transfer source data area
SAR
First block
Transfer destination data area
(set to block area)
Transfer
Block area
DAR
nth block
Figure 18.7
18.4.6
Memory map of block transfer mode
Chain Transfer
Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single activation source. If
MRB.CHNE is set to 1 and CHNS to 0, an interrupt request to the CPU is not generated on completion of the specified
number of transfer rounds or by setting the MRB.DISEL bit to 1. An interrupt request is sent to the CPU each time DTC
data transfer is performed. Data transfer has no effect on the ICU.IELSRn.IR bit of the activation source.
The SAR, DAR, CRA, CRB, MRA, and MRB registers can be set independently of each other to define the data transfer.
Figure 18.8 shows a chain transfer operation.
Data area
Transfer source data (1)
DTC vector table
Transfer information
allocated in the RAM
Transfer destination data (1)
DTC vector
address
Transfer information start
address
Transfer information
CHNE bit = 1
Transfer information
CHNE bit = 0
Transfer source data (2)
Transfer destination data (2)
Figure 18.8
Chain transfer operation
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18. Data Transfer Controller (DTC)
Writing 1 to the MRB.CHNE and CHNS bits enables chain transfer to be performed only after completion of the
specified data transfer. In repeat transfer mode, chain transfer is performed after completion of the specified data transfer.
For details on chain transfer conditions, see Table 18.3, Chain transfer conditions.
18.4.7
Operation Timing
Figure 18.9 to Figure 18.12 are timing diagrams that show the minimum number of execution cycles.
System clock
ICU.IELSRn.IR
DTC activation request
DTC access
R
Vector read
Figure 18.9
Transfer
information read
W
Data
transfer
Transfer
information write
Example 1 of DTC operation timing in normal transfer and repeat transfer modes
System clock
ICU.IELSRn.IR
DTC activation request
DTC access
Vector read
Figure 18.10
Transfer
information read
Data transfer
Transfer
information write
Example 2 of DTC operation timing in block transfer mode when the block size = 4
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18. Data Transfer Controller (DTC)
System clock
ICU.IELSRn.IR
DTC activation request
DTC access
R
Vector read
Figure 18.11
Transfer
information read
W
Data
transfer
R
Transfer
information
write
W
Data
transfer
Transfer
information
read
Transfer
information
write
Example 3 of DTC operation timing for chain transfer
System clock
ICU.IELSRn.IR
(2)
(1)
DTC activation request
Read skip enable
R
DTC access
Vector read
Note:
Data
transfer
RR
Transfer
information write
W
Data
transfer
Transfer
information write
When activation sources (vector numbers) of (1) and (2) are the same and the RRS bit = 1, the transfer
information read for request (2) is skipped.
Figure 18.12
18.4.8
Transfer
information read
W
Example of operation when a transfer information read is skipped, with the vector, transfer
information, and transfer destination data on the SRAM, and the transfer source data on the
peripheral module
Execution Cycles of DTC
Table 18.8 lists the execution cycles of single data transfer of the DTC.
For the order of the execution states, see section 18.4.7, Operation Timing.
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Table 18.8
18. Data Transfer Controller (DTC)
Execution cycles of DTC
Transfer
mode
Vector read
Normal
Cv + Cs1 + 1
Data transfer
Transfer information
read
0*1
0*1
3 × (Ci + Cs1) + 1*2
2 × (Ci + Cs1) + 1*3
Read
(Ci + Cs1)*4
Write
Internal
operation
2
Cr + Cs2 + 1
Cw + Cs2 + 1
Repeat
Cr + Cs2 + 1
Cw + Cs2 + 1
Block*5
P × (Cr + Cs2)
P × (Cw + Cs2)
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
4 × (Ci + Cs1) + 1
Transfer information write
0*1
When transfer information read is skipped.
When neither SAR nor DAR is set to address-fixed mode.
When SAR or DAR is set to address-fixed mode.
When SAR and DAR are set to address-fixed mode.
When the block size is 2 or more. If the block size is 1, the cycle number for normal transfer is applied.
P: Block size (initial settings of CRAH and CRAL)
Cv: Cycles for access to vector transfer information storage destination
Ci: Cycles for access to transfer information storage destination address
Cr: Cycles for access to data read destination
Cw: Cycles for access to data write destination
Cs1: When accessing SRAMHS: 2 cycles.
When accessing elsewhere: 0 cycles.
When a slave bus changes by a read/write data transfer, add 1 more cycle.
Cs2: When accessing SRAMHS and peripheral modules related to system control: 2 cycles.
When accessing elsewhere: 0 cycle.
When a slave bus change by a read/write data transfer, add 1 more cycle.
The unit is system clocks (ICLK) + 1 in the Vector read, Transfer information read, and Data transfer read columns and 2 in
the Internal operation column.
Cv, Ci, Cr, and Cw vary depending on the corresponding access destination. For the number of cycles for respective access
destinations, see section 51, SRAM, section 53, Flash Memory, and section 15.2.3, External Bus.
The frequency ratio of the system clock and peripheral clock is also taken into consideration.
The DTC response time is the time from when the DTC activation source is detected until DTC transfer starts.
This table does not include the time until DTC data transfer starts after the DTC activation source becomes active.
18.4.9
DTC Bus Mastership Release Timing
The DTC does not release bus mastership during transfer information reads. Before the transfer information is read or
written, the bus is arbitrated according to the priority determined by the bus master arbitrator. For bus arbitration, see
section 15, Buses.
18.5
DTC Setting Procedure
Before using the DTC, set the DTC Vector Base Register (DTCVBR). Figure 18.13 shows the procedure for setting the
DTC.
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18. Data Transfer Controller (DTC)
Start
Set the ICU.IELSRn.IELS[8:0] bit to 0 to disable the interrupt in
the NVIC and provide the following settings:
Set the DTCCR.RRS bit to 0
[1]
[1] Set the DTCCR.RRS bit to 0 to reset the transfer
information read skip flag. After that, transfer information
read is not skipped while the DTC is activated. Specify this
setting when transfer information is updated.
Set transfer information
(MRA, MRB, SAR, DAR, CRA, and CRB)
[2]
[2] Allocate the transfer information (MRA, MRB, SAR, DAR,
CRA, and CRB) in the data area. To set transfer
information, see section 18.2, Register Descriptions. To
allocate transfer information, see section 18.3.1, Allocating
Transfer Information and the DTC Vector Table.
Set transfer information start addresses in
the DTC vector table
[3]
[3] Set the transfer information start addresses in the DTC
vector table. To set the DTC vector table, see section
18.3.1, Allocating Transfer Information and the DTC Vector
Table.
Set the DTCCR.RRS bit to 1
[4]
[4] Set the DTCCR.RRS bit to 1 to enable skipping of the
second and the subsequent transfer information read cycles
for continuous DTC activation from the same interrupt
source. The RRS bit can be set to 1, but if this is set during
DTC transfer, it becomes valid from the next transfer.
Set the ICU.IELSRn.DTCE bit to 1.
Set the ICU.IELSRn.IELS as interrupt source.
The interrupt should be enabled in the NVIC.
Set the enable bit for
an activation source interrupt
[5]
[5] Set the ICU.IELSRn.DTCE bit to 1. Set ICU.IELSRn.IELS
as the interrupt sources that trigger the DTC. The interrupts
must be enabled in NVIC. See Table 14.4, Event table.
[6]
Setting for each activation
source
Common setting
for DTC
Set the DTCST.DTCST bit to 1
[6] Set the enable bit for the activation source interrupts to 1.
When a source interrupt is generated, the DTC is activated.
To set the interrupt source enable bit, see the settings for
the modules that are to be the activation sources.
[7] Set the DTC Module Start bit (DTCST.DTCST) to 1.
[7]
Note:
The DTCST.DTCST bit can be set even if the setting
for the activation sources is not complete.
End
Figure 18.13
18.6
DTC setting procedure
Examples of DTC Usage
18.6.1
Normal Transfer
This section provides an example of DTC usage and its application when receiving 128 bytes of data from an SCI.
(1)
Transfer information settings
In the MRA register, select a fixed source address (MRA.SM[1:0] = 00b), normal transfer mode (MRA.MD[1:0] = 00b),
and byte-sized transfer (MRA.SZ[1:0] = 00b). In the MRB register, specify incrementation of the destination address
(MRB.DM[1:0] = 10b) and single data transfer by a single interrupt (MRB.CHNE = 0 and MRB.DISEL = 0). The
MRB.DTS bit can be set to any value. Set the RDR register address of the SCI in the SAR register, the start address of
the SRAM area for data storage in the DAR register, and 128 (0080h) in the CRA register. The CRB register can be set to
any value.
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(2)
18. Data Transfer Controller (DTC)
DTC vector table settings
The start address of the transfer information for the RXI interrupt is set in the vector table for the DTC.
(3)
ICU settings and DTC module activation
Set the ICU.IELSRn.DTCE bit to 1 and set ICU.IELSRn.IELS as the SCI interrupt. The interrupt must be enabled in the
NVIC. Set the DTCST.DTCST bit to 1.
(4)
SCI settings
Enable the RXI interrupt by setting the SCR.RIE bit in the SCI to 1. If a reception error occurs during the SCI receive
operation, reception stops. To manage this, use settings that allow the CPU to accept receive error interrupts.
(5)
DTC transfer
Each time a reception of 1 byte by the SCI is complete, an RXI interrupt is generated to activate the DTC. The DTC
transfers the received byte from the RDR of the SCI to the SRAM, after which the DAR register is incremented and the
CRA register is decremented.
(6)
Interrupt handling
After 128 rounds of data transfer are complete and the value in the CRA register becomes 0, an RXI interrupt request is
generated for the CPU. Complete the process in the handling routine for this interrupt.
18.6.2
Chain Transfer
This section provides an example of chain transfer by the DTC and describes its use in the output of pulses by the
General PWM Timer (GPT). You can use chain transfer to transfer PWM timer compare data and change the period of
the PWM timer for GPT.
For the first of the chain transfers, normal transfer mode is specified for transfer to the GPT32m.GTCCRC register (m =
EH0 to EH3, E4 to E7, 8 to 13). For the second transfer, normal transfer mode is specified for transfer to the
GPT32m.GTCCRE register. For the third transfer, normal transfer mode is specified for transfer to the GPT32m.GTPBR
register. This is because clearing of the activation source and generation of an interrupt on completion of the specified
number of transfers are restricted to the third of the chain transfers, that is, transfer while MRB.CHNE = 0.
The following example shows how to use the counter overflow interrupt with a GPT32EH0.GTPR register as an
activating source for the DTC.
(1)
First transfer information settings
Set up transfer to the GPT32EH0.GTCCRC register:
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] = 00b) and word-sized transfer (MRA.SZ[1:0] = 10b).
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] = 00b) and set up chain transfer
(MRB.CHNE = 1 and MRB.CHNS = 0).
4. Set the SAR register to the first address of the data table.
5. Set the DAR register to the address of the GPT32EH0.GTCCRC register.
6. Set the CRAH and CRAL registers to the size of the data table. The CRB register can be set to any value.
(2)
Second transfer information settings
Set up transfer to the GPT32EH0.GTCCRE register:
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] = 00b) and word-sized transfer (MRA.SZ[1:0] = 10b).
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] = 00b) and set up chain transfer
(MRB.CHNE = 1 and MRB.CHNS = 0).
4. Set the SAR register to the first address of the data table.
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18. Data Transfer Controller (DTC)
5. Set the DAR register to the address of the GPT32EH0.GTCCRE register.
6. Set the CRAH and CRAL registers to the size of the data table. The CRB register can be set to any value.
(3)
Third transfer information settings
Set up transfer to the GPT32EH0.GTPBR registers:
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] = 00b) and word-sized transfer (MRA.SZ[1:0] = 10b).
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] = 00b) and set up single data transfer
per interrupt (MRB.CHNE = 0, MRB.DISEL = 0). The MRB.DTS bit can be set to any value.
4. Set the SAR register to the first address of the data table.
5. Set the DAR register to the address of the GPT32EH0.GTPBR register.
6. Set the CRA register to the size of the data table. The CRB register can be set to any value.
(4)
Transfer information assignment
Place the transfer information for use in the transfer to GPT32EH0.GTPBR immediately after the transfer control
information for use in the GPT32EH0.GTCCRC and GPT32EH0.GTCCRE registers.
(5)
DTC vector table
In the DTC vector table, set the address where the transfer control information for use in transfer to the
GPT32EH0.GTCCRC and GPT32EH0.GTCCRE registers starts.
(6)
ICU settings and DTC module activation
1. Set the ICU.IELSRn.DTCE bit associated with the GPT32EH0 counter overflow interrupt.
2. Set ICU.IELSRn.IELS[8:0] to 182 (B6h) for the GPT32EH0 counter overflow.
3. Set the DTCST.DTCST bit to 1.
(7)
GPT settings
1. Set the GPT32EH0.GTIOR register so that the GTCCRA and GTCCRB registers operate as output compare
registers.
2. Set the default PWM timer compare values in the GPT32EH0.GTCCRA and GPT32EH0.GTCCRB registers and
the next PWM timer compare values in the GPT32EH0.GTCCRC and GPT32EH0.GTCCRE registers.
3. Set the default PWM timer period values in the GPT32EH0.GTPR register and the next PWM timer period values
in the GPT32EH0.GTPBR register.
4. Set 1 to the output bit in PmnPFS.PDR, and set 00011b to the peripheral select bits in PmnPFS.PSEL[4:0].
(8)
GPT activation
Set the GPT32EH0.GTSTR.CSTRT bit to 1 to start the GPT32EH0.GTCNT counter.
(9)
DTC transfer
Each time a GPT32EH0 counter overflow is generated with the GPT32EH0.GTPR register, the next PWM timer
compare values are transferred to the GPT32EH0.GTCCRC and GPT32EH0.GTCCRE registers. The setting for the next
PWM timer period is transferred to the GPT32EH0.GTPBR register.
(10) Interrupt handling
After the specified rounds of data transfer are complete, for example when the value in the CRA register for GPT transfer
becomes 0, a GPT counter overflow interrupt request is issued for the CPU. Complete the process for this interrupt in the
handling routine.
18.6.3
Chain Transfer when Counter = 0
The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data
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18. Data Transfer Controller (DTC)
transfer information is repeatedly changed in the second transfer. Chain transfer enables transfers to be repeated 256
times or more.
The following procedure shows an example of configuring a 128-KB input buffer, where the input buffer is set so that its
lower address starts with 0000h. Figure 18.14 shows a chain transfer when the counter = 0.
1. Set the normal transfer mode to input data for the first data transfer. Set the following:
a. Transfer source address = fixed.
b. CRA register = 0000h (65,536) times.
c. MRB.CHNE bit = 1 (chain transfer is enabled).
d. MRB.CHNS bit = 1 (chain transfer is performed only when the transfer counter is 0).
e. MRB.DISEL bit = 0 (an interrupt request to the CPU is generated when the specified data transfer completes).
2. Prepare the upper 8-bit address of the start address at every 65,536 times of the transfer destination address for the
first data transfer in different area such as the flash. For example, when setting the input buffer to 20 0000h to
21 FFFFh, prepare 21h and 20h.
3. For the second data transfer:
a. Set the repeat transfer mode (with the source as the repeat area) to reset the transfer destination address of the
first data transfer.
b. Specify the upper 8 bits of the DAR register in the first transfer information area for the transfer destination.
c. Set the MRB.CHNE bit = 0 (chain transfer is disabled).
d. Set the MRB.DISEL bit = 0 (an interrupt request to the CPU is generated when the specified data transfer
completes).
e. When setting the input buffer to 20 0000h to 21 FFFFh, also set the transfer counter to 2.
4. The first data transfer is performed by an interrupt 65,536 times. When the transfer counter of the first data transfer
becomes 0, the second data transfer starts. Set the upper 8 bits of the transfer destination address of the first data
transfer to 21h. The lower 16 bits of the transfer destination address and the transfer counter of the first data transfer
becomes 0000h.
5. In succession, the first data transfer is performed by an interrupt 65,536 times as specified for the first data transfer.
When the transfer counter of the first data transfer becomes 0, the second data transfer starts. Set the upper 8 bits of
the transfer destination address of the first data transfer to 20h. The lower 16 bits of the transfer destination address
and the transfer counter of the first data transfer becomes 0000h.
6. Steps 4 and 5 are repeated indefinitely. Because the second data transfer is in repeat transfer mode, no interrupt
request to the CPU is generated.
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18. Data Transfer Controller (DTC)
Input circuit
Transfer information allocated in
the on-chip memory space
Input buffer
First data transfer
Transfer information
Chain transfer
(counter = 0)
Second data transfer
Transfer information
Upper 8 bits of DAR
Figure 18.14
18.7
Chain transfer when counter = 0
Interrupt Sources
When the DTC completes data transfer of the specified count or when data transfer with MRB.DISEL set to 1 is
complete, a DTC activation source generates an interrupt to the CPU. Interrupts to the CPU are controlled according to
the settings in the NVIC and ICU.IELSRn.IELS[8:0]. See section 14, Interrupt Controller Unit (ICU).
The DTC prioritizes activation sources by granting the smaller interrupt vector numbers higher priority. The priority of
interrupts to the CPU is determined by the NVIC priority.
18.8
Event Link
The DTC can produce an event link request on completion of one transfer request. When the destination for the transfer
is an external bus, the event link request is issued after completion of writing to the write buffer rather than after
completion of writing to the actual transfer destination.
18.9
Snooze Control Interface
To return to Software Standby mode from Snooze mode through the DTC, set SYSTEM.SNZEDCR.DTCZRED or
SYSTEM.SNZEDCR.DTCNZRED to 1. See section 11.8.3, Return to Software Standby Mode.
SYSTEM.SNZEDCR.DTCZRED enables or disables a Snooze end request on completion of the last DTC transmission,
detected on DTC transmission completion when CRA and CRB are 0.
SYSTEM.SNZEDCR.DTCNZRED enables or disables a Snooze end request on a not last DTC transmission completion
(CRA and CRB are not 0), detected on DTC transmission completion when CRA and CRB are not 0.
18.10 Module-Stop Function
Before transitioning to the module-stop function, Software Standby mode without a Snooze mode transition, or Deep
Software Standby mode, set the DTCST.DTCST bit to 0, then perform the operations described in the following sections.
The DTC is available in Snooze mode by setting LPW.SNZCR.SNZDTCEN to 1. See section 11, Low Power Modes.
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(1)
18. Data Transfer Controller (DTC)
Module-stop function
Writing 1 to the MSTPCRA.MSTPA22 bit enables the module-stop function of the DTC. If the DTC transfer is in
progress at the time 1 is written to the MSTPCRA.MSTPA22 bit, the transition to the module-stop state proceeds after
DTC transfer ends. When the MSTPCRA.MSTPA22 bit is 1, accessing the DTC registers is prohibited. Writing 0 to the
MSTPCRA.MSTPA22 bit releases the DTC from the module-stop state.
(2)
Software Standby and Deep Software Standby modes
Use the settings described in section 11.7.1, Transition to Software Standby Mode, or section 11.9.1, Transition to Deep
Software Standby Mode.
If DTC transfer operations are in progress when the WFI instruction is executed, the transition to Software Standby mode
or Deep Software Standby mode follows the completion of the DTC transfer.
When the snooze control circuit receives a snooze request in Software Standby mode, the MCU transfers to Snooze
mode. See section 11.8.1, Transition to Snooze Mode. DTC operation in Snooze mode can be selected in the
SYSTEM.SNZCR.SNZDTCEN bit. If DTC operation is enabled in Snooze mode, before transitioning to Software
Standby mode, set the DTCST.DTCST bit to 1. To return to Software Standby mode through the DTC, set
SYSTEM.SNZEDCR.DTCZRED or SYSTEM.SNZEDCR.DTCNZRED to 1. See section 11.8.3, Return to Software
Standby Mode. The DTC activation request from the ICU is stopped during Software Standby mode but not during
Snooze mode.
(3)
Notes on the module-stop function
For the WFI instruction and the register setting procedure, see section 11, Low Power Modes.
To perform a DTC transfer after returning from a low power mode without Snooze mode transition, set the
DTCST.DTCST bit to 1 again.
To use a request that is generated in Software Standby mode as an interrupt request to the CPU but not as a DTC
activation request, specify the CPU as the interrupt request destination as described in section 14.4.2, Selecting Interrupt
Request Destinations, then execute a WFI instruction. If DTC operation is enabled in Snooze mode, do not use the
module-stop function of the DTC.
18.11 Usage Notes
18.11.1
Transfer information Start Address
You must set multiples of 4 for the transfer information start addresses in the vector table. Otherwise, such addresses are
accessed with their lowest 2 bits regarded as 00b.
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19. Event Link Controller (ELC)
19.
Event Link Controller (ELC)
19.1
Overview
The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to
connect them to different modules, allowing direct link between the modules without CPU intervention.
Table 19.1 lists the ELC specifications and Figure 19.1 shows a block diagram.
Table 19.1
ELC specifications
Parameter
Specifications
Event link function
258 types of event signals can be directly connected to modules.The ELC can generate an
ELC event signal, and events that activate the DTC.
Module-stop function
Module-stop state can be set
Internal peripheral bus
ELC
ELSEGR0, 1
ELCR
ELSRn
DTC
Event control
PORT_IRQn
(n = 0 to 15)
GPT
DMAC
ADC12
DTC
DAC12
LVD
Port 1/2/3/4
SYSTEM_SNZREQ
CTSU
MOSC_STOP
Peripheral module
Port 1/2/3/4
ELSEGR0,1: Event Link Software Event Generation Register
ELCR:
Event Link Control Register
ELSRn:
Event Link Setting Register n (n = 0 to 18)
Figure 19.1
ELC block diagram
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19.2
19. Event Link Controller (ELC)
Register Descriptions
19.2.1
Event Link Controller Register (ELCR)
Address(es): ELC.ELCR 4004 1000h
b7
b6
b5
b4
b3
b2
b1
b0
ELCON
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
ELCON
All Event Link Enable
0: ELC function disabled
1: ELC function enabled.
R/W
The ELCR register controls the ELC operation.
19.2.2
Event Link Software Event Generation Register n (ELSEGRn) (n = 0, 1)
Address(es): ELC.ELSEGR0 4004 1002h, ELC.ELSEGR1 4004 1004h
b7
b6
b5
b4
b3
b2
b1
b0
WI
WE
—
—
—
—
—
SEG
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
SEG
Software Event Generation
0: Normal operation
1: Software event is generated.
W
b5 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
WE
SEG Bit Write Enable
0: Writes to SEG bit disabled
1: Writes to SEG bit enabled.
R/W
b7
WI
ELSEGR Register Write Disable
0: Writes to ELSEGR register enabled
1: Writes to ELSEGR register disabled.
W
SEG bit (Software Event Generation)
When 1 is written to the SEG bit while the WE bit is 1, a software event is generated. This bit is read as 0. Even when 1
is written to this bit, data is not stored. The WE bit must be set to 1 before writing to this bit.
A software event can trigger a linked DTC event.
WE bit (SEG Bit Write Enable)
The SEG bit can only be written to when the WE bit is 1. Clear the WI bit to 0 before writing to this bit.
[Setting condition]
If 1 is written to this bit while the WI bit is 0, this bit becomes 1.
[Clearing condition]
If 0 is written to this bit while the WI bit is 0, this bit becomes 0.
WI bit (ELSEGR Register Write Disable)
The ELSEGR register can only be written to when the write value to the WI bit is 0. This bit is read as 1. Before setting
the WE or SEG bit, the WI bit must be set to 0.
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19.2.3
19. Event Link Controller (ELC)
Event Link Setting Register n (ELSRn) (n = 0 to 18)
Address(es): ELC.ELSR0 4004 1010h, ELC.ELSR1 4004 1014h, ELC.ELSR2 4004 1018h, ELC.ELSR3 4004 101Ch, ELC.ELSR4 4004 1020h,
ELC.ELSR5 4004 1024h, ELC.ELSR6 4004 1028h, ELC.ELSR7 4004 102Ch, ELC.ELSR8 4004 1030h, ELC.ELSR9 4004 1034h,
ELC.ELSR10 4004 1038h, ELC.ELSR11 4004 103Ch, ELC.ELSR12 4004 1040h, ELC.ELSR13 4004 1044h,
ELC.ELSR14 4004 1048h, ELC.ELSR15 4004 104Ch, ELC.ELSR16 4004 1050h, ELC.ELSR17 4004 1054h, ELC.ELSR18 4004 1058h
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
Value after reset:
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
ELS[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
ELS[8:0]
Event Link Select
b8
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
b0
000000000: Event output disabled for the associated
peripheral module
000000001 to 111000101b: Number setting for the event
signal to be linked.
Other settings are prohibited.
R/W
The ELSRn register specifies an event signal to be linked to each peripheral module. Table 19.2 shows the association
between the ELSRn registers and the peripheral modules. Table 19.3 shows the association between the event signal
names set in the ELSRn register and the signal numbers.
Table 19.2
Association between the ELSRn registers and peripheral functions
Register name
Peripheral function (module)
Event name
ELSR0
GPT (A)
ELC_GPTA
ELSR1
GPT (B)
ELC_GPTB
ELSR2
GPT (C)
ELC_GPTC
ELSR3
GPT (D)
ELC_GPTD
ELSR4
GPT (E)
ELC_GPTE
ELSR5
GPT (F)
ELC_GPTF
ELSR6
GPT (G)
ELC_GPTG
ELSR7
GPT (H)
ELC_GPTH
ELSR8
ADC12A0
ELC_AD00
ELSR9
ADC12B0
ELC_AD01
ELSR10
ADC12A1
ELC_AD10
ELSR11
ADC12B1
ELC_AD11
ELSR12
DAC12 channel 0
ELC_DA0
ELSR13
DAC12 channel 1
ELC_DA1
ELSR14
PORT 1
ELC_PORT1
ELSR15
PORT 2
ELC_PORT2
ELSR16
PORT 3
ELC_PORT3
ELSR17
PORT 4
ELC_PORT4
ELSR18
CTSU
ELC_CTSU
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Table 19.3
Event number
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (1 of 6)
Interrupt request source
Name
Description
Port
PORT_IRQ0*1
External pin interrupt 0
002h
PORT_IRQ1*1
External pin interrupt 1
003h
PORT_IRQ2*1
External pin interrupt 2
004h
PORT_IRQ3*1
External pin interrupt 3
005h
PORT_IRQ4*1
External pin interrupt 4
006h
PORT_IRQ5*1
External pin interrupt 5
007h
PORT_IRQ6*1
External pin interrupt 6
008h
PORT_IRQ7*1
External pin interrupt 7
009h
PORT_IRQ8*1
External pin interrupt 8
00Ah
PORT_IRQ9*1
External pin interrupt 9
00Bh
PORT_IRQ10*1
External pin interrupt 10
00Ch
PORT_IRQ11*1
External pin interrupt 11
00Dh
PORT_IRQ12*1
External pin interrupt 12
00Eh
PORT_IRQ13*1
External pin interrupt 13
00Fh
PORT_IRQ14*1
External pin interrupt 14
010h
PORT_IRQ15*1
External pin interrupt 15
001h
020h
DMAC0
DMAC0_INT
DMAC transfer end 0
021h
DMAC1
DMAC1_INT
DMAC transfer end 1
022h
DMAC2
DMAC2_INT
DMAC transfer end 2
023h
DMAC3
DMAC3_INT
DMAC transfer end 3
024h
DMAC4
DMAC4_INT
DMAC transfer end 4
025h
DMAC5
DMAC5_INT
DMAC transfer end 5
026h
DMAC6
DMAC6_INT
DMAC transfer end 6
027h
DMAC7
DMAC7_INT
DMAC transfer end 7
02Ah
DTC
DTC_DTCEND*3
DTC transfer end
038h
LVD
LVD_LVD1
Voltage monitor 1 interrupt
LVD_LVD2
Voltage monitor 2 interrupt
039h
03Bh
MOSC
MOSC_STOP
Main clock oscillation stop
03Ch
Low power mode
SYSTEM_SNZREQ*2, *3
Snooze entry
040h
AGT0
AGT0_AGTI
AGT interrupt
041h
AGT0_AGTCMAI
Compare match A
042h
AGT0_AGTCMBI
Compare match B
043h
AGT1_AGTI
AGT interrupt
044h
AGT1
AGT1_AGTCMAI
Compare match A
045h
AGT1_AGTCMBI
Compare match B
046h
IWDT
IWDT_NMIUNDF
IWDT underflow
047h
WDT
WDT_NMIUNDF
WDT underflow
049h
RTC
RTC_PRD
Periodic interrupt
04Bh
ADC120
ADC120_ADI
A/D scan end interrupt
04Fh
ADC120_WCMPM*3
Compare match
050h
ADC120_WCMPUM*3
Compare mismatch
051h
ADC121_ADI
A/D scan end interrupt
055h
ADC121
ADC121_WCMPM*3
Compare match
056h
ADC121_WCMPUM*3
Compare mismatch
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Table 19.3
Event number
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (2 of 6)
Interrupt request source
Name
Description
ACMPHS
ACMP_HS0*1
High-Speed Analog Comparator interrupt 0
058h
ACMP_HS1*1
High-Speed Analog Comparator interrupt 1
059h
ACMP_HS2*1
High-Speed Analog Comparator interrupt 2
05Ah
ACMP_HS3*1
High-Speed Analog Comparator interrupt 3
05Bh
ACMP_HS4*1
High-Speed Analog Comparator interrupt 4
05Ch
ACMP_HS5*1
High-Speed Analog Comparator interrupt 5
IIC0_RXI
Receive data full
064h
IIC0_TXI
Transmit data empty
065h
IIC0_TEI
Transmit end
066h
IIC0_EEI
Transfer error
057h
063h
068h
IIC0
IIC1_RXI
Receive data full
069h
IIC1_TXI
Transmit data empty
06Ah
IIC1_TEI
Transmit end
06Bh
IIC1_EEI
Transfer error
IIC2_RXI
Receive data full
06Eh
IIC2_TXI
Transmit data empty
06Fh
IIC2_TEI
Transmit end
070h
IIC2_EEI
Transfer error
086h
DOC
DOC_DOPCI*3
Data Operation Circuit interrupt
094h
I/O port
IOPORT_GROUP1
Port 1 event
095h
IOPORT_GROUP2
Port 2 event
096h
IOPORT_GROUP3
Port 3 event
097h
IOPORT_GROUP4
Port 4 event
ELC
ELC_SWEVT0
Software event 0
ELC_SWEVT1
Software event 1
GPT32EH0
GPT0_CCMPA
Compare match A
0B1h
GPT0_CCMPB
Compare match B
0B2h
GPT0_CMPC
Compare match C
0B3h
GPT0_CMPD
Compare match D
0B4h
GPT0_CMPE
Compare match E
0B5h
GPT0_CMPF
Compare match F
0B6h
GPT0_OVF
Overflow
0B7h
GPT0_UDF
Underflow
0B8h
GPT0_ADTRGA
A/D converter start request A
0B9h
GPT0_ADTRGB
A/D converter start request B
06Dh
098h
IIC1
IIC2
099h
0B0h
0BAh
GPT1_CCMPA
Compare match A
0BBh
GPT32EH1
GPT1_CCMPB
Compare match B
0BCh
GPT1_CMPC
Compare match C
0BDh
GPT1_CMPD
Compare match D
0BEh
GPT1_CMPE
Compare match E
0BFh
GPT1_CMPF
Compare match F
0C0h
GPT1_OVF
Overflow
0C1h
GPT1_UDF
Underflow
0C2h
GPT1_ADTRGA
A/D converter start request A
0C3h
GPT1_ADTRGB
A/D converter start request B
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Table 19.3
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (3 of 6)
Event number
Interrupt request source
Name
Description
0C4h
GPT32EH2
GPT2_CCMPA
Compare match A
0C5h
GPT2_CCMPB
Compare match B
0C6h
GPT2_CMPC
Compare match C
0C7h
GPT2_CMPD
Compare match D
0C8h
GPT2_CMPE
Compare match E
0C9h
GPT2_CMPF
Compare match F
0CAh
GPT2_OVF
Overflow
0CBh
GPT2_UDF
Underflow
0CCh
GPT2_ADTRGA
A/D converter start request A
0CDh
GPT2_ADTRGB
A/D converter start request B
0CEh
GPT3_CCMPA
Compare match A
0CFh
GPT32EH3
GPT3_CCMPB
Compare match B
0D0h
GPT3_CMPC
Compare match C
0D1h
GPT3_CMPD
Compare match D
0D2h
GPT3_CMPE
Compare match E
0D3h
GPT3_CMPF
Compare match F
0D4h
GPT3_OVF
Overflow
0D5h
GPT3_UDF
Underflow
0D6h
GPT3_ADTRGA
A/D converter start request A
0D7h
GPT3_ADTRGB
A/D converter start request B
GPT4_CCMPA
Compare match A
0D8h
GPT32E4
0D9h
GPT4_CCMPB
Compare match B
0DAh
GPT4_CMPC
Compare match C
0DBh
GPT4_CMPD
Compare match D
0DCh
GPT4_CMPE
Compare match E
0DDh
GPT4_CMPF
Compare match F
0DEh
GPT4_OVF
Overflow
0DFh
GPT4_UDF
Underflow
0E0h
GPT4_ADTRGA
A/D converter start request A
0E1h
GPT4_ADTRGB
A/D converter start request B
0E2h
GPT5_CCMPA
Compare match A
0E3h
GPT32E5
GPT5_CCMPB
Compare match B
0E4h
GPT5_CMPC
Compare match C
0E5h
GPT5_CMPD
Compare match D
0E6h
GPT5_CMPE
Compare match E
0E7h
GPT5_CMPF
Compare match F
0E8h
GPT5_OVF
Overflow
0E9h
GPT5_UDF
Underflow
0EAh
GPT5_ADTRGA
A/D converter start request A
0EBh
GPT5_ADTRGB
A/D converter start request B
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Table 19.3
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (4 of 6)
Event number
Interrupt request source
Name
Description
0ECh
GPT32E6
GPT6_CCMPA
Compare match A
0EDh
GPT6_CCMPB
Compare match B
0EEh
GPT6_CMPC
Compare match C
0EFh
GPT6_CMPD
Compare match D
0F0h
GPT6_CMPE
Compare match E
0F1h
GPT6_CMPF
Compare match F
0F2h
GPT6_OVF
Overflow
0F3h
GPT6_UDF
Underflow
0F4h
GPT6_ADTRGA
A/D converter start request A
0F5h
GPT6_ADTRGB
A/D converter start request B
0F6h
GPT7_CCMPA
Compare match A
0F7h
GPT7_CCMPB
Compare match B
0F8h
GPT7_CMPC
Compare match C
0F9h
GPT7_CMPD
Compare match D
0FAh
GPT7_CMPE
Compare match E
0FBh
GPT7_CMPF
Compare match F
0FCh
GPT7_OVF
Overflow
0FDh
GPT7_UDF
Underflow
0FEh
GPT7_ADTRGA
A/D converter start request A
0FFh
GPT7_ADTRGB
A/D converter start request B
GPT8_CCMPA
Compare match A
100h
GPT32E7
GPT328
101h
GPT8_CCMPB
Compare match B
102h
GPT8_CMPC
Compare match C
103h
GPT8_CMPD
Compare match D
104h
GPT8_CMPE
Compare match E
105h
GPT8_CMPF
Compare match F
106h
GPT8_OVF
Overflow
107h
GPT8_UDF
Underflow
GPT9_CCMPA
Compare match A
10Bh
GPT9_CCMPB
Compare match B
10Ch
GPT9_CMPC
Compare match C
10Dh
GPT9_CMPD
Compare match D
10Eh
GPT9_CMPE
Compare match E
10Fh
GPT9_CMPF
Compare match F
110h
GPT9_OVF
Overflow
10Ah
GPT329
111h
GPT9_UDF
Underflow
GPT10_CCMPA
Compare match A
115h
GPT10_CCMPB
Compare match B
116h
GPT10_CMPC
Compare match C
117h
GPT10_CMPD
Compare match D
118h
GPT10_CMPE
Compare match E
114h
GPT3210
119h
GPT10_CMPF
Compare match F
11Ah
GPT10_OVF
Overflow
11Bh
GPT10_UDF
Underflow
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Table 19.3
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (5 of 6)
Event number
Interrupt request source
Name
Description
11Eh
GPT3211
GPT11_CCMPA
Compare match A
11Fh
GPT11_CCMPB
Compare match B
120h
GPT11_CMPC
Compare match C
121h
GPT11_CMPD
Compare match D
122h
GPT11_CMPE
Compare match E
123h
GPT11_CMPF
Compare match F
124h
GPT11_OVF
Overflow
125h
GPT11_UDF
Underflow
GPT12_CCMPA
Compare match A
129h
GPT12_CCMPB
Compare match B
12Ah
GPT12_CMPC
Compare match C
12Bh
GPT12_CMPD
Compare match D
12Ch
GPT12_CMPE
Compare match E
12Dh
GPT12_CMPF
Compare match F
12Eh
GPT12_OVF
Overflow
128h
GPT3212
12Fh
GPT12_UDF
Underflow
GPT13_CCMPA
Compare match A
133h
GPT13_CCMPB
Compare match B
134h
GPT13_CMPC
Compare match C
135h
GPT13_CMPD
Compare match D
136h
GPT13_CMPE
Compare match E
137h
GPT13_CMPF
Compare match F
138h
GPT13_OVF
Overflow
139h
GPT13_UDF
Underflow
132h
GPT3213
150h
GPT
GPT_UVWEDGE
UVW edge event
174h
SCI0
SCI0_RXI *4
Receive data full
*4
Transmit data empty
175h
SCI0_TXI
176h
SCI0_TEI
Transmit end
177h
SCI0_ERI *4
Receive error
178h
SCI0_AM
Address match event
17Ah
SCI1
SCI1_RXI
*4
SCI1_TXI *4
17Bh
Receive data full
Transmit data empty
17Ch
SCI1_TEI
Transmit end
17Dh
SCI1_ERI *4
Receive error
17Eh
SCI1_AM
Address match event
180h
SCI2
SCI2_RXI
*4
Receive data full
181h
SCI2_TXI *4
Transmit data empty
182h
SCI2_TEI
Transmit end
183h
SCI2_ERI
184h
SCI2_AM
186h
SCI3
*4
Receive error
Address match event
SCI3_RXI *4
*4
Receive data full
Transmit data empty
187h
SCI3_TXI
188h
SCI3_TEI
Transmit end
189h
SCI3_ERI *4
Receive error
18Ah
SCI3_AM
Address match event
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Table 19.3
Event number
19. Event Link Controller (ELC)
Association between event signal names set in ELSRn.ELS bits and signal numbers (6 of 6)
Interrupt request source
Name
Description
SCI4_RXI
*4
18Dh
SCI4_TXI
*4
18Eh
SCI4_TEI
Transmit end
18Fh
SCI4_ERI *4
Receive error
18Ch
SCI4
190h
Receive data full
Transmit data empty
SCI4_AM
Address match event
SCI5_RXI *4
Receive data full
193h
SCI5_TXI *4
Transmit data empty
194h
SCI5_TEI
Transmit end
195h
SCI5_ERI *4
Receive error
196h
SCI5_AM
Address match event
192h
198h
SCI5
SCI6
*4
SCI6_RXI
Receive data full
199h
SCI6_TXI *4
Transmit data empty
19Ah
SCI6_TEI
Transmit end
19Bh
SCI6_ERI *4
Receive error
19Ch
SCI6_AM
Address match event
19Eh
SCI7
*4
SCI7_RXI
Receive data full
19Fh
SCI7_TXI *4
Transmit data empty
1A0h
SCI7_TEI
Transmit end
1A1h
SCI7_ERI
1A2h
SCI7_AM
1A4h
SCI8
SCI8_TXI
1A6h
SCI8_TEI
*4
SCI8_ERI
1A8h
Receive error
Address match event
SCI8_RXI *4
1A5h
1A7h
*4
Receive data full
Transmit data empty
Transmit end
*4
Receive error
SCI8_AM
Address match event
SCI9_RXI *4
Receive data full
1ABh
SCI9_TXI *4
Transmit data empty
1ACh
SCI9_TEI
Transmit end
1ADh
SCI9_ERI *4
Receive error
1AEh
SCI9_AM
Address match event
1AAh
1BCh
SCI9
SPI0_SPRI
Receive data full
1BDh
SPI0_SPTI
Transmit data empty
1BEh
SPI0_SPII
Idle
1BFh
SPI0_SPEI
Receive error
1C0h
SPI0_SPTEND
Transmit end
1C1h
SPI0
SPI1_SPRI
Receive data full
1C2h
SPI1_SPTI
Transmit data empty
1C3h
SPI1_SPII
Idle
1C4h
SPI1_SPEI
Receive error
1C5h
SPI1_SPTEND
Transmit end
Note 1.
Note 2.
Note 3.
Note 4.
SPI1
Only pulse (edge detection) is supported.
ELSR8 to ELSR11, ELSR14 to ELSR17, and ELSR18 can select this event.
This event can occur in Snooze mode.
This event is not supported in FIFO mode.
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19.3
19. Event Link Controller (ELC)
Operation
19.3.1
Relation between Interrupt Handling and Event Linking
Event number for an event link is the same as that for the associated interrupt source. For information on generating
event signals, see the explanation in the chapter for each event source module.
19.3.2
Linking Events
When an event occurs and that event is already set as a trigger in the Event Link Setting Register (ELSRn), the associated
module is activated. The operation of the module must be set up in advance. Table 19.4 lists the operations of modules
when an event occurs.
Table 19.4
Module operations when event occurs
Module
Operations when event occurs
GPT
ADC12
Start A/D conversion
DAC12
Start D/A conversion
I/O ports
Change pin output based on the EORR (reset) or EOSR (set)
Latch pin state to EIDR
The following ports can be used for the ELC:
PORT 1
PORT 2
PORT 3
PORT 4.
CTSU
Start measurement operation
DTC
Start DTC data transfer
19.3.3
Start counting
Stop counting
Clear counting
Up counting
Down counting
Input capture.
Example Procedure for Linking Events
To link events:
1. Set the operation of the module for which an event is to be linked.
2. Set the appropriate ELSRn register for the module to be linked.
3. Set the ELCR.ELCON bit to 1 to enable linkage of all events.
4. Configure the module from which an event is output and activate the module. The link between the two modules is
now active.
5. To stop event linkage of modules individually, set 000000000b in the ELSRn.ELS[8:0] bits associated with the
modules. To stop linkage of all events, set the ELCR.ELCON bit to 0.
If the event link output from the RTC is to be used, set the ELC after the RTC is set, for example, for initialization and
time settings. Unintended events can be generated if the RTC settings are made after the ELC settings.
19.4
19.4.1
Usage Notes
Linking DMAC or DTC Transfer End Signals as Events
When linking the DMAC or DTC transfer end signals as events, do not set the same peripheral module as the DMAC or
DTC transfer destination and event link destination. If set, the peripheral module might be started before DMAC or DTC
transfer to the peripheral module is complete.
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19.4.2
19. Event Link Controller (ELC)
Setting Clocks
To link events, you must enable the ELC and the related modules. The modules cannot operate if the related modules are
in the module-stop state or in the specific low power mode in which the module is stopped (Software Standby mode or
Deep Software Standby mode). Some modules can perform in Snooze mode. For more information, see Table 19.3 and
section 11, Low Power Modes.
19.4.3
Settings for the Module-Stop Function
The Module Stop Control Register C (MSTPCRC) can enable or disable ELC operation. The ELC is initially stopped
after reset. Releasing the module-stop state enables access to the registers. The ELCON bit must be set to 0 before
disabling ELC operation using the Module Stop Control Register. For more information, see Table 19.3 and section 11,
Low Power Modes.
19.4.4
ELC Delay Time
In Figure 19.2, module A uses ELC and accesses module B through the ELC. There is a delay time in the ELC module
between module A and module B. See Table 19.5.
Table 19.5
ELC delay time
Clock domain
Clock frequency
ELC delay time
clock_A = clock_B
clock_A = clock_B
0 cycle
clock_A ≠ clock_B
clock_A = clock_B
1 cycle to 2 cycles
clock_A > clock_B
1 cycle to 2 cycles of B
clock_A < clock_B
1 cycle to 2 cycles of A
Delay time
Event source
Event destination
Module A
Module B
clock = clock_A
Figure 19.2
ELC
clock = clock_B
ELC delay time
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20.
I/O Ports
20.1
Overview
20. I/O Ports
The I/O port pins operate as general I/O port pins, I/O pins for peripheral modules, interrupt input pins, analog I/O, port
group function for the ELC, or bus control pins. All pins operate as input pins immediately after a reset, and pin functions
are switched by register settings. The I/O ports and peripheral modules for each pin are specified in the associated
registers.
Figure 20.1 shows a connection diagram for the I/O port registers. The configuration of the I/O ports differs depending
on the package. Table 20.1 lists the I/O port specifications by package, and Table 20.2 lists the port functions.
PCR
Peripheral output
enable
1
0
PDR
DSCR, NCODR
Peripheral output
1
0
EOSR
POSR
ELC
Internal peripheral bus
PODR
PORR
EORR
PSEL
PMR
ELC
Edge detect
EOF, EOR
Peripheral input/
interrupt
EIDR
PIDR
Read control
ISEL
ASEL
Analog
input or output
Figure 20.1
Note:
Connection diagram for I/O port registers
Figure 20.1 shows a basic port configuration. The configuration differs depending on the ports.
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Table 20.1
20. I/O Ports
I/O port specifications
Package
Port
PORT0
Package
Number of
pins
144 pins, 145 pins
P000 to P009, P014, P015
Number of
pins
100 pins
12 P000 to P008, P014, P015
11
PORT1
P100 to P115
16 P100 to P115
16
PORT2
P200 to P214
15 P200, P201, P205 to P214
12
PORT3
P300 to P313
14 P300 to P307
8
PORT4
P400 to P415
16 P400 to P415
16
PORT5
P500 to P506, P508, P511, P512
10 P500 to P504, P508
6
PORT6
P600 to P605, P608 to P614
13 P600 to P602, P608 to P610
6
PORT7
P700 to P705, P708 to P713
12 P708
1
PORT8
P800, P801
2 N/A
0
Total pins
Table 20.2
Total pins
76
I/O port functions
Port
PORT0
110
Port name
Open-drain
output
Input pull-up
P000 to P009, P014, P015
PORT1
P100 to P115
PORT2
P200
P201
P202 to P204, P207 to P214
P205, P206
PORT3
PORT4
Drive capacity
switching
5 V tolerant
-
-
Low, middle, high
-
-
-
-
-
-
Low, middle, high
-
Low, middle, high
P300 to P313
Low, middle, high
-
P400, P401, P407 to P415
Low, middle, high
P402 to P406
Low, middle, high
-
PORT5
P500 to P506, P508
Low, middle, high
-
P511, P512
Low, middle, high
PORT6
P600 to P605, P608 to P614
Low, middle, high
-
PORT7
P700 to P705
Low, middle, high
-
P708 to P713
Low, middle, high
PORT8
P800, P801
Low, middle, high
-
: Available
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20.2
20. I/O Ports
Register Descriptions
20.2.1
Port Control Register 1 (PCNTR1/PODR/PDR)
Address(es): PORT0.PCNTR1 4004 0000h, PORT1.PCNTR1 4004 0020h, PORT2.PCNTR1 4004 0040h, PORT3.PCNTR1 4004 0060h,
PORT4.PCNTR1 4004 0080h, PORT5.PCNTR1 4004 00A0h, PORT6.PCNTR1 4004 00C0h, PORT7.PCNTR1 4004 00E0h,
PORT8.PCNTR1 4004 0100h
PORT0.PODR 4004 0000h, PORT1.PODR 4004 0020h, PORT2.PODR 4004 0040h, PORT3.PODR 4004 0060h,
PORT4.PODR 4004 0080h, PORT5.PODR 4004 00A0h, PORT6.PODR 4004 00C0h, PORT7.PODR 4004 00E0h,
PORT8.PODR 4004 0100h
PORT0.PDR 4004 0002h, PORT1.PDR 4004 0022h, PORT2.PDR 4004 0042h, PORT3.PDR 4004 0062h,
PORT4.PDR 4004 0082h, PORT5.PDR 4004 00A2h, PORT6.PDR 4004 00C2h, PORT7.PDR 4004 00E2h,
PORT8.PDR 4004 0102h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PDR15 PDR14 PDR13 PDR12 PDR11 PDR10 PDR09 PDR08 PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
PDRn
Pmn Direction
0: Input (functions as an input pin)
1: Output (functions as an output pin).
R/W
b31 to b16
PODRn
Pmn Output Data
0: Low output
1: High output.
R/W
m = 0 to 8
n = 00 to 15
The Port Control Register 1 (PCNTR1/PODR/PDR) is a 32-bit and 16-bit read/write register that controls port direction
and port output data.
The PCNTR1 specifies the port direction and the output data, and is accessed in 32-bit units. The PDRn (bits [15:0] in
PCNTR1) and PODRn (bits [31:16] in PCNTR1) respectively, are accessed in 16-bit units.
The PDRn bits select the input or output direction for individual pins on the associated port when the pins are configured
as general I/O pins. Each pin on port m is associated with a PORTm.PCNTR1.PDRn bit. The I/O direction can be
specified in 1-bit units. Bits associated with non-existent pins are reserved. The write value should always be 0. P200 is
input only, so PORT2.PCNTR1.PDR00 is reserved. The PDRn bit in the PORTm.PCNTR1 register serves the same
function as the PDR bit in the PFS.PmnPFS register.
The PODRn bits hold data to be output from the general I/O pins. Bits associated with non-existent pins are reserved.
The write value should be 0. P200 is input only, so PORT2.PCNTR1.PODR00 is reserved. Writes to P200 have no effect.
The PODRn bit in the PORTm.PCNTR1 register serves the same function as the PODR bit in the PFS.PmnPFS register.
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20.2.2
20. I/O Ports
Port Control Register 2 (PCNTR2/EIDR/PIDR)
Address(es): PORT0.PCNTR2 4004 0004h, PORT1.PCNTR2 4004 0024h, PORT2.PCNTR2 4004 0044h, PORT3.PCNTR2 4004 0064h,
PORT4.PCNTR2 4004 0084h, PORT5.PCNTR2 4004 00A4h, PORT6.PCNTR2 4004 00C4h, PORT7.PCNTR2 4004 00E4h,
PORT8.PCNTR2 4004 0104h
PORT0.EIDR 4004 0004h, PORT1.EIDR 4004 0024h, PORT2.EIDR 4004 0044h, PORT3.EIDR 4004 0064h,
PORT4.EIDR 4004 0084h, PORT5.EIDR 4004 00A4h, PORT6.EIDR 4004 00C4h, PORT7.EIDR 4004 00E4h,
PORT8.EIDR 4004 0104h
PORT0.PIDR 4004 0006h, PORT1.PIDR 4004 0026h, PORT2.PIDR 4004 0046h, PORT3.PIDR 4004 0066h,
PORT4.PIDR 4004 0086h, PORT5.PIDR 4004 00A6h, PORT6.PIDR 4004 00C6h, PORT7.PIDR 4004 00E6h,
PORT8.PIDR 4004 0106h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
EIDR15 EIDR14 EIDR13 EIDR12 EIDR11 EIDR10 EIDR09 EIDR08 EIDR07 EIDR06 EIDR05 EIDR04 EIDR03 EIDR02 EIDR01 EIDR00
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIDR15 PIDR14 PIDR13 PIDR12 PIDR11 PIDR10 PIDR09 PIDR08 PIDR07 PIDR06 PIDR05 PIDR04 PIDR03 PIDR02 PIDR01 PIDR00
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b15 to b0
PIDRn
Pmn State
0: Low level
1: High level.
R
b31 to b16
EIDRn
Port Event Input Data*1
When an ELC_PORTx occurs:
0: Low input
1: High input.
R
m = 0 to 8
n = 00 to 15
x = 1 to 4
Note 1.
Supported for PORT1 to PORT4.
The Port Control Register 2 (PCNTR2/EIDR/PIDR) allows read access to the Pmn state and port event input data using
32-bit or 16-bit access.
The PCNTR2 specifies the Pmn state and port event input data, and is accessed in 32-bit units. The PIDRn (bits [15:0] in
PCNTR2) and EIDRn (bits [31:16] in PCNTR2) respectively, are accessed in 16-bit units. Bits associated with nonexistent pins are reserved. Reserved bits are read as undefined.
The PIDRn bits reflect individual pin states of the port, regardless of the values set in PmnPFS.PMR and
PORTm.PCNTR1.PDRn. The PIDRn bit in the PORTm.PCNTR2 register serves the same function as the PIDR bit in the
PFS.PmnPFS register.
A pin state cannot be reflected in PIDRn when one of the following functions is enabled:
Main clock oscillator (MOSC)
CS area controller (CSC)
Analog function (ASEL = 1)
Capacitive Touch Sensing Unit (CTSU)
USB 2.0 Full-Speed (USBFS) module.
The EIDRn bits latch a pin state when an ELC_PORTx signal occurs. Pin states can only be input to EIDRn when
PmnPFS.PMR and PORTm.PCNTR1.PDRn are 0. When the PmnPFS.ASEL bit is set to 1, the associated pin state is not
reflected in EIDRn.
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20.2.3
20. I/O Ports
Port Control Register 3 (PCNTR3/PORR/POSR)
Address(es): PORT0.PCNTR3 4004 0008h, PORT1.PCNTR3 4004 0028h, PORT2.PCNTR3 4004 0048h, PORT3.PCNTR3 4004 0068h,
PORT4.PCNTR3 4004 0088h, PORT5.PCNTR3 4004 00A8h, PORT6.PCNTR3 4004 00C8h, PORT7.PCNTR3 4004 00E8h,
PORT8.PCNTR3 4004 0108h
PORT0.PORR 4004 0008h, PORT1.PORR 4004 0028h, PORT2.PORR 4004 0048h, PORT3.PORR 4004 0068h,
PORT4.PORR 4004 0088h, PORT5.PORR 4004 00A8h, PORT6.PORR 4004 00C8h, PORT7.PORR 4004 00E8h,
PORT8.PORR 4004 0108h
PORT0.POSR 4004 000Ah, PORT1.POSR 4004 002Ah, PORT2.POSR 4004 004Ah, PORT3.POSR 4004 006Ah,
PORT4.POSR 4004 008Ah, PORT5.POSR 4004 00AAh, PORT6.POSR 4004 00CAh, PORT7.POSR 4004 00EAh,
PORT8.POSR 4004 010Ah
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Value after reset:
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
POSR
15
POSR
14
POSR
13
POSR
12
POSR
11
POSR
10
POSR
09
POSR
08
POSR
07
POSR
06
POSR
05
POSR
04
POSR
03
POSR
02
POSR
01
POSR
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
POSRn
Pmn Output Set
0: No effect on output
1: High output.
W
b31 to b16
PORRn
Pmn Output Reset
0: No effect on output
1: Low output.
W
m = 0 to 8
n = 00 to 15
The Port Control Register 3 (PCNTR3/PORR/POSR) is a 32-bit and 16-bit write register that controls the setting or
resetting of the port output data.
The PCNTR3 controls the setting or resetting of the port output data, and is accessed in 32-bit units. The POSRn (bits
[15:0] in PCNTR3) and PORRn (bits [31:16] in PCNTR3) respectively, are accessed in 16-bit units.
POSR changes PODR when set by a software write. For example, for P100, when PORT1.PCNTR3.POSR00 is 1,
PORT1.PCNTR1.PODR00 outputs 1. Bits associated with non-existent pins are reserved. The write value should always
be 0. P200 is input only, so PORT2.PCNTR3.POSR00 is reserved.
PORR changes PODR when reset by a software write. For example, for P100, when PORT1.PCNTR3.PORR00 is 1,
PORT1.PCNTR1.PODR00 outputs 0. Bits associated with non-existent pins are reserved. The write value should always
be 0. P200 is input only, so PORT2.PCNTR3.PORR00 is reserved.
Note:
Note:
When EORRn or EOSRn is set, writing is prohibited to PODRn, PORRn, and POSRn.
PORRn and POSRn should not be set at the same time.
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20.2.4
20. I/O Ports
Port Control Register 4 (PCNTR4/EORR/EOSR)
Address(es): PORT1.PCNTR4 4004 002Ch, PORT2.PCNTR4 4004 004Ch, PORT3.PCNTR4 4004 006Ch, PORT4.PCNTR4 4004 008Ch
PORT1.EORR 4004 002Ch, PORT2.EORR 4004 004Ch, PORT3.EORR 4004 006Ch, PORT4.EORR 4004 008Ch
PORT1.EOSR 4004 002Eh, PORT2.EOSR 4004 004Eh, PORT3.EOSR 4004 006Eh, PORT4.EOSR 4004 008Eh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Value after reset:
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
EOSR
15
EOSR
14
EOSR
13
EOSR
12
EOSR
11
EOSR
10
EOSR
09
EOSR
08
EOSR
07
EOSR
06
EOSR
05
EOSR
04
EOSR
03
EOSR
02
EOSR
01
EOSR
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
EOSRn
Pmn Event Output Set
When an ELC_PORTx occurs:
0: No effect on output
1: High output.
R/W
b31 to b16
EORRn
Pmn Event Output Reset
When an ELC_PORTx occurs:
0: No effect on output
1: Low output.
R/W
m = 1 to 4
n = 00 to 15
x = 1 to 4
The Port Control Register 4 (PCNTR4/EORR/EOSR) is a 32-bit and 16-bit read/write register that controls the setting or
resetting of the port output data by an event input from the ELC.
The PCNTR4 controls the setting or resetting of the port output data by an event input from the ELC, and is accessed in
32-bit units. The EOSRn (bits [15:0] in PCNTR4) and EORRn (bits [31:16] in PCNTR4) respectively, are accessed in
16-bit units.
EOSR changes PODR when set because an ELC_PORTx signal occurs. For example, for P100, if
PORT1.PCNTR4.EOSR00 is set to 1 when the ELC_PORTx occurs, PORT1.PCNTR1.PODR00 outputs 1. Bits
associated with non-existent pins are reserved. The write value must always be 0. P200 is input only, so
PORT2.PCNTR4.EOSR00 is reserved.
EORR changes PODR when reset because an ELC_PORTx signal occurs. For example, for P100, if
PORT1.PCNTR4.EORR00 is set to 1 when the ELC_PORTx occurs, PORT1.PCNTR1.PODR00 outputs 0. Bits
associated with non-existent pins are reserved. The write value must always be 0. P200 is input only, so
PORT2.PCNTR4.EORR00 is reserved.
Note:
Note:
When EORRn or EOSRn is set, writing is prohibited to PODRn, PORRn, and POSRn.
EORRn and EOSRn should not be set at the same time.
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20.2.5
20. I/O Ports
Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY)
(m = 0 to 8; n = 00 to 15)
Address(es): PFS.P000PFS 4004 0800h to PFS.P015PFS 4004 083Ch, PFS.P100PFS 4004 0840h to PFS.P115PFS 4004 087Ch,
PFS.P200PFS 4004 0880h to PFS.P214PFS 4004 08B8h, PFS.P300PFS 4004 08C0h to PFS.P313PFS 4004 08F4h,
PFS.P400PFS 4004 0900h to PFS.P415PFS 4004 093Ch, PFS.P500PFS 4004 0940h to PFS.P512PFS 4004 0970h,
PFS.P600PFS 4004 0980h to PFS.P614PFS 4004 09B8h, PFS.P700PFS 4004 09C0h to PFS.P713PFS 4004 09F4h,
PFS.P800PFS 4004 0A00h to PFS.P801PFS 4004 0A04h
PFS.P000PFS_HA 4004 0802h to PFS.P015PFS_HA 4004 083Eh, PFS.P100PFS_HA 4004 0842h to PFS.P115PFS_HA 4004 087Eh,
PFS.P200PFS_HA 4004 0882h to PFS.P214PFS_HA 4004 08BAh, PFS.P300PFS_HA 4004 08C2h to PFS.P313PFS_HA 4004 08F6h,
PFS.P400PFS_HA 4004 0902h to PFS.P415PFS_HA 4004 093Eh, PFS.P500PFS_HA 4004 0942h to PFS.P512PFS_HA 4004 0972h,
PFS.P600PFS_HA 4004 0982h to PFS.P614PFS_HA 4004 09BAh, PFS.P700PFS_HA 4004 09C2h to PFS.P713PFS_HA 4004 09F6h,
PFS.P800PFS_HA 4004 0A02h to PFS.P801PFS_HA 4004 0A06h
PFS.P000PFS_BY 4004 0803h to PFS.P015PFS_BY 4004 083Fh, PFS.P100PFS_BY 4004 0843h to PFS.P115PFS_BY 4004 087Fh,
PFS.P200PFS_BY 4004 0883h to PFS.P214PFS_BY 4004 08BBh, PFS.P300PFS_BY 4004 08C3h to PFS.P313PFS_BY 4004 08F7h,
PFS.P400PFS_BY 4004 0903h to PFS.P415PFS_BY 4004 093Fh, PFS.P500PFS_BY 4004 0943h to PFS.P512PFS_BY 4004 0973h,
PFS.P600PFS_BY 4004 0983h to PFS.P614PFS_BY 4004 09BBh, PFS.P700PFS_BY 4004 09C3h to PFS.P713PFS_BY 4004 09F7h,
PFS.P800PFS_BY 4004 0A03h to PFS.P801PFS_BY 4004 0A07h
b31
b30
b29
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
ASEL
ISEL
EOF
EOR
0*2
0
0
0
Value after reset:
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
PMR
0
0
0
0
0
0
0
0
0*2
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
DSCR[1:0]
—
—
—
NCOD
R
—
PCR
—
PDR
PIDR
PODR
0*2
0
0
0
0
0
0*2
0
0
x
0
PSEL[4:0]
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
PODR
Port Output Data
0: Low output
1: High output.
R/W
b1
PIDR
Pmn State
0: Low level
1: High level.
R
b2
PDR
Port Direction
0: Input (functions as an input pin)
1: Output (functions as an output pin).
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
PCR
Pull-up Control
0: Disable input pull-up
1: Enable input pull-up.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
NCODR
N-Channel Open-Drain Control
0: CMOS output
1: NMOS open-drain output.
R/W
b9 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b11, b10
DSCR[1:0]
Port Drive Capability
b11 b10
R/W
b13, b12
EOF/EOR
Event on Falling/Event on
Rising*1
b13 b12
R/W
b14
ISEL
IRQ Input Enable
0: Not used as an IRQn input pin
1: Used as an IRQn input pin.
R/W
b15
ASEL
Analog Input Enable
0: Not used as analog pin
1: Used as analog pin.
R/W
b16
PMR
Port Mode Control
0: Used as a general I/O pin
1: Used as an I/O port for peripheral functions.
R/W
b23 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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0
1
1
0
0
1
1
0: Low drive
1: Middle drive
0: Setting prohibited
1: High drive.
0: Don’t care
1: Detect rising edge
0: Detect falling edge
1: Detect both edges.
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20. I/O Ports
Bit
Symbol
Bit name
Description
R/W
b28 to b24
PSEL[4:0]
Peripheral Select
These bits select the peripheral function. For individual pin
functions, see the associated tables in this chapter.
R/W
b31 to b29
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Note 1.
Note 2.
P010PFS to P013PFS, P507PFS, P509PFS, P510PFS, P606PFS, P607PFS, P706PFS, and P707PFS for 32-bit, 16-bit, and
8-bit access are not available.
Supported for PORT1 to PORT4.
The initial value of P000 to P007, P108, P109, P110, P201 and P300 is not 0000_0000h.
P000 to P007 is 0000_8000h, P108 is 0001_0410h, P109 is 0001_0400h, P110 is 0001_0010h, P201 is 0000_0010h, and
P300 is 0001_0010h.
The Port mn Pin Function Select register (PmnPFS/PmnPFS_HA/PmnPFS_BY) is a 32-bit, 16-bit, and 8-bit read/write
control register that selects the port mn pin function, and is accessed in 32-bit units. PmnPFS_HA (bits [15:0] in
PmnPFS) is accessed in 16-bit units. PmnPFS_BY (bits [7:0]) is accessed in 8-bit units.
The PDR/PIDR/PODR bits serve the same function as the PCNTR. When these bits are read, the PCNTR value is read.
The PCR bit enables or disables an input pull-up resistor on the individual port pins. When a pin is in the input state with
the associated bit in PmnPFS.PCR set to 1, the pull-up resistor connected to the pin is enabled. When a pin is set as an
external bus pin, a general port output pin, or a peripheral function output pin, the pull-up resistor for the pin is disabled
regardless of the PCR setting. The pull-up resistor is also disabled in the reset state. Bits associated with non-existent
pins are reserved. The write value should be 0.
The NCODR bit specifies the output type for the port pins. Bits associated with non-existent pins are reserved. The write
value should be 0.
The DSCR bit switches the drive capacity of the port. If the drive capacity of a pin is fixed, the associated bit is a
read/write bit, but the drive capacity cannot be changed. Bits associated with non-existent pins are reserved. Reserved
bits are read as 0. The write value should be 0.
The EOR and EOF bits select the edge detection method for the port group input signal. These bits support rising, falling,
or both edge detections. When the EOR and EOF bits are set to 01b, 10b, or 11b, the input enable of the I/O cell is
asserted. Following that, the event pulse is input from the external pin, and the GPIO outputs the event pulse to the ELC.
Bits associated with non-existent pins are reserved. The write value should be 0.
The ISEL bit specifies IRQ input pins. This setting can be used in combination with the peripheral functions, although an
IRQn (external pin interrupt) of the same number must only be enabled for one pin.
The ASEL bit specifies analog pins. When a pin is set as an analog pin by this bit:
1. Specify it as a general I/O port with the Port Mode Control bit (PmnPFS.PMR).
2. Disable the pull-up resistor with the Pull-up Control bit (PmnPFS.PCR).
3. Specify the input in the Port Direction bit (PmnPFS.PDR). The pin state cannot be read at this point. The PmnPFS
register is protected by the Write-Protect Register (PWPR). Release write-protect before modifying the register.
The ISEL bit for an unspecified IRQn is reserved. The ASEL bit for an unspecified analog input/output pin is reserved.
The PMR bit specifies the port pin function. Bits associated with non-existent pins are reserved. The write value should
be 0.
The PSEL[4:0] bits assign the peripheral function.
For details on the peripheral settings for each product, see section 20.6, Peripheral Select Settings for each Product.
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20.2.6
20. I/O Ports
Write-Protect Register (PWPR)
Address(es): PMISC.PWPR 4004 0D03h
b7
b6
B0WI PFSWE
Value after reset:
1
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
PFSWE
PmnPFS Register Write
Enable
0: Writing to the PmnPFS register is disabled
1: Writing to the PmnPFS register is enabled.
R/W
b7
B0WI
PFSWE Bit Write Disable
0: Writing to the PFSWE bit is enabled
1: Writing to the PFSWE bit is disabled.
R/W
PFSWE bit (PmnPFS Register Write Enable)
Writing to the PmnPFS register is enabled only when the PFSWE bit is set to 1. You must first write 0 to the B0WI bit
before setting PFSWE to 1.
B0WI bit (PFSWE Bit Write Disable)
Writing to the PFSWE bit is enabled only when the B0WI bit is set to 0.
20.2.7
Ethernet Control Register (PFENET)
Address(es): PMISC.PFENET 4004 0D00h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
PHYM
ODE0
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
PHYMO
DE0
Ethernet Mode Setting ch0
0: RMII mode (ETHERC channel 0)
1: MII mode (ETHERC channel 0).
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
PHYMODE0 bit (Ethernet Mode Setting ch0)
The PHYMODE0 bit specifies the PHY mode of ETHERC channel 0. Select the same mode as that specified in the pin
function select bits (PmnPFS.PSEL[4:0]). When the signals for the RMII mode are specified in the PmnPFS.PSEL[4:0]
bits, set the PHYMODE bit to 0 (RMII mode). When the signals for the MII mode are specified in the
PmnPFS.PSEL[4:0] bits, set the PHYMODE bit to 1 (MII mode).
20.3
20.3.1
Operation
General I/O Ports
All pins except P000 to P007, P108 to P110, and P300 operate as general I/O ports after reset. General I/O ports are
organized as 16 bits per port and can be accessed by port with the Port Control Registers (PCNTRn, where n = 1 to 4), or
by individual pins with the Port mn Pin Function Select register. For details on these registers, see section 20, Register
Descriptions.
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20. I/O Ports
Each port has the following bits:
Port Direction bit (PDRn), which selects input or output direction
Port Output Data bit (PODRn), which holds data for output
Port Input Data bit (PIDRn), which indicates the pin state
Event Input Data bit (EIDRn), which indicates the pin state when an ELC_PORT1, 2, 3, or 4 signal occurs
Port Output Set bit (POSRn), which indicates the output value when a software write occurs
Port Output Reset bit (PORRn), which indicates the output value when a software write occurs
Event Output Set bit (EOSRn), which indicates the output value when an ELC_PORT1, 2, 3 or 4 signal occurs
Event Output Reset bit (EORRn), which indicates the output value when an ELC_PORT1, 2, 3 or 4 signal occurs.
20.3.2
Port Function Select
The following port functions are available for configuring each pin:
I/O configuration: Complementary or open-drain output, pull-up control, and drive strength
General I/O port: Port direction, output data setting, and reading input data
Alternate function: Configured function mapping to the pin.
Each pin is associated with a Port mn Pin Function Select register (PmnPFS), which includes the associated PODR,
PIDR, and PDR bits. In addition, the PmnPFS register includes:
PCR: Pull-up resistor control bit that turns the input pull-up MOS on or off
NCODR: N-channel open-drain control bit that selects the output type for each pin
DSCR: Drive capacity control bit that selects the drive capacity
EOR: Event on rising bit used to detect rising edges on the port input
EOF: Event on falling bit used to detect falling edges on the port input
ISEL: IRQ input enable bit to specify an IRQ input pin
ASEL: Analog input enable bit to specify an analog pin
PMR: Port mode control bit to specify the pin function of each port
PSEL[4:0]: Port function select bits to select the associated peripheral function.
These configurations can be made by a single-register access to the Port mn Pin Function Select register. For details, see
section 20, Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 8; n = 00 to 15).
20.3.3
Port Group Function for the ELC
In the MCU, PORT1 to PORT4 are assigned for the port group function.
20.3.3.1
Behavior when ELC_PORT1, 2, 3, or 4 is input from the ELC
The MCU supports the two functions described in this section when an ELC_PORT1, 2, 3, or 4 signal comes from the
ELC.
(1)
Input to EIDR
For the GPI function (PDR = 0 and PMR = 0 in the PmnPFS register), when an ELC_PORT1, 2, 3, or 4 signal comes
from the ELC, the input enable of the I/O cell is asserted, and data from the external pins are read into the EIDR bit.
For the GPO function (PDR = 1) or the peripheral mode (PMR = 1), 0 is input into the EIDR bit from the external pins.
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20. I/O Ports
ELC
ELC_PORT1, 2, 3, or 4
EIDR
PAD
en
Figure 20.2
(2)
Event ports input data
Output from PODR by EOSR/EORR
When an ELC_PORT1, 2, 3, or 4 signal occurs, the data is output from the PODR to the external pin based on the
EOSR/EORR bit settings as follows:
If EOSR is set to 1, when ELC_PORT1, 2, 3, or 4 signal occurs, the PODR register outputs 1 to the external pin.
Otherwise, when EOSR = 0, the PODR value is kept.
If EORR is set to 1, when ELC_PORT1, 2, 3, or 4 signal occurs, the PODR register outputs 0 to the external pin.
Otherwise, when EORR = 0, the PODR value is kept.
See Figure 20.3.
EOSR
ELC
PODR
PAD
EORR
en
ELC_PORT1, 2, 3, or 4
Figure 20.3
Event ports output data
20.3.3.2
Behavior when an event pulse is output to the ELC
To output the event pulse from the external pins to the ELC, set the EOR/EOF bits in the PmnPFS register. For details,
see section 20.2.5, Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 8; n = 00 to
15). When the EOR/EOF bits are set, the input enable of the I/O cell is asserted.
Data from the external pin is the input. For example, for PORT1, when the data is input from P100 to P115, the data of
those 16 pins is organized by OR logic. This data is formed into a one-shot pulse that goes to the ELC. The operation of
PORT2 to PORT4 is the same. See Figure 20.4.
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20. I/O Ports
EOR
EOF
ELC
PAD
Event pulse
Edge detect
From other PADs
Figure 20.4
20.4
Generation of event pulse
Handling of Unused Pins
Table 20.3 shows how to handle unused pins.
Table 20.3
Handling of unused pins
Pin name
Handling when unused
MD
Use as a mode pin
RES
Connect to VCC through a resistor (pulling up)
USB_DP
Keep pin open
USB_DM
Keep pin open
P200/NMI
Connect to VCC through a resistor (pulling up)
EXTAL
When the main clock oscillator is not used, set the MOSCCR.MOSTP bit to 1 (general port P212).
When this pin is not used as port P212, configure it in the same way as ports 1 to 8.
XTAL
When the main clock oscillator is not used, set the MOSCCR.MOSTP bit to 1 (general port P213).
When the external clock is input to the EXTAL pin, the XTAL pin functions as P213.
When this pin is not used as port P213, configure it in the same way as ports 1 to 8.
XCIN
Connect to VSS through a resistor (pulling down)
XCOUT
Keep pin open
P000 to P009
If the direction is set to input (PCNTR1.PDRn = 0), connect the associated pin to AVCC0 (pulled up)
through a resistor or to AVSS0 (pulled down) through a resistor*1
If the direction is set to output (PCNTR1.PDRn = 1), release the pin*1.
P1x to P8x
If the direction is set to input (PCNTR1.PDRn = 0), connect the associated pin to VCC (pulled up) through a
resistor or to VSS (pulled down) through a resistor*1,*2
If the direction is set to output (PCNTR1.PDRn = 1), release the pin*1, *3.
VREFH0, VREFH
Connect to AVCC0
VREFL0, VREFL
Connect to AVSS0
VBATT
Connect to VCC or VSS
Note 1.
Note 2.
Note 3.
Clear the PmnPFS.PMR, PmnPFS.ISEL, PmnPFS.PCR, and PmnPFS.ASEL bits to 0.
P108, P110, and P300 are recommended for pull up VCC (pulled up) through a resistor, because these pins are input pull-up
enabled from the initial value (PmnPFS.PCR=1).
P109 is recommended for setting the direction to output (PCNTR1.PDRn = 1), because this pin is output from the initial value.
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20.5
20.5.1
20. I/O Ports
Usage Notes
Procedure for Specifying the Pin Functions
To specify the I/O pin functions:
1. Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register.
2. Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register.
3. Clear the Port Mode Control bit in the PMR for the target pin to select the general I/O port.
4. Specify the I/O function for the pin through the PSEL[4:0] bit settings in the PmnPFS register.
5. Set the PMR bit to 1 as required to switch to the selected I/O function for the pin.
6. Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register.
7. Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register.
20.5.2
Procedure for Using Port Group Input
To use the port group input (PORT1 to PORT4):
1. Set the ELSRx.ELS[8:0] bits to 0000 0000b to ignore unexpected pulses. For more information, see section 19,
Event Link Controller (ELC).
2. Set the EOF/EOR bit of the PmnPFS register to specify the rising, falling, or both edge detections.
3. Execute a dummy read or wait for a short time, for example 100 ns. Ignoring of unexpected pulses depends on the
initial value of the external pin.
4. Set the ELSRx.ELS[8:0] bits to enable the event signals.
20.5.3
Port Output Data Register (PODR) Summary
This register outputs data as follows:
1. Output 0 if PCNTR4.EORRn is set to 1 when an ELC_PORT1, 2, 3, or 4 signal occurs.
2. Output 1 if PCNTR4.EOSRn is set to 1 when an ELC_PORT1, 2, 3, or 4 signal occurs.
3. Output 0 if PCNTR3.PORRn is set to 1.
4. Output 1 if PCNTR3.POSRn is set to 1.
5. Output 0 or 1 because PCNTR1.PODRn is set.
6. Output 0 or 1 because PmnPFS.PODRn is set.
Numbers in this list correspond to the priority for writing to the PODR. For example, if 1. and 3. from the list occur at the
same time, the higher priority event 1. is executed.
20.5.4
Notes on Using Analog Functions
To use an analog function, set the Port Mode Control bit (PMR) and Port Direction bit (PDR) to 0 so that the pin acts as
a general input port. Next, set the Analog Input Enable bit (ASEL) in the Port mn Pin Function Select register
(PmnPFS.ASEL) to 1.
20.5.5
I/O Buffer Specification
P402, P403, and P404 can be used as the RTC input, AGT input, and other peripheral functions.
Table 20.4 lists the P402, P403, P404 specifications.
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Table 20.4
20. I/O Ports
P402, P403, P404 specifications
Functions
I/O port
RTC and AGT
RTC and AGT
input enable register
RTC
Other peripheral
AGT
Other peripheral
enable register
CAC, GPT, CAN, SCI, SSIE, ETHERC (MII),
ETHERC (RMII), SDHI, Interrupt, and PDC
For details, see Table 20.13
Register settings for I/O pin functions on PORT4
P402
VBTICTLR .VCH0INEN RTCIC0
AGTIO0
AGTIO1
P402PFS.PSEL
and PMR
P403
VBTICTLR .VCH1INEN RTCIC1
AGTIO0
AGTIO1
P403PFS.PSEL
and PMR
P404
VBTICTLR .VCH2INEN RTCIC2
—
P404PFS.PSEL
and PMR
These RTC and AGT inputs are controlled by the VBTICTLR register, which has the highest priority for selecting the
RTC and AGT input functions. See Figure 20.5.
The VBTICTLR register is not initialized on reset. Therefore, when not using the RTC or AGT inputs, the associated bit
of the VBTICTLR register must be set to 0 after reset.
For more information on the VBTICTLR register, see section 12.2.2, VBATT Input Control Register (VBTICTLR).
VBATT Input Control Register
VBTICTLR.VCHnINEN
(n = 0 to 2)
PCR
Peripheral output
enable
1
PDR
0
DSCR, NCODR
Peripheral output
1
0
Internal peripheral bus
EOSR
ELC
P402 to P404
POSR
PODR
PORR
EORR
AGT,RTC input
PSEL
PMR
ELC
Edge detect
EOF, EOR
Peripheral input
EIDR
PIDR
Read control
Figure 20.5
P402, P403, P404 diagram
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20.6
20. I/O Ports
Peripheral Select Settings for each Product
This section describes the pin function select configuration by the PmnPFS register. Some pin names have added _A, _B,
and _C suffixes. When assigning IIC, SPI, SSIE, ETHERC, and SDHI functionality, select the functional pins having the
same suffix. The other pins can be selected regardless of the suffix. Assigning the same function to two or more pins
simultaneously is prohibited.
20.7
Notes on the PmnPFS Register Setting
(1) In the Port mn Pin Function Select register (PmnPFS), the PSEL bits must be set when the PMR bit of the target pin
is 0. If the PSEL bits are set when the PMR bit is 1, unexpected edges might be input for the input function or unexpected
pulses might be output to the external pin for the output function.
(2) Only the allowed values (functions) should be specified in the PSEL bits of PmnPFS. If a value that is not allowed for
the register is specified, the correct operation is not guaranteed.
(3) A single function should not be assigned to multiple pins by the PmnPFS register.
(4) PORT0 and PORT5 have the analog functions such as A/D converter and D/A converter. When these pins are used as
an analog function, to avoid loss of resolution, the PMR and PDR bits should be set to 0. After that, the ASEL bit should
be set to 1.
Table 20.5
PSEL[4:0]
settings
00000b (value
after reset)
Register settings for I/O pin functions (PORT0)
Pin
Function
Hi-z/JTAG/SWD
ASEL bit
P000
P002
P003
P004
P005
P006
P007
Hi-Z
AN000/
IVCMP2
ISEL bit
P001
AN001/
IVCMP2
AN002/
IVCMP2
AN007
AN100/
IVCMP2
AN101/
IVCMP2
AN102/
IVCMP2
AN107
IRQ6-DS
IRQ7-DS
IRQ8-DS
IRQ9-DS
IRQ10-DS
IRQ11-DS
DSCR[1:0] bits
Drive capacity control
*1
*1
*1
*1
*1
*1
*1
*1
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
: Available
Note 1.
The drive strength of this port cannot be controlled by PmnPFS.DSCR[1:0] bits.
Table 20.6
PSEL[4:0]
settings
00000b (value
after reset)
Register settings for I/O pin functions (PORT0)
Pin
Function
Hi-Z/JTAG/SWD
ASEL bit
ISEL bit
P008
P009
P014
P015
Hi-Z
AN003
AN004
AN005/
AN105/
DA0/
IVREF3
AN006/
AN106/
DA1/
IVCMP1
IRQ12-DS
IRQ13-DS
DSCR[1:0] bits
Drive capacity control
*1
*1
*1
IRQ13
*1
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
: Available
Note 1.
The drive strength of this port cannot be controlled by PmnPFS.DSCR[1:0] bits.
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S5D5 User’s Manual
Table 20.7
Register settings for I/O pin functions (PORT1)
Pin
PSEL[4:0]
settings
00000b (value
after reset)
20. I/O Ports
Function
Hi-Z/JTAG/SWD
P100
P101
P102
P103
P104
P105
P106
P107
Hi-Z
00001b
AGT
AGTIO0
AGTEE0
AGTO0
—
—
—
AGTOB0
AGTOA0
00010b
GPT
GTETRGA
GTETRGB
GTOWLO
GTOWUP
GTETRGB
GTETRGA
—
—
00011b
GPT*2
GTIOC5B
GTIOC5A
GTIOC2B_A
GTIOC2A_A
GTIOC1B
GTIOC1A
GTIOC8B
GTIOC8A
00100b
SCI
RXD0/MISO0/
SCL0
TXD0/MOSI0/
SDA0
SCK0
CTS0_RTS0/
SS0
RXD8/MISO8/
SCL8
TXD8/MOSI8/
SDA8
SCK8
CTS8_RTS8/
SS8
00101b
SCI
SCK1
CTS1_RTS1/
SS1
—
—
—
—
—
—
00110b
SPI*1
MISOA_A
MOSIA_A
RSPCKA_A
SSLA0_A
SSLA1_A
SSLA2_A
SSLA3_A
—
00111b
IIC*1
SCL1_B
SDA1_B
—
—
—
—
—
01000b
KINT
KR00
KR01
KR02
KR03
KR04
KR05
KR06
KR07
01010b
CAC/ADC12
—
—
ADTRG0
—
—
—
—
—
01011b
BUS
D00[A00/D00]/ D01[A01/D01]/ D02[A02/D02]/ D03[A03/D03]/ D04[A04/D04]/ D05[A05/D05]/ D06[A06/D06]/
DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
D07[A07/D07]/
DQ07
10000b
CAN
—
—
—
CRX0
CTX0
—
—
—
ASEL bit
-
-
-
-
-
-
-
-
ISEL bit
IRQ2
IRQ1
-
-
IRQ1
IRQ0
-
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 464 of 1734
S5D5 User’s Manual
Table 20.8
Register settings for I/O pin functions (PORT1)
Pin
PSEL[4:0]
settings
00000b (value
after reset)
20. I/O Ports
Function
P108
P109
TDO/SWO
P110
TDI
P111
P112
P113
P114
P115
Hi-Z/JTAG/SWD
TMS/SWDIO
Hi-Z
00010b
GPT
GTOULO
GTOVUP
GTOVLO
—
—
—
—
00011b
GPT*2
GTIOC0B_A
GTIOC1A_A
GTIOC1B_A
GTIOC3A_A
GTIOC3B_A
GTIOC2A
GTIOC2B
GTIOC4A
00100b
SCI
—
—
CTS2_RTS2/
SS2
SCK2
TXD2/MOSI2/
SDA2
RXD2/MISO2/
SCL2
—
—
00101b
SCI
CTS9_RTS9/
SS9
TXD9/MOSI9/
SDA9
RXD9/MISO9/
SCL9
SCK9
SCK1
—
—
—
00110b
SPI*1
SSLB0_B
MOSIB_B
MISOB_B
RSPCKB_B
SSLB0_B
—
—
—
01001b
CLKOUT/ACMPHS/RT
C
—
CLKOUT
VCOUT
—
—
—
—
—
01011b
BUS
—
—
—
A05
A04
A03
A02
A01
10000b
CAN
—
CTX1
CRX1
—
—
—
—
—
10010b
SSIE*1
—
—
—
—
SSIBCK0_B
SSILRCK0/SSI SSIRXD0_B
FS0_B
SSITXD0_B
ASEL bit
-
-
-
-
-
-
-
-
ISEL bit
-
-
IRQ3
IRQ4
-
-
-
-
—
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 465 of 1734
S5D5 User’s Manual
Table 20.9
20. I/O Ports
Register settings for I/O pin functions (PORT2)
Pin
PSEL[4:0]
settings
Function
P200
P201
P202
P203
P204
P205
P206
P207
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00001b
AGT
—
—
—
—
AGTIO1
AGTO1
—
—
00010b
GPT
—
—
—
—
GTIW
GTIV
GTIU
—
00011b
GPT*2
—
—
GTIOC5B
GTIOC5A
GTIOC4B
GTIOC4A
—
—
00100b
SCI
—
—
SCK2
CTS2_RTS2/
SS2
SCK4
TXD4/MOSI4/
SDA4
RXD4/MISO4/
SCL4
—
00101b
SCI
—
—
RXD9/MISO9/
SCL9
TXD9/MOSI9/
SDA9
SCK9
CTS9_RTS9/
SS9
—
—
00110b
SPI*1
—
—
MISOB_A
MOSIB_A
RSPCKB_A
SSLB0_A
SSLB1_A
SSLB2_A
00111b
IIC*1
—
—
—
—
SCL0_B
SCL1_A
SDA1_A
—
01001b
CLKOUT/ACMPHS/RT
C
—
—
—
—
—
CLKOUT
—
—
01010b
CAC/ADC12
—
—
—
—
CACREF
—
—
—
01011b
BUS
—
—
WR1/BC1
A19
A18
A16
WAIT
A17
01100b
CTSU
—
—
—
TSCAP
TS00
TSCAP
TS01
TS02
10000b
CAN
—
—
CRX0
CTX0
—
—
—
—
10001b
QSPI
—
—
—
—
—
—
—
QSSL
10010b
SSIE*1
—
—
—
—
SSIBCK0_C
SSILRCK0/SSI SSIDATA0_C
FS0_C
10011b
USBFS
—
—
—
—
USB_OVRCU
RB-DS
USB_OVRCU
RA-DS
10101b
SDHI*1
—
—
SD0DAT6_A
SD0DAT5_A
SD0DAT4_A
SD0DAT3_A
SD0DAT2_A
10110b
ETHERC (MII)
—
—
ET0_ERXD2
ET0_COL
ET0_RX_DV
ET0_WOL
ET0_LINKSTA
—
10111b
ETHERC (RMII)
—
—
—
—
—
ET0_WOL
ET0_LINKSTA
—
ASEL bit
-
-
-
-
-
-
-
-
ISEL bit
NMI
-
IRQ3-DS
IRQ2-DS
-
IRQ1-DS
IRQ0-DS
-
-
*3
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
DSCR[1:0] bits
Drive capacity control
—
USB_VBUSEN —
—
NCODR bit
N-ch open-drain
-
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
-
-
: Available
—: Setting prohibited
Note 1.
Note 2.
Note 3.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
The drive strength of this port cannot be controlled by PmnPFS.DSCR[1:0] bits.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 466 of 1734
S5D5 User’s Manual
Table 20.10
Register settings for I/O pin functions (PORT2)
Pin
PSEL[4:0]
settings
00000b (value
after reset)
20. I/O Ports
Function
Hi-Z/JTAG/SWD
P208
P209
P210
P211
P212
P213
P214
Hi-Z
00001b
AGT
—
—
—
—
AGTEE1
—
00010b
GPT
GTOVL0
GTOVUP
GTIW
GTIV
GTETRGD
GTETRGC
—
GTIU
00011b
GPT*2
—
—
—
—
GTIOC0B
GTIOC0A
—
00101b
SCI
—
—
—
—
RXD1/MISO1/
SCL1
TXD1/MOSI1/
SDA1
—
01010b
CAC/ADC12
—
—
—
—
—
ADTRG1
—
01011b
BUS
CS4
CS5
CS6
CS7
—
—
—
10001b
QSPI
QIO3
QIO2
QIO1
QIO0
—
—
QSPCLK
10101b
SDHI*1
SD0DAT0_B
SD0WP
SD0CD
SD0CMD_B
—
—
SD0CLK_B
10110b
ETHERC (MII)
ET0_LINKSTA
ET0_EXOUT
ET0_WOL
ET0_MDIO
—
—
ET0_MDC
10111b
ETHERC (RMII)
ET0_LINKSTA
ET0_EXOUT
ET0_WOL
ET0_MDIO
—
—
ET0_MDC
11010b
Trace (Debug)
TDATA3
TDATA2
TDATA1
TDATA0
—
—
TCLK
ASEL bit
-
-
-
-
-
-
-
ISEL bit
-
-
-
-
IRQ3
IRQ2
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 467 of 1734
S5D5 User’s Manual
Table 20.11
Register settings for I/O pin functions (PORT3)
Pin
PSEL[4:0]
settings
00000b (value
after reset)
20. I/O Ports
Function
Hi-Z/JTAG/SWD
P300
TCK/SWCLK
P301
P302
P303
P304
P305
P306
P307
Hi-Z
00001b
AGT
—
AGTIO0
—
—
—
—
—
—
00010b
GPT
—
GTOULO
GTOUUP
—
GTOWLO
GTOWUP
GTOULO
GTOUUP
00011b
GPT*2
GTIOC0A_A
GTIOC4B
GTIOC4A
GTIOC7B
GTIOC7A
—
—
—
00100b
SCI
—
RXD2/MISO2/
SCL2
TXD2/MOSI2/
SDA2
—
RXD6/MISO6/
SCL6
TXD6/MOSI6/
SDA6
SCK6
CTS6_RTS6/
SS6
00101b
SCI
—
CTS9_RTS9/
SS9
—
—
—
—
—
—
00110b
SPI*1
SSLB1_B
SSLB2_B
SSLB3_B
—
—
—
—
—
01011b
BUS
—
A06
A07
A08
A09
A10
A11
A12
10001b
QSPI
—
—
—
—
—
QSPCLK
QSSL
QIO0
-
-
-
-
-
-
-
-
ASEL bit
ISEL bit
-
IRQ6
IRQ5
-
IRQ9
IRQ8
-
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 468 of 1734
S5D5 User’s Manual
Table 20.12
20. I/O Ports
Register settings for I/O pin functions (PORT3)
Pin
PSEL[4:0]
settings
Function
P308
P309
P310
P311
P312
P313
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00001b
AGT
—
—
AGTEE1
AGTOB1
AGTOA1
—
00100b
SCI
—
—
—
—
—
—
00101b
SCI
—
RXD3
TXD3
SCK3
CTS3_RTS3/
SS3
—
01010b
CAC/ADC12
—
—
—
—
—
—
01011b
BUS
A13
A14
A15
CS2/RAS
CS3/CAS
A20
10001b
QSPI
QIO1
QIO2
QIO3
—
—
—
10101b
SDHI*1
—
—
—
—
—
SD0DAT7_A
10110b
ETHERC (MII)
—
—
—
—
—
ET0_ERXD3
ASEL bit
-
-
-
-
-
-
ISEL bit
-
-
-
-
-
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
-
-
-
-
-
: Available
—: Setting prohibited
Note 1.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 469 of 1734
S5D5 User’s Manual
Table 20.13
20. I/O Ports
Register settings for I/O pin functions (PORT4)
Pin
PSEL[4:0]
settings
Function
P400
P401
P402
P403
P404
P405
P406
P407
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00001b
AGT
AGTIO1
—
—
—
—
—
—
AGTIO0
00010b
GPT
—
GTETRGA
—
—
—
—
—
—
00011b
GPT*3
GTIOC6A
GTIOC6B
—
GTIOC3A
GTIOC3B
GTIOC1A
GTIOC1B
—
00100b
SCI
SCK4
CTS4_RTS4/
SS4
—
—
—
—
—
CTS4_RTS4/
SS4
00101b
SCI
SCK7
TXD7/MOSI7/
SDA7
RXD7/MISO7/
SCL7
CTS7_RTS7/
SS7
—
—
—
—
00110b
SPI*2
—
—
—
—
—
—
SSLB3_C
SSLB3_A
00111b
IIC*2
SCL0_A
SDA0_A
—
—
—
—
—
SDA0_B
01001b
CLKOUT/ACMPHS/RT
C
—
—
—
—
—
—
—
RTCOUT
01010b
CAC/ADC12
ADTRG1
—
CACREF
—
—
—
—
ADTRG0
01100b
CTSU
—
—
—
—
—
—
—
TS03
10000b
CAN
—
CTX0
CRX0
—
—
—
—
—
10010b
SSIE*2
AUDIO_CLK
—
AUDIO_CLK
SSIBCK0_A
SSILRCK0/SSI SSITXD0_A
FS0_A
SSIRXD0_A
—
10011b
USBFS
—
—
—
—
—
—
—
USB_VBUS
10101b
SDHI*2
—
—
—
SD1DAT7_B
SD1DAT6_B
SD1DAT5_B
SD1DAT4_B
—
10110b
ETHERC (MII)
ET0_WOL
ET0_MDC
ET0_MDIO
ET0_LINKSTA
ET0_EXOUT
ET0_TX_EN
ET0_RX_ER
ET0_EXOUT
10111b
ETHERC (RMII)*2
ET0_WOL
ET0_MDC
ET0_MDIO
ET0_LINKSTA
ET0_EXOUT
RMII0_TXD_E
N_B
RMII0_TXD1_
B
ET0_EXOUT
11000b
PDC
—
—
VSYNC
PIXD7
PIXD6
PIXD5
PIXD4
—
Don’t-care
AGT, RTC
—
—
AGTIO0*1/
AGTIO1*1/
RTCIC0*1
AGTIO0*1/
AGTIO1*1/
RTCIC1*1
RTCIC2*1
—
—
—
ASEL bit
-
-
-
-
-
-
-
-
ISEL bit
IRQ0
IRQ5-DS
IRQ4-DS
-
-
-
-
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
: Available
—: Setting prohibited
Note 1.
Note 2.
Note 3.
To use this pin function, set the associated pin as a general input (set the PmnPFS.PDR and PmnPFS.PMR bits to 0).
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 470 of 1734
S5D5 User’s Manual
Table 20.14
20. I/O Ports
Register settings for I/O pin functions (PORT4)
Pin
PSEL[4:0]
settings
Function
P408
P409
P410
P411
P412
P413
P414
P415
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00001b
AGT
—
—
AGTOB1
AGTOA1
AGTEE1
—
—
—
00010b
GPT
GTOWLO
GTOWUP
GTOVLO
GTOVUP
GTOULO
GTOUUP
—
—
00011b
GPT*2
GTIOC10B
GTIOC10A
GTIOC9B
GTIOC9A
—
—
GTIOC0B
GTIOC0A
00100b
SCI
—
—
RXD0/MISO0/
SCL0
TXD0/MOSI0/
SDA0
SCK0
CTS0_RTS0/
SS0
—
—
00101b
SCI
RXD3/MISO3/
SCL3
TXD3/MOSI3/
SDA3
SCK3
CTS3_RTS3/
SS3
—
—
—
—
00110b
SPI*1
—
—
MISOA_B
MOSIA_B
RSPCKA_B
SSLA0_B
SSLA1_B
SSLA2_B
00111b
IIC*1
SCL0_B
—
—
—
—
—
—
—
01100b
CTSU
TS04
TS05
TS06
TS07
TS08
TS09
TS10
TS11
10011b
USBFS
USB_ID
USB_EXICEN
—
—
—
—
—
USB_VBUSEN
10101b
SDHI*1
—
—
SD0DAT1_A
SD0DAT0_A
SD0CMD_A
SD0CLK_A
SD0WP
10110b
ETHERC (MII)
ET0_CRS
ET0_RX_CLK
ET0_ERXD0
ET0_ERXD1
ET0_ETXD0
ET0_ETXD1
10111b
ETHERC (RMII)*1
RMII0_CRS_D RMII0_RX_ER
V_A
_A
RMII0_RXD1_
A
RMII0_RXD0_
A
REF50CK0_A
RMII0_TXD0_
A
RMII0_TXD1_
A
RMII0_TXD_E
N_A
11000b
PDC
SD0CD
ET0_TX_EN
PIXCLK
HSYNC
PIXD0
PIXD1
PIXD2
PIXD3
PIXD4
PIXD5
ASEL bit
-
-
-
-
-
-
-
-
ISEL bit
IRQ7
IRQ6
IRQ5
IRQ4
-
-
IRQ9
IRQ8
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
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Table 20.15
Register settings for I/O pin functions (PORT5)
Pin
PSEL[4:0]
settings
00000b (value
after reset)
20. I/O Ports
Function
Hi-Z/JTAG/SWD
P500
P501
P502
P503
P504
P505
P506
Hi-Z
00001b
AGT
AGTOA0
AGTOB0
—
—
—
—
—
00010b
GPT
GTIU
GTIV
GTIW
GTETRGC
GTETRGD
—
—
00011b
GPT*2
GTIOC11A
GTIOC11B
GTIOC12A
GTIOC12B
GTIOC13A
GTIOC13B
—
00100b
SCI
—
—
—
CTS6_RTS6/
SS6
SCK6
RXD6/MISO6/
SCL6
TXD6/MOSI6/
SDA6
00101b
SCI
—
TXD5/MOSI5/
SDA5
RXD5/MISO5/
SCL5
SCK5
CTS5_RTS5/S —
S5
—
—
01011b
BUS
—
—
—
—
ALE
—
10001b
QSPI
QSPCLK
QSSL
QIO0
QIO1
QIO2
QIO3
—
10011b
USBFS
USB_VBUSEN USB_OVRCU
RA
USB_OVRCU
RB
USB_EXICEN
USB_ID
—
—
10101b
SDHI*1
SD1CLK_A
SD1CMD_A
SD1DAT0_A
SD1DAT1_A
SD1DAT2_A
SD1DAT3_A
SD1CD
AN016/
IVREF0
AN116/
IVREF1
AN017/
IVCMP0
AN117
AN018
AN118
AN019
ASEL bit
ISEL bit
-
IRQ11
IRQ12
-
-
IRQ14
IRQ15
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
-
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
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Table 20.16
20. I/O Ports
Register settings for I/O pin functions (PORT5)
Pin
PSEL[4:0]
settings
Function
P508
P511
P512
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00011b
GPT*2
—
GTIOC0B
GTIOC0A
00100b
SCI
SCK6
RXD4/MISO4/
SCL4
TXD4/MOSI4/
SDA4
00101b
SCI
SCK5
—
—
00111b
IIC
—
SDA2
SCL2
10000b
CAN
—
CRX1
CTX1
10101b
SDHI*1
SD1DAT3_A
—
—
11000b
PDC
—
PCKO
VSYNC
ASEL bit
AN020
-
-
ISEL bit
-
IRQ15
IRQ14
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
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Table 20.17
20. I/O Ports
Register settings for I/O pin functions (PORT6)
Pin
PSEL[4:0]
settings
Function
P600
P601
P602
P603
P604
P605
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00011b
GPT*1
GTIOC6B
GTIOC6A
GTIOC7B
GTIOC7A
GTIOC8B
GTIOC8A
00100b
SCI
—
—
—
—
—
—
00101b
SCI
SCK9
RXD9
TXD9
CTS9_RTS9/
SS9
—
—
01001b
CLKOUT/ACMPHS/RT
C
CLKOUT
—
—
—
—
—
01010b
CAC/ADC12
CACREF
—
—
—
—
—
01011b
BUS
RD
WR/
WR0/
DQM00
EBCLK/
SDCLK
D13[A13/D13]/ D12[A12/D12]/ D11[A11/D11]/
DQ13
DQ12
DQ11
ASEL bit
-
-
-
-
-
ISEL bit
-
-
-
-
-
-
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
-
-
: Available
—: Setting prohibited
Note 1.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
Table 20.18
Register settings for I/O pin functions (PORT6)
Pin
PSEL[4:0]
settings
Function
P608
P609
P610
P611
P612
P613
P614
00000b (value
after reset)
Hi-Z/JTAG/SWD
Hi-Z
00011b
GPT*1
GTIOC4B
GTIOC5A
GTIOC5B
—
—
—
—
00101b
SCI
—
—
—
CTS7_RTS7/
SS7
SCK7
TXD7
RXD7
01001b
CLKOUT/ACMPHS/RT
C
—
—
—
CLKOUT
—
—
—
01010b
CAC/ADC12
—
—
—
CACREF
—
—
—
01011b
BUS
A00/BC0/
DQM1
CS1/CKE
CS0/WE
SDCS
D08[A08/D08]/ D09[A09/D09]/ D10[A10/D10]/
DQ08
DQ09
DQ10
10000b
CAN
—
CTX1
CRX1
—
—
—
—
ASEL bit
-
-
-
-
-
-
-
ISEL bit
-
-
-
-
-
-
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
-
-
-
: Available
—: Setting prohibited
Note 1.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
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Table 20.19
Register settings for I/O pin functions (PORT7)
Pin
PSEL[4:0]
settings
00000b (value
after reset)
20. I/O Ports
Function
P700
P701
P702
P703
P704
P705
Hi-Z/JTAG/SWD
Hi-Z
00001b
AGT
—
—
—
—
AGTO0
00011b
GPT*2
GTIOC5A
GTIOC5B
GTIOC6A
GTIOC6B
—
—
00101b
SCI
—
—
—
—
—
—
00110b
SPI*1
MISOB_C
MOSIB_C
RSPCKB_C
SSLB0_C
SSLB1_C
SSLB2_C
01001b
CLKOUT/ACMPHS/RT
C
—
—
—
VCOUT
—
—
10000b
CAN
—
—
—
—
CTX0
CRX0
10101b
SDHI*1
SD1DAT3_B
SD1DAT2_B
SD1DAT1_B
SD1DAT0_B
SD1CLK_B
SD1CMD_B
10110b
ETHERC (MII)
ET0_ETXD1
ET0_ETXD0
ET0_ERXD1
ET0_ERXD0
ET0_RX_CLK
ET0_CRS
10111b
ETHERC (RMII)*1
RMII0_TXD0_
B
REF50CK0_B
RMII0_RXD0_
B
RMII0_RXD1_
B
RMII0_RX_ER
_B
RMII0_CRS_D
V_B
11000b
PDC
AGTIO0
PIXD3
PIXD2
PIXD1
PIXD0
HSYNC
PIXCLK
ASEL bit
-
-
-
-
-
-
ISEL bit
-
-
-
-
-
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
-
-
-
-
-
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
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Table 20.20
20. I/O Ports
Register settings for I/O pin functions (PORT7)
Pin
PSEL[4:0]
settings
Function
P708
P709
P710
P711
P712
P713
00000b (value after
reset)
Hi-Z/JTAG/SWD
Hi-Z
00001b
AGT
—
—
—
AGTEE0
AGTOB0
00011b
GPT*2
—
—
—
—
GTIOC2B
GTIOC2A
00101b
SCI
RXD1/MISO1/
SCL1
TXD1/MOSI1/
SDA1
SCK1
CTS1_RTS1/
SS1
—
—
00110b
SPI*1
SSLA3_B
—
—
—
—
—
01010b
CAC/ADC12
CACREF
—
—
—
—
—
01100b
CTSU
TS12
TS13
TS14
TS15
TS16
TS17
10010b
SSIE
AUDIO_CLK
—
—
—
—
—
10110b
ETHERC (MII)
ET0_ETXD3
ET0_ETXD2
ET0_TX_ER
ET0_TX_CLK
—
—
11000b
PDC
PCKO
—
—
—
—
—
ASEL bit
-
-
-
-
-
-
ISEL bit
IRQ11
IRQ10
-
-
-
-
AGTOA0
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
-
-
-
-
: Available
—: Setting prohibited
Note 1.
Note 2.
Renesas recommends using pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group
membership. For the interface, the AC portion of the electrical characteristics is measured for each group.
There are two types of output buffer, middle drive and high drive. Renesas recommends using the same drive buffer for output
skew spec (tGTISK).
Table 20.21
Register settings for I/O pin functions (PORT8)
Pin
PSEL[4:0]
settings
Function
P800
P801
00000b (value after Hi-Z/JTAG/SWD
reset)
Hi-Z
00101b
SCI
—
—
01011b
BUS
D14[A14/D14]/D
Q14
D15[A15/D15]/D
Q15
ASEL bit
-
-
ISEL bit
-
-
DSCR[1:0] bits
Drive capacity control
L/M/H
L/M/H
NCODR bit
N-ch open-drain
PCR bit
Pull-up
Number of pins
144 pins, 145 pins
100 pins
-
-
: Available
—: Setting prohibited
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21. Key Interrupt Function (KINT)
21.
Key Interrupt Function (KINT)
21.1
Overview
A key interrupt (KEY_INTKR) can be generated by setting the Key Return Mode Register (KRM) and inputting a rising
or falling edge on the key interrupt input pins, KR00 to KR07.
Table 21.1 shows the pin assignment for key interrupt detection, Table 21.2 shows the function configuration, and Figure
21.1 shows a block diagram.
Table 21.1
Assignment of key interrupt detection pins
Key Interrupt Mode Control n (n = 0 to 7)
Description
KRM0
Controls KR00 signal in 1-bit units
KRM1
Controls KR01 signal in 1-bit units
KRM2
Controls KR02 signal in 1-bit units
KRM3
Controls KR03 signal in 1-bit units
KRM4
Controls KR04 signal in 1-bit units
KRM5
Controls KR05 signal in 1-bit units
KRM6
Controls KR06 signal in 1-bit units
KRM7
Controls KR07 signal in 1-bit units
Table 21.2
Configuration of key interrupt function
Parameter
Configuration
Input
KR00 to KR07
Control registers
Key Return Control Register (KRCTL)
Key Return Mode Register (KRM)
Key Return Flag Register (KRF)
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21. Key Interrupt Function (KINT)
0
1
KR00
KREG
Filter
KRF0
KRM0
0
1
KRMD
0
KR01
Filter
1
KREG
0
KRF1
KRM1
1
KRMD
0
KR02
Filter
1
KREG
0
KRF2
KRM2
1
KRMD
0
KR03
Filter
1
KREG
0
KRF3
KRM3
1
KEY_INTKR
KRMD
0
KR04
Filter
1
KREG
0
KRF4
KRM4
1
KEY_INTKR mask signal
KRMD
0
KR05
Filter
1
KREG
0
KRF5
KRM5
1
KRMD
0
KR06
Filter
1
KREG
0
KRF6
KRM6
1
KRMD
0
KR07
Filter
1
KREG
0
KRF7
KRM7
1
KRMD
Figure 21.1
Note:
Key interrupt block diagram
In Figure 21.1, all key return factors are merged by an OR gate, and the key interrupt (KEY_INTKR) is the output
of the AND gate to mask the merged key return factor by the KEY_INTKR mask signal. When using KRFn
(KRMD = 1), the KEY_INTKR mask signal is used as the output mask that is asserted by clearing KRFn.
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21.2
21. Key Interrupt Function (KINT)
Register Descriptions
21.2.1
Key Return Control Register (KRCTL)
Address(es): KINT.KRCTL 4008 0000h
b7
b6
b5
b4
b3
b2
b1
b0
KRMD
—
—
—
—
—
—
KREG
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
KREG
Detection Edge Selection
(KR00 to KR07)
0: Falling edge
1: Rising edge.
R/W
b6 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
KRMD
Usage of Key Interrupt Flags
(KRF0 to KRF7)
0: Do not use key interrupt flags
1: Use key interrupt flags.
R/W
The KRCTL register controls the usage of the key interrupt flags, KRF0 to KRF7, and sets the detection edge.
21.2.2
Key Return Flag Register (KRF)
Address(es): KINT.KRF 4008 0004h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
KRF7
KRF6
KRF5
KRF4
KRF3
KRF2
KRF1
KRF0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
KRFn
Key Interrupt Flag n
0: No key interrupt detected
1: Key interrupt detected.
R/W
n = 0 to 7
Note:
When KRMD = 0, setting the KRFn bit to 1 is prohibited.
When setting the KRFn bit to 1, the KRFn value does not change. To clear the KRFn bit, confirm the target bit is 1 before writing
0 to the bit, then write 1 to the other bits.
The KRF register controls the key interrupt flags, KRF0 to KRF7.
21.2.3
Key Return Mode Register (KRM)
Address(es): KINT.KRM 4008 0008h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
KRM7
KRM6
KRM5
KRM4
KRM3
KRM2
KRM1
KRM0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
KRMn
Key Interrupt Mode Control n
0:No key interrupt signal detected
1:Key interrupt signal detected.
R/W
n = 0 to 7
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Note:
21. Key Interrupt Function (KINT)
The on-chip pull-up resistors can be applied by setting the pull-up function for the associated key interrupt input pin. For more
information, see section 20, I/O Ports.
Key interrupts can be assigned in the PmnPFS.PSEL bits. For more information, see section 20, I/O Ports.
An interrupt is generated when the target bit in the KRM register is set while a low level (KREG = 0) or a high level (KREG = 1)
is being input to the key interrupt input pin. To ignore this interrupt, set the KRM register after disabling the interrupt handling.
The KRM register sets the key interrupt mode.
21.3
Operation
21.3.1
Operation When Not Using Key Interrupt Flag (KRMD = 0)
A key interrupt (KEY_INTKR) is generated when the valid edge specified in the KREG bit is input to a key interrupt pin,
KR00 to KR07. To identify the channel to which the valid edge is input, read the port register and check the port level
after the key interrupt (KEY_INTKR) is generated.
The KEY_INTKR signal changes based on the input level of the key interrupt input pin, KR00 to KR07.
KRn
KEY_INTKR
Delay
Delay
Key interrupt
When KRMD = 0 and KREG = 0
Note: n = 00 to 07
Figure 21.2
Operation of KEY_INTKR signal when a key interrupt is input to a single channel
Figure 21.3 shows the operation when a valid edge is input to multiple key interrupt input pins. The KEY_INTKR signal
is set while a low level is being input to one pin (when KREG = 0). Therefore, even if a falling edge is input to another
pin in this period, a key interrupt (KEY_INTKR) is not generated again. See [1] in Figure 21.3.
KR00
KR01
[1]
KEY_INTKR
Delay
Key interrupt
Figure 21.3
21.3.2
Delay
Delay
When KRMD = 0 and KREG = 0
Operation of KEY_INTKR signal when key interrupts are input to multiple channels
Operation When Using the Key Interrupt Flags (KRMD = 1)
A key interrupt (KEY_INTKR) is generated when the valid edge specified in the KREG bit is input to a key interrupt pin,
KR00 to KR07. To identify the channels to which the valid edge is input, read the Key Return Flag Register (KRF) after
the key interrupt (KEY_INTKR) is generated. If the KRMD bit is set to 1, clear the KEY_INTKR signal by clearing the
associated bit in the KRF register.
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21. Key Interrupt Function (KINT)
As Figure 21.4 shows, only one interrupt is generated each time a falling edge is input to one channel, that is, when
KREG = 0, regardless of whether the KRFn bit is cleared before or after a rising edge is input.
(a) When KRF0 is cleared after a rising edge is input to the KR00 pin
KR00
KRF0
Cleared by
software
KEY_INTKR
Delay
Key interrupt
(b) When KRF0 is cleared before a rising edge is input to the KR00 pin
KR00
KRF0
Cleared by
software
KEY_INTKR
Delay
Key interrupt
Figure 21.4
When KRMD = 1 and KREG = 0
Basic operation of KEY_INTKR signal when key interrupt flag is used
The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 21.5. A falling edge is
also input to the KR01 and KR05 pins after a falling edge is input to the KR00 pin (when KREG = 0). The KRF1 bit is
set when the KRF0 bit is cleared. A key interrupt is generated 1 PCLKB clock cycle, after the KRF0 bit is cleared. See
[1] in Figure 21.5.
Also, after a falling edge is input to the KR05 pin, the KRF5 bit is set. The KRF1 bit is cleared at time [2] in the figure. A
key interrupt is generated 1 PCLKB clock cycle, after the KRF1 bit is cleared. See [3] in the figure. It is therefore
possible to generate a key interrupt when a valid edge is input to multiple channels.
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21. Key Interrupt Function (KINT)
KR00
KR01
KR05
KRF0
Cleared by software
Delay
[2]
KRF1
Cleared by software
Delay
KRF5
Cleared by
software
Delay
[1]
[3]
KEY_INTKR
Key interrupt
Key interrupt
Key interrupt
When KRMD = 1 and KREG = 0
Figure 21.5
21.4
Operation of KEY_INTKR signal when key interrupts are input to multiple channels
Usage Notes
If KEY_INTKR is used as the Snooze request, the KRMD bit must be set to 0.
If KEY_INTKR is used as the interrupt source for returning to Normal mode from Snooze mode and Software
Standby mode, the KRMD bit must be set to 1.
When the Key Interrupt function (KINT) is assigned to a pin, this pin input is always enabled in Software Standby
mode, and if the pin level changes, the associated KRFn flag can be set. Therefore, a key interrupt might occur on
canceling Software Standby mode.
To ignore changes to the key interrupt pin during a software standby, clear the associated KRM bit before entering
Software Standby mode. After canceling Software Standby mode, you must clear KRFn before the associated KRM bit
can be set.
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22. Port Output Enable for GPT (POEG)
22.
Port Output Enable for GPT (POEG)
22.1
Overview
Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT) output pins in the outputdisable state in one of the following ways:
Input level detection of the GTETRGn (n = A, B, C, D) pins
Output-disable request from the GPT
Comparator interrupt request detection
Oscillation stop detection of the clock generation circuit
Register settings.
The GTETRGn (n = A, B, C, D) pins can also be used as GPT external trigger input pins.
Table 22.1 lists the POEG specifications, Figure 22.1 shows a block diagram, and Table 22.2 lists the input pins.
Table 22.1
POEG specifications
Parameter
Specifications
Output-disable control through input level
detection
The GPT output pins can be disabled when a GTETRGn rising edge or high level is
sampled after polarity and filter selection
Output-disable request from the GPT
When the GTIOCA pin and the GTIOCB pin are driven to an active level
simultaneously, the GPT generates an output-disable request to the POEG.Through
reception of these requests, the POEG can control whether the GTIOCA and
GTIOCB pins are output-disabled.
GPT output pins can be set to be disabled when the GPT output pins detect a dead
time error.
Output-disable control through comparator
(ACMPHS) interrupt detection
The GPT output pins can be disabled when an interrupt request is generated by a
change in the output results of any of the comparators
Output-disable control through oscillation stop
detection
The GPT output pins can be disabled when oscillation of the clock generation circuit
stops
Output-disable control by software (registers)
The GPT output pins can be disabled by modifying the register settings
Interrupts
Allows output-disable control by the input level detection
Allows output-disable requests from the GPT or ACMPHS.
External trigger output to the GPT
(count start, count stop, count clear, up-count,
down-count, or input capture function)
The GTETRGn signals can be output to the GPT after polarity and filter selection
Noise filtering
Three times sampling for every PCLKB/1, PCLKB/8, PCLKB/32, or PCLKB/128 can
be set for any of the input pins GTETRGn
Positive or negative polarity can be selected for any of the input pins, GTETRGn
Signal state after polarity and filter selection can be monitored.
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22. Port Output Enable for GPT (POEG)
Group B
POEG Group A
Group C
Group D
IOCE
GPT Ch 0
GTINTAD.GRPABL
Group A
Ch 0
GTINTAD.GRPABH
Group B
Ch 13
GTINTAD.GRPDTE
Group C
IOCF
Group D
S
Ch 1
Ch 13
ACMPHS0
ACMPHS1
ACMPHS2
ACMPHS3
ACMPHS4
ACMPHS5
R
ICU
ACMP_HS0
ACMP_HS1
ACMP_HS2
ACMP_HS3
ACMP_HS4
ACMP_HS5
POEG_GROUP0
CDRE0
POEG_GROUP1
POEG_GROUP2
POEG_GROUP3
CDRE1
CDRE2
OPS
CDRE3
OPSCR.
GRP[1:0]
CDRE4
OPSCR.
GODF
CDRE5
GPT
OSTPF
Oscillation
Stop Detector
GTOUUP
GTOULO
GTOVUP
GTOVLO
GTOWUP
GTOWLO
OSTPE
MOSC_STOP
S
R
SSF
To ch 1
To ch 13
To ch 1
To ch 13
To ch 1
To ch 13
To ch 1
To ch 13
PIDF
INV
GTETRGA
Digital filter
NFCS[1:0]
PIDE
ST
GTETRGC
GTETRGD
GTIOC0A
GTIOC0B
GTIOR.
OADF[1:0]
GTIOC1A
GTIOC1B
GTIOR.
OBDF[1:0]
GTIOC13A
To ch 1
To ch 13
GTIOC13B
To ch 1
To ch 13
NFEN
GTETRGB
Ch 0
GTINTAD.
GRP[1:0]
To ch 1
To ch 13
To ch 1
To ch 13
Ch 1
Ch 13
Figure 22.1
Table 22.2
POEG block diagram
POEG input pins
Pin name
I/O
Description
GTETRGA
Input
GPT output pin output-disable request signal and GPT external trigger input pin A
GTETRGB
Input
GPT output pin output-disable request signal and GPT external trigger input pin B
GTETRGC
Input
GPT output pin output-disable request signal and GPT external trigger input pin C
GTETRGD
Input
GPT output pin output-disable request signal and GPT external trigger input pin D
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22.2
22. Port Output Enable for GPT (POEG)
Register Descriptions
22.2.1
POEG Group n Setting Register (POEGGn) (n = A to D)
Address(es): POEG.POEGGA 4004 2000h, POEG.POEGGB 4004 2100h, POEG.POEGGC 4004 2200h, POEG.POEGGD 4004 2300h
b31
b30
NFCS[1:0]
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
NFEN
INV
—
—
—
—
—
—
—
—
—
—
—
ST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
PIDE
SSF
0
0
0
0
Value after reset:
Value after reset:
CDRE5 CDRE4 CDRE3 CDRE2 CDRE1 CDRE0
0
0
0
0
0
0
—
OSTPE IOCE
0
0
0
OSTPF IOCF
0
PIDF
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIDF
Port Input Detection Flag
0: No output-disable request from the GTETRGn pin occurred
1: Output-disable request from the GTETRGn pin occurred.
R(/W)*1
b1
IOCF
Detection Flag for GPT or
ACMPHS Output-Disable
Request
0: No output-disable request from GPT disable request or
comparator interrupt occurred
1: Output-disable request from GPT disable request or
comparator interrupt occurred.
R(/W)*1
b2
OSTPF
Oscillation Stop Detection
Flag
0: No output-disable request from oscillation stop detection
R(/W)*1
occurred
1: Output-disable request from oscillation stop detection occurred.
b3
SSF
Software Stop Flag
0: No output-disable request from software occurred
1: Output-disable request from software occurred.
R/W
b4
PIDE
Port Input Detection Enable
0: Output-disable requests from the GTETRGn pins disabled
1: Output-disable requests from the GTETRGn pins enabled.
R/W*2
b5
IOCE
Enable for GPT OutputDisable Request
0: Output-disable requests from GPT disable request disabled
1: Output-disable requests from GPT disable request enabled.
R/W*2
b6
OSTPE
Oscillation Stop Detection
Enable
0: Output-disable requests from oscillation stop detection disabled R/W*2
1: Output-disable requests from oscillation stop detection enabled.
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b8
CDRE0
ACMP_HS0 Enable
0: Comparator 0 disable requests disabled
1: Comparator 0 disable requests enabled.
R/W*2
b9
CDRE1
ACMP_HS1 Enable
0: Comparator 1 disable requests disabled
1: Comparator 1 disable requests enabled.
R/W*2
b10
CDRE2
ACMP_HS2 Enable
0: Comparator 2 disable requests disabled
1: Comparator 2 disable requests enabled.
R/W*2
b11
CDRE3
ACMP_HS3 Enable
0: Comparator 3 disable requests disabled
1: Comparator 3 disable requests enabled.
R/W*2
b12
CDRE4
ACMP_HS4 Enable
0: Comparator 4 disable requests disabled
1: Comparator 4 disable requests enabled.
R/W*2
b13
CDRE5
ACMP_HS5 Enable
0: Comparator 5 disable requests disabled
1: Comparator 5 disable requests enabled.
R/W*2
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
ST
GTETRGn Input Status Flag 0: GTETRGn input after filtering was 0
1: GTETRGn input after filtering was 1.
R
b27 to
b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28
INV
GTETRGn Input Reverse
0: Input GTETRGn as-is
1: Input GTETRGn reversed.
R/W
b29
NFEN
Noise Filter Enable
0: Noise filtering disabled
1: Noise filtering enabled.
R/W
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22. Port Output Enable for GPT (POEG)
Bit
Symbol
Bit name
Description
R/W
b31, b30
NFCS[1:0]
Noise Filter Clock Select
b1 b0
R/W
Note 1.
Note 2.
0 0: GTETRGn pin input level sampled three times every PCLKB
0 1: GTETRGn pin input level sampled three times every
PCLKB/8
1 0: GTETRGn pin input level sampled three times every
PCLKB/32
1 1: GTETRGn pin input level sampled three times every
PCLKB/128.
Only 0 can be written to clear the flag.
Can be modified only once after a reset.
The POEGGA to POEGGD registers control the output-disable state of the GPT pins, interrupts, and the external trigger
input to the GPT. In the descriptions, POEGGn represents all of the POEGGA to POEGGD registers.
22.3
Output-Disable Control Operation
If any of the following conditions is satisfied, the GTIOCxA, GTIOCxB, and the 3-phase PWM output for BLDC motor
control pins can be set to output-disable:
Input level or edge detection of the GTETRGn pins
When POEGGn.PIDE is 1, the POEGGn.PIDF flag is set to 1.
Output-disable request from the GPT
When POEGGn.IOCE is 1, the POEGGn.IOCF flag is set to 1 if the disable request is enabled in the GTINTAD
register. The GTINTAD.GRPDTE, GTINTAD.GRPABH, and GTINTAD.GRPABL settings apply to the group
selected in the GPT registers GTINTAD.GRP[1:0] and OPSCR.GRP[1:0].
Comparator (ACMPHS) interrupt request detection
Comparator interrupt detection is activated when any of the POEGGn.CDRE[5:0] registers is 1. When the
associated comparator interrupt is generated, the GPT output pins are disabled. POEGGn.IOCF indicates the
detection status.
Oscillation stop detection for the clock generation circuit
When POEGGn.OSTPE is 1, the POEGGn.OSTPF flag is set to 1.
SSF bit setting
When POEGGn.SSF is set to 1, the PWM output is disabled.
The output-disable state is controlled in the GPT. The output-disable of the GTIOCxA and GTIOCxB pins is set in the
GTINTAD.GRP[1:0], GTIOR.OADF[1:0], and GTIOR.OBDF[1:0] bits in GPTx. The output-disable of the 3-phase
PWM output for the BLDC motor control pins is set in the OPSCR.GRP[1:0] bits and OPSCR.GODF bit in GPT_OPS.
22.3.1
Pin Input Level Detection Operation
If the input conditions set in POEGGn.PIDE, POEGGn.NFCS[1:0], POEGGn.NFEN, and POEGGn.INV occur on the
GTETRGn pins, the GPT output pins are output-disabled.
22.3.1.1
Digital filter
Figure 22.2 shows high level detection by the digital filter. When a high level associated with the POEGGn.INV polarity
setting is detected three times consecutively with the sampling clock selected in POEGGn.NFCS[1:0] and
POEGGn.NFEN, the detected level is recognized as high, and the GPT output pins are output-disabled. If even one low
level is detected during this interval, the detected level is not recognized as high. In addition, in an interval where the
sampling clock is not being output, changes of the levels on the GTETRGn pins are ignored.
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22. Port Output Enable for GPT (POEG)
1, 8, 32, 128 clocks
PCLKB
Sampling clock
GTETRGn input
GTIOCA
GTIOCB
(PCLKD)
When high level is sampled at all points
[1]
[2]
[3]
Flag set (GTETRGn received)
When low level is sampled at least once
[1]
[0]
[1]
Flag not set
Note: Each channel output can be set in the GPT setting.
Low level sampling can be set in the POEGGn.INV setting.
Figure 22.2
22.3.2
Example of digital filter operation
Output-Disable Requests from the GPT
For details on this operation, see the description of GTIOC Pin Output Negate Control in section 23, General PWM
Timer (GPT).
22.3.3
Comparator Interrupt Detection
If POEGGn.CDRE[5:0] is 1 when the associated comparator interrupt request is generated, the GPT output pins are
output-disabled for each group. The status flag is POEGGn.IOCF, which is shared with GPT output-disable detection.
22.3.4
Output-Disable Control Using Detection of Stopped Oscillation
When the oscillation stop detection function in the clock generation circuit detects stopped oscillation while
POEGGn.OSTPE is 1, the GPT output pins are output-disabled for each group.
22.3.5
Output-Disable Control Using Registers
The GPT output pins can be directly controlled by writing to the Software Stop flag, POEGGn.SSF.
22.3.6
Release from Output-Disable
To release the GPT output pins placed in the output-disable state, either return them to their initial state with a reset or
clear all of the following flags:
POEGGn.PIDF
POEGGn.IOCF
POEGGn.OSTPF
POEGGn.SSF.
Writing 0 to the POEGGn.PIDF flag is ignored (the flag is not cleared) if the external input pins, GTETRGn, are not
disabled and the POEGGn.ST bit is not set to 0.
Writing 0 to the POEGGn.IOCF flag is valid (the flag is cleared) only if all of the GTST.DTEF, GTST.OABHF, and
GTST.OABLF flags in the GPT are set to 0.
Writing 0 to the POEGGn.OSTPF flag is ignored (the flag is not cleared) if the OSTDSR.OSTDF flag in the clock
generation circuit is not set to 0. In addition, when the flag set and release occur at the same time, the flag set takes
precedence.
Figure 22.3 shows the release timing for output-disable. The output-disable is released at the beginning of the next count
cycle of the GPT after the flag is cleared.
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22. Port Output Enable for GPT (POEG)
GPT32EH0.GTCNT value
GPT32EH0.GTPR
GPT32EH0.GTCCRA
Flag clear
PIDF, IOCF
OSTPF, SSF
GTIOC0A
GTIOC0B
Output-disable
Figure 22.3
22.4
Output-disable release timing for the GPT pin outputs
Interrupt Sources
The POEG generates an interrupt request when triggered by these sources:
Output-disable control by the input level detection
Output-disable request from the GPT
Comparator interrupt request detection.
Table 22.3 lists the conditions for interrupt requests.
Table 22.3
Interrupt sources and conditions
Interrupt source
Symbol
Associated flag
Trigger conditions
POEG group A interrupt
POEG_GROUP0
POEGGA.IOCF
An output-disable request from a GPT disable request
occurred
An output-disable request from a comparator interrupt
occurred
POEG group B interrupt
POEG_GROUP1
POEGGA.PIDF
An output-disable request from the GTETRGA pin
occurred
POEGGB.IOCF
An output-disable request from a GPT disable request
occurred
An output-disable request from a comparator interrupt
occurred
POEG group C interrupt
POEG_GROUP2
POEGGB.PIDF
An output-disable request from the GTETRGB pin
occurred
POEGGC.IOCF
An output-disable request from a GPT disable request
occurred
An output-disable request from a comparator interrupt
occurred
POEG group D interrupt
POEG_GROUP3
POEGGC.PIDF
An output-disable request from the GTETRGC pin
occurred
POEGGD.IOCF
An output-disable request from a GPT disable request
occurred
An output-disable request from a comparator interrupt
occurred
POEGGD.PIDF
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An output-disable request from the GTETRGD pin
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22.5
22. Port Output Enable for GPT (POEG)
External Trigger Output to the GPT
The POEG outputs the GTETRGn signals as the GPT operation trigger signal for the following:
Count start
Count stop
Count clear
Up-count
Down-count
Input capture.
For the POEGGn.INV polarity setting signal, when the same level is input three times continuously with the sampling
clock selected in POEGGn.NFCS[1:0] and POEGGn.NFEN, that value is output. Set the control registers the same as for
the input level detection operation described in section 22.3.1, Pin Input Level Detection Operation. The state after
filtering can be monitored in POEGGn.ST.
Figure 22.4 shows the output timing of an external trigger to the GPT.
8, 16, 128 clocks
PCLKB
Sampling clock
GTETRGn pin
POEGGn.ST
(GTETRGn after filtering)
[1]
[1]
[2]
[1]
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[1]
Note: Each channel output can be set in the GPT settings.
Polarity can be reversed in POEGGn.INV.
Figure 22.4
22.6
22.6.1
Output timing of external trigger to GPT
Usage Notes
Transition to Software Standby Mode
When using the POEG, do not invoke Software Standby mode. In this mode, the POEG stops and therefore outputdisable of the pins cannot be controlled.
22.6.2
Specifying Pins Associated with the GPT
The POEG controls output-disable only when a pin is associated with the GPT in the PmnPFS.PMR and PmnPFS.PSEL
settings. When the pin is specified as a general I/O pin, the POEG does not perform output-disable control.
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23. General PWM Timer (GPT)
23.
General PWM Timer (GPT)
23.1
Overview
The General PWM Timer (GPT) is a 32-bit timer with four GPT32EH channels, four GPT32E channels, and six GPT32
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter.
The GPT can also be used as a general-purpose timer.
Table 23.1 lists the GPT specifications, Table 23.2 shows the GPT functions, Figure 23.1 shows a block diagram, Figure
23.2 shows the correspondence between the GPT channels and module names, and Table 23.3 lists the I/O pins.
Table 23.1
GPT specifications
Parameter
Specifications
Functions
Table 23.2
32 bits × 14 channels
Up-counting or down-counting (saw waves) or up/down-counting (triangle waves) for each counter
Clock sources independently selectable for each channel
Two I/O pins per channel
Two output compare/input capture registers per channel
For the two output compare/input capture registers of each channel, four registers are provided as
buffer registers and are capable of operating as comparison registers when buffering is not in use
In output compare operation, buffer switching can be at crests or troughs, enabling the generation of
laterally asymmetric PWM waveforms
Registers for setting up frame cycles in each channel with capability for generating interrupts at
overflow or underflow
Generation of dead times in PWM operation
Synchronous starting, stopping, and clearing counters for arbitrary channels
Starting, stopping, and clearing up/down counters in response to a maximum of eight ELC events
Starting, stopping, and clearing up/down counters in response to input level comparison
Starting, stopping, and clearing up/down counters in response to a maximum of four external triggers
Output pin disable function by dead time error and detected short-circuits between output pins
A/D converter start triggers can be generated
PWM waveform for controlling brushless DC motors can be generated
Compare match A to F event, overflow/underflow event, and input UVW edge event can be output to
the ELC
Enables the noise filter for input capture and input UVW
Bus clock: PCLKA
Core clock: PCLKD
Frequency ratio: PCLKA:PCLKD = 1:N (N = 1/2/4/8/16/32/64).
GPT functions (1 of 2)
Parameter
GPT32EH, GPT32E
GPT32
Count clock
PCLKD
PCLKD/4
PCLKD/16
PCLKD/64
PCLKD/256
PCLKD/1024
PCLKD
PCLKD/4
PCLKD/16
PCLKD/64
PCLKD/256
PCLKD/1024
Output compare/input capture registers (GTCCR)
GTCCRA
GTCCRB
GTCCRA
GTCCRB
Compare/buffer registers
GTCCRC
GTCCRD
GTCCRE
GTCCRF
GTCCRC
GTCCRD
GTCCRE
GTCCRF
Cycle setting register
GTPR
GTPR
Cycle setting buffer registers
GTPBR
GTPDBR
GTPBR
I/O pins
GTIOCA
GTIOCB
GTIOCA
GTIOCB
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Table 23.2
23. General PWM Timer (GPT)
GPT functions (2 of 2)
Parameter
External trigger input
GPT32EH, GPT32E
GPT32
GTETRGA
GTETRGB
GTETRGC
GTETRGD
GTETRGA
GTETRGB
GTETRGC
GTETRGD
GTPR register compare match, input
capture, input pin status, ELC event
input, and GTETRGn (n = A, B, C, D)
pin input
GTPR register compare match, input
capture, input pin status, ELC event
input, and GTETRGn (n = A, B, C, D)
pin input
Low output
Available
Available
High output
Available
Available
Toggle output
pin*1
Counter clear sources
Compare match output
Available
Available
Input capture function
Available
Available
Automatic addition of dead time
Available
Available
(no dead time buffer)
PWM mode
Available
Available
Phase count function
Available
Available
Buffer operation
Double buffer
Double buffer
One-shot operation
Available
Available
DTC activation
All the interrupt sources
All the interrupt sources
A/D converter start trigger
Compare match of GTADTRA or
GTADTRB
-
Brushless DC motor
control function
Available
Available
Interrupt sources
10 sources
GTCCRA compare match/input
capture (GPTn_CCMPA)
GTCCRB compare match/input
capture (GPTn_CCMPB)
GTCCRC compare match
(GPTn_CMPC)
GTCCRD compare match
(GPTn_CMPD)
GTCCRE compare match
(GPTn_CMPCE)
GTCCRF compare match
(GPTn_CMPF)
GTADTRA compare match
(GPTn_ADTRGA)
GTADTRB compare match
(GPTn_ADTRGB)
GTCNT overflow (GTPR compare
match) (GPTn_OVF)
GTCNT underflow (GPTn_UDF)
8 sources
GTCCRA compare match/input
capture (GPTn_CCMPA)
GTCCRB compare match/input
capture (GPTn_CCMPB)
GTCCRC compare match
(GPTn_CMPC)
GTCCRD compare match
(GPTn_CMPD)
GTCCRE compare match
(GPTn_CMPE)
GTCCRF compare match
(GPTn_CMPF)
GTCNT overflow (GTPR compare
match) (GPTn_OVF)
GTCNT underflow (GPTn_UDF)
Interrupt skipping function
Skips GTCNT overflows (GTPR
compare match) (GPTn_OVF)/
GTCNT underflow (GPTn_UDF)
interrupts (with interlocking function
for other interrupts or A/D conversion
requests).
-
Event linking (ELC) function
Available
Available
Noise filtering function
Available
Available
Note 1.
GTRETRGn connects to GPT through the POEG module. Therefore, to use the GPT function, supply the POEG clock by
clearing the MSTPD14 bit.
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23. General PWM Timer (GPT)
GPT32EH0
Control registers
Clock source
PCLKD
PCLKD/4
PCLKD/16
PCLKD/64
PCLKD/256
PCLKD/1024
GTWP
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GTDNSR
Cycle setting/
Cycle setting buffer registers
GTPDBR
GTPBR
GTPR
External
trigger (after noise filtering)
GTETRGA
GTETRGB
GTETRGC
GTETRGD
GTICASR
GTICBSR
GTCR
GTUDDTYC
GTIOR
GTINTAD
GTST
GTBER
GTITC
Interrupt request signals
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
GTSOTR
GPT0_CCMPA
GPT0_CCMPB
GPT0_CMPC
GPT0_CMPD
GPT0_CMPE
GPT0_CMPF
GPT0_ADTRGA
GPT0_ADTRGB
GPT0_OVF
GPT0_UDF
Counter (GTCNT)
Output disable request
Output compare
Output disable signals
Comparator
...
...
...
...
...
GPT3213
I/O pins
GTIOCA
Comparator
GTIOCB
Input capture
GTADTRA
GPT32EH1
GTCCRA
GTADTBRA
GTCCRB
GTADTDBRA
GTCCRC
GTADTRB
GTCCRD
GTADTBRB
GTCCRE
GTADTDBRB
GTCCRF
ELC event input
ELC_GPTA
ELC_GPTB
ELC_GPTC
ELC_GPTD
ELC_GPTE
ELC_GPTF
ELC_GPTG
ELC_GPTH
Output compare/input capture registers
A/D converter start request timing/
A/D converter start request timing buffer registers
A/D converter
start request
GPT32EH0.GTIOCAoutput
GPT_OPS
I/O pins
GTIU / GTIV / GTIW
Three-phase PWM wave generator
for brushless DC motor
OPSCR
GTOUUP / GTOULO
GTOVUP / GTOVLO
GTOWUP / GTOWLO
Output disable signals
Input UVW edge event signal (to ICU/ELC)
GTWP:
GTSTR:
GTSTP:
GTCLR:
GTSSR:
GTPSR:
General PWM Timer Write-Protection Register
General PWM Timer Software Start Register
General PWM Timer Software Stop Register
General PWM Timer Software Clear Register
General PWM Timer Start Source Select Register
General PWM Timer Stop Source Select Register
GTPR:
GTPBR:
GTPDBR:
GTADTRA:
GTADTBRA:
GTADTDBRA:
GTCSR:
GTUPSR:
GTDNSR:
General PWM Timer Clear Source Select Register
General PWM Timer Up Count Source Select Register
General PWM Timer Down Count Source Select Register
GTADTRB:
GTADTBRB:
GTADTDBRB:
GTICASR:
GTICBSR:
GTCR:
GTUDDTYC:
GTIOR:
GTINTAD:
GTST:
GTBER:
GTITC:
GTCNT:
GTCCRA:
GTCCRB:
GTCCRC:
GTCCRD:
GTCCRE:
GTCCRF:
General PWM Timer Input Capture Source Select Register A
General PWM Timer Input Capture Source Select Register B
General PWM Timer Control Register
General PWM Timer Count Direction and Duty Setting Register
General PWM Timer I/O Control Register
General PWM Timer Interrupt Output Setting Register
General PWM Timer Status Register
General PWM Timer Buffer Enable Register
General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register
General PWM Timer Counter
General PWM Timer Compare Capture Register A
General PWM Timer Compare Capture Register B
General PWM Timer Compare Capture Register C
General PWM Timer Compare Capture Register D
General PWM Timer Compare Capture Register E
General PWM Timer Compare Capture Register F
GTDTCR:
GTDVU:
GTDVD:
GTDBU:
GTDBD:
GTSOS:
GTSOTR:
General PWM Timer Cycle Setting Register
General PWM Timer Cycle Setting Buffer Register
General PWM Timer Cycle Setting Double-Buffer Register
General PWM Timer A/D Converter Start Request Timing Register A
General PWM Timer A/D Converter Start Request Timing Buffer Register A
General PWM Timer A/D Converter Start Request Timing Double-Buffer
Register A
General PWM Timer A/D Converter Start Request Timing Register B
General PWM Timer A/D Converter Start Request Timing Buffer Register B
General PWM Timer A/D Converter Start Request Timing Double-Buffer
Register B
General PWM Timer Dead Time Control Register
General PWM Timer Dead Time Value Register U
General PWM Timer Dead Time Value Register D
General PWM Timer Dead Time Buffer Register U
General PWM Timer Dead Time Buffer Register D
General PWM Timer Output Protection Function Status Register
General PWM Timer Output Protection Function Temporary Release Register
OPSCR:
Output Phase Switching Control Register
Figure 23.1
GPT block diagram
Figure 23.2 shows an example using multiple GPTs.
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23. General PWM Timer (GPT)
CH13 CH12 CH11 CH10
GPT3213
GPT3212
GPT3211
GPT3210
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
GPT329
GPT328
GPT32E7
GPT32E6
GPT32E5
GPT32E4
GPT32EH3
GPT32EH2
GPT32EH1
GPT32EH0
GPT32E
GPT32
Figure 23.2
Table 23.3
GPT32EH
Correspondence between GPT channels and module names
GPT I/O pins (1 of 2)
Channel
Pin name
I/O
Function
Shared
GTETRGA
Input
External trigger input pin A (after noise filtering)
GTETRGB
Input
External trigger input pin B (after noise filtering)
GTETRGC
Input
External trigger input pin C (after noise filtering)
GTETRGD
Input
External trigger input pin D (after noise filtering)
GTIOC0A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC0B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT32EH0
GPT32EH1
GPT32EH2
GPT32EH3
GPT32E4
GPT32E5
GPT32E6
GPT32E7
GPT328
GPT329
GPT3210
GPT3211
GPT3212
GPT3213
GTIOC1A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC1B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC2A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC2B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC3A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC3B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC4A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC4B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC5A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC5B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC6A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC6B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC7A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC7B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC8A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC8B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC9A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC9B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC10A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC10B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC11A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC11B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC12A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC12B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC13A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC13B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
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Table 23.3
23. General PWM Timer (GPT)
GPT I/O pins (2 of 2)
Channel
Pin name
I/O
Function
GPT_OPS
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U-phase)
23.2
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U-phase)
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V-phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V-phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W-phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W-phase)
Register Descriptions
Table 23.4 lists the registers in the GPT.
Table 23.4
Module
symbol
GPT32EHm
(m = 0 to 3)
GPT32Em
(m = 4 to 7)
GPT32m
(m = 8 to 13)
GPT32EHm
(m = 0 to 3)
GPT32Em
(m = 4 to 7)
GPT registers (1 of 2)
Register
symbol
Reset value
Address (m = 0 to 13)
Access
size
GPT32EH/
GPT32E
GPT32
General PWM Timer Write
Protection Register
GTWP
0000_0000h
4007 8000h + 0100h × m
32
General PWM Timer Software Start
Register
GTSTR
0000_0000h
4007 8004h + 0100h × m
32
General PWM Timer Software Stop
Register
GTSTP
FFFF_FFFFh
4007 8008h + 0100h × m
32
General PWM Timer Software Clear
Register
GTCLR
0000_0000h
4007 800Ch + 0100h × m
32
General PWM Timer Start Source
Select Register
GTSSR
0000_0000h
4007 8010h + 0100h × m
32
General PWM Timer Stop Source
Select Register
GTPSR
0000_0000h
4007 8014h + 0100h × m
32
General PWM Timer Clear Source
Select Register
GTCSR
0000_0000h
4007 8018h + 0100h × m
32
General PWM Timer Up Count
Source Select Register
GTUPSR
0000_0000h
4007 801Ch + 0100h × m
32
General PWM Timer Down Count
Source Select Register
GTDNSR
0000_0000h
4007 8020h + 0100h × m
32
General PWM Timer Input Capture
Source Select Register A
GTICASR
0000_0000h
4007 8024h + 0100h × m
32
General PWM Timer Input Capture
Source Select Register B
GTICBSR
0000_0000h
4007 8028h + 0100h × m
32
General PWM Timer Control
Register
GTCR
0000_0000h
4007 802Ch + 0100h × m
32
General PWM Timer Count
Direction and Duty Setting Register
GTUDDTYC
0000_0001h
4007 8030h + 0100h × m
32
General PWM Timer I/O Control
Register
GTIOR
0000_0000h
4007 8034h + 0100h × m
32
General PWM Timer Interrupt
Output Setting Register
GTINTAD
0000_0000h
4007 8038h + 0100h × m
32
()*1
General PWM Timer Status
Register
GTST
0000_8000h
4007 803Ch + 0100h × m
32
()*1
General PWM Timer Buffer Enable
Register
GTBER
0000_0000h
4007 8040h + 0100h × m
32
()*1
General PWM Timer Interrupt and
A/D Converter Start Request
Skipping Setting Register
GTITC
0000_0000h
4007 8044h + 0100h × m
32
-
Register name
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Table 23.4
Module
symbol
23. General PWM Timer (GPT)
GPT registers (2 of 2)
Register name
Register
symbol
Reset value
Address (m = 0 to 13)
Access
size
GPT32EH/
GPT32E
GPT32
General PWM Timer Counter
GTCNT
0000_0000h
4007 8048h + 0100h × m
32
General PWM Timer Compare
Capture Register A
GTCCRA
FFFF_FFFFh
4007 804Ch + 0100h × m
32
General PWM Timer Compare
Capture Register B
GTCCRB
FFFF_FFFFh
4007 8050h + 0100h × m
32
General PWM Timer Compare
Capture Register C
GTCCRC
FFFF_FFFFh
4007 8054h + 0100h × m
32
General PWM Timer Compare
Capture Register E
GTCCRE
FFFF_FFFFh
4007 8058h + 0100h × m
32
General PWM Timer Compare
Capture Register D
GTCCRD
FFFF_FFFFh
4007 805Ch + 0100h × m
32
General PWM Timer Compare
Capture Register F
GTCCRF
FFFF_FFFFh
4007 8060h + 0100h × m
32
General PWM Timer Cycle Setting
Register
GTPR
FFFF_FFFFh
4007 8064h + 0100h × m
32
General PWM Timer Cycle Setting
Buffer Register
GTPBR
FFFF_FFFFh
4007 8068h + 0100h × m
32
General PWM Timer Cycle Setting
Double-Buffer Register
GTPDBR
FFFF_FFFFh
4007 806Ch + 0100h × m
32
-
A/D Converter Start Request Timing
Register A
GTADTRA
FFFF_FFFFh
4007 8070h + 0100h × m
32
-
A/D Converter Start Request Timing
Buffer Register A
GTADTBRA
FFFF_FFFFh
4007 8074h + 0100h × m
32
-
A/D Converter Start Request Timing
Double-Buffer Register A
GTADTDBR
A
FFFF_FFFFh
4007 8078h + 0100h × m
32
-
A/D Converter Start Request Timing
Register B
GTADTRB
FFFF_FFFFh
4007 807Ch + 0100h × m
32
-
A/D Converter Start Request Timing
Buffer Register B
GTADTBRB
FFFF_FFFFh
4007 8080h + 0100h × m
32
-
A/D Converter Start Request Timing
Double-Buffer Register B
GTADTDBR
B
FFFF_FFFFh
4007 8084h + 0100h × m
32
-
GPT32EHm
(m = 0 to 3)
GPT32Em
(m = 4 to 7)
GPT32m
(m = 8 to 13)
General PWM Timer Dead Time
Control Register
GTDTCR
0000_0000h
4007 8088h + 0100h × m
32
()*1
General PWM Timer Dead Time
Value Register U
GTDVU
FFFF_FFFFh
4007 808Ch + 0100h × m
32
GPT32EHm
(m = 0 to 3)
GPT32Em
(m = 4 to 7)
General PWM Timer Dead Time
Value Register D
GTDVD
FFFF_FFFFh
4007 8090h + 0100h × m
32
-
General PWM Timer Dead Time
Buffer Register U
GTDBU
FFFF_FFFFh
4007 8094h + 0100h × m
32
-
General PWM Timer Dead Time
Buffer Register D
GTDBD
FFFF_FFFFh
4007 8098h + 0100h × m
32
-
General PWM Timer Output
Protection Function Status Register
GTSOS
0000_0000h
4007 809Ch + 0100h × m
32
-
General PWM Timer Output
Protection Function Temporary
Release Register
GTSOTR
0000_0000h
4007 80A0h + 0100h × m
32
-
Output Phase Switching Control
Register
OPSCR
0000_0000h
4007 8FF0h
32
GPT32EHm
(m = 0 to 3)
GPT32Em
(m = 4 to 7)
GPT32m
(m = 8 to 13)
GPT32EHm
(m = 0 to 3)
GPT32Em
(m = 4 to 7)
GPT_OPS
Note 1.
Some functions are reduced from GPT32EH/GPT32E.
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23.2.1
23. General PWM Timer (GPT)
General PWM Timer Write-Protection Register (GTWP)
Address(es): GPT32EHm.GTWP 4007 8000h + 0100h × m (m = 0 to 3)
GPT32Em.GTWP 4007 8000h + 0100h × m (m = 4 to 7)
GPT32m.GTWP 4007 8000h + 0100h × m (m = 8 to 13)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
WP
0
0
0
0
0
0
0
0
PRKEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
WP
Register Write Disable
0: Write to the register enabled
1: Write to the register disabled.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
PRKEY[7:0]
GTWP Key Code
When A5h is written to these bits, writing to the WP bit is
permitted. These bits are read as 0.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b16 —
To prevent accidental changes, the GTWP register enables or disables writing to following registers:
GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTICASR, GTICBSR, GTCR, GTUDDTYC, GTIOR, GTINTAD,
GTST, GTBER, GTITC, GTCNT, GTCCRA, GTCCRB, GTCCRC, GTCCRD, GTCCRE, GTCCRF, GTPR, GTPBR,
GTPDBR, GTADTRA, GTADTBRA, GTADTDBRA, GTADTRB, GTADTBRB, GTADTDBRB, GTDTCR, GTDVU,
GTDVD, GTDBU, GTDBD, GTSOS, GTSOTR.
23.2.2
General PWM Timer Software Start Register (GTSTR)
Address(es): GPT32EHm.GTSTR 4007 8004h + 0100h × m (m = 0 to 3)
GPT32Em.GTSTR 4007 8004h + 0100h × m (m = 4 to 7)
GPT32m.GTSTR 4007 8004h + 0100h × m (m = 8 to 13)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
0
0
CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The GTSTR starts the GTCNT counter operation for each channel n, where n = 0 to 13.
The GTSTR bit number represents the channel number. The GTSTR register is shared by all of the channels. The
GTCNT counter starts for the channel associated with the GTSTR bit where 1 is written. Writing 0 has no effect on the
status of the GTCNT counter and the value of GTSTR register. For the association between the GTSTR bit number and a
channel number, see Figure 23.2.
CSTRTn bit (Channel n GTCNT Count Start) (n = 0 to 13)
The CSTRTn bit starts channel n of the GTCNT counter operation. Writing to the GTSTR.CSTRTn bit (n = 0 to 13) has
no effect unless the GPTm.GTSSR.CSTRT bit is set to 1 (for GPT32EH, m = EH0 to EH3, for GPT32E, m = E4 to E7,
for GPT32, m = 8 to 13).
Read data shows the counter status of each channel (GTCR.CST bit). Zero means the counter is stopped and 1 means the
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23. General PWM Timer (GPT)
counter is running.
23.2.3
General PWM Timer Software Stop Register (GTSTP)
Address(es): GPT32EHm.GTSTP 4007 8008h + 0100h × m (m = 0 to 3)
GPT32Em.GTSTP 4007 8008h + 0100h × m (m = 4 to 7)
GPT32m.GTSTP 4007 8008h + 0100h × m (m = 8 to 13)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
1
1
CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The GTSTP register stops the GTCNT counter operation for each channel n, where n = 0 to 13.
The GTSTP bit number represents the channel number. The GTSTP register is shared by all of the channels. The GTCNT
counter stops for the channel associated with the GTSTP bit in which 1 is written. Writing 0 has no effect on the status of
GTCNT counter and the value of GTSTP register. For the association between the GTSTP bit number and a channel
number, see Figure 23.2.
CSTOPn bit (channel n GTCNT Count Stop) (n = 0 to 13)
The CSTOPn bit stops channel n of the GTCNT counter operation. Writing to the GTSTP.CSTOPn bit (n = 0 to 13) has
no effect unless the GPTm.GTPSR.CSTOP bit is set to 1 (for GPT32EH, m = EH0 to EH3, for GPT32E, m = E4 to E7,
for GPT32, m = 8 to 13).
Read data shows the counter status of each channel (invert of the GTCR.CST bit). Zero means the counter is running and
1 means the counter stops.
23.2.4
General PWM Timer Software Clear Register (GTCLR)
Address(es): GPT32EHm.GTCLR 4007 800Ch + 0100h × m (m = 0 to 3)
GPT32Em.GTCLR 4007 800Ch + 0100h × m (m = 4 to 7)
GPT32m.GTCLR 4007 800Ch + 0100h × m (m = 8 to 13)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
CCLR
13
CCLR
12
CCLR
11
CCLR
10
CCLR
9
CCLR
8
CCLR
7
CCLR
6
CCLR
5
CCLR
4
CCLR
3
CCLR
2
CCLR
1
CCLR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The GTCLR is a write-only register that clears the GTCNT counter operation for each channel n, where n = 0 to 13.
The GTCLR bit number represents the channel number. The GTCLR register is shared by all of the channels. The
GTCNT counter is cleared for the channel associated with the GTCLR bit number where 1 is written. Writing 0 has no
effect on the status of the GTCNT counter. For the association between the GTCLR bit number and a channel number,
see Figure 23.2.
CCLRn bit (Channel n GTCNT Count Clear) (n = 0 to 13)
Channel n of the GTCNT counter value is cleared on writing 1 to the CCLRn bit. This bit is read as 0.
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23.2.5
23. General PWM Timer (GPT)
General PWM Timer Start Source Select Register (GTSSR)
Address(es): GPT32EHm.GTSSR 4007 8010h + 0100h × m (m = 0 to 3)
GPT32Em.GTSSR 4007 8010h + 0100h × m (m = 4 to 7)
GPT32m.GTSSR 4007 8010h + 0100h × m (m = 8 to 13)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
CSTRT
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
SSELC SSELC SSELC SSELC SSELC SSELC SSELC SSELC
H
G
F
E
D
C
B
A
SSCBF SSCBF SSCBR SSCBR SSCAF SSCAF SSCAR SSCAR SSGTR SSGTR SSGTR SSGTR SSGTR SSGTR SSGTR SSGTR
AH
AL
AH
AL
BH
BL
BH
BL
GDF
GDR
GCF
GCR
GBF
GBR
GAF
GAR
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSGTRGAR
GTETRGA Pin Rising Input Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTETRGA
input
1: Counter start enabled on the rising edge of GTETRGA
input.
R/W
b1
SSGTRGAF
GTETRGA Pin Falling Input Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTETRGA
input
1: Counter start enabled on the falling edge of GTETRGA
input.
R/W
b2
SSGTRGBR
GTETRGB Pin Rising Input Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTETRGB
input
1: Counter start enabled on the rising edge of GTETRGB
input.
R/W
b3
SSGTRGBF
GTETRGB Pin Falling Input Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTETRGB
input
1: Counter start enabled on the falling edge of GTETRGB
input.
R/W
b4
SSGTRGCR
GTETRGC Pin Rising Input Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTETRGC
input
1: Counter start enabled on the rising edge of GTETRGC
input.
R/W
b5
SSGTRGCF
GTETRGC Pin Falling Input Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTETRGC
input
1: Counter start enabled on the falling edge of GTETRGC
input
R/W
b6
SSGTRGDR
GTETRGD Pin Rising Input Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTETRGD
input
1: Counter start enabled on the rising edge of GTETRGD
input.
R/W
b7
SSGTRGDF
GTETRGD Pin Falling Input Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTETRGD
input
1: Counter start enabled on the falling edge of GTETRGD
input.
R/W
b8
SSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTIOCA
input when GTIOCB input is 0
1: Counter start enabled on the rising edge of GTIOCA
input when GTIOCB input is 0.
R/W
b9
SSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTIOCA
input when GTIOCB input is 1
1: Counter start enabled on the rising edge of GTIOCA
input when GTIOCB input is 1.
R/W
b10
SSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTIOCA
input when GTIOCB input is 0
1: Counter start enabled on the falling edge of GTIOCA
input when GTIOCB input is 0.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b11
SSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTIOCA
input when GTIOCB input is 1
1: Counter start enabled on the falling edge of GTIOCA
input when GTIOCB input is 1.
R/W
b12
SSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTIOCB
input when GTIOCA input is 0
1: Counter start enabled on the rising edge of GTIOCB
input when GTIOCA input is 0.
R/W
b13
SSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Start Enable
0: Counter start disabled on the rising edge of GTIOCB
input when GTIOCA input is 1
1: Counter start enabled on the rising edge of GTIOCB
input when GTIOCA input is 1.
R/W
b14
SSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTIOCB
input when GTIOCA input is 0
1: Counter start enabled on the falling edge of GTIOCB
input when GTIOCA input is 0.
R/W
b15
SSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Start Enable
0: Counter start disabled on the falling edge of GTIOCB
input when GTIOCA input is 1
1: Counter start enabled on the falling edge of GTIOCB
input when GTIOCA input is 1.
R/W
b16
SSELCA
ELC_GPTA Event Source Counter
Start Enable
0: Counter start disabled on ELC_GPTA event input
1: Counter start enabled on ELC_GPTA event input.
R/W
b17
SSELCB
ELC_GPTB Event Source Counter
Start Enable
0: Counter start disabled on ELC_GPTB event input
1: Counter start enabled on ELC_GPTB event input.
R/W
b18
SSELCC
ELC_GPTC Event Source Counter
Start Enable
0: Counter start disabled on ELC_GPTC event input
1: Counter start enabled on ELC_GPTC event input.
R/W
b19
SSELCD
ELC_GPTD Event Source Counter
Start Enable
0: Counter start disabled on ELC_GPTD event input
1: Counter start enabled on ELC_GPTD event input.
R/W
b20
SSELCE
ELC_GPTE Event Source Counter
Start Enable
0: Counter start disabled on ELC_GPTE event input
1: Counter start enabled on ELC_GPTE event input.
R/W
b21
SSELCF
ELC_GPTF Event Source Counter
Start Enable
0: Counter start disabled on ELC_GPTF event input
1: Counter start enabled on ELC_GPTF event input.
R/W
b22
SSELCG
ELC_GPTG Event Source Counter
Start Enable
0: Counter start disabled on ELC_GPTG event input
1: Counter start enabled on ELC_GPTG event input.
R/W
b23
SSELCH
ELC_GPTH Event Source Counter
Start Enable
0: Counter start disabled on ELC_GPTH event input
1: Counter start enabled on ELC_GPTH event input.
R/W
b30 to b24 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Start
Enable
0: Counter start disabled by the GTSTR register
1: Counter start enabled by the GTSTR register.
R/W
CSTRT
The GTSSR sets the source to start the GTCNT counter.
SSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Start Enable)
The SSGTRGAR bit enables or disables GTCNT counter start on the rising edge of GTETRGA pin input.
SSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Start Enable)
The SSGTRGAF bit enables or disables GTCNT counter start on the falling edge of GTETRGA pin input.
SSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Start Enable)
The SSGTRGBR bit enables or disables GTCNT counter start on the rising edge of GTETRGB pin input.
SSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Start Enable)
The SSGTRGBF bit enables or disables GTCNT counter start on the falling edge of GTETRGB pin input.
SSGTRGCR bit (GTETRGC Pin Rising Input Source Counter Start Enable)
The SSGTRGCR bit enables or disables GTCNT counter start on the rising edge of GTETRGC pin input.
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23. General PWM Timer (GPT)
SSGTRGCF bit (GTETRGC Pin Falling Input Source Counter Start Enable)
The SSGTRGCF bit enables or disables GTCNT counter start on the falling edge of GTETRGC pin input.
SSGTRGDR bit (GTETRGD Pin Rising Input Source Counter Start Enable)
The SSGTRGDR bit enables or disables GTCNT counter start on the rising edge of GTETRGD pin input.
SSGTRGDF bit (GTETRGD Pin Falling Input Source Counter Start Enable)
The SSGTRGDF bit enables or disables GTCNT counter start on the falling edge of GTETRGD pin input.
SSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable)
The SSCARBL bit enables or disables GTCNT counter start on the rising edge of GTIOCA pin input, when GTIOCB
input is 0.
SSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable)
The SSCARBH bit enables or disables GTCNT counter start on the rising edge of GTIOCA pin input, when GTIOCB
input is 1.
SSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable)
The SSCAFBL bit enables or disables GTCNT counter start on the falling edge of GTIOCA pin input, when GTIOCB
input is 0.
SSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable)
The SSCAFBH bit enables or disables GTCNT counter start on the falling edge of GTIOCA pin input, when GTIOCB
input is 1.
SSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable)
The SSCBRAL bit enables or disables GTCNT counter start on the rising edge of GTIOCB pin input, when GTIOCA
input is 0.
SSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable)
The SSCBRAH bit enables or disables GTCNT counter start on the rising edge of GTIOCB pin input, when GTIOCA
input is 1.
SSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable)
The SSCBFAL bit enables or disables GTCNT counter start on the falling edge of GTIOCB pin input, when GTIOCA
input is 0.
SSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable)
The SSCBFAH bit enables or disables GTCNT counter start on the falling edge of GTIOCB pin input, when GTIOCA
input is 1.
SSELCm bit (ELC_GPTm Event Source Counter Start Enable) (m = A to H)
The SSELCm bit enables or disables GTCNT counter start at the ELC_GPTm event input.
CSTRT bit (Software Source Counter Start Enable)
The CSTRT bit enables or disables GTCNT counter start by the GTSTR register.
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23.2.6
23. General PWM Timer (GPT)
General PWM Timer Stop Source Select Register (GTPSR)
Address(es): GPT32EHm.GTPSR 4007 8014h + 0100h × m (m = 0 to 3)
GPT32Em.GTPSR 4007 8014h + 0100h × m (m = 4 to 7)
GPT32m.GTPSR 4007 8014h + 0100h × m (m = 8 to 13)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
CSTOP
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PSELC PSELC PSELC PSELC PSELC PSELC PSELC PSELC
H
G
F
E
D
C
B
A
PSCBF PSCBF PSCBR PSCBR PSCAF PSCAF PSCAR PSCAR PSGTR PSGTR PSGTR PSGTR PSGTR PSGTR PSGTR PSGTR
AH
AL
AH
AL
BH
BL
BH
BL
GDF
GDR
GCF
GCR
GBF
GBR
GAF
GAR
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PSGTRGAR
GTETRGA Pin Rising Input Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTETRGA
input
1: Counter stop enabled on the rising edge of GTETRGA
input.
R/W
b1
PSGTRGAF
GTETRGA Pin Falling Input Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTETRGA
input
1: Counter stop enabled on the falling edge of GTETRGA
input.
R/W
b2
PSGTRGBR
GTETRGB Pin Rising Input Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTETRGB
input
1: Counter stop enabled on the rising edge of GTETRGB
input.
R/W
b3
PSGTRGBF
GTETRGB Pin Falling Input Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTETRGB
input
1: Counter stop enabled on the falling edge of GTETRGB
input.
R/W
b4
PSGTRGCR
GTETRGC Pin Rising Input Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTETRGC
input
1: Counter stop enabled on the rising edge of GTETRGC
input.
R/W
b5
PSGTRGCF
GTETRGC Pin Falling Input Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTETRGC
input
1: Counter stop enabled on the falling edge of GTETRGC
input.
R/W
b6
PSGTRGDR
GTETRGD Pin Rising Input Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTETRGD
input
1: Counter stop enabled on the rising edge of GTETRGD
input.
R/W
b7
PSGTRGDF
GTETRGD Pin Falling Input Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTETRGD
input
1: Counter stop enabled on the falling edge of GTETRGD
input.
R/W
b8
PSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTIOCA
input when GTIOCB input is 0
1: Counter stop enabled on the rising edge of GTIOCA input
when GTIOCB input is 0.
R/W
b9
PSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTIOCA
input when GTIOCB input is 1
1: Counter stop enabled on the rising edge of GTIOCA input
when GTIOCB input is 1.
R/W
b10
PSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTIOCA
input when GTIOCB input is 0
1: Counter stop enabled on the falling edge of GTIOCA
input when GTIOCB input is 0.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b11
PSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTIOCA
input when GTIOCB input is 1
1: Counter stop enabled on the falling edge of GTIOCA
input when GTIOCB input is 1.
R/W
b12
PSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTIOCB
input when GTIOCA input is 0
1: Counter stop enabled on the rising edge of GTIOCB input
when GTIOCA input is 0.
R/W
b13
PSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Stop Enable
0: Counter stop disabled on the rising edge of GTIOCB
input when GTIOCA input is 1
1: Counter stop enabled on the rising edge of GTIOCB input
when GTIOCA input is 1.
R/W
b14
PSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTIOCB
input when GTIOCA input is 0
1: Counter stop enabled on the falling edge of GTIOCB
input when GTIOCA input is 0
R/W
b15
PSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Stop Enable
0: Counter stop disabled on the falling edge of GTIOCB
input when GTIOCA input is 1
1: Counter stop enabled on the falling edge of GTIOCB
input when GTIOCA input is 1
R/W
b16
PSELCA
ELC_GPTA Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTA event input
1: Counter stop enabled at the ELC_GPTA event input.
R/W
b17
PSELCB
ELC_GPTB Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTB event input
1: Counter stop enabled at the ELC_GPTB event input.
R/W
b18
PSELCC
ELC_GPTC Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTC event input
1: Counter stop enabled at the ELC_GPTC event input.
R/W
b19
PSELCD
ELC_GPTD Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTD event input
1: Counter stop enabled at the ELC_GPTD event input.
R/W
b20
PSELCE
ELC_GPTE Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTE event input
1: Counter stop enabled at the ELC_GPTE event input.
R/W
b21
PSELCF
ELC_GPTF Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTF event input
1: Counter stop enabled at the ELC_GPTF event input.
R/W
b22
PSELCG
ELC_GPTG Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTG event input
1: Counter stop enabled at the ELC_GPTG event input.
R/W
b23
PSELCH
ELC_GPTH Event Source Counter
Stop Enable
0: Counter stop disabled at the ELC_GPTH event input
1: Counter stop enabled at the ELC_GPTH event input.
R/W
b30 to b24 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Stop
Enable
0: Counter stop disabled by the GTSTP register
1: Counter stop enabled by the GTSTP register.
R/W
CSTOP
The GTPSR sets the source to stop the GTCNT counter.
PSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Stop Enable)
The PSGTRGAR bit enables or disables GTCNT counter stop on the rising edge of GTETRGA pin input.
PSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Stop Enable)
The PSGTRGAF bit enables or disables GTCNT counter stop on the falling edge of GTETRGA pin input.
PSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Stop Enable)
The PSGTRGBR bit enables or disables GTCNT counter stop on the rising edge of GTETRGB pin input.
PSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Stop Enable)
The PSGTRGBF bit enables or disables GTCNT counter stop on the falling edge of GTETRGB pin input.
PSGTRGCR bit (GTETRGC Pin Rising Input Source Counter Stop Enable)
The PSGTRGCR bit enables or disables GTCNT counter stop on the rising edge of GTETRGC pin input.
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23. General PWM Timer (GPT)
PSGTRGCF bit (GTETRGC Pin Falling Input Source Counter Stop Enable)
The PSGTRGCF bit enables or disables GTCNT counter stop on the falling edge of GTETRGC pin input.
PSGTRGDR bit (GTETRGD Pin Rising Input Source Counter Stop Enable)
The PSGTRGDR bit enables or disables GTCNT counter stop on the rising edge of GTETRGD pin input.
PSGTRGDF bit (GTETRGD Pin Falling Input Source Counter Stop Enable)
The PSGTRGDF bit enables or disables GTCNT counter stop on the falling edge of GTETRGD pin input.
PSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable)
The PSCARBL bit enables or disables GTCNT counter stop on the rising edge of GTIOCA pin input, when GTIOCB
input is 0.
PSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable)
The PSCARBH bit enables or disables GTCNT counter stop on the rising edge of GTIOCA pin input, when GTIOCB
input is 1.
PSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable)
The PSCAFBL bit enables or disables GTCNT counter stop on the falling edge of GTIOCA pin input, when GTIOCB
input is 0.
PSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable)
The PSCAFBH bit enables or disables GTCNT counter stop on the falling edge of GTIOCA pin input, when GTIOCB
input is 1.
PSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable)
The PSCBRAL bit enables or disables GTCNT counter stop on the rising edge of GTIOCB pin input, when GTIOCA
input is 0.
PSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable)
The PSCBRAH bit enables or disables GTCNT counter stop on the rising edge of GTIOCB pin input, when GTIOCA
input is 1.
PSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable)
The PSCBFAL bit enables or disables GTCNT counter stop on the falling edge of GTIOCB pin input, when GTIOCA
input is 0.
PSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable)
The PSCBFAH bit enables or disables GTCNT counter stop on the falling edge of GTIOCB pin input, when GTIOCA
input is 1.
PSELCm bit (ELC_GPTm Event Source Counter Stop Enable) (m = A to H)
The PSELCm bit enables or disables GTCNT counter stop at the ELC_GPTm event input.
CSTOP bit (Software Source Counter Stop Enable)
The CSTOP bit enables or disables GTCNT counter stop by the GTSTP register.
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23.2.7
23. General PWM Timer (GPT)
General PWM Timer Clear Source Select Register (GTCSR)
Address(es): GPT32EHm.GTCSR 4007 8018h + 0100h × m (m = 0 to 3)
GPT32Em.GTCSR 4007 8018h + 0100h × m (m = 4 to 7)
GPT32m.GTCSR 4007 8018h + 0100h × m (m = 8 to 13)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
CCLR
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
CSELC CSELC CSELC CSELC CSELC CSELC CSELC CSELC
H
G
F
E
D
C
B
A
CSCBF CSCBF CSCBR CSCBR CSCAF CSCAF CSCAR CSCAR CSGTR CSGTR CSGTR CSGTR CSGTR CSGTR CSGTR CSGTR
AH
AL
AH
AL
BH
BL
BH
BL
GDF
GDR
GCF
GCR
GBF
GBR
GAF
GAR
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CSGTRGAR
GTETRGA Pin Rising Input Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of GTETRGA
input
1: Counter clear enabled on the rising edge of GTETRGA
input.
R/W
b1
CSGTRGAF
GTETRGA Pin Falling Input Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of GTETRGA
input
1: Counter clear enabled on the falling edge of GTETRGA
input.
R/W
b2
CSGTRGBR
GTETRGB Pin Rising Input Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of GTETRGB
input
1: Counter clear enabled on the rising edge of GTETRGB
input.
R/W
b3
CSGTRGBF
GTETRGB Pin Falling Input Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of GTETRGB
input
1: Counter clear enabled on the falling edge of GTETRGB
input.
R/W
b4
CSGTRGCR GTETRGC Pin Rising Input Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of GTETRGC
input
1: Counter clear enabled on the rising edge of GTETRGC
input.
R/W
b5
CSGTRGCF
GTETRGC Pin Falling Input Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of GTETRGC
input
1: Counter clear enabled on the falling edge of GTETRGC
input.
R/W
b6
CSGTRGDR GTETRGD Pin Rising Input Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of GTETRGD
input
1: Counter clear enabled on the rising edge of GTETRGD
input.
R/W
b7
CSGTRGDF
GTETRGD Pin Falling Input Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of GTETRGD
input
1: Counter clear enabled on the falling edge of GTETRGD
input.
R/W
b8
CSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of GTIOCA
input when GTIOCB input is 0
1: Counter clear enabled on the rising edge of GTIOCA
input when GTIOCB input is 0.
R/W
b9
CSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of GTIOCA
input when GTIOCB input is 1
1: Counter clear enabled on the rising edge of GTIOCA
input when GTIOCB input is 1.
R/W
b10
CSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of GTIOCA
input when GTIOCB input is 0
1: Counter clear enabled on the falling edge of GTIOCA
input when GTIOCB input is 0.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b11
CSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of GTIOCA
input when GTIOCB input is 1
1: Counter clear enabled on the falling edge of GTIOCA
input when GTIOCB input is 1.
R/W
b12
CSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of GTIOCB
input when GTIOCA input is 0
1: Counter clear enabled on the rising edge of GTIOCB
input when GTIOCA input is 0.
R/W
b13
CSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Clear Enable
0: Counter clear disabled on the rising edge of GTIOCB
input when GTIOCA input is 1
1: Counter clear enabled on the rising edge of GTIOCB
input when GTIOCA input is 1.
R/W
b14
CSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of GTIOCB
input when GTIOCA input is 0
1: Counter clear enabled on the falling edge of GTIOCB
input when GTIOCA input is 0.
R/W
b15
CSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Clear Enable
0: Counter clear disabled on the falling edge of GTIOCB
input when GTIOCA input is 1
1: Counter clear enabled on the falling edge of GTIOCB
input when GTIOCA input is 1.
R/W
b16
CSELCA
ELC_GPTA Event Source Counter
Clear Enable
0: Counter clear disabled on ELC_GPTA event input
1: Counter clear enabled on ELC_GPTA event input.
R/W
b17
CSELCB
ELC_GPTB Event Source Counter
Clear Enable
0: Counter clear disabled on ELC_GPTB event input
1: Counter clear enabled on ELC_GPTB event input.
R/W
b18
CSELCC
ELC_GPTC Event Source Counter
Clear Enable
0: Counter clear disabled on ELC_GPTC event input
1: Counter clear enabled on ELC_GPTC event input.
R/W
b19
CSELCD
ELC_GPTD Event Source Counter
Clear Enable
0: Counter clear disabled on ELC_GPTD event input
1: Counter clear enabled on ELC_GPTD event input.
R/W
b20
CSELCE
ELC_GPTE Event Source Counter
Clear Enable
0: Counter clear disabled on ELC_GPTE event input
1: Counter clear enabled on ELC_GPTE event input.
R/W
b21
CSELCF
ELC_GPTF Event Source Counter
Clear Enable
0: Counter clear disabled on ELC_GPTF event input
1: Counter clear enabled on ELC_GPTF event input.
R/W
b22
CSELCG
ELC_GPTG Event Source Counter
Clear Enable
0: Counter clear disabled on ELC_GPTG event input
1: Counter clear enabled on ELC_GPTG event input.
R/W
b23
CSELCH
ELC_GPTH Event Source Counter
Clear Enable
0: Counter clear disabled on ELC_GPTH event input
1: Counter clear enabled on ELC_GPTH event input.
R/W
b30 to b24 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Clear
Enable
0: Counter clear disabled by the GTCLR register
1: Counter clear enabled by the GTCLR register.
R/W
CCLR
The GTCSR sets the source to clear the GTCNT counter.
CSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Clear Enable)
The CSGTRGAR bit enables or disables GTCNT counter clear on the rising edge of GTETRGA pin input.
CSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Clear Enable)
The CSGTRGAF bit enables or disables GTCNT counter clear on the falling edge of GTETRGA pin input.
CSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Clear Enable)
The CSGTRGBR bit enables or disables GTCNT counter clear on the rising edge of GTETRGB pin input.
CSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Clear Enable)
The CSGTRGBF bit enables or disables GTCNT counter clear on the falling edge of GTETRGB pin input.
CSGTRGCR bit (GTETRGC Pin Rising Input Source Counter Clear Enable)
The CSGTRGCR bit enables or disables GTCNT counter clear on the rising edge of GTETRGC pin input.
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23. General PWM Timer (GPT)
CSGTRGCF bit (GTETRGC Pin Falling Input Source Counter Clear Enable)
The CSGTRGCF bit enables or disables GTCNT counter clear on the falling edge of GTETRGC pin input.
CSGTRGDR bit (GTETRGD Pin Rising Input Source Counter Clear Enable)
The CSGTRGDR bit enables or disables GTCNT counter clear on the rising edge of GTETRGD pin input.
CSGTRGDF bit (GTETRGD Pin Falling Input Source Counter Clear Enable)
The CSGTRGDF bit enables or disables GTCNT counter clear on the falling edge of GTETRGD pin input.
CSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable)
The CSCARBL bit enables or disables GTCNT counter clear on the rising edge of GTIOCA pin input, when GTIOCB
input is 0.
CSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable)
The CSCARBH bit enables or disables GTCNT counter clear on the rising edge of GTIOCA pin input, when GTIOCB
input is 1.
CSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable)
The CSCAFBL bit enables or disables GTCNT counter clear on the falling edge of GTIOCA pin input, when GTIOCB
input is 0.
CSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable)
The CSCAFBH bit enables or disables GTCNT counter clear on the falling edge of GTIOCA pin input, when GTIOCB
input is 1.
CSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable)
The CSCBRAL bit enables or disables GTCNT counter clear on the rising edge of GTIOCB pin input, when GTIOCA
input is 0.
CSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable)
The CSCBRAH bit enables or disables GTCNT counter clear on the rising edge of GTIOCB pin input, when GTIOCA
input is 1.
CSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable)
The CSCBFAL bit enables or disables GTCNT counter clear on the falling edge of GTIOCB pin input, when GTIOCA
input is 0.
CSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable)
The CSCBFAH bit enables or disables GTCNT counter clear on the falling edge of GTIOCB pin input, when GTIOCA
input is 1.
CSELCm bit (ELC_GPTm Event Source Counter Clear Enable) (m = A to H)
The CSELCm bit enables or disables GTCNT counter clear at the ELC_GPTm event input.
CCLR bit (Software Source Counter Clear Enable)
The CCLR bit enables or disables GTCNT counter clear by the GTCLR register.
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23.2.8
23. General PWM Timer (GPT)
General PWM Timer Up Count Source Select Register (GTUPSR)
Address(es): GPT32EHm.GTUPSR 4007 801Ch + 0100h × m (m = 0 to 3)
GPT32Em.GTUPSR 4007 801Ch + 0100h × m (m = 4 to 7)
GPT32m.GTUPSR 4007 801Ch + 0100h × m (m = 8 to 13)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
USELC USELC USELC USELC USELC USELC USELC USELC
H
G
F
E
D
C
B
A
USCBF USCBF USCBR USCBR USCAF USCAF USCAR USCAR USGTR USGTR USGTR USGTR USGTR USGTR USGTR USGTR
AH
AL
AH
AL
BH
BL
BH
BL
GDF
GDR
GCF
GCR
GBF
GBR
GAF
GAR
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
USGTRGAR
GTETRGA Pin Rising Input Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of
GTETRGA input
1: Counter count up enabled on the rising edge of
GTETRGA input.
R/W
b1
USGTRGAF
GTETRGA Pin Falling Input Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of
GTETRGA input
1: Counter count up enabled on the falling edge of
GTETRGA input.
R/W
b2
USGTRGBR
GTETRGB Pin Rising Input Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of
GTETRGB input
1: Counter count up enabled on the rising edge of
GTETRGB input.
R/W
b3
USGTRGBF
GTETRGB Pin Falling Input Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of
GTETRGB input
1: Counter count up enabled on the falling edge of
GTETRGB input.
R/W
b4
USGTRGCR GTETRGC Pin Rising Input Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of
GTETRGC input
1: Counter count up enabled on the rising edge of
GTETRGC input.
R/W
b5
USGTRGCF
GTETRGC Pin Falling Input Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of
GTETRGC input
1: Counter count up enabled on the falling edge of
GTETRGC input.
R/W
b6
USGTRGDR GTETRGD Pin Rising Input Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of
GTETRGD input
1: Counter count up enabled on the rising edge of
GTETRGD input.
R/W
b7
USGTRGDF
GTETRGD Pin Falling Input Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of
GTETRGD input
1: Counter count up enabled on the falling edge of
GTETRGD input.
R/W
b8
USCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of GTIOCA
input when GTIOCB input is 0
1: Counter count up enabled on the rising edge of GTIOCA
input when GTIOCB input is 0.
R/W
b9
USCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of GTIOCA
input when GTIOCB input is 1
1: Counter count up enabled on the rising edge of GTIOCA
input when GTIOCB input is 1.
R/W
b10
USCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of GTIOCA
input when GTIOCB input is 0
1: Counter count up enabled on the falling edge of GTIOCA
input when GTIOCB input is 0.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b11
USCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of GTIOCA
input when GTIOCB input is 1
1: Counter count up enabled on the falling edge of GTIOCA
input when GTIOCB input is 1.
R/W
b12
USCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of GTIOCB
input when GTIOCA input is 0
1: Counter count up enabled on the rising edge of GTIOCB
input when GTIOCA input is 0.
R/W
b13
USCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Count Up Enable
0: Counter count up disabled on the rising edge of GTIOCB
input when GTIOCA input is 1
1: Counter count up enabled on the rising edge of GTIOCB
input when GTIOCA input is 1.
R/W
b14
USCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of GTIOCB
input when GTIOCA input is 0
1: Counter count up enabled on the falling edge of GTIOCB
input when GTIOCA input is 0.
R/W
b15
USCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Count Up Enable
0: Counter count up disabled on the falling edge of GTIOCB
input when GTIOCA input is 1
1: Counter count up enabled on the falling edge of GTIOCB
input when GTIOCA input is 1.
R/W
b16
USELCA
ELC_GPTA Event Source Counter
Count Up Enable
0: Counter count up disabled on ELC_GPTA event input
1: Counter count up enabled on ELC_GPTA event input.
R/W
b17
USELCB
ELC_GPTB Event Source Counter
Count Up Enable
0: Counter count up disabled on ELC_GPTB event input
1: Counter count up enabled on ELC_GPTB event input.
R/W
b18
USELCC
ELC_GPTC Event Source Counter
Count Up Enable
0: Counter count up disabled on ELC_GPTC event input
1: Counter count up enabled on ELC_GPTC event input.
R/W
b19
USELCD
ELC_GPTD Event Source Counter
Count Up Enable
0: Counter count up disabled on ELC_GPTD event input
1: Counter count up enabled on ELC_GPTD event input.
R/W
b20
USELCE
ELC_GPTE Event Source Counter
Count Up Enable
0: Counter count up disabled on ELC_GPTE event input
1: Counter count up enabled on ELC_GPTE event input.
R/W
b21
USELCF
ELC_GPTF Event Source Counter
Count Up Enable
0: Counter count up disabled on ELC_GPTF event input
1: Counter count up enabled on ELC_GPTF event input.
R/W
b22
USELCG
ELC_GPTG Event Source Counter
Count Up Enable
0: Counter count up disabled on ELC_GPTG event input
1: Counter count up enabled on ELC_GPTG event input.
R/W
b23
USELCH
ELC_GPTH Event Source Counter
Count Up Enable
0: Counter count up disabled on ELC_GPTH event input
1: Counter count up enabled on ELC_GPTH event input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
The GTUPSR register sets the source to count up the GTCNT counter.
When at least 1 bit in the GTUPSR register is set to 1, the GTCNT counter is counted up by the source that is set to 1 in
this register. In this case, GTCR.TPCS has no effect.
USGTRGAR bit (GTETRGA Pin Rising Input Source Counter Count Up Enable)
The USGTRGAR bit enables or disables GTCNT counter count up on the rising edge of GTETRGA pin input.
USGTRGAF bit (GTETRGA Pin Falling Input Source Counter Count Up Enable)
The USGTRGAF bit enables or disables GTCNT counter count up on the falling edge of GTETRGA pin input.
USGTRGBR bit (GTETRGB Pin Rising Input Source Counter Count Up Enable)
The USGTRGBR bit enables or disables GTCNT counter count up on the rising edge of GTETRGB pin input.
USGTRGBF bit (GTETRGB Pin Falling Input Source Counter Count Up Enable)
The USGTRGBF bit enables or disables GTCNT counter count up on the falling edge of GTETRGB pin input.
USGTRGCR bit (GTETRGC Pin Rising Input Source Counter Count Up Enable)
The USGTRGCR bit enables or disables GTCNT counter count up on the rising edge of GTETRGC pin input.
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23. General PWM Timer (GPT)
USGTRGCF bit (GTETRGC Pin Falling Input Source Counter Count Up Enable)
The USGTRGCF bit enables or disables GTCNT counter count up on the falling edge of GTETRGC pin input.
USGTRGDR bit (GTETRGD Pin Rising Input Source Counter Count Up Enable)
The USGTRGDR bit enables or disables GTCNT counter count up on the rising edge of GTETRGD pin input.
USGTRGDF bit (GTETRGD Pin Falling Input Source Counter Count Up Enable)
The USGTRGDF bit enables or disables GTCNT counter count up on the falling edge of GTETRGD pin input.
USCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable)
The USCARBL bit enables or disables GTCNT counter count up on the rising edge of GTIOCA pin input, when
GTIOCB input is 0.
USCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable)
The USCARBH bit enables or disables GTCNT counter count up on the rising edge of GTIOCA pin input, when
GTIOCB input is 1.
USCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable)
The USCAFBL bit enables or disables GTCNT counter count up on the falling edge of GTIOCA pin input, when
GTIOCB input is 0.
USCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable)
The USCAFBH bit enables or disables GTCNT counter count up on the falling edge of GTIOCA pin input, when
GTIOCB input is 1.
USCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable)
The USCBRAL bit enables or disables GTCNT counter count up on the rising edge of GTIOCB pin input, when
GTIOCA input is 0.
USCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable)
The USCBRAH bit enables or disables GTCNT counter count up on the rising edge of GTIOCB pin input, when
GTIOCA input is 1.
USCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable)
The USCBFAL bit enables or disables GTCNT counter count up on the falling edge of GTIOCB pin input, when
GTIOCA input is 0.
USCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable)
The USCBFAH bit enables or disables GTCNT counter count up on the falling edge of GTIOCB pin input, when
GTIOCA input is 1.
USELCm bit (ELC_GPTm Event Source Counter Count Up Enable) (m = A to H)
The USELCm bit enables or disables GTCNT counter count up at the ELC_GPTm event input.
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23.2.9
23. General PWM Timer (GPT)
General PWM Timer Down Count Source Select Register (GTDNSR)
Address(es): GPT32EHm.GTDNSR 4007 8020h + 0100h × m (m = 0 to 3)
GPT32Em.GTDNSR 4007 8020h + 0100h × m (m = 4 to 7)
GPT32m.GTDNSR 4007 8020h + 0100h × m (m = 8 to 13)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
DSELC DSELC DSELC DSELC DSELC DSELC DSELC DSELC
H
G
F
E
D
C
B
A
DSCBF DSCBF DSCBR DSCBR DSCAF DSCAF DSCAR DSCAR DSGTR DSGTR DSGTR DSGTR DSGTR DSGTR DSGTR DSGTR
AH
AL
AH
AL
BH
BL
BH
BL
GDF
GDR
GCF
GCR
GBF
GBR
GAF
GAR
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DSGTRGAR
GTETRGA Pin Rising Input Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of
GTETRGA input
1: Counter count down enabled on the rising edge of
GTETRGA input.
R/W
b1
DSGTRGAF
GTETRGA Pin Falling Input Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of
GTETRGA input
1: Counter count down enabled on the falling edge of
GTETRGA input.
R/W
b2
DSGTRGBR
GTETRGB Pin Rising Input Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of
GTETRGB input
1: Counter count down enabled on the rising edge of
GTETRGB input.
R/W
b3
DSGTRGBF
GTETRGB Pin Falling Input Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of
GTETRGB input
1: Counter count down enabled on the falling edge of
GTETRGB input.
R/W
b4
DSGTRGCR GTETRGC Pin Rising Input Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of
GTETRGC input
1: Counter count down enabled on the rising edge of
GTETRGC input.
R/W
b5
DSGTRGCF
GTETRGC Pin Falling Input Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of
GTETRGC input
1: Counter count down enabled on the falling edge of
GTETRGC input.
R/W
b6
DSGTRGDR GTETRGD Pin Rising Input Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of
GTETRGD input
1: Counter count down enabled on the rising edge of
GTETRGD input.
R/W
b7
DSGTRGDF
GTETRGD Pin Falling Input Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of
GTETRGD input
1: Counter count down enabled on the falling edge of
GTETRGD input.
R/W
b8
DSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of
GTIOCA input when GTIOCB input is 0
1: Counter count down enabled on the rising edge of
GTIOCA input when GTIOCB input is 0.
R/W
b9
DSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of
GTIOCA input when GTIOCB input is 1
1: Counter count down enabled on the rising edge of
GTIOCA input when GTIOCB input is 1.
R/W
b10
DSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of
GTIOCA input when GTIOCB input is 0
1: Counter count down enabled on the falling edge of
GTIOCA input when GTIOCB input is 0.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b11
DSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of
GTIOCA input when GTIOCB input is 1
1: Counter count down enabled on the falling edge of
GTIOCA input when GTIOCB input is 1.
R/W
b12
DSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of
GTIOCB input when GTIOCA input is 0
1: Counter count down enabled on the rising edge of
GTIOCB input when GTIOCA input is 0.
R/W
b13
DSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Count Down Enable
0: Counter count down disabled on the rising edge of
GTIOCB input when GTIOCA input is 1
1: Counter count down enabled on the rising edge of
GTIOCB input when GTIOCA input is 1.
R/W
b14
DSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of
GTIOCB input when GTIOCA input is 0
1: Counter count down enabled on the falling edge of
GTIOCB input when GTIOCA input is 0.
R/W
b15
DSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Count Down Enable
0: Counter count down disabled on the falling edge of
GTIOCB input when GTIOCA input is 1
1: Counter count down enabled on the falling edge of
GTIOCB input when GTIOCA input is 1.
R/W
b16
DSELCA
ELC_GPTA Event Source Counter
Count Down Enable
0: Counter count down disabled at ELC_GPTA event input
1: Counter count down enabled at ELC_GPTA event input.
R/W
b17
DSELCB
ELC_GPTB Event Source Counter
Count Down Enable
0: Counter count down disabled at ELC_GPTB event input
1: Counter count down enabled at ELC_GPTB event input.
R/W
b18
DSELCC
ELC_GPTC Event Source Counter
Count Down Enable
0: Counter count down disabled at ELC_GPTC event input
1: Counter count down enabled at ELC_GPTC event input.
R/W
b19
DSELCD
ELC_GPTD Event Source Counter
Count Down Enable
0: Counter count down disabled at ELC_GPTD event input
1: Counter count down enabled at ELC_GPTD event input.
R/W
b20
DSELCE
ELC_GPTE Event Source Counter
Count Down Enable
0: Counter count down disabled at ELC_GPTE event input
1: Counter count down enabled at ELC_GPTE event input.
R/W
b21
DSELCF
ELC_GPTF Event Source Counter
Count Down Enable
0: Counter count down disabled at ELC_GPTF event input
1: Counter count down enabled at ELC_GPTF event input.
R/W
b22
DSELCG
ELC_GPTG Event Source Counter
Count Down Enable
0: Counter count down disabled at ELC_GPTG event input
1: Counter count down enabled at ELC_GPTG event input.
R/W
b23
DSELCH
ELC_GPTH Event Source Counter
Count Down Enable
0: Counter count down disabled at ELC_GPTH event input
1: Counter count down enabled at ELC_GPTH event input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
The GTDNSR register sets the source to count down the GTCNT counter.
When at least 1 bit in the GTDNSR register is set to 1, the GTCNT counter is counted up by the source that is set to 1 in
this register. In this case, GTCR.TPCS has no effect.
DSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Count Down Enable)
The DSGTRGAR bit enables or disables GTCNT counter count down on the rising edge of GTETRGA pin input.
DSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Count Down Enable)
The DSGTRGAF bit enables or disables GTCNT counter count down on the falling edge of GTETRGA pin input.
DSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Count Down Enable)
The DSGTRGBR bit enables or disables GTCNT counter count down on the rising edge of GTETRGB pin input.
DSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Count Down Enable)
The DSGTRGBF bit enables or disables GTCNT counter count down on the falling edge of GTETRGB pin input.
DSGTRGCR bit (GTETRGC Pin Rising Input Source Counter Count Down Enable)
The DSGTRGCR bit enables or disables GTCNT counter count down on the rising edge of GTETRGC pin input.
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23. General PWM Timer (GPT)
DSGTRGCF bit (GTETRGC Pin Falling Input Source Counter Count Down Enable)
The DSGTRGCF bit enables or disables GTCNT counter count down on the falling edge of GTETRGC pin input.
DSGTRGDR bit (GTETRGD Pin Rising Input Source Counter Count Down Enable)
The DSGTRGDR bit enables or disables GTCNT counter count down on the rising edge of GTETRGD pin input.
DSGTRGDF bit (GTETRGD Pin Falling Input Source Counter Count Down Enable)
The DSGTRGDF bit enables or disables GTCNT counter count down on the falling edge of GTETRGD pin input.
DSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down
Enable)
The DSCARBL bit enables or disables GTCNT counter count down on the rising edge of GTIOCA pin input, when
GTIOCB input is 0.
DSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down
Enable)
The DSCARBH bit enables or disables GTCNT counter count down on the rising edge of GTIOCA pin input, when
GTIOCB input is 1.
DSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down
Enable)
The DSCAFBL bit enables or disables GTCNT counter count down on the falling edge of GTIOCA pin input, when
GTIOCB input is 0.
DSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down
Enable)
The DSCAFBH bit enables or disables GTCNT counter count down on the falling edge of GTIOCA pin input, when
GTIOCB input is 1.
DSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down
Enable)
The DSCBRAL bit enables or disables GTCNT counter count down on the rising edge of GTIOCB pin input, when
GTIOCA input is 0.
DSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down
Enable)
The DSCBRAH bit enables or disables GTCNT counter count down on the rising edge of GTIOCB pin input, when
GTIOCA input is 1.
DSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down
Enable)
The DSCBFAL bit enables or disables GTCNT counter count down on the falling edge of GTIOCB pin input, when
GTIOCA input is 0.
DSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down
Enable)
The DSCBFAH bit enables or disables GTCNT counter count down on the falling edge of GTIOCB pin input, when
GTIOCA input is 1.
DSELCm bit (ELC_GPTm Event Source Counter Count Down Enable) (m = A to H)
The DSELCm bit enables or disables GTCNT counter count down at the ELC_GPTm event input.
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23.2.10
23. General PWM Timer (GPT)
General PWM Timer Input Capture Source Select Register A (GTICASR)
Address(es): GPT32EHm.GTICASR 4007 8024h + 0100h × m (m = 0 to 3)
GPT32Em.GTICASR 4007 8024h + 0100h × m (m = 4 to 7)
GPT32m.GTICASR 4007 8024h + 0100h × m (m = 8 to 13)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
ASELC ASELC ASELC ASELC ASELC ASELC ASELC ASELC
H
G
F
E
D
C
B
A
ASCBF ASCBF ASCBR ASCBR ASCAF ASCAF ASCAR ASCAR ASGTR ASGTR ASGTR ASGTR ASGTR ASGTR ASGTR ASGTR
AH
AL
AH
AL
BH
BL
BH
BL
GDF
GDR
GCF
GCR
GBF
GBR
GAF
GAR
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ASGTRGAR
GTETRGA Pin Rising Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of
GTETRGA input
1: GTCCRA input capture enabled on the rising edge of
GTETRGA input.
R/W
b1
ASGTRGAF
GTETRGA Pin Falling Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
GTETRGA input
1: GTCCRA input capture enabled on the falling edge of
GTETRGA input.
R/W
b2
ASGTRGBR
GTETRGB Pin Rising Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of
GTETRGB input
1: GTCCRA input capture enabled on the rising edge of
GTETRGB input.
R/W
b3
ASGTRGBF
GTETRGB Pin Falling Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
GTETRGB input
1: GTCCRA input capture enabled on the falling edge of
GTETRGB input.
R/W
b4
ASGTRGCR
GTETRGC Pin Rising Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of
GTETRGC input
1: GTCCRA input capture enabled on the rising edge of
GTETRGC input.
R/W
b5
ASGTRGCF
GTETRGC Pin Falling Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
GTETRGC input
1: GTCCRA input capture enabled on the falling edge of
GTETRGC input.
R/W
b6
ASGTRGDR
GTETRGD Pin Rising Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of
GTETRGD input
1: GTCCRA input capture enabled on the rising edge of
GTETRGD input.
R/W
b7
ASGTRGDF
GTETRGD Pin Falling Input Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
GTETRGD input
1: GTCCRA input capture enabled on the falling edge of
GTETRGD input.
R/W
b8
ASCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of
GTIOCA input when GTIOCB input is 0
1: GTCCRA input capture enabled on the rising edge of
GTIOCA input when GTIOCB input is 0.
R/W
b9
ASCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of
GTIOCA input when GTIOCB input is 1
1: GTCCRA input capture enabled on the rising edge of
GTIOCA input when GTIOCB input is 1.
R/W
b10
ASCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
GTIOCA input when GTIOCB input is 0
1: GTCCRA input capture enabled on the falling edge of
GTIOCA input when GTIOCB input is 0.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b11
ASCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
GTIOCA input when GTIOCB input is 1
1: GTCCRA input capture enabled on the falling edge of
GTIOCA input when GTIOCB input is 1.
R/W
b12
ASCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of
GTIOCB input when GTIOCA input is 0
1: GTCCRA input capture enabled on the rising edge of
GTIOCB input when GTIOCA input is 0.
R/W
b13
ASCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the rising edge of
GTIOCB input when GTIOCA input is 1
1: GTCCRA input capture enabled on the rising edge of
GTIOCB input when GTIOCA input is 1.
R/W
b14
ASCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
GTIOCB input when GTIOCA input is 0
1: GTCCRA input capture enabled on the falling edge of
GTIOCB input when GTIOCA input is 0.
R/W
b15
ASCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled on the falling edge of
GTIOCB input when GTIOCA input is 1
1: GTCCRA input capture enabled on the falling edge of
GTIOCB input when GTIOCA input is 1.
R/W
b16
ASELCA
ELC_GPTA Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at ELC_GPTA event
input
1: GTCCRA input capture enabled at ELC_GPTA event
input.
R/W
b17
ASELCB
ELC_GPTB Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at ELC_GPTB event
input
1: GTCCRA input capture enabled at ELC_GPTB event
input.
R/W
b18
ASELCC
ELC_GPTC Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at ELC_GPTC event
input
1: GTCCRA input capture enabled at ELC_GPTC event
input.
R/W
b19
ASELCD
ELC_GPTD Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at ELC_GPTD event
input
1: GTCCRA input capture enabled at ELC_GPTD event
input.
R/W
b20
ASELCE
ELC_GPTE Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at ELC_GPTE event
input
1: GTCCRA input capture enabled at ELC_GPTE event
input.
R/W
b21
ASELCF
ELC_GPTF Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at ELC_GPTF event
input
1: GTCCRA input capture enabled at ELC_GPTF event
input.
R/W
b22
ASELCG
ELC_GPTG Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at ELC_GPTG event
input
1: GTCCRA input capture enabled at ELC_GPTG event
input.
R/W
b23
ASELCH
ELC_GPTH Event Source
GTCCRA Input Capture Enable
0: GTCCRA input capture disabled at ELC_GPTH event
input
1: GTCCRA input capture enabled at ELC_GPTH event
input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
The GTICASR register sets the source of input capture for GTCCRA.
ASGTRGAR bit (GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable)
The ASGTRGAR bit enables or disables input capture for GTCCRA on the rising edge of GTETRGA pin input.
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23. General PWM Timer (GPT)
ASGTRGAF bit (GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable)
The ASGTRGAF bit enables or disables input capture for GTCCRA on the falling edge of GTETRGA pin input.
ASGTRGBR bit (GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable)
The ASGTRGBR bit enables or disables input capture for GTCCRA on the rising edge of GTETRGB pin input.
ASGTRGBF bit (GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable)
The ASGTRGBF bit enables or disables input capture for GTCCRA on the falling edge of GTETRGB pin input.
ASGTRGCR bit (GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable)
The ASGTRGCR bit enables or disables input capture for GTCCRA on the rising edge of GTETRGC pin input.
ASGTRGCF bit (GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable)
The ASGTRGCF bit enables or disables input capture for GTCCRA on the falling edge of GTETRGC pin input.
ASGTRGDR bit (GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable)
The ASGTRGDR bit enables or disables input capture for GTCCRA on the rising edge of GTETRGD pin input.
ASGTRGDF bit (GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable)
The ASGTRGDF bit enables or disables input capture for GTCCRA on the falling edge of GTETRGD pin input.
ASCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture
Enable)
The ASCARBL bit enables or disables input capture for GTCCRA on the rising edge of GTIOCA pin input, when
GTIOCB input is 0.
ASCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture
Enable)
The ASCARBH bit enables or disables input capture for GTCCRA on the rising edge of GTIOCA pin input, when
GTIOCB input is 1.
ASCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture
Enable)
The ASCAFBL bit enables or disables input capture for GTCCRA on the falling edge of GTIOCA pin input, when
GTIOCB input is 0.
ASCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture
Enable)
The ASCAFBH bit enables or disables input capture for GTCCRA on the falling edge of GTIOCA pin input, when
GTIOCB input is 1.
ASCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture
Enable)
The ASCBRAL bit enables or disables input capture for GTCCRA on the rising edge of GTIOCB pin input, when
GTIOCA input is 0.
ASCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture
Enable)
The ASCBRAH bit enables or disables input capture for GTCCRA on the rising edge of GTIOCB pin input, when
GTIOCA input is 1.
ASCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture
Enable)
The ASCBFAL bit enables or disables input capture for GTCCRA on the falling edge of GTIOCB pin input, when
GTIOCA input is 0.
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23. General PWM Timer (GPT)
ASCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture
Enable)
The ASCBFAH bit enables or disables input capture for GTCCRA on the falling edge of GTIOCB pin input, when
GTIOCA input is 1.
ASELCm bit (ELC_GPTm Event Source Counter GTCCRA Input Capture Enable) (m = A to H)
The ASELCm bit enables or disables input capture for GTCCRA at the ELC_GPTm event input.
23.2.11
General PWM Timer Input Capture Source Select Register B (GTICBSR)
Address(es): GPT32EHm.GTICBSR 4007 8028h + 0100h × m (m = 0 to 3)
GPT32Em.GTICBSR 4007 8028h + 0100h × m (m = 4 to 7)
GPT32m.GTICBSR 4007 8028h + 0100h × m (m = 8 to 13)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
BSELC BSELC BSELC BSELC BSELC BSELC BSELC BSELC
H
G
F
E
D
C
B
A
BSCBF BSCBF BSCBR BSCBR BSCAF BSCAF BSCAR BSCAR BSGTR BSGTR BSGTR BSGTR BSGTR BSGTR BSGTR BSGTR
AH
AL
AH
AL
BH
BL
BH
BL
GDF
GDR
GCF
GCR
GBF
GBR
GAF
GAR
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BSGTRGAR
GTETRGA Pin Rising Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of
GTETRGA input
1: GTCCRB input capture enabled on the rising edge of
GTETRGA input.
R/W
b1
BSGTRGAF
GTETRGA Pin Falling Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
GTETRGA input
1: GTCCRB input capture enabled on the falling edge of
GTETRGA input.
R/W
b2
BSGTRGBR
GTETRGB Pin Rising Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of
GTETRGB input
1: GTCCRB input capture enabled on the rising edge of
GTETRGB input.
R/W
b3
BSGTRGBF
GTETRGB Pin Falling Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
GTETRGB input
1: GTCCRB input capture enabled on the falling edge of
GTETRGB input.
R/W
b4
BSGTRGCR
GTETRGC Pin Rising Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of
GTETRGC input
1: GTCCRB input capture enabled on the rising edge of
GTETRGC input.
R/W
b5
BSGTRGCF
GTETRGC Pin Falling Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
GTETRGC input
1: GTCCRB input capture enabled on the falling edge of
GTETRGC input.
R/W
b6
BSGTRGDR
GTETRGD Pin Rising Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of
GTETRGD input
1: GTCCRB input capture enabled on the rising edge of
GTETRGD input.
R/W
b7
BSGTRGDF
GTETRGD Pin Falling Input Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
GTETRGD input
1: GTCCRB input capture enabled on the falling edge of
GTETRGD input.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b8
BSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of
GTIOCA input when GTIOCB input is 0
1: GTCCRB input capture enabled on the rising edge of
GTIOCA input when GTIOCB input is 0.
R/W
b9
BSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of
GTIOCA input when GTIOCB input is 1
1: GTCCRB input capture enabled on the rising edge of
GTIOCA input when GTIOCB input is 1.
R/W
b10
BSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
GTIOCA input when GTIOCB input is 0
1: GTCCRB input capture enabled on the falling edge of
GTIOCA input when GTIOCB input is 0.
R/W
b11
BSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
GTIOCA input when GTIOCB input is 1
1: GTCCRB input capture enabled on the falling edge of
GTIOCA input when GTIOCB input is 1.
R/W
b12
BSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of
GTIOCB input when GTIOCA input is 0
1: GTCCRB input capture enabled on the rising edge of
GTIOCB input when GTIOCA input is 0.
R/W
b13
BSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the rising edge of
GTIOCB input when GTIOCA input is 1
1: GTCCRB input capture enabled on the rising edge of
GTIOCB input when GTIOCA input is 1.
R/W
b14
BSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
GTIOCB input when GTIOCA input is 0
1: Enable GTCCRB input capture on the falling edge of
GTIOCB input when GTIOCA input is 0.
R/W
b15
BSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled on the falling edge of
GTIOCB input when GTIOCA input is 1
1: GTCCRB input capture enabled on the falling edge of
GTIOCB input when GTIOCA input is 1.
R/W
b16
BSELCA
ELC_GPTA Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at ELC_GPTA event
input
1: GTCCRB input capture enabled at ELC_GPTA event
input.
R/W
b17
BSELCB
ELC_GPTB Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at ELC_GPTB event
input
1: GTCCRB input capture enabled at ELC_GPTB event
input.
R/W
b18
BSELCC
ELC_GPTC Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at ELC_GPTC event
input
1: GTCCRB input capture enabled at ELC_GPTC event
input.
R/W
b19
BSELCD
ELC_GPTD Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at ELC_GPTD event
input
1: GTCCRB input capture enabled at ELC_GPTD event
input.
R/W
b20
BSELCE
ELC_GPTE Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at ELC_GPTE event
input
1: GTCCRB input capture enabled at ELC_GPTE event
input.
R/W
b21
BSELCF
ELC_GPTF Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at ELC_GPTF event
input
1: GTCCRB input capture enabled at ELC_GPTF event
input.
R/W
b22
BSELCG
ELC_GPTG Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at ELC_GPTG event
input
1: GTCCRB input capture enabled at ELC_GPTG event
input.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b23
BSELCH
ELC_GPTH Event Source
GTCCRB Input Capture Enable
0: GTCCRB input capture disabled at ELC_GPTH event
input
1: GTCCRB input capture enabled at ELC_GPTH event
input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
The GTICBSR register sets the source of input capture for GTCCRB.
BSGTRGAR bit (GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable)
The BSGTRGAR bit enables or disables input capture for GTCCRB on the rising edge of GTETRGA pin input.
BSGTRGAF bit (GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable)
The BSGTRGAF bit enables or disables input capture for GTCCRB on the falling edge of GTETRGA pin input.
BSGTRGBR bit (GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable)
The BSGTRGBR bit enables or disables input capture for GTCCRB on the rising edge of GTETRGB pin input.
BSGTRGBF bit (GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable)
The BSGTRGBF bit enables or disables input capture for GTCCRB on the falling edge of GTETRGB pin input.
BSGTRGCR bit (GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable)
The BSGTRGCR bit enables or disables input capture for GTCCRB on the rising edge of GTETRGC pin input.
BSGTRGCF bit (GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable)
The BSGTRGCF bit enables or disables input capture for GTCCRB on the falling edge of GTETRGC pin input.
BSGTRGDR bit (GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable)
The BSGTRGDR bit enables or disables input capture for GTCCRB on the rising edge of GTETRGD pin input.
BSGTRGDF bit (GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable)
The BSGTRGDF bit enables or disables input capture for GTCCRB on the falling edge of GTETRGD pin input.
BSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture
Enable)
The BSCARBL bit enables or disables input capture for GTCCRB on the rising edge of GTIOCA pin input, when
GTIOCB input is 0.
BSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture
Enable)
The BSCARBH bit enables or disables input capture for GTCCRB on the rising edge of GTIOCA pin input, when
GTIOCB input is 1.
BSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture
Enable)
The BSCAFBL bit enables or disables input capture for GTCCRB on the falling edge of GTIOCA pin input, when
GTIOCB input is 0.
BSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture
Enable)
The BSCAFBH bit enables or disables input capture for GTCCRB on the falling edge of GTIOCA pin input, when
GTIOCB input is 1.
BSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture
Enable)
The BSCBRAL bit enables or disables input capture for GTCCRB on the rising edge of GTIOCB pin input, when
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23. General PWM Timer (GPT)
GTIOCA input is 0.
BSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture
Enable)
The BSCBRAH bit enables or disables input capture for GTCCRB on the rising edge of GTIOCB pin input, when
GTIOCA input is 1.
BSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture
Enable)
The BSCBFAL bit enables or disables input capture for GTCCRB on the falling edge of GTIOCB pin input, when
GTIOCA input is 0.
BSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture
Enable)
The BSCBFAH bit enables or disables input capture for GTCCRB on the falling edge of GTIOCB pin input, when
GTIOCA input is 1.
BSELCm bit (ELC_GPTm Event Source Counter GTCCRB Input Capture Enable) (m = A to H)
The BSELCm bit enables or disables input capture for GTCCRB at the ELC_GPTm event input.
23.2.12
General PWM Timer Control Register (GTCR)
Address(es): GPT32EHm.GTCR 4007 802Ch + 0100h × m (m = 0 to 3)
GPT32Em.GTCR 4007 802Ch + 0100h × m (m = 4 to 7)
GPT32m.GTCR 4007 802Ch + 0100h × m (m = 8 to 13)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
—
—
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
—
—
—
—
—
0
0
0
0
0
b24
b23
b22
b21
b20
b19
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
CST
0
0
0
0
0
0
0
0
0
0
0
TPCS[2:0]
b18
b17
b16
MD[2:0]
Bit
Symbol
Bit name
Description
R/W
b0
CST
Count Start
0: Count operation is stopped
1: Count operation is performed.
R/W
b15 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b18 to b16 MD[2:0]
Mode Select
b18
R/W
b23 to b19 —
Reserved
These bits are read as 0. The write value should be 0.
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b16
0 0 0: Saw-wave PWM mode (single buffer or double
buffer possible)
0 0 1: Saw-wave one-shot pulse mode (fixed buffer
operation)
0 1 0: Setting prohibited
0 1 1: Setting prohibited
1 0 0: Triangle-wave PWM mode 1 (32-bit transfer at
trough) (single buffer or double buffer possible)
1 0 1: Triangle-wave PWM mode 2 (32-bit transfer at crest
and trough) (single buffer or double buffer possible)
1 1 0: Triangle-wave PWM mode 3 (64-bit transfer at
trough) (fixed buffer operation)
1 1 1: Setting prohibited.
R/W
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Bit
23. General PWM Timer (GPT)
Symbol
Bit name
Description
R/W
b26 to b24 TPCS[2:0]
Timer Prescaler Select
b26
R/W
b31 to b27 —
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
0
0
1
1
0
0
b24
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64
0: PCLKD/256
1: PCLKD/1024.
R/W
The GTCR register controls GTCNT.
CST bit (Count Start)
The CST bit controls the GTCNT counter start and stop.
[Setting conditions]
The GTSTR value in which the channel number associated with the bit number is set to 1 with the GTSSR.CSTRT
bit at 1
The ELC event input or the GTIOCA/GTIOCB/GTETRGn port input event enabled by GTSSR as the counter start
source, occurs
1 is written by software directly.
[Clearing conditions]
GTSTP value in which the channel number associated with the bit number is set to 1 with the GTSSR.CSTOP bit at
1.
The ELC event input or the GTIOCA/GTIOCB/GTETRGn port input event enabled by GTSSR as the counter stop
source, occurs
0 is written by software directly.
MD[2:0] bits (Mode Select)
The MD[2:0] bits select the GPT operating mode. The MD[2:0] bits must be set while the GTCNT operation is stopped.
TPCS[2:0] bits (Timer Prescaler Select)
The TPCS[2:0] bits select the clock for GTCNT. A clock prescaler can be selected independently for each channel. The
TPCS[2:0] bits must be set while the GTCNT operation is stopped.
23.2.13
General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC)
Address(es): GPT32EHm.GTUDDTYC 4007 8030h + 0100h × m (m = 0 to 3)
GPT32Em.GTUDDTYC 4007 8030h + 0100h × m (m = 4 to 7)
GPT32m.GTUDDTYC 4007 8030h + 0100h × m (m = 8 to 13)
b31
b30
b29
b28
b27
b26
OBDTY OBDTY
R
F
b25
—
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
—
—
—
—
—
0
0
0
0
0
Value after reset:
Value after reset:
b24
OBDTY[1:0]
b23
b22
b21
b20
b19
b18
OADTY OADTY
R
F
b17
b16
—
—
—
—
OADTY[1:0]
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
UDF
UD
0
0
0
0
0
0
0
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b0
UD
Count Direction Setting
0: GTCNT counts down
1: GTCNT counts up.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b1
UDF
Forcible Count Direction
Setting
0: Not forcibly set
1: Forcibly set.
R/W
b15 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b17, 16
OADTY[1:0]
GTIOCA Output Duty Setting
b17 b16
R/W
b18
OADTYF
Forcible GTIOCA Output Duty
Setting
0: Not forcibly set
1: Forcibly set.
R/W
b19
OADTYR
GTIOCA Output Value
Selecting after Releasing
0%/100% Duty Setting
0: Apply output value set in 0%/100% duty to GTIOA[3:2]
function after releasing 0%/100% duty setting
1: Apply masked compare match output value to GTIOA[3:2]
function after releasing 0%/100% duty setting.
R/W
b23 to b20 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25, b24
OBDTY[1:0]
GTIOCB Output Duty Setting
b25 b24
R/W
b26
OBDTYF
Forcible GTIOCB Output Duty
Setting
0: Do not force setting
1: Force setting.
R/W
b27
OBDTYR
GTIOCB Output Value
Selecting after Releasing
0%/100% Duty Setting
0: Apply output value set in 0%/100% duty to GTIOB[3:2]
function after releasing 0%/100% duty setting
1: Apply masked compare match output value to GTIOB[3:2]
function after releasing 0%/100% duty setting.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b28 —
0
1
1
0
1
1
x: GTIOCA pin duty depends on compare match
0: GTIOCA pin duty = 0%
1: GTIOCA pin duty = 100%.
x: GTIOCB pin duty depends on compare match
0: GTIOCB pin duty = 0%
1: GTIOCB pin duty = 100%.
x: Don’t care
The GTUDDTYC register sets the direction in which GTCNT counts (up-counting or down-counting) and sets the duty
of the GTIOCA/GTIOCB pin output.
Count direction:
In saw-wave mode
When the UD value is set to 0 during up-counting, the count direction changes at an overflow (the timing synchronous
with count clock after the GTCNT value becomes the GTPR value). When the UD value is set to 1 during downcounting, the count direction changes at an underflow (the timing synchronous with count clock after the GTCNT value
becomes 0).
When the UD value changes from 1 to 0 with the UDF bit being 0 and while counting is stopped, the counter starts upcounting and the count direction changes at an overflow (the timing synchronous with count clock after the GTCNT
value becomes GTPR value). When the UD value changes from 0 to 1 with the UDF bit being 0 and while counting
stops, the counter starts down-counting and the count direction changes at an underflow (the timing synchronous with
count clock after the GTCNT value becomes 0).
When the UDF bit is set to 1 while counting stops, the UD bit value is reflected in the count direction when counting
starts.
Count direction:
In triangle-wave mode
When the UD value changes during counting, the count direction does not change. When the UD value changes while the
UDF bit is 0 and counting stops, the change is not reflected in the count direction when counting starts.
When the UDF bit is set to 1 while counting stops, the UD value is reflected in the count direction when counting starts.
UD bit (Count Direction Setting)
The UD bit sets the count direction (up-counting or down-counting.) for GTCNT.
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23. General PWM Timer (GPT)
UDF bit (Forcible Count Direction Setting)
The UDF bit forcibly sets the count direction when GTCNT starts operation as the UD value. Only write 0 to this bit
during counter operation. When 1 is written to UDF while counting stops, return UDF to 0 before counting starts.
Output duty
In saw-wave mode
When the OADTY/OBDTY value changes during up-counting, the duty is reflected at an overflow (GTCNT = GTPR).
When the OADTY/OBDTY value changes during down-counting, the duty is reflected at an underflow (GTCNT = 0).
When the OADTY/OBDTY value changes to 1 with the OADTYF/OBDTYF bit being 0 and while counting stops, the
output duty is not reflected at the starting counter operation. When the count direction is up, the output duty is reflected
at an overflow (GTCNT = GTPR). When the count direction is down, the output duty is reflected at an underflow
(GTCNT = 0).
When the OADTY/OBDTY value changes to 0 with the OADTYF/OBDTYF bit being 1 and while counting stops, the
output duty is reflected at the starting counter operation.
Output duty
In triangle-wave mode
When the OADTY/OBDTY value changes during counting, the duty is reflected at an underflow. When the
OADTY/OBDTY value changes to 1 with the OADTYF/OBDTYF bit being 0 and while counting stops, the output duty
is not reflected at the starting counter operation. The output duty is reflected at an underflow.
When the OADTY/OBDTY value changes to 0 with the OADTYF/OBDTYF bit being 1 and while counting stops, the
output duty is reflected at the starting counter operation.
OmDTY[1:0] bits (GTIOCm Output Duty Setting) (m = A, B)
The OmDTY[1:0] bits set the output duty of the GTIOCm pin to either 0%, 100%, or compare match control.
OmDTYF bit (Forcible GTIOCm Output Duty Setting) (m = A, B)
The OmDTYF bit forcibly sets the output duty cycle to the OmDTY setting. Set this bit to 0 during counter operation.
When OmDTYF bit is set to 1 while counting stops, return OmDTYF to 0 until the first period ends after the counter
starts.
OmDTYR bit (GTIOCm Output Value Selecting after Releasing 0%/100% Duty Setting) (m = A, B)
The OmDTYR bits select the value that is the object of output retained or toggled at cycle end, when the control changes
from 0%/100% duty setting to compare match for GTIOCm pin and GTIOR.GTIOm[3:2] are set to 00b (output retained
at cycle end) or GTIOR.GTIOm[3:2] are set to 11b (output toggled at cycle end).
While the duty 0%/100% setting operation is running, the compare match operation continues inside the GPT32. When
the OmDTYR bit is set to 1, the GTIOCm pin is in the output state selected by the GTIOR.GTIOm [3:2] bits at the end of
the cycle in this compare match operation.
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23.2.14
23. General PWM Timer (GPT)
General PWM Timer I/O Control Register (GTIOR)
Address(es): GPT32EHm.GTIOR 4007 8034h + 0100h × m (m = 0 to 3)
GPT32Em.GTIOR 4007 8034h + 0100h × m (m = 4 to 7)
GPT32m.GTIOR 4007 8034h + 0100h × m (m = 8 to 13)
b31
b30
NFCSB[1:0]
Value after reset:
Bit
b28
b27
b26
b25
NFBEN
—
—
OBDF[1:0]
b24
OBE
b23
b22
OBHLD OBDFL
T
b21
b20
b19
—
b18
b17
b16
GTIOB[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NFAEN
—
—
OADF[1:0]
0
0
0
0
0
0
NFCSA[1:0]
0
Value after reset:
b29
0
Symbol
Bit name
OAE
0
OAHLD OADFL
T
0
0
0
—
0
GTIOA[4:0]
0
0
0
Description
R/W
b4 to b0
GTIOA[4:0]
GTIOCA Pin Function Select
See Table 23.5.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
OADFLT
GTIOCA Pin Output Value
Setting at the Count Stop
0: The GTIOCA pin outputs low when counting stops
1: The GTIOCA pin outputs high when counting stops.
R/W
b7
OAHLD
GTIOCA Pin Output Setting at
the Start/Stop Count
0: The GTIOCA pin output level at the start/stop of counting
depends on the register setting
1: The GTIOCA pin output level is retained at the start/stop of
counting.
R/W
b8
OAE
GTIOCA Pin Output Enable
0: Output is disabled
1: Output is enabled.
R/W
b10, b9
OADF[1:0]
GTIOCA Pin Disable Value
Setting
b10 b9
R/W
b12, b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13
NFAEN
Noise Filter A Enable
0: The noise filter for the GTIOCA pin is disabled
1: The noise filter for the GTIOCA pin is enabled.
R/W
b15, b14
NFCSA[1:0]
Noise Filter A Sampling Clock
Select
b15 b14
R/W
b20 to b16 GTIOB[4:0]
GTIOCB Pin Function Select
See Table 23.5.
R/W
b21
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b22
OBDFLT
GTIOCB Pin Output Value
Setting at the Count Stop
0: The GTIOCB pin outputs low when counting stops
1: The GTIOCB pin outputs high when counting stops.
R/W
b23
OBHLD
GTIOCB Pin Output Setting at
the Start/Stop Count
0: The GTIOCB pin output level at the start/stop of counting
depends on the register setting
1: The GTIOCB pin output level is retained at the start/stop of
counting.
R/W
b24
OBE
GTIOCB Pin Output Enable
0: Output is disabled
1: Output is enabled.
R/W
b26, b25
OBDF[1:0]
GTIOCB Pin Disable Value
Setting
b26 b25
R/W
b28, b27
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b29
NFBEN
Noise Filter B Enable
0: Noise filter for GTIOCB pin is disabled
1: Noise filter for GTIOCB pin is enabled.
R/W
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0
0
1
1
0
0
1
1
0
0
1
1
0: Output disable is prohibited
1: GTIOCA pin is set to Hi-Z on output disable
0: Set GTIOCA pin to 0 on output disable
1: Set GTIOCA pin to 1 on output disable.
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
0: Output disable is prohibited
1: GTIOCB pin is set to Hi-Z on output disable
0: GTIOCB pin is set to 0 on output disable
1: GTIOCB pin is set to 1 on output disable.
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b31, b30
NFCSB[1:0]
Noise Filter B Sampling Clock
Select
b31 b30
R/W
0
0
1
1
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
The GTIOR register sets the functions of the GTIOCA and GTIOCB pins.
GTIOA[4:0] bits (GTIOCA Pin Function Select)
The GTIOA[4:0] bits select the GTIOCA pin function. For details, see Table 23.5.
OADFLT bit (GTIOCA Pin Output Value Setting at the Count Stop)
The OADFLT bit selects whether the GTIOCA pin outputs high or low when counting stops.
OAHLD bit (GTIOCA Pin Output Setting at the Start/Stop Count)
The OAHLD bit specifies whether the GTIOCA pin output level is retained or the level at the start/stop of counting
depends on the register setting.
When the OAHLD bit is set to 0:
The value specified in bit [4] of the GTIOA[4:0] bits is output when counting starts
The value specified in the OADFLT bit is output when counting stops
If the OADFLT bit is modified while counting stops, the new value is immediately reflected in the output.
When the OAHLD bit is set to 1:
The output is retained when counting starts or stops.
OAE bit (GTIOCA Pin Output Enable)
The OAE bit disables or enables the GTIOCA pin output.
When GTCCRA register is used as the input capture register (at least one bit in the GTICASR register is set to 1), the
GTIOCA pin does not output regardless of the OAE bit value.
OADF[1:0] bits (GTIOCA Pin Disable Value Setting)
The OADF[1:0] bits select the output value of GTIOCA pin when an output disable request occurs.
NFAEN bit (Noise Filter A Enable)
The NFAEN bit disables or enables the noise filter for input from the GTIOCA pin. Because changing the value of the bit
might lead to internal generation of an unexpected edge, select the output compare function for the relevant pin in the
GTIOR register before doing so.
NFCSA[1:0] bits (Noise Filter A Sampling Clock Select)
The NFCSA[1:0] bits set the sampling interval for the noise filter of the GTIOCA pin. When setting these bits, wait for 2
cycles of the selected sampling interval before setting the input capture function.
GTIOB[4:0] bits (GTIOCB Pin Function Select)
The GTIOB[4:0] bits select the GTIOCB pin function. For details, see Table 23.5.
OBDFLT bit (GTIOCB Pin Output Value Setting at the Count Stop)
The OBDFLT bit sets whether the GTIOCB pin outputs high or low when counting stops.
OBHLD bit (GTIOCB Pin Output Setting at the Start/Stop Count)
The OBHLD bit specifies whether the GTIOCB pin output level is retained or the level at the start/stop of counting
depends on the register setting.
When the OBHLD bit is set to 0:
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23. General PWM Timer (GPT)
The value specified in bit [4] of the GTIOB[4:0] bits is output when counting starts
The value specified in the OBDFLT bit is output when counting stops
If the OBDFLT bit is modified while counting stops, the new value is immediately reflected in the output.
When the OBHLD bit is set to 1:
The output is retained when counting starts or stops.
OBE bit (GTIOCB Pin Output Enable)
The OBE bit disables or enables the GTIOCB pin output.
When GTCCRB register is used as the input capture register (at least one bit in GTICBSR register is set to 1), the
GTIOCB pin does not output regardless of the OBE bit value.
OBDF[1:0] bits (GTIOCB Pin Disable Value Setting)
The OBDF[1:0] bits select the output value of GTIOCB pin when an output disable request occurs.
NFBEN bit (Noise Filter B Enable)
The NFBEN bit disables or enables the noise filter for input from the GTIOCB pin. Because changing the value of the bit
might lead to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the
GTIOR register before doing so.
NFCSB[1:0] bits (Noise Filter B Sampling Clock Select)
The NFCSB[1:0] bits set the sampling interval for the noise filter of the GTIOCB pin. When setting these bits, wait for 2
cycles of the selected sampling interval before setting the input capture function.
Table 23.5
Settings of GTIOA[4:0] and GTIOB[4:0] bits (1 of 2)
GTIOA/GTIOB[4:0] bits
Function
b4
b3
b2
b1
b0
b4
b3, b2
0
0
0
0
0
Initial output is low
0
0
0
0
1
Output retained at
cycle end
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
High output at GTCCRA/GTCCRB compare match
0
0
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
High output at GTCCRA/GTCCRB compare match
0
1
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
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b1, b0
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Low output at cycle
end
High output at cycle
end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Output toggled at
cycle end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
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Table 23.5
23. General PWM Timer (GPT)
Settings of GTIOA[4:0] and GTIOB[4:0] bits (2 of 2)
GTIOA/GTIOB[4:0] bits
Function
b4
b3
b2
b1
b0
b4
b3, b2
1
0
0
0
0
Set initial output high
1
0
0
0
1
Retain output at
cycle end
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
High output at GTCCRA/GTCCRB compare match
1
0
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
High output at GTCCRA/GTCCRB compare match
1
1
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
Note 1.
Note 2.
Note 3.
b1, b0
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Output low at cycle
end
Output high at cycle
end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Toggle output at
cycle end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
The cycle end means an overflow (GTCNT changes from GTPR to 0 in up-counting) or underflow (GTCNT changes from 0 to
GTPR in down-counting). The GTCNT counter is cleared for saw waves and for the trough (GTCNT changes from 0 to 1) for
triangle waves.
When the timing of a cycle end and the timing of a GTCCRA/GTCCRB compare match are the same in a compare-match
operation, the b3 and b2 settings are given priority in saw-wave PWM mode, and the b1 and b0 settings are given priority in any
other mode.
In event count operation where at least one bit in GTUPSR or GTDNSR is set to 1, the setting of b3 and b2 is ignored.
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23.2.15
23. General PWM Timer (GPT)
General PWM Timer Interrupt Output Setting Register (GTINTAD)
Address(es): GPT32EHm.GTINTAD 4007 8038h + 0100h × m (m = 0 to 3)
GPT32Em.GTINTAD 4007 8038h + 0100h × m (m = 4 to 7)
GPT32m.GTINTAD 4007 8038h + 0100h × m (m = 8 to 13)
GPT32EH, GPT32E
b31
—
b30
b29
b28
GRPAB GRPAB GRPDT
L
H
E
b27
b26
b25
b24
b23
b22
b21
b20
—
—
GRP[1:0]
—
—
—
—
b19
b18
b17
b16
ADTRB ADTRB ADTRA ADTRA
DEN
UEN
DEN
UEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
GRP[1:0]
—
—
—
—
—
—
—
—
Value after reset:
Value after reset:
GPT32
b31
—
GRPAB GRPAB
L
H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
b15 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b16
ADTRAUEN
GTADTRA Compare Match (UpCounting) A/D Converter Start Request
Enable
0: A/D converter start request disabled
1: A/D converter start request enabled.
R/W
b17
ADTRADEN
GTADTRA Compare Match (DownCounting) A/D Converter Start Request
Enable
0: A/D converter start request disabled
1: A/D converter start request enabled.
R/W
b18
ADTRBUEN
GTADTRB Compare Match (UpCounting) A/D Converter Start Request
Enable
0: A/D converter start request disabled
1: A/D converter start request enabled.
R/W
b19
ADTRBDEN
GTADTRB Compare Match (DownCounting) A/D Converter Start Request
Enable
0: A/D converter start request disabled
1: A/D converter start request enabled.
R/W
b23 to b20
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b25, b24
GRP[1:0]
Output Disable Source Select
b25 b24
b27, b26
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b28
GRPDTE
Dead Time Error Output Disable
Request Enable
0: Dead time error output disable request disabled
1: Dead time error output disable request enabled.
R/W
b29
GRPABH
Same Time Output Level High Disable
Request Enable
0: Same time output level high disable request
disabled
1: Same time output level high disable request
enabled.
R/W
b30
GRPABL
Same Time Output Level Low Disable
Request Enable
0: Same time output level low disable request
disabled
1: Same time output level low disable request
enabled.
R/W
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0
0
1
1
R/W
R/W
0: Group A output disable request
1: Group B output disable request
0: Group C output disable request
1: Group D output disable request.
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
The GTINTAD enables or disables interrupt requests, A/D converter start requests, and output disable requests.
ADTRAUEN bit (GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Enable)
The ADTRAUEN bit enables or disables A/D converter start requests generated by GTADTRA compare matches during
GTCNT up-counting. Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
ADTRADEN bit (GTADTRA Compare Match (Down-Counting) A/D Converter Start Request Enable)
The ADTRADEN bit enables or disables A/D converter start requests generated by GTADTRA compare matches during
GTCNT down-counting. Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
ADTRBUEN bit (GTADTRB Compare Match (Up-Counting) A/D Converter Start Request Enable)
The ADTRBUEN bit enables or disables A/D converter start requests generated by GTADTRB compare matches during
GTCNT up-counting. Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
ADTRBDEN bit (GTADTRB Compare Match (Down-Counting) A/D Converter Start Request Enable)
The ADTRBDEN bit enables or disables A/D converter start requests generated by GTADTRB compare matches during
GTCNT down-counting. Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
GRP[1:0] bits (Output Disable Source Select)
The GRP[1:0] bits select GTIOCA pin and GTIOCB pin output disable source. The output disable request to POEG
outputs to the group that is selected with GRP[1:0] bits when dead time error, same time output level high, or same time
output level low occurs based on the output disable request enable bit.
GTST.ODF shows the request of output disable source group that is selected with the GRP[1:0] bits. Set the GRP[1:0]
bits when both GTIOR.OAE and GTIOR.OBE are 0.
GRPDTE bit (Dead Time Error Output Disable Request Enable)
The GRPDTE bit enables or disables dead time error output disable request. Only GPT32EH and GPT32E have this bit.
GPT32 does not have this bit.
GRPABH bit (Same Time Output Level High Disable Request Enable)
The GRPABH bit enables or disables output disable request when the GTIOCA and GTIOCB pins output 1 at the same
time.
GRPABL bit (Same Time Output Level Low Disable Request Enable)
The GRPABL bit enables or disables output disable request when the GTIOCA and GTIOCB pins output 0 at the same
time.
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23.2.16
23. General PWM Timer (GPT)
General PWM Timer Status Register (GTST)
Address(es): GPT32EHm.GTST 4007 803Ch + 0100h × m (m = 0 to 3)
GPT32Em.GTST 4007 803Ch + 0100h × m (m = 4 to 7)
GPT32m.GTST 4007 803Ch + 0100h × m (m = 8 to 13)
GPT32EH, GPT32E
b31
—
b30
b29
b28
OABLF OABHF DTEF
b27
b26
b25
b24
b23
b22
b21
b20
—
—
—
ODF
—
—
—
—
b19
b18
b17
b16
ADTRB ADTRB ADTRA ADTRA
DF
UF
DF
UF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TUCF
—
—
—
—
TCFE
TCFD
TCFC
TCFB
TCFA
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
ODF
—
—
—
—
—
—
—
—
Value after reset:
Value after reset:
ITCNT[2:0]
TCFPU TCFPO TCFF
GPT32
—
OABLF OABHF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TUCF
—
—
—
—
—
—
—
TCFE
TCFD
TCFC
TCFB
TCFA
1
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
TCFPU TCFPO TCFF
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TCFA
Input Capture/Compare Match
Flag A
0: No input capture/compare match of GTCCRA is generated
1: An input capture/compare match of GTCCRA is generated.
R/(W)*1
b1
TCFB
Input Capture/Compare Match
Flag B
0: No input capture/compare match of GTCCRB is generated
1: An input capture/compare match of GTCCRB is generated.
R/(W)*1
b2
TCFC
Input Compare Match Flag C
0: No compare match of GTCCRC is generated
1: A compare match of GTCCRC is generated.
R/(W)*1
b3
TCFD
Input Compare Match Flag D
0: No compare match of GTCCRD is generated
1: A compare match of GTCCRD is generated.
R/(W)*1
b4
TCFE
Input Compare Match Flag E
0: No compare match of GTCCRE is generated
1: A compare match of GTCCRE is generated.
R/(W)*1
b5
TCFF
Input Compare Match Flag F
0: No compare match of GTCCRF is generated
1: A compare match of GTCCRF is generated.
R/(W)*1
b6
TCFPO
Overflow Flag
0: No overflow (crest) occurred
1: An overflow (crest) occurred.
R/(W)*1
b7
TCFPU
Underflow Flag
0: No underflow (trough) occurred
1: An underflow (trough) occurred.
R/(W)*1
b10 to b8
ITCNT[2:0]
GPTn_OVF/GPTn_UDF
Interrupt Skipping Count
Counter
Counter for counting the number of times a timer interrupt is
skipped
R
b14 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
TUCF
Count Direction Flag
0: GTCNT counter counts downward
1: GTCNT counter counts upward.
R
b16
ADTRAUF
GTADTRA Compare Match
(Up-Counting) A/D Converter
Start Request Flag
0: No compare match of GTADTRA at up-counting occurred
1: A compare match of GTADTRA at up-counting occurred.
R/(W)*1
b17
ADTRADF
GTADTRA Compare Match
(Down-Counting) A/D
Converter Start Request Flag
0: No compare match of GTADTRA at down-counting occurred
1: A compare match of GTADTRA at down-counting occurred.
R/(W)*1
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b18
ADTRBUF
GTADTRB Compare Match
(Up-Counting) A/D Converter
Start Request Flag
0: No compare match of GTADTRB at up-counting occurred
1: A compare match of GTADTRB at up-counting occurred.
R/(W)*1
b19
ADTRBDF
GTADTRB Compare Match
(Down-Counting) A/D
Converter Start Request Flag
0: No compare match of GTADTRB at down-counting occurred
1: A compare match of GTADTRB at down-counting occurred.
R/(W)*1
b23 to b20 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b24
Output Disable Flag
0: No output disable request is generated
1: An output disable request is generated.
R
b27 to b25 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28
DTEF
Dead Time Error Flag
0: No dead time error occurred
1: Dead time error occurred.
R
b29
OABHF
Same Time Output Level High
Flag
0: GTIOCA and GTIOCB pins do not output 1 at the same time
1: GTIOCA and GTIOCB pins output 1 at the same time.
R
b30
OABLF
Same Time Output Level Low
Flag
0: GTIOCA and GTIOCB pins do not output 0 at the same time
1: GTIOCA and GTIOCB pins output 0 at the same time.
R
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note 1.
ODF
Only 0 can be written to this bit. Do not write 1.
The GTST register indicates the status of the GPT.
TCFA flag (Input Capture/Compare Match Flag A)
TCFA is the status flag for the input capture or compare match of GTCCRA.
[Setting conditions]
GTCNT = GTCCRA when the GTCCRA register functions as a compare match register
GTCNT counter value is transferred to GTCCRA by the input capture signal when the GTCCRA register functions
as an input capture register.
[Clearing condition]
0 is written to this flag.
TCFB flag (Input Capture/Compare Match Flag B)
TCFB is the status flag for the input capture or compare match of GTCCRB.
[Setting conditions]
GTCNT = GTCCRB when the GTCCRB register functions as a compare match register
GTCNT counter value is transferred to GTCCRB by the input capture signal when the GTCCRB register function
as an input capture register.
[Clearing condition]
0 is written to this flag.
TCFC flag (Input Compare Match Flag C)
TCFC is the status flag for the compare match of GTCCRC.
[Setting condition]
GTCNT = GTCCRC
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
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23. General PWM Timer (GPT)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 01b, 10b, 11b (GTCCRC performs buffer operation).
TCFD flag (Input Compare Match Flag D)
TCFD is the status flag for the compare match of GTCCRD.
[Setting condition]
GTCNT = GTCCRD
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 10b, 11b (GTCCRD performs buffer operation).
TCFE flag (Input Compare Match Flag E)
TCFE is the status flag for the compare match of GTCCRE.
[Setting condition]
GTCNT = GTCCRE
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 01b, 10b, 11b (GTCCRE performs buffer operation).
TCFF flag (Input Compare Match Flag F)
TCFF is the status flag for the compare match of GTCCRF.
[Setting condition]
GTCNT = GTCCRF
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 10b, 11b (GTCCRF performs buffer operation).
TCFPO flag (Overflow Flag)
The TCFPO flag indicates when an overflow or a crest has occurred.
[Setting conditions]
In saw-wave mode, an overflow (GTCNT changes from GTPR to 0 in up-counting) has occurred
In triangle-wave mode, a crest (GTCNT changes from GTPR to GTPR-1) has occurred
In counting by hardware sources, an overflow (GTCNT changes from GTPR to 0 in up-counting) has occurred.
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23. General PWM Timer (GPT)
[Clearing condition]
0 is written to this flag.
TCFPU flag (Underflow Flag)
The TCFPU flag indicates when an underflow or a trough has occurred.
[Setting conditions]
In saw-wave mode, an underflow (GTCNT changes from 0 to GTPR in down-counting) has occurred
In triangle-wave mode, a trough (GTCNT changes from 0 to 1) has occurred
In counting by hardware sources, an underflow (GTCNT changes from 0 to GTPR in down-counting) has occurred.
[Clearing condition]
0 is written to this flag.
ITCNT[2:0] bits (GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter)
When the GPTn_OVF/GPTn_UDF (n = 0 to 7) interrupt skipping function is used (the GTITC.IVTC[1:0] bits are set to
a value other than 00b), the counter in the ITCNT[2:0] bits increments by 1 every time the GPTn_OVF/GPTn_UDF
interrupt source that is selected in GTITC.IVTC[1:0] is generated.
Only GPT32EH and GPT32E have these bits. GPT32 does not have these bits.
[Clearing conditions]
The GPTn_OVF/GPTn_UDF interrupt skipping function is not used (GTITC.IVTT[2:0] is 000b when
GTITC.IVTC[1:0] is 00b)
The GPTn_OVF/GPTn_UDF interrupt skipping count matches the specified count (ITCNT[2:0] matches the
skipping count specified in GTITC.IVTT[2:0]).
TUCF flag (Count Direction Flag)
The TUCF flag indicates the count direction of GTCNT. In event count operation, this flag is set to 1 in up-counting and
to 0 in down-counting.
ADTRAUF flag (GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Flag)
ADTRAUF is the status flag for the compare match of GTADTRA at up-counting.
[Setting condition]
GTCNT = GTADTRA at up-counting.
[Clearing condition]
0 is written to this flag.
ADTRADF flag (GTADTRA Compare Match (Down-Counting) A/D Converter Start Request Flag)
ADTRADF is the status flag for the compare match of GTADTRA at down-counting.
[Setting condition]
GTCNT = GTADTRA at down-counting.
[Clearing condition]
0 is written to this flag.
ADTRBUF flag (GTADTRB Compare Match (Up-Counting) A/D Converter Start Request Flag)
ADTRBUF is the status flag for the compare match of GTADTRB at up-counting.
[Setting condition]
GTCNT = GTADTRB at up-counting.
[Clearing condition]
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23. General PWM Timer (GPT)
0 is written to this flag.
ADTRBDF flag (GTADTRB Compare Match (Down-Counting) A/D Converter Start Request Flag)
ADTRBDF is the status flag for the compare match of GTADTRB at down-counting.
[Setting condition]
GTCNT = GTADTRB at down-counting.
[Clearing condition]
0 is written to this bit.
ODF flag (Output Disable Flag)
The ODF flag shows the request of the output disable source group that is selected in the GRP[1:0] bits. When output is
disabled, an output disable control is not released within the same cycle in which an output disable request is negated. It
is released in the next cycle.
DTEF flag (Dead Time Error Flag)
The DTEF flag indicates that the timer output toggle point after the automatic addition of dead time has exceeded the
timer cycle.
DTEF returns to 0 when the timer output toggle point after the automatic addition of dead time is within the timer cycle.
DTEF is read-only. Writing 0 to clear the flag is not allowed.
[Setting condition]
The timer output toggle point after the automatic addition of dead time has exceeded the timer cycle.
For triangle wave in up-counting: GTCCRA - GTDVU ≤ 0
For triangle wave in down-counting: GTCCRA - GTDVD < 0
For saw-wave one-shot pulse mode in up-counting:
GTCCRA - GTDVU < 0 or GTCCRA + GTDVD > GTPR
For saw-wave one-shot pulse mode in down-counting:
GTCCRA + GTDVU > GTPR or GTCCRA - GTDVD < 0
[Clearing condition]
The timer output toggle point after the automatic addition of dead time is within the timer cycle.
Only GPT32EH and GPT32E have this flag. GPT32 does not have this flag.
GPT32 has the automatic dead time setting function but it does not generate dead time error.
OABHF flag (Same Time Output Level High Flag)
The OABHF flag indicates that the GTIOCA and the GTIOCB pins output 1 at the same time.
When the GTIOCA or GTIOCB pin outputs 0, OABHF returns to 0. OABHF is read-only. Writing 0 to clear the flag is
not allowed. When an interrupt by the OABHF flag is enabled (GTINTAD.GRPABH = 1), the OABHF flag is output to
the POEG as an output disable request.
[Setting condition]
GTIOCA and GTIOCB pins output 1 at the same time when both the OAE and OBE bits are set to 1.
[Clearing conditions]
GTIOCA pin output value is different from GTIOCB pin output value when both the OAE and OBE bits are set to 1
GTIOCA and GTIOCB pins output 0 at the same time when both the OAE and OBE bits are set to 1
Either the OAE bit or OBE bit is set to 0.
OABLF flag (Same Time Output Level Low Flag)
The OABLF flag indicates that the GTIOCA and GTIOCB pins output 0 at the same time.
When the GTIOCA pin or GTIOCB pin outputs 1, OABLF returns to 0. OABLF is read-only. Writing 0 to clear the flag
is not allowed. When an interrupt by the OABLF flag is enabled (GTINTAD.GRPABL = 1), the OABLF flag is output to
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23. General PWM Timer (GPT)
the POEG as an output disable request.
[Setting condition]
The GTIOCA and GTIOCB pins output 0 at the same time when both the OAE and OBE bits are set to 1.
[Clearing conditions]
The GTIOCA pin output value is different from GTIOCB pin output value when both the OAE and OBE bits are set
to 1
The GTIOCA and GTIOCB pins output 1 at the same time when both the OAE and OBE bits are set to 1
Either the OAE bit or OBE bit is set to 0.
The compare-target signals to generate the OABHF/OABLF flag are the compare match outputs (PWM outputs) signals
before they are masked by the output disable function. When the output disable state is active, a compare match is
performed continuously in the GPT and the OABHF/OABLF flag is updated in association with the result of the
compared value.
23.2.17
General PWM Timer Buffer Enable Register (GTBER)
Address(es): GPT32EHm.GTBER 4007 8040h + 0100h × m (m = 0 to 3)
GPT32Em.GTBER 4007 8040h + 0100h × m (m = 4 to 7)
GPT32m.GTBER 4007 8040h + 0100h × m (m = 8 to 13)
GPT32EH, GPT32E
b31
Value after reset:
Value after reset:
b30
b29
—
ADTDB
0
0
0
b15
b14
—
b28
ADTTB[1:0]
b27
b26
b25
b24
ADTTA[1:0]
b23
b22
—
CCRS
WT
b21
—
ADTDA
0
0
0
0
0
0
0
0
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b31
b30
b29
b28
b27
b26
b25
b24
b20
PR[1:0]
b19
b18
b17
b16
CCRB[1:0]
CCRA[1:0]
0
0
0
0
0
b5
b4
b3
b2
b1
b0
—
—
—
BD[3]
BD[2]
BD[1]
BD[0]
0
0
0
0
0
0
0
b23
b22
b21
b20
b19
b18
b17
b16
—
CCRS
WT
GPT32
Value after reset:
Value after reset:
—
—
—
0
0
0
b15
b14
—
0
—
PR[1:0]
CCRB[1:0]
CCRA[1:0]
0
0
0
0
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
BD[1]
BD[0]
0
0
0
0
0
0
0
—
—
0
0
0
0
0
0
0
0
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BD[0]
GTCCR Buffer Operation Disable
0: Buffer operation is enabled
1: Buffer operation is disabled.
R/W
b1
BD[1]
GTPR Buffer Operation Disable
b2
BD[2]
GTADTR Buffer Operation Disable
R/W
b3
BD[3]
GTDV Buffer Operation Disable
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b17, b16
CCRA[1:0]
GTCCRA Buffer Operation
b17 b16
R/W
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R/W
0 0: No buffer operation
0 1: Single buffer operation (GTCCRA ↔ GTCCRC)
1 x: Double buffer operation (GTCCRA ↔ GTCCRC ↔
GTCCRD).
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b19, b18
CCRB[1:0]
GTCCRB Buffer Operation
b19 b18
R/W
b21, b20
PR[1:0]
GTPR Buffer Operation
b21 b20
R/W
b22
CCRSWT
GTCCRA and GTCCRB Forcible
Buffer Operation
Writing 1 to this bit forces a buffer transfer of GTCCRA
and GTCCRB. This bit automatically returns to 0 after 1 is
written. This bit is read as 0.
R/W
b23
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b25, b24
ADTTA[1:0]
GTADTRA Buffer Transfer Timing
Select
Triangle waves
R/W
0 0: No buffer operation
0 1: Single buffer operation (GTCCRB ↔ GTCCRE)
1 x: Double buffer operation (GTCCRB ↔ GTCCRE ↔
GTCCRF).
0 0: No buffer operation
0 1: Single buffer operation (GTPBR → GTPR)
1 x: Double buffer operation (GTPDBR → GTPBR →
GTPR).
b25 b24
0 0: No transfer
0 1: Transfer at crest
1 0: Transfer at trough
1 1: Transfer at both crest and trough.
Saw waves
b25 b24
0 0: No transfer
Values other than 0 0: Transfer on underflow (during
down-counting) or on overflow (during up-counting).
b26
ADTDA
GTADTRA Double Buffer Operation
0: Single buffer operation
(GTADTBRA → GTADTRA)
1: Double buffer operation
(GTADTDBRA → GTADTBRA → GTADTDRA).
R/W
b27
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b29, b28
ADTTB[1:0]
GTADTRB Buffer Transfer Timing
Select
Triangle waves
R/W
b29 b28
0 0: No transfer
0 1: Transfer at crest
1 0: Transfer at trough
1 1: Transfer at both crest and trough.
Saw waves
b29 b28
0 0: No transfer
Values other than 0 0: Transfer on underflow (in downcounting) or on overflow (in up-counting).
b30
ADTDB
GTADTRB Double Buffer Operation
0: Single buffer operation
(GTADTBRB → GTADTRB)
1: Double buffer operation
(GTADTDBRB → GTADTBRB → GTADTDRB).
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
The GTBER register provides settings for the buffer operation and must be set while the GTCNT operation is stopped.
BD[0] bit (GTCCR Buffer Operation Disable)
The BD[0] bit disables buffer operation using GTCCRA, GTCCRC, and GTCCRD combined and the buffer operation
using GTCCRB, GTCCRE, and GTCCRF combined.
When GTDTCR.TDE is 1 and when BD [0] is set to 0, GTCCRB does not perform buffer operation and the GTCCRB
register is automatically set to a compare match value for a negative-phase waveform with dead time.
BD[1] bit (GTPR Buffer Operation Disable)
The BD[1] bit disables buffer operation using GTPR, GTPBR, and GTPDBR combined.
BD[2] bit (GTADTR Buffer Operation Disable)
The BD[2] bit disables buffer operation using GTADTRA, GTADTBRA, and GTADTDBRA combined and buffer
operation using GTADTRB, GTADTBRB, and GTADTDBRB combined. In event count operation, this bit is not
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23. General PWM Timer (GPT)
available and the GTADTR buffer operation is not performed. Only GPT32EH and GPT32E have this bit. GPT32 does
not have this bit.
BD[3] bit (GTDV Buffer Operation Disable)
The BD[3] bit disables buffer operation using GTDVU and GTDBU combined and buffer operation using GTDVD and
GTDBD combined.
When the GTDTCR.TDFER bit is set to 1, even if BD[3] is set to 0, buffer operation is not performed and the GTDVD
value is set as a value of GTDVU automatically. In event count operation, this bit is not available and the GTDV buffer
operation is not performed. Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
CCRA[1:0] bits (GTCCRA Buffer Operation)
The CCRA[1:0] bits set buffer operation using GTCCRA, GTCCRC, and GTCCRD combined. When buffer operation is
restricted by the operating mode set in GTCR, the GTCR setting is given priority.*1
CCRB[1:0] bits (GTCCRB Buffer Operation)
The CCRB[1:0] bits set buffer operation using GTCCRB, GTCCRE, and GTCCRF combined. When buffer operation is
restricted by the operating mode set in GTCR, the GTCR setting is given priority.*1
PR[1:0] bits (GTPR Buffer Operation)
The PR[1:0] bits set buffer operation using GTPR, GTPBR, and GTPDBR combined. GPT32 does not have the PR[1]
bit. Only single buffer operation setting by PR[0] bit is available for GPT32.
CCRSWT bit (GTCCRA and GTCCRB Forcible Buffer Operation)
Writing 1 to the CCRSWT bit forces a buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0
after 1 is written. This bit is read as 0 and is only valid when counting is stopped with a specified compare match
operation.
ADTTA[1:0] bits (GTADTRA Buffer Transfer Timing Select)
The ADTTA[1:0] bits set the transfer timing for buffer operation of GTADTRA, GTADTBRA, and GTADTDBRA.
These bits are not available in event count operation. Only GPT32EH and GPT32E have these bits. GPT32 does not have
these bits.
ADTDA bit (GTADTRA Double Buffer Operation)
The ADTDA bit sets buffer operation using GTADTRA, GTADTBRA, and GTADTDBRA combined. This bit is not
available in event count operation. Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
ADTTB[1:0] bits (GTADTRB Buffer Transfer Timing Select)
The ADTTB[1:0] bits set the transfer timing for buffer operation of GTADTRB, GTADTBRB, and GTADTDBRB.
These bits are not available in event count operation. Only GPT32EH and GPT32E have these bits. GPT32 does not have
these bits.
ADTDB bit (GTADTRB Double Buffer Operation)
The ADTDB bit sets buffer operation using GTADTRB, GTADTBRB, and GTADTDBRB combined. This bit is not
available in event count operation. Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
Note 1. The buffer operation mode is fixed in saw-wave one-shot pulse mode or triangle-wave PWM mode 3 (64-bit
transfer at trough).
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23.2.18
23. General PWM Timer (GPT)
General PWM Timer Interrupt and A/D Converter Start Request Skipping
Setting Register (GTITC)
Address(es): GPT32EHm.GTITC 4007 8044h + 0100h × m (m = 0 to 3)
GPT32Em.GTITC 4007 8044h + 0100h × m (m = 4 to 7)
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
ADTBL
—
ADTAL
—
ITLF
ITLE
ITLD
ITLC
ITLB
ITLA
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
IVTT[2:0]
0
0
IVTC[1:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ITLA
GTCCRA Compare Match/Input
Capture Interrupt Link
0: GPTn_OVF/GPTn_UDF interrupt skipping function is
not linked
1: GPTn_OVF/GPTn_UDF interrupt skipping function is
linked
R/W
b1
ITLB
GTCCRB Compare Match/Input
Capture Interrupt Link
0: GPTn_OVF/GPTn_UDF interrupt skipping function is
not linked
1: GPTn_OVF/GPTn_UDF interrupt skipping function is
linked.
R/W
b2
ITLC
GTCCRC Compare Match Interrupt
Link
0: GPTn_OVF/GPTn_UDF interrupt skipping function is
not linked
1: GPTn_OVF/GPTn_UDF interrupt skipping function is
linked.
R/W
b3
ITLD
GTCCRD Compare Match Interrupt
Link
0: GPTn_OVF/GPTn_UDF interrupt skipping function is
not linked
1: GPTn_OVF/GPTn_UDF interrupt skipping function is
linked.
R/W
b4
ITLE
GTCCRE Compare Match Interrupt
Link
0: GPTn_OVF/GPTn_UDF interrupt skipping function is
not linked
1: GPTn_OVF/GPTn_UDF interrupt skipping function is
linked.
R/W
b5
ITLF
GTCCRF Compare Match Interrupt
Link
0: GPTn_OVF/GPTn_UDF interrupt skipping function is
not linked
1: GPTn_OVF/GPTn_UDF interrupt skipping function is
linked.
R/W
b7, b6
IVTC[1:0]
GPTn_OVF/GPTn_UDF Interrupt
Skipping Function Select
b7 b6
R/W
b10 to b8
IVTT[2:0]
GPTn_OVF/GPTn_UDF Interrupt
Skipping Count Select
b10
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
0 0: Do not perform skipping
0 1: Count and skip both overflow and underflow for saw
waves and crest for triangle waves
1 0: Count and skip both overflow and underflow for saw
waves and trough for triangle waves
1 1: Count and skip both overflow and underflow for saw
waves and both crest and trough for triangle
waves.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
R/W
b8
0: No skipping
1: Skipping count of 1
0: Skipping count of 2
1: Skipping count of 3
0: Skipping count of 4
1: Skipping count of 5
0: Skipping count of 6
1: Skipping count of 7.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b12
ADTAL
GTADTRA A/D Converter Start
Request Link
0: GPTn_OVF/GPTn_UDF interrupt skipping function is
not linked
1: GPTn_OVF/GPTn_UDF interrupt skipping function is
linked.
R/W
b13
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b14
ADTBL
GTADTRB A/D Converter Start
Request Link
0: GPTn_OVF/GPTn_UDF interrupt skipping function is
not linked
1: GPTn_OVF/GPTn_UDF interrupt skipping function is
linked.
R/W
b31 to b15
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The GTITC register sets the skipping function for the GTCNT counter overflow (GTPR compare match) interrupt
(GPTn_OVF) and underflow interrupt (GPTn_UDF). It also specifies whether to link other interrupts and A/D converter
start requests with the GPTn_OVF/GPTn_UDF interrupt skipping function. The output disable request to POEG cannot
be linked with the GPTn_OVF/GPTn_UDF interrupt skipping function. This register is not available in event count
operation. Only GPT32EH and GPT32E have this register. GPT32 does not have this register and it is read as 0.
ITLA bit (GTCCRA Compare Match/Input Capture Interrupt Link)
The ITLA bit specifies whether to link the GTCCRA compare match/input capture interrupt (GTCIA) with the
GPTn_OVF/GPTn_UDF interrupt skipping function.
ITLB bit (GTCCRB Compare Match/Input Capture Interrupt Link)
The ITLB bit specifies whether to link the GTCCRB compare match/input capture interrupt (GTCIB) with the
GPTn_OVF/GPTn_UDF interrupt skipping function.
ITLC bit (GTCCRC Compare Match Interrupt Link)
The ITLC bit specifies whether to link the GTCCRC compare match interrupt (GTCIC) with the
GPTn_OVF/GPTn_UDF interrupt skipping function.
ITLD bit (GTCCRD Compare Match Interrupt Link)
The ITLD bit specifies whether to link the GTCCRD compare match interrupt (GTCID) with the
GPTn_OVF/GPTn_UDF interrupt skipping function.
ITLE bit (GTCCRE Compare Match Interrupt Link)
The ITLE bit specifies whether to link the GTCCRE compare match interrupt (GTCIE) with the
GPTn_OVF/GPTn_UDF interrupt skipping function.
ITLF bit (GTCCRF Compare Match Interrupt Link)
The ITLF bit specifies whether to link the GTCCRF compare match interrupt (GTCIF) with the GPTn_OVF/GPTn_UDF
interrupt skipping function.
IVTC[1:0] bits (GPTn_OVF/GPTn_UDF Interrupt Skipping Function Select)
The IVTC[1:0] bits set the skipping function for the GTPR compare match (GTCNT overflow) interrupt (GPTn_OVF)
and GTCNT counter underflow interrupt (GPTn_UDF).
IVTT[2:0] bits (GPTn_OVF/GPTn_UDF Interrupt Skipping Count Select)
The IVTT[2:0] bits set the skipping count for the GTPR compare match (GTCNT overflow) interrupt (GPTn_OVF) and
GTCNT counter underflow interrupt (GPTn_UDF). When modifying the IVTT[2:0] bits, first set the IVTC[1:0] bits to
00b.
ADTAL bit (GTADTRA A/D Converter Start Request Link)
The ADTAL bit specifies whether to link the GTADTRA A/D converter start request with GPTn_OVF/GPTn_UDF
interrupt skipping function.
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23. General PWM Timer (GPT)
ADTBL bit (GTADTRB A/D Converter Start Request Link)
The ADTBL bit specifies whether to link the GTADTRB A/D converter start request with GPTn_OVF/GPTn_UDF
interrupt skipping function.
23.2.19
General PWM Timer Counter (GTCNT)
Address(es): GPT32EHm.GTCNT 4007 8048h + 0100h × m (m = 0 to 3)
GPT32Em.GTCNT 4007 8048h + 0100h × m (m = 4 to 7)
GPT32m.GTCNT 4007 8048h + 0100h × m (m = 8 to 13)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GTCNT is a 32-bit read/write counter and can only be written to after counting stops. GTCNT must be accessed in 32-bit
units. Access in 8-bit/16-bit units is prohibited. GTCNT must be set within the range of 0 ≤ GTCNT ≤ GTPR.
23.2.20
General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F)
Address(es): GPT32EHm.GTCCRA 4007 804Ch + 0100h × m (m = 0 to 3)
GPT32Em.GTCCRA 4007 804Ch + 0100h × m (m = 4 to 7)
GPT32m.GTCCRA 4007 804Ch + 0100h × m (m = 8 to 13)
GPT32EHm.GTCCRB 4007 8050h + 0100h × m (m = 0 to 3)
GPT32Em.GTCCRB 4007 8050h + 0100h × m (m = 4 to 7)
GPT32m.GTCCRB 4007 8050h + 0100h × m (m = 8 to 13)
GPT32EHm.GTCCRC 4007 8054h + 0100h × m (m = 0 to 3)
GPT32Em.GTCCRC 4007 8054h + 0100h × m (m = 4 to 7)
GPT32m.GTCCRC 4007 8054h + 0100h × m (m = 8 to 13)
GPT32EHm.GTCCRE 4007 8058h + 0100h × m (m = 0 to 3)
GPT32Em.GTCCRE 4007 8058h + 0100h × m (m = 4 to 7)
GPT32m.GTCCRE 4007 8058h + 0100h × m (m = 8 to 13)
GPT32EHm.GTCCRD 4007 805Ch + 0100h × m (m = 0 to 3)
GPT32Em.GTCCRD 4007 805Ch + 0100h × m (m = 4 to 7)
GPT32EHm.GTCCRF 4007 8060h + 0100h × m (m = 0 to 3)
GPT32Em.GTCCRF 4007 8060h + 0100h × m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GTCCRn registers are read/write registers.
GTCCRA and GTCCRB are registers used for both output compare and input capture.
GTCCRC and GTCCRE are compare match registers that can also function as buffer registers for GTCCRA and
GTCCRB.
GTCCRD and GTCCRF are compare match registers that can also function as buffer registers for GTCCRC and
GTCCRE (double-buffer registers for GTCCRA and GTCCRB).
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23.2.21
23. General PWM Timer (GPT)
General PWM Timer Cycle Setting Register (GTPR)
Address(es): GPT32EHm.GTPR 4007 8064h + 0100h × m (m = 0 to 3)
GPT32Em.GTPR 4007 8064h + 0100h × m (m = 4 to 7)
GPT32m.GTPR 4007 8064h + 0100h × m (m = 8 to 13)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GTPR is a read/write register that sets the maximum count value of GTCNT. For saw waves, the value of (GTPR + 1) is
the cycle. For triangle waves, the value of (GTPR value 2) is the cycle.
23.2.22
General PWM Timer Cycle Setting Buffer Register (GTPBR)
Address(es): GPT32EHm.GTPBR 4007 8068h + 0100h × m (m = 0 to 3)
GPT32Em.GTPBR 4007 8068h + 0100h × m (m = 4 to 7)
GPT32m.GTPBR 4007 8068h + 0100h × m (m = 8 to 13)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GTPBR is a read/write register that functions as a buffer register for GTPR.
23.2.23
General PWM Timer Cycle Setting Double-Buffer Register (GTPDBR)
Address(es): GPT32EHm.GTPDBR 4007 806Ch + 0100h × m (m = 0 to 3)
GPT32Em.GTPDBR 4007 806Ch + 0100h × m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GTPDBR is a 32-bit read/write register that functions as a buffer register for GTPBR (double-buffer register for GTPR).
Only GPT32EH and GPT32E have this register. GPT32 does not have this register. This register is read with the value
after reset.
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23.2.24
23. General PWM Timer (GPT)
A/D Converter Start Request Timing Register n (GTADTRn) (n = A, B)
Address(es): GPT32EHm.GTADTRA 4007 8070h + 0100h × m (m = 0 to 3)
GPT32Em.GTADTRA 4007 8070h + 0100h × m (m = 4 to 7)
GPT32EHm.GTADTRB 4007 807Ch + 0100h × m (m = 0 to 3)
GPT32Em.GTADTRB 4007 807Ch + 0100h × m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The GTADTRn registers are 32-bit read/write registers that set the timing of A/D converter start request generation.
When the GTADTRn value matches the GTCNT counter value, an A/D converter start request is generated. GTADTRn
must be accessed in 32-bit units. Access in 8-bit/16-bit units is prohibited. Only GPT32EH and GPT32E have this
register. GPT32 does not have this register. This register is read with the value after reset.
23.2.25
A/D Converter Start Request Timing Buffer Register n (GTADTBRn)
(n = A, B)
Address(es): GPT32EHm.GTADTBRA 4007 8074h + 0100h × m (m = 0 to 3)
GPT32Em.GTADTBRA 4007 8074h + 0100h × m (m = 4 to 7)
GPT32EHm.GTADTBRB 4007 8080h + 0100h × m (m = 0 to 3)
GPT32Em.GTADTBRB 4007 8080h + 0100h × m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The GTADTBRn registers are 32-bit read/write registers that function as buffer registers for GTADTRn. GTADTBRn
must be accessed in 32-bit units. Access in 8-bit/16-bit units is prohibited. Only GPT32EH and GPT32E have this
register. GPT32 does not have this register. This register is read with the value after reset.
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23.2.26
23. General PWM Timer (GPT)
A/D Converter Start Request Timing Double-Buffer Register n (GTADTDBRn)
(n = A, B)
Address(es): GPT32EHm.GTADTDBRA 4007 8078h + 0100h × m (m = 0 to 3)
GPT32Em.GTADTDBRA 4007 8078h + 0100h × m (m = 4 to 7)
GPT32EHm.GTADTDBRB 4007 8084h + 0100h × m (m = 0 to 3)
GPT32Em.GTADTDBRB 4007 8084h + 0100h × m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The GTADTDBRn registers are 32-bit read/write registers that function as buffer registers for GTADTBRn (doublebuffer registers for GTADTR). GTADTDBRn must be accessed in 32-bit units. Access in 8-bit/16-bit units is prohibited.
Only GPT32EH and GPT32E have this register. GPT32 does not have this register. This register is read with the value
after reset.
23.2.27
General PWM Timer Dead Time Control Register (GTDTCR)
Address(es): GPT32EHm.GTDTCR 4007 8088h + 0100h × m (m = 0 to 3)
GPT32Em.GTDTCR 4007 8088h + 0100h × m (m = 4 to 7)
GPT32m.GTDTCR 4007 8088h + 0100h × m (m = 8 to 13)
GPT32EH, GPT32E
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
TDFER
—
—
—
—
—
TDE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TDE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TDBDE TDBUE
GPT32
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
TDE
Negative-Phase Waveform Setting
0: GTCCRB is set without using GTDVU and GTDVD
1: GTDVU and GTDVD set the compare match value for
negative-phase waveform with automatic dead time in
GTCCRB.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
TDBUE
GTDVU Buffer Operation Enable
0: GTDVU buffer operation disabled
1: GTDVU buffer operation enabled.
R/W
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b5
TDBDE
GTDVD Buffer Operation Enable
0: GTDVD buffer operation disabled
1: GTDVD buffer operation enabled.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
TDFER
GTDVD Setting
0: GTDVU and GTDVD are set separately
1: The value written to GTDVU to GTDVD is automatically
set.
R/W
b31 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The GTDTCR register enables automatic setting of a compare match value for negative-phase waveform with dead time.
GPT32EH, GPT32E and GPT32 have dead time control function. GPT32 does not have the dead time buffer function
and only GTDVU register is used for setting dead time value.
TDE bit (Negative-Phase Waveform Setting)
The TDE bit specifies whether to use GTDVU and GTDVD. When GTDVU and GTDVD are used, the compare match
value for a negative-phase waveform with dead time obtained by the compare match value of a positive-phase waveform
(GTCCRA) and the dead time value (GTDVU and GTDVD), is automatically set in GTCCRB. The TDE bit setting is
ignored in saw-wave PWM mode, and automatic setting does not take place.
The GTCCRB value is automatically set and has the following upper and lower limit values. If the obtained GTCCRB
value is not within the upper or lower limit, the following limit value is set in GTCCRB and the GTST.DTEF flag is set
to 1. However, in triangle waves, when the obtained GTCCRB value exceeds the upper limit value, the GTST.DTEF flag
is set to 0.
Triangle waves:
Upper limit value: GTPR 1
Lower limit value: 1 in up-counting, 0 in down-counting
Saw-wave one-shot pulse mode:
Upper limit value: GTPR
Lower limit value: 0.
TDBUE bit (GTDVU Buffer Operation Enable)
The TDBUE bit enables buffer operation with GTDVU and GTDBU combined. The buffer transfer timing is the trough
for triangle waves, and an overflow or underflow for saw waves.
Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
TDBDE bit (GTDVD Buffer Operation Enable)
The TDBDE bit enables buffer operation with GTDVD and GTDBD combined. The buffer transfer timing is the trough
for triangle waves, and an overflow or underflow for saw waves. When this bit and the TDFER bit are set to 1
simultaneously, the TDFER bit setting is given priority.
Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
TDFER bit (GTDVD Setting)
The TDFER bit selects whether the value written to GTDVU is also set to GTDVD automatically.
Only GPT32EH and GPT32E have this bit. GPT32 does not have this bit.
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23.2.28
23. General PWM Timer (GPT)
General PWM Timer Dead Time Value Register n (GTDVn) (n = U, D)
Address(es): GPT32EHm.GTDVU 4007 808Ch + 0100h x m (m = 0 to 3)
GPT32Em.GTDVU 4007 808Ch + 0100h x m (m = 4 to 7)
GPT32m.GTDVU 4007 808Ch + 0100h x m (m = 8 to 13)
GPT32EHm.GTDVD 4007 8090h + 0100h x m (m = 0 to 3)
GPT32Em.GTDVD 4007 8090h + 0100h x m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GTDVn is a 32-bit read/write register that sets the dead time for generating PWM waveforms with dead time. GTDVU is
used for up-counting and GTDVD is used for down-counting.
Setting a GTDVn value greater than or equal to GTPR is prohibited. Setting a dead time value that exceeds the cycle is
prohibited. The compare match value set by the automatic dead time setting function for a negative waveform can be
confirmed by reading from GTCCRB.
When GTDVn is used, writing to GTCCRB is not allowed. When this register is set to 0, waveforms without dead time
are output. GTDVn must be accessed in 32-bit units. Access in 8-bit/16-bit units is prohibited. The way to rewrite
GTDVn differs by GPT channel number.
GPT32EH0 to GPT32EH3 and GPT32E4 to GPT32E7
When GTDVn buffer operation is enabled, GTDBn can be written at anytime. GTDBn is transferred to GTDVn at the
cycle end. When GTDVn buffer operation is disabled, stop the GPT using the CST bit in the GTCR register before
changing GTDVn to a new value.
GPT328 to GPT3213
While the GPT is running, changing the GTDVU values is prohibited. To change GTDVU to a new value, stop the GPT
with the CST bit in the GTCR register.
Only GPT32EH and GPT32E have the GTDVD register. GPT32 does not have the GTDVD register. This register is read
with the value after reset.
23.2.29
General PWM Timer Dead Time Buffer Register n (GTDBn) (n = U, D)
Address(es): GPT32EHm.GTDBU 4007 8094h + 0100h × m (m = 0 to 3)
GPT32Em.GTDBU 4007 8094h + 0100h × m (m = 4 to 7)
GPT32EHm.GTDBD 4007 8098h + 0100h × m (m = 0 to 3)
GPT32Em.GTDBD 4007 8098h + 0100h × m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GTDBn is a 32-bit read/write register that functions as a buffer register for GTDVn.
Only GPT32EH and GPT32E have this register. GPT32 does not have this register. This register is read with the value
after reset.
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23.2.30
23. General PWM Timer (GPT)
General PWM Timer Output Protection Function Status Register (GTSOS)
Address(es): GPT32EHm.GTSOS 4007 809Ch + 0100h x m (m = 0 to 3)
GPT32Em.GTSOS 4007 809Ch + 0100h × m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SOS[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
SOS[1:0]
Output Protection Function Status
b1 b0
R
b31 to b2
—
Reserved
These bits are read as 0. Writing to these bits is ignored.
R
0 0: Normal operation
0 1: Protected state (set GTCCRA = 0 during transfer at
trough or crest)
1 0: Protected state (set GTCCRA ≥ GTPR during transfer
at trough)
1 1: Protected state (set GTCCRA ≥ GTPR during transfer
at crest).
GTSOS is a status register that indicates the status of the output protection function. The output protection function is
enabled only when the dead time is automatically set (GTDTCR.TDE bit = 1) in triangle-wave mode.
Only GPT32EH and GPT32E have this register. GPT32 does not have this register. This register is read as 0000_0000h.
SOS[1:0] bits (Output Protection Function Status)
The SOS[1:0] bits indicate the status of the output protection function in triangle-wave PWM mode.
23.2.31
General PWM Timer Output Protection Function Temporary Release Register
(GTSOTR)
Address(es): GPT32EHm.GTSOTR 4007 80A0h + 0100h x m (m = 0 to 3)
GPT32Em.GTSOTR 4007 80A0h + 0100h × m (m = 4 to 7)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SOTR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SOTR
Output Protection Function
Temporary Release
0: Protected state is not released
1: Protected state is released.
R/W
b31 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The GTSOTR register temporarily releases the protected state of GTIOCB pin output when output protection is set. The
protected state can be released only when GTSOS.SOS[1:0] bits = 10b (protected state in which GTCCRA ≥ GTPR has
occurred during transfer at trough). The protected state cannot be released in any other case.
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23. General PWM Timer (GPT)
Only GPT32EH and GPT32E have this register. GPT32 does not have this register. This register is read as 0000_0000h.
SOTR bit (Output Protection Function Temporary Release)
The SOTR bit specifies whether to temporarily release the protected state of GTIOCB pin output in an output protected
state. When the SOTR bit is set to 1, the output protection function is canceled from the first trough. When the SOTR bit
is set to 0, output protection resumes from the first trough.
23.2.32
Output Phase Switching Control Register (OPSCR)
Address(es): GPT_OPS.OPSCR 4007 8FF0h
b31
b30
NFCS[1:0]
b29
b28
b27
b26
NFEN
—
—
GODF
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
GRP[1:0]
—
—
ALIGN
—
INV
N
P
FB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
EN
—
W
V
U
—
WF
VF
UF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
UF
Input Phase Soft Setting
R/W
b1
VF
These bits set the input phase from the software settings.
Setting these bits is valid when the OPSCR.FB bit = 1.
R/W
R/W
b2
WF
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
U
Input U-Phase Monitor
b5
V
Input V-Phase Monitor
These bits monitor the state of the input phase:
OPSCR.FB = 0: External input monitoring by PCLKD
OPSCR.FB = 1: Software settings (UF/VF/WF).
b6
W
Input W-Phase Monitor
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b8
EN
Enable-Phase Output Control
0: Do not output (Hi-Z on external pin)
1: Output.*1
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
FB
External Feedback Signal Enable
This bit selects the input phase from the software settings or
external input:
0: Select the external input
1: Select the software settings (OPSCR.UF, VF, WF).
R/W
b17
P
Positive-Phase Output (P) Control
0: Output level signal
1: Output level signal (PWM of GPT32EH0).
R/W
b18
N
Negative-Phase Output (N) Control
0: Output level signal
1: Output PWM signal (PWM of GPT32EH0).
R/W
b19
INV
Invert-Phase Output Control
0: Output positive logic (active-high)
1: Output negative logic (active-low).
R/W
b20
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b21
ALIGN
Input Phase Alignment
0: Input phase aligned to PCLKD
1: Input phase aligned to PWM.
R/W
b23, b22
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25, b24
GRP[1:0]
Output Disabled Source Selection
b25 b24
R/W
b26
GODF
Group Output Disable Function
0: This bit function is ignored
1: Group disable clears the OPSCR.EN bit.*1
R/W
b28, b27
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
R
R
R
0
0
1
1
0: Select Group A output disable source
1: Select Group B output disable source
0: Select Group C output disable source
1: Select Group D output disable source.
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23. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b29
NFEN
External Input Noise Filter Enable
0: Do not use a noise filter on the external input
1: Use a noise filter on the external input.
R/W
b31, b30
NFCS[1:0]
External Input Noise Filter Clock
Selection
Noise filter sampling clock setting of the external input:
R/W
Note 1.
b31 b30
0
0
1
1
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
When OPSCR.GODF = 1 and the signal value selected by the OPSCR.GRP[1:0] bit is high, the OPSCR.EN bit is set to 0.
The OPSCR register sets the output of the signal waveform required for brushless DC motor control.
UF, VF, WF bits (Input Phase Soft Setting)
The UF, VF, and WF bits set the input phase from the software settings. When OPSCR.FB bit is 1, these bits are valid.
The set value of the UF/VF/WF bits take the place of the U/V/W external inputs.
U, V, W bits (Input Phase Monitor)
When OPSCR.FB bit is 0, external inputs that are synchronized by PCLKD are monitored by these bits. When
OPSCR.FB bit is 1, the OPSCR.U, OPSCR.V, and OPSCR.W bits can read the OPSCR.UF, OPSCR.VF, and
OPSCR.WF bits.
EN bit (Enable-Phase Output Control)
The EN bit controls the output enable signal output phase (positive phase/reverse phase).
When OPSCR.EN bit = 1, the signal waveform is output.
When OPSCR.EN bit = 0, first set OPSCR.FB, OPSCR.UF/VF/WF (software setting is selected), OPSCR.P/N,
OPSCR.INV, OPSCR.RV, OPSCR.ALIGN, OPSCR.GRP, OPSCR.GODF, OPSCR.NFEN, and OPSCR.NFCS. Then, set
the EN bit to 1. Also, when OPSCR.GODF = 1 and the signal value selected by the OPSCR.GRP bit is high, the
OPSCR.EN bit is set to 0.
FB bit (External Feedback Signal Enable)
The FB bit selects the input phase from the software settings (OPSCR.UF, VF, WF) and external input such as a Hall
element.
P bit (Positive-Phase Output (P) Control)
The P bit selects the level signal output or PWM signal output for the positive-phase output (GTOUUP pin, GTOVUP
pin, GTOWUP pin).
N bit (Negative-Phase Output (N) Control)
The N bit selects the level signal output or PWM signal output for the negative-phase output (GTOULO pin, GTOVLO
pin, GTOWLO pin).
INV bit (Invert-Phase Output Control)
The INV bit selects either positive logic (active-high) output or negative logic (active-low) output for the output phase.
ALIGN bit (Input Phase Alignment)
The ALIGN bit selects the PCLKD or PWM for the sampling of the input phase (input phase is specified in the
OPSCR.FB bit).
When OPSCR.ALIGN bit = 0, input phase is aligned to PCLKD.
Note:
Note:
When PWM output is selected (OPSCR.P/N = 1) and the PCLKD input phase is aligned, the PWM pulse might be
short-pulsed.
When OPSCR.ALIGN bit = 1, input phase is aligned with PWM output.
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23. General PWM Timer (GPT)
GRP[1:0] bits (Output Disabled Source Selection)
The GRP[1:0] bits select the output disable source (A to D).
GODF bit (Group Output Disable Function)
When the GODF bit = 1 and the signal value selected by the OPSCR.GRP bit is high, the OPSCR.EN bit is set to 0.
When the GODF bit = 0, the bit is ignored.
NFEN bit (External Input Noise Filter Enable)
The NFEN bit selects the noise filter for external input.
When OPSCR.NFEN = 0, a noise filter is not used for the external input.
Note:
When this bit is switched because of an unintentional internal edge, set the OPSCR.EN bit to 0.
NFCS[1:0] bits (External Input Noise Filter Clock Selection)
The NFCS[1:0] bits select the clock for the external input noise filter. When the OPSCR.NFEN bit = 1, noise filter
sampling clock setting for external input is enabled.
1. Set the NFCS[1:0].
2. Wait for 2 cycles.
3. Set the OPSCR.EN bit to 1.
23.3
Operation
23.3.1
Basic Operation
Each channel has a 32-bit timer that performs a periodic count operation using the count clock and hardware sources.
The count function provides both up-counting and down-counting. The GTPR controls the count cycle. When the
GTCNT counter value matches the value in GTCCRA or GTCCRB, the output from the associated pin GTIOCA or
GTIOCB can be changed. GTCCRA or GTCCRB can be used as an input capture register with hardware resources.
GTCCRC and GTCCRD can function as buffer registers for GTCCRA. GTCCRE and GTCCRF can function as buffer
registers for GTCCRB.
23.3.1.1
(1)
Counter operation
Counter start and stop
The counter for each channel starts the count operation when GTCR.CST is set to 1. The GTCR.CST bit value is
changed by the following sources:
Writing to GTCR register
Writing 1 to the bit in GTSTR associated with the GPT channel number when the GTSSR.CSTRT bit is set to 1
Writing 1 to the bit in GTSTP associated with the GPT channel number when the GTPSR.CSTOP bit is set to 1
The hardware source selected in the GTSSR register
The hardware source selected in the GTPSR register.
(2)
Periodic count operation in up-counting by count clock
The GTCNT counter in each channel starts up-counting when the associated GTCR.CST bit is set to 1 with the GTUPSR
and GTDNSR registers set to 0000 0000h. When the GTCNT value changes from the GTPR value to 0 (overflow), the
GTST.TCFPO flag is set to 1. When GTCNT overflows, up-counting resumes from 0000 0000h.
Figure 23.3 shows an example of a periodic count operation in up-counting.
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23. General PWM Timer (GPT)
GTCNT counter value
GPT32EH0.GTPR register
0000 0000h
GTCR.CST bit
Time
Flag is cleared by software
GTST.TCFPO flag
Figure 23.3
Example of periodic count operation in up-counting by the count clock
Figure 23.4 shows an example for setting periodic count operation in up-counting.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.3, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction with the GTUDDTYC register.
In Figure 23.3, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter. In Figure 23.3, 0000 0000h is
set.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.4
(3)
Example setting for a periodic count operation in up-counting by the count clock
Periodic count operation in down-counting by count clock
The GTCNT counter in each channel can perform down-counting by setting GTUDDTYC.UD with the GTUPSR and
GTDNSR registers set to 0000 0000h. When GTCNT changes from 0 to the GTPR value (underflow), GTST.TCFPU is
set to 1. When the GTCNT counter underflows, down-counting resumes from the GTPR value.
Figure 23.5 shows an example of periodic count operation in down-counting by the count clock.
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23. General PWM Timer (GPT)
GTCNT counter value
GTCNT counter is written by software
GTPR register
0000 0000h
GTCR.CST bit
Time
Flag is cleared by software
GTST.TCFPU flag
Figure 23.5
Example of periodic count operation in down-counting by the count clock
Figure 23.6 shows an example setting for periodic count operation in down-counting by the count clock.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.5, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction with the GTUDDTYC register.
In Figure 23.5, after 10b is set in GTUDDTYC[1:0], 00b is set in
GTUDDTYC[1:0] (down-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.5, the GTPR value is set.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.6
(4)
Example setting for periodic count operation in down-counting by count clock
Event count operation in up-counting using hardware sources
The GTCNT counter in each channel can perform up-counting using hardware sources as set in GTUPSR.
When GTUPSR is set to enable, the count clock selected in GTCR.TPCS[2:0] and the count direction selected in
GTUDDTYC.UD are ignored. If up-counting and down-counting using hardware sources occur at the same time, the
GTCNT counter value does not change. The overflow behavior for up-counting using hardware sources is the same as
for up-counting by the count clock.
When GTCR.CST bit is set to 1 to count up using hardware sources, the count operation is enabled. When GTCR.CST is
set to 1, the counter cannot count up for 1 clock cycle as specified in GTCR.TPCS[2:0] because the count operation is
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23. General PWM Timer (GPT)
synchronized by the count clock selected in GTCR.TPCS[2:0]. Set GTCR.TPCS[2:0] to 000b to count up with a 1
PCLKD delay after GTCR.CST is set to 1.
Figure 23.7 shows an example of a periodic count operation in up-counting by a hardware source (rising edge of the
GTETRGA pin).
PCLKD
GTETRGA
N
GTCNT
Figure 23.7
N+1
Example of periodic count operation in up-counting using hardware sources
Figure 23.8 shows an example setting for periodic count operation in up-counting by a hardware source.
Set count source
Select the counting-up source with the GTUPSR register.
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.8
(5)
Example setting for an event count operation in up-counting using hardware sources
Event count operation in down-counting using hardware sources
The GTCNT counter in each channel can perform down-counting using hardware sources set in the GTDNSR register.
When GTDNSR is set to enable, the count clock selected in GTCR.TPCS[2:0] and the count direction selected in
GTUDDTYC.UD are ignored. If up-counting and down-counting using hardware sources occur at the same time,
GTCNT counter value does not change. The underflow behavior for down-counting using hardware sources is the same
as for down-counting by the count clock.
When GTCR.CST bit is set to 1 to count down using hardware sources, the count operation is enabled. When
GTCR.CST is set to 1, the counter cannot count down for 1 clock cycle as specified in GTCR.TPCS[2:0] because the
count operation is synchronized with the count clock selected by GTCR.TPCS[2:0]. Set GTCR.TPCS[2:0] to 000b to
count down with a 1 PCLKD delay after GTCR.CST is set to 1.
Figure 23.9 shows an example of a periodic count operation in down-counting by a hardware source (rising edge of the
GTETRGA pin).
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23. General PWM Timer (GPT)
PCLKD
GTETRGA
N+1
GTCNT
Figure 23.9
N
Example of event count operation in down-counting using hardware sources
Figure 23.10 shows an example setting for a periodic count operation in down-counting using a hardware source.
Set count source
Select the counting down source with the GTDNSR register.
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.10
(6)
Example setting for an event count operation in down-counting using hardware sources
Counter clear operation
The counter of each channel is cleared by the following sources:
Writing 0 to GTCNT register
Writing 1 to the bit in GTCLR associated with the GPT channel number when the GTCSR.CCLR bit is set to 1
The hardware source selected in GTCSR register.
Writing to the GTCNT register is prohibited during count operation. The GTCNT counter can be cleared both by writing
1 to the GTCLR and by the clear request of hardware sources, whether GTCNT is counting (GTCR.CST = 1) or not
(GTCR.CST = 0).
For saw waves selected by setting GTCR.MD[2:0] and the count direction flag showing down-counting (GTST.TUCF =
0), the GTCNT register is set to the value of the GTPR register when writing 1 to the GTCLR register or when clearing
by hardware sources is performed. When not in saw wave mode and down-counting, the GTCNT register is set to 0 when
writing 1 to the GTCLR register and when clearing by hardware sources is performed.
In event count operation when at least 1 bit in GTUPSR or GTDNSR is set to 1, after clear sources occur, both writing to
the GTCLR register and clearing by hardware sources are performed immediately, synchronized with PCLKD. If other
settings are used, clear is synchronized with the counter clock selected in GTCR.TPCS[2:0].
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23.3.1.2
23. General PWM Timer (GPT)
Waveform output by compare match
Compare match means that the GTCNT counter value matches the value of GTCCRA or GTCCRB. When a compare
match occurs, the compare match flag is generated synchronously with the count clock, including the event count. At the
same time the GPT can output low, high, or toggle output from the associated GTIOCA or GTIOCB output pin. In
addition, the GTIOCA or GTIOCB pin output can be low, high, or toggled at the cycle end, which is determined by
GTPR.
The cycle end is:
For saw waves in up-counting — when GTCNT changes from the GTPR value to 0 (overflow)
For saw waves in down-counting — when GTCNT changes from 0 to the GTPR value (underflow)
For saw waves — when the GTCNT counter is cleared
For triangle waves — when the GTCNT changes from 0 to 1 (trough).
(1)
Low output and high output
Figure 23.11 shows an example of low output and high output operation by a compare match of GTCCRA and
GTCCRB.
In this example, the GPT32EH0.GTCNT counter performs up-counting, and settings are made so that high is output from
the GTIOC0A pin by a GPT32EH0.GTCCRA compare match, and low is output from the GTOC0B pin by a
GPT32EH0.GTCCRB compare match. The pin level does not change when the specified level and pin level match.
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
GPT32EH0.GTCCRB register
Time
0000_0000h
No change
No change
GTIOC0A pin output
GTIOC0B pin output
No change
No change
[Setting examples]
GPT32EH0.GTIOR.GTIOA[4:0] bits: Initial output is low, high output at compare match, output retained at cycle end
GPT32EH0.GTIOR.GTIOB[4:0] bits: Initial output is high, low output at compare match, output retained at cycle end
Figure 23.11
Example of low output and high output operation
Figure 23.12 shows an example setting for low output and high output operation.
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.11, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.11, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.11, GTIOA[4:0] = 00010b, GTIOB[4:0] = 10001b.
*1
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
*1
Set compare match value
Set compare match values in the GTCCRA and GTCCRB registers.
Start count operation
Set GTCR.CST to 1 to start count operation.
Note 1.
Figure 23.12
(2)
When PWM delay generation circuit is used, reverse the setting order of GTIOC pin function
and enable GTIOC pin output.
Example setting for low output and high output operation
Toggled output
Figure 23.13 and Figure 23.14 show examples of toggled output operation by compare matches of GTCCRA and
GTCCRB. In Figure 23.13, the GPT32EH0.GTCNT counter performs up-counting, and settings are made so that the
GTIOC0A pin output by a GPT32EH0.GTCCRA compare match and GTIOC0B pin output by a GPT32EH0.GTCCRB
compare match are toggled.
In Figure 23.14, the GPT32EH0.GTCNT counter performs up-counting, and settings are made so that the GTIOC0A
output is toggled by a compare match of GPT32EH0.GTCCRA and the GTIOC0B output is toggled at the cycle end.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRB register
GPT32EH0.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
GTIOC0B pin output
[Setting examples]
GPT32EH0.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end
GPT32EH0.GTIOR.GTIOB[4:0] bits: Initial output is low, output toggled at compare match, output retained at cycle end
Figure 23.13
Example of toggled output operation (1)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
GTIOC0B pin output
[Setting examples]
GPT32EH0.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end
GPT32EH0.GTIOR.GTIOB[4:0] bits: Initial output is low, output retained at compare match, output toggled at cycle end
Figure 23.14
Example of toggled output operation (2)
Figure 23.15 shows an example setting for toggled output operation.
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.13 and Figure 23.14, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.13 and Figure 23.14, after 11b is set in GTUDDTYC[1:0],
01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.13, GTIOA[4:0] = 10011b, GTIOB[4:0] = 00011b.
In Figure 23.14, GTIOA[4:0] = 10011b, GTIOB[4:0] = 01100b.
*1
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
*1
Set compare match value
Set compare match values in the GTCCRA and GTCCRB registers.
Start count operation
Set GTCR.CST to 1 to start count operation.
Note 1.
When PWM delay generate circuit is used, reverse the setting order of GTIOC pin function
and enable GTIOC pin output.
Figure 23.15
Example setting for toggled output operation
23.3.1.3
Input capture function
The GTCNT counter value can be transferred to either GTCCRA or GTCCRB on detection of the hardware source that is
set in GTICASR and GTICBSR.
Figure 23.16 shows an example of the input capture function.
In this example, the GPT32EH0.GTCNT counter performs up-counting by the count clock, and settings are made so that
an input capture is performed to GTICCRA at both edges of the GTIOC0A input pin and to GTICCRB on the rising edge
of the GTIOC0B input pin.
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GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
E400h
C154h
9682h
1100h
Time
0000 0000h
GTIOC0A pin input
GTIOC0B pin input
GPT32EH0.GTCCRA register
1100h
GPT32EH0.GTCCRB register
E400h
9682h
C154h
[Setting examples]
GTICASR setting input capture at both edges
GTICBSR setting input capture at the rising edge
Figure 23.16
Example of input capture operation
Figure 23.17 shows an example setting for an input capture operation with count operation by the count clock.
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.16, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.16, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Select input capture source
Select the input capture source in GTICASR and GTICBSR.
In Figure 23.16, GTICASR = 0000_0F00h, GTICBSR = 0000 3000h.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.17
23.3.2
Example setting for input capture operation
Buffer Operation
The following buffer operations can be set with GTBER:
GTPR, GTPBR, and GTPDBR
GTCCRA, GTCCRC, and GTCCRD
GTCCRB, GTCCRE, and GTCCRF
GTADTRA, GTADTBRA, and GTADTDBRA
GTADTRB, GTADTBRB, and GTADTDBRB.
The following buffer operations can be set with GTDTCR:
GTDVU and GTDBU
GTDVU and GTDBD.
23.3.2.1
GTPR register buffer operation
GTPBR can function as a buffer register for GTPR, and GTPDBR can function as a buffer register for GTPBR (doublebuffer register for GTPR). The buffer transfer is performed at an overflow (during up-counting) or an underflow (during
down-counting) in saw-wave mode or in event count, and at a trough in triangle-wave mode.
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In saw-wave mode or in event count, the buffer transfer is performed when the following counter clear operations occur
during counting:
Clear by hardware sources (the clear source is selected in GTCSR[23:0])
Clear by software (when GTCSR.CCLR bit is 1 and GTCLRn bit is set to 1, n = channel number).
To set GTPR to function as double buffer, set GTBER.PR[1:0] to 10b or 11b. To set GTPR to not function as a buffer, set
GTBER.PR[1:0] to 00b.
Figure 23.18 to Figure 23.20 show examples of GTPR buffer operation, and Figure 23.21 shows an example setting for
GTPR buffer operation.
GTCNT counter value
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GTPBR register
Register write
bbbb
cccc
Buffer transfer
at overflow
GTPR register
Figure 23.18
aaaa
Register write
Register write
Buffer transfer
at overflow
bbbb
Buffer transfer
at overflow
cccc
Example of GTPR buffer operation with saw waves in up-counting
GTCNT counter value
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GTPBR register
aaaa
bbbb
Buffer transfer
at underflow
GTPR register
Figure 23.19
aaaa
Register write
cccc
Buffer transfer
at underflow
Buffer transfer
at underflow
bbbb
cccc
Example of GTPR buffer operation with saw waves in down-counting
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GTCNT counter value
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GTPDBR register
bbbb
cccc
Buffer transfer at trough
GTPBR register
aaaa
bbbb
Buffer transfer at trough
GTPR register
Figure 23.20
Register write
aaaa
Buffer transfer at trough
Buffer transfer at trough
cccc
Buffer transfer at trough
bbbb
Buffer transfer at trough
cccc
Example of GTPR double buffer operation with triangle waves
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Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.18 and Figure 23.19, 000b (saw-wave PWM mode) is set,
and in Figure 23.20, 100b (triangle-wave PWM mode 1) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.18, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting). In Figure 23.19, after 10b is set in
GTUDDTYC[1:0], 00b is set in GTUDDTYC[1:0] (down-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set buffer operation
Set buffer operation with GTBER.PR[1:0]. In Figure 23.18 and Figure
23.19, PR[1:0] = 01b. In Figure 23.20, PR[1:0] = 1xb.
Set buffer value
For buffer operation, set a value in 1 cycle after the current cycle in
GTPBR. For double-buffer operation, also set a value in 2 cycles after
the current cycle in GTPDBR.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set a value in 1 cycle after the current cycle in
GTPBR. For double-buffer operation, also set a value in 2 cycles after
the current cycle in GTPDBR.
Figure 23.21
Example setting for GTPR buffer operation
23.3.2.2
Buffer operation for GTCCRA and GTCCRB
GTCCRC can function as the GTCCRA buffer register and GTCCRD can function as the GTCCRC buffer register
(double-buffer register for GTCCRA). Similarly, GTCCRE can function as the GTCCRB buffer register and GTCCRF
can function as the GTCCRE buffer register (double-buffer register for GTCCRB).
To set GTCCRA or GTCCRB to function as a double buffer, set GTBER.CCRA[1:0] or GTBER.CCRB[1:0] to 10b or
11b. For single-buffer operation, set GTBER.CCRA[1:0] or GTBER.CCRB[1:0] to 01b. To set GTCCRA or GTCCRB
to not function as a buffer, set GTBER.CCRA[1:0] or GTBER.CCRB[1:0] to 00b.
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(1)
23. General PWM Timer (GPT)
When GTCCRA or GTCCRB functions as an output compare register
Buffer transfer occurs in the following situations:
Buffer transfer by overflow or underflow
Buffer transfer is performed at an overflow (during up-counting) or an underflow (during down-counting) in sawwave mode or in event count operation. In triangle-wave mode, buffer transfer is performed at a trough (trianglewave PWM mode 1) or a crest and trough (triangle-wave PWM mode 2).
Buffer transfer by counter clear
In saw-wave mode or in event count operation, during counting, buffer transfer (which is the same as an overflow
during up-counting or an underflow during down-counting) is performed by the counter clear sources the same as
shown in section 23.3.2.1, GTPR register buffer operation. In triangle-wave mode, buffer transfer is not performed
by the counter clear.
Forcible buffer transfer
When GTBER.CCRSWT bit is set to 1 while the count operation is stopped, the GTCCRA and the GTCCRB
register buffer transfer is performed forcibly in saw-wave mode, in event count operation and in triangle-wave
mode. Additionally, buffer transfer from the GTCCRD register to temporary register A and from the GTCCRF
register to temporary register B are performed in saw-wave 1 shot pulse mode or triangle-wave PWM mode 3.
Figure 23.22 to Figure 23.24 show examples of GTCCRA and GTCCRB buffer operation and Figure 23.25 shows an
example setting for GTCCRA and GTCCRB buffer operation.
GPT32EH0.GCNT counter value
GPT32EH0.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT32EH0.GTCCRC register
Register write
bbbb
Register write
cccc
Buffer transfer
at overflow
GPT32EH0.GTCCRA register
aaaa
Register write
bbbb
Buffer transfer
at overflow
Buffer transfer
at overflow
cccc
GTIOC0A pin output
Figure 23.22
Example of GTCCRA and GTCCRB buffer operation with output compare, saw waves in upcounting, high output at GTCCRA compare match, and low output at cycle end
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GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
Register write
cccc
GPT32EH0.GTCCRD register
Buffer transfer at
trough
bbbb
GPT32EH0.GTCCRC register
cccc
Buffer transfer at
trough
GPT32EH0.GTCCRA register
Buffer transfer at
trough
aaaa
Buffer transfer at
trough
bbbb
cccc
GTIOC0A pin output
Figure 23.23
Example of GTCCRA and GTCCRB double buffer operation with output compare, triangle waves,
buffer operation at trough, output toggled at GTCCRA compare match, and output retained at
cycle end
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
cccc
GPT32EH0.GTCCRF register
bbbb
Buffer transfer at
trough
GPT32EH0.GTCCRE register
aaaa
GPT32EH0.GTCCRB register
Register write
Register write
dddd
Buffer transfer at
crest
Buffer transfer at
trough
cccc
bbbb
dddd
Buffer transfer at
trough
Buffer transfer at
crest
Buffer transfer at
trough
aaaa
cccc
bbbb
Buffer transfer at
crest
Buffer transfer at
crest
dddd
GTIOC0B pin output
Figure 23.24
Example of GTCCRA and GTCCRB double buffer operation with output compare, triangle waves,
buffer operation at both troughs and crests, output toggled at GTCCRB compare match, and
output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.22, 000b (saw-wave PWM mode) is set, in Figure 23.23, 100b (triangle-wave PWM mode 1) is set, and in
Figure 23.24, 101b (triangle-wave PWM mode 2) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.22, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.22, GTIOA[4:0] = 00110b, in Figure 23.23, GTIOA[4:0] = 00011b, and in Figure 23.24, GTIOB[4:0] =
00011b.
*1
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
In Figure 23.22, CCRA = 01b, in Figure 23.23, CCRA = 1xb, and in Figure 23.24, CCRB = 1xb.
*1
Set compare match value
Set the GTIOCA pin transition in GTCCRA and GTIOCB pin transition in GTCCRB.
Set buffer value
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in 1 cycle after the current cycle (in saw-wave
mode or triangle-wave mode with buffer transfer at trough or crest) or half cycle after the current cycle (in trianglewave mode with buffer transfer at both trough and crest) in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in 2 cycles after the current cycle (in
saw-wave mode or triangle-wave mode with buffer transfer at trough or crest) or 1 cycle after the current cycle (in
triangle-wave mode with buffer transfer at both trough and crest) in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in 1 cycle after the current cycle (in
saw-wave mode or triangle-wave mode with buffer transfer at trough or crest) or half cycle after the current cycle (in
triangle-wave mode with buffer transfer at both trough and crest) in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in 2 cycles after the
current cycle (in saw-wave mode or triangle-wave mode with buffer transfer at trough or crest) or 1 cycle after the
current cycle (in triangle-wave mode with buffer transfer at both trough and crest) in GTCCRD and GTCCRF,
respectively.
Note 1.
Figure 23.25
When the PWM delay generation circuit is used, exchange the sequence of the step for Enable GTIOC pin
output and the step for Set compare-match value.
Example setting for GTCCRA and GTCCRB buffer operation with output compare
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(2)
23. General PWM Timer (GPT)
When GTCCRA or GTCCRB functions as an Input Capture Register
When an input capture is generated, the GTCNT counter value is transferred to GTCCRA and GTCCRB and the stored
GTCCRA and GTCCRB register values are transferred to the buffer registers. In input capture operation, the buffer
transfer is not performed by the counter clear.
Figure 23.26 and Figure 23.27 show examples of GTCCRA and GTCCRB buffer operation and Figure 23.28 shows an
example setting for GTCCRA and GTCCRB buffer operation.
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
GTIOC0A pin input
GPT32EH0.GTCCRA register
aaaa
Buffer transfer at input
capture
Buffer transfer at input
capture
aaaa
GPT32EH0.GTCCRC register
Figure 23.26
bbbb
cccc
Buffer transfer at
input capture
bbbb
Example of GTCCRA and GTCCRB buffer operation with input capture at both edges of GTIOC0A
input, saw waves in up-counting, and GTCNT counter cleared at both edges of GTIOC0A input
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
GTIOC0B pin input
GPT32EH0.GTCCRB register
aaaa
Buffer transfer at input
capture
GPT32EH0.GTCCRE register
Figure 23.27
Buffer transfer at input
capture
aaaa
Buffer transfer at input
capture
GPT32EH0.GTCCRF register
bbbb
Buffer transfer at input
capture
cccc
Buffer transfer at
input capture
bbbb
Buffer transfer at
input capture
aaaa
Example of GTCCRA and GTCCRB double buffer operation with input capture at both edges of
GTIOC0B input, saw waves in up-counting, and GTCNT counter cleared at both edges of
GTIOC0B input
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0] and count clear source with GTCSR.
In Figure 23.26, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 0F00h, and in Figure
23.27, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 0F00h.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.26, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Select input capture source
Select input capture source in the GTICASR and GTICBSR registers.
In Figure 23.26, GTICASR = 0000 0F00h, and in Figure 23.27, GTICBSR = 0000 F000h.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
In Figure 23.26, CCRA = 01b, and in Figure 23.27, CCRB = 1xb.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 23.28
Example setting for GTCCRA and GTCCRB buffer operation with input capture
23.3.2.3
Buffer operation for GTADTRA and GTADTRB
GTADTBRA can function as the GTADTRA buffer register and GTADTDBRA can function as the GTADTBRA buffer
register (double-buffer register for GTADTRA). Similarly, GTADTBRB can function as the GTADTRB buffer register
and GTADTDBRB can function as the GTADTBRB buffer register (double-buffer register for GTADTRB).
To set GTADTRA or GTADTRB to function as a double buffer, set GTBER.ADTDA or GTBER.ADTDB to 1. For
single buffer operation, set GTBER.ADTDA or GTBER.ADTDB to 0. To set GTADTRA or GTADTRB to not function
as a buffer, set GTBER.ADTTA[1:0] or GTBER.ADTTB[1:0] to 00b.
The buffer transfer timing can be set with the GTBER.ADTTA[1:0] bits. For saw waves, overflows (during up-counting)
or underflows (during down-counting) can be selected. For triangle waves, crests are selected when
GTBER.ADTTA[1:0] = 01b, troughs are selected when GTBER.ADTTA[1:0] = 10b, and both crests and troughs are
selected when GTBER.ADTTA[1:0] = 11b.
Figure 23.29 to Figure 23.31 show examples of GTADTRA and GTADTRB buffer operation and Figure 23.32 shows an
example setting for GTDTRA and GTADTRB buffer operation.
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23. General PWM Timer (GPT)
GTCNT counter value
GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GTADTBRA register
bbbb
Register write
cccc
Buffer transfer
at overflow
GTADTRA register
Register write
aaaa
Buffer transfer
at overflow
bbbb
Buffer transfer
at overflow
cccc
A/D converter
request A interrupt
Figure 23.29
Example of GTADTRA and GTADTRB buffer operation with saw waves in up-counting and A/D
converter start request interrupt generated by up-counting
GTCNT counter value
GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
cccc
GTADTDBRA register
Buffer transfer at
trough
GTADTBRA register
bbbb
aaaa
Buffer transfer at
trough
cccc
Buffer transfer at
trough
GTADTRA register
Register write
bbbb
Buffer transfer at
trough
cccc
A/D converter
request A interrupt
Figure 23.30
Example of GTADTRA and GTADTRB double buffer operation with triangle waves, buffer transfer
at troughs, and A/D converter start request interrupt generated by down-counting
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23. General PWM Timer (GPT)
GTCNT counter value
GTPR register
dddd
cccc
bbbb
aaaa
Time
0000 0000h
Register write
Register write
GTADTDBRB register
cccc
bbbb
Buffer transfer at
trough
GTADTBRB register
aaaa
GTADTRB register
cccc
Register write
Register write
dddd
Buffer transfer at
crest
Buffer transfer at
trough
bbbb
dddd
Buffer transfer at
trough
Buffer transfer at
crest
Buffer transfer at
trough
aaaa
cccc
bbbb
Buffer transfer at
crest
Buffer transfer at
crest
dddd
A/D converter
request B interrupt
Figure 23.31
Example of GTADTRA and GTADTRB double buffer operation with triangle waves, buffer transfer
at both troughs and crests, and A/D converter start request interrupt generated by both up- and
down-counting
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.29, 000b (saw-wave PWM mode) is set, in Figure 23.30 and Figure 23.31, 100b, 101b, or 110b (trianglewave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.29, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set buffer operation
Set buffer operation with ADTTA[1:0], ADTTB[1:0], ADTDA, and ADTDB in GTBER.
In Figure 23.29, ADTTA[1:0] = 01b, 10b, or 11b and ADTDA = 0, in Figure 23.30, ADTTA[1:0] = 10b and ADTDA = 1,
and in Figure 23.31, ADTTB[1:0] = 11b and ADTDB = 1.
Set compare match value
Set the A/D converter start request point in GTADTRA and GTADTRB.
Set buffer value
For buffer operation, set the A/D converter start request point in 1 cycle after the current cycle (in saw-wave mode or
triangle-wave mode with buffer transfer at trough or crest) or half cycle after the current cycle (in triangle-wave mode
with buffer transfer at both trough and crest) in GTADTBRA and GTADTBRB.
For double buffer operation, also set the A/D converter start request point in 2 cycles after the current cycle (in sawwave mode or triangle-wave mode with buffer transfer at trough or crest) or 1 cycle after the current cycle (in trianglewave mode with buffer transfer at both trough and crest) in GTADTDBRA and GTADTDBRB.
Enable A/D converter start request interrupt
Set to enable A/D converter start requests interrupts with ADTRAUEN, ADTRADEN, ADTRBUEN, and ADTRBDEN in
GTINTAD. In Figure 23.29, ADTRAUEN = 1, in Figure 23.30, ADTRADEN = 1, and in Figure 23.31, ADTRBUEN = 1
and ADTRBDEN = 1.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the A/D converter start request point in 1 cycle after the current cycle (in saw-wave mode or
triangle-wave mode with buffer transfer at trough or crest) or half cycle after the current cycle (in triangle-wave mode
with buffer transfer at both trough and crest) in GTADTBRA and GTADTBRB.
For double buffer operation, also set the A/D converter start request point in 2 cycles after the current cycle (in sawwave mode or triangle-wave mode with buffer transfer at trough or crest) or 1 cycle after the current cycle (in trianglewave mode with buffer transfer at both trough and crest) in GTADTDBRA and GTADTDBRB.
Figure 23.32
23.3.3
Example setting for GTADTRA and GTADTRB buffer operation
PWM Output Operating Mode
The GPT can output PWM waveforms to the GTIOCA or GTIOCB pin by a compare match between the GTCNT
counter and GTCCRA or GTCCRB. By setting GTDTCR, GTDVU, and GTDVD, the compare match value for a
negative-phase waveform with dead time can be automatically set to GTCCRB.
23.3.3.1
Saw-wave PWM mode
In saw-wave PWM mode, GTCNT performs saw-wave (half-wave) operation by setting the cycle in GTPR. A PWM
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23. General PWM Timer (GPT)
waveform is output to the GTIOCA or GTIOCB pin when a GTCCRA or GTCCRB compare match occurs. The pin
output value can be selected from low output, high output, or toggle output separately for a compare match and for the
cycle end according to the GTIOR setting.
Figure 23.33 shows an example of saw-wave PWM mode operation, and Figure 23.34 shows an example setting for sawwave PWM mode.
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT32EH0.GTCCRC register
Register write
cccc
eeee
Buffer transfer
at overflow
GPT32EH0.GTCCRA register
aaaa
Register write
GPT32EH0.GTCCRE register
cccc
Register write
Buffer transfer
at overflow
Register write
Register write
ffff
dddd
bbbb
Buffer transfer
at overflow
eeee
Buffer transfer
at overflow
GPT32EH0.GTCCRB register
Register write
dddd
Buffer transfer
at overflow
Buffer transfer
at overflow
ffff
GTIOC0A pin output
GTIOC0B pin output
Figure 23.33
Example of saw-wave PWM mode operation with up-counting, buffer operation, high output at
GTCCRA/GTCCRB compare match, and low output at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]. In Figure 23.33, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.33, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.33, GTIOA[4:0] = 00110b and GTIOB[4:0] = 00110b.
*1
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER. In Figure 23.33, CCRA = 01b and CCRB = 01b.
*1
Set compare match value
Set the GTIOCA pin transition in GTCCRA and GTIOCB pin transition in GTCCRB.
Set buffer value
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in 1 cycle after the current cycle in GTCCRC
and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in 2 cycles after the current cycle in
GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in 1 cycle after the current cycle in GTCCRC
and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in 2 cycles after the current cycle in
GTCCRD and GTCCRF, respectively.
Note 1.
Figure 23.34
When the PWM delay generating circuit is used, exchange the sequence of the step for Enable GTIOC pin
output and the step for Set compare-match value.
Example setting for saw-wave PWM mode
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23.3.3.2
23. General PWM Timer (GPT)
Saw-wave one-shot pulse mode
The saw-wave one-shot pulse mode is a mode in which the cycle is set in GTPR. The GTCNT counter performs sawwave (half-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of
GTCCRA or GTCCRB with buffer operation fixed.
Buffer operation in saw-wave one-shot pulse mode is different from the usual buffer operation. Buffer transfer is
performed from:
GTCCRC to GTCCRA at the cycle end
GTCCRE to GTCCRB at the cycle end
GTCCRD to temporary register A at the cycle end
GTCCRF to temporary register B at the cycle end
Temporary register A to GTCCRA at a GTCCRA compare match
Temporary register B to GTCCRB at a GTCCRB compare match.
The pin output value can be selected from low output, high output, or toggle output separately for a compare match and
the cycle end according to the GTIOR setting. When the GTBER.CCRSWT bit is set to 1 while the count operation is
stopped, the buffer is transferred forcibly from the GTCCRD register to temporary register A and from the GTCCRF
register to temporary register B. By setting GTDTCR, GTDVU, and GTDVD, a compare match value for a negativephase waveform with dead time can automatically be set to GTCCRB.
Figure 23.35 shows an example of saw-wave one-shot pulse mode operation, and Figure 23.36 shows an example setting
for saw-wave one-shot pulse mode.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT32EH0.GTCCRD register
Register write
Register write
eeee
Buffer transfer
at overflow
Temporary register A
gggg
eeee
Register write
GPT32EH0.GTCCRC register
Register write
Register write
dddd
Buffer transfer at
compare match
GPT32EH0.GTCCRA register
Buffer transfer
at overflow
bbbb
Buffer transfer at
compare match
dddd
gggg
Register write
GPT32EH0.GTCCRF register
Buffer transfer
at overflow
Buffer transfer
at overflow
eeee
Register write
Register write
ffff
Buffer transfer
at overflow
Temporary register B
hhhh
Register write
Register write
Register write
cccc
GPT32EH0.GTCCRE register
Buffer transfer at
compare match
GPT32EH0.GTCCRB register
ffff
aaaa
hhhh
Buffer transfer
at overflow
cccc
Buffer transfer at
compare match
Buffer transfer
at overflow
ffff
GTIOC0A pin output
GTIOC0B pin output
Figure 23.35
Example of saw-wave one-shot pulse mode operation with up-counting, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at
GTCCRA/GTCCRB compare match, and output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.35, 001b (saw-wave one-shot pulse mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.35, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0]
(up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.35, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
*1
Set buffer value
Set the GTIOCA pin transition immediately after the count start in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
*1
Set forcible buffer transfer
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly.
Set buffer value
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Note 1.
Figure 23.36
When the PWM delay generating circuit is used, exchange the sequence of the step for Enable GTIOC pin
output and the step for Set buffer value.
Example setting for saw-wave one-shot pulse mode
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23.3.3.3
23. General PWM Timer (GPT)
Triangle-wave PWM mode 1 (32-bit transfer at trough)
The triangle-wave PWM mode 1 is a mode in which the cycle is set in GTPR. The GTCNT counter performs trianglewave (full-wave) operation, and a PWM waveform is output to the GTIOCA or GTIOCB pin when a GTCCRA or
GTCCRB compare match occurs. Buffer transfer is performed at the trough. The pin output value can be selected from
low output, high output, or toggle output separately for a compare match and for the cycle end based on the GTIOR
setting.
By setting GTDTCR, GTDVU, and GTDVD, a compare match value for a negative-phase waveform with dead time can
automatically be set to GTCCRB.
Figure 23.37 shows an example of a triangle-wave PWM mode 1 operation, and Figure 23.38 shows an example setting
for a triangle-wave PWM mode 1.
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT32EH0.GTCCRC register
Register write
dddd
Register write
ffff
Buffer transfer at
trough
GPT32EH0.GTCCRA register
GPT32EH0.GTCCRE register
dddd
bbbb
Register write
Register write
cccc
aaaa
ffff
Register write
eeee
Buffer transfer at
trough
GPT32EH0.GTCCRB register
Buffer transfer at
trough
cccc
Buffer transfer at
trough
eeee
GTIOC0A pin output
GTIOC0B pin output
Figure 23.37
Example of triangle-wave PWM mode 1 operation with buffer operation, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at
GTCCRA/GTCCRB register compare match, and output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.37, 100b (triangle-wave PWM mode 1) is set.
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.37, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
*1
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
In Figure 23.37, CCRA = 01b and CCRB = 01b.
*1
Set compare match value
Set the GTIOCA pin and GTIOCB pin transitions in GTCCRA and GTCCRB,
respectively.
Set buffer value
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in 1 cycle
after the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in
2 cycles after the current cycle in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in 1 cycle
after the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in
2 cycles after the current cycle in GTCCRD and GTCCRF, respectively.
Note 1.
Figure 23.38
When the PWM delay generating circuit is used, exchange the sequence of the step for Enable GTIOC pin
output and the step for Set buffer value.
Example setting for triangle-wave PWM mode 1
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23.3.3.4
23. General PWM Timer (GPT)
Triangle-wave PWM mode 2 (32-bit transfer at crest and trough)
Similarly to triangle-wave PWM mode 1, in triangle-wave PWM mode 2 the cycle is set in GTPR. The GTCNT counter
performs triangle-wave (full-wave) operation, and a PWM waveform is output to the GTIOCA or GTIOCB pin when a
GTCCRA or GTCCRB compare match occurs. The buffer transfer is performed at both crests and troughs. The pin
output value can be selected from low output, high output, or toggle output separately for a compare match and for the
cycle end based on the GTIOR setting.
By setting GTDTCR, GTDVU, and GTDVD, a compare match value for a negative-phase waveform with dead time can
automatically be set to GTCCRB.
Figure 23.39 shows an example of triangle-wave PWM mode 2 operation, and Figure 23.40 shows an example setting for
triangle-wave PWM mode 2.
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT32EH0.GTCCRC register
GPT32EH0.GTCCRA register
Register write
ffff
GPT32EH0.GTCCRE register
hhhh
Buffer transfer at
crest
Buffer transfer at
trough
Register write
cccc
Buffer transfer at
crest
GPT32EH0.GTCCRB register
aaaa
dddd
ffff
Register write
eeee
Register write
dddd
bbbb
Register write
Register write
eeee
Buffer transfer at
crest
hhhh
Register write
gggg
Buffer transfer at
trough
cccc
Buffer transfer at
crest
gggg
GTIOC0A pin output
GTIOC0B pin output
Figure 23.39
Example of triangle-wave PWM mode 2 operation with buffer operation, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at
GTCCRA/GTCCRB compare match, and output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.39, 101b (triangle-wave PWM mode 2) is set.
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.39, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
*1
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
In Figure 23.39, CCRA = 01b and CCRB = 01b.
*1
Set compare match value
Set the GTIOCA pin and GTIOCB pin transitions in GTCCRA and GTCCRB,
respectively.
Set buffer value
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in half cycle
after the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in
1 cycle after the current cycle in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in half cycle
after the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in
1 cycle after the current cycle in GTCCRD and GTCCRF, respectively.
Note 1.
Figure 23.40
When the PWM delay generation circuit is used, exchange the sequence of the step for Enable GTIOC pin
output and the step for Set buffer value.
Example setting for triangle-wave PWM mode 2
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23.3.3.5
23. General PWM Timer (GPT)
Triangle-wave PWM mode 3 (64-bit transfer at trough)
The triangle-wave PWM mode 3 is a mode in which the cycle is set in GTPR. The GTCNT counter performs trianglewave (full-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of
GTCCRA or GTCCRB with buffer operation fixed. Buffer operation in triangle-wave PWM mode 3 is different from the
usual buffer operation. Buffer transfer is performed from:
GTCCRC to GTCCRA at the trough
GTCCRE to GTCCRB at the trough
GTCCRD to temporary register A at the trough
GTCCRF to temporary register B at the trough
Temporary register A to GTCCRA at the crest
Temporary register B to GTCCRB at the crest.
The pin output value can be selected from low output, high output, or toggle output separately for a compare match and
for the cycle end based on the GTIOR setting. By setting GTDTCR, GTDVU, and GTDVD, a compare match value for a
negative-phase waveform with dead time can automatically be set to GTCCRB.
Figure 23.41 shows an example of triangle-wave PWM mode 3 operation, and Figure 23.42 shows an example setting for
triangle-wave PWM mode 3.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT32EH0.GTCCRD register
hhhh
Buffer transfer at
trough
hhhh
ffff
Temporary register A
Register write
Register write
dddd
GPT32EH0.GTCCRC register
Buffer transfer at
crest
GPT32EH0.GTCCRA register
Buffer transfer at
trough
dddd
ffff
bbbb
Register write
Buffer transfer at
crest
hhhh
Register write
gggg
GPT32EH0.GTCCRF register
Buffer transfer at
trough
gggg
eeee
Temporary register B
Register write
Register write
cccc
GPT32EH0.GTCCRE register
Buffer transfer at
crest
GPT32EH0.GTCCRB register
aaaa
eeee
Buffer transfer at
trough
cccc
Buffer transfer at
crest
gggg
GTIOC0A pin output
GTIOC0B pin output
Figure 23.41
Example of triangle-wave PWM mode 3 operation with low output from the GTIOC0A pin and high
output from the GTIOC0B pin at count start, output toggled at GTCCRA/GTCCRB compare match,
and output retained at cycle end
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.41, 110b (triangle-wave PWM mode 3) is set.
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.41, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
*1
Set buffer value
Set the GTIOCA pin transition immediately after the count start in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
*1
Set forcible buffer transfer
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly.
Set buffer value
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Note 1.
Figure 23.42
23.3.4
When the PWM delay generating circuit is used, exchange the sequence of the step for Enable GTIOC pin
output and the step for Set buffer value.
Example setting for triangle-wave PWM mode 3
Automatic Dead Time Setting Function
By setting GTDTCR, a compare match value for a negative waveform with dead time obtained by a compare match
value for a positive waveform (GTCCRA value) and specified dead time values (GTDVU and GTDVD values) can
automatically be set to GTCCRB. The automatic dead time setting function can be used in saw-wave one-shot pulse
mode and all the triangle PWM modes.
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23. General PWM Timer (GPT)
Dead time can be separately set for the first half and second half of a waveform. Dead time for the transition in the first
half of a negative waveform is set in GTDVU and that in the second half is set in GTDVD. The same dead time can also
be set for the first and second halves by setting the GTDTCR.TDFER bit to 1.
GTDBU can be used as a buffer register of GTDVU, and GTDBD can be used as a buffer register of GTDVD. Buffer
transfer is performed at a GTCNT overflow (during up-counting) or an underflow (during down-counting), or at a
GTCNT counter clear for saw waves and at the trough for triangle waves.
The compare match value set by automatic dead time setting function can be confirmed by reading from GTCCRB.
Writing to GTCCRB is prohibited when the automatic dead time setting function is used.
Dead time setting beyond the cycle is prohibited. When a dead time error occurs, the compare match values for positive
and negative waveforms are adjusted to generate the waveforms with the dead time as shown in Table 23.6. The adjusted
value for the negative waveform is set for GTCCRB automatically. The adjusted value for the positive waveform is used
as internal signal and not set for GTCCRA.
In saw-wave one-shot pulse mode, when the adjusted value is beyond the cycle or the adjusted waveform toggle points
are in disorder, the complementarity of the waveforms is not guaranteed.
In triangle-wave mode, when the dead time is beyond the cycle by setting the value GTCCR = 0 or GTCCRA ≥ GTPR
for GTCCRA, the output protection function keeps the level of output. For details, see section 23.8.4, Output Protection
Function for GTIOC Pin Output. When the GTCCRA is GTCCRA ≥ GTPR + GTDVm, GTPR-1 is set for GTCCRB as
the upper limit value. The automatic dead time value setting to GTCCRB is performed at the next clock cycle count
when registers used for calculating the automatic dead time value are updated.
The way to rewrite GTDVm differs by GPT channel number.
Table 23.6
Compare match value after adjusting for dead time error
Compare match value after adjusting
PWM output
operating mode
Count
direction
First half/
Second half
Condition of dead time error
Positive waveform
Negative waveform
Saw-wave one-shot
pulse mode
Up
First half
GTCCRA - GTDVU < 0
GTDVU
0
Second half
GTCCRA + GTDVD > GTPR
GTPR - GTDVD
GTPR
Down
First half
GTCCRA + GTDVU > GTPR
GTPR - GTDVU
GTPR
Second half
GTCCRA - GTDVD < 0
GTDVD
0
Triangle-wave PWM
mode 1/2/3
Up
First half
GTCCRA - GTDVU ≤ 0
GTDVU + 1
1
Down
Second half
GTCCRA - GTDVD < 0
GTDVD
0
GPT32EH0 to GPT32EH3 and GPT32E4 to GPT32E7
When GTDVn buffer operation is enabled, GTDBn can be written at anytime. GTDBn is transferred to GTDVn at the
cycle end.
When GTDVn buffer operation is disabled, stop the GPT using the CST bit in the GTCR register before changing
GTDVn to a new value.
GPT328 to GPT3213
While GPT is running, changing the GTDVU values is prohibited. To change GTDVU to a new value, first stop the GPT
using the CST bit in the GTCR register.
Figure 23.43 to Figure 23.46 show examples of automatic dead time setting function operation for GPT32EH and
GPT32E. Figure 23.47 and Figure 23.48 show the setting examples.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
Time
0000 0000h
Register write
Register write
GPT32EH0.GTDBU/GTDBD
register
Buffer transfer at overflow
Buffer transfer at overflow
GPT32EH0.GTDVU/GTDVD
register
GPT32EH0.GTCCRB register
(Automatic setting)
GTCCRA - GTDVU
GTCCRA + GTDVD
GTCCRA
- GTDVU
GTCCRA + GTDVD
GTDVU/GTDVD values are
automatically set as dead time
GTIOC0A pin output
GTDVU
GTIOC0B pin output
Figure 23.43
GTDVD
GTDVU
GTDVD
Example of automatic dead time setting function operation with saw-wave one-shot pulse mode,
up-counting, GTDVU and GTDVD set to buffer operation, and active-high
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
Time
0000 0000h
Register write
Register write
GPT32EH0.GTDBU/GTDBD
register
Buffer transfer at underflow
Buffer transfer at underflow
GPT32EH0.GTDVU/GTDVD
register
GPT32EH0.GTCCRB register
(Automatic setting)
GTCCRA + GTDVU
GTCCRA - GTDVD
GTCCRA
+ GTDVU
GTDVU/GTDVD values are
automatically set as dead time
GTIOC0A pin output
GTIOC0B pin output
Figure 23.44
GTCCRA - GTDVD
GTDVU
GTDVD
GTDVU
GTDVD
Example of automatic dead time setting function operation with saw-wave one-shot pulse mode,
down-counting, GTDVU and GTDVD set to buffer operation, and active-high
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
Time
0000 0000h
Register write
Register write
GPT32EH0.GTDBU/GTDBD
register
Buffer transfer at trough
Buffer transfer at trough
GTCCRA - GTDVU
GTCCRA - GTDVU
GPT32EH0.GTDVU/GTDVD
register
GPT32EH0.GTCCRB register
(Automatic setting)
GTCCRA - GTDVD
GTDVU/GTDVD values are
automatically set as dead time
GTIOC0A pin output
GTDVD
GTDVU
GTIOC0B pin output
Figure 23.45
GTCCRA
- GTDVD
GTDVU
GTDVD
Example of automatic compare-match value setting function with dead time with triangle-wave
PWM mode 1, GTDVU and GTDVD set to buffer operation, active-high
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
Time
0000 0000h
Register write
Register write
GPT32EH0.GTDBU/GTDBD
register
Buffer transfer at trough
Buffer transfer at trough
GTCCRA - GTDVU
GTCCRA - GTDVU
GPT32EH0.GTDVU/GTDVD
register
GPT32EH0.GTCCRB register
(Automatic setting)
GTCCRA - GTDVD
GTCCRA GTDVD
GTDVU/D values are
automatically set as dead time
GTIOC0A pin output
GTDVU
GTDVD
GTDVU
GTDVD
GTIOC0B pin output
Figure 23.46
Example of automatic compare-match value setting function with dead time, with triangle-wave
PWM mode 2 or 3, GTDVU and GTDVD set to buffer operation, and active-high
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]. In Figure 23.43 and Figure 23.44, 001b (saw-wave one-shot pulse
mode) is set. In Figure 23.46, 110b (triangle-wave PWM mode 3) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.43, 01b is set after 11b is set in GTUDDTYC[1:0] (up count) In Figure 23.44, 00b is set after 10b is set in
GTUDDTYC[1:0] (down count).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.43, Figure 23.45, and Figure 23.46, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
*1
Set buffer value for compare match
Set the GTIOCA pin transition immediately after the count start in GTCCRC and GTCCRD.
*1
Set forcible buffer transfer for compare match
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly to GTCCRA.
Set buffer value for compare match
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and GTCCRD.
Set automatic dead time setting function
Set GTDTCR.TDE to 1 to enable the automatic dead time setting function.
Set buffer operation for dead time setting
Set buffer operation with TDBUE and TDBDE in GTDTCR.
Set dead time value
Set the first half dead time value in GTDVU and the second half dead time in GTDVD. When GTDVU is set with
GTDTCR.TDFER set to 1, the same value is also set to GTDVD; the same dead time value can be set for the first and
second halves.
Set buffer value for dead time
For buffer operation, set the first half dead time in 1 cycle after the current cycle in GTDBU and the second half dead
time in GTDBD.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in 1 cycle after the current cycle in GTCCRC and GTCCRD.
When the dead time register is used as a buffer register, set the first half dead time in 1 cycle after the current cycle in
GTDBU and the second half dead time in GTDBD.
Note 1.
Figure 23.47
When the PWM delay generation circuit is used, exchange the sequence of the step for Enable GTIOC pin
output and the step for Set buffer value for compare match.
Example setting for automatic dead time setting function with saw-wave one-shot pulse mode,
and triangle-wave PWM mode 3
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]. In Figure 23.45, 100b (triangle-wave PWM mode 1) is set. In Figure
23.46, 101b (triangle-wave PWM mode 2) is set.
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
In Figure 23.45 and Figure 23.46, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation for compare match
Set buffer operation with CCRA in GTBER.
*1
Set compare match value
Set the GTIOCA pin transition in GTCCRA.
*1
Set buffer value for compare match
For buffer operation, set the GTIOCA pin transition in 1 cycle after the current cycle (in triangle-wave PWM mode 1) or
half cycle after the current cycle (in triangle-wave PWM mode 2) in GTCCRC. For double buffer operation, also set the
GTIOCA pin transition in 2 cycles after the current cycle (in triangle-wave PWM mode 1) or 1 cycle after the current
cycle (in triangle-wave PWM mode 2) in GTCCRD.
Set automatic dead time setting function
Set GTDTCR.TDE to 1 to enable the automatic dead time setting function.
Set buffer operation for dead time setting
Set buffer operation with TDBUE and TDBDE in GTDTCR.
Set dead time value
Set the first half dead time value in GTDVU and the second half dead time in GTDVD. If GTDTCR.TDFER is set to 1,
when GTDVU is set, the same value is also set to GTDVD; the same dead time value can be set for the first and
second halves.
Set buffer value for dead time
For buffer operation, set the first half dead time in 1 cycle after the current cycle in GTDBU and the second half dead
time in GTDBD.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
When the compare match register is used for buffer operation, set the GTIOCA pin transition in 1 cycle after the
current cycle (in triangle-wave PWM mode 1) or half cycle after the current cycle (in triangle-wave PWM mode 2) in
GTCCRC. When the compare match register is used for double buffer operation, also set the GTIOCA pin transition in
2 cycles after the current cycle (in triangle-wave PWM mode 1) or 1 cycle after the current cycle (in triangle-wave
PWM mode 2) in GTCCRD. When the dead time register is used for buffer operation, set the first half dead time in 1
cycle after the current cycle in GTDBU and the second half dead time in GTDBD.
Note 1.
Figure 23.48
When the PWM delay generation circuit is used, exchange the sequence of the step for Enable GTIOC pin
output and the step for Set compare match value.
Example setting for automatic dead time setting function with triangle-wave PWM mode 1 or 2
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23.3.5
23. General PWM Timer (GPT)
Count Direction Changing Function
The count direction of the GTCNT counter can be changed by modifying the UD bit in GTUDDTYC.
In saw-wave mode, if the UD bit in GTUDDTYC is modified during count operation, the count direction is changed at an
overflow (when modified during up-counting) or an underflow (when modified during down-counting). If the
GTUDDTYC.UD bit is modified while the count operation is stopped and the GTUDDTYC.UDF bit is 0, the
GTUDDTYC.UD bit modification is not reflected at the start of counting and the count direction is changed at an
overflow or an underflow. If the UDF bit is set to 1 while the count operation is stopped, the GTUDDTYC.UD bit value
at that time is reflected at the start of counting.
In triangle-wave mode, the count direction does not change when the UD bit in GTUDDTYC is modified during the
count operation. Similarly, when the GTUDDTYC.UD bit is modified while the count operation is stopped and
GTUDDTYC.UDF bit is 0, the GTUDDTYC.UD bit value is not reflected to the count operation. If the
GTUDDTYC.UDF bit is set to 1 while the count operation is stopped, the GTUDDTYC.UD bit value at that time is
reflected at the start of counting.
If the count direction changes during a saw-wave count operation, the GTPR value after the start of up-counting is
reflected in the count cycle during up-counting and the GTPR value before the start of down-counting is reflected during
down-counting.
Figure 23.49 shows an example of count direction changing function operation.
GTCNT counter value
bbbb
aaaa
0000 0000h
Time
Register write
GTUDDTYC.UD bit
(Count direction setting)
Up-counting
GTST.TUCF flag
(Count direction flag)
23.3.6
aaaa
Up-counting
Down-counting
Register write
bbbb
GTPBR register
Figure 23.49
Down-counting
Up-counting
Register write
GTPR register
Register write
Register write
aaaa
Up-counting
Register write
Register write
bbbb
Buffer transfer at
overflow
Buffer transfer at
overflow
bbbb
aaaa
Buffer transfer at
underflow
Buffer transfer at
underflow
Buffer transfer at
overflow
bbbb
Example of count direction changing function operation during buffer operation
Function of Output Duty 0% and 100%
The output duty of the GTIOCA pin and the GTIOCB pin are set to 0% or 100% by changing the GTUDDTYC.OADTY
bit or GTUDDTYC.OBDTY bit.
In saw-wave mode, if the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified during the count
operation, the output duty setting is reflected at an overflow (when modified during up-counting) or an underflow (when
modified during down-counting). If the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified while
the count operation is stopped and the GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is 0, the output duty
modification is not reflected at the start of counting. The output duty changes at an overflow or an underflow. If the
GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is set to 1 while the count operation is stopped, the
GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit value at that time is reflected at the start of counting.
In triangle-wave mode, if the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified during the count
operation, the output duty setting is reflected at an underflow.
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23. General PWM Timer (GPT)
If the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified while the count operation is stopped and
the GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is 0, the output duty modification is not reflected at the
start of counting. The output duty changes at an underflow. If the GTUDDTYC.OADTY bit or the
GTUDDTYC.OBDTY bit is modified while the count operation is stopped and the GTUDDTYC.OADTYF or the
GTUDDTYC.OBDTYF bit is 1, the output duty modification is reflected at the start of counting.
In performing 0%/100% duty operation, GPT internally continues to:
Perform compare match operation
Set compare match flag
Output interrupt
Perform buffer operation.
When the control is changed from 0% or 100% duty setting to compare match, the output value of GTIOCA pin at cycle
end is decided by GTIOR.GTIOA[3:2] and GTUDDTYC.OADTYR. The output value of GTIOCB pin at cycle end is
decided by GTIOR.GTIOB[3:2] and GTUDDTYC.OBDTYR.
When GTIOR.GTIOA[3:2] and GTIOR.GTIOB[3:2] are set to 01b, the output pins output low at cycle end. When
GTIOR.GTIOA[3:2] and GTIOR.GTIOB[3:2] are set to 10b, the output pins output high at cycle end.
GTUDDTYC.OADTYR selects the value that is the object of output retained/toggled at cycle end, when
GTIOR.GTIOm[3:2] are set to 00b (output retained at cycle end) or when GTIOR.GTIOm[3:2] are set to 11b (output
toggled at cycle end). Table 23.7 shows the values of GTIOCA/GTIOCB pin output at cycle end.
Table 23.7
Output values after releasing 0% or 100% duty setting (m = A, B)
GTIOR.GTIOm[3:2]
Compare match value at
cycle end masked by 0% or
100% duty setting
GTUDDTYC.OmDTYR in duty
0% setting
GTUDDTYC.OmDTYR in duty
100% setting
0
1
0
1
00
(output retained at cycle end)
0
0
0
1
0
1
0
1
1
1
01
(low output at cycle end)
-
0
0
0
0
10
(high output at cycle end)
-
1
1
1
1
11
(output toggled at cycle end)
0
1
1
0
1
1
1
0
0
0
Figure 23.50 shows an example of output duty 0% and 100% functions.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
bbbb
aaaa
0000 0000h
Time
Register write
GTUDDTYC.OADTY
00b
Register write
Register write
11b
10b
00b
GTIOC0A pin output
GTIOC0B pin output
0%
100%
[Setting examples]
GPT32EH0.GTIOR.GTIOA[4:0] bits:
00011b
Initial low output, output toggled at compare match, output retained at cycle end
GPT32EH0.GTUDDTYC.OADTYR bit: 0b
Applied the value of duty 0%/100% output to GTIOA[3:2] bits function after 0%/100%
duty setting is released
GPT32EH0.GTIOR.GTIOB[4:0] bits: 00011b
Initial low output, output toggled at compare match, output retained at cycle end
GPT32EH0.GTUDDTYC.OBDTYR bit: 1
Applied the value of masked compare match output to GTIOB[3:2] bits function after
0%/100% duty setting is released
Figure 23.50
23.3.7
Example of output duty 0% and 100% functions
Hardware Count Start/Count Stop and Clear Operation
The GTCNT counter can be started, stopped, or cleared by the following hardware sources:
External trigger input
ELC event input
GTIOCA/GTIOCB pin input.
23.3.7.1
Hardware start operation
The GTCNT counter can be started by selecting a hardware source using GTSSR.
Figure 23.51 shows an example of a count start operation by a hardware source. Figure 23.52 shows the setting example.
GTCNT counter value
GTPR register
Count started at ELC event input
0000 0000h
Time
ELC_GPTA input
Figure 23.51
Example of count start operation by hardware source, started at the input of the signal from
ELC_GPTA
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.51, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.51, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.51, 0000 0000h is set.
Set hardware count start
Select a hardware source for starting count operation in GTSSR register.
In Figure 23.51, GTSSR.SSELCA = 1.
Set hardware source operation
Set operation of the hardware source selected by GTSSR register and
start counting. In Figure 23.51, the ELC_GPTA input operation is set.
Figure 23.52
Example setting for count start operation by a hardware source
23.3.7.2
Hardware stop operation
The GTCNT counter can be stopped by selecting a hardware source using GTPSR.
Figure 23.53 shows an example of a count stop operation by a hardware source. Figure 23.54 shows the setting example.
In this example, the count operation stops and restarts at the edge of the ELC event input.
GTCNT counter value
Count stopped at Count started at
ELC event input ELC event input
GTPR register
Software start
0000 0000h
Time
ELC_GPTA input
ELC_GPTB input
Figure 23.53
Example of count stop operation by a hardware source started by software, stopped at
ELC_GPTA input, and restarted at ELC_GPTB input
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.53, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.53, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.53, 0000 0000h is set.
Set hardware count start
Select a hardware source for starting count operation in GTSSR register,
and wait for count start by the hardware source. In Figure 23.53,
GTSSR.SSELCB = 1.
Set hardware count stop
Select a hardware source for stopping count operation in GTPSR
register and wait for count stop by the hardware source. In Figure 23.53,
GTPSR.PSELCA = 1.
Set hardware source operation
Set operation of the hardware source selected in GTSSR register or
GTPSR register, and start or stop counting. In Figure 23.53, ELC_GPTA
input operation and ELC_GPTB input operation are set.
Figure 23.54
Example setting for count stop operation by a hardware source
Figure 23.55 shows an example of a count start/stop operation by a hardware source. Figure 23.56 shows the setting
example. In this example, the counter operates during the high-level periods of the external trigger input GTETRGA.
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23. General PWM Timer (GPT)
Count stopped on the falling Count started on the rising
edge of GTETRGA
edge of GTETRGA
GTCNT counter value
GTPR register
Count started on the rising
edge of GTETRGA
0000 0000h
Time
GTETRGA pin input
Figure 23.55
Example of count start/stop operation by hardware source, started on the rising edge of
GTETRGA pin input and stopped on the falling edge of GTETRGA pin input
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.55, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.55, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.55, 0000 0000h is set.
Set hardware count start
Select a hardware source for starting count operation with GTSSR
register and wait for count start by the hardware source.
In Figure 23.55, GTSSR.SSGTRGAR = 1.
Set hardware count stop
Select a hardware source for stopping count operation with GTPSR
register and wait for count stop by the hardware source.
In Figure 23.55, GTPSR.PSGTRGAF = 1.
Set hardware source operation
Set operation of the hardware source selected in GTSSR or GTPSR and
start or stop counting.
In Figure 23.55, the GTETRGA pin operation is set.
Figure 23.56
Example setting for count start/stop operation by a hardware source
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23.3.7.3
23. General PWM Timer (GPT)
Hardware clear operation
The GTCNT counter can be cleared by selecting a hardware source using GTCSR. The GPTn_OVF/GPTn_UDF (n = 0
to 13) interrupt (overflow/underflow interrupt) is not generated when the GTCNT counter is cleared by a hardware
source or by software.
Figure 23.57 and Figure 23.58 show examples of the GTCNT counter clearing operation by a hardware source. Figure
23.59 shows the setting example. In this example, the GTCNT counter starts at the edge of the ELC_GPTA input, and the
counter stops/clears at the edge of the ELC_GPTB input.
GTCNT counter value
Count stopped/cleared at ELC
event input
Count started at ELC
event input
Clear by software (by writing 1 to
corresponding channel number bit of
GTCLR register)
Count started at ELC
event input
0000_0000h
Time
ELC_GPTA input
ELC_GPTB input
Figure 23.57
Examples of count clearing operation by hardware source with saw wave up-counting, started at
ELC_GPTA input, and stopped/cleared at ELC_GPTB input
GTCNT counter value
Count started at ELC
event input
Count stopped/cleared at
ELC event input
Count started at ELC
event input
GTPR register
0000_0000h
Clear by software (by writing 1 to
corresponding channel number bit
of GTCLR register)
Time
ELC_GPTA input
ELC_GPTB input
Figure 23.58
Examples of count clearing operation by hardware source with saw wave down-counting, started
at ELC_GPTA input, and stopped/cleared at ELC_GPTB input
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.57 and Figure 23.58, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.57, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting). In
Figure 23.58, after 10b is set in GTUDDTYC[1:0], 00b is set in GTUDDTYC[1:0] (down-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in the GTPR register.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.57, 0000 0000h is set and in Figure 23.58, the GTPR value is set.
Set hardware count start
Select a hardware source for starting count operation in GTSSR register and wait for count start by the
hardware source. In Figure 23.57 and Figure 23.58, GTSSR.SSELCA = 1.
Set hardware count stop
Select a hardware source for stopping count operation in GTPSR register and wait for count stop by
the hardware source. In Figure 23.57 and Figure 23.58, GTPSR.PSELCB = 1.
Set hardware count clear
Select a hardware source for clearing count operation in GTCSR register and wait for count clear by
the hardware source. In Figure 23.57 and Figure 23.58, GTCSR.CSELCB = 1.
Set hardware source operation
Set operation of the hardware source selected in GTSSR register, GTPSR register, or GTCSR register
and start, stop or clear counting.
In Figure 23.57 and Figure 23.58, the ELC_GPTA and ELC_GPTB event inputs are set.
Figure 23.59
Example setting for count clearing operation by a hardware source
The GPTn_OVF/GPTn_UDF (n = 0 to 13) interrupt (overflow/underflow interrupt) is not generated when the counter is
cleared by a hardware source or by software.
Figure 23.60 shows the relationship between the counter clearing by a hardware source and the GPTn_OVF (n = 0 to 13)
interrupt.
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GTCNT counter value
23. General PWM Timer (GPT)
Counter cleared
at overflow
GTPR register
Counter cleared by
hardware source
Clear by software (by
writing 1 to corresponding
channel number bit of
GTCLR register)
0000 0000h
Time
Hardware source counter
clear signal
GPTn_OVF (n = 0 to 13)
interrupt request
GPTn_OVF (n = 0 to 13) interrupt not generated
Figure 23.60
23.3.8
Relationship between counter clearing by hardware source and GPTn_OVF (n = 0 to 13) interrupt
Synchronized Operation
Synchronized operation on channels such as a synchronized start, stop, and clear operation can be performed.
23.3.8.1
Synchronized operation by software
The GTCNT counters can be started, stopped, and cleared on multiple channels by setting the associated GTSTR,
GTSTP, or GTCLR bits simultaneously to 1.
Count start with a phase difference is possible by setting the initial value in the GTCNT counter and setting the
associated GTSTR bits simultaneously to 1.
Figure 23.61 shows an example of a simultaneous start, stop, and clear by software. Figure 23.62 shows an example of
phase start operation by software.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
0000 0000h
Time
GPT32EH1.GTCNT counter value
GPT32EH1.GTPR register
0000 0000h
Time
GPT32EH2.GTCNT counter value
GPT32EH2.GTPR register
0000 0000h
Time
GPT32EH3.GTCNT counter value
GPT32EH3.GTPR register
Time
0000 0000h
Write 0000 000Fh in
GTSTR register
(count operation started
in channel 0/1/2/3)
Figure 23.61
Write 0000 000Fh in
GTSTP or GTCLR register
(count operation stopped or
cleared in channel 0/1/2/3)
Write 0000 000Fh in
GTSTR register
(count operation started
in channel 0/1/2/3)
Example of a simultaneous start, stop, and clear by software, with the same count cycle (GTPR
register value)
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
GPT32EH1.GTCNT counter value
GPT32EH1.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
GPT32EH2.GTCNT counter value
GPT32EH2.GTPR register
cccc
bbbb
aaaa
Set initial value
Time
0000 0000h
GPT32EH3.GTCNT counter value
GPT32EH3.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
Write 0000 000Fh in GTSTR register.
(Start count operation in channel 0/1/2/3.)
Figure 23.62
Example of software phase start with the same count cycle (GTPR register value)
23.3.8.2
Synchronized operation by hardware
The GTCNT counters can be started simultaneously by the following hardware sources:
External trigger input
ELC event input.
Figure 23.63 shows an example of a simultaneous start, stop, and clear operation by a hardware source. Figure 23.64
shows the setting example.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
0000 0000h
Time
GPT32EH1.GTCNT counter value
GPT32EH1.GTPR register
0000 0000h
Time
GPT32EH2.GTCNT counter value
GPT32EH2.GTPR register
Time
0000 0000h
GPT32EH3.GTCNT counter value
GPT32EH3.GTPR register
0000 0000h
ELC_GPTA input
Count operation of channel
0/1/2/3 started by
ELC event input
Count operation of channel
0/1/2/3 stopped or cleared
by ELC event input
Time
Count operation of channel
0/1/2/3 started by
ELC event input
ELC_GPTB input
Figure 23.63
Example of a simultaneous start, stop, and clear by hardware source with the same count cycle
(GTPR register value)
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]
In Figure 23.63, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 23.63, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in the GTPR register.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 23.63, 0000 0000h is set.
Set hardware count start
Select a hardware source for starting count operation with GTSSR register and wait for count start by
the hardware source. In Figure 23.63, GTSSR.SSELCA = 1.
Set hardware count stop
Select a hardware source for stopping count operation with GTPSR register and wait for count stop by
the hardware source. In Figure 23.63, GTPSR.PSELCB = 1.
Set hardware count clear
Select a hardware source for clearing count operation with GTCSR register and wait for count clear by
the hardware source. In Figure 23.63, GTCSR.CSELCB = 1.
Set hardware source operation
Set operation of the hardware source selected in GTSSR or GTPSR or GTCSR and start or stop or
clear counting. In Figure 23.63, ELC_GPTA and ELC_GPTB event inputs are set.
Figure 23.64
23.3.9
(1)
Example setting for simultaneous start by a hardware source
PWM Output Operation Examples
Synchronized PWM output
The GPT outputs 28 phases of linked PWM waveforms for a maximum of 14 channels by multiple GPTs.
Figure 23.65 shows an example in which four channels perform synchronized operation in saw-wave PWM mode and
eight phases of PWM waveforms are output. The GTIOCA is set so that it outputs low as the initial value, high at a
GTCCRA compare match, and low at the cycle end. The GTIOCB is set so that it outputs low as the initial value, high at
a GTCCRB compare match, and low at the cycle end.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter
GPT32EH0.GTPR register
GPT32EH0.GTCCRB register
GPT32EH0.GTCCRA register
GPT32EH1.GTCNT counter
GPT32EH1.GTPR register
GPT32EH1.GTCCRB register
GPT32EH1.GTCCRA register
GPT32EH2.GTCNT counter
GPT32EH2.GTPR register
GPT32EH2.GTCCRB register
GPT32EH2.GTCCRA register
GPT32EH3.GTCNT counter
GPT32EH3.GTPR register
GPT32EH3.GTCCRB register
GPT32EH3.GTCCRA register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2A pin output
GTIOC2B pin output
GTIOC3A pin output
GTIOC3B pin output
Figure 23.65
(2)
Example of synchronized PWM output
3-phase saw-wave complementary PWM output
Figure 23.66 shows an example in which three channels perform synchronized operation in saw-wave PWM mode and
3-phase complementary PWM waveforms are output. The GTIOCA pin is set so that it outputs low as the initial value,
high at a GTCCRA compare match, and low at the cycle end. The GTIOCB pin is set so that it outputs high as the initial
value, low at a GTCCRB compare match, and high at the cycle end.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
GPT32EH0.GTCCRB register
GPT32EH1.GTCNT counter
GPT32EH1.GTPR register
GPT32EH1.GTCCRA register
GPT32EH1.GTCCRB register
GPT32EH2.GTCNT counter
GPT32EH2.GTPR register
GPT32EH2.GTCCRA register
GPT32EH2.GTCCRB register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2B pin output
GTIOC2A pin output
Figure 23.66
(3)
Example of 3-phase saw-wave complementary PWM output
3-phase saw-wave complementary PWM output with automatic dead time setting
Figure 23.67 shows an example in which three channels perform synchronized operation in saw-wave one-shot pulse
mode with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set
so that it outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the
cycle end. The GTIOCB pin is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare
match, and retains the output at the cycle end.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter
GPT32EH0.GTPR register
GPT32EH0.GTCCRD register
GPT32EH0.GTCCRC register
GPT32EH1.GTCNT counter
GPT32EH1.GTPR register
GPT32EH1.GTCCRD register
GPT32EH1.GTCCRC register
GPT32EH2.GTCNT counter
GPT32EH2.GTPR register
GPT32EH2.GTCCRD register
GPT32EH2.GTCCRC register
GTIOC0A pin output
GTIOC0B pin output
GPT32EH0.GTDVU
GPT32EH0.GTDVD
GTIOC1A pin output
GTIOC1B pin output
GPT32EH1.GTDVU
GPT32EH1.GTDVD
GTIOC2A pin output
GTIOC2B pin output
GPT32EH2.GTDVU
Figure 23.67
(4)
GPT32EH2.GTDVD
Example of 3-phase saw-wave complementary PWM output with automatic dead time setting
3-phase triangle-wave complementary PWM output
Figure 23.68 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 1
and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set so that it outputs low as the initial
value, toggles the output at a GTCCRA compare match, and retains the output at the cycle end. The GTIOCB pin is set
so that it outputs high as the initial value, toggles the output at a GTCCRB compare match, and retains the output at the
cycle end.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
GPT32EH0.GTCCRB register
GPT32EH1.GTCNT counter
GPT32EH1.GTPR register
GPT32EH1.GTCCRA register
GPT32EH1.GTCCRB register
GPT32EH2.GTCNT counter
GPT32EH2.GTPR register
GPT32EH2.GTCCRA register
GPT32EH2.GTCCRB register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2A pin output
GTIOC2B pin output
Figure 23.68
(5)
Example of 3-phase triangle-wave complementary PWM output
3-phase triangle-wave complementary PWM output with automatic dead time setting
Figure 23.69 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 1
with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set so
that it outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the
cycle end. The GTIOCB pin is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare
match, and retains the output at the cycle end.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
GPT32EH1.GTCNT counter
GPT32EH1.GTPR register
GPT32EH1.GTCCRA register
GPT32EH2.GTCNT counter
GPT32EH2.GTPR register
GPT32EH2.GTCCRA register
GPT32EH0.GTDVU
GPT32EH0.GTDVD
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GPT32EH1.GTDVD
GPT32EH1.GTDVU
GTIOC1B pin output
GPT32EH2.GTDVD
GTIOC2A pin output
GPT32EH2.GTDVU
GTIOC2B pin output
Figure 23.69
(6)
Example of 3-phase triangle-wave complementary PWM output with automatic dead time setting
3-phase asymmetric triangle-wave complementary PWM output with automatic dead time
setting
Figure 23.70 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 3
with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA is set so that it
outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the cycle end.
The GTIOCB is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare match, and
retains the output at the cycle end.
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter
GPT32EH0.GTPR register
GPT32EH0.GTCCRC register
GPT32EH0.GTCCRD register
GPT32EH1.GTCNT counter
GPT32EH1.GTPR register
GPT32EH1.GTCCRC register
GPT32EH1.GTCCRD register
GPT32EH2.GTCNT counter
GPT32EH2.GTPR register
GPT32EH2.GTCCRC register
GPT32EH2.GTCCRD register
GPT32EH0.GTDVU
GPT32EH0.GTDVD
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GPT32EH1.GTDVD
GPT32EH1.GTDVU
GTIOC1B pin output
GTIOC2A pin output
GPT32EH2.GTDVD
GPT32EH2.GTDVU
GTIOC2B pin output
Figure 23.70
23.3.10
Example of 3-phase asymmetric triangle-wave complementary PWM output with automatic dead
time setting
Phase Counting Function
The phase difference between the GTIOCA and GTIOCB pin inputs is detected and the associated GTCNT counts up or
counts down. The detectable phase difference is available in any combination with the relationship between the edge and
the level of GTIOCA and GTIOCB pin inputs being set in the GTUPSR and GTDNSR registers. For details on count
operation, see section 23.3.1.1, Counter operation.
Figure 23.71 to Figure 23.80 show phase counting modes 1 to 5. Table 23.8 to Table 23.17 show conditions of upcounting or down-counting and lists settings for the GTUPSR and GTDNSR registers.
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.71
Table 23.8
Example of phase counting mode 1
Conditions of up-counting and down-counting in phase counting mode 1
GTIOCA pin input
GTIOCB pin input
high
Operation
Register setting
Up-counting
GTUPSR = 0000 6900h
GTDNSR = 0000 9600h
low
low
high
high
Down-counting
low
high
low
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.72
Example of phase counting mode 2 (A)
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Table 23.9
23. General PWM Timer (GPT)
Conditions of up-counting and down-counting in phase counting mode 2 (A)
GTIOCA pin input
GTIOCB pin input
high
Operation
Register setting
Don’t care
GTUPSR = 0000 0800h
GTDNSR = 0000 0400h
low
low
high
high
Up-counting
Don’t care
low
high
low
Down-counting
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Down-counting
Up-counting
Time
Figure 23.73
Table 23.10
Example of phase counting mode 2 (B)
Conditions of up-counting and down-counting in phase counting mode 2 (B)
GTIOCA pin input
GTIOCB pin input
high
Operation
Register setting
Don’t care
GTUPSR = 0000 0200h
GTDNSR = 0000 0100h
low
low
Down-counting
high
Don’t care
high
low
high
Up-counting
low
Don’t care
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.74
Table 23.11
Example of phase counting mode 2 (C)
Conditions of up-counting and down-counting in phase counting mode 2 (C)
GTIOCA pin input
GTIOCB pin input
high
Operation
Register setting
Don’t care
GTUPSR = 0000 0A00h
GTDNSR = 0000 0500h
low
low
Down-counting
high
Don’t care
high
Up-counting
low
Down-counting
high
low
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.75
Example of phase counting mode 3 (A)
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Table 23.12
23. General PWM Timer (GPT)
Conditions of up-counting and down-counting in phase counting mode 3 (A)
GTIOCA pin input
GTIOCB pin input
high
Operation
Register setting
Don’t care
GTUPSR = 0000 0800h
GTDNSR = 0000 8000h
low
low
high
Up-counting
high
Down-counting
low
Don’t care
high
low
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Down-counting
Up-counting
Time
Figure 23.76
Table 23.13
Example of phase counting mode 3 (B)
Conditions of up-counting and down-counting in phase counting mode 3 (B)
GTIOCA pin input
GTIOCB pin input
Operation
Register setting
high
Down-counting
low
Don’t care
GTUPSR = 0000 0200h
GTDNSR = 0000 2000h
low
high
high
low
high
Up-counting
low
Don’t care
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 23.77
Table 23.14
Example of phase counting mode 3 (C)
Conditions of up-counting and down-counting in phase counting mode 3 (C)
GTIOCA pin input
Operation
Register setting
high
GTIOCB pin input
Down-counting
low
Don’t care
GTUPSR = 0000 0A00h
GTDNSR = 0000 A000h
low
high
high
Up-counting
Down-counting
low
Don’t care
high
Up-counting
low
Don’t care
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT Counter
Up-counting
Down-counting
Time
Figure 23.78
Example of phase counting mode 4
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Table 23.15
23. General PWM Timer (GPT)
Conditions of up-counting and down-counting in phase counting mode 4
GTIOCA pin input
GTIOCB pin input
high
Operation
Register setting
Up-counting
GTUPSR = 0000 6000h
GTDNSR = 0000 9000h
low
low
Don’t care
high
high
Down-counting
low
high
Don’t care
low
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT
Up-counting
Time
Figure 23.79
Table 23.16
Example of phase counting mode 5 (A)
Conditions of up-counting and down-counting in phase counting mode 5 (A)
GTIOCA pin input
GTIOCB pin input
high
Operation
Register setting
Don’t care
GTUPSR = 0000 0C00h
GTDNSR = 0000 0000h
low
low
high
high
Up-counting
Don’t care
low
high
low
Up-counting
: Rising edge
: Falling edge
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23. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT
Up-counting
Time
Figure 23.80
Table 23.17
Example of phase counting mode 5 (B)
Conditions of up-counting and down-counting in phase counting mode 5 (B)
GTIOCA pin input
GTIOCB pin input
high
low
Operation
Register setting
Don’t care
GTUPSR = 0000 0C00h
GTDNSR = 0000 0000h
Up-counting
low
Don’t care
high
high
Up-counting
low
Don’t care
high
low
: Rising edge
: Falling edge
23.3.11
Output Phase Switching (GPT_OPS)
GPT_OPS provides a function for easy control of brushless DC motor operation using the Output Phase Switching
Control Register (OPSCR).
GPT_OPS outputs a PWM signal to be used for chopper control or level signal for each phase (U-positive phase/negative
phase, V-positive phase/negative phase, W-positive phase/negative phase) of the 6-phase motor control. This function
uses a soft setting value (OPSCR.UF, VF, WF) set by software or external signals detected by the Hall element, a PWM
waveform of GPT32EH0.GTIOCA.
Figure 23.81 shows the GPT_OPS control flow conceptual diagram.
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23. General PWM Timer (GPT)
(1)
OPSCR.
UF/VF/WF
From hall element
GTIU
GTIV
GTIW
Synchronize
noise filter
Input select
Soft setting (UF/VF/WF)
(5)
PCLKD
sample
Input phase
PWM edge
sample
Hall sensor
input edge sample
(every PCLKD)
To ELC
GPT_UVWEDGE
(Input U-phase)
(Input V-phase)
(Input W-phase)
PCLKD
External input (U/V/W)
Input selection
selector
OPS internal node name
(gtu_sync)
(gtv_sync)
(gtw_sync)
Input phase de-code
6-phase enable gen
(2)
OPS internal node name
(gtuup_en, gtulo_en)
(gtvup_en, gtvlo_en)
(gtwup_en, gtwlo_en)
(3)
Output select control
From GPT32EH0.GTIOCA
PWM
BUS clock
PCLKA
GPT32 core clock
PCLKD
Figure 23.81
To brushless DC motor
GTOUUP,
GTOULO,
GTOVUP,
GTOVLO,
GTOWUP,
GTOWLO
Conceptual diagram of GPT_OPS control flow
Figure 23.82 shows a 6-phase level signals output example of a GPT_OPS operation.
The GPT_UVWEDGE signal in Figure 23.82 is the Hall sensor input edge to ELC output.
Input sel after “U-phase”
GTIU
Input sel after “V-phase”
GTIV
Input sel after “W-phase”
GTIW
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Figure 23.82
Register settings: OPSCR.ALIGN = 0, OPSCR.EN = 1, OPSCR.P = 0, OPSCR.N = 0, OPSCR.INV = 0.
Example of 6-phase level output operation
Figure 23.83 shows a 6-phase PWM output example of a GPT_OPS operation (chopper control).
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23. General PWM Timer (GPT)
GPT32EH0 PWM
PWM
Input sel after “U-phase”
GTIU
Input sel after “V-phase”
GTIV
Input sel after “W-phase”
GTIW
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Figure 23.83
Register settings: OPSCR.ALIGN = 1, OPSCR.EN = 1, OPSCR.P = 1, OPSCR.N = 1, OPSCR.INV = 0.
Example of 6-phase PWM output operation with chopper control
Figure 23.84 shows an example of output disable control (6-phase PWM output operation).
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23. General PWM Timer (GPT)
GPT32EH0 PWM
PWM
"U-phase" after input
selection
GTIU
"V-phase" after input
selection
GTIV
"W-phase" after input
selection
GTIW
Output enable
OPSCR.EN
Output Disabled Source
Select
OPSCR.GRP
Auto clear
Setting by software
00b (Group A output disable request)
Group output disable
OPSCR.GODF
Clear by software
Output disable signal
from POEG to OPS
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Register settings: OPSCR.P = 1, OPSCR.N = 1, OPSCR.INV = 0.
Figure 23.84
Example of group output disable control operation
23.3.11.1
Input selection and synchronization of external input signal
In the GPT_OPS control flow conceptual diagram shown in Figure 23.81, (1) is a selection of input phase from software
settings and external input by the OPSCR.FB bit.
When OPSCR.FB bit = 0, select the external input. Enable the input signal after synchronization with the GPT core clock
(PCLKD). After carrying out noise filtering (optional), set the external input to the input phase of PWM (PWM of
GPT32EH0.GTIOCA) using falling edge sampling with OPSCR.ALIGN bit = 1.
When OPSCR.FB bit = 1, select the soft setting (OPSCR.UF, VF, WF) with the value of the input phase of PWM (PWM
of GPT32EH0.GTIOCA) using falling edge sampling with OPSCR.ALIGN bit = 1.
When OPSCR.ALIGN bit = 0, GPT_OPS operates with the input phase of PCLKD synchronization with either
OPSCR.FB bit = 0 or OPSCR.FB bit = 1. However, in some situations, the PWM pulse width of the output U/V/W
phases (PWM output mode) of switch timing (just before or just after) is shortened.
Table 23.18 shows the input selection process and setting of associated OPSCR bits.
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Table 23.18
23. General PWM Timer (GPT)
Input selection processing method
OPSCR register
Selection of input phase sampling method
(U/V/W-phase)
Synchronization input/output selection
process (GPT_OPS internal node name)
1
External Input at PWM Falling Edge Sampling
(PCLKD synchronization + falling edge sample)
0
External Input at PCLKD Synchronization Output
(PCLKD synchronization + through mode)
Input Phase
Input U-Phase (gtu_sync)
Input V-Phase (gtv_sync)
Input W-Phase (gtw_sync)
1
Software Settings at PWM Falling Edge Sampling
(OPSCR.UF, VF, WF of falling edge sample)
0
Software Setting Value Selection
(= OPSCR.UF/VF/WF value) (= PCLKD
synchronization)
FB bit
ALIGN bit
0
1
23.3.11.2
Input sampling
The OPSCR.U, V, W bits indicate the PCLKD sampling results of the input selected by the OPSCR.FB bit.
When OPSCR.FB bit = 0 and after synchronization with the GPT core clock (PCLKD) and noise filtering (optional),
OPSCR.U, V, W bits indicate the sampling results of the external input. When OPSCR.FB bit = 1, OPSCR.U, V, W bits
have the value (OPSCR.UF, VF, WF) of the soft setting.
23.3.11.3
Input phase decode
In the GPT_OPS control flow conceptual diagram shown in Figure 23.81, (2) enables the 6-phase signals by decoding
the input phase selected by the OPSCR.FB bit. The 6-phase enable signal is used for internal processing of GPT_OPS.
Table 23.19 shows the decode table of input phase.
Table 23.19
Decode table of input phase
Input phase (U/V/W)
(GPT_OPS internal node name)
6-phase enable {U/V/W (Up/Lo)} by decoding input phase
(GPT_OPS internal node name)
Input Uphase
Input Vphase
Input Wphase
U-phase
(Up)
U-phase
(Lo)
V-phase
(Up)
V-phase
(Lo)
W-phase
(Up)
W-phase
(Lo)
(gtu_sync)
(gtv_sync)
(gtw_sync)
(gtuup_en)
(gtulo_en)
(gtvup_en)
(gtvlo_en)
(gtwup_en)
(gtwlo_en)
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
23.3.11.4
Output selection control
In the GPT_OPS control flow conceptual diagram in Figure 23.81, (3) represents the selection of the output waveform by
setting the OPSCR register bit.
For output selection, the following bits are relevant:
The OPSCR.EN bit controls whether to output the 6-phase output, or to stop
The OPSCR.P and OPSCR.N bits can select from the level signal or PWM signal (chopper output) for the output
phase
The polarity of the output phase can be set to positive logic or negative logic by the OPSCR.INV bit.
Table 23.20 and Table 23.21 show the output selection control method using the OPSCR register bit.
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Table 23.20
23. General PWM Timer (GPT)
Output selection control method (positive phase)
Enable-phase output
control
Positive-phase output
(P) control
Invert-phase output
control
Output port name (positive phase = up)
(output selection internal node allocation)
OPSCR.EN bit
OPSCR.P bit
OPSCR.INV bit
GTOUUP
GTOVUP
GTOWUP
0
x
x
0
Output Stop
(External pin: Hi-Z)
GPT_OPS => 0 output
1
0
0
Level signal
(gtuup_en)
(gtvup_en)
(gtwup_en)
Level Output Mode
(Positive phase)
(Positive logic)
1
0
1
Level signal
( ~gtuup_en)
( ~gtvup_en)
( ~gtwup_en)
Level Output Mode
(Positive phase)
(Negative logic)
1
1
0
PWM signal
(PWM & gtuup_en)
(PWM & gtvup_en)
(PWM & gtwup_en)
PWM Output Mode
(Positive phase)
(Positive logic)
1
1
1
PWM signal
(~(PWM & gtuup_en))
(~(PWM & gtvup_en))
(~(PWM & gtwup_en))
PWM Output Mode
(Positive phase)
(Negative logic)
Table 23.21
Mode
Output selection control method (negative phase)
Enable-phase output
control
Negative-phase output
(N) control
Invert-phase output
control
Output port name (negative phase = Lo)
(output selection internal node allocation)
OPSCR.EN bit
OPSCR.N bit
OPSCR.INV bit
GTOULO
GTOVLO
GTOWLO
0
x
x
0
Output Stop
(External pin: Hi-Z)
GPT_OPS => 0 output
1
0
0
Level signal
(gtulo_en)
(gtvlo_en)
(gtwlo_en)
Level Output Mode
(Negative phase)
(Positive logic)
1
0
1
Level signal
( ~gtulo_en)
( ~gtvlo_en)
( ~gtwlo_en)
Level Output Mode
(Negative phase)
(Negative logic)
1
1
0
PWM signal
(PWM & gtulo_en)
(PWM & gtvlo_en)
(PWM & gtwlo_en)
PWM Output Mode
(Negative phase)
(Positive logic)
1
1
1
PWM signal
(~(PWM & gtulo_en))
(~(PWM & gtvlo_en))
(~(PWM & gtwlo_en))
PWM Output Mode
(Negative phase)
(Negative logic)
23.3.11.5
Mode
Output selection control (group output disable function)
When OPSCR.GODF = 1 and the signal value selected by the OPSCR.GRP bit is high (output disable request), the
GPT_OPS output pins are changed to Hi-Z asynchronously and the OPSCR.EN bit is set to 0 by the output disable
request signal synchronized with PCLKD. For the return, set the OPSCR.EN to 1 after clearing the output disable request
with software.
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23. General PWM Timer (GPT)
The timing of OPSCR.EN bit cleared to 0 is 3 PCLKD cycles after generating the output disable request. To perform
output disable control reliably, allow at least 4 PCLKD cycles after generating the output disable request (by clearing the
output disable request flag in POEG) until the output disable request is terminated. For an example of the operation of
group output disable control, see Figure 23.84.
23.3.11.6
Event Link Controller (ELC) output
In the GPT_OPS control flow conceptual diagram shown in Figure 23.81, (5) outputs the Hall sensor input signal edge to
the ELC.
The Hall sensor input edge signal is the logical OR of the rising and falling edge signals of each U-phase/V-phase/Wphase input sampled at PCLKD. That is, if the high period of each of the U-phase/V-phase/W-phase input is short in
duration, the Hall sensor edge input signal is not output at that time.
When OPSCR.FB bit is 0, the Hall sensor input edge signal is the logical OR of the edge signals of the external input
phase sampled at PCLKD.
When OPSCR.FB bit is 1, the Hall sensor input edge signal is the logical OR of the edge of the soft setting (OPSCR.UF,
VF, WF) sampled at PCLKD.
See Figure 23.82 to Figure 23.84 for examples of the output signal to the ELC.
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23.3.11.7
23. General PWM Timer (GPT)
GPT_OPS start operation setting flow
GPT32EH0 operation mode setting
GPT32EH0.GTIOCA set the PWM output operation mode of the saw-wave or triangle-wave.
For details, see section 23.3.3, PWM Output Operating Mode.
Counting of GPT32EH0
Start the count operation of GPT32EH0 and output a PWM waveform.
GPT_OPS input data set (only software setting is selected)
Set software setting to OPSCR.UF, VF, and WF bits.
Noise filter settings of GPT_OPS external input (only external input is selected)
When using a noise filter, set the sampling clock of the noise filter by OPSCR.NFCS bit.
Then the noise filter is enabled if OPSCR.NFEN bit = 1.
GPT_OPS input phase selection setting/input phase alignment setting
Select the input phase from the external input or software setting by OPSCR.FB bit.
Select the alignment of the input phase by OPSCR.ALIGN bit.
Setting the GPT_OPS output phase
Set the level output/PWM output of the positive/negative phase output by OPSCR.P/OPSCR.N bit.
Set the positive logic/negative logic of the output phase by OPSCR.INV bit.
GPT_OPS setting the group output disable function
Set the selection of output disable source by OPSCR.GRP bit.
Perform the setting of on/off of the group output disable function by OPSCR.GODF bit.
GPT_OPS Working
Setting the OPSCR.EN bit = 1 outputs the 6-phase output to drive the brushless DC motor from the
GPT_OPS.
Figure 23.85
23.4
23.4.1
Example setting of GPT_OPS start operation
Interrupt Sources
Overview
The GPT provides the following interrupt sources:
GTCCR input capture/compare match
GTADTR compare match
GTCNT counter overflow (GTPR compare match)/underflow.
Each interrupt source has its own status flag. When an interrupt source signal is generated, the associated status flag in
GTST is set to 1. The associated status flag in GTST can be cleared by writing 0. If flag set and flag clear occur at the
same time, flag clear takes priority over flag set. These flags are automatically updated by the internal state. Table 23.22
lists the GPT interrupt sources.
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Table 23.22
23. General PWM Timer (GPT)
Interrupt sources (1 of 4)
Name
0
GPT0_CCMPA
GPT32EH0.GTCCRA input capture/compare match
TCFA
Possible
GPT0_CCMPB
GPT32EH0.GTCCRB input capture/compare match
TCFB
Possible
GPT0_CMPC
GPT32EH0.GTCCRC compare match
TCFC
Possible
GPT0_CMPD
GPT32EH0.GTCCRD compare match
TCFD
Possible
GPT0_CMPE
GPT32EH0.GTCCRE compare match
TCFE
Possible
1
2
Interrupt source
Interrupt flag
DMAC/DTC
activation
Channel
GPT0_CMPF
GPT32EH0.GTCCRF compare match
TCFF
Possible
GPT0_ADTRGA
GPT32EH0.GTADTRA compare match
ADTRAUF
ADRTADF
Possible
GPT0_ADTRGB
GPT32EH0.GTADTRB compare match
ADTRBUF
ADRTBDF
Possible
GPT0_OVF
GPT32EH0.GTCNT overflow (GPT32EH0.GTPR compare
match)
TCFPO
Possible
GPT0_UDF
GPT32EH0.GTCNT underflow
TCFPU
Possible
GPT1_CCMPA
GPT32EH1.GTCCRA input capture/compare match
TCFA
Possible
GPT1_CCMPB
GPT32EH1.GTCCRB input capture/compare match
TCFB
Possible
GPT1_CMPC
GPT32EH1.GTCCRC compare match
TCFC
Possible
GPT1_CMPD
GPT32EH1.GTCCRD compare match
TCFD
Possible
GPT1_CMPE
GPT32EH1.GTCCRE compare match
TCFE
Possible
GPT1_CMPF
GPT32EH1.GTCCRF compare match
TCFF
Possible
GPT1_ADTRGA
GPT32EH1.GTADTRA compare match
ADTRAUF
ADRTADF
Possible
GPT1_ADTRGB
GPT32EH1.GTADTRB compare match
ADTRBUF
ADRTBDF
Possible
GPT1_OVF
GPT32EH1.GTCNT overflow (GPT32EH1.GTPR compare
match)
TCFPO
Possible
GPT1_UDF
GPT32EH1.GTCNT underflow
TCFPU
Possible
GPT2_CCMPA
GPT32EH2.GTCCRA input capture/compare match
TCFA
Possible
GPT2_CCMPB
GPT32EH2.GTCCRB input capture/compare match
TCFB
Possible
GPT2_CMPC
GPT32EH2.GTCCRC compare match
TCFC
Possible
GPT2_CMPD
GPT32EH2.GTCCRD compare match
TCFD
Possible
GPT2_CMPE
GPT32EH2.GTCCRE compare match
TCFE
Possible
GPT2_CMPF
GPT32EH2.GTCCRF compare match
TCFF
Possible
GPT2_ADTRGA
GPT32EH2.GTCCRE compare match
ADTRAUF
ADRTADF
Possible
GPT2_ADTRGB
GPT32EH2.GTCCRF compare match
ADTRBUF
ADRTBDF
Possible
GPT2_OVF
GPT32EH2.GTCNT overflow (GPT32EH2.GTPR compare
match)
TCFPO
Possible
GPT2_UDF
GPT32EH2.GTCNT underflow
TCFPU
Possible
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Table 23.22
23. General PWM Timer (GPT)
Interrupt sources (2 of 4)
Channel
Name
Interrupt source
Interrupt flag
DMAC/DTC
activation
3
GPT3_CCMPA
GPT32EH3.GTCCRA input capture/compare match
TCFA
Possible
GPT3_CCMPB
GPT32EH3.GTCCRB input capture/compare match
TCFB
Possible
GPT3_CMPC
GPT32EH3.GTCCRC compare match
TCFC
Possible
GPT3_CMPD
GPT32EH3.GTCCRD compare match
TCFD
Possible
GPT3_CMPE
GPT32EH3.GTCCRE compare match
TCFE
Possible
4
5
GPT3_CMPF
GPT32EH3.GTCCRF compare match
TCFF
Possible
GPT3_ADTRGA
GPT32EH3.GTADTRA compare match
ADTRAUF
ADRTADF
Possible
GPT3_ADTRGB
GPT32EH3.GTADTRB compare match
ADTRBUF
ADRTBDF
Possible
GPT3_OVF
GPT32EH3.GTCNT overflow (GPT32EH3.GTPR compare
match)
TCFPO
Possible
GPT3_UDF
GPT32EH3.GTCNT underflow
TCFPU
Possible
GPT4_CCMPA
GPT32E4.GTCCRA input capture/compare match
TCFA
Possible
GPT4_CCMPB
GPT32E4.GTCCRB input capture/compare match
TCFB
Possible
GPT4_CMPC
GPT32E4.GTCCRC compare match
TCFC
Possible
GPT4_CMPD
GPT32E4.GTCCRD compare match
TCFD
Possible
GPT4_CMPE
GPT32E4.GTCCRE compare match
TCFE
Possible
GPT4_CMPF
GPT32E4.GTCCRF compare match
TCFF
Possible
GPT4_ADTRGA
GPT32E4.GTADTRA compare match
ADTRAUF
ADRTADF
Possible
GPT4_ADTRGB
GPT32E4.GTADTRB compare match
ADTRBUF
ADRTBDF
Possible
GPT4_OVF
GPT32E4.GTCNT overflow (GPT32E4.GTPR compare
match)
TCFPO
Possible
GPT4_UDF
GPT32E4.GTCNT underflow
TCFPU
Possible
GPT5_CCMPA
GPT32E5.GTCCRA input capture/compare match
TCFA
Possible
GPT5_CCMPB
GPT32E5.GTCCRB input capture/compare match
TCFB
Possible
GPT5_CMPC
GPT32E5.GTCCRC compare match
TCFC
Possible
GPT5_CMPD
GPT32E5.GTCCRD compare match
TCFD
Possible
GPT5_CMPE
GPT32E5.GTCCRE compare match
TCFE
Possible
GPT5_CMPF
GPT32E5.GTCCRF compare match
TCFF
Possible
GPT5_ADTRGA
GPT32E5.GTADTRA compare match
ADTRAUF
ADRTADF
Possible
GPT5_ADTRGB
GPT32E5.GTADTRB compare match
ADTRBUF
ADRTBDF
Possible
GPT5_OVF
GPT32E5.GTCNT overflow (GPT32E5.GTPR compare
match)
TCFPO
Possible
GPT5_UDF
GPT32E5.GTCNT underflow
TCFPU
Possible
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Table 23.22
23. General PWM Timer (GPT)
Interrupt sources (3 of 4)
Channel
Name
Interrupt source
Interrupt flag
DMAC/DTC
activation
6
GPT6_CCMPA
GPT32E6.GTCCRA input capture/compare match
TCFA
Possible
GPT6_CCMPB
GPT32E6.GTCCRB input capture/compare match
TCFB
Possible
GPT6_CMPC
GPT32E6.GTCCRC compare match
TCFC
Possible
GPT6_CMPD
GPT32E6.GTCCRD compare match
TCFD
Possible
GPT6_CMPE
GPT32E6.GTCCRE compare match
TCFE
Possible
7
8
9
GPT6_CMPF
GPT32E6.GTCCRF compare match
TCFF
Possible
GPT6_ADTRGA
GPT32E6.GTADTRA compare match
ADTRAUF
ADRTADF
Possible
GPT6_ADTRGB
GPT32E6.GTADTRB compare match
ADTRBUF
ADRTBDF
Possible
GPT6_OVF
GPT32E6.GTCNT overflow (GPT32E6.GTPR compare
match)
TCFPO
Possible
GPT6_UDF
GPT32E6.GTCNT underflow
TCFPU
Possible
GPT7_CCMPA
GPT32E7.GTCCRA input capture/compare match
TCFA
Possible
GPT7_CCMPB
GPT32E7.GTCCRB input capture/compare match
TCFB
Possible
GPT7_CMPC
GPT32E7.GTCCRC compare match
TCFC
Possible
GPT7_CMPD
GPT32E7.GTCCRD compare match
TCFD
Possible
GPT7_CMPE
GPT32E7.GTCCRE compare match
TCFE
Possible
GPT7_CMPF
GPT32E7.GTCCRF compare match
TCFF
Possible
GPT7_ADTRGA
GPT32E7.GTADTRA compare match
ADTRAUF
ADRTADF
Possible
GPT7_ADTRGB
GPT32E7.GTADTRB compare match
ADTRBUF
ADRTBDF
Possible
GPT7_OVF
GPT32E7.GTCNT overflow (GPT32E7.GTPR compare
match)
TCFPO
Possible
GPT7_UDF
GPT32E7.GTCNT underflow
TCFPU
Possible
GPT8_CCMPA
GPT328.GTCCRA input capture/compare match
TCFA
Possible
GPT8_CCMPB
GPT328.GTCCRB input capture/compare match
TCFB
Possible
GPT8_CMPC
GPT328.GTCCRC compare match
TCFC
Possible
GPT8_CMPD
GPT328.GTCCRD compare match
TCFD
Possible
GPT8_CMPE
GPT328.GTCCRE compare match
TCFE
Possible
GPT8_CMPF
GPT328.GTCCRF compare match
TCFF
Possible
GPT8_OVF
GPT328.GTCNT overflow (GPT328.GTPR compare match)
TCFPO
Possible
GPT8_UDF
GPT328.GTCNT underflow
TCFPU
Possible
GPT9_CCMPA
GPT329.GTCCRA input capture/compare match
TCFA
Possible
GPT9_CCMPB
GPT329.GTCCRB input capture/compare match
TCFB
Possible
GPT9_CMPC
GPT329.GTCCRC compare match
TCFC
Possible
GPT9_CMPD
GPT329.GTCCRD compare match
TCFD
Possible
GPT9_CMPE
GPT329.GTCCRE compare match
TCFE
Possible
GPT9_CMPF
GPT329.GTCCRF compare match
TCFF
Possible
GPT9_OVF
GPT329.GTCNT overflow (GPT329.GTPR compare match)
TCFPO
Possible
GPT9_UDF
GPT329.GTCNT underflow
TCFPU
Possible
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Table 23.22
23. General PWM Timer (GPT)
Interrupt sources (4 of 4)
Channel
Name
Interrupt source
Interrupt flag
DMAC/DTC
activation
10
GPT10_CCMPA
GPT3210.GTCCRA input capture/compare match
TCFA
Possible
GPT10_CCMPB
GPT3210.GTCCRB input capture/compare match
TCFB
Possible
GPT10_CMPC
GPT3210.GTCCRC compare match
TCFC
Possible
GPT10_CMPD
GPT3210.GTCCRD compare match
TCFD
Possible
GPT10_CMPE
GPT3210.GTCCRE compare match
TCFE
Possible
GPT10_CMPF
GPT3210.GTCCRF compare match
TCFF
GPT10_OVF
GPT3210.GTCNT overflow (GPT3210.GTPR compare match) TCFPO
Possible
GPT10_UDF
GPT3210.GTCNT underflow
Possible
11
12
13
(1)
TCFPU
Possible
GPT11_CCMPA
GPT3211.GTCCRA input capture/compare match
TCFA
Possible
GPT11_CCMPB
GPT3211.GTCCRB input capture/compare match
TCFB
Possible
GPT11_CMPC
GPT3211.GTCCRC compare match
TCFC
Possible
GPT11_CMPD
GPT3211.GTCCRD compare match
TCFD
Possible
GPT11_CMPE
GPT3211.GTCCRE compare match
TCFE
Possible
GPT11_CMPF
GPT3211.GTCCRF compare match
TCFF
Possible
GPT11_OVF
GPT3211.GTCNT overflow (GPT3211.GTPR compare match)
TCFPO
Possible
GPT11_UDF
GPT3211.GTCNT underflow
TCFPU
Possible
GPT12_CCMPA
GPT3212.GTCCRA input capture/compare match
TCFA
Possible
GPT12_CCMPB
GPT3212.GTCCRB input capture/compare match
TCFB
Possible
GPT12_CMPC
GPT3212.GTCCRC compare match
TCFC
Possible
GPT12_CMPD
GPT3212.GTCCRD compare match
TCFD
Possible
GPT12_CMPE
GPT3212.GTCCRE compare match
TCFE
Possible
GPT12_CMPF
GPT3212.GTCCRF compare match
TCFF
Possible
GPT12_OVF
GPT3212.GTCNT overflow (GPT3212.GTPR compare match) TCFPO
Possible
GPT12_UDF
GPT3212.GTCNT underflow
TCFPU
Possible
GPT13_CCMPA
GPT3213.GTCCRA input capture/compare match
TCFA
Possible
GPT13_CCMPB
GPT3213.GTCCRB input capture/compare match
TCFB
Possible
GPT13_CMPC
GPT3213.GTCCRC compare match
TCFC
Possible
GPT13_CMPD
GPT3213.GTCCRD compare match
TCFD
Possible
GPT13_CMPE
GPT3213.GTCCRE compare match
TCFE
Possible
GPT13_CMPF
GPT3213.GTCCRF compare match
TCFF
Possible
GPT13_OVF
GPT3213.GTCNT overflow (GPT3213.GTPR compare match) TCFPO
Possible
GPT13_UDF
GPT3213.GTCNT underflow
Possible
TCFPU
GPTn_ADTRGA interrupt (n = 0 to 7)
When the GTCNT counter value matches with the GTADTRA register, an interrupt request is generated under the
following conditions:
In up-counting, the interrupt enable bit (ADTRAUEN) in the GTINTAD register is 1
In down-counting, the interrupt enable bit (ADTRADEN) in the GTINTAD register is 1.
In event count operation, this interrupt request is not generated.
(2)
GPTn_ADTRGB interrupt (n = 0 to 7)
When the GTCNT counter value matches with the GTADTRB register, an interrupt request is generated under the
following conditions:
In up-counting, the interrupt enable bit (ADTRBUEN) in the GTINTAD register is 1
In down-counting, the interrupt enable bit (ADTRBDEN) in the GTINTAD register is 1.
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23. General PWM Timer (GPT)
In event count operation, this interrupt request is not generated.
(3)
GPTn_CCMPA interrupt (n = 0 to 13)
An interrupt request is generated under the following conditions:
When the GTCCRA register functions as a compare match register, the GTCNT counter value matches with the
GTCCRA register.
When the GTCCRA register functions as an input capture register, the input-capture signal causes transfer of the
GTCNT counter value to the GTCCRA register.
(4)
GPTn_CCMPB interrupt (n = 0 to 13)
An interrupt request is generated under the following conditions:
When the GTCCRB register functions as a compare match register, the GTCNT counter value matches with the
GTCCRB register
When the GTCCRB register functions as an input capture register, the input-capture signal causes transfer of the
GTCNT counter value to the GTCCRB register.
(5)
GPTn_CMPC interrupt (n = 0 to 13)
An interrupt request is generated under the following condition:
When the GTCCRC register functions as a compare match register, the GTCNT counter value matches with the
GTCCRC register.
A compare match is not performed and an interrupt is not requested under the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 01b, 10b, 11b (buffer operation with the GTCCRC register).
(6)
GPTn_CMPD interrupt (n = 0 to 13)
An interrupt request is generated under the following condition:
When the GTCCRD register functions as a compare match register, the GTCNT counter value matches with the
GTCCRD register.
A compare match is not performed and an interrupt is not requested under the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 10b, 11b (buffer operation with the GTCCRD register).
(7)
GPTn_CMPE interrupt (n = 0 to 13)
An interrupt request is generated under the following condition.
When the GTCCRE register functions as a compare match register, the GTCNT counter value matches with the
GTCCRE register.
A compare match is not performed and an interrupt is not requested under the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 01b, 10b, 11b (buffer operation with the GTCCRE register).
(8)
GPTn_CMPF interrupt (n = 0 to 13)
An interrupt request is generated under the following condition:
When the GTCCRF register functions as a compare match register, the GTCNT counter value matches with the
GTCCRF register.
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23. General PWM Timer (GPT)
A compare match is not performed and an interrupt is not requested under the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 10b, 11b (buffer operation with the GTCCRF register).
(9)
GPTn_OVF interrupt (n = 0 to 13)
An interrupt request is generated under the following conditions:
In saw-wave mode, interrupt requests are enabled at overflows (when the GTCNT counter value changes from
GTPR to 0 during up-counting)
In triangle-wave mode, interrupt requests are enabled at crests (GTCNT changes from GTPR to GTPR-1)
In counting by hardware sources, overflow (GTCNT changes from GTPR to 0 in up count) has occurred.
(10) GPTn_UDF interrupt (n = 0 to 13)
An interrupt request is generated under the following conditions:
In saw-wave mode, interrupt requests are enabled at underflows (when the GTCNT counter value changes from 0 to
GTPR during down-counting)
In triangle-wave mode, interrupt requests are enabled at troughs (GTCNT changes from 0 to 1)
In counting by hardware sources, underflow (GTCNT changes from 0 to GTPR in down count) has occurred.
Table 23.23
Interrupt signals, interrupt permission bits, and interrupt status flags
Interrupt signal
Interrupt permission bit
Interrupt status flag
GPTn_UDF
— *1
GTST[7] (TCFPU)
GPTn_OVF
GTST[6] (TCFPO)
GPTn_ADTRGB
GTINTAD[19] (ADTRBDEN)
GTINTAD[18] (ADTRBUEN)
GTST[19] (ADTRBDF)
GTST[18] (ADTRBUF)
GPTn_ADTRGA
GTINTAD[17] (ADTRADEN)
GTINTAD[16] (ADTRAUEN)
GTST[17] (ADTRADF)
GTST[16] (ADTRAUF)
GPTn_CMPF
— *1
GTST[5] (TCFF)
GPTn_CMPE
GTST[4] (TCFE)
GPTn_CMPD
GTST[3] (TCFD)
GPTn_CMPC
GTST[2] (TCFC)
GPTn_CCMPB
GTST[1] (TCFB)
GPTn_CCMPA
GTST[0] (TCFA)
Note 1.
23.4.2
Interrupt is always permitted.
DMAC/DTC Activation
The DMAC and DTC can be activated by the interrupt in each channel. For details, see section 14, Interrupt Controller
Unit (ICU), and section 18, Data Transfer Controller (DTC).
23.4.3
Interrupt and A/D Conversion Request Skipping Function
By setting the GTITC register, the GTCNT counter overflow (GTPR compare match) interrupt (GPTn_OVF) and
underflow interrupt (GPTn_UDF) can be skipped. Other interrupts and A/D converter start request signals can be
skipped in coordination with the GPTn_OVF/GPTn_UDF skipping function.
The interrupt request skipping function only depends on the setting of GTITC register and is independent of the setting of
interrupt permission bits in the GTINTAD register.
When both troughs and crests are counted and skipped in triangle-wave mode, if the number of times of skipping is odd,
GPTn_OVF/GPTn_UDF interrupt requests cannot be generated at troughs only or at crests only depending on the
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23. General PWM Timer (GPT)
skipping counter start timing. To count both troughs and crests and generate the GPTn_OVF/GPTn_UDF interrupts at
troughs only or crests only in triangle-wave mode, you must set an even number of skips.
Similarly, in saw-wave mode, when both overflows and underflows are counted and skipped with the count direction
changed, GPTn_OVF interrupt requests cannot be generated on either overflows or underflows only. To count both
overflows and underflows with the count direction changed and generate the GPTn_OVF/GPTn_UDF interrupts on
either overflows or underflows only in saw wave mode, you must first check the skipping state.
Before changing the skipping count, you must release the skipping count setting (GTITC.IVTC[1:0] bits = 00b).
Figure 23.86 to Figure 23.91 show examples of skipping function operation.
GTCNT counter value
GTPR register
0000 0000h
Time
Skipped interrupt request
GPTn_OVF interrupt request at crest
GPTn_UDF interrupt request at trough
GPTn_OVF/GPTn_UDF interrupt request at
both crest and trough
Interrupt request generated during
up-counting
Interrupt request generated during
down-counting
Interrupt request generated during both
up-counting and down-counting
GTST.ITCNT[2:0]
(skipping counter)
Figure 23.86
Example of interrupt skipping function operation with triangle waves, counting and skipping
crests, and skipping count = 2
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23. General PWM Timer (GPT)
GTCNT counter value
GTPR register
0000 0000h
Time
Skipped interrupt request
GPTn_OVF interrupt request at crest
GPTn_UDF interrupt request at trough
GPTn_OVF/GPTn_UDF interrupt request at
both crest and trough
Interrupt request generated
during up-counting
Interrupt request generated
during down-counting
Interrupt request generated during
both up-counting and down-counting
GTST.ITCNT[2:0]
(skipping counter)
Figure 23.87
Example of interrupt skipping function operation with triangle waves, counting and skipping
troughs, and skipping count = 3
GTCNT counter value
GTPR register
0000 0000h
Time
Skipped interrupt request
GPTn_OVF interrupt request at crest
GPTn_UDF interrupt request at trough
GPTn_OVF/GPTn_UDF interrupt request at
both crest and trough
Interrupt request generated
during up-counting
Interrupt request generated
during down-counting
Interrupt request generated during
both up-counting and down-counting
GTST.ITCNT[2:0]
(skipping counter)
Figure 23.88
Example of interrupt skipping function operation with triangle waves, counting and skipping both
troughs and crests, and skipping count = 4
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23. General PWM Timer (GPT)
GTCNT counter value
GTPR register
0000 0000h
Time
Skipped interrupt request
GPTn_OVF interrupt request at crest
GPTn_UDF interrupt request at trough
GPTn_OVF/GPTn_UDF interrupt request at
both crest and trough
Interrupt request generated
during up-counting
Interrupt request generated
during down-counting
Interrupt request generated during
both up-counting and down-counting
GTST.ITCNT[2:0]
(skipping counter)
Figure 23.89
Example of interrupt skipping function operation with triangle waves, counting and skipping both
troughs and crests, skipping count = 3, and skipping started at up-counting
GTCNT counter value
GTPR register
0000 0000h
Time
Skipped interrupt request
GPTn_OVF interrupt request at crest
GPTn_UDF interrupt request at trough
GPTn_OVF/GPTn_UDF interrupt request at
both crest and trough
Interrupt request generated
during up-counting
Interrupt request generated
during down-counting
Interrupt request generated during
both up-counting and down-counting
GTST.ITCNT[2:0]
(skipping counter)
Figure 23.90
Example of interrupt skipping function operation with triangle waves, counting and skipping both
troughs and crests, skipping count = 3, and skipping started at down-counting
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23. General PWM Timer (GPT)
GTCNT counter value
GTPR register
0000 0000h
Time
Skipped interrupt request
Interrupt request generated at
overflow
Interrupt request generated at
underflow
Interrupt request generated at both
overflow and underflow
Interrupt request generated
during counting
GTST.ITCNT[2:0]
(Skipping counter)
Figure 23.91
23.5
Example of interrupt skipping function operation with saw waves, operation with count direction
changed, counting and skipping both overflows and underflows, and skipping count = 4
A/D Converter Start Request
An A/D converter start request can be issued at a compare match between the GTCNT counter and GTADTRA or
GTADTRB, and up-counting only, down-counting only, or both up-counting and down-counting can be specified.
In event count operation performing, A/D converter start requests interrupt cannot be generated. An A/D converter start
request does not direct output to the A/D converter module but results in output to ELC as event signals.
GTADTRA and GTADTRB each have two buffer registers. Buffer operation with GTADTRA combined with
GTADTBRA and GTADTDBRA, and buffer operation with GTADTRB combined with GTADTBRB and
GTADTDBRB can be performed.
Figure 23.92 shows an example of A/D converter start request operation, and Figure 23.93 shows an example setting for
A/D converter start request operation.
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23. General PWM Timer (GPT)
GTCNT counter value
GTPR register
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GTADTDBRA register
dddd
aaaa
dddd
Buffer transfer
at trough
GTADTRA register
aaaa
Register write
GTADTDBRB register
Register write
cccc
Buffer transfer
at trough
GTADTBRA register
Register write
Buffer transfer
at crest
Buffer transfer
at trough
Buffer transfer
at crest
Buffer transfer
at trough
Buffer transfer
at crest
cccc
Buffer transfer
at crest
dddd
Register write
cccc
Register write
Register write
bbbb
Buffer transfer
at trough
GTADTBRB register
Buffer transfer
at trough
Buffer transfer
at crest
Buffer transfer
at crest
bbbb
Buffer transfer
at trough
Buffer transfer
at crest
bbbb
Buffer transfer
at trough
GTADTRB register
Buffer transfer
at crest
A/D converter
request A interrupt
A/D converter
request B interrupt
Figure 23.92
Example of A/D converter start request timing operation with triangle waves, double buffer
operation, buffer transfer at both troughs and crests, A/D converter start request interrupt by
GTADTRA at both up-counting and down-counting, and A/D converter start request interrupt by
GTADTRB at down-counting
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23. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 23.92, 100b, 101b, or 110b (triangle-wave PWM mode) is set.
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set buffer operation
Set buffer operation with ADTTA[1:0], ADTTB[1:0], ADTDA, and ADTDB in GTBER.
In Figure 23.92, ADTTA[1:0] = 11b, ADTTB[1:0] = 11b, ADTDA = 1, and ADTDB =
1.
Set compare match value
Set the A/D converter start request points in GTADTRA and GTADTRB.
Set buffer value
For buffer operation, set the A/D converter start request points in 1 cycle after the
current cycle (in saw-wave mode or triangle-wave mode with buffer transfer at
trough or crest) or half cycle after the current cycle (in triangle-wave mode with
buffer transfer at both trough and crest) in GTADTBRA and GTADTBRB.
For double buffer operation, also set the A/D converter start request points in 2
cycles after the current cycle (in saw-wave mode or triangle-wave mode with buffer
transfer at trough or crest) or 1 cycle after the current cycle (in triangle-wave mode
with buffer transfer at both trough and crest) in GTADTDBRA and GTADTDBRB.
Enable A/D converter start request interrupt
Set to enable an A/D converter start request interrupt with ADTRAUEN,
ADTRADEN, ADTRBUEN, and ADTRBDEN in GTINTAD.
In Figure 23.92, ADTRAUEN = 1, ADTRADEN = 1, ADTRBUEN = 0, and
ADTRBDEN = 1.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the A/D converter start request points in 1 cycle after the
current cycle (in saw-wave mode or triangle-wave mode with buffer transfer at
trough or crest) or half cycle after the current cycle (in triangle-wave mode with
buffer transfer at both trough and crest) in GTADTBRA and GTADTBRB.
For double buffer operation, set the A/D converter start request points in 2 cycles
after the current cycle (in saw-wave mode or triangle-wave mode with buffer
transfer at trough or crest) or 1 cycle after the current cycle (in triangle-wave mode
with buffer transfer at both trough and crest) in GTADTDBRA and GTADTDBRB.
Figure 23.93
Example setting for A/D converter start request timing operation
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23.6
23.6.1
23. General PWM Timer (GPT)
Operations Linked by the ELC
Event Signal Output to the ELC
The GPT can perform operation linked with another module set in advance when its interrupt request signal is used as an
event signal by the ELC.
A/D converter start requests can be enabled and disabled individually with each up-counting and down-counting for both
interrupts and events output to ELC by enable bits of the interrupt request.
The GPT has the following ELC event signals:
Generating of compare match A interrupt (GPTn_CCMPA (n = 0 to 13))
Generating of compare match B interrupt (GPTn_CCMPB (n = 0 to 13))
Generating of compare match C interrupt (GPTn_CMPC (n = 0 to 13))
Generating of compare match D interrupt (GPTn_CMPD (n = 0 to 13))
Generating of compare match E interrupt (GPTn_CMPE (n = 0 to 13))
Generating of compare match F interrupt (GPTn_CMPF (n = 0 to 13))
Generating of overflow interrupt (GPTn_OVF (n = 0 to 13))
Generating of underflow interrupt (GPTn_UDF (n = 0 to 13))
A/D converter start request A interrupt (GPTn_ADTRGA (n = 0 to 7))
A/D converter start request B interrupt (GPTn_ADTRGB (n = 0 to 7)).
23.6.2
Event Signal Inputs from the ELC
The GPT can perform the following operations in response to a maximum of eight events from the ELC:
Start counting, stop counting, clear counting
Up-counting, down counting
Input capture.
See section 23.3, Operation for detail on hardware resources.
23.7
Noise Filter Function
Each pin for use in input capture and Hall sensor input to the GPT is equipped with a noise filter. The noise filter samples
input signals at the sampling clock and removes the pulses whose length is less than 3 sampling cycles.
The noise filter functionality includes enabling and disabling the noise filter for each pin and setting of the sampling
clock for each channel.
Figure 23.94 shows the timing of noise filtering.
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23. General PWM Timer (GPT)
Sampling clock
Noise filter enable/
disable register
Input capture input pin or
external trigger input pin
Eliminated
pulse
Matching
three times
Signal conveyed
internally
Noise filter disabled
Figure 23.94
Noise filter enabled
Timing of noise filtering
If noise filtering is enabled, the input capture operation or external trigger operation performs on the edges of the noise
filtered signal after a delay of a sampling interval × 3 + PCLKD. This is caused by the noise filtering for the input capture
input or external trigger operation.
23.8
23.8.1
Protection Function
Write-Protection for Registers
To prevent registers from being accidentally modified, registers can be write-protected in channel units by setting
GTWP.WP. Write-protection can be set for the following registers:
GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTICASR, GTICBSR, GTCR, GTUDDTYC, GTIOR,
GTINTAD,GTST, GTBER, GTITC, GTCNT, GTCCRA, GTCCRB, GTCCRC, GTCCRD, GTCCRE, GTCCRF, GTPR,
GTPBR, GTPDBR, GTADTRA, GTADTBRA, GTADTDBRA, GTADTRB, GTADTBRB, GTADTDBRB, GTDTCR,
GTDVU, GTDVD, GTDBU, GTDBD, GTSOS, GTSOTR.
23.8.2
Disabling of Buffer Operation
If the timing of buffer register write is delayed relative to the timing for the buffer transfer, buffer operation can be
suspended with the GTBER.BD setting. Buffer transfer can be temporarily disabled even when a buffer transfer
condition is generated during a buffer register write. This can be done by setting the associated GTBER.BD bit to 1
(buffer operation disabled) before a buffer register write and clearing the bit to 0 (buffer operation enabled) after
completion of writing to all buffer registers. Figure 23.95 shows an example of operation for disabling buffer operation.
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GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
0000 0000h
Time
Register write timing is too late
for buffer transfer timing
Register write
GPT32EH0.GTCCRF register
bbbb
cccc
Buffer transfer at trough
GPT32EH0.GTCCRE register
aaaa
Buffer transfer at crest
bbbb
Buffer transfer at trough
eeee
Buffer transfer at crest
cccc
eeee
Buffer transfer at crest
aaaa
GPT32EH0.GTCCRB register
dddd
Register write
Buffer transfer at crest
bbbb
cccc
GTBER.BD[0]
Set to 1 before
GPT32EH0.GTCCRF
register is written
Set to 1 before
GPT32EH0.GTCCRF
register is written
Cleared to 0 after
GPT32EH0.GTCCRF
register is written
Buffer transfer not performed
when GTBER.BD0 = 1
Figure 23.95
23.8.3
Cleared to 0 after
GPT32EH0.GTCCRF
register is written
Cleared to 0 after
GPT32EH0.GTCCRF
register is written
Set to 1 before
GPT32EH0.GTCCRF
register is written
Set to 1 before
GPT32EH0.GTCCRF
register is written
Cleared to 0 after
GPT32EH0.GTCCRF
register is written
Example of operation for disabling buffer operation with triangle waves, double buffer operation,
and buffer transfer at both troughs and crests
GTIOC Pin Output Negate Control
For protection from system failure, the output disable control that changes the GTIOC pin output value forcibly is
provided for GTIOC pin output by the request of output disable from POEG.
When dead time error occurs or the GTIOCA pin output value is the same as the GTIOCB pin output value, output
protection is required. The GPT detects this condition and generates output disable requests to POEG based on the
settings in the output disable request permission bits, such as GTINTAD.GRPDTE, GTINTAD.GRPABH, and
GTINTAD.GRPABL. After the POEG receives output disable requests from each channel and calculates external input
using an OR operation, the POEG generates output disable requests to GPT.
One output disable signal (representing the shared output disable request signal of the GTIOCA pin and the GTIOCB
pin) out of four output disable requests generated by the POEG is selected by setting GTINTAD.GRP[1:0]. The status of
the selected disable output request is monitored by reading the GTST.ODF bit. The output level during output disable is
based on the GTIOR.OADF[1:0] setting for the GTIOCA pin and the GTIOR.OBDF[1:0] setting for the GTIOCB pin.
The change to the output disable state is performed asynchronously by generating the output disable request from the
POEG. The release of the output disable state is performed at end of cycle by terminating the output disable request. The
timing of release of the output disable state is a minimum of 3 PCLKD cycles after terminating the output disable
request. To perform output disable control reliably, allow at least 4 PCLKD cycles after generating the output disable
request (by clearing the output disable request flag in POEG) until the output disable request is terminated.
When event count is performed or when the output disable state is to be released immediately without waiting for an end
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23. General PWM Timer (GPT)
of cycle, GTIOR.OADF[1:0] must be set to 00b (for GTIOCA pin) or GTIOR.OBDF[1:0] must be set to 00b (for
GTIOCB pin).
Figure 23.96 shows an example of the GTIOC pin output disable control operation.
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT32EH0.GTCCRC register
Register write
Register write
bbbb
cccc
Buffer transfer
at overflow
GPT32EH0.GTCCRA register
aaaa
Register write
Buffer transfer
at overflow
bbbb
Buffer transfer
at overflow
cccc
Negate control source
GTIOC0A pin output
GTIOC pin output low forcibly when the output
disable source is requested
Figure 23.96
23.8.4
Example of GTIOC pin output disable control operation with saw-wave up-counting, buffer
operation, active level 1, high output at GTCCRA compare match, low output at cycle end, and
low output at output disable
Output Protection Function for GTIOC Pin Output
In preparation for incorrect settings of the GTCCRA register (settings outside the range of 0 < GTCCRA < GTPR), the
output protection function for the GTIOC pin output (disabling function) is activated when the automatic dead time
setting (GTDTCR.TDE = 1) is made in triangle-wave mode. The status of the output protection function can be read
from GTSOS.SOS[1:0].
Figure 23.97 shows the output protection function state transition.
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23. General PWM Timer (GPT)
0 GTCCRA GTPR
or counting is stopped or
GTDTCR.TDE = 0
0 GTCCRA GTPR
or counting is stopped or
GTDTCR.TDE = 0
Normal state (not in output protected state)
(GTSOS.SOS[1:0] = 00b)
GTCCRA = 0 during
buffer transfer
GTCCRA
GTPR during buffer
transfer at trough
0 GTCCRA GTPR
or counting is stopped or
GTDTCR.TDE = 0
Output protected state
(GTSOS.SOS[1:0] = 01b)
GTCCRA
GTPR during
buffer transfer
at crest
Output protected state
(GTSOS.SOS[1:0] = 11b)
Output protected state
(GTSOS.SOS[1:0] = 10b)
Figure 23.97
Output protection function
23.8.4.1
Output protection function when the GTCCRA register is set to 0 during buffer
transfer
Figure 23.98 and Figure 23.99 show examples of output protection function operation when the GTCCRA register is set
to 0 during buffer transfer at troughs, and Figure 23.100 and Figure 23.101 show examples when the GTCCRA register
is set to 0 during buffer transfer at crests.
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
Time
0000 0000h
Correction to
secure dead time
GTIOC0A pin output
(active-low)
GTDVU
From the trough,
signals change after
one count-clock
GTIOC0B pin output
(active-low)
GTSOS.SOS[1:0]
bits
00
01
(1) Normal operation (2)
Transition
(1) Normal operation period:
(2) Transition period:
(3) Output holding period:
(4) Recovery period:
(5) Normal operation period:
Figure 23.98
(3) Output holding
00
(4)
Recovery
(5) Normal operation
Toggle output due to a compare match is performed normally.
When GTCCRA register = 0 is detected in the trough, the output protection status changes to
GTSOS.SOS[1:0] bits = 01b, and toggle output is continued up to the next crest.
The output is held while GTCCRA register = 0.
When 0 < GTCCRA register < GTPR register is detected in the trough, the output protection
status changes to GTSOS.SOS[1:0] bits = 00b, and holding output is maintained up to the
next crest.
Toggle output due to a compare match is performed normally.
Example of output protection operation when GTCCRA is set to 0 during buffer transfer at
troughs, with 0 < GTCCRA < GTPR restored during buffer transfer at troughs, and active-low
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GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
Time
0000 0000h
Correction to
secure dead time
GTIOC0A pin output
(active-low)
GTDVU
GTIOC0B pin output
(active-low)
GTSOS.SOS[1:0]
bits
From the trough, signals change
after one count clock
00
01
00
From the crest, signals change after one
count clock
(1) Normal operation
(1) Normal operation period:
(2) Transition period:
(3) Output holding
(4) Normal operation
Toggle output due to a compare match is performed normally.
When GTCCRA register = 0 is detected in the trough, the output protection status changes to
GTSOS.SOS[1:0] bits = 01b, and toggle output is continued up to the next crest.
The output is held while GTCCRA register = 0.
When 0 < GTCCRA register < GTPR register is detected in the crest, the output protection
status changes to GTSOS.SOS[1:0] bits = 00b, and toggle output due to a compare match is
performed normally.
(3) Output holding period:
(4) Normal operation period:
Figure 23.99
(2)
Transition
Example of output protection operation when GTCCRA is set to 0 during buffer transfer at
troughs, with 0 < GTCCRA < GTPR restored during buffer transfer at crests, and active-low
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
0000 0000h
Time
Correction to secure
dead time
GTIOC0A pin output
(active-low)
GTDVD GTDVU
GTIOC0B pin output
(active-low)
GTSOS.SOS[1:0]
bits
A pulse of one count
clock cycle is generated
00
01
(1) Normal operation
(1) Normal operation period:
(2) Transition period:
(3) Output holding period:
(4) Recovery period:
(5) Normal operation period:
Figure 23.100
00
From the trough, signals change after
one count clock
(2)
Transition
(3) Output holding
(4)
Recovery
(5) Normal operation
Toggle output due to a compare match is performed normally.
When GTCCRA register = 0 is detected in the trough, the output protection status changes to
GTSOS.SOS[1:0] bits = 01b, and toggle output is continued up to the next crest.
The output is held while GTCCRA register = 0.
When 0 < GTCCRA register < GTPR register is detected in the trough, the output protection
status changes to GTSOS.SOS[1:0] bits = 00b, and holding output is maintained up to the
next crest.
Toggle output due to a compare match is performed normally.
Example of output protection operation when GTCCRA is set to 0 during buffer transfer at crests,
with 0 < GTCCRA < GTPR restored during buffer transfer at troughs, and active-low
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
0000 0000h
GTIOC0A pin output
(active-low)
Time
Correction to secure
dead time
GTDVD GTDVU
GTIOC0B pin output
(active-low)
GTSOS.SOS[1:0]
bits
A pulse of one count
clock cycle is generated
00
01
From the trough, signals change after
one count clock
(1) Normal operation
(1) Normal operation period:
(2) Transition period:
(3) Output holding period:
(4) Normal operation period:
(2)
Transition
(3) Output holding
00
From the crest, signals change
after one count clock
(4) Normal operation
Toggle output due to a compare match is performed normally.
When GTCCRA register = 0 is detected in the trough, the output protection status changes to
GTSOS.SOS[1:0] bits = 01b, and toggle output is continued up to the next crest.
The output is held while GTCCRA register = 0.
When 0 < GTCCRA register < GTPR register Is detected in the crest, the output protection
status changes to GTSOS.SOS[1:0] bits = 00b, and toggle output due to a compare match is
performed normally.
Figure 23.101
Example of output protection operation when GTCCRA is set to 0 during buffer transfer at crests,
with 0 < GTCCRA < GTPR restored during buffer transfer at crests, and active-low
23.8.4.2
Output protection function when GTCCRA ≥ GTPR is set during buffer transfer
at troughs
Figure 23.102 and Figure 23.103 show examples of output protection function operation when GTCCRA ≥ GTPR is set
during buffer transfer at troughs.
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GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
(active-low)
GTIOC0B pin output
(active-low)
GTSOS.SOS[1:0]
bits
00
(1) Normal operation
10
From the trough, signals change after
one count clock
(2) Output holding
00
(3) Normal operation
(1) Normal operation period: Toggle output due to a compare match is performed normally.
(2) Output holding period:
When GTCCRA register GTPR register is detected in the trough, the output protection status
changes to GTSOS.SOS[1:0] bits = 10b, and the output is held while GTCCRA register GTPR
register.
(3) Normal operation period: When 0 < GTCCRA register < GTPR register is detected in the trough, the output protection
status changes to GTSOS.SOS[1:0] bits = 00b, and toggle output due to a compare match is
performed normally.
Figure 23.102
Example of output protection operation when GTCCRA ≥ GTPR is set during buffer transfer at
troughs, with 0 < GTCCRA < GTPR restored during buffer transfer at troughs, and active-low
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
Time
0000 0000h
GTIOC0A pin output
(active-low)
GTIOC0B pin output
(active-low)
GTSOS.SOS[1:0]
bits
00
(1) Normal operation
10
From the trough, signals change after
one count clock
(2) Output holding
00
From the crest, signals change after
one count clock
(4) Normal operation
(3)
Recovery
(1) Normal operation period: Toggle output due to a compare match is performed normally.
(2) Output holding period:
When GTCCRA register GTPR register is detected in the trough, the output protection status
changes to GTSOS.SOS[1:0] bits = 10b, and the output is held while GTCCRA register GTPR
register.
(3) Recovery period:
When 0 < GTCCRA register < GTPR register is detected in the crest, the output protection
status changes to GTSOS.SOS[1:0] bits = 00b, and holding output is maintained up to the next
trough.
(4) Normal operation period: Toggle output due to a compare match is performed normally.
Figure 23.103
Example of output protection operation when GTCCRA ≥ GTPR is set during buffer transfer at
troughs, with 0 < GTCCRA < GTPR restored during buffer transfer at crests, and active-low
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23.8.4.3
23. General PWM Timer (GPT)
Output protection function when GTCCRA ≥ GTPR is set during buffer transfer
at crests
Figure 23.104 and Figure 23.105 show examples of output protection function operation when GTCCRA ≥ GTPR is set
during buffer transfer at crests.
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
(active-low)
GTIOC0B pin output
(active-low)
From the crest,
signals change after
one count clock
GTSOS.SOS[1:0]
bits
00
(1) Normal operation
11
(2) Output holding
00
(3) Normal operation
(1) Normal operation period: Toggle output due to a compare match is performed normally.
(2) Output holding period:
When GTCCRA register GTPR register is detected in the crest, the output protection status
changes to GTSOS.SOS[1:0] bits = 11b, and the output is held while GTCCRA register GTPR
register.
(3) Normal operation period: When 0 < GTCCRA register < GTPR register is detected in the crest, the output protection
status changes to GTSOS.SOS[1:0] bits = 00b, and toggle output due to a compare match is
performed normally.
Figure 23.104
Example of output protection operation when GTCCRA ≥ GTPR is set during buffer transfer at
crests, with 0 < GTCCRA < GTPR restored during buffer transfer at crests, and active-low
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23. General PWM Timer (GPT)
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
Time
0000 0000h
GTIOC0A pin output
(active-low)
GTIOC0B pin output
(active-low)
From the crest,
signals change after
one count clock
GTSOS.SOS[1:0]
bits
00
11
00
From the trough, signals change
after one count clock
(1) Normal operation
(2) Output holding
(3)
Recovery
(4) Normal operation
(1) Normal operation period: Toggle output due to a compare match is performed normally.
When GTCCRA GTPR is detected in the crest, the output protection status changes to
(2) Output holding period:
GTSOS.SOS[1:0] = 11b, and the output is held while GTCCRA GTPR.
(3) Recovery period:
When 0 < GTCCRA < GTPR is detected in the trough, the output protection status changes to
GTSOS.SOS[1:0] = 00b, and holding output is maintained up to the next crest.
(4) Normal operation period: Toggle output due to a compare match is performed normally.
Figure 23.105
Example of output protection function operation when GTCCRA ≥ GTPR is set during buffer
transfer at crests, with 0 < GTCCRA < GTPR restored during buffer transfer at troughs, and
active-low
23.8.4.4
Restricted specification of output protection function
The value of the GTCCRA register must be set within the range of (0 < GTCCRA < GTPR) at count start. If an incorrect
value is set in the GTCCRA register during counting (a setting outside the range of 0 < GTCCRA < GTPR), the output
protection function deactivates the level of one of the positive and negative outputs.
The function does not operate correctly if the following conditions are not satisfied:
GTCCRA is 0 < GTCCRA < GTPR when counting starts
The register conditions must be GTCCRA < GTPR + GTDVD - 1 during buffer transfer at crests
When GTCCRA is greater than or equal to GTPR during buffer transfer at troughs, the register conditions must be
GTCCRA > GTDVU + 1.
23.8.4.5
Temporary cancellation of output protection function
When the GTSOTR.SOTR bit is set to 1 with GTSOS.SOS[1:0] bits equal to 10b (showing output protection state by
GTCCRA ≥ GTPR during buffer transfer at troughs), the output protection function for GTIOCB pin is temporarily
canceled. GTSOS.SOS[1:0] bits retain the value of 10b even when the output protection function is canceled. When the
SOTR bit is set to 0, the output protection function for GTIOCB pin resumes.
Figure 23.106 shows examples of temporary cancellation of output protection function operation when the GTCCRA ≥
GTPR is set during buffer transfer at troughs.
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23. General PWM Timer (GPT)
GTCCRA - GTDVD GTCCRA - GTDVD
GTCCRA - GTDVU GTCCRA - GTDVU
GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
(active-low)
GTIOC0B pin output
(active-low)
Register write
Register write
GTSOTR.SOTR bit
GTSOS.SOS[1:0] bits
00
(1) Normal operation
10
From the crest, signals change after one count clock
(3) Output protection is released (4) Output holding
(2) Output holding
temporary
00
(5) Normal operation
(1) Normal operation period:
(2) Output holding period:
Toggle output due to a compare match is performed normally.
When GTCCRA register GTPR register is detected in the trough, the output protection status changes to
GTSOS.SOS[1:0] bits = 10b, and the output is held while GTCCRA register GTPR register.
If GTSOTR.SOTR is set to 1 during the output holding period, the GTIOCB output is holding until the first trough after
the setting.
(3) Output protection releasing period: After GTSOTR.SOTR is set to 1, the GTIOCB output is performed normally at the first trough after the setting.
If GTSOTR.SOTR is set to 0 during the output protection releasing period, the output is holding at the first trough after
the setting.
(4) Output holding period:
Until 0 < GTCCRA register < GTPR register is detected in the trough, the output is holding.
When 0 < GTCCRA register < GTPR register is detected in the trough, the output protection status changes to
(5) Normal operation period:
GTSOS.SOS[1:0] bits = 00b, and toggle output due to a compare match is performed normally.
Figure 23.106
23.9
23.9.1
Example of temporary cancellation of output protection function operation when GTCCRA ≥
GTPR is set during buffer transfer at troughs, with 0 < GTCCRA < GTPR restored during buffer
transfer at troughs, and active-low
Initialization Method of Output Pins
Pin Settings after Reset
The GPT registers are initialized at a reset. Start counting after selecting the port pin function with the PmnPFS register,
setting GTIOR.OAE and GTIOR.OBE bits, and outputting the GPT function to external pins.
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GPT32EH0.GTCNT counter value
GPT32EH0.GTPR register
GPT32EH0.GTCCRA register
GPT32EH0.GTCCRB register
0000 0000h
Time
Hi-Z
GTIOC0A pin output
Hi-Z
GTIOC0B pin output
Reset is released. GTIOR.OAE and OBE bits Count operation starts.
are set.
Reset
GPT initialization settings
Count operation
[Setting examples]
GTIOR.GTIOA[4:0] bits: Initial low output, output retained at cycle end, output toggled at compare match
GTIOR.GTIOB[4:0] bits: Initial high output, output retained at cycle end, output toggled at compare match
Figure 23.107
23.9.2
Example of pin settings after reset
Pin Initialization Caused by Error during Operation
If an error occurs during GPT operation, the following four types of pin processing can be performed before pin
initialization:
Set the OAHLD and OBHLD bits in GTIOR to 1 and retain the outputs at count stop
Set the OAHLD and OBHLD bits in GTIOR to 0, specify arbitrary output values in OADFLT and OBDFLT in
GTIOR, and output the arbitrary values on count stop
Set the pin to output an arbitrary value as a general output port by setting the PDR, PODR, and PmnPFS registers of
the I/O port in advance. Set the OAE and OBE bits in GTIOR to 0 and the control bit associated with the pin in the
PmnPFS.PMR to 0 to allow arbitrary values to be output from the pin set as a general output port when an error
occurs.
Drive the output to a high impedance state using the POEG function.
When the automatic dead time setting is made, clear the GTDTCR.TDE bit to 0 after counting stops. When counting
stops, only the values of registers that are changed by a GPT external source change. If counting resumes, operation
continues from where it stopped. If counting stops, registers must be initialized before counting starts.
23.10 Usage Notes
23.10.1
Module-Stop Function Setting
The Module Stop Control Register can enable or disable GPT operation. The GPT module is initially stopped after reset.
Releasing the module-stop state enables access to the registers. For details, see section 11, Low Power Modes.
23.10.2
(1)
GTCCRn Settings during Compare Match Operation (n = A to F)
When automatic dead time setting is made in triangle-wave PWM mode
The GTCCRA register must satisfy the following conditions: GTDVU < GTCCRA, GTDVD < GTCCRA, and
GTCCRA < GTPR.
When the setting of GTCCRA = 0 or GTCCRA ≥ GTPR is made during count operation, the output protection function
is activated.
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23. General PWM Timer (GPT)
However, the function does not operate correctly if the following conditions are not satisfied:
GTCCRA is 0 < GTCCRA < GTPR when counting starts
The register conditions must be GTCCRA < GTPR + GTDVD - 1 during buffer transfer at crests
When GTCCRA is greater than or equal to GTPR during buffer transfer at troughs, the register conditions must be
GTCCRA > GTDVU + 1.
For details, see section 23.8.4, Output Protection Function for GTIOC Pin Output.
(2)
When automatic dead time setting is not made in triangle-wave PWM mode
The GTCCRA register must be set within the range of 0 < GTCCRA < GTPR. If GTCCRA = 0 or GTCCRA = GTPR is
set, a compare match occurs within the cycle only when GTCCRA = 0 or GTCCRA = GTPR is satisfied. When
GTCCRA > GTPR, no compare match occurs.
Similarly, GTCCRB must be set within the range of 0 < GTCCRB < GTPR. If GTCCRB = 0 or GTCCRB = GTPR is set,
a compare match occurs within the cycle only when GTCCRB = 0 or GTCCRB = GTPR is satisfied. When GTCCRB >
GTPR, no compare match occurs.
(3)
When automatic dead time setting is made in saw-wave one-shot pulse mode
The GTCCRC and GTCCRD registers must be set to satisfy the following restrictions. If the restrictions are not satisfied,
correct output waveforms with secured dead time might not be obtained:
In up-counting: GTCCRC < GTCCRD, GTCCRC > GTDVU, GTCCRD < GTPR - GTDVD
In down-counting: GTCCRC > GTCCRD, GTCCRC < GTPR - GTDVU, GTCCRD > GTDVD.
(4)
When automatic dead time setting is not made in saw-wave one-shot pulse mode
The GTCCRC and GTCCRD registers must be set to satisfy the following restrictions. If the restrictions are not satisfied,
two compare matches do not occur and pulse output cannot be performed:
In up-counting: 0 < GTCCRC < GTCCRD < GTPR
In down-counting: GTPR > GTCCRC > GTCCRD > 0.
Similarly, GTCCRE and GTCCRF must be set to satisfy the following restrictions. If the restrictions are not satisfied,
two compare matches do not occur and pulse output cannot be performed:
In up-counting: 0 < GTCCRE < GTCCRF < GTPR
In down-counting: GTPR > GTCCRE > GTCCRF > 0.
(5)
In saw-wave PWM mode
The GTCCRA register must be set with the range of 0 < GTCCRA < GTPR. If GTCCRA = 0 or GTCCRA = GTPR is
set, a compare match occurs within the cycle only when GTCCRA = 0 or GTCCRA = GTPR is satisfied. If GTCCRA >
GTPR is set, no compare match occurs.
Similarly, GTCCRB must be set with the range of 0 < GTCCRB < GTPR. If GTCCRB = 0 or GTCCRB = GTPR is set, a
compare match occurs within the cycle only when GTCCRB = 0 or GTCCRB = GTPR is satisfied. If GTCCRB > GTPR
is set, no compare match occurs.
23.10.3
Setting Range for the GTCNT Counter
The GTCNT counter register must be set with the range of 0 ≤ GTCNT ≤ GTPR.
23.10.4
Starting and Stopping the GTCNT Counter
The control timing of starting and stopping the GTCNT counter by the GTCR.CST bit synchronizes the count clock that
is selected in GTCR.TPCS[2:0]. When GTCR.CST is updated, the GTCNT counter starts/stops after a count clock that is
selected in GTCR.TPCS[2:0]. Therefore, an event generated before the GTCNT counter actually starts is ignored. On the
other hand, there might be cases where an event is accepted or an interrupt occurs after GTCR.CST is set to 0.
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23.10.5
(1)
23. General PWM Timer (GPT)
Priority Order of Each Event
GTCNT register
Table 23.24 shows a priority order of events updating GTCNT register.
Table 23.24
Priority order of sources updating GTCNT
Source updating GTCNT
Writing by CPU (Writing to GTCNT/GTCLR)
Priority order
High
Clear by hardware sources set in GTCSR
Count up or down by hardware sources set in GTUPSR/GTDNSR
Count operation
Low
If up-counting and down-counting by hardware sources occur at the same time, the GTCNT counter value does not
change. When there is a conflict between updating the GTCNT register and reading by the CPU, pre-update data is read.
(2)
GTCR.CST bit
When there is a conflict between starting/stopping by hardware sources set in the GTSSR/GTPSR registers and writing
by the CPU (writing to GTCR/GTSTR/GTSTP registers), writing by CPU has priority over starting/stopping by
hardware sources.
When there is a conflict between starting by hardware sources set in the GTSSR register and stopping by hardware
sources set in GTPSR register, the GTCR.CST bit value does not change. Where there is a conflict between updating the
GTCR.CST bit and reading by the CPU, pre-update data is read.
(3)
GTCCRm registers (m = A to F)
When there is a conflict between input capture/buffer transfer operation and writing to GTCCRm registers, writing to
GTCCRm registers has priority over input capture/buffer transfer operation. When there is a conflict between input
capture and writing to the counter register by the CPU or updating the counter register by hardware sources, the preupdate counter value is captured. Where there is a conflict between updating the GTCCRm registers and reading by the
CPU, pre-update data is read.
(4)
GTPR registers
When there is a conflict between buffer transfer operation and writing to the GTPR register, writing to GTPR register has
priority over buffer transfer operation. When there is a conflict between updating GTPR register and reading by the CPU,
pre-update data is read.
(5)
GTADTRm registers (m = A, B)
When there is a conflict between buffer transfer operation and writing to the GTADTRm registers, writing to the
GTADTRm registers has priority over buffer transfer operation. When there is a conflict between updating GTADTRm
registers and reading by the CPU, pre-update data is read.
(6)
GTDVm registers (m = U, D)
When there is a conflict between buffer transfer operation and writing to GTDVm registers, writing to GTDVm registers
has priority over buffer transfer operation. When there is a conflict between updating GTDVm registers and reading by
the CPU, pre-update data is read.
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24. PWM Delay Generation Circuit
24.
PWM Delay Generation Circuit
24.1
Overview
The MCU has 4 channel delay circuits that can connect to the General PWM Timer (GPT). Table 24.1 lists the
specifications for the PWM Delay Generation Circuit, Figure 24.1 shows a block diagram, and Table 24.2 lists the I/O
pins.
Table 24.1
Specifications of the PWM Delay Generation Circuit
Parameter
Specifications
Function
The circuit can control the timing with which signals on the two PWM output pins for channel
0/1/2/3 rise and fall to an accuracy of up to 1/32 times the period of the GPT clock (PCLKD).
GPT32EH0
Delay Generation Circuit
GTIOCA
GTIOC0A
GTIOCB
GTIOC0B
Delay Generation Circuit
GPT32EH1
Delay Generation Circuit
GTIOCA
GTIOC1A
GTIOCB
GTIOC1B
Delay Generation Circuit
GPT32EH2
Delay Generation Circuit
GTIOCA
GTIOC2A
GTIOCB
GTIOC2B
Delay Generation Circuit
GPT32EH3
Delay Generation Circuit
GTIOCA
GTIOC3A
GTIOCB
GTIOC3B
Delay Generation Circuit
GPT32E4
GTIOCA
GTIOC4A
GTIOCB
GTIOC4B
:
:
GPT3213
Figure 24.1
GTIOCA
GTIOCnA
GTIOCB
GTIOCnB
PWM delay generation circuit block diagram
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Table 24.2
24. PWM Delay Generation Circuit
PWM delay generation circuit I/O pins
I/O pin
I/O
Function
GTIOC0A
Output
Delayed output of GTIOCA pin of GPT channel 0
GTIOC0B
Output
Delayed output of GTIOCB pin of GPT channel 0
GTIOC1A
Output
Delayed output of GTIOCA pin of GPT channel 1
GTIOC1B
Output
Delayed output of GTIOCB pin of GPT channel 1
GTIOC2A
Output
Delayed output of GTIOCA pin of GPT channel 2
GTIOC2B
Output
Delayed output of GTIOCB pin of GPT channel 2
GTIOC3A
Output
Delayed output of GTIOCA pin of GPT channel 3
GTIOC3B
Output
Delayed output of GTIOCB pin of GPT channel 3
24.2
Register Descriptions
24.2.1
PWM Output Delay Control Register (GTDLYCR)
Address(es): GPT_ODC.GTDLYCR 4007 B000h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b1
b0
DLYRS DLLEN
T
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DLLEN
DLL Operation Enable
0: DLL operation disabled
1: DLL operation enabled.
R/W
b1
DLYRST
PWM Delay Generation Circuit
Reset
0: Normal operation
1: Reset.
R/W
b15 to b2
—
Reserved
These bits are read as 0. The write value should be 0. R/W
The GTDLYCR register controls the PWM delay generation circuit, which applies delays to the PWM outputs.
GTDLYCR register can be written when register write protection is disabled (GPT32EH0.GTWP.WP = 0).
DLLEN bit (DLL Operation Enable)
The DLLEN bit selects whether the on-chip DLL in the PWM delay generation circuit is activated or not.
DLYRST bit (PWM Delay Generation Circuit Reset)
The DLYRST bit resets the internal state of the PWM delay generation circuit.
24.2.2
PWM Output Delay Control Register 2 (GTDLYCR2)
Address(es): GPT_ODC.GTDLYCR2 4007 B002h
Value after reset:
b15
b14
b13
b12
—
—
—
—
0
0
0
0
b11
b10
b9
b8
DLYEN DLYEN DLYEN DLYEN
3
2
1
0
0
0
0
0
b7
b6
b5
b4
—
—
—
—
0
0
0
0
b3
b2
b1
b0
DLYBS DLYBS DLYBS DLYBS
3
2
1
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DLYBS0
PWM Delay Generation Circuit
bypass for channel 0
0: Delay generation circuit of channel 0 bypassed
1: Delay generation circuit of channel 0 not bypassed.
R/W
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24. PWM Delay Generation Circuit
Bit
Symbol
Bit name
Description
R/W
b1
DLYBS1
PWM Delay Generation Circuit
bypass for channel 1
0: Delay generation circuit of channel 1 bypassed
1: Delay generation circuit of channel 1 not bypassed.
R/W
b2
DLYBS2
PWM Delay Generation Circuit
bypass for channel 2
0: Delay generation circuit of channel 2 bypassed
1: Delay generation circuit of channel 2 not bypassed.
R/W
b3
DLYBS3
PWM Delay Generation Circuit
bypass for channel 3
0: Delay generation circuit of channel 3 bypassed
1: Delay generation circuit of channel 3 not bypassed.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
DLYEN0
PWM Delay Generation Circuit
enable for channel 0
0: Delay generation circuit of channel 0 enabled
1: Delay generation circuit of channel 0 disabled.
R/W
b9
DLYEN1
PWM Delay Generation Circuit
enable for channel 1
0: Delay generation circuit of channel 1 enabled
1: Delay generation circuit of channel 1 disabled.
R/W
b10
DLYEN2
PWM Delay Generation Circuit
enable for channel 2
0: Delay generation circuit of channel 2 enabled
1: Delay generation circuit of channel 2 disabled.
R/W
b11
DLYEN3
PWM Delay Generation Circuit
enable for channel 3
0: Delay generation circuit of channel 3 enabled
1: Delay generation circuit of channel 3 disabled.
R/W
b15 to b12
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The GTDLYCR2 register controls each channel of PWM delay generation circuit. GTDLYCR2 can be written when
register write protection is disabled (GPT32EH0.GTWP.WP = 0).
DLYBSn (n = 0 to 3) bit (PWM Delay Generation Circuit Bypass for channel n)
The DLYBSn bit selects whether delays are applied to PWM output signals from the GTIOCnA and GTIOCnB pins (n =
0 to 3) by the PWM delay generation circuit or whether the circuit is bypassed.
A signal delayed in the PWM delay generation circuit is output 3 cycles of GPT operation clock (PCLKD) later than if it
bypasses the PWM delay generation circuit.
DLYENn (n = 0 to 3) bit (PWM Delay Generation Circuit Enable for channel n)
The DLYENn bit selects whether channel n (n = 0 to 3) of PWM delay generation circuit is power on or off. If channel n
of the PWM delay generation circuit is not used, set to 1.
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24.2.3
24. PWM Delay Generation Circuit
GTIOCnA Rising Output Delay Register (GTDLYRnA) (n = 0 to 3)
Address(es): GPT_ODC.GTDLYR0A 4007 B018h, GPT_ODC.GTDLYR1A 4007 B01Ch,
GPT_ODC.GTDLYR2A 4007 B020h, GPT_ODC.GTDLYR3A 4007 B024h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
0
0
DLY[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
DLY[4:0]
GTIOCnA Output Rising
Edge Delay Setting
b4
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
b0
0 0 0 0 0: Delay on rising edges is not applied
0 0 0 0 1: Delay of 1/32 times PCLKD period applied
0 0 0 1 0: Delay of 2/32 times PCLKD period applied
0 0 0 1 1: Delay of 3/ 32 times PCLKD period applied
0 0 1 0 0: Delay of 4/ 32 times PCLKD period applied
0 0 1 0 1: Delay of 5/ 32 times PCLKD period applied
0 0 1 1 0: Delay of 6/ 32 times PCLKD period applied
0 0 1 1 1: Delay of 7/ 32 times PCLKD period applied
0 1 0 0 0: Delay of 8/ 32 times PCLKD period applied
0 1 0 0 1: Delay of 9/ 32 times PCLKD period applied
0 1 0 1 0: Delay of 10/ 32 times PCLKD period applied
0 1 0 1 1: Delay of 11/ 32 times PCLKD period applied
0 1 1 0 0: Delay of 12/ 32 times PCLKD period applied
0 1 1 0 1: Delay of 13/ 32 times PCLKD period applied
0 1 1 1 0: Delay of 14/ 32 times PCLKD period applied
0 1 1 1 1: Delay of 15/ 32 times PCLKD period applied
1 0 0 0 0: Delay of 16/ 32 times PCLKD period applied
1 0 0 0 1: Delay of 17/ 32 times PCLKD period applied
1 0 0 1 0: Delay of 18/ 32 times PCLKD period applied
1 0 0 1 1: Delay of 19/ 32 times PCLKD period applied
1 0 1 0 0: Delay of 20/ 32 times PCLKD period applied
1 0 1 0 1: Delay of 21/ 32 times PCLKD period applied
1 0 1 1 0: Delay of 22/ 32 times PCLKD period applied
1 0 1 1 1: Delay of 23/ 32 times PCLKD period applied
1 1 0 0 0: Delay of 24/ 32 times PCLKD period applied
1 1 0 0 1: Delay of 25/ 32 times PCLKD period applied
1 1 0 1 0: Delay of 26/ 32 times PCLKD period applied
1 1 0 1 1: Delay of 27/ 32 times PCLKD period applied
1 1 1 0 0: Delay of 28/ 32 times PCLKD period applied
1 1 1 0 1: Delay of 29/ 32 times PCLKD period applied
1 1 1 1 0: Delay of 30/ 32 times PCLKD period applied
1 1 1 1 1: Delay of 31/ 32 times PCLKD period applied.
R/W
The GTDLYRnA register sets a delay to be applied to rising edges of output signals on the GTIOCnA pin. On the timing
for the transfer of settings, see section 24.3.2, Timing for Transfer of GTDLYRnA, GTLDYRnB, GTDLYFnA, and
GTDLYFnB Register Settings.
GTDLYRnA can be written when register write protection is disabled (GPT32EHn.GTWP.WP = 0).
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24.2.4
24. PWM Delay Generation Circuit
GTIOCnA Falling Output Delay Register (GTDLYFnA) (n = 0 to 3)
Address(es): GPT_ODC.GTDLYF0A 4007 B028h, GPT_ODC.GTDLYF1A 4007 B02Ch,
GPT_ODC.GTDLYF2A 4007 B030h, GPT_ODC.GTDLYF3A 4007 B034h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
0
0
DLY[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
DLY[4:0]
GTIOCnA Output Falling
Edge Delay Setting
b4
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
b0
0 0 0 0 0: Delay on falling edges is not applied
0 0 0 0 1: Delay of 1/32 times PCLKD period applied
0 0 0 1 0: Delay of 2/32 times PCLKD period applied
0 0 0 1 1: Delay of 3/ 32 times PCLKD period applied
0 0 1 0 0: Delay of 4/ 32 times PCLKD period applied
0 0 1 0 1: Delay of 5/ 32 times PCLKD period applied
0 0 1 1 0: Delay of 6/ 32 times PCLKD period applied
0 0 1 1 1: Delay of 7/ 32 times PCLKD period applied
0 1 0 0 0: Delay of 8/ 32 times PCLKD period applied
0 1 0 0 1: Delay of 9/ 32 times PCLKD period applied
0 1 0 1 0: Delay of 10/ 32 times PCLKD period applied
0 1 0 1 1: Delay of 11/ 32 times PCLKD period applied
0 1 1 0 0: Delay of 12/ 32 times PCLKD period applied
0 1 1 0 1: Delay of 13/ 32 times PCLKD period applied
0 1 1 1 0: Delay of 14/ 32 times PCLKD period applied
0 1 1 1 1: Delay of 15/ 32 times PCLKD period applied
1 0 0 0 0: Delay of 16/ 32 times PCLKD period applied
1 0 0 0 1: Delay of 17/ 32 times PCLKD period applied
1 0 0 1 0: Delay of 18/ 32 times PCLKD period applied
1 0 0 1 1: Delay of 19/ 32 times PCLKD period applied
1 0 1 0 0: Delay of 20/ 32 times PCLKD period applied
1 0 1 0 1: Delay of 21/ 32 times PCLKD period applied
1 0 1 1 0: Delay of 22/ 32 times PCLKD period applied
1 0 1 1 1: Delay of 23/ 32 times PCLKD period applied
1 1 0 0 0: Delay of 24/ 32 times PCLKD period applied
1 1 0 0 1: Delay of 25/ 32 times PCLKD period applied
1 1 0 1 0: Delay of 26/ 32 times PCLKD period applied
1 1 0 1 1: Delay of 27/ 32 times PCLKD period applied
1 1 1 0 0: Delay of 28/ 32 times PCLKD period applied
1 1 1 0 1: Delay of 29/ 32 times PCLKD period applied
1 1 1 1 0: Delay of 30/ 32 times PCLKD period applied
1 1 1 1 1: Delay of 31/ 32 times PCLKD period applied.
R/W
The GTDLYFnA register sets a delay to be applied to falling edges of output signals on the GTIOCnA pin. On the timing
for the transfer of settings, see section 24.3.2, Timing for Transfer of GTDLYRnA, GTLDYRnB, GTDLYFnA, and
GTDLYFnB Register Settings.
GTDLYFnA can be written when register write protection is disabled (GPT32EHn.GTWP.WP = 0).
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24.2.5
24. PWM Delay Generation Circuit
GTIOCnB Rising Output Delay Register (GTDLYRnB) (n = 0 to 3)
Address(es): GPT_ODC.GTDLYR0B 4007 B01Ah, GPT_ODC.GTDLYR1B 4007 B01Eh,
GPT_ODC.GTDLYR2B 4007 B022h, GPT_ODC.GTDLYR3B 4007 B026h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
0
0
DLY[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
DLY[4:0]
GTIOCnB Output Rising
Edge Delay Setting
b4
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
b0
0 0 0 0 0: Delay on rising edges is not applied
0 0 0 0 1: Delay of 1/32 times PCLKD period applied
0 0 0 1 0: Delay of 2/32 times PCLKD period applied
0 0 0 1 1: Delay of 3/ 32 times PCLKD period applied
0 0 1 0 0: Delay of 4/ 32 times PCLKD period applied
0 0 1 0 1: Delay of 5/ 32 times PCLKD period applied
0 0 1 1 0: Delay of 6/ 32 times PCLKD period applied
0 0 1 1 1: Delay of 7/ 32 times PCLKD period applied
0 1 0 0 0: Delay of 8/ 32 times PCLKD period applied
0 1 0 0 1: Delay of 9/ 32 times PCLKD period applied
0 1 0 1 0: Delay of 10/ 32 times PCLKD period applied
0 1 0 1 1: Delay of 11/ 32 times PCLKD period applied
0 1 1 0 0: Delay of 12/ 32 times PCLKD period applied
0 1 1 0 1: Delay of 13/ 32 times PCLKD period applied
0 1 1 1 0: Delay of 14/ 32 times PCLKD period applied
0 1 1 1 1: Delay of 15/ 32 times PCLKD period applied
1 0 0 0 0: Delay of 16/ 32 times PCLKD period applied
1 0 0 0 1: Delay of 17/ 32 times PCLKD period applied
1 0 0 1 0: Delay of 18/ 32 times PCLKD period applied
1 0 0 1 1: Delay of 19/ 32 times PCLKD period applied
1 0 1 0 0: Delay of 20/ 32 times PCLKD period applied
1 0 1 0 1: Delay of 21/ 32 times PCLKD period applied
1 0 1 1 0: Delay of 22/ 32 times PCLKD period applied
1 0 1 1 1: Delay of 23/ 32 times PCLKD period applied
1 1 0 0 0: Delay of 24/ 32 times PCLKD period applied
1 1 0 0 1: Delay of 25/ 32 times PCLKD period applied
1 1 0 1 0: Delay of 26/ 32 times PCLKD period applied
1 1 0 1 1: Delay of 27/ 32 times PCLKD period applied
1 1 1 0 0: Delay of 28/ 32 times PCLKD period applied
1 1 1 0 1: Delay of 29/ 32 times PCLKD period applied
1 1 1 1 0: Delay of 30/ 32 times PCLKD period applied
1 1 1 1 1: Delay of 31/ 32 times PCLKD period applied.
R/W
The GTDLYRnB register sets a delay to be applied to rising edges of output signals on the GTIOCnB pin. On the timing
for the transfer of settings, see section 24.3.2, Timing for Transfer of GTDLYRnA, GTLDYRnB, GTDLYFnA, and
GTDLYFnB Register Settings.
GTDLYRnB can be written when register write protection is disabled (GPT32EHn.GTWP.WP = 0).
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24.2.6
24. PWM Delay Generation Circuit
GTIOCnB Falling Output Delay Register (GTDLYFnB) (n = 0 to 3)
Address(es): GPT_ODC.GTDLYF0B 4007 B02Ah, GPT_ODC.GTDLYF1B 4007 B02Eh,
GPT_ODC.GTDLYF2B 4007 B032h, GPT_ODC.GTDLYF3B 4007 B036h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
0
0
DLY[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
DLY[4:0]
GTIOCnB Output Falling
Edge Delay Setting
b4
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
b0
0 0 0 0 0: Delay on falling edges is not applied
0 0 0 0 1: Delay of 1/32 times PCLKD period applied
0 0 0 1 0: Delay of 2/32 times PCLKD period applied
0 0 0 1 1: Delay of 3/ 32 times PCLKD period applied
0 0 1 0 0: Delay of 4/ 32 times PCLKD period applied
0 0 1 0 1: Delay of 5/ 32 times PCLKD period applied
0 0 1 1 0: Delay of 6/ 32 times PCLKD period applied
0 0 1 1 1: Delay of 7/ 32 times PCLKD period applied
0 1 0 0 0: Delay of 8/ 32 times PCLKD period applied
0 1 0 0 1: Delay of 9/ 32 times PCLKD period applied
0 1 0 1 0: Delay of 10/ 32 times PCLKD period applied
0 1 0 1 1: Delay of 11/ 32 times PCLKD period applied
0 1 1 0 0: Delay of 12/ 32 times PCLKD period applied
0 1 1 0 1: Delay of 13/ 32 times PCLKD period applied
0 1 1 1 0: Delay of 14/ 32 times PCLKD period applied
0 1 1 1 1: Delay of 15/ 32 times PCLKD period applied
1 0 0 0 0: Delay of 16/ 32 times PCLKD period applied
1 0 0 0 1: Delay of 17/ 32 times PCLKD period applied
1 0 0 1 0: Delay of 18/ 32 times PCLKD period applied
1 0 0 1 1: Delay of 19/ 32 times PCLKD period applied
1 0 1 0 0: Delay of 20/ 32 times PCLKD period applied
1 0 1 0 1: Delay of 21/ 32 times PCLKD period applied
1 0 1 1 0: Delay of 22/ 32 times PCLKD period applied
1 0 1 1 1: Delay of 23/ 32 times PCLKD period applied
1 1 0 0 0: Delay of 24/ 32 times PCLKD period applied
1 1 0 0 1: Delay of 25/ 32 times PCLKD period applied
1 1 0 1 0: Delay of 26/ 32 times PCLKD period applied
1 1 0 1 1: Delay of 27/ 32 times PCLKD period applied
1 1 1 0 0: Delay of 28/ 32 times PCLKD period applied
1 1 1 0 1: Delay of 29/ 32 times PCLKD period applied
1 1 1 1 0: Delay of 30/ 32 times PCLKD period applied
1 1 1 1 1: Delay of 31/ 32 times PCLKD period applied.
R/W
The GTDLYFnB register sets a delay to be applied to falling edges of output signals on the GTIOCnB pin. On the timing
for the transfer of settings, see section 24.3.2, Timing for Transfer of GTDLYRnA, GTLDYRnB, GTDLYFnA, and
GTDLYFnB Register Settings.
GTDLYFnB can be written when register write protection is disabled (GPT32EHn.GTWP.WP = 0).
24.3
24.3.1
Operation
Adjustments to the Timing of Rising and Falling Edges in PWM Waveforms
The timing of rising and falling edges in PWM waveforms which are output from the GTIOCnA and GTIOCnB pins,
where n = channel number, can be delayed to an accuracy of 1/32 of the GPT operating clock (PCLKD) period.
If the timing of rising or falling edges in PWM waveforms output from the GTIOCnA and GTIOCnB pins must be
adjusted, initialize the PWM generation circuit as shown in the procedure in Figure 24.2.
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24. PWM Delay Generation Circuit
Initial setting
GTDLYCR.DLLEN = 0
GTDLYCR.DLLEN = 1
Enable the DLL
Wait for 20 µs
GTDLYCR.DLYRST = 1
Reset the PWM delay generation circuit
GTDLYCR.DLYRST = 0
GTDLYCR2.DLYBSn = 1
PWM delay generation circuit bypass off
End of initial settings
n = 0 to 3
Figure 24.2
Example of initialization flow for the PWM delay generation circuit
In the PWM delay generation circuit, delay can be applied to rising and falling edges of the PWM output to an accuracy
of 1/32 of the period of the GPT operation clock (PCLKD). This is described in section 23.3.3, PWM Output Operating
Mode. Delays associated with the settings are reflected in the PWM output with the timing described in section 24.3.2,
Timing for Transfer of GTDLYRnA, GTLDYRnB, GTDLYFnA, and GTDLYFnB Register Settings. Table 24.3 shows
the association between the GTDLYRnA, GTLDYRnB, GTDLYFnA, and GTDLYFnB registers and the PWM outputs.
Table 24.3
Association between PWM output pins and delay setting registers
PWM output pin
Rising-edge delay setting register
Falling-edge delay setting register
GTIOC0A
GTDLYR0A
GTDLYF0A
GTIOC0B
GTDLYR0B
GTDLYF0B
GTIOC1A
GTDLYR1A
GTDLYF1A
GTIOC1B
GTDLYR1B
GTDLYF1B
GTIOC2A
GTDLYR2A
GTDLYF2A
GTIOC2B
GTDLYR2B
GTDLYF2B
GTIOC3A
GTDLYR3A
GTDLYF3A
GTIOC3B
GTDLYR3B
GTDLYF3B
When the PWM delay generation circuit is in use, the timing with which a PWM output signal rises and falls can be
controlled to an accuracy of 1/32 of the period of the GPT operation clock (PCLKD). When this option is not in use, the
period of the PWM output waveform is controlled to an accuracy of one period of the input clock for the timer counter,
which is PCLKD. With the PWM delay generation circuit, the output can be controlled to an accuracy 32 times better.
Additionally, the delay settings also control the periods at high and low level for the PWM waveform to the given
accuracy. PWM delay generation circuit channels can be individually enabled or disabled.
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24.3.2
24. PWM Delay Generation Circuit
Timing for Transfer of GTDLYRnA, GTLDYRnB, GTDLYFnA, and GTDLYFnB
Register Settings
Settings for the GTDLYRnA, GTLDYRnB, GTDLYFnA, and GTDLYFnB registers are initially transferred to temporary
registers, and then reflected in the delay on the GTIOCnA and GTIOCnB (n = 0 to 3) outputs. Transfer of the settings
takes place on overflows (in up-counting) or underflows (in down-counting) for saw waves, and in the troughs of triangle
waves.
Figure 24.3 and Figure 24.4 show examples of the operation of the GTDLYR0A and GTDLYF0A registers.
GPT32EH0.GTCNT value
GPT32EH0.GTPR
yyyy
0000h
Time
Register writing
Register writing
GTDLYR0A.DLY
Register writing
b
c
Buffer transfer
at overflow
Temporary register
Register writing
a
b
d
Buffer transfer
at overflow
Buffer transfer
at overflow
c
GTIOC0A output
a
b
c
Delay on the rising edge
Figure 24.3
Example of GTLDYR0A register operation with PWM saw-wave generation
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24. PWM Delay Generation Circuit
GPT32EH0.GTCNT value
GPT32EH0.GTPR
yyyy
0000h
Time
Register writing
Register writing
Register writing
b
GTDLYF0A.DLY
c
Buffer transfer at trough
Temporary register
Register writing
a
b
d
Buffer transfer at trough
Buffer transfer at trough
c
GTIOC0A output
a
b
c
Delay on the falling edge
Figure 24.4
24.4
Example of GTLDYF0A register operation with PWM triangle-wave generation
Usage Notes
24.4.1
Module-Stop Function Settings
The Module Stop Control Register D (MSTPCRD) can enable or disable operation of the PWM delay generation circuit.
The PWM delay generation circuit is initially stopped after reset. Releasing the module-stop state enables access to the
registers. For details, see section 11, Low Power Modes.
24.4.2
Notes on Delay Settings for PWM Delay Generation Circuit
When the PWM delay generation circuit generates delays for a PWM output waveform and the waveform is toggled in
response to compare-matches, do not change the settings for delay while the compare-match value is within the ranges
listed in Table 24.4. This constraint applies to the GTDLYFnA, GTDLYRnA, GTDLFnB, and GTDLYRnB registers.
Table 24.4
Constraints on delay settings
Mode
Direction of counting
Compare-match value
Saw-wave mode
Up
GTPR - 2 or above
Down
2 or below
Down
2 or below
Triangle-wave mode
Figure 24.5 shows an example of how the constraints apply to the timing of setting GTDLYFnA in saw-wave waveform
one-shot pulse mode (counting up). Do not change the value set in GTDLYFnA while GTCCRD ≥ GTPR - 2.
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24. PWM Delay Generation Circuit
GTPR
Set GTPR - 2 to the
GTCCRD register
Set GTPR - 5 to the
GTCCRD register
GTDLYF0A register
GTDOG0A pin
Change of GTDLYF0A setting allowed
Figure 24.5
Change of GTDLYF0A setting not allowed
Constraints on the timing of GTDLYF0A register settings
Changing the values in the GTDLYFnA, GTDLYRnA, GTDLYFnB, and GTDLYRnB registers during periods where
changes to settings are not allowed, might lead to faulty output waveforms such as shifts in the timing of output
waveform transitions from the expected values.
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25. Asynchronous General-Purpose Timer (AGT)
25.
Asynchronous General-Purpose Timer (AGT)
25.1
Overview
The Asynchronous General-Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width
or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down counter. The reload register and the down counter are allocated
in the same address, and can be accessed with the AGT register.
Table 25.1 lists the AGT specifications, Figure 25.1 shows a block diagram, and Table 25.2 lists the I/O pins.
Table 25.1
AGT specifications
Parameter
Operating modes
Specifications
Timer mode
The count source is counted
Pulse output mode
The count source is counted and the output is inverted at each timer underflow
Event counter mode
An external event is counted
Pulse width
measurement mode
An external pulse width is measured
Pulse period
measurement mode
An external pulse period is measured
Count source (Operating clock)*2
PCLKB, PCLKB/2, PCLKB/8, AGTLCLK, AGTLCLK/2, AGTLCLK/4,
AGTLCLK/8, AGTLCLK/16, AGTLCLK/32, AGTLCLK/64, AGTLCLK/128,
AGTSCLK, AGTSCLK/2, AGTSCLK/4, AGTSCLK/8, AGTSCLK/16,
AGTSCLK/32, AGTSCLK/64, AGTSCLK/128, or underflow signal of AGT0*1
selectable.
Interrupt/Event link function (Output)
Underflow event signal or measurement complete event signal
When the counter underflows
When the measurement of the active width of the external input (AGTIO) is
complete in pulse width measurement mode
When the set edge of the external input (AGTIO) is input in pulse period
measurement mode
Compare match A event signal
When the values of AGT and AGTCMA matched (Compare match A
function enabled)
Compare match B event signal
When the values of AGT and AGTCMB matched (Compare match B
function enabled).
Selectable functions
Compare match function
One or two of the compare match A and B registers is selectable.
Note 1.
Note 2.
AGT0 cannot use the AGT0 underflow signal. AGT1 connects directly with the underflow event signal from the AGT0 timer.
Satisfy the frequency of the peripheral module clock (PCLKB) ≥ the frequency of the count source clock.
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25. Asynchronous General-Purpose Timer (AGT)
Data bus
16-bit
reload
register
TCMEA or
TCMEB = 1
TCK[2:0]
TCK[2:0]
= 000b
CKS[2:0]
AGTLCLK
PCLKB
= 100b
(LOCO clock
= 001b
Prescaler
PCLKB/8
for AGT)
1, 2, 4, 8, 16
= 011b
32, 64, 128
PCLKB/2
AGTSCLK = 110b
(Sub clock
= 100b or 110b
AGTLCLK or AGTSCLK
for AGT)
after division
Underflow event signal from AGT0*2
16-bit
reload
register
AGT underflows
AGT underflow or
AGT is rewritten
AGTCMA
AGTCMB
Comparison
circuit
Comparison
circuit
TCMEA and TCMEB = 0
TMOD[2:0]
= other than
010b
TSTART
TCMEA
Event is counted during polarity = 01b
period specified for AGTEEn*1
TIPF[1:0]
TCMEB
P402/AGTIOn pin = 10b
One edge/
both edges
switching
Polarity
selection
TEDGPL
TEDGSEL
Compare
match A event
signal
AGT
counter
Underflow
event signal/
Measurement
complete event
signal
TMOD[2:0]
= 011b or 100b
P403/AGTIOn pin = 11b
Compare
match B event
signal
16-bit counter
= 010b
Digital
filter
TCM TCM TUN TED
AF
BF DF GF
= 101b
TIOGT[1:0]
= 00b
Event is always counted
SEL[1:0]
16-bit
reload
register
Counter
control
circuit
Measurement
complete signal
= 00b
TMOD[2:0] = 001b
Pm*3/AGTIOn pin
TEDGSEL = 1
Q
Toggle flip-flop
TEDGSEL = 0
Q
AGTOn pin
TOE
AGTOAn pin
TOEA
TOPOLA = 1
Q
Toggle flip-flop
TOPOLA = 0
Q
AGTOBn pin
TOPOLB = 1
TOEB
CLR
CLR
Q
Toggle flip-flop
TOPOLB = 0
Q
CLR
TSTART, TSTOP, TUNDF, TCMAF, TCMBF: Bits in AGTCR register
TEDGSEL, TOE, TIPF[1:0], TIOGT[1:0]: Bits in AGTIOC register
TMOD[2:0], TEDGPL, TCK[2:0], Bits in AGTMR1 register
TCMEA, TOEA, TOPOLA, TCMEB, TOEB, TOPOLB: Bits in AGTCMSR register
SEL[1:0]: Bits in AGTIOSEL register
CKS[2:0] : Bit in AGTMR2 register
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
Note 1. The polarity can be selected by the EEPS bit in the AGTISR register.
Note 2. AGT0 cannot use AGT underflow event. AGT1 uses the underflow of AGT0.
Note 3. m = 100, 301, 407, and 705 (AGT0), m = 204 and 400 (AGT1).
Figure 25.1
Table 25.2
AGT block diagram
AGT I/O pins
Pin name
I/O
Function
AGTEEn
Input
External event input for AGT
AGTIOn*1
Input*1/output
External event input and pulse output for AGT
AGTOn
Output
Pulse output for AGT
AGTOAn
Output
Output compare match A output for AGT
AGTOBn
Output
Output compare match B output for AGT
Note:
Note 1.
Channel number (n = 0, 1).
AGTIO can also be used in Deep Software Standby mode.
AGTIO can be controlled by the VBTICTLR register.
For more information, see section 12.2.2, VBATT Input Control Register (VBTICTLR) and section 20.5.5, I/O Buffer
Specification.
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25.2
25. Asynchronous General-Purpose Timer (AGT)
Register Descriptions
25.2.1
AGT Counter Register (AGT)
Address(es): AGT0.AGT 4008 4000h, AGT1.AGT 4008 4100h
Value after reset:
Bit
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
b15 to b0
Note 1.
Note 2.
b15
16-bit counter and reload register
*1, *2
Setting range
R/W
0000h to FFFFh
R/W
When 1 is written to the TSTOP bit in the AGTCR register, the 16-bit counter is forcibly stopped and set to FFFFh.
When the TCK[2:0] bit setting in the AGTMR1 register is other than 001b (PCLKB/8) or 011b (PCLKB/2), if the AGT register is
set to 0000h, a request signal to the ICU, the DTC, and the ELC is generated once immediately after the count starts. The
AGTOn and AGTIOn outputs are toggled.
When the AGT register is set to 0000h in event counter mode, regardless of the value of TCK[2:0] bits, a request signal to the
ICU, the DTC, and the ELC is generated once immediately after the count starts.
In addition, the AGTOn output toggles even during a period other than the specified count period. When the AGT register is set
to 0001h or more, a request signal is generated each time AGT underflows.
AGT is a 16-bit register. The write value is written to the reload register and the read value is read from the counter.
The states of the reload register and the counter change according to the TSTART bit in the AGTCR register and
TCMEA/TCMEB bit in the AGTCMSR register. For details, see section 25.3.1, Reload Register and Counter Rewrite
Operation. The AGT register can be set with a 16-bit memory manipulation instruction.
25.2.2
AGT Compare Match A Register (AGTCMA)
Address(es): AGT0.AGTCMA 4008 4002h, AGT1.AGTCMA 4008 4102h
Value after reset:
Bit
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
b15 to b0
Note 1.
b15
16-bit compare match A data is
stored.*1
Setting range
R/W
0000h to FFFFh
R/W
Set the AGTCMA register to FFFFh when the compare match A is not used.
The AGTCMA register is a read/write register to set a value for compare match with the AGT counter. The states of the
reload register and compare register A change according to the TSTART bit in the AGTCR register. For details, see
section 25.3.2, Reload Register and Compare Register A/B Rewrite Operation. The AGTCMA register can be set by a
16-bit memory manipulation instruction.
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25.2.3
25. Asynchronous General-Purpose Timer (AGT)
AGT Compare Match B Register (AGTCMB)
Address(es): AGT0.AGTCMB 4008 4004h, AGT1.AGTCMB 4008 4104h
Value after reset:
Bit
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
b15 to b0
Note 1.
b15
16-bit compare match B data is
stored.*1
Setting range
R/W
0000h to FFFFh
R/W
Set the AGTCMB register to FFFFh when compare match B is not used.
The AGTCMB register is a read/write register to set a value for compare match with the AGT counter. The states of the
reload register and compare register B change according to the TSTART bit in the AGTCR register. For details, see
section 25.3.2, Reload Register and Compare Register A/B Rewrite Operation. The AGTCMB register can be set by a
16-bit memory manipulation instruction.
25.2.4
AGT Control Register (AGTCR)
Address(es): AGT0.AGTCR 4008 4008h, AGT1.AGTCR 4008 4108h
b7
b6
b5
b4
b3
TCMBF TCMAF TUNDF TEDGF
Value after reset:
0
0
0
—
0
0
b2
b1
b0
TSTOP TCSTF TSTAR
T
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TSTART
AGT Count Start *2
0: Count stops
1: Count starts.
R/W
b1
TCSTF
AGT Count Status
Flag *2
0: Count stopped
1: Count in progress.
R
b2
TSTOP
AGT Count Forced
Stop *1
0: Writing is invalid
1: The count is forcibly stopped.
W
b3
—
Reserved
The read value is 0. The write value should be 0.
R/W
b4
TEDGF
Active Edge Judgment
Flag
0: No active edge received
1: Active edge received.
R/(W)*3
b5
TUNDF
Underflow Flag
0: No underflow
1: Underflow.
R/(W)*3
b6
TCMAF
Compare Match A Flag
0: No match
1: Match.
R/(W)*3
b7
TCMBF
Compare Match B Flag
0: No match
1: Match.
R/(W)*3
Note 1.
Note 2.
Note 3.
When 1 (count is forcibly stopped) is written to the TSTOP bit, the TSTART and TCSTF bits are initialized at the same time.
The pulse output level is also initialized. The read value is 0.
For information on using the TSTART and TCSTF bits, see section 25.4.1, Count Operation Start and Stop Control.
Only 0 can be written to clear the flag.
TSTART bit (AGT Count Start)
The count operation is started by writing 1 to the TSTART bit and stopped by writing 0. When this bit is set to 1, the
TCSTF bit is set to 1 (count in progress) in synchronization with the count source. Also, after 0 is written to the TSTART
bit, the TCSTF bit is set to 0 (count stopped) in synchronization with the count source. For details, see section 25.4.1,
Count Operation Start and Stop Control.
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25. Asynchronous General-Purpose Timer (AGT)
TCSTF flag (AGT Count Status Flag)
The TCSTF flag indicates the AGT count status.
[Setting condition]
When 1 is written to the TSTART bit (the TCSTF flag is set to 1 in synchronization with the count source).
[Clearing conditions]
When 0 is written to the TSTART bit (the TCSTF flag is set to 0 in synchronization with the count source)
When 1 is written to the TSTOP bit.
TSTOP bit (AGT Count Forced Stop)
When 1 is written to the TSTOP bit, the count is forcibly stopped. The read value is 0.
TEDGF flag (Active Edge Judgment Flag)
The TEDGF flag indicates that an active edge was detected.
[Setting condition]
When the measurement of the active width of the external input (AGTIO) is complete in pulse width measurement
mode.
When the set edge of the external input (AGTIO) is input in pulse period measurement mode
[Clearing condition]
When 0 is written to this flag by a program.
TUNDF flag (Underflow Flag)
The TUNDF flag indicates that the counter underflowed.
[Setting condition]
When the counter underflows.
[Clearing condition]
When 0 is written to this flag by software.
TCMAF flag (Compare Match A Flag)
The TCMAF flag indicates that compare match A was detected.
[Setting condition]
When the value in the AGT register matches the value in the AGTCMA register.
[Clearing condition]
When 0 is written to this flag by software.
TCMBF flag (Compare Match B Flag)
The TCMBF flag indicates that compare match B was detected.
[Setting condition]
When the value in the AGT register matches the value in the AGTCMB register.
[Clearing condition]
When 0 is written to this flag by software.
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25.2.5
25. Asynchronous General-Purpose Timer (AGT)
AGT Mode Register 1 (AGTMR1)
Address(es): AGT0.AGTMR1 4008 4009h, AGT1.AGTMR1 4008 4109h
b7
b6
—
Value after reset:
Bit
0
Symbol
b5
b4
0
b2
TEDGP
L
TCK[2:0]
0
b3
0
0
Bit name
Mode*3
b1
b0
TMOD[2:0]
0
0
0
Description
R/W
b2
R/W
b2 to b0
TMOD[2:0]
Operating
b3
TEDGPL
Edge Polarity*4
0: Single-edge
1: Both-edge.
R/W
b6 to b4
TCK[2:0]
Count Source*1, *2, *5
b6
R/W
b7
—
Reserved
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
b0
0 0 0: Timer mode
0 0 1: Pulse output mode
0 1 0: Event counter mode
0 1 1: Pulse width measurement mode
1 0 0: Pulse period measurement mode.
Other settings are prohibited.
0
0
0
1
0
0
1
0
b4
0: PCLKB
1: PCLKB/8
1: PCLKB/2
0: Divided clock AGTLCLK specified in CKS[2:0] bits in AGTMR2
register
1 0 1: Underflow event signal from AGT0*6
1 1 0: Divided clock AGTSCLK specified in CKS[2:0] bits in AGTMR2
register.
Other settings are prohibited.
The read value is 0. The write value should be 0.
R/W
Write access to the AGTMR1 register initializes the output from the AGTOn, AGTIOn, AGTOAn and AGTOBn pins of the AGT
(n = 0, 1). For details on the output level at initialization, see the description of section 25.2.7, AGT I/O Control Register
(AGTIOC).
When event counter mode is selected, the external input (AGTIOn) is selected as the count source regardless of the setting of
TCK[2:0] bits.
Do not switch count sources during count operation. Only switch count sources when both the TSTART and TCSTF bits in the
AGTCR register are set to 0 (count is stopped).
The operating mode can only be changed when the count is stopped while both the TSTART and TCSTF bits in the AGTCR
register are set to 0 (count is stopped). Do not change the operating mode during count operation.
The TEDGPL bit is enabled only in event counter mode.
When running AGT in Software Standby and Deep Software Standby modes, set AGTSCLK or AGTLCLK (TCK[2:0] = 100b or
110b) as the count source.
AGT0 cannot use AGT0 underflow (setting prohibited). AGT1 uses the AGT0 underflow.
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25.2.6
25. Asynchronous General-Purpose Timer (AGT)
AGT Mode Register 2 (AGTMR2)
Address(es): AGT0.AGTMR2 4008 400Ah, AGT1.AGTMR2 4008 410Ah
Value after reset:
b7
b6
b5
b4
b3
LPM
—
—
—
—
0
0
0
0
0
b2
b1
b0
CKS[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CKS[2:0]
AGTSCLK/AGTLCLK
Count Source Clock
Frequency Division
Ratio *1, *2, *3
b2
R/W
b6 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
LPM
Low Power Mode
0: Normal mode
1: Low power mode.
R/W
Note 1.
Note 2.
Note 3.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1/1
1: 1/2
0: 1/4
1: 1/8
0: 1/16
1: 1/32
0: 1/64
1: 1/128.
Do not rewrite CKS[2:0] during count operation. Only rewrite the CKS[2:0] bits when both the TSTART and TCSTF bits in the
AGTCR register are set to 0 (count is stopped).
When count source is AGTSCLK/AGTLCLK, the switch of CKS[2:0] is valid.
Do not switch the TCK[2:0] bits in the AGTMR1 register when CKS[2:0] are not 000b. Switch the TCK[2:0] bits in the AGTMR1
register after CKS[2:0] are set to 000b, and wait for 1 cycle of the count source.
LPM bit (Low Power Mode)
The LPM bit sets the low power operation, which impacts access to certain AGT registers. Set 1 to operate in low power.
When this bit is 1, access to the following registers is prohibited:
AGT/AGTCMA/AGTCMB/AGTCR.
After this bit is switched from 1 to 0, the first access to the register is constrained as follows:
AGT: Read AGT register twice. Only the second reading of data is valid.
AGT, AGTCMA, AGTCMB, and AGTCR: Allow at least 2 cycles of the count source clock when writing to the
register.
25.2.7
AGT I/O Control Register (AGTIOC)
Address(es): AGT0.AGTIOC 4008 400Ch, AGT1.AGTIOC 4008 410Ch
b7
Value after reset:
b6
b5
b4
b3
b2
b1
b0
TIOGT[1:0]
TIPF[1:0]
—
TOE
—
TEDGS
EL
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TEDGSEL
I/O Polarity Switch
Function varies depending on the operating mode. See Table 25.3 and
Table 25.4.
The TEDGSEL bit switches the AGTO output polarity and the AGTIO
input/output edge and polarity. In pulse output mode, it only controls the
polarity of AGTOn output and AGTIOn output. AGTOn output and
AGTIOn output are initialized when the AGTMR1 register is written and
the TSTOP bit in the AGTCR register is written with 1.
R/W
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25. Asynchronous General-Purpose Timer (AGT)
Bit
Symbol
Bit name
Description
R/W
b1
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2
TOE
AGTOn Output Enable
0: AGTOn output disabled
1: AGTOn output enabled.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5, b4
TIPF[1:0]
Input Filter *3
b5 b4
R/W
b7, b6
TIOGT[1:0]
Count Control *1, *2, *4
b7 b6
R/W
Note 1.
Note 2.
Note 3.
Note 4.
0 0: No filter
0 1: Filter sampled at PCLKB
1 0: Filter sampled at PCLKB/8
1 1: Filter sampled at PCLKB/32.
These bits specify the sampling frequency of the filter for the AGTIOn
input. If the input to the AGTIOn pin is sampled and the value matches
three successive times, that value is taken as the input value.
0 0: Event is always counted
0 1: Event is counted during polarity period specified for AGTEEn.
Other settings are prohibited.
When AGTEEn pin is used, the polarity to count an event can be selected with the EEPS bit in the AGTISR register.
TIOGT[1:0] bits are enabled only in event counter mode.
When event counter mode operation is performed during Software Standby and Deep Software Standby modes, the digital filter
function cannot be used.
When using in Deep Software Standby mode, set TIOGT[1:0] = 00b (event is always counted).
Table 25.3
AGTIOn I/O edge and polarity switching
Operating mode
Function
Timer mode
Not used
Pulse output mode
0: Output is started at high (initialization level: high)
1: Output is started at low (initialization level: low).
Event counter mode
0: Count on rising edge
1: Count on falling edge.
Pulse width measurement mode
0: Low-level width is measured
1: High-level width is measured
Pulse period measurement mode
0: Measure from one rising edge to the next rising edge
1: Measure from one falling edge to the next falling edge.
Table 25.4
AGTOn output polarity switching
Operating mode
Function
All modes
0: Output is started at low (initialization level: low)
1: Output is started at high (initialization level: high).
25.2.8
AGT Event Pin Select Register (AGTISR)
Address(es): AGT0.AGTISR 4008 400Dh, AGT1.AGTISR 4008 410Dh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
EEPS
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
EEPS
AGTEEn Polarity
Selection
0: An event is counted during the low-level period
1: An event is counted during the high-level period.
R/W
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25. Asynchronous General-Purpose Timer (AGT)
Bit
Symbol
Bit name
Description
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
25.2.9
AGT Compare Match Function Select Register (AGTCMSR)
Address(es): AGT0.AGTCMSR 4008 400Eh, AGT1.AGTCMSR 4008 410Eh
b7
—
Value after reset:
0
b6
b5
b4
TOPOL TOEB TCMEB
B
0
0
0
b3
—
0
b2
b1
b0
TOPOL TOEA TCMEA
A
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TCMEA
Compare Match A
Register Enable*1, *2
0: Compare match A register disabled
1: Compare match A register enabled.
R/W
b1
TOEA
AGTOAn Output
Enable*1, *2
0: AGTOAn output disabled
1: AGTOAn output enabled.
R/W
b2
TOPOLA
AGTOAn Polarity
Select*1, *2
0: AGTOAn output is started on low
1: AGTOAn output is started on high.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
TCMEB
Compare Match B
Register Enable*1, *2
0: Compare match B register disabled
1: Compare match B register enabled.
R/W
b5
TOEB
AGTOBn Output
Enable*1, *2
0: AGTOBn output disabled
1: AGTOBn output enabled.
R/W
b6
TOPOLB
AGTOBn Polarity
Select*1, *2
0: AGTOBn output is started on low
1: AGTOBn output is started on high.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Do not rewrite the AGTCMSR register during a count operation. Only rewrite the AGTCMSR register when both the TSTART
and TCSTF bits in the AGTCR register are set to 0 (count is stopped).
Do not set to 1 when in pulse width measurement mode or pulse period measurement mode.
25.2.10
AGT Pin Select Register (AGTIOSEL)
Address(es): AGT0.AGTIOSEL 4008 400Fh, AGT1.AGTIOSEL 4008 410Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
TIES
—
—
SEL[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
SEL[1:0]
AGTIO Pin Select*1,*3
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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0 0: Select Pm*2/AGTIO as AGTIO
Pm/AGTIO can not be used as AGTIO input pin in
Deep Software Standby mode.
0 1: Setting prohibited
1 0: Select P402/AGTIO as AGTIO
P402/AGTIO can be used as AGTIO input pin in
Deep Software Standby mode. P402/AGTIOn is
input only. It cannot be used for output.
1 1: Select P403/AGTIO as AGTIO.
P403/AGTIO can be used as AGTIO input pin in
Deep Software Standby mode. P403/AGTIOn is
input only. It cannot be used for output.
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25. Asynchronous General-Purpose Timer (AGT)
Bit
Symbol
Bit name
Description
R/W
b4
TIES
AGTIO Input Enable
0: External event input is disabled during Software
Standby mode
1: External event input is enabled during Software
Standby mode.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Note 3.
P402/AGTIO and P403/AGTIO can be used as external event input pins for the AGT in Deep Software Standby mode.
Pm*2/AGTIO cannot be used as external event input pins for the AGT in Deep Software Standby mode. P402/AGTIO and
P403/AGTIO are input only.
When Pm/AGTIO is selected, you must set the Port mn Pin Function Select register. See section 20, I/O Ports.
m = 100, 301, 407, and 705 (AGT0), m = 204 and 400 (AGT1).
When P402/AGTIO and P403/AGTIO are selected, you must set the VBTICTLR register. See section 12, Battery Backup
Function.
The AGTIOSEL register sets the AGTIO pin when using the AGTIO in Deep Software Standby mode and Software
Standby mode. The AGTIOSEL register can be set with an 8-bit memory manipulation instruction.
SEL[1:0] bits (AGTIO Pin Select*1,*3)
The SEL[1:0] bits select the AGTIO pin function.
TIES bit (AGTIO Input Enable)
The TIES bit enables or disables an external event input.
25.3
25.3.1
Operation
Reload Register and Counter Rewrite Operation
Regardless of the operating mode, the timing of the rewrite operation to the reload register and the counter differs
depending on the value of the TSTART bit in the AGTCR register and of the TCMEA and TCMEB bit in the AGTCMSR
register. When the TSTART bit is 0 (count stops), the count value is directly written to the reload register and the counter.
When the TSTART bit is 1 (count starts) and the TCMEA bit and TCMEB bit are 0 (compare match A/B registers are
invalid), the value is written to the reload register in synchronization with the count source, and then to the counter in
synchronization with the next count source. When the TSTART bit is 1 (count starts) and the TCMEA bit or TCMEB bit
is 1 (compare match A register or compare match B register is valid), the value is written to the reload register in
synchronization with the count source, and then to the counter in synchronization with the underflow of the counter.
Figure 25.2 and Figure 25.3 show the timing of rewrite operation with TSTART bit value and TCMEA/TCMEB bit
value.
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25. Asynchronous General-Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register with software
Write 1234h to AGT register with software
Write 5678h to AGT register with software
Register write clock
Count source
TSTART bit in AGTCR
register
TCMEB bit in AGTCMSR
register
TCMEA bit in AGTCMSR
register
AGT register
FFFFh
5678h
1234h
Reload register load signal
Reload register load clock
Counter load signal
Counter load clock
Figure 25.2
Reload register
FFFFh
AGT counter
FFFFh
5678h
5678h
1234h
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh 1234h 1233h 1232h 1231h 1230h
Timing of rewrite operation with TSTART bit value and TCMEA/TCMEB bit value when compare
match register A or B is invalid
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25. Asynchronous General-Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register with software
Write 1234h to AGT register with software
Write 5678h to AGT register with software
Register write clock
Count source
TSTART bit in AGTCR
register
TCMEB bit in AGTCMSR
register
or
TCMEA bit in AGTCMSR
register
AGT register
FFFFh
5678h
1234h
Reload register load signal
Reload register load clock
Counter load signal
Counter load clock
Reload register
FFFFh
AGT counter
FFFFh
Figure 25.3
25.3.2
5678h
5678h
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh •••••
1234h
••••• 0002h 0001h 0000h 1234h1233h 1232h1231h
Timing of rewrite operation with TSTART bit value and TCMEA or TCMEB bit value when compare
match register A or B is valid
Reload Register and Compare Register A/B Rewrite Operation
Regardless of the operating mode, the timing of the rewrite operation to compare register A/B depends on the value of
the TSTART bit in the AGTCR register. When the TSTART bit is 0 (count stops), the count value is directly written to
the reload register and compare register A/B. When the TSTART bit is 1 (count starts), the value is written to the reload
register in synchronization with the count source, and then to the compare register in synchronization with the underflow
of the counter.
Figure 25.4 shows the timing of rewrite operation with TSTART bit value for compare register A. Compare register B
has the same timing as compare register A.
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25. Asynchronous General-Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register by a program
Write 2345h to AGTCMA register by a program
Write 1234h to AGTCMA register by a program
Register write clock
Count source
TSTART bit in AGTCR
register
AGT counter
AGTCMA register
5678h
FFFFh
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh 566Eh
1234h
...
0000h 5678h 5677h
2345h
Reload register A load signal
Reload register A load clock
Compare register A load signal
Compare register A load clock
Reload register of
compare match A
FFFFh
Compare register A
FFFFh
1234h
2345h
1234h
2345h
Underflow signal
Figure 25.4
25.3.3
Timing of rewrite operation with TSTART bit value for compare register A
Timer Mode
In timer mode, the AGT counter is decremented by the count source selected with bits TCK[2:0] in the AGTMR1
register. In timer mode, the count value is decremented by 1 on each rising edge of the count source. When the count
value reaches 0000h and the next count source is input, an underflow occurs and an interrupt request is generated.
Figure 25.5 shows the operation example in timer mode.
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25. Asynchronous General-Purpose Timer (AGT)
Count source
Reload register
Previous value
(0300h)
New value (1010h)
Counter reloading occurs
AGT counter
02FAh 02F9h 02F8h 02F7h 1010h 100Fh 100Eh •••••
••••• 0000h 1010h 100Fh 100Eh 100Dh 100Ch 100Bh
TUNDF bit in AGTCR
register
An underflow
occurs
Set to 0 with
software
Underflow signal
Figure 25.5
25.3.4
Operation example in timer mode
Pulse Output Mode
In pulse output mode, the counter is decremented by the count source selected with bits TCK[2:0] in the AGTMR1
register, and the output level of pins AGTIOn and AGTOn pins is inverted each time an underflow occurs.
In pulse output mode, the count value is decremented by 1 on each rising edge of the count source. When the count value
reaches 0000h and the next count source is input, an underflow occurs and an interrupt request is generated. In addition,
a pulse can be output from the AGTIOn and AGTOn pins. The output level is inverted each time an underflow occurs.
The pulse output from the AGTOn pin can be stopped with the TOE bit in the AGTIOC register. The output level can be
selected with the TEDGSEL bit in the AGTIOC register.
Figure 25.6 shows the operation example in pulse output mode.
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25. Asynchronous General-Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register
by a program
Write 0002h to
AGT register by a
program
Write 0004h to
AGT register by a
program
Count source
TSTART bit in
AGTCR register
AGT register
FFFFh
Reload register
FFFFh
AGT counter
FFFFh
0002h
0004h
0002h
0002h
0004h
0001h 0000h 0002h 0001h 0000h 0002h 0001h 0000h 0002h 0001h 0004h 0003h 0002h 0001h 0000h 0004h 0003h
TEDGSEL bit in
AGTIOC register
0
AGTO pin output
AGTIOn pin output
TUNDF bit in
AGTCR register
Set to 0 by a program
Underflow signal
Figure 25.6
25.3.5
Operation example in pulse output mode
Event Counter Mode
In event counter mode, the counter is decremented by an external event signal input to the AGTIOn pin. Various periods
for counting events can be set with the TIOGT[1:0] bits in the AGTIOC and AGTISR registers. In addition, the filter
function for the AGTIOn input can be specified with bits TIPF[1:0] in the AGTIOC register. The output from the
AGTOn pin can be toggled even in event counter mode.
Figure 25.7 shows the operation example in event counter mode.
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25. Asynchronous General-Purpose Timer (AGT)
Event counter mode is entered
Bits TMOD[2:0] in
AGTMR1 register
010b
Event is counted at rising edge
00h
AGTIOC register
TSTART bit
in AGTCR register
Event input is started
Event input is completed
AGTIOn pin
event input
AGT counter
FFFFh
TUNDF bit in
AGTCR register
FFFEh FFFDh
0000h
FFFFh
FFFEh
Counter initial value is set
Set to 0 by a program
Underflow signal
Figure 25.7
Operation example 1 in event counter mode
Figure 25.8 shows an operation example for counting during the specified period in event counter mode (TIOGT[1:0]
bits in the AGTIOC register are set to 01b).
Timing example when the setting of operating mode is as follows :
AGTMR1 register: TMOD[2:0] = 010b (event counter mode)
AGTIOC register: TIOGT[1:0] = 01b (event is counted during specified period for external interrupt pin )
TIPF[1:0] = 00b (no filter)
TEDGSEL = 1 (count at rising edge)
AGTISR register: EEPS = 1 (high-level period is counted)
TSTART bit in
AGTCR register
Event input to
AGTIOn pin
Event input starts
Note 2
Note 1
AGTEEn pin
AGT counter
FFFFh
FFFEh
FFFDh
FFFCh
FFFBh
FFFAh
FFF9h
FFF8h
The counter initial value is set
Figure 25.8
Operation example 2 in event counter mode
Note 1. To control synchronization, there is a delay of 2 cycles of the count source until count operation is affected. It is
also possible that the count start timing is shifted by 1 cycle because of the phase difference between the
AGTEEn and the sampling clock.
Note 2. Count operation can be performed for 2 cycles of the count source immediately after the count starts, depending
on the previous state before the count stops.
To disable the count for 2 cycles immediately after the count starts, write 1 to the TSTOP bit in the AGTCR
register to initialize the internal circuit, and then complete the operation settings before starting the count
operation.
25.3.6
Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the AGTIOn pin is measured. When the
level specified in the TEDGSEL bit in the AGTIOC register is input to the AGTIOn pin, the counter is decremented by
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25. Asynchronous General-Purpose Timer (AGT)
the count source selected by TCK[2:0] bits in the AGTMR1 register. When the specified level on the AGTIOn pin ends,
the counter is stopped, the TEDGF bit in the AGTCR register is set to 1 (active edge received), and an interrupt request is
generated. The measurement of pulse width data is performed by reading the count value while the counter is stopped.
Also, when the counter underflows during measurement, the TUNDF bit in the AGTCR register is set to 1 and an
interrupt request is generated.
Figure 25.9 shows the operation example in pulse width measurement mode.
This example applies when the high-level width of the measurement pulse is measured (TEDGSEL bit in AGTIOC register = 1)
FFFFh
n = AGT register content
Measurement is started
Counter content (hex)
n
Underflow
Measurement
is stopped
Measurement
is stopped
Measurement
is started
0000h
Measurement
is started
Time
TSTART bit in
AGTCR register
Set to 1 by a program
Measurement pulse
input to AGTIOn pin
Underflow event signal/
Measurement complete event signal
TEDGF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
TUNDF bit in
AGTCR register
Set to 0 by a program
Figure 25.9
25.3.7
Operation example in pulse width measurement mode
Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the AGTIOn pin is measured. The
counter is decremented by the count source selected with bits TCK[2:0] in the AGTMR1 register. When a pulse with the
level specified in the TEDGSEL bit in the AGTIOC register is input to the AGTIOn pin, the count value is transferred to
the read-out buffer on the rising edge of the count source. The value in the reload register is loaded to the counter at the
next rising edge. Simultaneously, the TEDGF bit in the AGTCR register is set to 1 (active edge received) and an interrupt
request is generated. The read-out buffer (AGT register) is read at this time and the difference from the reload value (see
section 25.4.5, How to Calculate Event Number, Pulse Width, and Pulse Period) is the period data of the input pulse. The
period data is retained until the read-out buffer is read. When the counter underflows, the TUNDF bit in the AGTCR
register is set to 1 (underflow) and an interrupt request is generated.
Figure 25.10 shows the operation example in pulse period measurement mode.
Only input pulses with a period longer than twice the period of the count source are measured. Also, the low-level and
high-level widths must both be longer than the period of the count source. If a pulse period shorter than these conditions
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25. Asynchronous General-Purpose Timer (AGT)
is input, the input might be ignored.
Count source
TSTART bit
in AGTCR register
Measurement pulse input
Counter is reloaded
AGT counter
Content of read-out buffer
0300h
0300h
02FFh 02FEh 0300h 02FFh 02FEh 02FDh02FCh 02FBh 02FAh 02F9h 02F8h 02F7h 0300h 02FFh ••••
02FFh
02FEh
02FBh 02FAh 02F9h 02F8h
02F7h
•••• 0001h 0000h 0300h 02FFh 02FEh
••••
•••• 0001h 0000h 0300h 02FFh
Counter value is read*1
Read signal of counter
*2
*2
02FEh
02F7h
Read data
TEDGF bit in
AGTCR register
TUNDF bit in
AGTCR register
*3
*3
Set to 0 by a program
*4
Underflow event signal/
Measurement complete event signal
Set to 0 by a program
*5
This example applies when the initial value of the AGT register is set to 0300h, the TEDGSEL bit in the AGTIOC
register is set to 0, and the period from one rising edge to the next edge of the measurement pulse is measured.
Note 1. Reading from the AGT register must be performed during the period from when the TEDGF bit is set to 1
(active edge received) until the next active edge is input. The content of the read-out buffer is retained until
the AGT register is read. If it is not read before the active edge is input, the measurement result of the
previous period is retained.
Note 2. When the AGT register is read in pulse period measurement mode, the content of the read-out buffer is read.
Note 3. When the active edge of the measurement pulse is input and then the set edge of an external pulse is input,
the TEDGF bit in the AGTCR register is set to 1 (active edge received).
Note 4. To set to 0 with software, write 0 to the TEDGF bit in the AGTCR register using an 8-bit memory manipulation
instruction.
Note 5. To set to 0 with software, write 0 to the TUNDF bit in the AGTCR register using an 8-bit memory manipulation
instruction.
Figure 25.10
25.3.8
Operation example in pulse period measurement mode
Compare Match Function
The compare match function detects matches (compare match) between the content of the AGTCMA or AGTCMB
register and the content of the AGT register. This function is enabled when the TCMEA bit or the TCMEB bit in the
AGTCMSR register is 1 (compare match A register or compare match B register is valid). The counter is decremented by
the count source selected with bits TCK[2:0] in the AGTMR1 register, and when the values of AGT and AGTCMA or
AGTCMB match, the TCMAF/TCMBF bit in the AGTCR register is set to 1 (match), and an interrupt request is
generated.
When compare match function is enabled, the timing of the rewrite operation to the reload register and the counter
differs. See section 25.3.1, Reload Register and Counter Rewrite Operation for details. In addition, the output level of the
AGTOAn and AGTOBn pins is inverted by the match and by the underflow. The output level can be selected with the
TOPOLA or TOPOLB bit in the AGTCMSR register.
Figure 25.11 shows the operation example in compare match mode.
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25. Asynchronous General-Purpose Timer (AGT)
n = AGT register content
m = Compare Match A register setting value
p = Compare Match B register setting value
FFFFh
Count starts
Counter content (hex)
Underflow
Underflow
n
Matched
Matched
m
Matched
Matched
p
Time
0000h
TSTART bit in
AGTCR register
Set to 1 by a program
AGTOAn pin
output
Output inverted by compare match
Output inverted by underflow
Output inverted by compare match
Output inverted by underflow
TCMAF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Compare match A
event signal
AGTOBn pin output
Output inverted by underflow
Output inverted by compare match
Output inverted by underflow
Output inverted by compare match
TCMBF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Compare match B
event signal
AGTO pin output
Output inverted by underflow
Output inverted by underflow
TUNDF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Underflow
event signal
Figure 25.11
25.3.9
Operation example in compare match mode (TOPOLA = 0, TOPOLB = 0)
Output Settings for Each Mode
Table 25.5 to Table 25.8 list the states of pins AGTOn, AGTIOn, AGTOAn, and AGTOBn in each mode.
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Table 25.5
25. Asynchronous General-Purpose Timer (AGT)
AGTOn pin setting
AGTIOC register
Operating mode
TOE bit
TEDGSEL bit
AGTOn pin output
All modes
1
1
Inverted output
0
Normal output
0 or 1
Output disabled
0
Table 25.6
AGTIOn pin setting
AGTIOC register
Operating mode
TEDGSEL bit
AGTIOn pin I/O
Timer mode
0 or 1
Input
(not used)
Pulse output mode
1
Normal output
0
Inverted output
0 or 1
Input
Event counter mode
Pulse width measurement mode
Pulse period measurement mode
Table 25.7
AGTOAn pin setting
AGTCMSR register
Operating mode
TOEA bit
TOPOLA bit
AGTOAn pin output
Timer mode
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(not used)
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(not used)
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(not used)
0
0
Prohibited
Pulse output mode
Event counter mode
Pulse width measurement mode
Pulse period measurement mode
Table 25.8
AGTOBn pin setting (1 of 2)
AGTCMSR register
Operating mode
TOEB bit
TOPOLB bit
AGTOBn pin output
Timer mode
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(not used)
1
1
Inverted output
0
Normal output
0 or 1
Output disabled
(not used)
Pulse output mode
0
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Table 25.8
25. Asynchronous General-Purpose Timer (AGT)
AGTOBn pin setting (2 of 2)
AGTCMSR register
Operating mode
TOEB bit
TOPOLB bit
AGTOBn pin output
Event counter mode
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(not used)
0
0
Prohibited
Pulse width measurement mode
Pulse period measurement mode
25.3.10
Standby Mode
The AGT can operate in Software Standby and Deep Software Standby modes. Set it to Software Standby mode or Deep
Software Standby mode with count operation start (TSTART = 1, TCSTF = 1).
Table 25.9 and Table 25.10 show the settings that can be used in Software Standby and Deep Software Standby modes.
Table 25.9
Usable settings for AGT0 in Software Standby and Deep Software Standby modes
Operating mode
TCK[2:0] bits of AGTMR1
register
Operating clock
Resurgence factor of
CPU
Timer mode
100b or 110b
AGTLCLK or AGTSCLK
—
Pulse output mode
100b or 110b
AGTLCLK or AGTSCLK
—
Event counter mode
- (Invalid)
AGTIOn
—
Pulse width measurement mode
100b or 110b
AGTLCLK or AGTSCLK
—
Pulse period measurement mode
100b or 110b
AGTLCLK or AGTSCLK
—
Table 25.10
Usable settings AGT1 in Software Standby and Deep Software Standby modes
Operating mode
TCK[2:0] bits of AGTMR1
register
Operating clock
Resurgence factor of
CPU
Timer mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Compare match A/B
Pulse output mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Compare match A/B
Event counter mode
(Invalid)
AGTIOn
Underflow
Compare match A/B
Pulse width measurement mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Active edge
Pulse period measurement mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Active edge
Note:
Release of Software Standby mode or Deep Software Standby mode is only AGT1.
Note 1. Only when AGT0 operates in Table 25.9.
25.3.11
Interrupt Sources
The AGT has three interrupt sources described in Table 25.11.
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Table 25.11
25. Asynchronous General-Purpose Timer (AGT)
AGT interrupt sources
DMAC/DTC
activation
Name
Interrupt source
AGTn_AGTI
When the counter underflows
When measurement of the active width of the external input (AGTIO) is complete in pulse width
measurement mode
When the set edge of the external input (AGTIO) is input in pulse period measurement mode.
Possible
AGTn_AGTCMAI
When the values of AGT and AGTCMA match
Possible
AGTn_AGTCMBI
When the values of AGT and AGTCMB match
Possible
Note:
Channel number (n = 0 or 1).
25.3.12
Event Signal Output to ELC
The AGT uses the Event Link Controller (ELC) to perform a link operation to a specified module using the interrupt
request signal as the event signal. The AGT outputs compare match A, compare match B, and underflow/measurement
complete signals as event signals. For details, see section 19, Event Link Controller (ELC).
25.4
25.4.1
Usage Notes
Count Operation Start and Stop Control
When the operating mode (see Table 25.1) is set to other than the event counter mode, or the count source is set to
other than AGT0 underflow (TCK[2:0] = 101b):
After 1 (count starts) is written to the TSTART bit in the AGTCR register while the count is stopped, the TCSTF
flag in the AGTCR register remains 0 (count stops) for 3 cycles of the count source. Do not access the registers
associated with AGT*1 other than the TCSTF flag until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF flag remains 1 for 3
cycles of the count source. When the TCSTF flag is set to 0, the count stops. Do not access the registers
associated with AGT*1 other than the TCSTF flag until this bit is set to 0.
Clear the interrupt register before changing the TSTART bit from 0 to 1. See section 14, Interrupt Controller
Unit (ICU) for details.
Note 1. Registers associated with AGT: AGT, AGTCMA, AGTCMB, AGTCR, AGTMR1, AGTMR2, AGTIOC, AGTISR,
and AGTCMSR.
When the operating mode (see Table 25.1) is set to event counter mode, or the count source is set to AGT0
underflow (TCK[2:0] = 101b)
After 1 (count starts) is written to the TSTART bit in the AGTCR register while the count is stopped, the TCSTF
bit in the AGTCR register remains 0 (count stops) for 2 cycles of the PCLKB. Do not access the registers
associated with AGT*1 other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for 2
cycles of the PCLKB. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers
associated with AGT*1 other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TSTART bit from 0 to 1. See section 14, Interrupt Controller
Unit (ICU) for details.
Note 1. Registers associated with AGT: AGT, AGTCMA, AGTCMB, AGTCR, AGTMR1, AGTMR2, AGTIOC, AGTISR
and AGTCMSR.
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25.4.2
25. Asynchronous General-Purpose Timer (AGT)
Access to Counter Register
When the TSTART and TCSTF bits in the AGTCR register are both 1 (count starts), allow at least 3 cycles of the count
source clock between writes when writing to the AGT register successively.
25.4.3
When Changing Mode
The registers associated with AGT operating mode (AGTMR1, AGTMR2, AGTIOC, AGTISR, AGTCMSR and
AGTIOC) can be changed only when the count is stopped with both the TSTART and TCSTF bits set to 0 (count stops).
Do not change these registers during count operation.
When the registers associated with AGT operating mode are changed, the values of bits TEDGF, TUNDF, TCMAF and
TCMBF are undefined. Before starting the count, write 0 to the following bits:
TEDGF (no active edge received)
TUNDF (no underflow)
TCMAF (no match)
TCMBF (no match).
25.4.4
Digital Filter
When using the digital filter, do not start the timer operation for 5 cycles of the digital filter clock after setting bits
TIPF[1:0] and when the TEDGSEL bit in the AGTIOC register changes.
25.4.5
How to Calculate Event Number, Pulse Width, and Pulse Period
In event counter mode, event number is expressed mathematically as follows:
Event number = initial value of counter [AGT register] - counter value of active event end
In pulse width measurement mode, pulse width is expressed mathematically as follows:
Pulse width = counter value of stopping measurement - counter value of next stopping measurement
In pulse period measurement mode, input pulse period is expressed mathematically as follows:
Period of input pulse = (initial value of counter [AGT register] - reading value of the read-out buffer) + 1
25.4.6
When Count Is Forcibly Stopped by TSTOP Bit
After the counter is forcibly stopped by the TSTOP bit in the AGTCR register, do not access the following I/O registers
for 1 cycle of the count source:
AGT
AGTCMA
AGTCMB
AGTCR
AGTMR1
AGTMR2.
25.4.7
When Selecting AGT0 Underflow as the Count Source
Operate the AGT according to the procedures described in this section when selecting the underflow signal of AGT as
the count source.
(1)
Procedure for starting operation
1. Set AGT0 and AGT1.
2. Start the count operation of AGT1.
3. Start the count operation of AGT0.
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25. Asynchronous General-Purpose Timer (AGT)
Procedure for stopping operation
1. Stop the count operation of AGT0.
2. Stop the count operation of AGT1.
3. Stop the count source clock of AGT1 (write 000b in the AGT1.AGTMR1.TCK[2:0] bits).
25.4.8
Reset of I/O Register
The I/O register of AGT is not initialized by different types of resets. For details, see section 6, Resets.
25.4.9
When Selecting PCLKB, PCLKB/8, or PCLKB/2 as the Count Source
When a reset is generated, the operation of AGT cannot be guaranteed. Set the registers associated with AGT again.
25.4.10
When Selecting AGTSCLK or AGTLCLK as the Count Source
The MSTPD2 bit in the MSTPCRD register must be set to 1 except when accessing the AGT1 registers. The MSTPD3
bit in the MSTPCRD register must be set to 1 except when accessing the AGT0 registers. When a reset occurs while
MSTPD2 or MSTPD3 bit is 0, the operation of AGT1 or AGT0 cannot be guaranteed. Set the registers associated with
AGT again.
25.4.11
When Switching Source Clock
When switching a clock source by changing SCKCR.CKSEL[2:0], the clock output from the selector stops for 4 cycles
of the switched clock. Therefore, when using the AGTIO, AGTEE, or both input as external event input, the clock source
should not be switched. If switching the clock source while using the external event input, extend the input pulse width
by 4 clock cycles of the switched source clock cycles.
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26. Realtime Clock (RTC)
26.
Realtime Clock (RTC)
26.1
Overview
The RTC has two counting modes, calendar count mode and binary count mode, these are used by switching register
settings. For calendar count mode, the RTC has a 100 year calendar from 2000 to 2099 and automatically adjusts dates
for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count
mode can be used for calendars other than the Gregorian (Western) calendar.
The sub-clock oscillator or LOCO can be selected as the count source of the time counters. The RTC uses a 128-Hz clock
acquired by dividing the count source by a prescaler. Year, month, date, day-of-week, a.m./p.m. (in 12-hour mode), hour,
minute, second, or 32-bit binary is counted by 1/128 second.
Table 26.1 lists the RTC specifications, Figure 26.1 shows a block diagram, and Table 26.2 lists the I/O pins.
Table 26.1
RTC specifications
Parameter
Specifications
Count mode
Calendar count mode/binary count mode
Count
source*1
Sub-clock oscillator (XCIN) or LOCO
Clock and calendar
functions
Calendar count mode
Year, month, date, day of week, hour, minute, second are counted, BCD display
12 hours/24 hours mode switching function
30 seconds adjustment function (a number less than 30 is rounded down to 00 seconds, and 30 seconds or
more are rounded up to 1 minute)
Automatic adjustment function for leap years
Binary count mode
Count seconds in 32 bits, binary display
Shared by both modes
Start/stop function
The sub-second digit is displayed in binary units (1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, or 64 Hz)
Clock error correction function
Clock (1-Hz/64-Hz) output
Interrupts
Alarm interrupt (RTC_ALM)
As an alarm interrupt condition, selectable for comparison with the following:
Calendar count mode: Year, month, date, day-of-week, hour, minute, or second can be selected
Binary count mode: Each bit of the 32-bit binary counter.
Periodic interrupt (RTC_PRD)
2 seconds, 1 second, 1/2 second, 1/4 second, 1/8 second, 1/16 second, 1/32 second, 1/64 second, 1/128
second, or 1/256 second can be selected as an interrupt period
Carry interrupt (RTC_CUP)
An interrupt is generated at either of the following conditions:
- When a carry from the 64-Hz counter to the second counter is generated
- When the 64-Hz counter is changed and the R64CNT register is read at the same time
Return from Software Standby mode or Deep Software Standby mode can be performed by an alarm
interrupt or periodic interrupt.
Time capture function
Times can be captured when the edge of the time capture event input pin is detected.
For every event input, month, date, hour, minute, and second are captured or the 32-bit binary counter value
is captured.
Event link function
Periodic event output (RTC_PRD)
Note 1.
The frequency of the peripheral module clock (PCLKB) must be the frequency of the count source clock.
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26. Realtime Clock (RTC)
Internal peripheral bus
Realtime clock (RTC)
Bus interface
To each
function
Prescaler
RCR2
XCIN
Sub-clock
oscillator
XCOUT
32.768 kHz
128 Hz generation
Time counter 1-Hz/64-Hz output
128 Hz
for XCIN
RADJ
R64CNT
RSECCNT/
BCNT0
RHRCNT/
BCNT2
RMINCNT/
BCNT1
RDAYCNT
RWKCNT/
BCNT3
RMONCNT
RYRCNT
RCR4
LOCO
128 Hz generation
RTCOUT
Alarm function
RSECAR/
BCNT0AR
RHRAR/
BCNT2AR
RDAYAR/
BCNT0AER
RYRAR
BCNT2AER
RMINAR/
BCNT1AR
RWKAR/
BCNT3AR
RMONAR/
BCNT1AER
RYRAREN/
BCNT3AER
Alarm comparison
Interrupt control
for LOCO
RFRH/
RFRL
RTC_ALM
RTC_PRD
RTC_CUP
Event signal output
(RTC_PRD)
RCR1
Time capture control unit
Time capture
event input pins
RTCICn
RSECCPn/
BCNT0CPn
RMINCPn/
BCNT1CPn
RHRCPn/
BCNT2CPn
RDAYCPn/
BCNT3CPn
RMONCPn
RTCCRn
n = 0 to 2
R64CNT:
RSECCNT/BCNT0:
RMINCNT/BCNT1:
RHRCNT/BCNT2:
RWKCNT/BCNT3:
RDAYCNT:
RMONCNT:
RYRCNT:
64-Hz counter
Second Counter/Binary Counter 0
Minute Counter/Binary Counter 1
Hour Counter/Binary Counter 2
Day-of-week Counter/Binary Counter 3
Date Counter
Month Counter
Year Counter
RCR1:
RCR2:
RCR4:
RADJ:
RSECAR/BCNT0AR:
Rtc Control Register 1
Rtc Control Register 2
Rtc Control Register 4
Time Error Adjustment Register
Second Alarm Register/binary Counter 0
Alarm Register
Figure 26.1
RTC block diagram
Table 26.2
RTC pin configuration
RFRH/RFRL:
RMINAR/BCNT1AR:
RHRAR/BCNT2AR:
RWKAR/BCNT3AR:
RDAYAR/BCNT0AER:
RMONAR/BCNT1AER:
RYRAR/BCNT2AER:
RYRAREN/BCNT3AER:
Frequency Register
Minute Alarm Register/Binary Counter 1 Alarm Register
Hour Alarm Register/Binary Counter 2 Alarm Register
Day-of-week Alarm Register/Binary Counter 3 Alarm Register
Date Alarm Register/Binary Counter 0 Alarm Enable Register
Month Alarm Register/Binary Counter 1 Alarm Enable Register
Year Alarm Register/Binary Counter 2 Alarm Enable Register
Year Alarm Enable Register/Binary Counter 3 Alarm Enable
Register
RTCCRn:
Time Capture Control Register n
RSECCPn/BCNT0CPn: Second Capture Register n/bcnt0 Capture Register n
RMINCPn/BCNT1CPn: Minute Capture Register n/bcnt1 Capture Register n
RHRCPn/BCNT2CPn: Hour Capture Register n/bcnt2 Capture Register n
RDAYCPn/BCNT3CPn: Date Capture Register n/bcnt3 Capture Register n
RMONCPn:
Month Capture Register n
Pin name
I/O
Function
XCIN
Input
Connect a 32.768-kHz crystal to these pins
XCOUT
Output
RTCOUT
Output
This pin is used to output a 1-Hz/64-Hz waveform, but not in Deep Software Standby mode
RTCIC0
Input
RTCIC1
Input
Time capture event input pins.
RTCIC0 to RTCIC2 can be controlled by the VBTICTLR register.
For more information, see section 12, Battery Backup Function and section 20, I/O Ports.
RTCIC2
Input
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26.2
26. Realtime Clock (RTC)
Register Descriptions
Write or read from the RTC registers as described in section 26.6.5, Notes on Writing to and Reading from Registers.
If the value in an RTC register after a reset is given as x (undefined bits) in the list, it is not initialized by a reset. When
RTC enters the reset state or a low power consumption state during counting operations, for example while the
RCR2.START bit is 1, the year, month, day of the week, date, hours, minutes, seconds, and 64-Hz counters continue to
operate.
Note:
A reset generated while writing to a register might destroy the register value. In addition, do not allow the MCU to
enter Software Standby mode or Deep Software Standby mode immediately after setting any of these registers.
For details, see section 26.6.4, Transitions to Low Power Modes after Setting Registers.
26.2.1
64-Hz Counter (R64CNT)
Address(es): RTC.R64CNT 4004 4000h
Value after reset:
b7
b6
b5
b4
b3
—
F1HZ
F2HZ
F4HZ
F8HZ
0
x
x
x
x
b2
b1
b0
F16HZ F32HZ F64HZ
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
b0
F64HZ
64 Hz
Indicate the state between 1 Hz and 64 Hz of the sub-second digit R
R/W
b1
F32HZ
32 Hz
R
b2
F16HZ
16 Hz
R
b3
F8HZ
8 Hz
R
b4
F4HZ
4 Hz
R
b5
F2HZ
2 Hz
R
b6
F1HZ
1 Hz
R
b7
—
Reserved
This bit is read as 0
R
The R64CNT counter is used in both calendar count mode and in binary count mode. The 64-Hz counter (R64CNT)
generates the period for a second by counting up periods of the 128-Hz clock. The state in the sub-second range can be
confirmed by reading this counter.
This counter is cleared to 00h by an RTC software reset or an execution of a 30-second adjustment. To read this counter,
follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
26.2.2
(1)
Second Counter (RSECCNT)/Binary Counter 0 (BCNT0)
In calendar count mode
Address(es): RTC.RSECCNT 4004 4002h
b7
b6
—
Value after reset:
x
b5
b4
b3
SEC10[2:0]
x
x
b2
b1
b0
SEC1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
SEC1[3:0]
1-Second Count
Counts from 0 to 9 every second. When a carry is generated, 1 is
added to the tens place.
R/W
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Bit
26. Realtime Clock (RTC)
Symbol
Bit name
Description
R/W
b6 to b4
SEC10[2:0]
10-Second Count
Counts from 0 to 5 for 60-second counting.
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RSECCNT counter sets and counts the BCD-coded second value. It counts the carries generated once per second in
the 64-Hz counter.
The setting range is decimal 00 to 59. The RTC does not operate normally if any other value is set. Before writing to this
register, be sure to stop the count operation using the START bit in RCR2.
To read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
(2)
In binary count mode
Address(es): RTC.BCNT0 4004 4002h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[7:0]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT0 is a read/write 32-bit binary counter b7 to b0 that performs count operation by a carry generated for each second
of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
26.2.3
(1)
Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1)
In calendar count mode
Address(es): RTC.RMINCNT 4004 4004h
b7
b6
—
x
Value after reset:
b5
b4
b3
MIN10[2:0]
x
x
b2
b1
b0
MIN1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MIN1[3:0]
1-Minute Count
Counts from 0 to 9 every minute. When a carry is generated, 1 is
added to the tens place.
R/W
b6 to b4
MIN10[2:0]
10-Minute Count
Counts from 0 to 5 for 60-minute counting
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RMINCNT counter sets and counts the BCD-coded minute value. It counts the carries generated once every minute
in the second counter.
A value from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
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26. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT1 4004 4004h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[15:8]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT1 is a read/write 32-bit binary counter b15 to b8 that performs count operation by a carry generated for each
second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START bit in
RCR2. To read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
26.2.4
(1)
Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2)
In calendar count mode
Address(es): RTC.RHRCNT 4004 4006h
Value after reset:
b7
b6
b5
—
PM
HR10[1:0]
x
x
x
b4
x
b3
b2
b1
b0
HR1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
HR1[3:0]
1-Hour Count
Counts from 0 to 9 once per hour. When a carry is generated, 1 is
added to the tens place.
R/W
b5, b4
HR10[1:0]
10-Hour Count
Counts from 0 to 2 once per carry from the ones place.
R/W
b6
PM
PM
AM/PM select for time counter setting.
0: AM
1: PM.
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RHRCNT counter sets and counts the BCD-coded hour value. It counts the carries generated once per hour in the
minute counter. The specifiable time differs based on the setting in the hours mode bit (RCR2.HR24):
When the RCR2.HR24 bit is 0 — from 00 to 11 (in BCD)
When the RCR2.HR24 bit is 1 — from 00 to 23 (in BCD).
If a value outside of this range is specified, the RTC does not operate correctly. Before writing to this register, be sure to
stop the count operation using the START bit in RCR2. The PM bit is only enabled when the RCR2.HR24 bit is 0.
Otherwise, the setting in the PM bit has no effect. To read this counter, follow the procedure in section 26.3.5, Reading
64-Hz Counter and Time.
(2)
In binary count mode
Address(es): RTC.BCNT2 4004 4006h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[23:16]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT2 is a read/write 32-bit binary counter b23 to b16 that performs count operation by a carry generated for each
second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START bit in
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26. Realtime Clock (RTC)
RCR2. To read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
26.2.5
(1)
Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3)
In calendar count mode
Address(es): RTC.RWKCNT 4004 4008h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
x
x
x
x
x
b2
b1
b0
DAYW[2:0]
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b2 to b0
DAYW[2:0]
Day-of-Week Counting
b2
R/W
b7 to b3
—
Reserved
Set these bits to 0. They are read as the set value.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: Sunday
1: Monday
0: Tuesday
1: Wednesday
0: Thursday
1: Friday
0: Saturday
1: Setting prohibited.
R/W
The RWKCNT counter is used for setting and counting in the coded day-of-week value. It counts the carries generated
once per day in the hour counter. A value from 0 through 6 can be specified. If a value outside of this range is specified,
the RTC does not operate correctly. Before writing to this register, be sure to stop the count operation using the START
bit in RCR2. To read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
(2)
In binary count mode
Address(es): RTC.BCNT3 4004 4008h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[31:24]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT3 is a read/write 32-bit binary counter b31 to b24 that performs count operation by a carry generated for each
second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START bit in
RCR2. To read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
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26.2.6
26. Realtime Clock (RTC)
Day Counter (RDAYCNT)
Address(es): RTC.RDAYCNT 4004 400Ah
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
DATE10[1:0]
x
x
b2
b1
b0
DATE1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DATE1[3:0]
1-Day Count
Counts from 0 to 9 once per day. When a carry is generated, 1 is
added to the tens place.
R/W
b5, b4
DATE10[1:0]
10-Day Count
Counts from 0 to 3 once per carry from the ones place
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RDAYCNT counter is used in calendar count mode to set and count the BCD-coded date value. It counts the carries
generated once per day in the hour counter. The count operation depends on the month and whether the year is a leap
year. Leap years are determined according to whether the year counter (RYRCNT) value is divisible by 400, 100, and 4.
A value from 01 through 31 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. When specifying a value, the range of specifiable days depends on the month and whether the year is a
leap year. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To read this
counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
26.2.7
Month Counter (RMONCNT)
Address(es): RTC.RMONCNT 4004 400Ch
Value after reset:
b7
b6
b5
b4
—
—
—
MON10
0
0
0
x
b3
b2
b1
b0
MON1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MON1[3:0]
1-Month Count
Counts from 0 to 9 once per month. When a carry is generated, 1
is added to the tens place.
R/W
b4
MON10
10-Month Count
Counts from 0 to 1 once per carry from the ones place
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RMONCNT counter is used in calendar count mode to set and count the BCD-coded month value. It counts the
carries generated once per month in the date counter.
A value from 01 through 12 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
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26.2.8
26. Realtime Clock (RTC)
Year Counter (RYRCNT)
Address(es): RTC.RYRCNT 4004 400Eh
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Value after reset:
b7
b6
b5
b4
b3
YR10[3:0]
x
x
x
b2
b1
b0
YR1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
YR1[3:0]
1-Year Count
Counts from 0 to 9 once per year. When a carry is generated, 1 is
added to the tens place.
R/W
b7 to b4
YR10[3:0]
10-Year Count
Counts from 0 to 9 once per carry from ones place. When a carry
is generated in the tens place, 1 is added to the hundreds place.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RYRCNT counter is used in calendar count mode to set and count the BCD-coded year value. It counts the carries
generated once per year in the month counter.
A value from 00 through 99 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 26.3.5, Reading 64-Hz Counter and Time.
26.2.9
(1)
Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register
(BCNT0AR)
In calendar count mode
Address(es): RTC.RSECAR 4004 4010h
b7
b6
ENB
x
Value after reset:
b5
b4
b3
SEC10[2:0]
x
x
b2
b1
b0
SEC1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
SEC1[3:0]
1 Second
Value for the ones place of seconds
R/W
b6 to b4
SEC10[2:0]
10 Seconds
Value for the tens place of seconds
R/W
b7
ENB
ENB
0: The register value is not compared with the RSECCNT counter value
1: The register value is compared with the RSECCNT counter value.
R/W
RSECAR is an alarm register associated with the BCD-coded second counter RSECCNT. When the ENB bit is set to 1,
the RSECAR value is compared with the RSECCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
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26. Realtime Clock (RTC)
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. RSECAR values
from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate
correctly. This register is cleared to 00h by an RTC software reset.
(2)
In binary count mode
Address(es): RTC.BCNT0AR 4004 4010h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[7:0]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT0AR is a read/write alarm register associated with the 32-bit binary counter b7 to b0. This register is set to 00h by
an RTC software reset.
26.2.10
(1)
Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR)
In calendar count mode
Address(es): RTC.RMINAR 4004 4012h
b7
b6
ENB
x
Value after reset:
b5
b4
b3
MIN10[2:0]
x
x
b2
b1
b0
MIN1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MIN1[3:0]
1 Minute
Value for the ones place of minutes
R/W
b6 to b4
MIN10[2:0]
10 Minutes
Value for the tens place of minutes
R/W
b7
ENB
ENB
0: The register value is not compared with the RMINCNT counter value
1: The register value is compared with the RMINCNT counter value.
R/W
RMINAR is an alarm register associated with the BCD-coded minute counter RMINCNT. When the ENB bit is set to 1,
the RMINAR value is compared with the RMINCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. RMINAR values
from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate
correctly. This register is cleared to 00h by an RTC software reset.
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26. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT1AR 4004 4012h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[15:8]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT1AR is a read/write alarm register associated with the 32-bit binary counter from b15 to b8. This register is cleared
to 00h by an RTC software reset.
26.2.11
(1)
Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register (BCNT2AR)
In calendar count mode
Address(es): RTC.RHRAR 4004 4014h
b7
b6
b5
ENB
PM
HR10[1:0]
x
x
Value after reset:
x
b4
x
b3
b2
b1
b0
HR1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
HR1[3:0]
1 Hour
Value for the ones place of hours
R/W
b5, b4
HR10[1:0]
10 Hours
Value for the tens place of hours
R/W
b6
PM
PM
Time alarm setting:
0: AM
1: PM.
R/W
b7
ENB
ENB
0: The register value is not compared with the RHRCNT counter value
1: The register value is compared with the RHRCNT counter value.
R/W
RHRAR is an alarm register associated with the BCD-coded hour counter RHRCNT. When the ENB bit is set to 1, the
RHRAR value is compared with the RHRCNT value. From the following alarm registers, only those selected with the
ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The specifiable
time differs according to the setting in the hours mode bit (RCR2.HR24):
When the RCR2.HR24 bit is 0 — From 00 to 11 (in BCD)
When the RCR2.HR24 bit is 1 — From 00 to 23 (in BCD).
If a value outside of this range is specified, the RTC does not operate correctly. When the RCR2.HR24 bit is 0, be sure to
set the PM bit. When the RCR2.HR24 bit is 1, the setting in the PM bit has no effect. This register is cleared to 00h by an
RTC software reset.
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26. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT2AR 4004 4014h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[23:16]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT2AR is a read/write alarm register associated with the 32-bit binary counter b23 to b16. This register is set to 00h
by an RTC software reset.
26.2.12
(1)
Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register
(BCNT3AR)
In calendar count mode
Address(es): RTC.RWKAR 4004 4016h
b7
b6
b5
b4
b3
ENB
—
—
—
—
x
x
x
x
x
Value after reset:
b2
b1
b0
DAYW[2:0]
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b2 to b0
DAYW[2:0]
Day-of-Week Setting
b2
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: Sunday
1: Monday
0: Tuesday
1: Wednesday
0: Thursday
1: Friday
0: Saturday
1: Setting prohibited.
b6 to b3
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RWKCNT counter value
1: The register value is compared with the RWKCNT counter value.
R/W
RWKAR is an alarm register associated with the coded day-of-week counter RWKCNT. When the ENB bit is set to 1,
the RWKAR value is compared with the RWKCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values all match, the IR flag associated with the RTC_ALM interrupt is set to 1. RWKAR values
from 0 through 6 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate
correctly. This register is set to 00h by an RTC software reset.
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26. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT3AR 4004 4016h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[31:24]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT3AR is a read/write alarm register associated with the 32-bit binary counter b31 to b24. This register is cleared to
00h by an RTC software reset.
26.2.13
(1)
Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register
(BCNT0AER)
In calendar count mode
Address(es): RTC.RDAYAR 4004 4018h
b7
b6
ENB
—
x
x
Value after reset:
b5
b4
b3
DATE10[1:0]
x
x
b2
b1
b0
DATE1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DATE1[3:0]
1 Day
Value for the ones place of days
R/W
b5, b4
DATE10[1:0]
10 Days
Value for the tens place of days
R/W
b6
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RDAYCNT counter value
1: The register value is compared with the RDAYCNT counter value.
R/W
RDAYAR is an alarm register associated with the BCD-coded date counter RDAYCNT. When the ENB bit is set to 1, the
RDAYAR value is compared with the RDAYCNT value. From the following alarm registers, only those selected with the
ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. RDAYAR values
from 01 through 31 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate
correctly. This register is cleared to 00h by an RTC software reset.
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26. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT0AER 4004 4018h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[7:0]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT0AER is a read/write register to set the alarm enable associated with the 32-bit binary counter b7 to b0. The binary
counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm register
(BCNTAR[31:0]) and, when all match, the IR flag associated with the RTC_ALM interrupt becomes 1. This register is
cleared to 00h by an RTC software reset.
26.2.14
(1)
Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register
(BCNT1AER)
In calendar count mode
Address(es): RTC.RMONAR 4004 401Ah
b7
b6
b5
b4
ENB
—
—
MON10
x
x
x
x
Value after reset:
b3
b2
b1
b0
MON1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MON1[3:0]
1 Month
Value for the ones place of months
R/W
b4
MON10
10 Months
Value for the tens place of months
R/W
b6, b5
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RMONCNT counter value
1: The register value is compared with the RMONCNT counter value.
R/W
RMONAR is an alarm register associated with the BCD-coded month counter RMONCNT. When the ENB bit is set to 1,
the RMONAR value is compared with the RMONCNT value. From the following alarm registers, only those selected
with the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. RMONAR values
from 01 through 12 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate
correctly. This register is cleared to 00h by an RTC software reset.
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26. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT1AER 4004 401Ah
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[15:8]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT1AER is a read/write register for setting the alarm enable associated with the 32-bit binary counter b15 to b8. The
binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm
register (BCNTAR[31:0]) and, when all match, the IR flag associated with the RTC_ALM interrupt is set to 1. This
register is cleared to 00h by an RTC software reset.
26.2.15
(1)
Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register
(BCNT2AER)
In calendar count mode
Address(es): RTC.RYRAR 4004 401Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
YR10[3:0]
x
x
x
b2
b1
b0
YR1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
YR1[3:0]
1 Year
Value for the ones place of years
R/W
b7 to b4
YR10[3:0]
10 Years
Value for the tens place of years
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RYRAR is an alarm register associated with the BCD-coded year counter RYRCNT. RYRAR values from 00 through 99
(in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate correctly. This register
is cleared to 0000h by an RTC software reset.
(2)
In binary count mode
Address(es): RTC.BCNT2AER 4004 401Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[23:16]
x
x
x
x
x
x: Undefined
BCNT2AER is a read/write register for setting the alarm enable associated with the 32-bit binary counter b23 to b16. The
binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm
register (BCNTAR[31:0]) and, when all match, the IR flag associated with the RTC_ALM interrupt is set to 1. This
register is cleared to 0000h by an RTC software reset.
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26.2.16
(1)
26. Realtime Clock (RTC)
Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable
Register (BCNT3AER)
In calendar count mode
Address(es): RTC.RYRAREN 4004 401Eh
b7
b6
b5
b4
b3
b2
b1
b0
ENB
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
Value after reset:
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RYRCNT counter value
1: The register value is compared with the RYRCNT counter value.
R/W
When the ENB bit in RYRAREN is set to 1, the RYRAR value is compared with the RYRCNT value. From the
following alarm registers, only those selected with the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. This register is
cleared to 00h by an RTC software reset.
(2)
In binary count mode
Address(es): RTC.BCNT3AER 4004 401Eh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[31:24]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT3AER is a read/write register for setting the alarm enable associated with the 32-bit binary counter b31 to b24. The
binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm
register (BCNTAR[31:0]) and, when all match, the IR flag associated with the RTC_ALM interrupt is set to 1. This
register is cleared to 00h by an RTC software reset.
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26.2.17
26. Realtime Clock (RTC)
RTC Control Register 1 (RCR1)
Address(es): RTC.RCR1 4004 4022h
b7
b6
b5
b4
PES[3:0]
x
Value after reset:
x
x
b3
b2
b1
b0
RTCOS
PIE
CIE
AIE
0
x
0
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
AIE
Alarm Interrupt Enable
0: An alarm interrupt request is disabled
1: An alarm interrupt request is enabled.
R/W
b1
CIE
Carry Interrupt Enable
0: A carry interrupt request is disabled
1: A carry interrupt request is enabled.
R/W
b2
PIE
Periodic Interrupt Enable
0: A periodic interrupt request is disabled
1: A periodic interrupt request is enabled.
R/W
b3
RTCOS
RTCOUT Output Select
0: RTCOUT outputs 1 Hz
1: RTCOUT outputs 64 Hz.
R/W
b7 to b4
PES[3:0]
Periodic Interrupt Select
b7
R/W
Note 1.
b4
0 1 1 0: Generate periodic interrupt every 1/256 second*1
0 1 1 1: Generate periodic interrupt every 1/128 second
1 0 0 0: Generate periodic interrupt every 1/64 second
1 0 0 1: Generate periodic interrupt every 1/32 second
1 0 1 0: Generate periodic interrupt every 1/16 second
1 0 1 1: Generate periodic interrupt every 1/8 second
1 1 0 0: Generate periodic interrupt every 1/4 second
1 1 0 1: Generate periodic interrupt every 1/2 second
1 1 1 0: Generate periodic interrupt every 1 second
1 1 1 1: Generate periodic interrupt every 2 seconds.
Other settings: No periodic interrupts are generated.
When LOCO is selected (RCR4.RCKSEL = 1) while PES[3:0] = 0110b, a periodic interrupt is generated every 1/128 second.
The RCR1 register is used in both calendar count mode and in binary count mode. Bits AIE, PIE, and PES[3:0] are
updated synchronously with the count source. When the RCR1 register is modified, check that all the bits are updated
before proceeding.
AIE bit (Alarm Interrupt Enable)
The AIE bit enables or disables alarm interrupt requests.
If the times indicated in the counters and alarm settings match in Deep Software Standby mode, the MCU returns from
the mode regardless of the AIE bit value.
CIE bit (Carry Interrupt Enable)
The CIE bit enables or disables interrupt requests when a carry to the RSECCNT/BCNT0 register occurs, or when a
carry to the 64-Hz counter (R64CNT) occurs while reading the 64-Hz counter.
PIE bit (Periodic Interrupt Enable)
The PIE bit enables or disabled a periodic interrupt.
If the periods indicated in the counters and PES[3:0] settings match in Deep Software Standby mode, the MCU returns
from the mode regardless of the PIE bit value.
RTCOS bit (RTCOUT Output Select)
The RTCOS bit selects the RTCOUT output period. The RTCOS bit must be rewritten while the count operation is
stopped (the RCR2.START bit is 0) and the RTCOUT output is disabled (the RCR2.RTCOE bit is 0). When RTCOUT is
output to an external pin, the RCR2.RTCOE bit must be enabled. For details on controlling the I/O ports, see section
20.5.1, Procedure for Specifying the Pin Functions.
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26. Realtime Clock (RTC)
PES[3:0] bits (Periodic Interrupt Select)
The PES[3:0] bits specify the period for the periodic interrupt. A periodic interrupt is generated with the period specified
in these bits.
26.2.18
(1)
RTC Control Register 2 (RCR2)
In calendar count mode
Address(es): RTC.RCR2 4004 4024h
b7
CNTM
D
Value after reset:
x
b6
b5
b4
b3
b2
b1
b0
HR24 AADJP AADJE RTCOE ADJ30 RESET START
x
x
x
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
START
Start
0: Prescaler and time counter are stopped
1: Prescaler and time counter operate normally.
R/W
b1
RESET
RTC Software Reset
In writing
0: Invalid (writing 0 has no effect)
1: The prescaler and the target registers for RTC software
reset *1 are initialized.
In reading
0: Normal time operation in progress, or an RTC software
reset has completed
1: RTC software reset in progress.
R/W
b2
ADJ30
30-Second Adjustment
In writing
0: Invalid (writing 0 has no effect)
1: 30-second adjustment is executed.
In reading
0: Normal time operation in progress, or 30-second adjustment has completed
1: 30-second adjustment in progress.
R/W
b3
RTCOE
RTCOUT Output Enable
0: RTCOUT output disabled
1: RTCOUT output enabled.
R/W
b4
AADJE
Automatic Adjustment Enable*2
0: Automatic adjustment is disabled
1: Automatic adjustment is enabled.
R/W
b5
AADJP
Automatic Adjustment Period
Select*2
0: The RADJ.ADJ[5:0] setting value is adjusted from the count
value of the prescaler every minute
1: The RADJ.ADJ[5:0] setting value is adjusted from the count
value of the prescaler every 10 seconds.
R/W
b6
HR24
Hours Mode
0: RTC operates in 12-hour mode
1: RTC operates in 24-hour mode.
R/W
b7
CNTMD
Count Mode Select
0: Calendar count mode
1: Binary count mode.
R/W
Note 1.
Note 2.
R64CNT, RSECAR/BCNT0AR, RMINAR/BCNT1AR, RHRAR/BCNT2AR, RWKAR/BCNT3AR, RDAYAR/BCNT0AER,
RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RTCCRy, RSECCPy/BCNT0CPy,
RMINCPy/BCNT1CPy, RHRCPy/BCNT2CPy, RDAYCPy/BCNT3CPy, RMONCPy, RCR2.ADJ30, RCR2.AADJE,
RCR2.AADJP.
When LOCO is selected, the setting of this bit is disabled.
The RCR2 register is related to hours mode, automatic adjustment function, enabling RTCOUT output, 30-second
adjustment, RTC software reset, and controlling count operation.
START bit (Start)
The START bit stops or restarts the prescaler or time counter operation. This bit is updated in synchronization with the
next cycle of the count source. When the START bit is modified, check that the bit is updated before proceeding.
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26. Realtime Clock (RTC)
RESET bit (RTC Software Reset)
The RESET bit initializes the prescaler and registers to be reset by RTC software.
When 1 is written to the RESET bit, initialization starts in synchronization with the count source. When the initialization
is complete, the RESET bit is automatically set to 0. Check that this bit is 0 before proceeding.
ADJ30 bit (30-Second Adjustment)
The ADJ30 bit is for 30-second adjustment.
When 1 is written to the ADJ30 bit, the RSECCNT value of 30 seconds or less is rounded down to 00 second and the
value of 30 seconds or more is rounded up to 1 minute.
The 30-second adjustment is performed in synchronization with the count source. When 1 is written to this bit, the
ADJ30 bit is automatically set to 0 after the 30-second adjustment is complete. If 1 is written to the ADJ30 bit, check that
the bit is 0 before proceeding. When the 30-second adjustment is performed, the prescaler and R64CNT are also reset.
The ADJ30 bit is cleared to 0 by an RTC software reset.
RTCOE bit (RTCOUT Output Enable)
The RTCOE bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin.
Use the START bit to stop counting before changing the value of the RTCOE bit. Do not stop counting (write 0 to the
START bit) and change the value of the RTCOE bit at the same time.
When RTCOUT is to be output from an external pin, enable the RTCOE bit and set up the port control for the pin.
AADJE bit (Automatic Adjustment Enable*2)
The AADJE bit controls (enables or disables) automatic adjustment.
Set the plus-minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJE bit.
The AADJE bit is cleared to 0 by an RTC software reset.
AADJP bit (Automatic Adjustment Period Select*2)
The AADJP bit selects the automatic-adjustment period.
Set the plus-minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJP bit.
The AADJP bit is cleared to 0 by an RTC software reset.
HR24 bit (Hours Mode)
The HR24 bit specifies whether the RTC operates in 12- or 24-hour mode.
Use the START bit to stop counting before changing the value of the HR24 bit. Do not stop counting (write 0 to the
START bit) and change the value of the HR24 bit at the same time.
CNTMD bit (Count Mode Select)
The CNTMD bit specifies whether the RTC count mode operates in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings. This bit is updated
synchronously with the count source, and its value is fixed before the RTC software reset is complete.
For details on initial settings, see section 26.3.1, Outline of Initial Settings of Registers after Power On.
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26. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.RCR2 4004 4024h
b7
b6
CNTM
D
—
x
x
Value after reset:
b5
b4
b3
AADJP AADJE RTCOE
x
x
0
b2
—
b1
b0
RESET START
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
START
Start
0: The 32-bit binary counter, 64-Hz counter, and prescaler are
stopped
1: The 32-bit binary counter, 64-Hz counter, and prescaler are
in normal operation.
R/W
b1
RESET
RTC Software Reset
In writing
0: Invalid (writing 0 has no effect)
1: The prescaler and the target registers for RTC software
reset*1 are initialized.
In reading
0: Normal time operation in progress, or RTC software reset
has completed
1: RTC software reset in progress.
R/W
b2
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b3
RTCOE
RTCOUT Output Enable
0: Disable RTCOUT output
1: Enable RTCOUT output.
R/W
b4
AADJE
Automatic Adjustment Enable*2
0: Disable automatic adjustment
1: Enable automatic adjustment.
R/W
b5
AADJP
Automatic Adjustment Period
Select*2
0: Add or subtract RADJ.ADJ [5:0] bits from prescaler count
value every 32 seconds
1: Add or subtract RADJ.ADJ [5:0] bits from prescaler count
value every 8 seconds.
R/W
b6
—
Reserved
This bit is undefined. The write value should be 0.
R/W
b7
CNTMD
Count Mode Select
0: Calendar count mode
1: Binary count mode.
R/W
Note 1.
Note 2.
R64CNT, RSECAR/BCNT0AR, RMINAR/BCNT1AR, RHRAR/BCNT2AR, RWKAR/BCNT3AR, RDAYAR/BCNT0AER,
RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RTCCRy, RSECCPy/BCNT0CPy,
RMINCPy/BCNT1CPy, RHRCPy/BCNT2CPy, RDAYCPy/BCNT3CPy, RMONCPy, RCR2.ADJ30, RCR2.AADJE,
RCR2.AADJP.
When LOCO is selected, the setting of this bit is disabled.
START bit (Start)
The START bit stops or restarts the prescaler or counter (clock) operation. This bit is updated in synchronization with the
count source. When the START bit is modified, check that the bit is updated before proceeding.
RESET bit (RTC Software Reset)
The RESET bit initializes the prescaler and registers to be reset by RTC software.
When 1 is written to the RESET bit, initialization starts in synchronization with the count source. When the initialization
is complete, the RESET bit is automatically set to 0. When 1 is written to the RESET bit, check that the bit is 0 before
proceeding.
RTCOE bit (RTCOUT Output Enable)
The RTCOE bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin.
Use the START bit to stop counting before changing the value of the RTCOE bit. Do not stop counting (write 0 to the
START bit) and change the value of the RTCOE bit at the same time. When an RTCOUT signal is to be output from an
external pin, enable the port control in addition to setting this bit.
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26. Realtime Clock (RTC)
AADJE bit (Automatic Adjustment Enable*2)
The AADJE bit controls (enables or disables) automatic adjustment.
Set the plus-minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJE bit. The AADJE bit is cleared to 0 by an RTC software reset.
AADJP bit (Automatic Adjustment Period Select*2)
The AADJP bit selects the automatic-adjustment period.
Correction period can be selected from 32 second units or 8 second units in binary count mode.
Set the plus-minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJP bit. The AADJP bit is cleared to 0 by an RTC software reset.
CNTMD bit (Count Mode Select)
The CNTMD bit specifies whether the RTC count mode operates in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings. This bit is updated
synchronously with the count source, and its value is fixed before the RTC software reset is complete.
For details on initial settings, see section 26.3.1, Outline of Initial Settings of Registers after Power On.
26.2.19
RTC Control Register 4 (RCR4)
Address(es): RTC.RCR4 4004 4028h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
RCKSE
L
0
0
0
0
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RCKSEL
Count Source Select
0: Sub-clock oscillator is selected
1: LOCO is selected.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RCR4 register selects the count source and is used in both calendar count mode and binary count mode.
When the RCKSEL bit is set to 0, the time is counted with the sub-clock oscillator. When the bit is set to 1, the time is
counted with LOCO.
RCKSEL bit (Count Source Select)
The RCKSEL bit selects the count source from the sub-clock oscillator and LOCO.
The count source must be selected only once before specifying the initial settings of the RTC registers at power on.
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26.2.20
26. Realtime Clock (RTC)
Frequency Register (RFRH/RFRL)
Address(es): RTC.RFRH.4004 402Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RFC16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RFC16
Reserved
Write 0 before writing to the RFRL register after a cold start
R/W
b15 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Address(es): RTC.RFRL.4004 402Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
RFC[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b15 to b0
RFC[15:0]
Frequency Comparison
Value
Write 00FFh to this register when using the LOCO
R/W
RFRL is a register for controlling the prescaler when LOCO is selected.
The RTC time counter operates on a 128-Hz clock signal as the base clock. Therefore, when LOCO is selected, LOCO is
divided by the prescaler to generate a 128-Hz clock signal. Set the frequency comparison value in the RFC[15:0] bits to
generate a 128-Hz clock from the LOCO frequency. Before writing to RFC[15:0] after a cold start, write 0000h to the
RFRH register.
A value from 0007h through 01FFh can be specified as the frequency comparison value. If a value outside of this range
is specified, the RTC does not operate correctly. Before writing to this register, be sure to stop the count operation
through the setting of the START bit in RCR2. The operating frequency of the peripheral module clock and the LOCO
should be such that the peripheral module clock is to the LOCO.
Calculation method of frequency comparison value:
RFC[15:0] = (LOCO clock frequency) / 128 - 1
When the LOCO frequency is 32.768 kHz, the RFRL register should be set to 00FFh.
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26.2.21
26. Realtime Clock (RTC)
Time Error Adjustment Register (RADJ)
Address(es): RTC.RADJ 4004 402Eh
b7
b6
b5
b4
PMADJ[1:0]
x
Value after reset:
x
b3
b2
b1
b0
x
x
ADJ[5:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b5 to b0
ADJ[5:0]
Adjustment Value
These bits specify the adjustment value from the prescaler
R/W
b7, b6
PMADJ[1:0]
Plus-Minus
b7 b6
R/W
0
0
1
1
0: Adjustment is not performed
1: Adjustment is performed by the addition to the prescaler
0: Adjustment is performed by the subtraction from the prescaler
1: Setting prohibited.
Adjustment is performed by the addition to or subtraction from the prescaler. If the automatic adjustment enable
(RCR2.AADJE) bit is 0, adjustment is performed when writing to the RADJ. If the RCR2.AADJE bit is 1, adjustment is
performed in the interval specified in the automatic adjustment period select (RCR2.AADJP) bit.
The current adjustment by software (disabling automatic adjustment) might be invalid if the following adjustment value
is specified within 320 cycles of the count source after the register setting. To perform adjustment consecutively, wait for
320 cycles or more of the count source after the register setting, then specify the next adjustment value.
RADJ is updated in synchronization with the count source. When RADJ is modified, check that all the bits are updated
before continuing with additional processing. This register is cleared to 00h by an RTC software reset. The setting of this
register is enabled only when the sub-clock oscillator is selected. When LOCO is selected, adjustment is not performed.
ADJ[5:0] bits (Adjustment Value)
The ADJ[5:0] bits specify the adjustment value (number of sub-clock cycles) from the prescaler.
PMADJ[1:0] bits (Plus-Minus)
The PMADJ[1:0] bits select whether the clock is set ahead or back depending on the error-adjustment value set in the
ADJ[5:0] bits.
26.2.22
Time Capture Control Register y (RTCCRy) (y = 0 to 2)
Address(es): RTC.RTCCR0 4004 4040h, RTC.RTCCR1 4004 4042h, RTC.RTCCR2 4004 4044h
b7
b6
b5
b4
b3
b2
TCEN
—
TCNF[1:0]
—
TCST
x
x
x
x
x
Value after reset:
x
b1
b0
TCCT[1:0]
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b1, b0
TCCT[1:0]
Time Capture Control
b1 b0
R/W
b2
TCST
Time Capture Status
0: No event is detected
1: An event is detected.*1
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
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0
0
1
1
0: No event is detected
1: Rising edge is detected
0: Falling edge is detected
1: Both edges are detected.
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26. Realtime Clock (RTC)
Bit
Symbol
Bit name
Description
R/W
b5, b4
TCNF[1:0]
Time Capture Noise
Filter Control
b5 b4
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
TCEN
Time Capture Event
Input Pin Enable
0: The RTCICn pin is disabled as the time capture event input
1: The RTCICn pin is enabled as the time capture event input.
(n = 0 to 2).
R/W
Note 1.
0
0
1
1
0: Noise filter is off
1: Setting prohibited
0: Noise filter is on (count source)
1: Noise filter is on (count source by divided by 32).
Indicates that an event is detected. Writing 1 to this bit has no effect. Writing 0 sets this bit to 0.
The RTCCRy register is used both in calendar count mode and in binary count mode. RTCCR0, RTCCR1, and RTCCR2
control the RTCIC0, RTCIC1, and RTCIC2 pins, respectively.
RTCCRy is updated in synchronization with the count source. When RTCCRy is modified, check that all the bits except
the TCST bit are updated before continuing with more processing. This register is cleared to 00h by an RTC software
reset. When RTCICn is used as the time capture pin, VBTICTLR.VCHnIEN (n = 0 to 2) must be set to 1. For more
information, see section 12, Battery Backup Function.
TCCT[1:0] bits (Time Capture Control)
The TCCT[1:0] bits control the edge detection of the time capture event input pins, RTCIC0, RTCIC1, and RTCIC2. The
detection edge is selectable. The TCCT[1:0] bits must be set while the VBTICTLR.VCHnIEN bit is 1.
TCST bit (Time Capture Status)
The TCST bit indicates that an event on the time capture event input pins, RTCIC0, RTCIC1, and RTCIC2, was detected.
When the TCST bit is 0, no event is detected. When the TCST bit is 1, this bit indicates that an event was detected on the
associated pin and the capture register is valid. When multiple events are detected, the capture time for the first event is
retained.
If an event is detected while the count operation is stopped (the RCR2.START bit is 0), the captured value is not
guaranteed. In this case, set the TCST bit to 0 to delete the captured value. Writing 0 sets the TCST bit to 0. Writing any
value other than 0 has no effect.
Set the TCST bit while the TCCT[1:0] bits are 00b (no event is detected). The TCST bit is set to 0 in synchronization
with the count source. When the TCST bit is set to 0, check that the bit is updated before continuing with additional
processing.
TCNF[1:0] bits (Time Capture Noise Filter Control)
The TCNF[1:0] bits control the noise filter of the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2).
When the noise filter is on, the count source divided by 1 or divided by 32 is selectable. In this case, when the input level
on the time capture event input pin matches three consecutive times at the set sampling period, the input level is
determined.
Set the TCNF[1:0] bits while the TCCT[1:0] bits are 00b (no event is detected). When the noise filter is used, set the
TCNF[1:0] bits, wait for 3 cycles of the specified sampling period, then set the TCCT[1:0] bits. Set the TCNF[1:0] bits
when the VBTICTLR.VCHnIEN bit is 1.
TCEN bit (Time Capture Event Input Pin Enable)
The TCEN bit enables or disables the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2). When the
functions of the time capture event input pins are multiplexed, VBTICTLR should be set first. If the TCEN bit is set to 0,
also set the TCCT[1:0] bits to 00b.
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26.2.23
(1)
26. Realtime Clock (RTC)
Second Capture Register y (RSECCPy) (y = 0 to 2)/BCNT0 Capture Register y
(BCNT0CPy) (y = 0 to 2)
In calendar count mode
Address(es): RTC.RSECCP0 4004 4052h, RTC.RSECCP1 4004 4062h, RTC.RSECCP2 4004 4072h
b7
b6
—
b4
b3
SEC10[2:0]
x
Value after reset:
b5
x
x
b2
b1
b0
SEC1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
SEC1[3:0]
1-Second Capture
Capture value for the ones place of seconds
R
b6 to b4
SEC10[2:0]
10-Second Capture
Capture value for the tens place of seconds
R
b7
—
Reserved
This bit is read as 0 after an RTC software reset
R
RSECCPy is a read-only register that captures the RSECCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RSECCP0, RSECCP1,
and RSECCP2 registers, respectively. This register is cleared to 00h by an RTC software reset. Before reading from this
register, be sure to stop the time capture event detection using the RTCCRy.TCCT[1:0] bits.
(2)
In binary count mode
Address(es): RTC.BCNT0CP0 4004 4052h, RTC.BCNT0CP1 4004 4062h, RTC.BCNT0CP2 4004 4072h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTCPy[7:0]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT0CPy is a read-only register that captures the BCNT0 value when a time capture event is detected. The event
detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the BCNT0CP0, BCNT0CP1, and
BCNT0CP2 registers, respectively.
This register is cleared to 00h by an RTC software reset. Before reading from this register, be sure to stop the time
capture event detection using the RTCCRy.TCCT[1:0] bits.
26.2.24
(1)
Minute Capture Register y (RMINCPy) (y = 0 to 2)/BCNT1 Capture Register y
(BCNT1CPy) (y = 0 to 2)
In calendar count mode
Address(es): RTC.RMINCP0 4004 4054h, RTC.RMINCP1 4004 4064h, RTC.RMINCP2 4004 4074h
b7
b6
—
Value after reset:
x
b5
b4
b3
MIN10[2:0]
x
x
b2
b1
b0
MIN1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MIN1[3:0]
1-Minute Capture
Capture value for the ones place of minutes
R
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Bit
26. Realtime Clock (RTC)
Symbol
Bit name
Description
R/W
b6 to b4
MIN10[2:0]
10-Minute Capture
Capture value for the tens place of minutes
R
b7
—
Reserved
This bit is read as 0 after an RTC software reset
R
RMINCPy is a read-only register that captures the RMINCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RMINCP0, RMINCP1,
and RMINCP2 registers, respectively.
This register is cleared to 00h by an RTC software reset. Before reading from this register, be sure to stop the time
capture event detection using the RTCCRy.TCCT[1:0] bits.
(2)
In binary count mode
Address(es): RTC.BCNT1CP0 4004 4054h, RTC.BCNT1CP1 4004 4064h, RTC.BCNT1CP2 4004 4074h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTCPy[15:8]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT1CPy is a read-only register that captures the BCNT1 value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the BCNT1CP0,
BCNT1CP1, and BCNT1CP2 registers, respectively.
This register is cleared to 00h by an RTC software reset. Before reading from this register, be sure to stop the time
capture event detection using the RTCCRy.TCCT[1:0] bits.
26.2.25
(1)
Hour Capture Register y (RHRCPy) (y = 0 to 2)/BCNT2 Capture Register y
(BCNT2CPy) (y = 0 to 2)
In calendar count mode
Address(es): RTC.RHRCP0 4004 4056h, RTC.RHRCP1 4004 4066h, RTC.RHRCP2 4004 4076h
Value after reset:
b7
b6
b5
—
PM
HR10[1:0]
x
x
x
b4
x
b3
b2
b1
b0
HR1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
HR1[3:0]
1-Hour Capture
Capture value for the ones place of hours
R
b5, b4
HR10[1:0]
10-Hour Capture
Capture value for the tens place of hours
R
b6
PM
PM
0: AM
1: PM.
R
b7
—
Reserved
This bit is read as 0 after an RTC software reset
R
RHRCPy is a read-only register that captures the RHRCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RHRCP0, RHRCP1, and
RHRCP2 registers, respectively. The PM bit is only enabled when the RCR2.HR24 bit is 0 (in 12-hour mode).
This register is cleared to 00h by an RTC software reset. Before reading from this register, be sure to stop the time
capture event detection using the RTCCRy.TCCT[1:0] bits.
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(2)
26. Realtime Clock (RTC)
In binary count mode
Address(es): RTC.BCNT2CP0 4004 4056h, RTC.BCNT2CP1 4004 4066h, RTC.BCNT2CP2 4004 4076h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTCPy[23:16]
x
Value after reset:
x
x
x
x
x: Undefined
BCNT2CPy is a read-only register that captures the BCNT2 value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the BCNT2CP0,
BCNT2CP1, and BCNT2CP2 registers, respectively.
This register is cleared to 00h by an RTC software reset. Before reading from this register, you must stop the time capture
event detection using the RTCCRy.TCCT[1:0] bits.
26.2.26
(1)
Date Capture Register y (RDAYCPy) (y = 0 to 2)/BCNT3 Capture Register y
(BCNT3CPy) (y = 0 to 2)
In calendar count mode:
Address(es): RTC.RDAYCP0 4004 405Ah, RTC.RDAYCP1 4004 406Ah, RTC.RDAYCP2 4004 407Ah
Value after reset:
b7
b6
—
—
x
x
b5
b4
b3
DATE10[1:0]
x
x
b2
b1
b0
DATE1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DATE1[3:0]
b5, b4
DATE10[1:0]
1-Day Capture
Capture value for the ones place of days
R
10-Day Capture
Capture value for the tens place of days
R
b7, b6
—
Reserved
These bits are read as 0 after an RTC software reset
R
RDAYCPy is a read-only register that captures the RDAYCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RDAYCP0, RDAYCP1,
and RDAYCP2 registers, respectively.
This register is cleared to 00h by an RTC software reset. Before reading from this register, be sure to stop the time
capture event detection using the RTCCRy.TCCT[1:0] bits.
(2)
In binary count mode
Address(es): RTC.BCNT3CP0 4004 405Ah, RTC.BCNT3CP1 4004 406Ah, RTC.BCNT3CP2 4004 407Ah
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTCPy[31:24]
Value after reset:
x
x
x
x
x
x: Undefined
BCNT3CPy is a read-only register that captures the BCNT3 value when a time capture event is detected.
The event detection times detected by the RTCTC0, RTCTC1, and RTCTC2 pins are stored in the BCNT3CP0,
BCNT3CP1, and BCNT3CP2 registers, respectively.
This register is cleared to 00h by an RTC software reset. Before reading from this register, be sure to stop the time
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26. Realtime Clock (RTC)
capture event detection using the RTCCRy.TCCT[1:0] bits.
26.2.27
(1)
Month Capture Register y (RMONCPy) (y = 0 to 2)
In calendar count mode:
Address(es): RTC.RMONCP0 4004 405Ch, RTC.RMONCP1 4004 406Ch, RTC.RMONCP2 4004 407Ch
Value after reset:
b7
b6
b5
b4
—
—
—
MON10
x
x
x
x
b3
b2
b1
b0
MON1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MON1[3:0]
1-Month Capture
Capture value for the ones place of months
R
b4
MON10
10-Month Capture
Capture value for the tens place of months
R
b7 to b5
—
Reserved
These bits are read as 0
R
RMONCPy is a read-only register that captures the RMONCNT value when a time capture event is detected.
The event detection times detected by the RTCIC0, RTCIC1, and RTCIC2 pins are stored in the RMONCP0,
RMONCP1, and RMONCP2 registers, respectively.
This register is cleared to 00h by an RTC software reset. Before reading from this register, be sure to stop the time
capture event detection using the RTCCRy.TCCT[1:0] bits.
26.3
Operation
26.3.1
Outline of Initial Settings of Registers after Power On
After the power is turned on, perform the initial settings for the clock setting, count mode setting, time error adjustment,
time setting, alarm, interrupt, and time capture control register.
Power on
Clock and count mode settings
Clock supply setting and count mode setting
Set the time
Time setting in the clock counter and initial
setting of the time error adjustment register
Set the alarm
Set the interrupt
Set the time capture control register
Figure 26.2
Initial setting of the alarm register
Initial setting of the interrupt control register
Initial setting of the time capture control register
Outline of initial settings after a power on
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26.3.2
26. Realtime Clock (RTC)
Clock and Count Mode Setting Procedure
Figure 26.3 shows how to set the clock and the count mode.
Select the count source
RCR4.RCKSEL bit setting
Supply 6 clocks of the count source
Supply 6 clocks of the clock selected by the
RCR4.RCKSEL bit
Set the START bit to 0
No
START = 0
Wait for the RCR2.START bit to become 0
Yes
No (LOCO)
RCKSEL = 0
Set frequency register
Yes (Sub-clock)
Select count mode
Execute RTC software reset
No
RESET = 0
RCR2.CNTMD bit setting*1
Write 1 to the RCR2.RESET bit
Wait for the RCR2.RESET bit to become 0
Yes
Note 1. This step is not required if the count mode is set concurrently by setting the START bit to 0.
A value associated with the count mode setting must be written to the RCR2.CNTMD bit.
Figure 26.3
26.3.3
Clock and count mode setting procedure
Setting the Time
Figure 26.4 shows how to set the time.
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26. Realtime Clock (RTC)
Set the START bit to 0
No
Write 0 to the RCR2.START bit
Wait for the RCR2.START bit to become 0
START = 0
Yes
Write 1 to the RCR2.RESET bit*1
Execute an RTC software reset
No
RESET = 0
Wait for the RCR2.RESET bit to become 0
Yes
Set the year, month, day of the week,
date, hour, minute, and second/binary
counters 3 to 0
Settings in arbitrary order is possible
No (LOCO)
RCKSEL = 0
Yes (Sub-clock)
Set clock error adjustment values
Set the START bit to 1
No
Set clock error
adjustment values
Write 1 to the RCR2.START bit
Wait for the RCR2.START bit to become 1
START = 1
Yes
Note 1. This step is not required for the time-setting procedure because an RTC software reset is
executed in the clock setting procedure of the initial settings for the power supply.
Figure 26.4
26.3.4
Setting the time
30-Second Adjustment
Figure 26.5 shows how to execute a 30-second adjustment.
Clock is in operation
Set the RCR2.ADJ30 bit to 1
No
ADJ30 = 0
Execute 30-second adjustment while the clock is in operation
(the RCR2.START bit is 1)
Write 1 to the RCR2.ADJ30 bit
Wait for the RCR2.ADJ30 bit to become 0
Yes
Figure 26.5
30-second adjustment
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26.3.5
26. Realtime Clock (RTC)
Reading 64-Hz Counter and Time
Figure 26.6 shows how to read a 64-Hz counter and time.
(a) To read the time without using interrupt
Disable the NVIC carry interrupt request
Write 1 to the Interrupt Clear-Enable Register
corresponding to the RTC_CUP interrupt
Enable the RTC carry interrupt request
Write 1 to the RCR1.CIE bit
Clear the interrupt flag
Write 0 to the IELSRn.IR bit and write 1 to the
Interrupt Clear-Pending Register
corresponding to the RTC_CUP interrupt
Read the counter
Yes
Pending status = 1?
Read the counter again when the Interrupt SetPending Register corresponding to the RTC_CUP
interrupt is 1
No
(b) To read the time using interrupts
Clear the interrupt flag
Enable the NVIC carry interrupt request
Enable the RTC carry interrupt request
Clear the interrupt flag
Write 0 to the IELSRn.IR bit and write
1 to the Interrupt Clear-Pending
Register corresponding to the
RTC_CUP interrupt
Write 1 to the Interrupt Set-Enable Register
corresponding to the RTC_CUP interrupt
Write 1 to the RCR1.CIE bit
Write 0 to the IELSRn.IR bit and write 1
to the Interrupt Clear-Pending Register
corresponding to the RTC_CUP interrupt
Read the counter
Yes
Interrupt?
No
Disable the RTC carry interrupt
Note 1.
Figure 26.6
Write 0 to the RCR1.CIE bit*1
Disable interrupts if required.
Reading time
If a carry occurs while the 64-Hz counter and time are being read, the correct time is not obtained, therefore they must be
read again. The procedure for reading the time without using interrupts is shown in (a) in Figure 26.6, and the procedure
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26. Realtime Clock (RTC)
using carry interrupts is shown in (b). To keep the program simple, Renesas recommends using method (a) in most cases.
26.3.6
Alarm Function
Figure 26.7 shows how to use the alarm function.
Disable the NVIC alarm interrupt request
Set alarm time
Enable the RTC alarm interrupt request
Wait for the completion of the alarm time
setting
Clear the interrupt flag
Enable the NVIC alarm interrupt request
Monitor alarm time
(wait for interrupt or check alarm flag)
Figure 26.7
Write 1 to the Interrupt Clear-Enable Register
corresponding to the RTC_ALM interrupt
Set alarm enable at the same time as or after the
alarm time setting
Write 1 to the RCR1.AIE bit
Wait for 200 µs or more
Write 0 to the IELSRn.IR bit and write 1 to the Interrupt
Clear-Pending Register corresponding to the RTC _ALM
interrupt, since the flag may have been set while the alarm
time was being set
Write 1 to the Interrupt Set-Enable Register
corresponding to the RTC_ALM interrupt
Wait for alarm interrupt or the interrupt Active Bit
Register corresponding to the RTC_ALM interrupt to
become 1
Using the alarm function
In calendar count mode, an alarm can be generated by any one of year, month, date, day-of-week, hour, minute or second,
or any combination of those. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm
time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting.
In binary count mode, an alarm can be generated in any bit combination of 32 bits. Write 1 to the ENB bit of the alarm
enable register associated with the target bit of the alarm, and set the alarm time in the alarm register. For bits that are not
the target of the alarm, write 0 to the ENB bit of the alarm enable register.
When the counter and the alarm time match, the IELSRn.IR bit and Interrupt Set-Pending/Clear-Pending Register
associated with the RTC_ALM interrupt are set to 1. Alarm detection can be confirmed by reading the interrupt SetPending Register associated with the RTC_ALM interrupt, but an interrupt should be used in most cases. If 1 is set in the
Interrupt Set-Enable Register associated with the RTC_ALM interrupt, an alarm interrupt is generated in the event of the
alarm, enabling the alarm to be detected.
Writing 0 sets the IELSRn.IR bit associated with the RTC_ALM interrupt to 0. If interrupt is enabled, the Interrupt SetPending/Clear-Pending Register associated with the RTC_ALM interrupt is cleared automatically after exiting the
interrupt handler. Otherwise, write 1 to the Interrupt Clear-Pending Register associated with the RTC_ALM interrupt to
clear it.
When the counter and the alarm time match in a low power state, the MCU returns from the low power state. In Deep
Software Standby mode, the MCU returns from the Deep Software Standby mode even when the alarm interrupt request
is disabled.
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26.3.7
26. Realtime Clock (RTC)
Procedure for Disabling Alarm Interrupt
Figure 26.8 shows the procedure for disabling the enabled alarm interrupt request.
Enable the alarm interrupt
The RCR1.AIE bit register is set to 1
Disable the alarm interrupt request of
the NVIC
Write 0 to the Interrupt Clear-Enable Register
corresponding to the RTC_ALM interrupt
Disable the alarm interrupt request of
the RTC
Write 0 to the RCR1.AIE bit
No
AIE bit = 0
Wait for the RCR1.AIE bit to be cleared to 0
Yes
Clear the interrupt flag
Figure 26.8
26.3.8
Write 0 to the IELSRn.IR bit and write 1 to the
Interrupt Clear-Pending Register corresponding to
the RTC_ALM interrupt because the flag might have
been set before the RCR1.AIE bit becomes 0
Procedure for disabling alarm interrupt request
Time Error Adjustment Function
The time error adjustment function is used to correct errors, running fast or slow, in the time caused by variation in the
precision of oscillation by the sub-clock oscillator. Because 32,768 cycles of the sub-clock oscillator constitute 1 second
of operation when the sub-clock oscillator is selected, the clock runs fast if the sub-clock frequency is high and slow if
the sub-clock frequency is low.
The time error adjustment functions include:
Automatic adjustment
Adjustment by software.
Use the RCR2.AADJE bit to select automatic adjustment or adjustment by software.
26.3.8.1
Automatic adjustment
Enable automatic adjustment by setting the RCR2.AADJE bit to 1. Automatic adjustment is the addition or subtraction of
the value counted by the prescaler to or from the value in the RADJ register every time the adjustment period selected by
the RCR2.AADJP bit elapses.
(1)
Example 1: Sub-clock oscillator running at 32.769 kHz
(a)
Adjustment procedure
When the sub-clock oscillator is running at 32.769 kHz, 1 second elapses every 32,769 clock cycles. The RTC is meant
to run at 32,768 clock cycles, so the clock runs fast by 1 clock cycle every second. The time on the clock is fast by 60
clock cycles per minute, so adjustment can take the form of setting the clock back by 60 cycles every minute.
Register settings (when RCR2.CNTMD = 0):
RCR2.AADJP = 0 (adjustment every minute)
RADJ.PMADJ[1:0] = 10b (adjustment is performed by the subtraction from the prescaler)
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26. Realtime Clock (RTC)
RADJ.ADJ[5:0] = 60 (3Ch).
(2)
Example 2: Sub-clock oscillator running at 32.766 kHz
(a)
Adjustment procedure
When the sub-clock oscillator is running at 32.766 kHz, 1 second elapses every 32,766 clock cycles. The RTC is meant
to run at 32,768 clock cycles, so the clock runs slow by 2 clock cycles every second. The time on the clock is slow by 20
clock cycles every 10 seconds, so adjustment can take the form of setting the clock forward by 20 cycles every 10
seconds.
Register settings (when RCR2.CNTMD = 0):
RCR2.AADJP = 1 (adjustment every 10 seconds)
RADJ.PMADJ[1:0] = 01b (adjustment is performed by the addition to the prescaler)
RADJ.ADJ[5:0] = 20 (14h).
(3)
Example 3: Sub-clock oscillator running at 32.764 kHz
(a)
Adjustment procedure
At 32.764 kHz, 1 second elapses on 32,764 clock cycles. Because the RTC operates for 32,768 clock cycles as 1 second,
the clock is delayed for 4 clock cycles per second. In 8 seconds, the delay is 32 clock cycles, therefore correction can be
made by advancing the clock 32 clock cycles every 8 seconds.
Register settings when the RCR2.CNTMD bit is 1:
RCR2.AADJP = 1 (adjustment every 8 seconds)
RADJ.PMADJ[1:0] = 01b (adjustment is performed by the addition to the prescaler)
RADJ.ADJ[5:0] = 32 (20h).
26.3.8.2
Adjustment by software
Enable adjustment by software by setting the RCR2.AADJE bit to 0. Adjustment by software is the addition or
subtraction of the value counted by the prescaler to or from the value in the RADJ register on execution of a write
instruction to the RADJ register.
(1)
Example 1: Sub-clock oscillator running at 32.769 kHz
(a)
Adjustment procedure
When the sub-clock oscillator is running at 32.769 kHz, 1 second elapses every 32,769 clock cycles. The RTC is meant
to run at 32,768 clock cycles, so the clock runs fast by one clock cycle every second. The time on the clock is fast by one
clock cycle per second, so adjustment can take the form of setting the clock back by 1 cycle every second.
(b)
Register settings
RADJ.PMADJ[1:0] = 10b (adjustment is performed by subtraction from the prescaler)
RADJ.ADJ[5:0] = 1 (01h).
This is written to the RADJ register once per 1-second interrupt.
26.3.8.3
Procedure for changing the mode of adjustment
When changing the mode of adjustment, change the value of the AADJE bit in RCR2 after setting the
RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
To change adjustment by software to automatic adjustment:
1.
Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
2.
Set the RCR2.AADJE bit to 1 (automatic adjustment is enabled).
3.
Use the RCR2.AADJP bit to select the period of adjustment.
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4.
26. Realtime Clock (RTC)
In RADJ, set the PMADJ[1:0] bits for addition or subtraction and the ADJ[5:0] bits to the value for use in time
error adjustment.
To change automatic adjustment to adjustment by software:
1. Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
2. Set the RCR2.AADJE bit to 0 (adjustment by software is enabled).
3. Proceed with the adjustment by setting the RADJ.PMADJ[1:0] bits for addition or subtraction and the
RADJ.ADJ[5:0] bits to the value for use in time error adjustment at the target time. After that, the time is adjusted
every time a value is written to the RADJ register.
26.3.8.4
Procedure for stopping adjustment
Stop the adjustment by setting the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
26.3.8.5
Capturing the time
The RTC is capable of storing the month, date, hour, minute and second/binary counters 3 to 0 by detecting an edge of a
signal on a time capture event input pin.
A noise filter can also be used on a time capture event input pin. If the noise filter is enabled, the TCST bit is set to 1
when the input level on the pin matches three times.
The noise filter can be switched on or off for each of the time capture event input pins. Set VBTICTLR.VCHnIEN (n = 0
to 2) to 1 to enable the RTCICn input. Operation when the noise filter is off is shown in Figure 26.9 and operation when
the noise filter is on is shown in Figure 26.10.
Count source
RTCICn (n = 0 to 2)
Internal event-input signal
Time counters
Capture register
AAAA
0
BBBB
AAAA
TCST
Detection of the
rising edge
Figure 26.9
No capturing when
TCST = 1
Timing of a time capture operation with the filter off
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26. Realtime Clock (RTC)
Count source
RTCICn (n = 0 to 2)
Internal event-input signal
(1)
(2)
(1)
(2)
(1)
Since the level has only matched
twice, it is not conveyed to the
internal circuits.
(2)
(3)
Since the level has matched three
times, it is conveyed to the internal
circuits.
Internal event-detection signal
Time counters
Capture register
AAAA
BBBB
0
BBBB
TCST
Detection of the rising edge
Figure 26.10
26.4
Timing of a time capture operation with the filter on
Interrupt Sources
The RTC has three interrupt sources and are listed in Table 26.3.
Table 26.3
RTC interrupt sources
Name
Interrupt source
RTC_ALM
Alarm interrupt
RTC_PRD
Periodic interrupt
RTC_CUP
Carry interrupt
(1)
Alarm interrupt (RTC_ALM)
This interrupt is generated based on the result of comparison between the alarm registers and RTC counters. For details,
see section 26.3.6, Alarm Function.
Because there is a possibility that the interrupt flag might be set to 1 when the settings of the alarm registers match the
clock counters, wait for the alarm time settings to be confirmed and clear the IELSRn.IR bit and the interrupt SetPending Register associated with the RTC_ALM interrupt to 0 again after modifying values of the alarm registers. After
the interrupt flag for the alarm interrupt is set to 1 and the state is returned to mismatching of the alarm registers and
clock counters, the flag is not set again until there is another match or the values of the alarm registers are modified
again.
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26. Realtime Clock (RTC)
Sequence for setting the alarm
Alarm register settings
in progress
Wait until the alarm
time setting is
confirmed
Alarm registers
Clock counters
Match while settings are being made
Interrupt flag
(the IRLSRn.IR bit and the
Interrupt Set-Pending Register
flag corresponding to the
RTC_ALM interrupt *1)
Note 1.
Alarm interrupt
accepted
See section 14, Interrupt Controller Unit (ICU) for details on the associated interrupt vector number.
Figure 26.11
(2)
Flag clearing by
software
Timing diagram for the alarm interrupt (RTC_ALM)
Periodic interrupt (RTC_PRD)
This interrupt is generated at intervals of 2 seconds, 1 second, 1/2 second, 1/4 second, 1/8 second, 1/16 second, 1/32
second, 1/64 second, 1/128 second, or 1/256 second. The interrupt interval can be selected through the RCR1.PES[3:0]
bits.
(3)
Carry interrupt (RTC_CUP)
This interrupt is generated when a carry to the second counter/binary counter 0 occurred or a carry to the R64CNT
counter occurred during read access to the 64-Hz counter.
R64CNT
signal
64 Hz
Interrupt generated by the simultaneous
occurrence of the selected edge of the
64-Hz signal and register reading
1 Hz
An interrupt is generated by a
carry to the second counter/
binary counter 0
Interrupt
Detail
Rising edges of the R64CNT signals
are detected in the same way.
64-Hz signal in R64CNT
Detection of the selected edge of the 64-Hz
signal
Register reading by the CPU
Interrupt generated by the simultaneous occurrence of
the edge of the 64-Hz signal and reading of R64CNT
R64CNT
Interrupt flag
(the IELSRn.IR bit and Interrupt Set-Pending
Register corresponding to the RTC_CUP
interrupt)
Figure 26.12
26.5
Timing diagram for the carry interrupt (RTC_CUP)
Event Link Output
The RTC generates periodic event output (RTC_PRD) event signal for the Event Link Controller (ELC) that can be used
to initiate operations by other modules selected in advance.
The periodic event signal is output at the interval selected from 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2, 1, and 2
seconds by setting the RCR1.PES[3:0] bits.
The event generation period immediately after the event generation is selected is not guaranteed.
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Note:
26. Realtime Clock (RTC)
If event linking from the RTC is used, only set the ELC after setting the RTC, for example initialization and time
settings. Setting the RTC after the ELC can lead to output of unexpected event signals.
26.5.1
Interrupt Handling and Event Linking
The RTC has a bit to enable or disable periodic interrupts. An interrupt request signal is output for the CPU when an
interrupt source is generated while the associated enable bit is enabled.
In contrast, an event link output signal is sent to other modules as an event signal through the ELC when an interrupt
source is generated, regardless of the setting of the associated interrupt enable bit.
Note:
26.6
Although alarm and periodic interrupts can still be output during Software Standby mode or Deep Software
Standby mode, the periodic event signals for the ELC are not output.
Usage Notes
26.6.1
Register Writing during Counting
The following registers must not be written to during counting, that is, while the RCR2.START bit is 1:
RSECCNT/BCNT0
RMINCNT/BCNT1
RHRCNT/BCNT2
RDAYCNT
RWKCNT/BCNT3
RMONCNT
RYRCNT
RCR1.RTCOS
RCR2.RTCOE
RCR2.HR24
RFRL.
The counter must be stopped before writing to any of these registers.
26.6.2
Use of Periodic Interrupts
The procedure for using periodic interrupts is shown in Figure 26.13.
The generation and period of the periodic interrupt can be changed by setting the RCR1.PES[3:0] bits. However, because
the prescaler R64CNT and RSECCNT/BCNT0 are used to generate interrupts, the interrupt period is not guaranteed
immediately after setting the RCR1.PES[3:0] bits. In addition, any of the following operation can affect the interrupt
period:
Stopping/restarting or resetting counter operation
Reset by RTC software
30-second adjustment by changing the RCR2 value.
When the time error adjustment function is used, the interrupt generation period after adjustment is added or subtracted
based on the adjustment value.
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26. Realtime Clock (RTC)
Set the period and enable interrupt requests
Set the RCR1.PES[3:0] bits and
write 1 to the RCR1.PIE bit
The period is not guaranteed
The first interrupt is generated
Confirm generation of the first periodic interrupt*1
The set period elapses
Interrupts are generated
with the specified period
An interrupt is generated
Confirm generation of a periodic interrupt
Note 1. When an interrupt generation period changes while the periodic interrupt is used, an interrupt
might be generated at the completion of the setting. If the interrupt is generated immediately
after the setting, the period is not guaranteed for two interrupts including the current interrupt.
Figure 26.13
26.6.3
Using the periodic interrupt function
RTCOUT (1-Hz/64-Hz) Clock Output
Stopping/restarting or resetting counter operation, reset by RTC software, and the 30-second adjustment by changing the
RCR2 value affects the period of RTCOUT (1-Hz/64-Hz) output. When the time error adjustment function is used, the
period of RTCOUT (1-Hz/64-Hz) output after adjustment is added or subtracted based on the adjustment value.
26.6.4
Transitions to Low Power Modes after Setting Registers
A transition to a low power state (Software Standby mode, Deep Software Standby mode, or battery backup) during a
write to an RTC register might corrupt the value in the register. After setting the register, confirm that the setting is in
place before initiating a transition to a low power state.
26.6.5
Notes on Writing to and Reading from Registers
When reading a counter register such as the second counter after writing to the counter register, follow the
procedure in section 26.3.5, Reading 64-Hz Counter and Time
The value written to the count registers, alarm registers, year alarm enable register, bits RCR2.AADJE, AADJP, and
HR24, RCR4 register, or frequency register is reflected when four read operations are performed after writing
The values written to the RCR1.CIE, RCR1.RTCOS, and RCR2.RTCOE bits can be read immediately after writing
To read the value from the timer counter after return from a reset, Software Standby mode, Deep Software Standby
mode, or the battery backup state, wait for1/128 second while the clock is operating (RCR2.START bit is 1)
After a reset is generated, write to the RTC register after 6 cycles of the count source clock elapse.
26.6.6
Changing the Count Mode
When changing the count mode (calendar/binary), set the RCR2.START bit to 0, stop the counting operation, then restart
it from the initial setting. For details on the initial setting, see section 26.3.1, Outline of Initial Settings of Registers after
Power On.
26.6.7
Initialization Procedure when the Realtime Clock Is Not To Be Used
Registers in the RTC are not initialized by a reset. Depending on the initial state, the generation of an unintentional
interrupt request or operation of the counter might lead to increased power consumption.
For applications that do not require a realtime clock, initialize the registers by following the initialization procedure
shown in Figure 26.14.
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26. Realtime Clock (RTC)
Alternatively, when the sub-clock oscillator is not used as the system clock or realtime clock, the counter can be stopped
by writing 0 (subclock oscillator is selected) to the RCR4.RCKSEL bit and stopping the sub-clock oscillator. To stop the
sub-clock oscillator, write 1 to the SOSCCR.SOSTP bit.
For details on the setting of the SOSCCR.SOSTP bit, see section 9, Clock Generation Circuit.
Select the count source
Supply 6 clocks of the count source
RCR4.RCKSEL bit setting
Supply 6 clocks of the clock selected by the
RCR4.RCKSEL bit
Clear the START bit to 0
No
START = 0
Wait for the RCR2.START bit to become 0
Yes
Select count mode
Execute RTC software reset
No
RESET = 0
RCR2.CNTMD bit setting*1
Write 1 to the RCR2.RESET bit
Wait for the RCR2.RESET bit to become 0
Yes
Disable interrupt requests
Note 1.
Figure 26.14
26.6.8
Write 0 to the RCR1.AIE, CIE, and PIE bits.
This step is not required if the count mode is set concurrently with setting the START bit to 0.
Initialization procedure
When Switching Source Clock
When switching a clock source by changing SCKCR.CKSEL[2:0], the clock output from the selector stops for 4 cycles
of the switched clock. If the RTC periodical interrupt or RTC periodical event output was generated at this time, the
interrupt or event is invalid.
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27.
27. Watchdog Timer (WDT)
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down-counter and can be used to reset the MCU when the counter underflows
because the system has run out of control and become unable to refresh the WDT. In addition, the WDT can be used to
generate a non-maskable interrupt or an underflow interrupt. The refresh-permitted period can be set to refresh the
counter and to detect when the system runs out of control.
27.1
Overview
Table 27.1 lists the WDT specifications and Figure 27.1 shows a block diagram.
Table 27.1
WDT specifications
Parameter
Specifications
Count source
Peripheral clock (PCLKB)
Clock division ratio
Division by 4, 64, 128, 512, 2,048, or 8,192
Counter operation
Counting down using a 14-bit down-counter
Conditions for starting the counter Auto start mode: Counting automatically starts after a reset, or after an underflow or refresh error
occurs
Register start mode: Counting is started by a refresh by writing to the WDTRR register.
Conditions for stopping the
counter
Reset (the down-counter and other registers return to their initial values)
A counter underflows or a refresh error is generated.
Window function
Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods)
WDT reset sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Non-maskable interrupt/interrupt
sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Reading of the counter value
The down-counter value can be read by the WDTSR register
Event link function (output)
Down-counter underflow event output
Refresh error event output.
Output signal (internal signal)
Reset output
Interrupt request output
Sleep mode count stop control output.
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27. Watchdog Timer (WDT)
Interrupt request (WDT_NMIUNDF)
Interrupt Controller Unit (ICU)
WDT reset output
Clock
frequency
divider
Reset control circuit
PCLKB/4
PCLKB/64
PCLKB
PCLKB/128
WDT control circuit
PCLKB/512
14-bit down-counter
WDTRR
WDTCR
WDTSR
WDTCSTPR
Option Function Select Register 0
(OFS0)
WDTRCR
PCLKB/2048
PCLKB/8192
Count stop control output
in Sleep mode
Event signal output
Internal peripheral bus
Figure 27.1
27.2
WDTRR:
WDTCR:
WDTSR:
WDTRCR:
WDTCSTPR:
Clock control circuit
Event Link Controller (ELC)
WDT Refresh Register
WDT Control Register
WDT Status Register
WDT Reset Control Register
WDT Stop Control Register
WDT block diagram
Register Descriptions
27.2.1
WDT Refresh Register (WDTRR)
Address(es): WDT.WDTRR 4004 4200h
Value after reset:
Bit
b7 to b0
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
Description
The down-counter is refreshed by writing 00h and then writing FFh to this register
R/W
R/W
The WDTRR register refreshes the down-counter of the WDT.
The down-counter of the WDT is refreshed by writing 00h and then writing FFh to WDTRR (refresh operation) within
the refresh-permitted period.
After the down-counter is refreshed, it starts counting down from the value selected in the WDT Timeout Period Select
bits (OFS0.WDTTOPS[1:0]) in the Option Function Select Register 0 in auto start mode. In register start mode, counting
down starts from the value selected in the Timeout Period Select bits (WDTCR.TOPS[1:0]) in the WDT Control
Register.
When 00h is written, the read value is 00h. When a value other than 00h is written, the read value is FFh. For details on
the refresh operation, see section 27.3.3, Refresh Operation.
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27.2.2
27. Watchdog Timer (WDT)
WDT Control Register (WDTCR)
Address(es): WDT.WDTCR 4004 4202h
Value after reset:
b15
b14
—
—
0
0
b13
b12
b11
b10
RPSS[1:0]
—
—
RPES[1:0]
1
0
0
1
1
b9
b8
b7
b6
b5
b4
CKS[3:0]
1
1
1
1
1
b3
b2
b1
b0
—
—
TOPS[1:0]
0
0
1
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
TOPS[1:0]
Timeout Period Select
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b4
CKS[3:0]
Clock Division Ratio Select
b7
R/W
b9, b8
RPES[1:0]
Window End Position Select
b9 b8
R/W
b11, b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13, b12
RPSS[1:0]
Window Start Position Select
b13 b12
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: 1,024 cycles (03FFh)
1: 4,096 cycles (0FFFh)
0: 8,192 cycles (1FFFh)
1: 16,384 cycles (3FFFh).
b4
0 0 0 1: PCLKB/4
0 1 0 0: PCLKB/64
1 1 1 1: PCLKB/128
0 1 1 0: PCLKB/512
0 1 1 1: PCLKB/2048
1 0 0 0: PCLKB/8192.
Other settings are prohibited.
0
0
1
1
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (do not specify window end position).
0: 25%
1: 50%
0: 75%
1: 100% (do not specify window start position).
Some constraints apply to writes to the WDTCR register. For details, see section 27.3.2, Controlling Writes to the
WDTCR, WDTRCR, and WDTCSTPR Registers.
In auto start mode, the settings in the WDTCR register are disabled, and the settings in Option Function Select Register 0
(OFS0) are enabled. The settings for the WDTCR register can also be made for the OFS0 register. For details, see section
27.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
TOPS[1:0] bits (Timeout Period Select)
The TOPS[1:0] bits select the timeout period, the period until the down-counter underflows, from 1,024, 4,096, 8,192,
and 16,384 cycles, taking the divided clock specified in the CKS[3:0] bits as 1 cycle. After the down-counter is
refreshed, the combination of the CKS[3:0] and TOPS[1:0] bits determines the number of PCLKB cycles until the
counter underflows.
Table 27.2 lists the relationship between the CKS[3:0] and TOPS[1:0] bit settings, the timeout period, and the number of
PCLKB cycles.
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Table 27.2
27. Watchdog Timer (WDT)
Timeout period settings
CKS[3:0] bits
TOPS[1:0] bits
b7
b6
b5
b4
b1
b0
Clock division ratio
Timeout period
(number of cycles)
PCLKB clock cycles
0
0
0
1
0
0
PCLKB/4
1,024
4,096
0
1
4,096
16,384
1
0
8,192
32,768
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
16,384
65,536
1,024
65,536
0
1
4,096
262,144
1
0
8,192
524,288
1
1
16,384
1,048,576
0
0
1,024
131,072
0
1
4,096
524,288
1
0
8,192
1,048,576
1
1
0
0
0
PCLKB/64
PCLKB/128
16,384
2,097,152
1,024
524,288
1
4,096
2,097,152
1
0
8,192
4,194,304
1
1
16,384
8,388,608
0
0
1,024
2,097,152
0
1
4,096
8,388,608
1
0
8,192
16,777,216
1
1
16,384
33,554,432
0
0
1,024
8,388,608
0
1
4,096
33,554,432
1
0
8,192
67,108,864
1
1
16,384
134,217,728
PCLKB/512
PCLKB/2048
PCLKB/8192
CKS[3:0] bits (Clock Division Ratio Select)
The CKS[3:0] bits specify the division ratio of the clock used for the down-counter. The division ratio can be selected
from the peripheral clock (PCLKB) divided by 4, 64, 128, 512, 2048, and 8192. Combined with the TOPS[1:0] bit
setting, this allows the WDT to be configured to a count period between 4,096 and 134,217,728 cycles of the PCLKB
clock.
RPES[1:0] bits (Window End Position Select)
The RPES[1:0] bits specify the window end position that indicates the refresh-permitted period. 75%, 50%, 25%, or 0%
of the timeout period can be selected for the window end position. Set the window end position to a value less than the
value for the window start position (window start position > window end position). If the window end position is greater
than the window start position, only the window start position setting is enabled.
RPSS[1:0] bits (Window Start Position Select)
The RPSS[1:0] bits specify the window start position that indicates the refresh-permitted period. 100%, 75%, 50%, or
25% of the timeout period can be selected for the window start position. Set the window start position to a value greater
than the value for the window end position. If the window start position is set to a value less than or equal to the window
end position, the window end position is set to 0%.
Table 27.3 lists the counter values for the window start and end positions, and Figure 27.2 shows the refresh-permitted
period set in the RPSS[1:0], RPES[1:0], and TOPS[1:0] bits.
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Table 27.3
27. Watchdog Timer (WDT)
Relationship between the timeout period and window start and end counter values
Timeout period
TOPS[1:0] bits
Window start and end counter value
Cycles
Counter value
100%
75%
50%
25%
0
0
1024
03FFh
03FFh
02FFh
01FFh
00FFh
0
1
4096
0FFFh
0FFFh
0BFFh
07FFh
03FFh
1
0
8192
1FFFh
1FFFh
17FFh
0FFFh
07FFh
1
1
16384
3FFFh
3FFFh
2FFFh
1FFFh
0FFFh
RPES[1:0] bits
RPSS[1:0] bits
b13
b12
1
b8
1
1
1
0
0
1
0
0
1
1
0
1
0
25
0
1
0
0
1
1
0
1
0
25
0
1
0
0
75
1
1
0
1
0
0
1
0
0
0
0
1
0
End
(%)
b9
1
1
Window
Start
(%)
0
Counting
started
100
25
50
75
75
50
75
50
50
25
25
50
75
Note: If window end setting window start setting, the window end setting
is set to 0%.
Figure 27.2
27.2.3
Underflow
0
100%
75%
50%
0%
25%
Refresh-permitted period
Refresh-prohibited period
RPSS[1:0] and RPES[1:0] bit settings and refresh-permitted period
WDT Status Register (WDTSR)
Address(es): WDT.WDTSR 4004 4204h
b15
b14
b13
b12
b11
b10
b9
b8
REFEF UNDFF
Value after reset:
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CNTVAL[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
CNTVAL[13:0]
Down-Counter Value
Value counted by the down-counter
R
b14
UNDFF
Underflow Flag
0: No underflow occurred
1: Underflow occurred.
R(/W)
*1
b15
REFEF
Refresh Error Flag
0: No refresh error occurred
1: Refresh error occurred.
R(/W)
*1
Note 1.
Only 0 can be written to clear the flag.
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27. Watchdog Timer (WDT)
CNTVAL[13:0] bits (Down-Counter Value)
Read the CNTVAL[13:0] bits to confirm the value of the down-counter. The read value might differ from the actual
count by 1.
UNDFF flag (Underflow Flag)
Read the UNDFF flag to confirm whether an underflow occurred in the down-counter. A value of 1 indicates that the
down-counter underflowed. Write 0 to the flag to set the value to 0. Writing 1 has no effect.
Clearing of the UNDFF flag takes (N+1) PCLKB cycles. In addition, clearing of the flag is ignored for (N+1) PCLKB
cycles after an underflow. N is specified in the WDTCR.CKS[3:0] bits as follows:
When WDTCR.CKS[3:0] = 0001b, N = 4
When WDTCR.CKS[3:0] = 0100b, N = 64
When WDTCR.CKS[3:0] = 1111b, N = 128
When WDTCR.CKS[3:0] = 0110b, N = 512
When WDTCR.CKS[3:0] = 0111b, N = 2048
When WDTCR.CKS[3:0] = 1000b, N = 8192
REFEF flag (Refresh Error Flag)
Read the REFEF flag to confirm whether a refresh error occurred, indicating that a refresh operation was performed
during a prohibited period. A value of 1 indicates that a refresh error occurred. Write 0 to the flag to set the value to 0.
Writing 1 has no effect.
Clearing of the REFEF flag takes (N+1) PCLKB cycles. In addition, clearing of the flag is ignored for (N+1) PCLKB
cycles after a refresh error. N is specified in the WDTCR.CKS[3:0] bits as follows:
When WDTCR.CKS[3:0] = 0001b, N = 4
When WDTCR.CKS[3:0] = 0100b, N = 64
When WDTCR.CKS[3:0] = 1111b, N = 128
When WDTCR.CKS[3:0] = 0110b, N = 512
When WDTCR.CKS[3:0] = 0111b, N = 2048
When WDTCR.CKS[3:0] = 1000b, N = 8192.
27.2.4
WDT Reset Control Register (WDTRCR)
Address(es): WDT.WDTRCR 4004 4206h
b7
b6
b5
b4
b3
b2
b1
b0
RSTIR
QS
—
—
—
—
—
—
—
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
b7
RSTIRQS
Reserved
These bits are read as 0. The write value should be 0.
R/W
Reset Interrupt Request Select
0: Non-maskable interrupt request or interrupt request output
is enabled
1: Reset output is enabled.
R/W
Some constraints apply to writes to the WDTRCR register. For details, see section 27.3.2, Controlling Writes to the
WDTCR, WDTRCR, and WDTCSTPR Registers.
In auto start mode, the WDTRCR register settings are disabled, and the settings in Option Function Select Register 0
(OFS0) are enabled. The settings for the WDTCR register can also be made for the OFS0 register. For details, see section
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27. Watchdog Timer (WDT)
27.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
27.2.5
WDT Count Stop Control Register (WDTCSTPR)
Address(es): WDT.WDTCSTPR 4004 4208h
b7
b6
b5
b4
b3
b2
b1
b0
SLCST
P
—
—
—
—
—
—
—
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
SLCSTP
Sleep-Mode Count Stop Control
0: Count stop is disabled
1: Count is stopped when transition to Sleep mode.
R/W
The WDTCSTPR register controls whether to stop the WDT counter in a low power mode. Some restrictions apply to
writes to the WDTCSTPR register. For details, see section 27.3.2, Controlling Writes to the WDTCR, WDTRCR, and
WDTCSTPR Registers.
In auto start mode, the WDTCSTPR register settings are disabled, and the settings in Option Function Select register 0
(OFS0) are enabled. The settings for the WDTCSTPR register can also be made for the OFS0 register. For details, see
section 27.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
SLCSTP bit (Sleep-Mode Count Stop Control)
The SLCSTP bit selects whether to stop counting when transition to Sleep mode.
27.2.6
Option Function Select Register 0 (OFS0)
For information on the OFS0 register, see section 27.3.7, Association between Option Function Select Register 0 (OFS0)
and WDT Registers.
27.3
Operation
27.3.1
Count Operation in Each Start Mode
The WDT has two start modes:
Auto start mode, in which counting automatically starts after a release from the reset state
Register start mode, in which counting is started with a refresh by writing to the register.
In auto start mode, counting automatically starts after release from the reset state in accordance with the settings in
Option Function Select Register 0 (OFS0) in the flash.
In register start mode, counting starts with a refresh by writing to the register after the respective registers are set after a
release from the reset state.
Select auto start mode or register start mode by setting the WDT Start Mode Select bit (OFS0.WDTSTRT) in the OFS0
register. When the auto start mode is selected, the settings in the WDT Control Register (WDTCR), WDT Reset Control
Register (WDTRCR), and WDT Count Stop Control Register (WDTCSTPR) are disabled, and the settings in the OFS0
register are enabled. When the register start mode is selected, the OFS0 register settings are disabled, and the settings in
the WDT Control Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT Count Stop Control
Register (WDTCSTPR) are enabled.
27.3.1.1
Register start mode
When the WDT Start Mode Select bit (OFS0.WDTSTRT) is 1, register start mode is selected and the WDT Control
Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT Count Stop Control Register (WDTCSTPR)
are enabled.
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27. Watchdog Timer (WDT)
After the reset state is released, set the following to Sleep mode in the WDTCSTPR register:
Clock division ratio
Window start and end positions
Timeout period in the WDTCR register
Reset output or interrupt request output in the WDTRCR register
Counter stop control during transitions to Sleep mode in the WDTCSTPR register.
Refresh the down-counter to start counting down from the value set in the Timeout Period Select bits
(WDTCR.TOPS[1:0]).
Thereafter, as long as the counter is refreshed in the refresh-permitted period, the value in the counter is reset each time
the counter is refreshed and down-counting continues. The WDT does not output the reset signal as long as counting
continues. However, if the down-counter underflows because the down-counter cannot be refreshed due to a program
runaway, or if a refresh error occurs because the counter was refreshed outside the refresh-permitted period, the WDT
outputs a reset signal or a non-maskable interrupt request/interrupt request (WDT_NMIUNDF). Reset output or interrupt
request output can be selected in the WDT Reset Interrupt Request Select bit (WDTRCR.RSTIRQS). Non-maskable
interrupt request or interrupt request can be selected in the WDT Underflow/Refresh Error Interrupt Enable bit
(NMIER.WDTEN).
Figure 27.3 shows an example of operation under the following conditions:
Register start mode (OFS0.WDTSTRT = 1)
Reset output is enabled (WDTRCR.RSTIRQS = 1)
The window start position is 75% (WDTCR.RPSS[1:0] = 10b)
The window end position is 25% (WDTCR.RPES[1:0] = 10b).
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27. Watchdog Timer (WDT)
Counter value
100%
Refreshprohibited
period
75%
Refreshpermitted
period
50%
25%
Refreshprohibited
period
0%
RES pin
Control
register
(WDTCR)
(1) Initial value
(2) Set value
Refresh
the counter
(active-high)
(2)
(1)
Writing to the
register is valid
(1)
Writing to the
register is invalid *1
(2)
(1)
Writing to Writing to the
the register register is invalid *1
is valid
(2)
Writing to the
register is valid
H
L
Counting starts
Counting starts
Underflow
Refresh error
flag
(active-high)
H
L
Underflow flag
(active-high)
H
L
Interrupt request
(WDT_NMIUNDF)
(active-high)
L
Reset output
from WDT
(active-high)
H
L
Counting starts
Refresh error
Refresh error
Status flag
cleared
Status flag
cleared
Note 1. See section 27.3.2, Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers.
Figure 27.3
Operation example in register start mode
27.3.1.2
Auto start mode
When the WDT Start Mode Select bit (OFS0.WDTSTRT) in the Option Function Select Register 0 (OFS0) is 0, auto
start mode is selected. The WDT Control Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT
Count Stop Control Register (WDTCSTPR) are disabled while the settings in the OFS0 register are enabled.
Within the reset state, the following values in the Option Function Select register 0 (OFS0) are set in the WDT registers:
Clock division ratio
Window start and end positions
Timeout period
Reset output or interrupt request
Counter stop control on transition to Sleep mode.
When the reset state is released, the down-counter automatically starts counting down from the value set in the WDT
Timeout Period Select bits (OFS0.WDTTOPS[1:0]).
Thereafter, as long as the counter is refreshed in the refresh-permitted period, the value in the counter is reset each time
the counter is refreshed and down-counting continues. The WDT does not output the reset signal as long as the counting
continues. However, if the down-counter underflows because refreshing of the down-counter is not possible due to a
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27. Watchdog Timer (WDT)
runaway program or if a refresh error occurs due to refreshing outside the refresh-permitted period, the WDT asserts the
reset signal or non-maskable interrupt request/interrupt request (WDT_NMIUNDF).
After the reset signal or non-maskable interrupt request/interrupt request is generated, the counter reloads the timeout
period after counting for 1 cycle. The value of the timeout period is set in the down-counter and counting restarts.
Reset output or interrupt request output can be selected in the WDT Reset Interrupt Request Select bit
(OFS0.WDTRSTIRQS). Non-maskable interrupt request or interrupt request can be selected in the WDT
Underflow/Refresh Error Interrupt Enable bit (NMIER.WDTEN).
Figure 27.4 shows an example of operation (non-maskable interrupt) under the following conditions:
Auto start mode (OFS0.WDTSTRT = 0)
Non-maskable interrupt request output is enabled (OFS0.WDTRSTIRQS = 0)
The window start position is 75% (WDTCR.RPSS[1:0] = 10b)
The window end position is 25% (WDTCR.RPES[1:0] = 10b).
Counter value
100
%
Refreshprohibited
period
75%
50%
Refreshpermitted
period
25%
Refreshprohibited
period
0%
RES pin
Refresh
the counter
(active-high)
H
L
Counting starts
Counting starts
Underflow
Refresh error flag
(active-high)
H
Underflow flag
(active-high)
H
Interrupt request
(WDT_NMIUNDF)
(active-high)
H
L
Reset output
from WDT
(active-high)
L
Figure 27.4
27.3.2
Counting starts
Refresh error
Counting starts
Refresh error
Status flag
cleared
L
L
Status flag
cleared
Operation example in auto start mode
Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers
Writing to the WDT Control Register (WDTCR), WDT Reset Control Register (WDTRCR), or WDT Count Stop
Control Register (WDTCSTPR) is possible once between the release from the reset state and the first refresh operation.
After a refresh (counting starts) or a write to WDTCR, WDTRCR or WDTCSTPR, the protection signal in the WDT
becomes 1 to protect WDTCR, WDTRCR and WDTCSTPR against subsequent write attempts. This protection is
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27. Watchdog Timer (WDT)
released by a reset source of the WDT. With other reset sources, the protection is not released.
Figure 27.5 shows control waveforms produced in response to writing to the WDTCR.
RES pin
Peripheral clock (PCLKB)
Data written to WDTCR
register
xxxxh
00F3h
WDTCR register write
signal (internal signal)
WDTCR register
Writing disabled
33F3h (initial value)
Register
protection signal
(internal signal)
Writing is possible
Figure 27.5
27.3.3
3300h
00F3h
00F3h
33F3h (initial value)
WDTCR register is protected
(writing-disabled period)
Control waveforms produced in response to writes to the WDTCR register
Refresh Operation
The down-counter is refreshed by writing the values 00h and FFh to the WDT Refresh Register (WDTRR). If a value
other than FFh is written after 00h, the down-counter is not refreshed. After an invalid value is written, correct refreshing
resumes by writing 00h and FFh to the WDTRR register.
When a register other than WDTRR is accessed or WDTRR is read between writing 00h and writing FFh to WDTRR,
correct refreshing is performed.
Writing to refresh the counter must be performed within the refresh-permitted period and whether this is done is
determined by writing FFh. For this reason, correct refreshing is performed even when 00h is written outside the refreshpermitted period.
[Example write sequences that are valid when refreshing the counter]
00h → FFh
00h ((n-1)th time) → 00h (nth time) → FFh
00h → access to another register or read from WDTRR → FFh.
[Example write sequences that are invalid when refreshing the counter]
23h (a value other than 00h) → FFh
00h → 54h (a value other than FFh)
00h→ AAh (00h and a value other than FFh) → FFh.
After FFh is written to the WDT Refresh Register (WDTRR), refreshing the down-counter requires up to 4 cycles of the
signal for counting. To meet this requirement, complete writing FFh to WDTRR 4 count cycles before the down-counter
underflows.
Figure 27.6 shows the WDT refresh-operation waveforms when the clock division ratio = PCLKB/64.
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27. Watchdog Timer (WDT)
Peripheral clock
(PCLKB)
Data written to
WDTRR register
00h
54h
00h
FFh
WDTRR register
write signal
(internal signal)
WDTRR register
Valid
FFh
00h
00h
FFh
Invalid
Refresh
synchronization
signal
Refresh signal
(after synchronization
with count cycle)
Counter value
FFh
Refresh request
(n+1)h
(n)h
(n)h
(n-1)h
(n-1)h 0FFFh
Refreshing
Figure 27.6
27.3.4
WDT refresh operation waveforms when WDTCR.CKS[3:0] = 0100b and WDTCR.TOPS[1:0] = 01b
Reset Output
When the Reset Interrupt Request Select bit (WDTRCR.RSTIRQS) is set to 1 in register start mode, or when the WDT
Reset Interrupt Request Select bit (OFS0.WDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 1 in
auto start mode, a reset signal is output for 1 cycle count when an underflow in the down-counter or a refresh error
occurs.
In register start mode, the down-counter is initialized (all bits set to 0) and stopped in that state after output of a reset
signal. After the reset state is released and the program is restarted, the counter is set up and counting down starts again
with a refresh. In auto start mode, counting down starts automatically after the reset state is released.
27.3.5
Interrupt Sources
When the Reset Interrupt Request Select bit (WDTRCR.RSTIRQS) is set to 0 in register start mode or when the WDT
Reset Interrupt Request Select bit (OFS0.WDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 0 in
auto start mode, an interrupt signal (WDT_NMIUNDF) is generated when an underflow in the counter or a refresh error
occurs. This interrupt can be used as a non-maskable interrupt or an interrupt. For details, see section 14, Interrupt
Controller Unit (ICU).
Table 27.4
WDT interrupt sources
Name
Interrupt source
DTC activation
DMAC activation
WDT_NMIUNDF
Down-counter underflow
Refresh error.
Not possible
Not possible
27.3.6
Reading the Down-Counter Value
The WDT stores the counter value in the down-counter value bits (WDTSR.CNTVAL[13:0]) in the WDT Status
Register. Check these bits to obtain the counter value.
Figure 27.7 shows the processing for reading the WDT down-counter value when the clock division ratio = PCLKB/64.
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27. Watchdog Timer (WDT)
Peripheral clock
(PCLKB)
Refreshing
Counter value
(n+1)h
Bits WDTSR.CNTVAL
[13:0]
(n+1)h
(n)h
(n-1)h
(n)h
(n-1)h
(n-1)h
0FFFh
(n-1)h
0FFFh
WDTSR.CNTVAL
[13:0] read signal
(internal signal)
WDTSR.CNTVAL
[13:0] read data
Figure 27.7
27.3.7
xxxxh
(n+1)h
(n)h
(n)h
0FFFh
Processing for reading WDT down-counter value when WDTCR.CKS[3:0] = 0100b and
WDTCR.TOPS[1:0] = 01b
Association between Option Function Select Register 0 (OFS0) and WDT
Registers
Table 27.5 lists the association between the Option Function Select register 0 (OFS0) used in auto start mode, and the
registers used in register start mode. Do not change the OFS0 register settings during WDT operation. For details on the
Option Function Select register 0 (OFS0), see section 7, Option Function Select Register 0 (OFS0).
Table 27.5
Association between Option Function Select register 0 (OFS0) and the WDT registers
OFS0 register
(enabled in auto start mode)
OFS0.WDTSTRT = 0
WDT registers
(enabled in register start mode)
OFS0.WDTSTRT = 1
Control target
Function
Down-counter
Timeout period select
OFS0.WDTTOPS[1:0]
WDTCR.TOPS[1:0]
Clock division ratio select
OFS0.WDTCKS[3:0]
WDTCR.CKS[3:0]
Window start position select
OFS0.WDTRPSS[1:0]
WDTCR.RPSS[1:0]
Window end position select
OFS0.WDTRPES[1:0]
WDTCR.RPES[1:0]
Reset output or interrupt
request output
Reset output or interrupt request
output select
OFS0.WDTRSTIRQS
WDTRCR.RSTIRQS
Count stop
Sleep-mode count stop control
OFS0.WDTSTPCTL
WDTCSTPR.SLCSTP
27.4
Link Operation by ELC
The WDT is capable of a link operation for the previously specified module when interrupt request signal is used as an
event signal by the ELC. The event signal is output by the counter underflow or refresh error.
An event signal is output regardless of the setting in the WDTRCR.RSTIRQS bit in register start mode or the
OFS0.WDTRSTIRQS bit in auto start mode. An event signal can also be output when the next interrupt source is
generated while the Refresh Error Flag (WDTSR.REFEF) or Underflow Flag (WDTSR.UNDFF) is 1. For details, see
section 19, Event Link Controller (ELC).
27.5
27.5.1
Usage Notes
ICU Event Link Setting Register n (IELSRn) Setting
Setting 47h to the ICU Event Link Setting Register n (IELSRn.IELS[8:0] bits) is prohibited when enabling the WDT
reset assertion (OFS0.WDTRSTIRQS = 1 or WDTRCR.RSTIRQS = 1) or when enabling the event link operation (47h is
set to ELSRm.ELS[8:0]).
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28. Independent Watchdog Timer (IWDT)
28.
Independent Watchdog Timer (IWDT)
28.1
Overview
The Independent Watchdog Timer (IWDT) is a 14-bit down counter that must be serviced periodically to prevent counter
underflow. The IWDT can be used to reset the MCU or to generate a non-maskable interrupt or an underflow interrupt.
Because the timer operates using an independent, dedicated clock source, it is particularly useful in returning the MCU to
a known state as a failsafe mechanism when the system runs out of control. The IWDT can be triggered automatically by
a reset, underflow, refresh error, or a refresh of the count value in the registers.
The functions of the IWDT are different from those of the WDT in the following ways:
The divided IWDT-dedicated clock (IWDTCLK) is used as the count source (not affected by PCLKB)
IWDT does not support the register start mode
When transitioning to a low power mode (excluding Deep Software Standby mode), the OFS0.IWDTSTPCTL bit
can be used to select whether to stop the counter or not.
Table 28.1 lists the IWDT specifications and Figure 28.1 shows a block diagram.
Table 28.1
IWDT specifications
Parameter
Count
source*1
Specifications
IWDT-dedicated clock (IWDTCLK)
Clock division ratio
Division by 1, 16, 32, 64, 128, or 256
Counter operation
Counting down using a 14-bit down-counter
Condition for starting the counter
Counting automatically starts after a reset
Conditions for stopping the
counter
Reset (the down-counter and other registers return to their initial values)
A counter underflows or a refresh error is generated. Counting restarts automatically.
Window function
Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods)
IWDT reset sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Non-maskable interrupt/interrupt
sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Reading of the counter value
The down-counter value can be read by the IWDTSR register
Event link function (output)
Down-counter underflow event output
Refresh error event output.
Output signal (internal signal)
Reset output
Interrupt request output
Sleep-mode count stop control output.
Auto start mode
Configurable to the following triggers:
Clock frequency division ratio after a reset (OFS0.IWDTCKS[3:0] bits)
Timeout period of the IWDT (OFS0.IWDTTOPS[1:0] bits)
Window start position in the IWDT (OFS0.IWDTRPSS[1:0] bits)
Window end position in the IWDT (OFS0.IWDTRPES[1:0] bits)
Reset output or interrupt request output (OFS0.IWDTRSTIRQS bit)
Down-count stop function at transition to Sleep mode, Software Standby mode, or Snooze mode
(OFS0.IWDTSTPCTL bit).
Note 1.
This must satisfy the frequency of the peripheral module clock (PCLKB) 4 × (the frequency of the count clock source after
division).
To use the IWDT, you must supply the IWDT-dedicated clock (IWDTCLK). The bus interface and registers operate with
PCLKB, and the 14-bit counter and control circuits operate with IWDTCLK.
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28. Independent Watchdog Timer (IWDT)
Interrupt request (IWDT_NMIUNDF)
Interrupt Controller Unit (ICU)
IWDT reset output
Reset control circuit
Clock
frequency
divider
IWDTCLK
IWDTCLK/16
IWDTCLK/32
IWDTCLK/64
IWDTCLK/128
IWDTCLK/256
IWDT control circuit
IWDTSR
Option Function Select Register 0
(OFS0)
14-bit counter
Count stop control output
in Sleep, Snooze, or Software Standby mode
IWDTRR
IWDTCLK
Clock control circuit
Event signal output
Event Link Controller (ELC)
IWDTRR:
IWDTSR:
Internal peripheral bus
Figure 28.1
28.2
IWDT Refresh Register
IWDT Status Register
IWDT block diagram
Register Descriptions
28.2.1
IWDT Refresh Register (IWDTRR)
Address(es): IWDT.IWDTRR 4004 4400h
Value after reset:
Bit
b7 to b0
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
Description
The down-counter is refreshed by writing 00h and then writing FFh to this register
R/W
R/W
The IWDTRR register refreshes the down-counter of the IWDT. The down-counter of the IWDT is refreshed by writing
00h and then writing FFh to IWDTRR (refresh operation) within the refresh-permitted period. After the down-counter is
refreshed, it starts counting down from the value selected in the IWDT Timeout Period Select bits
(OFS0.IWDTTOPS[1:0]) in Option Function Select Register 0 (OFS0).
When 00h is written, the read value is 00h. When a value other than 00h is written, the read value is FFh. For details on
the refresh operation, see section 28.3.2, Refresh Operation.
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28.2.2
28. Independent Watchdog Timer (IWDT)
IWDT Status Register (IWDTSR)
Address(es): IWDT.IWDTSR 4004 4404h
b15
b14
b13
b12
b11
b10
b9
b8
REFEF UNDFF
Value after reset:
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CNTVAL[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
CNTVAL[13:0]
Counter Value
Value counted by the down-counter
R
b14
UNDFF
Underflow Flag
0: No underflow occurred
1: Underflow occurred.
R/(W)*1
b15
REFEF
Refresh Error Flag
0: No refresh error occurred
1: Refresh error occurred.
R/(W)*1
Note 1.
Only 0 can be written to clear the flag.
CNTVAL[13:0] bits (Counter Value)
Read the CNTVAL[13:0] bits to confirm the value of the down-counter. The read value might differ from the actual
count by 1.
UNDFF flag (Underflow Flag)
Read the UNDFF flag to confirm whether an underflow occurred in the down-counter. A value of 1 indicates that the
down-counter underflowed. Write 0 to the flag to set the value to 0. Writing 1 has no effect.
Clearing of the UNDFF flag takes (N+2) IWDTCLK cycles and 2 PCLKB cycles. In addition, clearing of the flag is
ignored for (N+2) IWDTCLK cycles after an underflow. N is specified in the IWDTCKS[3:0] bits as follows:
When IWDTCKS[3:0] = 0000b, N = 1
When IWDTCKS[3:0] = 0010b, N = 16
When IWDTCKS[3:0] = 0011b, N = 32
When IWDTCKS[3:0] = 0100b, N = 64
When IWDTCKS[3:0] = 1111b, N = 128
When IWDTCKS[3:0] = 0101b, N = 256.
REFEF flag (Refresh Error Flag)
Read the REFEF flag to confirm whether a refresh error occurred. This indicates that a refresh operation was performed
during a prohibited period. A value of 1 indicates that a refresh error occurred. Write 0 to the flag to set the value to 0.
Writing 1 has no effect.
Clearing of the REFEF flag takes (N+2) IWDTCLK cycles and 2 PCLKB cycles. In addition, clearing of the flag is
ignored for (N+2) IWDTCLK cycles after a refresh error. N is specified in the IWDTCKS[3:0] bits as follows:
When IWDTCKS[3:0] = 0000b, N = 1
When IWDTCKS[3:0] = 0010b, N = 16
When IWDTCKS[3:0] = 0011b, N = 32
When IWDTCKS[3:0] = 0100b, N = 64
When IWDTCKS[3:0] = 1111b, N = 128
When IWDTCKS[3:0] = 0101b, N = 256.
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28.2.3
28. Independent Watchdog Timer (IWDT)
Option Function Select Register 0 (OFS0)
For information on Option Function Select Register 0 (OFS0), see section 7.2.1, Option Function Select Register 0
(OFS0).
IWDTTOPS[1:0] bits (IWDT Timeout Period Select)
The IWDTTOPS[1:0] bits select the timeout period, that is, the period until the down-counter underflows, from 128, 512,
1024, or 2048 cycles, taking the divided clock specified in the IWDTCKS[3:0] bits as 1 cycle.
After the down-counter is refreshed, the combination of the IWDTCKS[3:0] and IWDTTOPS[1:0] bits determines the
number of IWDTCLK cycles until the counter underflows.
Table 28.2 lists the relationship between the IWDTCKS[3:0] and IWDTTOPS[1:0] bit settings, the timeout period, and
the number of IWDTCLK cycles.
Table 28.2
Timeout period settings
IWDTCKS[3:0] bits
IWDTTOPS[1:0] bits
b7
b6
b5
b4
b1
b0
Clock division ratio
Timeout period
(number of cycles)
IWDTCLK cycles
0
0
0
0
0
0
IWDTCLK
128
128
0
1
512
512
1
0
1,024
1,024
1
1
2,048
2,048
0
0
0
1
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
1
0
0
128
2,048
0
1
IWDTCLK/16
512
8,192
1
0
1,024
16,384
1
1
2,048
32,768
0
0
128
4,096
0
1
512
16,384
1
0
1,024
32,768
1
1
2,048
65,536
0
0
128
8,192
0
1
512
32,768
1
0
1,024
65,536
1
1
2,048
131,072
IWDTCLK/32
IWDTCLK/64
0
0
128
16,384
0
1
IWDTCLK/128
512
65,536
1
0
1,024
131,072
1
1
2,048
262,144
0
0
128
32,768
0
1
512
131,072
1
0
1,024
262,144
1
1
2,048
524,288
IWDTCLK/256
IWDTCKS[3:0] bits (IWDT-Dedicated Clock Frequency Division Ratio Select)
The IWDTCKS[3:0] bits specify the division ratio of the clock used for the down-counter. The division ratio can be
selected from the IWDT-dedicated clock (IWDTCLK) divided by 1, 16, 32, 64, 128, and 256. Combined with the
IWDTTOPS[1:0] bit setting, the IWDT can be configured to a count period between 128 and 524,288 IWDTCLK cycles.
IWDTRPES[1:0] bits (IWDT Window End Position Select)
The IWDTRPES[1:0] bits specify the window end position that indicates the refresh-permitted period. 75%, 50%, 25%,
or 0% of the timeout period can be selected for the window end position. Set the window end position to a value less than
the window start position (window start position > window end position). If the window end position is greater than the
window start position, only the window start position setting is enabled.
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28. Independent Watchdog Timer (IWDT)
IWDTRPSS[1:0] bits (IWDT Window Start Position Select)
The IWDTRPSS[1:0] bits specify the window start position that indicates the refresh-permitted period. 100%, 75%,
50%, or 25% of the timeout period can be selected for the window start position. Set the window start position to a value
greater than the window end position. If the window start position is less than or equal to the window end position, the
window end position is set to 0%.
Table 28.3 lists the counter values for the window start and end positions, and Figure 28.2 shows the refresh-permitted
period set in the IWDTRPSS[1:0], IWDTRPES[1:0], and IWDTTOPS[1:0] bits.
Table 28.3
Relationship between the timeout period and window start and end counter values
IWDTTOPS[1:0] bits
Timeout period
Window start and end counter value
b1
b0
Cycles
Counter value
100%
75%
50%
25%
0
0
128
007Fh
007Fh
005Fh
003Fh
001Fh
0
1
512
01FFh
01FFh
017Fh
00FFh
007Fh
1
0
1,024
03FFh
03FFh
02FFh
01FFh
00FFh
1
1
2,048
07FFh
07FFh
05FFh
03FFh
01FFh
IWDTRPSS[1:0] bits
b13
1
1
0
0
b12
IWDTRPES[1:0] bits
b9
b8
1
1
1
0
1
0
Window
Start
(%)
End
(%)
Counting
started
Underflow
0
1
0
0
1
0
0
75
1
1
0
1
0
0
1
0
0
1
1
0
1
0
25
0
1
0
0
1
1
0
1
0
25
0
1
0
0
100
75
25
50
25
50
75
50
50
75
25
50
75
100%
75%
50%
25%
0%
Refresh-permitted period
Refresh-prohibited period
Note:
If window end setting window start setting, the window end setting is set to 0%.
Figure 28.2
IWDTRPSS[1:0] and IWDTRPES[1:0] bit settings and refresh-permitted period
IWDTRSTIRQS bit (IWDT Reset Interrupt Request Select)
The IWDTRSTIRQS bit specifies the behavior when an underflow or a refresh error occurs. Setting 1 selects reset
output. Setting 0 selects non-maskable interrupt or interrupt.
IWDTSTPCTL bit (IWDT Stop Control)
The IWDTSTPCTL bit selects whether to stop counting on transition to Sleep, Snooze, or Software Standby mode.
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28.3
28.3.1
28. Independent Watchdog Timer (IWDT)
Operation
Auto Start Mode
When the IWDT Start Mode Select bit (OFS0.IWDTSTRT) is 0, auto start mode is selected. Otherwise, the IWDT is
disabled.
Within the reset state, the following values in Option Function Select Register 0 (OFS0) are set in the IWDT registers:
Clock division ratio
Window start and end positions
Timeout period
Reset output or interrupt request
Counter stop control on transition to low power modes.
When the reset state is released, the down-counter automatically starts counting down from the value set in the IWDT
Timeout Period Select bits (OFS0.IWDTTOPS[1:0]).
After that, as long as the program continues normal operation and the counter is refreshed within the refresh-permitted
period, the value in the counter is reset each time the counter is refreshed and down-counting continues. The IWDT does
not output the reset signal as long as this procedure continues. However, if the counter underflows because the program
crashes, or because a refresh error occurs when an attempt is made to refresh outside the refresh-permitted period, the
IWDT asserts the reset signal or a non-maskable interrupt request/interrupt request (IWDT_NMIUNDF).
After the reset signal or non-maskable interrupt request/interrupt request is generated, the counter reloads the timeout
period after counting for 1 cycle, and restarts the count. Reset output or interrupt request output can be selected in the
IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS). Non-maskable interrupt request or interrupt request
can be selected in the IWDT Underflow/Refresh Error Interrupt Enable bit (NMIER.IWDTEN).
Figure 28.3 shows an example of operation under the following conditions:
Auto start mode (OFS0.IWDTSTRT = 0)
Non-maskable interrupt request output is enabled (OFS0.IWDTRSTIRQS = 0)
The window start position is 75% (OFS0.IWDTRPSS[1:0] = 10b)
The window end position is 25% (OFS0.IWDTRPES[1:0] = 10b).
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28. Independent Watchdog Timer (IWDT)
Counter value
100%
75%
50%
25%
0%
Refreshprohibited period
Refreshpermitted period
Refreshprohibited period
RES pin
Refresh
the counter
(active-high)
H
L
Counting starts
Counting starts
Underflow
Refresh error flag
(active-high)
H
Underflow flag
(active-high)
H
L
Interrupt request
(IWDT_NMIUNDF)
(active-high)
H
Counting starts
Refresh error
Counting starts
Refresh error
Status flag
cleared
L
Status flag
cleared
L
Reset output
from IWDT
(active-high) L
Figure 28.3
28.3.2
Operation example in auto start mode
Refresh Operation
The down-counter is refreshed by writing the values 00h and FFh to the IWDT Refresh Register (IWDTRR). If a value
other than FFh is written after 00h, the down-counter is not refreshed. If an invalid value is written, correct refreshing
resumes on a write of 00h and FFh to the IWDTRR register.
When writing is done in the order of 00h (first time) → 00h (second time), and if FFh is written after that, the writing
order 00h → FFh is satisfied. Writing 00h ((n-1)th time) → 00h (nth time) → FFh is valid, and the refresh is performed
correctly. When the first value written before 00h is not 00h, correct refreshing is performed as long as the operation
contains the write sequence of 00h → FFh.
Additionally, correct refreshing is performed when a register other than IWDTRR is accessed or IWDTRR is read
between writing 00h and writing FFh to IWDTRR. Writes to refresh the counter must be made within the refreshpermitted period, and this is determined by the FFh write. For this reason, correct refreshing is performed even when 00h
is written outside the refresh-permitted period.
[Example write sequences that are valid for refreshing the counter]
00h → FFh
00h ((n-1)th time) → 00h (nth time) → FFh
00h → access to another register or read from IWDTRR → FFh.
[Example write sequences that are invalid for refreshing the counter]
23h (a value other than 00h) → FFh
00h → 54h (a value other than FFh)
00h → AAh (00h and a value other than FFh) → FFh.
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28. Independent Watchdog Timer (IWDT)
After FFh is written to the IWDT Refresh Register (IWDTRR), refreshing the down-counter requires up to 4 cycles of
the signal for counting (the IWDT-Dedicated Clock Frequency Division Ratio Select bits (OFS0.IWDTCKS[3:0])
determine how many cycles of the IWDT-dedicated clock (IWDTCLK) make up 1 counting cycle. To meet this
requirement, complete writing FFh to IWDTRR 4 count cycles before the end of the refresh-permitted period or a
counter underflow. The value of the counter can be checked in the counter bits (IWDTSR.CNTVAL[13:0]).
[Example refreshing timings]
When the window start position is set to 1FFFh, even if 00h is written to IWDTRR before 1FFFh is reached (at
2002h, for example), refreshing occurs if FFh is written to IWDTRR after the value of the
IWDTSR.CNTVAL[13:0] bits reaches 1FFFh
When the window end position is set to 1FFFh, refreshing occurs if 2003h (4 count cycles before 1FFFh) or a
greater value is read from the IWDTSR.CNTVAL[13:0] bits immediately after a write of 00h → FFh to IWDTRR
When the refresh-permitted period continues until count 0000h, refreshing can be performed immediately before an
underflow. In this case, if 0003h (4 count cycles before an underflow) or a greater value is read from the
IWDTSR.CNTVAL[13:0] bits immediately after writing 00h → FFh to IWDTRR, no underflow occurs and
refreshing is performed.
Figure 28.4 shows the IWDT refresh-operation waveforms when PCLKB > IWDTCLK and the clock division ratio is
IWDTCLK.
Peripheral clock
(PCLKB)
IWDT-dedicated
clock (IWDTCLK)
Data written to
IWDTRR register
00h
54h
00h
FFh
IWDTRR register write
signal (internal signal)
IWDTRR register
Valid
FFh
00h
FFh
FFh
Invalid
Refresh
synchronization signal
Refresh signal
(after synchronization
with IWDTCLK)
Counter value
00h
Refresh request
(n+2)h
(n+1)h
(n)h
(n-1)h
(n-2)h
(n-3)h
3FFFh
Refreshing
Figure 28.4
28.3.3
IWDT refresh operation waveforms when OFS0.IWDTCKS[3:0] = 0000b, OFS0.IWDTTOPS[1:0] =
11b
Status Flags
The refresh error (IWDTSR.REFEF) and underflow (IWDTSR.UNDFF) flags retain the source of the reset signal output
from the IWDT or the source of the interrupt request from the IWDT. After a release from the reset state or interrupt
request generation, read the IWDTSR.REFEF and UNDFF flags to check for the reset or interrupt source. For each flag,
writing 0 clears the bit and writing 1 has no effect.
Leaving the status flags unchanged does not affect operation. If the flags are not cleared on the next reset or interrupt
request from the IWDT, the earlier reset or interrupt source is cleared and the new reset or interrupt source is written.
After 0 is written to each flag, up to 3 IWDTCLK cycles and 2 PCLKB cycles are required before the value is reflected.
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28.3.4
28. Independent Watchdog Timer (IWDT)
Reset Output
When the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS) in Option Function Select Register 0
(OFS0) is set to 1, a reset signal is output when an underflow in the down-counter or a refresh error occurs. Counting
down starts automatically after the reset output.
28.3.5
Interrupt Sources
When the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS) in Option Function Select Register 0
(OFS0) is set to 0, an interrupt signal (IWDT_NMIUNDF) is generated when an underflow in the counter or a refresh
error occurs. This interrupt can be used as a non-maskable interrupt or an interrupt. For details, see section 14, Interrupt
Controller Unit (ICU).
Table 28.4
IWDT interrupt source
Name
Interrupt source
DTC activation
DMAC activation
IWDT_NMIUNDF
Down-counter underflow
Refresh error.
Not possible
Not possible
28.3.6
Reading the Down-Counter Value
Because the counter is a IWDT-dedicated clock (IWDTCLK), the counter value cannot be read directly. The IWDT
synchronizes the counter value with the peripheral clock (PCLKB) and stores it in the down-counter value bits
(IWDTSR.CNTVAL[13:0]) in the IWDT Status register. Check these bits to obtain the counter value indirectly.
Reading the counter value requires multiple PCLKB clock cycles (up to 4 clock cycles), and the read counter value might
differ from the actual counter value by a value of one count.
Figure 28.5 shows the processing for reading the IWDT counter value when PCLKB > IWDTCLK and the clock division
ratio is IWDTCLK.
Peripheral clock
(PCLKB)
IWDT-dedicated
clock (IWDTCLK)
Refreshing
(after synchronization with IWDTCLK)
Counter value
IWDTSR.CNTVAL
[13:0] bits
(n+1)h
(n+1)h
(n)h
(n-1)h
(n)h
(n-2)h
(n-1)h
3FFFh
(n-3)h
(n-2)h
(n-3)h
3FFEh
3FFFh
IWDTSR.CNTVAL
[13:0] read signal
(internal signal)
IWDTSR.CNTVAL
[13:0] read data
Figure 28.5
28.4
xxxxh
(n+1)h
(n)h
(n-2)h
3FFFh
Processing for reading IWDT counter value when OFS0.IWDTCKS[3:0] = 0000b and
OFS0.IWDTTOPS[1:0] = 11b
Output to the Event Link Controller (ELC)
IWDT is capable of link operation for a specified module when the interrupt request signal is used as an event signal by
the ELC. The event signal is output by the counter underflow or refresh error.
An event signal is output regardless of the setting in the OFS0.WDTRSTIRQS bit. An event signal can also be output
when the next interrupt source is generated while the Refresh Error Flag (IWDTSR.REFEF) or Underflow Flag
(IWDTSR.UNDFF) is 1. For details, see section 19, Event Link Controller (ELC).
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28.5
28.5.1
28. Independent Watchdog Timer (IWDT)
Usage Notes
Refresh Operations
While configuring the refresh time, consider variations in the range of errors because of the accuracy of PCLKB and
IWDTCLK. Set values that ensure that refreshing is possible.
28.5.2
Constraints on the Clock Division Ratio Setting
Satisfy the following required frequency of the peripheral module clock (PCLKB):
PCLKB 4 (the frequency of the count clock source after division).
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29. Ethernet MAC Controller (ETHERC)
29.
Ethernet MAC Controller (ETHERC)
29.1
Overview
The MCU provides a one-channel Ethernet Controller (ETHERC) compliant with the Ethernet or IEEE802.3 Media
Access Control (MAC) layer protocol. Each ETHERC channel has one channel of the MAC layer interface. Connecting
the MCU to the physical layer LSI (PHY-LSI) allows the transmission and reception of frames compliant with the
Ethernet/IEEE802.3 standard. The ETHERC is connected to the Ethernet DMA Controller (EDMAC), so data can be
transferred without using the CPU.
Table 29.1 lists the ETHERC specifications, Figure 29.1 shows the configuration, and Table 29.2 lists the I/O pins.
Figure 29.2 and Figure 29.3 show examples of connections of the MCU to an external PHY-LSI.
Table 29.1
ETHERC specifications
Parameter
Specifications
Number of channels
One channel
Protocol
Flow control compliant with IEEE802.3x
Data transmission/reception
Frames compliant with the Ethernet/IEEE802.3 standard can be transmitted and received
Bit rate
Supports 10 Mbps and 100 Mbps
Operation modes
Supports full-duplex and half-duplex modes
Interfaces
Media Independent Interface (MII), Reduced Media Independent Interface (RMII), compliant with
the IEEE802.3u standard
Functions
Magic PacketTM detection
Wake-on-LAN (WOL) signal output
Hardware filtering of received multicast packets with a MAC address.
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29. Ethernet MAC Controller (ETHERC)
External bus controller
SRAM
ETHER bus
EDMAC arbiter
PCLKA*1
ETHER_EINT0 (EDMAC0)
EDMAC channel 0
(EDMAC0)
MDIO
Receive
circuit
ETHERC
channel 0
(ETHERC0)
Transmit
circuit
Internal peripheral bus
MII interface
MII/RMII channel 0
Note 1.
Figure 29.1
When using the ETHERC, set the clock to ICLK = PCLKA.
12.5 MHz ≤ PCLKA ≤ 120 MHz.
ETHERC configuration
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Table 29.2
29. Ethernet MAC Controller (ETHERC)
ETHERC I/O pins
Operating
mode
Pin name
I/O
Description
MII
ET0_TX_CLK*1
Input
Transmit clock
Timing reference signal for outputting the ET0_TX_EN, ET0_ETXD3 to
ET0_ETXD0, and ET0_TX_ER signals.
ET0_RX_CLK*1
Input
Receive clock
Timing reference signal for inputting the ET0_RX_DV, ET0_ERXD3 to
ET0_ERXD0, and ET0_RX_ER signals.
ET0_TX_EN*1
Output
Transmit data valid
This signal indicates that valid transmit data was output on pins ET0_ETXD3 to
ET0_ETXD0.
ET0_ETXD3 to ET0_ETXD0*1
Output
4-bit transmit data
ET0_TX_ER*1
Output
Transmit error
This signal notifies the PHY-LSI that an error occurred during transmission.
ET0_RX_DV*1
Input
Receive data valid
This signal indicates that valid receive data is on pins ET0_ERXD3 to
ET0_ERXD0.
ET0_ERXD3 to ET0_ERXD0*1
Input
4-bit receive data
ET0_RX_ER*1
Input
Receive error
This signal indicates that there is an error in a frame that is being transferred
from the PHY-LSI to the ETHERC.
ET0_CRS*1
Input
Carrier sense
ET0_COL*1
Input
Collision detection signal
ET0_MDC*1
Output
Management data clock
Reference clock signal for transfer of information on the ET0_MDIO pin.
ET0_MDIO*1
I/O
Management data Input/Output
Bidirectional data signal for exchanging management data with the PHY-LSI.
ET0_LINKSTA
Input
Link status input from the PHY-LSI
ET0_EXOUT
Output
General output pin
ET0_WOL
Output
Wake-on-LAN. This signal indicates that a Magic Packet was received.
REF50CK0*2
Input
Reference clock
Timing reference signal for the RMII0_TXD_EN, RMII0_TXD1 to RMII0_TXD0,
RMII0_CRS_DV, RMII0_RXD1 to RMII0_RXD0, and RMII0_RX_ER pins.
RMII0_TXD_EN*2
Output
Transmit data valid
This signal indicates that valid transmit data was output on the RMII0_TXD1 and
RMII0_TXD0 pins.
RMII0_TXD1 to RMII0_TXD0*2
Output
2-bit transmit data
RMII0_CRS_DV*2
Input
Carrier sense/receive data valid
This signal indicates that valid receive data is on the RMII0_RXD1 and
RMII0_RXD0 pins.
RMII0_RXD1 to RMII0_RXD0*2
Input
2-bit receive data
RMII0_RX_ER*2
Input
Receive error
This signal indicates that there is an error in a frame that is being transferred
from the PHY-LSI to the ETHERC. See the note in section 29.5.2, Input to
RMII0_RX_ER Pin While RMII Is Selected.
ET0_MDC*2
Output
Management data clock
Reference clock signal for transfer of information on the ET0_MDIO pin.
ET0_MDIO*2
I/O
Management data Input/Output
Bidirectional data signal for exchanging management data with the PHY-LSI.
ET0_LINKSTA
Input
Link status input from the PHY-LSI
ET0_EXOUT
Output
General output pin
ET0_WOL
Output
Wake-on-LAN. This signal indicates that a Magic Packet was received.
RMII
Note 1.
Note 2.
MII signal compliant with IEEE802.3u.
RMII signal compliant with IEEE802.3u.
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29. Ethernet MAC Controller (ETHERC)
MII (Media Independent Interface)
MCU
ET0_TX_ER
ET0_ETXD3
ET0_ETXD2
ET0_ETXD1
ET0_ETXD0
ET0_TX_EN
ET0_TX_CLK
ET0_MDC
ET0_MDIO
ET0_ERXD3
ET0_ERXD2
ET0_ERXD1
ET0_ERXD0
ET0_RX_CLK
ET0_CRS
ET0_COL
ET0_RX_DV
ET0_RX_ER
Figure 29.2
PHY-LSI
TX_ER
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
MDC
MDIO
RXD3
RXD2
RXD1
RXD0
RX_CLK
CRS
COL
RX_DV
RX_ER
Example of connection with PHY-LSI for MII
RMII (Reduced Media Independent Interface)
MCU
RMII0_TXD1
RMII0_TXD0
RMII0_TXD_EN
ET0_MDC
ET0_MDIO
RMII0_RXD1
RMII0_RXD0
REF50CK0
RMII0_CRS_DV
RMII0_RX_ER
Figure 29.3
PHY-LSI
TXD1
TXD0
TXD_EN
MDC
MDIO
RXD1
RXD0
RX_CLK
CRS_DV
RX_ER
Example of connection with PHY-LSI for RMII
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29.2
29. Ethernet MAC Controller (ETHERC)
Register Descriptions
29.2.1
ETHERC Mode Register (ECMR)
Address(es): ETHERC0.ECMR 4006 4100h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
TPC
ZPF
PFR
RXF
TXF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
PRCEF
—
—
MPDE
—
—
RE
TE
—
ILB
RTM
DM
PRM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
PRM
Promiscuous Mode
0: Disable promiscuous mode
1: Enable promiscuous mode.
R/W
b1
DM
Duplex Mode
0: Half-duplex mode
1: Full-duplex mode.
R/W
b2
RTM
Bit Rate
0: 10 Mbps
1: 100 Mbps.
R/W
b3
ILB
Internal Loopback Mode
R/W
0: Perform normal data transmission or reception
1: Loop data back in the ETHERC when full-duplex mode is selected.
b4
—
Reserved
The read value is 0. The write value should be 0.
R/W
b5
TE
Transmission Enable
0: Disable transmit function
1: Enable transmit function.
R/W
b6
RE
Reception Enable
0: Disable receive function
1: Enable receive function.
R/W
b8, b7
—
Reserved
The read value is 0. The write value should be 0.
R/W
b9
MPDE
Magic Packet Detection
Enable
0: Disable Magic Packet detection
1: Enable Magic Packet detection.
R/W
b11, b10
—
Reserved
The read value is 0. The write value should be 0.
R/W
b12
PRCEF
CRC Error Frame Receive
Mode
0: Notify EDMAC of a CRC error
1: Do not notify EDMAC of a CRC error.
R/W
b15 to b13 —
Reserved
The read value is 0. The write value should be 0.
R/W
b16
TXF
Transmit Flow Control
Operating Mode
0: Disable automatic PAUSE frame transmission
(PAUSE frame is not automatically transmitted)
1: Enable automatic PAUSE frame transmission
(PAUSE frame is automatically transmitted as required).
R/W
b17
RXF
Receive Flow Control
Operating Mode
0: Disable PAUSE frame detection
1: Enable PAUSE frame detection.
R/W
b18
PFR
PAUSE Frame Receive Mode
0: Do not transfer PAUSE frame to the EDMAC
1: Transfer PAUSE frame to the EDMAC.
R/W
b19
ZPF
0 Time PAUSE Frame Enable
0: Do not use PAUSE frames containing a pause_time parameter of 0 R/W
1: Use PAUSE frames containing a pause_time parameter of 0.
b20
TPC
PAUSE Frame Transmit
0: Transmit PAUSE frame even during a PAUSE period
1: Do not transmit PAUSE frame during a PAUSE period.
R/W
Reserved
The read value is 0. The write value should be 0.
R/W
b31 to b21 —
The ECMR register controls ETHERC operation. Except for the TE and RE bits, set the bits in this register during
initialization after a reset. When rewriting this register outside the initialization process, set the EDMAC0.EDMR.SWR
bit to 1 to reset the EDMAC and ETHERC, then set this register again.
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29. Ethernet MAC Controller (ETHERC)
PRM bit (Promiscuous Mode)
When the PRM bit is set to 1, the ETHERC operates in promiscuous mode, where all Ethernet frames are received. In
promiscuous mode, the ETHERC receives all valid frames regardless of whether the address matches the destination or
the broadcast address, and regardless of the multicast bit setting.
RTM bit (Bit Rate)
The RTM bit sets the bit rate when the RMII is selected.
ILB bit (Internal Loopback Mode)
When the ILB bit is set to 1, transmit frames can be looped back in the MCU. Set the DM bit to 1 (full-duplex mode) to
perform a loopback test.
TE bit (Transmission Enable)
When the TE bit is set to 1, the ETHERC transmit function is enabled. When the TE bit is set to 0, the transmit function
is disabled after the frame being processed is completely transmitted.
RE bit (Reception Enable)
When the RE bit is set to 1, the ETHERC receive function is enabled. When the RE bit is set to 0, the receive function is
disabled after the frame being processed is completely received.
PRCEF bit (CRC Error Frame Receive Mode)
When the PRCEF bit is set to 1, the EDMAC is not notified that a CRC error has occurred even when the error is
detected in a receive frame. Accordingly, the EDMAC0.EESR.CERF flag and RFS0 bit in receive descriptor 0 (RD0) do
not set to 1.
ZPF bit (0 Time PAUSE Frame Enable)
When the ZPF bit is 1, a PAUSE frame with a pause_time parameter of 0 is transmitted when a PAUSE frame transmit
request is canceled before the PAUSE time of the previously transmitted PAUSE frame has elapsed. After the PAUSE
frame containing the pause_time parameter of 0 is received, the ETHERC is ready for transmission.
When the ZPF bit is 0, even if the PAUSE frame transmit request from the receive FIFO is canceled, the next PAUSE
frame is not transmitted until the PAUSE time of the previously transmitted PAUSE frame has elapsed. When a PAUSE
frame containing a pause_time parameter of 0 is received, it is discarded.
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29.2.2
29. Ethernet MAC Controller (ETHERC)
Receive Frame Maximum Length Register (RFLR)
Address(es): ETHERC0.RFLR 4006 4108h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
0
0
0
0
0
RFL[11:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b11 to b0
RFL[11:0]
Receive Frame Maximum
Length
The set value becomes the maximum frame length. The minimum
value that can be set is 1,518 bytes, and the maximum value that
can be set is 2,048 bytes. Values less than 1,518 bytes are
regarded as 1,518 bytes, and values larger than 2,048 bytes are
regarded as 2,048 bytes.
R/W
Reserved
The read value is 0. The write value should be 0.
R/W
b31 to b12 —
The RFLR register specifies the maximum frame length that can be received by the MCU. Set the length in bytes. Do not
rewrite this register while the ECMR.RE bit is 1 (receive function enabled).
RFL[11:0] bits (Receive Frame Maximum Length)
The RFL[11:0] bits set the frame length to be checked. The frame length is the number of bytes in a field, extending from
the destination address to the frame check sequence [FCS] of the received frame. When this length exceeds the
RFL[11:0] bit value, the EDMAC is notified of a frame-too-long error, and the excess data is discarded.
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29.2.3
29. Ethernet MAC Controller (ETHERC)
ETHERC Status Register (ECSR)
Address(es): ETHERC0.ECSR 4006 4110h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
BFR
PSRTO
—
0
0
0
0
0
0
0
0
0
0
0
0
0
LCHNG MPD
0
ICD
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ICD
False Carrier Detect Flag
0: PHY-LSI has not detected a false carrier on the line
1: PHY-LSI detected a false carrier on the line.
R/W *1
b1
MPD
Magic Packet Detect Flag
0: Magic Packet not detected
1: Magic Packet detected.
R/W *1
b2
LCHNG
Link Signal Change Flag
0: Change in the ET0_LINKSTA signal not detected
1: Change in the ET0_LINKSTA signal detected (high to low, or low
to high).
R/W *1
b3
—
Reserved
The read value is 0. The write value should be 0.
R/W
b4
PSRTO
PAUSE Frame Retransmit
Over Flag
0: PAUSE frame retransmit count has not reached the upper limit
1: PAUSE frame retransmit count reached the upper limit.
R/W *1
b5
BFR
Continuous Broadcast Frame
Reception Flag
0: Continuous reception of broadcast frames not detected
1: Continuous reception of broadcast frames detected.
R/W *1
b31 to b6
—
Reserved
The read value is 0. The write value should be 0.
R/W
Note 1.
Write 1 to clear the flag.
The ECSR register indicates the status of the ETHERC. When any flag in the ECSR register is set to 1 while the
associated bit in the ECSIPR register is 1 (interrupt enabled), the EDMAC0.EESR.ECI flag is set to 1.
ICD flag (False Carrier Detect Flag)
The ICD flag indicates that the PHY-LSI has detected a false carrier on the line. The flag is set to 1 when a receive error
signal shown in Figure 29.11 is received from the PHY-LSI. The information might not be correct when signals input
from the PHY-LSI change faster than software recognizes the change. Check the timing of the PHY-LSI.
LCHNG flag (Link Signal Change Flag)
The LCHNG flag indicates that the ET0_LINKSTA signal input from the PHY-LSI has changed from high to low, or
from low to high. Check the PSR.LMON flag for the current link status. See section 29.5.1, Preventing the LCHNG Flag
from Erroneously Setting to 1 for more information.
PSRTO flag (PAUSE Frame Retransmit Over Flag)
The PSRTO flag indicates that the number of retransmissions reached the value set in the TPAUSER register when
retransmitting a PAUSE frame while the automatic PAUSE frame transmission is enabled.
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29.2.4
29. Ethernet MAC Controller (ETHERC)
ETHERC Interrupt Enable Register (ECSIPR)
Address(es): ETHERC0.ECSIPR 4006 4118h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
BFSIP PSRTO
R
IP
0
0
—
0
LCHNG MPDIP ICDIP
IP
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ICDIP
False Carrier Detect Interrupt Enable
0: Disable interrupt notification
1: Enable interrupt notification.
R/W
b1
MPDIP
Magic Packet Detect Interrupt Enable
0: Disable interrupt notification
1: Enable interrupt notification.
R/W
b2
LCHNGIP
LINK Signal Change Interrupt Enable
0: Disable interrupt notification
1: Enable interrupt notification.
R/W
b3
—
Reserved
The read value is 0. The write value should be 0.
R/W
b4
PSRTOIP
PAUSE Frame Retransmit Over
Interrupt Enable
0: Disable interrupt notification
1: Enable interrupt notification.
R/W
b5
BFSIPR
Continuous Broadcast Frame Reception
Interrupt Enable
0: Disable interrupt notification
1: Enable interrupt notification.
R/W
b31 to b6
—
Reserved
The read value is 0. The write value should be 0.
R/W
The ECSIPR register selects whether to notify the EDMAC of the status indicated in the ECSR register. Each bit is
associated with the flag with the same bit number in the ECSR register.
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29.2.5
29. Ethernet MAC Controller (ETHERC)
PHY Interface Register (PIR)
Address(es): ETHERC0.PIR 4006 4120h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
MDI
MDO
MMD
MDC
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MDC
MII/RMII Management
Data Clock
This value is output from the ET0_MDC pin to supply the management data
clock to the MII or RMII
R/W
b1
MMD
MII/RMII Management
Mode
0: Read
1: Write.
R/W
b2
MDO
MII/RMII Management
Data-Out
This value is output from the ET0_MDIO pin when the MMD bit is 1 (write),
and not when MMD is 0 (read)
R/W
b3
MDI
MII/RMII Management
Data-In
This bit indicates the level of the ET0_MDIO pin. The write value should be
0.
R
b31 to b4
—
Reserved
The read value is 0. The write value should be 0.
R/W
The PIR register accesses registers in the PHY-LSI through the MII or RMII. The management clock and management
data are controlled through software. See section 29.3.4, Accessing the MII and RMII Registers for details on accessing
the MII and RMII registers.
29.2.6
PHY Status Register (PSR)
Address(es): ETHERC0.PSR 4006 4128h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LMON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
Bit
Symbol
Bit name
Description
R/W
b0
LMON
ET0_LINKSTA Pin
Status Flag
The link status can be read by connecting the link signal output from the
PHY-LSI to the ET0_LINKSTA pin. For details on the polarity, see the
specifications of the connected PHY-LSI.
R
b31 to b1
—
Reserved
The read value is 0
R
The PSR register monitors the interface signals from PHY-LSI.
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29.2.7
29. Ethernet MAC Controller (ETHERC)
Random Number Generation Counter Upper Limit Setting Register (RDMLR)
Address(es): ETHERC0.RDMLR 4006 4140h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
RMD[19:16]
RMD[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b19 to b0
RMD[19:0]
Random Number Generation
Counter
00000h: Normal operation
00001h to FFFFFh: Setting prohibited.
R/W
b31 to b20
—
Reserved
The read value is 0. The write value should be 0.
R/W
The RDMLR register specifies the maximum value for the counter used in the random number generator. Do not rewrite
this register while the ECMR.TE bit is 1 (transmit function enabled) or while the ECMR.RE bit is 1 (receive function
enabled).
29.2.8
Interpacket Gap Register (IPGR)
Address(es): ETHERC0.IPGR 4006 4150h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
IPG[4:0]
1
0
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
IPG[4:0]
Interpacket Gap
00h: 16 bit times
01h: 20 bit times
:
:
14h: 96 bit times (initial value)
:
:
1Fh: 140 bit times.
R/W
b31 to b5
—
Reserved
The read value is 0. The write value should be 0.
R/W
The IPGR register specifies the Interpacket Gap (IPG) value. Do not rewrite this register while the ECMR.TE bit is 1
(transmit function enabled) or while the ECMR.RE bit is 1 (receive function enabled). See section 29.3.6, Adjusting
Transmission Efficiency by Changing the IPG for details on the IPG.
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29.2.9
29. Ethernet MAC Controller (ETHERC)
Automatic PAUSE Frame Register (APR)
Address(es): ETHERC0.APR 4006 4154h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
AP[15:0]
0
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
AP[15:0]
Automatic PAUSE
Time Setting
These bits set the value of the pause_time parameter for PAUSE frames that
are automatically transmitted. Transmission is not performed until a period
equal to the set value multiplied by 512 bit times has elapsed.
R/W
Reserved
The read value is 0. The write value should be 0.
R/W
b31 to b16 —
The APR register specifies the PAUSE time for PAUSE frames that are automatically transmitted. The value set in the
APR register is used for the pause_time parameter of the PAUSE frame. Do not rewrite this register while the ECMR.TE
bit is 1 (transmit function enabled) or while the ECMR.RE bit is 1 (receive function enabled).
29.2.10
Manual PAUSE Frame Register (MPR)
Address(es): ETHERC0.MPR 4006 4158h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
MP[15:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b15 to b0
MP[15:0]
Manual PAUSE Time
Setting
These bits set the value of the pause_time parameter for PAUSE frames
that are manually transmitted. Transmission is not performed until the set
value multiplied by 512 bit times has elapsed.
The read value is undefined.
W
Reserved
The read value is 0. The write value should be 0.
W
b31 to b16 —
The MPR register specifies the PAUSE time for PAUSE frames that are manually transmitted. The value set in the MPR
register is used for the pause_time parameter of the PAUSE frame. When a value is set to this register, a PAUSE frame is
transmitted. Rewrite this register while the ECMR.TE bit is 1 (transmit function enabled).
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29.2.11
29. Ethernet MAC Controller (ETHERC)
Received PAUSE Frame Counter (RFCF)
Address(es): ETHERC0.RFCF 4006 4160h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
RPAUSE[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
RPAUSE[7:0]
Received PAUSE Frame Count
Number of received PAUSE frames
R
b31 to b8
—
Reserved
The read value is 0
R
The RFCF register is a counter that indicates the number of received PAUSE frames. The counter is reset after this
register is read.
29.2.12
PAUSE Frame Retransmit Count Setting Register (TPAUSER)
Address(es): ETHERC0.TPAUSER 4006 4164h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
TPAUSE[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
TPAUSE[15:0]
Automatic PAUSE Frame Retransmit
Setting
0000h: Number of retransmissions is unlimited
0001h: Maximum number of retransmissions is 1
:
:
FFFFh: Maximum number of retransmissions is
65,535.
R/W
b31 to b16
—
Reserved
The read value is 0. The write value should be 0.
R/W
The TPAUSER register selects the maximum number of times a PAUSE frame is automatically transmitted. Do not
rewrite this register while the ECMR.TE bit is 1 (transmit function enabled).
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29.2.13
29. Ethernet MAC Controller (ETHERC)
PAUSE Frame Retransmit Counter (TPAUSECR)
Address(es): ETHERC0.TPAUSECR 4006 4168h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
TXP[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
TXP[7:0]
PAUSE Frame
Retransmit Count
Number of times a PAUSE frame was retransmitted
R
b31 to b8
—
Reserved
The read value is 0
R
The TPAUSECR register is a counter that indicates the number of times a PAUSE frame was automatically
retransmitted. The counter is reset after this register is read.
29.2.14
Broadcast Frame Receive Count Setting Register (BCFRR)
Address(es): ETHERC0.BCFRR 4006 416Ch
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
BCF[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
BCF[15:0]
Broadcast Frame Continuous
Receive Count Setting
0000h: Number of receptions is unlimited
0001h: Receive 1 frame
:
:
FFFFh: Receive 65,535 frames.
R/W
b31 to b16
—
Reserved
The read value is 0. The write value should be 0.
R/W
The BCFRR register specifies the number of times that broadcast frames can be received continuously. When the number
of received frames exceeds the BCF[15:0] bit value, the excess broadcast frames are discarded. Do not rewrite this
register while the EMCR.RE bit is 1 (receive function enabled).
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Page 756 of 1734
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29.2.15
29. Ethernet MAC Controller (ETHERC)
MAC Address Upper Bit Register (MAHR)
Address(es): ETHERC0.MAHR 4006 41C0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MAHR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
MAHR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MAHR[31:0]
MAC Address Upper Bit
See the following
R/W
The MAHR register specifies the upper 32 bits ([47:16]) of the 48-bit MAC address. For example, if the MAC address is
01-23-45-67-89-AB, set the register to 0123 4567h.
Set the MAHR register during initialization after a reset. Do not rewrite this register while the ECMR.TE bit is 1
(transmit function enabled) or while the ECMR.RE bit is 1 (receive function enabled). When rewriting this register, set
the EDMAC0.EDMR.SWR bit to 1 to reset the EDMAC and ETHERC, then set this register again.
29.2.16
MAC Address Lower Bit Register (MALR)
Address(es): ETHERC0.MALR 4006 41C8h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
—
—
These bits set the lower 16 bits of the MAC address
R/W
b31 to b16
—
Reserved
The read value is 0. The write value should be 0.
R/W
The MALR register specifies the lower 16 bits of the 48-bit MAC address. For example, if the MAC address is 01-23-4567-89-AB, set the register to 0000 89ABh.
Set the MALR register during initialization after a reset. Do not rewrite this register while the ECMR.TE bit is 1
(transmit function enabled) or while the ECMR.RE bit is 1 (receive function enabled). When rewriting this register, set
the EDMAC0.EDMR.SWR bit to 1 to reset the EDMAC and ETHERC, then set this register again.
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29.2.17
29. Ethernet MAC Controller (ETHERC)
Transmit Retry Over Counter Register (TROCR)
Address(es): ETHERC0.TROCR 4006 41D0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
TROCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
TROCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
TROCR[31:0]
Transmit Retry Over Counter
See the following
R/W
The TROCR register is a counter that indicates the number of frames that failed to be retransmitted. The register value is
incremented by 1 when a frame fails to be retransmitted 15 times. The counter stops when the register value becomes
FFFF FFFFh. Writing any value to the TROCR register clears the counter value to 0.
29.2.18
Late Collision Detect Counter Register (CDCR)
Address(es): ETHERC0.CDCR 4006 41D4h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
CDCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
CDCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
CDCR[31:0]
Late Collision Detect Counter
See the following
R/W
The CDCR register is a counter that indicates the number of late collisions that are detected after transmission starts.
When the register value becomes FFFF FFFFh, the counter stops. Writing any value to the CDCR register clears the
counter value to 0.
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29.2.19
29. Ethernet MAC Controller (ETHERC)
Lost Carrier Counter Register (LCCR)
Address(es): ETHERC0.LCCR 4006 41D8h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
LCCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
LCCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
LCCR[31:0]
Lost Carrier Counter
See the following
R/W
The LCCR register is a counter that indicates the number of times a loss of carrier is detected during frame transmission.
When the register value becomes FFFF FFFFh, the counter stops. Writing any value to the LCCR register clears the
counter value to 0.
29.2.20
Carrier Not Detect Counter Register (CNDCR)
Address(es): ETHERC0.CNDCR 4006 41DCh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
CNDCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
CNDCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
CNDCR[31:0]
Carrier Not Detect Counter
See the following
R/W
The CNDCR register is a counter that indicates the number of times a carrier is not detected during preamble
transmission. When the register value becomes FFFF FFFFh, the counter stops. Writing any value to the CNDCR
register clears the counter value to 0.
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29.2.21
29. Ethernet MAC Controller (ETHERC)
CRC Error Frame Receive Counter Register (CEFCR)
Address(es): ETHERC0.CEFCR 4006 41E4h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
CEFCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
CEFCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
CEFCR[31:0]
CRC Error Frame Receive Counter
See the following
R/W
The CEFCR register is a counter that indicates the number of received frames in which a CRC error was detected. When
the register value becomes FFFF FFFFh, the counter stops. Writing any value to the CEFCR register clears the counter
value to 0.
29.2.22
Frame Receive Error Counter Register (FRECR)
Address(es): ETHERC0.FRECR 4006 41E8h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
FRECR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
FRECR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
FRECR[31:0]
Frame Receive Error Counter
See the following
R/W
The FRECR register is a counter that indicates the number of times a frame receive error has occurred. The PHY-LSI
notifies the ETHERC of the frame receive error using the ET0_RX_ER pin. The FRECR register increments each time
the ET0_RX_ER pin goes high. When the register value becomes FFFF FFFFh, the counter stops. Writing any value to
the FRECR register clears the counter value to 0.
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29.2.23
29. Ethernet MAC Controller (ETHERC)
Too-Short Frame Receive Counter Register (TSFRCR)
Address(es): ETHERC0.TSFRCR 4006 41ECh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
TSFRCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
TSFRCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
TSFRCR[31:0]
Too-Short Frame Receive Counter
See the following
R/W
The TSFRCR register is a counter that indicates the number of times a short frame that is shorter than 64 bytes was
received. When the register value becomes FFFF FFFFh, the counter stops. Writing any value to the TSFRCR register
clears the counter value to 0.
29.2.24
Too-Long Frame Receive Counter Register (TLFRCR)
Address(es): ETHERC0.TLFRCR 4006 41F0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
TLFRCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
TLFRCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
TLFRCR[31:0]
Too-Long Frame Receive Counter
See the following
R/W
The TLFRCR register is a counter that indicates the number of times a long frame that is longer than the RFLR register
value was received. When the register value becomes FFFF FFFFh, the counter stops. Writing any value to the TLFRCR
register clears the counter value to 0.
Note:
The TLFRCR register does not increment when a frame is received with an alignment error. In this case, the
RFCR register increments.
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29.2.25
29. Ethernet MAC Controller (ETHERC)
Received Alignment Error Frame Counter Register (RFCR)
Address(es): ETHERC0.RFCR 4006 41F4h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
RFCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
RFCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
RFCR[31:0]
Received Alignment Error Frame Counter
See the following
R/W
The RFCR register is a counter that indicates the number of times a frame was received with an alignment error, meaning
that it is not an integral number of octets. When the register value becomes FFFF FFFFh, the counter stops. Writing any
value to the RFCR register clears the counter value to 0.
29.2.26
Multicast Address Frame Receive Counter Register (MAFCR)
Address(es): ETHERC0.MAFCR 4006 41F8h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MAFCR[31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
MAFCR[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MAFCR[31:0]
Multicast Address Frame Receive Counter
See the following
R/W
The MAFCR register is a counter that indicates the number of times a frame with the multicast address set was received.
When the register value becomes FFFF FFFFh, the counter stops. Writing any value to the MAFCR register clears the
counter value to 0.
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29.3
29. Ethernet MAC Controller (ETHERC)
Operation
This section provides an overview of the ETHERC operations. ETHERC supports the flow control compliant with
IEEE802.3x, and can transmit and receive PAUSE frames. When using the ETHERC, set the clock to ICLK = PCLKA
beforehand.
29.3.1
Transmission
The ETHERC transmitter assembles the transmit data into a frame and outputs it to the MII or RMII when a transmit
request is received from the EDMAC. The frame transmitted through the MII or RMII is transmitted on the line by the
PHY-LSI. Figure 29.4 shows the state transitions of the ETHERC transmitter.
Reset
ECMR.TE = 1
Transmission
stopped
Half-duplex mode
Idle
Carrier not sensed
Carrier sense
Transmission starts
(preamble transmitted)
Full-duplex mode
ECMR.TE = 0
Half-duplex mode
Half-duplex mode
Full-duplex mode
Collision
Carrier
detection
Preparation for
retransmission *1
Full-duplex mode
Carrier not detected
Carrier detected
Collision
Retransmission
failed 15 times
or
late collision
SFD
transmission
Error
Collision *2
Error
notification
Error
Data
transmission
Collision *2
Error
Normal transmission
Note 1.
Note 2.
CRC
transmission
Preparation for retransmission after a collision is detected includes transmitting a jam signal and adjusting transmission time
intervals using the backoff algorithm.
Preparation for retransmission is performed only when a collision is detected within 512 bit times after preamble transmission
starts. When a collision is detected after 512 bit times, only a jam signal is transmitted and processing using the backoff
algorithm is not performed.
Figure 29.4
ETHERC transmitter state transitions
The ETHERC transmitter state transitions are as follows:
1. When the ECMR.TE bit is set to 1, the ETHERC enters the transmit idle state.
2. When a transmit request is received from the EDMAC, the ETHERC enters the carrier sense state. The ETHERC
waits for the interpacket gap and then transmits a preamble to the MII or RMII. When full-duplex mode is selected,
carrier sensing is not required, and so the ETHERC transmits a preamble immediately after receiving a transmit
request from the EDMAC.
3. The ETHERC transmits the Start Frame Delimiter (SFD), transmit data, and CRC sequentially. When the
transmission completes successfully, the ETHERC notifies the EDMAC of successful completion, and the EDMAC
sets the EDMAC0.EESR.TC flag to 1. When a late collision or loss of carrier is detected during data transmission,
the ETHERC stops the transmission and notifies the EDMAC of the error.
4. After the time specified as the interpacket gap has elapsed, the ETHERC enters the idle state and continues the
transmission when the transmit data remains.
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29.3.2
29. Ethernet MAC Controller (ETHERC)
Reception
The ETHERC receiver separates the frame input from the MII or RMII into the preamble, SFD, receive data, and CRC,
and transmits only the receive data (destination address, source address, type/length, data/LLC). Figure 29.5 shows the
state transitions of the ETHERC receiver.
Reset
ET0_RX_DV = Low
ECMR.RE = 1
Reception
stopped
ECMR.RE = 0
Idle
Preamble
detected
Frame reception start
ET0_RX_DV = Low
False carrier
detected
Other station address
in normal mode
Wait for SFD
reception
SFD received
Destination
address reception
Own address, broadcast,
multicast, or
promiscuous mode
Error notification *1
Normal reception
Receive error detected
Receive error detected
Data reception
Reception ends
CRC reception
Note 1.
Figure 29.5
Data in error frames is also transferred to the receive buffer.
ETHERC receiver state transitions
The ETHERC receiver state transitions are as follows:
1. When the ECMR.RE bit is set to 1, the ETHERC enters the receive idle state.
2. When the SFD following the preamble of the receive packet is detected, the ETHERC starts reception. If the
received SFD is invalid, the ETHERC discards the frame.
3. In normal mode, the ETHERC starts data reception when the destination address of the receive frame is the address
of the MCU or the receive frame is a broadcast or multicast frame. In promiscuous mode, the ETHERC starts data
reception regardless of the receive frame type.
4. After receiving data from the MII or RMII, the ETHERC performs a CRC check. The ETHERC notifies the
EDMAC of the CRC check result. After the received data is transferred to the receive buffer, the CRC check result
is written back to the receive descriptor as status. The result is also reflected in the EDMAC0.EESR.CERF flag.
5. When the ECMR.RE bit is 1 after one frame is received, the ETHERC prepares to receive the next frame.
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29.3.3
29.3.3.1
29. Ethernet MAC Controller (ETHERC)
Frame Timing
MII frame timing
Figure 29.6 to Figure 29.11 show the MII frame timing.
ET0_TX_CLK
ET0_TX_EN
ET0_ETXD3 to
ET0_ETXD0
Preamble
SFD
Data
CRC
ET0_TX_ER
ET0_CRS
ET0_COL
Figure 29.6
MII frame transmit timing during normal transmission
ET0_TX_CLK
ET0_TX_EN
ET0_ETXD3 to
ET0_ETXD0
Preamble
JAM
ET0_TX_ER
ET0_CRS
ET0_COL
Figure 29.7
MII frame transmit timing when a collision occurs
ET0_TX_CLK
ET0_TX_EN
ET0_ETXD3 to
ET0_ETXD0
Preamble
SFD
Data
ET0_TX_ER
ET0_CRS
ET0_COL
Figure 29.8
MII frame transmit timing when a transmit error occurs
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29. Ethernet MAC Controller (ETHERC)
ET0_RX_CLK
ET0_RX_DV
ET0_ERXD3 to
ET0_ERXD0
Preamble
SFD
Data
CRC
ET0_RX_ER
Figure 29.9
MII frame receive timing during normal reception
ET0_RX_CLK
ET0_RX_DV
ET0_ERXD3 to
ET0_ERXD0
Preamble
SFD
Data
XXXX
ET0_RX_ER
Figure 29.10
MII frame receive timing for receive error notification
ET0_RX_CLK
ET0_RX_DV
ET0_ERXD3 to
ET0_ERXD0
XXXX
1110
XXXX
ET0_RX_ER
Figure 29.11
MII frame receive timing for false carrier notification
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29.3.3.2
29. Ethernet MAC Controller (ETHERC)
RMII frame timing
Figure 29.12 to Figure 29.14 show the RMII frame timing.
REF50CK0
RMII0_TX_EN
RMII0_TXD1
0
0
0
0
0
0
0
0
0
0
0
1
A
B
C
D
E
F
G
H
I
J
0
RMII0_TXD0
1
1
1
1
1
1
1
1
1
1
1
1
A
B
C
D
E
F
G
H
I
J
0
Preamble
Figure 29.12
SFD
Data
RMII frame transmit timing during normal transmission
REF50CK0
nibble boundary
RMII0_CRS_DV
RMII0_RXD1
0
0
0
0
0
0
0
0
0
0
0
1
A
B
C
D
E
F
G
H
I
J
0
RMII0_RXD0
0
0
0
0
0
1
1
1
1
1
1
1
A
B
C
D
E
F
G
H
I
J
0
|J|
Figure 29.13
|K|
Preamble
SFD
Data
RMII frame receive timing during normal reception
REF50CK0
RMII0_CRS_DV
RMII0_RXD1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
RMII0_RXD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
False carrier detected
Figure 29.14
RMII frame receive timing when a false carrier is detected
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29.3.4
29. Ethernet MAC Controller (ETHERC)
Accessing the MII and RMII Registers
Use the PIR register to access the MII and RMII registers in the PHY-LSI. Serial data in the MII and RMII management
frame format is transmitted and received through the ET0_MDC and ET0_MDIO pins controlled by software.
29.3.4.1
MII and RMII management frame format
Table 29.3 lists the MII and RMII management frame formats.
Table 29.3
Access type
Parameter
MII and RMII management frame formats
MII and RMII management frame
PRE
Number of bits 32
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
2
2
5
5
2
16
1
Read
1...1
01
10
00001
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
Write
1...1
01
01
00001
RRRRR
10
DDDDDDDDDDDDDDDD
Z
Note:
PRE (preamble): Send 32 consecutive 1s.
ST (start of frame): Send 01b.
OP (operation code): Send 10b for read or 01b for write.
PHYAD (PHY address): Up to 32 PHY-LSIs can be connected to one MAC. PHY-LSIs are selected with these 5 bits. When the
PHY-LSI address is 1, send 00001b.
REGAD (register address): One register is selected from up to 32 registers in the PHY-LSI. When the register address is 1,
send 00001b.
TA (turnaround): Use 2-bit turnaround time to avoid contention between the register address and data during a read operation.
Send 10b during a write operation. Release the bus for 1 bit during a read operation (Z is output).
(This is indicated as Z0 because 0 is output from the PHY-LSI on the next clock cycle.)
DATA (data): 16-bit data. Sequentially send or receive starting from the MSB.
IDLE (IDLE condition): Wait time before inputting the next MII or RMII management format. Release the bus during a write
operation (Z is output). No control is required, because a bus was already released during a read operation.
29.3.4.2
MII and RMII register access procedure
Access to the MII and RMII registers includes writing data in 1-bit units, reading data in 1-bit units, and releasing the
bus. Figure 29.15 to Figure 29.18 show examples of the MII and RMII register access timing. The access timing differs
with the PHY-LSI type.
(1) Write to the PHY interface register
PIR.MMD bit 1 (write)
PIR.MDO bit write data
PIR.MDC bit 0
(2) Write to the PHY interface register
PIR.MMD bit 1 (write)
PIR.MDO bit write data
PIR.MDC bit 1
ET0_MDC
ET0_MDIO
(1) (2) (3) (1) (2)
(3) Write to the PHY interface register
PIR.MMD bit 1 (write)
PIR.MDO bit write data
PIR.MDC bit 0
Figure 29.15
1-bit data write flow
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(1) Write to the PHY interface register
PIR.MMD bit 0 (read)
PIR.MDC bit 0
(2) Write to the PHY interface register
PIR.MMD bit 0 (read)
PIR.MDC bit 1
(3)Write to the PHY interface register
PIR.MMD bit 0 (read)
PIR.MDC bit 0
Figure 29.16
29. Ethernet MAC Controller (ETHERC)
ET0_MDC
ET0_MDIO
(1) (2) (3)
The PHY-LSI drives ET0_MDIO low
Bus release flow, with TA in read operation in Table 29.3
(1) Write to the PHY interface register
PIR.MMD bit 0 (read)
PIR.MDC bit 1
(2) Read the PHY interface register
Receive data PIR.MDI bit
ET0_MDC
ET0_MDIO
(1)
(1) (2) (3)
(3) Write to the PHY interface register
PIR.MMD bit 0 (read)
PIR.MDC bit 0
Figure 29.17
1-bit data read flow
(1) Write to the PHY interface register
PIR.MMD bit 0 (read)
PIR.MDC bit 0
ET0_MDC
ET0_MDIO
(1)
Figure 29.18
Bus release flow, with IDLE in write operation in Table 29.3
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29.3.5
29. Ethernet MAC Controller (ETHERC)
Magic Packet Detection
The ETHERC supports Wake-on-LAN (WOL). WOL is a function to detect a Magic Packet transmitted from a host
device or other device, and to wake the MCU from a low power mode such as Sleep. When the ETHERC detects a Magic
Packet, it outputs high on the ET0_WOL pin. Write 1 to the EDMAC0.EDMR.SWR bit to drive the ET0_WOL pin low.
Because a Magic Packet is transmitted in broadcast mode, it is received regardless of the destination MAC address
selected in the format. The ETHERC outputs high on the ET0_WOL pin only when the destination MAC address
matches its own MAC address. See the technical documentation provided by Advanced Micro Devices, Inc., for details
on the Magic Packet.
To use WOL in the MCU, use the procedure in the following example:
1. Configure the ICU to disable ETHER_EINT0 interrupt requests.
2. Set the ECMR.MPDE bit to 1 to enable Magic Packet detection, and set the ECMR.RE bit to 1 to enable reception.
3. Set the ECSIPR.MPDIP bit to 1 to enable notification of Magic Packet detection interrupts.
4. Set the EDMAC0.EESIPR.ECIIP bit to 1 to enable ETHERC status register source interrupts.
5. Configure the ICU to enable ETHER_EINT0 interrupt requests.
6. Change the CPU operating mode to Sleep mode or place unused peripherals in the module-stop state, as required.
7. When a Magic Packet is detected, an interrupt request is sent to the CPU. High is output on the ET0_WOL pin to
notify peripheral devices that the Magic Packet was detected.
29.3.5.1
Constraints on Magic Packet detection
The ETHERC receives packets, including broadcast packets, even when waiting to receive a Magic Packet. This means
that the receive data might already be stored in the receive FIFO of the EDMAC when a Magic Packet is detected. Also,
flags in the ECSR and EDMAC0.EESR registers might have changed. When returning to normal operation after
detecting a Magic Packet, set the EDMAC0.EDMR.SWR bit to 1 to reset the ETHERC and EDMAC.
29.3.6
Adjusting Transmission Efficiency by Changing the IPG
The IPG is a non-transmit period between transmit frames. The ETHERC can change the value of the IPG to increase or
decrease transmission efficiency based on the value set in the IPGR register. Typical values are specified in the
IEEE802.3 standard. When changing the setting, confirm that all devices in the same network operate normally.
IPG *1
Short IPG
Packet
Packet
Packet
Packet
Packet
Packet
IPG *1
Long IPG
Note 1.
Figure 29.19
Packet
Packet
Packet
Packet
Packet
The IPG may be longer than the set value depending on the condition of the line or system bus.
Differences in transmission efficiency based on changes in the IPG
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29.3.7
29. Ethernet MAC Controller (ETHERC)
Flow Control
The ETHERC can perform flow control compliant with IEEE802.3x in full-duplex mode, and the receiver and
transmitter can be set independently. PAUSE frames can be transmitted automatically or manually.
29.3.7.1
Automatic PAUSE frame transmission
When the ECMR.TXF bit is set to 1, automatic PAUSE frame transmission is enabled. A PAUSE frame is automatically
transmitted by a PAUSE frame transmit request from the EDMAC. The APR.AP[15:0] bit value is used for the
pause_time parameter of the PAUSE frame.
When a PAUSE frame is transmitted, if the EDMAC is still requesting PAUSE frame transmission after the PAUSE time
elapses, a PAUSE frame is transmitted again. The maximum number of PAUSE frame retransmissions can be set in the
TPAUSER.TPAUSE[15:0] bits. If the maximum number of retransmissions is reached, subsequent PAUSE frames are
not transmitted.
Figure 29.20 shows the procedure for setting up automatic PAUSE frame transmission.
Start
Set the threshold value that starts the flow control
Set the maximum number of PAUSE frame
retransmissions
Set the pause_time parameter
Enable automatic PAUSE frame transmission
Data reception
No
[1]
Set the threshold value in the
EDMAC0.FCFTR.RFDO[2:0] bits or
EDMAC0.FCFTR.RFFO[2:0] bits.
[2]
Set the maximum number of automatic
PAUSE frame retransmissions in the
TPAUSER.TPAUSE[15:0] bits.
[3]
Set the pause_time parameter of the automatic
PAUSE frame in the APR.AP[15:0] bits.
[4]
Set the ECMR.TXF bit to 1.
[5]
Set the ECMR.RE bit to 1.
[6]
Check whether the amount of receive FIFO data
or the number of received frames reached the
threshold.
[7]
Check whether the number of automatic
PAUSE frame retransmissions reached the
threshold.
Threshold Receive data?
Yes
Yes
Maximum = Retransmitted PAUSE frames?
No
PAUSE frame transmission
Figure 29.20
Example procedure for setting up automatic PAUSE frame transmission
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29.3.7.2
29. Ethernet MAC Controller (ETHERC)
Manual PAUSE frame transmission
A PAUSE frame can be manually transmitted at any time. When software writes the pause_time parameter of the PAUSE
frame to the MPR.MP[15:0] bits, the ETHERC transmits a PAUSE frame once. To transmit a PAUSE frame more than
once, write to the MPR.MP[15:0] bits for each transmission.
29.3.7.3
PAUSE frame reception
When the ECMR.RXF bit is set to 1, PAUSE frame detection is enabled. After a PAUSE frame is received, the ETHERC
completes transmission of the current frame and waits for the PAUSE time of the received PAUSE frame to elapse before
it can transmit the next frame. The ETHERC also increments the RFCF.RPAUSE[7:0] bit value.
However, while waiting for the PAUSE time to elapse, if a PAUSE frame that contains a pause_time parameter of 0 is
received and the ECMR.ZPF bit is 1, the ETHERC becomes ready to transmit immediately.
29.3.8
MAC Filter
The MAC filter operates in extended promiscuous mode when the FFLTR.EXTPRM bit setting is 1. In this mode, all
frames received by the Ethernet ports are transferred to the EDMAC without filtering. The MAC filter operates in normal
mode when the FFLTR.EXTPRM bit setting is 0. In this mode, the MAC filter module applies its hardware filtering
function to filter frames received by the Ethernet ports.
The MAC filter and EDMAC transfer received unicast frames if they are for the given node. Operation when multicast
frames are received can be selected from the following:
Frames are transferred to the EDMAC
Frames are not transferred to the EDMAC
Frames are transferred to the EDMAC only when the address matches the specified MAC address.
The MAC filter transfers received broadcast frames to the EDMAC for the receiving Ethernet port.
29.4
Interrupts
When a flag in the ECSR register is set to 1 and the associated bit in the ECSIPR register is 1, the ETHERC notifies the
EDMAC of the interrupt source status. After receiving the notification, the EDMAC sets the EDMAC0.EESR.ECI flag
to 1. When the EDMAC0.EESIPR.ECIIP bit is 1, the EDMAC sends an ETHER_EINT0 interrupt request to the CPU.
For details, see section 30, Ethernet DMA Controller (EDMAC).
29.5
29.5.1
Usage Notes
Preventing the LCHNG Flag from Erroneously Setting to 1
The ECSR.LCHNG flag might set to 1 even when the input level of the ET0_LINKSTA pin remains the same. In this
case, high level is input to the ET0_LINKSTA pin when setting the PFS.PmnPFS register to assign the ET0_LINKSTA
signal to a port, or when releasing the ETHERC and EDMAC software reset using the EDMAC0.EDMR.SWR bit. The
ECSR.LCHNG flag is set to 1 because the ET0_LINKSTA signal in the ETHERC is fixed at a low level regardless of the
input level to the external pin if the MPC does not assign the ET0_LINKSTA signal, or during an ETHERC and EDMAC
software reset.
To avoid erroneously generating a link signal change interrupt, clear the ECSR.LCHNG flag, and then set the
ECSIPR.LCHNGIP bit to 1.
29.5.2
Input to RMII0_RX_ER Pin While RMII Is Selected
When the width of a reception error signal received from the PHY-LSI is only 1 cycle of the REF50CK0 clock (50 MHz)
while the RMII is selected, the signal is not recognized as an error signal.
29.5.3
Collision Occurrence in Half-Duplex Mode
Transmission might start and communication might collide within 21 clock cycles (50 MHz) from reception in halfduplex mode.
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30. Ethernet DMA Controller (EDMAC)
30.
Ethernet DMA Controller (EDMAC)
30.1
Overview
The MCU provides one channel for the Ethernet DMA Controller (EDMAC), for the Ethernet Controller (ETHERC).
The EDMAC controls most of the transmit and receive buffer management for communications. This reduces the load on
the CPU and allows efficient data transmission and reception. The data transfers are controlled according to the
information referred to as descriptors, in memory.
EDMAC0 controls data transmission and reception for ETHERC0.
Table 30.1 lists the EDMAC specifications and Figure 30.1 shows the configuration. Figure 30.2 shows the configuration
of descriptors and the transmit and receive buffers in memory.
Table 30.1
EDMAC specifications
Parameter
Specifications
Data transmission and reception
Controls data transmission and reception according to descriptors
Supports single buffer frame transmission and reception (1 buffer per frame) and multi-buffer
frame transmission and reception (multiple buffers per frame).
Functions
Minimizes system bus occupancy time using block transfer (32-byte units)
Writes back the transmit or receive frame state to descriptors
Inserts padding in receive data.
Module-stop function
Module-stop state can be set to reduce power consumption
External bus controller
RAM
ETHER bus
EDMAC arbiter
PCLKA
Tx/Rx
Control
ETHER_EINT0 (EDMAC0)
Rx FIFO
EDMAC
channel 0
(EDMAC0)
Tx FIFO
Internal peripheral bus
ETHERC channel 0
(ETHERC0)
MII/RMII channel 0
Figure 30.1
EDMAC configuration
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30. Ethernet DMA Controller (EDMAC)
Internal bus
SDRAM
EDMAC arbiter
EDMAC0
Internal bus interface
RAM
Descriptor list
DMAC
receive unit
DMAC
transmit unit
Descriptor
information
stored
Descriptor
information
stored
Receive
FIFO
EDMAC0 descriptor
Transmit buffer
Transmit
descriptor
Receive buffer
Receive
descriptor
Transmit
FIFO
ETHERC0
Figure 30.2
Configuration of descriptors and transmit and receive buffers in memory
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30.2
30. Ethernet DMA Controller (EDMAC)
Register Descriptions
30.2.1
EDMAC Mode Register (EDMR)
EDMR
Address(es): EDMAC0.EDMR 4006 4000h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
DE
—
—
—
SWR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
DL[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SWR
Software Reset
When 1 is written, the associated channels of the EDMAC and
ETHERC are reset.
The TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR registers are not
reset with this bit.The read value is 0.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5, b4
DL[1:0]
Transmit/Receive Descriptor
Length
b5 b4
R/W
b6
DE
Big Endian Mode/Little
Endian Mode*1
0: Big endian mode
1: Little endian mode.
R/W
b31 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
0
0
1
1
0: 16 bytes
1: 32 bytes
0: 64 bytes
1: 16 bytes.
This setting applies to data for the transmit and receive buffers. It does not apply to transmit and receive descriptors and
registers.
The EDMR register controls EDMAC operation. Set the EDMR register during the initialization process after a reset.
When rewriting this register outside of the initialization process, set the SWR bit to 1 to reset the EDMAC and ETHERC,
then set this register again. If the ETHERC and EDMAC are reset during data transmission or reception, abnormal data
might be sent on the line. Do not rewrite this register while the ETHERC transmit or receive function is enabled. It takes
64 cycles of the peripheral module clock (PCLKA) to initialize the ETHERC and EDMAC. Complete the initialization
before accessing registers in the ETHERC and EDMAC.
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30.2.2
30. Ethernet DMA Controller (EDMAC)
EDMAC Transmit Request Register (EDTRR)
Address(es): EDMAC0.EDTRR 4006 4008h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
TR
Transmit Request
When 1 is written, the EDMAC reads the associated descriptor and transmits
frames where the TD0.TACT bit is 1. The TR bit clears to 0 after all the valid
frames are transmitted. Writing 0 to this bit has no effect.
R/W
b31 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The EDTRR register controls EDMAC transmission. After the EDMAC transmits one frame, it reads the next descriptor.
When the TD0.TACT bit in the descriptor is 1, the EDMAC continues transmission. When the TD0.TACT bit is 0, the
EDMAC sets the TR bit to 0 and stops transmission.
30.2.3
EDMAC Receive Request Register (EDRRR)
Address(es): EDMAC0.EDRRR 4006 4010h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
RR
Receive Request
0: Disable the receive function*1
1: Read receive descriptor and enable the receive function.
R/W
b31 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
If the receive function is disabled during frame reception, write-back to the receive descriptor is not performed successfully.
Subsequent pointers for reading a receive descriptor become abnormal and the EDMAC cannot operate normally. In this case,
to enable the EDMAC receive function again, execute a software reset by setting the EDMR.SWR bit to 1.
To disable the EDMAC receive function without resetting the EDMAC, set the ETHERC0.ECMR.RE bit to 0. After the EDMAC
completes reception and write-back to the receive descriptor is confirmed, set the RR bit to 0.
The EDRRR register controls EDMAC reception. When the RR bit is set to 1, the EDMAC reads the receive descriptor.
When the RD0.RACT bit is 1, the EDMAC waits for a receive request from the ETHERC. When the EDMAC has
received data for the receive buffer size, it reads the next descriptor and waits to receive a frame. If the RD0.RACT bit is
0, the EDMAC sets the RR bit to 0 and stops reception.
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30.2.4
30. Ethernet DMA Controller (EDMAC)
Transmit Descriptor List Start Address Register (TDLAR)
Address(es): EDMAC0.TDLAR 4006 4018h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
—
—
These bits specify the start address of the transmit descriptor
list. Set the start address according to the descriptor length
selected in the EDMR.DL[1:0] bits.
16-byte boundary: Lower 4 bits = 0000b
32-byte boundary: Lower 5 bits = 00000b
64-byte boundary: Lower 6 bits = 000000b.
R/W
The TDLAR register specifies the start address of the transmit descriptor list. Align each descriptor on the associated
boundary to the descriptor length selected in the EDMR.DL[1:0] bits. Do not rewrite the TDLAR register during
transmission. Rewrite the TDLAR register while the EDTRR.TR bit is 0.
30.2.5
Receive Descriptor List Start Address Register (RDLAR)
Address(es): EDMAC0.RDLAR 4006 4020h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
—
—
The start address of the receive descriptor list is set. Set the
start address according to the descriptor length selected in the
EDMR.DL[1:0] bits.
16-byte boundary: Lower 4 bits = 0000b
32-byte boundary: Lower 5 bits = 00000b
64-byte boundary: Lower 6 bits = 000000b.
R/W
The RDLAR register specifies the start address of the receive descriptor list. Allocate each descriptor on the associated
boundary to the descriptor length selected in the EDMR.DL[1:0] bits. Do not rewrite the RDLAR register during
reception. Rewrite the RDLAR register while the EDRRR.RR bit is 0.
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30.2.6
30. Ethernet DMA Controller (EDMAC)
ETHERC/EDMAC Status Register (EESR)
Address(es): EDMAC0.EESR 4006 4028h
b31
b30
b29
b28
b27
b26
—
TWB
—
—
—
TABT
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
—
—
—
—
CND
0
0
0
0
0
Value after reset:
Value after reset:
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
ADE
ECI
TC
TDE
TFUF
FR
RDE
RFOF
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
DLC
CD
TRO
RMAF
—
—
RRF
RTLF
RTSF
PRE
CERF
0
0
0
0
0
0
0
0
0
0
0
RABT RFCOF
Bit
Symbol
Bit name
Description
R/W
b0
CERF
CRC Error Flag
0: CRC error not detected
1: CRC error detected.
R/W
b1
PRE
PHY-LSI Receive Error Flag
0: PHY-LSI receive error not detected
1: PHY-LSI receive error detected.
R/W
b2
RTSF
Frame-Too-Short Error Flag
0: Frame-too-short error not detected
1: Frame-too-short error detected.
R/W
b3
RTLF
Frame-Too-Long Error Flag
0: Frame-too-long error not detected
1: Frame-too-long error detected.
R/W
b4
RRF
Alignment Error Flag
0: Alignment error not detected
1: Alignment error detected.
R/W
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
RMAF
Multicast Address Frame Receive
Flag
0: Multicast address frame not received
1: Multicast address frame received.
R/W
b8
TRO
Transmit Retry Over Flag
0: Transmit retry-over condition not detected
1: Transmit retry-over condition detected.
R/W
b9
CD
Late Collision Detect Flag
0: Late collision not detected
1: Late collision detected during frame transmission.
R/W
b10
DLC
Loss of Carrier Detect Flag
0: Loss of carrier not detected
1: Loss of carrier detected during frame transmission.
R/W
b11
CND
Carrier Not Detect Flag
0: Carrier detected when transmission started
1: Carrier not detected during preamble transmission.
R/W
b15 to b12 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
RFOF
Receive FIFO Overflow Flag
0: No overflow occurred
1: Overflow occurred.
R/W
b17
RDE
Receive Descriptor Empty Flag
0: EDMAC detected that the receive descriptor valid bit
(RD0.RACT) is 1
1: EDMAC detected that the receive descriptor valid bit
(RD0.RACT) is 0.
R/W
b18
FR
Frame Receive Flag
0: Frame not received
1: Frame received and update of the receive descriptor is
complete.
R/W
b19
TFUF
Transmit FIFO Underflow Flag
0: No underflow occurred
1: Underflow occurred.
R/W
b20
TDE
Transmit Descriptor Empty Flag
0: EDMAC detected that the transmit descriptor valid bit
(TD0.TACT) is 1
1: EDMAC detected that the transmit descriptor valid bit
(TD0.TACT) is 0.
R/W
b21
TC
Frame Transfer Complete Flag
0: Transfer not complete or no transfer requested
1: All frames indicated in the transmit descriptor were
completely transferred to the transmit FIFO.
R/W
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30. Ethernet DMA Controller (EDMAC)
Bit
Symbol
Bit name
Description
R/W
b22
ECI
ETHERC Status Register Source
Flag
0: ETHERC status interrupt source not detected
1: ETHERC status interrupt source detected.
R*1
b23
ADE
Address Error Flag
0: Invalid memory address not detected (normal operation)
1: Invalid memory address detected.*2
R/W
b24
RFCOF
Receive Frame Counter Overflow
Flag
0: Receive frame counter did not overflow
1: Receive frame counter overflowed.
R/W
b25
RABT
Receive Abort Detect Flag
0: Frame reception not aborted or no reception requested
1: Frame reception aborted.
R/W
b26
TABT
Transmit Abort Detect Flag
0: Frame transmission not aborted or no transmission
requested.
1: Frame transmission aborted.
R/W
b29 to b27 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b30
TWB
Write-Back Complete Flag
0: Write-back not complete or no transmission requested
1: Write-back to the transmit descriptor completed.
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
The ECI flag is read-only. When the source in the ECSR register is cleared, the ECI flag is also cleared.
When an address error is detected, the EDMAC halts the process. To resume operation, set the EDMR.SWR bit to 1 (resetting
the EDMAC and ETHERC), and then reconfigure the EDMAC and ETHERC.
The EESR register indicates the ETHERC and EDMAC communication status. Each flag in the EESR register can be
output as an interrupt request signal (ETHER_EINT0) from the EDMAC. Writing 1 clears all of the flags except ECI to
0. Writing 0 does not affect any of the flag values. The interrupt sources are enabled by setting the associated bits in the
EESIPR register.
CERF flag (CRC Error Flag)
The CERF flag is set to 1 when an error is detected while checking the frame check sequence (FCS) field of the receive
frame.
PRE flag (PHY-LSI Receive Error Flag)
The PRE flag indicates that the RX_ER signal output from the PHY-LSI is high.
RTSF flag (Frame-Too-Short Error Flag)
The RTSF flag indicates that a received frame is less than 64 bytes.
RTLF flag (Frame-Too-Long Error Flag)
The RTLF flag indicates that a received frame is greater than the upper limit of the receive frame length set in the
ETHERC0.RFLR register. The excess data is discarded.
RRF flag (Alignment Error Flag)
The RRF flag indicates that a frame is not an integral number of octets. The last word that is not an integral number of
octets is not transferred.
RMAF flag (Multicast Address Frame Receive Flag)
The RMAF flag indicates that a multicast frame was received.
TRO flag (Transmit Retry Over Flag)
The TRO flag indicates that a collision occurred again during the 15th retry of frame transmission.
CD flag (Late Collision Detect Flag)
The CD flag indicates that a late collision was detected during frame transmission.
DLC flag (Loss of Carrier Detect Flag)
The DLC flag indicates that a loss of carrier was detected during frame transmission.
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30. Ethernet DMA Controller (EDMAC)
CND flag (Carrier Not Detect Flag)
The CND flag is set to 1 when a carrier is not detected during preamble transmission.
RFOF flag (Receive FIFO Overflow Flag)
The RFOF flag indicates that the receive FIFO overflowed during frame reception.
RDE flag (Receive Descriptor Empty Flag)
The RDE flag indicates that the read receive descriptor is invalid. When this flag is set to 1, set the RD0.RACT bit in the
receive descriptor to 1 and set the EDRRR.RR bit to 1 to resume reception.
FR flag (Frame Receive Flag)
The FR flag indicates that a frame was received and the receive descriptor was updated. The FR flag is set to 1 every time
a frame is received.
TFUF flag (Transmit FIFO Underflow Flag)
The TFUF flag indicates that no data remains in the transmit FIFO during frame transmission. Incomplete data is sent to
the line.
TDE flag (Transmit Descriptor Empty Flag)
The TDE flag indicates that the TD0.TACT bit of the transmit descriptor is 0 while the previous transmit descriptor
indicates that the frame is not complete (TD0.TFP[1:0] bits are 10b or 00b) in multi-buffer frame transmission. As a
result, an incomplete frame might be sent.
When this flag is set to 1, perform a software reset and then set the EDTRR.TR bit to 1 to resume transmission.
Transmission starts from the address stored in the TDLAR register.
TC flag (Frame Transfer Complete Flag)
The TC flag indicates that all the data specified in the transmit descriptor was transmitted from the ETHERC. This flag is
set to 1 when one frame was transmitted in a single-buffer frame transmission or when the last data of a frame is
transmitted in a multi-buffer frame transmission and the TD0.TACT bit in the next transmit descriptor is 0. After frame
transmission is complete, the EDMAC writes the transfer status back to the descriptor.
ECI flag (ETHERC Status Register Source Flag)
The ECI flag is set to 1 when an interrupt request is generated by the ECSR register.
ADE flag (Address Error Flag)
The ADE flag indicates that the memory address that the EDMAC tried to use for transfer is invalid.
RFCOF flag (Receive Frame Counter Overflow Flag)
The RFCOF flag indicates that the next frame reception started while the number of frames stored in the receive FIFO
reached the maximum number of frames (16 frames). The received frame is discarded while the RFCOF flag is 1.
RABT flag (Receive Abort Detect Flag)
The RABT flag indicates that the ETHERC aborted frame reception because of a CRC error, PHY-LSI receive error,
frame-too-short error, frame-too-long error, or other errors.
TABT flag (Transmit Abort Detect Flag)
The TABT flag indicates that the ETHERC aborted frame transmission because of transmit retry over, loss of carrier, no
carrier detection, or other errors.
TWB flag (Write-Back Complete Flag)
The TWB flag indicates that the EDMAC completed writing back to the descriptor after frame transmission. This flag is
set to 1 after each frame transmission when the TRIMD.TIM bit is 0. It only is set to 1 when the TRIMD.TIS bit is 1.
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30.2.7
30. Ethernet DMA Controller (EDMAC)
ETHERC/EDMAC Status Interrupt Enable Register (EESIPR)
EESIPR
Address(es): EDMAC0.EESIPR 4006 4030h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
—
TWBIP
—
—
—
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
b24
0
0
0
0
b23
b22
b21
ECIIP
TCIP
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
0
0
TABTIP RABTI RFCOF ADEIP
P
IP
CNDIP DLCIP
0
b25
CDIP
0
0
TROIP RMAFI
P
0
0
b20
b19
b18
TDEIP TFUFIP FRIP
b17
b16
RDEIP RFOFI
P
RRFIP RTLFIP RTSFIP PREIP CERFI
P
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CERFIP
CRC Error Interrupt Request Enable
0: Disable CRC error interrupt requests
1: Enable CRC error interrupt requests.
R/W
b1
PREIP
PHY-LSI Receive Error Interrupt Request
Enable
0: Disable PHY-LSI receive error interrupt requests
1: Enable PHY-LSI receive error interrupt requests.
R/W
b2
RTSFIP
Frame-Too-Short Error Interrupt Request
Enable
0: Disable frame-too-short error interrupt requests
1: Enable frame-too-short error interrupt requests.
R/W
b3
RTLFIP
Frame-Too-Long Error Interrupt Request
Enable
0: Disable frame-too-long error interrupt requests
1: Enable frame-too-long error interrupt requests.
R/W
b4
RRFIP
Alignment Error Interrupt Request Enable
0: Disable alignment error interrupt requests
1: Enable alignment error interrupt requests.
R/W
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
RMAFIP
Multicast Address Frame Receive
Interrupt Request Enable
0: Disable multicast address frame receive interrupt
requests
1: Enable multicast address frame receive interrupt
requests.
R/W
b8
TROIP
Transmit Retry Over Interrupt Request
Enable
0: Disable transmit retry over interrupt requests
1: Enable transmit retry over interrupt requests.
R/W
b9
CDIP
Late Collision Detect Interrupt Request
Enable
0: Disable late collision detected interrupt requests
1: Enable late collision detected interrupt requests.
R/W
b10
DLCIP
Loss of Carrier Detect Interrupt Request
Enable
0: Disable loss of carrier detected interrupt requests
1: Enable loss of carrier detected interrupt requests.
R/W
b11
CNDIP
Carrier Not Detect Interrupt Request
Enable
0: Disable carrier not detected interrupt requests
1: Enable carrier not detected interrupt requests.
R/W
b15 to b12 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
RFOFIP
Receive FIFO Overflow Interrupt Request
Enable
0: Disable overflow interrupt requests
1: Enable overflow interrupt requests.
R/W
b17
RDEIP
Receive Descriptor Empty Interrupt
Request Enable
0: Disable receive descriptor empty interrupt requests
1: Enable receive descriptor empty interrupt requests.
R/W
b18
FRIP
Frame Receive Interrupt Request Enable
0: Disable frame reception interrupt requests
1: Enable frame reception interrupt requests.
R/W
b19
TFUFIP
Transmit FIFO Underflow Interrupt
Request Enable
0: Disable underflow interrupt requests
1: Enable underflow interrupt requests.
R/W
b20
TDEIP
Transmit Descriptor Empty Interrupt
Request Enable
0: Disable transmit descriptor empty interrupt requests
1: Enable transmit descriptor empty interrupt requests.
R/W
b21
TCIP
Frame Transfer Complete Interrupt
Request Enable
0: Disable frame transmission complete interrupt
requests
1: Enable frame transmission complete interrupt
requests.
R/W
b22
ECIIP
ETHERC Status Register Source Interrupt
Request Enable
0: Disable ETHERC status interrupt requests
1: Enable ETHERC status interrupt requests.
R/W
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30. Ethernet DMA Controller (EDMAC)
Bit
Symbol
Bit name
Description
R/W
b23
ADEIP
Address Error Interrupt Request Enable
0: Disable address error interrupt requests
1: Enable address error interrupt requests.
R/W
b24
RFCOFIP
Receive Frame Counter Overflow
Interrupt Request Enable
0: Disable receive frame counter overflow interrupt
requests
1: Enable receive frame counter overflow interrupt
requests.
R/W
b25
RABTIP
Receive Abort Detect Interrupt Request
Enable
0: Disable receive abort detected interrupt requests
1: Enable receive abort detected interrupt requests.
R/W
b26
TABTIP
Transmit Abort Detect Interrupt Request
Enable
0: Disable transmit abort detected interrupt requests
1: Enable transmit abort detected interrupt requests.
R/W
b29 to b27 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b30
TWBIP
Write-Back Complete Interrupt Request
Enable
0: Disable write-back complete interrupt requests
1: Enable write-back complete interrupt requests.
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
The EESIPR register enables interrupt requests associated with bits in the EESR register. When a bit in this register is 1,
the associated interrupt request is enabled.
30.2.8
ETHERC/EDMAC Transmit/Receive Status Copy Enable Register (TRSCER)
Address(es): EDMAC0.TRSCER 4006 4038h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
RMAFC
E
—
—
RRFCE
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
RRFCE
RRF Flag Copy Enable
0: Reflect the EESR.RRF flag status in the RD0.RFE bit of the receive
descriptor
1: Do not reflect the EESR.RRF flag status in the RD0.RFE bit of the
receive descriptor.
R/W
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
RMAFCE
RMAF Flag Copy Enable
0: Reflect the EESR.RMAF flag status in the RD0.RFE bit of the receive
descriptor
1: Do not reflect the EESR.RMAF flag status in the RD0.RFE bit of the
receive descriptor.
R/W
b31 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The TRSCER register selects whether the receive status indicated in the EESR.RMAF and RRF flags is reflected in the
RFE bit of the receive descriptor as a summary. The bits in this register are associated with bits in the EESR register that
have the same number. When the RMAFCE or RRFCE bit is set to 0, the associated receive status is reflected in the RFE
bit. When the RMAFCE or RRFCE bit is set to 1, the associated receive status is not reflected.
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30.2.9
30. Ethernet DMA Controller (EDMAC)
Missed-Frame Counter Register (RMFCR)
Address(es): EDMAC0.RMFCR 4006 4040h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
MFC[15:0]
0
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
MFC[15:0]
Missed-Frame Counter
These bits indicate the number of frames that are discarded and not
transferred to the receive buffer during reception
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b16 —
The RMFCR register indicates the number of frames that could not be stored in the receive FIFO and so were discarded
during reception. When the receive FIFO overflows, it stops receiving data, and the rest of frames are discarded. At the
same time, the RMFCR register value is incremented. When the RMFCR register value reaches FFFFh, count-up is
halted. Writing any value to the RMFCR register clears the counter value to 0.
For frames that are not completely received, after data in the receive FIFO is transferred to the receive buffer, the RACT
bit in the receive descriptor 0 (RD0) clears to 0 (descriptor disabled), the RFS9 bit is set to 1 (receive FIFO overflowed),
and the EESR.RFOF flag is set to 1 (overflow detected).
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30.2.10
30. Ethernet DMA Controller (EDMAC)
Transmit FIFO Threshold Register (TFTR)
Address(es): EDMAC0.TFTR 4006 4048h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
TFT[10:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
TFT[10:0]
Transmit FIFO Threshold
000h: Store-and-forward mode
001h to 00Ch: Setting prohibited
00Dh to 200h: The threshold is the set value multiplied by 4.
Example:
00Dh: 52 bytes
040h: 256 bytes
100h: 1024 bytes
200h: 2048 bytes
201h to 7FFh: Setting prohibited.
R/W
b31 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
When starting transmission before one frame of data is completely written, take care to prevent an underflow. To prevent a
transmit underflow, Renesas recommends using the initial value (store-and-forward mode).
The TFTR register specifies the transmit FIFO threshold at which the first transmission starts. The actual threshold is the
set value multiplied by 4.
The ETHERC starts transmission when the amount of data in the transmit FIFO exceeds the number of bytes set in this
register, when the transmit FIFO is full, or when one frame of data is completely written. Set the TFTR register while the
EDTRR.TR bit is 0.
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30.2.11
30. Ethernet DMA Controller (EDMAC)
FIFO Depth Register (FDR)
Address(es): EDMAC0.FDR 4006 4050h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
0
0
TFD[4:0]
0
0
0
0
0
RFD[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
RFD[4:0]
Receive FIFO Depth
b4
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b12 to b8
TFD[4:0]
Transmit FIFO Depth
b12
R/W
Reserved
These bits are read as 0. The write value should be 0.
b31 to b13 —
b0
01111: 4096 bytes.
Other settings are prohibited.
b8
00111: 2048 bytes.
Other settings are prohibited.
R/W
The FDR register specifies the transmit and receive FIFO depths. Set this register to 0000 070Fh before starting
transmission and reception.
30.2.12
Receive Method Control Register (RMCR)
Address(es): EDMAC0.RMCR 4006 4058h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RNR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RNR
Receive Request Reset
0: EDRRR.RR bit (Receive Request bit) is cleared to 0 when one
frame is received
1: EDRRR.RR bit (Receive Request bit) is not cleared to 0 when
one frame is received.
R/W
b31 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RMCR register specifies how to control the EDRRR.RR bit when receiving a frame. When the RNR bit is 0, the
EDRRR.RR bit clears to 0 when one frame is received, so it must be set to 1 by software to receive the subsequent frame.
When the RNR bit is 1, the EDRRR.RR bit does not clear to 0 when one frame is received, and the EDMAC reads the
next receive descriptor and continues frame reception. Renesas recommends setting the RNR bit to 1 when receiving
data continuously. Set the RMCR register while the EDRRR.RR bit is 0.
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30.2.13
30. Ethernet DMA Controller (EDMAC)
Transmit FIFO Underflow Counter (TFUCR)
Address(es): EDMAC0.TFUCR 4006 4064h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
UNDER[15:0]
0
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
UNDER[15:0]
Transmit FIFO Underflow Count
These bits indicate how many times the transmit FIFO
underflows. The counter stops when the counter value
reaches FFFFh.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b16 —
The TFUCR register indicates how many times the transmit FIFO underflows. Writing any value to the TFUCR register
clears the counter value to 0.
30.2.14
Receive FIFO Overflow Counter (RFOCR)
Address(es): EDMAC0.RFOCR 4006 4068h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
OVER[15:0]
0
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
OVER[15:0]
Receive FIFO Overflow Count
These bits indicate how many times the receive FIFO overflows.
The counter stops when the counter value reaches FFFFh.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b16 —
The RFOCR register indicates how many times the receive FIFO overflows. Writing any value to the RFOCR register
clears the counter value to 0.
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30.2.15
30. Ethernet DMA Controller (EDMAC)
Independent Output Signal Setting Register (IOSR)
Address(es): EDMAC0.IOSR 4006 406Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ELB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ELB
External Loopback Mode
0: Output low on the ET0_EXOUT pin
1: Output high on the ET0_EXOUT pin.
R/W
b31 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The IOSR register selects the output level of the ETHERC external output pin (ET0_EXOUT) in external loopback
mode. The ELB bit value is output on the ET0_EXOUT pin, which can be used to set the loopback mode for the PHYLSI. To use the loopback function of the PHY-LSI through this register, you must connect the PHY-LSI to the
ET0_EXOUT pin.
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30.2.16
30. Ethernet DMA Controller (EDMAC)
Flow Control Start FIFO Threshold Setting Register (FCFTR)
Address(es): EDMAC0.FCFTR 4006 4070h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
RFFO[2:0]
RFDO[2:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b2 to b0
RFDO[2:0]
Receive FIFO Data
PAUSE Output
Threshold
b2
R/W
b15 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b18 to b16 RFFO[2:0]
Receive FIFO Frame
PAUSE Output
Threshold
b18
R/W
b31 to b19 —
Reserved
These bits are read as 0. The write value should be 0.
b0
0 0 0:When 224 (256 to 32) bytes of data is stored in the receive FIFO
0 0 1:When 480 (512 to 32) bytes of data is stored in the receive FIFO
:
1 1 0:When 1760 (1792 to 32) bytes of data is stored in the receive
FIFO
1 1 1:When 2016 (2048 to 32) bytes of data is stored in the receive
FIFO.
b16
0 0 0:When 2 receive frames are stored in the receive FIFO
0 0 1:When 4 receive frames are stored in the receive FIFO
0 1 0:When 6 receive frames are stored in the receive FIFO
:
1 1 0:When 14 receive frames are stored in the receive FIFO
1 1 1:When 16 receive frames are stored in the receive FIFO.
R/W
The FCFTR register specifies the ETHERC flow control. Set the threshold to automatically transmit a PAUSE frame.
The threshold can be set using the data size (RFDO[2:0] bits) and the number of frames (RFFO[2:0] bits) stored in the
receive FIFO. Flow control starts when the stored data size or the number of stored frames reaches its threshold.
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30.2.17
30. Ethernet DMA Controller (EDMAC)
Receive Data Padding Insert Register (RPADIR)
Address(es): EDMAC0.RPADIR 4006 4078h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PADS[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
PADR[5:0]
0
0
0
0
Bit
Symbol
Bit name
b5 to b0
PADR[5:0]
Padding Slot
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b17, b16
PADS[1:0]
Padding Size
b17b16
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b18 —
Description
R/W
00h: Insert padding at the head of received data
01h: Insert padding between the 1st and 2nd bytes of received data
:
3Eh: Insert padding between the 62nd and 63rd bytes of received data
3Fh: Insert padding between the 63rd and 64th bytes of received data.
0 0: Do not insert padding
Other settings are prohibited.
R/W
The RPADIR register specifies the insertion of padding for received data. The padding value is 00h. Set the EDMR.SWR
bit to 1 to reset before rewriting the PRADIR register.
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30.2.18
30. Ethernet DMA Controller (EDMAC)
Transmit Interrupt Setting Register (TRIMD)
Address(es): EDMAC0.TRIMD 4006 407Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
TIM
—
—
—
TIS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TIS
Transmit Interrupt Enable
0: Disable transmit interrupts
1: Enable transmit Interrupts.
Set the EESR.TWB flag to 1 in the mode selected in the TIM bit to report
an interrupt.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
TIM
Transmit Interrupt Mode
0: Select transmission complete interrupt mode, where an interrupt
occurs when a frame is transmitted
1: Select write-back complete interrupt mode, where an interrupt occurs
when write-back to the transmit descriptor is complete while the TWBI
bit is 1.
R/W
b31 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The TRIMD register specifies the transmit interrupt mode and enables or disables transmit interrupts. When the
condition selected in this register is satisfied, the EESR.TWB flag is set to 1, and an interrupt request is output when the
EESIPR.TWBIP bit is 1.
30.2.19
Receive Buffer Write Address Register (RBWAR)
Address(es): EDMAC0.RBWAR 4006 40C8h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The RBWAR register indicates the last address to which the EDMAC wrote data to, when writing to the receive buffer.
Check the contents of this register to identify the address in the receive buffer to which the EDMAC is writing data to.
The address that the EDMAC is outputting to the receive buffer might not match the read value of the RBWAR register
during data reception. The RBWAR register is read-only. Do not write to this register.
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30.2.20
30. Ethernet DMA Controller (EDMAC)
Receive Descriptor Fetch Address Register (RDFAR)
Address(es): EDMAC0.RDFAR 4006 40CCh
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC is fetching
descriptor information from the receive descriptor. Check the contents of this register to identify which receive descriptor
information the EDMAC is using for active processing. The address of the receive descriptor that the EDMAC is
fetching might not match the read value of the RDFAR register during data reception. The RDFAR register is read-only.
Do not write to this register.
30.2.21
Transmit Buffer Read Address Register (TBRAR)
Address(es): EDMAC0.TBRAR 4006 40D4h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The TBRAR register indicates the last address from which the EDMAC read data, when reading data from the transmit
buffer. Check the contents of this register to identify which address in the transmit buffer the EDMAC is reading from.
The address that the EDMAC is outputting to the transmit buffer might not match the read value of the TBRAR register.
The TBRAR register is read-only. Do not write to this register.
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30.2.22
30. Ethernet DMA Controller (EDMAC)
Transmit Descriptor Fetch Address Register (TDFAR)
Address(es): EDMAC0.TDFAR 4006 40D8h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC is fetching the
descriptor information from the transmit descriptor. Check the contents of this register to identify which transmit
descriptor information the EDMAC is using for active processing. The address of the transmit descriptor that the
EDMAC fetches might not match the read value of the TDFAR register. The TDFAR is read only. Do not write to this
register.
30.3
Operation
The EDMAC transfers data according to the information written in the descriptor. Two descriptors are provided: transmit
and receive. A descriptor includes the buffer size, address, and transmit or receive status. The EDMAC transmits or
receives data continuously by using sequentially arranged descriptors.
30.3.1
Descriptor Lists and Data Buffers
To transfer data using the EDMAC, create the transmit and receive descriptor lists in memory, set the start address of the
transmit descriptor list in the TDLAR register, and set the start address of the receive descriptor list in the RDLAR
register. Also, the transmit and receive buffers associated with each descriptor are required.
Align the descriptor list on the appropriate address boundary according to the descriptor length set in the EDMR.DL[1:0]
bits. The transmit buffer can be aligned on a word boundary, halfword boundary, or byte boundary. When the valid
transmit buffer size is 16 bytes or less, align it on a 32-byte boundary. Align the receive buffer on a 32-byte boundary. Set
different addresses for the transmit and receive descriptors and buffers for EDMAC0.
30.3.1.1
Transmit descriptor
Figure 30.3 shows the relationship between a transmit descriptor and a transmit buffer. A transmit descriptor consists of
TD0 to TD2. The transmit frame and transmit buffer configuration can be specified as one buffer per frame (single-buffer
frame transmission) or multiple buffers per frame (multi-buffer frame transmission) by setting the transmit descriptor.
Transmit buffer
TFS
TFE
b0
TWBI
TD2
b31
TFP0
b31
TFP1
TD1
TDLE
TD0
TACT
b31 b30 b29 b28 b27 b26 b25
Valid transmit
data
b16
TBL
TBA
b0
Padding (4/20/52 bytes) *1
Note 1.
Figure 30.3
The padding size is determined by the descriptor length (16/32/64 bytes).
Relationship between transmit descriptor and transmit buffer
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(1)
30. Ethernet DMA Controller (EDMAC)
Transmit descriptor 0 (TD0)
Bit
Symbol
Bit name
Description
R/W
b25 to b0
TFS
Transmit Frame Status
Set all bits to 0 when creating a descriptor. After write-back, the bits
indicate the following:
TFS25 to TFS9: Reserved
TFS8: Transmit abort was detected (value is equivalent to the
EESR.TABT flag)
TFS7 to TFS4: Reserved
TFS3: No carrier was detected (value is equivalent to the EESR.CND
flag)
TFS2: Loss of carrier was detected (value is equivalent to the
EESR.DLC flag)
TFS1: Late collision during transmission was detected (value is
equivalent to the EESR.CD flag)
TFS0: Transmit retry over (value is equivalent to the EESR.TRO
flag).
When a bit is set to 1, it indicates that the associated error occurred
during frame transmission. When any of the TFS bits is set to 1, the
TFE bit is also set to 1. When any of bits TFS3 to TFS0 is set to 1,
TFS8 is also set to 1.
R/W
b26
TWBI
Write-Back Complete
Interrupt Enable
0: Do not generate interrupt when write-back to this descriptor is
complete
1: Generate interrupt when write-back to this descriptor is complete.
R/W
b27
TFE
Transmit Frame Error
0: Frame transmission is successfully complete
1: Error occurred during frame transmission (transmission aborted).
R/W
b29, b28
TFP[1:0]
Transmit Frame Position
b29 b28
R/W
b30
TDLE
Transmit Descriptor List End
When this bit is 1, it indicates that this descriptor is the last in the
descriptor list
R/W
b31
TACT
Transmit Descriptor Valid
This bit indicates that this descriptor is valid
R/W
Note:
0 0: Transmit buffer indicated in this descriptor is the middle of a
transmit frame (frame information is incomplete)
0 1: Transmit buffer indicated in this descriptor is the end of a
transmit frame (frame information is complete)
1 0: Transmit buffer indicated in this descriptor is the head of a
transmit frame (frame information is incomplete)
1 1: Transmit buffer indicated in this descriptor is all of a transmit
frame (one buffer per frame).
Bits for write-back are underlined.
TD0 specifies the transmit frame settings and indicates the status after transmission.
TFE bit (Transmit Frame Error)
When the TFE bit is 1, it indicates that any of the TFS bits is 1.
TFP[1:0] bits (Transmit Frame Position)
The TFP[1:0] bits indicate which part of a transmit frame corresponds to the transmit buffer indicated in this descriptor.
The TFP[1:0] and TD1.TBL bit settings must be logically consistent in the previous and next descriptors.
TACT bit (Transmit Descriptor Valid)
The TACT bit indicates that this descriptor is valid. The TACT bit is set to 1 by software. This bit sets to 0 when the
transmit frame is transferred or when the transmission is aborted.
(2)
Transmit descriptor 1 (TD1)
Bit
Symbol
Bit name
Description
R/W
b15 to b0
—
Reserved
The read value is 0. The write value should be 0.
R/W
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Bit
Symbol
b31 to b16 TBL
30. Ethernet DMA Controller (EDMAC)
Bit name
Description
R/W
Transmit Buffer Length
Specifies the valid byte length of the associated transmit buffer. Set a
value equal to or greater than 1.
R/W
TD1 specifies the valid byte length of the transmit buffer.
(3)
Transmit descriptor 2 (TD2)
Bit
Symbol
Bit name
Description
R/W
b31 to b0
TBA
Transmit Buffer Address
Specifies the start address of the transmit buffer. When the TD1.TBL bit
value is 1 to 16 bytes, align it on a 32-byte boundary.
R/W
TD2 specifies the start address of the transmit buffer.
30.3.1.2
Receive descriptor
Figure 30.4 shows the relationship between a receive descriptor and receive buffer. The receive frame and receive buffer
configuration can be specified as one buffer per frame (single-buffer frame transmission) or multiple buffers per frame
(multi-buffer frame transmission) by setting the receive descriptor. If the receive buffer length (RBL) is set to 0, the
operation indicated in the descriptor is not guaranteed.
Receive Buffer
RBL
RFS
b0
RFE
RD2
b31
RFP0
b31
RFP1
RD1
RDLE
RD0
RACT
b31 b30 b29 b28 b27 b26
b16 b15
RFL
RBA
Valid receive
data
b0
b0
Padding (4/20/52 bytes) *1
Note 1.
Figure 30.4
(1)
The padding size is determined by the descriptor length (16/32/64 bytes).
Relationship between receive descriptor and receive buffer
Receive descriptor 0 (RD0)
Bit
Symbol
Bit name
Description
b26 to b0
RFS
Receive Frame
Status
Set all bits to 0 when creating a descriptor. After write-back, the bits indicate the R/W
following:
RFS26 to RFS10: Reserved
RFS9: Receive FIFO overflow (value is equivalent to the EESR.RFOF flag)
RFS8: Receive abort was detected (value is equivalent to the EESR.RABT flag)
RFS7: Multicast address frame was received (value is equivalent to the
EESR.RMAF flag)
RFS6 and RFS5: Reserved
RFS4: Alignment error was detected (value is equivalent to the EESR.RRF flag)
RFS3: Frame-too-long error (value is equivalent to the EESR.RTLF flag)
RFS2: Frame-too-short error (value is equivalent to the EESR.RTSF flag)
RFS1: PHY-LSI receive error (value is equivalent to the EESR.PRE flag)
RFS0: CRC error (value is equivalent to the EESR.CERF flag).
When a bit is set to 1, it indicates that the associated error occurred during frame
reception. When any of the RFS bits is set to 1, the RFE bit is also set to 1.
Set the TRSCER register to select whether bits RFS7 and RFS4 are reflected in
the RFE bit. When any of the RFS3 to RFS0 bits is set to 1, RFS8 is also set to 1.
b27
RFE
Receive Frame Error 0: No error occurred in the received frame
1: Error occurred in the received frame.
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30. Ethernet DMA Controller (EDMAC)
Bit
Symbol
Bit name
Description
R/W
b29, b28
RFP[1:0]
Receive Frame
Position
b29 b28
R/W
b30
RDLE
Receive Descriptor
List End
When this bit is 1, it indicates that this descriptor is the last in the descriptor list
R/W
b31
RACT
Receive Descriptor
Valid
Indicates that this descriptor is valid
R/W
Note:
0 0: Receive buffer indicated in this descriptor is the middle of a receive frame
(frame information is incomplete)
0 1: Receive buffer indicated in this descriptor is the end of a receive frame
(frame information is complete)
1 0: Receive buffer indicated in this descriptor is the head of a receive frame
(frame information is incomplete)
1 1: Receive buffer indicated in this descriptor is all of a receive frame (one
buffer per frame).
Bits for write-back are underlined.
RD0 indicates the receive frame status.
RFE bit (Receive Frame Error)
When the RFE bit is 1, it indicates that any of the RFS bits is 1. Set the TRSCER register to select whether the RFS7 and
RFS4 bits of EDMAC0 are reflected in the RFE bit.
RFP[1:0] bits (Receive Frame Position)
The RFP[1:0] bits indicate which part of a receive frame corresponds to the receive buffer indicated in this descriptor.
RACT bit (Receive Descriptor Valid)
The RACT bit indicates that this descriptor is valid. The RACT bit is set to 1 by software. This bit clears to 0 when all the
data is transferred to the receive buffer indicated in RD2 or when the receive buffer becomes full.
(2)
Receive descriptor 1 (RD1)
Bit
Symbol
Bit name
Description
R/W
b15 to b0
RFL
Receive Frame
Length
Specifies the length (number of bytes) of the receive frame stored in the
buffer. This does not include the number of bytes for padding set in the
RPADIR register. These bits are written back to the descriptor associated
with the end of a frame.
R/W
Receive Buffer Length
Specifies the byte length of the associated receive buffer. Set an integral
multiple of 32 as the buffer length.
R/W
b31 to b16 RBL
Note:
Bits for write-back are underlined.
RD1 specifies the receive buffer length. When reception is complete, the receive frame length is written back.
(3)
Receive descriptor 2 (RD2)
Bit
Symbol
Bit name
Description
R/W
b31 to b0
RBA
Receive Buffer
Address
Specifies the start address of the receive buffer. Align the buffer address on
a 32-byte boundary.
R/W
RD2 specifies the start address of the receive buffer.
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30.3.2
30. Ethernet DMA Controller (EDMAC)
Transmission
When the EDTRR.TR bit is set to 1 while the ETHERC0.ECMR.TE bit is 1, the EDMAC reads the descriptor following
the previously used descriptor in the transmit descriptor list (or the descriptor indicated in the TDLAR register after a
reset). When the TACT bit is 1 in the transmit descriptor (TD0), the EDMAC sequentially reads transmit data from the
start address of the transmit buffer indicated in transmit descriptor 2 (TD2) and transfers it to the ETHERC through the
transmit FIFO. The ETHERC creates a transmit frame and starts transmission to the MII or RMII. When all data
indicated in the TD1.TBL bit is transferred, write-back is performed according on the TD0.TFP[1:0] bit setting as
follows:
When the TD0.TFP[1:0] bits are 00b or 10b (frame is incomplete), the TD0.TACT bit is written back
When the TD0.TFP[1:0] bits are 01b or 11b (frame is complete), the TD0.TACT, TD0.TFS, and TD0.TFE bits are
written back.
When the TD0.TACT bit in the read descriptor is 1, the EDMAC continues reading descriptors and transmit frames.
When the TD0.TACT bit in the read descriptor is 0, the EDMAC sets the EDTRR.TR bit to 0 and stops transmission.
EDMAC
CPU + Memory
Transmit
FIFO
ETHERC
Ethernet
ETHER/EDMAC
initialization
Descriptor and transmit
buffer settings
Start transmission
Read the descriptor
Transmit
data transf
er
Write back to the
descriptor
Read the descriptor
Transmit
d
ata transf
er
Frame
transmission
Write back to the
descriptor
Transmission
complete
Figure 30.5
Example of transmission flow
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30.3.3
30. Ethernet DMA Controller (EDMAC)
Reception
When the EDRRR.RR bit is set to 1 while the ETHERC0.ECMR.RE bit is 1, the EDMAC reads the receive descriptor
following the previously used descriptor (or the descriptor indicated in the RDLAR register after a reset) and then waits
for reception. When the RD0.RACT bit is 1, if the data stored in the receive FIFO is 32 bytes or more, or if the end byte
of the frame is stored in the receive buffer, the EDMAC transfers data from the receive FIFO to the receive buffer
indicated in Receive Descriptor 2 (RD2).
If the data length of the received frame is longer than the buffer length set in the RBL bit in receive descriptor 1 (RD1),
the EDMAC writes back 10b or 00b to the RD0.RFP[1:0] bits and 0 to the RD0.RACT bit when the receive buffer
becomes full, and then the EDMAC reads the next data. After that, the EDMAC transfers data to another receive buffer.
When the frame reception is complete or when the frame reception is aborted by an error, the EDMAC writes back 11b
or 01b to the RD0.RFP[1:0] bits, 0 to the RD0.RACT bit, and the receive frame length to the RD1.RFL bit. When the
RMCR.RNR bit is 1, the EDMAC reads the next descriptor and waits for reception. When the RNR bit is 0, the EDMAC
sets the EDRRR.RR bit to 0 and stops reception.
EDMAC
CPU + Memory
Receive
FIFO
ETHERC
Ethernet
ETHERC/EDMAC
initialization
Descriptor and receive
buffer settings
Start reception
Read the descriptor
Frame
reception
sfer
data tran
Receive
Write back to the descriptor
Read the descriptor
d
Receive
fer
ata trans
Write back to the descriptor
Read the descriptor
(prepare to receive the next
frame)
Figure 30.6
Reception
complete
Example of reception flow
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30.3.4
30. Ethernet DMA Controller (EDMAC)
Multi-Buffer Frame Transmission
30.3.4.1
Error processing while transmitting multi-buffer frame
If an error occurs during multi-buffer frame transmission, the EDMAC performs the processing shown in Figure 30.7. In
the figure, when the TACT bit of transmit descriptor 0 (TD0) is 0, the descriptor indicates that all data in the buffer is
successfully transmitted. When the TACT bit is 1, the descriptor indicates that data in the buffer is not yet transmitted. If
a frame transmit error*1 occurs in the head or at the middle of the frame while the TD0.TACT bit is 1, the EDMAC stops
data transmission from the transmit FIFO and EDMAC data transfer, and sets the TD0.TACT bit to 0.
After that, the EDMAC reads the next descriptor to see if the descriptor indicates the middle of the frame (TD0.TFP[1:0]
bits are 00b) or the end of the frame (TD0.TFP[1:0] bits are 01b). When the descriptor indicates the middle of the frame,
the EDMAC sets the TD0.TACT bit to 0 and reads the next descriptor. When the descriptor indicates the end of the
frame, in addition to setting the TD0.TACT bit to 0, the EDMAC also writes back to the TD0.TFE and TD0.TFS bits.
After an error occurs, data in the buffer is not transmitted until write-back to the descriptor for the end of the frame.
When the associated transmit error interrupt is enabled in the EESIPR register, an interrupt request is generated
immediately after write-back to the descriptor for the end of the frame.
Note 1. A transmit retry-over condition, late collision, or loss of carrier is detected, or a carrier is not detected.
TACT
TDLE
TFP1
TFP0
Descriptor
0 0 1 0
0 0 0 0
0 0 0 0
Set the TACT bit to 0
Transmit error
occurs
1 0 0 0
EDMAC
Read the descriptor
Set the TACT bit to 0
1 0 0 0
Read the descriptor
Set the TACT bit to 0
1 0 0 0
Read the descriptor
Set the TACT bit to 0
1 0 0 0
Read the descriptor
Set the TACT bit to 0, and 1 0 0 1
write to the TFE and TFS bits
The EDMAC does
not transmit data
that remains in the
buffer after an error
occurs. It only
processes the
descriptor.
One frame
Buffer
1 1 1 0
Data already transmitted
Untransmitted data
Figure 30.7
EDMAC operation after transmit error occurs
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30.3.4.2
30. Ethernet DMA Controller (EDMAC)
Error processing while receiving multi-buffer frame
If an error occurs during multi-buffer frame reception, the EDMAC performs the processing shown in Figure 30.8. In the
figure, when the RACT bit of the receive descriptor 0 (RD0) is 0, the descriptor indicates that data was successfully
received in the buffer. When the RACT bit is 1, the descriptor indicates that data is not yet received in the buffer. If a
frame receive error*1 occurs, the EDMAC stops receiving new data, but it transfers data that is already stored in the
receive FIFO to the receive buffer.
When the receive buffer becomes full during transfer, the EDMAC sets the RACT bit to 0 and the RFP[1:0] bits to 10b or
00b, and reads the next descriptor. After all data in the receive FIFO is transferred, the EDMAC writes back the status to
the descriptor.
When the associated receive error interrupt is enabled in the EESIPR register, an interrupt request is generated
immediately after write-back to the descriptor. When there is a request to receive a new frame, the EDMAC continues
reception using the descriptor following the descriptor where the error occurred.
Note 1. A CRC error, PHY-LSI receive error, frame-too-short error, frame-too-long error, or alignment error is detected.
RACT
RDLE
RFP1
RFP0
Descriptor
0 0 1 0
Head of a frame
0 0 0 0
EDMAC
Set the RACT bit to 0 and
write to the RFE and RFS bits
0 0 0 0
1 0 0 1
Read the descriptor
Write back
1 0 0 0
1 0 0 0
Receive error occurs
The EDMAC
subsequently
receives a new frame
from this buffer
1 0 0 0
1 0 0 0
Buffer
1 1 0 0
Data already received
Untransmitted data
Figure 30.8
EDMAC operation after receive error occurs
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30.4
30. Ethernet DMA Controller (EDMAC)
Interrupts
When any of the status flags in the EESR register is set to 1 while the associated interrupt request enable bit in the
EESIPR register is 1, EDMAC0 issues an ETHER_EINT0 interrupt request.
30.5
30.5.1
Usage Notes
Settings for the Module-Stop Function
The following bit in Module Stop Control Register B (MSTPCRB) enables or disables the EDMAC module operation:
The MSTPB15 bit enables or disables ETHERC0 and EDMAC0 operation
The modules are initially stopped after reset. Releasing the module-stop state enables access to the registers. For details,
see section 11, Low Power Modes.
30.5.2
Stopping the EDMAC during Operation
When stopping EDMAC operation by using a Sleep instruction or the module-stop function while the EDMAC is
running, confirm that the EDTRR.TR and EDRRR.RR bits are 0. If the EDMAC is stopped while the EDTRR.TR or
EDRRR.RR bit is 1, data for the frame that is being transmitted or received might not be complete, and the EDMAC
operation after exiting Sleep mode or the module-stop state is not guaranteed.
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31. USB 2.0 Full-Speed Module (USBFS)
31.
USB 2.0 Full-Speed Module (USBFS)
31.1
Overview
The MCU provides a USB 2.0 Full-Speed module (USBFS) that operates as a host or device controller compliant with
the Universal Serial Bus (USB) specification revision 2.0. The host controller supports USB 2.0 full-speed and lowspeed transfers, and the device controller supports USB 2.0 full-speed transfers. The USBFS has an internal USB
transceiver and supports all of the transfer types defined in the USB 2.0 specification.
The USBFS has a FIFO buffer for data transfers, providing a maximum of 10 pipes. Any endpoint number can be
assigned to pipes 1 to 9, based on the peripheral devices or the communication requirements for your system.
Table 31.1 lists the USBFS specifications, Figure 31.1 shows a block diagram, and Table 31.2 lists the I/O pins.
Table 31.1
USBFS specifications
Parameter
Specifications
Features
USB Device Controller (UDC) and USB 2.0 transceiver supporting host controller, device
controller, and On-The-Go (OTG) functions (one channel)
Host and device controller can be switched by software
Self-power or bus power mode selectable.
Host controller features:
Full-speed transfer (12 Mbps) and low-speed transfer (1.5 Mbps)
Automatic scheduling for SOF and packet transmissions
Programmable intervals for isochronous and interrupt transfers
Communications with multiple peripheral devices connected through a single hub.
Device controller features:
Full-speed transfer (12 Mbps)*1
Control transfer stage control function
Device state control function
Auto response function for SET_ADDRESS request
SOF interpolation.
Supported transfer types
Pipe configuration
FIFO buffer for USB communication
Up to 10 pipes selectable, including the Default Control Pipe (DCP)
Pipes 1 to 9 assignable to any endpoint number.
Control transfer
Bulk transfer
Interrupt transfer
Isochronous transfer.
Transfer conditions specifiable for each pipe:
Pipe 0: Control transfer with 64-byte single buffer
Pipes 1 and 2: Selectable to bulk transfer with 64-byte double buffer or isochronous transfer
with 256-byte double buffer
Pipes 3 to 5: Bulk transfer with 64-byte double buffer
Pipes 6 to 9: Interrupt transfer with 64-byte single buffer.
Other features
Reception end function using transaction count
Function that changes the BRDY interrupt event notification timing (BFRE)
Automatic clearing of the FIFO buffer after the data for the pipe specified in the
DnFIFO port (n = 0, 1) is read (DCLRM)
NAK setting function for response PID generated on transfer end (SHTNAK)
On-chip pull-up and pull-down resistors for D+ and D-.
Module-stop function
Module-stop state can be set to reduce power consumption
Note 1.
Low-speed transfer (1.5 Mbps) is not supported.
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31. USB 2.0 Full-Speed Module (USBFS)
LINK core
Internal peripheral bus
Registers
USB device
controller
USB_DP
USB_DM
USB protocol
engine
Interrupt
controller
FIFO buffer
controller
FIFO
controller
Bus interface controller
Registers
USB
transceiver
Memory
controller
USB clock (48 MHz)
USB clock control
Figure 31.1
USBFS block diagram
Table 31.2
USBFS pin configuration
1-port SRAM
(16-bit width)
PCLKB
USB clock (48 MHz)
PCLKB
Port
Pin name
I/O
Function
USBFS
USB_DP
I/O
D+ I/O for the on-chip USB transceiver.
Must be connected to the D+ data line of the USB bus.
USB_DM
I/O
D- I/O pin for the on-chip USB transceiver.
Must be connected to the D- data line of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin.
Must be connected to VBUS signal on the USB bus. VBUS pin status (connected or
disconnected) can be detected when the USBFS is a device controller.*1
USB_EXICEN
Output
Low-power control signal for the OTG power supply IC
USB_VBUSEN
Output
VBUS (5 V) enable signal for the external power supply IC
USB_OVRCURA
USB_OVRCURB
Input
Overcurrent pins for USBFS.
Must be connected to external overcurrent detection signals. When the OTG power
supply chip is connected, must be connected to the VBUS comparator signals.
USB_ID
Input
Must be connected to MicroAB connector ID input signal in OTG mode
VCC_USB
Input
USB transceiver input supply voltage
VSS_USB
Input
USB ground pin
Common
Note 1.
P407 is 5 V tolerant.
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31.2
31. USB 2.0 Full-Speed Module (USBFS)
Register Descriptions
31.2.1
System Configuration Control Register (SYSCFG)
Address(es): USBFS.SYSCFG 4009 0000h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
SCKE
—
—
—
0
0
0
0
0
0
0
0
0
b6
b5
b4
DCFM DRPD DPRPU
0
0
0
b3
b2
b1
b0
—
—
—
USBE
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
USBE
USBFS Operation Enable
0: Disable
1: Enable.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
DPRPU
D+ Line Resistor Control
0: Disable line pull-up
1: Enable line pull-up.
R/W
b5
DRPD
D+/D- Line Resistor Control
0: Disable line pull-down
1: Enable line pull-down.
R/W
b6
DCFM
Controller Function Select
0: Select device controller
1: Select host controller.
R/W
b9 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b10
SCKE
USB Clock Enable
0: Stop clock supply to the USBFS
1: Enable clock supply to the USBFS.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
After writing 1 to the SCKE bit, read it to confirm that it is set to 1.
USBE bit (USBFS Operation Enable)
The USBE bit enables or disables the operation of the USBFS.
Changing the USBE bit from 1 to 0 initializes the bits listed in Table 31.3. Only change this bit while the SCKE bit is 1.
In host controller mode, this bit must be set to 1 after setting the DRPD bit to 1, eliminating SYSSTS0.LNST[1:0] bit
chattering, and confirming that the USB bus state is stable.
Table 31.3
Registers initialized by writing 0 to the SYSCFG.USBE bit
Selected function
Device controller
Host controller
Register
Bit
Remarks
SYSSTS0
LNST[1:0]
Value is saved in host controller mode
DVSTCTR0
RHST[2:0]
-
INTSTS0
DVSQ[2:0]
Value is saved in host controller mode
USBADDR
USBADDR[6:0]
Value is saved in host controller mode
USBREQ
BREQUEST[7:0],
BMREQUESTTYPE[7:0]
Value is saved in host controller mode
USBVAL
WVALUE[15:0]
Value is saved in host controller mode
USBINDX
WINDEX[15:0]
Value is saved in host controller mode
USBLENG
WLENTUH[15:0]
Value is saved in host controller mode
DVSTCTR0
RHST[2:0]
-
FRMNUM
FRNM[10:0]
Value is saved in device controller mode
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31. USB 2.0 Full-Speed Module (USBFS)
DPRPU bit (D+ Line Resistor Control)
The DPRPU bit enables or disables pulling up the D+ line in device controller mode.
When the DPRPU bit is set to 1 in device controller mode, the USBFS pulls up the D+ line to notify the USB host that it
attached. Changing the DPRPU bit from 1 to 0 releases the pull-up, thereby notifying the USB host that it detached.
Set this bit to 1 in device controller mode and to 0 in host controller mode.
DRPD bit (D+/D- Line Resistor Control)
The DRPD bit enables or disables pulling down D+ and D- lines in host controller mode.
Set this bit to 1 in host controller mode and to 0 in device controller mode.
DCFM bit (Controller Function Select)
The DCFM bit selects the host or device function of the USBFS.
Only change this bit when the DPRPU and DRPD bits are both 0.
SCKE bit (USB Clock Enable)
The SCKE bit stops or enables the 48-MHz clock supply to the USBFS.
When this bit is 0, only SYSCFG is permitted to be read from and written to. The other registers related to the USB
should not be read from or written to.
31.2.2
System Configuration Status Register 0 (SYSSTS0)
Address(es): USBFS.SYSSTS0 4009 0004h
b15
b14
OVCMON[1:0]
0*1
Value after reset:
0*1
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
—
—
0
0
0
0
0
0
0
b6
b5
HTACT SOFEA
0
0
b4
b3
b2
—
—
IDMON
0
0
0*1
b1
b0
LNST[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
LNST[1:0]
USB Data Line Status Monitor
Indicates the status of the USB data lines. See Table 31.4
R
b2
IDMON
External ID0 Input Pin Monitor
0: USB_ID pin is low
1: USB_ID pin is high.
R
b4, b3
—
Reserved
These bits are read as 0 and cannot be modified
R
b5
SOFEA
Active Monitor When the Host
Controller Is Selected
0: SOF output stopped
1: SOF output operating.
R
b6
HTACT
USB Host Sequencer Status
Monitor
0: Host sequencer completely stopped
1: Host sequencer not completely stopped.
R
b13 to b7
—
Reserved
These bits are read as 0 and cannot be changed
R
b15, b14
OVCMON[1:0] External USB_OVRCURA/
USB_OVRCURB Input Pin
Monitor
OVCMON[1] indicates the USB_OVRCURA pin status.
OVCMON[0] indicates the USB_OVRCURB pin status.
R
Note 1.
Depends on the status of the USB_OVRCURA, USB_OVRCURB, and USB_ID pins.
LNST[1:0] bits (USB Data Line Status Monitor)
The LNST[1:0] bits indicate the state of the USB data lines, D+ and D-. For details, see Table 31.4.
In device controller mode, read the LNST[1:0] bits after connection processing (SYSCFG.DPRPU bit = 1). In host
controller mode, read them after enabling the pull-down of the lines (SYSCFG.DRPD bit = 1).
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Table 31.4
31. USB 2.0 Full-Speed Module (USBFS)
Status of the USB data bus lines (D+ and D-)
LNST[1:0] bits
During full-speed operation
During low-speed operation
00b
SE0
SE0
01b
J-State
K-State
10b
K-State
J-State
11b
SE1
SE1
SOFEA bit (Active Monitor When the Host Controller Is Selected)
The SOFEA bit is used in host controller mode to check whether the output of the last SOF is complete when the USBFS
is suspended because of a 0 setting in the DVSTCTR0.UACT bit.
In host controller mode, check that both the HTACT and SOFEA bits are 0 before setting the SYSCFG.USBE bit to 0 to
stop the USBFS, or before setting the SYSCFG.SCKE bit to 0 to stop the clock signal supply during communication.
HTACT bit (USB Host Sequencer Status Monitor)
The HTACT bit is set to 0 when the host sequencer of the USBFS is completely stopped.
In host controller mode, check that the HTACT bit is 0 before setting the DVSTCTR0.UACT bit to 0 to place the USBFS
in a suspended state, or before setting the SCKE bit to 0 to stop the clock signal supply during communication.
OVCMON[1:0] bits (External USB_OVRCURA/ USB_OVRCURB Input Pin Monitor)
The OVCMON[1:0] bits indicate the status of the overcurrent signals from an external power supply IC.
31.2.3
Device State Control Register 0 (DVSTCTR0)
Address(es): USBFS.DVSTCTR0 4009 0008h
Value after reset:
b15
b14
b13
b12
—
—
—
—
0
0
0
0
b11
b10
b9
b8
b7
b6
b5
HNPBT EXICE VBUSE WKUP RWUP USBRS RESU
OA
N
N
E
T
ME
0
0
0
0
0
0
0
b4
b3
UACT
—
0
0
b2
b1
b0
RHST[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
RHST[2:0]
USB Bus Reset Status
In host controller mode:
R
b2
b0
0 0 0:Communication speed indeterminate
(powered state or no connection)
1 x x:USB bus reset in progress
0 0 1:Low-speed connection
0 1 0:Full-speed connection.
In device controller mode:
b2
b0
0 0 0: Communication speed indeterminate
0 0 1: USB bus reset in progress
0 1 0: USB bus reset in progress or full-speed connection.
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
UACT
USB Bus Enable
0: Disable downstream port (disable SOF transmission)
1: Enable downstream port (enable SOF transmission).
R/W
b5
RESUME
Resume Output
0: Do not output resume signal
1: Output resume signal.
R/W
b6
USBRST
USB Bus Reset Output
0: Do not output USB bus reset signal
1: Output USB bus reset signal.
R/W
b7
RWUPE
Wakeup Detection Enable
0: Disable downstream port remote wakeup
1: Enable downstream port remote wakeup.
R/W
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31. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b8
WKUP
Wakeup Output
0: Do not output remote wakeup signal
1: Output remote wakeup signal.
R/W
b9
VBUSEN
USB_VBUSEN Output Pin Control
0: Output low on external USB_VBUSEN pin
1: Output high on external USB_VBUSEN pin.
R/W
b10
EXICEN
USB_EXICEN Output Pin Control
0: Output low on external USB_EXICEN pin
1: Output high on external USB_EXICEN pin.
R/W
b11
HNPBTOA
Host Negotiation Protocol (HNP)
Control
Use this bit when switching from device B to device A in
OTG mode. If the HNPBTOA bit is 1, the internal function
control remains in the suspended state until the HNP
processing ends even if SYSCFG.DPRPU = 0 or
SYSCFG.DCFM = 1.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b12 —
x: Don’t care
The USBFS controller does not support low-speed connections in device controller mode. When this value is read,
abnormal connection processing must be executed in higher level application software.
RHST[2:0] bits (USB Bus Reset Status)
The RHST[2:0] bits indicate the status of the USB bus reset.
In host controller mode, writing 1 to the USBRST bit causes the RHST[2:0] bits to set to 100b. When 0 is written to the
USBRST bit and the USBFS ends the SE0 state, the RHST[2:0] bits update to a new value.
In device controller mode, if the USBFS detects a USB bus reset, the RHST[2:0] bits indicate 010b if the DPRPU bit is
1, and a DVST interrupt is generated.
UACT bit (USB Bus Enable)
When set to 1 in host controller mode, the UACT bit enables USB bus operation by controlling SOF packet transmission
to the USB bus in addition to data and reception. The USBFS starts SOF packet output within one frame period after the
UACT bit is set to 1. When UACT is set to 0, the USBFS enters the idle state after the SOF packet output.
The USBFS sets the UACT bit to 0 on any of the following conditions:
A DTCH interrupt is detected during communication (when UACT = 1)
An EOFERR interrupt is detected during communication (when UACT = 1).
Always write 1 to the UACT bit at the end of the USB bus reset processing (writing 0 to the USBRST bit) or at the end
of resume processing from the suspended state (writing 0 to the RESUME bit).
In device controller mode, always set this bit to 0.
RESUME bit (Resume Output)
The RESUME bit controls the resume signal output in host controller mode.
When this bit is set to 1, the USBFS drives the USB port to the K-state and outputs the resume signal. The USBFS sets
the bit to 1 on the detection of a remote wakeup signal while the RWUPE bit is 1, and in the USB suspend state.
The USBFS continues outputting the K-state while the RESUME bit is 1, until the bit is set to 0 by software. The
RESUME bit must be 1 (resume period) for the time defined in the USB 2.0 specification. Only set this bit to 1 while the
interface is in the suspended state. Write 1 to the UACT bit simultaneously with the end of the resume processing
(writing 0 to the RESUME bit).
Always set this bit to 0 in device controller mode.
USBRST bit (USB Bus Reset Output)
The USBRST bit controls the output of the USB bus signal in host controller mode. When this bit is set to 1, the USBFS
drives the USB port to the SE0 state to reset the USB bus. The USBFS continues outputting SE0 while the USBRST bit
is 1, until the bit is cleared to 0 by software. The USBRST bit must be 1 (USB bus reset period) for the time defined in
the USB 2.0 specification. Writing 1 to the USBRST bit during communication (UACT bit = 1) or during resume
processing (RESUME bit = 1) prevents the USBFS from starting the USB bus reset processing until both the UACT and
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31. USB 2.0 Full-Speed Module (USBFS)
RESUME bits become 0. Write 1 to the UACT bit simultaneously with the end of the USB bus reset processing (writing
0 to the USBRST bit).
Always set this bit to 0 in device controller mode.
RWUPE bit (Wakeup Detection Enable)
The RWUPE bit enables or disables remote wakeup signals (resume signals) from downstream peripheral devices in host
controller mode. When this bit is set to 1, the USBFS detects a remote wakeup signal (K-state for 2.5 μs) from a
downstream peripheral device, and performs resume processing, driving the K-state.
When this bit is set to 0, the USBFS ignores remote wakeup signals (K-states) from peripheral devices connected to the
USB port. Do not stop the internal clock when the RWUPE bit is 1, even in the suspended state (SYSCFG.SCKE bit must
be set to 1).
Always set this bit to 0 in device controller mode.
WKUP bit (Wakeup Output)
The WKUP bit enables or disables remote wakeup signals (resume signals) to the USB bus in device controller mode.
The USBFS controls the output timing of the remote wakeup signals. When this bit is set to 1, the USBFS clears it to 0
after outputting the K-state for 10 ms. The USB 2.0 specification specifies that the USB bus idle state must be kept for
5 ms or longer before a remote wakeup signal is sent. If the USBFS writes 1 to the WKUP bit immediately after
detecting the suspended state, the K-state is output after 2 ms.
Only write 1 to the WKUP bit when the device is in the suspended state (INTSTS0.DVSQ[2:0] bits = 1xxb) and the USB
host enables the remote wakeup signal (RWUPE = 1). Do not stop the internal clock while this bit is 1, even in the
suspended state (SYSCFG.SCKE bit must be set to 1).
Always set this bit to 0 in host controller mode.
HNPBTOA bit (Host Negotiation Protocol (HNP) Control)
The HNPBTOA bit is used when switching from device B to device A while in OTG mode.
If the HNPBTOA bit is 1, the internal function control maintains the suspended state until HNP processing ends, even if
the SYSCFG.DPRPU bit is set to 0 or the SYSCFG.DCFM bit is set to 1. Resume (RESM) interrupts are not generated
even if a falling edge of D+ is detected.
The HNP processing ends when a host attach event is detected, because of a pull-up by the initiating party, or the
HNPBTOA bit is set to 0 by software because the HNP processing times out.
31.2.4
CFIFO Port Register (CFIFO/CFIFOL)
D0FIFO Port Register (D0FIFO/D0FIFOL)
D1FIFO Port Register (D1FIFO/D1FIFOL)
(1) When the MBW bit is 1
Address(es): USBFS.CFIFO 4009 0014h, USBFS.D0FIFO 4009 0018h, USBFS.D1FIFO 4009 001Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
FIFOPORT[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
(2) When the MBW bit is 0
Address(es): USBFS.CFIFOL 4009 0014h, USBFS.D0FIFOL 4009 0018h, USBFS.D1FIFOL 4009 001Ch
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
FIFOPORT[7:0]
Value after reset:
0
0
0
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31. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b15 to b0
FIFOPORT[15:0]*1
FIFO Port
Read receive data from the FIFO buffer or write transmit data to
the FIFO buffer by accessing these bits
R/W
Note 1.
The valid bits depend on the MBW settings (CFIFOSEL.MBW, D0FIFOSEL.MBW, and D1FIFOSEL.MBW) and BIGEND
settings (CFIFOSEL.BIGEND, D0FIFOSEL.BIGEND, and D1FIFOSEL.BIGEND) in the associated port select register. See
Table 31.5 and Table 31.6.
Three FIFO ports are available:
CFIFO
D0FIFO
D1FIFO.
Each FIFO port is configured with:
A port register (CFIFO, D0FIFO, or D1FIFO) that handles reading of data from the FIFO buffer and writing of data
to the FIFO buffer
A port select register (CFIFOSEL, D0FIFOSEL, or D1FIFOSEL) that selects the pipe assigned to the FIFO port
A port control register (CFIFOCTR, D0FIFOCTR, or D1FIFOCTR).
Each FIFO port has the following constraints:
Access to the FIFO buffer for DCP control transfers is through the CFIFO port
Access to the FIFO buffer for DMA or DTC transfers is through the D0FIO or D1FIFO port
The D0FIFO and D1FIFO ports can also be accessed by the CPU
When using functions specific to the FIFO port, such as the DMA or DTC transfer function, you cannot change the
pipe number selected in the CURPIPE[3:0] bits of the port select register
Registers configuring a FIFO port do not affect other FIFO ports
The same pipe must not be assigned to two or more FIFO ports
There are two FIFO buffer states, one giving access rights to the CPU and the other to the serial interface engine
(SIE). When the SIE has access rights, the FIFO buffer cannot be accessed by the CPU.
FIFOPORT[15:0] bits (FIFO Port)
When the FIFOPORT bit is accessed, the USBFS reads the received data from the FIFO buffer or writes the transmit data
to the FIFO buffer. The FIFO port register can be accessed only when the FRDY bit in the associated port control register
(CFIFOCTR, D0FIFOCTR, or D1FIFOCTR) is 1.
The valid bits in the FIFO port register depend on the MBW and BIGEND settings in the port select register
(CFIFOSEL, D0FIFOSEL, or D1FIFOSEL). See Table 31.5 and Table 31.6.
Table 31.5
Endian operation in 16-bit access
CFIFOSEL.BIGEND bit
D0FIFOSEL.BIGEND bit
D1FIFOSEL.BIGEND bit
Bits [15:8]
Bits [7:0]
0
N + 1 data
N + 0 data
1
N + 0 data
N + 1 data
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Table 31.6
31. USB 2.0 Full-Speed Module (USBFS)
Endian operation in 8-bit access
CFIFOSEL.BIGEND bit
D0FIFOSEL.BIGEND bit
D1FIFOSEL.BIGEND bit
Bits [15:8]
0
1
Note 1.
Bits [7:0]
Access
prohibited*1
N + 0 data
Access
prohibited*1
N + 0 data
Writing to or reading from an access-prohibited area is not allowed.
31.2.5
CFIFO Port Select Register (CFIFOSEL)
D0FIFO Port Select Register (D0FIFOSEL)
D1FIFO Port Select Register (D1FIFOSEL)
CFIFOSEL
Address(es): USBFS.CFIFOSEL 4009 0020h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
RCNT
REW
—
—
—
MBW
—
BIGEN
D
—
—
ISEL
—
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
b3
b2
b1
b0
CURPIPE[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
CURPIPE
[3:0]
CFIFO Port Access Pipe Specification
b3
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
ISEL
CFIFO Port Access Direction When
DCP Is Selected
0: Select reading from the FIFO buffer
1: Select writing to the FIFO buffer.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
BIGEND
CFIFO Port Endian Control
0: Little endian
1: Big endian.
R/W
b9
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10
MBW
CFIFO Port Access Bit Width
0: 8-bit width
1: 16-bit width.
R/W
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
REW
Buffer Pointer Rewind
0: Do not rewind buffer pointer
1: Rewind buffer pointer.
W*1
b15
RCNT
Read Count Mode
0: The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0],
D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) are
cleared when all receive data is read from the CFIFO.
In double buffer mode, the DTLN[8:0] value is cleared
when all data is read from only a single plane.
1: The DTLN[8:0] bits are decremented each time the
receive data is read from the CFIFO.
R/W
Note 1.
b0
0 0 0 0: DCP (default control pipe)
0 0 0 1: Pipe 1
0 0 1 0: Pipe 2
0 0 1 1: Pipe 3
0 1 0 0: Pipe 4
0 1 0 1: Pipe 5
0 1 1 0: Pipe 6
0 1 1 1: Pipe 7
1 0 0 0: Pipe 8
1 0 0 1: Pipe 9.
Other settings are prohibited.
Only 0 can be read.
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31. USB 2.0 Full-Speed Module (USBFS)
Do not specify the same pipe number that is in the CURPIPE[3:0] bits, also in the CFIFOSEL, D0FIFOSEL, and
D1FIFOSEL registers. When the CURPIPE[3:0] bits in the D0FIFOSEL and D1FIFOSEL registers are set to 0000b, no
pipe is selected.
Do not change the pipe number while DMA or DTC transfer is enabled.
CURPIPE[3:0] bits (CFIFO Port Access Pipe Specification)
The CURPIPE[3:0] bits specify the pipe number to use for reading or writing data through the CFIFO port. After writing
to these bits, read them to check that the written value agrees with the read value before proceeding to the next process.
Do not set the same pipe number to the CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL.
During FIFO buffer access, the current access setting is maintained until the access is complete, even if software attempts
to change the CURPIPE[3:0] setting.
ISEL bit (CFIFO Port Access Direction When DCP Is Selected)
After writing a new value to the ISEL bit with DCP as the selected pipe, read the ISEL bit to check that the written value
agrees with the read value before proceeding to the next process. Set the ISEL and CURPIPE[3:0] bits simultaneously.
MBW bit (CFIFO Port Access Bit Width)
The MBW bit specifies the bit width for accessing the CFIFO port.
When the selected pipe is receiving, set the CURPIPE[3:0] and MBW bits simultaneously. After a write to these bits
starts a data read from the FIFO buffer, do not change the bits until all of the data is read. When reading the FIFO buffer,
read with the access size that is set in MBW.
When the selected pipe is transmitting, the bit width cannot be changed from 8-bit to 16-bit while data is being written to
the FIFO buffer.
An odd number of bytes can also be written through byte-access control even when 16-bit width is selected.
REW bit (Buffer Pointer Rewind)
The REW bit specifies whether to rewind the buffer pointer.
When the selected pipe is receiving, setting this bit to 1 while the FIFO buffer is being read allows re-reading of the FIFO
buffer from the first data. In double buffering, this setting enables re-reading of the currently-read FIFO buffer plane
from the first entry.
Do not set this bit to 1 while simultaneously changing the CURPIPE[3:0] bits. Before setting the REW bit to 1, be sure to
check that the FRDY bit is 1.
To rewrite to the FIFO buffer from the first data unit for the transmitting pipe, use the BCLR bit.
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31. USB 2.0 Full-Speed Module (USBFS)
D0FIFOSEL, D1FIFOSEL
Address(es): USBFS.D0FIFOSEL 4009 0028h, USBFS.D1FIFOSEL 4009 002Ch
b15
RCNT
Value after reset:
0
b14
b13
b12
REW DCLRM DREQE
0
0
0
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
0
0
0
0
—
MBW
—
BIGEN
D
0
0
0
0
b3
b2
b1
b0
CURPIPE[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
CURPIPE
[3:0]
FIFO Port Access Pipe
Specification
b3
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
BIGEND
FIFO Port Endian Control
0: Little endian
1: Big endian.
R/W
b9
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10
MBW
FIFO Port Access Bit Width
0: 8-bit width
1: 16-bit width.
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b12
DREQE
DMA/DTC Transfer Request
Enable
0: Disable DMA/DTC transfer request
1: Enable DMA/DTC transfer request.
R/W
b13
DCLRM
Auto Buffer Memory Clear
Mode Accessed after
Specified Pipe Data is Read
0: Disable auto buffer clear mode
1: Enable auto buffer clear mode.
R/W
b14
REW
Buffer Pointer Rewind
0: Do not rewind buffer pointer
1: Rewind buffer pointer.
R/W*1
b15
RCNT
Read Count Mode
0: Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0],
D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) when all
receive data is read from DnFIFO (after the read of a single plane
in double buffer mode)
1: Decrement DTLN[8:0] bits each time receive data is read from
DnFIFO.
n = 0, 1.
R/W
Note 1.
b0
0 0 0 0: No pipe specification
0 0 0 1: Pipe 1
0 0 1 0: Pipe 2
0 0 1 1: Pipe 3
0 1 0 0: Pipe 4
0 1 0 1: Pipe 5
0 1 1 0: Pipe 6
0 1 1 1: Pipe 7
1 0 0 0: Pipe 8
1 0 0 1: Pipe 9.
Other settings are prohibited.
Only 0 can be read.
The same pipe must not be specified in the CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers.
When the CURPIPE[3:0] bits in D0FIFOSEL and D1FIFOSEL registers are set to 0000b, no pipe is selected. The pipe
number must not be changed while DMA or DTC transfer is enabled.
CURPIPE[3:0] bits (FIFO Port Access Pipe Specification)
The CURPIPE[3:0] bits specify the pipe number to use for reading or writing data through the DnFIFO port. After
writing to these bits, read them to check that the written value agrees with the read value before proceeding to the next
process. Do not set the same pipe number to the CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL.
During FIFO buffer access, the current access setting is maintained until the access is complete, even if software attempts
to change the CURPIPE[3:0] setting.
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31. USB 2.0 Full-Speed Module (USBFS)
MBW bit (FIFO Port Access Bit Width)
The MBW bit specifies the bit width for accessing the DnFIFO port.
When the selected pipe is receiving, after a write to these bits starts a data read from the FIFO buffer, do not change the
bits until all of the data is read. Set the CURPIPE[3:0] and MBW bits simultaneously. When reading the FIFO buffer,
read using the access size that is set in MBW.
When the selected pipe is transmitting, the bit width cannot be changed from 8-bit to 16-bit while data is being written to
the FIFO buffer.
An odd number of bytes can also be written through byte-access control even when 16-bit width is selected.
DREQE bit (DMA/DTC Transfer Request Enable)
The DREQE bit enables or disables the issuing of DMA or DTC transfer requests. To enable DMA or DTC transfer
requests, set this bit to 1 after setting the CURPIPE[3:0] bits. To change the CURPIPE[3:0] setting, first set this bit to 0.
DCLRM bit (Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read)
The DCLRM bit enables or disables automatic FIFO buffer clearing after the data in the selected pipe is read.
When this bit is set to 1, on receiving a zero-length packet while the FIFO buffer assigned to the selected pipe is empty,
or when reading of a received short packet is complete while the PIPECFG.BFRE bit is 1, the USBFS sets the BCLR bit
in the FIFO Port Control Register to 1.
When using the USBFS with the SOFCFG.BRDYM bit set to 1, set this bit to 0.
REW bit (Buffer Pointer Rewind)
The REW bit specifies whether to rewind the buffer pointer.
When the selected pipe is receiving, setting this bit to 1 while the FIFO buffer is being read allows re-reading of the FIFO
buffer from the first data. In double buffering, this setting enables re-reading of the currently-read FIFO buffer plane
from the first entry.
Do not set this bit to 1 while simultaneously changing the CURPIPE[3:0] bits. Before setting the bit to 1, be sure to check
that the FRDY bit is 1.
To rewrite to the FIFO buffer from the first data for the transmitting pipe, use the BCLR bit.
RCNT bit (Read Count Mode)
The RCNT bit specifies the read mode for the value in the CFIFOCTR.DTLN bit. When accessing DnFIFO with the
PIPECFG.BFRE bit set to 1, set the RCNT bit to 0.
31.2.6
CFIFO Port Control Register (CFIFOCTR)
D0FIFO Port Control Register (D0FIFOCTR)
D1FIFO Port Control Register (D1FIFOCTR)
Address(es): USBFS.CFIFOCTR 4009 0022h, USBFS.D0FIFOCTR 4009 002Ah, USBFS.D1FIFOCTR 4009 002Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
BVAL
BCLR
FRDY
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
DTLN[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
DTLN[8:0]
Receive Data Length
Indicates the receive data length.
The meaning of the values differs depending on the RCNT bit setting
in the port select register. For details, see the description of the
DTLN[8:0] bits.
R
b12 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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Bit
Symbol
Bit name
Description
R/W
b13
FRDY
FIFO Port Ready
0: FIFO port access disabled
1: FIFO port access enabled.
R
b14
BCLR
CPU Buffer Clear
0: No operation
1: Clear FIFO buffer on the CPU side.
R/W*1
b15
BVAL
Buffer Memory Valid Flag
0: Invalid (writing 0 has no effect)
1: Writing ended.
R/W
Note 1.
Only 0 can be read.
CFIFOCTR, D0FIFOCTR, and D1FIFOCTR registers correspond to the CFIFO, D0FIFO, and D1FIFO buffers.
DTLN[8:0] bits (Receive Data Length)
The DTLN[8:0] bits indicate the length of the receive data.
While the FIFO buffer is being read, the DTLN[8:0] bits indicate different values depending on the DnFIFOSEL.RCNT
bit (n = 0, 1), as follows:
RCNT = 0
The USBFS sets the DTLN[8:0] bits to indicate the length of the receive data until the CPU or DMA/DTC has read
all of the received data from a single FIFO buffer plane.
While the PIPECFG.BFRE bit = 1, the USBFS retains the length of the receive data until the BCLR bit is set to 1,
even after all the data is read.
RCNT = 1
The USBFS decrements the value indicated in the DTLN[8:0] bits each time data is read from the FIFO buffer. The
value is decremented by 1 when MBW = 0, and by 2 when MBW = 1.
The USBFS sets these bits to 0 when all the data is read from one FIFO buffer plane. In double buffer mode, if data
is received in one FIFO buffer plane before all of the data is read from the other plane, the USBFS sets these bits to
indicate the length of the receive data in the former plane when all of the data is read from the latter plane.
FRDY bit (FIFO Port Ready)
The FRDY bit indicates whether the FIFO port can be accessed by the CPU or DMA/DTC.
In the following cases, the USBFS sets the FRDY bit to 1 but data cannot be read through the FIFO port because there is
no data to be read:
A zero-length packet is received when the FIFO buffer assigned to the selected pipe is empty
A short packet is received and the data is completely read while the PIPECFG.BFRE bit = 1.
In these cases, set the BCLR bit to 1 to clear the FIFO buffer, and enable transmission and reception of the next data.
BCLR bit (CPU Buffer Clear)
Set the BCLR bit to 1 to clear the FIFO buffer on the CPU side for the selected pipe.
When double buffer mode is set for the FIFO buffer assigned to the selected pipe, the USBFS clears only one plane of the
FIFO buffer even when both planes are read-enabled.
When the DCP is the selected pipe, setting the BCLR bit to 1 allows the USBFS to clear the FIFO buffer regardless of
whether the CPU or SIE has access rights. To clear the buffer when the SIE has access rights, set the DCPCTR.PID[1:0]
bits to 00b (NAK response) before setting the BCLR bit to 1.
When the selected pipe is transmitting, if 1 is written to the BVAL flag and the BCLR bit simultaneously, the USBFS
clears the data that is already written, enabling the transmission of a zero-length packet.
When the selected pipe is not the DCP, only write 1 to the BCLR bit while the FRDY bit in the FIFO Port Control
Register is 1 (set by the USBFS).
BVAL flag (Buffer Memory Valid Flag)
Set the BVAL flag to 1 when data is completely written to the FIFO buffer on the CPU side for the pipe selected in
CURPIPE[3:0].
When the selected pipe is transmitting, set this flag to 1 in the following cases:
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To transmit a short packet, set this flag to 1 after data is written
To transmit a zero-length packet, set this flag to 1 before data is written to the FIFO buffer.
The USBFS then switches the FIFO buffer from the CPU to the SIE, enabling transmission.
When data of the maximum packet size is written for the pipe in continuous transfer mode, the USBFS sets the BVAL
flag to 1 and switches the FIFO buffer from the CPU to the SIE, enabling transmission.
Only write 1 to the BVAL flag while the FRDY bit is 1 (set by the USBFS). When the selected pipe is receiving, do not
set the BVAL flag to 1.
31.2.7
Interrupt Enable Register 0 (INTENB0)
Address(es): USBFS.INTENB0 4009 0030h
b15
b14
b13
b12
VBSE
RSME
SOFE
DVSE
0
0
0
0
Value after reset:
b11
b10
b9
b8
CTRE BEMPE NRDYE BRDYE
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
These bits are read as 0. The write value
should be 0.
R/W
b8
BRDYE
Buffer Ready Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b9
NRDYE
Buffer Not Ready Response Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b10
BEMPE
Buffer Empty Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b11
CTRE
Control Transfer Stage Transition Interrupt
Enable*1
0: Disable interrupt request
1: Enable interrupt request.
R/W
b12
DVSE
Device State Transition Interrupt Enable*1
0: Disable interrupt request
1: Enable interrupt request.
R/W
b13
SOFE
Frame Number Update Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b14
RSME
Resume Interrupt Enable*1
0: Disable interrupt request
1: Enable interrupt request.
R/W
b15
VBSE
VBUS Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
Note 1.
The RSME, DVSE, and CTRE bits can only be set to 1 in device controller mode. Do not set these bits to 1 in host controller
mode.
When a status flag in the INTSTS0 register is set to 1 and the associated interrupt request enable bit setting in the
INTENB0 register is 1, the USBFS issues a USBFS interrupt request.
Regardless of the INTENB0 register setting, the status flag in the INTSTS0 register is set to 1 in response to a state
change that satisfies the associated condition.
When an interrupt request enable bit in the INTENB0 register is switched from 0 to 1 while the associated status flag in
the INTSTS0 register is set to 1, a USBFS interrupt is requested.
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31.2.8
31. USB 2.0 Full-Speed Module (USBFS)
Interrupt Enable Register 1 (INTENB1)
Address(es): USBFS.INTENB1 4009 0032h
b15
b14
OVRC BCHGE
RE
0
Value after reset:
0
b13
—
b12
b11
DTCHE ATTCH
E
0
0
0
b10
b9
b8
b7
—
—
—
—
0
0
0
0
b6
b5
b4
EOFER SIGNE SACKE
RE
0
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
SACKE
Setup Transaction Normal Response
Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b5
SIGNE
Setup Transaction Error Interrupt
Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b6
EOFERRE
EOF Error Detection Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b10 to b7
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b11
ATTCHE
Connection Detection Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b12
DTCHE
Disconnection Detection Interrupt
Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b13
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b14
BCHGE
USB Bus Change Interrupt Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
b15
OVRCRE
Overcurrent Input Change Interrupt
Enable
0: Disable interrupt request
1: Enable interrupt request.
R/W
Note:
R/W
The bits in INTENB1 can only be set to 1 in host controller mode. Do not set these bits to 1 in device controller mode.
INTENB1 specifies the interrupt masks in host controller mode and for the setup transaction.
When a status flag in the INTSTS1 register sets to 1 and the associated interrupt request enable bit setting in the
INTENB1 register is 1, the USBFS issues a USBFS interrupt request.
Regardless of the INTENB1 register setting, the status flag in the INTSTS1 register sets to 1 in response to a state change
that satisfies the associated condition.
When an interrupt request enable bit in the INTENB1 register is switched from 0 to 1 while the associated status flag in
the INTSTS1 register sets to 1, a USBFS interrupt is requested.
Do not enable interrupts in device controller mode.
31.2.9
BRDY Interrupt Enable Register (BRDYENB)
Address(es): USBFS.BRDYENB 4009 0036h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B
RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BRDYE
BRDY Interrupt Enable for Pipe 0
0: Disable interrupt request
1: Enable interrupt request.
R/W
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31. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b1
PIPE1BRDYE
BRDY Interrupt Enable for Pipe 1
0: Disable interrupt request
1: Enable interrupt request.
R/W
b2
PIPE2BRDYE
BRDY Interrupt Enable for Pipe 2
0: Disable interrupt request
1: Enable interrupt request.
R/W
b3
PIPE3BRDYE
BRDY Interrupt Enable for Pipe 3
0: Disable interrupt request
1: Enable interrupt request.
R/W
b4
PIPE4BRDYE
BRDY Interrupt Enable for Pipe 4
0: Disable interrupt request
1: Enable interrupt request.
R/W
b5
PIPE5BRDYE
BRDY Interrupt Enable for Pipe 5
0: Disable interrupt request
1: Enable interrupt request.
R/W
b6
PIPE6BRDYE
BRDY Interrupt Enable for Pipe 6
0: Disable interrupt request
1: Enable interrupt request.
R/W
b7
PIPE7BRDYE
BRDY Interrupt Enable for Pipe 7
0: Disable interrupt request
1: Enable interrupt request.
R/W
b8
PIPE8BRDYE
BRDY Interrupt Enable for Pipe 8
0: Disable interrupt request
1: Enable interrupt request.
R/W
b9
PIPE9BRDYE
BRDY Interrupt Enable for Pipe 9
0: Disable interrupt request
1: Enable interrupt request.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
The BRDYENB register enables or disables the INTSTS0.BRDY bit to be set to 1 when a BRDY interrupt is detected for
each pipe.
When a status flag in the BRDYSTS register sets to 1 and the associated PIPEnBRDYE bit (n = 0 to 9) setting in the
BRDYENB register is 1, the INTSTS0.BRDY flag sets to 1. In this case, if the BRDYE bit in INTENB0 is 1, the USBFS
generates a BRDY interrupt request. While at least one PIPEnBRDY bit indicates 1, the USB generates the BRDY
interrupt request when the associated interrupt request enable bit in the BRDYENB register is changed from 0 to 1 by
software.
31.2.10
NRDY Interrupt Enable Register (NRDYENB)
Address(es): USBFS.NRDYENB 4009 0038h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9N PIPE8N PIPE7N PIPE6N PIPE5N PIPE4N PIPE3N PIPE2N PIPE1N PIPE0N
RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0NRDYE
NRDY Interrupt Enable for Pipe 0
0: Disable interrupt request
1: Enable interrupt request.
R/W
b1
PIPE1NRDYE
NRDY Interrupt Enable for Pipe 1
0: Disable interrupt request
1: Enable interrupt request.
R/W
b2
PIPE2NRDYE
NRDY Interrupt Enable for Pipe 2
0: Disable interrupt request
1: Enable interrupt request.
R/W
b3
PIPE3NRDYE
NRDY Interrupt Enable for Pipe 3
0: Disable interrupt request
1: Enable interrupt request.
R/W
b4
PIPE4NRDYE
NRDY Interrupt Enable for Pipe 4
0: Disable interrupt request
1: Enable interrupt request.
R/W
b5
PIPE5NRDYE
NRDY Interrupt Enable for Pipe 5
0: Disable interrupt request
1: Enable interrupt request.
R/W
b6
PIPE6NRDYE
NRDY Interrupt Enable for Pipe 6
0: Disable interrupt request
1: Enable interrupt request.
R/W
b7
PIPE7NRDYE
NRDY Interrupt Enable for Pipe 7
0: Disable interrupt request
1: Enable interrupt request.
R/W
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31. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b8
PIPE8NRDYE
NRDY Interrupt Enable for Pipe 8
0: Disable interrupt request
1: Enable interrupt request.
R/W
b9
PIPE9NRDYE
NRDY Interrupt Enable for Pipe 9
0: Disable interrupt request
1: Enable interrupt request.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
The NRDYENB register enables or disables the INTSTS0.NRDY bit to be set to 1 when a NRDY interrupt is detected
for each pipe.
When a status flag in the NRDYSTS register sets to 1 and the associated PIPEnNRDYE (n = 0 to 9) bit setting in the
NRDYENB register is 1, the INTSTS0.NRDY flag sets to 1. In this case, if the NRDYE bit in INTENB0 is 1, the USBFS
generates a NRDY interrupt request. While at least one PIPEnNRDY bit indicates 1, the USBFS generates the NRDY
interrupt request when the associated interrupt request enable bit in the NRDYENB register is changed from 0 to 1 by
software.
31.2.11
BEMP Interrupt Enable Register (BEMPENB)
Address(es): USBFS.BEMPENB 4009 003Ah
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B
EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BEMPE
BEMP Interrupt Enable for Pipe 0
0: Disable interrupt request
1: Enable interrupt request.
R/W
b1
PIPE1BEMPE
BEMP Interrupt Enable for Pipe 1
0: Disable interrupt request
1: Enable interrupt request.
R/W
b2
PIPE2BEMPE
BEMP Interrupt Enable for Pipe 2
0: Disable interrupt request
1: Enable interrupt request.
R/W
b3
PIPE3BEMPE
BEMP Interrupt Enable for Pipe 3
0: Disable interrupt request
1: Enable interrupt request.
R/W
b4
PIPE4BEMPE
BEMP Interrupt Enable for Pipe 4
0: Disable interrupt request
1: Enable interrupt request.
R/W
b5
PIPE5BEMPE
BEMP Interrupt Enable for Pipe 5
0: Disable interrupt request
1: Enable interrupt request.
R/W
b6
PIPE6BEMPE
BEMP Interrupt Enable for Pipe 6
0: Disable interrupt request
1: Enable interrupt request.
R/W
b7
PIPE7BEMPE
BEMP Interrupt Enable for Pipe 7
0: Disable interrupt request
1: Enable interrupt request.
R/W
b8
PIPE8BEMPE
BEMP Interrupt Enable for Pipe 8
0: Disable interrupt request
1: Enable interrupt request.
R/W
b9
PIPE9BEMPE
BEMP Interrupt Enable for Pipe 9
0: Disable interrupt request
1: Enable interrupt request.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
The BEMPENB register enables or disables the INTSTS0.BEMP bit to be set to 1 when a BEMP interrupt is detected for
each pipe.
When a status flag in the BEMPSTS register is set to 1 and the associated PIPEnBEMPE (n = 0 to 9) bit setting in the
BEMPENB register is 1, the INTSTS0.BEMP flag sets to 1. In this case, if the BEMPE bit in INTENB0 is 1, the USBFS
generates a BEMP interrupt request. While at least one PIPEnBEMP bit indicates 1, the USBFS generates the BEMP
interrupt request when the associated interrupt request enable bit in the BEMPENB register is changed from 0 to 1 by
software.
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31.2.12
31. USB 2.0 Full-Speed Module (USBFS)
SOF Output Configuration Register (SOFCFG)
Address(es): USBFS.SOFCFG 4009 003Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
TRNEN
SEL
—
BRDY
M
—
EDGES
TS
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
EDGESTS
Edge Interrupt Output Status Monitor*1
Indicates 1 during the edge processing of an edge
interrupt output signal
R
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
BRDYM
BRDY Interrupt Status Clear Timing
0: Clear BRDY flag by software
1: Clear BRDY flag by the USBFS through a data read
from the FIFO buffer or data write to the FIFO buffer.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b8
TRNENSEL
Transaction-Enabled Time Select*1
0: Not low-speed communication
1: Low-speed communication.
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
R/W
Confirm that these bits are 0 before stopping the clock supply to the USBFS.
EDGESTS bit (Edge Interrupt Output Status Monitor)
The EDGESTS bit indicates 1 during the edge processing of an edge interrupt output signal. Confirm that this bit is 0
before stopping the clock supply to the USBFS.
BRDYM bit (BRDY Interrupt Status Clear Timing)
The BRDYM bit specifies how the BRDY interrupt status flags for the pipes are cleared.
TRNENSEL bit (Transaction-Enabled Time Select)
When the USB port is in use for full-speed or low-speed communications, the TRNENSEL bit specifies the timing with
which the USBFS issues tokens in a frame (transaction-enabled time).
Set this bit to 1 when a low-speed device is connected. The bit is only valid in host controller mode. Set this bit to 0 in
device controller mode.
31.2.13
Interrupt Status Register 0 (INTSTS0)
Address(es): USBFS.INTSTS0 4009 0040h
b15
b14
VBINT RESM
Value after reset:
0
0
b13
b12
b11
b10
b9
SOFR
DVST
CTRT
BEMP
NRDY
0
0/1*1
0
0
0
b8
b7
b6
BRDY VBSTS
0
0*2
b5
b4
DVSQ[2:0]
0*3
0*3
b3
b2
VALID
0/1*3
0
b1
b0
CTSQ[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CTSQ[2:0]
Control Transfer Stage
b2
R
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b0
0 0 0: Idle or setup stage
0 0 1: Control read data stage
0 1 0: Control read status stage
0 1 1: Control write data stage
1 0 0: Control write status stage
1 0 1: Control write (no data) status stage
1 1 0: Control transfer sequence error.
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31. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b3
VALID
USB Request Reception
0: Setup packet not received
1: Setup packet received.
R/W*4
b6 to b4
DVSQ[2:0]
Device State
Indicates the device state.
R
b6
b4
0 0 0: Powered state
0 0 1: Default state
0 1 0: Address state
0 1 1: Configured state
1 x x: Suspend state.
b7
VBSTS
VBUS Input Status
0: USB_VBUS pin is low
1: USB_VBUS pin is high.
R
b8
BRDY
Buffer Ready Interrupt Status
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R
b9
NRDY
Buffer Not Ready Interrupt
Status
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R
b10
BEMP
Buffer Empty Interrupt Status
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R
b11
CTRT
Control Transfer Stage
Transition Interrupt Status *5
0: No control transfer stage transition interrupt occurred
1: Control transfer stage transition interrupt occurred.
R/W*4
b12
DVST
Device State Transition
Interrupt Status *5
0: No device state transition interrupt occurred
1: Device state transition interrupt occurred.
R/W*4
b13
SOFR
Frame Number Refresh
Interrupt Status
0: No SOF interrupt occurred
1: SOF interrupt occurred.
R/W*4
b14
RESM
Resume Interrupt Status *5,*6
0: No resume interrupt occurred
1: Resume interrupt occurred.
R/W*4
b15
VBINT
VBUS Interrupt Status *6
0: No VBUS interrupt occurred
1: VBUS interrupt occurred.
R/W*4
x: Don’t care
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
The value is 0 when the MCU is reset and 1 after a USB bus reset.
The value is 1 when the USB_VBUS pin is high and 0 when the USB_VBUS pin is low.
The value is 000b when the MCU is reset and 001b after a USB bus reset.
To clear the VBINT, RESM, SOFR, DVST, CTRT, or VALID bits, write 0 only to the bits to be cleared. Write 1 to the other bits.
Do not write 0 to the status bits indicating 0.
The status of the RESM, DVST, and CTRT bits are changed only in device controller mode. Set the associated interrupt enable
bits to 0 (disabled) in host controller mode.
The USBFS detects a change in the status indicated in the VBINT and RESM bits even while the clock supply is stopped
(SCKE bit = 0), and it requests the interrupt when the associated interrupt request bit is 1. Enable the clock supply before
clearing the status by software.
CTSQ[2:0] bits (Control Transfer Stage)
In host controller mode, the read value of the CTSQ[2:0] bits is invalid.
VALID bit (USB Request Reception)
In host controller mode, the read value of the VALID bit is invalid.
DVSQ[2:0] bits (Device State)
The DVSQ[2:0] bits are initialized by a USB bus reset. In host controller mode, the read value is invalid.
BRDY flag (Buffer Ready Interrupt Status)
The BRDY flag indicates the BRDY interrupt status.
The USBFS sets the BRDY bit to 1 when it detects a BRDY interrupt status (PIPEnBRDY = 1, n = 0 to 9) on at least one
pipe for which BRDY interrupts are enabled (BRDYENB.PIPEnBRDYE = 1).
For the conditions that cause the PIPEnBRDY status to be asserted, see section 31.3.3.1, BRDY interrupt.
The USBFS sets the BRDY bit to 0 when software writes 0 to all of the PIPEnBRDY bits associated with the
PIPEnBRDYE bits that are set to 1. Writing 0 to the BRDY flag in software does not clear the flag.
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31. USB 2.0 Full-Speed Module (USBFS)
NRDY flag (Buffer Not Ready Interrupt Status)
The NRDY flag indicates the NRDY interrupt status.
The USBFS sets the NRDY bit to 1 when it detects a NRDY interrupt status (PIPEnNRDY = 1, n = 0 to 9) on at least one
pipe for which NRDY interrupts are enabled (NRDYENB.PIPEnNRDYE = 1).
For the conditions that cause the PIPEnNRDY status to be asserted, see section 31.3.3.2, NRDY interrupt.
The USBFS sets the NRDY bit to 0 when software writes 0 to all of the PIPEnNRDY bits associated with the
PIPEnNRDYE bits that are set to 1. Writing 0 to the NRDY flag in software does not clear the flag.
BEMP flag (Buffer Empty Interrupt Status)
The BEMP flag indicates the BEMP interrupt status.
The USBFS sets the BEMP bit to 1 when it detects a BEMP interrupt status (PIPEnBEMP = 1, n = 0 to 9) on at least one
pipe for which the BEMP interrupts are enabled (BEMPENB.PIPEnBEMPE = 1).
For the conditions that cause the PIPEnBEMP status to be asserted, see section 31.3.3.3, BEMP interrupt.
The USBFS sets the BEMP bit to 0 when software writes 0 to all of the PIPEnBEMP bits associated with the
PIPEnBEMPE bits that are set to 1. Writing 0 to the BEMP flag in software does not clear the flag.
CTRT flag (Control Transfer Stage Transition Interrupt Status)
In device controller mode, the USBFS updates the value of the CTSQ[2:0] bits and sets the CTRT flag to 1 on detecting
a transition in the control transfer stage. When a control transfer stage transition interrupt occurs, clear the CTRT flag
before the USBFS detects the next control transfer stage transition.
Values read from the CTRT flag in host controller mode are invalid.
DVST flag (Device State Transition Interrupt Status)
In device controller mode, the USBFS updates the value of the DVSQ[2:0] bits and sets the DVST flag to 1 on detecting
a change in the device state. When a device state transition interrupt occurs, clear the DVST flag before the USBFS
detects the next device state transition.
Values read from the DVST flag in host controller mode are invalid.
SOFR flag (Frame Number Refresh Interrupt Status)
In host controller mode, the USBFS sets the SOFR flag to 1 on updating the frame number when the DVSTCTR0.UACT
bit is set to 1 by software. A SOFR interrupt is detected every 1 ms.
In device controller mode, the USBFS sets the SOFR flag to 1 on updating the frame number. A frame number refresh
interrupt is detected every 1 ms.
The USBFS can detect an SOFR interrupt through the internal interpolation function even when a corrupted SOF packet
is received from the USB host.
RESM flag (Resume Interrupt Status)
In device controller mode, the USBFS sets the RESM flag to 1 on detecting the falling edge of the signal on the USB_DP
pin in the suspended state (DVSQ[2:0] = 1xxb). Values read from the RESM flag in host controller mode are invalid.
VBINT flag (VBUS Interrupt Status)
The USBFS sets the VBINT flag to 1 on detecting a level change (high to low or low to high) in the USB_VBUS pin
input value. The USBFS sets the VBSTS flag to indicate the USB_VBUS pin input value. When a VBUS interrupt
occurs, eliminate transient elements by reading the VBSTS flag at least three times through software processing and
check that the values read are the same.
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31.2.14
31. USB 2.0 Full-Speed Module (USBFS)
Interrupt Status Register 1 (INTSTS1)
Address(es): USBFS.INTSTS1 4009 0042h
b15
b14
OVRC BCHG
R
Value after reset:
0
0
b13
—
0
b12
b11
DTCH ATTCH
0
0
b10
b9
b8
b7
—
—
—
—
0
0
0
0
b6
b5
EOFER SIGN
R
0
0
b4
b3
b2
b1
b0
SACK
—
—
—
—
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should
be 0.
R/W
b4
SACK
Setup Transaction Normal Response
Interrupt Status
0: No SACK interrupt occurred
1: SACK interrupt occurred.
R/W
*1
b5
SIGN
Setup Transaction Error Interrupt Status
0: No SIGN interrupt occurred
1: SIGN interrupt occurred.
R/W
*1
b6
EOFERR
EOF Error Detection Interrupt Status
0: No EOFERR interrupt occurred
1: EOFERR interrupt occurred.
R/W
*1
b10 to b7
—
Reserved
These bits are read as 0. The write value should
be 0.
R/W
b11
ATTCH
ATTCH Interrupt Status
0: No ATTCH interrupt occurred
1: ATTCH interrupt occurred.
R/W
*1
b12
DTCH
USB Disconnection Detection Interrupt
Status
0: No DTCH interrupt occurred
1: DTCH interrupt occurred.
R/W
*1
b13
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b14
BCHG
USB Bus Change Interrupt Status *2
0: No BCHG interrupt occurred
1: BCHG interrupt occurred.
R/W
*1
b15
OVRCR
Overcurrent Input Change Interrupt
Status *2
0: No OVRCR interrupt occurred
1: OVRCR interrupt occurred.
R/W
*1
Note 1.
Note 2.
To clear the bits in INTSTS1, write 0 only to the bits to be cleared. Write 1 to the other bits.
The USBFS detects a change in the status in the OVRCR or BCHG bit even when the clock supply is stopped (SYSCFG.SCKE
= 0), and it requests the interrupt when the associated interrupt request bit is 1. Enable the clock supply (SYSCFG.SCKE = 1)
before clearing the status through software. No other interrupts can be detected while the clock supply is stopped
(SYSCFG.SCKE bit = 0).
INTSTS1 is used to confirm the status of each interrupt in host controller mode. Only enable the status change interrupts
indicated in the bits in INTSTS1 in host controller mode.
SACK flag (Setup Transaction Normal Response Interrupt Status)
The SACK flag indicates the status of the setup transaction normal response interrupt in host controller mode.
The USBFS detects the SACK interrupt and sets this flag to 1 when an ACK response is returned from a peripheral
device during the setup transactions issued by the USBFS. If the associated interrupt enable bit is set to 1 by software, the
USBFS generates the interrupt.
Values read from the SACK flag in device controller mode are invalid.
SIGN flag (Setup Transaction Error Interrupt Status)
The SIGN flag indicates the status of setup transaction error interrupts in host controller mode.
The USBFS detects the SIGN interrupt and sets this flag to 1 when an ACK response is not returned from a peripheral
device three consecutive times during the setup transactions issued by the USBFS. If the associated interrupt enable bit is
set to 1 by software, the USBFS generates the interrupt.
The USBFS detects the SIGN interrupt when any of the following response conditions occur for three consecutive setup
transactions:
Timeout is detected by the USBFS when the peripheral device has returned no response
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31. USB 2.0 Full-Speed Module (USBFS)
A corrupted ACK packet is received
A handshake other than ACK (NAK, NYET, or STALL) is received.
Values read from the SIGN flag in device controller mode are invalid.
EOFERR flag (EOF Error Detection Interrupt Status)
The EOFERR flag indicates the status of the EOF error detection interrupts in host controller mode.
The USBFS detects the EOFERR interrupt and sets this flag to 1 on detecting that communication did not complete at the
EOF2 timing defined in the USB 2.0 specification. If the associated interrupt enable bit is set to 1 by software, the
USBFS generates the interrupt.
After detecting the EOFERR interrupt, the USBFS controls the hardware as follows, regardless of the associated
interrupt enable bit setting:
Sets the DVSTCTR0.UACT bit for the port in which the EOFERR interrupt was detected to 0
Puts the port in which the EOFERR interrupt occurred into the idle state.
Software must terminate all pipes in which communications are currently being carried out and re-enumerate the USB
port.
Values read from the EOFERR flag in device controller mode are invalid.
ATTCH flag (ATTCH Interrupt Status)
The ATTCH flag indicates the status of USB attach detection interrupts in host controller mode.
The USBFS detects the ATTCH interrupt and sets this flag to 1 on detecting a J- or K-state on the full- or low-speed
signal level for 2.5 μs. If the associated interrupt enable bit is set to 1 by software, the USBFS generates the interrupt.
The USBFS detects the ATTCH interrupt on any of the following conditions:
K-state, SE0, or SE1 changes to J-state, and J-state continues for 2.5 µs
J-state, SE0, or SE1 changes to K-state, and K-state continues for 2.5 µs.
Values read from the ATTCH flag in device controller mode are invalid.
DTCH flag (USB Disconnection Detection Interrupt Status)
The DTCH flag indicates the status of USB disconnection detection interrupts in host controller mode.
The USBFS detects the DTCH interrupt and sets this flag to 1 on detecting a USB bus detach event. If the associated
interrupt enable bit is set to 1 by software, the USBFS generates the interrupt.
The USBFS detects bus detach events based on the USB 2.0 specification.
After detecting the DTCH interrupt, the USBFS controls hardware as follows, regardless of the associated interrupt
enable bit setting:
Sets the DVSTCTR0.UACT bit for the port in which the DTCH interrupt was detected to 0
Puts the port in which the DTCH interrupt occurred into the idle state.
Software must terminate all pipes in which communications are being carried out and invoke the wait state for attaching
to the USB port (waiting for ATTCH interrupt generation).
Values read from the DTCH flag in device controller mode are invalid.
BCHG flag (USB Bus Change Interrupt Status)
The BCHG flag indicates the status of the USB bus change interrupts in host controller mode.
The USBFS detects the BCHG interrupt and sets this flag to 1 when a change in the full- or low-speed signal level occurs
on the USB port. This includes any change from J-state, K-state, or SE0 to J-state, K-state, or SE0. If the associated
interrupt enable bit is set to 1 by software, the USBFS generates the interrupt.
The USBFS sets the LNST[1:0] bits to indicate the input state of the USB port. When a BCHG interrupt occurs,
eliminate transient elements by repeat reading the LNST[1:0] bits through software until the same value is read at least
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31. USB 2.0 Full-Speed Module (USBFS)
three times.
A change in the USB bus state can be detected while the internal clock is stopped.
Values read from the BCHG flag in device controller mode are invalid.
OVRCR flag (Overcurrent Input Change Interrupt Status)
The OVRCR flag indicates the status of USB_OVRCURA and USB_OVRCURB input pin change interrupts.
The USBFS detects the OVRCR interrupt and sets this flag to 1 when a change (high to low or low to high) occurs in at
least one of the input values to the USB_OVRCURA and USB_OVRCURB pins. If the associated interrupt enable bit is
set to 1 by software, the USBFS generates the interrupt.
31.2.15
BRDY Interrupt Status Register (BRDYSTS)
Address(es): USBFS.BRDYSTS 4009 0046h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BRDY
BRDY Interrupt Status for Pipe 0*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b1
PIPE1BRDY
BRDY Interrupt Status for Pipe 1*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b2
PIPE2BRDY
BRDY Interrupt Status for Pipe 2*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b3
PIPE3BRDY
BRDY Interrupt Status for Pipe 3*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b4
PIPE4BRDY
BRDY Interrupt Status for Pipe 4*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b5
PIPE5BRDY
BRDY Interrupt Status for Pipe 5*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b6
PIPE6BRDY
BRDY Interrupt Status for Pipe 6*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b7
PIPE7BRDY
BRDY Interrupt Status for Pipe 7*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b8
PIPE8BRDY
BRDY Interrupt Status for Pipe 8*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
b9
PIPE9BRDY
BRDY Interrupt Status for Pipe 9*2
0: No BRDY interrupt occurred
1: BRDY interrupt occurred.
R/W*1
Reserved
These bits are read as 0. The write value should be 0. R/W
b15 to b10 —
Note 1.
Note 2.
When the SOFCFG.BRDYM bit is set to 0, to clear the status indicated in the bits in BRDYSTS, write 0 only to the bits to be
cleared. Write 1 to the other bits.
When the SOFCFG.BRDYM bit is set to 0, clear BRDY interrupts before accessing the FIFO.
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31.2.16
31. USB 2.0 Full-Speed Module (USBFS)
NRDY Interrupt Status Register (NRDYSTS)
Address(es): USBFS.NRDYSTS 4009 0048h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9N PIPE8N PIPE7N PIPE6N PIPE5N PIPE4N PIPE3N PIPE2N PIPE1N PIPE0N
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
RDY
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0NRDY
NRDY Interrupt Status for Pipe 0
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
0: No NRDY interrupt occurred
1: NRDY interrupt occurred.
R/W
b1
PIPE1NRDY
b2
PIPE2NRDY
b3
PIPE3NRDY
b4
PIPE4NRDY
b5
PIPE5NRDY
b6
PIPE6NRDY
b7
PIPE7NRDY
b8
PIPE8NRDY
b9
PIPE9NRDY
b15 to b10 —
Note 1.
NRDY Interrupt Status for Pipe 1
NRDY Interrupt Status for Pipe 2
NRDY Interrupt Status for Pipe 3
NRDY Interrupt Status for Pipe 4
NRDY Interrupt Status for Pipe 5
NRDY Interrupt Status for Pipe 6
NRDY Interrupt Status for Pipe 7
NRDY Interrupt Status for Pipe 8
NRDY Interrupt Status for Pipe 9
Reserved
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
These bits are read as 0. The write value should be 0. R/W
To clear the status indicated in the bits in NRDYSTS, write 0 only to the bits to be cleared. Write 1 to the other bits.
31.2.17
BEMP Interrupt Status Register (BEMPSTS)
Address(es): USBFS.BEMPSTS 4009 004Ah
b15
Value after reset:
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B
EMP
EMP
EMP
EMP
EMP
EMP
EMP
EMP
EMP
EMP
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BEMP
BEMP Interrupt Status for Pipe 0
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W
b1
b2
b3
b4
PIPE1BEMP
PIPE2BEMP
PIPE3BEMP
PIPE4BEMP
BEMP Interrupt Status for Pipe 1
BEMP Interrupt Status for Pipe 2
BEMP Interrupt Status for Pipe 3
BEMP Interrupt Status for Pipe 4
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31. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b5
PIPE5BEMP
BEMP Interrupt Status for Pipe 5
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W*1
b6
PIPE6BEMP
BEMP Interrupt Status for Pipe 6
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W*1
b7
PIPE7BEMP
BEMP Interrupt Status for Pipe 7
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W*1
b8
PIPE8BEMP
BEMP Interrupt Status for Pipe 8
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W*1
b9
PIPE9BEMP
BEMP Interrupt Status for Pipe 9
0: No BEMP interrupt occurred
1: BEMP interrupt occurred.
R/W*1
Reserved
These bits are read as 0. The write value should be 0. R/W
b15 to b10 —
Note 1.
To clear the status indicated in the bits in BEMPSTS, write 0 only to the bits to be cleared. Write 1 to the other bits.
31.2.18
Frame Number Register (FRMNUM)
Address(es): USBFS.FRMNUM 4009 004Ch
b15
b14
b13
b12
b11
OVRN
CRCE
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
FRNM[10:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
FRNM[10:0]
Frame Number
Latest frame number
R
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b14
CRCE
Receive Data Error
0: No error occurred
1: Error occurred.
R/W*1
b15
OVRN
Overrun/Underrun Detection Status
0: No error occurred
1: Error occurred.
R/W*1
Note 1.
To clear the status, write 0 only to the bits to be cleared. Write 1 to the other bits.
FRNM[10:0] flags (Frame Number)
The USBFS sets the FRNM[10:0] flags to indicate the latest frame number, which is updated every 1 ms, when an SOF
packet is issued or received.
CRCE flag (Receive Data Error)
The CRCE flag is set to 1 when a CRC error or bit stuffing error occurs during isochronous transfer. On detecting a CRC
error in host controller mode, the USBFS generates an internal NRDY interrupt.
To clear the CRCE flag, write 0 to it while writing 1 to the other bits in the FRMNUM register.
OVRN flag (Overrun/Underrun Detection Status)
The OVRN flag is set to 1 when an overrun or underrun error occurs during isochronous transfer. To clear the flag, write
0 to it while writing 1 to the other bits in the FRMNUM register.
In host controller mode, the OVRN flag is set to 1 on any of the following conditions:
For a transmitting isochronous pipe, the time to issue an OUT token comes before all of the transmit data is written
to the FIFO buffer
For a receiving isochronous pipe, the time to issue an IN token comes when no FIFO buffer planes are empty.
In device controller mode, the OVRN flag is set to 1 on any of the following conditions:
For a transmitting isochronous pipe, the IN token is received before all of the transmit data is written to the FIFO
buffer
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31. USB 2.0 Full-Speed Module (USBFS)
For a receiving isochronous pipe, the OUT token is received when no FIFO buffer planes are empty.
31.2.19
Device State Change Register (DVCHGR)
Address(es): USBFS.DVCHGR 4009 004Eh
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
DVCH
G
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b14 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
DVCHG
Device State Change
0: Disable writes to USBADDR.STSRECOV[3:0] and
USBADDR.USBADDR[6:0] bits
1: Enable writes to USBADDR.STSRECOV[3:0] and
USBADDR.USBADDR[6:0] bits.
R/W
For details, see section 31.3.1.5, Release from deep software standby mode because of USB suspend/resume interrupts.
31.2.20
USB Address Register (USBADDR)
Address(es): USBFS.USBADDR 4009 0050h
Value after reset:
b15
b14
b13
b12
—
—
—
—
0
0
0
0
b11
b10
b9
b8
STSRECOV[3:0]
0
0
0
b7
b6
b5
b4
—
0
0
b3
b2
b1
b0
0
0
USBADDR[6:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
USBADDR[6:0]
USB Address
In device controller mode, these bits indicate the USB address
assigned by the host when the USBFS processed the
SET_ADDRESS request successfully
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b11 to b8
STSRECOV[3:0]
Status Recovery
Recovery in device controller mode
R/W
b11
b8
1 0 0 1: Return to the full-speed state (bits DVSTCTR0.RHST[2:0]
= 010b), bits INTSTS0.DVSQ[2:0] = 001b (default state)
1 0 1 0: Return to the full-speed state (bits DVSTCTR0.RHST[2:0]
= 010b), bits INTSTS0.DVSQ[2:0] = 010b (address state)
1 0 1 1: Return to the full-speed state (bits DVSTCTR0.RHST[2:0]
= 010b), bits INTSTS0.DVSQ[2:0] = 011b (configured state).
Other settings are prohibited.
Recovery in host controller mode
b11
b8
0 1 0 0: Return to the low-speed state (bits DVSTCTR0.RHST[2:0]
= 001b)
1 0 0 0: Return to the full-speed state (bits DVSTCTR0.RHST[2:0]
= 010b).
Other settings are prohibited.
b15 to b12 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
USBADDR[6:0] bits (USB Address)
In device controller mode, the USBADDR[6:0] flags indicate the USB address received when the USBFS processed a
SetAddress request successfully. The USBFS sets the USBADDR[6:0] bits to 00h on detecting a USB bus reset.
Writing to these bits is enabled while the DVCHGR.DVCHG bit is set to 1. On recovering from a USB power shut-off,
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31. USB 2.0 Full-Speed Module (USBFS)
operation can resume from the USB address set before software shut-off.
In host controller mode, the USBADDR[6:0] bits are invalid.
STSRECOV[3:0] bits (Status Recovery)
Use the STSRECOV[3:0] bits to resume the state of the internal sequencer on recovering from USB power shut-off. For
details, see section 31.3.1.5, Release from deep software standby mode because of USB suspend/resume interrupts.
Writing to these bits is enabled while the DVCHGR.DVCHG bit is set to 1.
31.2.21
USB Request Type Register (USBREQ)
Address(es): USBFS.USBREQ 4009 0054h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
BREQUEST[7:0]
Value after reset:
0
0
0
0
0
b4
b3
b2
b1
b0
0
0
BMREQUESTTYPE[7:0]
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
BMREQUESTTYPE[7:0]
Request Type
USB request bmRequestType value
R/W
*1
b15 to b8
BREQUEST[7:0]
Request
USB request bRequest value
R/W
*1
Note 1.
In device controller mode, these bits can be read, but writing to them has no effect. In host controller mode, these bits are both
read/write bits.
USBREQ stores setup requests for control transfers.
In device controller mode, the USBREQ stores the received bRequest and bmRequestType values. In host controller mode,
it is set to the bRequest and bmRequestType values to be transmitted.
USBREQ is initialized by a USB bus reset.
BMREQUESTTYPE[7:0] bits (Request Type)
The BMREQUESTTYPE[7:0] bits hold the bmRequestType value of USB requests.
In host controller mode:
Set these bits to the value of the USB request data in transmission setup transactions. Do not change the value of the
bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the value of the USB request data in reception setup transactions. Writing to these bits has no
effect.
BREQUEST[7:0] bits (Request)
The BREQUEST[7:0] bits store bRequest value of the USB request.
In host controller mode:
Set these bits to the value of the USB request data in setup transmission transactions. Do not change the value of the
bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the value of the USB request data in reception setup transactions. Writing to these bits has no
effect.
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31.2.22
31. USB 2.0 Full-Speed Module (USBFS)
USB Request Value Register (USBVAL)
Address(es): USBFS.USBVAL 4009 0056h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WVALUE[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WVALUE[15:0]
Value
These bits store the USB request wValue value
R/W
*1
Note 1.
In device controller mode, these bits can be read, but writing to them has no effect. In host controller mode, these bits are both
read/write bits.
In device controller mode, USBVAL stores the received wValue value. In host controller mode, it is set to the wValue
value to be transmitted.
USBVAL is initialized by a USB bus reset.
WVALUE[15:0] bits (Value)
The WVALUE[15:0] bits store wValue value of the USB request.
In host controller mode:
Set these bits to the value of the wValue field in USB requests of transmission setup transactions. Do not change the
value of the bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the wValue value of USB requests in reception setup transactions. Writing to the bits has no
effect.
31.2.23
USB Request Index Register (USBINDX)
Address(es): USBFS.USBINDX 4009 0058h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WINDEX[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WINDEX[15:0]
Index
These bits store the USB request wIndex value
R/W*1
Note 1.
In device controller mode, these bits can be read, but writing to them has no effect. In host controller mode, these bits are both
read/write bits.
USBINDX stores setup requests for control transfers.
In device controller mode, it stores the received wIndex value. In host controller mode, it is set to the wIndex value to be
transmitted.
USBINDX is initialized by a USB bus reset.
WINDEX[15:0] bits (Index)
The WINDEX[15:0] bits hold the wIndex value of a USB request.
In host controller mode:
Set these bits to the wIndex value in USB requests in transmission setup transactions. Do not change the value of the
bits while the DCPCTR.SUREQ bit is 1.
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31. USB 2.0 Full-Speed Module (USBFS)
In device controller mode:
These bits indicate the wIndex value in USB requests received in reception setup transactions. Writing to these bits
has no effect.
31.2.24
USB Request Length Register (USBLENG)
Address(es): USBFS.USBLENG 4009 005Ah
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WLENTUH[15:0]
0
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WLENTUH[15:0]
Length
These bits store the USB request wLength value
R/W*1
Note 1.
In device controller mode, these bits can be read, but writing to them has no effect. In host controller mode, these bits are both
read/write bits.
USBLENG stores setup requests for control transfers.
In device controller mode, the value of wLength that is received is stored. In host controller mode, the value of wLength
to be transmitted is set.
USBLENG is initialized by a USB bus reset.
WLENTUH[15:0] bits (Length)
The WLENTUH[15:0] bits hold the wLength value of a USB request.
In host controller mode:
Set these bits to the wLength value in USB requests in transmission setup transactions. Do not change the value of
the bits while the DCPCTR.SUREQ bit is 1.
In device controller mode:
These bits indicate the wLength value in USB requests received in reception setup transactions. Writing to these bits
has no effect.
31.2.25
DCP Configuration Register (DCPCFG)
Address(es): USBFS.DCPCFG 4009 005Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
SHTNA
K
—
—
DIR
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
DIR
Transfer Direction *1
0: Data receiving direction
1: Data transmitting direction.
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
SHTNAK
Pipe Disabled at End of Transfer *1
0: Keep pipe open after transfer ends
1: Disable pipe after transfer ends.
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note 1.
R/W
R/W
R/W
Only set this bit while the PID is NAK. Before setting this bit, check that the DCPCTR.PBUSY bit is 0, and then change the
DCPCTR.PID[1:0] bits for the DCP from BUF to NAK. If the PID[1:0] bits are changed to NAK by the USBFS, checking the
PBUSY bit through software is not required.
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31. USB 2.0 Full-Speed Module (USBFS)
DIR bit (Transfer Direction)
In host controller mode, the DIR bit sets the transfer direction of the data stage and status stage for control transfers. In
device controller mode, set the DIR bit to 0.
SHTNAK bit (Pipe Disabled at End of Transfer)
The SHTNAK bit specifies whether to change PID to NAK on transfer end when the selected pipe is receiving. It is only
valid when the selected pipe is receiving.
When the SHTNAK bit is 1, the USBFS changes the DCPCTR.PID[1:0] bits for the DCP to NAK on determining that a
transfer has ended. The USBFS determines transfer end on the following condition:
A short packet, including a zero-length packet, is successfully received.
31.2.26
DCP Maximum Packet Size Register (DCPMAXP)
Address(es): USBFS.DCPMAXP 4009 005Eh
b15
b14
b13
b12
DEVSEL[3:0]
0
Value after reset:
0
0
0
b11
b10
b9
b8
b7
—
—
—
—
—
0
0
0
0
0
b6
b5
b4
b3
b2
b1
b0
0
0
0
MXPS[6:0]
1
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
MXPS[6:0]
Maximum Packet Size *1
These bits set the maximum data payload specification (maximum
packet size) for the DCP
R/W
b11 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
R/W
b15 to b12 DEVSEL[3:0]
Note 1.
Note 2.
Device
Select *2
b12
0 0 0 0: Address 0000b
0 0 0 1: Address 0001b
0 0 1 0: Address 0010b
0 0 1 1: Address 0011b
0 1 0 0: Address 0100b
0 1 0 1: Address 0101b.
Other settings are prohibited.
Only set the MXPS[6:0] bits while PID is NAK. Before setting these bits, check that the DCPCTR.PBUSY bit is 0, and then
change the DCPCTR.PID[1:0] bits for the DCP from BUF to NAK. If the PID[1:0] bits are changed to NAK by the USBFS,
checking the PBUSY bit through software is not required. After the MXPS[6:0] bits are set and the DCP is set to the
CURPIPE[3:0] bits in a port select register, clear the buffer by setting the BCLR bit in the port control register to 1.
Only set the DEVSEL[3:0] bits while PID is NAK and the DCPCTR.SUREQ bit is 0. Before setting these bits, check that the
DCPCTR.PBUSY bit is 0, and then change the DCPCTR.PID[1:0] bits for the DCP from BUF to NAK. If the PID[1:0] bits are
changed to NAK by the USBFS, checking the PBUSY bit through software is not required.
MXPS[6:0] bits (Maximum Packet Size)
The MXPS[6:0] bits specify the maximum data payload (maximum packet size) for the DCP. The initial value is 40h (64
bytes). Set the bits to a USB 2.0-compliant value. Do not write to the FIFO buffer or set PID = BUF while MXPS[6:0] is
set to 0.
DEVSEL[3:0] bits (Device Select)
In host controller mode, the DEVSEL[3:0] bits specify the address of the target peripheral device for a control transfer.
Set up the device address in the associated DEVADDn (n = 0 to 5) register first, and then set these bits to the
corresponding value. To set the DEVSEL[3:0] bits to 0010b, for example, first set the address in the DEVADD2 register.
In device controller mode, set these bits to 0000b.
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31.2.27
31. USB 2.0 Full-Speed Module (USBFS)
DCP Control Register (DCPCTR)
Address(es): USBFS.DCPCTR 4009 0060h
b15
b14
BSTS SUREQ
Value after reset:
0
0
b13
b12
b11
b10
b9
—
—
SUREQ
CLR
—
—
0
0
0
0
0
b8
b7
b6
b5
SQCLR SQSET SQMO PBUSY
N
0
0
1
0
b4
b3
b2
—
—
CCPL
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b2
CCPL
Control Transfer End Enable
0: Disable control transfer completion
1: Enable control transfer completion.
R/W
0
0
1
1
0: NAK response
1: BUF response (depends on the buffer state)
0: STALL response
1: STALL response.
b4, b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: DCP not used for the USB bus
1: DCP in use for the USB bus.
R
b6
SQMON
Sequence Toggle Bit Monitor
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set *2
Sets the sequence toggle bit in DCP transfers.
0: Invalid (writing 0 has no effect)
1: Set the expected value for the next transaction to
DATA1.
This bit is read as 0.
R/W*1
b8
SQCLR
Sequence Toggle Bit Clear *2
Clears the sequence toggle bit in DCP transfers.
0: Invalid (writing 0 has no effect)
1: Clear the expected value for the next transaction to
DATA0.
This bit is read as 0.
R/W*1
b10, b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b11
SUREQCLR
SUREQ Bit Clear
Clears the SUREQ bit in host controller mode.
0: Invalid (writing 0 has no effect)
1: Clear SUREQ to 0.
This bit is read as 0.
R/W
b13, b12
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
SUREQ
Setup Token Transmission
Sets up token transmission in host controller mode.
0: Invalid (writing 0 has no effect)
1: Transmit setup packet.
R/W
b15
BSTS
Buffer Status
0: Buffer access disabled
1: Buffer access enabled.
R
Note 1.
Note 2.
This bit is read as 0.
Only set the SQSET and SQCLR bits to 1 while PID is NAK. Before setting these bits, check that the PBUSY bit is 0, and then
change the PID[1:0] bits for the DCP from BUF to NAK. If the PID[1:0] bits are changed to NAK by the USBFS, checking the
PBUSY bit through software is not required.
PID[1:0] bits (Response PID)
The PID[1:0] bits control the USB response type during control transfers.
In host controller mode, to change the PID[1:0] setting from NAK to BUF:
When the transmitting direction is set:
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31. USB 2.0 Full-Speed Module (USBFS)
a. Write all of the transmit data to the FIFO buffer while the DVSTCTR0.UACT bit is 1 and PID is NAK.
b. Set PID[1:0] bits to 01b (BUF).
The USBFS then executes the OUT transaction.
When the receiving direction is set:
a. Check that the FIFO buffer is empty (or empty the buffer) while the DVSTCTR0.UACT bit is 1 and PID is
NAK.
b. Set PID[1:0] bits to 01b (BUF).
The USBFS then executes the IN transaction.
The USBFS changes the PID[1:0] setting as follows:
When the PID[1:0] bits are set to BUF (01b) by software and the USBFS has received data exceeding
MaxPacketSize, the USBFS sets the PID[1:0] to STALL (11b)
When a reception error, such as a CRC error, is detected three times consecutively, the USBFS sets the PID[1:0]
bits to NAK (00b)
On receiving the STALL handshake, the USBFS sets PID[1:0] to STALL (11b).
In device controller mode, the USBFS changes the PID[1:0] setting as follows:
On receiving a setup packet, the USBFS sets PID[1:0] to NAK (00b). The USBFS then sets the INTSTS0.VALID
flag to 1, and the PID[1:0] setting cannot be changed until software clears the VALID flag to 0.
When the PID[1:0] bits are set to BUF (01b) by software and the USBFS has received data exceeding
MaxPacketSize, the USBFS sets PID[1:0] to STALL (11b)
On detecting a control transfer sequence error, the USBFS sets PID[1:0] to STALL (1xb)
On detecting a USB bus reset, the USBFS sets PID[1:0] to NAK.
The USBFS does not check the PID[1:0] setting while processing a SET_ADDRESS request.
The PID[1:0] bits are initialized by a USB bus reset.
CCPL bit (Control Transfer End Enable)
In device controller mode, setting the CCPL bit to 1 enables the status stage of the control transfer to be completed.
When the bit is set to 1 by software while the associated PID[1:0] bits are set to BUF, the USBFS completes the control
transfer status stage.
During control read transfers, the USBFS transmits the ACK handshake in response to the OUT transaction from the
USB host. During control write or no-data control transfers, it transmits the zero-length packet in response to the IN
transaction from the USB host. On detecting a SET_ADDRESS request, the USBFS operates in auto response mode
from the setup stage up to the status stage completion regardless of the CCPL bit setting.
The USBFS changes the CCPL bit from 1 to 0 on receiving a new setup packet. Software cannot write 1 to the bit while
the INTSTS0.VALID bit is 1. The bit is initialized by a USB bus reset.
In host controller mode, always write 0 to the CCPL bit.
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether DCP is used for the transaction when USBFS changes the PID[1:0] bits from BUF to
NAK. The USBFS changes the PBUSY bit from 0 to 1 at the start of a USB transaction for the selected pipe. It changes
the PBUSY bit from 1 to 0 on completion of one transaction.
After PID is set to NAK by software, the value in the PBUSY bit indicates whether changes to pipe settings can proceed.
For details, see section 31.3.4.1, Pipe control register switching procedures.
SQMON bit (Sequence Toggle Bit Monitor)
The SQMON bit indicates the expected value of the sequence toggle bit for the next transaction during a DCP transfer.
The USBFS toggles the bit on normal completion of the transaction. It does not toggle the bit, however, when a DATAPID mismatch occurs during a transfer in the receiving direction.
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31. USB 2.0 Full-Speed Module (USBFS)
In device controller mode, the USBFS sets the SQMON bit to 1 (specifies DATA1 as the expected value) on successful
reception of the setup packet.
In device controller mode, the USBFS does not reference this bit during IN or OUT transactions at the status stage, and it
does not toggle the bit on normal completion.
SQSET bit (Sequence Toggle Bit Set)
The SQSET bit specifies DATA1 as the expected value of the sequence toggle bit for the next transaction during a DCP
transfer.
Do not set the SQCLR and SQSET bits to 1 simultaneously.
SQCLR bit (Sequence Toggle Bit Clear)
The SQCLR bit specifies DATA0 as the expected value of the sequence toggle bit for the next transaction during a DCP
transfer. It is read as 0.
Do not set the SQCLR and SQSET bits to 1 simultaneously.
SUREQCLR bit (SUREQ Bit Clear)
In host controller mode, setting the SUREQCLR bit to 1 clears the SUREQ bit to 0. The bit is read as 0.
If transfer stops while the SUREQ bit is set to 1 in a setup transaction, set the SUREQCLR bit to 1 by software. This is
not necessary at the end of a normal setup transaction, because the USBFS automatically clears the SUREQ bit to 0.
Only control the SUREQ bit through the SUREQCLR bit while the DVSTCTR0.UACT bit is 0. When UACT is 0,
communication is halted or no transfer is occurring because a bus disconnection was detected.
In device controller mode, always write 0 to this bit.
SUREQ bit (Setup Token Transmission)
In host controller mode, setting the SUREQ bit to 1 triggers the USBFS to transmit the setup packet. After completing
the setup transaction process, the USBFS generates either the SACK or SIGN interrupt and clears the SUREQ bit to 0.
The USBFS also clears the SUREQ bit to 0 when software sets the SUREQCLR bit to 1.
Before setting the SUREQ bit to 1, set the DCPMAXP.DEVSEL[3:0] bits, USBREQ, USBVAL, USBINDX, and
USBLENG appropriately to transmit the target USB request in the setup transaction. Also check that the PID[1:0] bits
for the DCP are set to NAK. After setting the SUREQ bit to 1, do not change the DCPMAXP.DEVSEL[3:0] bits,
USBREQ, USBVAL, USBINDX, or USBLENG until the setup transaction is complete (SUREQ bit = 1). Write 1 to the
SUREQ bit only when transmitting the setup token. Otherwise, write 0.
In device controller mode, always write 0 to this bit.
BSTS flag (Buffer Status)
The BSTS flag indicates the status of access to the DCP FIFO buffer. The meaning of this flag varies as follows
depending on the CFIFOSEL.ISEL setting:
When ISEL = 0, this flag indicates whether receive data can be read from the buffer
When ISEL = 1, this flag indicates whether transmit data can be written to the buffer.
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31.2.28
31. USB 2.0 Full-Speed Module (USBFS)
Pipe Window Select Register (PIPESEL)
Address(es): USBFS.PIPESEL 4009 0064h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
PIPESEL[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
PIPESEL[3:0]
Pipe Window Select
b3
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
b0
0 0 0 0: No pipe selected
0 0 0 1: Pipe 1
0 0 1 0: Pipe 2
0 0 1 1: Pipe 3
0 1 0 0: Pipe 4
0 1 0 1: Pipe 5
0 1 1 0: Pipe 6
0 1 1 1: Pipe 7
1 0 0 0: Pipe 8
1 0 0 1: Pipe 9.
Other settings are prohibited.
R/W
Set pipes 1 to 9 using the PIPESEL, PIPECFG, PIPEMAXP, PIPEPERI, PIPEnCTR, PIPEnTRE, and PIPEnTRN
registers (n = 0 to 9).
After selecting the pipe in the PIPESEL register, pipe functions must be set in the associated PIPECFG, PIPEMAXP, and
PIPEPERI registers. PIPEnCTR, PIPEnTRE, and PIPEnTRN can be set independently of the pipe selection in this
register.
PIPESEL[3:0] bits (Pipe Window Select)
The PIPESEL[3:0] bits select the pipe number associated with the PIPECFG, PIPEMAXP, and PIPEPERI registers used
for data writing and reading. Selecting a pipe number in the PIPESEL[3:0] bits allows writing to and reading from
PIPECFG, PIPEMAXP, and PIPEPERI associated with the selected pipe number.
When PIPESEL[3:0] = 0000b, 0 is read from all of the bits in PIPECFG, PIPEMAXP, and PIPEPERI. Writing to these
bits has no effect.
31.2.29
Pipe Configuration Register (PIPECFG)
Address(es): USBFS.PIPECFG 4009 0068h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
DIR
0
0
0
TYPE[1:0]
—
—
—
BFRE
DBLB
—
SHTNA
K
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
EPNUM[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
EPNUM[3:0]
Endpoint Number *1
Specifies the endpoint number for the selected pipe.
Setting 0000b indicates that the pipe is not used.
R/W
b4
DIR
Transfer Direction *2,*3
0: Receiving direction
1: Transmitting direction.
R/W
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
SHTNAK
Pipe Disabled at End of Transfer *1
0: Continue pipe operation after transfer ends
1: Disable pipe after transfer ends.
R/W
b8
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
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Bit
Symbol
31. USB 2.0 Full-Speed Module (USBFS)
Bit name
Mode *2,*3
Description
R/W
0: Single buffer
1: Double buffer.
R/W
R/W
b9
DBLB
Double Buffer
b10
BFRE
BRDY Interrupt Operation
Specification *2,*3
0: Generate BRDY interrupt on transmitting or
receiving data
1: Generate BRDY interrupt on completion of reading
data.
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b15, b14
TYPE[1:0]
Transfer
Type *1
Pipes 1 and 2
R/W
b15 b14
0
0
1
1
0: Pipe not used
1: Bulk transfer
0: Setting prohibited
1: Isochronous transfer.
Pipes 3 to 5
b15 b14
0
0
1
1
0: Pipe not used
1: Bulk transfer
0: Setting prohibited
1: Setting prohibited.
Pipes 6 to 9
b15 b14
0
0
1
1
Note 1.
Note 2.
Note 3.
0: Pipe not used
1: Setting prohibited
0: Interrupt transfer
1: Setting prohibited.
Only set the TYPE[1:0], SHTNAK, and EPNUM[3:0] bits while PID is NAK. Before setting these bits, check that the
PIPEnCTR.PBUSY bit is 0, and then change the PIPEnCTR.PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are
changed to 00 (NAK) by the USBFS, checking the PBUSY bit through software is not required.
Only set the BFRE, DBLB, and DIR bits while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port
select register. Before setting these bits, check that the PIPEnCTR.PBUSY bit is 0, and then change the PIPEnCTR.PID[1:0]
bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit through
software is not necessary.
To modify the BFRE, DBLB, or DIR bits after completing USB communication on the selected pipe, in addition to the
constraints described in Note 2, write 1 and 0 to the PIPEnCTR.ACLRM bit continuously through software and clear the FIFO
buffer assigned to the pipe.
PIPECFG specifies the transfer type, FIFO buffer access direction, and endpoint numbers for pipes 1 to 9. It also selects
single or double buffer mode, and whether to continue or disable pipe operation at the end of transfer.
EPNUM[3:0] bits (Endpoint Number)
The EPNUM[3:0] bits specify the endpoint number for the selected pipe. Setting 0000b indicates the pipe not used.
Set these bits so that the combination of the DIR and EPNUM[3:0] settings is different from those for other pipes. The
EPNUM[3:0] bits can be set to 0000b for all pipes.
DIR bit (Transfer Direction)
The DIR bit specifies the transfer direction for the selected pipe.
When software sets this bit to 0, the USBFS uses the selected pipe for receiving. When software sets this bit to 1, the
USBFS uses the selected pipe for transmitting.
SHTNAK bit (Pipe Disabled at End of Transfer)
The SHTNAK bit specifies whether to change the PIPEnCTR.PID[1:0] bits to 00b (NAK) at the end of transfer when the
selected pipe is set in the receiving direction. The bit is valid for pipes 1 to 5 in the receiving direction.
When software sets this bit to 1 for a receiving pipe, the USBFS changes the associated PIPEnCTR.PID[1:0] bits to 00b
(NAK) on determining the transfer end. The USBFS determines that the transfer has ended on the following conditions:
A short packet data (including a zero-length packet) was successfully received
The transaction counter is used and the number of packets specified for the transaction counter are successfully
received.
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31. USB 2.0 Full-Speed Module (USBFS)
DBLB bit (Double Buffer Mode)
The DBLB bit selects either single or double buffer mode for the FIFO buffer used by the selected pipe. The bit is valid
for pipes 1 to 5.
BFRE bit (BRDY Interrupt Operation Specification)
The BFRE bit specifies the BRDY interrupt generation timing from the USBFS to the CPU for the selected pipe.
When software sets the BFRE bit to 1 and the selected pipe is in the receiving direction, the USBFS detects the transfer
completion and generates the BRDY interrupt on reading the packet.
When a BRDY interrupt is generated with this setting, software must write 1 to the BCLR bit in the port control register.
The FIFO buffer assigned to the selected pipe is not enabled for reception until 1 is written to the BCLR bit.
When the BFRE bit is set to 1 by software and the selected pipe is in the transmitting direction, the USBFS does not
generate the BRDY interrupt. For details, see section 31.3.3.1, BRDY interrupt.
TYPE[1:0] bits (Transfer Type)
The TYPE[1:0] bits specify the transfer type for the pipe selected in the PIPESEL.PIPESEL[3:0] bits. Before setting PID
to BUF and starting USB communication on the selected pipe, set the TYPE[1:0] bits to a value other than 00b.
31.2.30
Pipe Maximum Packet Size Register (PIPEMAXP)
Address(es): USBFS.PIPEMAXP 4009 006Ch
b15
b14
b13
b12
DEVSEL[3:0]
0
Value after reset:
0
0
0
b11
b10
b9
—
—
—
0
0
0
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
MXPS[8:0]
0
0
0/1
*1
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
MXPS[8:0]
Maximum Packet Size *2
Pipes 1 and 2
1 byte (001h) to 256 bytes (100h)
Pipes 3 to 5
8 bytes (008h), 16 bytes (010h),
32 bytes (020h), 64 bytes (040h)
Bits [8:7] and [2:0] not supported.
Pipes 6 to 9
1 byte (001h) to 64 bytes (040h)
Bits [8:7] not supported.
R/W
b11 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
R/W
b15 to b12 DEVSEL[3:0]
Note 1.
Note 2.
Note 3.
Device
Select *3
b0
0 0 0 0: Address 0000b
0 0 0 1: Address 0001b
0 0 1 0: Address 0010b
0 0 1 1: Address 0011b
0 1 0 0: Address 0100b
0 1 0 1: Address 0101b.
Other settings are prohibited.
The value of the MXPS[8:0] bits is 000h when no pipe is selected in the PIPESEL.PIPESEL[3:0] bits and 040h when a pipe is
selected.
Only set the MXPS[8:0] bits while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port select
register. Before setting these bits, check that the PIPEnCTR.PBUSY bit is 0, and then change the PIPEnCTR.PID[1:0] bits from
01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit through software
is not necessary.
Only set the DEVSEL[3:0] bits while PID is NAK. Before setting these bits, check that the PIPEnCTR.PBUSY bit is 0, and then
change the PIPEnCTR.PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS,
checking the PBUSY bit through software is not required.
PIPEMAXP specifies the maximum packet size for pipes 1 to 9.
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31. USB 2.0 Full-Speed Module (USBFS)
MXPS[8:0] bits (Maximum Packet Size)
The MXPS[8:0] bits specify the maximum data payload (maximum packet size) for the selected pipe.
Set these bits to the appropriate value for each transfer type based on the USB 2.0 specification. When MXPS[8:0] = 0,
do not write to the FIFO buffer or set PID to BUF. These writes have no effect.
DEVSEL[3:0] bits (Device Select)
In host controller mode, the DEVSEL[3:0] bits specify the address of the target device for USB communication. Set up
the device address in the associated DEVADDn (n = 0 to 5) register first, and then set these bits to the corresponding
value. To set the DEVSEL[3:0] bits to 0010b, for example, first set the address in the DEVADD2 register.
In device controller mode, set these bits to 0000b.
31.2.31
Pipe Cycle Control Register (PIPEPERI)
Address(es): USBFS.PIPEPERI 4009 006Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
—
—
—
IFIS
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
b2
b1
b0
IITV[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
IITV[2:0]
*1
Interval Error Detection Interval
Specifies the interval error detection timing for the selected pipe
as the nth power of 2 of the frame timing
R/W
b11 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b12
IFIS
Isochronous IN Buffer Flush
0: Do not flush buffer
1: Flush buffer.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b13 —
Note 1.
Only set the IITV[2:0] bits while PID is NAK. Before setting these bits, check that the PBUSY bit is 0, and then change the
PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit
through software is not required.
PIPEPERI selects whether the buffer is flushed or not when an interval error occurred during isochronous IN transfers,
and sets the interval error detection interval for pipes 1 to 9.
IITV[2:0] bits (Interval Error Detection Interval)
To change the IITV[2:0] bits to another value after they are set and USB communication is performed, set the
PIPEnCTR.PID[1:0] bits to 00b (NAK) and then set the PIPEnCTR.ACLRM bit to 1 to initialize the interval timer.
The IITV[2:0] bits are not provided for pipes 3 to 5. Write 000b to the bit positions of the IITV[2:0] bits associated with
pipes 3 to 5.
IFIS bit (Isochronous IN Buffer Flush)
The IFIS bit specifies whether to flush the buffer when the pipe selected in the PIPESEL. PIPESEL[3:0] bits are used for
isochronous IN transfers.
In device controller mode when the selected pipe is for isochronous IN transfers, the USBFS automatically clears the
FIFO buffer if the USBFS fails to receive the IN token from the USB host within the interval set in the IITV[2:0] bits in
terms of frames.
When double buffering is specified (PIPECFG.DBLB = 1), the USBFS only clears the data in the previously used plane.
The USBFS clears the FIFO buffer on receiving the SOF packet immediately after the frame in which the USBFS
expected to receive the IN token. Even if the SOF packet is corrupted, the FIFO buffer is cleared at the time the SOF
packet is expected to be received by using the internal interpolation function.
When the host controller function is selected, set this bit to 0. Additionally, set this bit to 0 when the selected pipe is not
for isochronous transfer.
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31.2.32
31. USB 2.0 Full-Speed Module (USBFS)
PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)
PIPEnCTR (n = 1 to 5)
Address(es): USBFS.PIPE1CTR 4009 0070h, USBFS.PIPE2CTR 4009 0072h, USBFS.PIPE3CTR 4009 0074h,
USBFS.PIPE4CTR 4009 0076h, USBFS.PIPE5CTR 4009 0078h
b15
b14
b13
b12
b11
BSTS
INBUF
M
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
ATREP ACLRM SQCLR SQSET SQMO PBUSY
M
N
0
0
0
0
0
0
b4
b3
b2
—
—
—
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: Pipe n not in use for the transaction
1: Pipe n in use for the transaction.
R
b6
SQMON
Sequence Toggle Bit
Confirmation
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set *2
Sets the sequence toggle bit for pipe n.
0: Invalid (writing 0 has no effect)
1: Set the expected value for the next transaction to DATA1.
This bit is read as 0.
R/W*1
b8
SQCLR
Sequence Toggle Bit
Clear *2
Clears the sequence toggle bit for pipe n.
0: Invalid (writing 0 has no effect)
1: Clear the expected value for the next transaction to DATA0.
This bit is read as 0.
R/W*1
b9
ACLRM
Auto Buffer Clear Mode *3
0: Disable
1: Enable (initialize all buffers).
R/W
b10
ATREPM
Auto Response Mode *2
0: Disable auto response mode
1: Enable auto response mode.
R/W
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
INBUFM
Transmit Buffer Monitor
0: No data to be transmitted is in the FIFO buffer
1: Data to be transmitted is in the FIFO buffer.
R
b15
BSTS
Buffer Status
0: Buffer access by the CPU disabled
1: Buffer access by the CPU enabled.
R
Note 1.
Note 2.
Note 3.
0
0
1
1
0: NAK response
1: BUF response (depends buffer state)
0: STALL response
1: STALL response.
Only 0 can be read.
Only set the ATREPM bit or write 1 to the SQCLR or SQSET bit while PID is NAK. Before setting these bits, check that the
PBUSY bit is 0, and then change the PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by
the USBFS, checking the PBUSY bit through software is not necessary.
Only set the ACLRM bit while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port select register.
Before setting this bit, check that the PBUSY bit is 0, then change the PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0]
bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit through software is not necessary.
PIPEnCTR can be set for any pipe selection in the PIPESEL register.
PID[1:0] bits (Response PID)
The PID[1:0] bits specify the response type for the next transaction on the selected pipe.
The default PID[1:0] setting is NAK. Change the PID[1:0] setting to BUF to use the associated pipe for USB transfer.
Table 31.7 and Table 31.8 show the basic operations of the USBFS (when there are no errors in the communication
packets) based on the PID[1:0] bit setting.
After changing the PID[1:0] setting from BUF to NAK through software during USB communication on the selected
pipe, check that the PBUSY bit is 1 to determine if USB transfer on the pipe has actually entered the NAK state. If the
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31. USB 2.0 Full-Speed Module (USBFS)
USBFS changes the PID[1:0] bits to NAK, checking the PBUSY bit through software is not required.
The USBFS changes the PIPEnCTR.PID[1:0] setting in the following cases:
The USBFS sets PID to NAK on recognizing the completion of the transfer when the selected pipe is in the
receiving direction and the PIPECFG.SHTNAK bit for the selected pipe is set to 1 by software
The USBFS sets PID to STALL (11b) on receiving a data packet with a payload exceeding the maximum packet
size of the selected pipe
The USBFS sets PID to NAK on detecting a USB bus reset in device controller mode
The USBFS sets PID to NAK on detecting a reception error, such as a CRC error, three consecutive times in host
controller mode
The USBFS sets PID to STALL (11b) on receiving the STALL handshake in host controller mode.
To specify the response type, set the PID[1:0] bits as follows:
To transition from NAK (00b) to STALL, set 10b
To transition from BUF (01b) to STALL, set 11b
To transition from STALL (11b) to NAK, set 10b and then 00b
To transition from STALL to BUF, transition to NAK and then BUF.
Table 31.7
Operation of the USBFS based on the PID[1:0] setting in host controller mode
PID[1:0] value
Transfer type
Transfer direction
(DIR bit)
00b (NAK)
Does not depend on
the setting
Does not depend on
the setting
Does not issue tokens
01b (BUF)
Bulk or interrupt
Does not depend on
the setting
Issues tokens when the DVSTCTR0.UACT bit is 1 and the FIFO
buffer associated with the selected pipe is ready for transmission
and reception.
Does not issue tokens when the DVSTCTR0.UACT bit is 0 or the
FIFO buffer associated with the selected pipe is not ready for
transmission or reception.
Isochronous
Does not depend on
the setting
Issues tokens regardless of the status of the FIFO buffer associated
with the selected pipe
Does not depend on
the setting
Does not depend on
the setting
Does not issue tokens
10b (STALL) or
11b (STALL)
Table 31.8
USBFS operation
Operation of the USBFS based on the PID[1:0] setting in device controller mode (1 of 2)
Transfer direction
(DIR bit)
PID[1:0] value
Transfer type
00b (NAK)
Bulk or interrupt
Does not depend on
the setting
Returns NAK in response to the token from the USB host
Isochronous
Does not depend on
the setting
Returns nothing in response to the token from the USB host
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Table 31.8
31. USB 2.0 Full-Speed Module (USBFS)
Operation of the USBFS based on the PID[1:0] setting in device controller mode (2 of 2)
Transfer direction
(DIR bit)
PID[1:0] value
Transfer type
01b (BUF)
Bulk
Receiving direction
(DIR = 0)
Receives data and returns ACK in response to the OUT token from
the USB host if the FIFO buffer associated with the selected pipe is
ready for reception
Interrupt
Receiving direction
(DIR = 0)
Receives data and returns ACK in response to the OUT token from
the USB host if the FIFO buffer associated with the selected pipe is
ready for reception
Bulk or interrupt
Transmitting direction
(DIR = 1)
Transmits data in response to the token from the USB host if the
FIFO buffer associated with the selected pipe is ready for
transmission. Otherwise, returns NAK.
Isochronous
Receiving direction
(DIR = 0)
Receives data in response to the OUT token from the USB host if the
FIFO buffer associated with the selected pipe is ready for reception.
Otherwise, discards the data.
Isochronous
Transmitting direction
(DIR = 1)
Transmits data in response to the token from the USB host if the
associated FIFO buffer is ready for transmission. Otherwise,
transmits a zero-length packet.
Bulk or interrupt
Does not depend on
the setting
Returns STALL in response to the token from the USB host
Isochronous
Does not depend on
the setting
Returns nothing in response to the token from the USB host
10b (STALL) or
11b (STALL)
USBFS operation
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether the selected pipe is being used for the current transaction.
The USBFS changes the PBUSY bit from 0 to 1 at the start of the USB transaction for the selected pipe, and changes the
PBUSY bit from 1 to 0 on the completion of one transaction.
Reading the PBUSY bit by software after PID is set to NAK allows you to check whether changing the pipe setting is
possible. For details, see section 31.3.4.1, Pipe control register switching procedures.
SQMON bit (Sequence Toggle Bit Confirmation)
The SQMON bit indicates the expected value of the sequence toggle bit for the next transaction of the selected pipe.
When the selected pipe is not the isochronous transfer type, the USBFS toggles the SQMON flag on successful
completion of the transaction. However, the USBFS does not toggle the SQMON flag when a DATA-PID mismatch
occurs during transfer in the receiving direction.
SQSET bit (Sequence Toggle Bit Set)
Setting the SQSET bit to 1 through software causes the USBFS to set DATA1 as the expected value of the sequence
toggle bit for the next transaction on the selected pipe. The USBFS clears the SQSET bit to 0.
SQCLR bit (Sequence Toggle Bit Clear)
Setting the SQCLR bit to 1 through software causes the USBFS to clear the expected value of the sequence toggle bit for
the next transaction on the selected pipe to DATA0. The USBFS clears the SQCLR bit to 0.
ACLRM bit (Auto Buffer Clear Mode)
The ACLRM bit enables or disables auto buffer clear mode for the selected pipe. To completely clear the data in the
FIFO buffer allocated to the selected pipe, write 1 and then 0 to the ACLRM bit continuously.
Table 31.9 shows the data cleared by writing 1 and 0 to the ACLRM bit continuously and the cases in which this
processing is required.
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Table 31.9
Number
31. USB 2.0 Full-Speed Module (USBFS)
Data cleared by the USBFS when ACLRM = 1
Data cleared by setting the ACLRM bit
Situations requiring data clear
1
All data in the FIFO buffer allocated to the selected pipe (two
FIFO buffers in double buffer mode)
When initializing the selected pipe
2
Interval count value when the selected pipe is the isochronous
transfer type
When resetting the interval count value
3
Internal flags related to the PIPECFG.BFRE bit
When changing the PIPECFG.BFRE setting
4
FIFO buffer toggle control
When changing the PIPECFG.DBLB setting
5
Internal flags related to the transaction count
When forcing the transaction count function to terminate
ATREPM bit (Auto Response Mode)
The ATREPM bit enables or disables auto response mode for the selected pipe.
This bit can be set to 1 in device controller mode when the selected pipe is the bulk transfer type. When the bit is set to 1,
the USBFS responds to the token from the USB host as follows:
When the selected pipe is set for bulk IN transfers (PIPECFG.TYPE[1:0] = 01b and PIPECFG.DIR = 1):
a. When the ATREPM bit = 1 and PID = BUF, the USBFS transmits a zero-length packet in response to the IN
token.
b. The USBFS updates (allows toggling of) the sequence toggle bit (DATA-PID) each time the USBFS receives
ACK from the USB host. In a single transaction, the IN token is received, a zero-length packet is transmitted,
and then ACK is received. The USBFS does not generate the BRDY or BEMP interrupt.
When the selected pipe is set for bulk OUT transfers (PIPECFG.TYPE[1:0] = 01b and PIPECFG.DIR = 0):
When the ATREPM bit = 1 and PID = BUF, the USBFS returns NAK in response to the OUT token and generates
an NRDY interrupt.
For USB communication in auto response mode, set the ATREPM bit to 1 while the FIFO buffer is empty. Do not write
to the FIFO buffer during USB communication in auto response mode. When the selected pipe uses isochronous transfer,
always set this bit to 0.
In host controller mode, always set the ATREPM bit to 0.
INBUFM bit (Transmit Buffer Monitor)
The INBUMFM bit indicates the FIFO buffer status for the selected pipe in the transmitting direction.
When the selected pipe is set in the transmitting direction (PIPECFG.DIR = 1), the USBFS sets this bit to 1 when the
CPU or DMA/DTC completes writing data to at least one FIFO buffer plane.
The USBFS sets this bit to 0 when the USBFS completes transmission of the data from the FIFO buffer plane to which
all the data is written. In double buffer mode (PIPECFG.DBLB = 1), the USBFS sets the INBUFM bit to 0 when the
USBFS completes transmission of the data from the two FIFO buffer planes before the CPU or DMA/DTC completes
writing data to one FIFO buffer plane.
The INBUFM bit indicates the same value as the BSTS bit when the selected pipe is in the receiving direction
(PIPECFG.DIR = 0).
BSTS bit (Buffer Status)
The BSTS bit indicates the FIFO buffer status for the selected pipe.
The function of the BSTS bit depends on the PIPECFG.DIR, PIPECFG.BFRE, and DnFIFOSEL.DCLRM settings, as
shown in Table 31.10.
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Table 31.10
31. USB 2.0 Full-Speed Module (USBFS)
BSTS bit operation
DIR value
BFRE value
DCLRM value
BSTS bit function
0
0
0
Sets to 1 when receive data can be read from the FIFO buffer, and sets to 0 on
completion of data read
1
Setting prohibited
0
Sets to 1 when receive data can be read from the FIFO buffer, and sets to 0 when
software sets the BCLR bit in the port control register to 1 after the data read is
complete
1
Sets to 1 when receive data can be read from the FIFO buffer, and sets to 0 on
completion of data read
0
0
Sets to 1 when transmit data can be written to the FIFO buffer, and sets to 0 on
completion of data write
1
Setting prohibited
1
0
Setting prohibited
1
Setting prohibited
1
1
PIPEnCTR (n = 6 to 9)
Address(es): USBFS.PIPE6CTR 4009 007Ah, USBFS.PIPE7CTR 4009 007Ch, USBFS.PIPE8CTR 4009 007Eh, USBFS.PIPE9CTR 4009 0080h
b15
b14
b13
b12
b11
b10
BSTS
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b9
b8
b7
b6
b5
ACLRM SQCLR SQSET SQMO PBUSY
N
0
0
0
0
0
b4
b3
b2
—
—
—
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: Pipe n not in use for the transaction
1: Pipe n in use for the transaction.
R
b6
SQMON
Sequence Toggle Bit
Confirmation
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set *2
Sets the sequence toggle bit for pipe n:
0: Invalid (writing 0 has no effect)
1: Set the expected value for the next transaction to DATA1.
This bit is read as 0.
R/W
*1
b8
SQCLR
Sequence Toggle Bit
Clear *2
Clears the sequence toggle bit for pipe n:
0: Invalid (writing 0 has no effect)
1: Clear the expected value for the next transaction to DATA0.
This bit is read as 0.
R/W
*1
b9
ACLRM
Auto Buffer Clear Mode *3
0: Disable
1: Enable (all buffers initialized).
R/W
0 0: NAK response
0 1: BUF response (depends on the buffer state)
1 0: STALL response
1 1: STALL response.
b14 to b10 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
Buffer Status
0: Buffer access disabled
1: Buffer access enabled.
R
Note 1.
Note 2.
Note 3.
BSTS
Only 0 can be read. Only 1 can be written.
Only write 1 to the SQCLR or SQSET bit while PID is NAK. Before setting these bits, check that the PBUSY bit is 0, and then
change the PID[1:0] bits from 01b (BUF) to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking
the PBUSY bit through software is not required.
Only set the ACLRM bit while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port select register.
Before setting this bits, check that the PIPEnCTR.PBUSY bit is 0, and then change the PIPEnCTR.PID[1:0] bits from 01b (BUF)
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31. USB 2.0 Full-Speed Module (USBFS)
to 00b (NAK). If the PID[1:0] bits are changed to 00 (NAK) by the USBFS, checking the PBUSY bit through software is not
required.
PID[1:0] bits (Response PID)
The PID[1:0] bits specify the response type for the next transaction of the selected pipe.
The default PID[1:0] setting is NAK. Change the PID[1:0] setting to BUF to use the associated pipe for USB transfer.
Table 31.7 and Table 31.8 show the basic operation (when there are no errors in the transmitted and received packets) of
the USBFS depending on the PID[1:0] setting.
After changing the PID[1:0] setting from BUF to NAK through software during USB communication on the selected
pipe, check that the PBUSY bit is 1 to see if USB transfer on the selected pipe has actually entered the NAK state. If the
USBFS changes the PID[1:0] bits to NAK, checking the PBUSY bit through software is not required.
The USBFS changes the PIPEnCTR.PID[1:0] setting in the following cases:
The USBFS sets PID to STALL (11b) on receiving a data packet with a payload exceeding the maximum packet
size of the selected pipe
The USBFS sets PID to NAK on detecting a USB bus reset in device controller mode
The USBFS sets PID to NAK on detecting a reception error, such as a CRC error, three consecutive times in host
controller mode
The USBFS sets PID to STALL (11b) on receiving the STALL handshake in host controller mode.
To specify each response type, set the PID[1:0] bits as follows:
To transition from NAK (00b) to STALL, set 10b
To transition from BUF (01b) to STALL, set 11b
To transition from STALL (11b) to NAK, set 10b and then 00b
To transition from STALL to BUF, set 00b (NAK) and then 01b (BUF).
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether the selected pipe is being used for the current transaction.
The USBFS changes the PBUSY bit from 0 to 1 at the start of the USB transaction for the selected pipe, and changes the
PBUSY bit from 1 to 0 on completion of one transaction.
Reading the PBUSY bit through software after PID is set to NAK allows you to check whether changing the pipe setting
is possible.
SQMON bit (Sequence Toggle Bit Confirmation)
The SQMON bit indicates the expected value of the sequence toggle bit for the next transaction of the selected pipe.
The USBFS toggles the SQMON bit on successful completion of the transaction. However, the USBFS does not toggle
the SQMON bit when a DATA-PID mismatch occurs during transfer in the receiving direction.
SQSET bit (Sequence Toggle Bit Set)
Setting the SQSET bit to 1 through software causes the USBFS to set DATA1 as the expected value of the sequence
toggle bit for the next transaction on the selected pipe. The USBFS sets the SQSET bit to 0.
SQCLR bit (Sequence Toggle Bit Clear)
Setting the SQCLR bit to 1 through software causes the USBFS to clear the expected value of the sequence toggle bit for
the next transaction on the selected pipe to DATA0. The USBFS sets the SQCLR bit to 0.
ACLRM bit (Auto Buffer Clear Mode)
The ACLRM bit enables or disables auto buffer clear mode for the selected pipe. To completely clear the data in the
FIFO buffer allocated to the selected pipe, write 1 and then 0 to the ACLRM bit continuously.
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31. USB 2.0 Full-Speed Module (USBFS)
Table 31.11 shows the data cleared by writing 1 and 0 continuously to the ACLRM bit and the cases in which this
processing is required.
Table 31.11
Number
Data cleared by the USBFS when ACLRM = 1
Data cleared by setting the ACLRM bit
Situations requiring data clear
1
All data in the FIFO buffer allocated to the selected pipe
When initializing the selected pipe
2
Interval count value when the selected pipe is the
isochronous transfer type
When resetting the interval count value
3
Internal flags related to the PIPECFG.BFRE bit
When changing the PIPECFG.BFRE setting
4
Internal flags related to the transaction count
When forcing the transaction count function to terminate
BSTS bit (Buffer Status)
The BSTS bit indicates the FIFO buffer status for the selected pipe.
The function of the BSTS bit depends on the PIPECFG.DIR, PIPECFG.BFRE, and DnFIFOSEL.DCLRM settings, as
shown in Table 31.10.
31.2.33
PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 1 to 5)
Address(es): USBFS.PIPE1TRE 4009 0090h, USBFS.PIPE2TRE 4009 0094h, USBFS.PIPE3TRE 4009 0098h,
USBFS.PIPE4TRE 4009 009Ch, USBFS.PIPE5TRE 4009 00A0h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
TRENB TRCLR
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
TRCLR
Transaction Counter Clear
0: Invalid (writing 0 has no effect)
1: Clear counter value.
R/W
b9
TRENB
Transaction Counter Enable
0: Disable transaction counter
1: Enable transaction counter.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
Note:
Set each bit in PIPEnTRE while PID is NAK. Before setting these bits after changing the PIPEnCTR.PID[1:0] bits for the
selected pipe from BUF to NAK, check that the PIPEnCTR.PBUSY bit is 0. However, if the PID[1:0] bits are changed to NAK by
the USBFS, checking the PBUSY bit through software is not necessary.
TRCLR bit (Transaction Counter Clear)
When the TRCLR bit is set to 1, the USBFS clears the value of the transaction counter associated with the selected pipe
and then sets the TRCLR bit to 0.
TRENB bit (Transaction Counter Enable)
The TRENB bit enables or disables the transaction counter.
For receiving pipes, setting the TRENB bit to 1 after setting the total number of the packets to be received in the
PIPEnTRN.TRNCNT[15:0] bits through software allows the USBFS to control hardware on having received the number
of packets equal to the TRNCNT[15:0] setting, as follows:
When the PIPECFG.SHTNAK bit is 1, the USBFS changes the PID bits to NAK for the associated pipe on having
received the number of packets equal to the TRNCNT[15:0] setting
When the PIPECFG.BFRE bit is 1, the USBFS asserts the BRDY interrupt on having received the number of
packets equal to the TRNCNT[15:0] setting and then reading the last received data.
For transmitting pipes, set the TRENB bit to 0.
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31. USB 2.0 Full-Speed Module (USBFS)
When the transaction counter is not used, set this bit to 0. When the transaction counter is used, set the TRNCNT[15:0]
bits before setting this bit to 1. Set this bit to 1 before receiving the first packet to be counted by the transaction counter.
31.2.34
PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5)
Address(es): USBFS.PIPE1TRN 4009 0092h, USBFS.PIPE2TRN 4009 0096h, USBFS.PIPE3TRN 4009 009Ah,
USBFS.PIPE4TRN 4009 009Eh, USBFS.PIPE5TRN 4009 00A2h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
TRNCNT[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
TRNCNT[15:0]
Transaction Counter
When written to, this bit specifies the total packets
(number of transactions) to be received by the selected
pipe.
When read from, when PIPEnTRE.TRENB is 0, this bit
indicates the specified number of transactions.
When PIPEnTRE.TRENB is 1, this bit indicates the
current transaction count.
R/W
The PIPEnTRN registers retain their settings during a USB bus reset.
TRNCNT[15:0] bits (Transaction Counter)
The USBFS increments the value of the TRNCNT[15:0] bits by 1 when all of the following conditions are satisfied on
receiving the packet:
The PIPEnTRE.TRENB bit = 1
(TRNCNT[15:0] set value ≠ current counter value + 1) on receiving the packet
The payload of the received packet agrees with the PIPEMAXP.MXPS[8:0] setting.
The USBFS clears the value of the TRNCNT[15:0] bits to 0 when any of the following conditions are satisfied:
All of the following conditions are satisfied:
The PIPEnTRE.TRENB bit = 1
(TRNCNT[15:0] set value = current counter value + 1) on receiving the packet
The payload of the received packet agrees with the PIPEMAXP.MXPS[8:0] setting.
Both of the following conditions are satisfied:
The PIPEnTRE.TRENB bit = 1
The USBFS received a short packet.
Both of the following conditions are satisfied:
The PIPEnTRE.TRENB bit = 1
The PIPEnTRE.TRCLR bit was set to 1 by software.
For transmitting pipes, set the TRNCNT[15:0] bits to 0. When the transaction counter is not used, set the TRNCNT[15:0]
bits to 0.
Setting the number of transactions to be transferred to the TRNCNT[15:0] bits is only enabled when the
PIPEnTRE.TRENB bit is 0. To set the number of transactions to be transferred, set the TRCLR bit to 1 to clear the
current counter value before setting the PIPEnTRE.TRENB bit to 1.
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31.2.35
31. USB 2.0 Full-Speed Module (USBFS)
Device Address n Configuration Register (DEVADDn) (n = 0 to 5)
Address(es): USBFS.DEVADD0 4009 00D0h, USBFS.DEVADD1 4009 00D2h, USBFS.DEVADD2 4009 00D4h,
USBFS.DEVADD3 4009 00D6h, USBFS.DEVADD4 4009 00D8h, USBFS.DEVADD5 4009 00DAh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
USBSPD[1:0]
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7, b6
USBSPD[1:0]
Transfer Speed of Communication
Target Device
b7 b6
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: Do not use DEVADDn
1: Low-speed
0: Full-speed
1: Setting prohibited.
The DEVADDn register specifies the transfer speed of the peripheral device that is the communication target for pipes 0
to 9.
In host controller mode, set all the DEVADDn bits before starting communication with any pipes. Only change the bits in
DEVADDn when no valid pipes are using the bit settings. A valid pipe is defined as one that satisfies both of the
following conditions:
DEVADDn is selected in the DEVSEL[3:0] bits
The PID[1:0] bits are set to BUF for the selected pipe, or the selected pipe is the DCP with the DCPCTR.SUREQ bit
set to 1.
In device controller mode, set all bits in this register to 0.
USBSPD[1:0] bits (Transfer Speed of Communication Target Device)
The USBSPD[1:0] bits specify the USB transfer speed of the target peripheral device. Set these bits to 10b when a fullspeed device is connected through the hub. In host controller mode, the USBFS generates packets based on the
USBSPD[1:0] setting. In device controller mode, set these bits to 00b.
31.2.36
PHY Cross Point Adjustment Register (PHYSLEW)
Address(es): USBFS.PHYSLEW 4009 00F0h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
x
0
x
x
0
0
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
SLEWF SLEWF SLEWR SLEWR
01
00
01
00
1
1
1
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
SLEWR00
Driver Cross Point
Adjustment 00
0: Reserved
1: Host or device controller mode.
R/W
b1
SLEWR01
Driver Cross Point
Adjustment 01
0: Host or device controller mode
1: Reserved.
R/W
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31. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b2
SLEWF00
Driver Cross Point
Adjustment 00
0: Reserved
1: Host or device controller mode.
R/W
b3
SLEWF01
Driver Cross Point
Adjustment 01
0: Host or device controller mode
1: Reserved.
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b17, b16
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b19, b18
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b21, b20
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b22
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b23
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b31 to b24
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The PHYSLEW register adjusts the cross point of the driver. In both host and device controller modes, set this register
before operating the controller.
31.2.37
Deep Software Standby USB Transceiver Control/Pin Monitor Register
(DPUSR0R)
Address(es): USBFS.DPUSR0R 4009 0400h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
—
—
—
—
—
—
—
—
DVBST
S0
—
0
0
0
0
0
0
0
0
x
0
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b20
b19
b18
b17
b16
—
—
DM0
DP0
x
0
0
x
x
b4
b3
b2
b1
b0
DOVCB DOVCA
0
0
FIXPH DRPD0
Y0
0
0
—
0
RPUE0 SRPC0
0
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
SRPC0
USB Single-ended
Receiver Control
0: Disable input through DP and DM inputs
1: Enable input through DP and DM inputs.
R/W
b1
RPUE0*1
DP Pull-Up Resistor
Control
0: Disable DP pull-up resistor
1: Enable DP pull-up resistor.
R/W
b2
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b3
DRPD0*1
D+/D- Pull-Down Resistor
Control
0: Disable DP/DM pull-down resistor
1: Enable DP/DM pull-down resistor.
R/W
b4
FIXPHY0
USB Transceiver Output
Fix
0: Fix outputs in Normal mode and on return from Deep Software
Standby mode
1: Fix outputs on transition to Deep Software Standby mode.
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
DP0
USB D+ Input
Indicates D+ input signal on the USBFS side
R
b17
DM0
USB D- Input
Indicates D- input signal on the USBFS side
R
b19, b18
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b20
DOVCA0
USB OVRCURA Input
Indicates OVRCURA input signal on the USBFS side
R
b21
DOVCB0
USB OVRCURB Input
Indicates OVRCURB input signal on the USBFS side
R
b22
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b23
DVBSTS0
USB VBUS Input
Indicates VBUS input signal on the USBFS side
R
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
Note 1.
Use this bit during operation in Deep Software Standby mode. For details, see section 31.3.1.5, Release from deep software
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31. USB 2.0 Full-Speed Module (USBFS)
standby mode because of USB suspend/resume interrupts.
SRPC0 bit (USB Single-ended Receiver Control)
The SRPC0 bit controls the D+ and D- inputs of the USB transceiver. This bit is only valid when the FIXPHY0 bit is 1.
FIXPHY0 bit (USB Transceiver Output Fix)
The FIXPHY0 bit keeps the outputs of the USB transceiver disabled.
31.2.38
Deep Software Standby USB Suspend/Resume Interrupt Register (DPUSR1R)
Address(es): USBFS.DPUSR1R 4009 0404h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
—
—
—
—
—
—
—
—
DVBIN
T0
—
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
DVBSE
0
—
0
0
0
0
0
0
0
0
0
0
b20
b19
b18
—
—
0
0
0
0
0
b4
b3
b2
b1
b0
—
—
0
0
DOVR DOVR
CRB0 CRA0
DOVR DOVR
CRBE0 CRAE0
0
0
b17
b16
DMINT DPINT0
0
DMINT DPINT
E0
E0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DPINTE0
USB DP Interrupt
Enable/Clear
0: Disable recovery from Deep Software Standby mode by DP
input
1: Enable recovery from Deep Software Standby mode by DP
input.
R/W
b1
DMINTE0
USB DM Interrupt
Enable/Clear
0: Disable recovery from Deep Software Standby mode by DM
input
1: Enable recovery from Deep Software Standby mode by DM
input.
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
DOVRCRAE0
USB OVRCURA Interrupt
Enable/Clear
0: Disable recovery from Deep Software Standby mode by
OVRCURA input
1: Enable recovery from Deep Software Standby mode by
OVRCURA input.
R/W
b5
DOVRCRBE0
USB OVRCURB Interrupt
Enable/Clear
0: Disable recovery from Deep Software Standby mode by
OVRCURB input
1: Enable recovery from Deep Software Standby mode by
OVRCURB input.
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
DVBSE0
USB VBUS Interrupt
Enable/Clear
0: Disable recovery from Deep Software Standby mode by VBUS
input
1: Enable recovery from Deep Software Standby mode by VBUS
input.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
DPINT0
USB DP Interrupt Source
Recovery
0: System has not recovered from Deep Software Standby mode
1: System recovered from Deep Software Standby mode because
of DP.
R
b17
DMINT0
USB DM Interrupt Source
Recovery
0: System has not recovered from Deep Software Standby mode
1: System recovered from Deep Software Standby mode because
of DM input.
R
b19, b18
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b20
DOVRCRA0
USB OVRCURA Interrupt
Source Recovery
0: System has not recovered from Deep Software Standby mode
1: System recovered from Deep Software Standby mode because
of OVRCURA input.
R
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31. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b21
DOVRCRB0
USB OVRCURB Interrupt
Source Recovery
0: System has not recovered from Deep Software Standby mode
1: System recovered from Deep Software Standby mode because
of OVRCURB input.
R
b22
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b23
DVBINT0
USB VBUS Interrupt
Source Recovery
0: System has not recovered from Deep Software Standby mode
1: System recovered from Deep Software Standby mode because
of VBUS input.
R
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b24 —
DPINTE0 bit (USB DP Interrupt Enable/Clear)
The DPINET0 bit enables or disables triggering of recovery from Deep Software Standby mode by the DP input of the
USBFS. Writing 0 to this bit while the DPINT0 bit is 1 sets the DPINT0 bit to 0.
DMINTE0 bit (USB DM Interrupt Enable/Clear)
The DMINTE0 bit enables or disables triggering of recovery from Deep Software Standby mode by the DM input of the
USBFS. Writing 0 to this bit while the DMINT0 bit is 1 clears the DMINTE0 bit to 0.
DOVRCRAE0 bit (USB OVRCURA Interrupt Enable/Clear)
The DOVRCRAE0 bit enables or disables triggering of recovery from Deep Software Standby mode by the OVRCURA
input of the USBFS. Writing 0 to this bit while the DOVRCRA0 bit is 1 clears the DOVRCRAE0 bit to 0.
DOVRCRBE0 bit (USB OVRCURB Interrupt Enable/Clear)
The DOVRCRBE0 bit enables or disables triggering of recovery from Deep Software Standby mode by the OVRCURB
input of the USBFS. Writing 0 to this bit while the DOVRCRB0 bit is 1 clears the DOVRCRB0 bit to 0.
DVBSE0 bit (USB VBUS Interrupt Enable/Clear)
The DVBSE0 bit enables or disables triggering of recovery from Deep Software Standby mode by the VBUS input of the
USBFS. Writing 0 to this bit while the DVBINT0 bit is 1 clears the DVBINT0 bit to 0.
DPINT0 bit (USB DP Interrupt Source Recovery)
The DPINT0 bit indicates that the system has returned from Deep Software Standby mode because of the DP input of the
USBFS. This recovery is only enabled when the DPINTE0 bit is 1. Writing 0 to the DPINTE0 bit while this bit is 1 clears
this bit to 0.
DMINT0 bit (USB DM Interrupt Source Recovery)
The DMINT0 bit indicates that the system has returned from Deep Software Standby mode because of the DM input of
the USBFS. This recovery is only enabled when the DMINTE0 bit is 1. Writing 0 to the DPINTE0 bit while this bit is 1
clears this bit to 0.
DOVRCRA0 bit (USB OVRCURA Interrupt Source Recovery)
The DOVRCRA0 bit indicates that the system has returned from Deep Software Standby mode because of the
OVRCURA input of the USBFS. This recovery is only enabled when the DOVRCRAE0 bit is 1. Writing 0 to the
DOVRCRAE0 bit while this bit is 1 clears this bit to 0.
DOVRCRB0 bit (USB OVRCURB Interrupt Source Recovery)
The DOVRCRB0 bit indicates that the system has returned from Deep Software Standby mode because of the
OVRCURB input of the USBFS. This recovery is only enabled when the DOVRCRBE0 bit is 1. Writing 0 to the
DOVRCRBE0 bit while this bit is 1 clears this bit to 0.
DVBINT0 bit (USB VBUS Interrupt Source Recovery)
The DVBINT0 bit indicates that the system has returned from Deep Software Standby mode because of the VBUS input
of the USBFS. This recovery is only enabled when the DVBSE0 bit is 1. Writing 0 to the DVBSE0 bit while this bit is 1
clears this bit to 0.
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31.3
31. USB 2.0 Full-Speed Module (USBFS)
Operation
31.3.1
System Control
This section describes register settings required for initializing the USBFS and controlling power consumption.
31.3.1.1
Setting data to the USBFS registers
Setting the SYSCFG.USBE bit to 1 after starting the clock supply (SYSCFG.SCKE bit = 1) enables and starts USBFS
operation.
31.3.1.2
Selecting the controller function
The USBFS can operate as either a host or device controller.
Use the SYSCFG.DCFM bit to select one of these USBFS functions. The DCFM bit must be changed in the initial
settings immediately after a reset or in the D+ pull-up-disabled state (SYSCFG.DPRPU bit = 0) and D+ and D- pulldown-disabled state (SYSCFG.DRPD bit = 0).
31.3.1.3
Controlling the USB data bus using resistors
The USBFS provides pull-up and pull-down resistors for the D+ and D- lines. Pull these lines up or down by setting the
SYSCFG.DPRPU and DRPD bits.
In device controller mode, confirm that connection to the USB host is made, and then set the SYSCFG.DPRPU bit to 1
and pull up the D+ line (in full-speed communication).
When the SYSCFG.DPRPU bit is set to 0 during communication with a PC, the USBFS disables the pull-up resistor of
the USB data line, thereby notifying the USB host of disconnection.
In host controller mode, set the SYSCFG.DRPD bit to 1 to pull down the D+ and D- lines.
Table 31.12
USB data bus resistor control
SYSCFG register settings
USB data bus control
DRPD bit
DPRPU bit
D-
D+
Function
0
0
Open
Open
When resistors not used
0
1
Open
Pull-up
When operating as a device controller at full-speed
1
0
Pull-down
Pull-down
When operating as a host controller
1
1
—
—
Setting prohibited
31.3.1.4
Example external connection circuits
Figure 31.2 shows an example OTG connection in the self-powered system. The USBFS controls the pull-up resistor of
the D+ line and the pull-down resistor of D+ and D- lines. Select pull-up and pull-down for the lines in the
SYSCFG.DPRPU and SYSCFG.DRPD bits. In device controller mode, the pull-up resistor of USB data line is disabled if
SYSCFG.DPRPU bit is set to 0 while communicating with the USB host. The USBFS can use this to notify the USB host
of a device disconnect.
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31. USB 2.0 Full-Speed Module (USBFS)
External connection
MCU
OTG power supply
IC
USB_EXICEN
USB_VBUSEN
USB_OVRCURA
USB_OVRCURB
USB_ID
SHDN
OFFVBUS
STATUS1
STATUS2
ID_OUT
ID_IN
VBUS
USB transceiver
USB
AB connector
1.5 k
ID
USB_DP
27
VBUS
D+
USB_DM
D–
27
15.0 k
Figure 31.2
15.0 k
Example OTG connection in a self-powered system
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31. USB 2.0 Full-Speed Module (USBFS)
Figure 31.3 shows an example device connection in a self-powered system.
External connection
MCU
5V-tolerant buffer
15 k
USB_VBUS*1
1.0 µF
USB
transceiver
30 k
USB
B connector
1.5 k
USB_DP
27
VBUS
D+
USB_DM
D–
27
Note 1. The VBUS (5 V) can be directly connected to the MCU if
the VCC power supply of the MCU is not turned off when
the USB is connected. If the VCC power supply of the
MCU is turned off, the VBUS should be less than 3.6 V.
Figure 31.3
Example device connection in a self-powered system
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31. USB 2.0 Full-Speed Module (USBFS)
Figure 31.4 shows an example host connection.
External connection
MCU
USB_VBUSEN
Non-OTG
powersupply IC
for USB
host
USB_OVRCURA
USB transceiver
VBUS
USB
A connector
USB_DP
27
VBUS
D+
USB_DM
D–
27
15.0 k
15.0 k
Figure 31.4
Example host connection
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31. USB 2.0 Full-Speed Module (USBFS)
Figure 31.5 shows an example device connection in a bus-powered system.
External connection
System power
supply (3.3 V)
MCU
Each system power
supply (3.3 V)
Regulator
USB
B connector
VBUS
USB_VBUS
USB
transceiver
1.5 k
USB_DP
27
D+
USB_DM
D–
27
Figure 31.5
Example device connection in a bus-powered state
The examples of external circuits given in this section are simplified circuits, and their operation in every system is not
guaranteed.
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31.3.1.5
31. USB 2.0 Full-Speed Module (USBFS)
Release from deep software standby mode because of USB suspend/resume
interrupts
Deep Software Standby mode can be canceled by a USB suspend/resume interrupt. USB suspend/resume interrupts are
detected by the USB resume detecting unit, which controls and monitors the USB I/O pins to detect the interrupts.
Figure 31.6 shows a schematic diagram of the connection between the USB resume detecting unit and the USB I/O pins.
MCU
USB_EXICEN
USB_VBUSEN
Port outputs are retained
USB_OVRCURA
USB_OVRCURB
USB_VBUS
USB transceiver
USB resume detecting unit
1.5 k
DPUSR0R.FIXPHY0
USB_DP
USB_DM
15.0 k
15.0 k
DPUSR0R.SRPC0
Figure 31.6
Connection between the USB resume detecting unit and the USB I/O pins
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31. USB 2.0 Full-Speed Module (USBFS)
Table 31.13 shows the USB suspend and resume interrupt sources and their associated I/O pins.
Table 31.13
USB suspend and resume interrupt sources and their associated I/O pins
USB operating mode
Source
Pin name
Device, OTG
Resume
USB_DP
Host, OTG
Attach or detach
USB_DP, USB_DM
Device
Attach or detach
USB_VBUS
Host
Overcurrent detection
USB_OVRCURA
OTG
Overcurrent detection
USB_OVRCURA, USB_OVRCURB
Figure 31.7 shows the flow for setting the USBFS when entering Deep Software Standby mode from either host or
device controller mode. Figure 31.8 shows the flow for setting the USBFS when canceling Deep Software Standby mode
from host controller mode. Figure 31.9 shows the flow for setting the USBFS when canceling Deep Software Standby
mode from device controller mode.
Transition to Deep Software Standby mode
Save current USB status
USB device state
Pipe states
External control bit states
Control mask for USB outputs
Specify mask for signals to transceivers (DPUSR0R.FIXPHY0).
Control USB_DP and USB_DM (DPUSR0R.SRPC0).
Save previous values of USB output control
signals
Copy the contents of SYSCFG.DRPD to DPUSR0R.DRPD0 and
copy the contents of SYSCFG.DPRPU to DPUSR0R.RPUE0.
This prevents control signals to external modules from changing
while in Deep Software Standby mode.
Set interrupts to be detected by USB
resume detecting unit
Set USB suspend/resume interrupts as canceling sources
(enable and clear bits in DPUSR1R).
Enter Deep Software Standby mode
(execute WFI instruction)
Wait for an interrupt to cancel Deep
Software Standby mode
Figure 31.7
USBFS setup flow for transition to Deep Software Standby mode as host or device controller
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31. USB 2.0 Full-Speed Module (USBFS)
USB suspend/resume interrupt
detection
Check the recovery source and
status in each bit in DPUSR1R
Noise or recovery?
Suspended state: USB state is J-state.
Wait state for connection: USB state is SE0 state.
Overcurrent not detected.
Noise
Recovery
Rewrite saved USB status
Respecify interrupts to be detected
at USB resume detecting unit
USBE and DRPD bits in SYSCFG
of USB are included.
Enter Deep Software Standby mode
(execute WFI instruction)
Set DVCHGR.DVCHG bit
Set STSRECOV bit
Clear DVCHG bit
Cancel mask for USB outputs
Set I/O ports
Cancel saving of previous values of
USB output control signals
USBADDR of USB
Wait for an interrupt to cancel
the mode
Set the DVCHG bit to 0 after finishing writing to USBADDR.
Cancel mask for signals to the transceivers (DPUSR0R).
Reset ports to the status before transition to Deep Software Standby mode.
Return the values of SYSCFG to those before Deep Software Standby.
Next write 0 to DPUSR0R.DRPD0, DPUSR0R.RPUE0, and SYSCFG.DRPPU.
This cancels the saving of control signals to external modules.
To connection processing and
resume processing
Figure 31.8
USBFS setup flow for canceling Deep Software Standby mode as host controller
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31. USB 2.0 Full-Speed Module (USBFS)
USB suspend/resume interrupt
detection
Check the recovery source and
status in each bit in DPUSR1R
Suspended state: USB state is J-state.
Suspended state: VBUS state is 1.
Wait state for connection: VBUS state is 0.
Noise
Noise or recovery?
Respecify interrupts to be detected by
USB resume detecting unit
Recovery
Rewrite the saved USB information
USBE bit in SYSCFG of USB is included.
Do not set DPRPU bit.
Enter Deep Software Standby mode
(execute WFI instruction)
Set DVCHGR.DVCHG bit
Wait for an interrupt to cancel
the mode
Set USBADDR bits
Set STSRECOV bit
USBADDR of USB
Clear DVCHG bit
Set the DVCHG bit to 0 after finishing writing to USBADDR
Set DPRPU bit to 1
SYSCFG of USB
Cancel mask for USB
outputs
Cancel mask for signals to the transceivers (DPUSR0R)
Reset ports to the status before transition to Deep Software Standby mode
Set I/O ports
Cancel saving of previous values of
USB output control signals
Set the IOKEEP bit to 0.
This cancels saving of control signals to external modules.
To connection processing and
resume processing
Figure 31.9
31.3.2
USBFS setup flow for canceling Deep Software Standby mode as device controller
Interrupts
Table 31.14 lists the interrupt sources in the USBFS. When an interrupt generation condition is satisfied and the interrupt
output is enabled using the associated interrupt enable register, a USBFS interrupt request is issued to the Interrupt
Controller Unit (ICU) and an USBFS interrupt is generated.
Table 31.14
Interrupt sources (1 of 2)
Bit to be
set to 1
Name
Interrupt source
Applicable
controller
function
VBINT
VBUS interrupt
A change in the state of the USB_VBUS input pin was
detected (low to high or high to low)
Host or
device*1
INTSTS0.VBSTS
RESM
Resume interrupt
A change in the state of the USB bus was detected in
the suspended state (J-state to K-state or J-state to
SE0)
Device
—
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Table 31.14
Bit to be
set to 1
31. USB 2.0 Full-Speed Module (USBFS)
Interrupt sources (2 of 2)
Applicable
controller
function
Name
Interrupt source
SOFR
Frame number
update interrupt
In host controller mode:
An SOF packet with a different frame number was
transmitted
In device controller mode:
An SOF packet with a different frame number was
received.
Host or
device
—
DVST
Device state
transition interrupt
One of the following device state transitions was
detected:
- USB bus reset was detected
- Suspended state was detected
- SET_ADDRESS request was received
- SET_CONFIGURATION request was received
Device
INTSTS0.DVSQ[2:0]
CTRT
Control transfer
stage transition
interrupt
Device
A control transfer stage transition was detected
because of one of the following:
- Setup stage completed
- Control write transfer status stage transition occurred
- Control read transfer status stage transition occurred
- Control transfer completed
- Control transfer sequence error occurred.
INTSTS0.CTSQ[2:0]
BEMP
Buffer empty
interrupt
The buffer is empty after all FIFO buffer data was
transmitted
A packet larger than the maximum packet size was
received.
Host or
device
BEMPSTS.PIPEnBEMP
NRDY
Buffer not ready
interrupt
In host controller mode:
A STALL response was received from the peripheral
device in response to the issued token
The response from the peripheral device in response
to the issued token was not received successfully (no
response three times consecutively or packet
reception error three times consecutively)
An overrun or underrun error occurred during
isochronous transfer.
In device controller mode:
NAK was returned for an IN or OUT token while the
PID[1:0] bits were set to 01b (BUF)
A CRC error or bit stuffing error occurred during data
reception in isochronous transfer
An overrun or underrun occurred during data
reception in isochronus transfer.
Host or
device
NRDYSTS.PIPEnNRDY
BRDY
Buffer ready
interrupt
The buffer is ready (read/write state)
Host or
device
BRDYSTS.PIPEnBRDY
OVRCR
Overcurrent input
change interrupt
USB_OVRCURA or USB_OVRCURB input pin state
change was detected (low to high or high to low)
Host
INTSTS1.OVRCR
BCHG
Bus change
interrupt
USB bus state change was detected
Host or
device
SYSSTS0.LNST[1:0]
DTCH
Disconnect
Peripheral device disconnect was detected in fulldetection during fullspeed operation
speed operation
Host
DVSTCTR0.RHST[2:0]
ATTCH
Device connect
detection interrupt
J-state or K-state was detected on the USB bus for
2.5 µs continuously
This interrupt can be used to check whether
peripheral devices are connected.
Host
—
EOFERR
EOF error detection
interrupt
An EOF error was detected for a peripheral device
Host
—
SACK
Setup normal
interrupt
A setup transaction normal response (ACK) was
received
Host
—
SIGN
Setup error interrupt A setup transaction error (no response or ACK packet
corruption) was detected three consecutive times
Host
—
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Note 1.
31. USB 2.0 Full-Speed Module (USBFS)
Although this interrupt can be generated in host controller mode, it is not usually used in this mode.
Figure 31.10 shows the circuits related to the USBFS interrupts.
USBFS_USBR
USB bus reset detected
INTENB0
INTSTS0
VBSE
Set_Address detected
VBINT
Set_Configuration
detected
RSME
USBFS_USBI
RESM
SOFE
Suspended state detected
SOFR
Control write data stage
DVSE
DVST
Control read data stage
CTRE
CTRT
Control transfer end
BEMPE
BEMP
Control transfer error
NRDYE
NRDY
Control transfer setup receive
BRDYE
BRDY
Edge/level
detector
BEMP Interrupt Enable Register
OVRCRE
OVRCR
b9
b1
b0
BCHGE
b9
BCHG
DTCHE
BEMP interrupt
Status Register
DTCH
ATTCHE
b1
ATTCH
b0
EOFERRE
EOFERR
NRDY Interrupt Enable Register
b9
SIGNE
b1
b0
SIGN
SACKE
b9
SACK
INTENB1
NRDY Interrupt
Status Register
INTSTS1
b1
D0FIFOSEL
b0
DREQE
BRDY Interrupt Enable Register
DMA
transfer
request 0
USBFS_D0FIFO
D1FIFOSEL
b9
b1
b0
b9
DREQE
USBFS_D1FIFO
DMA
transfer
request 1
BRDY Interrupt
Status Register
b1
b0
Figure 31.10
USBFS interrupt-related circuits
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31. USB 2.0 Full-Speed Module (USBFS)
Table 31.15 shows the interrupts generated by the USBFS.
Table 31.15
USBFS interrupts
Interrupt name
Interrupt status flag
DTC
activation
DMAC
activation
USBFS_D0FIFO
DMA transfer request 0
Possible
Possible
USBFS_D1FIFO
DMA transfer request 1
Possible
Possible
USBFS_USBI
VBUS interrupt, resume interrupt, frame number update interrupt,
device state transition interrupt, control transfer stage transition
interrupt, buffer empty interrupt, buffer not ready interrupt, buffer ready
interrupt, overcurrent input change interrupt, bus change interrupt,
disconnect detection interrupt during full-speed operation, device
connect detection interrupt, EOF error detection interrupt, normal setup
operation interrupt, and setup error interrupt
Not possible
Not possible
USBFS_USBR
VBUS interrupt, resume interrupt, overcurrent input change interrupt,
and bus change interrupt
Not possible
Not possible
31.3.3
31.3.3.1
Priority
High
Low
—
Interrupt Descriptions
BRDY interrupt
The BRDY interrupt is generated in both host and device controller modes. This section describes the conditions in
which the USBFS sets the associated bit in BRDYSTS to 1. Under these conditions, the USBFS generates a BRDY
interrupt if software has set the bit in BRDYENB associated with the given pipe to 1 and the INTENB0.BRDYE bit to 1.
The conditions for generating and clearing the BRDY interrupt depend on the SOFCFG.BRDYM and PIPECFG.BFRE
settings for each pipe as follows:
(1)
When SOFCFG.BRDYM = 0 and PIPECFG.BFRE = 0
With these settings, the BRDY interrupt indicates that the FIFO port is accessible.
On any of the following conditions, the USBFS generates an internal BRDY interrupt request trigger and sets the
BRDYSTS.PIPEnBRDY bit associated with the selected pipe to 1.
(a)
For transmitting pipes
When the DIR bit is changed from 0 to 1 by software
When packet transmission is complete for a pipe while write-access from the CPU to the FIFO buffer for the pipe is
disabled (when the BSTS bit is read as 0)
When one FIFO buffer is empty on completion of writing data to the other FIFO buffer in double buffer mode
No request trigger is generated until the completion of writing data to the currently-written FIFO buffer even if
transmission to the other FIFO buffer is complete
When the hardware flushes the buffer of the pipe for isochronous transfers
When 1 is written to the PIPEnCTR.ACLRM bit, which causes the FIFO buffer to transition from the write-disabled
to write-enabled state.
No request trigger is generated for the DCP, that is, during data transmission for control transfers.
(b)
For receiving pipes
When packet reception is successfully complete, enabling the FIFO buffer to be read while read-access from the
CPU to the FIFO buffer for the given pipe is disabled (when the BSTS bit is read as 0). No request trigger is
generated for transactions in which a DATA-PID mismatch has occurred.
When one FIFO buffer is read-enabled on completion of reading data from the other FIFO buffer in double buffer
mode. No request trigger is generated until the completion of reading data from the currently-read FIFO buffer,
even if reception by the other FIFO buffer is complete.
In device controller mode, the BRDY interrupt is not generated in the status stage of control transfers. The PIPEnBRDY
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31. USB 2.0 Full-Speed Module (USBFS)
interrupt status of the selected pipe can be set to 0 by writing 0 to the associated PIPEnBRDY bit through software. In
this case, the other PIPEnBRDY bit should be set to 1.
Clear the BRDY status before accessing the FIFO buffer.
(2)
When SOFCFG.BRDYM = 0 and PIPECFG.BFRE = 1
With these settings, the USBFS generates a BRDY interrupt on the completion of reading all the data for a single transfer
using the receiving pipe, and sets the bit in BRDYSTS associated with the pipe to 1.
On any of the following conditions, the USBFS determines that the last data for a single transfer was received:
When a short packet including a zero-length packet is received
When the PIPEn Transaction Counter Register (PIPEnTRN) is used and the number of packets specified in the
PIPEnTRN.TRNCNT[15:0] bits are completely received.
When the data is completely read after any of the specified conditions is satisfied, the USBFS determines that all data for
a single transfer is completely read.
When a zero-length packet is received while the FIFO buffer is empty, the USBFS determines that all data for a single
transfer is completely read when the FRDY bit in the FIFO port control register is 1 and the DTLN[8:0] bits are 0. In this
case, to start the next transfer, write 1 to the BCLR bit in the associated port control register through software. With these
settings, the USBFS does not detect a BRDY interrupt for the transmitting pipe.
The PIPEnBRDY interrupt status of a pipe can be set to 0 by writing 0 to the associated BRDYSTS.PIPEnBRDY bit
through software. In this case, the other PIPEnBRDY bit should be set to 1.
In this mode, do not change the PIPECFG.BFRE bit setting until all data for a single transfer is processed. When it is
necessary to change the PIPECFG.BFRE bit before completion of processing, all FIFO buffers for the pipe must be
cleared using the PIPEnCTR.ACLRM bit.
(3)
When SOFCFG.BRDYM = 1 and PIPECFG.BFRE = 0
With these settings, the BRDYSTS.PIPEnBRDY values are linked to the BSTS bit setting for each pipe. In other words,
the BRDY interrupt status bits (PIPEnBRDY) are set to 1 or 0 by the USB depending on the FIFO buffer status.
(a)
For transmitting pipes
The BRDY interrupt status bits are set to 1 when the FIFO buffer is ready for write access, and are set to 0 when it is not
ready. The BRDY interrupt is not generated for the DCP in the transmitting direction even when it is ready for write
access.
(b)
For receiving pipes
The BRDY interrupt status bits set to 1 when the FIFO buffer is ready for read access, and set to 0 when all data is read
(not ready for read access).
When a zero-length packet is received while the FIFO buffer is empty, the associated bit is set to 1 and the BRDY
interrupt is continuously generated until software writes 1 to BCLR. With this setting, the PIPEnBRDY bit cannot be set
to 0 by software.
When the SOFCFG.BRDYM bit is set to 1, set the PIPECFG.BFRE bit for all pipes to 0.
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31. USB 2.0 Full-Speed Module (USBFS)
Figure 31.11 shows the timing of BRDY interrupt generation.
(1) Example of zero-length packet reception or data packet reception when BFRE = 0 (single-buffer mode)
*1
Token packet
USB bus
FIFO buffer status
Data packet
ACK handshake
Ready for reception
Ready for read access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
A BRDY interrupt is generated because the
FIFO buffer becomes ready for read access.*2
(2) Example of data packet reception when BFRE = 1 (single-buffer mode)
USB bus
Token packet
FIFO buffer status
data packet
ACK handshake
*1
Ready for reception
Ready for read access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
The FIFO buffer becomes
ready for read access*2
A BRDY interrupt is generated
because the transfer has ended*3
(3) Example of packet transmission (single-buffer mode)
*1
USB bus
Token packet
FIFO buffer status
Data packet
ACK handshake
Ready for transmission
Ready for write access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
A BRDY interrupt is generated
because the FIFO buffer
becomes ready for write access
Packet transmitted by host device
Packet transmitted by a function device
Note 1. The ACK handshake is not used in isochronous transfers.
Note 2. The FIFO buffer becomes ready for read access under the following condition:
When a packet is received while no data remains unread in the FIFO buffer in the CPU.
Note 3. A transfer ends under either of the following conditions:
(1) When a short packet including a zero-length packet is received.
(2) When the number of packets specified in the transaction counter are received.
Figure 31.11
Timing of BRDY interrupt generation
The condition for clearing the INTSTS0.BRDY bit depends on the SOFCFG.BRDYM bit setting, as shown in Table
31.16.
Table 31.16
BRDYM bit
Conditions for clearing the BRDY bit
Condition for clearing BRDY bit
0
When all bits in BRDYSTS are set to 0 by software
1
When the BSTS bits for all pipes become 0
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31.3.3.2
31. USB 2.0 Full-Speed Module (USBFS)
NRDY interrupt
On generating an internal NRDY interrupt request for the pipe whose PID bits are set to BUF by software, the USBFS
sets the associated PIPEnNRDY bit in NRDYSTS to 1. If the associated bit in NRDYENB is set to 1 by software, the
USBFS sets the INTSTS0.NRDY bit to 1 and generates a USBFS interrupt.
This section describes the conditions in which the USBFS generates the internal NRDY interrupt request for a given
pipe.
The internal NRDY interrupt request is not generated during setup transaction execution in host controller mode. During
setup transactions in host controller mode, the SACK or SIGN interrupt is detected.
The internal NRDY interrupt request is not generated during status stage execution of the control transfer in device
controller mode.
(1)
In host controller mode
(a)
For transmitting pipes
On any of the following conditions, the USBFS detects an NRDY interrupt:
For isochronous transfer pipes, when the time to issue an OUT token comes while there is no data to be transmitted
in the FIFO buffer. In this case, the USBFS transmits a zero-length packet following the OUT token and sets the
associated NRDYSTS.PIPEnNRDY bit and the FRMNUM.OVRN bit to 1.
During communications other than setup transactions on pipes not used for isochronous transfers, when any
combination of the following two cases occur three consecutive times:
No response is returned from the peripheral device (when timeout is detected before detection of the handshake
packet from the peripheral device
An error is detected in the packet from the peripheral device. In this case, the USBFS sets the associated
PIPEnNRDY bit to 1 and changes the associated PID[1:0] setting for the pipe to NAK.
During communications other than setup transactions, when the STALL handshake is received from the peripheral
device. In this case, the USBFS sets the associated PIPEnNRDY bit to 1 and changes the PID[1:0] setting for the
associated pipe to STALL (11b).
(b)
For receiving pipes
For isochronous transfer pipes, when the time to issue an IN token comes but there is no space available in the FIFO
buffer. In this case, the USBFS discards the received data for the IN token and sets the PIPEnNRDY bit associated
with the pipe and the OVRN bit to 1. When a packet error is detected in the received data for the IN token, the
USBFS also sets the FRMNUM.CRCE bit to 1.
For non-isochronous transfer pipes, when any combination of the following two cases occur three consecutive
times:
No response is returned from the peripheral device for the IN token issued by the USBFS (when timeout is
detected before detection of the DATA packet from the peripheral device)
An error is detected in the packet from the peripheral device. In this case, the USBFS sets the associated
PIPEnNRDY bit to 1 and changes the associated PID[1:0] setting for the pipe to NAK.
For isochronous transfer pipes, when no response is returned from the peripheral device for the IN token (when
timeout is detected before detection of the DATA packet from the peripheral device) or an error is detected in the
packet from the peripheral device. In this case, the USBFS sets the PIPEnNRDY bit associated with the pipe to 1.
The PID[1:0] setting for the pipe is not changed.
For isochronous transfer pipes, when a CRC error or a bit stuffing error is detected in the received data packet. In
this case, the USBFS sets the PIPEnNRDY bit associated with the pipe and the CRCE bit to 1.
When the STALL handshake is received. In this case, the USBFS sets the PIPEnNRDY bit associated with the pipe
to 1 and changes the PID[1:0] setting for the associated pipe to STALL.
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31. USB 2.0 Full-Speed Module (USBFS)
(2)
In device controller mode
(a)
For transmitting pipes
When an IN token is received while there is no data to be transmitted in the FIFO buffer. In this case, the USBFS
generates a NRDY interrupt request on reception of the IN token and sets the NRDYSTS.PIPEnNRDY bit to 1. For
an isochronous transfer pipe in which an interrupt is generated, the USBFS transmits a zero-length packet and sets
the FRMNUM.OVRN bit to 1.
(b)
For receiving pipes
When an OUT token is received but there is no space available in the FIFO buffer. For an isochronous transfer pipe
in which an interrupt is generated, the USBFS generates a NRDY interrupt request on reception of the OUT token
and sets the PIPEnNRDY bit to 1 and OVRN bit to 1. For a non-isochronous transfer pipe in which an interrupt is
generated, the USBFS generates a NRDY interrupt request when a NAK handshake is transferred after the data
following the OUT token is received, and sets the PIPEnNRDY bit to 1. The NRDY interrupt request is not
generated during retransmission because of a DATA-PID mismatch. In addition, the NRDY interrupt request is not
generated if an error occurs in the DATA packet.
For isochronous transfer pipes, when a token is not received successfully within an interval frame. In this case, the
USBFS generates an NRDY interrupt request when the SOF is received, and sets the PIPEnNRDY bit to 1.
Figure 31.12 shows the timing of NRDY interrupt generation in device controller mode.
(1) Example of data transmission (single-buffer mode)
*1
IN token packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
NAK handshake
Ready for write access (there is no data to be transmitted)
*3
An NRDY interrupt is generated
(2) Example of data reception: OUT token reception (single-buffer mode)
*1
OUT token packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
Data packet
NAK handshake
Ready for read access (there is no space to receive data)
*3
(CRCE bit)*3
An NRDY interrupt is generated
(3) Example of data reception: PING token reception (single-buffer mode)
PING packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
NAK handshake
Ready for read access (there is no space to receive data)
*3
An NRDY interrupt is generated
Packet transmitted by host device
Packet transmitted by a function device
Note 1. The handshake is not used in isochronous transfers.
Note 2. The CRCE and OVRN bits change only while the target pipe is set to isochronous transfers.
Note 3. The value of the PIPEnNRDY bit changes to 1 only when the PIPEnPID[1:0] bits are set to 01b (BUF response).
Figure 31.12
Timing of NRDY interrupt generation in device controller mode
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31.3.3.3
31. USB 2.0 Full-Speed Module (USBFS)
BEMP interrupt
On detecting a BEMP interrupt for the pipe whose PID bits are set to BUF by software, the USBFS sets the associated
BEMPSTS.PIPEnBEMP bit to 1. If the associated bit in BEMPENB is set to 1 by software, the USBFS sets the
INTSTS0.BEMP bit to 1 and generates a USBFS interrupt. This section describes the conditions in which the USBFS
generates an internal BEMP interrupt request.
(1)
For transmitting pipes
When the FIFO buffer of the associated pipe is empty on completion of transmission, including zero-length packet
transmission, and in single buffer mode, an internal BEMP interrupt request is generated simultaneously with the BRDY
interrupt for a non-DCP pipe. The internal BEMP interrupt request is not generated in any of the following conditions:
When the CPU or DMA/DTC has already started writing data to the FIFO buffer of the CPU on completion of
transmitting data from one FIFO buffer in double buffer mode
When the buffer is cleared (emptied) by setting the PIPEnCTR.ACLRM or the BCLR bit to 1 in the port control
register
When an IN transfer (zero-length packet transmission) is performed during the control transfer status stage in device
controller mode.
(2)
For receiving pipes
When a successfully-received data packet size exceeds the specified maximum packet size. In this case, the USBFS
generates a BEMP interrupt request, sets the associated BEMPSTS.PIPEnBEMP bit to 1, discards the received data, and
changes the associated PID[1:0] setting for the pipe to STALL (11b). The USBFS returns no response in host controller
mode, and returns STALL response in device controller mode.
The internal BEMP interrupt request is not generated in any of the following conditions:
When a CRC error or a bit stuffing error is detected in the received data
When a setup transaction is being performed:
Writing 0 to the BEMPSTS.PIPEnBEMP bit clears the status
Writing 1 to the BEMPSTS.PIPEnBEMP bit has no effect.
Figure 31.13 shows the timing of the BEMP interrupt generation in device controller mode.
(1) Example of data transmission
USB bus
*1
IN token packet
Data packet
ACK handshake
Ready for transmission
FIFO buffer status
Ready for write access
(there is no data to be
transmitted)
BEMP interrupt
(BEMPSTS.PIPEnBEMP bit)
A BEMP interrupt is generated
(2) Example of data reception
OUT token packet
USB bus
Data packet (maximum
packet size over)
STALL handshake
BEMP interrupt
(BEMPSTS.PIPEnBEMP bit)
A BEMP interrupt is generated
Packet transmitted by host device
Packet transmitted by a function device
Note 1. The handshake is not used in isochronous transfers.
Figure 31.13
Timing of BEMP interrupt generation in device controller mode
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31.3.3.4
31. USB 2.0 Full-Speed Module (USBFS)
Device state transition interrupt (device controller mode)
Figure 31.14 shows a diagram of the USBFS device state transitions. The USBFS controls device states and generates
device state transition interrupts. However, recovery from the suspended state (resume signal detection) is detected by
means of the resume interrupt. Device state transition interrupts can be enabled or disabled independently in INTENB0.
Devices whose states have changed can be checked in the INTSTS0.DVSQ[2:0] bits.
When a transition is made to the default state, a device state transition interrupt is generated after a USB bus reset is
detected.
The USBFS controls device states, and device state transition interrupts can be generated, only in device controller
mode.
Suspended state detection
(DVST is set to 1)
Suspended
state
(DVSQ = 100b)
Powered
state
(DVSQ = 000b)
Resume (RESM is set to 1)
USB bus reset detection
(DVST is set to 1)
USB bus reset detection
(DVST is set to 1)
Suspended state detection
(DVST is set to 1)
Suspended
state
(DVSQ = 101b)
Default
state
(DVSQ = 001b)
Resume (RESM is set to 1)
SetAddress
execution
(Address = 0)
(DVST is set to 1)
SetAddress execution
(DVST is set to 1)
(Address > 0)
Suspended state detection
(DVST is set to 1)
Suspended
state
(DVSQ = 110b)
Address
state
(DVSQ = 010b)
SetConfiguration
execution
(configuration value = 0)
(DVST is set to 1)
Resume (RESM is set to 1)
SetConfiguration execution
(configuration value 0)
(DVST is set to 1)
Suspended state detection
(DVST is set to 1)
Suspended
state
(DVSQ = 111b)
Configured
state
(DVSQ = 011b)
Resume (RESM is set to 1)
Note:
Figure 31.14
For a transition indicated by a solid line, the DVST bit is set to 1.
For a resume indicated by a dashed line, the RESM bit is set to 1.
Device state transitions
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31.3.3.5
31. USB 2.0 Full-Speed Module (USBFS)
Control transfer stage transition interrupt (device controller mode)
Figure 31.15 shows a diagram of the control transfer stage transitions of the USBFS. The USBFS controls the control
transfer sequence and generates control transfer stage transition interrupts. Control transfer stage transition interrupts can
be enabled or disabled independently in INTENB0. Transfer stages that have transitioned can be checked in the
INTSTS0.CTSQ[2:0] bits.
Control transfer stage transition interrupts are generated only in device controller mode. This section describes control
transfer sequence errors. If an error occurs, the DCPCTR.PID[1:0] bits are set to 1xb (STALL response).
(1)
Control read transfer errors
An OUT token is received but no data is transferred in response to the IN token at the data stage
An IN token is received at the status stage
A data packet with DATAPID = DATA0 is received at the status stage.
(2)
Control write transfer errors
An IN token is received but no ACK is returned in response to the OUT token at the data stage
A data packet with DATAPID = DATA0 is received as the first data packet at the data stage
An OUT token is received at the status stage.
(3)
Control write no data transfer errors
An OUT token is received at the status stage.
At the control write transfer data stage, if the receive data length exceeds the wLength value of the USB request, it is not
recognized as a control transfer sequence error. At the control read transfer status stage, packets other than zero-length
packets are received by an ACK response and the transfer ends normally.
When a CTRT interrupt occurs in response to a sequence error (INTSTS0.CTRT = 1), the CTSQ[2:0] = 110b value is
saved until the CTRT bit is set to 0, clearing the interrupt status. While CTSQ[2:0] = 110b is being saved, no CTRT
interrupt for ending the setup stage is generated, even if a new USB request is received. The USBFS saves the setup stage
completion status, and it generates a CTRT interrupt after the interrupt status is cleared by software.
Setup token reception
S etup token reception
C TS Q = 110b
control transfer
sequence error
5
Error
detection
Error detection and setup token
reception are enabled at all stages
in this fram e.
S etup
token reception
C TSQ = 000b
setup stage
A CK
transm ission
1
C TSQ = 001b
control read
data stage
O UT token
2
C TSQ = 010b
control read
status stage
AC K
transm ission
4
C TS Q = 000b
idle stage
4
A CK
transm ission
1
C TSQ = 011b
control w rite
data stage
IN token
3
C TSQ = 100b
control w rite
status stage
1
C TSQ = 101b
no data control
status stage
A CK
transm ission
AC K
reception
AC K
reception
N ote:
C TR T interrupts
1
Setup stage end
2
C ontrol read transfer status stage transition
3
C ontrol w rite transfer status stage transition
4
C ontrol transfer end
5
C ontrol transfer sequence error
Figure 31.15
Control transfer stage transitions
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31.3.3.6
31. USB 2.0 Full-Speed Module (USBFS)
Frame update interrupt
In host controller mode, an interrupt is generated when the frame number is updated.
In device controller mode, an SOFR interrupt is generated when the frame number is updated. The USBFS updates the
frame number and generates an SOFR interrupt if it detects a new SOF packet during full-speed operation.
31.3.3.7
VBUS interrupt
When the USB_VBUS pin level changes, a VBUS interrupt is generated. The level of the USB_VBUS pin can be
checked with the INTSTS0.VBSTS bit. Whether the host controller is connected or disconnected can be confirmed using
the VBUS interrupt. If the system is activated with the host controller connected, the first VBUS interrupt is not
generated, because there is no change in the USB_VBUS pin level.
31.3.3.8
Resume interrupt
In device controller mode, a resume interrupt is generated when the device state is the Suspend state, and the USB bus
state has changed (from J-state to K-state, or from J-state to SE0). Recovery from the Suspend state is detected by means
of the resume interrupt.
In host controller mode, no resume interrupt is generated. Use the BCHG interrupt to detect a change in the USB bus
state.
31.3.3.9
OVRCR interrupt
An OVRCR interrupt is generated when the USB_OVRCURA or USB_OVRCURB pin level has changed. The levels of
the USB_OVRCURA and USB_OVRCURB pins can be checked in the SYSSTS0.OVCMON[1:0] bits. The external
power supply IC can check whether overcurrent is detected using the OVRCR interrupt.
For OTG connections, the OVRCR interrupt allows you to check whether a change is detected in the VBUS comparator.
31.3.3.10
BCHG interrupt
A BCHG interrupt is generated when the USB bus state has changed. The BCHG interrupt can be used to detect whether
a peripheral device is connected and can also be used to detect a remote wakeup in host controller mode. The BCHG
interrupt is generated in both host and device controller modes.
31.3.3.11
DTCH interrupt
A DTCH interrupt occurs when a USB bus disconnect is detected in host controller mode. The USBFS detects bus
disconnects in compliance with the USB 2.0 specification.
On interrupt detection, all pipes in which communications are being carried out for the relevant port must be terminated
by software. The pipes enter the wait state for a bus connection to the port, waiting for an ATTCH interrupt to occur.
Regardless of the value set in the associated interrupt enable bit, the USBFS hardware:
Sets the DVSTCTR0.UACT bit for the port in which the DTCH interrupt is detected, to 0
Puts the port in which the DTCH interrupt occurred into an idle state.
31.3.3.12
SACK interrupt
A SACK interrupt is generated when an ACK response for the transmitted setup packet is received from the peripheral
device in host controller mode. The SACK interrupt can be used to confirm that the setup transaction is successfully
complete.
31.3.3.13
SIGN interrupt
A SIGN interrupt is generated when an ACK response for the transmitted setup packet is not correctly received from the
peripheral device three consecutive times in host controller mode. The SIGN interrupt can be used to detect that no ACK
response was transmitted from the peripheral device or that corruption of an ACK packet occurred.
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31.3.3.14
31. USB 2.0 Full-Speed Module (USBFS)
ATTCH interrupt
An ATTCH interrupt is generated when J-state or K-state of the full-speed signal level is detected on the USB port for
2.5 μs in host controller mode. To be more specific, an ATTCH interrupt is detected on any of the following conditions:
When K-state, SE0, or SE1 changes to J-state, and J-state continues at 2.5 µs
When J-state, SE0, or SE1 changes to K-state, and K-state continues at 2.5 µs.
31.3.3.15
EOFERR interrupt
An EOFERR interrupt occurs when the USBFS detects that communication is not complete at the EOF2 timing defined
in the USB 2.0 specification.
On interrupt detection, all pipes in which communications are being carried out for the relevant port must be terminated
by software, and the port must be re-enumerated. Regardless of the value set in the associated interrupt enable bit, the
USBFS hardware:
Sets the DVSTCTR0.UACT bit for the port in which the EOFERR interrupt is detected to 0
Puts the port in which the EOFERR interrupt is generated into the idle state.
31.3.4
Pipe Control
Table 31.17 lists the pipe settings for the USBFS. USB data transfer is performed through logical pipes that software
associates with endpoints. The USBFS provides 10 pipes that are used for data transfer. Set up the pipes based on your
system specifications.
Table 31.17
Register
name
DCPCFG
PIPECFG
DCPMAXP
PIPEMAXP
PIPEPERI
Pipe settings (1 of 2)
Bit name
Setting
Notes
TYPE
Transfer type
Pipes 1 to 9: Settable
BFRE
BRDY interrupt mode
Pipes 1 to 5: Settable
DBLB
Double buffer select
Pipes 1 to 5: Settable
DIR
Transfer direction select
IN or OUT settable
EPNUM
Endpoint number
Pipes 1 to 9: Settable
A value other than 0000b must be set when the pipe is used.
SHTNAK
Selects disabled state for
pipe when transfer ends
Pipes 1 and 2: Settable only for bulk transfers
Pipes 3 to 5: Settable
DEVSEL
Device select
Referenced only in host controller mode
MXPS
Maximum packet size
Compliant with the USB 2.0 specification
IFIS
Buffer flush
Pipes 1 and 2: Settable only for isochronous transfers
Pipes 3 to 9: Setting disabled
IITV
Interval counter
Pipes 1 and 2: Settable only for isochronous transfers
Pipes 3 to 5: Setting disabled
Pipes 6 to 9: Settable only in host controller mode
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Table 31.17
Register
name
DCPCTR
PIPEnCTR
PIPEnTRE
PIPEnTRN
31. USB 2.0 Full-Speed Module (USBFS)
Pipe settings (2 of 2)
Bit name
Setting
Notes
BSTS
Buffer status
For the DCP, receive buffer status and transmit buffer status are switched
with the ISEL bit
INBUFM
IN buffer monitor
Available only for pipes 1 to 5
SUREQ
Setup request
Settable only for the DCP and controlled in host controller mode
SUREQCLR
SUREQ clear
Settable only for the DCP and controlled in host controller mode
ATREPM
Auto response mode
Pipes 1 to 5: Settable only in device controller mode
ACLRM
Auto buffer clear
Pipes 1 to 9: Settable
SQCLR
Sequence clear
Clears the data toggle bit
SQSET
Sequence set
Sets the data toggle bit
SQMON
Sequence monitor
Monitors the data toggle bit
PBUSY
Pipe busy status
-
PID
Response PID
See section 31.3.4.6, Response PID
TRENB
Transaction counter enable
Pipes 1 to 5: Settable
TRCLR
Current transaction counter
clear
Pipes 1 to 5: Settable
TRNCNT
Transaction counter
Pipes 1 to 5: Settable
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31.3.4.1
31. USB 2.0 Full-Speed Module (USBFS)
Pipe control register switching procedures
The following bits in the pipe control registers can be changed only when USB communication is prohibited (PID =
NAK).
Do not change the following registers and bits when USB communication is enabled (PID = BUF):
Bits in DCPCFG and DCPMAXP
SQCLR and SQSET bits in DCPCTR
Bits in PIPECFG, PIPEMAXP, and PIPEPERI
ATREPM, ACLRM, SQCLR, and SQSET bits in PIPEnCTR
Bits in PIPEnTRE and PIPEnTRN.
To set these bits when USB communication is enabled (PID = BUF):
1. A request to change the bits in the pipe control register occurs.
2. Set the PID[1:0] bits associated with the pipe to NAK.
3. Wait until the associated PBUSY bit clears to 0.
4. Set the bits in the pipe control register.
The following bits in the pipe control registers can be changed only when the selected pipe information is not set in the
CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL.
Do not set the following registers when the CURPIPE[3:0] bits are set:
Bits in DCPCFG and DCPMAXP
Bits in PIPECFG, PIPEMAXP and PIPEPERI.
To change pipe information, you must set the CURPIPE[3:0] bits in the port select registers to a pipe other than the one
to be changed. For the DCP, the buffer must be cleared using the BCLR bit in the port control register after the pipe
information is changed.
31.3.4.2
Transfer types
The PIPECFG.TYPE[1:0] bits specify the following transfer types for each pipe:
DCP: No setting is necessary (fixed at control transfer)
Pipes 1 and 2: Set to bulk or isochronous transfer
Pipes 3 to 5: Set to bulk transfer
Pipes 6 to 9: Set to interrupt transfer.
31.3.4.3
Endpoint number
The PIPECFG.EPNUM[3:0] bits are used to set the endpoint number for each pipe. The DCP is fixed at endpoint 0. The
other pipes can be set from endpoint 1 to 15.
DCP: No setting is required (fixed at endpoint 0)
Pipes 1 to 9: Select and set the endpoint numbers from 1 to 15 so that the combination of the PIPECFG.DIR and
EPNUM[3:0] bits is unique.
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31.3.4.4
31. USB 2.0 Full-Speed Module (USBFS)
Maximum packet size setting
Specify the maximum packet size for each pipe in the DCPMAXP.MXPS[6:0] and PIPEMAXP.MXPS[8:0] bits. The
DCP and pipes 1 to 5 can be set to any of the maximum pipe sizes defined in the USB 2.0 specification. For pipes 6 to 9,
the maximum packet size is 64 bytes. Set the maximum packet size as follows before starting a transfer (PID = BUF):
DCP: Set to 8, 16, 32, or 64
Pipes 1 to 5: Set to 8, 16, 32, or 64 for bulk transfers
Pipes 1 and 2: Set between 1 and 256 for isochronous transfers
Pipes 6 to 9: Set between 1 and 64.
31.3.4.5
Transaction counter for pipes 1 to 5 in the receiving direction
When the specified number of transactions is complete in the data packet receiving direction, the USBFS recognizes that
the transfer ended. Two transaction counters are provided: one is the PIPEnTRN register, which specifies the number of
transactions to be executed, and the other is the current counter, which internally counts the number of executed
transactions. If the PIPECFG.SHTNAK bit is set to 1, when the current counter value matches the specified number of
transactions, the associated PIPEnCTR.PID[1:0] bits are set to NAK and the subsequent transfer is disabled. The
transactions can be counted again from the beginning by initializing the current counter of the transaction counter
function through the PIPEnTRE.TRCLR bit. The data read from PIPEnTRN differs depending on the
PIPEnTRE.TRENB setting as follows:
The TRENB bit = 0: Specified transaction counter value can be read
The TRENB bit = 1: Current counter value indicating the internally counted number of executed transactions can be
read.
The following constraints apply when working with the TRCLR bit:
If the transactions are being counted and PID = BUF, the current counter cannot be cleared
If there is any data left in the buffer, the current counter cannot be cleared.
31.3.4.6
Response PID
Specify the response PID for each pipe in the PID[1:0] bits in DCPCTR and PIPEnCTR. This section describes the
USBFS operation with different response PID settings.
(1)
Software response PID settings in host controller mode
Select the response PID to specify the execution of transactions as follows:
NAK setting: Using pipes is disabled and no transactions are executed
BUF setting: Transactions are executed based on the FIFO buffer state:
OUT direction: An OUT token is issued if the FIFO buffer contains transmit data
IN direction: An IN token is issued if the FIFO buffer is not full and can receive data.
STALL setting: Using pipes is disabled and no transactions are executed.
Note:
(2)
Use the DCPCTR.SUREQ bit to execute setup transactions for the DCP.
Software response PID settings in device controller mode
Select the response PID to respond to transactions from the host as follows:
NAK setting: A NAK response is returned to all generated transactions
BUF setting: A response is returned to transactions based on the FIFO buffer
STALL setting: A STALL response is returned to all generated transactions.
Note:
For setup transactions, an ACK response is always returned, regardless of the PID[1:0] bits setting, and the USB
request is stored in the register.
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31. USB 2.0 Full-Speed Module (USBFS)
Sections (3) and (4) describe situations in which the USBFS writes to the PID[1:0] bits because of specific transaction
results.
(3)
Hardware response PID settings in host controller mode
NAK setting: PID = NAK is set in the following cases, and issuing of tokens is automatically stopped:
When a non-isochronous transfer is performed and an NRDY interrupt is generated
(for details, see section 31.3.3.2, NRDY interrupt.)
If a short packet is received when the PIPECFG.SHTNAK bit is set to 1 for bulk transfers
If transaction counting ends when the SHTNAK bit is set to 1 for bulk transfers.
BUF setting: The USBFS does not write this setting.
STALL setting: PID = STALL is set in the following cases, and issuing of tokens is automatically stopped:
When STALL is received in response to a transmitted token
When a received data packet exceeds the maximum packet size.
(4)
Hardware response PID settings in device controller mode
NAK setting: PID = NAK is set in the following cases, and a NAK response is returned to transactions:
When the setup token is received normally (DCP only)
If transaction counting ends or a short packet is received when the PIPECFG.SHTNAK bit is set to 1 for bulk
transfers.
BUF setting: There is no BUF writing by the USBFS.
STALL setting: PID = STALL is set in the following cases, and a STALL response is returned to transactions:
When a received data packet exceeds the maximum packet size
When a control transfer sequence error is detected (DCP only).
31.3.4.7
Data PID sequence bit
The USBFS automatically toggles the sequence bit in the data PID when data is transferred successfully in the control
transfer data stage, bulk transfer, and interrupt transfer. The sequence bit of the next data PID to be transmitted can be
confirmed with the SQMON bit in DCPCTR and PIPEnCTR. When data is transmitted, the sequence bit toggles on ACK
handshake reception. When data is received, the sequence bit toggles on ACK handshake transmission. The SQCLR and
SQSET bits in DCPCTR and PIPEnCTR registers can be used to change the data PID sequence bit.
In device controller mode when control transfers are used, the USBFS automatically sets the sequence bit for stage
transitions. DATA1 is returned when the setup stage ends. The sequence bit is not referenced and PID = DATA1 is
returned in the status stage. Therefore, no software settings are required. However, in host controller mode when control
transfers are used, the sequence bit must be set by software for the stage transitions.
For ClearFeature requests for transmission or reception, the data PID sequence bit must be set by software in both host
and device controller modes.
31.3.4.8
Response PID = NAK function
The USBFS provides a function for disabling pipe operation (PID response = NAK) when the final data packet of a
transaction is received. The USBFS automatically distinguishes this based on reception of a short packet or the
transaction counter. Enable this function by setting the PIPECFG.SHTNAK bit to 1.
When the double buffer mode is being used for the FIFO buffer, using this function enables the reception of data packets
in transfer units. If pipe operation is disabled, software must enable the pipe again (PID response = BUF).
The response PID = NAK function can be used only for bulk transfers.
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31.3.4.9
31. USB 2.0 Full-Speed Module (USBFS)
Auto response mode
For bulk transfer pipes (1 to 5), when the PIPEnCTR.ATREPM bit is set to 1, a transition is made to auto response mode.
During an OUT transfer (PIPECFG.DIR = 0), OUT-NAK mode is invoked, and during an IN transfer (DIR = 1), null auto
response mode is invoked.
31.3.4.10
OUT-NAK mode
For bulk OUT transfer pipes, NAK is returned in response to an OUT token, and an NRDY interrupt is output when the
PIPEnCTR.ATREPM bit is set to 1. To transition from normal mode to OUT-NAK mode, specify OUT-NAK mode while
pipe operation is disabled (PID[1:0] = 00b for NAK response). Next, enable pipe operation (PID[1:0] = 01b for BUF
response), on which OUT-NAK mode becomes valid. If an OUT token is received immediately before pipe operation is
disabled, the token data is normally received, and an ACK is returned to the host.
To transition from OUT-NAK mode to normal mode, cancel OUT-NAK mode while pipe operation is disabled (NAK).
Next, enable pipe operation (BUF). In normal mode, reception of OUT data is enabled.
31.3.4.11
Null auto response mode
For bulk IN transfer pipes, zero-length packets are continuously transmitted when the PIPEnCTR.ATREPM bit is set to
1.
To transition from normal mode to null auto response mode, specify null auto response mode while pipe operation is
disabled (response PID = NAK). Next, enable pipe operation (response PID = BUF) on which null auto response mode
becomes valid. Before setting null auto response mode, check that PIPEnCTR.INBUFM = 0, because the mode can be
set only when the buffer is empty. If the INBUFM bit is 1, empty the buffer using the PIPEnCTR.ACLRM bit. Do not
write data from the FIFO port while a transition to null auto response mode is being made.
To transition from null auto response mode to normal mode, keep the pipe operation disabled (response PID = NAK) for
the period of the zero-length packet transmission (about 10 µs) before canceling the null auto response mode. In normal
mode, data can be written from the FIFO port, so packet transmission to the host is enabled by enabling pipe operation
(response PID = BUF).
31.3.5
FIFO Buffer
The USBFS provides a FIFO buffer for data transfers, and it manages the memory area used for each pipe. The FIFO
buffer has two states depending on whether the access right is assigned to the system (CPU side) or the USBFS (SIE
side).
(1)
Buffer status
Table 31.18 and Table 31.19 show the buffer status in the USBFS. The FIFO buffer status can be confirmed using the
DCPCTR.BSTS and PIPEnCTR.INBUFM bits. The transfer direction for the FIFO buffer can be specified in either the
PIPECFG.DIR or CFIFOSEL.ISEL bit (when DCP is selected).
The INBUFM bit is valid for pipes 0 to 5 in the transmitting direction.
When a transmitting pipe uses double buffering, software can read the BSTS bit to monitor the FIFO buffer status on the
CPU side and the INBUFM bit to monitor the FIFO buffer status on the SIE side. When write access to the FIFO port by
the CPU or DMA/DTC is slow and the buffer empty status cannot be determined using the BEMP interrupt, software can
use the INBUFM bit to confirm the end of transmission.
Table 31.18
Buffer status indicated in the BSTS bit (1 of 2)
ISEL or DIR
BSTS
FIFO buffer status
0 (receiving direction)
0
There is no received data, or data is being received.
Reading from the FIFO port is disabled.
0 (receiving direction)
1
There is received data, or a zero-length packet is received.
Reading from the FIFO port is allowed.
When a zero-length packet is received, reading is not possible and the buffer must be cleared.
1 (transmitting direction) 0
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Transmission has not completed.
Writing to the FIFO port is disabled.
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Table 31.18
31. USB 2.0 Full-Speed Module (USBFS)
Buffer status indicated in the BSTS bit (2 of 2)
ISEL or DIR
BSTS
1 (transmitting direction) 1
Table 31.19
FIFO buffer status
Transmission is complete.
CPU write is allowed.
Buffer status indicated in the INBUFM bit
DIR
INBUFM
FIFO buffer status
0 (receiving direction)
Invalid
Invalid
1 (transmitting direction)
0
Transmission is complete.
There is no data waiting to be transmitted.
1 (transmitting direction)
1
The FIFO port has written data to the buffer.
There is data to be transmitted.
31.3.6
FIFO Buffer Clearing
Table 31.20 shows the methods for clearing the FIFO buffer. The FIFO buffer can be cleared using BCLR bit in the port
control register, DnFIFOSEL.DCLRM, or the PIPEnCTR.ACLRM bit.
Single or double buffering can be selected for pipes 1 to 5 in the PIPECFG.DBLB bit.
Table 31.20
Buffer clearing methods
Mode for automatically clearing
the FIFO buffer after reading the
specified pipe data
Auto buffer clear mode for
discarding all received packets
CFIFOCTR
DnFIFOCTR
DnFIFOSEL
PIPEnCTR
Bit used
BCLR
DCLRM
ACLRM
Clearing condition
Cleared by writing 1
1: Mode valid
0: Mode invalid
1: Mode valid
0: Mode invalid.
FIFO buffer
clearing mode
Clearing FIFO buffer on the
CPU side
Register used
(1)
Auto buffer clear mode function
The USBFS discards all received data packets if the PIPEnCTR.ACLRM bit is set to 1. If a correct data packet is
received, the ACK response is returned to the host controller. The auto buffer clear mode function can only be set in the
FIFO buffer reading direction.
Setting the ACLRM bit to 1 and then to 0 clears the FIFO buffer of the selected pipe regardless of the access direction.
An access cycle of at least 100 ns is required for the internal hardware sequence processing between ACLRM = 1 and
ACLRM = 0.
31.3.7
FIFO Port Functions
Table 31.21 shows the settings for the FIFO port functions. In write access, writing data until the maximum packet size is
reached automatically enables transmission of the data. To enable transmission before the maximum packet size is
reached, set the BVAL flag in the port control register to end writing. To send a zero-length packet, use the BCLR bit to
clear the buffer, and then set the BVAL flag to end writing.
In reading, reception of new packets is automatically enabled when all data is read. Data cannot be read when a zerolength packet is received (DTLN[8:0] = 0), so the buffer must be cleared with the BCLR bit. The length of the receive
data can be confirmed in the DTLN[8:0] bits in the port control register.
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Table 31.21
31. USB 2.0 Full-Speed Module (USBFS)
FIFO port function settings
Register name
Bit name
Description
CFIFOSEL,
DnFIFOSEL
(n = 0, 1)
RCNT
Selects DTLN[8:0] read mode
REW
FIFO buffer rewind (re-read, rewrite)
DCLRM
Automatically clears receive data for a specified pipe after the data is read (only for DnFIFO)
DREQE
Enables DMA/DTC transfers (only for DnFIFO)
MBW
FIFO port access bit width
BIGEND
Selects FIFO port endian
ISEL
FIFO port access direction (only for DCP)
CFIFOCTR,
DnFIFOCTR
(n = 0, 1)
(1)
CURPIPE
Selects the current pipe
BVAL
Ends writing to the FIFO buffer
BCLR
Clears the FIFO buffer on the CPU side
DTLN
Checks the length of receive data
FIFO port selection
Table 31.22 shows the pipes that can be selected with the different FIFO ports. The pipe to be accessed must be selected
in the CURPIPE[3:0] bits in the port select register. After the pipe is selected, software must check whether the written
value can be read correctly from the CURPIPE[3:0] bits. If the previous pipe number is read, it indicates that the USBFS
is modifying the pipe. Next, software checks that the FRDY bit in the port control register is 1.
In addition, software must specify the bus width to be accessed in the MBW bit in the port select register. The FIFO
buffer access direction conforms to the PIPECFG.DIR setting. For the DCP only, the ISEL bit in the port select register
determines the direction.
Table 31.22
FIFO port access by pipe
Pipe
Access method
Ports that can be used
DCP
CPU access
CFIFO port register
Pipes 1 to 9
CPU access
CFIFO port register
D0FIFO/D1FIFO port register.
DMA/DTC access
D0FIFO/D1FIFO port register
(2)
REW bit
It is possible to temporarily stop access to a pipe currently being accessed, access a different pipe, and then continue
processing for the first pipe again. The REW bit in the port select register is used for this processing.
If a pipe is selected in the CURPIPE[3:0] bits in the port select register with the REW bit set to 1, the pointer used for
reading from and writing to the FIFO buffer is reset, and reading or writing can be carried out from the first byte. If a pipe
is selected with 0 set for the REW bit, data can be read and written in continuation from the previous selection, without
the pointer being reset.
To access the FIFO port, software must check that the FRDY bit in the port control register is 1 after selecting a pipe.
31.3.8
(1)
DMA Transfers (D0FIFO and D1FIFO Ports)
Overview of DMA transfers
For pipes 1 to 9, the FIFO port can be accessed using the DMAC. When buffer access for a pipe targeted for DMA
transfer is enabled, a DMA transfer request is issued.
Select the unit of transfer to the FIFO port in the DnFIFOSEL.MBW bit, and select the pipe targeted for the DMA
transfer in the DnFIFOSEL.CURPIPE[3:0] bits. Do not change the selected pipe during the DMA transfer.
(2)
DnFIFO auto clear mode (D0FIFO and D1FIFO port reading direction)
If 1 is set in the DnFIFOSEL.DCLRM bit, the USBFS automatically clears the FIFO buffer of the selected pipe when
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31. USB 2.0 Full-Speed Module (USBFS)
reading of data from the FIFO buffer is complete.
Table 31.23 shows the packet reception and FIFO buffer clearing processing by software for each of the settings. As
shown in the table, the buffer clearing conditions depend on the value set in the PIPECFG.BFRE bit. Using the
DnFIFOSEL.DCLRM bit eliminates the need for the buffer to be cleared by software in any situation that requires buffer
clearing. This enables the DMA transfers without involving software.
The DnFIFO auto clear mode can only be set in the FIFO buffer reading direction.
Table 31.23
Packet reception and FIFO buffer clearing processing by software
Register setting
Buffer status
when packet is received
DCLRM = 0
BFRE = 0
DCLRM = 1
BFRE = 1
BFRE = 0
BFRE = 1
Buffer full
No clearing required
No clearing required
No clearing required
No clearing required
Zero-length packet reception
Clearing required
Clearing required
No clearing required
No clearing required
Normal short packet reception
No clearing required
Clearing required
No clearing required
No clearing required
Transaction count end
No clearing required
Clearing required
No clearing required
No clearing required
31.3.9
Control Transfers Using the DCP
The DCP is used for data transfers in the control transfer data stage. The FIFO buffer of the DCP is a 64-byte single
buffer with a fixed area for both control reads and control writes. The FIFO buffer can be accessed only through the
CFIFO port.
31.3.9.1
(1)
Control transfers in host controller mode
Setup stage
The USQREQ, USBVAL, USBINDX, and USBLENG registers are used to transmit USB requests for setup transactions.
Writing the setup packet data to the registers and then writing 1 to the DCPCTR.SUREQ bit transmits the specified data
for the setup transaction. On completion of the transaction, the SUREQ bit clears to 0. Do not change these USB request
registers while SUREQ = 1.
When an attached function device is detected, software must issue the first setup transaction for the device using this
sequence with the DCPMAXP.DEVSEL[3:0] bits set to 0 and the DEVADD0.USBSPD[1:0] bits set appropriately.
When an attached function device is shifted to the Address state, software must issue setup transactions using this
sequence with the assigned USB address set in the DEVSEL[3:0] bits and the bits in DEVADDn associated with the
specified USB address set appropriately. For example, when PIPEMAXP.DEVSEL[3:0] = 0010b, make appropriate
settings in DEVADD2. When PIPEMAXP.DEVSEL[3:0] = 0101b, make appropriate settings in DEVADD5.
When the setup transaction data is sent, an interrupt request is generated based on the response from the peripheral
device (SIGN or SACK bit in INTSTS1). This interrupt request allows software to check the setup transaction result.
A DATA0 data packet (USB request) for the setup transaction is always transmitted regardless of the status of the
DCPCTR.SQMON bit.
(2)
Data stage
The data stage is used to transfer data using the DCP FIFO buffer.
Before accessing the DCP FIFO buffer, specify the access direction in the CFIFOSEL.ISEL bit. Specify the transfer
direction in the DCPCFG.DIR bit.
For the first data packet of the data stage, the data PID must be transferred as DATA1. Set data PID = DATA1 in the
DCPCTR.SQSET bit and set the PID bits = BUF. Completion of data transfer is detected using the BRDY or BEMP
interrupt.
For control write transfers, when the number of data bytes to be sent is an integer multiple of the maximum packet size,
software must send a zero-length packet at the end.
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(3)
31. USB 2.0 Full-Speed Module (USBFS)
Status stage
The status stage is used for zero-length packet data transfers in the reverse direction of the data stage. As in the data
stage, data is transfered using the DCP FIFO buffer. Transactions are executed using the same procedure as the data
stage.
Data packets in the status stage must be transmitted and received with the data PID set to DATA1 using the
DCPCTR.SQSET bit.
When a zero-length packet is received, check the receive-data length in the CFIFOCTR.DTLN[8:0] bits after a BRDY
interrupt is generated, and then clear the FIFO buffer using the BCLR bit.
31.3.9.2
(1)
Control transfers in device controller mode
Setup stage
The USBFS sends an ACK response to a normal setup packet for the USBFS. The USBFS operates in the setup stage as
follows:
On receiving a new setup packet, the USBFS sets the following bits:
Sets the INTSTS0.VALID bit to 1
Sets the DCPCTR.PID[1:0] bits to NAK
Sets the DCPCTR.CCPL bit to 0.
When the USBFS receives a data packet following a setup packet, it stores the USB request parameters in USBREQ,
USBVAL, USBINDX, and USBLENG.
Before performing the response processing for a control transfer, set the VALID flag to 0. When the VALID bit = 1, PID
= BUF cannot be set, and the data stage cannot be terminated.
Using the VALID bit function, the USBFS can suspend a request being processed when it receives a new USB request
during a control transfer and return a response to the latest request.
In addition, the USBFS automatically detects the direction bit (bmRequestType bit [8]) and the request data length
(wLength) in the received USB request. It distinguishes between control read transfers, control write transfers, and nodata control transfers, and it controls stage transitions. For an incorrect sequence, a sequence error occurs in the control
transfer stage transition interrupt, and the interrupt is reported to software. For a diagram of the stage control by the
USBFS, see Figure 31.15.
(2)
Data stage
The DCP must be used to execute data transfers for received USB requests. Before accessing the DCP FIFO buffer,
specify the access direction in the CFIFOSEL.ISEL bit.
If the transfer data is larger than the size of the DCP FIFO buffer, execute the data transfer using the BRDY interrupt for
control write transfers and the BEMP interrupt for control read transfers.
(3)
Status stage
Control transfers are terminated by setting the DCPCTR.CCPL bit to 1 while the DCPCTR.PID[1:0] bits are set to BUF.
After this setting is made, the USBFS automatically executes the status stage based on the data transfer direction
determined at the setup stage. The procedure is as follows:
For control read transfers
The USBFS receives a zero-length packet from the USB host and transmits an ACK response.
For control write transfers and no-data control transfers
The USBFS transmits a zero-length packet and receives an ACK response from the USB host.
(4)
Control transfer auto response function
The USBFS automatically responds to a correct SET_ADDRESS request. If any of the following errors occurs in the
SET_ADDRESS request, a response from software is required:
bmRequestType is not 00h: Any transfer other than a control write transfer
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wIndex is not 00h: Request error
wLength is not 00h: Any transfer other than a no-data control transfer
wValue is larger than 7Fh: Request error
INTSTS0.DVSQ[2:0] are 011b (Configured state): Control transfer of a device state error.
For all requests other than the SET_ADDRESS request, a response is required from the associated software.
31.3.10
Bulk Transfers (Pipes 1 to 5)
The FIFO buffer usage (single/double buffer setting) is configurable for bulk transfers. The USBFS provides the
following functions for bulk transfers:
BRDY interrupt function (PIPECFG.BFRE bit), see section 31.3.3.1, (2) When SOFCFG.BRDYM = 0 and
PIPECFG.BFRE = 1
Transaction count function (PIPEnTRE.TRENB, TRCLR, and PIPEnTRN.TRNCNT[15:0] bits), see section
31.3.4.5, Transaction counter for pipes 1 to 5 in the receiving direction
Response PID = NAK function (PIPECFG.SHTNAK bit), see section 31.3.4.8, Response PID = NAK function
Auto response mode (PIPEnCTR.ATREPM bit), see section 31.3.4.9, Auto response mode.
31.3.11
Interrupt Transfers (Pipes 6 to 9)
In device controller mode, the USBFS performs interrupt transfers based on the timing dictated by the host controller. In
host controller mode, software can set the timing for issuing tokens using the interval counter.
31.3.11.1
Interval counter for interrupt transfers in host controller mode
Specify the transaction interval for interrupt transfers in the PIPEPERI.IITV[2:0] bits. The USBFS issues interrupt
transfer tokens based on this interval.
(1)
Counter initialization
The USBFS initializes the interval counter under the following conditions:
Power-on reset
This initializes the IITV[2:0] bits.
FIFO buffer initialization using the PIPEnCTR.ACLRM bit:
This does not initialize the IITV[2:0] bits, but does initialize the count value. Setting the PIPEnCTR.ACLRM bit to
0 starts counting from the value set in IITV[2:0].
The interval counter is not initialized in the following case:
USB bus reset or USB suspended
The IITV[2:0] bits are not initialized. Setting 1 to the DVSTCTR0.UACT bit starts counting from the value saved
before entering the USB bus reset state or USB Suspend state.
(2)
Operation when tokens cannot be transmitted or received even on token generation
No token is generated in the following cases even at token generation time. In these cases, the USBFS tries to execute the
transaction in the next interval:
When the PID is set to NAK or STALL
When the FIFO buffer is full at token transmit time in the receiving (IN) direction
When there is no data to be transmitted in the FIFO buffer at token transmit time in the transmitting (OUT)
direction.
31.3.12
Isochronous Transfers (Pipes 1 and 2)
The USBFS provides the following functions for isochronous transfers:
Notification of isochronous transfer error
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31. USB 2.0 Full-Speed Module (USBFS)
Interval counter specified in the PIPEPERI.IITV[2:0] bits
Isochronous IN transfer data setup control (IDLY function)
Isochronous IN transfer buffer flush function specified in the PIPEPERI.IFIS bit.
31.3.12.1
Error detection in isochronous transfers
The USBFS provides a function for detecting the errors described in this section, so that when errors occur in
isochronous transfers, they can be controlled by software. Table 31.24 and Table 31.25 show the priority order for errors
detected by the USBFS and the associated interrupts.
(a)
PID errors
The PID value of the received packet is invalid.
(b)
CRC errors and bit stuffing errors
A CRC error is found in a received packet or the bit stuffing is invalid.
(c)
Maximum packet size exceeded
The data size of the received packet exceeds the specified maximum packet size.
(d)
Overrun and underrun errors
In host controller mode:
The FIFO buffer is full at token transmit time in the IN (receiving) direction
There is no data to be sent in the FIFO buffer at token transmit time in the OUT (transmitting) direction.
In device controller mode:
There is no data to be sent in the FIFO buffer at token receive time in the IN (transmitting) direction
The FIFO buffer is full at token receive time in the OUT (receiving) direction.
(e)
Interval errors
In device controller mode, the following cases are treated as an interval error:
Failure to receive an IN token in the interval frame during an isochronous IN transfer
Failure to receive an OUT token in the interval frame during an isochronous OUT transfer.
Table 31.24
Detection
priority
Error detection for token transmission and reception
Error
Generated interrupt and status
1
PID error
No interrupts are generated in either host or device controller mode (ignored as a corrupted
packet)
2
CRC or bit stuffing error
No interrupts are generated in either host or device controller mode (ignored as a corrupted
packet)
3
Overrun or underrun error
An NRDY interrupt is generated to set the FRMNUM.OVRN bit to 1 in both host and device
controller modes.
In device controller mode, a zero-length packet is transmitted in response to an IN token. No
data packets are received in response to OUT token.
4
Interval error
An NRDY interrupt is generated in device controller mode. No interrupt is generated in host
controller mode.
Table 31.25
Detection
priority
1
Error detection for data packet reception (1 of 2)
Error
Generated interrupt and status
PID error
No interrupts are generated (ignored as a corrupted packet.)
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Table 31.25
Detection
priority
31. USB 2.0 Full-Speed Module (USBFS)
Error detection for data packet reception (2 of 2)
Error
Generated interrupt and status
2
CRC or bit stuffing error
An NRDY interrupt is generated and the FRMNUM.CRCE bit is set to 1 in both host and device
controller modes
3
Maximum packet size
exceeded error
A BEMP interrupt is generated and the PID[1:0] bits are set to STALL in both host and device
controller modes
31.3.12.2
DATA-PID
In device controller mode, the USBFS responds to a received PID as follows:
(1)
IN direction
DATA0: Transmitted as data packet PID
DATA1: Not transmitted
DATA2: Not transmitted
mDATA: Not transmitted.
(2)
OUT direction
DATA0: Received normally as data packet PID
DATA1: Received normally as data packet PID
DATA2: Packets ignored
mDATA: Packets ignored.
31.3.12.3
Interval counter
The isochronous transfer interval can be set in the PIPEPERI.IITV[2:0] bits. In device controller mode, the interval
counter enables the functions as shown in Table 31.26. In host controller mode, the USBFS generates the token issuance
timing, and the interval counter operation is the same as that for interrupt transfers.
Table 31.26
Transfer
direction
IN
OUT
Interval counter functions in device controller mode
Function
Conditions for detection
Transmit buffer flush
Failure to receive an IN token successfully in the interval frame during an isochronous IN
transfer
Notification of no reception of
token
Failure to receive an OUT token successfully in the interval frame during an isochronous
OUT transfer
The interval count is performed when an SOF is received or for interpolated SOFs, so the isochronism can be maintained
even if an SOF is corrupt. The frame interval can be set to 2IITV frames.
(1)
Counter initialization in device controller mode
The USBFS initializes the interval counter under the following conditions:
Power-on reset
This initializes the PIPEPERI.IITV[2:0] bits.
FIFO buffer initialization using the ACLRM bit
This does not initialize the IITV[2:0] bits, but does initialize the count value.
After the interval counter is initialized, the interval count starts under one of the following conditions when a packet is
transferred successfully:
An SOF is received after data is transmitted in response to an IN token when PID = BUF
An SOF is received after data is received in response to an OUT token when PID = BUF.
The interval counter is not initialized in the following conditions:
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31. USB 2.0 Full-Speed Module (USBFS)
When the PID[1:0] bits are set to NAK or STALL
This does not stop the interval timer. The USBFS attempts the transaction in the next interval.
When the USB bus is reset or USBFS is suspended
This does not initialize the IITV[2:0] bits. When an SOF is received, the interval counter starts counting from the
value set before SOF was received.
(2)
Interval counting and transfer control in host controller mode
The USBFS controls the interval between token issuance operations based on the PIPEPERI.IITV[2:0] bit settings.
Specifically, the USBFS issues a token for a selected pipe once every 2IITV frames.
PID bit setting
Token
DATA
SOF
OUT
DATA
SOF
OUT
SOF
USB bus
SOF
The USBFS starts counting the token issuance interval at the frame following the frame in which the PID[1:0] bits are set
to BUF by software.
NAK
BUF
BUF
BUF
Token
not issued
Token
not issued
Token
issued
Token
issued
Interval counter started
PID bit setting
Token
DATA
SOF
OUT
SOF
DATA
SOF
OUT
SOF
DATA
SOF
OUT
USB bus
SOF
Token issuance when IITV = 0
SOF
Figure 31.16
NAK
BUF
BUF
BUF
BUF
BUF
BUF
Token
not issued
Token
not issued
Token
issued
Token
not issued
Token
issued
Token
not issued
Token
issued
Interval counter started
Figure 31.17
Token issuance when IITV = 1
When the selected pipe is set for isochronous transfers, the USBFS performs the following operation in addition to
controlling the token issuance interval. The USBFS issues a token even when the NRDY interrupt generation condition
is satisfied.
(a)
When the selected pipe is for isochronous IN transfers
The USBFS generates an NRDY interrupt when the USBFS issues an IN token but does not successfully receive a packet
from a peripheral device (no response or packet error).
The USBFS sets the FRMNUM.OVRN bit to 1, generating an NRDY interrupt, when the time to issue an IN token
occurs while the USBFS cannot receive data because the FIFO buffer is full, because the CPU or DMAC/DTC is too
slow in reading data from the FIFO buffer.
(b)
When the selected pipe is for isochronous OUT transfers
The USBFS sets the OVRN bit to 1, generating an NRDY interrupt and transmitting a zero-length packet, when the time
to issue an OUT token comes while there is no data to be transmitted in the FIFO buffer, or because the CPU or
DMAC/DTC is too slow in writing data to the FIFO buffer.
The token issuance interval is reset on any of the following conditions:
When the USBFS is reset through a reset pin
This initializes the IITV[2:0] bits.
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31. USB 2.0 Full-Speed Module (USBFS)
When the PIPEnCTR.ACLRM bit is set to 1 by software.
(3)
Interval counting and transfer control in device controller mode
(a)
When the selected pipe is for isochronous OUT transfers
The USBFS generates an NRDY interrupt when it fails to receive a data packet within the interval set in the
PIPEPERI.IITV[2:0] bits.
The USBFS also generates an NRDY interrupt when it fails to receive data because of a CRC error or other errors
contained in the data packet or because the FIFO buffer is full.
The NRDY interrupt is generated on SOF packet reception. Even if the SOF packet is corrupted, internal interpolation
allows the interrupt to be generated when the SOF packet is received. However, when the IITV bits are set to a value
other than 0, the USBFS generates an NRDY interrupt on receiving an SOF packet for every interval after interval
counting starts.
When the PID[1:0] bits are set to NAK by software after starting the interval timer, the USBFS does not generate an
NRDY interrupt on receiving an SOF packet.
The timing for starting interval counting depends on the IITV[2:0] setting as follows:
When the IITV[2:0] bits = 0:
Interval counting starts at the next frame after software changes the PID[1:0] bits of the selected pipe to BUF.
PID bit setting
Token
DATA
SOF
OUT
DATA
SOF
OUT
SOF
USB bus
SOF
When the IITV[2:0] bits ≠ 0:
Interval counting starts on completion of successful reception of the first data packet after the PID[1:0] bits for the
selected pipe are changed to BUF.
NAK
NAK
BUF
BUF
Token
reception
not delayed
Token
reception
not delayed
Token
reception
is delayed
Token
reception
is delayed
Interval counter started
PID bit setting
Token
DATA
SOF
OUT
SOF
DATA
SOF
OUT
SOF
DATA
SOF
OUT
USB bus
SOF
Relationship between frames and expected token reception when IITV[2:0] = 0
SOF
Figure 31.18
NAK
BUF
BUF
BUF
BUF
BUF
BUF
Token
reception
not delayed
Token
reception
not delayed
Token
reception
is delayed
Token
reception
not delayed
Token
reception
is delayed
Token
reception
not delayed
Token
reception
is delayed
Interval counter started
Figure 31.19
(b)
Relationship between frames and expected token reception when IITV[2:0] ≠ 0
When the selected pipe is for isochronous IN transfers
The PIPEPERI.IFIS bit must be 1 for this use case. When IFIS = 0, the USBFS transmits a data packet in response to a
received IN token regardless of the PIPEPERI.IITV[2:0] setting.
When IFIS is 1 and there is data to be transmitted in the FIFO buffer, the USBFS clears the FIFO buffer when it fails to
receive an IN token in the frame at the interval set in the IITV[2:0] bits.
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The USBFS also clears the FIFO buffer when it fails to receive an IN token successfully because of a bus error, such as a
CRC error, contained in the IN token.
The FIFO buffer is cleared on SOF packet reception. Even if the SOF packet is corrupted, the internal interpolation
allows the FIFO buffer to be cleared when the SOF packet is received.
The timing to start interval counting depends on the IITV[2:0] setting, as with OUT transfers.
The interval is counted on any of the following conditions in device controller mode:
When a hardware reset is applied to the USBFS (which also sets the IITV[2:0] bits to 000b)
When the PIPEnCTR.ACLRM bit is set to 1 by software
When the USBFS detects a USB bus reset.
(4)
Transmit data setup for isochronous transfers in device controller mode
With isochronous data transmission using the USBFS in device controller mode, after data is written to the FIFO buffer,
a data packet can be transmitted in the first frame after the SOF packet is detected. This isochronous transfer transmit
data setup function can identify the frame that started transmission.
When double buffering is used, transmission is only enabled for the buffer to which data writing was completed first,
even after the data write to both buffers is complete. Accordingly, even if multiple IN tokens are received, only one
packet of FIFO buffer data is transmitted.
When the FIFO buffer is ready to transmit data when an IN token is received, data is transferred and a normal response is
returned. However, if the FIFO buffer cannot transmit data, a zero-length packet is transmitted and an underrun error
occurs.
Figure 31.20 shows an example transmission using the isochronous transfer transmission data setup function when IITV
= 0 (every frame) is set.
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31. USB 2.0 Full-Speed Module (USBFS)
(1) Example of reception start 1 (transmit data is ready before IN token reception start)
SOF
SOF
SOF
SOF
Receive token
Transmit packet
Writing
Empty
Buffer A
Empty
Buffer B
Write end
Transfer enabled
Writing
Write end
(2) Example of reception start 2 (transmit data is ready after IN token reception start 1)
SOF
IN
Receive token
IN
Zerolength
Transmit packet
Empty
Buffer A
Writing
IN
Zerolength
Data-A
Write end
Transfer enabled
Empty
Empty
Buffer B
(3) Example of reception start 3 (transmit data is ready after IN token reception start 2)
SOF
SOF
IN
Receive token
Zerolength
Transmit packet
Empty
Buffer A
Writing
Empty
Buffer B
Write end
SOF
SOF
IN
IN
Data-A
Transfer enabled
Data-B
Empty
Write end
Writing
Write end
Writing
Transfer enabled
Empty
(4) Example of IN token reception out of interval
Receive token
SOF
SOF
IN
Zerolength
Transmit packet
Buffer A
Empty
Buffer B
Figure 31.20
(5)
Writing
Empty
SOF
IN
Write end
Writing
IN
Zerolength
Data-A
Transfer enabled
Empty
Write end
SOF
IN
Data-B
Writing
Write end
Transfer enabled
Empty
Example data setup operation
Transmit buffer flush for isochronous transfers in device controller mode
In device controller mode during isochronous data transmission, if the USBFS receives an SOF packet for the next frame
without receiving an IN token in the interval frame, it operates as if the IN token is corrupt and clears the buffer that is
enabled for transmission, putting that buffer in the writing enabled state.
When double buffering is used and writing to both buffers is complete, the cleared FIFO buffer is assumed to be the one
where the data was transmitted in the interval frame, and transmission is enabled for the FIFO buffer that was not cleared
on SOF packet reception.
The timing of the buffer flush function depends on the PIPEPERI.IITV[2:0] setting as follows:
When IITV = 0:
The buffer flush operation starts from the first frame after the pipe is enabled
When IITV ≠ 0:
The buffer flush operation starts after the first normal transaction.
Figure 31.21 shows an example buffer flush. When an unanticipated token is received before the interval frame, the
USBFS sends the write data or a zero-length packet as an underrun error, depending on the data setup status.
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31. USB 2.0 Full-Speed Module (USBFS)
SOF
Buffer A
SOF
Empty
Writing
Write end
SOF
Transfer enabled
SOF
Empty
Writing
Write end
Buffer is flushed
Buffer B
Empty
Figure 31.21
Write end
Writing
Transfer enabled
Example buffer flush operation
Figure 31.22 shows an example interval error occurrence. There are five types of interval errors, as shown in the figure.
An interval error occurs at timing 1 , and the buffer flush function is activated.
If an interval error occurs during an IN transfer, the buffer flush function is activated. If it occurs during an OUT transfer,
an NRDY interrupt is generated. Use the FRMNUM.OVRN bit to distinguish between this and NRDY interrupts
triggered by received packet errors and overrun errors.
For tokens that are shaded in the figure, responses are returned based on the FIFO buffer status.
IN direction:
If the buffer is ready to transfer data, the data is transferred and a normal response is returned
If the buffer is not ready to transfer data, a zero-length packet is transmitted and an underrun error occurs.
OUT direction:
If the buffer is ready to receive data, the data is received and a normal response is returned
If the buffer is not ready to receive data, the received data is discarded and an overrun error occurs.
SOF
(1) Normal transfer
Token
(2) Token corrupted
Token
(3) Packet inserted
Token
(4) Frame misaligned 1
Token
(5) Frame misaligned 2
Token
(6) Token delayed
Token
Token
1
Token
Token
1
Token
1
Token
Token
Token
Token
Token
Token
Token
1
Token
1
Token
1
Token
1
Token
Token
Token
Interval when IITV = 1
Token
Token received in the specified interval
Token
Token received in the frame outside the interval
Figure 31.22
31.3.13
Example interval error occurrence when IITV = 1
SOF Interpolation Function
In device controller mode, if packet reception is disabled at intervals of 1 ms because the SOF packet is corrupted or
missing, the USBFS interpolates the SOF. SOF interpolation begins when the USBE and SCKE bits in SYSCFG are set
to 1 and an SOF packet is received.
The interpolation function is initialized under the following conditions:
MCU reset
USB bus reset
Suspend state detection.
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The SOF interpolation operates as follows:
The interpolation function is not activated until an SOF packet is received
When the first SOF packet is received, interpolation is performed by counting 1 ms on the 48-MHz internal clock
When the second and subsequent SOF packets are received, interpolation is performed at the previous reception
interval
Interpolation is not performed in the Suspend state or on reception of a USB bus reset.
The USBFS supports the following functions controlled by SOF packet reception. These functions operate normally with
SOF interpolation if the SOF packet is missing:
Updating of the frame number
SOFR interrupt timing
Isochronous transfer interval count.
If an SOF packet is missing during full-speed operation, the FRMNUM.FRNM[10:0] bits are not updated.
31.3.14
Pipe Schedule
31.3.14.1
Conditions for generating transactions
In host controller mode, when the DVSTCTR0.UACT bit is set to 1, the USBFS generates transactions under the
conditions shown in Table 31.27.
Table 31.27
Conditions for generating transactions
Conditions for generation
Transaction
DIR
PID
IITV0
Buffer state
SUREQ
Setup
—*1
—*1
—*1
—*1
1 setting
IN
BUF
Invalid
Receive area
exists
—*1
OUT
BUF
Invalid
Transmit data
exists
—*1
IN
BUF
Valid
Receive area
exists
—*1
OUT
BUF
Valid
Transmit data
exists
—*1
IN
BUF
Valid
*2
—*1
Valid
*3
—*1
Control transfer data stage, status stage,
bulk transfer
Interrupt transfer
Isochronous transfer
OUT
Note 1.
Note 2.
Note 3.
BUF
An em dash (—) in the table indicates that the condition is unrelated to the generating of tokens. “Valid” indicates that, for
interrupt transfers and isochronous transfers, a transaction is generated only in transfer frames that are based on the interval
counter. “Invalid” indicates that a transaction is generated regardless of the interval counter.
This indicates that a transaction is generated regardless of whether there is a receive area. If there is no receive area, however,
the received data is discarded.
This indicates that a transaction is generated regardless of whether there is any data to be transmitted. If there is no data to be
transmitted, however, a zero-length packet is transmitted.
31.3.14.2
Transfer schedule
This section describes the transfer scheduling within a frame of the USBFS. After the USBFS sends an SOF, the transfer
is carried out in the following sequence:
1. Execution of periodic transfers:
A pipe is searched for in the order pipe 1 pipe 2 pipe 6 pipe 7 pipe 8 pipe 9, and then if there is a pipe
for which an isochronous or interrupt transfer transaction can be generated, the transaction is generated.
2. Setup transactions for control transfers:
The DCP is checked, and if a setup transaction is possible, it is sent.
3. Execution of bulk transfers, control transfer data stages, and control transfer status stages:
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31. USB 2.0 Full-Speed Module (USBFS)
A pipe is searched for in the order DCP pipe 1 pipe 2 pipe 3 pipe 4 pipe 5, and then if there is a pipe
for which a transaction for a bulk transfer, a control transfer data stage, or a control transfer status stage can be
generated, the transaction is generated.
When a transaction is generated, processing moves to the next pipe transaction regardless of whether the response
from the peripheral device is ACK or NAK. If there is time for transfer within the frame, step 3 is repeated.
31.3.14.3
Enabling USB communication
Setting the DVSTCTR0.UACT bit to 1 initiates an SOF transmission, and transaction generation is enabled. Setting the
UACT bit to 0 stops SOF transmission and the Suspend state is invoked. If the UACT setting is changed from 1 to 0,
processing stops after the next SOF is sent.
31.4
31.4.1
Usage Notes
Settings for the Module-Stop State
USBFS operation can be disabled or enabled using Module Stop Control Register B (MSTPCRB). The USBFS is
initially stopped after reset. Releasing the module-stop state enables access to the registers. For details, see section 11,
Low Power Modes.
31.4.2
Clearing the Interrupt Status Register on Exiting Software Standby Mode
Because the input buffer is always enabled in Software Standby mode, an unexpected interrupt might occur under the
following conditions:
When the interrupt is enabled in Normal mode
When the interrupt is disabled in Software Standby mode
When the input level of the pin that cancels software standby is changed in Software Standby mode.
These conditions might cause the associated interrupt flag in the Interrupt Status Register to set unexpectedly. After the
MCU exits Software Standby mode, the unexpected interrupt might be sent to the interrupt controller. To avoid this,
always clear the INTSTS0 and INTSTS1 registers in the canceling sequence.
31.4.3
Clearing the Interrupt Status Register after Setting Up the Port Function
The input buffer is disabled before the PmnPFS.PSEL and PmnPFS.PMR ports are set up, so the internal signal is fixed
high or low. The input buffer is enabled after the port is set so that the external pin state is propagated to the MCU. An
unexpected interrupt might occur at this time, causing the VBINT and OVRCR bits in INTSTS0 and INTSTS1, or other
interrupt status flags to set to 1. To avoid a malfunction, always clear the INTSTS0 and INTSTS1 registers after setting
up the port.
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32. Serial Communications Interface (SCI)
32.
Serial Communications Interface (SCI)
32.1
Overview
The Serial Communications Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:
Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter (ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol.
Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be
configured independently using an on-chip baud rate generator.
Table 32.1 lists the SCI specifications, Figure 32.1 shows a block diagram of SCI channel n, and Table 32.2 lists the I/O
pins by mode.
Table 32.1
SCI specifications (1 of 2)
Parameter
Specifications
Serial communication modes
Transfer speed
Bit rate specifiable with the on-chip baud rate generator
Full-duplex communications
Transmitter: Continuous transmission possible using double-buffering
Receiver: Continuous reception possible using double-buffering.
Asynchronous
Clock synchronous
Smart card interface
Simple IIC
Simple SPI.
I/O pins
See Table 32.2
Data transfer
Selectable as LSB-first or MSB-first transfer
Interrupt sources
Transmit end, transmit data empty, receive data full, receive error, receive
data ready, and address match
Completion of generation of a start condition, restart condition, or stop
condition (for simple IIC mode).
Module-stop function
Module-stop state can be set for each channel
Snooze end request
Asynchronous mode
SCI0 address mismatch (SCI0_DCUF)
Data length
7, 8, or 9 bits
Transmission stop bit
1 or 2 bits
Parity
Even parity, odd parity, or no parity
Receive error detection
Parity, overrun, and framing errors
Hardware flow control
Transmission and reception controllable with CTSn_RTSn pins
Transmission/reception
Selectable to 1-stage register or 16-stage FIFO
Address match
Interrupt request/event output can be issued upon detecting a match between
received data and the value in the compare match register
Address mismatch (SCI0
only) receive data
Snooze end request can be issued on detecting a mismatch between the
received data and the value in the compare match register
Start-bit detection
Selectable to low level or falling edge detection
Break detection
Breaks from framing errors detectable by reading from SPTR register
Clock source
Selectable to internal or external clock
Double-speed mode
Baud rate generator double-speed mode is selectable
Multi-processor
communications function
Serial communication enabled between multiple processors
Noise cancellation
Digital noise filters included on signal paths from RXDn pin inputs
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Table 32.1
32. Serial Communications Interface (SCI)
SCI specifications (2 of 2)
Parameter
Clock synchronous
mode
Smart card interface
mode
Specifications
Data length
8 bits
Receive error detection
Overrun error
Clock source
Selectable to internal clock (master mode) or external clock (slave mode)
Hardware flow control
Transmission and reception controllable with CTSn_RTSn pins
Transmission/ reception
Selectable to 1-stage register or 16-stage FIFO
Error processing
Error signal can be automatically transmitted on detecting a parity error during
reception
Data can be automatically retransmitted on receiving an error signal during
transmission
Simple IIC mode
Simple SPI mode
Data type
Both direct and inverse convention supported
Transfer format
I2C bus format (MSB-first only)
Operating mode
Master (single-master operation only)
Transfer rate
Up to 400 kbps
Noise cancellation
The signal paths from input on the SCLn and SDAn pins incorporate digital
noise filters, and provide an adjustable interval for noise cancellation
Data length
8 bits
Error detection
Overrun error
Clock source
Selectable to internal clock (master mode) or external clock (slave mode)
SS input pin function
High impedance state can be invoked on the output pins by driving the SSn
pin high
Clock settings
Configurable between four clock phase and clock polarity settings
Bit rate modulation function
Error reduction through correction of outputs from the on-chip baud rate
generator
Event link function
Error event output for receive error or error signal detection (SCIn_ERI)*1
Receive data full event output (SCIn_RXI)*1,*2
Transmit data empty event output (SCIn_TXI)*1,*2
Transmit end event output (SCIn_TEI)*1,*2
Address match event output (SCIn_AM)*1
Note 1. Channel number, n = 0 to 9.
Note 2. Using this event link function is prohibited when FIFO operation is selected in asynchronous mode.
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32. Serial Communications Interface (SCI)
Bus interface
S5D5 User’s Manual
Module data bus
RDRHL
RDR
RXDn/SCLn/
MISOn
FRDRH
FRDRL
TDRHL
TDR
FTDRH
FTDRL
TSR
RSR
Parity addition
Match check
Parity check
TXDn/SDAn/
MOSIn
SCMR
SSR/SSR_SMCI/
SSR_FIFO
SCR/SCR_SMCI
SMR/SMR_SMCI
SEMR
SPMR
FCR
FDR
LSR
CDR
DCCR
SPTR
SIMR1/2/3
SISR
PCLKA
PCLKA/4
PCLKA/16
PCLKA/64
(To ICU/ELC)
SCIn_TEI
SCIn_TXI
SCIn_RXI
SCIn_ERI
SCIn_AM
SCI0_DCUF
(snooze end request)
External clock
RSR: Receive Shift Register
RDR: Receive Data Register
TSR: Transmit Shift Register
TDR: Transmit Data Register
SMR/SMR_SMCI: Serial Mode Register
SCR/SCR_SMCI: Serial Control Register
SSR/SSR_SMCI/SSR_FIFO: Serial Status Register
SCMR: Smart Card Mode Register
BRR: Bit Rate Register
MDDR: Modulation Duty Register
SEMR: Serial Extended Mode Register
SPMR: SPI Mode Register
SIMR1/2/3: I2C Mode Register 1/2/3
SISR: I2C Status Register
RDRHL: Receive 9-Bit Data Register
Figure 32.1
Clock
Baud rate
generator
Transmission
and reception
control
SSn/
CTSn_RTSn
SCKn
BRR
MDDR
Internal
peripheral
bus
FRDRH/L: Receive FIFO Data Register
TDRHL: Transmit 9-Bit Data Register
FTDRH/L: Transmit FIFO Data Register
FCR: FIFO Control Register
FDR: FIFO Data Count Register
LSR: Line Status Register
CDR: Compare Match Data Register
DCCR: Data Compare Match Control Register
SPTR: Serial Port Register
SCI channel n block diagram
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Table 32.2
32. Serial Communications Interface (SCI)
SCI input/output pins (1 of 2)
Channel
Pin name
Input/Output
Function
SCI0
SCK0
Input/Output
SCI0 clock input/output
RXD0/SCL0/
MISO0
Input/Output
SCI0 receive data input
SCI0 I2C clock input/output
SCI0 slave transmit data input/output
TXD0/SDA0/
MOSI0
Input/Output
SCI0 transmit data output
SCI0 I2C data input/output
SCI0 master transmit data input/output
SS0/CTS0_RTS0
Input/Output
SCI0 chip select input, active-low
SCI0 transfer start control input/output, active-low
SCK1
Input/Output
SCI1 clock input/output
RXD1/SCL1/
MISO1
Input/Output
SCI1 receive data input
SCI1 I2C clock input/output
SCI1 slave transmit data input/output
TXD1/SDA1/
MOSI1
Input/Output
SCI1 transmit data output
SCI1 I2C data input/output
SCI1 master transmit data input/output
SS1/CTS1_RTS1
Input/Output
SCI1 chip select input, active-low
SCI1 transfer start control input/output, active-low
SCK2
Input/Output
SCI2 clock input/output
RXD2/SCL2/
MISO2
Input/Output
SCI2 receive data input
SCI2 I2C clock input/output
SCI2 slave transmit data input/output
TXD2/SDA2/
MOSI2
Input/Output
SCI2 transmit data output
SCI2 I2C data input/output
SCI2 master transmit data input/output
SS2/CTS2_RTS2
Input/Output
SCI2 chip select input, active-low
SCI2 transfer start control input/output, active-low
SCK3
Input/Output
SCI3 clock input/output
RXD3/SCL3/
MISO3
Input/Output
SCI3 receive data input
SCI3 I2C clock input/output
SCI3 slave transmit data input/output
TXD3/SDA3/
MOSI3
Input/Output
SCI3 transmit data output
SCI3 I2C data input/output
SCI3 master transmit data input/output
SS3/CTS3_RTS3
Input/Output
SCI3 chip select input, active-low
SCI3 transfer start control input/output, active-low
SCK4
Input/Output
SCI4 clock input/output
RXD4/SCL4/
MISO4
Input/Output
SCI4 receive data input
SCI4 I2C clock input/output
SCI4 slave transmit data input/output
TXD4/SDA4/
MOSI4
Input/Output
SCI4 transmit data output
SCI4 I2C data input/output
SCI4 master transmit data input/output
SS4/CTS4_RTS4
Input/Output
SCI4 chip select input, active-low
SCI4 transfer start control input/output, active-low
SCK5
Input/Output
SCI5 clock input/output
RXD5/SCL5/
MISO5
Input/Output
SCI5 receive data input
SCI5 I2C clock input/output
SCI5 slave transmit data input/output
TXD5/SDA5/
MOSI5
Input/Output
SCI5 transmit data output
SCI5 I2C data input/output
SCI5 master transmit data input/output
SS5/CTS5_RTS5
Input/Output
SCI5 chip select input, active-low
SCI5 transfer start control input/output, active-low
SCI1
SCI2
SCI3
SCI4
SCI5
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Table 32.2
32. Serial Communications Interface (SCI)
SCI input/output pins (2 of 2)
Channel
Pin name
Input/Output
Function
SCI6
SCK6
Input/Output
SCI6 clock input/output
RXD6/SCL6/
MISO6
Input/Output
SCI6 receive data input
SCI6 I2C clock input/output
SCI6 slave transmit data input/output
TXD6/SDA6/
MOSI6
Input/Output
SCI6 transmit data output
SCI6 I2C data input/output
SCI6 master transmit data input/output
SS6/CTS6_RTS6
Input/Output
SCI6 chip select input, active-low
SCI6 transfer start control input/output, active-low
SCK7
Input/Output
SCI7 clock input/output
RXD7/SCL7/
MISO7
Input/Output
SCI7 receive data input
SCI7 I2C clock input/output
SCI7 slave transmit data input/output
TXD7/SDA7/
MOSI7
Input/Output
SCI7 transmit data output
SCI7 I2C data input/output
SCI7 master transmit data input/output
SS7/CTS7_RTS7
Input/Output
SCI7 chip select input, active-low
SCI7 transfer start control input/output, active-low
SCK8
Input/Output
SCI8 clock input/output
RXD8/SCL8/
MISO8
Input/Output
SCI8 receive data input
SCI8 I2C clock input/output
SCI8 slave transmit data input/output
TXD8/SDA8/
MOSI8
Input/Output
SCI8 transmit data output
SCI8 I2C data input/output
SCI8 master transmit data input/output
SS8/CTS8_RTS8
Input/Output
SCI8 chip select input, active-low
SCI8 transfer start control input/output, active-low
SCK9
Input/Output
SCI9 clock input/output
RXD9/SCL9/
MISO9
Input/Output
SCI9 receive data input
SCI9 I2C clock input/output
SCI9 slave transmit data input/output
TXD9/SDA9/
MOSI9
Input/Output
SCI9 transmit data output
SCI9 I2C data input/output
SCI9 master transmit data input/output
SS9/CTS9_RTS9
Input/Output
SCI9 chip select input, active-low
SCI9 transfer start control input/output, active-low
SCI7
SCI8
SCI9
32.2
Register Descriptions
32.2.1
Receive Shift Register (RSR)
RSR is a shift register that receives serial data input from the RXDn pin and converts it into parallel data. When one
frame of data is received, the data is automatically transferred to the RDR register, RDRHL register, or the receive FIFO.
The RSR register cannot be directly accessed by the CPU.
32.2.2
Receive Data Register (RDR)
Address(es): SCI0.RDR 4007 0005h, SCI1.RDR 4007 0025h, SCI2.RDR 4007 0045h, SCI3.RDR 4007 0065h,
SCI4.RDR 4007 0085h, SCI5.RDR 4007 00A5h, SCI6.RDR 4007 00C5h, SCI7.RDR 4007 00E5h,
SCI8.RDR 4007 0105h, SCI9.RDR 4007 0125h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
RDR is an 8-bit register that stores receive data. When one frame of serial data is received, the received serial data is
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32. Serial Communications Interface (SCI)
transferred from the RSR register to the RDR register, and the RSR register can receive more data. Because RSR and
RDR function as a double buffer, continuous receive operations can be performed.
Read the RDR register only once after a receive data full interrupt (SCIn_RXI) occurs.
Note:
If the next frame of data is received before the receive data is read from the RDR register, an overrun error
occurs. The RDR register cannot be written to by the CPU.
32.2.3
Receive 9-Bit Data Register (RDRHL)
Address(es): SCI0.RDRHL 4007 0010h, SCI1.RDRHL 4007 0030h, SCI2.RDRHL 4007 0050h, SCI3.RDRHL 4007 0070h,
SCI4.RDRHL 4007 0090h, SCI5.RDRHL 4007 00B0h, SCI6.RDRHL 4007 00D0h, SCI7.RDRHL 4007 00F0h,
SCI8.RDRHL 4007 0110h, SCI9.RDRHL 4007 0130h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RDRHL is a 16-bit register that stores receive data. Use this register when asynchronous mode and 9-bit data length are
selected.
The lower 8 bits of RDRHL are a shadow register of RDR, so access to the RDRHL register affects the RDR register.
Access to the RDRHL register is prohibited if 7-bit or 8-bit data length is selected.
After one frame of data is received, the received data is transferred from the RSR register to the RDRHL register,
allowing the RSR register to receive more data.
The RSR and RDRHL registers have a double-buffered structure to enable continuous reception. The RDRHL register
should be read only when a receive data full interrupt (SCIn_RXI) request is issued. An overrun error occurs when the
next frame of data is received before the received data is read from the RDRHL register.
The CPU cannot write to the RDRHL register. Bits [15:9] are fixed to 0. These bits are read as 0. The write value should
be 0.
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32.2.4
32. Serial Communications Interface (SCI)
Receive FIFO Data Register H, L, HL (FRDRH, FRDRL, FRDRHL)
Receive FIFO Data Register H (FRDRH)
Address(es): SCI0.FRDRH 4007 0010h, SCI1.FRDRH 4007 0030h, SCI2.FRDRH 4007 0050h, SCI3.FRDRH 4007 0070h,
SCI4.FRDRH 4007 0090h, SCI5.FRDRH 4007 00B0h, SCI6.FRDRH 4007 00D0h, SCI7.FRDRH 4007 00F0h,
SCI8.FRDRH 4007 0110h, SCI9.FRDRH 4007 0130h
Receive FIFO Data Register L (FRDRL)
Address(es): SCI0.FRDRL 4007 0011h, SCI1.FRDRL 4007 0031h, SCI2.FRDRL 4007 0051h, SCI3.FRDRL 4007 0071h,
SCI4.FRDRL 4007 0091h, SCI5.FRDRL 4007 00B1h, SCI6.FRDRL 4007 00D1h, SCI7.FRDRL 4007 00F1h,
SCI8.FRDRL 4007 0111h, SCI9.FRDRL 4007 0131h
Receive FIFO Data Register HL (FRDRHL)
Address(es): SCI0.FRDRHL 4007 0010h, SCI1.FRDRHL 4007 0030h, SCI2.FRDRHL 4007 0050h, SCI3.FRDRHL 4007 0070h,
SCI4.FRDRHL 4007 0090h, SCI5.FRDRHL 4007 00B0h, SCI6.FRDRHL 4007 00D0h, SCI7.FRDRHL 4007 00F0h,
SCI8.FRDRHL 4007 0110h, SCI9.FRDRHL 4007 0130h
SCIn.FRDRHL
SCIn.FRDRH
SCIn.FRDRL
b15
b14
b13
b12
b11
b10
b9
—
RDF
ORER
FER
PER
DR
MPB
0
0
0
0
0
0
0
Value after reset:
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
RDAT[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
RDAT[8:0]
Serial Receive Data
Valid only in asynchronous mode, including multi-processor
mode, and clock synchronous mode, and with FIFO selected.
Stores the serial receive data.
R
b9
MPB
Multi-Processor Bit Flag
Stores the value of the multi-processor bit in the serial receive
data (RDAT[8:0]):
0: Data transmission cycle
1: ID transmission cycle.
Valid only in asynchronous mode with SMR.MP = 1, and with
FIFO selected.
R
b10
DR
Receive Data Ready Flag
This flag is the same as SSR_FIFO.DR:
0: Receiving is in progress, or no received data remains in the
FRDRH and FRDRL registers after reception is successfully
completed
1: Next receive data is not received for a period after reception is
successfully completed.
R*1
b11
PER
Parity Error Flag
0: No parity error occurred in the first data of FRDRH and FRDRL R
1: Parity error occurred in the first data of FRDRH and FRDRL.
b12
FER
Framing Error Flag
0: No framing error occurred in the first data of FRDRH and
R
FRDRL
1: Framing error occurred in the first data of FRDRH and FRDRL.
b13
ORER
Overrun Error Flag
This flag is the same as SSR_FIFO.ORER:
0: No overrun error occurred
1: Overrun error occurred.
R*1
b14
RDF
Receive FIFO Data Full Flag
This flag is the same as SSR_FIFO.RDF:
0: The amount of receive data written in FRDRH and FRDRL is
less than the specified receive triggering number
1: The amount of receive data written in FRDRH and FRDRL is
equal to or greater than the specified receive triggering
number.
R*1
b15
—
Reserved
This bit is read as 0
R
Note 1.
If this flag is read, it indicates the same value as that read from the SSR_FIFO register. Write 0 to the SSR_FIFO register to
clear the flag.
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32. Serial Communications Interface (SCI)
FRDRHL is a 16-bit register that consists of the 8-bit FRDRH and FRDRL registers.
FRDRH and FRDRL constitute a 16-stage FIFO register that stores serial receive data and related status information
readable by software. This register is only valid in asynchronous mode, including multi-processor mode, or clock
synchronous mode.
The SCI completes reception of one frame of serial data by transferring the received data from the Receive Shift Register
(RSR) into FRDRH and FRDRL for storage. Continuous reception is executed until 16 stages are stored. If data is read
when there is no received data in FRDRH and FRDRL, the value is undefined. When FRDRH and FRDRL are full,
subsequent serial receive data is lost. The CPU can read from the FRDRH and FRDRL registers but cannot write to
them.
Reading 1 from the RDF, ORER, or DR flags of the FRDRH register is the same as reading from those bits in the
SSR_FIFO register. When writing 0 to clear a flag in the SSR_FIFO register after reading the FRDRH register, write 0
only to the flag that is to be cleared and write 1 to the other flags.
When reading both the FRDRH and FRDRL registers, read in the order from FRDRH to FRDRL. FDRHL register can
be accessed in 16-bit units.
32.2.5
Transmit Data Register (TDR)
Address(es): SCI0.TDR 4007 0003h, SCI1.TDR 4007 0023h, SCI2.TDR 4007 0043h, SCI3.TDR 4007 0063h,
SCI4.TDR 4007 0083h, SCI5.TDR 4007 00A3h, SCI6.TDR 4007 00C3h, SCI7.TDR 4007 00E3h,
SCI8.TDR 4007 0103h, SCI9.TDR 4007 0123h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
TDR is an 8-bit register that stores transmit data.
When the SCI detects that the TSR register is empty, it transfers the transmit data written in the TDR register to the TSR
register and starts transmission.
The double-buffered structure of the TDR and TSR registers enables continuous serial transmission. If the next transmit
data is already written to TDR when one frame of data is transmitted, the SCI transfers the written data to the TSR
register to continue transmission.
The CPU can read from or write to TDR at any time. Only write transmit data to TDR once after each instance of the
transmit data empty interrupt (SCIn_TXI).
32.2.6
Transmit 9-Bit Data Register (TDRHL)
Address(es): SCI0.TDRHL 4007 000Eh, SCI1.TDRHL 4007 002Eh, SCI2.TDRHL 4007 004Eh, SCI3.TDRHL 4007 006Eh,
SCI4.TDRHL 4007 008Eh, SCI5.TDRHL 4007 00AEh, SCI6.TDRHL 4007 00CEh, SCI7.TDRHL 4007 00EEh,
SCI8.TDRHL 4007 010Eh, SCI9.TDRHL 4007 012Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TDRHL is a 16-bit register that stores transmit data. Use the TDRHL register when asynchronous mode and 9-bit data
length are selected.
The lower 8 bits of TDRHL are a shadow register of TDR, so access to TDRHL affects the TDR register. Access to the
TDRHL register is prohibited if 7-bit or 8-bit data length is selected.
When empty space is detected in the TSR register, the transmit data stored in the TDRHL register is transferred to the
TSR register and transmission starts.
The TSR and TDRHL registers have a double-buffered structure to support continuous transmission. When the next data
to be transmitted is stored in TDRHL after one frame of data is transmitted, the transmitting operation is continued by
transferring the data from the TDRHL register to the TSR register.
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32. Serial Communications Interface (SCI)
The CPU can read from and write to the TDRHL register. Bits [15:9] in the TDRHL register are fixed to 1. These bits are
read as 1. The write value should be 1.
Write transmit data to the TDRHL register only once a transmit data empty interrupt (SCIn_TXI) request is issued.
32.2.7
Transmit FIFO Data Register H, L, HL (FTDRH, FTDRL, FTDRHL)
Transmit FIFO Data Register H (FTDRH)
Address(es): SCI0.FTDRH 4007 000Eh, SCI1.FTDRH 4007 002Eh, SCI2.FTDRH 4007 004Eh, SCI3.FTDRH 4007 006Eh,
SCI4.FTDRH 4007 008Eh, SCI5.FTDRH 4007 00AEh, SCI6.FTDRH 4007 00CEh, SCI7.FTDRH 4007 00EEh,
SCI8.FTDRH 4007 010Eh, SCI9.FTDRH 4007 012Eh
Transmit FIFO Data Register L (FTDRL)
Address(es): SCI0.FTDRL 4007 000Fh, SCI1.FTDRL 4007 002Fh, SCI2.FTDRL 4007 004Fh, SCI3.FTDRL 4007 006Fh,
SCI4.FTDRL 4007 008Fh, SCI5.FTDRL 4007 00AFh, SCI6.FTDRL 4007 00CFh, SCI7.FTDRL 4007 00EFh,
SCI8.FTDRL 4007 010Fh, SCI9.FTDRL 4007 012Fh
Transmit FIFO Data Register HL (FTDRHL)
Address(es): SCI0.FTDRHL 4007 000Eh, SCI1.FTDRHL 4007 002Eh, SCI2.FTDRHL 4007 004Eh, SCI3.FTDRHL 4007 006Eh,
SCI4.FTDRHL 4007 008Eh, SCI5.FTDRHL 4007 00AEh, SCI6.FTDRHL 4007 00CEh, SCI7.FTDRHL 4007 00EEh,
SCI8.FTDRHL 4007 010Eh, SCI9.FTDRHL 4007 012Eh
SCIn.FTDRHL
SCIn.FTDRH
SCIn.FTDRL
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
MPBT
1
1
1
1
1
1
1
Value after reset:
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
TDAT[8:0]
1
1
1
1
1
Bit
Symbol
Bit name
Description
R/W
b8 to b0
TDAT[8:0]
Serial Transmit Data
Specifies the serial transmit data.
Valid only in asynchronous mode, including multi-processor
mode, and clock synchronous mode, and with FIFO selected.
W
b9
MPBT
Multi-Processor Transfer Bit Flag
Specifies the multi-processor bit in the transmission frame:
0: Data transmission cycle
1: ID transmission cycle.
Valid only in asynchronous mode with SMR.MP = 1, and with
FIFO selected.
W
b15 to b10
—
Reserved
The write value should be 1
W
FTDRHL is a 16-bit register that consists of 8-bit registers, FTDRH and FTDRL.
FTDRH and FTDRL constitute a 16-stage FIFO register that stores data for serial transmission and a multi-processor
transfer bit. This register is only valid in asynchronous mode, including multi-processor mode, or clock synchronous
mode.
When the SCI detects that the Transmit Shift Register (TSR) is empty, it transfers data written in the FTDRH and
FTDRL registers to the TSR register and starts serial transmission. Continuous serial transmission is executed until no
transmit data is left in FTDRH and FTDRL. When FTDRHL is full of transmit data, no more data can be written. If
writing new data is attempted, the data is ignored. The CPU can write to the FTDRH and FTDRL registers but cannot
read them.
When writing to both the FTDRH and FTDRL registers, write in the order from FTDRH to FTDRL.
MPBT flag (Multi-Processor Transfer Bit Flag)
The MPBT flag specifies the value of the multi-processor bit of the transmit frame. When FCR.FM = 1, SSR.MPBT is
invalid.
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32.2.8
32. Serial Communications Interface (SCI)
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers
transmit data from TDR, TDRHL, or transmit FIFO to the TSR register, and then sends the data to the TXDn pin. The
CPU cannot directly access the TSR register.
32.2.9
Serial Mode Register (SMR) for Non-Smart Card Interface Mode
(SCMR.SMIF = 0)
Address(es): SCI0.SMR 4007 0000h, SCI1.SMR 4007 0020h, SCI2.SMR 4007 0040h, SCI3.SMR 4007 0060h,
SCI4.SMR 4007 0080h, SCI5.SMR 4007 00A0h, SCI6.SMR 4007 00C0h, SCI7.SMR 4007 00E0h,
SCI8.SMR 4007 0100h, SCI9.SMR 4007 0120h
b7
b6
b5
b4
b3
b2
CM
CHR
PE
PM
STOP
MP
0
0
0
0
0
0
Value after reset:
b1
b0
CKS[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKS[1:0]
Clock Select
b1 b0
R/W*4
b2
MP
Multi-Processor Mode
Valid only in asynchronous mode:
0: Disable multi-processor communications function
1: Enable multi-processor communications function.
R/W*4
b3
STOP
Stop Bit Length
Valid only in asynchronous mode:
0: 1 stop bit
1: 2 stop bits.
R/W*4
b4
PM
Parity Mode
Valid only when the PE bit is 1:
0: Selects even parity
1: Selects odd parity.
R/W*4
b5
PE
Parity Enable
Valid only in asynchronous mode:
When transmitting:
0: Do not add parity bit
1: Add parity bit.
When receiving:
0: Do not check parity bit
1: Check parity bit.
R/W*4
b6
CHR
Character Length
Selects the transmit/receive character length in combination
with the SCMR.CHR1 bit:
R/W*4
0
0
1
1
0: PCLKA clock (n = 0)*1
1: PCLKA/4 clock (n = 1)*1
0: PCLKA/16 clock (n = 2)*1
1: PCLKA/64 clock (n = 3).*1
CHR1 CHR
0 0: Transmit/receive in 9-bit data length
0 1: Transmit/receive in 9-bit data length
1 0: Transmit/receive in 8-bit data length (initial value)
1 1: Transmit/receive in 7-bit data length.*3
Valid only in asynchronous mode.*2
b7
Note 1.
Note 2.
Note 3.
Note 4.
CM
Communication Mode
R/W*4
0: Asynchronous mode or simple IIC mode
1: Clock synchronous mode or simple SPI mode.
n is the decimal notation of the value of n in the BRR register. See section 32.2.17, Bit Rate Register (BRR).
In any mode other than asynchronous mode, this bit setting is invalid and a fixed data length of 8 bits is used.
LSB-first is fixed and the MSB (bit [7]) in the TDR register is not transmitted in transmit mode.
Writable only when SCR.TE = 0 and SCR.RE = 0 (both serial transmission and reception are disabled).
The SMR register sets the communication format and the clock source for the on-chip baud rate generator.
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32. Serial Communications Interface (SCI)
CKS[1:0] bits (Clock Select)
The CKS[1:0] bits select the clock source for the on-chip baud rate generator. For the relationship between the settings of
these bits and the baud rate, see section 32.2.17, Bit Rate Register (BRR).
MP bit (Multi-Processor Mode)
The MP bit disables or enables the multi-processor communications function. The PE and PM bit settings are invalid in
multi-processor mode.
STOP bit (Stop Bit Length)
The STOP bit selects the stop bit length in transmission.
In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the
start bit of the next transmit frame.
PM bit (Parity Mode)
The PM bit selects the parity mode (even or odd) for transmission and reception. The PM bit setting is invalid in multiprocessor mode.
PE bit (Parity Enable)
When the PE bit is set to 1, the parity bit is added to the transmit data, and the parity bit is checked at reception.
Regardless of the PE bit setting, the parity bit is not added or checked in multi-processor format.
CHR bit (Character Length)
The CHR bit selects the data length for transmission and reception in combination with the SCMR.CHR1 bit. In modes
other than asynchronous, a fixed data length of 8 bits is used.
CM bit (Communication Mode)
The CM bit selects the communication mode:
Asynchronous mode or simple IIC mode
Clock synchronous mode or simple SPI mode.
32.2.10
Serial Mode Register for Smart Card Interface Mode (SMR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SMR_SMCI 4007 0000h, SCI1.SMR_SMCI 4007 0020h, SCI2.SMR_SMCI 4007 0040h, SCI3.SMR_SMCI 4007 0060h,
SCI4.SMR_SMCI 4007 0080h, SCI5.SMR_SMCI 4007 00A0h, SCI6.SMR_SMCI 4007 00C0h, SCI7.SMR_SMCI 4007 00E0h,
SCI8.SMR_SMCI 4007 0100h, SCI9.SMR_SMCI 4007 0120h
b7
b6
b5
b4
GM
BLK
PE
PM
0
0
0
0
Value after reset:
b3
b2
b1
b0
BCP[1:0]
CKS[1:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKS[1:0]
Clock Select
b1 b0
R/W*2
b3, b2
BCP[1:0]
Base Clock Pulse
Selects the number of base clock cycles in combination with
the SCMR.BCP2 bit. Table 32.3 lists the combinations of the
SCMR.BCP2 and SMR.BCP[1:0] bits.
R/W*2
b4
PM
Parity Mode
Valid only when the PE bit is 1:
0: Selects even parity
1: Selects odd parity.
R/W*2
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0 0: PCLKA clock (n = 0)*1
0 1: PCLKA/4 clock (n = 1)*1
1 0: PCLKA/16 clock (n = 2)*1
1 1: PCLKA/64 clock (n = 3).*1
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32. Serial Communications Interface (SCI)
Bit
Symbol
Bit name
Description
R/W
b5
PE
Parity Enable
When this bit is set to 1, a parity bit is added to transmit data,
and the parity of received data is checked. Set this bit to 1 in
smart card interface mode.
R/W*2
b6
BLK
Block Transfer Mode
0: Non-block transfer mode operation
1: Block transfer mode operation.
R/W*2
b7
GM
GSM Mode
0: Non-GSM mode operation
1: GSM mode operation.
R/W*2
Note 1.
Note 2.
n is the decimal notation of the value of n in the BRR register. See section 32.2.17, Bit Rate Register (BRR).
Writable only when SCR_SMCI.TE = 0 and SCR_SMCI.RE = 0 (both serial transmission and reception are disabled).
The SMR_SMCI register sets the communication format and clock source for the on-chip baud rate generator.
CKS[1:0] bit (Clock Select)
The CKS[1:0] bits select the clock source for the on-chip baud rate generator. For the relationship between the settings of
these bits and the baud rate, see section 32.2.17, Bit Rate Register (BRR).
BCP[1:0] bits (Base Clock Pulse)
The BCP[1:0] bits select the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set
these bits in combination with the SCMR.BCP2 bit.
For details, see section 32.6.4, Receive Data Sampling Timing and Reception Margin.
Table 32.3
Combinations of SCMR.BCP2 and SMR_SMCI.BCP[1:0] bits
SCMR.BCP2 bit
Note 1.
SMR_SMCI.BCP[1:0] bits
Number of base clock cycles for 1-bit transfer period
0
00
93 clock cycles (S = 93)*1
0
01
128 clock cycles (S = 128)*1
0
10
186 clock cycles (S = 186)*1
0
11
512 clock cycles (S = 512)*1
1
00
32 clock cycles (S = 32)*1 (initial value)
1
01
64 clock cycles (S = 64)*1
1
10
372 clock cycles (S = 372)*1
1
11
256 clock cycles (S = 256)*1
S is the value of S in the BRR register. See section 32.2.17, Bit Rate Register (BRR).
PM bit (Parity Mode)
The PM bit selects the parity mode for transmission and reception (even or odd). For details on the usage of this bit in
smart card interface mode, see section 32.6.2, Data Format (Except in Block Transfer Mode).
PE bit (Parity Enable)
Set the PE bit to 1. The parity bit is added to the transmit data before transmission, and the parity bit is checked at
reception.
BLK bit (Block Transfer Mode)
Setting the BLK bit to 1 enables the block transfer mode operation. For details, see section 32.6.3, Block Transfer Mode.
GM bit (GSM Mode)
Setting the GM bit to 1 enables GSM mode operation.
In GSM mode, the SSR_SMCI.TEND flag set timing is moved forward to 11.0 ETUs (elementary time unit = 1-bit
transfer time) from the start bit, and the clock output control function is enabled. For details, see section 32.6.6, Serial
Data Transmission (Except in Block Transfer Mode) and section 32.6.8, Clock Output Control.
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32.2.11
32. Serial Communications Interface (SCI)
Serial Control Register (SCR) for Non-Smart Card Interface Mode (SCMR.SMIF
= 0)
Address(es): SCI0.SCR 4007 0002h, SCI1.SCR 4007 0022h, SCI2.SCR 4007 0042h, SCI3.SCR 4007 0062h,
SCI4.SCR 4007 0082h, SCI5.SCR 4007 00A2h, SCI6.SCR 4007 00C2h, SCI7.SCR 4007 00E2h,
SCI8.SCR 4007 0102h, SCI9.SCR 4007 0122h
b7
b6
b5
b4
b3
b2
TIE
RIE
TE
RE
MPIE
TEIE
0
0
0
0
0
0
Value after reset:
b1
b0
CKE[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKE[1:0]
Clock Enable
Asynchronous mode:
R/W*1
b1 b0
0 0: On-chip baud rate generator.
The SCKn pin is available for use as an I/O port
based on the I/O port settings
0 1: On-chip baud rate generator.
A clock with the same frequency as the bit rate is
output from the SCKn pin
1 x: External clock.
Input a clock with a frequency 16 times the bit rate
from the SCKn pin when the SEMR.ABCS bit is 0.
Input a clock signal with a frequency eight times the
bit rate when the SEMR.ABCS bit is 1.
Clock synchronous mode:
b1 b0
0 x: Internal clock
The SCKn pin functions as the clock output pin
1 x: External clock
The SCKn pin functions as the clock input pin.
b2
TEIE
Transmit End Interrupt Enable
0: Disable SCIn_TEI interrupt requests
1: Enable SCIn_TEI interrupt requests.
R/W
b3
MPIE
Multi-Processor Interrupt Enable
Valid in asynchronous mode when SMR.MP = 1:
0: Non-multiprocessor reception
1: When data with the multi-processor bit set to 0 is
received, the data is not read, and setting the status
flags RDRF, ORER, and FER in SSR to 1 is disabled.
When data with the multi-processor bit set to 1 is
received, the MPIE bit is automatically set to 0, and
non-multiprocessor reception is resumed.
R/W*3
b4
RE
Receive Enable
0: Disable serial reception
1: Enable serial reception.
R/W*2
b5
TE
Transmit Enable
0: Disable serial transmission
1: Enable serial transmission.
R/W*2
b6
RIE
Receive Interrupt Enable
0: Disable SCIn_RXI and SCIn_ERI interrupt requests
1: Enable SCIn_RXI and SCIn_ERI interrupt requests.
R/W
b7
TIE
Transmit Interrupt Enable
0: Disable SCIn_TXI interrupt requests
1: Enable SCIn_TXI interrupt requests.
R/W
x: Don’t care
Note 1.
Note 2.
Note 3.
Writable only when TE = 0 and RE = 0.
1 can be written only when TE = 0 and RE = 0, when the SMR.CM bit is 1. After setting TE or RE to 1, only 0 can be written to
TE and RE. When the SMR.CM bit is 0 and the SIMR1.IICM bit is 0, writing is enabled under any condition.
When writing a new value to a bit other than the MPIE bit of this register in multi-processor mode (SMR.MP bit = 1), write 0 to
the MPIE bit using the store instruction to avoid accidentally setting the MPIE bit to 1 by a read-modify-write operation when
using a bit manipulation instruction.
The SCR register controls operation and clock source selection for transmission and reception.
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32. Serial Communications Interface (SCI)
CKE[1:0] bits (Clock Enable)
The CKE[1:0] bits select the clock source and the SCKn pin function.
TEIE bit (Transmit End Interrupt Enable)
The TEIE bit enables or disables SCIn_TEI interrupt requests. Set TEIE to 0 to disable an SCIn_TEI interrupt request.
In simple IIC mode, SCIn_TEI is allocated to the interrupt on completion of issuing a start, restart, or stop condition
(STIn). In this case, the TEIE bit can be used to enable or disable the STI.
MPIE bit (Multi-Processor Interrupt Enable)
When the MPIE bit is set to 1 and data with the multi-processor bit set to 0 is received, the data is not read, and setting
the status flags RDRF, RDF, ORER, and FER in SSR/SSR_FIFO to 1 is disabled. When data with the multi-processor bit
set to 1 is received, the MPIE bit is automatically cleared to 0, and non-multiprocessor reception resumes. For details, see
section 32.4, Multi-Processor Communication Function.
When the MPB bit in the SSR register is 0, the receive data is not transferred from the RSR register to the RDR register,
a receive error is not detected, and setting the flags ORER and FER to 1 is disabled.
When the MPB bit is set to 1, the MPIE bit is automatically set to 0, SCIn_RXI and SCIn_ERI interrupt requests are
enabled (if the RIE bit in SCR is set to 1), and setting of the ORER and FER flags to 1 is enabled.
Set MPIE to 0 if the multi-processor communications function is not used.
RE bit (Receive Enable)
The RE bit enables or disables serial reception. When the RE bit is set to 1, serial reception starts by detecting the start bit
in asynchronous mode or the synchronous clock input in clock synchronous mode. Set the reception format in the SMR
register before setting the RE bit to 1.
When non-FIFO operation is selected and reception is halted by setting the RE bit to 0, the RDRF, ORER, FER, and PER
flags in the SSR register are not affected, and the previous values are saved.
When FIFO operation is selected and reception is halted by setting the RE bit to 0, the RDF, ORER, FER, PER, and DR
flags in SSR_FIFO are not affected and the previous values are saved.
TE bit (Transmit Enable)
The TE bit enables or disables serial transmission.
When the TE bit is set to 1, serial transmission starts by writing transmit data to the TDR register. Set the transmission
format in the SMR register before setting the TE bit to 1.
RIE bit (Receive Interrupt Enable)
The RIE bit enables or disables SCIn_RXI and SCIn_ERI interrupt requests.
Setting the RIE bit to 0 disables SCIn_RXI and SCIn_ERI interrupt requests.
To cancel an SCIn_ERI interrupt request, read 1 from the ORER, FER, or PER flag in SSR/SSR_FIFO, then set the flag
to 0, or set the RIE bit to 0.
TIE bit (Transmit Interrupt Enable)
The TIE bit enables or disables SCIn_TXI interrupt requests. Set TIE to 0 to disable the SCIn_TXI interrupt requests. Set
the TIE bit to 1 while the TE bit is 1. Set TE and TIE simultaneously to 1 before the transfer starts, for the SCIn_TXI
interrupt to occur.
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32.2.12
32. Serial Communications Interface (SCI)
Serial Control Register for Smart Card Interface Mode (SCR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SCR_SMCI 4007 0002h, SCI1.SCR_SMCI 4007 0022h, SCI2.SCR_SMCI 4007 0042h, SCI3.SCR_SMCI 4007 0062h,
SCI4.SCR_SMCI 4007 0082h, SCI5.SCR_SMCI 4007 00A2h, SCI6.SCR_SMCI 4007 00C2h, SCI7.SCR_SMCI 4007 00E2h,
SCI8.SCR_SMCI 4007 0102h, SCI9.SCR_SMCI 4007 0122h
b7
b6
b5
b4
b3
b2
TIE
RIE
TE
RE
MPIE
TEIE
0
0
0
0
0
0
Value after reset:
b1
b0
CKE[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKE[1:0]
Clock Enable
When SMR_SMCI.GM = 0:
R/W*1
b1 b0
0 0: Disable output
The SCKn pin is available for use as an I/O port if
set up in the I/O port settings
0 1: Output clock
1 x: Setting prohibited.
When SMR_SMCI.GM = 1:
b1 b0
0 0: Fix output low
x 1: Output clock
1 0: Fix output high.
b2
TEIE
Transmit End Interrupt Enable
Set this bit to 0 in smart card interface mode
R/W
b3
MPIE
Multi-Processor Interrupt Enable
Set this bit to 0 in smart card interface mode
R/W
b4
RE
Receive Enable
0: Disable serial reception
1: Enable serial reception.
R/W*2
b5
TE
Transmit Enable
0: Disable serial transmission
1: Enable serial transmission.
R/W*2
b6
RIE
Receive Interrupt Enable
0: Disable SCIn_RXI and SCIn_ERI interrupt requests
1: Enable SCIn_RXI and SCIn_ERI interrupt requests.
R/W
b7
TIE
Transmit Interrupt Enable
0: Disable SCIn_TXI interrupt requests
1: Enable SCIn_TXI interrupt requests.
R/W
x: Don’t care
Note 1.
Note 2.
Writable only when TE = 0 and RE = 0.
1 can be written only when TE = 0 and RE = 0. After setting TE or RE to 1, only 0 can be written to TE and RE.
The SCR_SMCI register sets the transmission and reception control, interrupt control, and clock source selection for
transmission and reception.
For details on interrupt requests, see section 32.10, Interrupt Sources.
CKE[1:0] bits (Clock Enable)
The CKE[1:0] bits control the clock output from the SCKn pin.
In GSM mode, clock output can be dynamically switched. For details, see section 32.6.8, Clock Output Control.
TEIE bit (Transmit End Interrupt Enable)
Set the TEIE bit to 0 in smart card interface mode.
MPIE bit (Multi-Processor Interrupt Enable)
Set the MPIE bit to 0 in smart card interface mode.
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32. Serial Communications Interface (SCI)
RE bit (Receive Enable)
The RE bit enables or disables serial reception.
When the RE bit is set to 1, serial reception starts by detecting the start bit. Set the reception format in the SMR_SMCI
register before setting the RE bit to 1.
If reception is halted by setting the RE bit to 0, the ORER, FER, and PER flags in SSR_SMCI are not affected and the
previous values are saved.
TE bit (Transmit Enable)
The TE bit enables or disables serial transmission. When the TE bit is set to 1, serial transmission is started by writing
transmit data to TDR. Set the transmission format in the SMR_SMCI register before setting the TE bit to 1.
RIE bit (Receive Interrupt Enable)
The RIE bit enables or disables SCIn_RXI and SCIn_ERI interrupt requests. Setting the RIE bit to 0 disables SCIn_RXI
and SCIn_ERI interrupt requests.
To cancel an SCIn_ERI interrupt request, read 1 from the ORER, FER, or PER flag in the SSR_SMCI register, then set
the flag to 0, or set the RIE bit to 0.
TIE bit (Transmit Interrupt Enable)
The TIE bit enables or disables SCIn_TXI interrupt requests.
Set the TIE bit to 0 to disable the SCIn_TXI interrupt requests. Set the TIE bit to 1 while the TE bit is 1. Set the TE and
TIE bits to 1 simultaneously before transfer starts, for the SCIn_TXI interrupt to occur.
32.2.13
Serial Status Register (SSR) for Non-Smart Card Interface and Non-FIFO Mode
(SCMR.SMIF = 0 and FCR.FM = 0)
Address(es): SCI0.SSR 4007 0004h, SCI1.SSR 4007 0024h, SCI2.SSR 4007 0044h, SCI3.SSR 4007 0064h,
SCI4.SSR 4007 0084h, SCI5.SSR 4007 00A4h, SCI6.SSR 4007 00C4h, SCI7.SSR 4007 00E4h,
SCI8.SSR 4007 0104h, SCI9.SSR 4007 0124h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MPBT
Multi-Processor Bit Transfer
Sets the value of the multi-processor bit in the
transmission frame:
0: Data transmission cycle
1: ID transmission cycle.
R/W
b1
MPB
Multi-Processor
Value of the multi-processor bit in the reception frame:
0: Data transmission cycle
1: ID transmission cycle.
R
b2
TEND
Transmit End Flag
0: A character is being transmitted
1: Character transfer is complete.
R
b3
PER
Parity Error Flag
0: No parity error occurred
1: Parity error occurred.
R/(W)*1
b4
FER
Framing Error Flag
0: No framing error occurred
1: Framing error occurred.
R/(W)*1
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: Overrun error occurred.
R/(W)*1
b6
RDRF
Receive Data Full Flag
0: No received data in RDR register
1: Received data in RDR register.
R/(W)*1
b7
TDRE
Transmit Data Empty Flag
0: Transmit data in TDR register
1: No transmit data in TDR register.
R/(W)*1
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Note 1.
32. Serial Communications Interface (SCI)
Only 0 can be written to clear the flag after reading 1.
The SSR register provides the SCI status flags and transmission and reception multi-processor bits.
MPBT bit (Multi-Processor Bit Transfer)
The MPBT bit sets the value of the multi-processor bit in the transmit frame.
MPB bit (Multi-Processor)
The MPB bit holds the value of the multi-processor bit in the reception frame. This bit does not change when the
SCR.RE bit is 0.
TEND flag (Transmit End Flag)
The TEND flag indicates the completion of transmission.
[Setting conditions]
When the SCR.TE bit is set to 0 to disable serial transmission and the FCR.FM bit is set to 0 (non-FIFO selected).
When the SCR.TE bit is set to 1, the TEND flag is not affected and keeps the value 1.
When the TDR register is not updated on transmission of the tail-end bit of a character being transmitted.
[Clearing conditions]
When transmit data is written to the TDR register while the SCR.TE bit is 1
When 0 is written to TDRE after reading TDRE = 1 while the SCR.TE bit is 1.
PER flag (Parity Error Flag)
The PER flag indicates that a parity error occurred during reception in asynchronous mode and the reception ended
abnormally.
[Setting condition]
When a parity error is detected during reception in asynchronous mode, when the address match function is disabled
(DCCR.DCME = 0).
Although receive data is transferred to the RDR register when the parity error occurs, no SCIn_RXI interrupt
request occurs. When the PER flag is set to 1, the subsequent receive data is not transferred to the RDR register.
[Clearing condition]
When 0 is written to PER after reading PER = 1. After writing 0 to the PER bit, read the PER bit to check that it is
actually set to 0.
When the SCR.RE bit is set to 0 to disable serial reception, the PER flag is not affected and retains its previous value.
FER flag (Framing Error Flag)
The FER flag indicates that a framing error occurred during reception in asynchronous mode and the reception ended
abnormally.
[Setting condition]
When 0 is sampled as the stop bit during reception in asynchronous mode when the address match function is
disabled (DCCR.DCME = 0).
In 2-stop-bit mode, only the first stop bit is checked, but the second stop bit is not checked. Although receive data is
transferred to the RDR register when the framing error occurs, no SCIn_RXI interrupt request occurs. Also, when
the FER flag is to 1, the subsequent receive data is not transferred to the RDR register.
[Clearing condition]
When 0 is written to FER after reading FER = 1. After writing 0 to the FER bit, read the FER bit to check that it is
actually set to 0.
When the SCR.RE bit is set to 0 (serial reception is disabled), the FER flag is not affected and keeps its previous value.
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32. Serial Communications Interface (SCI)
ORER flag (Overrun Error Flag)
The ORER flag indicates that an overrun error occurred during reception and the reception ended abnormally.
[Setting condition]
When the next data is received before receive data that does not have a parity error and a framing error is read from
the RDR register.
The data received before an overrun error occurred is saved in the RDR register, but data received after the error is
lost. When the ORER flag is set to 1, receive data is not forwarded to the RDR register. In clock synchronous mode,
serial transmission and reception are stopped.
[Clearing condition]
When 0 is written to ORER flag after 1 is read. After writing 0 to the ORER bit, read the ORER bit to check that it
is actually set to 0.
When the SCR.RE bit is set to 0 to disable serial reception, the ORER flag is not affected and keeps its previous value.
RDRF flag (Receive Data Full Flag)
The RDRF flag indicates the presence of receive data in the RDR register.
[Setting condition]
When the reception ends normally, and receive data is forwarded from the RSR register to the RDR register.
[Clearing conditions]
When 0 is written to RDRF flag after 1 is read
When data is read from the RDR register.
Note:
Do not clear the RDRF flag by accessing RDRF bit in SSR register unless communication is aborted.
TDRE flag (Transmit Data Empty Flag)
The TDRE flag indicates the presence of transmit data in the TDR register.
[Setting conditions]
When the SCR.TE bit is 0
When data is transmitted from the TDR register to the TSR register.
[Clearing conditions]
When 0 is written to TDRE flag after 1 is read
When the SCR.TE bit is 1 and data is written to the TDR register.
Note:
Do not clear the RDRF flag by accessing RDRF bit in SSR register unless communication is aborted.
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32.2.14
32. Serial Communications Interface (SCI)
Serial Status Register for Non-Smart Card Interface and FIFO Mode
(SSR_FIFO) (SCMR.SMIF = 0 and FCR.FM = 1)
Address(es): SCI0.SSR_FIFO 4007 0004h, SCI1.SSR_FIFO 4007 0024h, SCI2.SSR_FIFO 4007 0044h, SCI3.SSR_FIFO 4007 0064h,
SCI4.SSR_FIFO 4007 0084h, SCI5.SSR_FIFO 4007 00A4h, SCI6.SSR_FIFO 4007 00C4h, SCI7.SSR_FIFO 4007 00E4h,
SCI8.SSR_FIFO 4007 0104h, SCI9.SSR_FIFO 4007 0124h
b7
b6
b5
b4
b3
b2
b1
b0
TDFE
RDF
ORER
FER
PER
TEND
—
DR
1
0
0
0
0
0
x
0
Value after reset:
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
DR
Receive Data Ready Flag
0: Receiving is in progress, or no received data remains
in FRDRHL after reception is successfully completed
(receive FIFO empty)
1: Next receive data is not received for a period after
normal reception is complete, when the amount of data
stored in the FIFO is equal to or less than the receive
triggering number.
R/(W)*1
b1
—
Reserved
The read value is undefined. The write value should be 1. R/W
b2
TEND
Transmit End Flag
0: A character is being transmitted
1: Character transfer is complete.
R/(W)*1
b3
PER
Parity Error Flag
0: No parity error occurred
1: Parity error occurred.
R/(W)*1
b4
FER
Framing Error Flag
0: No framing error occurred
1: Framing error occurred.
R/(W)*1
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: Overrun error occurred.
R/(W)*1
b6
RDF
Receive FIFO Data Full Flag
0: The amount of receive data written in FRDRHL is less
than the specified receive triggering number
1: The amount of receive data written in FRDRHL is
equal to or greater than the specified receive triggering
number.
R/(W)*1
b7
TDFE
Transmit FIFO Data Empty Flag
0: The amount of transmit data written in FTDRHL
exceeds the specified transmit triggering number
1: The amount of transmit data written in FTDRHL is
equal to or less than the specified transmit triggering
number.
R/(W)*1
Note 1.
Only 0 can be written, to clear the flag after reading 1.
The SSR_FIFO register provides the SCI with FIFO mode status flags.
DR flag (Receive Data Ready Flag)
The DR flag indicates that the amount of data stored in the Receive FIFO Data Register (FRDRHL) falls below the
specified receive triggering number, and that no next data is received after 15 ETUs (elementary time units) from the last
stop bit in asynchronous mode. This flag is valid only in asynchronous mode, including multi-processor mode, when
FIFO operation is selected.
In clock synchronous mode, the DR flag is not set to 1.
[Setting condition]
When FRDRHL contains less data than the specified receive triggering number, and no next data is received after
15 ETUs*1 from the last stop bit, and the SSR_FIFO.FER and SSR_FIFO.PER flags are 0.
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32. Serial Communications Interface (SCI)
[Clearing conditions]
When 1 is read from DR, after all received data is read
When the FCR.FM bit is changed from 0 to 1.
Note 1. This is equivalent to 1.5 frames in the 8-bit format with one stop bit.
The DR flag is only set to 1 when FIFO is selected in asynchronous mode, including multi-processor mode. It is
not set to 1 in other operation modes.
TEND flag (Transmit End Flag)
The TEND flag indicates that FTDRHL does not contain valid data when transmitting the last bit of a serial character, so
the transmission is halted.
[Setting condition]
When FTDRHL does not contain transmit data when the last bit of a 1-byte serial character is transmitted.
[Clearing conditions]
When transmit data is written to FTDRHL while the SCR.TE bit is 1
When 0 is written to TEND after 1 is read from TEND, when the SCR.TE bit is 1
When the FCR.FM bit is changed from 0 to 1.
PER flag (Parity Error Flag)
The PER flag indicates whether there is a parity error in the data read from the FRDRHL register in asynchronous mode
when the address match function is disabled (DCCR.DCME = 0).
[Setting condition]
When data is received and a parity error is detected, when the address match function is disabled (DCCR.DCME =
0).
[Clearing condition]
When 0 is written to PER after reading PER = 1.
The reception operation is continuous, and the receive data is stored in the FRDRHL register even when a parity error
occurs during reception.
When the SCR.RE bit is set to 0 (serial reception is disabled), the PER flag is not affected and keeps its previous value.
FER flag (Framing Error Flag)
The FER flag indicates whether there is a framing error in the data read from the FRDRHL register in asynchronous
mode when the address match function is disabled (DCCR.DCME = 0).
[Setting condition]
When 0 is sampled as the stop bit during reception when the address match function is disabled (DCCR.DCME =
0).
[Clearing condition]
When 0 is written to FER after reading FER = 1.
The reception operation is continuous, and the receive data is stored in the FRDRHL register, even when a framing error
occurs during reception.
When the SCR.RE bit is set to 0 (serial reception is disabled), the FER flag is not affected and keeps its previous value.
ORER flag (Overrun Error Flag)
The ORER flag indicates that the receive operation stopped abnormally because an overrun error occurred.
[Setting condition]
When the next serial reception completes while the receive FIFO is full with 16-byte receive data.
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32. Serial Communications Interface (SCI)
[Clearing condition]
When 0 is written to ORER after reading ORER = 1.
When the SCR.RE bit is set to 0 disabling serial reception, the ORER flag is not affected and keeps its previous value.
RDF flag (Receive FIFO Data Full Flag)
The RDF flag indicates that receive data is transferred to the FRDRHL register, and the amount of data in FRDRHL is
equal to or exceeds the specified receive triggering number. When RTRG is set to 0, the RDF flag is not set even when
the amount of data in the receive FIFO is equal to 0.
[Setting condition]
When the amount of receive data equal to or greater than the specified receive triggering number is stored in
FRDRHL,*1 and the FIFO is not empty.
[Clearing conditions]
When 0 is written to RDF after reading RDF = 1
When FRDRHL is read by the DMAC or DTC, but only when the block transfer is the last transmission
When the setting and clearing conditions occur at the same time, the RDF bit is set to 0. After that, when the amount
of data stored in the FRDRHL register is the same as or greater than the RTRG value, RDF is set to 1 after 1
PCLKA.
Note:
Do not clear the RDF flag by accessing RDF bit in the SSR register before reading receive data unless
communication is aborted.
Note 1. Because FRDRHL is a 16-stage FIFO register, the maximum amount of data that can be read when RDF is 1 is
equivalent to the specified receive triggering number. If an attempt is made to read after all the data in FRDRHL
is read, the data is undefined.
TDFE flag (Transmit FIFO Data Empty Flag)
The TDFE flag indicates that when data is transferred from the FTDRHL register into the TSR register, that the amount
of data in FTDRHL is below the specified transmit triggering number, and writing of transmit data to FTDRHL is
enabled.
[Setting conditions]
When the TE bit in SCR is 0
When the amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering
number.*1
[Clearing conditions]
When writing to FTDRHL is executed on the last transmission while the DMAC or DTC is activated
When 0 is written to the TDFE bit after reading TDFE = 1.
The setting conditions are given priority when TE = 0. When the setting condition and clearing condition occur at
the same time, the TDFE flag is set to 0. After that, when the amount of data stored in the FTDRHL register is equal
to or less than the TTRG value, TDFE is set to 1 after 1 PCLKA.
Note:
Do not clear the TDFE flag by accessing TDFE bit in the SSR register before writing transmit data unless
communication is aborted.
Note 1. Because the FTDRHL register is a 16-stage FIFO register, when the TDFE flag is 1, the maximum amount of
data that can be written to the FTDRHL register is 16 minus FDR.T[4:0] bytes. If more data is written, data is
discarded.
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32.2.15
32. Serial Communications Interface (SCI)
Serial Status Register for Smart Card Interface Mode (SSR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SSR_SMCI 4007 0004h, SCI1.SSR_SMCI 4007 0024h, SCI2.SSR_SMCI 4007 0044h, SCI3.SSR_SMCI 4007 0064h,
SCI4.SSR_SMCI 4007 0084h, SCI5.SSR_SMCI 4007 00A4h, SCI6.SSR_SMCI 4007 00C4h, SCI7.SSR_SMCI 4007 00E4h,
SCI8.SSR_SMCI 4007 0104h, SCI9.SSR_SMCI 4007 0124h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MPBT
Multi-Processor Bit Transfer
Set this bit to 0 in smart card interface mode
R/W
b1
MPB
Multi-Processor
Set this bit to 0 in smart card interface mode
R
b2
TEND
Transmit End Flag
0: A character is being transmitted
1: Character transfer is complete.
R
b3
PER
Parity Error Flag
0: No parity error occurred
1: Parity error occurred.
R/(W)*1
b4
ERS
Error Signal Status Flag
0: No low error signal response
1: Low error signal response occurred.
R/(W)*1
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: Overrun error occurred.
R/(W)*1
b6
RDRF
Receive Data Full Flag
0: No received data in RDR register
1: Received data in RDR register.
R/(W)*1
b7
TDRE
Transmit Data Empty Flag
0: Transmit data in TDR register
1: No transmit data in TDR register.
R/(W)*1
Note 1.
Only 0 can be written to clear the flag after reading 1.
The SSR_SMCI register provides SCI with smart card interface mode status flags.
TEND flag (Transmit End Flag)
When there is no error signal from the receiving side, the TEND flag is set to 1 when more data for transfer is ready to be
transferred to the TDR register.
[Setting conditions]
When the SCR_SMCI.TE bit = 0 to disable serial transmission. When the SCR_SMCI.TE bit is changed from 0 to
1, the TEND flag is not affected and keeps the value 1.
When a specified period elapses after the latest transmission of 1 byte, the ERS flag is 0, and the TDR register is not
updated.
The set timing is determined by the following register settings:
When SMR_SMCI.GM = 0 and SMR_SMCI.BLK = 0, 12.5 ETUs after the start of transmission
When SMR_SMCI.GM = 0 and SMR_SMCI.BLK = 1, 11.5 ETUs after the start of transmission
When SMR_SMCI.GM = 1 and SMR_SMCI.BLK = 0, 11.0 ETUs after the start of transmission
When SMR_SMCI.GM = 1 and SMR_SMCI.BLK = 1, 11.0 ETUs after the start of transmission.
[Clearing conditions]
When transmit data is written to the TDR register while the SCR_SMCI.TE bit is 1
When 0 is written to TDRE after reading 1 is read while the SCR_SMCI.TE bit is 1.
PER flag (Parity Error Flag)
The PER flag indicates that a parity error occurred during reception in asynchronous mode and the reception ended
abnormally.
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32. Serial Communications Interface (SCI)
[Setting condition]
When a parity error is detected during reception. Although receive data is transferred to RDR when a parity error
occurs, no SCIn_RXI interrupt request occurs. After the PER flag is set to 1, the subsequent receive data is not
transferred to RDR.
[Clearing condition]
When 0 is written to PER after reading PER = 1. After writing 0 to the PER bit, read the bit to check that it is
actually set to 0.
When the RE bit in SCR_SMCI is set to 0 (serial reception is disabled), the PER flag is not affected and keeps its
previous value.
ERS flag (Error Signal Status Flag)
[Setting condition]
When a low error signal is sampled.
[Clearing condition]
When 0 is written to the ERS flag after 1 is read.
ORER flag (Overrun Error Flag)
The ORER flag indicates that an overrun error occurred during reception and the reception ended abnormally.
[Setting condition]
When the next data is received before receive data that does not have a parity error is read from the RDR register.
The data received before an overrun error occurred is saved in the RDR, but data received after the error is lost.
When the ORER flag is set to 1, receive data is not forwarded to the RDR register.
[Clearing condition]
When 0 is written to the ORER flag after 1 is read. After writing 0 to the ORER flag, read it to verify that it is
actually set to 0.
When the RE bit in SCR_SMCI is set to 0, the ORER flag is not affected and keeps its previous value.
RDRF flag (Receive Data Full Flag)
The RDRF flag indicates the presence of receive data in the RDR register.
[Setting condition]
When the reception ends normally, and receive data is forwarded from the RSR register to the RDR register.
[Clearing conditions]
When 0 is written to the RDRF flag after 1 is read
When data is read from the RDR register.
Note:
Do not clear the RDRF flag by accessing RDRF bit in the SSR register unless communication is aborted.
TDRE flag (Transmit Data Empty Flag)
The TDRE flag indicates the presence of transmit data in the TDR register.
[Setting conditions]
When the SCR_SMCI.TE bit is 0
When data is transmitted from the TDR register to the TSR register.
[Clearing conditions]
When 0 is written to the TDRE flag after 1 is read
When the SCR_SMCI.TE bit is 1 and data is written to the TDR register.
Note:
Do not clear the TDRE flag by accessing TDRE bit in the SSR register unless communication is aborted.
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32.2.16
32. Serial Communications Interface (SCI)
Smart Card Mode Register (SCMR)
Address(es): SCI0.SCMR 4007 0006h, SCI1.SCMR 4007 0026h, SCI2.SCMR 4007 0046h, SCI3.SCMR 4007 0066h,
SCI4.SCMR 4007 0086h, SCI5.SCMR 4007 00A6h, SCI6.SCMR 4007 00C6h, SCI7.SCMR 4007 00E6h,
SCI8.SCMR 4007 0106h, SCI9.SCMR 4007 0126h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
BCP2
—
—
CHR1
SDIR
SINV
—
SMIF
1
1
1
1
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
SMIF
Smart Card Interface Mode Select
0: Non-smart card interface mode
(asynchronous mode, clock synchronous mode, simple
SPI mode, or simple IIC mode)
1: Smart card interface mode.
R/W*1
b1
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b2
SINV
Transmitted/Received Data Invert
0: TDR register contents are transmitted as they are. Receive
data is stored as received in the RDR register.
1: TDR register contents are inverted before being
transmitted. Receive data is stored in inverted form in the
RDR register.
R/W*1
The SINV bit can be used in the following modes:
Smart card interface mode
Asynchronous mode including multi-processor mode
Clock synchronous mode
Simple SPI mode.
Set the SINV bit to 0 for operation in simple IIC mode.
b3
SDIR
Transmitted/Received Data
Transfer Direction
R/W*1
0: Transfer LSB-first
1: Transfer MSB-first.
The SDIR bit can be used in the following modes:
Smart card interface mode
Asynchronous mode including multi-processor mode
Clock synchronous mode
Simple SPI mode.
Set the SDIR bit to 1 for operation in simple IIC mode.
b4
CHR1
Character Length 1
Valid only in asynchronous mode.*2
Selects the transmit/receive character length in combination
with the SMR.CHR bit:
R/W*1
CHR1 CHR
0
0
1
1
0: Transmit/receive in 9-bit data length
1: Transmit/receive in 9-bit data length
0: Transmit/receive in 8-bit data length (initial value)
1: Transmit/receive in 7-bit data length.*3
b6, b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b7
BCP2
Base Clock Pulse 2
Selects the number of base clock cycles in combination with
the SMR_SMCI.BCP[1:0] bits.
Table 32.4 lists the combinations of the SCMR.BCP2 and
SMR_SMCI.BCP[1:0] bits.
R/W*1
Note 1.
Note 2.
Note 3.
Writable only when the TE and RE bits in SCR/SCR_SMCI are 0 (both serial transmission and reception are disabled).
The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.
LSB-first must be selected and the value of the MSB (bit [7]) in TDR cannot be transmitted.
The SCMR register selects the smart card interface and communication format.
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32. Serial Communications Interface (SCI)
SMIF bit (Smart Card Interface Mode Select)
Setting the SMIF bit to 1 selects the smart card interface mode.
Setting SMIF to 0 selects all other modes as follows:
Asynchronous mode, including multi-processor mode
Clock synchronous mode
Simple SPI mode
Simple IIC mode.
SINV bit (Transmitted/Received Data Invert)
The SINV bit inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit.
To invert the parity bit, invert the PM bit in SMR or SMR_SMCI.
CHR1 bit (Character Length 1)
The CHR1 bit selects the data length of transmit/receive data in combination with the CHR bit in the SMR register.
A fixed data length of 8 bits is used in modes other than asynchronous mode.
BCP2 bit (Base Clock Pulse 2)
The BCP2 bit selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode.
Set this bit in combination with the SMR_SMCI.BCP[1:0] bits.
Table 32.4
Combinations of the SCMR.BCP2 and SMR_SMCI.BCP[1:0] bits
SCMR.BCP2 bit
SMR_SMCI.BCP[1:0] bits
Number of base clock cycles for 1-bit transfer period
0
00
93 clock cycles (S = 93)*1
0
01
128 clock cycles (S = 128)*1
0
10
186 clock cycles (S = 186)*1
0
11
512 clock cycles (S = 512)*1
1
00
32 clock cycles (S = 32)*1 (initial value)
1
01
64 clock cycles (S = 64)*1
1
10
372 clock cycles (S = 372)*1
1
11
256 clock cycles (S = 256)*1
Note 1.
See section 32.2.17, Bit Rate Register (BRR).
32.2.17
Bit Rate Register (BRR)
Address(es): SCI0.BRR 4007 0001h, SCI1.BRR 4007 0021h, SCI2.BRR 4007 0041h, SCI3.BRR 4007 0061h,
SCI4.BRR 4007 0081h, SCI5.BRR 4007 00A1h, SCI6.BRR 4007 00C1h, SCI7.BRR 4007 00E1h,
SCI8.BRR 4007 0101h, SCI9.BRR 4007 0121h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
BRR is an 8-bit register that adjusts the bit rate.
As each SCI channel has independent baud rate generator control, different bit rates can be set for each channel. Table
32.5 shows the relationship between the setting (N) and the bit rate (B) in the BRR for asynchronous mode, multiprocessor transfer, clock synchronous mode, smart card interface mode, simple SPI mode, and simple IIC mode.
The initial value of the BRR register is FFh. The BRR register can be read by the CPU, but it can be written to only when
the TE and RE bits in SCR/SCR_SMCI are 0.
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Table 32.5
32. Serial Communications Interface (SCI)
Relationship between N setting in BRR and bit rate B
SEMR settings
Mode
Asynchronous, multiprocessor
transfer
BGDM
bit
ABCS
bit
ABCSE
bit
0
0
0
BRR setting
N=
1
0
1
0
1
1
0
N=
N=
Don’t
care
PCLKA × 106
64 × 22n-1 × B
-1
Error (%) = {
-1
Error (%) = {
-1
Error (%) = {
-1
Error (%) = {
PCLKA × 106
B × 64 × 22n-1 × (N + 1)
- 1} × 100
0
0
Don’t
care
Error
1
Clock synchronous,
simple SPI
N=
N=
Smart card interface
N=
Simple IIC*1
N=
PCLKA × 106
32 ×
22n-1
×B
PCLKA × 106
16 ×
22n-1
×B
PCLKA × 106
12 × 22n-1 × B
PCLKA × 106
B × 32 × 22n-1 × (N + 1)
PCLKA × 106
B × 16 × 22n-1 × (N + 1)
PCLKA × 106
B × 12 × 22n-1 × (N + 1)
- 1} × 100
- 1} × 100
- 1} × 100
-
PCLKA × 106
-1
8 × 22n-1 × B
PCLKA × 106
-1
S × 22n+1 × B
PCLKA × 106
Error (%) = {
B × S × 22n+1 × (N + 1)
-1} × 100
-
PCLKA × 106
-1
64 × 22n-1 × B
B: Bit rate (bps)
N: BRR setting for on-chip baud rate generator (0 N 255)
PCLKA: Operating frequency (MHz)
n and S: Determined by the SMR/SMR_SMCI and SCMR register settings as listed in Table 32.7 and Table 32.8.
Note 1. Adjust the bit rate so that the high and low level widths of the SCL output in simple IIC mode satisfy the I2C bus
standard.
Table 32.6
Calculating widths at high and low levels for SCL
Mode
SCL
Formula (result in seconds)
IIC
Width at high level (minimum value)
Width at low level (minimum value)
Table 32.7
(N+1) × 4 × 2
2n-1
(N+1) × 4 × 2
2n-1
×7×
×8×
1
PCLKA × 10
6
1
PCLKA × 10
6
Clock source settings
SMR or SMR_SMCI.CKS[1:0] bit setting
CKS[1:0] bits
Clock source
00
PCLKA clock
0
01
PCLKA/4 clock
1
10
PCLKA/16 clock
2
11
PCLKA/64 clock
3
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
n
Page 915 of 1734
S5D5 User’s Manual
Table 32.8
32. Serial Communications Interface (SCI)
Base clock settings in smart card interface mode
SCMR.BCP2 bit setting
SMR_SMCI.BCP[1:0] bit setting
Base clock cycles for 1-bit period
S
0
00
93 clock cycles
93
0
01
128 clock cycles
128
0
10
186 clock cycles
186
0
11
512 clock cycles
512
1
00
32 clock cycles
32
1
01
64 clock cycles
64
1
10
372 clock cycles
372
1
11
256 clock cycles
256
Table 32.9 and Table 32.10 list examples of BRR (N) settings in asynchronous mode. Table 32.11 lists the maximum bit
rate selectable for each operating frequency. Table 32.15 lists examples of BRR (N) settings in smart card interface
mode.
In smart card interface mode, the number of base clock cycles S in a 1-bit data transfer time can be selected. For details,
see section 32.6.4, Receive Data Sampling Timing and Reception Margin. Table 32.12 and Table 32.14 list the maximum
bit rates with the external clock input.
When either the Asynchronous Mode Base Clock Select bit (ABCS) or the Baud Rate Generator Double-speed Mode
Select bit (BGDM) in the Serial Extended Mode Register (SEMR) is set to 1 in asynchronous mode, the bit rate becomes
twice the value listed in Table 32.16. When both of those registers are set to 1, the bit rate becomes four times the listed
value.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 916 of 1734
S5D5 User’s Manual
Table 32.9
32. Serial Communications Interface (SCI)
Examples of BRR settings for different bit rates in asynchronous mode (1)
Operating frequency PCLKA (MHz)
Bit rate
(bps)
8
9.8304
10
12
12.288
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
2
141
0.03
2
174
-0.26
2
177
-0.25
2
212
0.03
2
217
0.08
150
2
103
0.16
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
207
0.16
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
103
0.16
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
207
0.16
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
103
0.16
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
51
0.16
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
25
0.16
0
31
0.00
0
32
-1.36
0
38
0.16
0
39
0.00
19200
0
12
0.16
0
15
0.00
0
15
1.73
0
19
-2.34
0
19
0.00
31250
0
7
0.00
0
9
-1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
—
—
—
0
7
0.00
0
7
1.73
0
9
-2.34
0
9
0.00
Operating frequency PCLKA (MHz)
Bit rate
(bps)
14
16
17.2032
n
N
18
Error (%)
19.6608
n
N
Error (%)
n
N
Error (%)
110
2
248
-0.17
3
70
0.03
3
75
0.48
n
3
N
79
Error (%)
-0.12
n
3
N
86
Error (%)
0.31
150
2
181
0.16
2
207
0.16
2
223
0.00
2
233
0.16
2
255
0.00
300
2
90
0.16
2
103
0.16
2
111
0.00
2
116
0.16
2
127
0.00
600
1
181
0.16
1
207
0.16
1
223
0.00
1
233
0.16
1
255
0.00
1200
1
90
0.16
1
103
0.16
1
111
0.00
1
116
0.16
1
127
0.00
2400
0
181
0.16
0
207
0.16
0
223
0.00
0
233
0.16
0
255
0.00
4800
0
90
0.16
0
103
0.16
0
111
0.00
0
116
0.16
0
127
0.00
9600
0
45
-0.93
0
51
0.16
0
55
0.00
0
58
-0.69
0
63
0.00
19200
0
22
-0.93
0
25
0.16
0
27
0.00
0
28
1.02
0
31
0.00
31250
0
13
0.00
0
15
0.00
0
16
1.20
0
17
0.00
0
19
-1.70
38400
—
—
—
0
12
0.16
0
13
0.00
0
14
-2.34
0
15
0.00
Note:
In this example, SEMR.ABCS = 0, SEMR.ABCSE = 0, and SEMR.BGDM = 0.
When either the ABCS or BGDM bit is set to 1, the bit rate doubles.
When both ABCS and BGDM are set to 1, the bit rate quadruples.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 917 of 1734
S5D5 User’s Manual
Table 32.10
32. Serial Communications Interface (SCI)
Examples of BRR settings for different bit rates in asynchronous mode (2)
Operating frequency PCLKA (MHz)
20
Bit rate
(bps)
25
30
33
Error (%)
40
n
N
Error (%)
n
N
Error (%)
n
N
n
N
n
N
110
3
88
-0.25
3
110
-0.02
3
132 0.13
3
145 0.33
3
177 -0.25
150
3
64
0.16
3
80
0.47
3
97
3
106 0.39
3
129 0.16
-0.35
Error (%)
Error (%)
300
2
129 0.16
2
162 -0.15
2
194 0.16
2
214 -0.07
3
64
600
2
64
0.16
2
80
2
97
2
106 0.39
2
129 0.16
1200
1
129 0.16
1
162 -0.15
1
194 0.16
1
214 -0.07
2
64
0.47
0.47
-0.35
-0.35
0.16
0.16
2400
1
64
0.16
1
80
1
97
1
106 0.39
1
129 0.16
4800
0
129 0.16
0
162 -0.15
0
194 0.16
0
214 -0.07
1
64
9600
0
64
0.16
0
80
0.47
0
97
-0.35
0
106 0.39
0
129 0.16
19200
0
32
-1.36
0
40
-0.76
0
48
-0.35
0
53
-0.54
0
64
0.16
31250
0
19
0.00
0
24
0.00
0
29
0.00
0
32
0.00
0
39
0.00
38400
0
15
1.73
0
19
1.73
0
23
1.73
0
26
-0.54
0
32
-1.36
0.16
Operating frequency PCLKA (MHz)
50
Bit rate
(bps)
60
120
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
3
221
-0.02
—
—
—
—
—
—
150
3
162
-0.15
3
194
0.16
—
—
—
300
3
80
0.47
3
97
-0.35
3
194
0.16
600
2
162
-0.15
3
48
-0.35
3
97
-0.35
1200
2
80
0.47
2
97
-0.35
3
48
-0.35
2400
1
162
-0.15
2
48
-0.35
2
97
-0.35
4800
1
80
0.47
1
97
-0.35
2
48
-0.35
9600
0
162
-0.15
1
48
-0.35
1
97
-0.35
19200
0
80
0.47
0
97
-0.35
1
48
-0.35
31250
0
49
0.00
0
59
0.00
0
119
0
38400
0
40
-0.76
0
48
-0.35
0
97
-0.35
Note:
In this example, SEMR.ABCS = 0, SEMR.ABCSE = 0, and SEMR.BGDM = 0.
When either the ABCS or BGDM bit is set to 1, the bit rate doubles.
When both ABCS = 1 and BGDM = 1, the bit rate quadruples.
Table 32.11
Maximum bit rate for each operating frequency in asynchronous mode (1 of 2)
SEMR settings
n
Maximum
bit rate
N (bps)
PCLKA
(MHz)
BGDMbit
ABCS bit
Maximum
bit rate
ABCSE bit n N (bps)
0
0
0
250,000
16
0
0
0
0 0 500,000
0
0
0
500,000
1
0
0 0 1,000,000
0
0
0
0
0
0 0
PCLKA
(MHz)
BGDM bit ABCS bit
ABCSE bit
8
0
0
1
0
1
1
9.8304
SEMR settings
1
0
0
0
1,000,000
1
0
0 0 2,000,000
Don’t care Don’t care
1
0
0
1,333,333
Don’t care Don’t care 1
0 0 2,666,666
0
0
0
0
0
307,200
0
1
0
0
0
614,400
1
0
0
0
0
1
0
0
0
1
0
0
Don’t care Don’t care
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
17.2032
0
0
0 0 537,600
1
0
0 0 1,075,200
0
0
0 0
1,228,800
1
0
0 0 2,150,400
1,638,400
Don’t care Don’t care 1
0 0 2,867,200
1
Page 918 of 1734
S5D5 User’s Manual
Table 32.11
32. Serial Communications Interface (SCI)
Maximum bit rate for each operating frequency in asynchronous mode (2 of 2)
SEMR settings
n
Maximum
bit rate
N (bps)
PCLKA
(MHz)
SEMR settings
BGDMbit
ABCS bit
Maximum
bit rate
ABCSE bit n N (bps)
0
0
312,500
18
0
0
0
0 0 562,500
0
0
625,000
1
0
0 0 1,125,000
0
0
0
0
0 0
1
0
0 0 2,250,000
Don’t care Don’t care 1
0 0 3,000,000
0
PCLKA
(MHz)
BGDM bit ABCS bit
ABCSE bit
10
0
0
0
1
0
1
0
0
1
0
0
0
1,250,000
Don’t care Don’t care
1
0
0
1,666,666
0
0
0
0
0
375,000
1
0
0
0
750,000
0
0
0
0
1
0
0
0
1,500,000
Don’t care Don’t care
1
0
0
2,000,000
0
0
0
0
0
384,000
1
0
0
0
768,000
0
0
0
0
0
0
0 0
1
0
0
0
1,536,000
1
0
0 0 2,500,000
Don’t care Don’t care
1
0
0
2,048,000
Don’t care Don’t care 1
0 0 3,333,333
0
0
0
0
0
437,500
0
1
0
0
0
875,000
0
0
0
0
12
1
12.288
1
14
1
1
30
33
19.6608
1
20
0
0 0 614,400
1
0
0 0 1,228,800
0
0
0 0
1
0
0 0 2,457,600
Don’t care Don’t care 1
0 0 3,276,800
0
1
25
0
1
0
0
0 0 625,000
1
0
0 0 1,250,000
0
0
0 0 781,250
1
0
0 0 1,562,500
0
0
0 0
0
0
0
1,750,000
1
0
0 0 3,125,000
Don’t care Don’t care
1
0
0
2,333,333
Don’t care Don’t care 1
0 0 4,166,666
0
0
0
0
0
937,500
0
1
0
0
0
1,875,000
1
0
0
0
0
1
0
0
0
3,750,000
Don’t care Don’t care
1
0
0
5,000,000
0
0
0
0
0
1,031,250
1
0
0
0
2,062,500
0
0
0
0
0
0
0 0
1
0
0
0
4,125,000
1
0
0 0 7,500,000
Don’t care Don’t care
1
0
0
5,500,000
Don’t care Don’t care 1
0 0 10,000,000
0
0
0
0
0
1,250,000
0
1
0
0
0
2,500,000
0
0
0
0
0
0
0 0
1
0
0
0
5,000,000
1
0
0 0 15,000,000
1
0
0
6,666,666
Don’t care Don’t care 1
0 0 20,000,000
1
40
1
1
Don’t care Don’t care
Table 32.12
50
0
0
0 0 1,562,500
1
0
0 0 3,125,000
0
0
0 0
1
0
0 0 6,250,000
Don’t care Don’t care 1
0 0 8,333,333
0
1
60
1
120
1
0
0
0 0 1,875,000
1
0
0 0 3,750,000
0
0
0 0 3,750,000
1
0
0 0 7,500,000
Maximum bit rate with external clock input in asynchronous mode (1 of 2)
PCLKA
(MHz)
External input
clock (MHz)
8
Maximum bit rate (bps)
SEMR.ABCS bit = 0
SEMR.ABCS bit = 1
2.0000
125,000
250,000
9.8304
2.4576
153,600
307,200
10
2.5000
156,250
312,500
12
3.0000
187,500
375,000
12.288
3.0720
192,000
384,000
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 919 of 1734
S5D5 User’s Manual
Table 32.12
32. Serial Communications Interface (SCI)
Maximum bit rate with external clock input in asynchronous mode (2 of 2)
PCLKA
(MHz)
External input
clock (MHz)
14
16
17.2032
Maximum bit rate (bps)
SEMR.ABCS bit = 0
SEMR.ABCS bit = 1
3.5000
218,750
437,500
4.0000
250,000
500,000
4.3008
268,800
537,600
18
4.5000
281,250
562,500
19.6608
4.9152
307,200
614,400
20
5.0000
312,500
625,000
25
6.2500
390,625
781,250
30
7.5000
468,750
937,500
33
8.2500
515,625
1,031,250
40
10.0000
625,000
1,250,000
50
12.5000
781,250
1,562,500
60
15.0000
937,500
1,875,000
120
30.0000
1,875,000
3,750,000
Table 32.13
BRR settings for different bit rates in clock synchronous and simple SPI modes
Operating frequency PCLKA (MHz)
Bit
rate
(bps)
8
10
16
20
n
N
n
N
n
N
250
3
124
—
—
3
249
500
2
249
—
—
3
1k
2
124
—
—
2
2.5 k
1
199
1
249
5k
1
99
1
124
10 k
0
199
0
249
25 k
0
79
0
99
50 k
0
39
0
100 k
0
19
250 k
0
7
500 k
0
3
1M
0
1
25
n
N
124
—
—
249
—
2
99
1
199
1
0
49
0
0
24
0
9
0
4
30
33
n
N
n
N
3
233
—
3
97
3
2
124
2
155
1
249
2
77
99
1
124
1
159
0
199
0
79
0
99
0
39
0
0
15
0
0
7
0
3
40
50
60
120
n
N
n
N
n
N
n
N
n
N
116
3
128
3
155
3
194
3
233
2
187
2
205
2
249
3
77
3
2
93
2
102
2
124
2
155
3
93
3
186
46
3
93
155
1
187
1
205
1
249
2
77
249
1
74
1
82
1
99
1
124
2
93
3
46
1
149
2
0
124
0
149
0
164
1
49
1
74
61
1
74
1
149
49
0
62
0
74
0
82
0
99
19
0
24
0
29
0
32
0
39
0
124
0
149
1
74
0
49
0
59
1
29
0
9
—
—
0
14
—
—
0
0
4
—
—
—
—
—
—
0
19
0
24
0
29
1
14
9
—
—
0
14
0
0
1
—
—
0
2
—
—
29
0
3
0
4
0
5
0
0
0*1
11
—
—
—
—
—
—
0
0*1
0
1
—
—
110
2.5 M
0
0*1
5M
7.5 M
10 M
0
0*1
0
2
0
5
0
1
0
3
0
2
Space: Setting prohibited.
—: Can be set, but an error occurs.
Note 1.
Continuous transmission or reception is not possible. After transmitting or receiving one frame of data, a 1-bit period elapses
before starting to transmit or receive the next frame of data. The output of the synchronization clock is stopped for a 1-bit
period. Therefore, it takes 9 bits worth of time to transfer one frame (8 bits) of data, and the average transfer rate is 8/9 times
the bit rate. When the FIFO is selected, this setting (BRR = 00h and SMR.CKS[1:0] = 00b) is not available.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 920 of 1734
S5D5 User’s Manual
Table 32.14
PCLKA
(MHz)
32. Serial Communications Interface (SCI)
Maximum bit rate with external clock input in clock synchronous and simple SPI modes
External input clock
(MHz)
Maximum bit rate
(Mbps)
8
1.3333
1.3333333
10
1.6667
1.6666667
12
2.0000
2.0000000
14
2.3333
2.3333333
16
2.6667
2.6666667
18
3.0000
3.0000000
20
3.3333
3.3333333
25
4.1667
4.1666667
30
5.0000
5.0000000
33
5.5000
5.5000000
40
6.6667
6.6666667
50
8.3333
8.3333333
60
10.0000
10.0000000
120
20.0000 (clock synchronous mode)
20.00000000
10.0000 (simple SPI mode)
10.00000000
Table 32.15
BRR settings for different bit rates in smart card interface mode, n = 0, S = 372
Operating frequency PCLKA (MHz)
7.1424
10.00
10.7136
13.00
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9600
0
0
0.00
0
1
-30
0
1
-25
0
1
-8.99
Operating frequency PCLKA (MHz)
14.2848
16.00
18.00
20.00
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9600
0
1
0.00
0
1
12.01
0
2
-15.99
0
2
-6.66
Operating frequency PCLKA (MHz)
25.00
30.00
33.00
40.00
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9600
0
3
-12.49
0
3
5.01
0
4
-7.59
0
5
-6.66
Operating frequency PCLKA (MHz)
50.00
60.00
120.00
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9600
0
6
0.01
0
7
5.01
0
16
-1.17
Table 32.16
Maximum bit rate for each operating frequency in smart card interface mode (S = 32) (1 of 2)
PCLKA
(MHz)
Maximum bit rate
(bps)
n
N
10.00
156,250
0
0
10.7136
167,400
0
0
13.00
203,125
0
0
16.00
250,000
0
0
18.00
281,250
0
0
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Aug 30, 2019
Page 921 of 1734
S5D5 User’s Manual
Table 32.16
32. Serial Communications Interface (SCI)
Maximum bit rate for each operating frequency in smart card interface mode (S = 32) (2 of 2)
PCLKA
(MHz)
Maximum bit rate
(bps)
n
N
20.00
312,500
0
0
25.00
390,625
0
0
30.00
468,750
0
0
33.00
515,625
0
0
40.00
625,000
0
0
50.00
781,250
0
0
60.00
937,500
0
0
120.00
1,875,000
0
0
Table 32.17
BRR settings for different bit rates in simple IIC mode
Operating frequency PCLKA (MHz)
Bit rate
(bps)
8
10
16
20
25
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
10 k
0
24
0.0
0
30
0.8
1
12
-3.8
1
15
-2.3
1
19
-2.3
25 k
0
9
0.0
0
12
-3.8
1
4
0.0
1
5
4.2
1
7
-2.3
0
4
0.0
0
5
4.2
1
2
-16.7
1
2
4.2
1
3
-2.3
50 k
100
k*1
0
2
-16.7
0
3
-21.9
0
4
0.0
0
6
-10.7
1
1
-2.3
0
0
0.0
0
0
25
0
1
0.0
0
2
-16.7
0
2
4.2
350 k
0
1
-10.7
0
1
11.6*2
400 k*1
0
1
-21.9
0
1
-2.3*2
250 k
Operating frequency PCLKA (MHz)
Bit rate
(bps)
30
33
40
50
n
N
Error (%)
n
N
Error (%)
n
N
10 k
1
22
1.9
1
25
-0.8
0
25 k
1
8
4.2
1
9
3.1
50 k
1
4
-6.3
1
4
3.1
1
2
-21.9
1
2
-14.1
100
k*1
Error (%)
60
n
N
Error (%)
n
N
Error (%)
124 0.0
2
9
-2.3
1
46
-0.3
0
49
0.0
2
3
-2.3
0
74
0.0
0
24
0.0
2
1
-2.3
0
37
-1.3
0
12
-3.9
1
3
-2.3
0
18
-1.3
250 k
0
3
-6.3
0
3
3.1
0
4
0.0
0
5
4.2
0
7
-6.3
350 k
0
2
-10.7
0
2
-1.8
0
3
-10.7
0
4
-10.7
0
4
7.1
3
-2.3*2
0
4
-6.3
400
k*1
0
1
17.2
0
2
-14.1
0
3
-21.9
0
Operating frequency
PCLKA (MHz)
Bit rate
(bps)
120
n
N
Error (%)
10 k
1
93
-0.3
25 k
0
149 0.0
50 k
0
74
0.0
0
37
-1.3
250 k
0
14
0.0
350 k
0
10
-2.6
0
9
-6.3
100
400
k*1
k*1
Note 1.
Note 2.
The bit rate of 100 kbps and 400 kbps indicates the set value at which the error is on the minus side.
The minimum value of low width is smaller than 1.3 s which is the standard value of the fast mode.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 922 of 1734
S5D5 User’s Manual
Table 32.18
32. Serial Communications Interface (SCI)
Minimum widths at SCL high and low levels at multiple bit rates in simple IIC mode
Operating frequency PCLKA (MHz)
8
10
N
Min. widths at
SCL high/low
levels (μs)
n
24
43.75/50.00
0
0
9
17.50/20.00
50 k
0
4
100 k
0
2
250 k
0
0
16
N
Min. widths at
SCL high/low
levels (μs)
n
30
43.40/49.60
1
0
12
18.2/20.80
8.75/10.00
0
5
5.25/6.00
0
3
1.75/2.00
0
0
20
N
Min. widths at
SCL high/low
levels (μs)
n
N
Min. widths at
SCL high/low
levels (μs)
12
45.5/52.00
1
15
44.80/51.20
1
4
17.50/20.00
1
5
16.80/19.20
8.40/9.60
1
2
10.50/12.00
1
2
8.40/9.60
5.60/6.40
0
4
4.38/5.00
0
6
4.90/5.60
1.40/1.60
0
1
1.75/2.00
0
2
2.10/2.40
350 k
0
1
1.40/1.60
400 k
0
1
1.40/1.60
Min. widths at
SCL high/low
levels (μs)
Bit rate
(bps)
n
10 k
0
25 k
Operating frequency PCLKA (MHz)
25
30
N
Min. widths at
SCL high/low
levels (μs)
n
1
19
44.80/51.20
1
7
17.92/20.48
50 k
1
3
100 k
1
250 k
0
Bit rate
(bps)
n
10 k
25 k
350 k
400 k
0
0
33
N
Min. widths at
SCL high/low
levels (μs)
n
1
22
42.93/49.60
1
8
16.80/19.20
8.96/10.24
1
4
1
4.48/5.12
1
2
1.68/1.92
0
1
1.12/1.28*1
1
1.12/1.28*1
40
N
Min. widths at
SCL high/low
levels (μs)
n
N
1
25
44.12/50.42
0
124 43.75/50.00
1
9
16.97/19.39
0
49
17.50/20.00
9.33/10.66
1
4
8.48/9.70
0
24
8.75/10.00
2
5.60/6.40
1
2
5.09/5.82
0
12
4.55/5.20
3
1.86/2.13
0
3
1.70/1.94
0
4
1.75/2.00
0
2
1.40/1.60
0
2
1.27/1.45
0
3
1.40/1.60
0
2
1.40/1.60
0
2
1.27 /1.45
0
3
1.40/1.60
Operating frequency PCLKA (MHz)
50
60
120
Bit rate
(bps)
n
N
Min. widths at
SCL high/low
levels (μs)
10 k
2
9
44.80/51.20
1
46
43.87/50.13
1
93
25 k
2
3
17.92/20.48
0
74
17.50/20.00
0
149 17.50/20.00
50 k
2
1
8.96/10.24
0
37
8.87/10.13
0
74
8.75/10.00
100 k
1
3
4.48/5.12
0
18
4.43/5.07
0
37
4.43/5.07
250 k
0
5
1.68/1.92
0
7
1.87/2.13
0
14
1.75/2.00
350 k
0
4
1.40/1.60
0
4
1.17/1.33
0
10
1.28/1.47
400 k
0
3
1.12/1.28
0
4
1.17/1.33
0
8
1.05/1.20
Note 1.
n
N
Min. widths at
SCL high/low
levels (μs)
n
N
Min. widths at
SCL high/low
levels (μs)
43.87/50.13
The minimum value of low width is smaller than 1.3 s which is the standard value of the fast mode. The setting values are the
same as in Table 32.17.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 923 of 1734
S5D5 User’s Manual
32.2.18
32. Serial Communications Interface (SCI)
Modulation Duty Register (MDDR)
Address(es): SCI0.MDDR 4007 0012h, SCI1.MDDR 4007 0032h, SCI2.MDDR 4007 0052h, SCI3.MDDR 4007 0072h,
SCI4.MDDR 4007 0092h, SCI5.MDDR 4007 00B2h, SCI6.MDDR 4007 00D2h, SCI7.MDDR 4007 00F2h,
SCI8.MDDR 4007 0112h, SCI9.MDDR 4007 0132h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
The MDDR register corrects the bit rate adjusted by the BRR register.
When the SEMR.BRME bit is set to 1, the bit rate generated by the on-chip baud rate generator is evenly corrected using
the settings in the MDDR register (M/256). Table 32.19 shows the relationship between the MDDR setting (M) and the
bit rate (B).
The initial value of the MDDR register is FFh. Bit [7] in this register is fixed to 1. The CPU can read the MDDR register,
but the MDDR register is only writable when the TE and RE bits in SCR/SCR_SMCI are 0.
Table 32.19
Relationship between MDDR setting (M) and bit rate (B) when bit rate modulation function is used
SEMR settings
Mode
BGDM
bit
ABCS
bit
ABCSE
bit
0
0
0
Asynchronous,
multi-processor
transfer
BRR setting
N=
1
0
1
0
1
1
0
N=
N=
Don’t
care
Clock synchronous,
simple SPI*1
64 ×
22n-1
× (256/M) × B
-1
Error (%)
={
-1
Error (%)
={
-1
Error (%)
={
-1
Error (%)
={
PCLKA × 106
B × 64 × 22n-1 × (256/M) × (N + 1)
- 1} × 100
0
0
Don’t
care
PCLKA × 106
Error
PCLKA × 106
32 ×
N=
16 × 22n-1 × (256/M) × B
PCLKA × 106
12 ×
Simple IIC*2
N=
22n-1
× (256/M) × B
PCLKA × 106
8 × 22n-1 × (256/M) × B
Smart card interface
N=
× (256/M) × B
PCLKA × 106
1
N=
22n-1
PCLKA × 106
S×
22n+1
× (256/M) × B
PCLKA × 106
64 × 22n-1 × (256/M) × B
PCLKA × 106
B × 32 × 22n-1 × (256/M) × (N + 1)
PCLKA × 106
B × 16 × 22n-1 × (256/M) × (N + 1)
PCLKA × 106
B × 12 × 22n-1 × (256/M) × (N + 1)
- 1} × 100
- 1} × 100
- 1} × 100
—
-1
-1
Error (%)
={
PCLKA × 106
B×S×
22n+1
× (256/M) × (N + 1)
-1} × 100
—
-1
B: Bit rate (bps)
M: MDDR setting (128 ≤ MDDR ≤ 255)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
PCLKA: Operating frequency (MHz)
n and S: Determined by the SMR/SMR_SMCI and SCMR register settings as listed in Table 32.7 and Table 32.8 in section 32, Bit
Rate Register (BRR).
Note 1.
Note 2.
Do not use this function in clock synchronous mode or in the highest speed settings in simple SPI mode (SMR.CKS[1:0] = 00b,
SCR.CKE[1] = 0, and BRR = 0).
Adjust the bit rate so that the high and low level widths of the SCL output in simple IIC mode satisfy the I2C standard.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 924 of 1734
S5D5 User’s Manual
32. Serial Communications Interface (SCI)
Table 32.20 and Table 32.21 list examples of N settings in BRR and M settings in MDDR in asynchronous mode.
Table 32.20
Examples of BRR and MDDR settings for different bit rates in asynchronous mode (1)
Operating frequency PCLKA (MHz)
8
9.8304
16
Bit rate
(bps)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
38,400
0
5
236
0
0.03
0
7
(256)*1
0
0.00
0
10
173
1
-0.01
57,600
0
3
236
0
0.03
0
4
240
0
0.00
0
4
236
0
0.03
115,200
0
1
236
0
0.03
0
1
192
0
0.00
0
4
236
1
0.03
230,400
0
0
236
0
0.03
0
0
192
0
0.00
0
1
189
1
0.14
460,800
0
0
236
1
0.03
0
0
192
1
0.00
0
0
189
1
0.14
Error
(%)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
Operating frequency PCLKA (MHz)
12
12.288
Bit rate
(bps)
n
N
38,400
0
57,600
14
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
8
236
0
0.03
0
9
(256)*1
0
0.00
0
16
191
1
0.00
0
5
236
0
0.03
0
4
192
0
0.00
0
13
236
1
0.03
115,200
0
2
236
0
0.03
0
4
192
1
0.00
0
6
236
1
0.03
230,400
0
2
236
1
0.03
0
2
230
1
-0.17
0
2
202
1
-0.11
460,800
0
0
157
1
-0.18
0
0
154
1
-0.26
0
0
135
1
0.14
Operating frequency PCLKA (MHz)
16
17.2032
18
Bit rate
(bps)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
38,400
0
11
236
0
0.03
0
13
(256)*1
0
0.00
0
18
166
1
-0.01
57,600
0
7
236
0
0.03
0
6
192
0
0.00
0
18
249
1
-0.01
115,200
0
3
236
0
0.03
0
6
192
1
0.00
0
8
236
1
0.03
230,400
0
1
236
0
0.03
0
3
219
1
-0.20
0
1
210
0
0.14
460,800
0
1
236
1
0.03
0
1
219
1
-0.20
0
0
210
0
0.14
Note 1.
In this example, the ABCS and ABCSE bits in the SEMR register are 0. SEMR.BRME = 0 (M = 256) disables the bit rate
modulation function.
Table 32.21
Examples of BRR and MDDR settings for different bit rates in asynchronous mode (2)
Operating frequency PCLKA (MHz)
19.6608
20
25
Bit rate
(bps)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
38,400
0
15
(256)*2
0
0.00
0
10
173
0
-0.01
0
11
151
0
0.00
57,600
0
9
240
0
0.00
0
9
236
0
0.03
0
7
151
0
0.00
115,200
0
4
240
0
0.00
0
4
236
0
0.03
0
3
151
0
0.00
230,400
0
1
192
0
0.00
0
4
236
1
0.03
0
1
151
0
0.00
460,800
0
0
192
0
0.00
0
0
189
0
0.14
0
0
151
0
0.00
Error
(%)
n
N
M
BGDM
bit
Error
(%)
Operating frequency PCLKA (MHz)
30
33
Bit rate
(bps)
n
N
38,400
0
57,600
115,200
40
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
36
194
1
0.01
0
14
143
0
0.01
0
21
173
0
-0.01
0
10
173
0
-0.01
0
9
143
0
0.01
0
38
230
1
-0.01
0
10
173
1
-0.01
0
4
143
0
0.01
0
9
236
0
0.03
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 925 of 1734
S5D5 User’s Manual
32. Serial Communications Interface (SCI)
Operating frequency PCLKA (MHz)
30
33
Bit rate
(bps)
n
N
230,400
0
460,800
0
40
M
BGDM
bit
Error
(%)
6
220
1
-0.09
0
4
143
1
0.01
0
4
236
0
0.03
3
252
1
0.14
0
1
229
0
0.10
0
4
236
1
0.03
n
N
BGDM
bit
M
Error
(%)
n
N
M
BGDM
bit
Error
(%)
Operating frequency PCLKA (MHz)
50
60
120
Bit rate
(bps)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
38,400
0
23
151
0
0.00
0
36
194
0
0.01
0
73
194
0
0.01
57,600
0
15
151
0
0.00
0
21
173
0
-0.01
0
58
232
0
0.00
115,200
0
7
151
0
0.00
0
10
173
0
-0.01
0
21
173
0
-0.01
230,400
0
3
151
0
0.00
0
10
173
1
-0.01
0
10
173
0
-0.01
0
1
151
0
0.00
0
6
220
1
-0.09
0
10
173
1
-0.09
460,800
Note 2.
In this example, the ABCS and ABCSE bits in the SEMR register are 0.
SEMR.BRME = 0 (M = 256) disables the bit rate modulation function.
32.2.19
Serial Extended Mode Register (SEMR)
Address(es): SCI0.SEMR 4007 0007h, SCI1.SEMR 4007 0027h, SCI2.SEMR 4007 0047h, SCI3.SEMR 4007 0067h,
SCI4.SEMR 4007 0087h, SCI5.SEMR 4007 00A7h, SCI6.SEMR 4007 00C7h, SCI7.SEMR 4007 00E7h,
SCI8.SEMR 4007 0107h, SCI9.SEMR 4007 0127h
b7
b6
b5
RXDES BGDM NFEN
EL
Value after reset:
Bit
0
Symbol
0
0
b4
b3
b2
ABCS ABCSE BRME
0
0
0
b1
b0
—
—
0
0
Bit name
Description
R/W
b0, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
BRME
Bit Rate Modulation
Enable
0: Disable bit rate modulation function
1: Enable bit rate modulation function.
R/W*1
b3
ABCSE
Asynchronous Mode
Extended Base Clock
Select 1
Valid only in asynchronous mode with SCR.CKE[1] = 0:
0: Clock cycles for 1-bit period determined by combination of the BGDM and
ABCS bits in the SEMR register
1: Baud rate is 6 base clock cycles for 1-bit period.
R/W*1
b4
ABCS
Asynchronous Mode
Base Clock Select
Valid only in asynchronous mode:
0: Selects 16 base clock cycles for 1-bit period
1: Selects 8 base clock cycles for 1-bit period.
R/W*1
b5
NFEN
Digital Noise Filter
Function Enable
In asynchronous mode:
0: Disable noise cancellation function for RXDn input signal
1: Enable noise cancellation function for RXDn input signal.
In simple IIC mode:
0: Disable noise cancellation function for SCLn and SDAn input signals
1: Enable noise cancellation function for SCLn and SDAn input signals.
The NFEN bit must be 0 in all other modes.
R/W*1
b6
BGDM
Baud Rate Generator
Double-Speed Mode
Select
Valid only in asynchronous mode with SCR.CKE[1] = 0:
0: Output the clock with single frequency
1: Output the clock with double frequency.
R/W*1
b7
RXDESEL
Asynchronous Start Bit
Edge Detection Select
Valid only in asynchronous mode:
0: Detect low level on RXDn pin as start bit
1: Detect falling edge of RXDn pin as start bit.
R/W*1
Note 1.
Writable only when the TE and RE bits in SCR/SCR_SMCI are 0 (both serial transmission and reception are disabled).
The SEMR register selects the clock source for the 1-bit period in asynchronous mode.
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Aug 30, 2019
Page 926 of 1734
S5D5 User’s Manual
32. Serial Communications Interface (SCI)
BRME bit (Bit Rate Modulation Enable)
The BRME bit enables or disables the bit rate modulation function. The bit rate generated by the on-chip baud rate
generator is evenly corrected when this function is enabled.
ABCSE bit (Asynchronous Mode Extended Base Clock Select 1)
The ABCSE bit sets the pulse number for the base clock in a 1-bit period to 6, and the double-frequency clock is output
from the baud rate generator. When the bit rate is set to 6 while dividing the bus clock frequency, use the ABCSE bit to
set SMR.CKS[1:0] = 00b and BRR = 0. Set this bit to 0 except in asynchronous mode.
ABCS bit (Asynchronous Mode Base Clock Select)
The ABCS bit selects the number of clock cycles for a 1-bit period. Set this bit to 0 except in asynchronous mode.
NFEN bit (Digital Noise Filter Function Enable)
The NFEN bit enables or disables the digital noise filter function.
When the digital noise filter function is enabled:
Noise cancellation is applied to the RXDn input signal in asynchronous mode
Noise cancellation is applied to the SDAn and SCLn input signals in simple IIC mode.
In all other modes, set the NFEN bit to 0 to disable the digital noise filter function. When the function is disabled, input
signals are transferred as received.
BGDM bit (Baud Rate Generator Double-Speed Mode Select)
The BGDM bit selects whether or not to double the base clock frequency output from the baud rate generator.
The BGDM bit is valid when the on-chip baud rate generator is selected as the clock source (SCR.CKE[1] = 0) in
asynchronous mode (SMR.CM = 0). The base clock is generated by the clock output from the baud rate generator. When
the BGDM bit is set to 1, the base clock cycle is halved and the bit rate is doubled.
Set this bit to 0 in modes other than asynchronous mode.
RXDESEL bit (Asynchronous Start Bit Edge Detection Select)
The RXDSEL bit selects the detection method of the start bit for reception in asynchronous mode. When a break occurs,
data reception operation depends on the setting of this bit. Set this bit to 1 when reception must be stopped while a break
occurs or when reception must be started without keeping the RXDn pin input at a high level for the period of one data
frame or longer after the completion of the break.
Set this bit to 0 in modes other than asynchronous mode.
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32.2.20
32. Serial Communications Interface (SCI)
Noise Filter Setting Register (SNFR)
Address(es): SCI0.SNFR 4007 0008h, SCI1.SNFR 4007 0028h, SCI2.SNFR 4007 0048h, SCI3.SNFR 4007 0068h,
SCI4.SNFR 4007 0088h, SCI5.SNFR 4007 00A8h, SCI6.SNFR 4007 00C8h, SCI7.SNFR 4007 00E8h,
SCI8.SNFR 4007 0108h, SCI9.SNFR 4007 0128h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
NFCS[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
NFCS[2:0]
Noise Filter Clock Select
In asynchronous mode, selects the standard setting for the base
clock as follows:
R/W*1
b2
b0
0 0 0: Use clock signal divided by 1 with noise filter.
In simple IIC mode, selects the standard settings for the clock source
of the on-chip baud rate generator selected in the SMR.CKS[1:0] bits:
b2
b0
0 0 1: Use clock signal divided by 1 with noise filter
0 1 0: Use clock signal divided by 2 with noise filter
0 1 1: Use clock signal divided by 4 with noise filter
1 0 0: Use clock signal divided by 8 with noise filter.
Other settings are prohibited.
b7 to b3
Note 1.
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Writing to these bits is only possible when the RE and TE bits in SCR/SCR_SMCI are 0 (serial reception and transmission
disabled).
The SNFR register sets the digital noise filter clock.
NFCS[2:0] bits (Noise Filter Clock Select)
The NFCS[2:0] bits select the sampling clock for the digital noise filter. To use the noise filter in asynchronous mode, set
these bits to 000b. In simple IIC mode, set the bits to a value in the range from 001b to 100b.
32.2.21
IIC Mode Register 1 (SIMR1)
Address(es): SCI0.SIMR1 4007 0009h, SCI1.SIMR1 4007 0029h, SCI2.SIMR1 4007 0049h, SCI3.SIMR1 4007 0069h,
SCI4.SIMR1 4007 0089h, SCI5.SIMR1 4007 00A9h, SCI6.SIMR1 4007 00C9h, SCI7.SIMR1 4007 00E9h,
SCI8.SIMR1 4007 0109h, SCI9.SIMR1 4007 0129h
b7
b6
b5
b4
b3
IICDL[4:0]
Value after reset:
0
0
0
0
0
b2
b1
b0
—
—
IICM
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICM
Simple IIC Mode Select
SMIF IICM
R/W*1
0
0
1
1
b2, b1
—
Reserved
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0: Asynchronous mode including multi-processor mode, clock
synchronous mode, or simple SPI mode
1: Simple IIC mode
0: Smart card interface mode
1: Setting prohibited.
These bits are read as 0. The write value should be 0.
R/W
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32. Serial Communications Interface (SCI)
Bit
Symbol
Bit name
Description
R/W
b7 to b3
IICDL[4:0]
SDA Delay Output Select
SDA signal output delay in cycles of the clock signal from the on-chip
baud rate generator:
R/W*1
b7
b3
0 0 0 0 0: No output delay
0 0 0 0 1: 0 to 1 cycle
0 0 0 1 0: 1 to 2 cycles
0 0 0 1 1: 2 to 3 cycles
0 0 1 0 0: 3 to 4 cycles
0 0 1 0 1: 4 to 5 cycles
:
1 1 1 1 0: 29 to 30 cycles
1 1 1 1 1: 30 to 31 cycles.
Note 1.
Writing to these bits is only possible when the RE and TE bits in the SCR register are 0 (both serial transmission and reception
are disabled).
SIMR1 selects simple IIC mode and the number of delay stages for the SDAn output.
IICM bit (Simple IIC Mode Select)
In combination with the SCMR.SMIF bit, the IICM bit selects the operating mode.
IICDL[4:0] bits (SDA Delay Output Select)
The IICDL[4:0] bits specify an output delay on the SDAn pin relative to the falling edge of the output on the SCLn pin.
The available delay settings range from no delay to 31 cycles, with the clock signal from the on-chip baud rate generator
as the base. The signal obtained by frequency-dividing PCLKA by the divisor set in SMR.CKS[1:0] is supplied as the
clock signal from the on-chip baud rate generator. Set these bits to 00000b unless the operation is in simple IIC mode. In
simple IIC mode, set the bits to a value in the range from 00001b to 11111b.
32.2.22
IIC Mode Register 2 (SIMR2)
Address(es): SCI0.SIMR2 4007 000Ah, SCI1.SIMR2 4007 002Ah, SCI2.SIMR2 4007 004Ah, SCI3.SIMR2 4007 006Ah,
SCI4.SIMR2 4007 008Ah, SCI5.SIMR2 4007 00AAh, SCI6.SIMR2 4007 00CAh, SCI7.SIMR2 4007 00EAh,
SCI8.SIMR2 4007 010Ah, SCI9.SIMR2 4007 012Ah
b7
Value after reset:
b6
b5
—
—
IICACK
T
b4
b3
b2
—
—
—
0
0
0
0
0
0
b1
b0
IICCSC IICINT
M
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICINTM
IIC Interrupt Mode Select
0: Use ACK/NACK interrupts
1: Use reception and transmission interrupts.
R/W*1
b1
IICCSC
Clock Synchronization
0: Do not synchronize with clock signal
1: Synchronize with clock signal.
R/W*1
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
IICACKT
ACK Transmission Data
0: ACK transmission
1: NACK transmission and ACK/NACK reception.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Writing to these bits is only possible when the RE and TE bits in the SCR register are 0 (serial reception and transmission
disabled).
SIMR2 selects how reception and transmission are controlled in simple IIC mode.
IICINTM bit (IIC Interrupt Mode Select)
The IICINTM bit selects the sources of interrupt requests in simple IIC mode.
IICCSC bit (Clock Synchronization)
Set the IICCSC bit to 1 to synchronize the internally generated SCL clock signal when the SCLn pin is driven low
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32. Serial Communications Interface (SCI)
because of a wait inserted by another device, for example.
The SCL clock signal is not synchronized if this bit is 0. The SCL clock signal is generated according to the rate selected
in the BRR register regardless of the level being input on the SCLn pin.
Set this bit to 1 except during debugging.
IICACKT bit (ACK Transmission Data)
Transmitted data contains ACK bits. Set the IICACKT bit to 1 when ACK and NACK bits are received.
32.2.23
IIC Mode Register 3 (SIMR3)
Address(es): SCI0.SIMR3 4007 000Bh, SCI1.SIMR3 4007 002Bh, SCI2.SIMR3 4007 004Bh, SCI3.SIMR3 4007 006Bh,
SCI4.SIMR3 4007 008Bh, SCI5.SIMR3 4007 00ABh, SCI6.SIMR3 4007 00CBh, SCI7.SIMR3 4007 00EBh,
SCI8.SIMR3 4007 010Bh, SCI9.SIMR3 4007 012Bh
b7
b6
IICSCLS[1:0]
Value after reset:
0
b5
b4
IICSDAS[1:0]
0
0
b3
b2
b1
b0
IICSTIF IICSTP IICRST IICSTA
REQ AREQ REQ
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICSTAREQ
Start Condition Generation
0: Do not generate start condition
1: Generate start condition.*1, *3, *5, *6
R/W
b1
IICRSTAREQ
Restart Condition
Generation
0: Do not generate restart condition
1: Generate restart condition.*2, *3, *5, *6
R/W
b2
IICSTPREQ
Stop Condition Generation
0: Do not generate stop condition
1: Generate stop condition.*2, *3, *5, *6
R/W
b3
IICSTIF
Issuing of Start, Restart, or
Stop Condition Completed
Flag
0: No requests are being made for generating conditions, or a
condition is being generated
1: Generation of start, restart, or stop condition is complete.
When 0 is written to IICSTIF, it is set to 0.*4
R/W*4
b5, b4
IICSDAS[1:0]
SDA Output Select
b5 b4
R/W
b7, b6
IICSCLS[1:0]
SCL Output Select
b7 b6
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
0
0
1
1
0
0
1
1
0: Output serial data
1: Generate start, restart, or stop condition
0: Output low on SDAn pin
1: Drive SDAn pin to high-impedance state.
0: Output serial clock
1: Generate start, restart, or stop condition
0: Output low on SCLn pin
1: Drive SCLn pin to high-impedance state.
Only generate a start condition after checking the bus state and confirming that the bus is free.
Generate a restart or stop condition after checking the bus state and confirming that the bus is busy.
Do not set more than one of the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits to 1 at a given time.
Write only 0. When 1 is written, the value is ignored.
Execute the generation of a condition after the value of the IICSTIF flag is 0.
Do not write 0 to this bit while it is 1. Generation of a condition is suspended by writing 0 to this bit while it is 1.
IICSTAREQ bit (Start Condition Generation)
When a start condition is to be generated, set both IICSDAS[1:0] and IICSCLS[1:0] to 01b in addition to setting the
IICSTAREQ bit to 1.
[Setting condition]
On writing 1 to the bit.
[Clearing condition]
On completion of start condition generation.
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32. Serial Communications Interface (SCI)
IICRSTAREQ bit (Restart Condition Generation)
When a restart condition is to be generated, set both IICSDAS[1:0] and IICSCLS[1:0] to 01b in addition to setting the
IICRSTAREQ bit to 1.
[Setting condition]
On writing 1 to the bit.
[Clearing condition]
On completion of restart condition generation.
IICSTPREQ bit (Stop Condition Generation)
When a stop condition is to be generated, set both IICSDAS[1:0] and IICSCLS[1:0] to 01b in addition to setting the
IICSTPREQ bit to 1.
[Setting condition]
On writing 1 to the bit.
[Clearing condition]
On completion of stop condition generation.
IICSTIF flag (Issuing of Start, Restart, or Stop Condition Completed Flag)
After generating a condition, the IICSTIF flag indicates that the condition generation is complete. When using the
IICSTAREQ, IICRSTAREQ, or IICSTPREQ bit to cause generation of a condition, do so after setting the IICSTIF flag
to 0.
When the IICSTIF flag is 1 when an interrupt request is enabled by setting the SCR.TEIE bit, an STI request is output.
[Setting condition]
On completion of a start, restart, or stop condition generation.
If the setting condition conflicts with any of the clearing conditions for the flag, the clearing condition takes
precedence.
[Clearing conditions]
On writing 0 to the bit. After writing 0 to the IICSTIF bit, read the bit to check that it is actually set to 0.
On writing 0 to the SIMR1.IICM bit when operation is not in simple IIC mode
On writing 0 to the SCR.TE bit.
IICSDAS[1:0] bits (SDA Output Select)
The IICSDAS[1:0] bits control output from the SDAn pin. Set IICSDAS[1:0] and IICSCLS[1:0] to the same value.
IICSCLS[1:0] bits (SCL Output Select)
The IICSCLS[1:0] bits control output from the SCLn pin. Set IICSCLS[1:0] and IICSDAS[1:0] to the same value.
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32.2.24
32. Serial Communications Interface (SCI)
IIC Status Register (SISR)
Address(es): SCI0.SISR 4007 000Ch, SCI1.SISR 4007 002Ch, SCI2.SISR 4007 004Ch, SCI3.SISR 4007 006Ch,
SCI4.SISR 4007 008Ch, SCI5.SISR 4007 00ACh, SCI6.SISR 4007 00CCh, SCI7.SISR 4007 00ECh,
SCI8.SISR 4007 010Ch, SCI9.SISR 4007 012Ch
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
IICACK
R
0
0
x
x
0
x
0
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
IICACKR
ACK Reception Data Flag
0: ACK received
1: NACK received.
R
b1
—
Reserved
This bit is read as 0
R
b2
—
Reserved
The read value is undefined
R
b3
—
Reserved
This bit is read as 0
R
b5, b4
—
Reserved
The read value is undefined
R
b7, b6
—
Reserved
These bits are read as 0
R
SISR monitors the state in simple IIC mode.
IICACKR flag (ACK Reception Data Flag)
Received ACK and NACK bits can be read from the IICACKR flag. The IICACKR flag is updated on the rising edge of
the SCLn clock for the received ACK/NACK bit.
32.2.25
SPI Mode Register (SPMR)
Address(es): SCI0.SPMR 4007 000Dh, SCI1.SPMR 4007 002Dh, SCI2.SPMR 4007 004Dh, SCI3.SCI3 4007 006Dh,
SCI4.SPMR 4007 008Dh, SCI5.SPMR 4007 00ADh, SCI6.SPMR 4007 00CDh, SCI7.SCI7 4007 00EDh,
SCI8.SPMR 4007 010Dh, SCI9.SPMR 4007 012Dh
b7
b6
CKPH CKPOL
Value after reset:
0
0
b5
b4
b3
b2
b1
b0
—
MFF
—
MSS
CTSE
SSE
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSE
SSn Pin Function Enable
0: Disable SSn pin function
1: Enable SSn pin function.
R/W*1
b1
CTSE
CTS Enable
0: Disable CTS function (enable RTS output function)
1: Enable CTS function.
R/W*1
b2
MSS
Master Slave Select
0: Transmit through TXDn pin and receive through RXDn pin (master
mode)
1: Receive through TXDn pin and transmit through RXDn pin (slave
mode).
R/W*1
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
MFF
Mode Fault Flag
0: No mode fault error
1: Mode fault error.
R/W*2
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
CKPOL
Clock Polarity Select
0: Do not invert clock polarity
1: Invert clock polarity.
R/W*1
b7
CKPH
Clock Phase Select
0: Do not delay clock
1: Delay clock.
R/W*1
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Note 1.
Note 2.
32. Serial Communications Interface (SCI)
Writing to these bits is only possible when the RE and TE bits in the SCR register are 0 (both serial transmission and reception
are disabled).
Only 0 can be written to this bit, to clear the flag.
The SPMR register selects settings for simple SPI mode.
SSE bit (SSn Pin Function Enable)
Set the SSE bit to 1 to use the SSn pin to control transmission and reception in simple SPI mode. Set this bit to 0 in all
other modes. In simple SPI mode, when master mode is selected (SCR.CKE[1:0] = 00b and SPMR.MSS = 0) and there is
a single master, the SSn pin on the master side is not required to control reception and transmission. In such a case, set
the SSE bit to 0. Do not set both the SSE and CTSE bits to 1 as the operation is the same as when these bits are set to 0.
CTSE bit (CTS Enable)
Set the CTSE bit to 1 if the SSn pin is to be used for inputting the CTS control signal to control transmission and
reception. The RTS signal is output when this bit is set to 0. Set this bit to 0 in smart card interface mode, simple SPI
mode, and simple IIC mode. Do not set both the CTSE and SSE bits to 1 as the operation is the same as when these bits
are set to 0.
MSS bit (Master Slave Select)
The MSS bit selects between master or slave operation in simple SPI mode. The functions of the TXDn and RXDn pins
are reversed when this bit is set to 1, so that data is received through the TXDn pin and transmitted through the RXDn
pin. Set this bit to 0 in modes other than simple SPI mode.
MFF flag (Mode Fault Flag)
The MFF flag indicates mode fault errors. In a multi-master configuration, determine the mode fault error occurrence by
reading this flag.
[Setting condition]
When input on the SSn pin is low during master operation in simple SPI mode (SSE bit = 1 and MSS bit = 0).
[Clearing condition]
On writing 0 to the bit after it is read as 1.
CKPOL bit (Clock Polarity Select)
The CKPOL bit selects the polarity of the clock signal output through the SCKn pin. See Figure 32.70 for details. Set the
CKPOL bit to 0 in all modes other than simple SPI mode and clock synchronous mode.
CKPH bit (Clock Phase Select)
The CKPH bit selects the phase of the clock signal output through the SCKn pin. See Figure 32.70 for details. Set the
CKPH bit to 0 in all modes other than simple SPI mode and clock synchronous mode.
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32.2.26
32. Serial Communications Interface (SCI)
FIFO Control Register (FCR)
Address(es): SCI0.FCR 4007 0014h, SCI1.FCR 4007 0034h, SCI2.FCR 4007 0054h, SCI3.FCR 4007 0074h,
SCI4.FCR 4007 0094h, SCI5.FCR 4007 00B4h, SCI6.FCR 4007 00D4h, SCI7.FCR 4007 00F4h,
SCI8.FCR 4007 0114h, SCI9.FCR 4007 0134h
b15
b14
b13
b12
b11
RSTRG[3:0]
Value after reset:
1
1
1
b10
b9
b8
b7
RTRG[3:0]
1
1
0
0
b6
b5
b4
TTRG[3:0]
0
0
0
0
b3
b2
b1
DRES TFRST RFRST
0
0
0
0
b0
FM
0
Bit
Symbol
Bit name
Description
R/W
b0
FM
FIFO Mode Select
Valid only in asynchronous mode, including multi-processor mode,
or clock synchronous mode:
0: Non-FIFO mode.
Selects TDR/RDR or TDRHL/RDRHL for communication.
1: FIFO mode.
Selects FTDRHL/FRDRHL for communication.
R/W*1
b1
RFRST
Receive FIFO Data Register
Reset
Valid only when FCR.FM = 1:
0: Do not reset FRDRHL
1: Reset FRDRHL.
R/W
b2
TFRST
Transmit FIFO Data
Register Reset
Valid only when FCR.FM = 1:
0: Do not reset FTDRHL
1: Reset FTDRHL.
R/W
b3
DRES
Receive Data Ready Error
Select Bit
Selects the interrupt requested when detecting receive data ready: R/W
0: Receive data full interrupt (SCIn_RXI)
1: Receive error interrupt (SCIn_ERI).
b7 to b4
TTRG[3:0]
Transmit FIFO Data Trigger
Number
Valid only in asynchronous mode, including multi-processor mode,
or clock synchronous mode:
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
b11 to b8
RTRG[3:0]
Receive FIFO Data Trigger
Number
Valid only in asynchronous mode, including multi-processor mode,
or clock synchronous mode:
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
b15 to b12
RSTRG[3:0]
RTS Output Active Trigger
Number Select
Valid only in asynchronous mode, including multi-processor mode,
or clock synchronous mode, while FCR.FM = 1, SPMR.CTSE = 0,
and SPMR.SSE = 0:
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
Note 1.
Writable only when TE = 0 and RE = 0.
FCR selects FIFO mode, resets FTDRHL and FRDRHL, selects the FIFO data trigger number for transmission or
reception, and selects the RTS output active trigger number.
FM bit (FIFO Mode Select)
When the FM bit is set to 1, FTDRHL and FRDRHL are selected for communication. When the FM bit is set to 0, TDR
and RDR, or TDRHL and RDRHL are selected for communication.
RFRST bit (Receive FIFO Data Register Reset)
When the RFRST bit is set to 1, the FRDRHL register is reset and the received data count resets to 0. When 1 is written
to the RFRST bit, it is set to 0 after 1 PCLKA.
TFRST bit (Transmit FIFO Data Register Reset)
When the TFRST bit is set to 1, the FTDRHL register is reset and the transmit data count resets to 0. When 1 is written to
the TFRST bit, it is set to 0 after 1 PCLKA.
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32. Serial Communications Interface (SCI)
DRES bit (Receive Data Ready Error Select Bit)
On detecting a receive data ready error, the DRES bit selects between an SCIn_RXI interrupt request or an SCIn_ERI
interrupt request. Set the DRES bit to 1 when starting the DMAC or DTC and reading from the FRDRH and FRDRL
registers.
TTRG[3:0] bits (Transmit FIFO Data Trigger Number)
The TDFE flag is set to 1 when the amount of transmit data in FTDRHL is equal to or less than the transmit triggering
number specified in the TTRG[3:0] bits, and software can write data to FTDRHL. If SCR.TIE = 1, an SCIn_TXI
interrupt request occurs.
RTRG[3:0] bits (Receive FIFO Data Trigger Number)
The RDF flag is set to 1 when the amount of receive data in FRDRHL is equal to or greater than the specified receive
triggering number specified in the RTRG[3:0] bits, and software can read data from FRDRHL. If SCR.RIE = 1, an
SCIn_RXI interrupt request occurs.
When RTRG[3:0] is 0, the RDF flag is not set even when the amount of data in the receive FIFO is equal to 0.
Additionally, an SCIn_RXI interrupt does not occur.
RSTRG[3:0] bits (RTS Output Active Trigger Number Select)
When the amount of receive data stored in FRDRHL is equal to or greater than the receive triggering number specified in
the RSTRG[3:0] bits, the RTS signal goes high.
When RSTRG[3:0] is 0, the RTS signal does not go high even when the amount of data in FRDRHL is equal to 0.
32.2.27
FIFO Data Count Register (FDR)
Address(es): SCI0.FDR 4007 0016h, SCI1.FDR 4007 0036h, SCI2.FDR 4007 0056h, SCI3.FDR 4007 0076h,
SCI4.FDR 4007 0096h, SCI5.FDR 4007 00B6h, SCI6.FDR 4007 00D6h, SCI7.FDR 4007 00F6h,
SCI8.FDR 4007 0116h, SCI9.FDR 4007 0136h
Value after reset:
b15
b14
b13
—
—
—
0
0
0
b12
b11
b10
b9
b8
T[4:0]
0
0
0
0
0
b7
b6
b5
—
—
—
0
0
0
b4
b3
b2
b1
b0
0
0
R[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
R[4:0]
Receive FIFO Data Count
Indicates the amount of receive data stored in FRDRHL.
Valid only in asynchronous mode, including multi-processor mode, or
clock synchronous mode, when FCR.FM = 1.
R
b7 to b5
—
Reserved
These bits are read as 0.
R
b12 to b8
T[4:0]
Transmit FIFO Data Count
Indicates the amount of non-transmitted data stored in FTDRHL.
Valid only in asynchronous mode, including multi-processor mode, or
clock synchronous mode, when FCR.FM = 1.
R
Reserved
These bits are read as 0
R
b15 to b13 —
The FDR register indicates the amount of data stored in FRDRHL and FTDRHL.
R[4:0] bits (Receive FIFO Data Count)
The R[4:0] bits indicate the amount of receive data stored in FRDRHL. 00h indicates no receive data, and 10h indicates
that the maximum received data is stored in FRDRHL.
T[4:0] bits (Transmit FIFO Data Count)
The T[4:0] bits indicate the amount of non-transmitted data stored in FTDRHL. 00h indicates no transmit data, and 10h
indicates that all (maximum amount) of the data to be transmitted is stored in FTDRHL.
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32.2.28
32. Serial Communications Interface (SCI)
Line Status Register (LSR)
Address(es): SCI0.LSR 4007 0018h, SCI1.LSR 4007 0038h, SCI2.LSR 4007 0058h, SCI3.LSR 4007 0078h,
SCI4.LSR 4007 0098h, SCI5.LSR 4007 00B8h, SCI6.LSR 4007 00D8h, SCI7.LSR 4007 00F8h,
SCI8.LSR 4007 0118h, SCI9.LSR 4007 0138h
b15
b14
b13
—
—
—
0
0
0
Value after reset:
b12
b11
b10
b9
b8
PNUM[4:0]
0
0
0
b7
b6
b5
—
0
0
0
b4
b3
b2
FNUM[4:0]
0
0
0
0
0
b1
b0
—
ORER
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ORER
Overrun Error Flag
Valid only in asynchronous mode, including multi-processor mode,
or clock synchronous mode, with FIFO operation selected:
0: No overrun error occurred
1: Overrun error occurred.
R*1
b1
—
Reserved
This bit is read as 0
R
b6 to b2
FNUM[4:0]
Framing Error Count
Indicates the amount of data with a framing error in the receive data
stored in the Receive FIFO Data Register (FRDRHL)
R
b7
—
Reserved
This bit is read as 0
R
b12 to b8
PNUM[4:0]
Parity Error Count
Indicates the amount of data with a parity error in the receive data
stored in the Receive FIFO Data Register (FRDRHL)
R
b15 to b13
—
Reserved
These bits are read as 0
R
Note 1.
Write 0 to SSR_FIFO.ORER to clear the flag.
The LSR register indicates the receive error status.
ORER bit (Overrun Error Flag)
The ORER bit reflects the value in SSR_FIFO.ORER.
FNUM[4:0] bits (Framing Error Count)
The FNUM[4:0] value indicates the amount of data stored in the FRDRHL register with a framing error.
PNUM[4:0] bits (Parity Error Count)
The PNUM[4:0] value indicates the amount of data stored in the FRDRHL register with a parity error.
32.2.29
Compare Match Data Register (CDR)
Address(es): SCI0.CDR 4007 001Ah, SCI1.CDR 4007 003Ah, SCI2.CDR 4007 005Ah, SCI3.CDR 4007 007Ah,
SCI4.CDR 4007 009Ah, SCI5.CDR 4007 00BAh, SCI6.CDR 4007 00DAh, SCI7.CDR 4007 00FAh,
SCI8.CDR 4007 011Ah, SCI9.CDR 4007 013Ah
Value after reset:
Bit
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
Symbol
Bit name
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
CMPD[8:0]
0
0
0
0
0
Description
R/W
b8 to b0
CMPD[8:0]
Compare Match Data
Holds compare data pattern for address match wakeup function
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The CDR register sets the compare data for the address match function.
CMPD[8:0] bits (Compare Match Data)
The CMPD[8:0] bits set the data to be compared to receive data for the address match function, when the address match
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32. Serial Communications Interface (SCI)
function is enabled (DCCR.DCME = 1).
Three bit lengths are available:
CMPD[6:0] with 7-bit length
CMPD[7:0] with 8-bit length
CMPD[8:0] with 9-bit length.
32.2.30
Data Compare Match Control Register (DCCR)
Address(es): SCI0.DCCR 4007 0013h, SCI1.DCCR 4007 0033h, SCI2.DCCR 4007 0053h, SCI3.DCCR 4007 0073h,
SCI4.DCCR 4007 0093h, SCI5.DCCR 4007 00B3h, SCI6.DCCR 4007 00D3h, SCI7.DCCR 4007 00F3h,
SCI8.DCCR 4007 0113h, SCI9.DCCR 4007 0133h
b7
b6
DCME IDSEL
Value after reset:
0
1
b5
b4
b3
b2
b1
b0
—
DFER
DPER
—
—
DCMF
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DCMF
Data Compare Match Flag
0: Not matched
1: Matched.
R/(W)*1
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R
b3
DPER
Data Compare Match Parity
Error Flag
0: No parity error occurred
1: Parity error occurred.
R/(W)*1
b4
DFER
Data Compare Match
Framing Error Flag
0: No framing error occurred
1: Framing error occurred.
R/(W)*1
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
IDSEL
ID Frame Select
Valid only in asynchronous mode, including multi-processor mode:
0: Always compare data regardless of the MPB bit value
1: Only compare data when MPB bit is 1 (ID frame).
R/W
b7
DCME
Data Compare Match
Enable
Valid only in asynchronous mode, including multi-processor mode:
0: Disable address match function
1: Enable address match function.
R/W
Note 1.
Only 0 can be written to clear the flag after reading 1.
The DCCR register controls the address match function.
DCMF flag (Data Compare Match Flag)
The DCMF flag indicates that the SCI detected a match of the comparison data (CDR.CMPD) with the receive data.
[Setting condition]
When comparison data (CDR.CMPD) matches the receive data, when DCCR.DCME = 1.
[Clearing condition]
When 0 is written after 1 is read from DCMF.
Clearing the SCR.RE bit to 0 does not affect the DCMF flag, which keeps its previous value.
DPER flag (Data Compare Match Parity Error Flag)
The DPER flag indicates that a parity error occurred on address match detection (receive data match detection).
[Setting condition]
When a parity error is detected in the frame in which an address match is detected.
[Clearing conditions]
When 0 is written after 1 is read from DPER.
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32. Serial Communications Interface (SCI)
Clearing the SCR.RE bit to 0 (serial reception is disabled) does not affect the DPER flag, which keeps its previous value.
DFER flag (Data Compare Match Framing Error Flag)
The DFER flag indicates that a framing error occurred on address match detection (receive data match detection).
[Setting conditions]
When a stop bit of the frame in which an address match is detected is 0.
When in 2-stop-bit mode, only the first stop bit is checked for a value of 1, while the second stop bit is not checked.
[Clearing conditions]
When 0 is written after 1 is read from DFER.
When the SCR.RE bit is set to 0 (serial reception is disabled), the DFER flag is not affected and keeps its previous value.
IDSEL bit (ID Frame Select)
The IDSEL bit selects whether to compare data regardless of the MPB bit value or to compare data only when MPB = 1
(ID frame), when the address match function is enabled.
DCME bit (Data Compare Match Enable)
The DCME bit enables or disables the address match function (data compare match function).
If the SCI detects a match between comparison data (CDR.CMPD) and receive data, the DCME bit clears automatically
and the SCI operates in receive mode without the data compare match function. See section 32.3.6, Address Match
(Receive Data Match Detection) Function.
The write value must be 0 for all modes other than asynchronous mode.
32.2.31
Serial Port Register (SPTR)
Address(es): SCI0.SPTR 4007 001Ch, SCI1.SPTR 4007 003Ch, SCI2.SPTR 4007 005Ch, SCI3.SPTR 4007 007Ch,
SCI4.SPTR 4007 009Ch, SCI5.SPTR 4007 00BCh, SCI6.SPTR 4007 00DCh, SCI7.SPTR 4007 00FCh,
SCI8.SPTR 4007 011Ch, SCI9.SPTR 4007 013Ch
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SPB2I SPB2D RXDM
O
T
ON
0
1
1
Bit
Symbol
Bit name
Description
R/W
b0
RXDMON
Serial Input Data Monitor
Indicates the state of the RXDn pin:
0: RXDn pin is low
1: RXDn pin is high.
R
b1
SPB2DT
Serial Port Break Data
Select
Selects the output level of the TXDn pin when SCR.TE = 0:
0: Output low level on TXDn pin
1: Output high level on TXDn pin.
R/W
b2
SPB2IO
Serial Port Break I/O
Selects whether the value of SPB2DT is output to TXDn pin:
0: Do not output value of SPB2DT bit on TXDn pin
1: Output value of SPB2DT bit on TXDn pin.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SPTR register provides confirmation of the serial reception pin (RXDn pin) status and sets the transmission pin
(TXDn pin) status.
This register can only be used in asynchronous mode.
The TXDn pin status is determined by the combination of SCR.TE, SPTR.SPB2IO, and SPTR.SPB2DT bit settings, as
shown in Table 32.22.
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Table 32.22
32. Serial Communications Interface (SCI)
TXDn pin status
Value of
SCR.TE
Value of
SPTR.SPB2IO
Value of
SPTR.SPB2DT
TXDn pin status
0
0
x
Hi-Z (initial value)
0
1
0
Low level output
0
1
1
High level output
1
x
x
Serial transmit data is output
x: Don’t care.
Note:
32.3
Use the SPTR register in asynchronous mode only. Using this register in any other mode is not guaranteed.
Operation in Asynchronous Mode
Figure 32.2 shows the general format for asynchronous serial communications. One frame consists of a start bit (low
level), transmit or receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the
communications line is held in the mark state (high level) when not communicating.
The SCI monitors the communications line. When the SCI detects a low, it regards that as a start bit and starts serial
communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communications. Both the
transmitter and receiver have a double-buffered structure in addition to FIFO mode, so that data can be read or written
during transmission or reception, enabling continuous data transmission and reception.
Idle state
(mark state)
1
LSB
0
Serial data
D0
1
MSB
D1
D2
Start bit
D3
D4
D5
D6
D7
Transmit/receive data
1 bit
7, 8 or 9 bits
1
0/1
1
Parity bit
Stop bit
1 or 0 bit
1 or 2 bits
One unit of transfer data (character or frame)
Figure 32.2
32.3.1
Data format in asynchronous serial communications with 8-bit data, parity bit, and 2 stop bits
Serial Data Transfer Format
Table 32.23 lists the serial data transfer formats that can be used in asynchronous mode. Any of the 18 transfer formats
can be selected in the SMR and SCMR register settings. For details on the multi-processor function, see section 32.4,
Multi-Processor Communication Function.
Table 32.23
Serial transfer formats in asynchronous mode (1 of 3)
SCMR
setting
SMR
setting
CHR1
CHR
PE
MP
STOP
0
0
0
0
0
Serial transfer format and frame length
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2
3
S
9-bit data
4
5
6
7
8
9
10
11
12
13
STOP
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Table 32.23
32. Serial Communications Interface (SCI)
Serial transfer formats in asynchronous mode (2 of 3)
SCMR
setting
SMR
setting
CHR1
CHR
PE
MP
STOP
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
Serial transfer format and frame length
1
1
0
0
1
1
0
0
1
1
—
—
0
0
0
0
0
0
0
0
0
0
1
1
1
2
S
3
4
5
6
7
8
9
10
11
12
9-bit data
STOP
STOP
S
9-bit data
P
STOP
S
9-bit data
P
STOP
S
8-bit data
STOP
S
8-bit data
STOP
STOP
S
8-bit data
P
STOP
S
8-bit data
P
STOP
S
7-bit data
STOP
S
7-bit data
STOP
STOP
S
7-bit data
P
STOP
S
7-bit data
P
STOP
S
9-bit data
MPB
STOP
S
9-bit data
MPB
STOP
13
0
1
STOP
0
1
0
1
STOP
0
1
0
1
STOP
0
1
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Table 32.23
32. Serial Communications Interface (SCI)
Serial transfer formats in asynchronous mode (3 of 3)
SCMR
setting
SMR
setting
CHR1
CHR
PE
MP
STOP
1
0
—
1
0
1
0
1
1
1
1
Serial transfer format and frame length
—
—
—
1
1
1
1
2
S
3
4
5
6
7
8
9
10
11
8-bit data
MPB
STOP
S
8-bit data
MPB
STOP
S
7-bit data
MPB
STOP
S
7-bit data
MPB
STOP
12
13
1
STOP
0
1
STOP
S:
STOP:
P:
MPB:
Start bit
Stop bit
Parity bit
Multi-processor bit
32.3.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times*1 the bit rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Because receive data is sampled on the rising edge of the 8th pulse*1 of the base clock, data is latched at the middle of
each bit, as shown in Figure 32.3. The reception margin in asynchronous mode is determined by the following formula
(1):
M=
(0.5 -
1
) - (L - 0.5) F 2N
D - 0.5
N
(1 + F)
× 100 [%] ... Formula (1)
M: Reception margin
N: Ratio of bit rate to clock
(N = 16 when SEMR.ABCSE = 0 and SEMR.ABCS = 0. N = 8 when SEMR.ABCS = 1. N = 6 when SEMR.ABCSE = 1.)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 13)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined using the following formula:
M = {0.5 - 1/(2 × 16)} × 100 (%) = 46.875%
This represents the computed value. Renesas recommends a margin of 20% to 30% in system design.
Note 1. In this example, the SEMR.ABCS bit is 0 and the SEMR.ABCSE is 0. When the ABCS bit is 1 and the ABCSE bit
is 0, a frequency of 8 times the bit rate is used as a base clock, and receive data is sampled on the rising edge of
the 4th pulse of the base clock.
When the ABCSE bit is 1, a frequency of 6 times the bit rate is used as a base clock, and the receive data is
sampled on the rising edge of the 3rd pulse of the base clock.
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32. Serial Communications Interface (SCI)
16 clock pulses
8 clock pulses
0
7
15 0
7
15 0
Internal base clock
Receive data (RXDn)
D0
Start bit
D1
Synchronization
sampling timing
Data sampling
timing
Figure 32.3
32.3.3
Receive data sampling timing in asynchronous mode
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be
selected as the SCI transfer clock, based on the SMR.CM and SCR.CKE[1:0] settings.
When an external clock is input to the SCKn pin, the clock frequency must be 16 times the bit rate (when SEMR.ABCS
= 0) or 8 times the bit rate (when SEMR.ABCS = 1).
When the SCI uses its internal clock, the clock can be output from the SCKn pin. The frequency of the clock output in
this case is equal to the bit rate, and the phase is configured so that the rising edge of the clock is in the middle of the
transmit data, as shown in Figure 32.4.
SCKn
TXDn
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 32.4
32.3.4
Phase relationship between output clock and transmit data in asynchronous mode when
SMR.CHR = 0, PE = 1, MP = 0, and STOP = 1
Double-Speed Operation and Frequency of 6 Times the Bit Rate
When the SEMR.ABCS bit is set to 1 and 8 pulses of the base clock for a 1-bit period is selected, the SCI operates on the
bit rate that is equal to twice the value when ABCS is set to 0. When the SEMR.BGDM bit is set to 1, the cycle of the
base clock is half and the bit rate is double the value when BGDM is set to 0. When the SCR.CKE[1] bit is set to 0 and
the on-chip baud rate generator is selected, setting the ABCS and BGDM bits to 1 allows the SCI to operate at a bit rate
equal to four times the value when the ABCS and BGDM bits are set to 0. When the SEMR.ABCSE bit is set to 1, the
number of basic clock pulses is 6 during a period of 1 bit, and the SCI operates at a bit rate that is equal to 16/3 times the
value when SEMR.ABCS = 0, SEMR.BGDM = 0, and SMER.ABCSE = 0.
As shown by formula (1) in section 32.3.2, Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode, the reception margin decreases when the SEMR.ABCS or SEMR.ABCSE bit in SEMR is set to 1. Therefore, if
the target bit rate can be obtained with ABCS or ABCSE set to 0, it is recommended that you use the SCI with ABCS and
ABCSE set to 0.
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32.3.5
32. Serial Communications Interface (SCI)
CTS and RTS Functions
The CTS function uses the input on the CTSn_RTSn pin in transmission control. Setting the SPMR.CTSE bit to 1
enables the CTS function. When the CTS function is enabled, placing a low level on the CTSn_RTSn pin causes
transmission to start.
Driving the CTSn_RTSn pin high while transmission is in progress does not affect transmission of the current frame.
In the RTS function, which uses the output on the CTSn_RTSn pin, a low level is output when reception becomes
possible. Conditions for the output of low and high levels are shown in this section.
[Conditions for low-level output]
(a)
Non-FIFO selected when all of the following conditions are satisfied
The value of the SCR.RE bit is 1
Reception is not in progress
There is no received data yet to be read
The ORER, FER, and PER flags in the SSR register are all 0.
(b)
FIFO selected when all of the following conditions are satisfied
The value of the SCR.RE bit is 1
The amount of receive data written in FRDRHL is equal to or less than the specified receive triggering number
The ORER bit in the SSR_FIFO register (ORER in FRDRH) is 0.
[Condition for high-level output]
(a)
Non-FIFO selected
The conditions for low-level output are not satisfied
When reception is terminated with SCR.RE = 0 without reading the RDR register after reception is complete, RTS
remains high. At this time, read the SCR register for dummy values after writing 0 to SCR.RE.
(b)
FIFO selected
The conditions for low-level output are not satisfied.
32.3.6
Address Match (Receive Data Match Detection) Function
The address match function can be used only in asynchronous mode.
If the DCCR.DCME bit is set to 1*4, when one frame of data is received, the SCI compares that received data with the
data set in CDR.CMPD. If the SCI detects a match to the comparison data (CDR.CMPD*3) with the received data, the
SCI can issue the SCIn_RXI interrupt request.
If the SMR.MP bit is set to 0, comparison occurs only for valid data in receive format. In multi-processor mode
(SMR.MP bit = 1), if the DCCR.IDSEL bit is set to 1, receive data where the MPB bit is 1 is subject to comparison for
address match. Receive data where the MPB bit is 0 is always treated as a mismatch.
If the DCCR.IDSEL bit is set to 0, SCI performs address match detection regardless of the MPB bit value of the received
data. Until SCI detects a match between the comparison data (CDR.CMPD*3) and the receive data, received data is
skipped (discarded), and the SCI cannot detect a parity error or framing error.
When SCI detects a match, the DCCR.DCME bit is automatically cleared, and the DCCR.DCMF flag is set to 1. If the
DCCR.IDSEL bit is set to 1, the SCR.MPIE bit is automatically cleared. If DCCR.IDSEL is set to 0, the value of the
SCR.MPIE bit is retained. If the SCR.RIE bit is set to 1, the SCI issues an SCIn_RXI interrupt request.
If the SCI detects a framing error in the receive data for which a match is detected, the DCCR.DFER bit is set to 1, and if
the SCI detects a parity error in that frame, the DCCR.DPER bit is set to 1. The compared receive data is not stored in the
RDR register*1, and SSR.RDRF remains 0.*2
After the SCI detects a match, and DCCR.DCME is automatically cleared, the SCI receives the next data continuously
based on the current register setting.
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32. Serial Communications Interface (SCI)
When the DCCR.DFER or DCCR.DPER flag is set, the address match is not performed. Before enabling the address
match function, set the DCCR.DFER and DCCR.DPER flags to 0.
Examples of the address match function are shown in Figure 32.5 and Figure 32.6.
Note 1. When FCR.FM = 1, this refers to the FRDRHL register.
Note 2. When FCR.FM = 1, this refers to the SSR_FIFO.RDF flag.
Note 3. This comparative target can select one length of 3 types: CMPD[6:0] with 7-bit length, CMPD[7:0] with 8-bit
length, and CMPD[8:0] with 9-bit length.
Note 4. Set the DCCR.DCME bit to 1 before receiving the start bit of the received frame that performs address matching.
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32. Serial Communications Interface (SCI)
Data (ID1)
1
Data (Data1)
Start bit
0
Stop bit Start bit
D0
D1
D7
Parity
1
0
D0
D1
D7
Parity
SCIn_AM
SCIn_DCUF
DCME
DCMF flag
SCIn_RXI interrupt flag
(IELSRn.IR)
RDRF flag
DPER flag
DFER flag
RDR
If compare mismatched,
the flag is NOT set
Not stored to RDR if CDR
setting value mismatched
to receive data
(a) Example of compare mismatch between receive data and CDR (8-bit length/parity/non-multiprocessor mode)
Data (ID2)
1
Start bit
0
Data (Data2)
Stop bit Start bit
D0
D1
D7
Parity
1
0
Stop bit Start bit
D0
D1
D7
Parity
1
0
SCIn_AM
SCIn_DCUF
DCME
DCMF
MPIE
Clear the flag
SCIn_RXI int flag
(IELSRn.IR)
RDRF
DFER
RDR
Data2
DCME = 0
If error occurs,
the flag is set
Not stored to RDR, if CDR
setting value mismatched
to receive data
Non-address
match receive, and
set the flag
Stored
receive data
(b) Example of compare match between receive data and CDR (8-bit length/parity/non-multiprocessor mode)
Figure 32.5
Example of address match (1) non-multiprocessor mode
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32. Serial Communications Interface (SCI)
Data (ID1)
Data (Data0)
1
Start bit
0
MPB
D0
D1
D7
0
Stop bit Start bit
1
0
MPB Stop bit Start bit
D0
D1
D7
1
1
SCIn_AM
SCIn_DCUF
DCME
DCMF
SCIn_RXI int flag
(IELSRn.IR)
RDRF
DPER
DFER
RDR
If compare mismatched,
the flag is not set
The data in which MPB is 0 is
detected as mismatched
Not stored to RDR if CDR
setting mismatched to
receive data
(a) Example of compare mismatch between receive data and CDR (8-bit length/IDSEL = 1/multi-processor mode)
Data (Data2)
Data (ID2)
1
Start bit
0
MPB Stop bit Start bit
D0
D1
D7
1
1
0
Stop bit Start bit
D0
D1
D7
MPB
1
0
SCIn_AM
SCIn_DCUF
DCME
DCMF
MPIE
Clear the Flag
SCIn_RXI int flag
(IELSRn.IR)
RDRF
DFER
RDR
Data2
DCME = 0
If error occurs,
the flag is set
Not stored to RDR if CDR
setting value mismatched
to receive data
Non-address match and
non-multiprocessor and
set the flag
Stored
receive data
(b) Example of compare match between receive data and CDR (8-bit length/IDSEL = 1/multi-processor mode)
Figure 32.6
Example of address match (2) multi-processor mode
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32.3.7
32. Serial Communications Interface (SCI)
SCI Initialization in Asynchronous Mode
Before transmitting and receiving data, start by writing the initial value 00h to the SCR register, then continue through
the SCI initialization procedure (select non-FIFO or FIFO) shown in Figure 32.7 and Figure 32.8. Whenever the
operating mode or transfer format is to be changed, the SCR register must be initialized before the change is made.
When the external clock is used in asynchronous mode, ensure that the clock signal is supplied during initialization.
Note:
Note:
When the SCR.RE bit is set to 0, the ORER, FER, RDRF, RDF, PER, and DR flags in SSR/SSR_FIFO, and the
RDR and RDRHL registers are not initialized. When the TE bit is set to 0, the TEND flag for the selected FIFO
buffer is not initialized.
Switching the value of the SCR.TE bit from 1 to 0 or 0 to 1 while the SCR.TIE bit is 1 leads to the generation of an
SCIn_TXI interrupt request.
[ 1 ] Set the FCR.FM bit to 0.
Start initialization
Set the SCR.TIE, RIE, TE, RE, and
TEIE bits to 0
[ 2 ] Set the clock selection in SCR.
When the clock output is selected in asynchronous mode,
the clock is output immediately after SCR settings are made.
Set the FCR.FM bit to 0
[1]
Set the SCR.CKE[1:0] bits
[2]
Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits to 0
[3]
[ 3 ] Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits to 0.
Step [3] can be skipped if the values have not been changed
from the initial values.
[ 4 ] Set data transmission/reception format in SMR, SCMR, and
SEMR.
[ 5 ] Write a value corresponding to the bit rate to BRR.
This step is not necessary if an external clock is used.
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[4]
Set a value in BRR
[5]
Set a value in MDDR
[6]
[ 7 ] Make I/O port settings to enable input and output functions
as required for TXDn, RXDn, and SCKn pins.
Set the I/O port functions
[7]
Set the SCR.TE or RE bit to 1, and
set the SCR.TIE and RIE bits
[ 8 ] Set the SCR.TE or RE bit to 1. Also set the SCR.TIE and
RIE bits. Setting the TE and RE bits allows TXDn and RXDn
to be used.
[8]
[ 6 ] Write the value obtained by correcting a bit rate error in
MDDR. This step is not necessary if the BRME bit in SEMR
is set to 0 or an external clock is used.
Initialization completion
Figure 32.7
Example flow of SCI initialization in asynchronous mode with non-FIFO selected
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32. Serial Communications Interface (SCI)
Start initialization
[ 1 ] Set the FCR.FM, TFRST, and RFRST bits to 1
(FIFO mode enabled, transmit/receive FIFOs empty).
Set the FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0] bits.
Set the SCR.TIE, RIE, TE, RE, and
TEIE bits to 0
Set the FCR.FM, TFRST, and RFRST bits to 1.
Set the FCR.TTRG[3:0], RTRG[3:0], and
RSTRG[3:0] bits
[1]
[ 2 ] Set the clock selection in SCR.
When the clock output is selected in asynchronous mode,
the clock is output immediately after SCR settings are made.
[ 3 ] Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits to 0.
Step [3] can be skipped if the values are not changed from
the initial values.
Set the SCR.CKE[1:0] bits
[2]
Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits to 0
[3]
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[4]
Set a value in BRR
[5]
[ 6 ] Write the value obtained by correcting a bit rate error in
MDDR. This step is not required if the BRME bit in SEMR is
set to 0 or an external clock is used.
Set a value in MDDR
[6]
[ 7 ] Set the FCR.TFRST and RFRST bits to 0.
[7]
[ 8 ] Make I/O port settings to enable input and output functions
as required for TXDn, RXDn, and SCKn pins.
Set the I/O port functions
[8]
[ 9 ] Set the SCR.TE or RE bit to 1. Also set the SCR.TIE and
RIE bits. Setting the TE and RE bits allows TXDn and RXDn
to be used.
Set the SCR.TE or RE bit to 1, and
set the SCR.TIE and RIE bits
[9]
Set the FCR.TFRST and RFRST bits to 0
[ 4 ] Set data transmission/reception format in SMR, SCMR, and
SEMR.
[ 5 ] Write a value corresponding to the bit rate to BRR.
This step is not required if an external clock is used.
Initialization completion
Figure 32.8
32.3.8
(1)
Example SCI initialization flow in synchronous mode with FIFO selected
Serial Data Transmission in Asynchronous Mode
Non-FIFO selected
Figure 32.9, Figure 32.10, and Figure 32.11 show examples of serial transmission in asynchronous mode.
In serial transmission, the SCI operates as described in this section. When the SCR.TE bit is set to 1, the high level for
one frame (preamble) is output to TXD.
1. The SCI transfers data from the TDR*1 register to the TSR register when data is written to TDR*1 in the SCIn_TXI
interrupt handling routine.
The SCIn_TXI interrupt request at the beginning of transmission is generated when the SCR.TE and SCR.TIE bits
are set to 1 simultaneously by a single instruction.
2. Transmission starts after the SPMR.CTSE bit is set to 0 (CTS function is disabled) or a low level on the
CTSn_RTSn pin causes data transfer from the TDR*1 register to the TSR register. If the SCR.TIE bit is 1, an
SCIn_TXI interrupt request is generated. Continuous transmission is possible by writing the next transmit data to
the TDR*1 register in the SCIn_TXI interrupt handling routine before transmission of the current transmit data is
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32. Serial Communications Interface (SCI)
complete. When SCIn_TEI interrupt requests are in use, set the SCR.TIE bit to 0 (SCIn_TXI interrupt requests are
disabled) and the SCR.TEIE bit to 1 (an SCIn_TEI interrupt request is enabled) after the last of the data to be
transmitted is written to the TDR*1 register from the handling routine for SCIn_TXI requests.
3. Data is sent from the TXDn pin in the following order:
Start bit
Transmit data
Parity bit or multi-processor bit (can be omitted depending on the format)
Stop bit.
4. The SCI checks for an update of the TDR register on the output of the stop bit.
5. When the TDR register is updated, setting the SPMR.CTSE bit to 0 (CTS function is disabled) or a low level input
on the CTSn_RTSn pin, causes the transfer of the next transmit data from the TDR*1 register to the TSR register
and the transmission of the stop bit, after which serial transmission of the next frame starts.
6. If the TDR register is not updated, the SSR.TEND flag is set to 1, the stop bit is sent, and the mark state is entered,
where 1 is output. If the SCR.TEIE bit is 1, the SSR.TEND flag is set to 1 and an SCIn_TEI interrupt request is
generated.
Note 1. Only write data to the TDRHL register when 9-bit data length is selected.
Figure 32.9, Figure 32.10, and Figure 32.11 show examples of serial transmission in asynchronous mode.
Start bit
1
0
SCR.TE bit
Data
D0 D1
Parity bit Stop bit
D7 0/1
1
0
D0
D1
D7 0/1
1
0
1 frame
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Note 1.
Figure 32.9
Data written to TDR in
SCIn_TXI interrupt
handling routine
SCIn_TXI interrupt Data written to TDR in
request generated SCIn_TXI interrupt
handling routine
Data written to TDR in
SCIn_TXI interrupt
handling routine
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example operation for serial transmission in asynchronous mode (1) with 8-bit data, parity bit, 1
stop bit, CTS function not used, and at the beginning of transmission
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32. Serial Communications Interface (SCI)
CTSn_RTSn pin
Data
Start bit
1
0 D0 D1
SCR.TE bit
Parity bit
D7 0/1 1
Stop bit
0 D0 D1
D7 0/1 1
Idle state
(mark state)
0
1 frame
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Data written to TDR in SCIn_TXI
Data written to TDR
interrupt handling routine
in SCIn_TXI interrupt
handling routine
SCIn_TXI interrupt
Data written to TDR in
SCIn_TXI interrupt handling
routine
request generated
Note 1.
Figure 32.10
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example operation for serial transmission in asynchronous mode (2) with 8-bit data, parity bit,
one stop bit, CTS function used, and at the beginning of transmission
Start bit
1
SCR.TE bit
Data
0 D0 D1
Parity bit
Stop bit
D7 0/1 1
1
Data written to TDR in
SCIn_TXI interrupt
handling routine
1 frame
Figure 32.11
0 D0 D1
D7 0/1 1
Idle state
(mark state)
(TIE = 0)
SSR.TEND flag
Note 1.
D7 0/1 1
(TIE = 1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SCIn_TXI interrupt
request generated
0 D0 D1
Data written to TDR in SCIn_TXI
interrupt handling routine
(Set the TIE bit to 0 and the TEIE bit to
1 after writing the last data)
SCIn_TXI interrupt
request generated
SCIn_TEI interrupt
request generated
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example operation for serial transmission in asynchronous mode (3) with 8-bit data, parity bit,
one stop bit, CTS function not used, and from the middle of transmission until transmission
completion
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32. Serial Communications Interface (SCI)
Initialization
[1]
[1] SCI Initialization:
Set data transmission.
After the SCR.TE bit is set to 1, 1 is output for a
Frame (preamble), and transmission is enabled.
[2]
[2] Transmit data write to TDR by an SCIn_TXI interrupt
request. When transmit data is transferred from TDR
to TSR, a transmit data empty interrupt (SCIn_TXI)
request is generated. Write transmit data to TDR once
in the SCIn_TXI interrupt processing routine.
Start transmission
No
SCIn_TXI interrupt
[3] Serial transmission continuation procedure:
To continue serial transmission write transmit data to
TDR once using an SCIn_TXI interrupt request.
Transmit data can also be written to TDR by activating
the DMAC or DTC.
When SCIn_TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after
the last of the data to be transmitted is written to
TDR.
Yes
Write transmit data to TDR
No
All data transmitted?
[3]
Yes
[4] Break output at the end of serial transmission:
To output a break in serial transmission, after setting
the output state (LOW level output) of TXDn pin by
SPTR.SPB2IO and SPTR.SPB2DT bits, set the
SCR.TE bit to 0.
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt
Yes
No
Break output
[4]
Yes
Set TXD port function
Note:
The TDR register becomes the TDRHL register when
9-bit data length is selected.
Set bits TIE, TE, and TEIE in SCR to 0
End
Figure 32.12
(2)
Example flow of serial transmission in asynchronous mode with non-FIFO selected
FIFO selected
Figure 32.13 shows an example of a data format that is written to FTDRH and FTDRL in asynchronous mode.
Data corresponding to the data length is set to FTDRH and FTDRL. Write 0 for unused bits. Write in order from FTDRH
to FTDRL.
Data
Length
Transmit data in FTDRH, FTDRL
Register
Setting
FTDRHL
FTDRH
SCMR.
CHR1
SMR.
CHR
b7
7 bits
1
0
8 bits
1
0
9 bits
FTDRL
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
Don’t
care
—
—
—
—
—
—
—
b7
b6
—
b5
b4
b3
b2
b1
b0
7-bit transmit data
8-bit transmit data
9-bit transmit data
—: Invalid. The write value should be 0.
Figure 32.13
Data format written to FTDRH and FTDRL with FIFO selected
In serial transmission, the SCI operates as described in this section. When the TE bit is set to 1, the high level is output to
TXD for one frame (preamble).
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32. Serial Communications Interface (SCI)
1. The SCI transfers data from the FTDRL*1 register to the TSR register when data is written to FTDRL*1 in the
SCIn_TXI interrupt handling routine. The amount of data that can be written to FTDRL is 16 minus FDR.T[4:0]
bytes. The SCIn_TXI interrupt request at the beginning of the transmission is generated when the SCR.TE and
SCR.TIE bits are set to 1 simultaneously by a single instruction.
2. Transmission starts after the SPMR.CTSE bit is set to 0 (CTS function is disabled) or a low level on the
CTSn_RTSn pin causes data transfer from the FTDRL*1 register to the TSR register. When the amount of transmit
data written in FTDRL is equal to or less than the specified transmit triggering number, SSR_FIFO.TDFE is set to
1. If the SCR.TIE bit is 1, an SCIn_TXI interrupt request is generated. Continuous transmission is possible by
writing the next transmit data to FTDRL*1 in the SCIn_TXI interrupt handling routine before transmission of the
current transmit data is complete. When SCIn_TEI interrupt requests are in use, set the SCR.TIE bit to 0 (SCIn_TXI
interrupt requests are disabled) and the SCR.TEIE bit to 1 (an SCIn_TEI interrupt request is enabled) after the last
of the data to be transmitted is written to the FTDRL*1 *2 register from the handling routine for SCIn_TXI requests.
3. Data is sent from the TXDn pin in the following order:
Start bit
Transmit data
Parity bit or multi-processor bit (can be omitted depending on the format)
Stop bit.
4. On output of the stop bit, the SCI checks whether non-transmitted data remains in the FTDRL*3 register.
5. When data is set to FTDRL*3, setting the SPMR.CTSE bit to 0 (CTS function is disabled) or a low level input on the
CTSn_RTSn pin causes transfer of the next transmit data from FTDRL*1 to TSR and transmission of the stop bit,
after which serial transmission of the next frame starts.
6. If data is not set in FTDRL*3, the TEND flag in SSR_FIFO is set to 1, the stop bit is sent, and the mark state is
entered in which 1 is output. If the SCR.TEIE bit is 1, the SSR_FIFO.TEND flag is set to 1 and an SCIn_TEI
interrupt request is generated.
Note 1. Write data not to FTDRL but to the FTDRH and FTDRL registers.
Note 2. Write data in the order from FTDRH to FTDRL when 9-bit data length is selected.
Note 3. The SCI only checks for an update to the FTDRL register and not the FTDRH register when 9-bit data length is
selected.
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32. Serial Communications Interface (SCI)
Figure 32.14 shows an example flow of serial transmission in asynchronous mode with FIFO selected.
Initialization
[1]
[1]
SCI initialization:
Set data transmission.
After the SCR.TE bit is set to 1, 1 is output for a frame
(preamble), and transmission is enabled.
[2]
Transmit data write to FTDRL*1 by an SCIn_TXI interrupt
request:
When transmit data is transferred from FTDRL to TSR,
when the amount of transmit data written in FTDRL is
equal to or less than the specified transmit triggering
number, a transmit data FIFO empty interrupt
(SCIn_TXI) request is generated. Write transmit data to
FTDRL*1, *2 once in the SCIn_TXI interrupt handling
routine.
[3]
Serial transmission continuation procedure :
To continue serial transmission, write all transmit data to
FTDRL using an SCIn_TXI interrupt request and clear
the SSR_FIFO.TDFE flag to 0. The amount of
transmission data that is possible to write is 16 - (the
number of stored transmit FIFO data ).
Transmit data can also be written to FTDRL by activating
the DMAC or DTC. When data Is written to FTDRL by
DMAC or DTC, the TDFE flag is cleared automatically .
Therefore, do not write to the TDFE flag.
When SCIn_TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last
of the data to be transmitted is written to FTDRL.
[4]
Break output at the end of serial transmission :
To output a break in serial transmission , after setting the
output state (low level output) of the TXDn pin using
SPTR.SPB2IO and SPTR.SPB2DT bits, set the SCR.TE
bit to 0.
Start data transmission
SCIn_TXI interrupt?
No
[2]
Yes
Write transmit data to FTDRL*1, *2
All transmit data
written to FTDRL*1, *2 register?
[3]
No
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt?
Yes
Break output?
No
Yes
Set TXD port functions
[4]
Note 1.
Set bits SCR.TE, TIE, and TEIE to 0
Note 2.
When data length is 9 bits, this refers to FTDRH and
FTDRL registers.
When data length is 9 bits, write in the order from
FTDRH to FTDRL.
End
Figure 32.14
32.3.9
(1)
Example flow of serial transmission in asynchronous mode with FIFO selected
Serial Data Reception in Asynchronous Mode
Non-FIFO selected
Figure 32.15 and Figure 32.16 show an example of the operation for serial data reception in asynchronous mode.
In serial data reception, the SCI operates as follows:
1. When the value of the SCR.RE bit becomes 1, the output signal on the CTSn_RTSn pin goes low.
2. The SCI monitors the communications line and when it detects a start bit, the SCI performs internal
synchronization, stores receive data in RSR, and checks the parity bit and stop bit.
3. If an overrun error occurs, the SSR.ORER flag is set to 1. If the SCR.RIE bit is 1, an SCIn_ERI interrupt request is
generated. Receive data is not transferred to the RDR*1 register.
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32. Serial Communications Interface (SCI)
4. If a parity error is detected, the SSR.PER flag is set to 1 and receive data is transferred to the RDR*1 register. If the
SCR.RIE bit is 1, an SCIn_ERI interrupt request is generated.
5. If a frame error is detected, the SSR.FER flag is set to 1 and receive data is transferred to the RDR*1 register. If the
SCR.RIE bit is 1, an SCIn_ERI interrupt request is generated.
6. When reception finishes successfully, receive data is transferred to the RDR*1 register. If the SCR.RIE bit is 1, an
SCIn_RXI interrupt request is generated. Continuous reception is enabled by reading the receive data transferred to
the RDR register in the SCIn_RXI interrupt handling routine before reception of the next receive data completes.
Reading the received data that was transferred to the RDR register causes the CTSn_RTSn pin to output low.
Note 1. Only read data in the RDRHL register when 9-bit data length is selected.
Data
Start bit
1
D0
0
D1
Parity Stop
bit
bit
D7
0/1
Data
Start bit
1
0
D0
D1
Parity Stop
bit
bit
D7
0/1
1
Idle state
(mark state)
0
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.FER flag
SCIn_RXI
interrupt
request
generated
1 frame
Note 1.
Figure 32.15
RDR data read in SCIn_RXI
interrupt handling routine
SCIn_ERI interrupt request
generated by framing error
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI operation for serial reception in asynchronous mode (1) when the RTS function is
not used, and with 8-bit data, parity bit, and 1 stop bit
1
Data
Start bit
0
D0
Parity Stop
bit
bit
D7
0/1
1
Data
Start bit
0
D0
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
Start bit
0
Data
D0
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.FER flag
SCIn_RXI
interrupt
request
generated
RDR data read in SCIn_RXI
interrupt handling routine
SCIn_ERI interrupt request
generated by framing error
Error flag is cleared
CTSn_RTSn pin
1 frame
Note 1.
Figure 32.16
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI operation for serial reception in asynchronous mode (2) when RTS function is
used, and with 8-bit data, parity bit, and 1 stop bit
Table 32.24 lists the states of the flags in the SSR register and receive data handling when a receive error is detected.
If a receive error is detected, an SCIn_ERI interrupt request is generated but an SCIn_RXI interrupt request is not
generated. Data reception cannot be resumed while the receive error flag is 1. Also, set the ORER, FER, and PER bits to
0 before resuming reception. In addition, be sure to read the RDR or RDRHL register during overrun error processing.
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32. Serial Communications Interface (SCI)
When a reception is forcibly terminated by setting the SCR.RE bit to 0 during operation, read the RDR or RDRHL
register because received data that is not yet read might be left in the RDR or RDRHL.
Figure 32.17 and Figure 32.18 show example flows of serial data reception.
Table 32.24
Flags in SSR Status Register and receive data handling
Flags in the SSR Status Register
ORER
FER
PER
Receive data
Receive error type
1
0
0
Lost
Overrun error
0
1
0
Transferred to RDR
Framing error
0
0
1
Transferred to RDR
Parity error
1
1
0
Lost
Overrun error + framing error
1
0
1
Lost
Overrun error + parity error
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
Lost
Overrun error + framing error + parity error
Note 1.
Only read data in the RDRHL register when 9-bit data length is selected.
[1] SCI initialization:
Set data reception.
[1]
Initialization
Start data reception
Read ORER, PER, and FER flags in SSR
[2] [3] Receive error processing and break detection:
If a receive error occurs, an SCIn_ERI interrupt is generated. An
error is identified by reading the ORER, PER, and FER flags in SSR.
After performing the appropriate error processing, always set the
ORER, PER, and FER flags to 0. Reception cannot be resumed if
any of these flags is set to 1. For a framing error, a break can be
detected by reading the value of the input port associated with the
RXDn pin.
[2]
Yes
SSR.ORER flag = 1,
SSR.PER flag = 1, or
SSR.FER flag = 1?
[3]
No
Error processing
(Continued to next page)
No
[4] Read the receive data in RDR once in the SCIn_RXI interrupt
handling routine.
[5] Serial reception continuation procedure:
To continue serial reception, before the stop bit of a frame is
received, read data from RDR in the SCIn_RXI interrupt processing
routine. The RDR data can also be read by activating the DMAC or
DTC.
SCIn_RXI interrupt?
Yes*1
No
Note 1.
Note 2.
Read receive data in RDR*2
[4]
All data received?
[5]
Do not set RE to 0 before reading RDR.
The RDR register becomes the RDRHL register when 9-bit
data length is selected.
Yes
Set bits RIE and RE in SCR to 0
End
Figure 32.17
Example flow of serial reception in asynchronous mode with non-FIFO selected (1)
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32. Serial Communications Interface (SCI)
[3]
Error processing
No
SSR.ORER flag = 1
Yes
Overrun error processing
No
[6]
[ 6 ] Processing in response to an overrun error:
Read the RDR. In combination with step [ 7 ], this
makes the correct reception of the next frame possible.
SSR.FER flag = 1?
Yes
Break?
Yes
No
Framing error processing
No
Set RE bit in SCR to 0
SSR.PER flag = 1?
Yes
Parity error processing
Set the SSR.ORER, PER,
and FER flags to 0
[7]
[ 7 ] Clearing the error flag:
Write 0 to the error flag.
Read the SSR.ORER, PER, and FER flags
[8]
[ 8 ] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
End
Note:
Figure 32.18
The RDR register becomes the RDRHL register when 9-bit data length is selected.
Example flow of serial reception in asynchronous mode with non-FIFO selected (2)
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32. Serial Communications Interface (SCI)
FIFO selected
Figure 32.19 shows the example of a data format that is written to FRDRH and FRDRL in asynchronous mode.
In asynchronous mode, 0 is written to the MPB flag in the FRDRH register. Data that corresponds to the data length is
written to FRDRH and FRDRL. Unused bits are written as 0. Read in the order from FRDRH to FRDRL. If software
reads FRDRL, the SCI updates FER, PER, and receive data (RDAT[8:0]) in the FRDRL register with the next data. The
flags RDF, ORER, and DR in the FRDRH register always reflect the associated flags in the SSR_FIFO register.
Data
Length
Receive data in FRDRH, FRDRL
Register
Setting
FRDRHL
FRDRH
SCMR.
CHR1
SMR.
CHR
b7
b6
7 bits
1
0
—
RDF
8 bits
1
1
—
0
Don’t
care
—
9 bits
Note:
b5
FRDRL
b4
b3
b2
b1
b0
ORER
FER
PER
DR
0
0
RDF
ORER
FER
PER
DR
0
0
RDF
ORER
FER
PER
DR
0
b7
b6
0
b5
b4
b3
b2
b1
b0
7-bit receive data
8-bit receive data
9-bit receive data
0 is always read for MPB flag (FRDRH[1]).
When data length is 7 bits, 0 is always read for FRDRH[0] and FRDRL[7].
When data length is 8 bits, 0 is always read for FRDRH[0].
FRDRH[7] bit is read as an indefinite value.
Figure 32.19
Data format stored in FRDRH and FRDRL with FIFO selected
In serial data reception, the SCI operates as follows:
1. When the value of the SCR.RE bit becomes 1, the output signal on the CTSn_RTSn pin goes low.
2. When the SCI monitors the communications line and detects a start bit, it performs internal synchronization, stores
receive data in the RSR register, and checks the parity bit and stop bit.
3. If an overrun error occurs, the SSR_FIFO.ORER flag is set to 1. If the SCR.RIE bit in SCR is 1, an SCIn_ERI
interrupt request is generated. Receive data is not transferred to the FRDRL*1 register.
4. If a parity error is detected, the PER flag and receive data are transferred to the FRDRL*1 register. If the RIE bit is
set to 1, an SCIn_ERI interrupt request is generated.
5. If a framing error is detected, the FER flag and receive data are transferred to the FRDRL*1 register. If the RIE bit is
set to 1, an SCIn_ERI interrupt request is generated.
6. After a framing error is detected and when SCI detects that the continuous receive data is for one frame, reception
stops.
7. When the amount of data stored in the FRDRL register falls below the specified receive triggering number, and the
next data is not received after 15 ETUs from the last stop bit in asynchronous mode, the SSR_FIFO.DR bit is set to
1. When the RIE bit is 1 and the FCR.DRES bit is 0, the SCI generates an SCIn_RXI interrupt request. When the
FCR.DRES bit is 1, SCI generates an SCIn_ERI interrupt request.
8. When reception finishes successfully, receive data is transferred to the FRDRL*1 register. The RDF bit is set to 1
when the amount of receive data written to FRDRHL is equal to or greater than the specified receive triggering
number. When the SCR.RIE bit in SCR is 1, an SCIn_RXI interrupt request is generated. Continuous reception is
enabled by reading the receive data transferred to the FRDRL*2 register in the SCIn_RXI interrupt handling routine,
before an overrun error occurs. If the received data that is transferred to FRDRL*3 is less than the RTS trigger
number, the CTSn_RTSn pin outputs low.
Note 1. Only read data in the FRDRH and FRDRL registers when 9-bit data length is selected.
Note 2. Read data in the order from FRDRH to FRDRL when 9-bit data length is selected.
Note 3. The SCI only checks for an update to the FRDRL register and not to the FRDRH register when 9-bit data length
is selected.
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32. Serial Communications Interface (SCI)
[1]
Initialization
[ 1 ] SCI initialization:
Set data reception.
Start data reception
*1
*1
Read ORER , PER, FER, And DR
flags in SSR_FIFO
SSR_FIFO.ORER*1 flag = 1,
SSR_FIFO.PER flag = 1,
SSR_FIFO.FER flag = 1, or
DR*1flag = 1 ?
[2]
Yes
[3]
Error processing
No
No
(Continued to next page)
SCIn_RXI interrupt?
Yes
No
Read receive data in FRDRHL
[4]
All data received?
[5]
[ 4 ] Read the receive data in FRDRHL in the
SCIn_RXI interrupt handling routine. The receive
data stored in the FRDRHL register is read until
the amount of stored data is below the
FCR.RTRG value. Confirm the amount of
reception data in the FIFO by reading FDR.R.
[ 5 ] Serial reception continuation procedure:
To continue serial reception, before an overrun
error occurs, read data from FRDRHL in the
SCIn_RXI interrupt handling routine and clear
RDF flag and DR flag to 0.
The FRDRHL data can also be read by activating
the DMA or DTC. The RDF flag is cleared
automatically in this case. Therefore, do not write
to the RDF flag.
Yes
Set bits RIE and RE in SCR to 0
[ 2 ] [ 3 ] Receive error processing and break
detection:
If a receive error occurs, an SCIn_ERI interrupt
is generated. A break can be detected by
reading the SPTR.RXDMON bit. An error is
identified by reading the ORER*1, PER, DR*1,
and FER flags in SSR_FIFO. After performing
the appropriate error processing, be sure to set
the ORER*1 flag to 0. Reception cannot be
resumed if ORER*1 flag is set to 1. The reception
operation is continuous, even if FER = 1 or
PER = 1 or DR*1 = 1.
Note 1.
Can be read in the FRDRHL.ORER and DR flags.
End
Figure 32.20
Example flow of serial reception in asynchronous mode with FIFO selected (1)
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32. Serial Communications Interface (SCI)
[3]
Error processing
No
SSR_FIFO.ORER flag = 1?
Yes
Overrun error processing
No
[6]
[ 6 ] Processing in response to an overrun error:
The FRDRHL register is read and a space is made in the
FRDRHL register.
SSR_FIFO.FER flag = 1?
Yes
Yes
Break?
No
Framing error processing
Break flow
[7]
[8]
No
SSR_FIFO.PER flag = 1?
[ 7 ] When a break is detected, transfer of the
receive data to FRDRHL stops after the
detection. When the break ends at
SEMR.RXDESEL = 0, the last stored data of
FRDRHL is break error frame (All 0 data).
Yes
Parity error processing
[8]
No
[ 8 ] Framing error processing / parity error processing:
All error occurrence data stored in the FRDRHL
register is read. (Or write 1 to the FCR.RFRST bit
and empty the FRDRHL register.)
[ 9 ] The reading of the receive data (when FCR.DRES is 1):
All receive data stored in the FRDRHL register is read.
SSR_FIFO.DR flag = 1?
Yes
Reception data reading in the
FRDRHL register
[9]
Set the SSR_FIFO.ORER, PER, DR, and
FER flags to 0
[10]
[10] Clearing the error flag:
Write 0 to the error flag.
Read the SSR_FIFO.ORER, PER, DR, and
FER flags
[11]
[11] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
End
Figure 32.21
Example flow of serial reception in asynchronous mode with FIFO selected (2)
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32.4
32. Serial Communications Interface (SCI)
Multi-Processor Communication Function
The multi-processor communication function enables the SCI to transmit and receive data by sharing a communication
line between multiple processors, using asynchronous serial communication in which the multi-processor bit is added. In
multi-processor communication, a unique ID code is allocated to each receiving station. Serial communication cycles
consist of an ID transmission cycle to specify the receiving station and a data transmission cycle to transmit data to the
specified receiving station.
The multi-processor bit is used to distinguish between the ID transmission cycle and the data transmission cycle:
When the multi-processor bit is set to 1, the transmission cycle is the ID transmission cycle
When the multi-processor bit is set to 0, the transmission cycle is the data transmission cycle.
Figure 32.22 shows an example of communication between processors using a multi-processor format. First, a
transmitting station transmits communication data in which the multi-processor bit set to 1 is added to the ID code of the
receiving station. Next, the transmitting station transmits communication data in which the multi-processor bit set to 0 is
added to the transmit data. After receiving communication data with the multi-processor bit set to 1, the receiving station
compares the received ID with the ID of the receiving station itself. If the two match, the receiving station receives
communication data that is subsequently transmitted. If the received ID does not match with the ID of the receiving
station, the receiving station skips the communication data until it receives data in which the multi-processor bit is set to
1.
(1)
Non-FIFO selected
To support this function, SCI provides the SCR.MPIE bit. When the MPIE bit is set to 1, the following operations are
disabled until the reception of data in which the multi-processor bit is set to 1:
Transfer of receive data from the RSR register to the RDR register (the RDRHL register when 9-bit data length is
selected)
Detection of a receive error
Setting of the respective RDRF, ORER, and FER status flags in the SSR register.
When the SCI receives a character in which the multi-processor bit is set to 1, the SSR.MPBT bit is set to 1 and the
SCR.MPIE bit is automatically cleared, returning the SCI to non-multiprocessor reception operation. If the SCR.RIE bit
is set to 1, an SCIn_RXI interrupt is generated.
When the multi-processor format is specified, the parity bit function is disabled. Apart from this, there is no difference
from the operation in non-multiprocessor asynchronous mode. The clock used for multi-processor communication is the
same as the clock used in non-multiprocessor asynchronous mode.
Transmitting
station
Communication line
Receiving
station A
(ID = 01)
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 02)
(ID = 03)
(ID = 04)
(MPB = 1)
Serial data
AAh
01h
(MPB = 1)
ID transmission cycle =
specification of a receiving station
(MPB = 0)
Data transmission cycle = data
transmission to the receiving
station specified by ID
MPB: Multi-processor bit
Figure 32.22
Example of communication using multi-processor format with transmission of data AAh to
receiving station A
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32. Serial Communications Interface (SCI)
FIFO selected
For data transmission, software must write data to FTDRHL.MPBT that corresponds to transmit data in FTDRHL.TDAT.
For data reception, the multi-processor bit that is part of the receive data is written to FRDRHL.MPB, and receive data is
written to FRDRL.
When the MPIE bit is set to 1, the following operations are disabled until reception of data in which the multi-processor
bit is set to 1:
Transfer of receive data from the RSR register to the FRDRHL register
Detection of a receive error
Break
Setting of the respective RDF, ORER, and FER status flags in the SSR_FIFO register.
When SCI receives an 8-bit character in which the multi-processor bit is set to 1, the FRDRHL.MPB bit is set to 1 and
receive data is written to FRDRHL.RDAT. The SCR.MPIE bit is automatically cleared, returning the SCI to nonmultiprocessor reception operation. If the SCR.RIE bit is set to 1, an SCIn_RXI interrupt is generated.
When the multi-processor format is specified, the parity bit function is disabled. Apart from this, there is no difference
from operation in non-multiprocessor asynchronous mode with non-FIFO selected.
32.4.1
(1)
Multi-Processor Serial Data Transmission
Non-FIFO selected
Figure 32.23 shows an example flow of multi-processor data transmission. In the ID transmission cycle, the ID must be
transmitted with the SSR.MPBT bit set to 1. In the data transmission cycle, the data must be transmitted with the MPBT
bit set to 0. The rest of the operations are the same as operations in asynchronous mode.
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32. Serial Communications Interface (SCI)
Initialization
[1]
Start data transmission
SCIn_TXI interrupt?
[1]
SCI initialization:
Set data transmission.
After the SCR.TE bit is set to 1, 1 is output for a frame, and
transmission is enabled.
[2]
SCIn_TXI interrupt request:
When transmit data is transferred from TDR to TSR, a
transmit data empty interrupt (SCIn_TXI) request is
generated.
Set the MPBT bit in SSR to 0 or 1, and write transmit data to
TDR in the SCIn_TXI interrupt processing routine.
[3]
Serial transmission continuation procedure :
To continue serial transmission, write transmit data to TDR
once using an SCIn_TXI interrupt request.
Transmit data can also be written to TDR by activating the
DMAC or DTC.
When SCIn_TEI interrupt requests are in use , set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last of
the data to be transmitted is written to the TDR.
[4]
Break output at the end of serial transmission :
To output a break in serial transmission , after setting the
output state (low level output ) of the TXDn pin by
SPTR.SPB2IO and SPTR.SPB2DT bits, set the SCR.TE bit
to 0.
No
[2]
Yes
Set MPBT bit in SSR
Write transmit data to TDR
All transmit data
written to TDR register?
No
[3]
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt?
Yes
Break output?
No
[4]
Yes
Set TXD port functions
Set bits SCR.TE, TIE, and TEIE to 0
End
Figure 32.23
(2)
Example flow of multi-processor serial transmission with non-FIFO selected
FIFO selected
Figure 32.24 shows an example of the data format that is written to FTDRH and FTDRL in multi-processor mode. The
FTDRH.MPBT bit is set to 1. Data is set to FTDRH and FTDRL with the correct data length. Write 0 for unused bits.
Write in the order from FTDRH to FTDRL.
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Data
Length
32. Serial Communications Interface (SCI)
Transmit data in FTDRH, FTDRL
Register
Setting
FTDRHL
SCMR. SMR.
CHR1 CHR
FTDRL
b7
b6
b5
b4
b3
b2
b1
b0
b7
0
—
—
—
—
—
—
MPBT
—
—
1
1
—
—
—
—
—
—
MPBT
—
0
Don’t
care
—
MPBT
7 bits
1
8 bits
9 bits
FTDRH
—
—
—
—
—
b6
b5
b4
b3
b2
b1
b0
7-bit transmit data
8-bit transmit data
9-bit transmit data
—: Invalid. The write value should be 0.
Figure 32.24
Data format written to FTDRH and FTDRL in multi-processor mode with FIFO selected
Figure 32.25 shows an example flow of multi-processor data transmission with FIFO selected. In the ID transmission
cycle, the ID must be transmitted with the FTDRH.MPBT bit set to 1. In the data transmission cycle, data must be
transmitted with the MPBT bit set to 0. Rest of the operations are the same as operations in asynchronous mode with
non-FIFO selected.
Initialization
[1]
Start data transmission
SCIn_TXI interrupt
[1]
SCI initialization:
Set data transmission.
After the SCR.TE bit is set to 1, 1 is output for a frame, and
transmission is enabled.
[2]
Transmit data write to FTDRHL by an SCIn_TXI interrupt
request:
When transmit data is transferred from FTDRHL to TSR ,
when the quantity of receive data written in FTDRHL is equal
to or less than the specified transmit triggering number,
a transmit data FIFO empty interrupt (SCIn_TXI) request is
generated.
[3]
Serial transmission continuation procedure :
To continue serial transmission, write transmit data and MPBT
to FTDRHL once using an SCIn_TXI interrupt request.
Transmit data can also be written to FTDRHL by activating the
DTC.
When SCIn_TEI interrupt requests are in use , set the SCR.TIE
bit to 0 and the SCR.TEIE bit to 1 after the last of the data to
be transmitted is written to the FTDRHL.
[4]
Break output at the end of serial transmission :
To output a break in serial transmission , after setting the
output state (LOW level output) of TXDn pin by
SPTR.SPB2IO and SPTR.SPB2DT bits, set the SCR.TE bit to
0.
No
[2]
Yes
Write transmit data and MPBT
to FTDRHL
All transmit data
written to FTDRHL register?
[3]
No
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt
Yes
Break output
No
[4]
Yes
Set TXD port functions
Set bits SCR.TE, TIE, and TEIE to 0
End
Figure 32.25
Example flow of serial transmission in multi-processor mode with FIFO selected
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32.4.2
(1)
32. Serial Communications Interface (SCI)
Multi-Processor Serial Data Reception
Non-FIFO selected
Figure 32.27 and Figure 32.28 are example flows of multi-processor data reception. When the SCR.MPIE bit is set to 1,
reading communication data is skipped until the reception of communication data in which the multi-processor bit is set
to 1. When communication data in which the multi-processor bit is set to 1 is received, the received data is transferred to
the RDR register, or the RDRHL register when 9-bit data length is selected, and the SCIn_RXI interrupt request is
generated. The rest of the operations are the same as in asynchronous mode.
Figure 32.26 shows an example operation for data reception.
Data (ID1)
1
Data (Data1)
Start bit
0
MPB Stop bit Start bit
D0
D1
D7
1
1
0
MPB Stop bit
D0
D1
D7
0
1
1
Idle state
(mark state)
MPIE
SCIn_RXI interrupt flag
(IRn In ICU*1)
RDR value
ID1
MPIE = 0
SCIn_RXI interrupt
request (multi-processor
interrupt) generated
RDR data read in
SCIn_RXI interrupt
handling routine
MPIE bit set to 1 again
when the received ID
does not match the ID of
the receiving station itself
SCIn_RXI interrupt
request not generated.
RDR retains the state.
(a) When the received ID does not match the ID of the receiving station itself
Data (ID2)
1
Data (Data2)
Start bit
0
MPB Stop bit Start bit
D0
D1
D7
1
1
0
MPB Stop bit
D0
D1
D7
0
1
1
Idle state
(mark state)
MPIE
SCIn_RXI interrupt flag
(IELSRn.IR*1)
ID1
RDR value
MPIE = 0
ID2
SCIn_RXI interrupt
request (multi-processor
interrupt) generated
RDR data read in
SCIn_RXI interrupt
handling routine
Since the received ID matches
the ID of the receiving station
itself, reception continued and
data received in SCIn_RXI
interrupt handling routine
Data2
MPIE bit set to 1 again
(b) When the received ID matches the ID of the receiving station itself
Note 1.
Figure 32.26
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI reception with 8-bit data, multi-processor bit, and 1 stop bit
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32. Serial Communications Interface (SCI)
In itialization
[ 1 ] S C I initialization:
S et data reception.
[1 ]
[ 2 ] ID reception cycle:
S et S C R .M P IE bit to 1 and w ait for ID
re ception.
S tart data reception
S et M P IE bit in S C R to 1
[2 ]
R ead O R E R and FE R flags in S S R
FE R flag = 1 or O R E R flag = 1
Y es
No
No
S C In_R X I interrupt?
[3 ]
Y es
R ead receive data in R D R
No
ID of receiving station itself?
Y es
R ead O R E R and F E R flags in S S R
FE R flag = 1 or O R E R flag = 1
Y es
[ 3 ] S C I status confirm atIon and reception
and com parison of ID:
R ead data in R D R *1 at the first S C In_R X I
interrupt and com pare it w ith the ID of
the receiving statIon itself. If the ID does
not m atch the ID of the receiving station
itself, set the M P IE bit to 1 again, and
w ait for another S C In_R X I interrupt
re quest.
[ 4 ] D ata reception at an S C In_R X I interrupt:
R ead data in R D R *1 once in the
S C In_R X I interrupt routine.
[ 5 ] R eceive error processing and break
detection:
If a receive error occurs, an error is
identified by reading O R E R and FE R
flags in S S R . A fter perform ing the
appropriate error processing, be sure to
set O R E R a nd FE R flags to 0. R eception
cannot be resum ed if any of these flags
is set to 1. In the case of a fram ing error,
a break can be detected by reading
S P T R .R X D M O N bit.
No
No
S C In _R X I interrupt
[4 ]
Y es
R ead receive data in R D R
No
A ll data received?
[5 ]
E rror processing
Y es
S et R E and R IE bits in S C R to 0.
(C ontinued to next page)
E nd
Note 1.
Figure 32.27
The RDR register becomes the RDRHL register when 9-bit data length is selected.
Example flow of multi-processor serial reception with non-FIFO selected (1)
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32. Serial Communications Interface (SCI)
[5]
Error processing
No
SSR .O R ER flag = 1?
Yes
O verrun error processing
No
[6 ]
[ 6 ] Processing in response to an overrun error:
R ead the R D R *1 . In com bination w ith step [ 7 ],
this m akes correct reception of the next fram e
possible.
SSR .FER flag = 1?
Yes
Break?
Yes
No
Fram ing error processing
Set R E bit in SC R to 0
Set the SSR .O R ER , PER ,
and FER flags to 0.
[7 ]
[ 7 ] C learing the error flag:
W rite 0 to the error flag.
R ead the SSR.O R ER , PER , and FER flags.
[8 ]
[ 8 ] C onfirm ing that the error flag is cleared:
R ead the error flag to confirm that its value is 0.
End
Note 1.
Figure 32.28
The RDR register becomes the RDRHL register when 9-bit data length is selected.
Example flow of multi-processor serial reception with non-FIFO selected (2)
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32. Serial Communications Interface (SCI)
FIFO selected
Figure 32.29 shows an example of a data format that is written to FRDRH and FRDRL in multi-processor mode.
In multi-processor mode, the MPB value that is a part of the receive data is written to the FRDRH.MPB flag. A value of
0 is written to the FRDRH.PER flag. Data is written to FRDRH and FRDRL with the correct data length. Unused bits are
written with 0.
Read in the order from FRDRH to FRDRL. When software reads the FRDRL register, the SCI updates FER, MPB, and
receive data (RDAT[8:0]) in FRDRL with the next data. The RDF, ORER and DR flags in the FRDRH register always
reflect the associated flags in the SSR_FIFO register.
Data
Length
Receive data in FRDRH, FRDRL
Register
Setting
FRDRHL
FRDRH
FRDRL
SCMR.
CHR1
SMR.
CHR
b7
b6
b5
b4
b3
b2
b1
7 bits
1
0
—
RDF
ORER
FER
0
DR
MPB
0
8 bits
1
1
—
RDF
ORER
FER
0
DR
MPB
0
0
Don’t
care
—
RDF
ORER
FER
0
DR
MPB
9 bits
Note:
b0
b7
0
b6
b5
b4
b3
b2
b1
b0
7-bit receive data
8-bit receive data
9-bit receive data
When data length is 7 bits, 0 is always read for FRDRH[0] and FRDRL[7]
When data length is 8 bits, 0 is always read for FRDRH[0]
FRDRH[7] bit is read as an indefinite value.
Figure 32.29
Data format stored in FRDRH and FRDRL in multi-processor mode with FIFO selected
Figure 32.30 shows an example flow of multi-processor data reception with FIFO selected.
When the SCR.MPIE is set to 1, reading communication data is skipped until the reception of communication data in
which the multi-processor bit is set to 1. When communication data in which the multi-processor bit is set to 1 is
received, the received data, MPB and the associated errors are transferred to the FRDRHL register. The SCR.MPIE bit is
automatically cleared and non-multiprocessor reception continues.
If a framing error occurs and the SSR_FIFO.FER flag is set to 1, the SCI continues data reception. The rest of the
operations are the same as operations in asynchronous mode with non-FIFO selected.
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32. Serial Communications Interface (SCI)
[ 1 ] SCI initialization:
Initialization
[ 2 ] ID reception cycle:
Set the SCR.MPIE bit to 1 and wait for ID reception.
Start data reception
No
Set data reception.
[1]
Set MPIE bit in SCR to 1.
[2]
SCIn_RXI interrupt?
[3]
[ 3 ] SCI status confirmation and reception and
comparison of ID:
SCI stores first data (MPB = 1) and subsequent
received data in FRDRHL.
RDF is set to 1 and an SCIn_RXI interrupt request is
generated when a quantity of receive data equal to or
greater than the specified receive triggering number
is stored in FRDRHL. When the quantity of data
stored in FRDRHL falls the specified receive
triggering number and received data is equal to or
Yes
Read receive data and flags in FRDRHL*1.
FER flag = 1 or ORER flag = 1
greater than 1, and no next data is received after the
elapse of 15 ETUs from the last stop bit,
SSR_FIFO.DR is set to 1. An SCIn_RXI interrupt
request is generated when FCR.DRES bit is 0.
Read data in FRDRHL at the first SCIn_RXI interrupt,
Yes
No
ID of receiving station itself?
No
Yes
and compare it with the ID of the receiving station
itself.
If the ID does not match the ID of the receiving
station itself, the SCI reads until the data with MPB =
1, and compares next ID. If it is no data with MPB = 1
Yes
Receive data is still
in FRDRHL ?
in FRDRHL, set the MPIE bit to 1 again and wait for
another SCIn_RXI interrupt request.
No
No
SCIn_RXI interrupt?
[4]
interrupt routine.
[ 5 ] Receive error processing and break detection:
If a receive error occurs, an error is identified by
reading the ORER and FER flags in SSR_FIFO. After
Yes
Read receive data and flags in FRDRHL*1.
FER flag = 1 or ORER flag = 1
[ 4 ] Data reception at an SCIn_RXI interrupt:
Read data in FRDRHL once in the SCIn_RXI
performing the appropriate error processing, be sure
to set the SSR_FIFO.ORER and SSR_FIFO.FER
flags to 0. Reception cannot be resumed if the
SSR_FIFO.ORER flag is set to 1. When framing error
is detected, a break can be detected by reading the
Yes
No
SPTR.RXDMON bit.
No
All data received?
[5]
Error processing
Yes
(Same as Figure 34.28)
Set RE and RIE bits in SCR to 0.
End
Note 1.
If FRDRH and FRDRL are used instead of FRDRHL, read in order from FRDRH to FRDRL.
Figure 32.30
32.5
Example flow of serial reception in multi-processor mode with FIFO selected
Operation in Clock Synchronous Mode
Figure 32.31 shows the data format for clock synchronous serial data communications.
In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in
transfer data consists of 8-bit data. In clock synchronous mode, no parity bit can be added.
In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data
reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is
output, the transmission line holds the last bit as output state. When the SPMR.CKPH bit is 1 in slave mode, the
transmission line holds the first bit output state.
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32. Serial Communications Interface (SCI)
Within the SCI, the transmitter and receiver are independent units, enabling full-duplex communications by using a
common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data
can be written during transmission or the previous receive data can be read during reception, enabling continuous data
transfer.
However, it is not possible to perform continuous transfer in the fastest bit rate setting (BRR[7:0] = 00h and
SMR.CKS[1:0] = 00b). Therefore, when the FIFO is selected, this setting (BRR[7:0] = 00h and SMR.CKS[1:0] = 00b) is
not available.
One unit of transfer data (character or frame)
1
Synchronization
clock
*1
*
LSB
Serial data
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Don't care
Bit 7
Don't care
Note 1. Holds a high level except during continuous transfer.
Figure 32.31
32.5.1
Data format in clock synchronous serial communications with LSB-first order
Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the
SCKn pin can be selected based on the SCR.CKE[1:0] setting.
When the SCI operates on an internal clock, the synchronization clock is output from the SCKn pin. 8 synchronization
clock pulses are output in the transfer of one character. When no transfer is performed, the clock is held high. However,
when only data reception is performed while the CTS function is disabled, the synchronization clock output starts when
the SCR.RE bit set to 1. The synchronization clock stops when it goes high*1 and an overrun error occurs, or the SCR.RE
bit is set to 0.
When only data reception occurs and the CTS function is enabled, the clock output does not start when the SCR.RE bit
set to 1 and the CTSn_RTSn pin input is high. The synchronization clock output starts when the SCR.RE bit is set to 1
and the CTSn_RTSn pin input is low. Following that, when the CTSn_RTSn pin input is high on completion of the frame
reception, the synchronization clock output stops when it goes high. If the CTSn_RTSn pin input continues to be low, the
synchronization clock stops when it goes high*1 and an overrun error occurs, or when the SCR.RE bit is set to 0.
Note 1. The signal is held high when SPMR.CKPH is 0 and SPMR.CKPOL is 0, or when SPMR.CKPH = 1 and
SPMR.CKPOL = 1.
It is held low when SPMR.CKPH is 0 and SPMR.CKPOL is 1, or when SPMR.CKPH is 1 and SPMR.CKPOL is 0.
32.5.2
CTS and RTS Functions
In the CTS function, the CTSn_RTSn pin input controls the start of data reception or transmission when the clock source
is the internal clock. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled,
setting the CTSn_RTSn pin low causes data reception or transmission to start.
Setting the CTSn_RTSn pin high while the data transmission or reception is in progress does not affect transmission or
reception of the current frame.
In the RTS function, the CTSn_RTSn pin output is used to request the start of data reception or transmission when the
clock source is an external synchronizing clock. The CTSn_RTSn output goes low when serial communication becomes
possible. Conditions for output of the CTSn_RTSn low and high are as follows:
[Conditions for low-level output]
(a)
Non-FIFO selected when all of the following conditions are satisfied
The value of the SCR.RE bit or the SCR.TE bit is 1
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32. Serial Communications Interface (SCI)
When serial communication is enabled
There is no received data available to be read when the SCR.RE bit is 1
Transmit data is written when the SCR.TE bit is 1 and SCR.CKE[1] bit is 0
Data is available for transmission in the TSR register when SCR.TE bit is 1 and SCR.CKE[1] bit is 1
The SSR.ORER flag is 0.
(b)
FIFO selected when all of the following conditions are satisfied
The value of the SCR.RE bit or the SCR.TE bit is 1
When serial communication is enabled
The amount of receive data written in FRDRHL is less than the specified CTSn_RTSn output triggering number
when SCR.RE = 1
Data that has not been transmitted is available in FTDRHL when the SCR.TE bit is 1 and the SCR.CKE[1] bit is 0
Data is available for transmission in the TSR register when the SCR.TE bit is 1 and the SCR.CKE[1] bit is 1
The SSR_FIFO.ORER flag is 0.
[Condition for high-level output]
(a)
Non-FIFO selected
The conditions for low-level output are not satisfied
When reception is terminated with SCR.RE = 0 without reading the RDR register after reception is complete, RTS
remains high. At this time, read the SCR register for dummy values after writing 0 to SCR.RE.
(b)
FIFO selected
The conditions for low-level output are not satisfied.
32.5.3
SCI Initialization in Clock Synchronous Mode
Before transmitting and receiving data, start by writing the initial value 00h to the SCR register, then continue through
the SCI initialization procedure in 32.5.2 CTS and RTS Functions. Anytime that the operating mode or transfer format is
to be changed, the SCR register must be initialized before the change can be made.
Note:
Note:
Setting the SCR.RE bit to 0 does not initialize the ORER, FER, RDRF, RDF, PER and DR flags in
SSR/SSR_FIFO or the RDR and the RDRHL registers. When the TE bit is set to 0, the TEND flag for the selected
FIFO buffer is not initialized.
Switching the value of the SCR.TE bit from 1 to 0 or 0 to 1 when the SCR.TIE bit is 1 generates an SCIn_TXI
interrupt request.
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32. Serial Communications Interface (SCI)
Start initialization
Set the SCR.TIE, RIE, TE, RE, and
TEIE bits to 0
Set the FCR.FM bit to 0
[1]
[ 1 ] Set the FCR.FM bit to 0.
Set the SCR.CKE[1:0] bits
[ 2]
[ 2 ] Set the clock selection in SCR.
Set the SIMR1.IICM bit to 0
Set the SPMR.CKPH and CKPOL bits
[3]
[ 3 ] Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits.
Step [3] can be skipped if the values have not been changed from the initial values.
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[ 4]
[ 4 ] Set data transmission/reception format in SMR, SCMR, and SEMR.
Set a value in BRR
[ 5]
[ 5 ] Write a value associated with the bit rate to BRR.
This step is not necessary if an external clock is used.
Set a value in MDDR
[ 6]
[ 6 ] Write the value obtained by correcting a bit rate error in MDDR. This step is not
required if the BRME bit in SEMR is set to 0 or an external clock is used.
Set the I/O port functions
[7]
[ 7 ] Make I/O port settings to enable input and output functions as required for TXDn,
RXDn, and SCKn pins.
Set the SCR.TE or RE bit to 1, and
set the SCR.TIE and RIE bits
[ 8]
[ 8 ] Set the SCR.TE or RE bit to 1. Also set the SCR.TIE and RIE bits.
Setting the TE and RE bits allows TXDn and RXDn to be used.
Initialization completion
Note:
In simultaneous transmit and receive operations, the TE and RE bits in SCR must both be set to 0 or set to 1
simultaneously.
Figure 32.32
Example flow of SCI initialization in clock synchronous mode with non-FIFO selected
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32. Serial Communications Interface (SCI)
Start initialization
Set the SCR.TIE, RIE, TE, RE, and
TEIE bits to 0
Set the FCR.FM, TFRST, and RFRST bits to 1
Set the FCR.TTRG[3:0], RTRG[3:0], and
RSTRG[3:0] bits
Set the SCR.CKE[1:0] bits
Set the SIMR1.IICM bit to 0
Set the SPMR.CKPH and CKPOL bits
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[ 1 ] [ 1 ] Set the FCR.FM, TFRST, and RFRST bits to 1. This enables FIFO mode and clears the
transmit/receive FIFOs. Set the trigger values in FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0].
[ 2 ] [ 2 ] Set the clock selection in SCR.
[ 3 ] [ 3 ] Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits.
Step [3] can be skipped if the values have not been changed from the initial values.
[ 4 ] [ 4 ] Set data transmission/reception format in SMR, SCMR, and SEMR.
Set a value in BRR
[ 5]
[ 5 ] Write the value associated with the bit rate to BRR.
This step is not necessary if an external clock is used.
Set a value in MDDR
[ 6]
[ 6 ] Write the value obtained by correcting a bit rate error in MDDR. This step is not necessary if the
BRME bit in SEMR is set to 0 or an external clock is used.
Set the FCR.TFRST and RFRST bits to 0
[ 7 ] [ 7 ] Set the FCR.TFRST and RFRST bits to 0.
Set the I/O port functions
[ 8]
[ 8 ] Make I/O port settings to enable input and output functions as required for TXDn, RXDn, and
SCKn pins.
Set the SCR.TE or RE bit to 1, and
set the SCR.TIE and RIE bits
[ 9]
[ 9 ] Set the SCR.TE or RE bit to 1. Also set the SCR.TIE and RIE bits.
Setting the TE and RE bits allows TXDn and RXDn to be used.
Initialization completion
Note:
In simultaneous transmit and receive operations, the TE and RE bits in SCR must both be set to 0 or set to 1
simultaneously.
Figure 32.33
32.5.4
(1)
Example flow of SCI initialization in clock synchronous mode with FIFO selected
Serial Data Transmission in Clock Synchronous Mode
Non-FIFO selected
Figure 32.34, Figure 32.35, and Figure 32.36 show examples of serial transmission in clock synchronous mode.
In serial data transmission, the SCI operates as follows:
1. The SCI transfers data from the TDR register to the TSR register when data is written to TDR in the SCIn_TXI
interrupt handling routine. The SCIn_TXI interrupt request at the beginning of transmission is generated when the
TE bit is set to 1, but only after the TIE bit in the SCR is also set to 1, or SCR.TE and SCR.TIE are both set to 1
simultaneously using a single instruction.
2. After transferring data from TDR to TSR, SCI starts transmission. When the SCR.TIE bit is set to 1, an SCIn_TXI
interrupt request is generated. Continuous transmission is enabled by writing the next transmit data to TDR in the
SCIn_TXI interrupt handling routine before the transmission of the current transmit data finishes. When SCIn_TEI
interrupt requests are in use, set the SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last of the data to be
transmitted is written to the TDR register from the handling routine for SCIn_TXI requests.
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32. Serial Communications Interface (SCI)
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is
specified and in synchronization with the input clock, when the use of an external clock is specified. Output of the
clock signal is suspended until the input CTS signal is low when the SPMR.CTSE bit is 1.
4. The SCI checks for updates to the TDR register on the output of the last bit.
5. When the TDR register is updated, the next transmit data is transferred from TDR to TSR, and serial transmission of
the next frame starts.
6. If TDR is not updated, the SSR.TEND flag is set to 1. The TXDn pin retains the output state of the last bit. If the
SCR.TEIE bit is 1, an SCIn_TEI interrupt request is generated and the SCKn pin is held high.
Figure 32.34, Figure 32.35, and Figure 32.36 show examples of serial data transmission.
Transmission does not start while a receive error flag (ORER, FER, or PER in SSR) is set to 1. Always set the receive
error flags to 0 before starting transmission.
Note:
Setting the SCR.RE bit to 0 does not clear the receive error flags.
Synchronization clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
Bit 0
SCR.TE bit
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Data written to TDR in
SCIn_TXI interrupt handling
routine
SCIn_TXI
interrupt
request generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
1 frame
Note 1.
Figure 32.34
SCIn_TXI
interrupt
request
generated
SCIn_TXI interrupt
request generated
Data written to TDR in
SCIn_TXI interrupt handling
routine
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of serial data transmission in clock synchronous mode when the CTS function is not
used at the beginning of transmission
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32. Serial Communications Interface (SCI)
CTSn_RTSn pin
Synchronization clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
SCR.TE bit
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
SCIn_TXI interrupt
request generated
SCIn_TXI interrupt
Request generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
Data written to TDR in
SCIn_TXI interrupt
handling routine
Data written to TDR in
SCIn_TXI interrupt
handling routine
1 frame
Note 1.
Figure 32.35
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example of serial data transmission in clock synchronous mode when the CTS function is used
at the beginning of transmission
Synchronization
clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
(TIE = 1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
(TIE = 0)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
1 frame
Note 1.
Figure 32.36
SCIn_TXI
interrupt
request
generated
Data written to TDR in
SCIn_TXI interrupt handling
routine
(Set the TIE bit to 0 and the
TEIE bit to 1 after writing the
last data)
SCIn_TEI
interrupt request
generated
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of serial data transmission in clock synchronous mode from the middle of transmission
until transmission completion
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32. Serial Communications Interface (SCI)
[1]
Initialization
Start transmission
SCIn_TXI interrupt?
No
[2]
Yes
Write transmit data to TDR
All data transmitted?
No
[3]
Yes
[1] SCI initialization:
Set data transmission.
[2] Write transmit data to TDR by an SCIn_TXI interrupt request:
When transmit data is transferred from TDR to TSR, a transmit data
empty interrupt (SCIn_TXI) request is generated.
Transmit data is written to TDR once from the handling routine for
SCIn_TXI requests.
[3] Serial transmission continuation procedure:
To continue serial transmission, write transmit data to TDR on
accepting a transmit data empty interrupt (SCIn_TXI) request.
Transmit data can also be written to TDR by activating the DMAC or
DTC by the SCIn_TXI interrupt request.
When SCIn_TEI interrupt requests are in use, set the SCR.TIE bit to
0 and the SCR.TEIE bit to 1 after the last of the data to be
transmitted is written to TDR.
Set the TIE bit in SCR to 0, and
set the TEIE bit in SCR to 1
SCIn_TEI Interrupt?
No
Yes
Set bits TIE, TE, and TEIE in SCR to 0
End
Note:
When the external clock is in use (the value of the SCR.CKE[1:0] bits is 10b or 11b), the rising edge on the SCK pin for
the last bit sets the SSR.TEND flag to 1. Setting the SCR.TE bit to 0 immediately after this might lead to insufficient
received-data hold time on the receiver side.
Figure 32.37
(2)
Example flow of serial transmission in clock synchronous mode with non-FIFO selected
FIFO selected
Figure 32.38 shows an example of serial transmission in clock synchronous mode with FIFO selected.
In serial data transmission, the SCI operates as follows:
1. The SCI transfers data from the FTDRL*1 register to the TSR register when data is written to FTDRL*1 in the
SCIn_TXI interrupt handling routine. The amount of data that can be written to FTDRL is 16 minus FDR.T[4:0]
bytes. The SCIn_TXI interrupt request at the beginning of transmission is generated when the SCR.TE bit is set to
1, but only after the SCR.TIE bit is also set to 1, or when SCR.TE and SCR.TIE are set to 1 simultaneously using a
single instruction.
2. After transferring data from FTDRL to TSR, the SCI starts transmission. When the amount of transmit data written
in FTDRL is equal to or less than the specified transmit triggering number, the SSR_FIFO.TDFE is set to 1. When
the SCR.TIE bit is set to 1, an SCIn_TXI interrupt request is generated. Continuous transmission is enabled by
writing the next transmit data to FTDRL in the SCIn_TXI interrupt handling routine before transmission of the
current transmit data has finished. When SCIn_TEI interrupt requests are in use, set the SCR.TIE bit to 0 and the
SCR.TEIE bit to 1 after the last of the data to be transmitted is written to the FTDRL from the handling routine for
SCIn_TXI requests.
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is
specified and in synchronization with the input clock when the use of an external clock is specified. Output of the
clock signal is suspended until the input CTS signal is low, when the SPMR.CTSE bit is 1.
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32. Serial Communications Interface (SCI)
4. The SCI checks whether non-transmitted data remains in FTDRL on output of the stop bit.
5. When FTDRL is updated, the next transmit data is transferred from FTDRL to TSR and serial transmission of the
next frame starts.
6. If FTDRL is not updated, the SSR_FIFO.TEND flag is set to 1. The TXDn pin keeps the output state of the last bit.
If the SCR.TEIE bit is 1, an SCIn_TEI interrupt request is generated and the SCKn pin is held high.
Note 1. In clock synchronous mode, FTDRH is not used.
Initialization
[1]
Start data transmission
SCIn_TXI interrupt?
No
[2] Transmit data write to FTDRL by an SCIn_TXI interrupt request:
When transmit data is transferred from FTDRL to TSR, and when the
amount of transmit data written in FTDRL is equal to or less than the
specified transmit triggering number, a transmit data FIFO empty
[ 3 ] interrupt (SCIn_TXI) request is generated. Write transmit data to
FTDRL once in the SCIn_TXI interrupt handling routine.
[2]
Yes
Write transmit data to FTDRL
All transmit data
written to FTDRL register?
[1] SCI initialization:
Set data transmission.
After the SCR.TE bit is set to 1, 1 is output for a frame, and
transmission is enabled.
No
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt?
Yes
[3] Serial transmission continuation procedure:
To continue serial transmission, write the next transmit data to FTDRL
in the SCIn_TXI interrupt handling routine and clear the
SSR_FIFO.TDFE flag to 0 before transmission of the current transmit
data has finished.
Transmit data can also be written to FTDRL by activating the DMAC or
DTC. The TDFE flag is cleared automatically in this case. Do not write
to the TDFE flag.
When SCIn_TEI interrupt requests are in use, set the SCR.TIE bit to 0
and the SCR.TEIE bit to 1 after the last of the data to be transmitted is
written to the FTDRL.
Set bits SCR.TE, TIE, and TEIE to 0
End
Note:
When the external clock is in use (the value of the SCR.CKE[1:0] bits is 10b or 11b), the rising edge on the SCK pin for
the last bit sets the SSR_FIFO.TEND flag to 1. Setting the SCR.TE bit to 0 immediately after this may lead to
insufficient hold time for receive data on the receiver side.
Figure 32.38
32.5.5
(1)
Example flow of serial transmission in clock synchronous mode with FIFO selected
Serial Data Reception in Clock Synchronous Mode
Non-FIFO selected
Figure 32.39 and Figure 32.40 show examples of SCI operation for serial reception in clock synchronous mode.
In serial data reception, the SCI operates as follows:
1. When the value of the SCR.RE bit becomes 1, the CTSn_RTSn pin goes low.
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32. Serial Communications Interface (SCI)
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
input or output, and stores the receive data in the RSR register.
3. If an overrun error occurs, the SSR.ORER bit is set to 1. If the SCR.RIE bit is 1, an SCIn_ERI interrupt request is
generated. Receive data is not transferred to the RDR register.
4. When reception completes successfully, receive data is transferred to the RDR register. If the SCR.RIE bit is 1, an
SCIn_RXI interrupt request is generated. Continuous reception is enabled by reading the received data transferred
to the RDR register in the SCIn_RXI interrupt handling routine before the reception of the next receive data
completes. Reading the received data from RDR causes the CTSn_RTSn pin to output low.
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.ORER flag
SCIn_RXI interrupt RDR data read in SCIn_RXI
request generated interrupt handling routine
SCIn_RXI interrupt
request generated
SCIn_ERI interrupt request
generated by overrun error
1 frame
Note 1.
Figure 32.39
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example operation of serial reception in clock synchronous mode (1) when the RTS function is
not used
Synchronization
clock
Serial data
Bit 7
Bit 6
Bit 0
Bit 7
Bit 0
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.ORER flag
SCIn_RXI interrupt
request generated
SCIn_RXI
interrupt request
generated
RDR data read in
SCIn_RXI interrupt
handling routine
SCIn_ERI interrupt request
generated by overrun error
CTSn_RTSn pin
1 frame
Note 1.
Figure 32.40
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example operation of serial reception in clock synchronous mode (2) when RTS function is used
Data transfer cannot resume while the receive error flag is 1. Therefore, clear the ORER, FER, and PER bits in the SSR
register to 0 before resuming data reception. Additionally, be sure to read the RDR register during overrun error
processing. When a data reception is forcibly terminated by setting the SCR.RE bit to 0 during operation, read the RDR
register because the received data that is not yet read might be left in the RDR register.
Figure 32.41 shows an example flow of serial data reception.
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32. Serial Communications Interface (SCI)
Initialization
[1]
Start data reception
[2]
Read ORER flag in SSR
SSR.ORER = 1
No
Yes
[2] [3] Receive error processing:
If a receive error occurs, read the ORER flag in SSR,
perform the relevant error processing, then set the
ORER flag to 0. Data reception cannot be resumed while
the ORER flag is 1.
[3]
Error processing
(Continued below)
No
[1] SCI initialization:
Make input port settings for pins to be used as RXDn
pins.
SCIn_RXI interrupt
[4] Read the receive data in RDR once in the receive
data full interrupt (SCIn_RXI) request handling routine.
[5] Serial reception continuation procedure:
To continue serial reception, before the MSB (bit [7]) of a
frame is received, finish reading the receive data in RDR.
The RDR data can also be read by activating the DMAC
or DTC by an SCIn_RXI interrupt request.
Yes
Read receive data in RDR
[4]
[6] Processing in response to an overrun error:
Read the RDR. In combination with step [7], this makes
the correct reception of the next frame possible.
[7] Clearing the error flag:
Write 0 to the error flag.
No
All data received?
[5]
[8] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
Yes
Set bits RIE and RE in SCR to 0
End
[3]
Error processing
Overrun error processing
[6]
Clear the SSR.ORER flag to 0
[7]
Read the SSR.ORER flag
[8]
End
Figure 32.41
(2)
Example flow of serial reception in clock synchronous mode with non-FIFO selected
FIFO selected
Figure 32.42 shows an example of serial reception in clock synchronous mode with FIFO selected.
In serial data reception, the SCI operates as follows:
1. When the value of the SCR.RE bit becomes 1, the CTSn_RTSn pin goes low.
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32. Serial Communications Interface (SCI)
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
input or output, and stores the receive data in the RSR register.
3. If an overrun error occurs, the SSR_FIFO.ORER bit is set to 1. If the SCR.RIE bit is 1, an SCIn_ERI interrupt
request is generated. Received data is not transferred to the FRDRL*1 register.
4. When data reception completes successfully, the receive data is transferred to the FRDRL*1 register. The RDF bit is
set to 1 when the amount of the receive data stored in FRDRL is equal to or greater than the specified receive
triggering number. If the SCR.RIE bit is 1, an SCIn_RXI interrupt request is generated. Continuous data reception is
enabled by reading the receive data transferred to FRDRL*2 in the SCIn_RXI interrupt handling routine before an
overrun error occurs. If the amount of received data that is transferred to FRDRL is less than the RTS trigger
number, the CTSn_RTSn pin goes low.
Note 1. In clock synchronous mode, FRDRH is not used.
Note 2. Read data in the order from FRDRH to FRDRL, when RDF and ORER are read with receive data.
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32. Serial Communications Interface (SCI)
Initialization
[1]
[1] SCI initialization:
Make input port-pin settings for pins to be used as RXDn
pins.
Start data reception
[2]
Read ORER*1 flag in SSR_FIFO
Yes
SSR_FIFO.ORER = 1?
No
[3]
Error processing
(Continued below)
No
SCIn_RXI interrupt?*2
Yes
Read receive data in FRDRL
No
All data received?
[4]
[5]
[2] [3] Receive error processing:
If a receive error occurs, read the ORER flag in
SSR_FIFO, perform the relevant error processing, then
set the SSR_FIFO.ORER flag to 0. Data reception
cannot be resumed while the ORER flag is 1.
[4] Receive data stored in FRDRL register is read until
the amount of stored data is less than the FCR.RTRG
value. Software can check readable data in FDR.R[4:0].
[5] Serial reception continuation procedure:
To continue serial reception, before overrun error occurs,
finish reading the receive data in FRDRL and clear the
SSR_FIFO.RDF flag to 0. The FRDRL data can also be
read by activating the DMAC or DTC by an SCIn_RXI
interrupt request. The RDF flag is cleared automatically
in this case. Do not write to the RDF flag.
[6] Processing in response to an overrun error:
Read the FRDRL. In combination with step [7], this
makes the correct reception of the next frame possible.
[7] Clearing the error flag:
Write 0 to the error flag.
[8] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
Yes
Set bits RIE and RE in SCR to 0
End
[3]
Error processing
Overrun error processing
[6]
Clear the SSR_FIFO.ORER flag to 0
[7]
Read the SSR_FIFO.ORER flag
[8]
Note 1.
Note 2.
End
Figure 32.42
ORER can also be read from FRDRH.ORER.
However, to clear the ORER flag, write 0 to the
associated bit in the SSR_FIFO register.
All receive data is an integer multiple of the
FIFO triggering number.
Example flow of serial reception in clock synchronous mode with FIFO selected
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32.5.6
(1)
32. Serial Communications Interface (SCI)
Simultaneous Serial Data Transmission and Reception in Clock Synchronous
Mode
Non-FIFO selected
Figure 32.43 shows an example flow of simultaneous serial transmission and reception operations in clock synchronous
mode. After initializing the SCI, use the following procedure for simultaneous serial data transmission and reception
operations.
To switch from transmit mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the data transmission by verifying that the SSR.TEND flag is set to 1.
2. Initialize the SCR register, and then set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously with
a single instruction.
To switch from receive mode to simultaneous transmit and receive mode:
1. Check that SCI completes the data reception.
2. Set the RIE and RE bits to 0 in the SCR register, and then check that the receive error flag ORER in the SSR register
is 0.
3. Set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously using a single instruction.
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32. Serial Communications Interface (SCI)
[1]
Initialization
[1] SCI initialization:
The TXDn pin can act as the output pin for transmitted
data and the RXDn pin can act as the input pin for
received data at the same time.
Start data transmission/reception
No
SCIn_TXI interrupt?
[2] Transmit data write:
Write transmit data to TDR once in the SCIn_TXI interrupt
request handling routine.
Yes
[2]
Write transmit data to TDR
[3] Receive error processing:
If a receive error occurs, read the ORER flag in SSR,
perform the relevant error processing, then set the ORER
flag to 0. Data reception cannot be resumed while the
ORER flag is 1.
Read ORER flag in SSR
Yes
SSR.ORER = 1?
No
No
Error processing
SCIn_RXI interrupt?
Yes
No
[3]
Read receive data in RDR
[4]
All data received?
[5]
Yes
Clear TIE, RIE, TE, RE, and TEIE
bits in SCR to 0
[4] Reading receive data:
Read the receive data in RDR once in the SCIn_RXI
interrupt request handling routine.
[5] Serial transmission or reception continuation
procedure:
To continue serial transmission and reception, before the
MSB (bit [7]) of the current frame is received, finish
reading the receive data in RDR by the SCIn_RXI
interrupt. Also, before the MSB (bit [7]) of the current frame
is transmitted, write data to TDR by the SCIn_TXI
interrupt.
Transmit data can also be written to TDR by activating the
DMAC or DTC by a transmit data empty interrupt
(SCIn_TXI) request. Similarly, the RDR data can also be
read by activating the DMAC or DTC by a receive data full
interrupt (SCIn_RXI) request.
End
Note:
When switching from transmit or receive operation to simultaneous transmit and receive operations, first set the TIE,
RIE, TE, RE, and TEIE bits in SCR to 0, then set the TIE, RIE, TE, and RE bits to 1 simultaneously.
Figure 32.43
(2)
Example flow of simultaneous serial transmission and reception in clock synchronous mode with
non-FIFO selected
FIFO selected
Figure 32.44 shows an example flow of simultaneous serial transmit and receive operations in clock synchronous mode
with FIFO selected.
After initializing the SCI, use the following procedure for simultaneous serial data transmit and receive operations.
To switch from transmit mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the transmission by verifying that the SSR_FIFO.TEND flag is set to 1.
2. Initialize the SCR register, then set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously using a
single instruction.
To switch from receive mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the reception.
2. Set the RIE and RE bits to 0, then check that the receive error flag ORER in SSR_FIFO is 0.
3. Set the TIE, RIE, TE, and RE bits in SCR to 1 simultaneously using a single instruction.
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32. Serial Communications Interface (SCI)
[1] SCI initialization:
The TXDn pin can act as the output pin for transmitted data and the
RXDn pin can act as the input pin for received data at the same time.
[1]
Initialization
Start data transmission/reception
No
[2] Transmit data write:
Write transmit data to FTDRL in the SCIn_TXI Interrupt request
handling routine. The amount of transmit data that can be written is
16 minus the amount of stored transmit FIFO data.
SCIn_TXI interrupt
Yes
[3] Receive error processing:
If a receive error occurs, read the ORER flag in SSR_FIFO, perform
the relevant error processing, then set the ORER flag to 0. Data
reception cannot be resumed while the ORER flag is 1.
[2]
Write transmit data to FTDRL
Read ORER *1 flag in SSR_FIFO
Yes
SSR_FIFO.ORER = 1
No
No
SCIn_RXI interrupt
Error processing
*2
Yes
Read receive data in FRDRL
[4]
All data received?
[5]
No
[3]
Yes
Clear TIE, RIE, TE, RE, and TEIE
bits in SCR to 0
[4] Reading receive data:
The receive data stored in FRDRL register is read until the number of
stored data is less than the FCR.RTRG value. Software can check
readable data in FDR.R[4:0].
[5] Serial transmission or reception continuation procedure:
To continue serial reception, before overrun error occurs, finish
reading the receive data in FRDRL and clear the SSR_FIFO.RDF flag
to 0. To continue serial transmission, before transmission of the
current transmit data has finished, write the next transmit data to
FTDRL in the SCIn_TXI interrupt handling routine and clear the
SSR_FIFO.TDFE flag to 0.
Transmit data can also be written to FTDRL by activating the DMAC
or DTC by a transmit FIFO data empty interrupt (SCIn_TXI) request.
Similarly, the FRDRL data can also be read by activating the DMAC
or DTC by a receive FIFO data full interrupt (SCIn_RXI) request. The
RDF and TDFE flags are cleared automatically in this case. Do not
write to the RDF and TDFE flags.
Note 1.
Note 2.
End
Figure 32.44
32.6
ORER can also read from FRDRH.ORER. To clear the
ORER flag, write 0 to SSR_FIFO.ORER.
The total receive data amount must be an integral multiple
of the FIFO triggering number.
Example flow of simultaneous serial transmission and reception in clock synchronous mode with
FIFO selected
Operation in Smart Card Interface Mode
The SCI supports smart card (IC card) interfaces conforming to ISO/IEC 7816-3 (standard for Identification Cards), as
an extended function of the SCI.
Smart card interface mode can be selected using the appropriate register.
32.6.1
Example Connection
Figure 32.45 shows an example connection between a smart card (IC card) and the MCU. Because the MCU
communicates with an IC card using a single transmission line, interconnect the TXDn and RXDn pins and pull up the
data transmission line to VCC using a resistor, as shown in Figure 32.45.
Setting the SCR_SMCI.TE and SCR_SMCI.RE bits to 1 with an IC card disconnected, enables closed-loop transmission
or reception, allowing self-diagnosis. To supply an IC card with the clock pulses generated by the SCI, input the SCKn
pin output to the CLK pin of an IC card.
An output port of the MCU can be used to output a reset signal.
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32. Serial Communications Interface (SCI)
VCC
VCC
TXDn
I/O
Data line
RXDn
SCKn
CLK
Clock line
Port
RST
Reset line
IC card
Main unit of the device to
be connected
Figure 32.45
32.6.2
Example connection with a smart card (IC card)
Data Format (Except in Block Transfer Mode)
Figure 32.46 shows the data transfer formats in smart card interface mode:
One frame consists of 8-bit data and a parity bit in asynchronous mode
During transmission, a value of at least 2 ETUs (elementary time unit — the time required for transferring 1 bit) is
set as a guard time from the end of the parity bit until the start of the next frame
If a parity error is detected during reception, a low error signal is output for 1 ETU after a period of 10.5 ETUs
elapses from the start bit
If an error signal is sampled during transmission, the same data is automatically retransmitted after at least 2 ETUs.
In normal transmission/reception
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Output from the transmitting station
When a parity error occurs
Ds
D0
D1
D2
D3
D4
D5
DE
Output from the transmitting station
Ds:
D0 to D7:
Dp:
DE:
Figure 32.46
Start bit
Data bits
Parity bit
Error signal
Output from the
receiving station
Data formats in smart card interface mode
For communications with IC cards of the direct convention type and inverse convention type, follow the procedures in
this section.
(1)
Direct Convention Type
For the direct convention type, logic levels 1 and 0 indicate the Z and A states, respectively, and data is transferred with
LSB-first for the start character, as shown in Figure 32.47. Therefore, data in the start character in the figure is 3Bh.
When using the direct convention type, write 0 to both the SCMR.SDIR and SCMR.SINV bits. Write 0 to the
SMR_SMCI.PM bit to use even parity, which is prescribed by the smart card standard.
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
(Z) state
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Figure 32.47
Direct convention with SDIR in SCMR = 0, SINV in SCMR = 0, and PM in SMR_SMCI = 0
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(2)
32. Serial Communications Interface (SCI)
Inverse Convention Type
For the inverse convention type, logic levels 1 and 0 indicate the A and Z states, respectively, and data is transferred with
MSB-first for the start character, as shown in Figure 32.48. Therefore, data in the start character in the figure is 3Fh.
When using the inverse convention type, write 1 to both the SCMR.SDIR and SCMR.SINV bits. The parity bit is logic
level 0 to produce even parity, which is required by the smart card standard, and corresponds to the Z state. Because the
SINV bit of the MCU only inverts data bits D7 to D0, write 1 to the PM bit in SMR_SMCI to invert the parity bit for both
transmission and reception.
(Z)
A
Z
Z
A
A
A
A
A
A
Z
(Z) state
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
Figure 32.48
32.6.3
Inverse convention with SDIR in SCMR = 1, SINV in SCMR = 1, and PM in SMR_SMCI = 1
Block Transfer Mode
Block transfer mode differs from non-block transfer mode of the smart card interface mode as follows:
If a parity error is detected during reception, no error signal is output. Because the PER bit in SSR_SMCI is set by
error detection, clear the PER bit before receiving the parity bit of the next frame.
During transmission, at least 1 ETU is set as a guard time from the end of the parity bit until the start of the next
frame
Because the same data is not retransmitted, the TEND flag in SSR_SMCI is set to 11.5 ETUs after transmission
starts
In block transfer mode, the ERS flag in SSR_SMCI indicates the error signal status as in non-block transfer mode of
smart card interface mode, but the flag is read as 0 because no error signal is transferred.
32.6.4
Receive Data Sampling Timing and Reception Margin
Only the clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode.
In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit
rate set up in the SCMR.BCP2 and SMR_SMCI.BCP[1:0] bits.
For data reception, the SCI samples the falling edge of the start bit using the base clock to perform synchronization.
Receive data is sampled on the 16th, 32nd, 186th, 128th, 46th, 64th, 93rd, and 256th rising edges of the base clock so that
it can be latched at the middle of each bit as shown in Figure 32.49. The reception margin is determined by the following
formula:
M = (0.5 -
D - 0.5
1
) - (L - 0.5) F N
2N
(1 + F)
× 100 [%]
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Duty cycle of clock (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N = 372 in the specified formula, the reception margin is determined using the
following formula:
M = {0.5 - 1/(2 × 372)} × 100 [%] = 49.866%
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32. Serial Communications Interface (SCI)
372 clocks
372 clocks
186 clocks
0
186 clocks
185
371 0
185
371 0
Base clock
Receive data (RXDn)
Start bit
D0
D1
Synchronization sampling
timing
Data sampling timing
Figure 32.49
32.6.5
Receive data sampling timing in smart card interface mode when clock frequency is 372 times the
bit rate
Initialization of the SCI
Before transmitting and receiving data, write the initial value of 00h in the SCR_SMCI register and initialize the SCI
using the example flow shown in Figure 32.50.
Be sure to set the initial value in the TIE, RIE, TE, RE, and TEIE bits in the SCR_SMCI register before switching from
transmission to reception mode or from reception to transmission mode. When SCR_SMCI.RE is set to 0, the RDR
register is not initialized.
To change from reception mode to transmission mode, first check that the reception is complete, then initialize the SCI.
At the end of initialization, set SSR_SMCI.TE = 1 and SSR_SMCI.RE = 0. Reception completion can be verified by
reading the SCIn_RXI request, ORER, or PER flag in SSR_SMCI.
To change transmission mode to reception mode, first check that the transmission is complete, then initialize the SCI. At
the end of the initialization, set SSR_SMCI.TE = 0 and SSR_SMCI.RE = 1. Transmission completion can be verified by
reading the TEND flag in SSR_SMCI.
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32. Serial Communications Interface (SCI)
Start initialization
Set SCR_SMCI.TIE, RIE, TE, RE, TEIE,
and CKE[1:0] to 0
[1]
[1]
Stop the communication and initialize SKE[1:0].
Set SIMR1.IICM to 0
Set SCMR.SMIF to 1
[2]
[2]
Set to smart card interface mode.
Set SSR_SMCI.ORER, ERS ,PER to 0
[3]
[3]
Write to SSR_SMCI after reading SSR_SMCI.
Set SPMR.CKPH, CKPOL
[4]
[4]
Set the transmission or reception format in SPMR.
Set SMR_SMCI.GM, BLK, PM, BCP[1:0],
CKS[1:0], and set SMR_SMCI.PE to 1
[5]
[ 5 ] Set the operation mode and the transmission or reception
format in SMR_SMCI.
Set SCMR.BCP2, SDIR, SINV
[6]
Set SEMR.BRME and SEMR.RXDESEL to 0
[7]
Set a value in BRR
[8]
Set the I/O port functions
[9]
Set a value in SCR_SMCI.CKE[1:0]
[ 10 ]
Set SCR_SCMI.TE or RE to 1, and
set SCR_SMCI.TIE, RIE
[ 11 ]
[6]
Set the transmission or reception format in SCMR.
[7]
Set SEMR.BRME and SEMR.RXDESEL to 0.
[8]
Write the value for the bit rate in BRR.
[9]
Set the I/O port functions for TXDn, RXDn, and SCKn.
[ 10 ] Set SCR_SMCI.CKE[1:0]. Although the function depends on
SMR_SMCI.GM, when the CKE[0] bit is set to 1, the clock is output
from the SCKn pin.
[ 11 ] Set the TE or RE bit in SCR_SMCI to 1, and then set the TIE
and RIE bits in SCR_SMCI. Do not simultaneously set the TE and
RE bits to 1 if self-diagnosis is not used.
Initialization completed
Figure 32.50
Example flow of SCI initialization in smart card interface mode
Figure 32.51 shows a timing diagram when data transmission is performed by transitioning to smart card interface mode
according to the flow in Figure 32.50. Figure 32.51 shows when the GM bit in SMR_SMCI is set to 0. The timing in
Figure 32.51 shows when the port is connected as SCKn and TXDn, the pins are Hi-Z because CKE[0] bit in SCR_SMCI
is 0.
Start the clock output to the SCK pin by setting the CKE[0] bit in SCR_SMCI to 1, then start data transmission by
writing the transmit data after setting the TE bit in SCR_SMCI to 1. When the TE bit in SCR_SMCI changes from 0 to 1,
there is a preamble period for one frame before data transmission starts. In smart card interface mode, the TXDn pin is
Hi-Z when there is a preamble period. Pull-up or pull-down for the SCKn and TXDn pins is required outside the MCU.
In smart card interface mode, even when the TE and RE bits in SCR_SMCI are 0, the clock is continuously output if the
clock output setting is used.
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32. Serial Communications Interface (SCI)
Connect port
SCKn
Mode
SCKn starts when CKE[0] = 1
Hi-Z
Smart card interface mode
SCR.TE
Preamble period
TXDn
Ds
Hi-Z
TE = 1
Figure 32.51
32.6.6
Data transfer
D0
D1
Write transfer data
Example timing of data transmission in smart card interface mode
Serial Data Transmission (Except in Block Transfer Mode)
Serial data transmission in smart card interface mode (except in block transfer mode) is different from that in non-smart
card interface mode, in that an error signal is sampled and data can be retransmitted in smart card mode. Figure 32.52
shows the data retransfer operation during transmission.
In Figure 32.52:
[1] indicates that when an error signal from the receiver end is sampled after 1-frame data is transmitted, the
SSR_SMCI.ERS flag is set to 1. If the SCR_SMCI.RIE bit is 1, an SCIn_ERI interrupt request is generated. Clear
the ERS flag to 0 before the next parity bit is sampled.
[2] indicates that for a frame in which an error signal is received, the SSR_SMCI.TEND flag is not set. Data is
retransferred from TDR to TSR, allowing automatic data retransmission.
[3] indicates that if no error signal is returned from the receiver, the ERS flag is not set to 1.
[4] indicates that SCI determines that the transmission of 1-frame data, including the retransfer, is complete, and the
TEND flag is set. If the SCR_SMCI.TIE bit is 1, an SCIn_TXI interrupt request is generated. Write transmit data to
the TDR to start transmission of the next data.
Figure 32.54 shows an example flow of serial transmission. All the processing steps are automatically performed using
an SCIn_TXI interrupt request to activate the DMAC or DTC.
When the SSR_SMCI.TEND flag is set to 1 in transmission and when the SCR_SMCI.TIE bit is 1, an SCIn_TXI
interrupt request is generated.
The DMAC or DTC is activated by an SCIn_TXI interrupt request if the SCIn_TXI interrupt request is previously
specified as a source of DMAC or DTC activation, allowing the transfer of transmit data. The TEND flag is
automatically set to 0 when the DMAC or DTC transfers data.
If an error occurs, the SCI automatically retransmits the same data. During this retransmission, the TEND flag is kept at
0 and the DMAC or DTC is not activated. Therefore, the SCI and DMAC or DTC automatically transmit the specified
number of bytes, including retransmission when an error occurs. Because the ERS flag is not automatically cleared, set
the RIE bit to 1 to enable an SCIn_ERI interrupt request to be generated if an error occurs, and clear the ERS flag to 0.
When transmitting or receiving data using the DMAC or DTC, always enable the DMAC or DTC before making the SCI
settings.
For DMAC or DTC settings, see section 17, DMA Controller (DMAC) and section 18, Data Transfer Controller (DTC).
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32. Serial Communications Interface (SCI)
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(n + 1)-th transfer
frame
Retransfer frame
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
SCIn_TXI interrupt signal
[2]
[4]
SSR_SMCI.ERS flag
[1]
Figure 32.52
[3]
Data retransfer operation in SCI transmission mode
The SSR_SMCI.TEND flag is set at different timings depending on the SMR_SMCI.GM bit setting. Figure 32.53 shows
the TEND flag generation timing.
I/O data
Ds
D0
D1
D2
D3
D4
D5
D6
D7
SSR_SMCI.TEND flag
(SCIn_TXI interrupt)
DE
Guard
time
When GM bit in SMR_SMCI = 0
When GM bit in SMR_SMCI = 1
Figure 32.53
Dp
Ds:
Start bit
D0 to D7:
Dp:
DE:
Data bits
Parity bit
Error signal
12.5 ETU (11.5 ETU in block transfer mode)
11.0 ETU
SSR.TEND flag generation timing during transmission
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32. Serial Communications Interface (SCI)
Start
Initialization
Start data transmission
SSR_SMCI.ERS flag = 0?
No
Yes
Error processing
No
SCIn_TXI interrupt
Yes
Write transmit data to TDR
No
Write all transmit data
Yes
SSR_SMCI.ERS flag = 0?
Yes
No
Error processing
No
SCIn_TXI interrupt?
Yes
Set bits TIE, RIE, and TE
in SCR_SMCI to 0
End
Figure 32.54
32.6.7
Example flow of smart card interface transmission
Serial Data Reception (Except in Block Transfer Mode)
Serial data reception in smart card interface mode is similar to that in non-smart card interface mode. Figure 32.55 shows
the data retransfer operation in reception mode.
[1] indicates that if a parity error is detected in the receive data, the SSR_SMCI.PER flag is set to 1. When the
SCR_SMCI.RIE bit is 1, an SCIn_ERI interrupt request is generated. Clear the PER flag to 0 before the next parity
bit is sampled.
[2] indicates that for a frame in which a parity error is detected, no SCIn_RXI interrupt is generated.
[3] indicates that when no parity error is detected, the SCR_SMCI.PER flag is not set to 1.
[4] indicates that data is determined to be received successfully. When the SCR_SMCI.RIE bit is 1, an SCIn_RXI
interrupt request is generated.
Figure 32.56 shows an example flow of serial data reception. All the processing steps are automatically performed using
an SCIn_RXI interrupt request to activate the DMAC or DTC.
In reception, setting the RIE bit to 1 allows an SCIn_RXI interrupt request to be generated. The DMAC or DTC is
activated by an SCIn_RXI interrupt request if the SCIn_RXI interrupt request is previously specified as a source of
DMAC or DTC activation, allowing the transfer of receive data.
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32. Serial Communications Interface (SCI)
If an error occurs during reception and either the ORER or PER flag in SSR_SMCI is set to 1, a receive error interrupt
(SCIn_ERI) request is generated. Clear the error flag after the error occurrence. If an error occurs, the DMAC or DTC is
not activated and receive data is skipped. Therefore, the number of bytes of receive data specified in the DMAC or DTC
is transferred.
If a parity error occurs and the PER flag is set to 1 during reception, the receive data is transferred to RDR, therefore
allowing the data to be read.
When a reception is forced to terminate by setting SCR_SMCI.RE to 0 during operation, read the RDR register because
the received data that is not yet read might be left in the RDR.
Note:
For operations in block transfer mode, see section 32.3.9, Serial Data Reception in Asynchronous Mode.
nth transfer frame
(n + 1)th transfer
frame
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Ds D0 D1 D2 D3 D4
SCIn_RXI interrupt signal
[2]
[4]
[1]
[3]
SSR_SMCI.PER flag
Figure 32.55
Data retransfer operation in SCI reception mode
Start
Initialization
Start data reception
SSR_SMCI.ORER = 0 and
SSR_SMCI.PER = 0?
No
Yes
Error processing
No
SCIn_RXI interrupt
Yes
Read data from RDR
No
All data received?
Yes
Set bits RIE and RE
in SCR_SMCI to 0
Figure 32.56
Example flow of smart card interface reception
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32.6.8
32. Serial Communications Interface (SCI)
Clock Output Control
When the GM bit in SMR_SMCI is set to 1, the clock output can be controlled by the CKE[1: 0] bits in SCR_SMCI. For
details on the CKE[1:0] bits, see section 32.2.12, Serial Control Register for Smart Card Interface Mode (SCR_SMCI)
(SCMR.SMIF = 1). When setting the clock output, the base clock described in section 32.6.4, Receive Data Sampling
Timing and Reception Margin is output.
Figure 32.57 shows an example timing for the clock output control when the CKE[1] bit in SCR_SMCI is set to 0 and the
CKE[0] bit in SCR_SMCI is controlled.
When the GM bit in SMR_SMCI is 0, output control by the CKE[0] bit in SCR_SMCI is immediately reflected on the
SCK pin, so there is a possibility that pulses with an unintended width might be output from the SCK pin.
When the GM bit in SMR_SMCI is 1, the clock with the same pulse width as the base clock is output even if the CKE[0]
bit in SCR_SMCI is changed.
Base clock
CKE[0]
When GM = 0
SCK
When GM = 1
Figure 32.57
32.7
Clock output control
Operation in Simple IIC Mode
Simple IIC mode format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame
after a start condition or restart condition, a master device can specify a slave device as the partner for communications.
The currently specified slave device remains valid until a new slave device is specified or a stop condition is satisfied.
The 8 data bits in all frames are transmitted in the order starting from the MSB.
The I2C bus format and timing of the I2C bus are shown in Figure 32.58 and Figure 32.59.
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32. Serial Communications Interface (SCI)
7-bit address format transmission
S
SLA (7 bits)
W#
A
DATA (8 bits)
A
A/A#
P
1
7
1
1
8
1
1
1
n: Number of transfer frames
n (n = 1 or larger)
: Master device Slave device
7-bit address format reception
S
SLA (7 bits)
R
A
DATA (8 bits)
A
A#
P
1
7
1
1
8
1
1
1
: Slave device Mater device
n (n = 1 or larger)
10-bit address format transmission
S
11110b + SLA
(2 bits)
W#
A
SLA (8 bits)
A
DATA (8 bits)
A
A/A#
P
1
7
1
1
8
1
8
1
1
1
n (n = 1 or larger)
10-bit address format reception
S
11110b + SLA
(2 bits)
W#
A
SLA (8 bits)
A
Sr
11110b + SLA
(2 bits)
R
A
DATA (8 bits)
A
A#
P
1
7
1
1
8
1
1
7
1
1
8
1
1
1
n (n = 1 or larger)
Figure 32.58
I2C bus format
MSB
LSB
SDAn
D7-D1
D0
SCLn
1-7
8
9
SLA
R/W#
A
S
Figure 32.59
D7-D1
D0
1-7
8
DATA
9
A
D7-D1
D0
1-7
8
DATA
9
A
P
I2C bus timing when SLA is 7 bits
S: Indicates a start condition, when the master device changes the level on the SDAn line from high to low while the
SCLn line is high
SLA: Indicates a slave address, by which the master device selects a slave device
R/W#: Indicates the direction of transfer (reception or transmission). The value 1 indicates transfer from the slave
device to the master device and 0 indicates transfer from the master device to the slave device
A/A#: Indicates an acknowledge bit. This is returned by the slave device for master transmission and by the master
device for master reception. Return low indicates ACK and return high indicates NACK
Sr: Indicates a restart condition, when the master device changes the level on the SDAn line from high to low while
the SCLn line is high and after the setup time elapses
DATA: Indicates the data being received or transmitted
P: Indicates a stop condition, when the master device changes the level on the SDAn line from low to high while the
SCLn line is high.
32.7.1
Generation of Start, Restart, and Stop Conditions
Writing 1 to the SIMR3.IICSTAREQ bit causes the generation of a start condition. The generation of a start condition
proceeds through the following operations:
The level on the SDAn line falls (from the high level to the low level) and the SCLn line is kept in the released state
The hold time for the start condition is set as half of a bit period at the bit rate determined by the BRR setting
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32. Serial Communications Interface (SCI)
The level on the SCLn line falls (from the high level to the low level), the IICSTAREQ bit in SIMR3 is set to 0, and
a start-condition generated interrupt is output.
Writing 1 to the IICRSTAREQ bit in SIMR3 causes the generation of a restart condition. The generation of a restart
condition proceeds through the following operations:
The SDAn line is released and the SCLn line is kept at a low level
The period at low level for the SCLn line is set as half of a bit period at the bit rate determined by the BRR setting
The SCLn line is released (transition from the low to the high level)
When a high level is detected on the SCLn line, the setup time for the restart condition is set as half of a bit period at
the bit rate determined by the BRR setting
The level on the SDAn line falls (from the high level to the low level)
The hold time for the restart condition is set as half of a bit period at the bit rate determined by the BRR setting
The level on the SCLn line falls (from the high level to the low level), the SIMR3.IICRSTAREQ bit is set to 0, and
a restart-condition generated interrupt is output.
Writing 1 to the SIMR3.IICSTPREQ bit causes the generation of a stop condition. The generation of a stop condition
proceeds through the following operations:
The level on the SDAn line falls (from the high level to the low level) and the SCLn line is kept at the low level
The period at low level for the SCLn line is set as half of a bit period at the bit rate determined by the BRR setting
The SCLn line is released (transition from the low to the high level)
When a high level is detected on the SCLn line, the setup time for the stop condition is set as half of a bit period at
the bit rate determined by the BRR setting
The SDAn line is released (transition from the low to the high level), the SIMR3.IICSTPREQ bit is set to 0, and a
stop-condition generated interrupt is output.
Figure 32.60 shows the timing of operations in the generation of start, restart, and stop conditions.
SCLn
SDAn
SIMR3.IICSTAREQ
SIMR3.IICRSTAREQ
SIMR3.IICSTPREQ
SIMR3.IICSDAS[1:0]
11b 01b
SIMR3.IICSCLS[1:0]
00b
Start-condition generated
interrupt request
Figure 32.60
32.7.2
01b
00b
Restart-condition generated
interrupt request
01b
11b
Stop-condition generated
interrupt request
Timing of operations in generation of start, restart, and stop conditions
Clock Synchronization
The SCLn line can be driven low if a wait is inserted by a slave device at the other side of the transfer. Setting the
SIMR2.IICCSC bit to 1 applies control to obtain synchronization when a difference arises between the levels of the
internal SCLn clock signal and the level being input on the SCLn pin.
When the SIMR2.IICCSC bit is set to 1, the level of the internal SCLn clock signal changes from low to high. Counting
to determine the period at a high level stops while the low level is being input on the SCLn pin. Counting to determine
the period at a high level starts after the transition of the input on the SCLn pin to the high level.
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32. Serial Communications Interface (SCI)
The interval from this time until counting, to determine the period at high level that starts on the transition of the SCLn
pin to the high level, is the total of the delay of SCLn output, delay for noise filtering of the input on the SCLn pin (2 or
3 cycles of sampling clock for the noise filter), and delay for internal processing (1 or 2 cycles of PCLKA). The period at
high level of the internal SCLn clock is extended even when other devices do not place the low level on the SCLn line.
If the SIMR2.IICCSC bit is 1, synchronization is obtained for the transmission and reception of data by taking the logical
AND of the input on the SCLn pin and the internal SCLn clock. If the SIMR2.IICCSC bit is 0, synchronization with the
internal SCLn clock is obtained for the transmission and reception of data.
If a slave device inserts a wait period into the interval until the transition of the internal SCLn clock signal from the low
to the high level after a request for the generation of a start, restart, or stop condition is issued, the time until generation is
prolonged by that period.
If a slave device inserts a wait period after a transition of the internal SCLn clock signal from the low to the high level,
although the generation-completed interrupt is issued without stopping the waiting period, generation of the condition
itself is not guaranteed. Figure 32.61 shows an example operation for synchronizing the clocks.
SCLn output from the
other device
SCLn line
Internal SCLn clock
Clock driving transfer
internally
Counting of the period
at low level starts.
Counting of the period
at high level starts.
Counting is stopped until the SCLn
line being at the high level is
conveyed within the SCI.
Figure 32.61
32.7.3
Counting of the period
at high level starts.
Counting is stopped while the SCLn
line is at the low level.
Example operations for clock synchronization
SDA Output Delay
The SIMR1.IICDL[4:0] bits can be used to set a delay for the output on the SDAn pin relative to the falling edges of
output on the SCLn pin. Delay settings from 0 to 31 are selectable. The delay settings represent periods of th6e
associated numbers of cycles of the clock signal from the on-chip baud rate generator (derived by frequency-dividing the
base clock, PCLKA, by the divisor selected in the SMR.CKS[1:0] bits). A delay for output on the SDAn pin applies to
the start condition/restart condition/stop condition signal, 8-bit transmit data, and an acknowledge bit.
If the SDA output delay is shorter than the time required for the level on the SCLn pin to fall, the change of the output on
the SDAn pin starts while the output level on the SCLn pin is falling, creating a possibility of erroneous operation of
slave devices. Ensure that the settings for output delay on the SDAn pin specify a time period greater than the time that
the output on the SCLn pin takes to fall (300 ns for IIC in standard mode and fast mode).
Figure 32.62 shows the timing of delays in SDA output.
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32. Serial Communications Interface (SCI)
Clock signal from the on-chip
baud rate generator (internal signal)
Output on the SCLn pin
Output on the SDAn pin
(IICDL[4:0] = 00000b)
Output on the SDAn pin
(IICDL[4:0] = 00001b)
Output on the SDAn pin
(IICDL[4:0] = 00010b)
Output on the SDAn pin
(IICDL[4:0] = 00111b)
Output on the SDAn pin
(IICDL[4:0] = 01000b)
Figure 32.62
32.7.4
Timing of delays in SDA output
SCI Initialization in Simple IIC Mode
Before transferring data, write the initial value of 00h to SCR and initialize the interface as shown in the example in
Figure 32.63. Always set SCR to its initial value before making any changes to the operating mode or transfer format.
In simple IIC mode, the open-drain setting for the communication ports should be made on the port side.
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32. Serial Communications Interface (SCI)
[ 1 ] Set the I/O ports to allow the use (on N-channel opendrain output pins) of the SCLn and SDAn pin functions.
Start of initialization
[ 2 ] Place the SCLn and SDAn pins in a high-impedance
state until a start condition is to be generated.
Set the TIE, RIE, TE, RE, TEIE and
CKE[1:0] bits in SCR to 0
Set the I/O port functions
Set the IICSDAS[1:0] and IICSCLS[1:0] bits
in SIMR3 to 11b
[2]
Set up the transfer or reception format in
SMR and SCMR
[3]
Set the value in BRR
[4]
Set a value in MDDR
[5]
Set the values in SEMR, SNFR, SIMR1,
SIMR2, and SPMR
[6]
Set the SCR.RE and TE bit to 1 and set the
SCR.TIE, RIE and TEIE bits
[7]
Start of transmission or reception
Figure 32.63
32.7.5
[1]
[ 3 ] Set the format for transmission and reception in SMR
and SCMR.
In SMR, set the CKS[1:0] bits to the target value and
set the other bits to 0.
In SCMR, set the SDIR bit to 1 and the SINV and SMIF
bits to 0.
[ 4 ] Write the value for the target bit rate to BRR.
[ 5 ] Write the value obtained by correcting a bit rate error in
MDDR. This step is not required if the BRME bit in
SEMR is cleared to 0.
[ 6 ] Set the values in SEMR, SNFR, SIMR1, SIMR2, and
SPMR.
In SEMR, set the NFEN and BRME bits.
In SNFR, set the NFCS[2:0] bits.
In SIMR1, set the IICM bit to 1 and the IICDL[4:0] bits
as required.
In SIMR2, set the IICACKT and IICCSC bits to 1 and
the IICINTM bits as required.
In SPMR, set all the bits to 0.
[ 7 ] Set the RE and TE bits in SCR to 1. Then, set the
SCR.TIE, RIE, and TEIE bits (for transmission and
when the SIMR2.IICINTM bit is 1, set the RIE bit to 0).
Setting the TE and RE bits to 1 makes the SCLn and
SDAn pin functions available.
Example flow of SCI initialization in simple IIC mode
Operation in Master Transmission in Simple IIC Mode
Figure 32.64 and Figure 32.65 show examples of master transmission and Figure 32.66 shows an example flow of data
transmission. The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts) and
the value of the SCR.RIE bit is assumed to be 0 (SCIn_RXI and SCIn_ERI interrupt requests are disabled). See Table
32.29 for more information on the STI interrupt.
When 10-bit slave addresses are in use, steps [3] and [4] in Figure 32.66 are repeated twice.
In simple IIC mode, the transmit data empty interrupt (SCIn_TXI) is generated when communication of one frame is
complete, unlike the SCIn_TXI interrupt request generation timing during clock synchronous transmission.
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32. Serial Communications Interface (SCI)
Start condition
Slave address (7 bits)
Transmitted data
W#
Stop condition
SCLn
D7
SDAn
D6
D1
ACK
D0
D7
D6
D1
D0
ACK/NACK
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Acceptance of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
STI interrupt flag
(IELSRn.IR*1)
Generation of STI interrupt
Acceptance of request
Reception of ACK
SISR.IICACKR flag
Generation of request
Reception of NACK
Reception of ACK
Note 1.
Figure 32.64
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example 1 of operations for master transmission in simple IIC mode with 7-bit slave addresses,
transmission interrupts, and reception interrupts
When the SIMR2.IICINTM bit is set to 0, using ACK/NACK interrupts during master transmission, the DMAC or DTC
is activated by the ACK interrupt as the trigger and required number of data bytes are transmitted. When the NACK is
received, error processing such as transmission stop and retransmission is performed using the NACK interrupt as the
trigger.
Start condition
Slave address (7 bits)
Transmitted data
W#
Stop condition
SCLn
SDAn
D7
D6
D1
D0
ACK
D7
D6
D1
D0
NACK
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Generation of SCIn_TXI interrupt request
SCIn_RXI interrupt flag
(IELSRn.IR*1)
STI interrupt flag
(IELSRn.IR*1)
Generation of STI interrupt request
Note 1.
Figure 32.65
Acceptance of SCIn_TXI
interrupt request
Generation of SCIn_RXI interrupt request Acceptance of SCIn_RXI interrupt request
Acceptance of STI interrupt request
Generation of STI interrupt request
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Example 2 of operations for master transmission in simple IIC mode with 7-bit slave addresses,
ACK interrupts, and NACK interrupts
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32. Serial Communications Interface (SCI)
Initialization
[1]
Start of transmission
Simultaneously set the SIMR3.IICSTAREQ bit to
1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt?
[2]
No
Yes
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 00b
Write the slave address and value for the
R/W bit in TDR
SCIn_TXI interrupt?
[3]
No
Yes
SISR.IICACKR = 0?
No
[4]
If 10-bit slave addresses are in use, processing of
[ 3 ] and [ 4 ] is repeated twice.
Yes
Write transmit data in TDR
SCIn_TXI interrupt?
No
Yes
No
[5]
All data transmitted?
Yes
Simultaneously set the SIMR3.IICSTPREQ bit to
1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt?
[6]
No
Yes
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 11b
End
Figure 32.66
Example flow of master transmission in simple IIC mode with transmission interrupts and
reception interrupts
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32.7.6
32. Serial Communications Interface (SCI)
Master Reception in Simple IIC Mode
Figure 32.67 shows an example operation in simple IIC mode master reception and Figure 32.68 shows an example flow
of master reception.
The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts).
In simple IIC mode, the transmit data empty interrupt (SCIn_TXI) is generated when the communication of one frame is
complete, unlike the SCIn_TXI interrupt request generation timing during clock synchronous transmission.
Start
condition
Slave address (7 bits)
Stop condition
Received data
R
SCLn
SDAn
D7
D6
D1
D0
ACK
D7
D6
D1
D0
NACK
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SCIn_RXI is assumed to have been disabled
by setting SCR.RIE = 0.
STI interrupt flag
(IELSRn.IR*1)
Generation of SCIn_RXI interrupt request
Acceptance of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
Acceptance of STI interrupt request
Generation of STI interrupt request
Generation of STI interrupt request
Note 1.
See section 14, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Figure 32.67
Example operations for master reception in simple IIC mode with 7-bit slave addresses,
transmission interrupts, and reception interrupts
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32. Serial Communications Interface (SCI)
[1]
Initialization
Start of reception
Simultaneously set the SIMR3.IICSTAREQ bit
to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt?
[2]
No
Yes
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 00b
Write the slave address and value for
the R/W bit to TDR
SCIn_TXI interrupt?
[3]
No
Yes
SISR.IICACKR = 0?
No
[4]
Yes
Set SIMR2.IICACKT to 0
Set SCR.RIE to 1
Next data is the last?
Yes
[5]
No
Set SIMR2.IICACKT to 1
[6]
Write FFh as dummy data to TDR
Write FFh as dummy data to TDR
SCIn_RXI interrupt?
No
SCIn_RXI interrupt?
No
Yes
Yes
Read received data from RDR
SCIn_TXI interrupt?
Yes
Read received data from RDR
No
SCIn_TXI interrupt?
No
Yes
Simultaneously set the SIMR3.IICSTPREQ bit to
1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt?
[7]
No
Yes
Set the SIMR3.IICSTIF flag to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 11b
End
Figure 32.68
Example flow of master reception in simple IIC mode with transmission interrupts and reception
interrupts
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32.8
32. Serial Communications Interface (SCI)
Operation in Simple SPI Mode
As an extended function, SCI supports a simple SPI mode that handles transfer between one or multiple master devices
and multiple slave devices.
To place the SCI in simple SPI mode, use the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0,
SMR.CM = 1) and set the SPMR.SSE bit to 1. When the configuration only has a single master, the SSn pin function on
the master side is not required to connect the device used as the master in simple SPI mode. Therefore, in such a case, set
the SPMR.SSE bit to 0.
Figure 32.69 shows an example of connections for simple SPI mode. Use a general port pin to produce the SSn output
signal from the master.
In simple SPI mode, data is transferred in synchronization with clock pulses in the same way as in clock synchronous
mode. One character of data for transfer consists of 8 bits of data, and parity bits cannot be appended. The data can be
inverted by setting the SCMR.SINV bit to 1.
Because the receiver and transmitter are independent of each other within the SCI module, full-duplex communications
are possible, with a common clock signal. Additionally, because both the transmitter and receiver have a buffered
structure, it is possible to write the next transmit data while transmission is in progress and also read previously received
data while reception is in progress. This enables continuous transfer.
Device 1 (master)
Device 2 (slave)
Port pin (output)
SSn (input)
Port pin (output)
SSn (input)
*1
SCKn (input)
SCKn (output)
MISOn (output)
MISOn (input)
MOSIn (input)
MOSIn (output)
Device 3 (slave)
SSn (input)
SCKn (input)
MISOn (output)
MOSIn (input)
Note 1. The SSn input is not required in a single-master system
(the interface is used with the setting SPMR.SSE = 0).
Figure 32.69
32.8.1
Example connections using simple SPI mode in single master mode with SPMR.SSE bit = 0
States of Pins in Master and Slave Modes
The direction (input or output) of pins for the simple SPI mode interface differs according to whether the device is a
master (SCR.CKE[1:0] = 00b or 01b and SPMR.MSS = 0) or slave (SCR.CKE[1:0] = 10b or 11b and SPMR.MSS = 1).
Table 32.25 lists the relationship between the pin states, mode, and level on the SSn pin.
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Table 32.25
32. Serial Communications Interface (SCI)
States of pins by mode and input level on SSn pin
Mode
Input on SSn pin
State of TXDn pin
State of RXDn pin
State of SCKn pin
Master mode*1
High level
(transfer can proceed)
Output for data
transmission*2
Input for received data
Clock output*3
Low level
(transfer cannot proceed)
High-impedance
Input for received data
(but disabled)
High-impedance
High level
(transfer cannot proceed)
Input for received data
(but disabled)
High-impedance
Clock input
(but disabled)
Low level
(transfer can proceed)
Input for received data
Output for data
transmission
Clock input
Slave mode
Note 1. When there is only a single master (SPMR.SSE = 0), transfer is possible regardless of the input level on the SSn
pin. This is equivalent to the input of a high level on the SSn pin. Because the SSn pin function is not required,
the pin is available for other purposes.
Note 2. The MOSIn pin output is in a high-impedance state when serial transmission is disabled (SCR.TE bit = 0).
Note 3. The SCKn pin output is in a high-impedance state when serial transmission is disabled (SCR.TE and RE bits =
00b) in a multi-master configuration (SPMR.SSE = 1).
32.8.2
SS Function in Master Mode
Setting the SCR.CKE[1:0] bits to 00b and the SPMR.MSS bit to 0 selects master operation.
In single-master configurations (SPMR.SSE = 0), the SSn pin is not used, and so the transmission or reception can
proceed regardless of the value of the SSn pin.
When the level on the SSn pin is high in a multi-master configuration (SPMR.SSE = 1), a master device outputs clock
signals from the SCKn pin before starting the transmission or reception to indicate that there are no other masters or
another master is performing reception or transmission.
When the level on the SSn pin is low in a multi-master configuration (SPMR.SSE = 1), there are other masters, and this
indicates that transmission or reception is in progress. The MOSIn output and SCKn pins are placed in a high-impedance
state and starting transmission or reception is not possible. In addition, the value of the SPMR.MFF bit is 1, indicating a
mode fault error. In a multi-master configuration, start the error processing by reading the SPMR.MFF flag. Even if a
mode fault error occurs while transmission or reception is in progress, the transmission or reception does not stop, but the
MOSIn and SCKn pin outputs are placed in the high-impedance state after completion of the transfer. Use a general port
pin to produce the SS output signal from the master.
32.8.3
SS Function in Slave Mode
Setting the SCR.CKE[1:0] bits to 10b and the SPMR.MSS bit to 1 selects slave operation. When the SSn pin is high, the
MISOn output pin is in a high-impedance state and the clock input through the SCKn pin is ignored. When the SSn pin is
low, the clock input through the SCKn pin is valid and transmission or reception can proceed.
If the input on the SSn pin changes from low to high during transmission or reception, the MISOn output pin is placed in
a high-impedance state. Meanwhile, the internal processing for transmission or reception continues at the rate of the
clock input through the SCKn pin until processing for the character being transmitted or received is complete, after
which it stops, and the appropriate interrupt (SCIn_TXI, SCIn_RXI, or SCIn_TEI) is generated.
32.8.4
Relationship between Clock and Transmit/Receive Data
The CKPOL and CKPH bits in the SPMR register can be used to set up the clock for use in transmission and reception in
four different ways. The relation between the clock signal and the transmission and reception of data is shown in Figure
32.70. The relation is the same for both master and slave operation. This is the same as when the level on the SSn pin is
high.
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32. Serial Communications Interface (SCI)
One unit of transfer data (character or frame)
(1) When CKPH = 0
SSn pin
(slave)
SCKn pin
(CKPOL = 0)
SCKn pin
(CKPOL = 1)
MOSIn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MISOn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CKPH = 1
SSn pin
(slave)
SCKn pin
(CKPOL = 0)
SCKn pin
(CKPOL = 1)
MOSIn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MISOn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 32.70
32.8.5
Relation between clock signal and transmit or receive data in simple SPI mode
SCI Initialization in Simple SPI Mode
Initialization in simple SPI mode is the same as in clock synchronous mode. See Figure 32.32 for an example
initialization flow. The CKPOL and CKPH bits in the SPMR register must be set to ensure that the clock signal is
suitable for both master and slave devices.
Always initialize the SCR register before making any changes to the operating mode or transfer format.
Note:
Note:
32.8.6
Only the RE bit is set to 0. The SSR.ORER, FER, PER, and RDR flags are not initialized.
Changing the value of the TE bit from 1 to 0 or from 0 to 1 leads to the generation of a transmit data empty
interrupt (SCIn_TXI), if the value of the SCR.TIE bit is 1.
Transmission and Reception of Serial Data in Simple SPI Mode
In master operation, ensure that the SSn pin of the slave device on the other side of the transfer is at a low level before
starting the transfer and at the high level on completion of the transfer. Otherwise, the procedures are the same as in clock
synchronous mode.
32.9
Bit Rate Modulation Function
Using the bit rate modulation function, the bit rate can be evenly corrected using the number specified in the MDDR
register when the PCLKA is selected in the CKS[1:0] bits in SMR/SMR_SMCI.
Figure 32.71 shows an example where PCLKA is selected in the CKS[1:0] bits in SMR/SMR_SMCI, the BRR bit is set
to 0, and the MDDR is set to 160 in asynchronous mode. In this example, the cycle of the base clock is evenly corrected
(256/160) and the bit rate is also corrected (160/256).
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Note:
32. Serial Communications Interface (SCI)
Enabling an internal clock causes bias, and expansion and contraction are generated in the pulse width of the
internal base clock.
Do not use this function in clock synchronous mode and in the highest speed settings in simple SPI mode
(SMR.CKS[1:0] = 00b, SCR.CKE[1] = 0, and BRR = 0).
Internal clock
(bit rate counter input)
Internal base clock
Transmit/receive data
1-bit interval is 16 cycles of the internal base clock.
(a) When the bit modulation function is not used
160 clocks from 256 clocks are evenly enabled (96 clocks are disabled) by setting MDDR.
Internal clock
(bit rate counter input)
Internal base clock
Transmit/receive data
1-bit interval is 16 cycles of the internal base clock.
This figure shows an example when 1-bit interval is corrected to 52/32. (1-bit interval is evenly corrected to 256/160.)
(b) The bit rate is corrected (160/256) using the bit rate modulation function
Figure 32.71
Example internal base clock when bit rate modulation function is used
32.10 Interrupt Sources
32.10.1
Buffer Operation for SCIn_TXI and SCIn_RXI Interrupts (non-FIFO selected)
If the conditions for an SCIn_TXI and SCIn_RXI interrupt are satisfied while the interrupt status flag in the Interrupt
Controller Unit (ICU) is 1, the ICU does not output the interrupt request but saves it internally, with a capacity for saving
of one request per source.
When the interrupt status flag in the ICU becomes 0, the interrupt request saved within the ICU is output. The internally
saved interrupt request is automatically discarded when the actual interrupt is output. Clearing of the associated interrupt
enable bit (the TIE or RIE bit in the SCR/SCR_SMCI) can also be used to discard an internally saved interrupt request.
32.10.2
Buffer Operation for SCIn_TXI and SCIn_RXI Interrupts (FIFO selected)
Even when an interrupt status flag in the ICU is set to 1, the SCIn_TXI and SCIn_RXI interrupts do not output interrupt
requests to the ICU. When an interrupt status flag of the ICU is cleared to 0, and if the conditions for SCIn_TXI and
SCIn_RXI interrupts are satisfied, an interrupt request is generated.
32.10.3
(1)
Interrupts in Asynchronous, Clock Synchronous, and Simple SPI Modes
Non-FIFO selected
Table 32.26 lists the interrupt sources in asynchronous mode, clock synchronous mode, and simple SPI mode. A different
interrupt vector can be assigned to each interrupt source. Individual interrupt sources can be enabled or disabled with the
enable bits in the SCR register.
If the SCR.TIE bit is 1, an SCIn_TXI interrupt request is generated when transmit data is transferred from the TDR or
TDRHL register*1 to the TSR register. An SCIn_TXI interrupt request can also be generated by using a single instruction
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32. Serial Communications Interface (SCI)
to set the SCR.TE and SCR.TIE bits to 1 simultaneously. An SCIn_TXI interrupt request can activate the DMAC or DTC
to handle data transfer.
An SCIn_TXI interrupt request is not generated by setting the SCR.TE bit to 1 when SCR.TIE is 0 or by setting the
SCR.TIE bit to 1 when the SCR.TE is 1.*2
When new data is not written by the time of transmission of the last bit of the current transmit data and SCR.TEIE is 1,
the SSR.TEND flag is set to 1 and an SCIn_TEI interrupt request is generated. Additionally, when SCR.TE is 1, the
SSR.TEND flag retains the value of 1 until more transmit data is written to the TDR or TDRHL register*1, and setting
SCR.TEIE to 1 leads to the generation of an SCIn_TEI interrupt request.
Writing data to the TDR or TDRHL register*1 leads to the clearing of the SSR.TEND flag and, after a certain time,
discarding of the SCIn_TEI interrupt request.
If the SCR.RIE bit is 1, an SCIn_RXI interrupt request is generated when received data is stored in the RDR register. An
SCIn_RXI interrupt request can activate the DMAC or DTC to handle data transfer.
Setting any of the ORER, FER, and PER flags in the SSR register to 1 while the SCR.RIE bit is 1 leads to the generation
of an SCIn_ERI interrupt request. An SCIn_RXI interrupt request is not generated at this time. Clearing all three flags
(ORER, FER, and PER) leads to discarding of the SCIn_ERI interrupt request.
(2)
FIFO selected
Table 32.27 lists interrupt sources in FIFO selected mode.
If the SCR.TIE bit is 1, an SCIn_TXI interrupt request is generated when the amount of stored data in the FTDRL
register becomes the threshold value indicated in FCR.TTRG or below. An SCIn_TXI interrupt request can also be
generated by using a single instruction to set the SCR.TE and SCR.TIE bits to 1 at the same time.
An SCIn_TXI interrupt request is not generated by setting SCR.TE to 1 when SCR.TIE is 0 or by setting SCR.TIE to 1
when SCR.TE is 1.
If SCR.TEIE is 1 and if the next data is not written to the FTDRL register by the time the last bit of the transmit data is
sent, the SSR_FIFO.TEND flag is set to 1 and the SCIn_TEI interrupt request is generated.
If SCR.RIE is 1, the SCIn_RXI interrupt request is generated when the stored amount of data in the FRDRL register is
equal to or greater than the threshold value indicated in FCR.RTRG. When RTRG is 0, an SCIn_RXI interrupt does not
occur even when the amount of data in the receive FIFO is equal to 0.
If the SCR.RIE bit is 1, when the SSR_FIFO.ORER flag is set to 1 or data with a framing error or a parity error is stored
in the FRDRL register, the SCIn_ERI interrupt request is generated. When the amount of data stored in the FRDRL
register is at or above the threshold value, the SCIn_RXI interrupt request is also generated. The SCIn_ERI interrupt
request can be canceled, in which case the SSR_FIFO.ORER, FER, and PER flags are all cleared.
Note 1. When asynchronous mode and 9-bit data length are selected.
Note 2. To temporarily prohibit the SCIn_TXI interrupts on transmission of the last of the data when a new round of
transmission is to be started, after handling the transmission-completed interrupt, control the activation of the
interrupt by using the interrupt request enable bit in the ICU rather than using the SCR.TIE bit. This approach can
prevent the suppression of the SCIn_TXI interrupt requests in the transfer of new data.
Table 32.26
SCI interrupt sources with non-FIFO selected
Name
Interrupt source
Interrupt flag
Interrupt
enable
DTC activation
DMAC activation
SCIn_ERI
Receive error*1
ORER, FER, PER, DFER, DPER
RIE
Not possible
Not possible
SCIn_RXI
SCIn_AM
Receive data full
RDRF
RIE
Possible
Possible
Address match
DCMF
RIE
Possible
Possible
Address match
DCMF
—
Possible
Possible
SCIn_TXI
Transmit data empty
TDRE
TIE
Possible
Possible
SCIn_TEI
Transmit end
TEND
TEIE
Not possible
Not possible
Note 1. The interrupt flag is only ORER when in clock synchronous and simple SPI mode.
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Table 32.27
Name
SCIn_ERI
SCIn_RXI
32. Serial Communications Interface (SCI)
SCI interrupt sources with FIFO selected
Interrupt source
Receive
error*1
Interrupt
enable
Interrupt flag
DTC activation
DMAC activation
ORER, FER, PER, DFER, DPER
RIE
Not possible
Not possible
DR (when FCR.DRES = 1)
RIE
Not possible
Not possible
Receive data full
RDF
RIE
Possible
Possible
Receive data ready
DR (when FCR.DRES = 0)
RIE
Possible
Possible
Address match
DCMF
RIE
Possible
Possible
SCIn_AM
Address match
DCMF
—
Possible
Possible
SCIn_TXI
Transmit data empty
TDFE
TIE
Possible
Possible
SCIn_TEI
Transmit end
TEND
TEIE
Not possible
Not possible
Note 1. The interrupt flag is only ORER when in clock synchronous and simple SPI mode.
32.10.4
Interrupts in Smart Card Interface Mode
Table 32.28 lists the interrupt sources in smart card interface mode. A transmit end interrupt (SCIn_TEI) request and an
address match (SCIn_AM) request cannot be used in this mode.
Table 32.28
SCI Interrupt sources
Name
Interrupt source
Interrupt flag
Interrupt enable
DTC activation
DMAC activation
SCIn_ERI
Receive error or error
signal detection
ORER, FER, ERS
RIE
Not possible
Not possible
SCIn_RXI
Receive data full
RDRF
RIE
Possible
Possible
SCIn_TXI
Transmit end
TEND
TIE
Possible
Possible
Data transmission or reception using the DMAC or DTC is also possible in smart card interface mode. In transmission,
when the SSR_SMCI.TEND flag is set to 1, an SCIn_TXI interrupt request is generated. The SCIn_TXI interrupt request
activates the DMAC or DTC, allowing the transfer of transmit data if the SCIn_TXI request is previously specified as a
source for DMAC or DTC activation. The TEND flag is automatically set to 0 when the DMAC or DTC transfers data.
If an error occurs, the SCI automatically retransmits the same data. During the retransmission, the TEND flag is kept at 0
and the DMAC or DTC is not activated. Therefore, SCI and DMAC or DTC automatically transmit the specified number
of bytes, including retransmission after an error occurrence. However, the SSR_SMCI.ERS flag is not automatically
cleared to 0 at error occurrence. Therefore, the ERS flag must be cleared by previously setting the SCR_SMCI.RIE bit to
1 to enable an SCIn_ERI interrupt request to be generated at error occurrence.
When transmitting or receiving data using the DMAC or DTC, always enable the DMAC or DTC before setting the SCI.
For DMAC or DTC settings, see section 17, DMA Controller (DMAC) and section 18, Data Transfer Controller (DTC).
In reception, an SCIn_RXI interrupt request is generated when receive data is set to RDR. This SCIn_RXI interrupt
request activates the DMAC or DTC, allowing transfer of the receive data if the SCIn_RXI request is previously
specified as a source of DMAC or DTC activation. If an error occurs, the error flag is set. Therefore, the DMAC or DTC
is not activated and an SCIn_ERI interrupt request is issued to the CPU instead. The error flag must be cleared.
32.10.5
Interrupts in Simple IIC Mode
Table 32.29 lists the interrupt sources in simple IIC mode. The STI interrupt is allocated to the transmit end interrupt
(SCIn_TEI) request. The receive error interrupt (SCIn_ERI) and the address match (SCIn_AM) request cannot be used.
The DMAC or DTC can also be used to handle transfer in simple IIC mode.
When the SIMR2.IICINTM bit is 1:
An SCIn_RXI request is generated on the falling edge of the SCLn signal for the 8th bit. If SCIn_RXI is previously
set up as an activation source for the DMAC or DTC, the SCIn_RXI request activates the DMAC or DTC to handle
transfer of the received data.
An SCIn_TXI request is generated on the falling edge of the SCLn signal for the 9th bit (acknowledge bit). If
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32. Serial Communications Interface (SCI)
SCIn_TXI is previously set up as an activation source for the DMAC or DTC, the SCIn_TXI request activates the
DMAC or DTC to handle the transfer of the transmit data.
When the SIMR2.IICINTM bit is 0:
An SCIn_RXI request (ACK detection) is generated if the input on the SDAn pin is low on the rising edge of the
SCLn signal for the 9th bit (acknowledge bit)
An SCIn_TXI request (NACK detection) is generated if the input on the SDAn pin is high on the rising edge of the
SCLn signal for the 9th bit (acknowledge bit)
If SCIn_RXI is previously set up as an activation source for the DMAC or DTC, the SCIn_RXI request activates the
DMAC or DTC to handle the transfer of the received data.
If the DMAC or DTC is used for data transfer in reception or transmission, always set up and enable the DMAC or DTC
before setting up the SCI.
When the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits in SIMR3 are used to generate a start condition, restart
condition, or stop condition, the STI request is issued when generation is complete.
Table 32.29
SCI interrupt sources
Interrupt flag
Interrupt
enable
DTC
activation
Name
Interrupt source
DMAC activation
SCIn_RXI
Reception, ACK detection
—
RIE
Possible
Possible
SCIn_TXI
Transmission, NACK detection
—
TIE
Possible
Possible
STIn
Completion of generation of a start,
restart, or stop condition
IICSTIF
TEIE
Not possible
Not possible
Note 1. Activation of the DTC is only possible when the SIMR2.IICINTM bit is 1 (use reception and transmission
interrupts).
32.11 Event Linking
By using interrupt request signals as event signals, the SCI can provide linked operation through the ELC for modules
selected in advance. Event signals can be output regardless of the values of the associated interrupt request enable bits.
(1)
Error event output (receive error or error signal detected)
Indicates abnormal termination because of a parity error during reception in asynchronous mode
Indicates abnormal termination because of a framing error during reception in asynchronous mode
Indicates abnormal termination because of an overrun error during reception
Indicates detection of the error signal during transmission in smart card interface mode
Indicates that when the SSR_FIFO.FER and PER flags are 0, and receive data less than the receive FIFO data
trigger number is in the receive FIFO buffer, 15 ETUs elapse when FIFO is selected and the FCR.DRES bit is 1.
(2)
Receive data full event output
Indicates that ACK is detected if the SIMR2.IICINTM bit is 0 in simple IIC mode
Indicates that the 8th-bit SCLn falling edge is detected if the SIMR2.IICINTM bit is 1 in simple IIC mode
When the SIMR2.IICINTM bit is 1 during master transmission in simple IIC mode, set the ELC so that receive data
full events are not used.
(a)
Non-FIFO selected
Indicates that received data is set in the Receive Data Register (RDR or RDRHL).
(b)
FIFO selected
Using this event output is prohibited.
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(3)
32. Serial Communications Interface (SCI)
Transmit data empty event output
Indicates that the SCR/SCR_SMCI.TE bit is changed from 0 to 1
Indicates that transmission is complete in smart card interface mode
Indicates that NACK is detected if the SIMR2.IICINTM bit is 0 in simple IIC mode
Indicates that the 9th-bit SCLn falling edge is detected if the SIMR2.IICINTM bit is 1 in simple IIC mode.
(a)
Non-FIFO selected
Indicates that transmit data is transferred from the Transmit Data Register (TDR or TDRHL) to the Transmit Shift
Register (TSR).
(b)
FIFO selected
Using this event output is prohibited.
(4)
Transmit end event output
Indicates the completion of transmission
Indicates that the starting condition, restart condition, or stop condition is generated in simple IIC mode
When FIFO is selected, using this event output is prohibited.
(5)
Address match event output
Indicates a match of the comparison data (CDR.CMPD) with one frame of receive data when DCCR.DCME is set
to 1 in asynchronous mode, including multiprocessor mode.
32.12 Address mismatch event output (SCI0_DCUF)
The address mismatch event output, SCI0_DCUF, indicates a mismatch of the comparison data (CDR.CMPD) with one
frame of receive data when DCCR.DCME is set to 1 in asynchronous mode, including multi-processor mode. This event
can be used for snooze end request only.
32.13 Noise Cancellation Function
Figure 32.72 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of a 2-stage
flip-flop circuit and a match detection circuit. When the input signals of the noise filter and the output signals of the 2stage flip-flop circuits completely match, the matched level is conveyed as an internal signal. Unless a match occurs, the
previous value is retained. When the same level is retained for 3 cycles or longer on the sampling clock of the noise filter,
it is considered as a valid receive signal. A change in pulse for 3 cycles or shorter is considered as noise, not as a receive
signal.
When SEMR.ABCS = 0 and SEMR.ABCSE = 0, the cycle is 1/16 the period of 1 transfer bit.
When SEMR.ABCS = 1 and SEMR.ABCSE = 0, the cycle is 1/8 the period of 1 transfer bit.
When SEMR.ABCSE = 1, the cycle is 1/6 the period of 1 transfer bit.
In asynchronous mode, the noise cancellation function can be applied to the receive signal input on the RXDn pin. The
receive level of the RXDn is sampled in the flip-flop circuit of the noise filter on the base clock of asynchronous mode.
In simple IIC mode, this function can be used for each input on SDAn and SCLn. The sampling clock for the noise
cancellation function is selected in the SNFR.NFCS[2:0] bit by dividing the baud rate generator source clock by 1,2,4, or
8.
If the base clock is stopped with the noise filter enabled and the base clock input is restarted again, the noise filter
operation resumes from the state where the clock was stopped. When SCR.TE and SCR.RE are set to 0 during base clock
input, all of the noise filter flip-flop values are initialized to 1. Accordingly, if the input data is 1 when reception
operation resumes, the function determines that a level match is detected and the result is conveyed as an internal signal.
When the level being input corresponds to 0, the initial output of the noise filter is retained until the level matches in 3
consecutive sampling cycles.
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32. Serial Communications Interface (SCI)
TXDn/SDAn,
RXDn/SCLn
Internal signal
Un-match
match
cmp
TXDn/SDAn,
RXDn/SCLn
inputs
Baud rate generator
Clock source
Base clock of
Asynchronous mode
D
1 div
2 div
4 div
8 div
Q
CLK
D
D
CLK
Q
CLK
NFCS[2:0] bits
Figure 32.72
Q
NFEN bit
Digital noise filter circuit block diagram
32.14 Usage Notes
32.14.1
Settings for the Module-Stop Function
The Module Stop Control Register B (MSTPCRB) can enable or disable SCI operation. The SCI is initially stopped after
reset. Releasing the module-stop state enables access to the registers. For details, see section 11, Low Power Modes.
32.14.2
(1)
SCI Operation during Low Power State
Transmission
When setting the module to the stopped state or in transitions to Software Standby, stop operation (by setting the TIE,
TE, and TEIE bits in the SCR/SCR_SMCI to 0) after switching the TXDn pin to the general I/O port pin function. When
setting the I/O port as an SCI connection, the SPTR register can control the state of the TXDn pin. Setting the TE bit to 0
initializes the TSR register and the TEND bit in the SSR/SSR_SMCI is initialized to 1 with non-FIFO selected. The
value is kept, with FIFO selected. Depending on the port settings and SPTR register settings, output pins might output
the level before a transition to the low power state is made after release from the module-stopped state or Software
Standby mode. When transitions to these states are made during transmission, the transmitted data becomes
indeterminate.
To transmit data in the same transmission mode after cancellation of the low power state:
1. Set the TE bit to 1.
2. Read SSR/SSR_FIFO/SSR_SMCI.
3. Write data to TDR sequentially to start data transmission.
To transmit data with a different transmission mode, initialize the SCI first.
Figure 32.73 shows an example flow of transition to Software Standby mode during transmission. Figure 32.74 and
Figure 32.75 show the port pin states during transition to Software Standby mode.
Before specifying the module-stop state or making a transition to Software Standby mode from the transmission mode
using DTC transfer, stop the transmit operations (TE = 0). To start transmission after cancellation using the DTC, set the
TE bit to 1. The SCIn_TXI interrupt flag is set to 1 and transmission starts using the DTC.
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32. Serial Communications Interface (SCI)
(2)
Reception
(a)
When address match function is not used as wakeup condition
Before specifying the module-stop state or making a transition to Software Standby mode, stop the receive operations
(RE = 0 in SCR/SCR_SMCI). If transition is made during data reception, the received data is invalid.
Figure 32.76 shows an example flow of transition to Software Standby mode during reception.
(b)
When address match function is used as wakeup condition
Before specifying the module-stop state or making a transition to Software Standby mode:
1. Set the operations after cancellation of the low power state.
2. Set CDR.CMPD and DCCR.DCME to 1.
3. Set the receive operations (RE = 1 in SCR/SCR_SMCI).
4. Set the module-stop state or Software Standby mode.
When SCI transfers to low power mode, if the receive data pin (RXD) is at the low level, set SEMR.RXDESEL = 0.
When setting SEMR.RXDESEL = 1, there is a possibility that a start bit (falling edge of RXDn pin) cannot be detected
on release of the low power mode.
Figure 32.77 shows an example flow of transition to Software Standby mode during reception with address match.
(c)
When using SCI0 in Snooze mode
When using SCI0 in Snooze mode, some restrictions apply, including maximum bit rates. For details, see section 11,
Low Power Modes.
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32. Serial Communications Interface (SCI)
Start of transmission
No
All data transmitted?
[1]
[1] Data being transmitted is lost. Data can be
normally transmitted from the CPU by setting
the TE bit in SCR/SCR_SMCI to 1, reading
SSR/SSR_FIFO/SSR_SMCI, and writing
Software Standby mode. However, if the DMAC
or DTC is activated, the data remaining in the
DMAC or DTC is transmitted when both the TE
and TIE bits in SCR/SCR_SMCI are set to 1.
Yes
Read TEND flag in SSR/SSR_FIFO/SSR_SMCI
No
SSR/SSR_FIFO/SSR_SMCI.TEND = 1
Yes
Set the I/O port function and SPTR register
[2]
SCR/SCR_SMCI.TE bit = 0
[3]
Transition to Software Standby mode
[4]
[2] Make the I/O port function and SPTR register
settings to switch the TXDn pin to operate as a
general I/O port.
[3] Set SCR/SCR_SMCI.TE bit to 0. If
SCR/SCR_SMCI.TIE = 1 and
SCR/SCR_SMCI.TEIE = 1, these are set to 0
simultaneously with the SCR.TE bit.
[4] This includes the setting for the module-stop
state.
Cancel Software Standby mode
No
Change operating mode?
Yes
Set the I/O port function
Initialization
SCR/SCR_SMCI.TE bit = 1
Start data transmission
Figure 32.73
Example flow of transition to Software Standby mode during transmission
Transition to
Software Standby
mode
Software Standby mode
canceled
PmnPFS.PMR bit setting
(TXDn pin function setting)
SPTR.SPB2IO bit
SCR/SCR_SMCI.TE bit
The level at transition to
Software Standby mode is
retained
SCKn output pin
TXDn output pin
Port input/output
Port
The TXDn output pin state
(Low or High level) after
PmnPFS.PMR bit setting is
set as a SPTR register
Figure 32.74
The level before transition to
software standby mode is
output
Stop
High output
SCI TXDn output
The TXDn pin status when
being TE = 0, can be
controlled by SPTR register
SPTR.SPB2DT bit set value
Port pin states during transition to Software Standby mode with internal clock and asynchronous
transmission
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32. Serial Communications Interface (SCI)
Software Standby
mode canceled
Transition to Software
Standby mode
PmnPFS.PMR bit setting
SCR/SCR_SMCI.TE bit
SCKn output pin
TXDn output pin
Port input/output
Last TXD bit retained
Marking output
Figure 32.75
Port input/output
Port
SCI TXDn output
Port
The level before transition to
software standby mode is output
SCI TXDn output
Port pin states during transition to Software Standby mode with internal clock and clock
synchronous transmission
Data reception
No
SCIn_RXI interrupt?
[1]
[ 1 ] Received data is invalid.
Yes
Read receive data in RDR
SCR/SCR_SMCI.RE = 0
Make transition to Software Standby mode
[2]
[ 2 ] Setting for the module-stop state is included.
Cancel Software Standby mode
Change operating mode?
No
Yes
Initialization
SCR/SCR_SMCI.RE = 1
Start data reception
Figure 32.76
Example flow of transition to Software Standby mode during reception
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32. Serial Communications Interface (SCI)
Data reception
SCIn_RXI interrupt?
No
[1]
[ 1 ] Data being received is invalid.
Yes
Read receive data in RDR
SCR/SCR_SMCI.RE = 0
[ 2 ] Setting for the module stop state is included.
Set the operation mode in cancel of software
standby
Set a compared data to CDR
DCCR.DCME = 1
SCR/SCR_SMCI.RE = 1
[2]
Make transition to Software Standby mode
Cancel Software Standby mode
Change operating mode?
No
Yes
Initialization
Start/continue data reception
Figure 32.77
32.14.3
(1)
Example flow of transition to Software Standby mode during reception with address match
Break Detection and Processing
Non-FIFO selected
When a framing error is detected, a break can be detected by reading the RXDn pin value directly. In a break, the input
from the RXDn pin becomes all 0s, and the SSR.FER flag is set to 1 to indicate a framing error. The SSR.PER flag might
also be set to 1 to indicate a parity error. The SCI continues the receive operation even after a break is received.
Therefore, even if the FER flag is 0, indicating that no framing error occurred, it is set to 1 again. When the
SEMR.RXDESEL bit is 1, the SCI sets the SSR.FER flag to 1 and stops the receiving operations until a start bit of the
next data frame is detected. If the SSR.FER flag is set to 0, the SSR.FER flag retains 0 during the break.
When the RXDn pin is set to 1 and the break ends, detecting the beginning of the start bit on the first falling edge of the
RXDn pin allows the SCI to start the receiving operation.
(2)
FIFO selected
After a framing error is detected and when the SCI detects that continuous receive data is 0 for 1 frame, reception stops.
When a framing error is detected, a break can be detected by reading the SPTR.RXDMON bit value. After the RXD
signal is in the mark state and the break is finished, data reception to the FRDRHL register resumes.
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32.14.4
32. Serial Communications Interface (SCI)
Mark State and Production of Breaks
When the SCR/SCR_SMCI.TE bit is 0, disabling serial transmission, the state of the TXDn pin can be set using the
SPTR.SPB2IO and SPTR.SPB2DT bits. With this approach, a TXDn pin can be placed in the mark state to transmit a
break.
Before setting the SCR/SCR_SMCI.TE bit to 1, enabling serial transmission, set the SPB2IO and SPB2DT bits to put the
communication line in the mark state (the state of 1), and change the TxDn pin using the I/O port function. To output a
break on data transmission, after setting the TXDn pin to output 0 by setting the SPB2IO and SPB2DT bits, change the
TXDn pin using the I/O port function and set the SCR/SCR_SMCI.TE bit to 0. When the SCR/SCR_SMCI.TE bit is set
to 0, the transmitter is initialized regardless of the current state of transmission.
32.14.5
Receive Error Flags and Transmit Operation in Clock Synchronous and Simple
SPI Modes
Transmission cannot start when a receive error flag (ORER) in SSR/SSR_FIFO is set to 1, even if data is written to TDR
or FTDRL*2. Be sure to set the receive error flags to 0 before starting transmission.
Note 1. The receive error flags cannot be set to 0 when serial reception is disabled by setting the RE bit in
SCR/SCR_SMCI to 0.
Note 2. Do not use the FTDRH register in simple SPI mode.
32.14.6
Restrictions on Clock Synchronous Transmission in Clock Synchronous and
Simple SPI Modes
When the external clock source is used as a synchronization clock, the following restrictions apply.
(1)
Start of transmission
Wait at least the following time from writing transmit data to TDR to the start of the external clock input:
1 PCLKA cycle + data output delay time for the slave (tDO) + setup time for the master (tSU). See Figure 32.78.
(2)
Continuous transmission
Write the next transmit data to TDR or TDRHL before the falling edge of the transmit clock for bit [7] (see Figure
32.78).
When updating TDR after bit [7] has started to transmit, update TDR while the synchronization clock is in the low-level
period, and set the high-level width of the transmit clock (bit [7]) to 4 PCLKA cycles or longer (see Figure 32.78).
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32. Serial Communications Interface (SCI)
Set t 1 PCLKA cycle + data output delay time for the slave (tDO) + setup time for the master (tSU)) before
transmission is started when the external clock is used.
Update TDR before bit [7] is started to transmit when continuous
transmission is performed on the external clock
Synchronous clock
(external clock)
t
Next frame of data
First frame of data
TDR
SCIn_TXI interrupt
flag (IELSRn.IR*1)
D0
Serial transmit data
D2
D1
D3
D4
D5
D6
D7
D0
D1
(1) Start of transmission and (2) Continuous transmission (a)
Set t 4 cycles of PCLKA if TDR is updated after bit [7] starts to transmit when continuous transmission is performed
on the external clock.
t
Synchronous clock
(external clock)
Next frame of data
Previous frame of data
TDR
SCIn_TXI interrupt
flag (IELSRn.IR*1)
Serial transmit data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D3
D2
(2) Continuous transmission (b)
Note 1.
See section 14, Interrupt Controller Unit (ICU) for information on the associated interrupt event number.
Figure 32.78
32.14.7
Restrictions on use of external clock in clock synchronous transmission
Restrictions on Using DMAC or DTC
During transmission or reception operations using the DMAC or DTC, do not set transfer data for the DMAC/DTC.
(1)
Writing data to TDR (FTDRHL)
(a)
Non-FIFO selected
Data can be written to TDR and TDRHL. However, if new data is written to TDR or TDRHL when transmit data remains
in TDR or TDRHL, the previous data in TDR and TDRHL is lost because it was not transferred to TSR yet. When using
DMAC or DTC, be sure to write transmit data to TDR or TDRHL in the SCIn_TXI interrupt request handling routine.
(b)
FIFO selected
It is possible to write data to the FTDRH and FTDRL registers when SCR.TE is 1. Confirm the amount of writable data
using the FDR.T[4:0] bits.
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(2)
32. Serial Communications Interface (SCI)
Reading data from RDR (FRDRHL)
When using the DMAC or DTC to read RDR and RDRHL, be sure to set the receive data full interrupt (SCIn_RXI) as
the activation source of the relevant SCI.
32.14.8
Notes on Starting Transfer
When transfer starts while the Interrupt Status flag (IELSRn.IR) in the ICU is 1, follow the procedure in this section to
clear interrupt requests before permitting operations (by setting the SCR/SCR_SMCI.TE or SCR/SCR_SMCI.RE bit to
1). For details on the Interrupt Status flag, see section 14, Interrupt Controller Unit (ICU).
1. Confirm that the transfer has stopped (the SCR/SCR_SMCI.TE or SCR/SCR_SMCI.RE bit is 0).
2. Set the associated interrupt enable bit (SCR/SCR_SMCI.TIE or SCR/SCR_SMCI.RIE) to 0.
3. Read the associated interrupt enable bit (SCR/SCR_SMCI.TIE or SCR/SCR_SMCI.RIE bit) to check that it actually
becomes 0.
4. Set the Interrupt Status flag, IELSRn.IR, in the ICU to 0.
32.14.9
External Clock Input in Clock Synchronous and Simple SPI Modes
In clock synchronous mode and simple SPI mode, the external clock (SCKn) must be input as follows:
High-pulse period, low-pulse period = 2 PCLKA cycles or more, period = 6 PCLKA cycles or more.
32.14.10
(1)
Limitations on Simple SPI Mode
Master mode
Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set in the
SPMR.CKPH and CKPOL bits when the SPMR.SSE bit is 1. This prevents the clock line from being placed in the
high-impedance state when the SCR.TE bit is set to 0 or unexpected edges from being generated on the clock line
when the SCR.TE bit changes from 0 to 1. When the SPMR.SSE bit is 0 in single master mode, pulling up or pulling
down the clock line is not required because the clock line is not placed in the high-impedance state even when the
SCR.TE bit is set to 0.
For the clock delay setting (SPMR.CKPH bit is 1), the receive data full interrupt (SCIn_RXI) is generated before
the final clock edge on the SCKn pin, as indicated in Figure 32.79. If the TE and RE bits in the SCR register become
0 before the final edge of the clock signal on the SCKn pin, the SCKn pin is placed in the high-impedance state, so
the width of the last clock pulse of the transfer clock is shortened. Additionally, an SCIn_RXI interrupt might lead
to the input signal on the SSn pin of a connected slave going to the high level before the final edge of the clock
signal on the SCKn pin, leading to incorrect operation of the slave.
In a multi-master configuration, the SCKn pin output goes to high-impedance while the input on the SSn pin is at
the low level if a mode fault error occurs while a character is being transferred, stopping supply of the clock signal
to the connected slave. Reset the connected slave to avoid misaligned bits when transfer is restarted.
SCKn
(CKPOL = 0)
SCKn
(CKPOL = 1)
RXDn
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
SCIn_RXI
interrupt source
Figure 32.79
(2)
Timing of SCIn_RXI interrupt in simple SPI mode with clock delay
Slave mode
Wait at least the following time from writing transmit data in the TDR register to the start of the external clock
input:
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32. Serial Communications Interface (SCI)
1 PCLKA cycle + data output delay for the slave (tDO) + setup time for the master (tSU).
Also, wait at least 5 PCLKA cycles from the input of the low level on the SSn pin to the start of the external clock
input.
Provide an external clock signal to the master for the data length for transfer
Control the input on the SSn pin before the start and after the end of data transfer
When the input level on the SSn pin changes from low to high while a character is being transferred, set the TE and
RE bits in the SCR register to 0 and, after restoring the settings, restart transfer of the first byte.
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33. IrDA Interface
33.
IrDA Interface
33.1
Overview
The IrDA interface sends and receives IrDA data communication waveforms in cooperation with SCI1, according to the
IrDA (Infrared Data Association) standard 1.0.
Enabling the IrDA function using the IRE bit in the IRCR register allows the encoding and decoding of the TXD1 and
RXD1 signals of the SCI1 to waveforms conforming to the IrDA standard 1.0 (IRTXD1 and IRRXD1 pins).
Connecting the waveforms to an infrared transmitter/receiver implements infrared data communication conforming to
the IrDA standard 1.0 system.
With the IrDA standard 1.0 system, data transfer can be started at 9,600 bps and the transfer rate can be changed
whenever necessary. Because the IrDA interface cannot change the transfer rate automatically, the transfer rate must be
changed through software.
Figure 33.1 shows the interaction between the IrDA interface and SCI1.
IrDA
SCI1
IRE bit = 0
TXD1/IRTXD1
Phase inverter
Pulse encoder
Phase inverter
Pulse decoder
IRE bit = 1
RXD1/IRRXD1
TXD1
IRE bit = 1
RXD1
IRE bit = 0
IRCR
Internal peripheral bus
Figure 33.1
Table 33.1
Interaction between the IrDA interface and SCI1
IrDA interface I/O pins
Pin name
I/O
Function
IRTXD1
Output
Data to be transmitted
IRRXD1
Input
Received data
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33.2
33. IrDA Interface
Register Descriptions
33.2.1
IrDA Control Register (IRCR)
Address(es): IRDA.IRCR 4007 0F00h
b7
b6
b5
b4
IRE
—
—
—
0
0
0
0
Value after reset:
b3
b2
IRTXINV IRRXINV
0
0
b1
b0
—
—
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
IRRXINV
IRRXD Polarity Switching
0: Use IRRXD input as received data as-is
1: Use IRRXD input as received data after the polarity is inverted.
R/W
b3
IRTXINV
IRTXD Polarity Switching
0: Output data to be transmitted to IRTXD as-is
1: Output data to be transmitted IRTXD after the polarity is inverted.
R/W
b6 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
IRE
IrDA Enable
0: Use serial input/output pins for normal serial communication
1: Use serial input/output pins for IrDA data communication.
R/W
Note:
The IRCR register values are retained in Sleep, Software Standby, and Deep Software Standby modes.
IRRXINV bit (IRRXD Polarity Switching)
The IRRXINV bit inverts the logic level of the IRRXD input. When inverted, the high-level pulse width is applied to the
low-level pulse width.
IRTXINV bit (IRTXD Polarity Switching)
The IRTXINV bit inverts the logic level of the IRTXD output. When inverted, the high-level pulse width is applied to the
low-level pulse width.
IRE bit (IrDA Enable)
The IRE bit configures the I/O pins for normal communication mode or IrDA data communication mode.
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33.3
33. IrDA Interface
Operation
33.3.1
IrDA Interface Setup Procedure
To set up IrDA interface operation:
1. Set the associated pins to IRTXD1 and IRRXD1 in the Pin Function Control Register (PmnPFS.PSEL = 00101b) of
the I/O ports function.
2. Specify the peripheral function in the Pin Function Control Register (PmnPFS.PMR = 1) of the I/O ports function.
3. Specify the IrDA function in the IRCR register.
4. Set the SCI1-related registers of the Serial Communications Interface (SCI).
33.3.2
Transmission
During transmission, the signals output from SCI1 (UART frames) are converted to IR frame data through the IrDA
interface (see Figure 33.2). When the IRCR.IRTXINV bit is 0 and serial data is 0, high-level pulses with 3/16 the width
of the bit rate (1-bit width period) are output (initial setting). The standard prescribes that the minimum high-level pulse
width must be 1.41 μs and the maximum high-level pulse width must be (3/16 + 2.5%) × bit rate or (3/16 × bit rate) +
1.08 μs. When the serial data is 1, no pulses are output.
UART frame
Data
Start bit
0
1
0
1
0
Stop bit
0
1
Transmission
1
0
1
Reception
IR frame
Data
Start bit
0
1
0
1
Bit period
Figure 33.2
33.3.3
0
Stop bit
0
1
1
0
1
Pulse width is 1.41 µs to the bit period × (3/16+2.5%)
or (the bit period × 3/16) + 1.08 µs
IrDA transmission and reception
Reception
During reception, IR frame data is converted to UART frame data through the IrDA interface and is input to SCI1.
Low-level data is input to SCI1 when the IRCR.IRRXINV bit is 0 and a high-level pulse is detected. High-level data is
input to SCI1 when no pulse is detected for a 1-bit period.
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33.4
33.4.1
33. IrDA Interface
Usage Notes
Settings for the Module-Stop Function
IrDA operation can be disabled or enabled using the Module Stop Control Register. IrDA is initially stopped after reset.
Releasing the module-stop state enables access to the registers. For details, see section 11, Low Power Modes.
33.4.2
Asynchronous Reference Clock for SCI1
The IrDA receives a clock with frequency 16 times the bit rate from SCI1 and operates in conjunction with SCI1.
When using the IrDA, set the SCI1.SEMR.ABCS bit to 0.
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.
I2C Bus Interface (IIC)
34.1
Overview
The MCU has a 3-channel I2C Bus Interface (IIC) module that conforms with and provides a subset of the NXP I2C bus
(inter-integrated circuit bus) interface functions. Table 34.1 lists the IIC specifications, Figure 34.1 shows a block
diagram, and Figure 34.2 shows an example of I/O pin connections to external circuits, with an I2C bus configuration.
Table 34.2 lists the I/O pins.
Table 34.1
IIC specifications (1 of 2)
Parameter
Specifications
Communications format
I2C bus format or SMBus format
Master or slave mode selectable
Automatic securing of the setup times, hold times, and bus-free times for the transfer rate.
Transfer rate
Fast-mode Plus supported, up to 1 Mbps
SCL clock
For master operation, the duty cycle of the SCL clock is selectable in the range from 4% to 96%
Issuing and detecting
conditions
Start, restart, and stop conditions are automatically generated
Start conditions (including restart conditions) and stop conditions are detectable.
Slave address
Configurable for up to three different slave addresses
7-bit and 10-bit address formats supported, including simultaneous use
General call addresses, device ID addresses, and SMBus host addresses detectable.
Acknowledgment
For transmission, automatic loading of the acknowledge bit.
Transfer of the next transmit data can be automatically suspended on detection of a not-acknowledge bit.
For reception, automatic transmission of the acknowledge bit.
If a wait between the 8th and 9th clock cycles is selected, software can control the value in the
acknowledge field in response to the received value.
Wait function
During reception, the following wait periods are available by holding the SCL clock low:
Waiting between the 8th and 9th clock cycles
Waiting between the 9th clock cycle and the 1st clock cycle of the next transfer.
SDA output delay
function
Output timing of transmitted data, including the acknowledge bit, can be delayed
Arbitration
For multi-master operation:
- SCL clock synchronization is possible when conflict occurs with the SCL signal from another master
- When issuing the start condition creates conflict on the bus, loss of arbitration is detected by testing for
mismatching between the internal signal for the SDA line and the level on the SDA line
- In master operation, loss of arbitration is detected by testing for mismatching between the signal on the
SDA line and the internal signal for the SDA line
Loss of arbitration because the start condition occurs while the bus is busy is detectable, to prevent the
issuing of double start conditions
Loss of arbitration is detectable on transfer of a not-acknowledge bit because the internal signal for the
SDA line and the level on the SDA line do not match
Loss of arbitration because mismatching of internal and line levels for data is detectable in slave
transmission
Timeout function
Internal detection of long-interval stops of the SCL clock
Noise cancellation
Digital noise filters for both the SCL and SDA signals
Programmable window for noise cancellation by the filters.
Interrupt sources
Transfer error or occurrence of events: arbitration detection, NACK, timeout, start or restart condition, or
stop condition)
Receive data full, including matching with a slave address
Transmit data empty, including matching with a slave address
Transmit end.
Module-stop function
Module-stop state can be set to reduce power consumption
IIC operating modes
Master transmit
Master receive
Slave transmit
Slave receive.
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
Table 34.1
IIC specifications (2 of 2)
Parameter
Specifications
Event link function
(output)
Transfer error or occurrence of events: arbitration detection, NACK, timeout, start or restart condition, or
stop condition
Receive data full, including matching with a slave address
Transmit data empty, including matching with a slave address
Transmit end.
Wakeup function*1
CPU can return from Software Standby mode using a wakeup event
Note 1. Only supported for IIC0. IIC1 and IIC2 are not supported.
PCLKB
PS
CKS[2:0]
ICMR1
BC[2:0]
FMPE
IIC (PCLKB/1 to PCLKB/128)
Output
control
SCLn
ICBRH
Transfer clock
generator
CLO
Noise
canceller
ICBRL
SCLE
SCLI
ICCR1
SCLn, SDAn
NFE
NF[1:0]
Transmission/
reception control
circuit
PS
IICRST
SDAI
ST, RS, SP
DLCS
ICCR2
BBSY, MST, TRS
WAIT, RDRFS
ICFER
SDA output delay control
SDDL[2:0]
ICMR2
ICMR3
ACKBT
ACKBR
ACK output circuit
ICDRT
SARU0
SARL0
SARU1
SARL1
SARU2
SARL2
Internal data bus
IIC, IIC/2
FMPE
NACKE
Output
control
SDAn
ICDRS
NACK decision/ACK
reception circuit
Address comparator
Noise
canceller
NF[1:0]
ICDRR
Arbitration decision
circuit
NFE
ICSR1
MALE, NALE, SALE
ICSER
Bus state decision
circuit
NACKF
TMOE
ICSR2
TMOS, TMOH, TMOL
Timeout circuit
TMOF
ICIER
Interrupt request
(IICn_TXI,IICn_TEI,IICn_RXI,IICn_EEI,IIC0_WUI)
Interrupt generator
Event output to ELC
(IICn_TXI,IICn_TEI,IICn_RXI,IICn_EEI)
Figure 34.1
IIC block diagram
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
Power supply for pull-up
SCLin
SCL
SCL
SDA
SDA
SCLout#
SDAin
SCLout#
SCLout#
SDAin
SDAin
SDAout#
SDAout#
SDA
SCLin
(Slave 2)
(Slave 1)
Figure 34.2
SCL
SCLin
SDA
(Master)
SCL
SDAout#
I/O pin connection to an external circuit (I2C bus configuration example)
The input level of the signals for IIC is CMOS when I2C bus is selected (ICMR3.SMBS = 0), or TTL when SMBus is
selected (ICMR3.SMBS = 1).
Table 34.2
IIC I/O pins
Channel
Pin name
I/O
Function
IIC0
SCL0
I/O
IIC0 serial clock I/O pin
SDA0
I/O
IIC0 serial data I/O pin
SCL1
I/O
IIC1 serial clock I/O pin
SDA1
I/O
IIC1 serial data I/O pin
SCL2
I/O
IIC2 serial clock I/O pin
SDA2
I/O
IIC2 serial data I/O pin
IIC1
IIC2
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.2
Register Descriptions
I2C Bus Control Register 1 (ICCR1)
34.2.1
Address(es): IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h, IIC2.ICCR1 4005 3200h
b7
b6
b5
ICE
IICRST
CLO
0
0
0
Value after reset:
b4
b3
SOWP SCLO
1
b2
b1
b0
SDAO
SCLI
SDAI
1
1
1
1
Bit
Symbol
Bit name
Description
R/W
b0
SDAI
SDA Line Monitor
0: SDAn line is low
1: SDAn line is high.
R
b1
SCLI
SCL Line Monitor
0: SCLn line is low
1: SCLn line is high.
R
b2
SDAO
SDA Output Control/Monitor
Read:
0: IIC drove SDAn pin low
1: IIC released SDAn pin.
Write:
0: Drive SDAn pin low through IIC
1: Release SDAn pin through IIC.
R/W
b3
SCLO
SCL Output Control/Monitor
Read:
0: IIC drove SCLn pin low
1: IIC released SCLn pin.
Write:
0: Drive SCLn pin low through IIC
1: Release SCLn pin through IIC.
Use an external pull-up resistor to drive the signal high.
R/W
b4
SOWP
SCLO/SDAO Write Protect
0: Write enable SCLO and SDAO bits
1: Write protect SCLO and SDAO bits.
This bit is read as 1.
R/W
b5
CLO
Extra SCL Clock Cycle Output
0: Do not output extra SCL clock cycle (default)
1: Output extra SCL clock cycle.
This bit clears automatically after one clock cycle is output.
R/W
b6
IICRST
IIC-Bus Interface Internal
Reset
0: Release IIC reset or internal reset
1: Initiate IIC reset or internal reset.
This setting clears the bit counter and the SCLn/SDAn output latch.
R/W
b7
ICE
IIC-Bus Interface Enable
0: Disable (SCLn and SDAn pins in inactive state)
1: Enable (SCLn and SDAn pins in active state).
Used in combination with the IICRST bit to select either IIC or
internal reset.
R/W
SDAO bit (SDA Output Control/Monitor) and SCLO bit (SCL Output Control/Monitor)
The SDAO and SCLO bits directly control the SDAn and SCLn signals output from the IIC.
When writing to these bits, also write 0 to the SOWP bit. Setting these bits results in input to the IIC by the input buffer.
When slave mode is selected, a start condition might be detected and the bus might be released, depending on the bit
settings.
Do not rewrite these bits during a start condition, stop condition, restart condition, or during transmission, or reception.
Operation after rewriting under the specified conditions is not guaranteed. When reading these bits, the state of signals
output from the IIC can be read.
CLO bit (Extra SCL Clock Cycle Output)
The CLO bit allows the output of an extra SCL clock cycle for debugging or error processing. Normally, set this bit to 0.
Setting this bit to 1 in a normal communication state causes a communication error. For details on this function, see
section 34.12.2, Extra SCL Clock Cycle Output Function.
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IICRST bit (IIC-Bus Interface Internal Reset)
The IICRST bit initiates an internal state reset of the IIC. Setting this bit to 1 initiates an IIC reset or internal reset.
Whether an IIC reset or internal reset is initiated is determined by setting this bit in combination with the ICE bit.
Table 34.3 lists the IIC resets.
The IIC reset initializes all registers except ICCR1.ICE and ICCR1.IICRST bits, and internal states of the IIC. In
addition to the internal states of the IIC, the internal reset initializes the following:
Bit counter (ICMR1.BC[2:0] bits)
I2C Bus Shift Register (ICDRS)
I2C Bus Status Registers (ICSR1 and ICSR2)
SDAO and SCLO Output Control/Monitor (ICCR1.SCLO and ICCR1.SDAO bits)
I2C Bus Control Register 2 (except ICCR2.BBSY bit).
For the reset conditions of each register, see section 34.15, State of Registers when Issuing each Condition.
An internal reset initiated with the IICRST bit set to 1 during operation (with the ICE bit set to 1) resets the internal states
of the IIC without initializing the port settings and the control and setting registers of the IIC when the bus or IIC hangs
up because of a communication error. If the IIC hangs up in a low level output state, resetting the internal states cancels
the low level output state and releases the bus with the SCLn pin and SDAn pin at high impedance.
Note:
If an internal reset is initiated using the IICRST bit for a bus hang-up that occurs during communication with the
master device in slave mode, the slave and master devices might enter different states, because the bit counter
information differs. For this reason, do not initiate an internal reset in slave mode. Initiate recovery processing
from the master device. If an internal reset is necessary because the IIC hangs with the SCLn line in a low level
output state in slave mode, initiate an internal reset, and then issue a restart condition from the master device, or
issue a stop condition and resume communication from the start condition. If communication is restarted by
initiating a reset solely in the slave device without issuing a start or restart condition from the master device,
synchronization is lost because the master and slave devices operate asynchronously.
Table 34.3
IIC resets
IICRST
ICE
State
Specifications
1
0
IIC reset
Resets all registers except ICCR1.ICE and ICCR1.IICRST bits, and the internal states of
the IIC
1
Internal reset
Resets the following:
ICMR1.BC[2:0] bits
ICSR1, ICSR2, ICDRS registers
SDAO and SCLO Output Control/Monitor (ICCR1.SCLO and ICCR1.SDAO bits)
I2C Bus Control Register 2 (except ICCR2.BBSY bit)
Internal states of the IIC.
ICE bit (IIC-Bus Interface Enable)
The ICE bit selects the active or inactive state of the SCLn and SDAn pins. It can also be combined with the IICRST bit
to initiate two types of resets. See Table 34.3 for the reset types.
Set the ICE bit to 1 when using the IIC. The SCLn and SDAn pins are placed in the active state when the ICE bit is set to
1. Set the ICE bit to 0 when the IIC is not used. The SCLn and SDAn pins are placed in the inactive state when the ICE
bit is set to 0. Do not assign the SCLn or SDAn pin to the IIC when setting up the pin function control. Slave address
comparison is performed if the pins are assigned to the IIC.
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I2C Bus Control Register 2 (ICCR2)
34.2.2
Address(es): IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h, IIC2.ICCR2 4005 3201h
b7
b6
b5
b4
b3
b2
b1
b0
BBSY
MST
TRS
—
SP
RS
ST
—
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b1
ST
Start Condition Issuance
Request
0: Do not issue a start condition request
1: Issue a start condition request.
R/W
b2
RS
Restart Condition Issuance
Request
0: Do not issue a restart condition request
1: Issue a restart condition request.
R/W
b3
SP
Stop Condition Issuance
Request
0: Do not issue a stop condition request
1: Issue a stop condition request.
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
TRS
Transmit/Receive Mode
0: Receive mode
1: Transmit mode.
R/W*1
b6
MST
Master/Slave Mode
0: Slave mode
1: Master mode.
R/W*1
b7
BBSY
Bus Busy Detection Flag
0: I2C bus released (bus free state)
1: I2C bus occupied (bus busy state).
R
Note 1.
The MST and TRS bits can be written to when the ICMR1.MTWP bit is set to 1.
ST bit (Start Condition Issuance Request)
The ST bit requests transition to master mode and triggers a start condition.
When this bit is set to 1, a start condition is issued when the BBSY flag is set to 0 (bus free state). For details on issuing
a start condition, see section 34.11, Start, Restart, and Stop Condition Issuing Function.
[Setting condition]
When 1 is written to the ST bit.
[Clearing conditions]
When 0 is written to the ST bit
When a start condition is issued (a start condition is detected)
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
Note:
Set the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). Arbitration
might be lost if the ST bit is set to 1 (start condition request) when the BBSY flag is 1 (bus busy state).
RS bit (Restart Condition Issuance Request)
The RS bit requests that a restart condition be issued in master mode.
When this bit is set to 1 to request a restart condition, a restart condition is issued when the BBSY flag is set to 1 (bus
busy state) and the MST bit is set to 1 (master mode). For details on issuing a restart condition, see section 34.11, Start,
Restart, and Stop Condition Issuing Function.
[Setting condition]
When 1 is written to the RS bit with the BBSY flag in ICCR2 set to 1.
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[Clearing conditions]
When 0 is written to the RS bit
When a restart condition is issued (a start condition is detected)
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
Note:
Note:
Do not set the RS bit to 1 while issuing a stop condition.
If 1 (restart condition request) is written to the RS bit in slave mode, the restart condition is not issued, but the RS
bit remains set to 1. If the operating mode changes to master mode without the bit being cleared, a restart
condition might be issued.
SP bit (Stop Condition Issuance Request)
The SP bit requests that a stop condition be issued in master mode.
When this bit is set to 1, a stop condition is issued when the BBSY flag is set to 1 (bus busy state) and the MST bit is set
to 1 (master mode). For details on this function, see section 34.11, Start, Restart, and Stop Condition Issuing Function.
[Setting condition]
When 1 is written to the SP bit with both the BBSY flag and the MST bit in ICCR2 set to 1.
[Clearing conditions]
When 0 is written to the SP bit
When a stop condition is issued (a stop condition is detected)
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When a start condition and a restart condition are detected
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
Note:
Note:
Writing to the SP bit is not possible while the BBSY flag is 0 (bus free state).
Do not set the SP bit to 1 while a restart condition is being issued.
TRS bit (Transmit/Receive Mode)
The TRS bit indicates transmit or receive mode.
The IIC is in receive mode when the TRS bit is 0 and in transmit mode when the bit is 1. The combination of the TRS bit
and the MST bit indicates the operating mode of the IIC.
The value of the TRS bit automatically changes to 1 for transmit mode or 0 for receive mode when a start condition is
issued or detected and the R/W# bit is set. Although writing to the TRS bit is possible when the MTWP bit in ICMR1 is
set to 1, writing to this bit is not required during normal usage.
[Setting conditions]
When a start condition is issued normally because of a start condition request (when a start condition is detected
with the ST bit set to 1)
When a restart condition is issued normally because of a restart condition request (when a restart condition is
detected with the RS bit set to 1)
When the R/W# bit appended to the slave address is set to 0 in master mode
When the address received in slave mode matches the address enabled in ICSER, with the R/W# bit set to 1
When 1 is written to the TRS bit with the MTWP bit in ICMR1 set to 1.
[Clearing conditions]
When a stop condition is detected
When the AL (arbitration-lost) flag in ICSR2 is set to 1
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When the R/W# bit appended to the slave address is set to 1 in master mode
In slave mode, on a match between the received address and the address enabled in ICSER when the value of the
received R/W# bit is 0, including when the received address is the general call address
In slave mode, when a restart condition is detected (a start condition is detected with ICCR2.BBSY = 1 and
ICCR2.MST = 0)
When 0 is written to the TRS bit with the MTWP bit in ICMR1 set to 1
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
MST bit (Master/Slave Mode)
The MST bit indicates master or slave mode. The IIC is in slave mode when the MST bit is set to 0 and is in master mode
when the bit is set to 1. The combination of the MST bit and the TRS bit indicates the operating mode of the IIC.
The value of the MST bit automatically changes to 1 for master mode or 0 for slave mode when a start condition is
issued, or when a stop condition is issued or detected. Although writing to the MST bit is possible when the MTWP bit in
ICMR1 is set to 1, writing to this bit is not necessary during normal usage.
[Setting conditions]
When a start condition is issued normally because of a start condition request (when a start condition is detected
with the ST bit set to 1)
When 1 is written to the MST bit with the MTWP bit in ICMR1 set to 1.
[Clearing conditions]
When a stop condition is detected
When the AL (arbitration-lost) flag in ICSR2 is set to 1
When 0 is written to the MST bit with the MTWP bit in ICMR1 set to 1
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
BBSY flag (Bus Busy Detection Flag)
The BBSY flag indicates whether the I2C bus is occupied (bus busy state) or released (bus free state).
The flag is set to 1 when the SDAn line changes from high to low when the SCLn line is high, assuming that a start
condition was issued.
The flag is set to 0 when the SDAn line changes from low to high with the SCLn line high, if the bus free time (ICBRL
setting) start condition is not detected, assuming that a stop condition was issued.
[Setting condition]
When a start condition is detected.
[Clearing conditions]
When the bus free time (ICBRL setting) start condition is not detected after detecting a stop condition
When 1 is written to the IICRST bit in ICCR1 with the ICE bit in ICCR1 set to 0 (IIC reset).
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I2C Bus Mode Register 1 (ICMR1)
34.2.3
Address(es): IIC0.ICMR1 4005 3002h, IIC1.ICMR1 4005 3102h, IIC2.ICMR1 4005 3202h
b7
b6
MTWP
Value after reset:
0
b5
b4
CKS[2:0]
0
0
b3
b2
BCWP
0
1
b1
b0
BC[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
BC[2:0]
Bit Counter
b2
R/W*1
b3
BCWP
BC Write Protect
0: Write enable BC[2:0] bits
1: Write protect BC[2:0] bits.
This bit is read as 1.
R/W*1
b6 to b4
CKS[2:0]
Internal Reference Clock Select
Select the internal reference clock source (IIC) for the IIC.
R/W
0
0
0
0
1
1
1
1
b6
0
0
0
0
1
1
1
1
b7
Note 1.
MTWP
MST/TRS Write Protect
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: 9 bits
1: 2 bits
0: 3 bits
1: 4 bits
0: 5 bits
1: 6 bits
0: 7 bits
1: 8 bits.
b4
0: PCLKB clock
1: PCLKB/2 clock
0: PCLKB/4 clock
1: PCLKB/8 clock
0: PCLKB/16 clock
1: PCLKB/32 clock
0: PCLKB/64 clock
1: PCLKB/128 clock.
0: Write protect MST and TRS bits in ICCR2
1: Write enable MST and TRS bits in ICCR2.
R/W
Rewrite the BC[2:0] bits and set the BCWP bit to 0 at the same time.
BC[2:0] bits (Bit Counter)
The BC[2:0] bits function as a counter that indicates the number of bits remaining to be transferred on detection of a
rising edge on the SCLn line. Although BC[2:0] are read/write bits, it is not required to access these bits under normal
conditions.
To write to these bits, specify the number of bits to be transferred plus one, for an additional acknowledge bit, between
transferred frames when the SCLn line is at a low level.
The value in the BC[2:0] bits returns to 000b at the end of a data transfer, including the acknowledge bit, or when a start
or restart condition is detected.
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I2C Bus Mode Register 2 (ICMR2)
34.2.4
Address(es): IIC0.ICMR2 4005 3003h, IIC1.ICMR2 4005 3103h, IIC2.ICMR2 4005 3203h
b7
b6
DLCS
Value after reset:
0
b5
b4
SDDL[2:0]
0
0
b3
—
0
0
b2
b1
b0
TMOH TMOL
1
TMOS
1
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOS
Timeout Detection Time Select
0: Select long mode
1: Select short mode.
R/W
b1
TMOL
Timeout L Count Control
0: Disable count while SCLn line is low
1: Enable count while SCLn line is low.
R/W
b2
TMOH
Timeout H Count Control
0: Disable count while SCLn line is high
1: Enable count while SCLn line is high.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6 to b4
SDDL[2:0]
SDA Output Delay Counter
When ICMR2.DLCS = 0 (IIC)
R/W
b6
b4
0 0 0: No output delay
0 0 1: 1 IIC cycle
0 1 0: 2 IIC cycles
0 1 1: 3 IIC cycles
1 0 0: 4 IIC cycles
1 0 1: 5 IIC cycles
1 1 0: 6 IIC cycles
1 1 1: 7 IIC cycles.
When ICMR2.DLCS = 1 (IIC/2)
b6
0
0
0
0
1
1
1
1
b7
Note 1.
DLCS
SDA Output Delay Clock Source
Select
0
0
1
1
0
0
1
1
b4
0: No output delay
1: 1 or 2 IIC cycles
0: 3 or 4 IIC cycles
1: 5 or 6 IIC cycles
0: 7 or 8 IIC cycles
1: 9 or 10 IIC cycles
0: 11 or 12 IIC cycles
1: 13 or 14 IICcycles.
0: Select internal reference clock (IIC) as clock source for SDA
output delay counter
1: Select internal reference clock divided by 2 (IIC/2) as clock
source for SDA output delay counter.*1
R/W
The setting DLCS = 1 (IIC/2) is only valid when SCL is low. When SCL is high, the DLCS = 1 setting becomes invalid and the
clock source becomes the internal reference clock (IIC).
TMOS bit (Timeout Detection Time Select)
The TMOS bit selects long or short mode for the timeout detection time when the timeout function is enabled
(ICFER.TMOE = 1).
When this bit is set to 0, long mode is selected. When it is set to 1, short mode is selected.
In long mode, the timeout detection internal counter functions as a 16 bit-counter. In short mode, the counter functions as
a 14-bit counter. While the SCLn line is in the state that enables this counter as specified in the TMOH and TMOL bits,
the counter counts up in synchronization with the internal reference clock (IIC) as a count source.
For details on this function, see section 34.12.1, Timeout Function.
TMOL bit (Timeout L Count Control)
The TMOL bit enables or disables up-counting on the internal counter of the timeout function while the SCLn line is
held low and the timeout function is enabled (ICFER.TMOE = 1).
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TMOH bit (Timeout H Count Control)
The TMOH bit enables or disables up-counting on the internal counter of the timeout function while the SCLn line is
held high and the timeout function is enabled (ICFER.TMOE = 1).
SDDL[2:0] bits (SDA Output Delay Counter)
The SDDL[2:0] bits can be used to delay the SDA output. This counter works with the clock source selected in the DLCS
bit. This setting can be used for all types of SDA output, including the transmission of the acknowledge bit.
Set the SDA output delay to meet the I2C bus standard for the data enable time/acknowledge enable time,*1 or the
SMBus standard, within [data hold time (300 ns or more + the SCL-clock low-level period) - the data setup time (250
ns)]. If a value outside the standard is set, communication between the devices might malfunction or falsely indicate a
start or stop condition, depending on the bus state.
For details on this function, see section 34.5, SDA Output Delay Function.
Note 1. Data enable time/acknowledge enable time
3,450 ns for up to 100 kbps: Standard-mode (Sm)
900 ns for up to 400 kbps: Fast-mode (Fm)
450 ns for up to 1 Mbps: Fast-mode Plus (Fm+).
I2C Bus Mode Register 3 (ICMR3)
34.2.5
Address(es): IIC0.ICMR3 4005 3004h, IIC1.ICMR3 4005 3104h, IIC2.ICMR3 4005 3204h
b7
SMBS
Value after reset:
0
b6
b5
b4
b3
b2
b1
WAIT RDRFS ACKW ACKBT ACKBR
P
0
0
0
0
0
b0
NF[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
NF[1:0]
Noise Filter Stage Select
b1 b0
R/W
b2
ACKBR
Receive Acknowledge
0: 0 received as the acknowledge bit (ACK reception)
1: 1 received as the acknowledge bit (NACK reception).
R
b3
ACKBT
Transmit Acknowledge
0: Send 0 as the acknowledge bit (ACK transmission)
1: Send 1 as the acknowledge bit (NACK transmission).
R/W*1
b4
ACKWP
ACKBT Write Protect
0: Write protect ACKBT bit
1: Write enable ACKBT bit.
R/W*1
b5
RDRFS
RDRF Flag Set Timing
Select
0: Set the RDRF flag on the rising edge of the 9th SCL clock cycle. The
SCLn line is not held low on the falling edge of the 8th clock cycle
1: Set the RDRF flag on the rising edge of the 8th SCL clock cycle. The
SCLn line is held low on the falling edge of the 8th clock cycle.
Low-hold is released by writing to ACKBT.
R/W*2
b6
WAIT
WAIT
0: No wait. SCLn us not helps low during the period between 9th clock
cycle and 1st clock cycle
1: Wait. SCLn is held low during the period between 9th clock cycle and 1st
clock cycle.
Low-hold is released by reading ICDRR.
R/W*2
b7
SMBS
SMBus/IIC-Bus Select
0: Select I2C bus
1: Select SMBus.
R/W
Note 1.
Note 2.
0 0: Filter out noise of up to 1 IIC cycle (single-stage filter)
0 1: Filter out noise of up to 2 IIC cycles (2-stage filter)
1 0: Filter out noise of up to 3 IIC cycles (3-stage filter)
1 1: Filter out noise of up to 4 IIC cycles (4-stage filter).
Write to the ACKBT bit only while the ACKWP bit is already 1. If the application writes 1 to both the ACKWP and ACKBT bits at
the same time, the ACKBT bit is not set to 1.
The WAIT and RDRFS bits are only valid in receive mode (invalid in transmit mode).
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NF[1:0] bits (Noise Filter Stage Select)
The NF[1:0] bits select the number of stages in the digital noise filter.
For details on this function, see section 34.6, Digital Noise Filter Circuits.
Note:
Set the noise range to be filtered out by the noise filter within a range less than the SCLn line high-level period or
low-level period. If the noise range is set to a value of [SCL clock width: high-level period or low-level period,
whichever is shorter] - [1.5 internal reference clock (IIC) cycles + analog noise filter: 120 ns (reference values)]
or more, the SCL clock is regarded as noise by the noise filter function of the IIC, which might prevent the IIC
from operating normally.
ACKBR bit (Receive Acknowledge)
The ACKBR bit stores the acknowledge bit information received from the receive device in transmit mode.
[Setting condition]
When 1 is received as the acknowledge bit with the TRS bit in ICCR2 set to 1.
[Clearing conditions]
When 0 is received as the acknowledge bit with the TRS bit in ICCR2 set to 1
When 1 is written to the IICRST bit in ICCR1 while the ICE bit in ICCR1 is 0 (IIC reset).
ACKBT bit (Transmit Acknowledge)
The ACKBT bit sets the acknowledge bit to be sent in receive mode.
[Setting condition]
When 1 is written to this bit with the ACKWP bit set to 1.
[Clearing conditions]
When 0 is written to this bit with the ACKWP bit set to 1
When stop condition issuance is detected with the SP bit in ICCR2 set to 1
When 1 is written to the IICRST bit in ICCR1 while the ICE bit in ICCR1 is 0 (IIC reset).
ACKWP bit (ACKBT Write Protect)
The ACKWP bit controls write enabling of the ACKBT bit.
RDRFS bit (RDRF Flag Set Timing Select)
The RDRFS bit selects the RDRF flag set timing in receive mode and also selects whether to hold the SCLn line low on
the falling edge of the 8th SCL clock cycle.
When the RDRFS bit is 0, the SCLn line is not held low on the falling edge of the 8th SCL clock cycle, and the RDRF
flag is set to 1 on the rising edge of the 9th SCL clock cycle.
When the RDRFS bit is 1, the RDRF flag is set to 1 on the rising edge of the 8th SCL clock cycle, and the SCLn line is
held low on the falling edge of the 8th SCL clock cycle. The low-hold of the SCLn line is released by a write to the
ACKBT bit.
After data is received with this setting, the SCLn line is automatically held low before the acknowledge bit is sent. This
enables processing to send ACK (ACKBT = 0) or NACK (ACKBT = 1), based on the receive data.
WAIT bit (WAIT)
The WAIT bit controls whether to forcefully hold the period between the 9th SCL clock cycle and the 1st SCL clock cycle
low until the receive data buffer (ICDRR) is completely read each time a single-byte data is received in receive mode.
When the WAIT bit is 0, the receive operation is continued without holding the period between the 9th and the 1st SCL
clock cycle low. When both the RDRFS and WAIT bits are 0, continuous receive operation is enabled with the double
buffer.
When the WAIT bit is 1, the SCLn line is held low from the falling edge of the 9th clock cycle until the ICDRR value is
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read each time a single-byte data is received. This enables the receive operation in byte units.
Note:
When the value of the WAIT bit is to be read, be sure to first read the ICDRR.
SMBS bit (SMBus/IIC-Bus Select)
Setting the SMBS bit to 1 selects the SMBus and enables the HOAE bit in ICSER.
I2C Bus Function Enable Register (ICFER)
34.2.6
Address(es): IIC0.ICFER 4005 3005h, IIC1.ICFER 4005 3105h, IIC2.ICFER 4005 3205h
Value after reset:
b7
b6
b5
FMPE
SCLE
NFE
0
1
1
b4
b3
NACKE SALE
1
0
b2
b1
b0
NALE
MALE
TMOE
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOE
Timeout Function Enable
0: Disable
1: Enable.
R/W
b1
MALE
Master Arbitration-Lost
Detection Enable
0: Disable the arbitration-lost detection function and disable automatic
clearing of the MST and TRS bits in ICCR2 when arbitration is lost
1: Enable the arbitration-lost detection function and enable automatic
clearing of the MST and TRS bits in ICCR2 when arbitration is lost.
R/W
b2
NALE
NACK Transmission
Arbitration-Lost Detection
Enable
0: Disable
1: Enable.
R/W
b3
SALE
Slave Arbitration-Lost
Detection Enable
0: Disable
1: Enable.
R/W
b4
NACKE
NACK Reception Transfer
Suspension Enable
0: Do not suspend transfer operation during NACK reception (disable
transfer suspension)
1: Suspend transfer operation during NACK reception (enable transfer
suspension).
R/W
b5
NFE
Digital Noise Filter Circuit
Enable
0: Do not use the digital noise filter circuit
1: Use the digital noise filter circuit.
R/W
b6
SCLE
SCL Synchronous Circuit
Enable
0: Do not use the SCL synchronous circuit
1: Use the SCL synchronous circuit.
R/W
b7
FMPE*1
Fast-Mode Plus Enable
0: Do not use the Fm+ slope control circuit for the SCLn and SDAn pins
1: Use the Fm+ slope control circuit for the SCLn and SDAn pins.
R/W
Note 1.
The Fast-mode Plus enable bit (FMPE) is supported only by IIC0 (SCL0-A, SDA0-A). Bit [7] is reserved in IIC1 and IIC2.
TMOE bit (Timeout Function Enable)
The TMOE bit enables or disables the timeout function.
For details on this function, see section 34.12.1, Timeout Function.
MALE bit (Master Arbitration-Lost Detection Enable)
The MALE bit specifies whether to use the arbitration-lost detection function in master mode. For normal operation, set
this bit to 1.
NALE bit (NACK Transmission Arbitration-Lost Detection Enable)
The NALE bit specifies whether to cause loss of arbitration when ACK is detected during the transmission of NACK in
receive mode, for example, when slaves with the same address exist on the bus, or when two or more masters select the
same slave device simultaneously with a different number of receive bytes.
SALE bit (Slave Arbitration-Lost Detection Enable)
The SALE bit specifies whether to cause loss of arbitration when a value different from the value being transmitted is
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detected on the bus in slave transmit mode, for example, when slaves with the same address exist on the bus, or when a
mismatch with the transmit data occurs because of noise.
NACKE bit (NACK Reception Transfer Suspension Enable)
The NACKE bit specifies whether to continue or discontinue the transfer operation when NACK is received from the
slave device in transmit mode. For normal operation, set this bit to 1.
When NACK is received with the NACKE bit set to 1, the next transfer operation is suspended. When the NACKE bit is
0, the next transfer operation is continued regardless of the received acknowledge content.
For details, see section 34.9.2, NACK Reception Transfer Suspension Function.
SCLE bit (SCL Synchronous Circuit Enable)
The SCLE bit specifies whether to synchronize the SCL clock with the SCL input clock. For normal operation, set this
bit to 1.
When the SCLE bit is set to 0 (no SCL synchronous circuit used), the IIC does not synchronize the SCL clock with the
SCL input clock. With this setting, the IIC outputs the SCL clock with the transfer rate set in ICBRH and ICBRL,
regardless of the SCLn line state. For this reason, if the bus load of the I2C bus line is much larger than the specification
value, or if the SCL clock output overlaps in multiple masters, a short-cycle SCL clock that does not meet the
specification might be output. When no SCL synchronous circuit is used, it also affects the issuance of the start, restart,
and stop conditions, and the continuous output of extra SCL clock cycles.
Do not set this bit to 0 except when checking the output of the set transfer rate.
FMPE bit (Fast-Mode Plus Enable)
The FMPE bit specifies whether to use a slope control circuit for Fast-mode Plus (Fm+).
When this bit is set to 1, a slope control circuit conforming to the I2C bus Fast-mode Plus (Fm+) standard (tof) is
selected. When this bit is set to 0, a slope control circuit conforming to the I2C bus Standard-mode (Sm) and Fast-mode
(Fm) standards (tof) is selected.
Set this bit to 1 when using transmission rates up to 1 Mbps (Fast-mode Plus (Fm+) standard). Set it to 0 when using
other transmission rates (up to 100 kbps (Sm) or up to 400 kbps (Fm)) or for SMBus (10 to 100 kbps).
I2C Bus Status Enable Register (ICSER)
34.2.7
Address(es): IIC0.ICSER 4005 3006h, IIC1.ICSER 4005 3106h, IIC2.ICSER 4005 3206h
b7
b6
b5
b4
HOAE
—
DIDE
—
0
0
0
0
Value after reset:
b3
b2
b1
b0
GCAE SAR2E SAR1E SAR0E
1
0
0
1
Bit
Symbol
Bit name
Description
R/W
b0
SAR0E
Slave Address Register 0 Enable
0: Disable slave address in SARL0 and SARU0
1: Enable slave address in SARL0 and SARU0.
R/W
b1
SAR1E
Slave Address Register 1 Enable
0: Disable slave address in SARL1 and SARU1
1: Enable slave address in SARL1 and SARU1.
R/W
b2
SAR2E
Slave Address Register 2 Enable
0: Disable slave address in SARL2 and SARU2
1: Enable slave address in SARL2 and SARU2.
R/W
b3
GCAE
General Call Address Enable
0: Disable general call address detection
1: Enable general call address detection.
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
DIDE
Device ID Address Detection
Enable
0: Disable device ID address detection
1: Enable device ID address detection.
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
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Bit
Symbol
Bit name
Description
R/W
b7
HOAE
Host Address Enable
0: Disable host address detection
1: Enable host address detection.
R/W
SARyE bit (Slave Address Register y Enable) (y = 0 to 2)
The SARyE bit enables or disables the received slave address and the slave address set in SARLy and SARUy.
When this bit is set to 1, the slave address set in SARLy and SARUy is enabled and is compared with the received slave
address. When this bit is set to 0, the slave address set in SARLy and SARUy is disabled and is ignored even if it matches
the received slave address.
GCAE bit (General Call Address Enable)
The GCAE bit specifies whether to ignore the general call address (0000 000b + 0 [W]: All 0) when it is received.
When this bit is set to 1, if the received slave address matches the general call address, the IIC recognizes the received
slave address as the general call address independently of the slave addresses set in SARLy and SARUy (y = 0 to 2), and
performs the data receive operation. When this bit is set to 0, the received slave address is ignored even if it matches the
general call address.
DIDE bit (Device ID Address Detection Enable)
The DIDE bit specifies whether to recognize and execute the device ID address when a device ID (1111 100b) is received
in the first frame after a start or restart condition is detected.
When this bit is set to 1, if the received first frame matches the device ID, the IIC recognizes that the device ID address
was received. When the next R/W# bit is 0 (W), the IIC recognizes the second and the subsequent frames as slave
addresses and continues the receive operation. When this bit is set to 0, the IIC ignores the received first frame even if it
matches the device ID address, and recognizes the first frame as a normal slave address.
For details on the device ID function, see section 34.7.3, Device ID Address Detection.
HOAE bit (Host Address Enable)
The HOAE bit specifies whether to ignore the received host address (0001 000b) when the SMBS bit in ICMR3 is 1.
When this bit is set to 1 while the SMBS bit in ICMR3 is 1, if the received slave address matches the host address, the
IIC recognizes the received slave address as the host address independently of the slave addresses set in SARLy and
SARUy (y = 0 to 2), and performs the receive operation.
When the SMBS bit in ICMR3 or the HOAE bit is set to 0, the received slave address is ignored even if it matches the
host address.
I2C Bus Interrupt Enable Register (ICIER)
34.2.8
Address(es): IIC0.ICIER 4005 3007h, IIC1.ICIER 4005 3107h, IIC2.ICIER 4005 3207h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TIE
TEIE
RIE
NAKIE
SPIE
STIE
ALIE
TMOIE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOIE
Timeout Interrupt Request Enable
0: Disable timeout interrupt (TMOI) request
1: Enable timeout interrupt (TMOI) request.
R/W
b1
ALIE
Arbitration-Lost Interrupt Request
Enable
0: Disable arbitration-lost interrupt (ALI) request
1: Enable arbitration-lost interrupt (ALI) request.
R/W
b2
STIE
Start Condition Detection Interrupt
Request Enable
0: Disable start condition detection interrupt (STI) request
1: Enable start condition detection interrupt (STI) request.
R/W
b3
SPIE
Stop Condition Detection Interrupt
Request Enable
0: Disable stop condition detection interrupt (SPI) request
1: Enable stop condition detection interrupt (SPI) request.
R/W
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Bit
Symbol
Bit name
Description
R/W
b4
NAKIE
NACK Reception Interrupt Request
Enable
0: Disable NACK reception interrupt (NAKI) request
1: Enable NACK reception interrupt (NAKI) request.
R/W
b5
RIE
Receive Data Full Interrupt Request
Enable
0: Disable receive data full interrupt (IICn_RXI) request
1: Enable receive data full interrupt (IICn_RXI) request.
R/W
b6
TEIE
Transmit End Interrupt Request
Enable
0: Disable transmit end interrupt (IICn_TEI) request
1: Enable transmit end interrupt (IICn_TEI) request.
R/W
b7
TIE
Transmit Data Empty Interrupt
Request Enable
0: Disable transmit data empty interrupt (IICn_TXI) request
1: Enable transmit data empty interrupt (IICn_TXI) request.
R/W
TMOIE bit (Timeout Interrupt Request Enable)
The TMOIE bit enables or disables timeout interrupt (TMOI) requests when the TMOF flag in ICSR2 is 1. To cancel a
TMOI interrupt request, set the TMOF flag or the TMOIE bit to 0.
ALIE bit (Arbitration-Lost Interrupt Request Enable)
The ALIE bit enables or disables arbitration-lost interrupt (ALI) requests when the AL flag in ICSR2 is 1. To cancel an
ALI interrupt request, set the AL flag or the ALIE bit to 0.
STIE bit (Start Condition Detection Interrupt Request Enable)
The STIE bit enables or disables start condition detection interrupt (STI) requests when the START flag in ICSR2 is 1.
To cancel an STI interrupt request, set the START flag or the STIE bit to 0.
SPIE bit (Stop Condition Detection Interrupt Request Enable)
The SPIE bit enables or disables stop condition detection interrupt (SPI) requests when the STOP flag in ICSR2 is 1. To
cancel an SPI interrupt request, set the STOP flag or the SPIE bit to 0.
NAKIE bit (NACK Reception Interrupt Request Enable)
The NAKIE bit enables or disables NACK reception interrupt (NAKI) requests when the NACKF flag in ICSR2 is 1. To
cancel an NAKI interrupt request, set the NACKF flag or the NAKIE bit to 0.
RIE bit (Receive Data Full Interrupt Request Enable)
The RIE bit enables or disables receive data full interrupt (IICn_RXI) requests when the RDRF flag in ICSR2 is 1.
TEIE bit (Transmit End Interrupt Request Enable)
The TEIE bit enables or disables transmit end interrupt (IICn_TEI) requests when the TEND flag in ICSR2 is 1. To
cancel an IICn_TEI interrupt request, set the TEND flag or the TEIE bit to 0.
TIE bit (Transmit Data Empty Interrupt Request Enable)
The TIE bit enables or disables transmit data empty interrupt (IICn_TXI) requests when the TDRE flag in ICSR2 is 1.
I2C Bus Status Register 1 (ICSR1)
34.2.9
Address(es): IIC0.ICSR1 4005 3008h, IIC1.ICSR1 4005 3108h, IIC2.ICSR1 4005 3208h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
HOA
—
DID
—
GCA
AAS2
AAS1
AAS0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
AAS0
Slave Address 0 Detection Flag
0: Slave address 0 not detected
1: Slave address 0 detected.
R/(W)
*1
b1
AAS1
Slave Address 1 Detection Flag
0: Slave address 1 not detected
1: Slave address 1 detected.
R/(W)
*1
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Bit
Symbol
Bit name
Description
R/W
b2
AAS2
Slave Address 2 Detection Flag
0: Slave address 2 not detected
1: Slave address 2 detected.
R/(W)
*1
b3
GCA
General Call Address Detection
Flag
0: General call address not detected
1: General call address detected.
R/(W)
*1
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
DID
Device ID Address Detection Flag
0: Device ID command not detected
1: Device ID command detected.
This bit is set to 1 when the first frame received immediately after
a start condition is detected, matches a value of (device ID (1111
100b) + 0[W]).
R/(W)
*1
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
HOA
Host Address Detection Flag
0: Host address not detected
1: Host address detected.
This bit is set to 1 when the received slave address matches the
host address (0001 000b).
R/(W)
*1
Note 1.
Only 0 can be written to clear the flag.
AASy flag (Slave Address y Detection Flag) (y = 0 to 2)
The AASy flag indicates whether slave address y was detected.
[Setting conditions]
For 7-bit address format (SARUy.FS = 0):
When the received slave address matches the SVA[6:0] value in SARLy, with the SARyE bit in ICSER set to 1
(slave address y detection enabled).
The AASy flag is set to 1 on the rising edge of the 9th SCL clock cycle in the frame.
For 10-bit address format: (SARUy.FS = 1):
When the received slave address matches a value of (11110b + SVA[1:0] in SARUy), and the subsequent address
matches the SARLy value, with the SARyE bit in ICSER set to 1 (slave address y detection enabled).
The AASy flag is set to 1 on the rising edge of the 9th SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the AASy flag after reading AASy = 1
When a stop condition is detected
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
For 7-bit address format (SARUy.FS = 0):
When the received slave address does not match the SVA[6:0] value in SARLy, with the SARyE bit in ICSER set to
1 (slave address y detection enabled).
The AASy flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
For 10-bit address format (SARUy.FS = 1):
When the received slave address does not match a value of 11110b + SVA[1:0] in SARUy, with the SARyE bit in
ICSER set to 1 (slave address y detection enabled)
The AASy flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
When the received slave address matches a value of 11110b + SVA[1:0] in SARUy, and the subsequent address
does not match the SARLy value, with the SARyE bit in ICSER set to 1 (slave address y detection enabled).
The AASy flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
GCA flag (General Call Address Detection Flag)
The GCA flag indicates whether the general call address was detected.
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[Setting condition]
When the received slave address matches the general call address (0000 000b + 0 [W]), with the GCAE bit in
ICSER set to 1 (general call address detection enabled).
The GCA flag is set to 1 on the rising edge of the 9th SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the GCA flag after reading GCA = 1
When a stop condition is detected
When the received slave address does not match the general call address (0000 000b + 0 [W]), with the GCAE bit in
ICSER set to 1 (general call address detection enabled).
The GCA flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
DID flag (Device ID Address Detection Flag)
The DID flag indicates whether the device ID address was detected.
[Setting condition]
When the first frame received immediately after a start or restart condition is detected matches a value of (device ID
(1111 100b) + 0 [W]), with the DIDE bit in ICSER set to 1 (device ID address detection enabled).
The DID flag is set to 1 on the rising edge of the 9th SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the DID flag after reading DID = 1
When a stop condition is detected
When the first frame received immediately after a start or restart condition is detected does not match a value of the
device ID (1111 100b), with the DIDE bit in ICSER set to 1 (device ID address detection enabled).
The DID flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
When the first frame received immediately after a start or restart condition is detected matches a value of (device ID
(1111 100b) + 0 [W]), and the second frame does not match any slave address from 0 to 2, with the DIDE bit in
ICSER set to 1 (device ID address detection enabled).
The DID flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
HOA flag (Host Address Detection Flag)
The HOA flag indicates whether the host address was detected.
[Setting condition]
When the received slave address matches the host address (0001 000b), with the HOAE bit in ICSER set to 1 (host
address detection enabled).
The HOA flag is set to 1 on the rising edge of the 9th SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the HOA flag after reading HOA = 1
When a stop condition is detected
When the received slave address does not match the host address (0001 000b), with the HOAE bit in ICSER set to 1
(host address detection enabled).
The HOA flag is set to 0 on the rising edge of the 9th SCL clock cycle in the frame.
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
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I2C Bus Status Register 2 (ICSR2)
34.2.10
Address(es): IIC0.ICSR2 4005 3009h, IIC1.ICSR2 4005 3109h, IIC2.ICSR2 4005 3209h
b7
b6
TDRE
TEND
0
0
Value after reset:
b5
b4
b3
b2
RDRF NACKF STOP START
0
0
0
0
b1
b0
AL
TMOF
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOF
Timeout Detection Flag
0: Timeout not detected
1: Timeout detected.
R/(W)*1
b1
AL
Arbitration-Lost Flag
0: Arbitration not lost
1: Arbitration lost.
R/(W)*1
b2
START
Start Condition Detection Flag
0: Start condition not detected
1: Start condition detected.
R/(W)*1
b3
STOP
Stop Condition Detection Flag
0: Stop condition not detected
1: Stop condition detected.
R/(W)*1
b4
NACKF
NACK Detection Flag
0: NACK not detected
1: NACK detected.
R/(W)*1
b5
RDRF
Receive Data Full Flag
0: ICDRR contains no receive data
1: ICDRR contains receive data.
R/(W)*1
b6
TEND
Transmit End Flag
0: Data being transmitted
1: Data transmit complete.
R/(W)*1
b7
TDRE
Transmit Data Empty Flag
0: ICDRT contains transmit data
1: ICDRT contains no transmit data.
R
Note 1.
Only 0 can be written, to clear the flag.
TMOF flag (Timeout Detection Flag)
The TMOF flag is set to 1 when IIC detects a timeout because the SCLn line state remains unchanged for the set period.
[Setting condition]
When the SCLn line state remains unchanged for the period specified in the ICMR2.TMOH, TMOL, and TMOS
bits while the ICFER.TMOE bit is 1 (timeout function enabled) in master or in slave mode and the received slave
address matches.
[Clearing conditions]
When 0 is written to the TMOF flag after reading TMOF = 1
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
AL flag (Arbitration-Lost Flag)
The AL flag indicates that the bus mastership is lost in arbitration because of a bus conflict or because of some other
reason, when a start condition was issued, or an address and data was transmitted.
The IIC monitors the level on the SDAn line during transmission. If the level on the line does not match the value of the
bit being output, the IIC sets the AL flag to 1 to indicate that the bus is occupied by another device. The IIC can also set
the flag to indicate the detection of arbitration loss during NACK transmission in master mode or during data
transmission in slave mode.
[Setting conditions]
When master arbitration-lost detection is enabled (ICFER.MALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of the SCL clock except
for the ACK period during data transmission in master transmit mode
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When a start condition is detected while the ST bit in ICCR2 is 1 (start condition requested) or the internal SDA
output state does not match the SDAn line level
When the ST bit in ICCR2 is 1 (start condition requested), with the BBSY flag in ICCR2 set to 1.
When NACK arbitration-lost detection is enabled (ICFER.NALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of the SCL clock in the
ACK period during NACK transmission in receive mode.
When slave arbitration-lost detection is enabled (ICFER.SALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of the SCL clock, except
for the ACK period during data transmission in slave transmit mode.
[Clearing conditions]
When 0 is written to the AL flag after reading AL = 1
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
Table 34.4
Relationship between arbitration-lost generation sources and arbitration-lost enable functions
ICFER
ICSR2
MALE
NALE
SALE
AL
Error
Arbitration-lost generation source
1
×
×
1
Start condition
issuance error
When internal SDA output state does not match SDAn line level when a
start condition is detected, while the ST bit in ICCR2 is 1
When ST in ICCR2 is set to 1 while BBSY in ICCR2 is 1
1
Transmit data
mismatch
When transmit data (including slave address) does not match the bus
state in master transmit mode
×
1
×
1
NACK
transmission
mismatch
When ACK is detected during transmission of NACK in master or slave
receive mode
×
×
1
1
Transmit data
mismatch
When transmit data does not match the bus state in slave transmit mode
×: Don’t care
START flag (Start Condition Detection Flag)
The START flag indicates whether a start or restart condition is detected.
[Setting condition]
When a start or restart condition is detected.
[Clearing conditions]
When 0 is written to the START flag after reading START = 1
When a stop condition is detected
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
STOP flag (Stop Condition Detection Flag)
The STOP flag indicates whether a stop condition is detected.
[Setting condition]
When a stop condition is detected.
[Clearing conditions]
When 0 is written to the STOP flag after reading STOP = 1
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
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NACKF flag (NACK Detection Flag)
The NACKF flag indicates whether a NACK was detected.
[Setting condition]
When acknowledge is not received (NACK received) from the receive device in transmit mode, with the NACKE
bit in ICFER set to 1 (transfer suspension enabled).
[Clearing conditions]
When 0 is written to the NACKF flag after reading NACKF = 1
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
Note:
When the NACKF flag is set to 1, the IIC suspends data transmission and reception. Writing to ICDRT in transmit
mode or reading from ICDRR in receive mode with the NACKF flag set to 1 does not enable data transmit or
receive operation. To restart data transmission or reception, set the NACKF flag to 0.
RDRF flag (Receive Data Full Flag)
The RDRF flag indicates whether the IDCRR contains receive data.
[Setting conditions]
When receive data is transferred from ICDRS to ICDRR
The RDRF flag is set to 1 on the rising edge of the 8th or 9th SCL clock cycle (selected in the RDRFS bit in ICMR3).
When the received slave address matches after a start (or restart) condition is detected with the TRS bit in ICCR2 set
to 0.
[Clearing conditions]
When 0 is written to the RDRF flag after reading RDRF = 1
When data is read from ICDRR
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
TEND flag (Transmit End Flag)
The TEND flag indicates whether data transmission is still being transmitted or is complete.
[Setting condition]
On the rising edge of the 9th SCL clock cycle while the TDRE flag is 1.
[Clearing conditions]
When 0 is written to the TEND flag after reading TEND = 1
When data is written to ICDRT
When a stop condition is detected
When 1 is written to the IICRST bit in ICCR1 to initiate an IIC reset or an internal reset.
TDRE flag (Transmit Data Empty Flag)
The TDRE flag indicates whether the ICDRT contains transmit data.
[Setting conditions]
When data is transferred from ICDRT to ICDRS and ICDRT becomes empty
When the TRS bit in ICCR2 is set to 1
When the received slave address matches while the TRS bit is 1.
[Clearing conditions]
When data is written to ICDRT
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When the TRS bit in ICCR2 is set to 0
When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset.
Note:
When the NACKF flag is set to 1 while the NACKE bit in ICFER is 1, the IIC suspends data transmission and
reception. In this case, if the TDRE flag is 0 (next transmit data written), data is transferred to the ICDRS register
and the ICDRT register becomes empty on the rising edge of the 9th clock cycle, but the TDRE flag is not set to 1.
I2C Bus Wakeup Unit Register (ICWUR)
34.2.11
Address(es): IIC0.ICWUR 4005 3016h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
WUE
WUIE
WUF
WUAC
K
—
—
—
WUAFA
0
0
0
1
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
WUAFA
Wakeup Analog Filter Additional Selection
0: Do not add the wakeup analog filter
1: Add the wakeup analog filter.
R/W
b3 to b1
—
Reserved
These bit are read as 0. The write value should be 0.
R/W
b4
WUACK
ACK Bit for Wakeup Mode
Choice of four response modes in combination with
ICCR1.IICRST and WUACK. See Table 34.5.
R/W
b5
WUF
Wakeup Event Occurrence Flag
0: Slave address not matching during wakeup
1: Slave address matching during wakeup.
R/W
b6
WUIE
Wakeup Interrupt Request Enable
0: Disable wakeup interrupt request (IIC0_WUI)
1: Enable wakeup interrupt request (IIC0_WUI).
R/W
b7
WUE
Wakeup Function Enable
0: Disable wakeup function
1: Enable wakeup function.
R/W
Table 34.5
Wakeup mode
IICRST
WUACK
Operation mode
Description
0
0
Normal wakeup mode 1
ACK response on 9th SCL, and SCL low hold after 9th SCL
0
1
Normal wakeup mode 2
No ACK response immediately and SCL low hold between 8th and 9th SCL.
SCL low-hold release and ACK response on 9th SCL.
1
0
Command recovery mode
ACK response on 9th SCL and no SCL low hold
1
1
EEP response mode
NACK response on 9th SCL and no SCL low hold
WUF flag (Wakeup Event Occurrence Flag)
The WUF flag indicates whether the slave address is matching during wakeup.
[Setting condition]
When PCLKB is supplied after a slave-address match in the first 8th SCL low during wakeup mode.
[Clearing conditions]
When 0 is written to the WUF flag after reading WUF = 1
When ICE = 0 and IICRST = 1.
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S5D5 User’s Manual
I2C-Bus Wakeup Unit Register 2 (ICWUR2)
34.2.12
Address(es): IIC0.ICWUR2 4005 3017h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
1
1
1
1
1
b2
b1
b0
WUSY WUAS WUSE
F
YF
N
1
0
1
Bit
Symbol
Bit name
Description
R/W
b0
WUSEN
Wakeup Function Synchronous Enable
0: IIC asynchronous operation enable
1: IIC synchronous operation enable.
R/W
b1
WUASYF
Wakeup Function Asynchronous
Operation Status Flag
0: IIC synchronous circuit operation condition
1: IIC asynchronous circuit operation condition.
R
b2
WUSYF
Wakeup Function Synchronous Operation
Status Flag
0: IIC asynchronous circuit operation condition
1: IIC synchronous circuit operation condition.
R
b7 to b3
—
Reserved
These bits are read as1. The write value should be 1.
R/W
WUSEN bit (Wakeup Function Synchronous Enable)
The WUSEN bit is used in combination with the WUASYF flag (or WUSYF flag) to switch between the PCLKB
synchronous and asynchronous operation, when a wakeup effective function is enabled (ICWUR.WUE = 1).
The PCLKB operation switches from synchronous to asynchronous operation:
When the ICCR2.BBSY flag is 0, if the WUASYF flag at 0 writes 0 to the WUSEN bit. The reception occurs
independently of the operation of PCLKB (with PCLKB stopped) after it switches to the PCLKB asynchronous
operation, on wakeup event detection.
The PCLKB operation switches from asynchronous to synchronous operation:
When 1 is written to the WUSEN bit, with the WUASYF flag at 1, when a wakeup event is detected. After writing
1, the WUASYF flag immediately becomes 0.
When the stop condition is detected with the wakeup event undetected.
WUASYF flag (Wakeup Function Asynchronous Operation Status Flag)
The WUASYF flag can place the IIC in PCLKB asynchronous operation when wakeup effective function is enabled
(ICWUR.WUE = 1).
[Setting condition]
When the ICCR2.BBSY flag is 0, and WUSEN bit is set to 0 with the ICWUR.WUE bit set to 1.
[Clearing conditions]
When 1 is written to the WUSEN bit after detecting the wakeup event with ICWUR.WUE bit set to 1
When a stop condition is detected with WUSEN bit set to 1 before detecting the wakeup event with WUASY flag
set to 1 with ICWUR.WUE bit set to 1
When 1 is written to the WUSEN bit with the WUASYF flag set to 1, and a wakeup event is detected with
ICWUR.WUE set to 1
ICCR1.ICE = 0 and ICCRST = 1 (ICC reset)
ICWUR.WUE = 0.
WUSYF flag (Wakeup Function Synchronous Operation Status Flag)
WUSYF flag can place the IIC in PCLKB synchronous operation when wakeup effective function is enabled
(ICWUR.WUE = 1). When this flag is used, the WUASYF flag is always reserved.
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[Setting conditions]
When 1 is written to the WUSEN bit after detecting the wakeup event with ICWUR.WUE bit set to 1 and WUSYF
flag set to 0, with ICWUR.WUE bit set to 1
When a stop condition is detected with WUSEN bit set to 1, before detecting the wakeup event with WUSYF flag
set to 0, with ICWUR.WUE bit set to 1
ICCR1.ICE = 0 and ICCRST = 1 (ICC reset)
ICWUR.WUE = 0.
[Clearing condition]
When the ICCR2.BBSY flag is 0 with the ICWUR.WUE bit set to 1 after writing 0 to the WUSEN bit.
34.2.13
Slave Address Register L y (SARLy) (y = 0 to 2)
Address(es): IIC0.SARL0 4005 300Ah, IIC1.SARL0 4005 310Ah, IIC2.SARL0 4005 320Ah,
IIC0.SARL1 4005 300Ch, IIC1.SARL1 4005 310Ch, IIC2.SARL1 4005 320Ch,
IIC0.SARL2 4005 300Eh, IIC1.SARL2 4005 310Eh, IIC2.SARL2 4005 320Eh
b7
b6
b5
b4
b3
b2
b1
SVA[6:0]
Value after reset:
0
0
0
0
b0
SVA0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SVA0
10-Bit Address LSB
Slave address setting
R/W
b7 to b1
SVA[6:0]
7-Bit Address/10-Bit Address Lower Bits
Slave address setting
R/W
SVA0 bit (10-Bit Address LSB)
When the 10-bit address format is selected (SARUy.FS = 1), the SVA0 bit functions as the LSB of a 10-bit address and is
combined with the SVA[6:0] bits to form the lower 8 bits of a 10-bit address.
This bit is valid when the SARyE bit in ICSER is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1.
When the SARUy.FS or SARyE bit is 0, the setting in this bit is ignored.
SVA[6:0] bits (7-Bit Address/10-Bit Address Lower Bits)
When the 7-bit address format is selected (SARUy.FS = 0), the SVA[6:0] bits function as a 7-bit address. When the 10bit address format is selected (SARUy.FS = 1), these bits combined with the SVA0 bit to form the lower 8 bits of a 10-bit
address. When the SARyE bit in ICSER is 0, the setting in these bits is ignored.
34.2.14
Slave Address Register U y (SARUy) (y = 0 to 2)
Address(es): IIC0.SARU0 4005 300Bh, IIC1.SARU0 4005 310Bh, IIC2.SARU0 4005 320Bh,
IIC0.SARU1 4005 300Dh, IIC1.SARU1 4005 310Dh, IIC2.SARU1 4005 320Dh,
IIC0.SARU2 4005 300Fh, IIC1.SARU2 4005 310Fh, IIC2.SARU2 4005 320Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
SVA[1:0]
0
0
0
0
0
0
0
b0
FS
0
Bit
Symbol
Bit name
Description
R/W
b0
FS
7-Bit/10-Bit Address Format Select
0: Select 7-bit address format
1: Select 10-bit address format.
R/W
b2, b1
SVA[1:0]
10-Bit Address Upper Bits
Slave address setting
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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FS bit (7-Bit/10-Bit Address Format Select)
The FS bit selects a 7-bit or 10-bit address format for slave address y (in SARLy and SARUy).
When the SARyE bit in ICSER is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 0, the 7-bit address
format is selected for slave address y, the SVA[6:0] setting in SARLy is valid, and the SVA[1:0] and SVA0 settings in
SARLy are ignored.
When the SARyE bit in ICSER is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1, the 10-bit address
format is selected for slave address y and the SVA[1:0] and SARLy settings are valid.
When the SARyE bit in ICSER is 0 (SARLy and SARUy disabled), the SARUy.FS setting is invalid.
SVA[1:0] bits (10-Bit Address Upper Bits)
When the 10-bit address format is selected (FS = 1), the SVA[1:0] bits function as the upper 2 bits of a 10-bit address.
These bits are valid when the SARyE bit in ICSER is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1.
When the SARUy.FS or SARyE bit is 0, the setting in these bits is ignored.
I2C Bus Bit Rate Low-Level Register (ICBRL)
34.2.15
Address(es): IIC0.ICBRL 4005 3010h, IIC1.ICBRL 4005 3110h, IIC2.ICBRL 4005 3210h
Value after reset:
Bit
b7
b6
b5
—
—
—
1
1
1
Symbol
b4
b3
b2
b1
b0
1
1
BRL[4:0]
1
1
Bit name
1
Description
R/W
b4 to b0
BRL[4:0]
Bit Rate Low-Level Period
Low-level period of SCL clock
R/W
b7 to b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
ICBRL is a 5-bit register that sets the low-level period of the SCL clock. ICBRL also works to generate the data setup
time for the automatic SCL low-hold operation (see section 34.9, Automatic Low-Hold Function for SCL). When the IIC
is used only in slave mode, this register must be set to a value longer than the data setup time.*1
ICBRL counts the low-level period with the internal reference clock source (IIC) specified in the CKS[2:0] bits in
ICMR1.
If the digital noise filter is enabled (the NFE bit in ICFER is 1), set the ICBRL register to a value at least one greater than
the number of stages in the noise filter. For this number, see the description of the ICMR3.NF[1:0] bits.
Note 1. Data setup time (tSU: DAT)
250 ns for up to 100 kbps: Standard-mode (Sm)
100 ns for up to 400 kbps: Fast-mode (Fm)
50 ns for up to 1 Mbps: Fast-mode Plus (Fm+)
I2C Bus Bit Rate High-Level Register (ICBRH)
34.2.16
Address(es): IIC0.ICBRH 4005 3011h, IIC1.ICBRH 4005 3111h, IIC2.ICBRH 4005 3211h
Value after reset:
b7
b6
b5
—
—
—
1
1
1
b4
b3
b2
b1
b0
1
1
BRH[4:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
BRH[4:0]
Bit Rate High-Level Period
High-level period of SCL clock
R/W
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Bit
Symbol
Bit name
Description
R/W
b7 to b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
ICBRH is a 5-bit register that sets the high-level period of the SCL clock. ICBRH is valid in master mode. If the IIC is
used only in slave mode, no setting is required in this register.
ICBRH counts the high-level period with the internal reference clock source (IIC) specified in the CKS[2:0] bits in
ICMR1.
If the digital noise filter is enabled (the NFE bit in ICFER is 1), set the ICBRH register to a value at least one greater than
the number of stages in the noise filter. For this number, see the description of the ICMR3.NF[1:0] bits.
The IIC transfer rate and the SCL clock duty are calculated using the following expressions (1) to (5):
1. ICFER.SCLE = 0
Transfer rate = 1/{[(BRH + 1) + (BRL + 1)]/IICφ*1 + tr*2 + tf*2}
Duty cycle = {tr + [(BRH + 1)/IICφ]}/{tr + tf + [(BRH + 1) + (BRL + 1)]/IICφ}
2. ICFER.SCLE = 1 and ICFER.NFE = 0 and CKS[2:0] = 000b (IICφ = PCLKB)
Transfer rate = 1/{[(BRH + 3) + (BRL+ 3)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 3)/IICφ]}/{tr + tf + [(BRH + 3) + (BRL + 3)]/IICφ}
3. ICFER.SCLE = 1 and ICFER.NFE = 1 and CKS[2:0] = 000b (IICφ = PCLKB)
Transfer rate = 1/{[(BRH + 3 + nf*3) + (BRL + 3 + nf)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 3 + nf)/IICφ]}/{tr + tf + [(BRH + 3 + nf) + (BRL + 3 + nf)]/IICφ}
4. ICFER.SCLE = 1 and ICFER.NFE = 0 and CKS[2:0] ≠ 000b
Transfer rate = 1/{[(BRH + 2) + (BRL + 2)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 2)/IICφ]}/{tr + tf + [(BRH + 2) + (BRL + 2)]/IICφ}
5. ICFER.SCLE = 1 and ICFER.NFE = 1 and CKS[2:0] ≠ 000b
Transfer rate = 1/{[(BRH + 2 + nf) + (BRL + 2 + nf)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 2 + nf)/IICφ]}/{tr + tf + [(BRH + 2 + nf) + (BRL + 2 + nf)]/IICφ}
Note 1. IICφ = PCLKB × Division ratio.
Note 2. The SCLn line rise time (tr) and SCLn line fall time (tf) depend on the total bus line capacitance (Cb) and the pullup resistor (Rp). For details, see the I2C bus standard from NXP Semiconductors.
Note 3. nf = Number of digital noise filter stages selected in the ICMR3.NF bit.
Table 34.6
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 0
Transfer rate (kbps)
CKS[2:0]
BRH[4:0](ICBRH)
BRL[4:0](ICBRL)
PCLKB (MHz)
NF[1:0]
Computation expression
100
100b
14 (EEh)
17 (F1h)
60
—
(1)
400
010b
8 (E8h)
19 (F3h)
60
—
(1)
1000
000b
15 (EFh)
29 (FDh)
60
—
(1)
Table 34.7
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 1 and NFE = 0
Transfer rate (kbps)
CKS[2:0]
BRH[4:0](ICBRH)
BRL[4:0](ICBRL)
PCLKB (MHz) NF[1:0]
Computation expression
100
100b
13 (EDh)
16 (F0h)
60
—
(4)
400
010b
7 (E7h)
18 (F2h)
60
—
(4)
1000
000b
13 (EDh)
27 (FBh)
60
—
(2)
Table 34.8
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 1 and NFE = 1
Transfer rate (kbps)
CKS[2:0]
BRH[4:0](ICBRH)
BRL[4:0](ICBRL
PCLKB (MHz) NF[1:0]
Computation expression
100
100b
11 (EBh)
14 (EEh)
60
01b
(5)
400
010b
5 (E5h)
16 (F0h)
60
01b
(5)
1000
000b
11 (EBh)
25 (F9h)
60
01b
(3)
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.2.17
I2C Bus Transmit Data Register (ICDRT)
Address(es): IIC0.ICDRT 4005 3012h, IIC1.ICDRT 4005 3112h, IIC2.ICDRT 4005 3212h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
When ICDRT detects a space in the I2C Bus Shift Register (ICDRS), it transfers the transmit data that is written to
ICDRT to ICDRS and starts transmitting data in transmit mode.
The double-buffer structure of ICDRT and ICDRS allows continuous transmit operation if the next transmit data is
written to ICDRT while the ICDRS data is being transmitted.
ICDRT can always be read from and written to. Write transmit data to ICDRT when a transmit data empty interrupt
(IICn_TXI) request is generated.
34.2.18
I2C Bus Receive Data Register (ICDRR)
Address(es): IIC0.ICDRR 4005 3013h, IIC1.ICDRR 4005 3113h, IIC2.ICDRR 4005 3213h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
When 1 byte of data is received, the received data is transferred from the I2C Bus Shift Register (ICDRS) to ICDRR to
enable the next data to be received.
The double-buffer structure of ICDRS and ICDRR allows continuous receive operation if the received data is read from
ICDRR while ICDRS is receiving data. ICDRR cannot be written to. Read data from ICDRR when a receive data full
interrupt (IICn_RXI) request is generated.
If ICDRR receives the next receive data before the current data is read from ICDRR while the RDRF flag in ICSR2 is 1,
the IIC automatically holds the SCL clock low for 1 cycle before the RDRF flag is set to 1 again.
34.2.19
Value after reset:
I2C Bus Shift Register (ICDRS)
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
ICDRS is an 8-bit shift register to transmit and receive data.
During transmission, transmit data is transferred from ICDRT to ICDRS and is sent from the SDAn pin. During
reception, data is transferred from ICDRS to ICDRR after 1 byte of data is received. ICDRS cannot be accessed directly.
34.3
34.3.1
Operation
Communication Data Format
The I2C bus format consists of 8-bit data and 1-bit acknowledge. The frame following a start or restart condition is an
address frame that specifies a slave device with which the master device communicates. The specified slave is valid until
a new slave is specified or a stop condition is issued.
Figure 34.3 shows the I2C bus format, and Figure 34.4 shows the I2C bus timing.
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[7-bit address format]
S
SLA (7 bits)
R/W#
A
1
7
1
1
DATA (8 bits)
8
A
A/A#
P
1
1
1
n (n = 1 or more)
[10-bit address format]
S
11110b+SLA(2 bits) W#
1
7
1
A
SLA (8 bits)
A
DATA (8 bits)
A
A/A#
P
1
8
1
8
1
1
1
n (n = 1 or more)
S 11110b+SLA(2 bits) W#
A
SLA (8 bits)
A
Sr 11110b+SLA(2 bits)
R
A
DATA (8 bits)
A
A/A#
P
1
1
8
1
1
1
1
8
1
1
1
7
1
7
n (n = 1 or more)
n: Number of transfer frames
Figure 34.3
SCLn
I2C bus format
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDAn
S
SLA
Figure 34.4
R/W#
A
Data
A
Data
A
P
I2C bus timing when the SLA setting = 7 bits
S:
Start condition. The master device drives the SDAn line low from high while the SCLn line is high.
SLA:
Slave address, by which the master device selects a slave device
R/W#:
Indicates the direction of data transfer: from the slave device to the master device when R/W# is 1, or from the master device
to the slave device when R/W# is 0
A:
Acknowledge. The receive device drives the SDAn line low. In master transmit mode, the slave device returns acknowledge.
In master receive mode, the master device returns acknowledge.
A#:
Not Acknowledge. The receive device drives the SDAn line high.
Sr:
Restart condition. The master device drives the SDAn line low from the high level after the setup time has elapsed with the
SCLn line high.
DATA:
Transmitted or received data
P:
Stop condition. The master device drives the SDAn line high from low while the SCLn line is high.
34.3.2
Initial Settings
Before starting data transmission and reception, initialize the IIC using the procedure shown in Figure 34.5.
1. Set the ICCR1.ICE bit set to 0 to set the SCLn and SDAn pins to the inactive state.
2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset.
3. Set the ICCR1.ICE bit to 1 to initiate internal reset, which initializes the flags and the internal state of the ICSR1
register.
4. Set the SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL registers (y = 0 to 2), and set the other registers as
required. For the initial IIC settings, see Figure 34.5.
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5. When the required register settings are complete, set the ICCR1.IICRST bit to 0, to release the IIC reset.
Note:
This procedure is not necessary if the IIC initialization is already complete.
Initial settings
Set ICE in ICCR1 to 0
Set IICRST in ICCR1 to 1
Set ICE in ICCR1 to 1
Set SARLy and SARUy.
Set ICSER
Set CKS[2:0] in ICMR1 and
ICBRL/ICBRH
SCLn, SDAn pins not driven
IIC reset
Internal reset, SCLn and SDAn pins in active state
Set slave address format and slave address
Set transfer bit rate*1
Set ICMR2 and ICMR3
*2
Set ICFER
Set ICIER
Set IICRST in ICCR1 to 0
Set interrupt enable
Release from the internal reset state
End
y = 0 to 2
Note 1. When the IIC is used only in slave mode, set the ICBRL register to a value
longer than the data setup time.
Note 2. Set these registers as required.
Figure 34.5
34.3.3
Example IIC initialization flow
Master Transmit Operation
In master transmit operation, the IIC outputs the SCL clock and transmit data signals as the master device, and the slave
device returns the acknowledgments. Figure 34.6 shows an example of master transmission, and Figure 34.7 to Figure
34.9 show the operation timing in master transmission.
To set up and perform master transmission:
1. To initialize the IIC, follow the procedure in section 34.3.2, Initial Settings.
2. Read the BBSY flag in ICCR2 to check that the bus is free, and then set the ST bit in ICCR2 to 1 (start condition
request). On receiving the request, the IIC issues a start condition. At the same time, the BBSY and START flags in
ICSR2 automatically set to 1 and the ST bit is automatically set to 0. If the start condition is detected and the
internal levels for the SDA output state and the levels on the SDAn line match while the ST bit is 1, the IIC
recognizes that the start condition requested by the ST bit is successfully complete, and the MST and TRS bits in
ICCR2 automatically set to 1, placing the IIC in master transmit mode. The TDRE flag in ICSR2 also automatically
sets to 1 in response to the setting of the TRS bit to 1.
3. Check that the TDRE flag in ICSR2 is 1, and then write the value for transmission (the slave address and the R/W#
bit) to ICDRT. When the transmit data is written to ICDRT, the TDRE flag is automatically set to 0, the data is
transferred from ICDRT to ICDRS, and the TDRE flag again sets to 1. After the byte containing the slave address
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34. I2C Bus Interface (IIC)
and R/W# bit is transmitted, the value of the TRS bit automatically updates to select master transmit or master
receive mode based on the value of the transmitted R/W# bit. If the value of the R/W# bit is 0, the IIC continues in
master transmit mode.
If the ICSR2.NACKF flag is 1, indicating that no slave device recognized the address or that there was an error in
communications, write 1 to the ICCR2.SP bit to issue a stop condition.
To transmit data with an address in the 10-bit format, start by writing 1111 0b, the 2 upper bits of the slave address,
and W to ICDRT as the first address transmission. For the second address transmission, write the 8 lower bits of the
slave address to ICDRT.
4. After confirming that the TDRE flag in ICSR2 is 1, write the transmit data to the ICDRT register. The IIC
automatically holds the SCLn line low until the transmit data is ready or a stop condition is issued.
5. After all bytes of transmit data are written to the ICDRT register, wait until the value in the TEND flag in ICSR2
returns to 1, and then set the SP bit in ICCR2 to 1 (stop condition requested). On receiving a stop condition request,
the IIC issues the stop condition. For details, see section 34.11.3, Issuing a Stop Condition.
6. On detecting the stop condition, the IIC automatically sets the MST and TRS bits in ICCR2 to 00b and enters slave
receive mode. In addition, the IIC automatically sets the TDRE and TEND flags to 0, and sets the STOP flag in
ICSR2 to 1.
7. After checking that the ICSR2.STOP flag is 1, set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
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Master transmission
[1] Process initial settings.
Initial settings
No
ICCR2.BBSY = 0?
[2] Check I2C bus occupation and issue
a start condition.
Yes
ICCR2.ST = 1
ICSR2.NACKF = 0?
No
Yes
No
ICSR2.TDRE = 1?
Yes
[3] Transmit slave address and W (first byte).
[4] Check ACK and set transmit data.
Write data to ICDRT
No
All data transmitted?
Yes
No
ICSR2.TEND = 1?
Yes
ICSR2.STOP = 0
[5] Check end of last data transmission
and issue a stop condition.
ICCR2.SP = 1
No
ICSR2.STOP = 1?
[6] Check stop condition issuance.
Yes
ICSR2.NACKF = 0
ICSR2.STOP = 0
[7] Execute processing for the next transfer
operation.
End of master transmission
Figure 34.6
Example master transmission flow
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Automatic low-hold (to prevent wrong transmission)
S
1
2
b7
b6
3
4
5
6
7
b5
b4
b3
b2
b1
8
9
1
2
3
4
5
6
7
8
9
b7
b6
b5
b4
b3
b2
b1
b0
ACK
1
2
3
4
b7
b6
b5
b4
SCLn
SDAn
b0
ACK
W
7-bit slave address
DATA 1
DATA 2
BBSY
MST
TRS
Transmit data (7-bit address + W)
Transmit data (DATA 1)
Transmit data (DATA 2)
TDRE
TEND
RDRF
ICDRT
DATA 1
7-bit address + W
DATA 2
7-bit address + W
ICDRS
DATA 3
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
START
ST
Write data to
Write data to
Write 1
ICDRT
ICDRT
to ST (7-bit address + W)
(DATA 1)
[2]
[3]
Figure 34.7
Write data to
ICDRT
(DATA 2)
Write data to
ICDRT
(DATA 3)
[4]
[4]
[4]
Master transmit operation timing (1) with 7-bit address format
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
8
9
1
2
b7
b6
b5
b4
b3
b2
b1
Upper 10-bit addresses (11110b + 2 bits)
b0
ACK
b7
b6
W
3
4
5
6
7
8
9
1
2
3
4
b1
b0
ACK
b7
b6
b5
b4
SCLn
SDAn
b5
b4
b3
b2
Lower 10-bit addresses
DATA 1
BBSY
MST
TRS
Transmit data (upper 10 bits + W)
Transmit data (DATA 1)
Transmit data (lower 10 bits)
TDRE
TEND
RDRF
ICDRT
DATA 1
Lower 10 bits
10-bit address + W
Upper 10 bits + W
ICDRS
DATA 1
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
ACKBR
DATA 2
Lower 10 bits
X (ACK/NACK)
0 (ACK)
0 (ACK)
START
ST
Write data to
Write 1 Write data to
ICDRT
ICDRT
to ST (11110b + 2
(lower 8 bits)
bits + W)
[2]
[3]
Figure 34.8
Write data to
ICDRT
(DATA 1)
Write data to
ICDRT
(DATA 2)
[4]
[4]
Master transmit operation timing (2) with 10-bit address format
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7
8
9
1
2
3
ACK
b7
b6
b5
4
5
6
7
8
9
1
2
3
b4
b3
DATA n-1
b2
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
9
P
b4
b3
DATA n
b2
b1
b0
A/NA
SCLn
SDAn
b1
b0
DATA n-2
BBSY
MST
TRS
Transmit data (DATA n)
Transmit data (DATA n-1)
TDRE
TEND
RDRF
ICDRT
DATA n-1
ICDRS
DATA n-2
DATA n
DATA n-1
DATA n
XXXX (Initial value/final receive data)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
ACKBR
0 (ACK)
X (ACK/NACK)
STOP
SP
Figure 34.9
34.3.4
Write data to ICDRT
(Final transmit data [DATA n])
Write 1
to SP
Clear
STOP to 0
[4]
[5]
[7]
Master transmit operation timing (3)
Master Receive Operation
In master receive operation, the IIC as a master device outputs the SCL clock, receives data from the slave device, and
returns acknowledgments. Because the IIC must start by sending a slave address to the associated slave device, the slave
address part of the procedure is performed in master transmit mode, but the subsequent steps are in master receive mode.
Figure 34.10 and Figure 34.11 show examples of master reception (7-bit address format), and Figure 34.12 to Figure
34.14 show the operation timing in master reception.
To set up and perform master reception:
1. To initialize the IIC, follow the procedure in section 34.3.2, Initial Settings.
2. Read the BBSY flag in ICCR2 to check that the bus is free, and then set the ST bit in ICCR2 to 1 to request the issue
of a start condition. On receiving the request, the IIC issues a start condition. When the IIC detects the start
condition, the BBSY and START flags in ICSR2 automatically set to 1, and the ST bit automatically sets to 0. If the
start condition is detected and the levels for the SDA output and the levels on the SDAn line match while the ST bit
is 1, the IIC recognizes that issuance of the start condition as requested by the ST bit is successfully complete, and
the MST and TRS bits in ICCR2 automatically set to 1, placing the IIC in master transmit mode. The TDRE flag in
ICSR2 also is automatically set to 1 in response to the setting of the TRS bit to 1.
3. Check that the TDRE flag in ICSR2 is 1, and then write the value for transmission (the first byte indicates the slave
address and value of the R/W# bit) to ICDRT. When the transmit data is written to ICDRT, the TDRE flag is
automatically set to 0, the data is transferred from ICDRT to ICDRS, and the TDRE flag again is set to 1. When the
byte containing the slave address and R/W# bit is transmitted, the value of the ICCR2.TRS bit automatically
updates to select transmit or receive mode based on the value of the transmitted R/W# bit. If the value of the R/W#
bit is 1, the TRS bit is set to 0 on the rising edge of the 9th cycle of the SCL clock, placing the IIC in master receive
mode. At this time, the TDRE flag is set to 0 and the ICSR2.RDRF flag is automatically set to 1.
If the ICSR2.NACKF flag is 1, indicating that no slave device recognized the address or that there is an error in
communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit
address, and then issue a restart condition. After that, transmit 1111 0b, the two upper bits of the slave address, and
the R bit to place the IIC in master receive mode.
4. Dummy read ICDRR after confirming that the RDRF flag in ICSR2 is 1. Doing so causes the IIC to start output of
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34. I2C Bus Interface (IIC)
the SCL clock and start data reception.
5. After 1 byte of data is received, the RDRF flag in ICSR2 is set to 1 on the rising edge of the 8th or 9th cycle of the
SCL clock, as selected in the RDRFS bit in ICMR3. Reading ICDRR produces the received data, and automatically
sets the RDRF flag to 0. The value of the acknowledgment field received during the 9th cycle of the SCL clock is
returned as the value set in the ICMR3.ACKBT bit. If the next byte to be received is the second-to-last byte, set the
ICMR3.WAIT bit to 1 for wait insertion before reading ICDRR, containing the second-to-last byte. In addition to
enabling NACK output, even when interrupts or other operations result in delays in setting the ICMR3.ACKBT bit
to 1 (NACK) in step (6), this fixes the SCLn line to the low level on the rising edge of the 9th clock cycle in
reception of the last byte, which enables the issuing of a stop condition.
6. When the ICMR3.RDRFS bit is 0, and the slave device must be notified that it is to end transfer for data reception
after transfer of the next and final byte, set the ICMR3.ACKBT bit to 1 (NACK).
7. After reading the second-to-last byte from the ICDRR register, if the value of the ICSR2.RDRF flag is 1, write 1 to
the SP bit in ICCR2 (stop condition requested), and then read the last byte from ICDRR. When ICDRR is read, the
IIC is released from the wait state and issues the stop condition after low-level output in the 9th clock cycle is
complete or the SCLn line is released from the low-hold state.
8. On detecting the stop condition, the IIC automatically sets the MST and TRS bits in ICCR2 to 00b and enters slave
receive mode. Additionally, detection of the stop condition sets the ICSR2.STOP flag to 1.
9. Check that the ICSR2.STOP flag is 1, and then set the ICSR2.NACKF and ICSR2.STOP flags to 0 for the next
transfer operation.
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Master reception starts
Initial settings
No
(1) Process initial settings.
ICCR2.BBSY = 0?
(2) Check I2C bus occupation and issue a start condition.
Yes
ICCR2.ST = 1
No
ICSR2.TDRE = 1?
Yes
Write to the ICDRT register
(3) Transmit the slave address followed by
R and check ACK.
No
ICSR2.RDRF = 1?
Yes
ICSR2.NACKF = 0?
No
Yes
ICMR3.WAIT = 1
Next data = last byte?
(4) Set to WAIT.
Yes
No
Dummy read the ICDRR register
No
(5) Set to NACK.
When receiving 2 bytes, perform dummy
read.
ICSR2.RDRF = 1?
Yes
Set ICMR3.ACKBT
(6) Read received data
When receiving 1 byte, perform
dummy read.
Read the ICDRR register
No
ICSR2.RDRF = 1?
Yes
ICSR2.STOP = 0
ICSR2.STOP = 0
ICCR2.SP = 1
ICCR2.SP = 1
Read the ICDRR register
Dummy read the ICDRR register
(7) Read the last data,
release SCL by the ACKBT setting,
and generate a stop condition.
ICMR3.WAIT = 0
No
ICSR2.STOP = 1?
(8) Confirm that the stop condition
has been generated.
Yes
ICSR2.NACKF = 0
ICSR2.STOP = 0
(9) Execute processing for the next transfer
operation.
Master reception ends
Figure 34.10
Example master reception flow with 7-bit address format and 1 or 2 bytes
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Master reception
[1] Process initial
settings.
Initial settings
No
ICCR2.BBSY = 0?
[2] Check I2C bus occupation and issue a start
condition.
Yes
ICCR2.ST = 1
No
ICSR2.TDRE = 1?
Yes
Write data to ICDRT
No
[3] Transmit the slave address followed
by R and check ACK.
ICSR2.RDRF = 1?
Yes
No
ICSR2.NACKF = 0?
Yes
[4] Perform dummy read.
Perform dummy read of ICDRR
No
ICSR2.RDRF = 1?
Yes
Next data = Final byte - 1?
No
Next data = Final byte - 2?
No
Yes
[5] Read received data and prepare for receiving
final data.
Yes
ICMR3.WAIT = 1
Read ICDRR
Set ICMR3.ACKBT
[6] Set the acknowledgment and read data of
(final byte – 1 byte).
Read ICDRR
No
ICSR2.RDRF = 1?
Yes
ICSR2.STOP = 0
ICSR2.STOP = 0
ICCR2.SP = 1
ICCR2.SP = 1
Read ICDRR
Perform dummy read of ICDRR
[7] Read final data and issue a stop
condition.
ICMR3.WAIT = 0
No
ICSR2.STOP = 1?
[8] Check stop condition issuance.
Yes
ICSR2.NACKF = 0
[9] Execute processing for the next transfer
operation.
ICSR2.STOP = 0
End of master reception
Figure 34.11
Example master reception flow with 7-bit address format and 3 or more bytes
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S5D5 User’s Manual
Automatic low hold
(to prevent wrong transmission)
S
Master transmit mode
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
Master receive mode
8
9
1
2
3
4
5
6
7
8
9
1
2
3
ACK
b7
b6
b5
b4
b3
b2
b1
b0
ACK
b7
b6
b5
4
SCLn
SDAn
7-bit slave address
b0
R
DATA 1
b4
DATA 2
BBSY
MST
TRS
Transmit data (7-bit address + R)
TDRE
Receive data (7-bit address + R)
TEND
Receive data (DATA 1)
RDRF
7-bit address + R
ICDRT
ICDRS
7-bit address + R
ICDRR
XXXX (Initial value/last data for reception)
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
DATA 1
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
START
ST
Write 1 Write data to ICDRT
to ST (7-bit address + R)
[2]
[3]
Figure 34.12
Read ICDRR
(Dummy read)
Read ICDRR
(DATA 1)
[4]
[5]
Master receive operation timing (1) with 7-bit address format, when RDRFS = 0
Master transmit mode
Automatic low hold (to prevent wrong transmission)
1 to 7
S
8
1 to 8
9
9
Sr
1
2
3
4
b6
b5
b4
5
6
7
b2
b1
Master receive mode
8
9
1
2
3
ACK
b7
b6
b5
4
SCLn
SDAn
b7
b1
Upper 10 bits
b0
W
ACK
b7
b0
ACK
Lower 10 bits
b7
b3
Upper 10-bit addresses (11110b + 2 bits)
b0
R
b4
DATA 1
BBSY
MST
TRS
Transmit data (upper 10 bits + W)Transmit data (lower 10 bits)
Transmit data (upper 10 bits + R)
TDRE
Transmit data (upper 10 bits + R)
TEND
RDRF
ICDRT
Upper 10 bits + W
ICDRS
Upper 10 bits + W
Upper 10 bits + R
Lower 10 bits
Lower 10 bits
Upper 10 bits + R
XXXX (Initial value/last data for reception)
ICDRR
DATA 1
XXXX (Initial value/last data for reception)
0 (ACK)
ACKBT
X (ACK/NACK)
ACKBR
0 (ACK)
0 (ACK)
0 (ACK)
START
ST
RS
Write 1 Write data to ICDRT
to ST (11110b + 2 bits + W)
Write data to
ICDRT
(lower 8 bits)
[2]
Figure 34.13
Clear
START to 0
Write 1 Write data to ICDRT
to RS (11110b + 2 bits + R)
Read ICDRR
(Dummy read)
[3]
[4]
Master receive operation timing (2) with 10-bit address format, when RDRFS = 0
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Automatic low hold (WAIT)
7
8
9
1
2
3
b1
b0
ACK
b7
b6
b5
Automatic low hold (WAIT)
4
5
6
7
8
9
1
2
3
b4
b3
b2
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
9
b4
b3
b2
b1
b0
NACK
P
SCLn
SDAn
DATA n-2
DATA n
DATA n-1
BBSY
MST
TRS
TDRE
TEND
Receive data (DATA n-1)
Receive data (DATA n-2)
Receive data (DATA n)
RDRF
XXXX (last data for transmission
[7-bit addresses + R/Upper 10 bits + R])
ICDRT
ICDRS
ICDRR
DATA n-2
DATA n-1
DATA n-2
0 (ACK)
DATA n
0
1 (NACK)
0 (ACK)
ACKBT
ACKBR
DATA n
DATA n-1
DATA n-3
0 (ACK)
0 (ACK)
1 (NACK)
STOP
SP
WAIT
Write 1
to WAIT
Read ICDRR
(DATA n-2)
[5]
Figure 34.14
34.3.5
Write 1
Read ICDRR
to ACKBT (DATA n-1)
[6]
Write 1
to SP
Read ICDRR
Clear
Clear
(last data for reception
WAIT to 0 STOP to 0
[DATA n])
[7]
[9]
Master receive operation timing (3) when RDRFS = 0
Slave Transmit Operation
In slave transmit operation, the master device outputs the SCL clock, the IIC transmits data as a slave device, and the
master device returns the acknowledgments.
Figure 34.15 shows an example of slave transmission, and Figure 34.16 and Figure 34.17 show the operation timing in
slave transmission.
To set up and perform slave transmission:
1. To initialize the IIC, follow the procedure in section 34.3.2, Initial Settings.
After the initialization, the IIC stays in the standby state until it receives a slave address that matches.
2. After receiving a matching slave address, the IIC sets one of the associated bits ICSR1.HOA, GCA, and
AASy (y = 0 to 2) flags to 1 on the rising edge of the 9th cycle of the SCL clock and outputs the value set in the
ICMR3.ACKBT bit to the acknowledge bit on the 9th cycle of the SCL clock. If the value of the received R/W# bit
is 1, the IIC automatically places itself in slave transmit mode by setting both the ICCR2.TRS bit and the
ICSR2.TDRE flag to 1.
3. Check that the ICSR2.TEND flag is 1, and write the transmit data to the ICDRT register. If the IIC receives no
acknowledge from the master device (receives an NACK signal) while the ICFER.NACKE bit is 1, the IIC
suspends transfer of the next data.
4. Wait until the ICSR2.TEND flag is set to 1 while the ICSR2.TDRE flag is 1, after the ICSR2.NACKF flag is set to
1 or the last byte for transmission is written to the ICDRT register. When the ICSR2.NACKF flag or the TEND flag
is 1, the IIC drives the SCLn line low on the 9th falling edge of the SCL clock.
5. When the ICSR2.NACKF flag or the ICSR2.TEND flag is 1, dummy read ICDRR to complete the processing. This
releases the SCLn line.
6. On detecting the stop condition, the IIC automatically sets the ICSR1.HOA, GCA, and AASy (y = 0 to 2) flags, the
ICSR2.TDRE and TEND flags, and the ICCR2.TRS bit to 0, and enters slave receive mode.
7. Check that the ICSR2.STOP flag is 1, and then set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
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Slave transmission
[1] Process initial settings.
Initial settings
ICSR2.NACKF = 0?
No
Yes
No
ICSR2.TDRE = 1?
Yes
Write data to ICDRT
[2], [3] Check ACK and set transmit data.
Checking of ACK not necessary immediately after
address is received.
No
All data transmitted?
Yes
No
ICSR2.TEND = 1?
Yes
Read ICDRR
No
ICSR2.STOP = 1?
[4] Dummy read to release the SCL.
[5] Check stop condition detection.
Yes
ICSR2.NACKF = 0
[6] Execute processing for the next transfer operation.
ICSR2.STOP = 0
End of slave transmission
Figure 34.15
Example slave transmission flow
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Slave receive mode
S
1
2
b7
b6
3
4
5
6
7
b5
b4
b3
b2
b1
Slave transmit mode
8
9
1
2
3
b7
b6
b5
Automatic low hold (to prevent wrong transmission)
4
5
6
7
8
b4
b3
b2
b1
b0
9
1
2
b7
b6
3
4
b5
b4
SCLn
SDAn
ACK
b0
R
7-bit slave address
ACK
DATA 1
DATA 2
BBSY
MST
TRS
Transmit data (DATA 2)
Transmit data (DATA 1)
TDRE
TEND
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
DATA 1
DATA 2
7-bit address + R
ICDRS
DATA 3
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
START
NACKF
Write data to Write data to
ICDRT
ICDRT
(DATA 1)
(DATA 2)
[3]
Figure 34.16
Write data to
ICDRT
(DATA 3)
[3]
[3]
Slave transmit operation timing (1) with 7-bit address format
7
8
9
1
2
3
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
b4
b3
b2
b1
b0
9
1
2
3
b7
b6
b5
4
5
6
7
8
b4
b3
b2
b1
b0
9
P
SCLn
SDAn
DATA n-2
ACK
DATA n-1
NACK
DATA n
BBSY
MST
TRS
Transmit data (DATA n-1)
Transmit data (DATA n)
TDRE
TEND
RDRF
AASy
ICDRT
ICDRS
DATA n-1
DATA n
DATA n-2
DATA n-1
DATA n
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
ACKBR
0 (ACK)
1 (NACK)
STOP
NACKF
Write data to ICDRT
(last data for transmission
[DATA n])
[4]
Figure 34.17
Clear
Dummy read ICDRR
NACKF
(SCLn line is released)
to 0
[5]
Clear
STOP
to 0
[7]
Slave transmit operation timing (2)
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.3.6
Slave Receive Operation
In slave receive operation, the master device outputs the SCL clock and transmit data, and the IIC returns
acknowledgments as a slave device.
Figure 34.18 shows an example of slave reception, and Figure 34.19 and Figure 34.20 show the operation timing in slave
reception.
To set up and perform slave reception:
1. To initialize the IIC, follow the procedure in section 34.3.2, Initial Settings.
After initialization, the IIC stays in the standby state until it receives a slave address that matches.
2. After receiving a matching slave address, the IIC sets one of the associated ICSR1.HOA, GCA, and AASy (y = 0 to
2) flags to 1 on the rising edge of the 9th cycle of the SCL clock and outputs the value set in the ICMR3.ACKBT bit
to the acknowledge bit on the 9th cycle of the SCL clock. If the value of the received R/W# bit is 0, the IIC
continues to place itself in slave receive mode and sets the RDRF flag in ICSR2 to 1.
3. Check that the ICSR2.STOP flag is 0 and the ICSR2.RDRF flag is 1, and then dummy read the ICDRR register. The
dummy value consists of the slave address and R/W# bit when the 7-bit address format is selected, or the lower 8
bits when the 10-bit address format is selected.
4. When ICDRR is read, the IIC automatically sets the ICSR2.RDRF flag to 0. If reading of ICDRR is delayed and the
next byte is received while the RDRF flag is still set to 1, the IIC holds the SCLn line low until 1 SCL cycle before
the point where RDRF must be set. In this case, reading ICDRR releases the SCLn line from being held at the low
level.
When the ICSR2.STOP flag is 1 and the ICSR2.RDRF flag is also 1, read ICDRR until all the data is completely
received.
5. On detecting the stop condition, the IIC automatically clears the ICSR1.HOA, GCA, and AASy (y = 0 to 2) flags to
0.
6. Check that the ICSR2.STOP flag is 1, then set the ICSR2.STOP flag to 0 for the next transfer operation.
Slave reception
[1] Process initial settings.
Initial settings
ICSR2.STOP = 0?
No
Yes
No
ICSR2.RDRF = 1?
Yes
Yes
Read ICDRR
No
ICSR2.RDRF = 1?
Yes
No
[2], [3], [4] Read receive data
(dummy read first).
Read ICDRR (last data)
All data received?
Yes
No
ICSR2.STOP = 1?
[5] Check stop condition detection.
Yes
ICSR2.STOP = 0
[6] Execute processing for the next
transfer.
End of slave reception
Figure 34.18
Example slave reception flow
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
Automatic low hold
(to prevent failure to receive data)
S
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
8
9
1
2
3
4
5
6
7
8
b7
b6
b5
b4
b3
b2
b1
b0
9
1
2
b7
b6
3
4
b5
b4
SCLn
SDAn
ACK
b0
7-bit slave address
W
ACK
DATA 1
DATA 2
BBSY
MST
TRS
TDRE
Receive data (7-bit address + W)
TEND
Receive data (DATA 1)
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
7-bit address + W
ICDRS
DATA 1
XXXX (Initial value/last data for reception)
ICDRR
DATA 2
DATA 1
7-bit address + W
0 (ACK)
ACKBT
X (ACK/NACK)
ACKBR
0 (ACK)
0 (ACK)
START
NACKF
Figure 34.19
Read ICDRR
(Dummy read
[7-bit address + W])
Read ICDRR
(DATA 1)
[3]
[3][4]
Slave receive operation timing (1) with 7-bit address format, when RDRFS = 0
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
b1
b0
ACK
b7
b6
b5
b4
b3
b2
b1
b0
ACK
b7
b6
b5
b4
b3
b2
b1
b0
ACK
P
SCLn
SDAn
DATA n-2
DATA n-1
DATA n
BBSY
MST
TRS
TDRE
TEND
Receive data (DATA n-2)
Receive data (DATA n-1)
Receive data (DATA n)
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
ICDRS
ICDRR
DATA n-2
DATA n
DATA n-1
DATA n-3
DATA n-2
DATA n-1
DATA n
0 (ACK)
ACKBT
0 (ACK)
0 (ACK)
ACKBR
0 (ACK)
STOP
NACKF
Figure 34.20
Read ICDRR
(DATA n-2)
Read ICDRR
(DATA n-1)
[3] [4]
[3] [4]
Read ICDRR
(DATA n)
[3] [4]
Clear
STOP to 0
[6]
Slave receive operation timing (2) when RDRFS = 0
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.4
SCL Synchronization Circuit
For generation of the SCL clock, IIC starts counting the value for the high-level period specified in ICBRH when it
detects a rising edge on the SCLn line, and drives the SCLn line low when it completes counting. When IIC detects the
falling edge of the SCLn line, it starts counting the value for the low-level period specified in ICBRL, and then stops
driving the SCLn line, releasing the line when it completes counting. The IIC repeats this process to generate the SCL
clock.
If multiple master devices are connected to the I2C bus, a collision of SCL signals might arise because of contention with
another master device. In such cases, the master devices must synchronize their SCL signals. Because this
synchronization of SCL signals must be bit by bit, IIC is equipped with an SCL synchronization circuit to obtain bit-bybit synchronization of the SCL clock signals by monitoring the SCLn line while in master mode.
When IIC detects a rising edge on the SCLn line and starts counting the high-level period specified in ICBRH, and the
level on the SCLn line falls because an SCL signal is being generated by another master device, IIC performs the
following:
1. Stops counting when it detects the falling edge.
2. Drives the level on the SCLn line low.
3. Starts counting the low-level period specified in ICBRL.
When the IIC finishes counting the low-level period, it stops driving the SCLn line low to release the line. If the lowlevel period of the SCL clock signal from the other master device is longer than the low-level period set in the IIC, the
low-level period of the SCL signal is extended. When the low-level period for the other master device ends, the SCL
signal rises because the SCLn line is released. When the IIC finishes outputting the low-level period of the SCL clock,
the SCLn line is released and the SCL clock rises. That is, when SCL signals from more than one master are contending,
the high-level period of the SCL signal is synchronized with that of the clock with the narrower period, and the low-level
period of the SCL signal is synchronized with that of the clock with the broader period. However, such synchronization
of the SCL signal is only enabled when the SCLE bit in ICFER is set to 1.
[SCL clock generation]
Rising of SCL detected
(High-level period count start)
Compare match
(Counter clear, low-drive start)
ICBRH
ICBRH
ICBRH
SCLn
ICBRL
Falling of SCLn detected
(Low-level period count start)
[SCL synchronization]
Compare match
(Counter clear, SCLn line released)
Counter clear
ICBRH
ICBRL
Counter clear
Low-level output of
other master device
Low-level output of
other master device
ICBRH
ICBRH
SCLn
ICBRL
ICBRL
ICBRL
ICBRH: I2C Bus Bit Rate High-Level Register (SCL clock high-level period counter)
ICBRL: I2C Bus Bit Rate Low-Level Register (SCL clock low-level period counter)
Figure 34.21
Generation and synchronization of SCL signal from IIC
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.5
SDA Output Delay Function
The IIC module provides a function for delaying the output on the SDA line. The delay can be applied to all outputs on
the SDA line, including the issuing of start, restart, and stop conditions, data, and the ACK and NACK signals.
With this function, SDA output is delayed from the detection of a falling edge of the SCL signal to ensure that the SDA
signal is output within the interval during which the SCL clock is low. This approach helps prevent erroneous operation
of communications devices, with the aim of satisfying the 300-ns minimum data-hold time requirement of the SMBus
specification. The output delay function is enabled by setting the SDDL[2:0] bits in ICMR2 to a value other than 000b,
and disabled by setting the same bits to 000b.
When the SDA output delay function is enabled, for example, the DLCS bit in ICMR2 selects the clock source for the
SDA output delay counter, either as the internal base clock (IIC) for the IIC module or as the internal base clock divided
by two (IIC/2). The counter counts the number of cycles set in the SDDL[2:0] bits in ICMR2. When the delay count is
reached, the IIC module places the required output (start, restart, or stop condition, data, or an ACK or NACK signal) on
the SDA line.
Analog noise filter delay time + PCLKB sampling error (1 PCLKB (max))
Digital noise filter delay time (NFE, NF[1:0] settings = 0.5 PCLKB (min), 1 IIC to 4 IIC (max))
Transmit mode
SDA output delay time (DLCS, SDDL[2:0] settings = 0 (min) to 14 IIC (max))
S
SDA output release timing
8
9
SCLn
SDAn
b7 to b1
b0
ACK/NACK
SDA output delay
Receive mode
SDA output release timing
1 to 7
8
P
9
SCLn
SDAn
b0
b7 to b1
ACK/NACK
SDA output delay
Master mode
ICBRH
SCLn
ST
SDAn
ICBRL
ICBRH
1
b7
ICBRL
ICBRL
2 to 8
b6 to b0
*1
9
ICBRH
ICBRH
ICBRL
RS
1 to 9
ICBRL
SP
ACK/NACK
*1
*1
BBSY
ST
SDA output delay
Note 1. The output delay function is set by the DLCS and SDDL [2:0] bits when a start (ST), restart (RS), or stop (SP) condition is issued.
Figure 34.22
SDA output delay function
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.6
Digital Noise Filter Circuits
The internal circuitry sees the states of the SCLn and SDAn pins through analog and digital noise-filter circuits. Figure
34.23 shows a block diagram of the digital noise-filter circuit.
The on-chip digital noise-filter circuit of the IIC consists of four flip-flop circuit stages connected in series, and a matchdetection circuit.
The number of valid stages in the digital noise filter is selected in the NF[1:0] bits in ICMR3. The selected number of
valid stages determines the noise-filtering capability as a period from 1 to 4 IIC cycles.
The input signal to the SCLn pin (or SDAn pin) is sampled on falling edges of the IIC signal. When the input signal
level matches the output level of the number of valid flip-flop circuit stages as selected in the NF[1:0] bits in ICMR3, the
signal level is conveyed to the subsequent stage. If the signal levels do not match, the previous value is saved.
If the ratio between the frequency of the internal operating clock (PCLKB) and the transfer rate is small, for example, for
a data transfer at 400 kbps with PCLKB = 4 MHz, the digital noise filter might lead to the elimination of the required
signals as noise. In such cases, it is possible to disable the digital noise-filter circuit by setting the ICFER.NFE bit to 0,
and use only the analog noise filter circuit.
Mismatch
Match
D
Q
CLK
Comparator
PCLKB
Four-stage digital noise filter
D
Q
D
CLK
Q
CLK
D
Q
D
CLK
Q
CLK
IIC
D
Q
CLK
NF[1:0]
NFE
NFE: Digital Noise Filter Circuit Enable bit
NF[1:0]: Noise Filter Stage Select bits
Figure 34.23
34.7
Digital noise filter circuit block diagram
Address Match Detection
IIC can set three unique slave addresses in addition to the general call address and host address. The slave addresses can
be 7-bit or 10-bit slave addresses.
34.7.1
Slave-Address Match Detection
IIC can set three unique slave addresses and has a slave address detection function for each unique slave address. When
the SARyE bit (y = 0 to 2) in ICSER is set to 1, the slave addresses set in SARUy and SARLy (y = 0 to 2) can be
detected.
When the IIC detects a match of the set slave address, the associated AASy (y = 0 to 2) flag in ICSR1 is set to 1 on the
rising edge of the 9th SCL clock cycle, and the RDRF flag in ICSR2 or the TDRE flag in ICSR2 is set to 1 by the
subsequent R/W# bit. This causes a receive data full interrupt (IICn_RXI) or transmit data empty interrupt (IICn_TXI) to
be generated. The AASy flag identifies which slave address is specified.
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
Figure 34.24 to Figure 34.26 show the AASy flag set timing in three cases.
7-bit address format: slave reception
S
1
2
3
4
5
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
7-bit slave address
BBSY
Data (DATA 1)
Data (DATA 2)
ACK
Address match
AASy
Receive data (7-bit address)
TRS
Receive data (DATA 1)
TDRE
RDRF
Read ICDRR
(Dummy read [7-bit address])
Read ICDRR
(DATA 1)
7-bit address format: slave transmission
S
1
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
7-bit slave address
BBSY
Data (DATA 1)
Data (DATA 2)
ACK
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(DATA 1)
Figure 34.24
Write data to ICDRT
(DATA 2)
Write data to ICDRT
(DATA 3)
AASy flag set timing with 7-bit address format
10-bit address format: slave reception
S
1
2
3
4
5
1
1
1
1
0
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Upper 2 bits
10-bit slave address (lower 8 bits)
Data
ACK
BBSY
Address match
AASy
Receive data (lower addresses)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [lower addresses])
10-bit address format: slave transmission
S
1
2
3
4
5
1
1
1
1
0
6
7
8
9
1 to 8
9
Sr
1
2
3
4
5
1
1
1
1
0
6
7
8
9
R
ACK
SCLn
SDAn
BBSY
Upper 2 bits
W
ACK Lower 8 bits ACK
R
Upper 2 bits
Address match
AASy
Receive data (lower addresses)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [lower addresses])
Figure 34.25
AASy flag set timing with 10-bit address format
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
[When SAR0L = 7-bit address, SAR1L = 7-bit address, and SAR2 = 10-bit address (1)]
S
1
2
3
4
5
6
7
8
9
1 to 8
9
DATA
ACK
Sr
1
3
2
4
5
6
7
8
9
SCLn
SDAn
R/W# ACK
7-bit slave address (SAR0L)
R/W# ACK
7-bit slave address (SAR1L)
BBSY
Address mismatch
AAS0
Address match
Address match
AAS1
AAS2
[When SAR0L = 7-bit address, SAR1L = 7-bit address, and SAR2 = 10-bit address (2)]
S
1
2
3
4
5
6
7
8
9
1 to 8
9
DATA
ACK
Sr
1
2
3
4
5
1
1
1
1
0
6
7
8
9
W
ACK
SCLn
SDAn
R/W# ACK
7-bit slave address (SAR1L)
Upper 2 bits
BBSY
AAS0
AAS1
Address match
Address mismatch
AAS2
[When SAR0L = 7-bit address, SAR1L = 7-bit address, and SAR2 = 10-bit address (3)]
S
1
2
3
4
5
1
1
1
1
0
6
7
8
9
1 to 8
9
Sr
1
3
2
4
5
6
7
8
9
SCLn
SDAn
Upper 2 bits
W
ACK Lower 8 bits ACK
R/W# ACK
7-bit slave address (SAR0L)
BBSY
Address match
AAS0
AAS1
AAS2
Address mismatch
Address match
Figure 34.26
34.7.2
AASy flag set and clear timing with 7- and 10-bit address formats mixed
Detection of General Call Address
The IIC provides detection of the general call address (0000 000b + 0 [W]). General call address detection is enabled by
setting the GCAE bit in ICSER to 1.
If the address received after a start or restart condition is issued is 0000 000b + 1[R] (start byte), the IIC recognizes this
as the address of a slave device with an all-zero address, but not as the general call address.
When the IIC detects the general call address, both the GCA flag in ICSR1 and the RDRF flag in ICSR2 set to 1 on the
rising edge of the 9th cycle of the SCL clock. This leads to the generation of a receive data full interrupt (IICn_RXI). The
value of the GCA flag can be checked to confirm that the general call address is transmitted.
Operation after detection of the general call address is the same as normal slave receive operation.
[General call address reception]
S
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Data (DATA 1)
Data (DATA 2)
ACK
BBSY
AAS0
AAS1
Receive data (7-bit address)
Receive data (DATA 1)
AAS2
GCA
General call address match (0000 000b + W)
RDRF
Read ICDRR
(Dummy read [7-bit address])
Figure 34.27
Read ICDRR
(DATA 1)
Timing of GCA flag setting during reception of general call address
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.7.3
Device ID Address Detection
The IIC module provides detection of the device ID address in compliance with the I2C bus specification, revision 03.
When IIC receives 1111 100b as the first byte after a start or restart condition is issued with the DIDE bit in ICSER set to
1, it recognizes the address as a device ID, sets the DID flag in ICSR1 to 1 on the rising edge of the 8th SCL clock cycle
when the subsequent R/W# bit is 0, and then compares the second and subsequent bytes with its own slave address. If the
address matches the value in the slave address register, the IIC sets the associated AASy (y = 0 to 2) flag in ICSR1 to 1.
When the first byte received after the issue of a start or restart condition matches the device ID address (1111 100b) again
and the subsequent R/W# bit is 1, IIC does not compare the second and subsequent bytes, and sets the ICSR2.TDRE flag
to 1.
In the device ID address detection function, IIC sets the DID flag to 0 if a match with the IIC slave address is not
obtained, or a match with the device ID address is not obtained after a match with the IIC slave address, and a restart
condition is detected. If the first byte after the detection of a start or restart condition matches the device ID address (1111
100b) and the R/W# bit is 0, IIC sets the DID flag to 1 and compares the second and subsequent bytes with the slave
address of IIC. If the R/W# bit is 1, the DID flag holds the previous value and IIC does not compare the second and
subsequent bytes. In this way, reception of a device ID address can be checked by reading the DID flag after confirming
that TDRE = 1.
Additionally, prepare the device ID fields (3 bytes: 12 bits indicating the manufacturer + 9 bits identifying the part + 3
bits indicating the revision) that must be sent to the host after reception of a continuous device ID field as normal
transmit data. For details on the information that must be included in device ID fields, contact NXP Semiconductors.
Device-ID reception
S
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
W
ACK
1
to
8
9
Sr
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
R
ACK
SCLn
SDAn
Address
ACK
BBSY
Slave address match
AASy
Device-ID match (1111 100b + R)
Device-ID match (1111 100b + W)
DID
Receive data (7-bit address/lower 10 bits)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [7-bit address/lower 10 bits])
When address received after a restart condition is detected does not match the device-ID
S
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
W
ACK
1
to
8
9
Sr
1
2
3
4
5
6
7
8
9
R/W
ACK
SCLn
SDAn
Address
7-bit slave address (other station)
ACK
BBSY
Slave address match
Receive data (7-bit address/lower 10 bits)
Slave address mismatch
AASy
Device-ID mismatch
Device-ID match (1111 100b + W)
DID
RDRF
Read ICDRR
(Dummy read [7-bit address/lower 10 bits])
When address before the device-ID + R does not match the slave address
S
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
R
NACK
1
to
8
9
Sr
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
R
NACK
SCLn
SDAn
NACK
Comparing of the second and
subsequent bytes is stopped.
BBSY
AASy
DID
Device-ID match (1111 100b + R)
Device-ID match (1111 100b + R)
The previous value is retained.
TDRE
RDRF
Figure 34.28
AASy and DID flag set and clear timing during reception of device ID
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34. I2C Bus Interface (IIC)
S5D5 User’s Manual
34.7.4
Host Address Detection
The IIC provides host address detection while the SMBus is operating. When the HOAE bit in ICSER is set to 1 while
the SMBS bit in ICMR3 is 1, the IIC can detect the host address (0001 000b) in slave receive mode (MST and TRS bits
= 00b in ICCR2).
When the IIC detects the host address, the HOA flag in ICSR1 is set to 1 on the rising edge of the 9th SCL clock cycle. At
the same time, the RDRF flag in ICSR2 is set to 1 when the R/W# bit is 0 (Wr bit). This causes a receive data full
interrupt (IICn_RXI) to be generated. The HOA flag indicates that the host address was sent from another device.
If the bit following the host address (0001 000b) is a read bit (R/W# bit = 1), the IIC can also detect the host address.
After the host address is detected, the IIC operates in the same manner as in normal slave operation.
Host address reception
S
1
2
3
4
5
6
7
8
9
0
0
0
1
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Data (DATA 1)
Data (DATA 2)
ACK
BBSY
AAS0
Receive data (7-bit address)
AAS1
Receive data (DATA 1)
AAS2
HOA
Host address match (0001 000b)
RDRF
Read ICDRR
(Dummy read [7-bit address])
Figure 34.29
34.8
Read ICDRR
(DATA 1)
HOA flag set timing during reception of host address
Wakeup Function
The IIC provides a wakeup function that causes the MCU to transition from Software Standby mode to normal operation.
The wakeup function enables the reception of data when the system clock is stopped, and generates a wakeup interrupt
signal on a match of the slave address of the received data. This wakeup interrupt signal triggers the return to normal
operation.
The wakeup function has four operation modes:
Normal wakeup mode 1
Normal wakeup mode 2
Command recovery mode
EEP response mode.
Table 34.9 describes the behavior in these modes.
Table 34.9
Wakeup operation modes
Operation mode
ACK response timing
ACK response before wakeup
SCL state during wakeup
Normal wakeup mode 1
Before wakeup
ACK
Fixed low
Normal wakeup mode 2
After wakeup
Before wakeup: no response
After wakeup: ACK response
Fixed low
Command recovery mode
Before wakeup
ACK
Open
EEP response mode
Before wakeup
NACK
Open
Precautions on the use of the wakeup function
1. Disable the wakeup function (WUE = 0) after a wakeup interrupt triggers the transition from Software Standby
mode to normal operation.
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2. Do not change the content of the IIC registers while WUF = 0, even if the wakeup interrupt recovers the system
clock. Specify the register settings after confirming that WUF = 1.
3. Set WUE = WUIE = 1 and MST = TRS = 0 (slave reception mode) before entering Software Standby mode.
4. Do not transition to Software Standby mode while BBSY = 1.
5. The wakeup function supports the 7-bit slave address of the slave address register SARL0, the general call address,
and the host address. 10-bit slave addresses, SARL1 and SARL2, are not supported.
6. When the wakeup function is enabled, disable the interrupts selectable in the TIE, TEIE, RIE, NAKIE, SPIE, STIE,
ALIE, and TMOIE bits in the ICIER register.
7. When the wakeup function is enabled, do not use the timeout function.
8. If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for
example, the IRQn, the WUF flag is not set to 1. Follow the procedures shown in Figure 34.31 and Figure 34.36.
34.8.1
Normal Wakeup Mode 1
This section describes the behavior, timing, and an example operation of the normal wakeup mode 1.
In normal wakeup mode, a wakeup interrupt triggered by the match of the slave address initiates the transition to normal
operation as follows:
Before wakeup:
ACK is sent in response to the data received with the own slave address of the IIC.
During wakeup:
ACK response is made on the 9th clock cycle of SCL, after which SCL is held low.*1
After wakeup:
Normal operation continues.
If the slave address does not match, the SCL line is not held low after the 9th clock cycle of SCL, and the slave
operation continues.
Figure 34.30 shows an operation example, and Figure 34.32 shows the detailed timing.
Note 1. Between the 9th clock cycle and the 1st clock cycle during wakeup, WAIT = 1 is invalid.
If the transition from Software Standby mode is triggered by an interrupt (such as IRQn) other than a wakeup interrupt,
such as the IRQn for example, the WUF flag is not set to 1. Figure 34.31 shows an operation example.
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IIC normal operation
No
BBSY = 0
*1
[1] Wait until I2C bus is free and stay in standby state.
Yes
MST = 0 & TRS = 0
(Slave receive)
No
Yes
IICRST = 0 (& ICE = 1)
[2] Negate internal reset (if asserted).
WUACK Setting, WUIE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt.
WUE = 1
[4] Enable wakeup function.
WUSEN = 0
[5] Set WUSEN to 0.
No
WUASYF = 1
Yes
ICIER = 00h
[6] Disable all interrupt requests except WUI.
WFI instruction
[7] Stop PCLKB to IIC. IIC continues to receive.
Wakeup interrupt
WUF = 1
No
[9] Wait for WUF = 1.
[10] Set WUSEN to 1.
WUSEN = 1
WUSYF = 1
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match).
No
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling.
WUF = 0
WUF = 0
No
Yes
WUIE = 0
[12] Disable wakeup interrupt.
WUE = 0
[13] Disable wakeup function.
TRS = 1
No
Slave receive processing
Yes
Slave transmit processing
Note 1.
Do not issue start condition between BBSY = 0 and executing WFI instruction.
Figure 34.30
Note:
Example operation of normal wakeup mode 1 when wakeup is triggered by a wakeup interrupt on
match of the slave address
See Precautions on the use of the wakeup function.
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WUE = 1
WUSEN = 0
[1] Start PCLKB to IIC due to other return factor (IRQ).
WUASYF = 1
No
[2] Set WUSEN to 1.
Yes
[3] Disable wakeup interrupts.
ICIER = 00h
WFI instruction
[4] Disable wakeup function.
*1
[5] Reset IIC (ICE = 0 & IICRST = 1).
Start system clock due to
other return factor (IRQ)
WUSEN = 0
[1]
Yes
No
Continue
slave mode?
Yes
No
[2]
WUSEN = 1
WUSYF = 1
Wakeup interrupt
WUSEN = 1
No
No
WUSYF = 1
Yes
Yes
WUIE = 0
[3]
WUIE = 0
WUE = 0
[4]
WUE = 0
ICE = 0 & IICRST = 1
[5]
ICE = IICRST = 1, initialize
[6]
ICE = 1 & IICRST = 0
[7]
From here, the sequence is the same
as step [9] onward, as in Figure 34.30
for normal wakeup mode 1, and
Figure 34.33 for normal wakeup
mode 2.
[6] Reset IIC (internal reset: ICE = 1 & IICRST = 1).
Initial settings.
[7] Negate internal reset.
IIC normal operation
Note 1.
Figure 34.31
Note:
Before this step, the flow is the same as Figure 31.30.
Example operation of normal wakeup modes 1 and 2 when wakeup by the interrupt other than IIC
wakeup interrupt, for example, IRQn
For details on the IIC initial settings, see section 34.3.2, Initial Settings.
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Normal wakeup mode 1
As with normal operation, an ACK response when there is a match with the IIC own slave address, and low hold between SCL until the return
Before wake-up: own slave ACK response. During wake-up: SCL low hold after at 9th SCL. After wake-up: continue normal operation.
Active
Software Standby Active
(during wake-up)
Software Standby (before wake-up)
Active (after wake-up)
Continue to receive after returning (WAIT = 0)
WFI command
ST
WUACK = 0 (ACK return)
1
SCL
2
3
4
5
6
7
SLAVE ADDRESS
SDA
8
W
ICDRR read
9
Low hold period
1
2
3
4
5
6
7
8
WUF 0 clear
(0 write after 1 read)
9
DATA
ACK
ICDRR read
SP
ACK
WUF
AAS0
RDRF
TRS
Continue to transmit after returning (WAIT = 0)
WUF 0 clear
ICDRT write
WUACK = 0 (ACK return)
SCL
1
2
SDA
3
4
5
6
SLAVE ADDRESS
7
8
9
Low hold period
1
2
ICDRT write
3
R ACK
4
5
6
7
8
DATA
9
1
SP
2
ACK
3
4
5
6
DATA
7
8
9
NACK
WUF
AAS0
TDRE
TRS
Asynchronous synchronous switching period
Figure 34.32
34.8.2
Timing of normal wakeup mode 1
Normal Wakeup Mode 2
This section describes the behavior, timing, and an example operation of normal wakeup mode 2.
A wakeup interrupt triggered by a match of the slave address initiates the transition to normal operation as follows:
Before wakeup:
No response to data received with its own slave address until the end of the 8th SCL cycle.
During wakeup:
SCL line held low during the 8th and 9th clock cycles.
After wakeup:
ACK returns on the 9th clock cycle of SCL, and normal operation continues.
If the slave address does not match, the SCL line is not held low after the 8th SCL clock cycle, and the slave
operation continues.
Figure 34.34 provides detailed timing and Figure 34.33 shows an example operation.
If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, such as the IRQn
for example, the WUF flag is not set to 1. Follow the operation shown in Figure 34.31.
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IIC normal operation
No
BBSY = 0
*1
[1] Wait until I2C bus is free and stay in standby state.
Yes
MST = 0 & TRS = 0
(Slave receive)
No
Yes
IICRST = 0 (& ICE = 1)
[2] Negate internal reset (if asserted).
WUACK Setting, WUIE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt.
WUE = 1
[4] Enable wakeup function.
WUSEN = 0
[5] Set WUSEN to 0.
No
WUASYF = 1
Yes
ICIER = 00h
[6] Disable all interrupt requests except WUI.
WFI instruction
[7] Stop PCLKB to IIC. IIC continues to receive.
Wakeup interrupt
WUF = 1
No
[9] Wait for WUF = 1.
[10] Set WUSEN to 1.
WUSEN = 1
WUSYF = 1
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match).
No
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling.
WUF = 0
WUF = 0
No
Yes
WUIE = 0
[12] Disable wakeup interrupt.
WUE = 0
[13] Disable wakeup function.
TRS = 1
No
Slave receive processing
Yes
Slave transmit processing
Note 1.
Do not issue start condition between BBSY = 0 and executing WFI instruction.
Figure 34.33
Note:
Example operation of normal wakeup mode 2 when wakeup is triggered by a wakeup interrupt on
match of the slave address
See Precautions on the use of the wakeup function.
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Normal wakeup mode 2
SCL held low until wakeup on own slave match. ACK response after wakeup.
Before wakeup: own slave – response. During wake-up: SCL held low between 8th and 9th SCL. After wakeup: normal operation continues after own slave ACK response.
Active
Software Standby active
(during wakeup)
Software Standby (before wakeup)
Active (after wakeup)
Continue to receive after returning (WAIT = 0)
WFI command
1
SCL
ICDRR read
WUF = 0 clear
ST
2
3
4
5
6
7
SLAVE ADDRESS
SDA
8
W
Low hold period
NACK
9
1
2
3
4
5
ACK
6
7
8
ICDRR read
SP
9
DATA
ACK
WUF
AAS0
RDRF
TRS
WUF = 0 clear
Continue to transmit after returning (WAIT = 0)
1
SCL
SDA
2
3
4
5
6
SLAVE ADDRESS
ICDRT write
7
8
R
Low hold period
NACK
9
1
2
ICDRT write
3
ACK
4
5
6
DATA
7
8
9
ACK
1
SP
2
3
4
5
DATA
6
7
8
9
N ACK
WUF
AAS0
TDRE
TRS
Asynchronous synchronous switching period
Figure 34.34
34.8.3
Timing of normal wakeup mode 2
Command Recovery Mode and EEP Response Mode (Special Wakeup Modes)
This section describes the behavior, timing, and example operations of the command recovery and EEP response modes.
In the command recovery and EEP response modes, the SCL line is not held low during the wakeup period (after the rise
of the 9th clock cycle of SCL). Therefore, other IIC devices can use the I2C bus during this period.
A wakeup interrupt triggered by a match of the slave address initiates the transition to normal operation as follows:
Before wakeup: In response to data received with its own slave address, IIC returns ACK (command recovery
mode) or NACK (EEP response mode).
During wakeup: The SCL line is not held low.
After wakeup:
Normal operation continues after IIC initialization.
If the slave address does not match, the slave operation continues.
Note:
Note:
Because the SCL line is not held low during wakeup, transmission or reception of the data that follows the slave
address is not possible.
The command recovery and EEP response modes are internal reset states (ICE = IICRST = 1). Therefore, the
match of the slave address does not set the flags HOA, GCA, ASS0, ASS1, and ASS2 in the ICSR1 register.
If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, such as the IRQn
for example, the WUF flag is not set to 1. Follow the operation shown in Figure 34.36.
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IIC normal operation
No
BBSY = 0
*1
[1] Wait until I2C bus is free and stay in standby state.
Yes
MST = 0 & TRS = 0
(Slave receive)
No
Yes
IICRST = 1 & ICE = 1
[2] Internal reset is asserted.
WUACK Setting, WUIE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt.
WUE = 1
[4] Enable wakeup function.
WUSEN = 0
[5] Set WUSEN to 0.
No
WUASYF = 1
Yes
[6] Disable all interrupt requests except WUI.
ICIER = 00h
[7] Stop PCLKB to IIC. IIC continues to receive.
WFI instruction
Wakeup interrupt
WUF = 1
No
WUSEN = 1
WUSYF = 1
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match).
[9] Wait for WUF = 1.
[10] Set WUSEN = 1.
No
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling.
WUF = 0
WUF = 0
No
Yes
WUIE = 0
[12] Disable wakeup interrupt.
WUE = 0
[13] Disable wakeup function.
ICE = 0 & IICRST = 1
ICE = IICRST = 1; Initialize
ICE = 1 & IICRST = 0
[14] Reset IIC (ICE = 0 & IICRST = 1).
[15] Reset IIC (internal reset: ICE = 1 & IICRST = 1). Make initial settings.
[16] Negate internal reset.
IIC Normal Operation
Note 1.
Figure 34.35
Note:
Do not issue start condition between BBSY = 0 and executing WFI instruction.
Example operation of command recovery mode and EEP response mode when wakeup is
triggered by a wakeup interrupt on match of the slave address
See Precautions on the use of the wakeup function.
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WUE = 1
[1] Start PCLKB to IIC due to other return factor (IRQ).
WUSEN = 0
[2] Set WUSEN to 1.
[3] Disable wakeup interrupts.
WUASYF = 1
No
[4] Disable wakeup function.
Yes
[5] Reset IIC (ICE = 0 & IICRST = 1).
ICIER = 00h
WFI instruction
Start system clock supply by
other return factor (IRQ)
[1]
WUSEN = 0
Yes
No
No
Continue slave mode
in Command return mode/
EEP response mode?
[2]
WUSEN = 1
Yes
WUSYF = 1
Wakeup interrupt
No
From here, the sequence is the same
as step [9] onward, as in Figure
34.35.
Yes
WUIE = 0
[3]
WUE = 0
[4]
ICE = 0 & IICRST = 1
[5]
ICE = IICRST = 1, initialize
[6]
ICE = 1 & IICRST = 0
[7]
[6] Reset IIC (internal reset: ICE = 1 & IICRST = 1).
Make initial settings.
[7] Negate internal reset.
IIC normal operation
Figure 34.36
Note:
Example operation of command recovery mode and EEP response mode when wakeup is
triggered by the interrupt other than IIC wakeup interrupt, for example, the IRQn
For details on the IIC initial settings, see section 34.3.2, Initial Settings.
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Command recovery and EEP response modes
Reply ACK / NACK in the period from wakeup start to wakeup processing.
Reply ACK if own slave is specified again after IICRST release after wakeup.
Before wakeup: own slave ACK/NACK response. During wakeup: no SCL low hold. After wakeup: continue normal operation.
Active
Software Standby active
(during wakeup)
Software Standby (before wakeup)
Active (after wakeup)
WFI command
SCL
1
2
SDA
3
4
5
6
7
SLAVE ADDRESS
8
R/W#
9
1
2
A/NA
3
5
6
DATA
0
BC
4
0
BBSY
START
WUF
AAS0
TDRE/
RDRF
Asynchronous synchronous switching period
Figure 34.37
34.8.4
Timing of command recovery and EEP response modes
Precautions for WFI Instruction Execution
In the wakeup function examples shown in Figure 34.30, Figure 34.33, and Figure 34.35, make sure that the start
condition is not issued during the period from the setting of BBSY = 0 to the execution of the WFI instruction.
When a start condition is issued during this period, NACK is returned after the reception of the first byte of the first data
block. Detection of the start or restart condition then enables the wakeup function.
34.9
34.9.1
Automatic Low-Hold Function for SCL
Function to Prevent Wrong Transmission of Transmit Data
If the I2C Bus Shift Register (ICDRS) is empty when data has not been written to the I2C Bus Transmit Data Register
(ICDRT) with the IIC in transmission mode (TRS bit = 1 in ICCR2), the SCLn line is automatically held at the low level
over subsequent intervals. This low-hold period is extended until the transmit data is written, which prevents the
unintended transmission of erroneous data.
Master transmit mode
Low-level interval after a start or restart condition is issued
Low-level interval between the 9th clock cycle of one transfer and the 1st clock cycle of the next.
Slave transmit mode
Low-level interval between the 9th clock cycle of one transfer and the 1st clock cycle of the next.
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Automatic low-hold
(to prevent wrong
transmission)
1
2
Master transmit mode
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
Automatic low-hold (to prevent wrong transmission)
8
9
W
ACK
1
2
3
4
5
6
7
8
9
SCLn
SDAn
7-bit slave address
Data (DATA 1)
ACK
BBSY
Transmit data (7-bit address + W)
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(7-bit address + W)
Write data to ICDRT
(DATA 1)
Slave transmit mode
S
1
Write data to ICDRT
(DATA 2)
Automatic low-hold (to prevent wrong transmission)
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
Automatic low-hold
(to prevent wrong
transmission)
1
2
3
SCLn
SDAn
7-bit slave address
BBSY
Data (DATA 1)
ACK
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(DATA 1)
Figure 34.38
34.9.2
Write data to ICDRT
(DATA 2)
Automatic low-hold operation in transmit mode
NACK Reception Transfer Suspension Function
This function suspends transfer operation when NACK is received in transmit mode (TRS bit = 1 in ICCR2). This
function is enabled when the NACKE bit in ICFER is set to 1. If the next transmit data is already written (TDRE flag = 0
in ICSR2) when NACK is received, the next data transmission on the falling edge of the 9th SCL clock cycle is
automatically suspended. This prevents the SDAn line output level from being held low when the MSB of the next
transmit data is 0.
If the transfer operation is suspended by this function (NACKF flag = 1 in ICSR2), transmit and receive operations are
discontinued. To restore transmit or receive operations, set the NACKF flag to 0. In master transmit mode, after a restart
or stop condition is issued, set the NACKF flag to 0, and then issue a start condition again.
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S5D5 User’s Manual
Master transmit mode
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
Bus free time (ICBRL)
8
9
P
S
1
2
3
4
5
6
7
8
9
W
ACK
SCLn
SDAn
W
7-bit slave address
BBSY
Transmit data
(7-bit address + W)
AASy
NACK
Transfer suspended
7-bit slave address
Transmit data
(7-bit address + W)
Transmit data (DATA 1)
Transmit data (DATA 1)
TRS
TDRE
NACKF
Write data to ICDRT register Write data to ICDRT
(7-bit address + W)
register (DATA 1)
Write 1
to SP bit
Slave transmit mode
S
1
Clear
NACKF flag
Write data to ICDRT
register
(7-bit address + W)
Write data to ICDRT
register (DATA 1)
Automatic low-hold (to prevent wrong transmission)
2
3
4
5
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
P
Bus free time
(ICBRL)
SCLn
SDAn
7-bit slave address
Data (DATA 1)
Transfer suspended
BBSY
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
NACKF
Write data to ICDRT
register (DATA 1)
Figure 34.39
34.9.3
Write data to ICDRT
register (DATA 2)
Write 1 to SP bit
Clear NACKF flag
Suspension of data transfer when NACK is received, when NACKE = 1
Function to Prevent Failure to Receive Data
If response processing is delayed when receive data (ICDRR) read is delayed for a period of one transfer frame or more
with receive data full (RDRF flag = 1 in ICSR2) in receive mode (TRS = 0 in ICCR2), the IIC holds the SCLn line low
automatically immediately before the next data is received to prevent failure to receive data.
This function is also enabled even if the read processing of the final receive data is delayed and, in the meantime, the IIC
slave address is designated after a stop condition is issued. This function does not interfere with other communication
because the IIC does not hold the SCLn line low when a mismatch with its own slave address occurs after a stop
condition is issued.
Periods in which the SCLn line is held low can be selected with a combination of the WAIT and RDRFS bits in ICMR3.
(1)
1-byte receive operation and automatic low-hold function using the WAIT bit
When the WAIT bit in ICMR3 is set to 1, IIC performs a 1-byte receive operation using the WAIT bit function.
Additionally, when the ICMR3.RDRFS bit is 0, IIC automatically sends the ACKBT bit value in ICMR3 for the
acknowledge bit in the period from the falling edge of the 8th SCL clock cycle to the falling edge of the 9th SCL clock
cycle, and automatically holds the SCLn line low on the falling edge of the 9th SCL clock cycle using the WAIT bit
function. This low-hold is released by reading data from ICDRR, which enables byte-wise receive operation.
The WAIT bit function is enabled for receive frames after a match with the IIC slave address, including the general call
address and host address, is obtained in master or slave receive mode.
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(2)
1-byte receive operation (ACK/NACK transmission control) and automatic low-hold function
using the RDRFS bit
When the RDRFS bit in ICMR3 is set to 1, the IIC performs a 1-byte receive operation using the RDRFS bit function.
When the RDRFS bit is set to 1, the RDRF (receive data full) flag in ICSR2 is set to 1 on the rising edge of the 8th SCL
clock cycle, and the SCLn line is automatically held low on the falling edge of the 8th SCL clock cycle. This low-hold is
released by writing a value to the ACKBT bit in ICMR3, but cannot be released by reading data from ICDRR, which
enables receive operation through the ACK or NACK transmission control based on the data received in byte units.
The RDRFS bit function is enabled for receive frames after a match with the IIC slave address, including the general call
address and host address, is obtained in master or slave receive mode.
Automatic low-hold
(to prevent failure to receive data)
RDRFS = 0, WAIT = 0
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
SCLn
SDAn
ACK
ACK
Data
ACK
Data
Data
RDRF
Read ICDRR
RDRFS = 0, WAIT = 1
9
Read ICDRR
Automatic low-hold (WAIT)
1
2
3
4
5
Read ICDRR
Automatic lowhold (WAIT)
1
Automatic low-hold (WAIT)
6
7
8
9
1
2
3
4
5
6
7
8
9
SCLn
SDAn
ACK
ACK
Data
ACK
Data
RDRF
Read ICDRR
Read ICDRR
RDRFS = 1, WAIT = 0
2
3
Read ICDRR
Automatic low-hold
(to prevent failure to
receive data)
8
Automatic low-hold (RDRFS)
4
5
6
7
8
9
1
2
3
4
5
6
7
Automatic lowhold (RDRFS)
9
1
SCLn
SDAn
ACK
Data
Data
ACK
RDRF
ACKBT
Write 0 to ACKBT
RDRFS = 1, WAIT = 1
2
3
4
5
Automatic low-hold
(RDRFS)
6
7
8
Read ICDRR Read ICDRR
Automatic low-hold (WAIT)
9
1
2
3
4
5
6
7
Write 0 to ACKBT
Automatic low-hold
(RDRFS)
9
1
8
SCLn
SDAn
Data
ACK
Data
ACK
RDRF
ACKBT
Write 0 to ACKBT
Figure 34.40
Read ICDRR
Read ICDRR Write 0 to ACKBT
Automatic low-hold operation in receive mode using the RDRFS and WAIT bits
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34. I2C Bus Interface (IIC)
34.10 Arbitration-Lost Detection Functions
In addition to the normal arbitration-lost detection function defined by the I2C bus standard, IIC provides functions to
prevent double-issue of a start condition, detect arbitration-lost during the transmission of NACK, and detect arbitrationlost in slave transmit mode.
34.10.1
Master Arbitration-Lost Detection (MALE Bit)
IIC drives the SDAn line low to issue a start condition. However, if the SDAn line was already driven low by another
master device issuing a start condition, IIC regards its own start condition as an error and considers this a loss in
arbitration. Priority is given to transfer by the other master device. Similarly, if a request to issue a start condition is made
by setting the ST bit in ICCR2 to 1 while the bus is busy (BBSY flag = 1 in ICCR2), IIC regards this as a double-issuingof-start-condition error and considers itself to have lost the arbitration. This prevents a failure of transfer resulting from a
start condition issued while transfer is in progress.
When a start condition is issued successfully, if the transmit data including the address bits (internal SDA output level)
and the level on the SDAn line do not match (high output as the internal SDA output, meaning the SDAn pin is in the
high-impedance state) and a low level is detected on the SDAn line, IIC loses the arbitration.
After a loss in arbitration of mastership, the IIC immediately enters slave receive mode. If a slave address, including the
general call address, matches its own address at this time, the IIC continues in slave operation.
A loss in arbitration of mastership is detected when the following conditions are met while the MALE bit in ICFER is 1
(master arbitration-lost detection enabled).
[Master arbitration-lost conditions]
Mismatching of the internal level for output on SDA and the level on the SDAn line after a start condition was
issued by setting the ST bit in ICCR2 to 1 while the BBSY flag in ICCR2 is set to 0 (erroneous issuing of a start
condition)
Setting of the ST bit in ICCR2 to 1 (start condition double-issue error) while the BBSY flag is 1
When the transmit data excluding acknowledge (internal SDA output level) does not match the level on the SDAn
line in master transmit mode (MST and TRS bits = 11b in ICCR2).
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[When slave addresses conflict]
1
S
2
3
4
5
6
Transmit data mismatch
(arbitration lost)
Release SCL/SDA
SCLn
SDAn
1
S
1
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
0
ACK
Data
BBSY
Data
Address match
Address mismatch
MST
TRS
AL
AASy
TDRE
Clear AL to 0
[When data transmission conflicts after general call address is sent]
S
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
Transmit data mismatch
(arbitration lost)
5
Release SCL/SDA
SCLn
SDAn
S
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
ACK
0
Data
BBSY
MST
Receive data
TRS
AL
GCA
General call address match (0000 000b + W)
Clear AL to 0
RDRF
Read ICDRR
Figure 34.41
Examples of master arbitration-lost detection when MALE = 1
Bus free (BBSY = 0) start condition issuance (ST = 1) error
Bus busy (BBSY =1) start condition issuance (ST = 1) error
SDA mismatch
PCLKB
PCLKB
PCLKB
SCLn
SCLn
SCLn
SDAn
SDAn
SDAn
S
1
SCLn
SDAn
ST = 1, BBSY = 1
S
1
2
S
SCLn
SCLn
SDAn
SDAn
ST = 1, BBSY = 1
BBSY
BBSY
BBSY
MST
MST
MST
TRS
TRS
TRS
AASy
AASy
AASy
ST
ST
ST
AL
AL
AL
Write 1 to ST
Figure 34.42
Write 1 to ST
1
2
6
7
8
9
7-bit/10-bit slave address
R
ACK
1
ST = 1,
BBSY = 1
Write 1 to ST
Arbitration-lost when start condition is issued when MALE = 1
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34.10.2
Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit)
This function causes arbitration to be lost if the internal SDA output level does not match the level on the SDAn line
during transmission of NACK in receive mode. Arbitration is lost because of a conflict between NACK and ACK
transmissions when two or more master devices receive data from the same slave device simultaneously in a multimaster system. Such conflict occurs when multiple master devices send or receive the same information through a single
slave device. Figure 34.43 shows an example of arbitration-lost detection during the transmission of NACK.
NACK transmission mismatch
(arbitration lost)
[Conflict during transmission of NACK (ACK received)]
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
Release SCL/SDA
8
9
SCLn
SDAn
ACK
Data
2
3
4
5
6
7
8
9
Data
1
2
3
4
5
NACK
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Data
ACK
ACK
Data
Data
BBSY
MST
Receive data
TRS
Receive data
AL
RDRFS
RDRF
ACKBT
Write 1 to RDRFS
Figure 34.43
Read ICDRR
Read ICDRR
Write 1 to ACKBT
Clear AL to 0
Example of arbitration-lost detection during transmission of NACK when NALE = 1
The following description explains arbitration-lost detection using an example in which two master devices (master A
and master B) and a single slave device are connected through the bus. In this example, master A receives 2 bytes of data
from the slave device, and master B receives 4 bytes of data from the slave device.
If master A and master B access the slave device simultaneously, because the slave address is identical, arbitration is not
lost in either master A or B during access to the slave device. Therefore, both master A and master B recognize that they
have obtained the bus mastership and operate as such. Master A sends NACK when it has received the 2 final bytes of
data from the slave device. Meanwhile, master B sends ACK because it has not received the required 4 bytes of data.
The NACK transmission from master A and the ACK transmission from master B conflict. In general, if a conflict like
this occurs, master A cannot detect the ACK transmitted by master B and issues a stop condition. The stop condition
issue conflicts with the SCL clock output of master B, which disrupts communication.
When IIC receives ACK during transmission of NACK, it detects a defeat in conflict with other master devices and
causes arbitration to be lost. If arbitration is lost during transmission of NACK, IIC immediately cancels the slave match
condition and enters slave receive mode. This prevents a stop condition from being issued, preventing a communication
failure on the bus.
Similarly, in the ARP command processing of SMBus, the function to detect loss of arbitration during transmission of
NACK is also available for eliminating the extra clock cycle processing, such as FFh transmission processing, which is
required if the UDID (Unique Device Identifier) of the assigned address does not match in the Get UDID general
processing after the Assign Address command.
The IIC detects arbitration-lost during transmission of NACK when the following condition is met with the NALE bit in
ICFER set to 1 (arbitration-lost detection during NACK transmission enabled).
[Condition for arbitration-lost during NACK transmission]
When the internal SDA output level does not match the SDAn line (ACK is received) during transmission of NACK
(ACKBT bit = 1 in ICMR3).
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34.10.3
Slave Arbitration-Lost Detection (SALE Bit)
This function causes arbitration to be lost if the transmit data (internal SDA output level) and the level on the SDAn line
do not match (high output as the internal SDA output, meaning the SDAn pin is in the high-impedance state), and the low
level is detected on the SDAn line in slave transmit mode. This arbitration-lost detection function is mainly used when
transmitting a UDID (Unique Device Identifier) over an SMBus.
When IIC loses slave arbitration, IIC is immediately released from the slave-matched state and enters slave receive
mode. This function can detect conflicts of data during transmission of UDIDs over an SMBus and eliminates
subsequent redundant processing for the transmission of FFh.
IIC detects slave arbitration-lost when the following condition is met with the SALE bit in ICFER set to 1 (slave
arbitration-lost detection enabled).
[Condition for slave arbitration-lost]
When transmit data excluding acknowledge (internal SDA output level) does not match the SDAn line in slave
transmit mode (MST and TRS bits = 01b in ICCR2).
Transmit data mismatch
(arbitration lost)
[Conflict during data transmission]
2
3
4
5
6
7
8
9
1
2
3
4
Release SCL/SDA
5
SCLn
SDAn
ACK
Data
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
SCLn
SDAn
Data
ACK
ACK
0
Data
BBSY
MST
TRS
AL
TDRE
Write data to ICDRT
Figure 34.44
Clear AL to 0
Example of slave arbitration-lost detection when SALE = 1
34.11 Start, Restart, and Stop Condition Issuing Function
34.11.1
Issuing a Start Condition
IIC issues a start condition when the ST bit in ICCR2 is set to 1. When the ST bit is set to 1, a start condition request is
made, and IIC issues a start condition when the BBSY flag in ICCR2 is 0 (bus free state). When a start condition is
issued normally, IIC automatically shifts to the master transmit mode.
To issue a start condition:
1. Drive the SDAn line low (high level to low level).
2. Ensure that the time set in ICBRH and the start condition hold time elapse.
3. Drive the SCLn line low (high level to low level).
4. Detect low level on the SCLn line and ensure the low-level period of the SCLn line set in ICBRL elapses.
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34.11.2
Issuing a Restart Condition
IIC issues a restart condition when the RS bit in ICCR2 is set to 1.
When the RS bit is set to 1, a restart condition request is made, and IIC issues a restart condition when the BBSY flag in
ICCR2 is 1 (bus busy state) and the MST bit in ICCR2 is 1 (master mode).
To issue a restart condition:
1. Release the SDAn line.
2. Ensure that the low-level period of the SCLn line set in ICBRL elapses.
3. Release the SCLn line (low level to high level).
4. Detect a high level on the SCLn line and ensure the time set in ICBRL and the restart condition setup time elapse.
5. Drive the SDAn line low (high level to low level).
6. Ensure the time set in ICBRH and the restart condition hold time elapse.
7. Drive the SCLn line low (high level to low level).
8. Detect a low level on the SCLn line and ensure the low-level period of the SCLn line set in ICBRL elapses.
Note:
When issuing restart condition requests, write the slave address to ICDRT after confirming that ICCR2.RS = 0.
Data written while ICCR2.RS = 1 is not forwarded because of the retransmission condition before the occurrence.
[Restart condition issuing operation]
[Start condition issuing operation]
ICBRH
SCLn
SDAn
Hold time
ICBRL
ICBRH
SCLn
S Issue start
condition
SDAn
IIC
IIC
BBSY
BBSY
MST
MST
TRS
TRS
TDRE
TDRE
7 bits address +R/W#
ICDRT
Setup time
ICBRL
ICBRL
ICBRH
Hold time
ICBRL
Sr
Issue restart
condition
9
ACK/NACK
7 bits address +R/W#
ICDRT
START
START
RS
ST
Write 1 to ST bit
Write to ICDRT (7 bits address +R/W#)
Write 1 to RS bit
Accept start condition issuance
Figure 34.45
Write to ICDRT (7 bits address +R/W#)
Accept restart condition issuance
Start and restart condition issue timing using the ST and RS bits
Figure 34.46 shows the operation timing when a restart condition is issued after the master transmission.
To issue a restart condition after the master transmission:
1. Initialize the IIC using the details provided in section 34.3.2, Initial Settings.
2. Read the BBSY flag in IICR2 to check that the bus is free, and then set the ST bit in ICCR2 to 1 (start condition
issuance request). On receiving the request, IIC issues a start condition. At the same time, the BBSY flag and the
START flag in ICSR2 are automatically set to 1 and the ST bit automatically sets to 0. If the start condition is
detected and the internal levels for the SDA output state and the levels on the SDAn line match while the ST bit is 1,
IIC recognizes that a start condition is successfully issued as requested by the ST bit. The MST and TRS bits in
ICCR2 automatically set to 1, placing IIC in master transmit mode. The TDRE flag in ICSR2 also automatically sets
to 1 when the TRS bit is set to 1.
3. Check that the TDRE flag in ICSR2 is 1, and then write the value for transmission (the slave address and the R/W#
bit) to ICDRT. After the transmit data is written to ICDRT, the TDRE flag automatically sets to 0, the data is
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transferred from ICDRT to ICDRS, and the TDRE flag again sets to 1. After the byte containing the slave address
and R/W# bit has been transmitted, the value of the TRS bit is automatically updated to select master transmit or
master receive mode according to the value of the transmitted R/W# bit. If the value of the R/W# bit is 0, IIC
continues in master transmit mode. If the ICSR2.NACKF flag is 1 at this time, indicating that no slave device
recognized the address or that there was an error in communications, write 1 to ICCR2.SP bit to issue a stop
condition. To transmit data with an address in the 10-bit format, start by writing 1111 0b, the 2 upper bits of the
slave address, and W to ICDRT as the first address transmission. Then, as the second address transmission, write the
8 lower bits of the slave address to ICDRT.
4. After confirming that the TDRE flag in ICSR2 is 1, write the data for transmission to the ICDRT register. IIC
automatically holds the SCLn line low until the data for transmission is ready, and a restart or stop condition is
issued.
5. After all bytes of data for transmission are written to the ICDRT register, wait until the value of the TEND flag in
ICSR2 returns to 1. Then, after checking that the START flag in ICSR2 is 1, set the START flag in ICSR2 to 0.
6. Set the RS bit in ICCR2 to 1 (restart condition issuance request). Upon receiving the request, IIC issues a restart
condition.
7. After checking that the START flag in ICSR2 is 1, write the value for transmission (the slave address and the R/W#
bit) to ICDRT.
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
8
9
1
2
3
b0
ACK
b7
b6
b5
4
5
6
7
8
9
b4
b3
b2
b1
b0
ACK
1
Sr
SCL0
SDA0
7-bit slave address
W
b7
Data (DATA 1)
7-bit slave address
BBSY
MST
TRS
Transmit data (7-bit address + W)
Transmit data (DATA 1)
Transmit data (7-bit address + R)
TDRE
TEND
RDRF
7-bit address+W
ICDRT
Data (DATA 1)
7-bit address+W
ICDRS
7-bit address+R
Data (DATA 1)
7-bit address+R
XXXX (Initial value / Last data for reception)
ICDRR
“0” (ACK)
ACKBT
“X” (ACK/NACK)
ACKBR
“0” (ACK)
“0” (ACK)
START
ST
RS
Write data to
Write data to
ICDRT
Write 1
ICDRT
to ST (7-bit address + W) (DATA 1)
(2)
Figure 34.46
34.11.3
(3)
(4)
Clear
Write data to
Write 1
START
ICDRT
to RS
(7-bit address + R)
to 0
(5)
(6)
(7)
Restart condition issue timing after master transmission.
Issuing a Stop Condition
IIC issues a stop condition when the SP bit in ICCR2 is set to 1.
When the SP bit is set to 1, a stop condition request is made, and the IIC issues a stop condition when the BBSY flag in
ICCR2 is 1 (bus busy state) and the MST bit in ICCR2 is 1 (master mode).
To issue a stop condition:
1. Drive the SDAn line low (high level to low level).
2. Ensure that the low-level period of the SCLn line set in ICBRL elapses.
3. Release the SCLn line (low level to high level).
4. Detect a high level on the SCLn line and ensure that the time set in ICBRH and the stop condition setup time elapse.
5. Release the SDAn line (low level to high level).
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6. Ensure the time set in ICBRL and the bus free time elapse.
7. Clear the BBSY flag to 0 to release the bus mastership.
ICBRL
ICBRH
SCLn
SDAn
ICBRL
ICBRH
8
b0
ICBRL
9
Issue stop
condition
ACK/NACK
Setup time
ICBRL
ICBRH
Bus free time
P
IIC
BBSY
MST
TRS
TDRE
STOP
SP
Write 1 to SP
Figure 34.47
Accept stop condition issuance
Clear STOP to 0
Stop condition issue timing using the SP bit
34.12 Bus Hanging
If the clock signals from the master and slave devices are out of synchronization because of noise or other factors, the I2C
bus might hang with a fixed level on the SCLn line or SDAn line.
To manage bus hanging, the IIC has the following:
A timeout function to detect hanging by monitoring the SCLn line
A function for the output of an extra SCL clock cycle to release the bus from a hung state because of clock signals
being out of synchronization
An IIC reset function
An internal reset function.
By checking the SCLO, SDAO, SCLI, and SDAI bits in ICCR1, it is possible to see whether the IIC or its
communicating partner is placing the low level on the SCLn or SDAn lines.
34.12.1
Timeout Function
The timeout function can detect when the SCLn line is stuck longer than the predetermined time. IIC can detect an
abnormal bus state by monitoring that the SCLn line is stuck low or high for a predetermined time.
The timeout function monitors the SCLn line state and counts the low-level or high-level period using the internal
counter. The timeout function resets the internal counter each time the SCLn line changes (rises or falls), but continues to
count unless the SCLn line changes. If the internal counter overflows because no SCLn line changes, IIC can detect the
timeout and report the bus hung state.
This timeout function is enabled when the ICFER.TMOE bit is 1. It detects a hung state when the SCLn line is stuck low
or high during the following conditions:
The bus is busy (ICCR2.BBSY flag is 1) in master mode (ICCR2.MST bit is 1)
IIC slave address is detected (ICSR1 register is not 00h) and the bus is busy (ICCR2.BBSY flag is 1) in slave mode
(ICCR2.MST bit is 0)
The bus is free (ICCR2.BBSY flag is 0) while a start condition is requested (ICCR2.ST bit is 1).
The internal counter of the timeout function uses the internal reference clock (IIC) set in the CKS[2:0] bits in ICMR1 as
a count source. It functions as a 16-bit counter when long mode is selected (TMOS bit = 0 in ICMR2) or a 14-bit counter
when short mode is selected (TMOS bit = 1).
The SCLn line level (low, high, or both levels) during which this counter is activated can be selected in the TMOH and
TMOL bits in ICMR2. If both TMOL and TMOH bits are set to 0, the internal counter is disabled.
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[Timeout function]
Start internal
counter
Start internal
counter
Clear internal
counter
Start internal
counter
Clear internal
counter
Clear internal
counter
Start internal
counter
Start internal
counter
Start internal
counter
Clear internal
counter
Clear internal
counter
Clear internal
counter
Clear internal
counter
IIC
BBSY
TMOE
TMOH
TMOL
Write 1 to TMOH
[Example of operation when TMOH = 1 and TMOL = 1]
Clear internal counter
7
8
9
When a stat condition is issued
S
1
Bus free time
2
7
7-bit slave address
Write 0 to TMOE
In the slave-address matched state
14-bit counter
overflows
TMOS = 1
TMOS = 0
Start internal counter
P
A/NA
Write 1 to TMOL
Write 0 to TMOL
8
9
R/W# ACK
1
16-bit counter
overflows
2
Data
BBSY
ST
TMOE
TMOF
Figure 34.48
34.12.2
Timeout function using the TMOE, TMOS, TMOH, and TMOL bits
Extra SCL Clock Cycle Output Function
In master mode, this function outputs extra SCL clock cycles to release the SDAn line of the slave device from being
held at the low level because the master is out of synchronization with the slave device.
This function is mainly used in master mode to release the SDAn line of the slave device from being fixed low by
including extra cycles of SCL output from IIC. It uses single cycles of the SCL clock for a bus error where IIC cannot
issue a stop condition because the slave device is holding the SDAn line at the low level. Do not use this function in
normal situations. Using it when communications are proceeding correctly leads to malfunctioning.
When the CLO bit in ICCR1 is set to 1 in master mode, a single cycle of the SCL clock at the transfer rate specified in the
CKS[2:0] bits in ICMR1, and in the ICBRH and ICBRL registers, is output as an extra clock cycle. After output of this
single cycle of the SCL clock, the CLO bit is automatically set to 0. More extra clock cycles can be output consecutively
by writing 1 to the CLO bit through software after having read CLO = 0.
When the IIC module is in master mode and the slave device is holding the SDAn line at the low level because
synchronization with the slave device is lost because of effects like noise, the output of a stop condition is not possible.
This function can be used to output extra cycles of SCL one by one to make the slave device release the SDAn line from
being held at the low level, and recover the bus from an unusable state. Release of the SDAn line by the slave device can
be monitored by reading the SDAI bit in ICCR1. After confirming the release of the SDAn line by the slave device,
complete the communication by reissuing the stop condition.
Use this function with the MALE bit in ICFER set to 0 (master arbitration-lost detection disabled). If the MALE bit is set
to 1 (enabled), arbitration is lost when the value of the SDAO bit in ICCR1 does not match the state of the SDAn line.
[Output conditions for using the CLO bit in ICCR1]
When the bus is free (BBSY flag in ICCR2 = 0) or in master mode (MST bit = 1 and BBSY flag = 1 in ICCR2)
When the communication device does not hold the SCLn line low.
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Figure 34.49 shows the operation timing of the extra SCL clock cycle output function (CLO bit).
ICBRH
SCLn
SDAn line is held low because of irregular bits
ICBRH
ICBRL
Extra clock cycle
output
ICBRL
9
ACK or Data 0
SDAn
Release SDAn line
ICBRH
MSB or Next Data
ICBRL
Extra clock cycle
output
Data 1
IIC
BBSY
MST
TRS
CLO
Accept CLO output
Figure 34.49
34.12.3
Write 1 to CLO
Write 1 to CLO
Extra SCL clock cycle output function using the CLO bit
IIC Reset and Internal Reset
The IIC module has two types of resets:
IIC reset, which initializes all registers, including the BBSY flag in ICCR2
Internal reset, which releases the IIC from the slave-address matched state and initializes the internal counter while
saving other settings.
After issuing a reset, always set the IICRST bit in ICCR1 to 0.
Both types of resets are valid for release from bus-hung states, because both restore the output state of the SCLn and
SDAn pins to the high-impedance state.
Issuing a reset during slave operation might lead to a loss of synchronization between the master device clock and the
slave device clock, therefore, avoid this when possible. In addition, monitoring of the bus state, such as for the presence
of a start condition, is not possible during an IIC reset (ICE and IICRST bits = 01b in ICCR1).
For a detailed description of the IIC and internal resets, see section 34.15, State of Registers when Issuing each
Condition.
34.13 SMBus Operation
IIC supports data communication conforming to the SMBus Specification, version 2.0. To perform SMBus
communication, set the SMBS bit in ICMR3 to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the
SMBus standard, set the CKS[2:0] bits in ICMR1, ICBRH, and ICBRL. In addition, specify the values in the DLCS bit
in ICMR2 and the SDDL[2:0] bits in ICMR2 to meet the data hold time specification of 300 ns or more. When the IIC is
used only as a slave device, the transfer rate setting is not required, but ICBRL must be set to a value longer than the data
setup time (250 ns).
For the SMBus device default address (1100 001b), use one of the slave address registers L0 to L2 (SARL0, SARL1, and
SARL2), and set the associated FS bit (7- or 10-bit address format select) in SARUy (y = 0 to 2) to 0 (7-bit address
format).
When transmitting the UDID (Unique Device Identifier), set the SALE bit in ICFER to 1 to enable the slave arbitrationlost detection function.
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34.13.1
(1)
34. I2C Bus Interface (IIC)
SMBus Timeout Measurement
Measuring slave device timeout
The following period (timeout interval: TLOW: SEXT) must be measured for slave devices in SMBus communication:
From start condition to stop condition.
To measure timeout for slave devices, measure the period from start condition detection to stop condition detection with
the GPT using the IIC start condition detection interrupt (STIn) and stop condition detection interrupt (SPIn). The
measured timeout period must be within the total clock low-level period [slave device] TLOW: SEXT: 25 ms (maximum)
of the SMBus standard.
If the time measured with the GPT exceeds the clock low-level detection timeout TTIMEOUT: 25 ms (minimum) of the
SMBus standard, the slave device must release the bus by writing 1 to the IICRST bit in ICCR1 to issue an internal reset
of the IIC. When an internal reset is issued, the IIC stops driving the bus for the SCLn and SDAn pins and makes the
SCLn/SDAn pin output high-impedance, which releases the bus.
(2)
Measuring master device timeout
The following periods (timeout interval: TLOW: MEXT) must be measured for master devices in SMBus communication:
From start condition to acknowledge bit
Between acknowledge bits
From acknowledge bit to stop condition.
To measure timeout for master devices, measure these periods with the GPT using the IIC start condition detection
interrupt (STIn), stop condition detection interrupt (SPIn), transmit end interrupt (IICn_TEI), or receive data full
interrupt (IICn_RXI). The measured timeout period must be within the total clock low-level extended period (master
device) TLOW: MEXT: 10 ms (maximum) of the SMBus standard, and the total of all TLOW: MEXT values from the start
condition to stop condition must be within TLOW: SEXT: 25 ms (maximum).
For the ACK receive timing (rising edge of the 9th SCL clock cycle), monitor the TEND flag in ICSR2 in master transmit
mode (master transmitter) and the RDRF flag in ICSR2 in master receive mode (master receiver). Perform byte-wise
transmit operations in master transmit mode, and hold the RDRFS bit in ICMR3 at 0 until the byte immediately before
the reception of the final byte in master receive mode. While the RDRFS bit is 0, the RDRF flag is set to 1 on the rising
edge of the 9th SCL clock cycle.
If the period measured with GPT exceeds the total clock low-level extended period (master device), TLOW: MEXT: 10 ms
(maximum) of the SMBus standard or the total of measured periods exceeds the clock low-level detection timeout,
TTIMEOUT: 25 ms (minimum) of the SMBus standard, the master device must stop the transaction by issuing a stop
condition. In master transmit mode, immediately stop the transmit operation (stop writing data to ICDRT).
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SMBus standard
Start
TLOW:SEXT: Total clock low-level extended period (slave device)
TLOW:MEXT: Total clock low-level extended period (master device)
Stop
TLOW:SEXT
Clk ACK
TLOW:MEXT
S
2
1
7
8
9
Clk ACK
TLOW:MEXT
1
2
7
8
9
Clk ACK
TLOW:MEXT
1
2
7
8
TLOW:MEXT
9
P
SCLn
SDAn
7-bit slave address
R/W# ACK
Data
ACK
Data
A/NA
BBSY
TDRE
TEND
RDRF
RDRFS
START
STOP
Measured with the GPT
Figure 34.50
34.13.2
SMBus timeout measurement
Packet Error Code (PEC)
The MCU provides a CRC calculator, which enables transmission of a packet error code (PEC) or allows checking the
received data in SMBus data communication for the IIC. For the CRC-generating polynomials of the CRC calculator, see
section 38, Cyclic Redundancy Check (CRC) Calculator.
In master transmit mode, the PEC data can be generated by writing all transmit data to the CRC Data Input register
(CRCDIR) in the CRC calculator.
In master receive mode, the PEC data can be checked by writing all receive data to CRCDIR in the CRC calculator and
comparing the obtained value in the CRC Data Output Register (CRCDOR) with the received PEC data.
To send ACK or NACK based on the match or mismatch result when the final byte is received as a result of the PEC code
check, set the RDRFS bit in ICMR3 to 1 before the rising edge of the 8th SCL clock cycle during reception of the final
byte, and hold the SCLn line low on the falling edge of the 8th clock cycle.
34.13.3
SMBus Host Notification Protocol (Notify ARP Master Command)
In communications over an SMBus, a slave device can temporarily act as a master device to notify the SMBus host (or
ARP master) of its own slave address or to request its own slave address from the SMBus host.
For a product using the MCU to operate as an SMBus host or ARP master, the host address (0001 000b) sent from the
slave device must be detected as a slave address, and so the IIC has a function for detecting the host address. To detect
the host address as a slave address, set the SMBS bit in ICMR3 and the HOAE bit in ICSER to 1. Operation after the host
address is detected is the same as normal slave operation.
34.14 Interrupt Sources
The IIC issues four types of interrupt requests:
Transfer error or event occurrence (detection of arbitration-lost, NACK, timeout, start or restart condition, or stop
condition)
Receive data full
Transmit data empty
Transmit end.
Table 34.10 lists details about the interrupt requests. The receive data full and transmit data empty interrupts can activate
data transfer by the DTC or DMAC.
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Table 34.10
Interrupt sources
Symbol
Interrupt source
IICn_EEI*5
Transfer error or event generation
Interrupt flag
DMAC/DTC
activation
AL
Not possible
NACKF
Interrupt condition
AL = 1, ALIE = 1
NACKF = 1, NAKIE = 1
TMOF
TMOF = 1, TMOIE = 1
START
START = 1, STIE = 1
STOP
STOP = 1, SPIE = 1
IICn_RXI*2, *5
Receive data full
RDRF
Possible
RDRF = 1, RIE = 1
IICn_TXI*1, *5
Transmit data empty
TDRE
Possible
TDRE = 1, TIE = 1
IICn_TEI*3, *5
Transmit end
TEND
Not possible
TEND = 1, TEIE = 1
IIC0_WUI*4
Slave address match during wakeup
function
WUF
Not possible
Slave address match
Slave receive complete
RWAK operation ASY0 = 1
WUIE = 1
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
There is a delay between the execution of a write instruction for a peripheral module by the CPU and actual writing to the
module. When an interrupt flag is cleared or masked, read the relevant flag again to check whether clearing or masking is
complete, and then return from interrupt handling. Not doing so creates the possibility of repeated processing of the same
interrupt.
Because IICn_TXI is an edge-detected interrupt, it does not require clearing. Additionally, the TDRE flag in ICSR2 (condition for
IICn_TXI) is automatically set to 0 when transmit data is written to ICDRT or a stop condition is detected (STOP flag = 1 in
ICSR2).
Because IICn_RXI is an edge-detected interrupt, it does not require clearing. Additionally, the RDRF flag in ICSR2 (condition
for IICn_RXI) automatically is set to 0 when data is read from ICDRR.
When using the IICn_TEI interrupt, clear the TEND flag in ICSR2 in the IICn_TEI interrupt handling. The TEND flag in ICSR2
automatically is set to 0 when transmit data is written to ICDRT or a stop condition is detected (STOP flag = 1 in ICSR2).
Only channel 0 has a wakeup function, therefore IIC0_WUI is for channel 0 only.
Channel number (n = 0 to 2).
Clear or mask each flag during interrupt handling.
34.14.1
Buffer Operation for IICn_TXI and IICn_RXI Interrupts
If the conditions for generating an IICn_TXI or IICn_RXI interrupt are satisfied while the associated IR flag is 1, the
interrupt request is not output for the ICU but is saved internally. One request per source can be saved internally.
An interrupt request that is saved within the ICU is output when the ICU.IELSRn.IR flag becomes 0. Internally saved
interrupt requests are automatically cleared under normal conditions. They can also be cleared by writing 0 to the
interrupt enable bit within the associated peripheral module.
34.15 State of Registers when Issuing each Condition
The IIC has two dedicated resets, IIC reset and internal reset. Table 34.11 lists the registers state when issuing each
condition.
Table 34.11
Register states when issuing each condition (1 of 2)
Registers
ICCR1
Reset
ICE, IICRST
Reset
IIC reset
(ICE = 0, IICRST = 1)
Start or restart
condition detection
Stop condition detection
Saved
Saved
Saved
Saved
Reset
Reset
Reset
Saved
Set
Saved
Reset
Saved
Saved
TRS,MST
Set or saved
Reset
Others
Reset
Reset or Saved
SCLO, SDAO
Others
ICCR2
Internal reset
(ICE = 1, IICRST = 1)
BBSY
Saved
Reset
ST
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Table 34.11
Register states when issuing each condition (2 of 2)
Registers
ICMR1
BC[2:0]
Reset
IIC reset
(ICE = 0, IICRST = 1)
Reset
Reset
Others
ICMR2
Reset
Reset
Internal reset
(ICE = 1, IICRST = 1)
Start or restart
condition detection
Stop condition detection
Saved
Reset
Reset
Saved
Saved
Saved
Saved
Saved
ICMR3
Reset
Reset
Saved
Saved
Saved
ICFER
Reset
Reset
Saved
Saved
Saved
ICSER
Reset
Reset
Saved
Saved
Saved
ICIER
Reset
Reset
Saved
Saved
Saved
ICSR1
Reset
Reset
Reset
Saved
Reset
Reset
Reset
Reset
Saved
Reset
ICSR2
TDRE, TEND
START
Set
STOP
Saved
Set
Others
Saved
Saved
ICWUR
Reset
Reset
Saved
Saved
Saved
SARL0, SARL1, SARL2
SARU0, SARU1, SARU2
Reset
Reset
Saved
Saved
Saved
ICBRH, ICBRL
Reset
Reset
Saved
Saved
Saved
ICDRT
Reset
Reset
Saved
Saved
Saved
ICDRR
Reset
Reset
Saved
Saved
Saved
ICDRS
Reset
Reset
Reset
Saved
Saved
Timeout function
Reset
Reset
Operating
Operating
Operating
Bus free time
measurement
Reset
Reset
Operating
Operating
Operating
ICWUR2
Reset
Reset
Saved
Saved
WUSEN
Others
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34. I2C Bus Interface (IIC)
34.16 Output to the Event Link Controller (ELC)
IIC0 to IIC2 modules handle the event output for the ELC for the following sources:
(1)
Transfer error event
When a transfer error event occurs, the associated event signal can be output to another module by the ELC.
(2)
Receive data full
When a receive data register becomes full, the associated event signal can be output to another module by the ELC.
(3)
Transmit data empty
When a transmit data register becomes empty, the associated event signal can be output to another module by the ELC.
(4)
Transmit end
On completion of the transfer, the associated event signal can be output to another module by the ELC.
34.16.1
Interrupt Handling and Event Linking
Each of the IIC interrupt types (see Table 34.10) has an enable bit to control enabling and disabling of the associated
interrupt signal. An interrupt request signal is output to the CPU when an interrupt source condition is satisfied while the
associated enable bit is set.
The associated event link output signals are sent to other modules as event signals by the ELC when the interrupt source
conditions are satisfied, regardless of the interrupt enable bit settings. For details on interrupt sources, see Table 34.10.
34.17 Usage Notes
34.17.1
Settings for the Module-Stop Function
IIC operation can be disabled or enabled using Module Stop Control Register B (MSTPCRB). IIC is initially stopped
after reset. Releasing the module-stop state enables access to the registers.
For details, see section 11, Low Power Modes.
34.17.2
Starting Transfer after an Interrupt Occurrence
If the IR flag associated with the IIC interrupt is 1 when the transfer is started (ICCR1.ICE bit = 1), follow the procedure
shown here to clear the interrupts before enabling operations. Starting transfer with the IR flag set to 1 while the
ICCR1.ICE bit is 1 leads to an interrupt request being internally saved after transfer starts, and this can lead to
unanticipated behavior of the IR flag.
To clear interrupts before starting transfer:
1. Confirm that the ICCR1.ICE bit is 0.
2. Set the relevant interrupt enable bits, such as ICIER.TIE, in the peripheral function, to 0.
3. Read the relevant interrupt enable bits, such as ICIER.TIE, in the peripheral function, and confirm that their value is 0.
4. Set the IR flag to 0.
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35. Controller Area Network (CAN) Module
35.
Controller Area Network (CAN) Module
35.1
Overview
The Controller Area Network (CAN) module uses a message-based protocol to receive and transmit data between
multiple slaves and masters in electromagnetically noisy applications. The module complies with the ISO 11898-1 (CAN
2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in
normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported.
Table 35.1 lists the CAN module specifications and Figure 35.1 shows a block diagram. The CAN module requires an
additional external CAN transceiver.
Table 35.1
CAN module specifications (1 of 2)
Parameter
Specifications
Data transfer rate
ISO11898-1-compliant for standard and extended frames
Bit rate
Data transfer rate programmable up to 1 Mbps (fCAN 8 MHz)
fCAN: CAN clock source
Message box
32 mailboxes, with two selectable mailbox modes
Normal mode: 32 mailboxes independently configurable for either transmission or reception
FIFO mode: 24 mailboxes independently configurable for either transmission or reception, with
remaining mailboxes used for receive and transmit 4-stage FIFOs.
Reception
Acceptance filter
Eight acceptance masks (one for every four mailboxes)
Masks independently enabled or disabled for each mailbox.
Transmission
Mode transition for bus-off
recovery
Mode transition for the recovery from the bus-off state selectable to:
ISO11898-1 specification-compliant
Automatic invoking of CAN halt mode on bus-off entry
Automatic invoking of CAN halt mode on bus-off end
Invoking of CAN halt mode through software
Transition to error-active state through software.
Error status monitoring
Monitoring of CAN bus errors, including stuff error, form error, ACK error, 15-bit CRC error, bit error,
and ACK delimiter error
Detection of transition to error states, including error-warning, error-passive, bus-off entry, and bus-off
recovery
Support for reading of error counters.
Time stamping
Time stamp function using a 16-bit counter
Reference clock selectable to 1-bit, 2-bit, 4-bit, and 8-bit time periods.
Interrupt function
Support for five interrupt sources: reception complete, transmission complete, receive FIFO, transmit
FIFO, and error interrupts
CAN sleep mode
CAN clock stopped to reduce power consumption
Software support unit
Three software support units:
Acceptance filter support
Mailbox search support, including receive mailbox search, transmit mailbox search, and message lost
search
Channel search support.
CAN clock source
PCLKB or CANMCLK
Support for data frame and remote frame reception
Reception ID format selectable to only standard ID, only extended ID, or mixed IDs
Programmable one-shot reception function
Selectable between overwrite mode (unread message overwritten) and overrun mode (unread
message saved)
Reception complete interrupt independently enabled or disabled for each mailbox.
Support for data frame and remote frame transmission
Transmission ID format selectable to only standard ID, only extended ID, or mixed IDs)
Programmable one-shot transmission function
Broadcast messaging function
Priority mode selectable based on message ID or mailbox number
Support for transmission request abort, with abort completion confirmed in status flag
Transmission complete interrupt independently enabled or disabled for each mailbox.
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Table 35.1
35. Controller Area Network (CAN) Module
CAN module specifications (2 of 2)
Parameter
Specifications
Test mode
Three test modes available for evaluation purposes:
Listen-only mode
Self-test mode 0 (external loopback)
Self-test mode 1 (internal loopback).
Module-stop function
Module-stop state can be set to reduce power consumption
Internal peripheral bus
CAN control registers
CRXi
Protocol
controller
CTXi
fCANCLK
Baud rate
prescaler
(BRP)
Acceptance
filter
ID priority
transmission
controller
Mailboxes
Timer
Peripheral module clock
(PCLKB)
CCLKS
EXTAL
CANMCLK
BRP:
CCLKS:
fCANCLK:
fCAN:
Figure 35.1
fCAN
Bit in the BCR register
Bit in the BCR register
CAN communication clock
CAN system clock
CANi reception complete interrupt
CANi transmission complete interrupt
Interrupt
generator
CANi receive FIFO interrupt
CANi transmit FIFO interrupt
CANi error interrupt
CAN module block diagram (i = 0, 1)
The CAN module includes the following blocks:
CAN input and output pins
CRXi and CTXi, where i = 0, 1
Protocol controller
Handles CAN protocol processing such as bus arbitration, bit timing during transmission and reception, stuffing,
and error handling.
Mailboxes
Consists of 32 mailboxes, which can be configured as either transmit or receive. Each mailbox has an individual ID,
data length code (DLC), data field (8 bytes), and time stamp.
Acceptance filter
Performs filtering of received messages. MKR0 to MKR7 are used for the filtering process.
Timer
Used for the time stamp function. The timer value when a message is stored in the mailbox is written as the time
stamp value.
Interrupt generator
Generates five types of interrupts:
CANi reception complete interrupt
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35. Controller Area Network (CAN) Module
CANi transmission complete interrupt
CANi receive FIFO interrupt
CANi transmit FIFO interrupt
CANi error interrupt.
The CAN module communicates using the pins listed in Table 35.2. These pins are multiplexed with other signals on the
MCU. For details, see section 20, I/O Ports.
Table 35.2
CAN module I/O pins
Pin name
I/O
Function
CRX0
Input
Data receive pin
CTX0
Output
Data transmit pin
CRX1
Input
Data receive pin
CTX1
Output
Data transmit pin
35.2
Register Descriptions
35.2.1
Control Register (CTLR)
Address(es): CAN0.CTLR 4005 0840h, CAN1.CTLR 4005 1840h
Value after reset:
b15
b14
b13
—
—
RBOC
0
0
0
b12
b11
BOM[1:0]
0
b10
SLPM
0
1
b9
b8
b7
b6
CANM[1:0]
TSPS[1:0]
0
0
1
0
b5
b4
b3
TSRC
TPM
MLM
0
0
0
b2
b1
IDFM[1:0]
0
0
b0
MBM
0
Bit
Symbol
Bit name
Description
R/W
b0
MBM
CAN Mailbox Mode
Select*1
0: Normal mailbox mode
1: FIFO mailbox mode.
R/W
b2, b1
IDFM[1:0]
ID Format Mode Select
*1
b2 b1
R/W
b3
MLM
Message Lost Mode
Select*1
0: Overwrite mode
1: Overrun mode.
R/W
b4
TPM
Transmission Priority
Mode Select*1
0: ID priority transmit mode
1: Mailbox number priority transmit mode.
R/W
b5
TSRC
Time Stamp Counter
Reset Command*4
0: Nothing occurred
1: Reset.*3
R/W
b7, b6
TSPS[1:0]
Time Stamp Prescaler
Select*1
b7 b6
R/W
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0 0: Standard ID mode
All mailboxes, including FIFO mailboxes, handle only standard IDs
0 1: Extended ID mode
All mailboxes, including FIFO mailboxes, handle only extended IDs
1 0: Mixed ID mode
All mailboxes, including FIFO mailboxes, handle both standard and
extended IDs. In normal mailbox mode, use the associated IDE bit
to differentiate standard and extended IDs. In FIFO mailbox mode,
the associated IDE bits are used for mailboxes 0 to 23, the IDE bits
in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE
bit associated with mailbox 24 is used for the transmit FIFO.
1 1: Setting prohibited.
0
0
1
1
0: Every bit time
1: Every 2-bit time
0: Every 4-bit time
1: Every 8-bit time.
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35. Controller Area Network (CAN) Module
Bit
Symbol
Bit name
Description
R/W
b9, b8
CANM[1:0]
CAN Operating Mode
Select*5
b9 b8
R/W
b10
SLPM
CAN Sleep Mode*5,*6
0: All other modes
1: CAN sleep mode.
R/W
b12, b11
BOM[1:0]
Bus-Off Recovery
Mode*1
b12 b11
R/W
b13
RBOC
Forcible Return from
Bus-Off*2
0: Nothing occurred
1: Forced return from bus-off state.*3
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
0
0
1
1
0: CAN operation mode
1: CAN reset mode
0: CAN halt mode
1: CAN reset mode (forced transition).
0 0: Normal mode (ISO11898-1-compliant)
0 1: Enter CAN halt mode automatically on entering bus-off state
1 0: Enter CAN halt mode automatically on end of bus-off state
1 1: Enter CAN halt mode during bus-off recovery period through a software request.
Write to the BOM[1:0], TSPS[1:0], TPM, MLM, IDFM[1:0], and MBM bits in CAN reset mode.
Set the RBOC bit to 1 in the bus-off state.
This bit automatically is set to 0 after being set to 1. It should read as 0.
Set the TSRC bit to 1 in CAN operation mode.
When the CANM[1:0] and SLPM bits are changed, check STR to ensure that the mode is switched. Do not change the
CANM[1:0] bits or SLPM bit until the mode is switched.
Write to the SLPM bit in CAN reset mode or CAN halt mode. When changing the SLPM bit, write 0 or 1 to only the SLPM bit.
MBM bit (CAN Mailbox Mode Select)
When the MBM bit is 0 (normal mailbox mode), mailboxes 0 to 31 are configured as transmit or receive mailboxes.
When the MBM bit is 1 (FIFO mailbox mode), mailboxes 0 to 23 are configured as transmit or receive mailboxes.
Mailboxes 24 to 27 are configured as a transmit FIFO, and mailboxes 28 to 31 are configured as a receive FIFO.
Transmit data is written into mailbox 24, the window mailbox for the transmit FIFO. Receive data is read from mailbox
28, the window mailbox for the receive FIFO.
Table 35.3 lists the mailbox configuration.
IDFM[1:0] bits (ID Format Mode Select)
The IDFM[1:0] bits specify the ID format.
MLM bit (Message Lost Mode Select)
The MLM bit specifies the operation when a new message is captured in the unread mailbox. Overwrite mode or overrun
mode can be selected. In both cases, the mode applies to all mailboxes, including the receive FIFO.
When the MLM bit is 0, all mailboxes are set to overwrite mode. Any new message received overwrites the pre-existing
message.
When the MLM bit is 1, all mailboxes are set to overrun mode. Any new message received does not overwrite the preexisting message, and it is discarded.
TPM bit (Transmission Priority Mode Select)
The TPM bit specifies the priority when transmitting messages. ID priority transmit mode or mailbox number transmit
mode can be selected. All mailboxes are set for either ID priority transmission or mailbox number priority transmission.
When TPM is 0, ID priority transmit mode is selected and transmission priority is arbitrated as defined in the ISO118981 CAN specification. In ID priority transmit mode, mailboxes 0 to 31 (in normal mailbox mode), and mailboxes 0 to 23
(in FIFO mailbox mode), and the transmit FIFO are compared for the IDs of mailboxes configured for transmission. If
two or more mailbox IDs are the same, the mailbox with the smaller number has higher priority.
Only the next message to be transmitted from the transmit FIFO is included in the transmission arbitration. If a FIFO
message is being transmitted, the next pending message within the transmit FIFO is included in the transmission
arbitration.
When TPM is 1, mailbox number transmit mode is selected and the transmit mailbox with the smallest mailbox number
has the highest priority. In FIFO mailbox mode, the transmit FIFO has lower priority than normal mailboxes (0 to 23).
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35. Controller Area Network (CAN) Module
TSRC bit (Time Stamp Counter Reset Command)
The TSRC bit resets the time stamp counter. When it is set to 1, TSR is set to 0000h. TSRC is set to 0 automatically.
TSPS[1:0] bits (Time Stamp Prescaler Select)
The TSPS[1:0] bits select the prescaler for the time stamp. The reference clock for the time stamp can be selected to 1bit, 2-bit, 4-bit, or 8-bit time periods.
CANM[1:0] bits (CAN Operating Mode Select)
The CANM[1:0] bits select one of the following modes for the CAN module: CAN operation mode, CAN reset mode, or
CAN halt mode. CAN sleep mode is set in the SLPM bit. For details, see section 35.3, Operation Modes.
When the CAN module enters CAN halt mode based on the BOM[1:0] setting, the CANM[1:0] bits are automatically set
to 10b.
SLPM bit (CAN Sleep Mode)
When the SLPM bit is set to 1, the CAN module enters CAN sleep mode. When the SLPM bit is set to 0, the CAN
module exits CAN sleep mode. For details, see section 35.3, Operation Modes.
BOM[1:0] bits (Bus-Off Recovery Mode)
The BOM[1:0] bits select bus-off recovery mode for the CAN module.
When the BOM[1:0] bits are 00b, the recovery from bus-off is compliant with the ISO11898-1 specification. The CAN
module recovers CAN communication (error-active state) after detecting 11 consecutive recessive bits 128 times. A busoff recovery interrupt request occurs when recovering from bus-off.
When the BOM[1:0] bits are 01b and the CAN module reaches the bus-off state, the CANM[1:0] bits in CTLR set 10b to
enter CAN halt mode. No bus-off recovery interrupt request occurs when recovering from bus-off, and TECR and RECR
are set to 00h.
When the BOM[1:0] bits are 10b, the CANM[1:0] bits are set to 10b as soon as the CAN module reaches the bus-off
state. The CAN module enters CAN halt mode after recovery from the bus-off state, and after detecting 11 consecutive
recessive bits 128 times. A bus-off recovery interrupt request occurs when recovering from bus-off, and TECR and
RECR are set to 00h.
When the BOM[1:0] bits are 11b, the CAN module enters CAN halt mode by setting the CANM[1:0] bits to 10b while
the CAN module is still in the bus-off state. No bus-off recovery interrupt request occurs when recovering from bus-off,
and TECR and RECR are set to 00h. However, the interrupt does occur if the CAN module recovers from bus-off after
detecting 11 consecutive recessive bits 128 times before the CANM[1:0] bits are set to 10b.
If the CPU requests an entry to CAN reset mode at the same time as the CAN module attempts to enter CAN halt mode
(at bus-off entry when the BOM[1:0] bits are 01b, or at bus-off end when the BOM[1:0] bits are 10b), then the CPU
request has higher priority.
RBOC bit (Forcible Return from Bus-Off)
When the RBOC bit is set to 1 in the bus-off state, the CAN module forcibly exits bus-off. It is set to 0 automatically, and
the error state changes from bus-off to error-active. When the RBOC bit is set to 1, RECR and TECR clear to 00h and the
BOST bit in STR is set to 0, indicating no bus-off state. The other registers remain unchanged when RBOC is set to 1. No
bus-off recovery interrupt request occurs. Use the RBOC bit only when the BOM[1:0] bits are 00b (normal mode).
Table 35.3
Mailbox configuration
Mailbox
MBM bit = 0 (normal mailbox mode)
Mailboxes 0 to 23
Normal mailbox
MBM bit = 1 (FIFO mailbox mode)*1 to *5
Normal mailbox
Mailboxes 24 to 27
Transmit FIFO
Mailboxes 28 to 31
Receive FIFO
Note 1.
Note 2.
The transmit FIFO is controlled by TFCR. The MCTL_TXj registers associated with mailboxes 24 to 27 are disabled.
MCTL_TX24 to MCTL_TX27 cannot be used by the transmit FIFO.
The receive FIFO is controlled by RFCR. The MCTL_RXj registers associated with mailboxes 28 to 31 are disabled.
MCTL_RX28 to MCTL_RX31 cannot be used by the receive FIFO.
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Note 3.
Note 4.
Note 5.
35. Controller Area Network (CAN) Module
See the MIER_FIFO description for information on the FIFO interrupts.
The bits in MKIVLR associated with mailboxes 24 to 31 are disabled. Set 0 to these bits.
The transmit and receive FIFOs can be used for both data frames and remote frames.
35.2.2
Bit Configuration Register (BCR)
Address(es): CAN0.BCR 4005 0844h, CAN1.BCR 4005 1844h
b31
b30
b29
b28
TSEG1[3:0]
b27
b26
—
—
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BRP[9:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
SJW[1:0]
—
—
—
—
—
—
—
—
CCLKS
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
0
TSEG2[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CCLKS
CAN Clock Source
Selection
0: PCLKB (generated by the PLL clock)
1: CANMCLK (generated by the main clock oscillator).
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b10 to b8
TSEG2[2:0]
Time Segment 2 Control
b10
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b13, b12
SJW[1:0]
Synchronization Jump
Width Control
b13 b12
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25 to b16
BRP[9:0]
Baud Rate Prescaler
Select *1
These bits set the frequency of the CAN communication clock
(fCANCLK)
R/W
b27, b26
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b28
TSEG1[3:0]
Time Segment 1 Control
b31
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
b8
0: Setting prohibited
1: 2 Tq
0: 3 Tq
1: 4 Tq
0: 5 Tq
1: 6 Tq
0: 7 Tq
1: 8 Tq.
0: 1 Tq
1: 2 Tq
0: 3 Tq
1: 4 Tq.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b28
0: Setting prohibited
1: Setting prohibited
0: Setting prohibited
1: 4 Tq
0: 5 Tq
1: 6 Tq
0: 7 Tq
1: 8 Tq
0: 9 Tq
1: 10 Tq
0: 11 Tq
1: 12 Tq
0: 13 Tq
1: 14 Tq
0: 15 Tq
1: 16 Tq.
Tq: Time Quantum
Note 1.
Do not select a value less than or equal to 1 while the SCKSCR.CKSEL[2:0] bits are 011b (selecting the main clock oscillator).
For setting the bit timing, see section 35.4, Data Transfer Rate Configuration. Set BCR before entering CAN halt or
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35. Controller Area Network (CAN) Module
operation mode from reset mode. After the setting is made once, this register can be written to in CAN reset or CAN halt
mode. 32-bit read/write accesses must be performed carefully so as not to change bits [7:0].
CCLKS bit (CAN Clock Source Selection)
When the CCLKS bit is 0, the peripheral module clock (PCLKB) produced by the PLL frequency synthesizer is used as
the CAN clock source (fCAN). When the CCLKS bit is 1, CANMCLK produced externally by the EXTAL pins is used
as the CAN clock source (fCAN).
TSEG2[2:0] bits (Time Segment 2 Control)
The TSEG2[2:0] bits specify the length of the phase buffer segment 2 (PHASE_SEG2) with a Tq value. A value from 2
to 8 Tq can be set. Set a value smaller than that in the TSEG1[3:0] bits.
SJW[1:0] bits (Synchronization Jump Width Control)
The SJW[1:0] bits specify the synchronization jump width with a Tq value. A value from 1 to 4 Tq can be set. Set a value
smaller than or equal to that in the TSEG2[2:0] bits.
BRP[9:0] bits (Baud Rate Prescaler Select)
The BRP[9:0] bits set the frequency of the CAN communication clock (fCANCLK). The fCANCLK cycle is 1 Tq. If the
setting is P (0 to 1023), the baud rate prescaler divides fCAN by P + 1.
TSEG1[3:0] bits (Time Segment 1 Control)
The TSEG1[3:0] bits specify the total length of the propagation time segment (PROP_SEG) and phase buffer segment 1
(PHASE_SEG1) with a time quantum (Tq) value. A value from 4 to 16 Tq can be set.
35.2.3
Mask Register k (MKRk) (k = 0 to 7)
Address(es): CAN0.MKR[0] 4005 0400h to CAN0.MKR[7] 4005 041Ch, CAN1.MKR[0] 4005 1400h to CAN1.MKR[7] 4005 141Ch
b31
b30
b29
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
SID[10:0]
b16
EID[17:0]
EID[17:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b17 to b0
EID[17:0]
Extended ID
0: Do not compare associated EID[17:0] bits
1: Compare associated EID[17:0] bits.
R/W
b28 to b18
SID[10:0]
Standard ID
0: Do not compare associated SID[10:0] bits
1: Compare associated SID[10:0] bits.
R/W
b31 to b29
—
Reserved
The read value is undefined. The write value should be 0.
R/W
For the mask function in FIFO mailbox mode, see section 35.6, Acceptance Filtering and Masking Functions.
Write to MKR0 to MKR7 in CAN reset mode or CAN halt mode.
EID[17:0] bits (Extended ID)
The EID[17:0] bits are the filter mask bits associated with the CAN extended ID bits. They are used to receive extended
ID messages. When an EID[17:0] bit is set to 0, the received ID is not compared with the associated mailbox ID. When
an EID[17:0] bit is set to 1, the received ID is compared with the associated mailbox ID.
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35. Controller Area Network (CAN) Module
SID[10:0] bits (Standard ID)
The SID[10:0] bits are the filter mask bits associated with the CAN standard ID bits. They are used to receive both
standard ID and extended ID messages. When an SID[10:0] bit is set to 0, the received ID is not compared with the
associated mailbox ID. When an SID[10:0] bit is set to 1, the received ID is compared with the associated mailbox ID.
35.2.4
FIFO Received ID Compare Registers 0 and 1 (FIDCR0 and FIDCR1)
Address(es): CAN0.FIDCR0 4005 0420h, CAN0.FIDCR1 4005 0424h, CAN1.FIDCR0 4005 1420h, CAN1.FIDCR1 4005 1424h
b31
b30
b29
IDE
RTR
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
SID[10:0]
b17
b16
EID[17:0]
EID[17:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b17 to b0
EID[17:0]
Extended ID
Extended ID of the data and remote frames
R/W
b28 to b18
SID[10:0]
Standard ID
Standard ID of the data and remote frames
R/W
b29
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b30
RTR
Remote Transmission
Request
0: Data frame
1: Remote frame.
R/W
b31
IDE
ID Extension*1
0: Standard ID
1: Extended ID.
R/W
Note 1.
The IDE bit is enabled when the CTLR.IDFM[1:0] bits are 10b (mixed ID mode). When the IDFM[1:0] bits are not 10b, only write
0 to IDE. It reads as 0.
FIDCR0 and FIDCR1 are enabled when the MBM bit in CTLR is set to 1 (FIFO mailbox mode). In this mode, the
EID[17:0], SID[10:0], RTR, and IDE bits in mailbox 28 to mailbox 31 are disabled. Write to FIDCR0 and FIDCR1 in
CAN reset mode or CAN halt mode. For information on using FIDCR0 and FIDCR1, see section 35.6.
EID[17:0] bits (Extended ID)
The EID[17:0] bits set the extended ID of data frames and remote frames. They are used to receive extended ID
messages.
SID[10:0] bits (Standard ID)
The SID[10:0] bits set the standard ID of data frames and remote frames. They are used to receive both standard ID and
extended ID messages.
RTR bit (Remote Transmission Request)
The RTR bit sets the frame format to data frames or remote frames:
When both RTR bits in FIDCR0 and FIDCR1 are set to 0, only data frames are received
When both RTR bits in FIDCR0 and FIDCR1 are set to 1, only remote frames are received
When the RTR bits in FIDCR0 and FIDCR1 are set to different values, both data frames and remote frames are
received.
IDE bit (ID Extension*1)
The IDE bit sets the ID format to standard ID or extended ID. The IDE bit is enabled when the IDFM[1:0] bits in CTLR
are 10b (mixed ID mode):
When both IDE bits in FIDCR0 and FIDCR1 are set to 0, only standard ID frames are received
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35. Controller Area Network (CAN) Module
When both IDE bits in FIDCR0 and FIDCR1 are set to 1, only extended ID frames are received
When IDE bits in FIDCR0 and FIDCR1 are set to different values, both standard and extended ID frames are
received.
35.2.5
Mask Invalid Register (MKIVLR)
Address(es): CAN0.MKIVLR 4005 0428h, CAN1.MKIVLR 4005 1428h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MB31
MB30
MB29
MB28
MB27
MB26
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MB31 to
MB0
Mask Invalid
0: Mask valid
1: Mask invalid.
R/W
Each bit in MKIVLR is associated with a mailbox of the same number. Bit [0] in MKIVLR corresponds to mailbox 0
(MB0), and bit [31] corresponds to mailbox 31 (MB31).*1
When a bit is set to 1, the associated acceptance mask register becomes invalid for the associated mailbox. When a mask
invalid bit is set to 1, a message is received by the associated mailbox only if the receive message ID matches the
mailbox ID exactly.
Write to MKIVLR in CAN reset or halt mode.
Note 1. Set bits [31:24] to 0 in FIFO mailbox mode.
35.2.6
Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31; m = 0 to 7)
Table 35.4 lists the CANi mailbox memory mapping, and Table 35.5 lists the CAN data frame configuration.
The value after reset of the CANi mailbox is undefined.
Write to MBj_ID, MBj_DL, MBj_Dm, and MBj_TS only when the related MCTL_TXj or MCTL_RXj register (j = 0 to
31) is 00h and the associated mailbox is not processing an abort request.
See Table 35.4 for detailed register addresses.
Table 35.4
CANi mailbox memory mapping (1 of 2)
Address
Message content
CAN0
CAN1
Memory mapping
4005 0200h + 16 × j + 0
4005 1200h + 16 × j + 0
IDE, RTR, SID10 to SID6
4005 0200h + 16 × j + 1
4005 1200h + 16 × j + 1
SID5 to SID0, EID17, EID16
4005 0200h + 16 × j + 2
4005 1200h + 16 × j + 2
EID15 to EID8
4005 0200h + 16 × j + 3
4005 1200h + 16 × j + 3
EID7 to EID0
4005 0200h + 16 × j + 4
4005 1200h + 16 × j + 4
—
4005 0200h + 16 × j + 5
4005 1200h + 16 × j + 5
Data length code (DLC[3:0])
4005 0200h + 16 × j + 6
4005 1200h + 16 × j + 6
Data byte 0
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Table 35.4
35. Controller Area Network (CAN) Module
CANi mailbox memory mapping (2 of 2)
Address
Message content
CAN0
CAN1
Memory mapping
4005 0200h + 16 × j + 7
4005 1200h + 16 × j + 7
Data byte 1
4005 0200h + 16 × j + 8
4005 1200h + 16 × j + 8
Data byte 2
4005 0200h + 16 × j + 9
4005 1200h + 16 × j + 9
Data byte 3
4005 0200h + 16 × j + 10
4005 1200h + 16 × j + 10
Data byte 4
4005 0200h + 16 × j + 11
4005 1200h + 16 × j + 11
Data byte 5
4005 0200h + 16 × j + 12
4005 1200h + 16 × j + 12
Data byte 6
4005 0200h + 16 × j + 13
4005 1200h + 16 × j + 13
Data byte 7
4005 0200h + 16 × j + 14
4005 1200h + 16 × j + 14
Time stamp upper byte
4005 0200h + 16 × j + 15
4005 1200h + 16 × j + 15
Time stamp lower byte
Table 35.5
CAN data frame configuration
SID10 to SID6
SID5 to SID0
EID17 to EID16
EID15 to EID8
EID7 to EID0
DLC3 to DLC1
DATA0
DATA1
DATA7
The previous value of each mailbox is retained unless a new message is received.
Address(es): CAN0.MB0_ID 4005 0200h to CAN0.MB31_ID 4005 03F0h, CAN1.MB0_ID 4005 1200h to CAN1.MB31_ID 4005 13F0h
b31
b30
b29
IDE
RTR
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
SID[10:0]
b17
b16
EID[17:0]
EID[17:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b17 to b0
EID[17:0]
Extended ID *1
Extended ID of the data and remote frames
R/W
b28 to b18
SID[10:0]
Standard ID
Standard ID of the data and remote frames
R/W
b29
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b30
RTR
Remote Transmission Request
0: Data frame
1: Remote frame.
R/W
b31
IDE
ID Extension *2
0: Standard ID
1: Extended ID.
R/W
Note 1.
Note 2.
If the mailbox receives a message with data length (set in DLC[3:0]) of n bytes, where n is less than 8, the data in the DATAn to
DATA7 registers in the mailbox is undefined. DATA0 to DATA7 are data registers for this mailbox. For example, if data length is
6 bytes (DLC[3:0] = 6h), the data in DATA6 and DATA7 registers is undefined.
The IDE bit is enabled when the CTLR.IDFM[1:0] bits are 10b (mixed ID mode). When the IDFM[1:0] bits are not 10b, only write
0 to IDE. It reads as 0.
Address(es): CAN0.MB0_DL 4005 0204h to CAN0.MB31_DL 4005 03F4h, CAN1.MB0_DL 4005 1204h to CAN1.MB31_DL 4005 13F4h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
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b3
b2
b1
b0
DLC[3:0]
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x
Value after reset:
35. Controller Area Network (CAN) Module
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DLC[3:0]
Data Length Code *1
b3
R/W
b15 to b4
—
Reserved
The read value is undefined. The write value should be 0.
b0
0 0 0 0: Data length = 0 byte
0 0 0 1: Data length = 1 byte
0 0 1 0: Data length = 2 bytes
0 0 1 1: Data length = 3 bytes
0 1 0 0: Data length = 4 bytes
0 1 0 1: Data length = 5 bytes
0 1 1 0: Data length = 6 bytes
0 1 1 1: Data length = 7 bytes
1 x x x: Data length = 8 bytes.
R/W
x: Don’t care
Note 1.
If the mailbox receives a message with data length (set in DLC[3:0]) of n bytes, where n is less than 8, the data in the DATAn to
DATA7 registers in the mailbox is undefined. DATA0 to DATA7 are data registers for this mailbox. For example, if data length is
6 bytes (DLC[3:0] = 6h), the data in DATA6 and DATA7 registers is undefined.
Address(es): CAN0.MB0_D0 4005 0206h to CAN0.MB31_D0 4005 03F6h, CAN1.MB0_D0 4005 1206h to CAN1.MB31_D0 4005 13F6h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA0
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D1 4005 0207h to CAN0.MB31_D1 4005 03F7h, CAN1.MB0_D1 4005 1207h to CAN1.MB31_D1 4005 13F7h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA1
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D2 4005 0208h to CAN0.MB31_D2 4005 03F8h, CAN1.MB0_D2 4005 1208h to CAN1.MB31_D2 4005 13F8h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA2
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D3 4005 0209h to CAN0.MB31_D3 4005 03F9h, CAN1.MB0_D3 4005 1209h to CAN1.MB31_D3 4005 13F9h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA3
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D4 4005 020Ah to CAN0.MB31_D4 4005 03FAh, CAN1.MB0_D4 4005 120Ah to CAN1.MB31_D4 4005 13FAh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA4
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D5 4005 020Bh to CAN0.MB31_D5 4005 03FBh, CAN1.MB0_D5 4005 120Bh to CAN1.MB31_D5 4005 13FBh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA5
Value after reset:
x
x
x
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35. Controller Area Network (CAN) Module
Address(es): CAN0.MB0_D6 4005 020Ch to CAN0.MB31_D6 4005 03FCh, CAN1.MB0_D6 4005 120Ch to CAN1.MB31_D6 4005 13FCh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA6
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D7 4005 020Dh to CAN0.MB31_D7 4005 03FDh, CAN1.MB0_D7 4005 120Dh to CAN1.MB31_D7 4005 13FDh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA7
Value after reset:
x
x
x
x
x
x: Undefined
Bit
Symbol
b7 to b0
Note 1.
Note 2.
Bit name
DATA0 to
DATA7
Data Bytes 0 to
7*1,*2
Description
R/W
DATA0 to DATA7 store the transmitted or received CAN message data.
Transmission or reception starts from DATA0. The bit order on the CAN
bus is MSB-first, and transmission or reception starts from bit [7].
R/W
If the mailbox receives a message with data length (set in DLC[3:0]) of n bytes, where n is less than 8, the data in the DATAn to
DATA7 registers in the mailbox is undefined. DATA0 to DATA7 are data registers for this mailbox. For example, if data length is
6 bytes (DLC[3:0] = 6h), the data in DATA6 and DATA7 registers is undefined.
If the mailbox receives a remote frame, the previous values of DATA0 to DATA7 in the mailbox are saved.
Address(es): CAN0.MB0_TS 4005 020Eh to CAN0.MB31_TS 4005 03FEh, CAN1.MB0_TS 4005 120Eh to CAN1.MB31_TS 4005 13FEh
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
TSH[7:0]
Value after reset:
x
x
x
x
x
b4
b3
b2
b1
b0
x
x
x
TSL[7:0]
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b7 to b0
TSL[7:0]
Time Stamp Lower Byte
R/W
b15 to b8
TSH[7:0]
Time Stamp Higher Byte
The TSH[7:0] and TSL[7:0] bits store the counter value of the time
stamp when received messages are stored in the mailbox.
R/W
EID[17:0] bits (Extended ID)
The EID[17:0] bits set the extended ID for data frames and remote frames. They are used to transmit or receive extended
ID messages.
SID[10:0] bits (Standard ID)
The SID[10:0] bits set the standard ID for data frames and remote frames. They are used to transmit or receive both
standard ID and extended ID messages.
RTR bit (Remote Transmission Request)
The RTR bit sets the frame format for data frames or remote frames.
The receive mailbox only receives frames with the format specified in the RTR bit
The transmit mailbox transmits with the frame format specified in the RTR bit
The receive FIFO mailbox receives the data frame, remote frame, or both frames specified in the RTR bit in
FIDCR0 and FIDCR1
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35. Controller Area Network (CAN) Module
The transmit FIFO mailbox transmits the data frame or remote frame specified in the RTR bit in the transmit
message.
IDE bit (ID Extension)
The IDE bit sets the ID format to standard IDs or extended IDs. The IDE bit is enabled when the IDFM[1:0] bits in
CTLR are 10b (mixed ID mode).
The receive mailbox only receives the ID format specified in the IDE bit
The transmit mailbox transmits with the ID format specified in the IDE bit
The receive FIFO mailbox receives messages with the standard ID and extended ID settings specified in the IDE bit
in FIDCR0 and FIDCR1
The transmit FIFO mailbox transmits messages with the standard ID or extended ID settings specified in the IDE bit
in the transmit message.
DLC[3:0] bits (Data Length Code)
The DLC[3:0] bits specify the data length to be transmitted in data frames. When a remote frame is used to request data,
this field specifies the requested data length.
When a data frame is received, the received data length is stored in this field. When a remote frame is received, this field
stores the requested data length.
35.2.7
Mailbox Interrupt Enable Register (MIER)
Address(es): CAN0.MIER 4005 042Ch, CAN1.MIER 4005 142Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MB31
MB30
MB29
MB28
MB27
MB26
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MB31 to MB0
Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
Bit [31] is associated with mailbox 31 (MB31), and bit [0] with
mailbox 0 (MB0).
R/W
MIER can enable interrupts for each mailbox independently. This register is available in normal mailbox mode. Do not
access this register in FIFO mailbox mode.
Each bit is associated with the mailbox having the same number. These bits enable or disable transmission and reception
complete interrupts for the associated mailboxes:
Bit [0] in MIER corresponds to mailbox 0 (MB0)
Bit [31] in MIER corresponds to mailbox 31 (MB31).
Write to MIER only when the associated MCTL_TXj or MCTL_RXj register (j = 0 to 31) is 00h and the associated
mailbox is not processing a transmission or reception abort request.
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35.2.8
35. Controller Area Network (CAN) Module
Mailbox Interrupt Enable Register for FIFO Mailbox Mode (MIER_FIFO)
Address(es): CAN0.MIER_FIFO 4005 042Ch, CAN1.MIER_FIFO 4005 142Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
MB29
MB28
—
—
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b23 to b0
MB23 to MB0
Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
Bit [23] is associated with mailbox 23 (MB23), and bit [0] with
mailbox 0 (MB0).
R/W
b24
MB24
Transmit FIFO Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b25
MB25
Transmit FIFO Interrupt
Generation Timing Control
0: Generate every time transmission completes
1: Generate when the transmit FIFO empties on transmission
completion.
R/W
b27, b26
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b28
MB28
Receive FIFO Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b29
MB29
Receive FIFO Interrupt
Generation Timing Control*1
0: Generate every time reception completes
1: Generate when the receive FIFO becomes a buffer warning*2
on reception completion.
R/W
b31, b30
—
Reserved
The read value is undefined. The write value should be 0.
R/W
Note 1.
Note 2.
No interrupt request occurs when the receive FIFO becomes buffer warning because it is full.
Buffer warning indicates a state in which the third message is stored in the receive FIFO.
The MIER_FIFO register can independently enable interrupts for each mailbox and FIFO. This register is available in
normal mailbox mode and FIFO mailbox mode. Do not access it in normal mailbox mode.
The MB0 to MB23 bits are associated with the mailbox having the same number. These bits enable or disable the
transmission and reception complete interrupts for the associated mailboxes:
Bit [0] in MIER_FIFO is associated with mailbox 0 (MB0)
Bit [23] in MIER_FIFO is associated with mailbox 23 (MB23).
MB24, MB25, MB28, and MB29 specify whether the transmit and receive FIFO interrupts are enabled or disabled, and
the timing of interrupt requests.
Write to MIER_FIFO only when the associated MCTL_TXj or MCTL_RXj register (j = 0 to 31) is 00h and the
associated mailbox is not processing a transmission or reception abort request. In addition, change the bits in
MIER_FIFO for the associated FIFO only when the TFE bit in TFCR is 0 and the TFEST bit is 1, and the RFE bit in
RFCR is 0 and the RFEST bit in RFCR is 1.
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35.2.9
35. Controller Area Network (CAN) Module
Message Control Register for Transmit (MCTL_TXj) (j = 0 to 31)
Transmit mode (when the TRMREQ bit is 1 and the RECREQ bit is 0)
Address(es): CAN0.MCTL_TX[0] 4005 0820h to CAN0.MCTL_TX[31] 4005 083Fh,
CAN1.MCTL_TX[0] 4005 1820h to CAN1.MCTL_TX[31] 4005 183Fh
b7
b6
TRMRE RECRE
Q
Q
Value after reset:
0
0
b5
b4
b3
—
ONESH
OT
—
0
0
0
b2
b1
b0
TRMAB TRMAC SENTD
T
TIVE
ATA
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SENTDATA
Transmission Complete Flag
*1,*2
0: Transmission not complete
1: Transmission complete.
R/W
b1
TRMACTIVE
Transmission-in-Progress
Status Flag
0: Transmission pending or not requested
1: Transmission in progress.
R
b2
TRMABT
Transmission Abort Complete
Flag*1,*2
0: Transmission started, transmission abort failed because
transmission completed, or transmission abort not requested
1: Transmission abort complete.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
ONESHOT
One-Shot Enable*2,*3
0: Disable one-shot transmission
1: Enable one-shot transmission.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
RECREQ
Receive Mailbox Request
*2,*3,*4,*5
0: Do not configure for reception
1: Configure for reception.
R/W
b7
TRMREQ
Transmit Mailbox Request
*2,*4
0: Do not configure for transmission
1: Configure for transmission.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Write 0 only. Writing 1 has no effect.
When writing to bits of this register, write 1 to SENTDATA and TRMABT if these bits are not the write target.
To enter one-shot transmit mode, write 1 to the ONESHOT bit at the same time as setting the TRMREQ bit to 1. To exit oneshot transmit mode, write 0 to the ONESHOT bit after the message is transmitted or aborted.
Do not set both the RECREQ and TRMREQ bits to 1.
When setting the RECREQ bit to 0, set the SENTDATA, TRMACTIVE, and TRMABT flags to 0 simultaneously.
MCTL_TXj sets mailbox j to transmit mode or receive mode. In transmit mode, MCTL_TXj also controls and indicates
the transmission status. Do not access MCTL_TXj if mailbox j is in receive mode. Only write to MCTL_TXj in CAN
operation or halt mode. Do not use MCTL_TX24 to MCTL_TX31 in FIFO mailbox mode.
SENTDATA flag (Transmission Complete Flag)
The SENTDATA flag is set to 1 when data transmission from the associated mailbox is complete. The SENTDATA flag
is set to 0 through a software write. To set it to 0, first set the TRMREQ bit to 0. The SENTDATA and TRMREQ flags
cannot be set to 0 simultaneously. To transmit a new message from the associated mailbox, set the SENTDATA flag to 0.
TRMACTIVE flag (Transmission-in-Progress Status Flag)
The TRMACTIVE flag is set to 1 when the associated mailbox of the CAN module begins transmitting a message. It is
set to 0 when the CAN module loses CAN bus arbitration, a CAN bus error occurs, or data transmission completes.
TRMABT flag (Transmission Abort Complete Flag)
The TRMABT flag is set to 1 in the following cases:
Following a transmission abort request, when the transmission abort is complete before starting transmission
Following a transmission abort request, when the CAN module detects CAN bus arbitration-lost or a CAN bus error
In one-shot transmission mode (RECREQ = 0, TRMREQ = 1, and ONESHOT = 1), when the CAN module detects
a CAN bus arbitration-lost or a CAN bus error.
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35. Controller Area Network (CAN) Module
The TRMABT flag does not set to 1 when data transmission is complete. The SENTDATA flag is set to 1. The TRMABT
flag is set to 0 through a software write.
ONESHOT bit (One-Shot Enable)
When the ONESHOT bit is set to 1 in transmit mode (RECREQ = 0 and TRMREQ = 1), the CAN module transmits a
message only one time. The CAN module does not transmit the message again if a CAN bus error or CAN bus
arbitration-lost occurs. When transmission is complete, the SENTDATA flag is set to 1. If transmission does not
complete because of a CAN bus error or CAN bus arbitration-lost error, the TRMABT flag is set to 1. Set the ONESHOT
bit to 0 after the SENTDATA or TRMABT flag is set to 1.
RECREQ bit (Receive Mailbox Request)
The RECREQ bit selects the receive modes listed in Table 35.10.
When the RECREQ bit is set to 1, the associated mailbox is configured for reception of a data or remote frame.
When the RECREQ bit is set to 0, the associated mailbox is not configured for reception of a data or remote frame.
Due to hardware protection, the RECREQ bit cannot be set to 0 through a software write during the following period:
Hardware protection is started from the acceptance filter processing (the beginning of the CRC field)
Hardware protection is released:
For the mailbox that is specified to receive the incoming message, after the received data is stored in the mailbox
or a CAN bus error occurs. This means that the maximum period of hardware protection is from the beginning of
CRC field to the end of the 7th bit of EOF.
For the other mailboxes, after acceptance filter processing
If no mailbox is specified to receive the message, after acceptance filter processing.
When setting the RECREQ bit to 1, do not set the TRMREQ bit to 1. To change the configuration of a mailbox from
transmission to reception, first abort the transmission and then set the SENTDATA and TRMABT flags to 0 before
changing to reception.
Note:
MCTL_TXj.RECREQ is the mirror bit of MCTL_RXj.RECREQ.
TRMREQ bit (Transmit Mailbox Request)
The TRMREQ bit selects the transmit modes listed in Table 35.10.
When the TRMREQ bit is set to 1, the associated mailbox is configured for transmission of a data or remote frame.
When the TRMREQ bit is set to 0, the associated mailbox is not configured for transmission of a data or remote frame.
If the TRMREQ bit is changed from 1 to 0 to cancel the associated transmission request, either the TRMABT or
SENTDATA flag is set to 1. When setting the TRMREQ bit to 1, do not set the RECREQ bit to 1. To change the
configuration of a mailbox from reception to transmission, first abort the reception, and then set the NEWDATA and
MSGLOST bits to 0 before changing to transmission.
Note:
MCTL_TXj.TRMREQ is the mirror bit of MCTL_RXj.TRMREQ.
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35.2.10
35. Controller Area Network (CAN) Module
Message Control Register for Receive (MCTL_RXj) (j = 0 to 31)
Receive mode (when the TRMREQ bit is 0 and the RECREQ bit is 1)
Address(es): CAN0.MCTL_RX[0] 4005 0820h to CAN0.MCTL_RX[31] 4005 083Fh,
CAN1.MCTL_RX[0] 4005 1820h to CAN1.MCTL_RX[31] 4005 183Fh
b7
b6
TRMRE RECRE
Q
Q
Value after reset:
Bit
0
0
Symbol
b5
b4
b3
—
ONESH
OT
—
0
0
0
b2
b1
b0
MSGL INVALD NEWD
OST
ATA
ATA
0
Bit name
Flag*1,*2
0
0
Description
R/W
0: No data received, or 0 was written to the bit
1: New message being stored or was stored in the mailbox.
R/W
b0
NEWDATA
Reception Complete
b1
INVALDATA
Reception-in-Progress Status
Flag
0: Message valid
1: Message being updated.
R
b2
MSGLOST
Message Lost Flag*1,*2
0: Message not overwritten or overrun
1: Message overwritten or overrun.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
0: Disable one-shot reception
1: Enable one-shot reception.
R/W
Enable*2,*3
b4
ONESHOT
One-Shot
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
RECREQ
Receive Mailbox Request
*2,*3,*4,*5
0: Do not configure for reception
1: Configure for reception.
R/W
b7
TRMREQ
Transmit Mailbox Request
*2,*4
0: Do not configure for transmission
1: Configure for transmission.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Write 0 only. Writing 1 has no effect.
When writing to the bits in this register, write 1 to the NEWDATA and MSGLOST bits if they are not the write target.
To enter one-shot receive mode, write 1 to the ONESHOT bit at the same time as setting the RECREQ bit to 1. To exit one-shot
receive mode, write 0 to the ONESHOT bit after writing 0 to the RECREQ bit and confirming that it is 0.
Do not set both the RECREQ and TRMREQ bits to 1.
When setting the RECREQ bit to 0, set the MSGLOST, NEWDATA, and RECREQ bits to 0 simultaneously.
MCTL_RXj sets mailbox j to transmit or receive mode. In receive mode, MCTL_RXj also controls and indicates the
reception status. Do not access MCTL_RXj if mailbox j is in transmit mode. Only write to the MCTL_RXj in CAN
operation or halt mode. Do not use MCTL_RX24 to MCTL_RX31 in FIFO mailbox mode.
NEWDATA flag (Reception Complete Flag)
The NEWDATA flag is set to 1 when a new message is being stored or was stored in the mailbox. Always set this bit to 1
simultaneously with the INVALDATA flag. The NEWDATA flag is cleared to 0 through a software write. The
NEWDATA flag cannot be set to 0 through a software write while the associated INVALDATA flag is 1.
INVALDATA flag (Reception-in-Progress Status Flag)
After the completion of a message reception, the INVALDATA flag is set to 1 while the received message is being
updated into the associated mailbox. The INVALDATA flag is set to 0 immediately after the message is stored. If the
mailbox is read while the INVALDATA flag is 1, the data is undefined.
MSGLOST flag (Message Lost Flag)
The MSGLOST flag is set to 1 when the mailbox is overwritten or overrun by a new received message while the
NEWDATA flag is 1. The MSGLOST flag is set to 1 at the end of the 6th bit of EOF. The MSGLOST flag is set to 0
through a software write.
In both overwrite and overrun modes, the MSGLOST flag cannot be set to 0 through a software write during the 5
PCLKB cycles following the 6th bit of EOF.
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35. Controller Area Network (CAN) Module
ONESHOT bit (One-Shot Enable)
When the ONESHOT bit is set to 1 in receive mode (RECREQ = 1 and TRMREQ = 0), the mailbox receives a message
only one time. The mailbox does not behave as a receive mailbox after having received the message one time. The
behavior of the NEWDATA and INVALDATA flags is the same as in normal receive mode. In one-shot receive mode,
the MSGLOST flag does not set to 1. To set the ONESHOT bit to 0, first write 0 to the RECREQ bit and ensure that it is
0.
RECREQ bit (Receive Mailbox Request)
The RECREQ bit selects receive modes listed in Table 35.10.
When the RECREQ bit is set to 1, the associated mailbox is configured for reception of a data frame or remote frame.
When the RECREQ bit is set to 0, the associated mailbox is not configured for reception of a data frame or remote frame.
Due to hardware protection, the RECREQ bit cannot be set to 0 through a software write during the following period:
Hardware protection is started from the acceptance filter processing (the beginning of the CRC field)
Hardware protection is released:
For the mailbox that is specified to receive the incoming message, after the received data is stored in the mailbox
or a CAN bus error occurs. This means that the maximum period of hardware protection is from the beginning of
the CRC field to the end of the 7th bit of EOF.
For the other mailboxes, after acceptance filter processing
If no mailbox is specified to receive the message, after acceptance filter processing.
When setting the RECREQ bit to 1, do not set the TRMREQ bit to 1. To change the configuration of a mailbox from
transmission to reception, first abort the transmission and then set the SENTDATA and TRMABT flags to 0 before
changing to reception.
Note:
MCTL_RXj.RECREQ is the mirror bit of MCTL_TXj.RECREQ.
TRMREQ bit (Transmit Mailbox Request)
The TRMREQ bit selects the transmit modes listed in Table 35.10.
When the TRMREQ bit is set to 1, the associated mailbox is configured for transmission of a data or remote frame.
When the TRMREQ bit is set to 0, the associated mailbox is not configured for transmission of a data or remote frame.
If the TRMREQ bit is changed from 1 to 0 to cancel the associated transmission request, either the TRMABT or
SENTDATA flag is set to 1. When setting the TRMREQ bit to 1, do not set the RECREQ bit to 1. To change the
configuration of a mailbox from reception to transmission, first abort the reception and then set the NEWDATA and
MSGLOST bits to 0 before changing to transmission.
Note:
MCTL_RXj.TRMREQ is the mirror bit of MCTL_TXj.TRMREQ.
35.2.11
Receive FIFO Control Register (RFCR)
Address(es): CAN0.RFCR 4005 0848h, CAN1.RFCR 4005 1848h
b7
b6
b5
b4
b3
RFEST RFWST RFFST RFMLF
Value after reset:
1
0
0
0
b2
b1
RFUST[2:0]
0
0
b0
RFE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RFE
Receive FIFO Enable
0: Disable receive FIFO
1: Enable receive FIFO.
R/W
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35. Controller Area Network (CAN) Module
Bit
Symbol
Bit name
Description
R/W
b3 to b1
RFUST[2:0]
Receive FIFO Unread Message
Number Status
b3
R
b4
RFMLF
Receive FIFO Message Lost Flag
0: Receive FIFO message not lost
1: Receive FIFO message lost.
R/W
b5
RFFST
Receive FIFO Full Status Flag
0: Receive FIFO not full
1: Receive FIFO full (4 unread messages).
R
b6
RFWST
Receive FIFO Buffer Warning
Status Flag
0: Receive FIFO has no buffer warning
1: Receive FIFO has buffer warning (3 unread messages).
R
b7
RFEST
Receive FIFO Empty Status Flag
0: Unread message in receive FIFO
1: No unread message in receive FIFO.
R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b1
0: No unread message
1: 1 unread message
0: 2 unread messages
1: 3 unread messages
0: 4 unread messages
1: Reserved
0: Reserved
1: Reserved.
Write to RFCR in CAN operation or halt mode.
RFE bit (Receive FIFO Enable)
When the RFE bit is set to 1, the receive FIFO is enabled.
When the RFE bit is set to 0, the receive FIFO is disabled for reception and becomes empty (RFEST bit = 1). Write 0 to
the RFE bit simultaneously with setting the RFMLF flag.
Do not set this bit to 1 in normal mailbox mode (MBM bit in CTLR = 0). Due to hardware protection, the RFE bit cannot
be set to 0 through a software write during the following period:
Hardware protection is started from acceptance filter processing (the beginning of the CRC field)
When hardware protection is released:
If the receive FIFO is specified to receive the incoming message, after the received data is stored in the receive
FIFO or a CAN bus error occurs. This means that the maximum period of hardware protection is from the
beginning of the CRC field to the end of the 7th bit of EOF.
If the receive FIFO is not specified to receive the message, after acceptance filter processing.
RFUST[2:0] bits (Receive FIFO Unread Message Number Status)
The RFUST[2:0] bits indicate the number of unread messages in the receive FIFO. The value of the RFUST[2:0] bits
initializes to 000b when the RFE bit is set to 0.
RFMLF flag (Receive FIFO Message Lost Flag)
The RFMLF flag is set to 1 (receive FIFO message lost) when the receive FIFO receives a new message and is full. It is
set to 1 at the end of the 6th bit of EOF.
The RFMLF flag is set to 0 through a software write. Writing 1 has no effect. In both overwrite and overrun modes, if the
receive FIFO is full and determined to have received a message, the RFMLF flag cannot be set to 0 (receive FIFO
message was not lost) through a software write because of hardware protection during the 5 PCLKB cycles following the
6th bit of EOF.
RFFST flag (Receive FIFO Full Status Flag)
The RFFST flag is set to 1 (receive FIFO is full) when the number of unread messages in the receive FIFO is 4. It is 0
(receive FIFO is not full) when the number of unread messages in the receive FIFO is less than 4. The flag is set to 0
when the RFE bit is 0.
RFWST flag (Receive FIFO Buffer Warning Status Flag)
The RFWST flag is set to 1 (receive FIFO is a buffer warning) when the number of unread messages in the receive FIFO
is 3. It is 0 (receive FIFO is not a buffer warning) when the number of unread messages in the receive FIFO is less than 3
or equal to 4. The RFWST flag is set to 0 when the RFE bit is 0.
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35. Controller Area Network (CAN) Module
RFEST flag (Receive FIFO Empty Status Flag)
The RFEST flag is set to 1 (no unread message in receive FIFO) when the number of unread messages in the receive
FIFO is 0. It is set to 1 when the RFE bit is set to 0. The flag is set to 0 (unread message in receive FIFO) when the
number of unread messages in the receive FIFO is one or more. Figure 35.2 shows the receive FIFO mailbox operation.
Receive FIFO mailbox
Frame 1
Frame 2
Frame 3
Frame 4
Frame 1
CAN bus
Frame 2
Frame 3
Frame 4
Frame 1
Internal bus
Frame 2
Frame 3
Frame 4
RFCR.RFEST flag
RFCR.RFWST flag
RFCR.RFFST bit
CANi receive FIFO interrupt
Bits 29 and 28 in MIER_FIFO = 01b
CANi receive FIFO interrupt
Bits 29 and 28 in MIER_FIFO = 11b
RFPCR
Figure 35.2
35.2.12
Receive FIFO mailbox operation when bits [29] and [28] in MIER_FIFO = 01b or 11b
Receive FIFO Pointer Control Register (RFPCR)
Address(es): CAN0.RFPCR 4005 0849h, CAN1.RFPCR 4005 1849h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b7 to b0
The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR
W
When the receive FIFO is not empty, write FFh to RFPCR through software to increment the CPU pointer to the next
mailbox location. Do not write to RFPCR when the RFE bit in RFCR is 0 (receive FIFO disabled).
Both the CAN and CPU pointers increment when a new message is received and the RFFST flag is 1 (receive FIFO is
full) in overwrite mode. When the RFMLF flag is 1 in this state, the CPU pointer does not increment on a software write
to RFPCR.
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35.2.13
35. Controller Area Network (CAN) Module
Transmit FIFO Control Register (TFCR)
Address(es): CAN0.TFCR 4005 084Ah, CAN1.TFCR 4005 184Ah
b7
b6
TFEST TFFST
Value after reset:
1
0
b5
b4
—
—
0
0
b3
b2
b1
b0
TFUST[2:0]
0
0
TFE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TFE
Transmit FIFO Enable
0: Disable transmit FIFO
1: Enable transmit FIFO.
R/W
b3 to b1
TFUST[2:0]
Transmit FIFO Unsent Message
Number Status
b3
R
b5, b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
TFFST
Transmit FIFO Full Status
0: Transmit FIFO not full
1: Transmit FIFO full (4 unsent messages).
R
b7
TFEST
Transmit FIFO Empty Status
0: Unsent message in transmit FIFO
1: No unsent message in transmit FIFO.
R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b1
0: 0 unsent messages
1: 1 unsent message
0: 2 unsent messages
1: 3 unsent messages
0: 4 unsent messages
1: Reserved
0: Reserved
1: Reserved.
Write to TFCR in CAN operation or halt mode.
TFE bit (Transmit FIFO Enable)
Setting the TFE bit set to 1 enables the transmit FIFO. Setting the TFE bit to 0 empties the transmit FIFO (TFEST bit =
1), and unsent messages in the transmit FIFO are lost in the following ways:
Immediately if a message from the transmit FIFO is not scheduled for the next transmission or already in
transmission
On completion of transmission, on a CAN bus error, a CAN bus arbitration-lost, or an entry to CAN halt mode, if a
message from the transmit FIFO is scheduled for the next transmission or is already in transmission.
Before setting the TFE bit to 1 again, ensure that the TFEST bit is set to 1. After setting the TFE bit to 1, write transmit
data to mailbox 24.
Do not set the TFE bit to 1 in normal mailbox mode (MBM bit in CTLR = 0).
TFUST[2:0] bits (Transmit FIFO Unsent Message Number Status)
The TFUST[2:0] bits indicate the number of unsent messages in the transmit FIFO. They are set to 000b after TFE bit is
set to 0 and transmission is aborted or completed.
TFFST bit (Transmit FIFO Full Status)
The TFFST bit is set to 1 (transmit FIFO is full) when the number of unsent messages in the transmit FIFO is 4. The
TFFST bit is set to 0 (transmit FIFO is not full) when the number of unsent messages in the transmit FIFO is less than 4.
The TFFST bit is set to 0 when transmission from the transmit FIFO is aborted.
TFEST bit (Transmit FIFO Empty Status)
The TFEST bit is set to 1 (no message in transmit FIFO) when the number of unsent messages in the transmit FIFO is 0.
The TFEST bit is set to 1 when transmission from the transmit FIFO is aborted. The TFEST bit is set to 0 (message in
transmit FIFO) when the number of unsent messages in the transmit FIFO is not 0.
Figure 35.3 shows the transmit FIFO mailbox operation.
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35. Controller Area Network (CAN) Module
Transmit FIFO mailbox
Frame 1
Frame 2
Frame 3
Frame 4
CAN bus
Frame 1
Frame 1
Internal bus
Frame 2
Frame 3
Frame 2
Frame 3
Frame 4
Frame 4
TFCR.TFEST flag
TFCR.TFFST bit
CANi transmit FIFO interrupt
Bits 25 and 24 in MIER_FIFO = 01b
CANi transmit FIFO interrupt
Bits 25 and 24 in MIER_FIFO = 11b
TFPCR
Figure 35.3
35.2.14
Transmit FIFO mailbox operation when bits [25] and [24] in MIER_FIFO = 01b or 11b
Transmit FIFO Pointer Control Register (TFPCR)
Address(es): CAN0.TFPCR 4005 084Bh, CAN1.TFPCR 4005 184Bh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b7 to b0
The CPU pointer for the transmit FIFO is incremented by writing FFh to TFPCR
W
When the transmit FIFO is not full, write FFh to TFPCR through software to increment the CPU pointer for the transmit
FIFO to the next mailbox location.
Do not write to TFPCR when the TFE bit in TFCR is 0 (transmit FIFO disabled).
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35.2.15
35. Controller Area Network (CAN) Module
Status Register (STR)
Address(es): CAN0.STR 4005 0842h, CAN1.STR 4005 1842h
b15
—
Value after reset:
0
b14
b13
b12
RECST TRMST BOST
0
0
b11
b10
b9
b8
EPST SLPST HLTST RSTST
0
0
1
0
1
b7
EST
0
b6
b5
b4
b3
TABST FMLST NMLST TFST
0
0
0
0
b2
b1
b0
RFST
SDST
NDST
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
NDST
NEWDATA Status Flag
0: No mailbox with NEWDATA = 1
1: 1 or more mailboxes with NEWDATA = 1.
R
b1
SDST
SENTDATA Status Flag
0: No mailbox with SENTDATA = 1
1: 1 or more mailboxes with SENTDATA = 1.
R
b2
RFST
Receive FIFO Status Flag
0: Empty receive FIFO
1: Message in receive FIFO.
R
b3
TFST
Transmit FIFO Status Flag
0: Transmit FIFO is full
1: Transmit FIFO is not full.
R
b4
NMLST
Normal Mailbox Message Lost
Status Flag
0: No mailbox with MSGLOST = 1
1: 1 or more mailboxes with MSGLOST = 1.
R
b5
FMLST
FIFO Mailbox Message Lost Status
Flag
0: RFMLF = 0
1: RFMLF = 1.
R
b6
TABST
Transmission Abort Status Flag
0: No mailbox with TRMABT = 1
1: 1 or more mailboxes with TRMABT = 1.
R
b7
EST
Error Status Flag
0: No error occurred
1: Error occurred.
R
b8
RSTST
CAN Reset Status Flag
0: Not in CAN reset mode
1: In CAN reset mode.
R
b9
HLTST
CAN Halt Status Flag
0: Not in CAN halt mode
1: In CAN halt mode.
R
b10
SLPST
CAN Sleep Status Flag
0: Not in CAN sleep mode
1: In CAN sleep mode.
R
b11
EPST
Error-Passive Status Flag
0: Not in error-passive state
1: In error-passive state.
R
b12
BOST
Bus-Off Status Flag
0: Not in bus-off state
1: In bus-off state.
R
b13
TRMST
Transmit Status Flag
0: Bus idle or reception in progress
1: Transmission in progress or module in bus-off state.
R
b14
RECST
Receive Status Flag
0: Bus idle or transmission in progress
1: Reception in progress.
R
b15
—
Reserved
This bit is read as 0.
R
NDST flag (NEWDATA Status Flag)
The NDST flag is set to 1 when at least one NEWDATA flag in MCTL_RXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. It is set to 0 when all NEWDATA flags are 0.
SDST flag (SENTDATA Status Flag)
The SDST flag is set to 1 when at least one SENTDATA flag in MCTL_TXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. It is set to 0 when all SENTDATA flags are 0.
RFST flag (Receive FIFO Status Flag)
The RFST flag is set to 1 when the receive FIFO is not empty. It is set to 0 when the receive FIFO is empty or normal
mailbox mode is selected.
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35. Controller Area Network (CAN) Module
TFST flag (Transmit FIFO Status Flag)
The TFST flag is set to 1 when the transmit FIFO is not full. It is set to 0 when the transmit FIFO is full or normal
mailbox mode is selected.
NMLST flag (Normal Mailbox Message Lost Status Flag)
The NMLST flag is set to 1 when at least one MSGLOST flag in MCTL_RXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. It is set to 0 when all MSGLOST flags are 0.
FMLST flag (FIFO Mailbox Message Lost Status Flag)
The FMLST flag is set to 1 when the RFMLF flag in RFCR is 1, regardless of the value of MIER_FIFO. It is set to 0
when the RFMLF flag is 0.
TABST flag (Transmission Abort Status Flag)
The TABST flag is set to 1 when at least one TRMABT flag in MCTL_TXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. It is set to 0 when all TRMABT flags are 0.
EST flag (Error Status Flag)
The EST flag is set to 1 when at least one error is detected by EIFR, regardless of the value of EIER. It is set to 0 when
no error is detected by EIFR.
RSTST flag (CAN Reset Status Flag)
The RSTST flag is set to 1 when the CAN module is in CAN reset mode. It is 0 when the CAN module is not in CAN
reset mode. It remains 1, even when the state changes from CAN reset to sleep mode.
HLTST flag (CAN Halt Status Flag)
The HLTST flag is set to 1 when the CAN module is in CAN halt mode. It is set to 0 when the CAN module is not in
CAN halt mode. It remains 1, even when the state changes from CAN halt to sleep mode.
SLPST flag (CAN Sleep Status Flag)
The SLPST flag is set to 1 when the CAN module is in CAN sleep mode. It is set to 0 when the CAN module is not in
CAN sleep mode.
EPST flag (Error-Passive Status Flag)
The EPST flag is set to 1 when the value of TECR or RECR exceeds 127 and the CAN module is in an error-passive state
(128 ≤ TEC < 256 or 128 ≤ REC < 256). It is set to 0 when the CAN module is not in the error-passive state.
BOST flag (Bus-Off Status Flag)
The BOST flag is set to 1 when the value of TECR exceeds 255 and the CAN module is in the bus-off state (TEC ≥ 256).
It is set to 0 when the CAN module is not in the bus-off state.
TRMST flag (Transmit Status Flag)
The TRMST flag is set to 1 when the CAN module performs as a transmitter node or is in the bus-off state. It is set to 0
when the CAN module performs as a receiver node or is in the bus-idle state.
RECST flag (Receive Status Flag)
The RECST flag is set to 1 when the CAN module performs as a receiver node. It is set to 0 when the CAN module
performs as a transmitter node or is in the bus-idle state.
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35.2.16
35. Controller Area Network (CAN) Module
Mailbox Search Mode Register (MSMR)
Address(es): CAN0.MSMR 4005 0853h, CAN1.MSMR 4005 1853h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MBSM[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
MBSM[1:0]
Mailbox Search Mode Select
b1 b0
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: Receive mailbox search mode
1: Transmit mailbox search mode
0: Message lost search mode
1: Channel search mode.
Write to MSMR in CAN operation or halt mode.
MBSM[1:0] bits (Mailbox Search Mode Select)
The MBSM[1:0] bits select the search mode for the mailbox search function.
When the MBSM[1:0] bits are 00b, receive mailbox search mode is selected. In this mode, the search targets are the
NEWDATA flag in MCTL_RXj (j = 0 to 31) for the normal mailbox, and the RFEST bit in RFCR.
When the MBSM[1:0] bits are 01b, transmit mailbox search mode is selected. In this mode, the search target is the
SENTDATA flag in MCTL_TXj.
When the MBSM[1:0] bits are 10b, message lost search mode is selected. In this mode, the search targets are the
MSGLOST flag in MCTL_RXj for the normal mailbox and the RFMLF flag in RFCR.
When the MBSM[1:0] bits are 11b, channel search mode is selected. In this mode, the search target is CSSR. See section
35.2.18, Channel Search Support Register (CSSR).
35.2.17
Mailbox Search Status Register (MSSR)
Address(es): CAN0.MSSR 4005 0852h, CAN1.MSSR 4005 1852h
Value after reset:
b7
b6
b5
SEST
—
—
1
0
0
b4
b3
b2
b1
b0
0
0
MBNST[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
MBNST[4:0]
Search Result Mailbox
Number Status
These bits output the smallest mailbox number that is found in each
mode of MSMR
R
b6, b5
—
Reserved
These bits are read as 0
R
b7
SEST
Search Result Status
0: Search result found
1: No search result.
R
MBNST[4:0] bits (Search Result Mailbox Number Status)
In all MSMR modes, the MBNST[4:0] bits output the smallest found mailbox number. In receive mailbox search mode,
transmit mailbox search mode, and message lost search mode, the value of the mailbox (the search result to be output) is
updated under the following conditions:
When the NEWDATA, SENTDATA, or MSGLOST flag for a mailbox output by MBNST is set to 0
When the NEWDATA, SENTDATA, or MSGLOST flag for a mailbox with a smaller number than of MBNST is
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35. Controller Area Network (CAN) Module
set to 1.
If the MBSM[1:0] bits are set to 00b (receive mailbox search mode) or 10b (message lost search mode), the receive FIFO
(mailbox 28) is output when it is not empty and there are no unread received messages and no lost messages in any of the
normal mailboxes (0 to 23). If the MBSM[1:0] bits are set to 01b (transmit mailbox search mode), the transmit FIFO
(mailbox 24) is not output. Table 35.6 lists the behavior of the MBNST[4:0] bits in FIFO mailbox mode.
In channel search mode, the MBNST[4:0] bits output the associated channel number. After MSSR is read by software,
the next target channel number is output.
SEST bit (Search Result Status)
The SEST bit is set to 1 (no search result) when no associated mailbox is found after searching all mailboxes. For
example, in transmit mailbox search mode, the SEST bit is set to 1, when no SENTDATA flag for the mailboxes is 1. The
SEST bit is set to 0 when at least one SENTDATA flag is 1. When the SEST bit is 1, the value of the MBNST[4:0] bits is
undefined.
Table 35.6
Behavior of MBNST[4:0] bits in FIFO mailbox mode
MBSM[1:0] bits
Mailbox 24 (transmit FIFO)
Mailbox 28 (receive FIFO)
00b
Mailbox 24 is not output
Mailbox 28 is output when no MCTL_RXj.NEWDATA flag for the normal
mailboxes is set to 1 (new message is being stored or was stored in the mailbox)
and the receive FIFO is not empty
01b
Mailbox 28 is not output
10b
Mailbox 28 is output when no MCTL_RXj.MSGLOST flag for the normal
mailboxes is set to 1 (message is overwritten or overrun) and the RFCR.RFMLF
flag is set to 1 (receive FIFO message lost) in the receive FIFO
11b
Mailbox 28 is not output
35.2.18
Channel Search Support Register (CSSR)
Address(es): CAN0.CSSR 4005 0851h, CAN1.CSSR 4005 1851h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b7 to b0
When the value for the channel search is input, the channel number is output to MSSR
R/W
The bits in CSSR, which are set to 1, are encoded by an 8/3 encoder (the LSB position has the higher priority) and output
to the MBNST[4:0] bits in MSSR. MSSR outputs the updated value whenever MSSR is read by software.
Write to CSSR only when the MSMR.MBSM[1:0] bits are 11b (channel search mode). Write to CSSR in CAN operation
mode or CAN halt mode.
Figure 35.4 shows writes to and reads from CSSR and MSSR.
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35. Controller Area Network (CAN) Module
Address
CSSR
b7
b6
0
1
b3
0
0
1
0
b0
CAN0
1
4005 0851h
0
8/3 encoder
CAN0
MSSR
b7
b2
4005 0852h
b0
(1st read)
0
0
0
0
0
0
0
0
(Search result: Channel no. 0 read)
(2nd read)
0
0
0
0
0
0
1
1
(Search result: Channel no. 3 read)
(3rd read)
0
0
0
0
0
1
1
0
(Search result: Channel no. 6 read)
(4th read)
1
0
0
Figure 35.4
(Search result: No corresponding channel no.)
Writes to and reads from CSSR and MSSR
The value of CSSR is also updated whenever MSSR is read. On this read, the value prior to conversion by the 8/3
encoder can be read.
35.2.19
Acceptance Filter Support Register (AFSR)
Address(es): CAN0.AFSR 4005 0856h, CAN1.AFSR 4005 1856h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b15 to b0
After the standard ID of a received message is written, the value converted for data table search can be read
R/W
Note:
Write to AFSR in CAN operation mode or CAN halt mode.
The acceptance filter support unit (ASU) can be used for data table (8 bits × 256) searches. In the data table, all standard
IDs that you create are set as valid or invalid in bit units. When AFSR is written with data in 16-bit units including the
SID[10:0] bits in MBj_ID (j = 0 to 31), in which a received standard ID is stored, a decoded row (byte offset) position
and column (bit) position for data table search can be read. The ASU can be used for standard (11-bit) IDs only.
The ASU is enabled in the following cases:
When the ID to be received cannot be masked by the acceptance filter. For example, if IDs to be received are 078h,
087h, and 111h.
When there are too many IDs to receive, and the software filtering time is expected to be shortened.
Note:
AFSR cannot be set in CAN reset mode.
Figure 35.5 shows the writes to and reads from AFSR.
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35. Controller Area Network (CAN) Module
Address
b15
b8
b7
b0
SID SID SID SID SID SID SID SID SID SID SID
10
9
8
7
6
5
4
3
2
1
0
When writing*1
CAN0
4005 0856h
3/8 decoder
b15
b8
b7
b0
SID SID SID SID SID SID SID SID
10
9
8
7
6
5
4
3
When reading
Column (bit) position in data table
CAN0
4005 0856h
Row (byte offset) position in data table
Note 1. Write the same value as the 16-bit unit data, including the SID[10:0] bits in MBj_ID (j = 0 to 31).
Figure 35.5
35.2.20
Writes to and reads from AFSR
Error Interrupt Enable Register (EIER)
Address(es): CAN0.EIER 4005 084Ch, CAN1.EIER 4005 184Ch
Value after reset:
b7
b6
b5
BLIE
OLIE
ORIE
0
0
0
b4
b3
BORIE BOEIE
0
b2
b1
b0
EPIE
EWIE
BEIE
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BEIE
Bus Error Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b1
EWIE
Error-Warning Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b2
EPIE
Error-Passive Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b3
BOEIE
Bus-Off Entry Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b4
BORIE
Bus-Off Recovery Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b5
ORIE
Overrun Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b6
OLIE
Overload Frame Transmit Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b7
BLIE
Bus Lock Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
EIER enables or disables each error interrupt source independently in EIFR. Write to EIER in CAN reset mode.
BEIE bit (Bus Error Interrupt Enable)
When the BEIE bit is 0, no error interrupt request occurs even if the BEIF bit in EIFR is 1. When the BEIE bit is 1, an
error interrupt request occurs if the BEIF bit is set to 1.
EWIE bit (Error-Warning Interrupt Enable)
When the EWIE bit is 0, no error interrupt request occurs even if the EWIF bit in EIFR is 1. When the EWIE bit is 1, an
error interrupt request is generated if the EWIF bit is set to 1.
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35. Controller Area Network (CAN) Module
EPIE bit (Error-Passive Interrupt Enable)
When the EPIE bit is 0, no error interrupt request occurs even if the EPIF bit in EIFR is 1. When the EPIE bit is 1, an
error interrupt request occurs if the EPIF bit is set to 1.
BOEIE bit (Bus-Off Entry Interrupt Enable)
When the BOEIE bit is 0, no error interrupt request occurs even if the BOEIF bit in EIFR is 1. When the BOEIE bit is 1,
an error interrupt request occurs if the BOEIF bit is set to 1.
BORIE bit (Bus-Off Recovery Interrupt Enable)
When the BORIE bit is 0, no error interrupt request occurs even if the BORIF bit in EIFR is 1. When the BORIE bit is 1,
an error interrupt request occurs if the BORIF bit is set to 1.
ORIE bit (Overrun Interrupt Enable)
When the ORIE bit is 0, no error interrupt request occurs even if the ORIF bit in EIFR is 1. When the ORIE bit is 1, an
error interrupt request occurs if the ORIF bit is set to 1.
OLIE bit (Overload Frame Transmit Interrupt Enable)
When the OLIE bit is 0, no error interrupt request occurs even if the OLIF bit in EIFR is 1. When the OLIE bit is 1, an
error interrupt request occurs if the OLIF bit is set to 1.
BLIE bit (Bus Lock Interrupt Enable)
When the BLIE bit is 0, no error interrupt request occurs even if the BLIF bit in EIFR is 1. When the BLIE bit is 1, an
error interrupt request occurs if the BLIF bit is set to 1.
35.2.21
Error Interrupt Factor Judge Register (EIFR)
Address(es): CAN0.EIFR 4005 084Dh, CAN1.EIFR 4005 184Dh
Value after reset:
b7
b6
b5
BLIF
OLIF
ORIF
0
0
0
b4
b3
BORIF BOEIF
0
b2
b1
b0
EPIF
EWIF
BEIF
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BEIF
Bus Error Detect Flag
0: No bus error detected
1: Bus error detected.
R/W
b1
EWIF
Error-Warning Detect Flag
0: No error-warning detected
1: Error-warning detected.
R/W
b2
EPIF
Error-Passive Detect Flag
0: No error-passive detected
1: Error-passive detected.
R/W
b3
BOEIF
Bus-Off Entry Detect Flag
0: No bus-off entry detected
1: Bus-off entry detected.
R/W
b4
BORIF
Bus-Off Recovery Detect Flag
0: No bus-off recovery detected
1: Bus-off recovery detected.
R/W
b5
ORIF
Receive Overrun Detect Flag
0: No receive overrun detected
1: Receive overrun detected.
R/W
b6
OLIF
Overload Frame Transmission
Detect Flag
0: No overload frame transmission detected
1: Overload frame transmission detected.
R/W
b7
BLIF
Bus Lock Detect Flag
0: No bus lock detected
1: Bus lock detected.
R/W
If an event associated with one of these bits occurs, the associated bit in EIFR is set to 1, regardless of the setting of
EIER.
Clear the bits to 0 through a software write. If a bit is set to 1 at the same time that software clears it, it becomes 1. When
setting a single bit to 0 in software, use the transfer instruction (MOV) to ensure that only the specified bit is set to 0 and
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35. Controller Area Network (CAN) Module
the other bits are set to 1. Writing 1 has no effect to these bit values.
BEIF flag (Bus Error Detect Flag)
The BEIF flag is set to 1 when a bus error is detected.
EWIF flag (Error-Warning Detect Flag)
The EWIF flag is set to 1 when the value of the receive error counter (REC) or transmit error counter (TEC) exceeds 95.
It is set to 1 only when REC or TEC initially exceeds 95. If 0 is written to the EWIF flag by software while REC or TEC
remains greater than 95, the EWIF flag does not set to 1 until REC or TEC goes below 95 and then exceeds 95 again.
EPIF flag (Error-Passive Detect Flag)
The EPIF flag is set to 1 when the CAN error state becomes error-passive, when the receive error counter (REC) or
transmit error counter (TEC) value exceeds 127. It is set to 1 only when REC or TEC initially exceeds 127. If 0 is written
to the EPIF flag by software while REC or TEC remains greater than 127, the flag does not set to 1 until REC or TEC
goes below 127 and then exceeds 127 again.
BOEIF flag (Bus-Off Entry Detect Flag)
The BOEIF flag is set to 1 when the CAN error state becomes bus-off, when the transmit error counter (TEC) value
exceeds 255. It also is set to 1 when the BOM[1:0] bits in CTLR are 01b (automatic entry to CAN halt mode on bus-off
entry) and the CAN module becomes the bus-off state.
BORIF flag (Bus-Off Recovery Detect Flag)
The BORIF flag is set to 1 when the CAN module recovers from the bus-off state normally by detecting 11 consecutive
recessive bits 128 times in the following conditions:
When the BOM[1:0] bits in CTLR are 00b
When the BOM[1:0] bits in CTLR are 10b
When the BOM[1:0] bits in CTLR are 11b.
However, the BORIF flag does not set to 1 if the CAN module recovers from the bus-off state in the following
conditions:
When the CANM[1:0] bits in CTLR are set to 01b or 11b (CAN reset mode)
When the RBOC bit in CTLR is set to 1 (forced return from bus-off)
When the BOM[1:0] bits in CTLR are set to 01b
When the BOM[1:0] bits in CTLR are set to 11b and the CANM[1:0] bits in CTLR are set to 10b (CAN halt mode)
before normal recovery occurs.
Table 35.7 lists the behavior of the BOEIF and BORIF bits for each CTLR.BOM[1:0] bit setting.
Table 35.7
Behavior of BOEIF and BORIF flags for each CTLR.BOM[1:0] setting
BOM[1:0] bits
BOEIF bit
BORIF bit
00b
Set to 1 on entry to the bus-off state
Sets to 1 on exit from the bus-off state
01b
Does not set to 1
10b
Sets to 1 on exit from the bus-off state
11b
Sets to 1 if normal bus-off recovery occurs before the CANM[1:0] bits
are set to 10b (CAN halt mode)
ORIF flag (Receive Overrun Detect Flag)
The ORIF flag is set to 1 when a receive overrun occurs. It does not set to 1 in overwrite mode.
In overwrite mode, a reception complete interrupt request occurs if an overwrite condition occurs and the ORIF bit is not
set to 1.
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35. Controller Area Network (CAN) Module
In overrun mode with normal mailbox mode, if an overrun occurs in any of mailboxes 0 to 31, this flag is set to 1. In
overrun mode with FIFO mailbox mode, if an overrun occurs in any of mailboxes 0 to 23 or the receive FIFO, this bit is
set to 1.
OLIF flag (Overload Frame Transmission Detect Flag)
The OLIF flag is set to 1 if the transmitting condition of an overload frame is detected when the CAN module is
transmitting or receiving.
BLIF flag (Bus Lock Detect Flag)
The BLIF flag is set to 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN
operation mode. After the BLIF flag is set to 1, 32 consecutive dominant bits are detected again under either of the
following conditions:
Recessive bits are detected after this flag changes to 0 from 1
The CAN module enters CAN reset or halt mode and then enters CAN operation mode again after this flag changes
to 0 from 1.
35.2.22
Receive Error Count Register (RECR)
Address(es): CAN0.RECR 4005 084Eh, CAN1.RECR 4005 184Eh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
Bit
Description
b7 to b0
Receive error count function
R
RECR increments or decrements the counter value based on the error status of the CAN module during reception.
R/W
RECR indicates the value of the receive error counter. See the CAN specification (ISO11898-1) for the increment and
decrement conditions of the receive error counter. The value of RECR in the bus-off state is undefined.
35.2.23
Transmit Error Count Register (TECR)
Address(es): CAN0.TECR 4005 084Fh, CAN1.TECR 4005 184Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
Bit
Description
R/W
b7 to b0
Transmit error count function
TECR increments or decrements the counter value based on the error status of the CAN module during
transmission.
R
TECR indicates the value of the transmit error counter. See the CAN specification (ISO11898-1) for information about
the increment and decrement conditions of the transmit error counter. The value of TECR in the bus-off state is
undefined.
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35.2.24
35. Controller Area Network (CAN) Module
Error Code Store Register (ECSR)
Address(es): CAN0.ECSR 4005 0850h, CAN1.ECSR 4005 1850h
b7
b6
b5
b4
b3
b2
b1
b0
EDPM
ADEF
BE0F
BE1F
CEF
AEF
FEF
SEF
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Flag *1,*2
Description
R/W
0: No stuff error detected
1: Stuff error detected.
R/W
b0
SEF
Stuff Error
b1
FEF
Form Error Flag *1,*2
0: No form error detected
1: Form error detected.
R/W
b2
AEF
ACK Error Flag *1,*2
0: No ACK error detected
1: ACK error detected.
R/W
b3
CEF
CRC Error Flag *1,*2
0: No CRC error detected
1: CRC error detected.
R/W
b4
BE1F
Bit Error (recessive) Flag *1,*2
0: No bit error (recessive) detected
1: Bit error (recessive) detected.
R/W
b5
BE0F
Bit Error (dominant) Flag *1,*2
0: No bit error (dominant) detected
1: Bit error (dominant) detected.
R/W
b6
ADEF
ACK Delimiter Error Flag *1,*2
0: No ACK delimiter error detected
1: ACK delimiter error detected.
R/W
b7
EDPM
Error Display Mode Select *3,*4
0: Output first detected error code
1: Output accumulated error code.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Writing 1 has no effect on these bit values.
To write 0 to the SEF, FEF, AEF, CEF, BE1F, BE0F, and ADEF bits, use the transfer (MOV) instruction to ensure that only the
specified bit is set to 0 and the other bits are set to 1.
Write to the EDPM bit in CAN reset or halt mode.
If more than one error condition is detected simultaneously, all related bits are set to 1.
ECSR indicates whether an error occurs on the CAN bus. See the CAN specification (ISO11898-1) for the conditions
when each error occurs.
Clear all of the bits except the EDPM bit to 0 through a software write. If a bit is set to 1 at the same time that software
clears it, it becomes 1.
SEF flag (Stuff Error Flag)
The SEF flag is set to 1 when a stuff error is detected.
FEF flag (Form Error Flag)
The FEF flag is set to 1 when a form error is detected.
AEF flag (ACK Error Flag)
The AEF flag is set to 1 when an ACK error is detected.
CEF flag (CRC Error Flag)
The CEF flag is set to 1 when a CRC error is detected.
BE1F flag (Bit Error (recessive) Flag)
The BE1F flag is set to 1 when a recessive bit error is detected.
BE0F flag (Bit Error (dominant) Flag)
The BE0F flag is set to 1 when a dominant bit error is detected.
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35. Controller Area Network (CAN) Module
ADEF flag (ACK Delimiter Error Flag)
The ADEF flag is set to 1 when a form error is detected with the ACK delimiter during transmission.
EDPM bit (Error Display Mode Select)
The EDPM bit selects the output mode of ECSR. When the EDPM bit is set to 0, ECSR outputs the first error code.
When the EDPM bit is set to 1, ECSR outputs the accumulated error code.
35.2.25
Time Stamp Register (TSR)
Address(es): CAN0.TSR 4005 0854h, CAN1.TSR 4005 1854h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
R/W
b15 to b0
Free-running counter value for the time stamp function
R
Note:
Read TSR in 16-bit units.
When TSR is read, the value of the time stamp counter (16-bit free-running counter) at that moment, is read. The time
stamp counter reference clock is configured in the TSPS[1:0] bits in CTLR. The counter stops in CAN sleep and halt
modes, and is initialized in CAN reset mode. Its value is stored in the TSL[7:0] and TSH[7:0] bits in MBj_TS when a
received message is stored in a receive mailbox.
35.2.26
Test Control Register (TCR)
Address(es): CAN0.TCR 4005 0858h, CAN1.TCR 4005 1858h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
TSTM[1:0]
0
0
0
0
0
0
b0
TSTE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TSTE
CAN Test Mode Enable
0: Disable CAN test mode
1: Enable CAN test mode.
R/W
b2, b1
TSTM[1:0]
CAN Test Mode Select
b2 b1
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: Not CAN test mode
1: Listen-only mode
0: Self-test mode 0 (external loopback)
1: Self-test mode 1 (internal loopback).
TCR controls the CAN test mode. Write to TCR in CAN halt mode only.
(1)
Listen-only mode
The CAN specification (ISO11898-1) recommends an optional bus monitoring mode. In listen-only mode, valid data
frames and valid remote frames can be received. However, only recessive bits can be sent on the CAN bus. The ACK bit,
overload flag, and active error flag cannot be sent.
Listen-only mode can be used for baud rate detection.
Do not request transmission from any mailboxes in listen-only mode.
Figure 35.6 shows the connection when listen-only mode is selected.
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35. Controller Area Network (CAN) Module
CTXi
CRXi
Recessive level
CTXi
(internal)
Figure 35.6
(2)
CRXi
(internal)
Connection when listen-only mode is selected (i = 0, 1)
Self-test mode 0 (external loopback)
Self-test mode 0 is provided for CAN transceiver tests. In this mode, the protocol module treats its own transmitted
messages as those received by the CAN transceiver and stores them into the receive mailbox. To be independent from
external stimulation, the protocol module generates the ACK bit.
Connect the CTXi and CRXi pins to the transceiver.
Figure 35.7 shows the connection when self-test mode 0 is selected.
CAN transceiver
CTXi
CRXi
ACK
CTXi
(internal)
Figure 35.7
(3)
CRXi
(internal)
Connection when self-test mode 0 is selected (i = 0, 1)
Self-test mode 1 (internal loopback)
Self-test mode 1 is provided for self-test functions.
In self-test mode 1, the protocol controller treats its transmitted messages as received messages and stores them into the
receive mailbox. To be independent from external stimulation, the protocol controller generates the ACK bit.
In self-test mode 1, the protocol controller performs an internal feedback from the internal CTXi pin to the internal CRXi
pin. The input value of the external CRXi pin is ignored. The external CTXi pin outputs only recessive bits. The CTXi
and CRXi pins are not required to be connected to the CAN bus or any external device.
Figure 35.8 shows the connection when self-test mode 1 is selected.
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35. Controller Area Network (CAN) Module
CTXi
CRXi
Recessive level
ACK
CTXi
(internal)
Figure 35.8
35.3
CRXi
(internal)
Connection when self-test mode 1 is selected (i = 0, 1)
Operation Modes
The CAN module operation modes include:
CAN reset mode
CAN halt mode
CAN operation mode
CAN sleep mode.
Figure 35.9 shows the transitions between the operation modes.
CPU reset
CANM[1:0] = 01b or 11b
when SLPM = 0
CAN Sleep mode*2
CANM[1:0] = 00b
CAN reset mode
CANM[1:0]
= 00b
CANM[1:0] = 10b
when SLPM = 0
SLPM = 1
CAN operation mode
CANM[1:0]
= 01b, 11b
SLPM = 1
CANM[1:0]
= 10b
CANM[1:0]
= 01b, 11b
CAN halt mode
TEC > 255
CANM[1:0] = 10b
CANM[1:0]
= 01b, 11b
When BOM[1:0] = 00b or 11b
(no halt request) and 11
consecutive recessive bits are
detected 128 times or RBOC = 1
CAN operation mode
(bus-off state)
CANM[1:0] = 10b*1
CANM, SLPM, BOM, RBOC: Bits in CTLR
Note 1. The transition timing from the bus-off state to CAN halt mode depends on the setting of the CTLR.BOM[1:0] bits.
When the CTLR.BOM[1:0] bits are 01b, the state transition occurs immediately after entering the bus-off state.
When the CTLR.BOM[1:0] bits are 10b, the state transition occurs at the end of the bus-off state.
When the CTLR.BOM[1:0] bits are 11b, the state transition occurs at the setting of the CTLR.CANM[1:0] bits to 10b (CAN
halt mode).
Note 2. Change the CTLR.SLPM bit to set or cancel CAN sleep mode.
Figure 35.9
35.3.1
Transition between different operation modes
CAN Reset Mode
CAN reset mode is provided for CAN communication configuration. When the CTLR.CANM[1:0] bits are set to 01b or
11b, the CAN module enters CAN reset mode. The STR.RSTST bit then is set to 1. Do not change the
CTLR.CANM[1:0] bits until the RSTST bit is 1. Set BCR before exiting CAN reset mode to any other modes.
The following registers are initialized to their reset values after entering CAN reset mode, and their initial values are
saved during CAN reset mode:
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35. Controller Area Network (CAN) Module
MCTL_TXj and MCTL_RXj
STR (except for the SLPST and TFST bits)
EIFR
RECR
TECR
TSR
MSSR
MSMR
RFCR
TFCR
TCR
ECSR (except for the EDPM bit).
The following registers retain their previous values even after entering CAN reset mode:
CTLR
STR (only the SLPST and TFST bits)
MIER and MIER_FIFO
EIER
BCR
CSSR
ECSR (only the EDPM bit)
MBj_ID, MBj_DL, MBj_Dm and MBj_TS
MKRk
FIDCR0 and FIDCR1
MKIVLR
AFSR
RFPCR
TFPCR.
35.3.2
CAN Halt Mode
CAN halt mode is used for mailbox configuration and test mode setting.
When the CTLR.CANM[1:0] bits are set to 10b, CAN halt mode is selected. Then the STR.HLTST bit is set to 1. Do not
change the CTLR.CANM[1:0] bits until the HLTST bit is 1.
See Table 35.8 for the state transition conditions when transmitting or receiving.
All registers except for the RSTST, HLTST, and SLPST bits in STR remain unchanged when the CAN enters CAN halt
mode.
Do not change CTLR (except for the CANM[1:0] and SLPM bits) and EIER in CAN halt mode. BCR can be changed in
CAN halt mode only when listen-only mode is selected for automatic baud rate detection.
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Table 35.8
35. Controller Area Network (CAN) Module
Operation in CAN reset and halt modes
Operation mode
Receiver
Transmitter
Bus-off
CAN reset mode
(forced transition)
CANM[1:0] = 11b
CAN module enters CAN reset
mode without waiting for the end
of message reception
CAN module enters CAN reset
mode without waiting for the end
of message transmission
CAN module enters CAN reset mode
without waiting for the end of bus-off
recovery
CAN reset mode
CANM[1:0] = 01b
CAN module enters CAN reset
mode without waiting for the end
of message reception
CAN module enters CAN reset
mode after waiting for the end of
message transmission*1,*4
CAN module enters CAN reset mode
without waiting for the end of bus-off
recovery
CAN halt mode
CAN module enters CAN halt
mode after waiting for the end of
message reception*2,*3
CAN module enters CAN halt
mode after waiting for the end of
message transmission*1,*4
When the BOM[1:0] bits are 00b:
A halt request from software is accepted
only after bus-off recovery.
When the BOM[1:0] bits are 01b:
CAN module automatically enters CAN
halt mode without waiting for the end of
bus-off recovery, regardless of a halt
request from software.
When the BOM[1:0] bits are 10b:
CAN module automatically enters CAN
halt mode after waiting for the end of
bus-off recovery, regardless of a halt
request from software.
When the BOM[1:0] bits are 11b:
CAN module enters CAN halt mode
without waiting for the end of bus-off
recovery, if a halt is requested by
software during bus-off.
BOM[1:0] bits: Bits in CTLR
Note 1.
Note 2.
Note 3.
Note 4.
35.3.3
If transmission of multiple messages is requested, a mode transition occurs on completion of the first transmission. If the CAN
reset mode is being requested during suspend transmission, mode transition occurs when the bus is idle, the next transmission
ends, or the CAN module becomes a receiver.
If the CAN bus is locked at the dominant level, the program can detect this state by monitoring the BLIF bit in EIFR.
If a CAN bus error occurs during reception after CAN halt mode is requested, the CAN module transitions to CAN halt mode.
If a CAN bus error or arbitration-lost occurs during transmission after CAN reset mode or CAN halt mode is requested, the CAN
module transits to the requested CAN mode.
CAN Sleep Mode
CAN sleep mode reduces power consumption by stopping the clock supply to the CAN module. After a reset from an
MCU pin or a software reset, the CAN module starts from CAN sleep mode.
When the SLPM bit in CTLR is set to 1, the CAN module enters CAN sleep mode. Then the SLPST bit in STR is set to
1. Do not change the value of the SLPM bit until the SLPST bit is 1. The other registers remain unchanged when the
CAN module enters CAN sleep mode.
Write to the SLPM bit in CAN reset mode and CAN halt mode. Do not change any registers (except for the SLPM bit)
during CAN sleep mode. Read operation is still allowed.
When the SLPM bit is set to 0, the CAN module is released from CAN sleep mode. When the CAN module exits CAN
sleep mode, the other registers remain unchanged.
35.3.4
CAN Operation Mode (Excluding Bus-Off State)
CAN operation mode is used for CAN communication.
When the CANM[1:0] bits in CTLR are set to 00b, the CAN module enters CAN operation mode. Then, the RSTST and
HLTST bits in STR set to 0. Do not change the value of the CANM[1:0] bits until the RSTST and HLTST bits are 0.
If 11 consecutive recessive bits are detected after entering CAN operation mode, the following occurs:
The CAN module becomes an active node on the network, which enables transmission and reception of CAN
messages
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35. Controller Area Network (CAN) Module
Error monitoring of the CAN bus, such as receive and transmit error counters, is performed.
During CAN operation mode, the CAN module might be in one of the following three sub-modes, depending on the
status of the CAN bus.
Idle mode: No transmission or reception occurs
Receive mode: A CAN message sent by another node is being received
Transmit mode: A CAN message is being transmitted. The CAN module receives a message transmitted by the
local node simultaneously when self-test mode 0 (TSTM[1:0] bits in TCR = 10b) or self-test mode 1 (TSTM[1:0]
bits = 11b) is selected.
Figure 35.10 demonstrates the sub-modes in CAN operation mode.
Idle mode
STR.TRMST = 0
STR.RECST = 0
SOF
detected
Transmission
starts
Transmission
completed
Transmit mode
STR.TRMST = 1
STR.RECST = 0
Figure 35.10
35.3.5
Reception
completed
Lost in arbitration
Receive mode
STR.TRMST = 0
STR.RECST = 1
Sub-modes of CAN operation mode
CAN Operation Mode (Bus-Off State)
The CAN module enters the bus-off state based on the incrementing/decrementing rules for the transmit and error
counters defined in the CAN specifications. The following cases apply when the CAN module is recovering from the
bus-off state. When the CAN module is in the bus-off state, the values of the CAN-related registers remain unchanged,
except for those in STR, EIFR, RECR, TECR, and TSR.
(1)
When CTLR.BOM[1:0] = 00b (normal mode)
The CAN module enters the error-active state after it completes recovery from the bus-off state and CAN communication
is enabled. The BORIF flag in EIFR is set to 1 (bus-off recovery detected) at this time.
(2)
When CTLR.RBOC = 1 (forced return from bus-off)
The CAN module enters the error-active state when it is in the bus-off state and the RBOC bit is 1. CAN communication
is enabled again after 11b consecutive recessive bits are detected. The BORIF bit does not set to 1 at this time.
(3)
When CTLR.BOM[1:0] = 01b (automatic transition to CAN halt mode on bus-off)
The CAN module enters CAN halt mode when it reaches the bus-off state. The BORIF flag does not set to 1 at this time.
(4)
When CTLR.BOM[1:0] = 10b (automatic transition to CAN halt mode on bus-off end)
The CAN module enters CAN halt mode when it completes recovery from bus-off. The BORIF flag is set to 1 at this
time.
(5)
When CTLR.BOM[1:0] = 11b (automatic transition to CAN halt mode through software) and
CTLR.CANM[1:0] = 10b (CAN halt mode) during bus-off state
The CAN module enters CAN halt mode when it is in the bus-off state and the CANM[1:0] bits are set to 10b (CAN halt
mode). The BORIF flag does not set to 1 at this time.
If the CANM[1:0] bits are not set to 10b during bus-off, the same behavior as (1) applies.
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35.4
35. Controller Area Network (CAN) Module
Data Transfer Rate Configuration
This section describes how to configure the data transfer rate.
35.4.1
Clock Setting
The CAN module has a CAN clock generator that can be set by the CCLKS and BRP[9:0] bits in the BCR register.
Figure 35.11 shows a block diagram of the CAN clock generator.
CCLKS*1
Peripheral module clock
(PCLKB)*1
0
1
fCAN
Baud rate
prescaler
1/(P + 1)
fCANCLK
P = 0 to 1023
EXTAL
CCLKS:
fCAN:
P:
fCANCLK:
Bit in the BCR register
CAN system clock
Value selected in BRP[9:0] bits in BCR (P = 0 to 1023)
CAN communication clock (fCANCLK = fCAN/(P + 1))
Note 1. See section 9, Clock Generation Circuit. When using the CAN module while the CCLKS bit is
cleared to 0, PLL must be selected as the source of the peripheral module clock.
Figure 35.11
35.4.2
Block diagram of CAN clock generator
Bit Timing Setting
The bit time consists of the following three segments shown in Figure 35.12.
Bit time
SS
TSEG1
TSEG2
Sample point
The range of each segment:
Bit time = 8 Tq to 25 Tq
SS = 1 Tq
TSEG1 = 4 Tq to 16 Tq
TSEG2 = 2 Tq to 8 Tq
SJW = 1 Tq to 4 Tq
Setting of TSEG1 and TSEG2: TSEG1 > TSEG2 SJW
Figure 35.12
35.4.3
Bit timing
Data Transfer Rate
The data transfer rate depends on the division value of fCAN (CAN system clock), the division value of the baud rate
prescaler, and the Tq count for 1 bit time.
Data transfer rate
(bps)
=
fCAN
Baud rate prescaler division
value*1
x number of Tq of 1 bit time
=
fCANCLK
Tq count for 1 bit time
Note 1. Division value of baud rate prescaler = P + 1 (P: 0 to 1023), where P is the BRP[9:0] setting in BCR.
Table 35.9 lists data transfer rate examples.
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Table 35.9
35. Controller Area Network (CAN) Module
Data transfer rate examples
fCAN
50 MHz
48 MHz
40 MHz
32 MHz
Data transfer rate
Tq count
P+1
Tq count
P+1
Tq count
P+1
Tq count
P+1
1 Mbps
10Tq
25Tq
5
2
8Tq
12Tq
16Tq
6
4
3
10Tq
20Tq
4
2
8Tq
16Tq
4
2
500 kbps
10Tq
25Tq
10
4
8Tq
12Tq
16Tq
12
8
6
10Tq
20Tq
8
4
8Tq
16Tq
8
4
250 kbps
10Tq
25Tq
20
8
8Tq
12Tq
16Tq
24
16
12
10Tq
20Tq
16
8
8Tq
16Tq
16
8
125 kbps
10Tq
25Tq
40
16
8Tq
12Tq
16Tq
48
32
24
10Tq
20Tq
32
16
8Tq
16Tq
32
16
83.3 kbps
10Tq
25Tq
60
24
8Tq
12Tq
16Tq
72
48
36
8Tq
10Tq
16Tq
20Tq
60
48
30
24
8Tq
16Tq
48
24
33.3 kbps
10Tq
25Tq
150
60
8Tq
12Tq
16Tq
180
120
90
8Tq
10Tq
20Tq
150
120
60
8Tq
10Tq
16Tq
20Tq
120
96
60
48
35.5
Mailbox and Mask Register Structure
Figure 35.13 shows the structure of the 32 mailbox registers: MBj_ID, MBj_DL, MBj_Dm, and MBj_TS.
Address
b7
b0
IDE
RTR
SID5
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0200h + 16 j + 0
4005 0200h + 16 j + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0200h + 16 j + 2
EID7
EID0
4005 0200h + 16 j + 3
EID6
EID5
EID4
EID3
EID2
EID1
4005 0200h + 16 j + 4
DLC3 DLC2 DLC1 DLC0
Figure 35.13
4005 0200h + 16 j + 5
DATA0
4005 0200h + 16 j + 6
DATA1
4005 0200h + 16 j + 7
DATA7
4005 0200h + 16 j + 13
TSH
4005 0200h + 16 j + 14
TSL
4005 0200h + 16 j + 15
Structure of the mailbox registers (j = 0 to 31)
Figure 35.14 shows the structure of the eight mask registers: MKRk.
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35. Controller Area Network (CAN) Module
Address
b7
SID5
b0
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0400h + 4 k + 0
4005 0400h + 4 k + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0400h + 4 k + 2
EID7
EID0
4005 0400h + 4 k + 3
EID6
EID5
EID4
EID3
EID2
EID1
MKRk register
Figure 35.14
Structure of the MKRk registers (k = 0 to 7)
Figure 35.15 shows the structure of the two FIFO receive ID compare registers: FIDCR0 and FIDCR1.
Address
b7
b0
IDE
RTR
SID5
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0420h + 4 n + 0
4005 0420h + 4 n + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0420h + 4 n + 2
EID7
EID0
4005 0420h + 4 n + 3
EID6
EID5
EID4
EID3
EID2
EID1
FIDCRn register
Figure 35.15
35.6
Structure of the FIDCRn registers (n = 0, 1)
Acceptance Filtering and Masking Functions
The acceptance filtering and masking functions allow you to select and receive messages with multiple IDs for
mailboxes within a specified range.
The MKRk registers can mask the standard ID and the extended ID for 29 bits.
MKR0 controls mailboxes 0 to 3
MKR1 controls mailboxes 4 to 7
MKR2 controls mailboxes 8 to 11
MKR3 controls mailboxes 12 to 15
MKR4 controls mailboxes 16 to 19
MKR5 controls mailboxes 20 to 23
MKR6 controls mailboxes 24 to 27 in normal mailbox mode and the receive FIFO mailboxes 28 to 31 in FIFO
mailbox mode
MKR7 controls mailboxes 28 to 31 in normal mailbox mode and the receive FIFO mailboxes 28 to 31 in FIFO
mailbox mode.
MKIVLR disables acceptance filtering independently for each mailbox.
The IDE bit in MBj_ID is valid when the IDFM[1:0] bits in CTLR are 10b (mixed ID mode).
The RTR bit in MBj_ID selects a data or remote frame.
In FIFO mailbox mode, the normal mailboxes (0 to 23) use one associated register from MKR0 to MKR5 for acceptance
filtering. The receive FIFO mailboxes (28 to 31) use two registers, MKR6 and MKR7, for acceptance filtering.
The receive FIFO also uses two registers, FIDCR0 and FIDCR1, for ID comparison. The EID[17:0], SID[10:0], RTR,
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35. Controller Area Network (CAN) Module
and IDE bits in mailbox 28 to mailbox 31 for the receive FIFO are disabled. As acceptance filtering depends on the result
of two logic OR operations, two ranges of IDs can be received into the receive FIFO.
MKIVLR is disabled for the receive FIFO.
If different standard ID and extended ID values are set in the IDE bits in FIDCR0 and FIDCR1, both ID formats are
received.
If different data frame and remote frame values are set in the RTR bits in FIDCR0 and FIDCR1, both data and remote
frames are received.
When a combination of two ranges of IDs is not necessary, set the same mask value and the same ID in both the FIFO ID
and mask registers.
Figure 35.16 shows the associations between the mask registers and mailboxes. Figure 35.17 shows the acceptance
filtering.
Normal mailbox mode
FIFO mailbox mode
Mailbox 0
Mailbox 0
MKR0 register
MKR0 register
Mailbox 3
Mailbox 3
Mailbox 4
Mailbox 4
MKR1 register
MKR1 register
Mailbox 7
Mailbox 7
Mailbox 8
Mailbox 8
MKR2 register
MKR2 register
Mailbox 11
Mailbox 11
Mailbox 12
Mailbox 12
MKR3 register
MKR3 register
Mailbox 15
Mailbox 15
Mailbox 16
Mailbox 16
MKR4 register
MKR4 register
Mailbox 19
Mailbox 19
Mailbox 20
Mailbox 20
MKR5 register
MKR5 register
Mailbox 23
Mailbox 24
MKR6 register
Mailbox 27
Mailbox 28
MKR7 register
Mailbox 31
Figure 35.16
Mailbox 23
MKR6 register
FIDCR0 register
MKR7 register
FIDCR1 register
Mailbox 24
Transmit FIFO
Mailbox 27
Mailbox 28
Receive FIFO
Mailbox 31
Associations between mask registers and mailboxes
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35. Controller Area Network (CAN) Module
ID setting of MBj_ID
(j = 0 to 31)*1
ID value of received
message
Setting of MKIVLR*2
Setting of MKRk
(k = 0 to 7)
Mask bit values
0: IDs not compared
1: IDs compared
Acceptance judge signal
(internal signal)
Acceptance judge signal
0: Receiving message is ignored
(not stored in any mailbox)
1: Receiving message is stored in a mailbox
which matches the ID
Note 1. The settings of FIDCR0 and FIDCR1 are used in FIFO mailbox mode.
Note 2. Invalid in FIFO mailboxes.
Figure 35.17
35.7
Acceptance filtering
Reception and Transmission
Table 35.10 lists the CAN communication mode settings.
Table 35.10
Settings for CAN receive and transmit modes
MCTL_TXj.TRMREQ
and
MCTL_RXj.TRMREQ
MCTL_TXj.RECREQ
and
MCTL_RXj.RECREQ
MCTL_TXj.ONESHOT
and
MCTL_RXj.ONESHOT
Mailbox communication mode
0
0
0
Mailbox disabled or transmission being aborted
0
0
1
Can be configured only when transmission or reception
from a mailbox programmed in one-shot mode is aborted
0
1
0
Configured as a receive mailbox for a data or remote
frame
0
1
1
Configured as a one-shot receive mailbox for a data or
remote frame
1
0
0
Configured as a transmit mailbox for a data or remote
frame
1
0
1
Configured as a one-shot transmit mailbox for a data or
remote frame
1
1
0
Do not set
1
1
1
Do not set
j = 0 to 31
When a mailbox is configured as a receive mailbox or a one-shot receive mailbox, the following restrictions apply:
Before configuring the mailbox, set MCTL_RXj to 00h
A received message is stored in the first mailbox that matches the condition resulting from the receive mode settings
and acceptance filtering. The matching mailbox with the smallest number takes priority for storing the received
message.
In CAN operation mode, the CAN module does not receive its own transmitted data even if the ID is a match. In
self-test mode, however, the CAN module receives its own transmitted data and returns ACK.
When configuring a mailbox as a transmit mailbox or a one-shot transmit mailbox, the following constraint applies:
Before configuring a mailbox, ensure that MCTL_TXj is 00h and that there is no pending abort process.
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35.7.1
35. Controller Area Network (CAN) Module
Reception
Figure 35.18 shows an operation example of data frame reception in overwrite mode. The example shows the
overwriting of the first message when the CAN module receives two consecutive CAN messages that match the
receiving conditions in MCTL_RXj (j = 0 to 31).
Receive message in mailbox j
SOF
CRC
ACK
Receive message in mailbox j
EOF
IFS SOF
CRC
ACK
EOF
IFS
CAN bus
Acceptance filtering
Acceptance filtering
MCTL_RX[j].RECREQ
MCTL_RX[j].INVALDATA
MCTL_RX[j].NEWDATA
MCTL_RX[j].MSGLOST
CANi reception
complete interrupt
STR.RECST
CANi error
interrupt
j = 0 to 31
Figure 35.18
Operation example of data frame reception in overwrite mode
1. When an SOF is detected on the CAN bus, the RECST bit in STR is set to 1 (reception in progress) if the CAN
module has no message ready to start transmission.
2. Acceptance filtering starts at the beginning of the CRC field to select the receive mailbox.
3. After a message is received, the NEWDATA flag in MCTL_RXj for the receive mailbox is set to 1 (new message is
being stored or was stored in the mailbox). The INVALDATA flag in MCTL_RXj is set to 1 (message is being
updated) at the same time, and then the INVALDATA flag is set to 0 (message valid) again after the complete
message is transferred to the mailbox.
4. When the interrupt enable bit in MIER for the receive mailbox is 1 (interrupt enabled), the INVALDATA flag is set
to 0, which triggers a CAN0 reception complete interrupt request.
5. After reading the message from the mailbox, the NEWDATA flag must be set to 0 by software.
6. In overwrite mode, if the next CAN message is received while the NEWDATA flag in MCTL_RXj is set to 1, the
MSGLOST flag in MCTL_RXj is set to 1 (message was overwritten). The new received message is transferred to
the mailbox. The CAN0 reception complete interrupt request occurs the same as in step 4.
Figure 35.19 shows an operation example of data frame reception in overrun mode. The example shows the overrunning
of the second message when the CAN module receives two consecutive CAN messages that match the receiving
conditions in MCTL_RXj (j = 0 to 31).
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35. Controller Area Network (CAN) Module
Receive message in mailbox j
SOF
CRC
ACK
Receive message in mailbox j
EOF
IFS SOF
CRC
ACK
EOF
IFS
CAN bus
Acceptance filtering
Acceptance filtering
MCTL_RX[j].RECREQ
MCTL_RX[j].INVALDATA
MCTL_RX[j].NEWDATA
MCTL_RX[j].MSGLOST
CANi reception
complete interrupt
STR.RECST
CANi error
interrupt
j = 0 to 31
Figure 35.19
Operation example of data frame reception in overrun mode
Steps 1 to 5 are the same as in overwrite mode.
6. In overrun mode, if the next CAN message is received before the NEWDATA flag in MCTL_RXj is set to 0, the
MSGLOST flag in MCTL_RXj is set to 1 (message overrun). The new received message is discarded and a CANi
error interrupt request occurs if the associated interrupt enable bit in EIER is set to 1 (interrupt enabled).
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35.7.2
35. Controller Area Network (CAN) Module
Transmission
Figure 35.20 shows an operation example of data frame transmission.
Transmission message in mailbox j
SOF
CRC
CRC
delimiter
Transmission message in mailbox k
EOF
IFS SOF
CRC
CRC
delimiter
EOF
IFS
CAN bus
Next transmission scan
Next transmission scan
Next transmission scan
MCTL_TX[j].TRMREQ
Mailbox j
MCTL_TX[j].TRMACTIVE
MCTL_TX[j].SENTDATA
MCTL_TX[k].TRMREQ
Mailbox k
MCTL_TX[k].TRMACTIVE
MCTL_TX[k].SENTDATA
CANi transmission complete interrupt
STR.TRMST
j, k = 0 to 31, j k
Figure 35.20
Operation example of data frame transmission
1. When a TRMREQ bit in MCTL_TXj (j = 0 to 31) is set to 1 (transmit mailbox) in the bus-idle state, mailbox
scanning starts to decide the highest-priority mailbox for transmission. When the transmit mailbox is decided, the
TRMACTIVE flag in MCTL_TXj is set to 1 (from acceptance of transmission request to completion of
transmission, or error or arbitration-lost), the TRMST bit in STR is set to 1 (transmission in progress), and the CAN
module starts transmission.*1
2. If other TRMREQ bits are set, the transmission scanning starts with the CRC delimiter for the next transmission.
3. If transmission is complete without losing arbitration, the SENTDATA flag in MCTL_TXj is set to 1 (transmission
complete) and the TRMACTIVE flag is set to 0 (transmission is pending or transmission is not requested). If the
interrupt enable bit in MIER is 1 (interrupt enabled), the CANi transmission complete interrupt request is generated.
4. When requesting the next transmission from the same mailbox, set the SENTDATA flag and TRMREQ bit to 0, and
then set the TRMREQ bit to 1 after checking that the SENTDATA flag and TRMREQ bit are set to 0.
Note 1. If arbitration is lost after the CAN module starts transmission, the TRMACTIVE flag is set to 0. Transmission
scanning is performed again to search for the highest-priority transmit mailbox from the beginning of the CRC
delimiter. If an error occurs either during transmission or following arbitration-lost, transmission scanning is
performed again to search for the highest-priority transmit mailbox from the start of the error delimiter.
35.8
Interrupts
The CAN module provides the following interrupts for each channel. Table 35.11 lists the CAN interrupts.
CANi reception complete interrupt for mailboxes 0 to 31 (CANi_RXM)
CANi transmission complete interrupt for mailboxes 0 to 31 (CANi_TXM)
CANi receive FIFO interrupt (CANi_RXF)
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35. Controller Area Network (CAN) Module
CANi transmit FIFO interrupt (CANi_TXF)
CANi error interrupt (CANi_ERS).
Eight interrupt sources are available for CANi error interrupts. Check EIFR to determine whether these sources were
triggered:
Bus error
Error-warning
Error-passive
Bus-off entry
Bus-off recovery
Receive overrun
Overload frame transmission
Bus lock.
Table 35.11
Module
CANi
i = 0, 1
CAN interrupts
Interrupt
name
Interrupt source
Source flag
CANi_ERS
Bus lock detected
EIFR.BLIF
CANi_RXF
Overload frame transmission detected
EIFR.OLIF
Overrun detected
EIFR.ORIF
Bus-off recovery detected
EIFR.BORIF
Bus-off entry detected
EIFR.BOEIF
Error-passive detected
EIFR.EPIF
Error-warning detected
EIFR.EWIF
Bus error detected
EIFR.BEIF
Receive FIFO message received (MIER_FIFO.MB29 = 0)
RFCR.RFUST[2:0]
Receive FIFO warning (MIER_FIFO.MB29 = 1)
CANi_TXF
Transmit FIFO message transmission completed (MIER_FIFO.MB25 = 0)
TFCR.TFUST[2:0]
FIFO last message transmission completed (MIER_FIFO.MB25 = 1)
35.9
35.9.1
CANi_RXM
Mailbox 0 to 31 message received
MCTL_RX0.NEWDATA to
MCTL_RX31.NEWDATA
CANi_TXM
Mailbox 0 to 31 message transmission completed
MCTL_TX0.SENTDATA to
MCTL_TX31.SENTDATA
Usage Notes
Settings for the Module-Stop Function
CAN operation can be disabled or enabled using Module Stop Control Register B (MSTPCRB). The CAN module is
initially stopped after reset. Releasing the module-stop state enables access to the registers. For details, see section 11,
Low Power Modes.
35.9.2
Settings for the Operating Clock
The settings for the operating clock can be made as follows:
The following clock constraint must be satisfied for the CAN module when the CCLKS bit is 1:
fPCLKB fCANMCLK
The source of the peripheral module clock must be PLL for the CAN module when the CCLKS bit is 0.
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36. Serial Peripheral Interface (SPI)
36.
Serial Peripheral Interface (SPI)
36.1
Overview
The MCU provides two independent channels for the Serial Peripheral Interface (SPI). The SPI channels are capable of
high-speed, full-duplex, synchronous serial communications with multiple processors and peripheral devices. Table 36.1
lists the SPI specifications, Figure 36.1 shows a block diagram, and Table 36.2 lists the I/O pins.
In this section, n indicates A or B, and i indicates 0 or 1. A lower-case letter i in pin and signal names indicates a value
from 0 to 3, and a lower-case letter m in SPI Command Register m (SPCMDm) indicates a value from 0 to 7.
Table 36.1
SPI specifications (1 of 2)
Parameter
Specifications
Number of channels
Two channels
SPI transfer functions
Use of MOSI (master out/slave in), MISO (master in/slave out), SSL (slave select), and RSPCK (SPI
clock) signals allows serial communications through SPI operation (4-wire method) or clock
synchronous operation (3-wire method)
Transmit-only operation available
Communication mode selectable to full-duplex or transmit-only
RSPCK polarity switching
RSPCK phase switching.
Data format
Bit rate
In master mode, the on-chip baud rate generator generates RSPCK by frequency-dividing PCLKA (the
division ratio ranges from divided by 2 to divided by 4096)
In slave mode, the minimum PCLKA clock divided by 4 can be input as RSPCK (PCLKA divided by 4 is
the maximum RSPCK frequency)
Width at high level: 2 PCLKA cycles; width at low level: 2 PCLKA cycles.
Buffer configuration
Double buffer configuration for the transmit and receive buffers
128 bits for the transmit and receive buffers.
Error detection
SSL control function
Control in master transfer
Transfers of up to eight commands each can be executed sequentially in looped execution
For each command, the following can be set:
SSL signal value, bit rate, RSPCK polarity and phase, transfer data length, MSB- or LSB-first, burst,
RSPCK delay, SSL negation delay, and next-access delay
Transfers can be initiated by writing to the transmit buffer
MOSI signal value specifiable in SSL negation
RSPCK auto-stop function.
Interrupt sources
Interrupt sources:
Receive buffer full interrupt
Transmit buffer empty interrupt
SPI error interrupt (mode fault, overrun, parity error)
SPI idle interrupt (SPI idle)
Transmission-complete interrupt.
MSB-first or LSB-first selectable
Transfer bit length selectable to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits
128-bit transmit and receive buffers
Up to four frames transferrable in one round of transmission or reception (each frame consisting of up
to 32 bits)
Byte swap operating function.
Mode fault error detection
Underrun error detection
Overrun error detection*1
Parity error detection.
Four SSL pins (SSLn0 to SSLn3) for each channel
In single master mode, SSLn0 to SSLn3 pins are output
In multi-master mode, SSLn0 pin for input, and SSLn1 to SSLn3 pins either for output or unused
In slave mode, SSLn0 pin for input, and SSLn1 to SSLn3 pins unused
Controllable delay from SSL output assertion to RSPCK operation (RSPCK delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable delay from RSPCK stop to SSL output negation (SSL negation delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable wait for next-access SSL output assertion (next-access delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Function for changing SSL polarity.
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Table 36.1
36. Serial Peripheral Interface (SPI)
SPI specifications (2 of 2)
Parameter
Specifications
Event link function (output)
The following events can be output to the Event Link Controller (ELC):
Receive buffer full signal
Transmit buffer empty signal
Mode fault, underrun, overrun, or parity error signal
SPI idle signal
Transmission-complete signal.
Other functions
Switching between CMOS output and open-drain output
SPI initialization function
Loopback mode.
Module-stop function
Module-stop state can be set to reduce power consumption
In master reception, when the RSPCK auto-stop function is enabled, an overrun error does not occur because the transfer
clock is stopped on overrun error detection.
Bus interface
Note 1.
Module data bus
SPRX
SPTX
Internal
peripheral bus
SPBR
SPCR
SSLP
Baud rate
generator
SPPCR
SPSR
PCLKA
SPDR/SPDR_HA
SPSCR
Parity circuit
SPSSR
SPDCR
SPCKD
SSLND
SPND
Shift register
SPCR2
SPCMD
SPDCR2
Selector
Normal
Transmission/
reception controller
Event output
Clock
Loopback
MOSIn
Normal
Loopback
Loopback 2
MISOn
Normal
Master
Loopback 2
Slave
Master
SPIi_SPTI interrupt
Loopback
Loopback 2
SPIi_SPRI interrupt
Slave
SPIi_SPII interrupt
SPIi_SPEI interrupt
SSLn0
SPIi_SPTEND interrupt
SSLn1 to SSLn3
RSPCKn
SPCR:
SPI Control Register
SPCR2:
SPI Control Register 2
SSLP:
SPI Slave Select Polarity Register
SPPCR:
SPI Pin Control Register
SPSR:
SPI Status Register
SPDR/SPDR_HA:SPI Data Register
SPSCR:
SPI Sequence Control Register
SPSSR:
SPI Sequence Status Register
SPDCR:
SPI Data Control Register
SPCKD:
SPI Clock Delay Register
Figure 36.1
SSLND:
SPND:
SPCMD:
SPBR:
SPTX:
SPRX:
SPDCR2:
SPI Slave Select Negation Delay Register
SPI Next-Access Delay Register
SPI Command Registers 0 to 7 (eight registers)
SPI Bit Rate Register
SPI Transmit Buffer
SPI Receive Buffer
SPI Data Control Register 2
SPI block diagram
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36. Serial Peripheral Interface (SPI)
Table 36.2 lists the I/O pins used in the SPI. The SPI automatically switches the I/O direction of the SSLn0 pin. SSLn0 is
set as an output when SPI is a single master and as an input when SPI is a multi-master or a slave. The RSPCKn, MOSIn,
and MISOn pins are automatically set as inputs or outputs based on the master or slave setting and the level input on the
SSLn0 pin. For details, see section 36.3.2, Controlling the SPI Pins.
Table 36.2
SPI I/O pins
Channel
Pin name
I/O
Function
SPI0
RSPCKA
I/O
Clock input/output
MOSIA
I/O
Master transmit data input/output
MISOA
I/O
Slave transmit data input/output
SSLA0
I/O
Slave selection input/output
SSLA1
Output
Slave selection output
SSLA2
Output
Slave selection output
SSLA3
Output
Slave selection output
RSPCKB
I/O
Clock input/output
MOSIB
I/O
Master transmit data input/output
MISOB
I/O
Slave transmit data input/output
SSLB0
I/O
Slave selection input/output
SSLB1
Output
Slave selection output
SSLB2
Output
Slave selection output
SSLB3
Output
Slave selection output
SPI1
36.2
Register Descriptions
36.2.1
SPI Control Register (SPCR)
Address(es): SPI0.SPCR 4007 2000h, SPI1.SPCR 4007 2100h
b7
Value after reset:
b6
SPRIE
SPE
0
0
b5
b4
b3
b2
b1
SPTIE SPEIE MSTR MODF TXMD
EN
0
0
0
0
0
b0
SPMS
0
Bit
Symbol
Bit name
Description
R/W
b0
SPMS
SPI Mode Select
0: Select SPI operation (4-wire method)
1: Select clock synchronous operation (3-wire method).
R/W
b1
TXMD
Communications Operating Mode
Select
0: Select full-duplex synchronous serial communications
1: Select serial communications with transmit-only.
R/W
b2
MODFEN Mode Fault Error Detection Enable
0: Disable detection of mode fault errors
1: Enable detection of mode fault errors.
R/W
b3
MSTR
SPI Master/Slave Mode Select
0: Select slave mode
1: Select master mode.
R/W
b4
SPEIE
SPI Error Interrupt Enable
0: Disable SPI error interrupt requests
1: Enable SPI error interrupt requests.
R/W
b5
SPTIE
Transmit Buffer Empty Interrupt
Enable
0: Disable transmit buffer empty interrupt requests
1: Enable transmit buffer empty interrupt requests.
R/W
b6
SPE
SPI Function Enable
0: Disable SPI function
1: Enable SPI function.
R/W
b7
SPRIE
SPI Receive Buffer Full Interrupt
Enable
0: Disable SPI receive buffer full interrupt requests
1: Enable SPI receive buffer full interrupt requests.
R/W
If the SPCR.MSTR, SPCR.MODFEN, or SPCR.TXMD bit is changed while the SPCR.SPE bit is 1, do not perform
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36. Serial Peripheral Interface (SPI)
subsequent operations.
SPMS bit (SPI Mode Select)
The SPMS bit selects the SPI operation (4-wire method) or clock synchronous operation (3-wire method).
The SSLn0 to SSLn3 pins are not used in clock synchronous operation. The RSPCKn, MOSIn, and MISOn pins handle
the communication. For clock synchronous operation in master mode (SPCR.MSTR = 1), the SPCMDm.CPHA bit can
be set to either 0 or 1. For clock synchronous operation in slave mode (SPCR.MSTR = 0), always set the CPHA bit to 1.
Do not perform the operations if the CPHA bit is set to 0 for the clock synchronous operation in slave mode
(SPCR.MSTR = 0).
TXMD bit (Communications Operating Mode Select)
The TXMD bit selects full-duplex synchronous serial communications or transmit-only operations. When this bit is set to
1, SPI only performs transmit operations but not receive operations (see section 36.3.6, Data Transfer Modes), and the
receive buffer full interrupt requests cannot be used.
MODFEN bit (Mode Fault Error Detection Enable)
The MODFEN bit enables or disables the detection of mode fault errors (see section 36.3.8, Error Detection). In addition,
the SPI determines the I/O direction of the SSLn0 to SSLn3 pins based on a combination of the MODFEN and MSTR
bits (see section 36.3.2, Controlling the SPI Pins).
MSTR bit (SPI Master/Slave Mode Select)
The MSTR bit selects master or slave mode for SPI. Based on the MSTR bit settings, SPI determines the direction of the
RSPCKn, MOSIn, MISOn, and SSLn0 to SSLn3 pins.
SPEIE bit (SPI Error Interrupt Enable)
The SPEIE bit enables or disables the generation of SPI error interrupt requests when one of the following occurs:
The SPI detects a mode fault error or underrun error and sets the SPSR.MODF flag to 1
The SPI detects an overrun error and sets the SPSR.OVRF flag to 1
The SPI detects a parity error and sets the SPSR.PERF flag to 1.
For details, see section 36.3.8, Error Detection.
SPTIE bit (Transmit Buffer Empty Interrupt Enable)
The SPTIE bit enables or disables the generation of transmit buffer empty interrupt requests when the SPI detects that the
transmit buffer is empty. To generate a transmit buffer empty interrupt request when transmission starts, set the SPE and
SPTIE bits to 1 at the same time or set the SPE bit to 1 after setting the SPTIE bit to 1.
When the SPTIE bit is 1, transmit buffer interrupts are generated even when the SPI function is disabled (when the SPE
bit is changed to 0).
SPE bit (SPI Function Enable)
The SPE bit enables or disables the SPI function. The SPE bit cannot be set to 1 when the SPSR.MODF flag is 1. For
details, see section 36.3.8, Error Detection.
Setting the SPE bit to 0 disables the SPI function and initializes a part of the module function. For details, see section
36.3.9, Initializing the SPI. In addition, a transmit buffer empty interrupt request is generated when the SPE bit is
changed from 0 to 1 or from 1 to 0.
SPRIE bit (SPI Receive Buffer Full Interrupt Enable)
The SPRIE bit enables or disables the generation of an SPI receive buffer full interrupt request when the SPI detects a
receive buffer full write after completion of a serial transfer.
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36.2.2
36. Serial Peripheral Interface (SPI)
SPI Slave Select Polarity Register (SSLP)
Address(es): SPI0.SSLP 4007 2001h, SPI1.SSLP 4007 2101h
Value after reset:
b7
b6
b5
b4
—
—
—
—
0
0
0
0
b3
b2
b1
b0
SSL3P SSL2P SSL1P SSL0P
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSL0P
SSL0 Signal Polarity Setting
0: Set SSL0 signal to active-low
1: Set SSL0 signal to active-high.
R/W
b1
SSL1P
SSL1 Signal Polarity Setting
0: Set SSL1 signal to active-low
1: Set SSL1 signal to active-high.
R/W
b2
SSL2P
SSL2 Signal Polarity Setting
0: Set SSL2 signal to active-low
1: Set SSL2 signal to active-high.
R/W
b3
SSL3P
SSL3 Signal Polarity Setting
0: Set SSL3 signal to active-low
1: Set SSL3 signal to active-high.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the contents of SSLP are changed while the SPCR.SPE bit is 1, do not perform subsequent operations.
36.2.3
SPI Pin Control Register (SPPCR)
Address(es): SPI0.SPPCR 4007 2002h, SPI1.SPPCR 4007 2102h
Value after reset:
b7
b6
—
—
0
0
b5
b4
MOIFE MOIFV
0
b3
b2
b1
b0
—
—
SPLP2
SPLP
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SPLP
SPI Loopback
0: Normal mode
1: Loopback mode (data is inverted for transmission).
R/W
b1
SPLP2
SPI Loopback 2
0: Normal mode
1: Loopback mode (data is not inverted for transmission).
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
MOIFV
MOSI Idle Fixed Value
0: Set level output on MOSIn pin during MOSI idling to correspond to
low
1: Set level output on MOSIn pin during MOSI idling to correspond to
high.
R/W
b5
MOIFE
MOSI Idle Value Fixing
Enable
0: Set MOSI output value to equal final data from previous transfer
1: Set MOSI output value to equal value set in the MOIFV bit.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the contents of SPPCR are changed while the SPCR.SPE bit is 1, do not perform subsequent operations.
SPLP bit (SPI Loopback)
The SPLP bit selects the mode of the SPI pins. When this bit is set to 1, SPI shuts off the path between the MISOn pin
and the shift register if the SPCR.MSTR bit is 1, and between the MOSIn pin and the shift register if the SPCR.MSTR bit
is 0. SPI then connects the input path and output path for the shift register (loopback mode).
SPLP2 bit (SPI Loopback 2)
The SPLP2 bit selects the mode of the SPI pins. When this bit is set to 1, SPI shuts off the path between the MISOn pin
and the shift register if the SPCR.MSTR bit is 1, and between the MOSIn pin and the shift register if the SPCR.MSTR bit
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36. Serial Peripheral Interface (SPI)
is 0. SPI then connects the input path and the output path for the shift register (loopback mode).
MOIFV bit (MOSI Idle Fixed Value)
If the MOIFE bit is 1 in master mode, the MOIFV bit determines the MOSIn pin output value during the SSL negation
period, including the SSL retention period during a burst transfer.
MOIFE bit (MOSI Idle Value Fixing Enable)
The MOIFE bit fixes the MOSIn output value when SPI is in master mode and in an SSL negation period, including the
SSL retention period during a burst transfer. When the MOIFE bit is 0, the SPI outputs the last data from the previous
serial transfer during the SSL negation period to the MOSIn pin. When the MOIFE bit is 1, the SPI outputs the fixed
value set in the MOIFV bit to the MOSIn pin.
36.2.4
SPI Status Register (SPSR)
Address(es): SPI0.SPSR 4007 2003h, SPI1.SPSR 4007 2103h
b7
b6
SPRF
—
0
0
Value after reset:
b5
b4
SPTEF UDRF
1
b3
PERF
0
b2
b1
MODF IDLNF
0
0
0
b0
OVRF
0
Bit
Symbol
Bit name
Description
R/W
b0
OVRF
Overrun Error Flag
0: No overrun error occurred
1: Overrun error occurred.
R/(W)*1
b1
IDLNF
SPI Idle Flag
0: SPI is in the idle state
1: SPI is in the transfer state.
R
b2
MODF
Mode Fault Error Flag
0: No mode fault or underrun error occurred
1: Mode fault error or underrun error occurred.
R/(W)*1
b3
PERF
Parity Error Flag
0: No parity error occurred
1: Parity error occurred.
R/(W)*1
b4
UDRF
Underrun Error Flag
0: Mode fault error occurred (MODF = 1)
1: Underrun error occurred (MODF = 1).
This bit is invalid when MODF flag is 0.
R/W*1,*2
b5
SPTEF
SPI Transmit Buffer Empty Flag
0: Data is in the transmit buffer
1: No data is in the transmit buffer.
R/(W)*3
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
SPRF
SPI Receive Buffer Full Flag
0: No valid data is in SPDR/SPDR_HA
1: Valid data is in SPDR/SPDR_HA.
R/(W)*3
Note 1.
Note 2.
Note 3.
Only 0 can be written to clear the flag after reading 1.
The UDRF flag clears at the same time that software clears the MODF flag.
The write value should be 1.
OVRF flag (Overrun Error Flag)
The OVRF flag indicates the occurrence of an overrun error. In master mode (SPCR.MSTR bit = 1), when the RSPCK
clock auto-stop function is enabled (SPCR2.SCKASE bit = 1), overrun errors do not occur. This flag does not set to 1.
For details, see section 36.3.8.1, Overrun errors.
[Setting condition]
When the next serial transfer ends while the SPCR.TXMD bit is 0 and the receive buffer is full.
[Clearing condition]
When 0 is written to the OVRF flag after the OVRF flag is confirmed to be 1 by a read of SPSR.
IDLNF flag (SPI Idle Flag)
The IDLNF flag indicates the transfer status of the SPI.
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36. Serial Peripheral Interface (SPI)
[Setting conditions]
Master mode
When conditions 1. and 2. in the master mode, in the clearing conditions, are not satisfied.
Slave mode
When the SPCR.SPE bit is 1, enabling the SPI function.
[Clearing conditions]
Master mode
When condition 1. OR conditions 2., 3., and 4. are satisfied.
1. The SPCR.SPE bit is 0, indicating that the SPI is initialized.
2. The transmit buffer (SPTX) is empty, indicating that data for the next transfer is not set.
3. The SPSSR.SPCP[2:0] bits are 000b, indicating the beginning of sequence control.
4. The SPI internal sequencer enters the idle state, indicating that the operations up to the next-access delay are
complete.
Slave mode
When condition 1. is satisfied.
MODF flag (Mode Fault Error Flag)
The MODF flag indicates the occurrence of a mode fault error or an underrun error. Use the UDRF flag to identify which
error occurred.
[Setting conditions]
Multi-master mode
When the input level of the SSLni pin changes to an active level while the SPCR.MSTR bit is 1 (master mode) and
the SPCR.MODFEN bit is 1 (mode fault error detection is enabled). The SPI detects a mode fault error.
Slave mode
When condition 1. OR 2. is satisfied.
1. The SSLni pin is negated before the RSPCK cycle necessary for data transfer ends while the SPCR.MSTR bit is 0
(slave mode) and the SPCR.MODFEN bit is 1 (mode fault error detection is enabled). The SPI detects a mode fault
error.
2. The serial transfer begins while the SPCR.MSTR bit is 0 (slave mode), the SPCR.SPE bit is 1, and the transmission
data is not prepared. The SPI detects an underrun error.
The active level of the SSLni signal is determined by the SSLP.SSLiP bit (SSLi signal polarity setting bit).
[Clearing condition]
When 0 is written to the MODF flag after the MODF flag is confirmed to be 1 by a read of SPSR.
PERF flag (Parity Error Flag)
The PERF flag indicates the occurrence of a parity error.
[Setting condition]
When a serial transfer ends while the SPCR.TXMD bit is 0 and the SPCR2.SPPE bit is 1. The SPI detects a parity
error.
[Clearing condition]
When 0 is written to the PERF flag after the PERF flag is confirmed to be 1 by a read of SPSR.
UDRF flag (Underrun Error Flag)
The UDRF flag indicates the occurrence of an underrun error.
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36. Serial Peripheral Interface (SPI)
[Setting condition]
When the serial transfer begins while the SPCR.MSTR bit is 0 (slave mode), the SPCR.SPE bit is 1, and the
transmission data is not prepared. The SPI detects an underrun error.
[Clearing condition]
When 0 is written to the UDRF flag after the UDRF flag is confirmed to be 1 by a read of SPSR.
SPTEF flag (SPI Transmit Buffer Empty Flag)
The SPTEF flag indicates the status of the transmit buffer for the SPI Data Register (SPDR/SPDR_HA).
[Setting conditions]
When condition 1. OR 2. is satisfied.
1. The SPCR.SPE bit is 0 (the SPI is initialized).
2. Transmit data was transferred from the transmit buffer to the shift register.
[Clearing condition]
When data written to SPDR/SPDR_HA equals the number of frames set in the SPFC[1:0] bits in the SPI Data
Control Register (SPDCR).
Data can only be written to SPDR/SPDR_HA when the SPTEF flag is 1. If data is written to the transmit buffer of
SPDR/SPDR_HA when the SPTEF flag is 0, the data in the transmit buffer is not updated.
SPRF flag (SPI Receive Buffer Full Flag)
The SPRF flag indicates the status of the receive buffer for the SPI Data Register (SPDR/SPDR_HA).
[Setting condition]
When a serial transfer ends while the Communication Operating Mode Select bit (TXMD) in the SPI Control
Register (SPCR) is 0, the SPRF flag is 0, and the SPI transfers the receive data from the shift register to
SPDR/SPDR_HA. However, when the OVRF flag is 1, the SPRF flag does not change from 0 into 1.
[Clearing condition]
When received data is read from the SPDR/SPDR_HA.
36.2.5
SPI Data Register (SPDR/SPDR_HA)
Address(es): SPI0.SPDR 4007 2004h, SPI1.SPDR 4007 2104h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address(es): SPI0.SPDR_HA 4007 2004h, SPI1.SPDR_HA 4007 2104h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPDR/SPDR_HA is the interface with the buffers that hold data for transmission and reception by the SPI. When
accessing this register in words (the SPLW bit is 1), access SPDR. When accessing it in halfwords (the SPLW bit is 0),
access SPDR_HA.
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36. Serial Peripheral Interface (SPI)
The transmit buffer (SPTX) and receive buffer (SPRX) are independent but are both mapped to SPDR/SPDR_HA.
Figure 36.2 shows the configuration.
SPI Data Register
*1
SPDR/SPDR_HA
Internal peripheral bus
Transmit buffer
SPTX0
SPTX1
SPTX2
SPTX3
*1
Shift
register
Receive buffer
*1
SPRX0
SPRX1
SPRX2
SPRX3
Transmit data
Receive data
*1
Note 1. The destination buffer and stage for access is automatically switched by the hardware.
Figure 36.2
Configuration of SPDR/SPDR_HA
The transmit and receive buffers each have four stages. The number of stages to be used is selectable in the number of
frames specification bits in the SPI Data Control Register (SPDCR.SPFC[1:0]). The eight stages of the buffer are all
mapped to the single address of SPDR/SPDR_HA.
Data written to SPDR/SPDR_HA is written to a transmit-buffer stage (SPTXn) (n = 0 to 3) and then transmitted from the
buffer. The receive buffer holds the received data on the completion of reception. The receive buffer is not updated if an
overrun is generated.
Additionally, if the data length is other than 32 bits, bits not referred to in SPTXn (n = 0 to 3) are stored in the associated
bits in SPRXn (n = 0 to 3). For example, if the data length is 9 bits, the received data is stored in the SPRXn[8:0] bits, and
the SPTXn[31:9] bits are stored in the SPRXn[31:9] bits.
(1)
Bus interface
SPDR/SPDR_HA is an interface with 32-bit wide transmit and receive buffers, each of which has four stages, for a total
of 32 bytes. The 32 bytes are mapped to the 4-byte address space for SPDR/SPDR_HA. The unit of access for
SPDR/SPDR_HA is selected by the SPI Word Access/Halfword Access Specification bit in the SPI Data Control
Register (SPDCR.SPLW). SPDR can also be accessed with the access size specified by the SPI Byte Access bit in the
SPI Data Control Register (SPDCR.SPBYT).
Flush the transmission data at the LSB end of the register, and store the received data at the LSB end.
This section describes the operations involved in writing to and reading from SPDR/SPDR_HA.
(a)
Writing
Data written to SPDR/SPDR_HA is written to a transmit buffer (SPTXn). This is not affected by the value of the
SPDCR.SPRDTD bit, unlike when reading from SPDR/SPDR_HA. The transmit buffer includes a transmit buffer write
pointer that is automatically updated to reference the next stage each time data is written to SPDR/SPDR_HA.
Figure 36.3 shows the configuration of the bus interface with the transmit buffer when writing to SPDR.
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36. Serial Peripheral Interface (SPI)
SPDR/SPDR_HA
S5D5 User’s Manual
SPTX0
SPTX1
SPTX2
SPTX3
Write access + setting in the SPFC[1:0] bits
Figure 36.3
Configuration of SPDR/SPDR_HA for write access
The sequence for switching the transmit buffer write pointer differs with the setting of the number of frames specification
bits in the SPI Data Control Register (SPDCR.SPFC[1:0]). The relationship of the SPFC[1:0] setting and the sequence of
pointer switching among SPTX0 to SPTX3 is as follows:
When SPFC[1:0] = 00b: SPTX0 → SPTX0 → SPTX0 → …
When SPFC[1:0] = 01b: SPTX0 → SPTX1 → SPTX0 → SPTX1 → …
When SPFC[1:0] = 10b: SPTX0 → SPTX1 → SPTX2 → SPTX0 → SPTX1 → …
When SPFC[1:0] = 11b: SPTX0 → SPTX1 → SPTX2 → SPTX3 → SPTX0 → SPTX1 → …
When 1 is written to the SPI Function Enable bit in the SPI Control Register (SPCR.SPE) while the value of the bit is 0,
SPTX0 is the destination the next time writing proceeds.
When writing to the transmit buffer (SPTXn) after generating the transmit buffer empty interrupt (when SPSR.SPTEF is
1), write the number of frames set in SPFC[1:0] in the SPI Data Control Register (SPDCR). Even when the specified
number of frames is written to the transmit buffer (SPTXn), the value of the buffer is not updated after completion of the
writing and before the next transmit buffer empty interrupt is generated (when SPTEF is 0).
(b)
Reading
SPDR/SPDR_HA can be accessed to read the value of a receive buffer (SPRXn) or a transmit buffer (SPTXn). The
setting in the SPI Receive/Transmit Data Select bit in the SPI Data Control Register (SPDCR.SPRDTD) selects whether
the reading is of the receive or transmit buffer. The sequence of reading the SPDR/SPDR_HA register is controlled by
the independent receive buffer and transmit buffer read pointers.
Figure 36.4 shows the configuration of the bus interface with the receive and transmit buffers for a read from
SPDR/SPDR_HA.
SPRX0
SPRX1
0
SPDR/SPDR_HA
SPRX2
SPRX3
Read access to receive buffer +
setting in the SPFC[1:0] bits
SPTX0
SPTX1
1
SPTX2
SPTX3
SPRDTD
Figure 36.4
Read access to transmit buffer +
setting in the SPFC[1:0] bits
Configuration of SPDR/SPDR_HA for read access
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36. Serial Peripheral Interface (SPI)
Reading the receive buffer switches the receive buffer read pointer to the next buffer automatically. The switching
sequence for the receive buffer read pointer is the same as that for the transmit buffer write pointer. However, when 1 is
written to the SPI function enable bit in the SPI Control Register (SPCR.SPE) while the value of the bit is 1, SPRX0 is
referenced by the buffer read pointer the next time that the reading proceeds.
The transmit buffer read pointer is updated when writing to SPDR/SPDR_HA, and is not updated when reading from the
transmit buffer. When reading from the transmit buffer, the value most recently written to SPDR/SPDR_HA is read.
However, after generation of the transmit buffer empty interrupt, the values read from the transmit buffer are all 0s in the
interval after the completion of writing the number of frames of data specified in the SPDCR.SPFC[1:0] bits and before
the generation of the next buffer empty interrupt (when SPTEF is 0).
36.2.6
SPI Sequence Control Register (SPSCR)
Address(es): SPI0.SPSCR 4007 2008h, SPI1.SPSCR 4007 2108h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SPSLN[2:0]
0
0
Bit
Symbol
Bit name
Description
b2 to b0
SPSLN[2:0]
SPI Sequence Length
Specification
b2
b7 to b3
—
Reserved
0
b0 Sequence Length
R/W
Referenced SPCMD0 to SPCMD7 (No.)
0 0 0: 1
0→0→…
0 0 1: 2
0→1→0→…
0 1 0: 3
0→1→2→0→…
0 1 1: 4
0→1→2→3→0→…
1 0 0: 5
0→1→2→3→4→0→…
1 0 1: 6
0→1→2→3→4→5→0→…
1 1 0: 7
0→1→2→3→4→5→6→0→…
1 1 1: 8
0→1→2→3→4→5→6→7→0→…
The sequence length that is set in these bits determines the order in
which the SPCMD0 to SPCMD07 registers are referenced. The setting
defines the relationship between the sequence length and the
SPCMD0 to SPCMD7 registers referenced by the SPI. In slave mode,
the SPI references SPCMD0.
These bits are read as 0. The write value should be 0.
R/W
R/W
SPSCR specifies the sequence length when the SPI operates in master mode. Before changing the SPSCR.SPSLN[2:0]
bits while both the SPCR.MSTR and SPCR.SPE bits are 1, always check that the SPSR.IDLNF flag is 0.
SPSLN[2:0] bits (SPI Sequence Length Specification)
The SPSLN[2:0] bits specify the sequence length when SPI in master mode performs sequential operations. SPI in
master mode changes the SPCMD0 to SPCMD7 registers to be referenced, and the order in which they are referenced is
based on this sequence length setting. In slave mode, SPCMD0 is referenced.
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36.2.7
36. Serial Peripheral Interface (SPI)
SPI Sequence Status Register (SPSSR)
Address(es): SPI0.SPSSR 4007 2009h, SPI1.SPSSR 4007 2109h
b7
b6
—
Value after reset:
0
b5
b4
SPECM[2:0]
0
0
b3
b2
—
0
0
b1
b0
SPCP[2:0]
0
0
0
Bit
Symbol
Bit name
Description
b2 to b0
SPCP[2:0]
SPI Command Pointer
b3
—
Reserved
This bit is read as 0.
R
b6 to b4
SPECM[2:0]
SPI Error Command
b6
R
b7
—
Reserved
This bit is read as 0.
b2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
R
b0
0: SPCMD0
1: SPCMD1
0: SPCMD2
1: SPCMD3
0: SPCMD4
1: SPCMD5
0: SPCMD6
1: SPCMD7.
b4
0: SPCMD0
1: SPCMD1
0: SPCMD2
1: SPCMD3
0: SPCMD4
1: SPCMD5
0: SPCMD6
1: SPCMD7.
R
SPSSR indicates the sequence control status when the SPI operates in master mode. Any writes to SPSSR are ignored.
SPCP[2:0] bits (SPI Command Pointer)
The SPCP[2:0] bits indicate the SPCMDm register that is referenced to by the pointer during sequence control by the
SPI. For the SPI sequence control, see section 36.3.10.1, Master mode operation.
SPECM[2:0] bits (SPI Error Command)
The SPECM[2:0] bits indicate the SPCMDm register that is specified in the SPCP[2:0] bits when an error is detected
during sequence control by the SPI. The SPI updates the SPECM[2:0] bits only when an error is detected. If both the
SPSR.OVRF and SPSR.MODF flags are 0 and there is no error, the values of the SPECM[2:0] bits have no meaning.
For the SPI error detection function, see section 36.3.8, Error Detection. For the SPI sequence control, see section
36.3.10.1, Master mode operation.
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36.2.8
36. Serial Peripheral Interface (SPI)
SPI Bit Rate Register (SPBR)
Address(es): SPI0.SPBR 4007 200Ah, SPI1.SPBR 4007 210Ah
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
SPBR sets the bit rate in master mode. If the contents of SPBR are changed while both the SPCR.MSTR and SPCR.SPE
bits are 1, do not perform subsequent operations.
When the SPI is used in slave mode, the bit rate depends on the bit rate of the input clock regardless of the settings in
SPBR and the SPCMDm.BRDV[1:0] bits (bit rate division setting). Use bit rates that satisfy the electrical characteristics.
The bit rate is determined by combinations of the SPBR and SPCMDm.BRDV[1:0] settings. The equation for calculating
the bit rate is as follows:
Bit rate =
f (PCLKA)
2 × (n + 1) × 2N
In the equation, n denotes an SPBR setting (0, 1, 2, …, 255), and N denotes a BRDV[1:0] setting (0, 1, 2, 3).
Table 36.3 lists examples of the relationship among the SPBR settings, the BRDV[1:0] settings, and bit rates.
Table 36.3
Relationship among SPBR settings, BRDV[1:0] settings, and bit rates
Bit rate
SPBR
(n)
BRDV[1:0]
bits (N)
Division
ratio
PCLKA =
32 MHz
PCLKA =
36 MHz
PCLKA =
40 MHz
PCLKA =
50 MHz
PCLKA =
60 MHz
PCLKA =
80 MHz
0
0
2
16.0 Mbps
18.0 Mbps
20.0 Mbps
25.0 Mbps
30.0 Mbps
Not supported
1
0
4
8.00 Mbps
9.00 Mbps
10.0 Mbps
12.5 Mbps
15.0 Mbps
20.0 Mbps
25.0 Mbps
30.0 Mbps
2
0
6
5.33 Mbps
6.00 Mbps
6.67 Mbps
8.33 Mbps
10.0 Mbps
13.3 Mbps
16.7 Mbps
20.0 Mbps
3
0
8
4.00 Mbps
4.50 Mbps
5.00 Mbps
6.25 Mbps
7.50Mbps
10.0 Mbps
12.5 Mbps
15.0 Mbps
4
0
10
3.20 Mbps
3.60 Mbps
4.00 Mbps
5.00 Mbps
6.00 Mbps
8.00 Mbps
10.0 Mbps
12.0 Mbps
5
0
12
2.67 Mbps
3.00 Mbps
3.33 Mbps
4.16 Mbps
5.00 Mbps
6.67 Mbps
8.33 Mbps
10.0 Mbps
5
1
24
1.33 Mbps
1.50 Mbps
1.67 Mbps
2.08 Mbps
2.50 Mbps
3.33 Mbps
4.17 Mbps
5.00 Mbps
5
2
48
667 kbps
750 kbps
833 kbps
1.04 Mbps
1.25 Mbps
1.67 Mbps
2.08 Mbps
2.50 Mbps
5
3
96
333 kbps
375 kbps
417 kbps
521 kbps
625 kbps
833 kbps
1.04 Mbps
1.25 Mbps
255
3
4096
7.81 kbps
8.80 kbps
9.78 kbps
12.2 kbps
14.6 kbps
19.5 kbps
24.4 kbps
29.3 kbps
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PCLKA =
100 MHz
PCLKA =
120 MHz
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36.2.9
36. Serial Peripheral Interface (SPI)
SPI Data Control Register (SPDCR)
Address(es): SPI0.SPDCR 4007 200Bh, SPI1.SPDCR 4007 210Bh
b7
—
Value after reset:
b6
b5
b4
SPBYT SPLW SPRDT
D
0
0
0
0
b3
b2
b1
b0
—
—
SPFC[1:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
SPFC[1:0]
Number of Frames
Specification
b1 b0
R/W
0
0
1
1
0: 1 frame
1: 2 frames
0: 3 frames
1: 4 frames.
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
SPRDTD
SPI Receive/Transmit Data
Select
0: Read SPDR/SPDR_HA values from receive buffer
1: Read SPDR/SPDR_HA values from transmit buffer, but only if
the transmit buffer is empty.
R/W
b5
SPLW
SPI Word Access/Halfword
Access Specification
0: Set SPDR_HA to valid for halfword access
1: Set SPDR to valid for word access.
R/W
b6
SPBYT
SPI Byte Access Specification
0: SPDR is accessed in halfword or word (SPLW is valid)
1: SPDR is accessed in byte (SPLW is invalid).
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Up to four frames can be transmitted or received in one round of transmission or reception. The amount of data in each
transfer is controlled by the combination of the SPCMDm.SPB[3:0] bits, the SPSCR.SPSLN[2:0] bits, and the
SPDCR.SPFC[1:0] bits.
When changing the SPDCR.SPFC[1:0] bits while the SPCR.SPE bit is 1, always check that the SPSR.IDLNF flag is 0.
SPFC[1:0] bits (Number of Frames Specification)
The SPFC[1:0] bits specify the number of frames that can be stored in SPDR/SPDR_HA per transfer activation. Up to
four frames can be transmitted or received in one round of transmission or reception.
When the number of transmission data frames specified in the SPFC[1:0] bits is written to the SPDR/SPDR_HA register,
SPI clears the SPSR.SPTEF flag to 0 and begins transmitting. After that, when the number of transmission data frames
specified in the SPFC[1:0] bits is transmitted to the shift register, the SPI generates the transmit buffer empty interrupt
(SPSR.SPTEF is set to 1).
When the number of data frames specified in the SPFC[1:0] bits is received, the SPI generates the receive buffer full
interrupt (SPSR.SPRF is set to 1).
Table 36.4
Settable combinations of the SPSLN[2:0] and SPFC[1:0] bits (1 of 2)
Setting
SPSLN[2:0]
SPFC[1:0]
Number of frames in
a single sequence
Number of frames at which transmission or receive buffer
is filled
1-1
000b
00b
1
1
1-2
000b
01b
2
2
1-3
000b
10b
3
3
1-4
000b
11b
4
4
2-1
001b
01b
2
2
2-2
001b
11b
4
4
3
010b
10b
3
3
4
011b
11b
4
4
5
100b
00b
5
1
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Table 36.4
36. Serial Peripheral Interface (SPI)
Settable combinations of the SPSLN[2:0] and SPFC[1:0] bits (2 of 2)
Setting
SPSLN[2:0]
SPFC[1:0]
Number of frames in
a single sequence
Number of frames at which transmission or receive buffer
is filled
6
101b
00b
6
1
7
110b
00b
7
1
8
111b
00b
8
1
SPRDTD bit (SPI Receive/Transmit Data Select)
The SPRDTD bit selects whether the SPDR/SPDR_HA reads values from the receive buffer or from the transmit buffer.
If reading the transmit buffer, the value written to SPDR/SPDR_HA register immediately beforehand is read. Read the
transmit buffer before the writing of the number of frames set in the SPFC[1:0] bits is finished and after the generation of
the transmit buffer empty interrupt (when SPSR.SPTEF is 1).
For details, see section 36.2.5, SPI Data Register (SPDR/SPDR_HA).
SPLW bit (SPI Word Access/Halfword Access Specification)
The SPLW bit specifies the access width for SPDR. Access to SPDR_HA in halfwords is valid when the SPLW bit is 0
and access to SPDR in words is valid when the SPLW bit is 1. Also, when this bit is 0, set the SPCMDm.SPB[3:0] bits
(SPI data length setting) from 8 to 16 bits. Do not perform any operations when 20, 24, or 32 bits is specified.
SPBYT bit (SPI Byte Access Specification)
This bit is used to set the data width of access to the SPI Data Register (SPDR). When SPBYT = 0, use word or half word
access to SPDR. When SPBYT = 1 (in that case, SPLW is invalid), use byte access to SPDR.
When SPBYT = 1, set the SPI Data Length bits (SPB[3:0]) in the SPI Command Register n (SPCMDn) to 0 bits. If
SPB[3:0] are set to 9 to 16, 20, 24, or 32 bits, subsequent operation is not guaranteed.
36.2.10
SPI Clock Delay Register (SPCKD)
Address(es): SPI0.SPCKD 4007 200Ch, SPI1.SPCKD 4007 210Ch
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SCKDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SCKDL[2:0]
RSPCK Delay Setting
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK
1: 2 RSPCK
0: 3 RSPCK
1: 4 RSPCK
0: 5 RSPCK
1: 6 RSPCK
0: 7 RSPCK
1: 8 RSPCK.
R/W
SPCKD specifies the RSPCK delay, the period from the beginning of SSLni signal assertion to RSPCK oscillation, when
the SPCMDm.SCKDEN bit is 1. If the contents of SPCKD are changed while both the SPCR.MSTR and SPCR.SPE bits
are 1, do not perform subsequent operations.
SCKDL[2:0] bits (RSPCK Delay Setting)
The SCKDL[2:0] bits specify an RSPCK delay value when the SPCMDm.SCKDEN bit is 1. When using the SPI in slave
mode, set the SCKDL[2:0] bits to 000b.
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36.2.11
36. Serial Peripheral Interface (SPI)
SPI Slave Select Negation Delay Register (SSLND)
Address(es): SPI0.SSLND 4007 200Dh, SPI1.SSLND 4007 210Dh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SLNDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SLNDL[2:0]
SSL Negation Delay Setting
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK
1: 2 RSPCK
0: 3 RSPCK
1: 4 RSPCK
0: 5 RSPCK
1: 6 RSPCK
0: 7 RSPCK
1: 8 RSPCK.
R/W
SSLND specifies the SSL negation delay, the period from the transmission of a final RSPCK edge to the negation of the
SSLni signal during a serial transfer by the SPI in master mode. If the contents of SSLND are changed while both the
SPCR.MSTR and SPCR.SPE bits are 1, do not perform subsequent operations.
SLNDL[2:0] bits (SSL Negation Delay Setting)
The SLNDL[2:0] bits specify an SSL negation delay value when the SPI is in master mode. When using the SPI in slave
mode, set the SLNDL[2:0] bits to 000b.
36.2.12
SPI Next-Access Delay Register (SPND)
Address(es): SPI0.SPND 4007 200Eh, SPI1.SPND 4007 210Eh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SPNDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SPNDL[2:0]
SPI Next-Access Delay Setting
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK + 2 PCLKA
1: 2 RSPCK + 2 PCLKA
0: 3 RSPCK + 2 PCLKA
1: 4 RSPCK + 2 PCLKA
0: 5 RSPCK + 2 PCLKA
1: 6 RSPCK + 2 PCLKA
0: 7 RSPCK + 2 PCLKA
1: 8 RSPCK + 2 PCLKA.
R/W
SPND specifies the next-access delay, the non-active period of the SSLni signal after termination of a serial transfer,
when the SPCMDm.SPNDEN bit is 1. If the contents of SPND are changed while both the SPCR.MSTR and SPCR.SPE
bits are 1, do not perform subsequent operations.
SPNDL[2:0] bits (SPI Next-Access Delay Setting)
The SPNDL[2:0] bits specify a next-access delay when the SPCMDm.SPNDEN bit is 1. When using the SPI in slave
mode, set the SPNDL[2:0] bits to 000b.
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36.2.13
36. Serial Peripheral Interface (SPI)
SPI Control Register 2 (SPCR2)
Address(es): SPI0.SPCR2 4007 200Fh, SPI1.SPCR2 4007 210Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
SCKAS
E
PTE
SPIIE
SPOE
SPPE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SPPE
Parity Enable
0: Do not add parity bit to transmit data and do not check parity bit of
receive data
1: When SPCR.TXMD = 0: Add parity bit to transmit data and check
parity bit of receive data
When SPCR.TXMD = 1: Add parity bit to transmit data but do not
check parity bit of receive data.
R/W
b1
SPOE
Parity Mode
0: Select even parity for transmission and reception
1: Select odd parity for transmission and reception.
R/W
b2
SPIIE
SPI Idle Interrupt Enable
0: Disable idle interrupt requests
1: Enable idle interrupt requests.
R/W
b3
PTE
Parity Self-Testing
0: Disable self-diagnosis function of the parity circuit
1: Enable self-diagnosis function of the parity circuit.
R/W
b4
SCKASE
RSPCK Auto-Stop Function
Enable
0: Disable RSPCK auto-stop function
1: Enable RSPCK auto-stop function.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the SPPE, SPOE, or SCKASE bit in SPCR2 is changed while the SPCR.SPE bit is 1, do not perform subsequent
operations.
SPPE bit (Parity Enable)
The SPPE bit enables or disables the parity function.
When the SPCR.TXMD bit is 0 and this bit is 1, the parity bit is added to transmit data and parity checking is performed
for receive data.
When the SPCR.TXMD bit is 1 and this bit is 1, the parity bit is added to transmit data but parity checking is not
performed for receive data.
SPOE bit (Parity Mode)
The SPOE bit specifies odd or even parity.
When even parity is set, parity bit addition is performed so that the total number of 1-bits in the transmit or receive
character plus the parity bit is even. Similarly, when odd parity is set, parity bit addition is performed so that the total
number of 1-bits in the transmit or receive character plus the parity bit is odd.
The SPOE bit is only valid when the SPPE bit is 1.
SPIIE bit (SPI Idle Interrupt Enable)
The SPIIE bit enables or disables the generation of SPI idle interrupt requests when an idle state is detected in the SPI
and the SPSR.IDLNF flag clears to 0.
PTE bit (Parity Self-Testing)
The PTE bit enables self-diagnosis of the parity circuit to check whether the parity function is operating correctly.
SCKASE bit (RSPCK Auto-Stop Function Enable)
The SCKASE bit enables or disables the RSPCK auto-stop function. When this function is enabled, the RSPCK clock is
stopped before an overrun error occurs when data is received in master mode. For details, see section 36.3.8.1, Overrun
errors.
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36.2.14
36. Serial Peripheral Interface (SPI)
SPI Command Registers 0 to 7 (SPCMD0 to SPCMD7)
Address(es): SPI0.SPCMD0 4007 2010h, SPI0.SPCMD1 4007 2012h, SPI0.SPCMD2 4007 2014h, SPI0.SPCMD3 4007 2016h,
SPI0.SPCMD4 4007 2018h, SPI0.SPCMD5 4007 201Ah, SPI0.SPCMD6 4007 201Ch, SPI0.SPCMD7 4007 201Eh,
SPI1.SPCMD0 4007 2110h, SPI1.SPCMD1 4007 2112h, SPI1.SPCMD2 4007 2114h, SPI1.SPCMD3 4007 2116h,
SPI1.SPCMD4 4007 2118h, SPI1.SPCMD5 4007 211Ah, SPI1.SPCMD6 4007 211Ch, SPI1.SPCMD7 4007 211Eh
b15
b14
b13
b12
b11
b10
SCKDE SLNDE SPNDE LSBF
N
N
N
Value after reset:
0
0
0
0
b9
b8
SPB[3:0]
0
1
b7
b6
SSLKP
1
1
0
b5
b4
SSLA[2:0]
0
0
b3
b2
BRDV[1:0]
0
1
b1
b0
CPOL
CPHA
0
1
1
Bit
Symbol
Bit name
Description
R/W
b0
CPHA
RSPCK Phase Setting
0: Select data sampling on leading edge, data change on trailing
edge
1: Select data change on leading edge, data sampling on trailing
edge.
R/W
b1
CPOL
RSPCK Polarity Setting
0: Set RSPCK low during idle
1: Set RSPCK high during idle.
R/W
b3, b2
BRDV[1:0]
Bit Rate Division Setting
b3 b2
R/W
b6 to b4
SSLA[2:0]
SSL Signal Assertion Setting
b7
SSLKP
SSL Signal Level Keeping
b11 to b8
SPB[3:0]
SPI Data Length Setting
b12
LSBF
SPI LSB First
0: MSB first
1: LSB first.
R/W
b13
SPNDEN
SPI Next-Access Delay
Enable
0: Select next-access delay of 1 RSPCK + 2 PCLKA
1: Select next-access delay equal to the setting in the SPI NextAccess Delay Register (SPND).
R/W
b14
SLNDEN
SSL Negation Delay Setting
Enable
0: Select SSL negation delay of 1 RSPCK
1: Select SSL negation delay equal to the setting in the SPI Slave
Select Negation Delay Register (SSLND).
R/W
b15
SCKDEN
RSPCK Delay Setting Enable
0: Select RSPCK delay of 1 RSPCK
1: Select RSPCK delay equal to the setting in the SPI Clock Delay
Register (SPCKD).
R/W
0
0
1
1
0: Base bit rate
1: Base bit rate divided by 2
0: Base bit rate divided by 4
1: Base bit rate divided by 8.
b6
R/W
b4
0 0 0: SSL0
0 0 1: SSL1
0 1 0: SSL2
0 1 1: SSL3
1 x x: Setting prohibited.
x: Don’t care.
0: Negate all SSL signals on completion of transfer
1: Keep SSL signal level from the end of transfer until the beginning
of the next access.
R/W
b11
R/W
b8
0100 to 0111: 8 bits
1 0 0 0: 9 bits
1 0 0 1: 10 bits
1 0 1 0: 11 bits
1 0 1 1: 12 bits
1 1 0 0: 13 bits
1 1 0 1: 14 bits
1 1 1 0: 15 bits
1 1 1 1: 16 bits
0 0 0 0: 20 bits
0 0 0 1: 24 bits
0010, 0011: 32 bits.
The SPCMDm registers specify the transfer format for SPI in master mode. Each channel has eight SPI Command
Registers (SPCMD0 to SPCMD7). Some of the bits in the SPCMD0 register are used to set the transfer mode for the SPI
in slave mode. The SPI in master mode sequentially references the SPCMDm registers based on the settings in the
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36. Serial Peripheral Interface (SPI)
SPSCR.SPSLN[2:0] bits and executes the serial transfer that is set in the referenced SPCMDm register.
Set the SPCMDm registers while the transmit buffer is empty (SPSR.SPTEF is 1 and data for the next transfer is not set)
and before the setting of the data to be transmitted when that SPCMDm register is referenced.
The SPCMDm register referenced by the SPI in master mode can be checked with the SPSSR.SPCP[2:0] bits. If the
contents of SPCMDm are changed while the SPCR.MSTR bit is 0 and the SPCR.SPE bit is 1, do not perform subsequent
operations.
CPHA bit (RSPCK Phase Setting)
The CPHA bit selects the RSPCK phase of the SPI in master or slave mode. Data communications between SPI modules
require the same RSPCK phase setting between the modules.
CPOL bit (RSPCK Polarity Setting)
The CPOL bit selects the RSPCK polarity of the SPI in master or slave mode. Data communications between SPI
modules require the same RSPCK polarity setting between the modules.
BRDV[1:0] bits (Bit Rate Division Setting)
The BRDV[1:0] bits determine the bit rate. The bit rate is determined by the combination of the settings in the
BRDV[1:0] bits and SPBR (see section 36.2.8, SPI Bit Rate Register (SPBR)). The SPBR settings determine the base bit
rate. The BRDV[1:0] setting selects the bit rate obtained by dividing the base bit rate by 1, 2, 4, or 8. Different
BRDV[1:0] bit settings can be specified in the SPCMDm registers. This enables execution of serial transfers at different
bit rates for each command.
SSLA[2:0] bits (SSL Signal Assertion Setting)
The SSLA[2:0] bits control the SSLni signal assertion when the SPI performs serial transfers in master mode. When an
SSLni signal is asserted, its polarity is determined by the value set in the associated SSLP. When the SSLA[2:0] bits are
set to 000b in multi-master mode, serial transfers are performed with all the SSL signals in the negated state (as the
SSLn0 pin acts as input).
When using the SPI in slave mode, set the SSLA[2:0] bits to 000b.
SSLKP bit (SSL Signal Level Keeping)
When the SPI in master mode performs a serial transfer, the SSLKP bit specifies whether the SSLni signal level for the
current command is to be kept or negated between the SSL negation associated with the current command and the SSL
assertion associated with the next command. Setting the SSLKP bit to 1 enables a burst transfer. For details, see (4) Burst
transfers in 36.3.10.1 Master mode operation. When using the SPI in slave mode, set the SSLKP bit to 0.
SPB[3:0] bits (SPI Data Length Setting)
The SPB[3:0] bits specify the transfer data length for the SPI in master or slave mode. When the SPLW bit is 0, set these
bits from 8 to 16 bits.
LSBF bit (SPI LSB First)
The LSBF bit specifies the data format of the SPI in master or slave mode to MSB-first or LSB-first.
SPNDEN bit (SPI Next-Access Delay Enable)
The SPNDEN bit specifies the next-access delay, the period from the time the SPI in master mode terminates a serial
transfer and sets the SSLni signal inactive until the SPI enables the SSLni signal assertion for the next access. If the
SPNDEN bit is 0, the SPI sets the next-access delay to 1 RSPCK + 2 PCLKA. If the SPNDEN bit is 1, the SPI inserts a
next-access delay in accordance with the SPND setting.
When using the SPI in slave mode, set the SPNDEN bit to 0.
SLNDEN bit (SSL Negation Delay Setting Enable)
The SLNDEN bit specifies the SSL negation delay, the period from the time the SPI in master mode stops RSPCK
oscillation until the SPI sets the SSLni signal to inactive. If the SLNDEN bit is 0, the SPI sets the SSL negation delay to
1 RSPCK. If the SLNDEN bit is 1, the SPI negates the SSL signal at the SSL negation delay determined by the SSLND
setting.
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36. Serial Peripheral Interface (SPI)
When using the SPI in slave mode, set the SLNDEN bit to 0.
SCKDEN bit (RSPCK Delay Setting Enable)
The SCKDEN bit specifies the SPI clock delay, the period between when the SPI in master mode asserts the SSLni signal
until the RSPCK starts oscillation. If the SCKDEN bit is 0, the SPI sets the RSPCK delay to 1 RSPCK. If the SCKDEN
bit is 1, the SPI starts the oscillation of RSPCK at the RSPCK delay determined by the SPCKD setting.
When using the SPI in slave mode, set the SCKDEN bit to 0.
36.2.15
SPI Data Control Register 2 (SPDCR2)
Address(es): SPI0.SPDCR2 4007 2020h, SPI1.SPDCR2 4007 2120h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
BYSW
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
b0
BYSW
Byte Swap Operating Mode Select
b7 to b1
—
Reserved
Description
R/W
0: Byte Swap OFF
1: Byte Swap ON.
R/W
These bits are read as 0. The write value should be 0.
R/W
SPI Data Control Register2 (SPDCR2) is the setting register, that is to swap a transmit/receive data in byte units. When a
data of transmit buffers copies to a shift register, it is to swap in byte units. When a data of shift register copies to a
receive buffers, it is to swap in byte units.
BYSW bit (Byte Swap Operating Mode Select)
It is a setting bit, that is to swap a transmit/receive data in byte units. When byte access is valid (SPDCR.SPBYT = 1),
byte swap is invalid. When byte swap is valid, parity function must be invalid (SPCR2.SPPE bit = 0). Setting change of
BYSW bit must be SPCR.SPE bit = 0.
A data after byte swap is different by a data length (setting of SPCMD.SPB[3:0]).
When byte swap, A data length (setting of SPB[3:0]) must be set to 32 bit or 16 bit. Other case of data length (that is 8 to
15, 20, 24 bit length), byte swap is not guaranteed. Before swap and after swap (length data (32 bit/16 bit)) are as shown:
Length data 32 bit (SPB[3:0] = 0010 or 0011)
Before swap: [31:24] [23:16] [15:8] [7:0]
After swap: [7:0] [15:8] [23:16] [31:24]
Length data 16 bit (SPB[3:0] = 1111)
Before swap: [31:24] [23:16]
After swap: [23:16] [31:24].
When byte access mode (SPDCR.SPBT = 1), byte swap setting is invalid.
When byte swap is valid, set parity function to invalid (SPCR2.SPPE = 0). When the parity function set to valid, the
behavior is not guaranteed.
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36.3
36. Serial Peripheral Interface (SPI)
Operation
In this section, the serial transfer period refers to the period from the beginning of driving valid data to the fetching of the
final valid data.
36.3.1
Overview of SPI Operation
SPI is capable of synchronous serial transfers in the following modes:
Slave mode (SPI operation)
Single master mode (SPI operation)
Multi-master mode (SPI operation)
Slave mode (clock synchronous operation)
Master mode (clock synchronous operation).
The SPI mode can be selected by using the MSTR, MODFEN, and SPMS bits in SPCR. Table 36.5 lists the relationship
between the SPI modes and SPCR settings, and provides a description for each mode.
Table 36.5
Relationship between SPCR settings and SPI modes (1 of 2)
Mode
Slave (SPI
operation)
MSTR bit setting
MODFEN bit setting
0
Single master
(SPI operation)
1
Multi-master
(SPI operation)
Slave (clock
synchronous
operation)
1
0
Master (clock
synchronous
operation)
1
0 or 1
0
1
0
0
SPMS bit setting
0
0
0
1
1
RSPCKn signal
Input
Output
Output/Hi-Z
Input
Output
MOSIn signal
Input
Output
Output/Hi-Z
Input
Output
MISOn signal
Output/Hi-Z
Input
Input
Output
Input
Hi-Z*1
SSLn0 signal
Input
Output
Input
Hi-Z*1
SSLn1 to SSLn3 signals
Hi-Z*1
Output
Output/Hi-Z
Hi-Z*1
Hi-Z*1
SSL polarity change
function
Supported
Supported
Supported
-
-
Max transfer rate
PCLKA/4
PCLKA/2
PCLKA/2
PCLKA/4
PCLKA/2
RSPCKn input
On-chip baud rate
generator
On-chip baud rate
generator
RSPCKn input
On-chip baud rate
generator
One (CPHA = 1)
Two
Clock source
Clock polarity
Clock phase
Two
Two
Two
First transfer bit
Two
MSB/LSB
Transfer data length
8 to 16, 20, 24, 32 bits
Possible
(CPHA = 1)
Possible
(CPHA = 0,1)
Possible
(CPHA = 0,1)
-
-
RSPCK delay control
Not supported
Supported
Supported
Not supported
Supported
SSL negation delay
control
Not supported
Supported
Supported
Not supported
Supported
Next-access delay control
Not supported
Supported
Supported
Not supported
Supported
SSL input
active or
RSPCK
oscillation
Write to transmit
buffer on generation
of transmit buffer
empty interrupt
request
(SPTEF = 1)
Write to transmit
buffer on generation
of transmit buffer
empty interrupt
request
(SPTEF = 1)
RSPCK oscillation
Write to transmit
buffer on generation
of transmit buffer
empty interrupt
request
(SPTEF = 1)
Not supported
Supported
Supported
Not supported
Supported
Burst transfer
Transfer trigger
Sequence control
Transmit buffer empty
detection
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Table 36.5
36. Serial Peripheral Interface (SPI)
Relationship between SPCR settings and SPI modes (2 of 2)
Slave (SPI
operation)
Mode
Single master
(SPI operation)
Multi-master
(SPI operation)
Slave (clock
synchronous
operation)
Master (clock
synchronous
operation)
Supported*2
Receive buffer full
detection
Supported*2
Overrun error detection
Supported*2, *4
Supported*2, *4
Supported*2
Supported*2
Supported*2,*3
Parity error detection
Mode fault error detection
Supported
(MODFEN = 1)
Not supported
Supported
Not supported
Not supported
Underrun error detection
Supported
Not supported
Not supported
Supported
Not supported
Note 1.
Note 2.
Note 3.
Note 4.
This function is not supported in this mode.
When the SPCR.TXMD bit is 1, receiver buffer full detection, overrun error detection, and parity error detection are not
performed.
When the SPCR2.SPPE bit is 0, parity error detection is not performed.
When the SPCR2.SCKASE bit is 1, overrun error detection is not performed.
36.3.2
Controlling the SPI Pins
The SPI can switch pin states based on the settings in the MSTR, MODFEN, and SPMS bits in SPCR and the
PmnPFS.NCODR bit for the I/O ports. Table 36.6 lists the relationship between the pin states and bit settings. Setting the
PmnPFS.NCODR bit for an I/O port to 0 selects the CMOS output. Setting it to 1 selects the open-drain output. The I/O
port settings must follow this relationship.
Table 36.6
Relationship between pin states and bit settings
Pin state*2
Mode
Pin
PmnPFS.NCODR bit for I/O
ports = 0
PmnPFS.NCODR bit for I/O
ports = 1
Single master mode (SPI operation)
(MSTR = 1, MODFEN = 0, SPMS = 0)
RSPCKn
CMOS output
Open-drain output
SSLn0 to SSLn3
CMOS output
Open-drain output
MOSIn
CMOS output
Open-drain output
MISOn
Input
Input
RSPCKn*3
CMOS output/Hi-Z
Open-drain output/Hi-Z
SSLn0
Input
Input
SSLn1 to SSLn3*3
CMOS output/Hi-Z
Open-drain output/Hi-Z
MOSIn*3
CMOS output/Hi-Z
Open-drain output/Hi-Z
MISOn
Input
Input
RSPCKn
Input
Input
SSLn0
Input
Input
SSLn1 to SSLn3*5
Hi-Z*1
Hi-Z*1
MOSIn
Multi-master mode (SPI operation)
(MSTR = 1, MODFEN = 1, SPMS = 0)
Slave mode (SPI operation)
(MSTR = 0, SPMS = 0)
Master mode
(clock synchronous operation)
(MSTR = 1, MODFEN = 0, SPMS = 1)
Slave mode
(clock synchronous operation)
(MSTR = 0, SPMS = 1)
Note 1.
Input
Input
MISOn*4
CMOS output/Hi-Z
Open-drain output/Hi-Z
RSPCKn
CMOS output
Open-drain output
SSLn0 to SSLn3*5
Hi-Z*1
Hi-Z*1
MOSIn
CMOS output
Open-drain output
MISOn
Input
Input
Input
Input
Hi-Z*1
Hi-Z*1
MOSIn
Input
Input
MISOn
CMOS output
Open-drain output
RSPCKn
SSLn0 to
SSLn3*5
This function is not supported in this mode.
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Note 2.
Note 3.
Note 4.
Note 5.
36. Serial Peripheral Interface (SPI)
SPI settings are not reflected in multiplexed pins for which the SPI function is not selected.
When SSLn0 is at the active level, the pin state is Hi-Z.
When SSLn0 is at the non-active level or the SPCR.SPE bit is 0, the pin state is Hi-Z.
These pins are available for use as I/O port pins.
The SPI in single master mode (SPI operation) or multi-master mode (SPI operation) determines the MOSI signal values
during the SSL negation period (including the SSL retention period during a burst transfer) based on the MOIFE and
MOIFV bit settings in SPPCR, as listed in Table 36.7.
Table 36.7
MOSI signal value determination during SSL negation
MOIFE bit
MOIFV bit
MOSIn signal value during SSL negation
0
0, 1
Final data from previous transfer
1
0
Low
1
1
High
36.3.3
36.3.3.1
SPI System Configuration Examples
Single master and single slave with the MCU as a master
Figure 36.5 shows a single-master and single-slave SPI system configuration example where the MCU is a master. In the
single-master/single-slave configuration, the SSLn0 to SSLn3 outputs of the MCU (master) are not used. The SSL input
of the SPI slave is fixed to the low level, and the SPI slave is maintained in the selected state.*1
The MCU (master) drives the RSPCKn and MOSIn signals. The SPI slave drives the MISO signal.
Note 1. In the transfer format configured when the SPCMDm.CPHA bit is 0, the SSL signal cannot be fixed to the active
level for some slave devices. In situations where the SSL signal cannot be fixed, the SSLni output of the MCU
must be connected to the SSL input of the slave device.
MCU (master)
SPI slave
RSPCKn
RSPCK
MOSIn
MOSI
MISOn
MISO
SSLn0
SSLn1
SSL0
SSLn2
SSL1
SSLn3
SSL2
SPCK
MOSI
MISO
SSL
SSL3
Figure 36.5
Single-master/single-slave configuration example with the MCU as a master
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36.3.3.2
36. Serial Peripheral Interface (SPI)
Single master and single slave with the MCU as a slave
Figure 36.6 shows a single-master and single-slave SPI system configuration example where the MCU is a slave. When
the MCU operates as a slave, the SSLn0 pin is used as SSL input. The SPI master drives the RSPCK and MOSI signals.
The MCU (slave) drives the MISOn signal.*1
In the single-slave configuration when the SPCMDm.CPHA bit is set to 1, the SSLn0 input of the MCU (slave) is fixed
to the low level and the MCU (slave) stays selected. This enables serial transfer execution (Figure 36.7).
Note 1. When SSLn0 is at the non-active level, the pin state is Hi-Z.
MCU (slave)
SPI master
SPCK
RSPCKn
RSPCK
MOSI
MOSIn
MOSI
MISO
MISOn
MISO
SSL
SSL0
SSLn0
SSL1
SSLn1
SSL2
SSLn2
SSL3
SSLn3
Figure 36.6
Single-master/single-slave configuration example with the MCU as a slave and CPHA = 0
SPI master
MCU (slave, CPHA = 1)
MOSI
RSPCKn
RSPCK
MOSIn
MOSI
MISO
MISOn
MISO
SSL
SSLn0
SSL0
SPCK
SSLn1
SSL1
SSLn2
SSL2
SSL3
SSLn3
Figure 36.7
Single-master/single-slave configuration example with the MCU as a slave and CPHA = 1
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36.3.3.3
36. Serial Peripheral Interface (SPI)
Single master and multi slave with the MCU as a master
Figure 36.8 shows a single-master/multi-slave SPI system configuration example where the MCU is a master. In this
example, the SPI system includes the MCU (master) and four slaves (SPI slave 0 to SPI slave 3).
The RSPCKn and MOSIn outputs of the MCU (master) are connected to the RSPCK and MOSI inputs of SPI slaves 0 to
3. The MISO outputs of SPI slaves 0 to 3 are all connected to the MISOn input of the MCU (master). The SSLn0 to
SSLn3 outputs of the MCU (master) are connected to the SSL inputs of SPI slaves 0 to 3, respectively.
The MCU (master) drives the RSPCKn, MOSIn, and SSLn0 to SSLn3 signals. Of the SPI slaves 0 to 3, the slave that
receives low-level input into the SSL input drives the MISO signal.
MCU (master)
SPI slave 0
RSPCKn
RSPCK
SPCK
MOSIn
MOSI
MISOn
MISO
SSLn0
SSL0
SSL
SSLn1
SSL1
SSLn2
SSL2
SSLn3
SSL3
SPI slave 1
SPCK
MOSI
MISO
SSL
SPI slave 2
SPCK
MOSI
MISO
SSL
SPI slave 3
SPCK
MOSI
MISO
SSL
Figure 36.8
Single master/multi-slave configuration example with the MCU as a master
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36.3.3.4
36. Serial Peripheral Interface (SPI)
Single master and multi-slave with the MCU as a slave
Figure 36.9 shows a single master/multi-slave SPI system configuration example where the MCU is used as a slave. In
this example, the SPI system includes an SPI master and two MCUs (slaves X and Y).
The SPCK and MOSI outputs of the SPI master are connected to the RSPCKn and MOSIn inputs of the MCUs (slaves X
and Y). The MISOn outputs of the MCUs (slaves X and Y) are all connected to the MISO input of the SPI master. The
SSLX and SSLY outputs of the SPI master are connected to the SSLn0 inputs of the MCUs (slaves X and Y,
respectively).
The SPI master drives the SPCK, MOSI, SSLX, and SSLY signals. Of the MCUs (slaves X and Y), the slave that
receives low-level input into the SSLn0 input drives the MISOn signal.
SPI master
MCU (slave X)
SPCK
RSPCKn
RSPCK
MOSI
MOSIn
MOSI
MISO
MISOn
MISO
SSLX
SSLn0
SSL0
SSLY
SSLn1
SSL1
SSLn2
SSL2
SSLn3
SSL3
MCU (slave Y)
RSPCKn
RSPCK
MOSIn
MOSI
MISOn
MISO
SSLn0
SSL0
SSLn1
SSL1
SSLn2
SSL2
SSLn3
SSL3
Figure 36.9
Single master/multi-slave configuration example with the MCU as a slave
36.3.3.5
Multi master and multi slave with the MCU as a master
Figure 36.10 shows a multi-master/multi-slave SPI system configuration example where the MCU is a master. In this
example, the SPI system includes two MCUs (masters X and Y) and two SPI slaves (SPI slaves 1 and 2).
The RSPCKn and MOSIn outputs of the MCUs (masters X and Y) are connected to the RSPCK and MOSI inputs of SPI
slaves 1 and 2. The MISO outputs of SPI slaves 1 and 2 are connected to the MISOn inputs of the MCUs (masters X and
Y). Any generic port Y output from the MCU (master X) is connected to the SSLn0 input of the MCU (master Y). Any
generic port X output of the MCU (master Y) is connected to the SSLn0 input of the MCU (master X). The SSLn1 and
SSLn2 outputs of the MCUs (masters X and Y) are connected to the SSL inputs of the SPI slaves 1 and 2. In this
configuration example, because the system can be comprised solely of SSLn0 input, and SSLn1, SSLn2 outputs for slave
connections, the SSLn3 output of the MCU is not required.
The MCU drives the RSPCKn, MOSIn, SSLn1, and SSLn2 signals when the SSLn0 input level is high. When the SSLn0
input level is low, the MCU detects a mode fault error, sets RSPCKn, MOSIn, SSLn1, and SSLn2 to Hi-Z, and releases
the SPI bus directly to the other master. Of the SPI slaves 1 and 2, the slave that receives low-level input into the SSL
input drives the MISO signal.
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36. Serial Peripheral Interface (SPI)
MCU (master Y)
MCU (master X)
RSPCKn
RSPCK
MOSI
MOSIn
RSPCKn
RSPCK
MISO
MISOn
SSL0
SSLn0
MISO
MISOn
SSL0
SSLn0
SSL1
SSLn1
SSL1
SSLn1
SSL2
SSLn2
SSL2
SSLn2
SSL3
SSLn3
SSL3
SSLn3
Port Y
Port X
MOSIn
MOSI
SPI slave 1
SPCK
MOSI
MISO
SSL
SPI slave 2
SPCK
MOSI
MISO
SSL
Figure 36.10
Multi-master/multi-slave configuration example with the MCU as a master
36.3.3.6
Master and slave in clock synchronous mode with the MCU as a master
Figure 36.11 shows a master and slave in clock synchronous mode where the MCU is a master. In this configuration,
SSLn0 to SSLn3 of the MCU (master) are not used.
The MCU (master) drives the RSPCKn and MOSIn signals. The SPI slave drives the MISO signal.
MCU (master)
SPI slave
RSPCKn
RSPCK
SPCK
MOSIn
MOSI
MISOn
MISO
MOSI
SSLn0
SSL0
SSL
MISO
SSLn1
SSL1
SSLn2
SSL2
SSLn3
SSL3
Figure 36.11
Configuration example of master/slave in clock synchronous mode with the MCU as a master
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36.3.3.7
36. Serial Peripheral Interface (SPI)
Master and slave in clock synchronous mode with the MCU as a slave
Figure 36.12 shows a master and slave in clock synchronous mode where the MCU is used as a slave. When the MCU
operates as a slave in clock synchronous mode, the MCU (slave) drives the MISOn signal and the SPI master drives the
SPCK and MOSI signals. In addition, SSLn0 to SSLn3 of the MCU (slave) are not used.
The MCU (slave) can only execute serial transfers in the single slave configuration when the SPCMDm.CPHA bit is set
to 1.
SPI master
MCU (slave)
SPCK
RSPCKn
RSPCK
MOSI
MOSIn
MOSI
MISO
MISOn
MISO
SSL
SSLn0
SSL0
SSLn1
SSL1
SSLn2
SSL2
SSLn3
SSL3
Figure 36.12
36.3.4
Configuration example of master and slave in clock synchronous mode with the MCU as a slave
and CPHA = 1
Data Formats
The data format of the SPI depends on the settings in SPI Command Register m (SPCMDm) (m = 0 to 7) and the parity
enable bit in SPI Control Register 2 (SPCR2.SPPE). Regardless of whether the MSB or LSB is first, the SPI treats the
range from the LSB bit in the SPI Data Register (SPDR/SPDR_HA) to the bit corresponding to the selected data length,
as transfer data.
This section shows the format of one frame of data before or after transfer.
(a)
Data format with parity disabled
When parity is disabled, transmission or reception of data proceeds with the length in bits selected in the SPI data length
setting in SPI Command Register m (SPCMDm.SPB[3:0]).
(b)
Data format with parity enabled
When parity is enabled, transmission or reception of data proceeds with the length in bits selected in the SPI data length
setting in SPI Command Register m (SPCMDm.SPB[3:0]). In this case, however, the last bit is a parity bit.
With parity disabled
D0
D1
D2
Dn-2
Dn-1
Dn
Dn-1
P
SPCMDm.SPB[3:0] (m = SPSSR.SPCP[2:0])
With parity enabled
D0
D1
D2
Dn-2
SPCMDm.SPB[3:0] (m = SPSSR.SPCP[2:0])
Figure 36.13
Data format with parity disabled and enabled
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36.3.4.1
36. Serial Peripheral Interface (SPI)
Operation when parity is disabled (SPCR2.SPPE = 0)
When parity is disabled, data for transmission is copied to the shift register with no pre-processing. This section
describes the connection between the SPI Data Register (SPDR/SPDR_HA) and the shift register in terms of the
combination of MSB- or LSB-first order and data length.
(1)
MSB-first transfer with 32-bit data
Figure 36.14 shows the transfer operations of the SPI Data Register (SPDR) and the shift register with parity disabled, an
SPI data length of 32 bits, and MSB-first selected.
In transmission, bits T31 to T00 from the current stage of the transmit buffer are copied to the shift register. Data for
transmission is shifted out from the shift register from T31 to T30, and continuing to T00, in that order.
In reception, received data is shifted in bit by bit through bit 0 of the shift register. When R31 to R00 bits are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T08
T07
T06
T05
T04
T03
T02
T01
T00
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
Bit 31
T23
Bit 0
Shift register
Transfer end
Shift register
Bit 31
R31
R30
R29
R28
R27
R26
R25
R24
R23
Bit 0
R08
R07
R06
R05
R04
R03
R02
R01
R00
R08
R07
R06
R05
R04
R03
R02
R01
R00
Input
Copy
R31
R30
R29
R28
R27
R26
R25
Bit 31
R24
R23
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 36.14
(2)
MSB-first transfer with 32-bit data and parity disabled
MSB-first transfer with 24-bit data
Figure 36.15 shows the transfer operations of the SPI Data Register (SPDR) and the shift register with parity disabled, an
SPI data length of 24 bits, and MSB-first selected.
In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are copied to the shift
register. Data for transmission is shifted out from the shift register from T23 to T22, and continuing to T00, in that order.
In reception, received data is shifted in bit-by-bit through bit [0] of the shift register. When the R23 to R00 bits are
collected after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive
buffer. At this time, the upper 8 bits of the transmit buffer are stored in the upper 8 bits of the receive buffer. Writing 0 to
bits T31 to T24 at the time of transmission leads to 0 being inserted in the upper 8 bits of the receive buffer.
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36. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 23
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T08
T07
T06
T05
T04
T03
T02
T01
T00
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 23
Shift register
Bit 31
Bit 0
Transfer end
Bit 24
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
Shift register
Bit 23
R23
Bit 0
R08
R07
R06
R05
R04
R03
R02
R01
R08
R07
R06
R05
R04
R03
R02
R01
R00
Input
Copy
T31
T30
T29
T28
Bit 31
T27
T26
T25
T24
Bit 24
R23
Bit 23
Receive buffer
R00
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 36.15
MSB-first transfer with 24-bit data and parity disabled
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(3)
36. Serial Peripheral Interface (SPI)
LSB-first transfer with 32-bit data
Figure 36.16 shows the transfer operations of the SPI Data Register (SPDR) and the shift register with parity disabled, an
SPI data length of 32 bits, and LSB-first selected.
In transmission, bits T31 to T00 from the current stage of the transmit buffer are reordered bit-by-bit to obtain the order
T00 to T31 for copying to the shift register. Data for transmission is shifted out from the shift register in order from T00,
to T01, and continuing to T31, in that order.
In reception, received data is shifted in bit-by-bit through bit [0] of the shift register. When the R00 to R31 bits are
collected after the input of the required number of RSPCK cycles, the value in the shift register is copied to the receive
buffer.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T23
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
R23
R24
R25
R26
R27
R28
R29
R30
R31
R08
R07
R06
R05
R04
R03
R02
R01
R00
Input
Copy
R31
R30
R29
R28
Bit 31
R27
R26
R25
R24
R23
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 36.16
LSB-first transfer with 32-bit data and parity disabled
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36. Serial Peripheral Interface (SPI)
LSB-first transfer with 24-bit data
Figure 36.17 shows the transfer operations of the SPI Data Register (SPDR) and the shift register with parity disabled, an
SPI data length of 24 bits, and LSB-first selected.
In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are reordered bit-by-bit
to obtain the order T00 to T23 for copying to the shift register. Data for transmission is shifted out from the shift register
in order from T00 to T01, and continuing to T23, in that order.
In reception, received data is shifted in bit-by-bit through bit [8] of the shift register. When the R00 to R23 bits are
collected after the input of the required number of RSPCK cycles, the value in the shift register is copied to the receive
buffer.
At this time, the upper 8 bits of the transmit buffer are stored in the upper 8 bits of the receive buffer. Writing 0 to the T31
to T24 bits at the time of transmission leads to 0 being inserted in the upper 8 bits of the receive buffer.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T23
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Input
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
R23
T24
T25
T26
T27
T28
T29
T30
T31
R08
R07
R06
R05
R04
R03
R02
R01
R00
Copy
T31
T30
T29
T28
Bit 31
T27
T26
T25
T24
R23
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 36.17
LSB-first transfer with 24-bit data and parity disabled
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36.3.4.2
36. Serial Peripheral Interface (SPI)
Operation when parity is enabled (SPCR2.SPPE = 1)
When parity is enabled, the lowest-order bit of the data for transmission becomes a parity bit. Hardware calculates the
value of the parity bit.
(1)
MSB-first transfer with 32-bit data
Figure 36.18 shows the transfer operations of the SPI Data Register (SPDR) and the shift register with parity enabled, an
SPI data length of 32 bits, and MSB-first selected.
In transmission, the value of the parity bit (P) is calculated from bits T31 to T01. This replaces the final bit, T00, and the
whole value is copied to the shift register. Data is transmitted in the order T31, T30, …, T01, and P.
In reception, received data is shifted in bit-by-bit through bit [0] of the shift register. When the R31 to P bits are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On
copying of data to the shift register, the data from R31 to P is checked for parity.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T08
T23
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
T31
T30
T29
T28
T27
T26
T25
T24
T23
Parity added
T08
T07
T06
T05
T04
T03
T02
T01
T08
T07
T06
T05
T04
T03
T02
T01
P
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
Bit 31
T23
P
Bit 0
Shift register
Transfer end
Shift register
Bit 31
R31
R30
R29
R28
R27
R26
R25
R24
R23
Bit 0
R08
R07
R06
R05
R04
R03
R02
R01
P
R08
R07
R06
R05
R04
R03
R02
R01
P
Input
Copy
R31
R30
R29
R28
R27
R26
R25
R24
Bit 31
R23
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 36.18
(2)
MSB-first transfer with 32-bit data and parity enabled
MSB-first transfer with 24-bit data
Figure 36.19 shows the transfer operations of the SPI Data Register (SPDR) and the shift register with parity enabled, an
SPI data length of 24 bits, and MSB-first selected.
In transmission, the value of the parity bit (P) is calculated from bits T23 to T01. This replaces the final bit, T00, and the
whole is copied to the shift register. Data is transmitted in the order T23, T22, …, T01, and P.
In reception, received data is shifted in bit-by-bit through bit [0] of the shift register. When the R23 to P bits are collected
after the input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On
copying of data to the shift register, the data from R23 to P is checked for parity. At this time, the upper 8 bits of the
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36. Serial Peripheral Interface (SPI)
transmit buffer are stored in the upper 8 bits of the receive buffer. Writing 0 to bits T31 to T24 at the time of transmission
leads to 0 being inserted in the upper 8 bits of the receive buffer.
Transfer start
Transmit buffer
Bit 23
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T08
T23
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity added
T31
T30
T29
T28
T27
T26
T25
T24
T23
T08
T07
T06
T05
T04
T03
T02
T01
P
T08
T07
T06
T05
T04
T03
T02
T01
P
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 23
Shift register
Bit 31
Bit 0
Transfer end
Bit 24
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
Shift register
Bit 23
R23
Bit 0
R08
R07
R06
R05
R04
R03
R02
R01
R08
R07
R06
R05
R04
R03
R02
R01
P
Input
Copy
T31
T30
T29
T28
T27
T26
T25
T24
Bit 24
Bit 31
R23
Bit 23
Receive buffer
P
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 36.19
(3)
MSB-first transfer with 24-bit data and parity enabled
LSB-first transfer with 32-bit data
Figure 36.20 shows the transfer operations of the SPI Data Register (SPDR) and the shift register with parity enabled, an
SPI data length of 32 bits, and LSB-first selected.
In transmission, the value of the parity bit (P) is calculated from bits T30 to T00. This replaces the final bit, T31, and the
whole is copied to the shift register. Data is transmitted in the order T00, T01, …, T30, and P.
In reception, received data is shifted in bit-by-bit through bit [0] of the shift register. When the R00 to P bits are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On
copying of data to the shift register, the data from R00 to P is checked for parity.
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36. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T08
T23
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
Parity added
Bit 31
P
Bit 0
T30
T29
T28
T27
T26
T25
T24
T23
T08
T07
T06
T05
T04
T03
T02
T01
T23
T24
T25
T26
T27
T28
T29
T30
T00
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
P
Bit 0
Shift register
Transfer end
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
Input
R23
R24
R25
R26
R27
R28
R29
R30
P
R08
R07
R06
R05
R04
R03
R02
R01
R00
Copy
P
R30
R29
R28
R27
Bit 31
R26
R25
R24
R23
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 36.20
LSB-first transfer with 32-bit data and parity enabled
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36. Serial Peripheral Interface (SPI)
LSB-first transfer with 24-bit data
Figure 36.21 shows the transfer operations of the SPI Data Register (SPDR) and the shift register with parity enabled, an
SPI data length of 24 bits, and LSB-first selected.
In transmission, the value of the parity bit (P) is calculated from bits T22 to T00. This replaces the final bit, T23, and the
whole is copied to the shift register. Data is transmitted in the order T00, T01, …, T22, and P.
In reception, received data is shifted in bit-by-bit through bit [8] of the shift register. When the R00 to P bits are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On
copying of data to the shift register, the data from R00 to P is checked for parity. At this time, the upper 8 bits of the
transmit buffer are stored in the upper 8 bits of the receive buffer. Writing 0 to bits T31 to T24 at the time of transmission
leads to 0 being inserted in the upper 8 bits of the receive buffer.
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
T08
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
Parity added
Bit 0
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
P
T08
T07
T06
T05
T04
T03
T02
T01
T00
P
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Input
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
P
T24
T25
T26
T27
T28
T29
T30
T31
R08
R07
R06
R05
R04
R03
R02
R01
R00
Copy
T31
T30
T29
T28
T27
Bit 31
T26
T25
T24
P
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 36.21
LSB-first transfer with 24-bit data and parity enabled
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36.3.5
36.3.5.1
36. Serial Peripheral Interface (SPI)
Transfer Formats
Transfer format when CPHA = 0
Figure 36.22 shows an example transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 0. Do
not perform clock synchronous operation (SPCR.SPMS = 1) when the SPI operates in slave mode (SPCR.MSTR = 0)
and the CPHA bit is 0. In the figure, RSPCKn (CPOL = 0) indicates the RSPCKn signal waveform when the
SPCMDm.CPOL bit is 0, and RSPCKn (CPOL = 1) indicates the RSPCKn signal waveform when the CPOL bit is 1. The
sampling timing represents the timing at which the SPI fetches serial transfer data into the shift register. The I/O
directions of the signals depend on the SPI settings. For details, see section 36.3.2, Controlling the SPI Pins.
When the SPCMDm.CPHA bit is 0, the driving of valid data to the MOSIn and MISOn signals commences on an SSLni
signal assertion. The first RSPCKn signal change that occurs after the SSLni signal assertion becomes the first transfer
data fetch. After this, data is sampled every 1 RSPCK cycle. The change timing for MOSIn and MISOn signals is 1/2
RSPCK cycles after the transfer data fetch timing. The CPOL bit setting does not affect the RSPCK signal operation
timing as it only affects the signal polarity.
t1 denotes the period from an SSLni signal assertion to RSPCKn oscillation (RSPCK delay). t2 denotes the period from
the termination of RSPCKn oscillation to an SSLni signal negation (SSL negation delay). t3 denotes the period in which
SSLni signal assertion is suppressed for the next transfer after the end of the serial transfer (next-access delay). t1, t2, and
t3 are controlled by a master device running on the SPI system. For a description of t1, t2, and t3 when the SPI is in
master mode, see section 36.3.10.1, Master mode operation.
Start
End
Serial transfer period
RSPCK
cycle
1
2
3
4
5
6
7
8
RSPCKn
(CPOL = 0)
RSPCKn
(CPOL = 1)
Sampling
timing
MOSIn
MISOn
SSLni
t1
Figure 36.22
t2
t3
SPI transfer format when CPHA = 0
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36.3.5.2
36. Serial Peripheral Interface (SPI)
When CPHA = 1
Figure 36.23 shows an example transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 1.
However, when the SPCR.SPMS bit is 1, the SSLni signals are not used, and only the three signals RSPCKn, MOSIn,
and MISOn handle the communication. In Figure 36.23, RSPCK (CPOL = 0) indicates the RSPCKn signal waveform
when the SPCMDm.CPOL bit is 0, and RSPCK (CPOL = 1) indicates the RSPCKn signal waveform when the CPOL bit
is 1. The sampling timing represents the timing at which the SPI fetches serial transfer data into the shift register. The I/O
directions of the signals depend on the SPI mode (master or slave). For details, see section 36.3.2, Controlling the SPI
Pins.
When the SPCMDm.CPHA bit is 1, the driving of invalid data to the MISOn signal commences on an SSLni signal
assertion. The output of valid data to the MOSIn and MISOn signals commences at the first RSPCKn signal change that
occurs after the SSLni signal assertion. After this, data is updated every 1 RSPCK cycle. The transfer data fetch timing is
1/2 RSPCK cycles after the data update timing. The SPCMDm.CPOL bit setting does not affect the RSPCKn signal
operation timing; it only affects the signal polarity.
t1, t2, and t3 are the same as when CPHA = 0. For a description of t1, t2, and t3 when the MCU SPI is in master mode,
see section 36.3.10.1, Master mode operation.
Start
RSPCK
cycle
End
Serial transfer period
1
2
3
4
5
6
7
8
RSPCKn
(CPOL = 0)
RSPCKn
(CPOL = 1)
Sampling
timing
MOSIn
MISOn
SSLni
t1
Figure 36.23
t2
t3
SPI transfer format when CPHA = 1
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36.3.6
36. Serial Peripheral Interface (SPI)
Data Transfer Modes
Full-duplex synchronous serial communications or transmit operations can only be selected in the Communications
Operating Mode Select bit (SPCR.TXMD). The SPDR/SPDR_HA access shown in Figure 36.24 and Figure 36.25
indicate the condition of access to the register, where W denotes a write cycle.
36.3.6.1
Full-duplex synchronous serial communications (SPCR.TXMD = 0)
Figure 36.24 shows an example of operation where the Communications Operating Mode Select bit (SPCR.TXMD) is
set to 0. In this example, the SPI performs an 8-bit serial transfer when SPDCR.SPFC[1:0] bits are 00b, the
SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0. The numbers given for RSPCKn in the waveform represent
the number of RSPCK cycles, indicating the number of transferred bits.
SPDR_HA access
RSPCKn
(CPHA = 1, CPOL = 0)
Receive buffer
state
W
W
1
2
3
4
5
6
7
8
1
Empty
2
3
4
5
6
7
8
Full
SPIi_SPRI
(1)
SPRF
OVRF
(2)
Figure 36.24
Operation example when SPCR.TXMD = 0
The operation of the flags at timings (1) and (2) in Figure 36.24 is as follows:
1. When a serial transfer ends with the receive buffer of SPDR_HA empty, the SPI generates a receive buffer full
interrupt request (SPIi_SPRI) (the SPI sets the SPSR.SPRF flag to 1) and copies the received data from the shift
register to the receive buffer.
2. When a serial transfer ends with the receive buffer of SPDR_HA holding data that was received in the previous
serial transfer, the SPI sets the SPSR.OVRF flag to 1 and discards the received data in the shift register.
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36.3.6.2
36. Serial Peripheral Interface (SPI)
Transmit operations only (SPCR.TXMD = 1)
Figure 36.25 shows an example of operation where the Communications Operating Mode Select bit (SPCR.TXMD) is
set to 1. In this example, the SPI performs an 8-bit serial transfer when SPDCR.SPFC[1:0] bits are 00b, the
SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0. The numbers given for RSPCKn in the waveform represent
the number of RSPCK cycles, indicating the number of transferred bits.
W
SPDR_HA access
RSPCKn
(CPHA = 1, CPOL = 0)
TXMD
(TXMD = 1)
W
1
2
3
4
5
6
7
1
8
2
3
4
5
6
7
8
(1)
Receive buffer
state
Empty
SPIi_SPRI
(2)
SPRF
OVRF
(3)
Figure 36.25
Operation example when SPCR.TXMD = 1
The operation of the flags at timings (1) to (3) in Figure 36.25 is as follows:
1. Make sure there is no data left in the receive buffer (the SPSR.SPRF flag is 0) and the SPSR.OVRF flag is 0 before
entering transmit-only mode (SPCR.TXMD = 1).
2. When a serial transfer ends with the receive buffer of SPDR_HA empty, if the transmit-only mode is selected
(SPCR.TXMD = 1), the SPSR.SPRF flag retains the value of 0, and SPI does not copy the data in the shift register
to the receive buffer.
3. Because the receive buffer of SPDR_HA does not hold data that was received in the previous serial transfer, even
when a serial transfer ends, the SPSR.OVRF flag retains the value of 0, and the data in the shift register is not
copied to the receive buffer.
In transmit-only mode (SPCR.TXMD = 1), the SPI transmits data but does not receive data. Therefore, the SPSR.SPRF
and SPSR.OVRF flags remain 0 at timings (1) to (3).
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36.3.7
36. Serial Peripheral Interface (SPI)
Transmit Buffer Empty and Receive Buffer Full Interrupts
Figure 36.26 and Figure 36.27 show examples of operation of the transmit buffer empty interrupt (SPIi_SPTI) and the
receive buffer full interrupt (SPIi_SPRI). The SPDR_HA register accesses shown in these figures indicate the condition
of access to the register, where W denotes a write cycle and R denotes a read cycle. In the example in Figure 36.26, the
SPI performs an 8-bit serial transfer when SPCR.TXMD bit is 0, the SPDCR.SPFC[1:0] bits are 00b, the
SPCMDm.CPHA bit is 0, and the SPCMDm.CPOL bit is 0. In the example in Figure 36.27, the SPI performs an 8-bit
serial transfer when SPCR.TXMD bit is 0, the SPDCR.SPFC[1:0] bits are 00b, the SPCMDm.CPHA bit is 1, and the
SPCMDm.CPOL bit is 0. The numbers given for RSPCKn in the waveform represent the number of RSPCK cycles,
indicating the number of transferred bits.
SPDR_HA access
W
W
RSPCKn
(CPHA = 0, CPOL = 0)
Transmit buffer state
2
1
Empty
Full
(1)
3
4
R
5
6
Empty
7
8
1
2
3
4
Full
(2)
5
6
7
8
Empty
(3)
(4)
SPIi_SPTI
SPTEF
Receive buffer state
Empty
Full
Empty
(4)
Full
(5)
SPIi_SPRI
SPRF
Figure 36.26
Operation example of the SPIi_SPTI and SPIi_SPRI interrupts when CPHA = 0 and CPOL = 0
SPDR_HA access
W
W
RSPCKn
(CPHA = 1, CPOL = 0)
Transmit buffer state
1
Empty
Full
(1)
2
3
R
4
5
Empty
(2)
6
7
8
1
2
3
4
Full
(3)
5
6
7
8
Empty
(4)
SPIi_SPTI
SPTEF
Receive buffer state
Empty
Full
(4)
Empty
Full
(5)
SPIi_SPRI
SPRF
Figure 36.27
Operation example of the SPIi_SPTI and SPIi_SPRI interrupts when CPHA = 1 and CPOL = 0
The operation of the SPI at timings (1) to (5) in Figure 36.27 is as follows:
1. When transmit data is written to SPDR_HA and when the transmit buffer of SPDR_HA is empty (data for the next
transfer is not set), the SPI writes data to the transmit buffer and clears the SPSR.SPTEF flag to 0.
2. If the shift register is empty, the SPI copies the data in the transmit buffer to the shift register, generates a transmit
buffer empty interrupt request (SPIi_SPTI), and sets the SPSR.SPTEF flag to 1. How a serial transfer is started
depends on the mode of the SPI. For details, see section 36.3.10, SPI Operation, and section 36.3.11, Clock
Synchronous Operation.
3. When transmit data is written to SPDR_HA either by the transmit buffer empty interrupt routine, or by the
processing of the transmit buffer empty state using the SPTEF flag, the SPI writes data to the transmit buffer and
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36. Serial Peripheral Interface (SPI)
clears the SPTEF flag to 0. Because the data being transferred serially is stored in the shift register, the SPI does not
copy the data in the transmit buffer to the shift register.
4. When the serial transfer ends and the receive buffer of SPDR_HA is empty, SPI copies the receive data in the shift
register to the receive buffer, generates a receive buffer full interrupt request (SPIi_SPRI), and sets the SPRF flag to
1. Because the shift register becomes empty on completion of the serial transfer, when the transmit buffer is full
before the serial transfer ended, the SPI sets the SPTEF flag to 1 and copies data in the transmit buffer to the shift
register. Even when the received data is not copied from the shift register to the receive buffer in an overrun error
status, on completion of the serial transfer, the SPI determines that the shift register is empty, so the data transfer
from the transmit buffer to the shift register is enabled.
5. When SPDR_HA is read either by the receive buffer full interrupt routine or processing of the receive buffer full
state using the SPRF flag, the receive data can be read.
If SPDR_HA is written to when the transmit buffer holds data that is not yet transmitted (the SPTEF flag is 0), the SPI
does not update data in the transmit buffer. When writing to SPDR_HA, always use either a transmit buffer empty
interrupt request or the processing of the transmit buffer empty interrupt using the SPTEF flag. To use a transmit buffer
empty interrupt, set the SPTIE bit in SPCR to 1. If the SPI function is disabled (the SPCR.SPE bit is 0), set the SPTIE bit
to 0.
When the serial transfer ends and the receive buffer is full (the SPRF flag is 1), SPI does not copy data from the shift
register to the receive buffer, and it detects an overrun error (see section 36.3.8, Error Detection). To prevent a receive
data overrun error, read the received data using a receive buffer full interrupt request before the next serial transfer ends.
To use an SPI receive buffer full interrupt, set the SPCR.SPRIE bit to 1.
Transmission and reception interrupts or the associated IELSRn.IR flags (where n is the interrupt vector number) in the
ICU can be used to confirm the states of the transmit and receive buffers.
Similarly, the SPTEF and SPRF flags can be used to confirm the states of the transmit and receive buffers. See section
14, Interrupt Controller Unit (ICU) for the interrupt vector numbers.
36.3.8
Error Detection
In normal SPI serial transfers, data written to the transmit buffer of SPDR/SPDR_HA is transmitted, and the received
data can be read from the receive buffer of SPDR/SPDR_HA. In some cases, non-normal transfers can be executed when
SPDR/SPDR_HA is accessed, depending on the status of the transmit or receive buffer or the status of the SPI at the
beginning or end of the serial transfer.
If a non-normal transfer operation occurs, the SPI detects the event as an underrun error, overrun error, parity error, or
mode fault error. Table 36.8 lists the relationship between non-normal transfer operations and the SPI error detection
function.
Table 36.8
Operation
Relationship between non-normal transfer operations and SPI error detection (1 of 2)
Occurrence condition
SPI operation
Error detection
1
SPDR/SPDR_HA is written when the transmit buffer
is full
Keeps the contents of the transmit buffer
Missing write data.
None
2
SPDR/SPDR_HA is read when the receive buffer is
empty
Outputs the contents of the receive buffer and
previously received data
None
3
Serial transfer is started in slave mode when the SPI
is not able to transmit data
Underrun error
4
Serial transfer terminates when the receive buffer is
full
Keeps the contents of the receive buffer
Missing receive data.
Overrun error
5
An incorrect parity bit is received when performing
full-duplex synchronous serial communications with
the parity function enabled
Asserts the parity error flag.
Parity error
6
The SSLn0 input signal is asserted when the serial
transfer is idle in multi-master mode
Stops driving of the RSPCKn, MOSIn,
SSLn1 to SSLn3 output signals
Disables the SPI function.
Mode fault error
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Suspends serial transfer
Missing transmit and receive data
Stops driving of the MISOA output signal
Disables the SPI function.
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Table 36.8
Operation
36. Serial Peripheral Interface (SPI)
Relationship between non-normal transfer operations and SPI error detection (2 of 2)
Occurrence condition
SPI operation
Error detection
7
The SSLn0 input signal is asserted during serial
transfer in multi-master mode
Suspends serial transfer
Missing transmit and receive data
Stops driving of the RSPCKn, MOSIn,
SSLn1 to SSLn3 output signals
Disables the SPI function.
Mode fault error
8
The SSLn0 input signal is negated during serial
transfer in slave mode
Mode fault error
Suspends serial transfer
Missing transmit and receive data
Stops driving of the MISOn output signal
Disables the SPI function.
In operation 1 described in Table 36.8, the SPI does not detect an error. To prevent data omission during the writing to
SPDR/SPDR_HA, write operations to SPDR/SPDR_HA must be executed using a transmit buffer empty interrupt
request (when the SPSR.SPTEF flag is 1).
Similarly, the SPI does not detect an error in operation 2. To prevent extraneous data from being read, SPDR/SPDR_HA
read operations must be executed with an SPI receive buffer full interrupt request (when the SPSR.SPRF flag is 1).
For the other errors in the figure, see the following sections:
Underrun error (operation 3): section 36.3.8.4, Underrun errors
Overrun error (operation 4): section 36.3.8.1, Overrun errors
Parity error (operation 5): section 36.3.8.2, Parity errors
Mode fault error (operations 6 to 8): section 36.3.8.3, Mode fault errors.
For the transmit and receive interrupts, see section 36.3.7, Transmit Buffer Empty and Receive Buffer Full Interrupts.
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36.3.8.1
36. Serial Peripheral Interface (SPI)
Overrun errors
If a serial transfer ends when the receive buffer of SPDR/SPDR_HA is full, the SPI detects an overrun error and sets the
SPSR.OVRF flag to 1. When the OVRF flag is 1, the SPI does not copy data from the shift register to the receive buffer,
so the data prior to the error occurrence is retained in the receive buffer. To set the OVRF flag to 0, write 0 to the OVRF
flag after the CPU reads SPSR with the OVRF flag set to 1.
Figure 36.28 shows an example of operation of the OVRF and SPRF flags. The SPSR and SPDR_HA accesses shown in
the figure indicate the condition of access to the register, where W denotes a write cycle and R a read cycle. In this
example, the SPI performs an 8-bit serial transfer when SPCMDm.CPHA bit is 1 and the SPCMDm.CPOL bit is 0. The
numbers given for RSPCKn in the waveform represent the number of RSPCK cycles, indicating the number of
transferred bits.
SPSR access
R
SPDR_HA access
W
R
RSPCKn
(CPHA = 1, CPOL = 0)
1
Receive buffer
state
2
3
4
5
6
7
8
1
2
Figure 36.28
4
5
6
7
8
Empty
SPRF
OVRF
3
Full
(2)
(3)
(4)
(1)
Operation example of the OVRF and SPRF flags
The operation of the flags at times (1) to (4) in the figure is as follows:
1. If a serial transfer terminates with the SPRF flag set to 1 (receive buffer full), the SPI detects an overrun error, and
sets the OVRF flag to 1. The SPI does not copy the data in the shift register to the receive buffer. Even when the
SPPE bit is 1, parity errors are not detected. In master mode, the SPI copies the value of the pointer to the SPCMDm
register using the SPSSR.SPECM[2:0] bits.
2. When SPDR_HA is read, the SPI outputs the data in the receive buffer. The SPRF flag is then set to 0. The receive
buffer becoming empty does not set the OVRF flag to 0.
3. If the serial transfer ends with the OVRF flag set to 1 (overrun error occurred), the SPI does not copy data in the
shift register to the receive buffer (the SPRF flag does not set to 1). A receive buffer full interrupt is not generated.
Even when the SPPE bit is 1, parity errors are not detected. In master mode, the SPI does not update the
SPSSR.SPECM[2:0] bits. In an overrun error state when the SPI does not copy the received data from the shift
register to the receive buffer, on termination of the serial transfer, the SPI determines that the shift register is empty.
This enables data transfer from the transmit buffer to the shift register.
4. If 0 is written to the OVRF flag after SPSR is read when the OVRF flag is 1, the OVRF flag clears to 0.
The occurrence of an overrun can be checked either by reading SPSR or by using an SPI error interrupt and reading
SPSR. When executing a serial transfer, you must ensure that overrun errors are detected early, for example, by reading
SPSR immediately after SPDR_HA is read. In master mode, the value of the pointer to the SPCMDm register on the
error occurrence can be checked by reading the SPSSR.SPECM[2:0] bits.
If an overrun error occurs and the OVRF flag is set to 1, normal reception operations cannot be performed until the
OVRF flag is cleared to 0.
When the RSPCK auto-stop function is enabled in master mode, an overrun error does not occur. Figure 36.29 and
Figure 36.30 show the clock stop waveform when a serial transfer continues while the receive buffer is full in master
mode.
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36. Serial Peripheral Interface (SPI)
Start
Start
End
Serial transfer period
End
Serial transfer period
R
SPDR_HA access
RSPCK
cycle
1
2
3
4
5
6
7
RSPCK
cycle
8
1
2
3
4
5
6
7
8
Clock is stopped
RSPCKn
(CPOL = 0)
(2)
RSPCKn
(CPOL = 1)
Sampling
timing
MOSIn
MISOn
SSLni
t2
t1
Receive buffer
state
t3
t2
t1
Empty
Em
pty
Full
Full
SPRF
(Receive buffer full flag)
OVRF
(Overrun error flag)
Low
Receive buffer
read
(1)
SPI transfer format (CPHA = 1)
Output: Undefined (0 or 1)
Input: Don’t care
t1: SPI Clock Delay Register (SPCKD)
t2: SPI Slave Select Negation Delay Register (SSLND)
t3: SPI Next-Access Delay Register (SPND)
Figure 36.29
Clock stop waveform when serial transfer continues while receive buffer is full in master mode
(CPHA = 1)
Start
Start
End
Serial transfer period
End
Serial transfer period
SPDR_HA access
R
RSPCK
cycle
1
2
3
4
5
6
7
RSPCK
cycle
8
1
2
3
4
5
6
7
8
Clock is stopped
RSPCKn
(CPOL = 0)
(2)
RSPCKn
(CPOL = 1)
Sampling
timing
MOSIn
MISOn
SSLni
t2
t1
Receive buffer
state
t3
t2
t1
Empty
Em
pty
Full
Full
SPRF
(Receive buffer full flag)
OVRF
(Overrun error flag)
Low
SPI transfer format (CPHA = 0)
Receive buffer
read
(1)
t1:SPI Clock Delay Register (SPCKD)
Output: Undefined (0 or 1)
Input: Don’t care
t2: SPI Slave Select Negation Delay Register (SSLND)
t3: SPI Next-Access Delay Register (SPND)
Figure 36.30
Clock stop waveform when serial transfer continues while receive buffer is full in master mode
(CPHA = 0)
The operation of the flags at times (1) and (2) in the figure is as follows:
1. When the receive buffer is full, an overrun error does not occur because the RSPCK clock is stopped.
2. If SPDR_HA is read while the clock is stopped, data in the receive buffer can be read. The RSPCK clock restarts
after reading the receive buffer (after the SPSR.SPRF flag clears to 0).
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36.3.8.2
36. Serial Peripheral Interface (SPI)
Parity errors
When a full-duplex synchronous serial communication is performed with the SPCR.TXMD bit set to 0 and the
SPCR2.SPPE bit set to 1, the SPI checks for parity errors when serial transfer ends. On detecting a parity error in the
received data, the SPI sets the SPSR.PERF flag to 1. Because the SPI does not copy data in the shift register to the
receive buffer when the SPSR.OVRF flag is set to 1, parity error detection is not performed for the received data. To set
the PERF flag to 0, write 0 to the PERF flag after the SPSR register is read with the PERF flag set to 1.
Figure 36.31 shows an example of operation of the OVRF and PERF flags. The SPSR access shown in Figure 36.31
indicates the condition of access to the register, where W denotes a write cycle and R a read cycle. In this example, fullduplex synchronous serial communication is performed while the SPCR.TXMD bit is 0 and the SPCR2.SPPE bit is 1.
The SPI performs an 8-bit serial transfer when SPCMDm.CPHA bit is 1 and the SPCMDm.CPOL bit is 0. The numbers
given for RSPCKn in the waveform represent the number of RSPCK cycles, meaning the number of transferred bits.
SPSR access
R
W
RSPCKn
(CPHA = 1, CPOL = 0)
1
2
3
4
5
6
7
PERF
OVRF
Figure 36.31
8
1
(1)
2
3
4
5
6
7
8
(2)
(3)
Operation example of the PERF flag
The operation of the flags at times (1) to (3) in the figure is as follows:
1. If a serial transfer terminates with the SPI not detecting an overrun error, the SPI copies the data in the shift register
to the receive buffer. The SPI checks the received data at this time and sets the PERF flag to 1 if a parity error is
detected. In master mode, the SPI copies the value of the SPCMDm pointer to the SPSSR.SPECM[2:0] bits.
2. If 0 is written to the PERF flag after the SPSR register is read when the PERF flag is 1, the PERF flag clears to 0.
3. When the SPI detects an overrun error and the serial transfer is terminated, the data in the shift register is not copied
to the receive buffer. The SPI does not perform parity error detection at this time.
Parity errors can be checked for either by reading the SPSR register or using an SPI error interrupt and reading the SPSR
register. When executing a serial transfer, such checks are required to ensure the early detection of parity errors. When
the SPI is used in master mode, the value of the SPCMDm pointer at the error occurrence can be checked by reading the
SPSSR.SPECM[2:0] bits.
36.3.8.3
Mode fault errors
The SPI operates in multi-master mode when the SPCR.MSTR bit is 1, the SPCR.SPMS bit is 0, and the
SPCR.MODFEN bit is 1. If the active level is input for the SSLn0 input signal of the SPI in multi-master mode, the SPI
detects a mode fault error regardless of the status of the serial transfer, and sets the SPSR.MODF flag to 1. On detecting
the mode fault error, the SPI copies the value of the SPCMDm pointer to the SPSSR.SPECM[2:0] bits. The active level
of the SSLn0 signal is determined by the SSLP.SSL0P bit.
When the MSTR bit is 0, the SPI operates in slave mode. The SPI detects a mode fault error if the MODFEN bit of the
SPI in slave mode is 1, and the SPMS bit is 0, and if the SSLn0 input signal is negated during the serial transfer period
(from the time the driving of valid data is started to the time the final valid data is fetched).
On detecting a mode fault error, the SPI stops the driving of output signals and clears the SPCR.SPE bit to 0 (see section
36.3.9, Initializing the SPI). For multi-master configuration, detection of a mode fault error is used to stop the driving of
output signals and the SPI function, which allows the master to be released.
The occurrence of a mode fault error can be checked either by reading SPSR or by using an SPI error interrupt and
reading SPSR. SPSR polling is required for detecting mode fault errors if the SPI error interrupt is not used. When using
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36. Serial Peripheral Interface (SPI)
the SPI in master mode, the value of the SPCMDm pointer at the error occurrence can be checked by reading the
SPSSR.SPECM[2:0] bits.
When the MODF flag is 1, writing 1 to the SPE bit is ignored by the SPI. To enable the SPI function after the detection of
a mode fault error, the MODF flag must be set to 0.
36.3.8.4
Underrun errors
When the serial transfer begins while the SPCR.MSTR bit is 0 (slave mode), the SPCR.SPE bit is 1 and the transmission
data not prepared, the SPI detects an underrun error. Then, SPI sets the SPSR.MODF and SPSR.UDRF flags to 1.
On detecting an underrun error, the SPI stops the driving of output signals and clears the SPCR.SPE bit to 0 (see section
36.3.9, Initializing the SPI).
The occurrence of an underrun error can be checked either by reading SPSR or by using an SPI error interrupt and
reading SPSR. SPSR polling is required for detecting underrun errors if the SPI error interrupt is not used.
When the MODF flag is 1, writing 1 to the SPE bit is ignored by the SPI. To enable the SPI function after the detection of
an underrun error, the MODF flag must be cleared to 0.
36.3.9
Initializing the SPI
If 0 is written to the SPCR.SPE bit or the SPI sets the SPE bit to 0 because of the detection of a mode fault error or an
underrun error, the SPI disables the SPI function and initializes some of the module functions. When a system reset is
generated, the SPI initializes all of the module functions. This section describes initialization by clearing of the
SPCR.SPE bit and by a system reset.
36.3.9.1
Initialization by clearing of the SPE bit
When the SPCR.SPE bit is set to 0, the SPI performs the following initialization:
Suspends any serial transfer that is being executed
Stops the driving of output signals (Hi-Z) in slave mode
Initializes the internal state of the SPI
Initializes the transmit buffer of the SPI (the SPSR.SPTEF flag is set to 1).
Initialization by clearing of the SPE bit does not initialize the control bits of the SPI. For this reason, the SPI can be
started in the same transfer mode that is in use prior to initialization when the SPE bit is set to 1 again.
The SPSR.SPRF, SPSR.OVRF, SPSR.MODF, SPSR.PERF, and SPSR.UDRF flags are not initialized, and the value of
the SPI Sequence Status Register (SPSSR) is not initialized. Therefore, even after the SPI is initialized, data from the
receive buffer can be read to check the status of error occurrence during an SPI transfer.
The transmit buffer is initialized to an empty state (the SPSR.SPTEF flag is set to 1). Therefore, if the SPCR.SPTIE bit is
set to 1 after SPI initialization, a transmit buffer empty interrupt is generated. To disable any transmit buffer empty
interrupts when the SPI is initialized, write 0 to the SPTIE bit at the same time as writing 0 to the SPE bit.
36.3.9.2
System reset
An initialization by a system reset completely initializes the SPI by initializing all the SPI control bits, status bits, and
data registers, in addition to meeting the requirements described in section 36.3.9.1, Initialization by clearing of the SPE
bit.
36.3.10
36.3.10.1
SPI Operation
Master mode operation
The only difference between single- and multi-master mode operation lies in mode fault error detection (see section
36.3.8, Error Detection). The SPI does not detect mode fault errors in single master mode and does so in multi-master
mode. This section explains the operations that are the same for single- and multi-master modes.
(1)
Starting a serial transfer
The SPI updates the data in the transmit buffer (SPTX) when data is written to the SPI Data Register (SPDR/SPDR_HA)
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36. Serial Peripheral Interface (SPI)
and the SPI transmit buffer is empty (data for the next transfer is not set and the SPSR.SPTEF flag is 1). When the shift
register is empty after the number of frames set in the SPDCR.SPFC[1:0] bits are written to the SPDR/SPDR_HA, the
SPI copies data from the transmit buffer to the shift register and starts serial transfer. On copying transmit data to the shift
register, the SPI changes the status of the shift register to full. On termination of the serial transfer, it changes the status
of the shift register to empty. The status of the shift register cannot be referenced.
The polarity of the SSLni output pins depends on the SSLP register settings. For details on the SPI transfer format, see
section 36.3.5, Transfer Formats.
(2)
Terminating a serial transfer
Regardless of the SPCMDm.CPHA bit setting, the SPI terminates the serial transfer after transmitting an RSPCKn edge
corresponding to the final sampling timing. If free space is available in the receive buffer (SPRX) (the SPSR.SPRF flag
is 0), on termination of the serial transfer, the SPI copies data from the shift register to the receive buffer of the
SPDR/SPDR_HA register.
The final sampling timing varies depending on the bit length of transfer data. In master mode, the SPI data length
depends on the SPCMDm.SPB[3:0] bit setting. The polarity of the SSLni output pin depends on the SSLP register
settings. For details on the SPI transfer format, see section 36.3.5, Transfer Formats.
(3)
Sequence control
The transfer format used in master mode is determined by the SPSCR, SPCMDm, SPBR, SPCKD, SSLND, and SPND
registers.
The SPSCR register determines the sequence configuration for serial transfers that are executed by the SPI in master
mode. The following items are set in the SPCMDm register:
SSLni pin output signal value
MSB- or LSB-first
Data length
Some of the bit rate settings
RSPCK polarity and phase
Whether SPCKD is to be referenced
Whether SSLND is to be referenced
Whether SPND is to be referenced.
SPBR holds some of the bit rate settings, including SPCKD (SPI clock delay), SSLND (SSL negation delay), and SPND
(next-access delay).
Based on the sequence length assigned in SPSCR, the SPI makes up a sequence comprised of a part or all of the
SPCMDm register. The SPI contains a pointer to the SPCMDm register that makes up the sequence. The value of this
pointer can be checked by reading the SPSSR.SPCP[2:0] bits. When the SPCR.SPE bit is set to 1 and the SPI function is
enabled, the SPI loads the pointer to the commands in SPCMD0, and incorporates the SPCMD0 settings into the transfer
format at the beginning of serial transfer. The SPI increments the pointer each time the next-access delay period for a
data transfer ends. On completion of the serial transfer that corresponds to the final command in the sequence, the SPI
sets the pointer to SPCMD0, and in this way the sequence is executed repeatedly.
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Sequence length setting
36. Serial Peripheral Interface (SPI)
Determining of reference command
Loading of transfer format settings
SPSCR
Command
pointer control
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
SPCMD6
SPCMD7
CPHA
CPOL
BRDV[1:0]
SSLA[2:0]
SSLKP
SPB[3:0]
LSBF
SLNDEN
SCKDEN
SPCKD
SPNDEN
SSLND
SPND
Transfer format determiner
Figure 36.32
Procedure for determining the form of a serial transfer in master mode
In this section, a frame is the combination of the data in SPDR/SPDR_HA and the settings in SPCMDm.
Data
(SPDR/SPDR_HA)
+
Settings
(SPCMD)
Figure 36.33
Frame
Data
Settings
Conceptual diagram of frames
Figure 36.34 shows the correspondence between the commands and the transmit and receive buffers in the sequence of
operations specified by the settings in Table 36.4.
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Setting 1-1
36. Serial Peripheral Interface (SPI)
SPTX0/SPRX0
SPCMD0
Only 1 frame
Setting 1-2
Setting 1-3
SPTX0/SPRX0
SPTX1/SPRX1
SPCMD0
SPCMD0
1st frame
2nd frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPCMD0
SPCMD0
SPCMD0
1st frame
2nd frame
3rd frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPTX3/SPRX3
SPCMD0
SPCMD0
SPCMD0
SPCMD0
1st frame
2nd frame
3rd frame
4th frame
SPTX0/SPRX0
SPTX1/SPRX1
SPCMD0
SPCMD1
1st frame
2nd frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPTX3/SPRX3
SPCMD0
SPCMD1
SPCMD0
SPCMD1
1st frame
2nd frame
3rd frame
4th frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPCMD0
SPCMD1
SPCMD2
1st frame
2nd frame
3rd frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPTX3/SPRX3
SPCMD0
SPCMD1
SPCMD2
SPCMD3
1st frame
2nd frame
3rd frame
4th frame
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
1st frame
2nd frame
3rd frame
4th frame
5th frame
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
SPCMD6
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
7th frame
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
SPCMD6
SPCMD7
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
7th frame
8th frame
Setting 1-4
Setting 2-1
Setting 2-2
Setting 3
Setting 4
Setting 5
Setting 6
Setting 7
Setting 8
Figure 36.34
Correspondence between SPI Command register and transmit and receive buffers in sequence
operations
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(4)
36. Serial Peripheral Interface (SPI)
Burst transfers
If the SPCMDm.SSLKP bit that the SPI references during the current serial transfer is 1, the SPI maintains the SSLni
signal level during the serial transfer until the beginning of the SSLni signal assertion for the next serial transfer. If the
SSLni signal level for the next serial transfer is the same as the SSLni signal level for the current serial transfer, the SPI
can execute continuous serial transfers while keeping the SSLni signal assertion status (burst transfer).
Figure 36.35 shows an example of an SSLni signal operation for a burst transfer that is implemented using the SPCMD0
and SPCMD1 register settings. This section describes SPI operations (1) to (7) shown in Figure 36.35.
Note:
The polarity of the SSLni output signal depends on the SSLP register settings.
RSPCKn
(CPHA = 1,
CPOL = 0)
SSLni
(1)
Figure 36.35
(2)
(3)
(4)
(5)
(6)
(7)
Example of burst transfer operation using the SSLKP bit
The SPI operation at times (1) to (7) in the figure is as follows:
1. Based on the SPCMD0 settings, the SPI asserts the SSLni signal and inserts RSPCK delays.
2. The SPI executes serial transfers in accordance with the SPCMD0 settings.
3. The SPI inserts an SSL negation delay.
4. Because the SPCMD0.SSLKP bit is 1, the SPI keeps the SSLni signal value specified in SPCMD0. This period is
sustained at a minimum for a period equal to the next-access delay in SPCMD0. If the shift register is empty after
the passage of the minimum period, this period is sustained until the transmit data is stored in the shift register for
the next transfer.
5. Based on the SPCMD1 settings, the SPI asserts the SSLni signal and inserts RSPCK delays.
6. The SPI executes serial transfers in accordance with the SPCMD1 settings.
7. Because the SPCMD1.SSLKP bit is 0, the SPI negates the SSLni signal. In addition, a next-access delay is inserted
in accordance with SPCMD1.
If the SSLni signal output settings in the SPCMDm register where 1 is assigned to the SSLKP bit are different from the
SSLni signal output settings in the SPCMDm register to be used in the next transfer, the SPI switches the SSLni signal
status to SSLni signal assertion as shown in (5) in Figure 36.35. This corresponds to the command for the next transfer.
Note:
If such an SSLni signal switching occurs, the slaves that drive the MISOn signal compete, and the collision of
signal levels might occur.
The SPI in master mode references the SSLni signal operation within the module when the SSLKP bit is not used. When
the SPCMDm.CPHA bit is 0, the SPI can accurately start serial transfers by using the SSLni signal assertion for the next
transfer that is detected internally.
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36. Serial Peripheral Interface (SPI)
RSPCK delay (t1)
The RSPCK delay value of the SPI in master mode depends on the SPCMDm.SCKDEN bit setting and the SPCKD
register setting. The SPI determines the SPCMDm register to be referenced during a serial transfer by pointer control,
and determines the RSPCK delay value by using the SPCMDm.SCKDEN bit and SPCKD, as listed in Table 36.9. For a
definition of the RSPCK delay, see section 36.3.5, Transfer Formats.
Table 36.9
Relationship among the SCKDEN bit, SPCKD register, and RSPCK delay
SPCMDm.SCKDEN bit
SPCKD.SCKDL[2:0] bits
RSPCK delay
0
000b to 111b
1 RSPCK
1
000b
1 RSPCK
001b
2 RSPCK
010b
3 RSPCK
011b
4 RSPCK
100b
5 RSPCK
101b
6 RSPCK
(6)
110b
7 RSPCK
111b
8 RSPCK
SSL negation delay (t2)
The SSL negation delay value of the SPI in master mode depends on the SPCMDm.SLNDEN bit setting and the SSLND
register setting. The SPI determines the SPCMDm register to be referenced by pointer control during a serial transfer,
and determines the SSL negation delay by using the SPCMDm.SLNDEN bit and SSLND, as listed in Table 36.10. For a
definition of the SSL negation delay, see section 36.3.5, Transfer Formats.
Table 36.10
Relationship among the SLNDEN bit, SSLND, and SSL negation delay
SPCMDm.SLNDEN bit
SSLND.SLNDL[2:0] bits
SSL negation delay
0
000b to 111b
1 RSPCK
1
000b
1 RSPCK
001b
2 RSPCK
010b
3 RSPCK
011b
4 RSPCK
100b
5 RSPCK
101b
6 RSPCK
(7)
110b
7 RSPCK
111b
8 RSPCK
Next-access delay (t3)
The next-access delay value of the SPI in master mode depends on the SPCMDm.SPNDEN bit setting and the SPND
register setting. The SPI determines the SPCMDm register to be referenced during serial transfer by pointer control, and
determines the next-access delay during serial transfer by using the SPCMDm.SPNDEN bit and SPND, as listed in Table
36.11. For a definition of the next-access delay, see section 36.3.5, Transfer Formats.
Table 36.11
Relationship among the SPNDEN bit, SPND, and next-access delay (1 of 2)
SPCMDm.SPNDEN bit
SPND.SPNDL[2:0] bits
Next-access delay
0
000b to 111b
1 RSPCK + 2 PCLKA
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Table 36.11
36. Serial Peripheral Interface (SPI)
Relationship among the SPNDEN bit, SPND, and next-access delay (2 of 2)
SPCMDm.SPNDEN bit
SPND.SPNDL[2:0] bits
Next-access delay
1
000b
1 RSPCK + 2 PCLKA
001b
2 RSPCK + 2 PCLKA
010b
3 RSPCK + 2 PCLKA
011b
4 RSPCK + 2 PCLKA
100b
5 RSPCK + 2 PCLKA
101b
6 RSPCK + 2 PCLKA
110b
7 RSPCK + 2 PCLKA
111b
8 RSPCK + 2 PCLKA
(8)
Initialization flow
Figure 36.36 shows an example of initialization flow for the SPI operation when the SPI is used in master mode. For a
description of how to set up the Interrupt Controller Unit (ICU), DMAC, and I/O ports, see the descriptions given in the
individual blocks.
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36. Serial Peripheral Interface (SPI)
Start of initialization in
master mode
Set SPI Slave Select Polarity
Register (SSLP)
• Sets polarity of SSL signal
Set SPI Pin Control Register
(SPPCR)
• Sets output mode (CMOS/open-drain)
• Sets MOSI signal value when transfer is in idle state
Set SPI Bit Rate Register (SPBR)
• Sets transfer bit rate
Set SPI Data Control Register
(SPDCR)
• Sets number of frames to be used
Set SPI Clock Delay Register
(SPCKD)
• Sets RSPCK delay
Set SPI Slave Select Negation
Delay Register (SSLND)
• Sets SSL negation delay
Set SPI Next-Access Delay Register
(SPND)
• Sets next-access delay
Set SPI Control Register 2 (SPCR2)
• Sets parity function
• Sets interrupt mask
SPI Sequence Control Register
(SPSCR)
Set SPI Command Registers 0 to 7
(SPCMD0 to SPCMD7)
• Sets sequence length
• Sets SSL signal level
• Enables RSPCK delay
• Enables SSL negation delay
• Enables next-access delay
• Sets MSB or LSB first
• Sets data length
• Sets transfer bit rate
• Sets clock phase
• Sets clock polarity
• Sets SSL assertion signal
Set Interrupt Controller Unit (ICU)
(When using interrupts)
Set DMAC
(When using the DMAC)
Set I/O ports
Set SPI Control Register (SPCR)
• Sets master mode
• Sets interrupt mask
• Sets SPI mode
Read SPI Control Register (SPCR)
End of initialization in
master mode
Figure 36.36
Example of initialization flow in master mode for SPI operation
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36. Serial Peripheral Interface (SPI)
Software processing flow
Figure 36.37 to Figure 36.39 show examples of the software processing flow.
(a)
Transmit processing flow
When transmitting data and when the SPIi_SPII interrupt is enabled, the CPU is notified of the completion of data
transmission after the last writing of data for transmission.
Processing for transmission
Start processing
for transmission
Pre-transfer processing
End of initial settings
SPIi_SPTI interrupt ?
or
SPSR.SPTEF = 1? *1
Clear SPSR.MODF, OVRF,
PERF and UDRF flags
[1] Clear error sources
Yes
Write data for transmission to
SPDR/SPDR_HA
[2] Disable SPIi_SPII interrupts
Set SPCR2.SPIIE = 0
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
processing for
transmission
[3] Set the SPE bit to enabled.
Enable the required interrupts at the
same time.
Using interrupts is prohibited if the
user uses the flag for polling
Proceed to
processing for
reception
Proceed to
error
processing
Note 1. Before writing data for transmission to SPDR/
SPDR_HA, check that the transmit buffer is empty
by reading the SPSR.SPTEF flag, if the flag for
polling is used.
Note 2. Setting the idle interrupt is prohibited
(SPCR2.SPIIE = 0) if the flag for polling is
used.
Note 3. Wait more than 1 PCLKA after writing data for
transmission to SPDE and before starting to
poll PSR.IDLNF if the flag for polling is used.
Figure 36.37
(b)
No
Has the last of the
data been written?
[4] [4] Access when interrupt handling
routine is executed once to the
number of frames set in
No
SPDCR.SPFC[1:0]
Yes
SPCR.SPTIE = 0,
SPCR2.SPIIE
=1
Yes
or
SPCR.SPTIE = 0,
*2
SPCR2.SPIIE = 0
SPIi_SPII interrupt?
or
SPSR.IDLNF = 0?*3
No
Yes
SPCR.SPE = 0,
SPCR2.SPIIE = 0
End of
processing for
transmission
Transmission flow in master mode
Receive processing flow
The SPI does not handle receive-only operation, so processing for transmission is required.
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36. Serial Peripheral Interface (SPI)
Pre-transfer processing
Processing for reception
Start processing
for reception
End of initial settings
Clear SPSR.MODF, OVRF,
PERF and UDRF flags
[1] Clear error sources
SPIi_SPRI interrupt?
or
SPSR.SPRF = 1?
No
Yes
Set SPCR2.SPIIE = 0
[2] Disable SPIi_SPII interrupts
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
processing for
transmission
[3] Set the SPE bit to enabled.
Enable the required interrupts at
the same time.
Using interrupts is prohibited if the
user uses the flag for polling
Proceed to
processing for
reception
Proceed to
error
processing
Read receive data from SPDR/
SPDR_HA
Has the last of the
data been read?
(c)
[4] Access when routine is executed
once to the number of frames set in
SPDCR.SPFC[1:0]
No
Yes
SPCR.SPRIE = 0
End of
processing for
reception
Figure 36.38
[4]
[5] Prohibition of operation is handled by
processing for transmission
Reception flow in master mode
Error processing flow
The SPI detects mode fault errors, underrun errors, overrun errors, and parity errors. When a mode fault error is
generated, the SPCR.SPE bit is automatically cleared, stopping operations for transmission and reception. For errors
from other sources, the SPCR.SPE bit is not cleared and operations for transmission and reception continue. Therefore,
Renesas recommends clearing the SPCR.SPE bit to stop operations for errors other than mode fault errors. Not doing so
leads to the updating of the SPSSR.SPECM[2:0] bits.
When an error is detected by using an interrupt, clear the ICU.IELSRn.IR flag in the error processing routine. If this is
not done, the ICU.IELSRn.IR flag might continue to indicate the SPIi_SPTI or SPIi_SPRI interrupt request. If the
SPIi_SPRI interrupt request is indicated, read the receive buffer and initialize the sequencer in the SPI.
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36. Serial Peripheral Interface (SPI)
Error processing
Pre-transfer processing
Start error
processing
End of initial settings
Clear SPSR.MODF, OVRF,
PERF and UDRF flags
[1] Clear error sources
SPIi_SPEI interrupt?
or
SPSR.MODF/OVRF/PERF/UDRF
= 1?
No
Yes
Set SPCR2.SPIIE = 0
[2] Disable SPIi_SPII interrupts
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
processing for
transmission
[3] Set the SPE bit to enabled.
Enable the required interrupts at
the same time.
Using interrupts is prohibited if
the user uses the flag for polling
Proceed to
processing for
reception
Proceed to
error
processing
SPSR.MODF = 0?
No
Yes
SSLn0 = inactive?
SPCR.SPE = 0
[4]
Set SPCR.SPTIE = 0,
SPRIE = 0, SPEIE = 0,
and SPCR2.SPIIE = 0
Error processing
No
[4] Read port register and confirm that
SSLn0 pin is at the inactive level.
[5]
[5] Clear ICU.IELSRn.IR flag
corresponding to SPIi_SPTI,
SPIi_SPRI
Clear SPSR.MODF, OVRF,
PERF and UDRF flags
Repeat transfer processing
End of error
processing
Figure 36.39
[6] Run initialization and other processing again
Processing order can be changed
Error processing flow in master mode
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36.3.10.2
(1)
36. Serial Peripheral Interface (SPI)
Slave mode operation
Starting a serial transfer
When the SPCMD0.CPHA bit is 0, if the SPI detects an SSLn0 input signal assertion, it must drive valid data to the
MISOn output signal. For this reason, when the CPHA bit is 0, the assertion of the SSLn0 input signal triggers the start of
a serial transfer.
When the CPHA bit is 1, if the SPI detects the first RSPCKn edge in an SSLn0 signal asserted condition, it must drive
valid data to the MISOn output signal. For this reason, when the CPHA bit is 1, the first RSPCKn edge in an SSLn0
signal asserted condition triggers the start of a serial transfer.
Regardless of the CPHA bit setting, the SPI drives the MISOn output signal on SSLn0 signal assertion. The data that is
output by the SPI is either valid or invalid, depending on the CPHA bit setting.
For details on the SPI transfer format, see section 36.3.5, Transfer Formats. The polarity of the SSLn0 input signal
depends on the SSLP.SSL0P setting.
(2)
Terminating a serial transfer
Regardless of the SPCMD0.CPHA bit setting, the SPI terminates the serial transfer after detecting an RSPCKn edge
corresponding to the final sampling timing. When free space is available in the receive buffer (the SPSR.SPRF flag is 0),
on the termination of serial transfer, the SPI copies the received data from the shift register to the receive buffer of the
SPDR/SPDR_HA register. On termination of a serial transfer, the SPI changes the status of the shift register to empty,
regardless of the receive buffer state. A mode fault error occurs if the SPI detects an SSLn0 input signal negation from
the beginning of the serial transfer to the end of the serial transfer (see section 36.3.8, Error Detection).
The final sampling timing changes depending on the bit length of the transfer data. In slave mode, the SPI data length is
determined by the SPCMD0.SPB[3:0] bit setting. The polarity of the SSLn0 input signal is determined by the
SSLP.SSL0P bit setting. For details on the SPI transfer format, see section 36.3.5, Transfer Formats.
(3)
Notes on single slave operations
If the SPCMD0.CPHA bit is 0, the SPI starts serial transfers when it detects the assertion edge for an SSLn0 input signal.
In the type of configuration shown in Figure 36.7, for example, if the SPI is used in single slave mode, the SSLn0 signal
is fixed at the active state. Therefore, when the CPHA bit is set to 0, the SPI cannot correctly start a serial transfer. To
correctly execute transmit and receive operations by the SPI in slave mode when the SSLn0 input signal is fixed at the
active state, the CPHA bit must be set to 1. Do not fix the SSLn0 input signal if there is a requirement for setting the
CPHA bit to 0.
(4)
Burst transfer
If the SPCMD0.CPHA bit is 1, continuous serial transfer (burst transfer) can be executed while retaining the assertion
state for the SSLn0 input signal. When the CPHA bit is 1, the serial transfer period is the period from the first RSPCKn
edge to the sampling timing for the reception of the final bit in an SSLn0 signal active state. Even when the SSLn0 input
signal remains at the active level, the SPI can accommodate burst transfers because it can detect the start of an access.
When the CPHA bit is 0, the second and subsequent serial transfers during burst transfer cannot be executed correctly.
(5)
Initialization flow
Figure 36.40 shows an example of initialization flow for SPI operation when the SPI is used in slave mode. For a
description of how to set up the ICU, DMAC, and I/O ports, see the descriptions given in the individual blocks.
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36. Serial Peripheral Interface (SPI)
Start of initialization in
slave mode
Set SPI Slave Select Polarity
Register (SSLP)
• Sets polarity of SSLn0 input signal
Set SPI Data Control Register
(SPDCR)
• Sets number of frames to be used
Set SPI Control Register 2 (SPCR2)
• Sets parity function
• Sets interrupt mask
Set SPI Command Register 0
(SPCMD0)
• Sets MSB or LSB first
• Sets data length
• Sets clock phase
• Sets clock polarity
Set Interrupt Controller Unit (ICU)
(When using interrupts)
Set DMAC
(When using the DMAC)
Set I/O ports
Set SPI Control Register (SPCR)
• Sets slave mode
• Sets mode fault error detection
• Sets interrupt mask
• Sets SPI mode
Read SPI Control Register (SPCR)
End of initialization in
slave mode
Figure 36.40
Example initialization flow in slave mode for SPI operation
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(6)
36. Serial Peripheral Interface (SPI)
Software processing flow
Figure 36.41 to Figure 36.43 show examples of the flow of software processing.
(a)
Transmit processing flow
Pre-transfer processing
Processing for transmission
Start processing
for transmission
End of initial settings
Clear SPSR.MODF, OVRF,
UDRF, and PERF flags
[1] Clear error sources
[2] Disable SPIi_SPII interrupts
Set SPCR2.SPIIE = 0
[3] Set the SPE bit to enabled.
Enable the required interrupts at the
same time.
Using the interrupt is prohibited if
the user uses the flag for polling
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
processing for
transmission
Proceed to
processing for
reception
Proceed to
error
processing
No
SPIi_SPTI interrupt?
or
SPSR.SPTEF = 1? *1
Yes
Write data for transmission to
SPDR/SPDR_HA
Has the last of the
data been written?
[4]
[4] Access when routine is executed
once to the number of frames set
in SPDCR.SPFC[1:0]
No
Yes
End of
processing for
transmission
Note 1. Proceed to processing for writing data for
transmission to SPDR/SPDR_HA after checking
transmit buffer empty by reading SPSR.SPTEF flag
if the user uses the flag for polling.
Figure 36.41
(b)
Transmission flow in slave mode
Receive processing flow
The SPI does not handle receive-only operation, so processing for transmission is required.
Pre-transfer processing
Processing for reception
Start processing
for reception
End of initial settings
Clear the SPSR.MODF, OVRF,
UDRF, and PERF flags
[1] Clear error sources
SPIi_SPRI interrupt?
or
SPSR.SPRF = 1?
No
Yes
Set SPCR2.SPIIE = 0
[2] Disable SPIi_SPII interrupts
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
processing for
transmission
[3] Set the SPE bit to enabled.
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the user uses the flag for polling
Proceed to
processing for
reception
Proceed to
error
processing
Read receive data from SPDR/
SPDR_HA
[4]
Has the last of the
data been read?
No
[4] Access when routine is executed
once to the number of frames set in
SPDCR.SPFC[1:0].
Yes
SPCR.SPRIE = 0
End of
processing for
reception
Figure 36.42
Reception flow in slave mode
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(c)
36. Serial Peripheral Interface (SPI)
Error processing flow
In slave operation, even when a mode fault error is generated, the SPSR.MODF flag can be cleared regardless of the state
of the SSLn0 pin.
When an error is detected by using an interrupt, clear the ICU.IELSRn.IR flag in the error processing routine. If this is
not done, the ICU.IELSRn.IR flag might continue to indicate the SPIi_SPTI or SPIi_SPRI interrupt request. If the
SPIi_SPRI interrupt request is indicated, read the receive buffer and initialize the sequencer in the SPI.
Error processing
Pre-transfer processing
Start error
processing
End of initial settings
Clear SPSR.MODF, OVRF,
UDRF, and PERF flags
[1] Clear error sources
SPIi_SPEI interrupt?
or
SPSR.MODF/OVRF/PERF
= 1?
No
Yes
Set SPCR2.SPIIE = 0
[2] Disable SPIi_SPII interrupts
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
processing for
transmission
[3] Set the SPE bit to enabled.
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the user uses the flag for polling
Proceed to
processing for
reception
Proceed to
error
processing
SPSR.MODF = 0?
No
Yes
SPCR.SPE = 0
Set SPCR.SPTIE = 0,
SPRIE = 0, SPEIE = 0,
and SPCR2.SPIIE = 0
Error processing
[4]
[4] Clear ICU.IELSRn.IR flag
corresponding to SPIi_SPTI,
SPIi_SPRI
Clear SPSR.MODF, UDRF,
OVRF, and PERF flags
Repeat transfer processing
End of error
processing
Figure 36.43
36.3.11
[5] Run initialization and other processing again
Processing order can be changed
Error processing flow for slave mode
Clock Synchronous Operation
Setting the SPCR.SPMS bit to 1 selects clock synchronous operation of the SPI. In clock synchronous operation, the
SSLni pin is not used, and the RSPCKn, MOSIn, and MISOn pins handle the communication. All SSLni pins are
available as I/O port pins.
Although clock synchronous operation does not require the use of the SSLni pin, operation of the module is the same as
in SPI operation. In both master and slave operations, communications can be performed with the same flow as in SPI
operation. However, mode fault errors are not detected because the SSLni pin is not used.
Additionally, do not perform operation if the clock synchronous operation is enabled when the SPCMDm.CPHA bit is
set to 0 in slave mode (SPCR.MSTR = 0).
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36.3.11.1
(1)
36. Serial Peripheral Interface (SPI)
Master mode operation
Starting serial transfer
The SPI updates the data in the transmit buffer (SPTX) of SPDR/SPDR_HA when data is written to the
SPDR/SPDR_HA register and the transmit buffer is empty (data for the next transfer is not set and the SPSR.SPTEF flag
is 1). When the shift register is empty after the number of frames set in the SPDCR.SPFC[1:0] bits are written to the
SPDR/SPDR_HA, the SPI copies data from the transmit buffer to the shift register and starts serial transmission. On
copying transmit data to the shift register, the SPI changes the status of the shift register to full, and on termination of
serial transfer, it changes the status of the shift register to empty. The status of the shift register cannot be referenced.
Transfer in clock synchronous operation is conducted without the SSLn0 output signal. For details on the SPI transfer
format, see section 36.3.5, Transfer Formats.
(2)
Terminating serial transfer
The SPI terminates the serial transfer after transmitting an RSPCKn edge corresponding to the sampling timing. If free
space is available in the receive buffer (the SPSR.SPRF flag is 0), on termination of serial transfer, the SPI copies data
from the shift register to the receive buffer of the SPI Data Register (SPDR/SPDR_HA).
The final sampling timing varies depending on the bit length of transfer data. In master mode, the SPI data length
depends on the SPCMDm.SPB[3:0] bit setting. Transfer in clock synchronous operation is conducted without the SSLn0
output signal. For details on the SPI transfer format, see section 36.3.5, Transfer Formats.
(3)
Sequence control
The transfer format used in master mode is determined by the SPSCR, SPCMDm, SPBR, SPCKD, SSLND, and SPND
registers. Although the SSLni signals are not output in clock synchronous operation, these settings are valid.
The SPSCR register determines the sequence configuration for serial transfers that are executed by the SPI in master
mode. The following parameters are specified in the SPCMDm register:
SSLni output signal value
MSB or LSB first
Data length
Some of the bit rate settings
RSPCKn polarity and phase
Whether SPCKD is to be referenced
Whether SSLND is to be referenced
Whether SPND is to be referenced.
SPBR holds some of the bit rate settings such as SPCKD, an SPI clock delay value, SSLND, an SSL negation delay, and
SPND, a next-access delay value.
Based on the sequence length that is assigned to SPSCR, the SPI makes up a sequence comprised of a part or all of
SPCMDm register. The SPI contains a pointer to the SPCMDm register that makes up the sequence. The value of this
pointer can be checked by reading the SPSSR.SPCP[2:0] bits. When the SPCR.SPE bit is set to 1 and the SPI function is
enabled, the SPI loads the pointer to the commands in SPCMD0 register, and incorporates the SPCMD0 register setting
into the transfer format at the beginning of serial transfer. The SPI increments the pointer each time the next-access delay
period for a data transfer ends. On completion of the serial transfer that corresponds to the final command comprising the
sequence, the SPI sets the pointer to the SPCMD0 register, and in this manner the sequence is executed repeatedly.
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Sequence length
setting
36. Serial Peripheral Interface (SPI)
Determining
reference command
Loading transfer format settings
SPSCR
Command
pointer control
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
SPCMD6
SPCMD7
CPHA
CPOL
BRDV[1:0]
SSLA[2:0]
SSLKP
SPB[3:0]
LSBF
SCKDEN
SPCKD
SLNDEN
SSLND
SPNDEN
SPND
Transfer format determiner
Figure 36.44
Procedure for determining the form of serial transmission in master mode
In this section, a frame is the combination of the data (SPDR/SPDR_HA) and the settings (SPCMDm).
Data
(SPDR/SPDR_HA)
+
Settings
(SPCMD)
Figure 36.45
Frame
Data
Settings
Conceptual diagram of frames
Figure 36.46 shows the relationship between the command and the transmit and receive buffers in the sequence of
operations specified by the settings in Table 36.4.
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Setting 1-1
36. Serial Peripheral Interface (SPI)
SPTX0/SPRX0
SPCMD0
Only 1 frame
Setting 1-2
Setting 1-3
SPTX0/SPRX0
SPTX1/SPRX1
SPCMD0
SPCMD0
1st frame
2nd frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPCMD0
SPCMD0
SPCMD0
1st frame
2nd frame
3rd frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPTX3/SPRX3
SPCMD0
SPCMD0
SPCMD0
SPCMD0
1st frame
2nd frame
3rd frame
4th frame
SPTX0/SPRX0
SPTX1/SPRX1
SPCMD0
SPCMD1
1st frame
2nd frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPTX3/SPRX3
SPCMD0
SPCMD1
SPCMD0
SPCMD1
1st frame
2nd frame
3rd frame
4th frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPCMD0
SPCMD1
SPCMD2
1st frame
2nd frame
3rd frame
SPTX0/SPRX0
SPTX1/SPRX1
SPTX2/SPRX2
SPTX3/SPRX3
SPCMD0
SPCMD1
SPCMD2
SPCMD3
1st frame
2nd frame
3rd frame
4th frame
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
1st frame
2nd frame
3rd frame
4th frame
5th frame
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
SPCMD6
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
7th frame
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPTX0/SPRX0
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4
SPCMD5
SPCMD6
SPCMD7
1st frame
2nd frame
3rd frame
4th frame
5th frame
6th frame
7th frame
8th frame
Setting 1-4
Setting 2-1
Setting 2-2
Setting 3
Setting 4
Setting 5
Setting 6
Setting 7
Setting 8
Figure 36.46
Correspondence between SPI Command register and transmit and receive buffers in sequence
operations
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(4)
36. Serial Peripheral Interface (SPI)
Initialization flow
Figure 36.47 shows an example of initialization flow for clock synchronous operation when the SPI is used in master
mode. For a description of how to set up the ICU, DMAC, and I/O ports, see the descriptions given in the individual
blocks.
Start of initialization in
master mode
Set SPI pin control register
(SPPCR)
Set SPI bit rate register (SPBR)
• Sets MOSI signal value when transfer is in idle state .
• Sets transfer bit rate.
Set SPI data control register
(SPDCR)
• Sets number of frames to be used .
Set SPI clock delay register
(SPCKD)
• Sets RSPCK delay value.
Set SPI slave select negation delay
register (SSLND)
• Sets SSL negation delay value.
Set SPI next-access delay register
(SPND)
• Sets next-access delay value.
Set SPI control register 2 (SPCR2)
• Sets parity function.
• Sets interrupt mask.
SPI sequence control register
(SPSCR)
Set SPI command registers 0 to 7
(SPCMD0 to SPCMD7)
• Sets sequence length.
• Sets RSPCK delay enable.
• Sets SSL negation delay enable.
• Sets next-access delay enable.
• Sets MSB or LSB first.
• Sets data length.
• Sets transfer bit rate.
• Sets clock polarity.
Set interrupt controller
(when using an interrupt)
Set DMAC
(when using the DMAC)
Set I/O ports
Set SPI control register (SPCR)
• Sets master mode.
• Sets interrupt mask.
• Sets SPI mode.
Read SPI control register (SPCR)
End of initialization in
master mode
Figure 36.47
Example of initialization flow in master mode for clock synchronous operation
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36. Serial Peripheral Interface (SPI)
Software processing flow
Software processing during clock synchronous master operation is the same as that for SPI master operation. For details,
see section 36.3.10.1, (9) Software processing flow. Mode fault errors do not occur in clock synchronous operation.
36.3.11.2
(1)
Slave mode operation
Starting serial transfer
When the SPCR.SPMS bit is 1, the first RSPCKn edge triggers the start of a serial transfer in the SPI, and the SPI drives
the MISOn output signal. The SSLn0 input signal is not used in clock synchronous operation. For details on the SPI
transfer format, see section 36.3.5, Transfer Formats.
(2)
Terminating serial transfer
The SPI terminates the serial transfer after detecting an RSPCKn edge corresponding to the final sampling timing. When
free space is available in the receive buffer (the SPSR.SPRF flag is 0), on termination of serial transfer the SPI copies
received data from the shift register to the receive buffer of the SPDR/SPDR_HA register. On termination of a serial
transfer the SPI changes the status of the shift register to empty regardless of the receive buffer.
The final sampling timing changes depending on the bit length of transfer data. In slave mode, the SPI data length
depends on the SPCMD0.SPB[3:0] bit setting. For details on the SPI transfer format, see section 36.3.5, Transfer
Formats.
(3)
Initialization flow
Figure 36.48 shows an example of initialization flow for clock synchronous operation when the SPI is used in slave
mode. For a description of how to set up the ICU, DMAC, and I/O ports, see the descriptions given in the individual
blocks.
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36. Serial Peripheral Interface (SPI)
Start of initialization in
slave mode
Set SPI Data Control Register
(SPDCR)
Set SPI Control Register 2 (SPCR2)
• Sets number of frames to be used
• Sets parity function
• Sets interrupt mask
Set SPI Command Register 0
(SPCMD0)
• Sets MSB or LSB first
• Sets data length
• Sets clock phase
• Sets clock polarity
Set Interrupt Controller Unit (ICU)
(When using interrupts)
Set DMAC
(When using the DMAC)
Set I/O ports
Set SPI Control Register (SPCR)
• Sets slave mode
• Sets interrupt mask
• Sets SPI mode
Read SPI Control Register (SPCR)
End of initialization in
slave mode
Figure 36.48
(4)
Example of initialization flow in slave mode for clock synchronous operation
Software processing flow
Software processing during clock synchronous slave operation is the same as that for SPI slave operation. For details, see
section 36.3.10.2, (6) Software processing flow. Mode fault errors do not occur in clock synchronous mode.
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36.3.12
36. Serial Peripheral Interface (SPI)
Loopback Mode
When 1 is written to the SPPCR.SPLP2 bit or SPPCR.SPLP bit, the SPI shuts off the path between the MISOn pin and
the shift register if the SPCR.MSTR bit is 1, or between the MOSIn pin and the shift register if the SPCR.MSTR bit is 0,
and connects the input and output paths of the shift register. The SPI does not shut off the path between the MOSIn pin
and the shift register if the SPCR.MSTR bit is 1, or between the MISOn pin and the shift register if the SPCR.MSTR bit
is 0. This is called loopback mode. When a serial transfer is executed in loopback mode, the transmit data for the SPI or
the reversed transmit data becomes the received data for the SPI.
Table 36.12 lists the relationship among the SPLP2 and SPLP bits and the received data. Figure 36.49 shows the
configuration of the shift register I/O paths when the SPI in master mode is set to loopback mode (SPPCR.SPLP2 = 1,
SPPCR.SPLP = 0 or 1).
Table 36.12
SPLP2 and SPLP bit settings and received data
SPPCR.SPLP2 bit
SPPCR.SPLP bit
Received data
0
0
Input data from the MOSIn pin or MISOn pin
0
1
Inverted transmit data
1
0
Transmit data
1
1
Transmit data
Transmission
(MOSIn/MISOn)
Shift register
Loopback
Loopback 2
Reception
(MISOn/MOSIn)
Figure 36.49
36.3.13
Normal
Configuration of Shift register I/O paths in loopback mode for master mode
Self-Diagnosis of Parity Bit Function
The parity circuit consists of a parity bit adding unit used for transmit data and an error detecting unit used for received
data. To detect defects in the parity bit adding unit and error detecting unit of the parity circuit, self-diagnosis is executed
for the parity circuit following the flow shown in Figure 36.50.
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36. Serial Peripheral Interface (SPI)
Start of self-diagnosis of
parity circuit
Select full-duplex synchronous serial communications (SPCR.TXMD = 0)
Enable parity circuit self-diagnosis function (SPCR2.PTE = 1)
Enable parity function (SPCR2.SPPE = 1)
Select loopback mode (SPPCR.SPLP2 = 1)
Parity error occurred
Add correct parity bit to
transmit data and transfer it
No parity error
No parity error
Add incorrect parity bit to
transmit data and transfer it
Parity error occurred
Disable the parity circuit self-diagnosis function (SPCR2.PTE = 0)
Loopback operation with
parity bit added at
normal operation
Parity error occurred
No parity error
Incorrect parity bit
added
Check data stored in
transmit data register
Correct parity bit added
Normal end
No defect in parity circuit
Figure 36.50
Erroneous end
Erroneous end
Defect found in parity bit adding unit
No defect in error detecting unit
Defect found in error
detecting unit
Self-diagnosis flow for parity circuit
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36.3.14
36. Serial Peripheral Interface (SPI)
Interrupt Sources
The SPI interrupt sources include:
Receive buffer full
Transmit buffer empty
SPI error (mode fault, underrun, overrun, or parity error)
SPI idle
Transmission-complete
The DTC or DMAC can be activated by the receive buffer full or transmit buffer empty interrupt to perform data transfer.
Because the vector address for the SPIi_SPEI (SPI error interrupt) is allocated to interrupt requests on mode fault,
underrun, overrun, and parity errors, the actual interrupt source must be determined from the flags. Interrupt sources for
the SPI are listed in Table 36.13. An interrupt is generated on satisfaction of one of the interrupt conditions in Table
36.13. Clear the receive buffer full and transmit buffer empty sources through a data transfer.
When using the DTC or DMAC to perform data transmission and reception, the DTC or DMAC must be set up first to a
transfer-enabled status before making the SPI settings. For information on setting up the DTC or DMAC, see section 17,
DMA Controller (DMAC), or section 18, Data Transfer Controller (DTC).
If the conditions for generating a transmit buffer empty or receive buffer full interrupt occur while the ICU.IELSRn.IR
flag is 1, the interrupt is not output as a request for the ICU but is retained internally (the capacity for retention is one
request per source). A retained interrupt request is output when the ICU.IELSRn.IR flag clears to 0. A retained interrupt
request is automatically discarded when it is output as an actual interrupt request. The interrupt enable bit (the
SPCR.SPTIE or SPCR.SPRIE bit) for an internally retained interrupt request can also be cleared to 0.
Table 36.13
SPI interrupt sources
Interrupt source
Symbol
Interrupt condition
DMAC or DTC activation
Receive buffer full
SPIi_SPRI
Receive buffer becomes full (SPSR.SPRF flag is 1) while
the SPCR.SPRIE bit is 1
Possible
Transmit buffer empty
SPIi_SPTI
Transmit buffer becomes empty (SPSR.SPTEF flag is 1)
while the SPCR.SPTIE bit is 1
Possible
SPI error (mode fault,
underrun, overrun, or parity
error)
SPIi_SPEI
SPSR.MODF, OVRF, PERF, or UDRF flag is set to 1
while the SPCR.SPEIE bit is 1
Impossible
SPI idle
SPIi_SPII
SPSR.IDLNF flag clears to 0 while the SPCR2.SPIIE bit
is 1
Impossible
Transmission-complete
SPIi_SPTEND
Master mode: Interrupt is generated when the IDLNF
flag (SPI idle flag) changes from 1 to 0
Slave mode: interrupt occurs on conditions shown in
Table 36.15
Impossible
36.4
Output to the Event Link Controller (ELC)
The ELC can produce the following event output signals:
Receive buffer full event output
Transmit buffer empty event output
Mode-fault, underrun, overrun, or parity error event output
SPI idle event output
Transmission-completed event output.
The event link output signal is output regardless of the interrupt enable bit setting.
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36.4.1
36. Serial Peripheral Interface (SPI)
Receive Buffer Full Event Output
This event signal is output when received data is transferred from the shift register to the SPDR/SPDR_HA on
completion of serial transfer.
36.4.2
Transmit Buffer Empty Event Output
This event signal is output when data for transmission is transferred from the transmit buffer to the shift register and
when the value of the SPE bit changes from 0 to 1.
36.4.3
Mode-Fault, Underrun, Overrun, or Parity Error Event Output
This event signal is output when mode fault, underrun, overrun, or parity error is detected. See section 36.5.4,
Constraints on Mode-Fault, Underrun, Overrun, or Parity Error Event Output if using this event signal.
(1)
Mode-fault
Table 36.14 lists the conditions for occurrence of a mode-fault event.
Table 36.14
Conditions for mode fault occurrence
SPI mode
SPCR.MODFEN bit
SSLn0 pin
Remarks
SPI operation (SPMS = 0)
Slave (SPCR.MSTR bit = 0)
1
Not active
Event is output only when the pin is deactivated during
transmission
(2)
Underrun
This event signal is output in response to an underrun when a serial transfer starts while the transmission data is not
ready, and the value of the SPCR.MSTR bit is 0 and the SPCR.SPE bit is 1. Under these conditions, the MODF and
UDRF flags set to 1.
(3)
Overrun
This event signal is output in response to an overrun when a serial transfer completes while the receive buffer contains
unread data and the value of the SPCR.TXMD bit is 0. Under these conditions, the OVRF flag is set to 1.
(4)
Parity error
This event signal is output in response to a parity error detected on the completion of a serial transfer while the value of
the TXMD bit in SPCR is 0 and the value of the SPPE bit in SPCR2 is 1.
36.4.4
(1)
SPI Idle Event Output
In master mode
In master mode, an event is output when the condition for setting the IDLNF flag (SPI idle flag) to 0 is satisfied.
(2)
In slave mode
In slave mode, an event is output when the SPCR.SPE bit is set to 0 (SPI is initialized).
36.4.5
Transmission-Completed Event Output
During both SPI operation and clock synchronous operation in master mode, an event is output when the IDLNF flag
(SPI idle flag) changes from 1 to 0. Table 36.15 lists the conditions for occurrence of a transmission-completed event in
slave mode.
Table 36.15
Conditions for generation of transmission-complete event in slave mode
SPI mode
Transmit buffer state
Shift register state
Other
SPI operation (SPMS = 0)
Empty
Empty
Negation of SSLn0 input
Clock synchronous operation
(SPMS = 1)
Empty
Empty
Edge detection of the last RSPCKn
Whether the operation is in master mode or slave mode, an event is not output if 0 is written to the SPCR.SPE bit in
transmission or the SPCR.SPE bit is cleared by the mode-fault error or the underrun error.
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36.5
36.5.1
36. Serial Peripheral Interface (SPI)
Usage Notes
Settings for the Module-Stop Function
SPI operation can be disabled or enabled using Module Stop Control Register B (MSTPCRB). The SPI is initially
stopped after reset. Releasing the module-stop state enables access to the registers. For details, see section 11, Low
Power Modes.
36.5.2
Constraint on Low Power Functions
When using the module-stop function and entering a low power mode other than Sleep, set the SPCR.SPE bit to 0 before
completing communication.
36.5.3
Constraints on Starting Transfer
If the ICU.IELSRn.IR flag is 1 when transfer starts, the interrupt request is internally saved, which can lead to
unanticipated behavior of the ICU.IELSRn.IR flag.
To prevent this, use the following procedure to clear interrupt requests before enabling operations (by setting the
SPCR.SPE bit to 1):
1. Confirm that the transfer stopped (the SPCR.SPE bit is 0).
2. Set the associated interrupt enable bit (SPCR.SPTIE or SPCR.SPRIE) to 0.
3. Read the associated interrupt enable bit (SPCR.SPTIE or SPCR.SPRIE) and confirm that its value is 0.
4. Set the ICU.IELSRn.IR flag to 0.
36.5.4
Constraints on Mode-Fault, Underrun, Overrun, or Parity Error Event Output
Using the mode-fault, underrun, overrun, or parity error event is prohibited if the SPI is in multi-master mode (when the
SPCR.SPMS bit is 0, the SPCR.MSTR bit is 1, and the SPCR.MODFEN bit is 1).
36.5.5
Constraints on the SPRF and SPTEF Flags
If the polling flags, SPRF and SPTEF, are used, interrupt usage is prohibited, and you must set the SPCR.SPRIE and
SPCR.SPTIE bits to 0. Either the interrupts or flags can be used, but not both.
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37. Quad Serial Peripheral Interface (QSPI)
37.
Quad Serial Peripheral Interface (QSPI)
37.1
Overview
The Quad Serial Peripheral Interface (QSPI) module is a memory controller for connecting a serial ROM (nonvolatile
memory, such as a serial flash memory, serial EEPROM, or serial FeRAM) that has an SPI-compatible interface.
Table 37.1 lists the QSPI specifications, Figure 37.1 shows a block diagram, and Table 37.2 lists the I/O pins.
Table 37.1
QSPI specifications
Parameter
Specifications
Number of channels
1 channel
SPI
Support for Extended SPI, Dual SPI, and Quad SPI protocols
Configurable to SPI mode 0 and SPI mode 3
Address width selectable to 8, 16, 24, or 32 bits.
Timing adjustment function
Configurable to support a wide range of serial flash
Flash read function
Support for Read, Fast Read, Fast Read Dual Output, Fast Read Dual I/O, Fast Read Quad
Output, and Fast Read Quad I/O instructions
Substitutable instruction code
Adjustable number of dummy cycles
Prefetch function
Polling processing
SPI bus cycle extension function.
Direct communication function
Flexible support for a wide variety of serial flash instructions and functions through software
control, including erase, write, ID read, and power-down control
Interrupt source
Error interrupts
Module-stop function
Module-stop state can be set to reduce power consumption
CKG
Cycle control
QSPI_INTR
interrupt
Internal
bus
Bus interface
QSPCLK
SEQ
SSB
Sequence
control
SSB signal
generation
QSSL
RX
QIO0
REG
BIF
SCK
SCK signal
generation
SFMSMD
SFMSSC
SFMSCK
SFMSST
SFMCOM
SFMCMD
SFMCST
SFMSIC
SFMSAC
SFMSDC
SFMSPC
SFMPMD
SFMCNT1
Reception
PCNT
Port control
TX
Transmission
QIO1
QIO2
QIO3
TAG
Address
management
Figure 37.1
QSPI block diagram
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Table 37.2
37. Quad Serial Peripheral Interface (QSPI)
QSPI I/O pins
Pin name
I/O
Function
QSPCLK
Output
QSPI clock output pin
QSSL
Output
QSPI slave select pin
QIO0
I/O
Data 0 input/output
QIO1
I/O
Data 1 input/output
QIO2
I/O
Data 2 input/output
QIO3
I/O
Data 3 input/output
37.2
Register Descriptions
37.2.1
Transfer Mode Control Register (SFMSMD)
Address(es): QSPI.SFMSMD 6400 0000h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
SFMCC
E
—
—
—
0
0
0
0
Value after reset:
SFMOS SFMO SFMOE SFMM SFMPA SFMPF
W
HW
X
D3
E
E
0
0
0
0
0
0
SFMSE[1:0]
0
0
—
0
SFMRM[2:0]
0
0
0
Bits
Symbol
Bit name
Description
R/W
b2 to b0
SFMRM[2:0]
Serial interface read mode
select
b2
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5, b4
SFMSE[1:0]
QSSL extension function
select after SPI bus access
b5 b4
R/W
b6
SFMPFE
Prefetch function select
0: Disable function
1: Enable function.
R/W
b7
SFMPAE
Function select for stopping
prefetch at locations other
than on byte boundaries
0: Disable function
1: Enable function.
R/W
b8
SFMMD3
SPI mode select.
Initial value determined by input to CFGMD3.
0: SPI mode 0
1: SPI mode 3.
R/W
b9
SFMOEX
Extension select for the I/O
buffer output enable signal for
the serial interface
0: Do not extend
1: Extend by 1 QSPCLK.
R/W
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0
0
0
0
1
1
1
0: Standard Read
1: Fast Read
0: Fast Read Dual Output
1: Fast Read Dual I/O
0: Fast Read Quad Output
1: Fast Read Quad I/O
0: Setting prohibited (unpredictable operation can
result)
1 1 1: Setting prohibited (unpredictable operation can
result).
0
0
1
1
0
0
1
1
0
0
1
b0
0: Do not extend QSSL
1: Extend QSSL by 33 QSPCLK
0: Extend QSSL by 129 QSPCLK
1: Extend QSSL infinitely.
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37. Quad Serial Peripheral Interface (QSPI)
Bits
Symbol
Bit name
Description
R/W
b10
SFMOHW
Hold time adjustment for
serial transmission
0: Do not extend high-level width of QSPCLK during
transmission
1: Extend high-level width of QSPCLK by 1 PCLKA during
transmission.
R/W
b11
SFMOSW
Setup time adjustment for
serial transmission
0: Do not extend low-level width of QSPCLK during
transmission
1: Extend low-level width of QSPCLK by 1 PCLKA during
transmission.
R/W
b14 to b12
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
SFMCCE
Read instruction code select
0: Set default instruction code for each instruction
1: Write instruction code in the SFMSIC register.
R/W
b31 to b16
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
37.2.2
Chip Selection Control Register (SFMSSC)
Address(es): QSPI.SFMSSC 6400 0004h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
SFMSL SFMSH
D
D
1
1
SFMSW
0
1
1
1
Bits
Symbol
Bit name
Description
R/W
b3 to b0
SFMSW
Minimum high-level width select
for QSSL signal
b3
R/W
b4
SFMSHD
QSSL signal release timing select
0: Release QSSL 0.5 QSPCLK cycles after the last rising
edge of QSPCLK
1: Release QSSL 1.5 QSPCLK cycles after the last rising
edge of QSPCLK.
R/W
b5
SFMSLD
QSSL signal output timing select
0: Output QSSL 0.5 QSPCLK cycles before the first rising
edge of QSPCLK
1: Output QSSL 1.5 QSPCLK cycles before the first rising
edge of QSPCLK.
R/W
b31 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: 1 QSPCLK
1: 2 QSPCLK
0: 3 QSPCLK
1: 4 QSPCLK
0: 5 QSPCLK
1: 6 QSPCLK
0: 7 QSPCLK
1: 8 QSPCLK
0: 9 QSPCLK
1: 10 QSPCLK
0: 11 QSPCLK
1: 12 QSPCLK
0: 13 QSPCLK
1: 14 QSPCLK
0: 15 QSPCLK
1: 16 QSPCLK.
Page 1219 of 1734
S5D5 User’s Manual
37.2.3
37. Quad Serial Peripheral Interface (QSPI)
Clock Control Register (SFMSKC)
Address(es): QSPI.SFMSKC 6400 0008h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
SFMDT
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
SFMDV
0
1
0
Bits
Symbol
Bit name
Description
b4 to b0
SFMDV
Serial interface reference cycle
select. (Pay attention to
irregularities.)
b4
b5
SFMDTY
Duty ratio correction function
select for the QSPCLK signal
0: Make no correction
1: Delay the rising of the QSPCLK signal by 0.5 PCLKA
cycles. Valid when PCLKA is multiplied by an odd number.
R/W
b31 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
b0
0: 2 PCLKA
1: 3 PCLKA (multiplied by an odd number)*1
0: 4 PCLKA
1: 5 PCLKA (multiplied by an odd number)*1
0: 6 PCLKA
1: 7 PCLKA (multiplied by an odd number)*1
0: 8 PCLKA
1: 9 PCLKA (multiplied by an odd number)*1
0: 10 PCLKA
1: 11 PCLKA (multiplied by an odd number)*1
0: 12 PCLKA
1: 13 PCLKA (multiplied by an odd number)*1
0: 14 PCLKA
1: 15 PCLKA (multiplied by an odd number)*1
0: 16 PCLKA
1: 17 PCLKA (multiplied by an odd number)*1
0: 18 PCLKA
1: 20 PCLKA
0: 22 PCLKA
1: 24 PCLKA
0: 26 PCLKA
1: 28 PCLKA
0: 30 PCLKA
1: 32 PCLKA
0: 34 PCLKA
1: 36 PCLKA
0: 38 PCLKA
1: 40 PCLKA
0: 42 PCLKA
1: 44 PCLKA
0: 46 PCLKA
1: 48 PCLKA.
R/W
When PCLKA multiplied by an odd number is selected, the high-level width of the QSPCLK signal is longer than the low-level
width by 1 PCLKA before duty ratio correction.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 1220 of 1734
S5D5 User’s Manual
37.2.4
37. Quad Serial Peripheral Interface (QSPI)
Status Register (SFMSST)
Address(es): QSPI.SFMSST 6400 000Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
PFOFF PFFUL
1
—
0
0
PFCNT
0
0
0
Bits
Symbol
Bit name
Description
b4 to b0
PFCNT
Number of bytes of prefetched
data
b4
b5
—
Reserved
This bit is read as 0
R
b6
PFFUL
Prefetch buffer state
0: Prefetch buffer has free space
1: Prefetch buffer is full.
R
b7
PFOFF
Prefetch function operating state
0: Prefetch function operating
1: Prefetch function not enabled or not operating.
R
b31 to b8
—
Reserved
These bits are read as 0
R
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
R/W
b0
0 0 0 0 0: 0 byte
0 0 0 0 1: 1 byte
0 0 0 1 0: 2 bytes
0 0 0 1 1: 3 bytes
0 0 1 0 0: 4 bytes
0 0 1 0 1: 5 bytes
0 0 1 1 0: 6 bytes
0 0 1 1 1: 7 bytes
0 1 0 0 0: 8 bytes
0 1 0 0 1: 9 bytes
0 1 0 1 0: 10 bytes
0 1 0 1 1: 11 bytes
0 1 1 0 0: 12 bytes
0 1 1 0 1: 13 bytes
0 1 1 1 0: 14 bytes
0 1 1 1 1: 15 bytes
1 0 0 0 0: 16 bytes
1 0 0 0 1: 17 bytes
1 0 0 1 0: 18 bytes.
Other settings are reserved.
R
Page 1221 of 1734
S5D5 User’s Manual
37.2.5
37. Quad Serial Peripheral Interface (QSPI)
Communication Port Register (SFMCOM)
Address(es): QSPI.SFMCOM 6400 0010h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
x
x
x
Value after reset:
Value after reset:
SFMD
x
x
x
x
x
x: Undefined
Bits
Symbol
Bit name
Description
R/W
b7 to b0
SFMD
Port select for direct
communication with the SPI bus
Input to and output from this port is converted to an SPI bus
cycle. This port is only accessible in direct communication
mode, when DCOM = 1. Access to this port is ignored in the
ROM access mode.
R/W
b 31 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
37.2.6
Communication Mode Control Register (SFMCMD)
Address(es): QSPI.SFMCMD 6400 0014h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DCOM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bits
Symbol
Bit name
Description
R/W
b0
DCOM
Mode select for communication
with the SPI bus
0: ROM access mode
1: Direct communication mode.
R/W
b 31 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 1222 of 1734
S5D5 User’s Manual
37.2.7
37. Quad Serial Peripheral Interface (QSPI)
Communication Status Register (SFMCST)
Address(es): QSPI.SFMCST 6400 0018h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
EROM
R
—
—
—
—
—
—
COMB
SY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bits
Symbol
Bit name
Description
R/W
b0
COMBSY
SPI bus cycle completion state
in direct communication
0: No serial transfer being processed
1: Serial transfer being processed.
R
b6 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
EROMR
ROM access detection status
in direct communication mode
0: ROM access not detected
1: ROM access detected.
R/(W)*1
b31 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Only 0 can be written to this bit.
37.2.8
Instruction Code Register (SFMSIC)
Address(es): QSPI.SFMSIC 6400 0020h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bits
Symbol
Bit name
b7 to b0
SFMCIC
Serial flash instruction code to
substitute
b31 to b8
—
Reserved
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
SFMCIC
0
0
0
0
0
Description
R/W
R/W
These bits are read as 0. The write value should be 0.
R/W
Page 1223 of 1734
S5D5 User’s Manual
37.2.9
37. Quad Serial Peripheral Interface (QSPI)
Address Mode Control Register (SFMSAC)
Address(es): QSPI.SFMSAC 6400 0024h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
SFM4B
C
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
SFMAS
1
0
Bits
Symbol
Bit name
Description
R/W
b1, b0
SFMAS
Number of address bytes
select for the serial interface
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
SFM4BC
Default instruction code select,
when the serial interface
address width is 4 bytes
0: Do not use 4-byte address read instruction code
1: Use 4-byte address read instruction code.
R/W
b31 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
0
0
1
1
0: 1 byte
1: 2 bytes
0: 3 bytes
1: 4 bytes.
Page 1224 of 1734
S5D5 User’s Manual
37.2.10
37. Quad Serial Peripheral Interface (QSPI)
Dummy Cycle Control Register (SFMSDC)
Address(es): QSPI.SFMSDC 6400 0028h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
0
0
Value after reset:
SFMXE SFMXS
N
T
SFMXD
1
Value after reset:
1
1
1
1
1
1
1
0
0
SFMDN[3:0]
0
0
0
0
Bits
Symbol
Bit name
Description
R/W
b3 to b0
SFMDN[3:0]
Number of dummy cycles
select for Fast Read
instructions
b3
R/W
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: Default dummy cycles for each instruction:
- Fast Read Quad I/O: 6 QSPCLK
- Fast Read Quad Output: 8 QSPCLK
- Fast Read Dual I/O: 4 QSPCLK
- Fast Read Dual Output: 8 QSPCLK
- Fast Read: 8 QSPCLK.
1: 3 QSPCLK*1
0: 4 QSPCLK
1: 5 QSPCLK
0: 6 QSPCLK
1: 7 QSPCLK
0: 8 QSPCLK
1: 9 QSPCLK
0: 10 QSPCLK
1: 11 QSPCLK
0: 12 QSPCLK
1: 13 QSPCLK
0: 14 QSPCLK
1: 15 QSPCLK
0: 16 QSPCLK
1: 17 QSPCLK.
b5, b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
SFMXST
XIP mode status
0: Normal (non-XIP) mode
1: XIP mode.
R
b7
SFMXEN
XIP mode permission in the
QSPI
0: Prohibit XIP mode
1: Permit XIP mode.
R/W
b15 to b8
SFMXD
Mode data for serial flash.
Controls XIP mode
R/W
b31 to b16
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
To avoid a conflict with the input/output switch of the serial flash pin connected to QIO0 pin, select more than 4 QSPCLK
dummy cycles when the output enable signal is extended by setting the SFMOEX bit in the SFMSMD register to 1.
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 1225 of 1734
S5D5 User’s Manual
37.2.11
37. Quad Serial Peripheral Interface (QSPI)
SPI Protocol Control Register (SFMSPC)
Address(es): QSPI.SFMSPC 6400 0030h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
SFMSD
E
—
—
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Value after reset:
Value after reset:
SFMSPI
0
0
Bits
Symbol
Bit name
Description
R/W
b1, b0
SFMSPI
SPI protocol select
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
SFMSDE
Minimum time select for
input/output switch, when Dual
SPI or Quad SPI protocol is
selected and in standard read
mode
0: Do not allocate minimum switch time
1: Allocate minimum switch time equivalent to 1 QSPCLK.
R/W
b31 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
37.2.12
0
0
1
1
0: Extended SPI protocol
1: Dual SPI protocol
0: Quad SPI protocol
1: Setting prohibited.
Port Control Register (SFMPMD)
Address(es): QSPI.SFMPMD 6400 0034h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
SFMW
PL
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bits
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
SFMWPL
WP pin level specification
0: Low level
1: High level.
R/W
b31 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 1226 of 1734
S5D5 User’s Manual
37.2.13
37. Quad Serial Peripheral Interface (QSPI)
External QSPI Address Register (SFMCNT1)
Address(es): QSPI.SFMCNT1 6400 0804h
b31
b30
b29
b28
b27
b26
QSPI_EXT[5:0]
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bits
Symbol
Bit name
Description
R/W
b25 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b26
QSPI_EXT[5:0]
Bank switching address
When accessing from 6000 0000h to 63FF FFFFh, the
address bus is set from QSPI_EXT[5:0] to the upper 6
bits of the internal bus address
R/W
37.3
Memory Map
37.3.1
Internal Bus Space
The locations of the serial flash and control registers in the AHB space are determined by the address range of the
configured area.
External QSPI device space
(4-byte address)
64 MB 63 banks
MCU internal space
FFFF FFFFh
FFFF FFFFh
System for CM4
Bank switching
QSPI.EXT[5:0]
FC00 0000h
QSPI bank 62 to 60
E000 0000h
F000 0000h
Set QSPI.EXT[5:0] to upper
6 bits of internal bus address
Reserved
QSPI bank 59 to 56
E000 0000h
9800 0000h
SDRAM
9000 0000h
Reserved
8720 0000h
8000 0000h
External address space
(CS area)
Reserved
7000 0000h
QSPI
6800 0000h
Peripheral and data
flash
6400 0000h
6000 0000h
4000 0000h
QSPI bank 55 to 16
7000 0000h
Reserved
6000 0000h
QSPI register
QSPI ROM window
(64 MB)
4000 0000h
QSPI bank 15 to 12
3000 0000h
Reserved
QSPI bank 11 to 08
2000 0000h
Code flash
0000 0000h
Figure 37.2
[Configuration]
Serial flash area 0000 0000h to FBFF
FFFFh
QSPI bank 07 to 04
1000 0000h
QSPI bank 03 to 00
0000 0000h
Default area setting and AHB space memory map
R01UM0009EU0130 Rev.1.30
Aug 30, 2019
Page 1227 of 1734
S5D5 User’s Manual
37.3.2
37. Quad Serial Peripheral Interface (QSPI)
Address Width of the SPI Space and SPI Bus
The SPI space has a 32-bit address width for referencing the serial flash. When the SPI space is accessed for a read, an
SPI bus cycle starts automatically, and data read from the serial flash is returned.
The address width of the SPI space is fixed at 32 bits. However, the address width of the SPI bus is selectable to 8, 16,
24, or 32 bits in the SFMAS[1:0] bits in the SFMSAC register. If the address width of the SPI bus is selected as 8, 16, or
24 bits, only the lower part of the address used to access the SPI space is posted to the serial flash through the SPI bus. As
a result, the mirror image of the serial flash corresponding to the address width of the SPI bus repeatedly appears in the
SPI space.
SPI 9-bit address width
SPI 8-bit address width
SPI 32-bit address width
SPI 24-bit address width
SPI 16-bit address width
(SFMAS[1:0] = 00)
(SFMAS[1:0] = 00)
(SFMAS[1:0] = 11)
(SFMAS[1:0] = 10)
(SFMAS[1:0] = 01)
FFFF FFFFh
FFFF FFFFh
FFFF FFFFh
FFFF FFFFh
FFFF FFFFh
256 bytes #
FFFF FF00h
512 bytes #
256 bytes #
FFFF FE00h
256 bytes #
512 bytes #
64 KB #
256 bytes #
256 bytes #
512 bytes #
256 bytes #
FFFF 0000h
16 MB #
64 KB #
FF00 0000h
4 GB
00FF FFFFh
64 KB #
16 MB
0000 FFFFh
512 bytes #
64 KB
512 bytes #
0000 01FFh
512 bytes
0000 0000h
0000 0000h
0000 0000h
0000 0000h
256 bytes #
256 bytes #
256 bytes #
256 bytes #
256 bytes #
256 bytes
0000 00FFh
0000 0000h
# : Mirror image
Figure 37.3
Note:
Memory map of SPI space
The SPI bus address width is selectable to 8, 16, 24, or 32 bits in the SFMAS[1:0] bits in the SFMSAC register.
When an 8-bit address width is selected, the address information of the ninth bit can be embedded in the Read
instruction code. The address map in the figures is for the SPI 9-bit address width. For details on the Read
instruction, see section 37.6.2, Standard Read Instruction.
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37.4
37. Quad Serial Peripheral Interface (QSPI)
SPI Bus
37.4.1
SPI Protocol
The QSPI supports Extended SPI, Dual SPI, and Quad SPI, in addition to the SPI protocol used for serial flash
connection. The initial state is Extended SPI. To change the protocol, set the SFMSPI bit in the SFMSPC register. The
Extended SPI protocol always outputs instruction codes from a single QIO0 pin. It performs subsequent address and data
I/O operations using one to four pins, depending on the instruction code format.
Instruction
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit data
QSPCLK
QSSL
Mode
QIO0
7
6
5
4
3
2
1
0
n-1 n-2 n-3
3
2
1
0
1
0
QIO1
7
6
5
4
3
2
1
0
High or low
QIO2
QIO3
Figure 37.4
Extended SPI protocol example 1 for Fast Read
Instruction
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
QSPCLK
QSSL
Mode
QIO0
n-4 n-8 n-12 n-16 12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
QIO1
n-3 n-7 n-11 n-15 13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
QIO2
n-2 n-6 n-10 n-14 14
10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
QIO3
n-1 n-5 n-9 n-13 15
11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Figure 37.5
7
6
5
4
3
2
1
0
Extended SPI protocol example 2 for Fast Read Quad I/O
The Dual SPI protocol performs the I/O operation of all signals such as instruction codes, addresses, and data using two
pins, QIO0 and QIO1.
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37. Quad Serial Peripheral Interface (QSPI)
Instruction
n-bit (1 to 4 bytes) address
8-bit data
Dummy cycles
8-bit data
8-bit data
8-bit data
QSPCLK
QSSL
Mode
QIO0
6
4
2
0
n-2 n-4 n-6 n-8
6
4
2
0
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
QIO1
7
5
3
1
n-1 n-3 n-5 n-7
7
5
3
1
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
QIO2
High or low
QIO3
Figure 37.6
Dual SPI protocol example for Fast Read
The Quad SPI protocol performs the I/O operation of all signals such as instruction codes, addresses, and data using four
pins, QIO0, QIO1, QIO2, and QIO3.
Instruction
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
QSPCLK
QSSL
Mode
QIO0
4
0
n-4 n-8 n-12 n-16 12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
QIO1
5
1
n-3 n-7 n-11 n-15 13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
QIO2
6
2
n-2 n-6 n-10 n-14 14
10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
QIO3
7
3
n-1 n-5 n-9 n-13 15
11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Figure 37.7
Quad SPI protocol example for Fast Read
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37.4.2
37. Quad Serial Peripheral Interface (QSPI)
SPI Mode
The initial SPI mode is set to SPI mode 0 or 3 by the CFGMD3 pin. This can be switched by changing the register setting
during operation. The difference between SPI modes 0 and 3 is the standby level of the QSPCLK signal. The standby
level of the QSPCLK signal is low in SPI mode 0, and is high in SPI mode 3.
Serial data is output from the QSPI on a falling edge of the serial clock and is read into the external flash on a rising edge
of the serial clock. Serial data is output from the external flash on a falling edge of the serial clock and is read into the
QSPI on the next falling edge of the serial clock.
QSPCLK
(SPI mode 3)
QSPCLK
(SPI mode 0)
QSSL
QIO0 to QIO3
(out)
MSB
LSB
QIO0 to QIO3
(in)
Figure 37.8
37.5
MSB
LSB
Basic serial interface timing
SPI Bus Timing Adjustment
The timing of the SPI bus signal can be adjusted in the registers. The configured timing is applied to all SPI bus accesses,
for both ROM access and direct communication.
37.5.1
SPI Bus Reference Cycles
The SPI bus operates on reference cycles obtained by multiplying PCLKA by an integer. The reference cycles are
selectable within the range of PCLKA multiplied by 2 to 48 in the SFMDV[4:0] bits in the SFMSKC register.
Table 37.3
Relationship among SFMDV[4:0] bits, cycle multiplier, and serial clock frequencies (1 of 2)
PCLKA frequency (MHz)
SFMDV[4:0]
Cycle multiplier
120
11111
48
2.50
11110
46
2.61
11101
44
2.73
11100
42
2.86
11011
40
3.00
11010
38
3.16
11001
36
3.33
11000
34
3.53
10111
32
3.75
10110
30
4.00
10101
28
4.29
10100
26
4.62
10011
24
5.00
10010
22
5.45
10001
20
6.00
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Table 37.3
37. Quad Serial Peripheral Interface (QSPI)
Relationship among SFMDV[4:0] bits, cycle multiplier, and serial clock frequencies (2 of 2)
PCLKA frequency (MHz)
SFMDV[4:0]
Cycle multiplier
120
10000
18
6.67
01111
17
7.06
01110
16
7.50
01101
15
8.00
01100
14
8.57
01011
13
9.23
01010
12
10.00
01001
11
10.91
01000
10
12.00
37.5.2
00111
9
13.33
00110
8
15.00
00101
7
17.14
00100
6
20.00
00011
5
24.00
00010
4
30.00
00001
3
40.00
00000
2
60.00
QSPCLK Signal Duty Ratio
When the reference clock is configured as PCLKA multiplied by an even number, the high- and low-level widths of the
QSPCLK signal match each other. When PCLKA is multiplied by an odd number, however, the high-level width is
longer than the low-level width by 1 PCLKA.
To make the duty ratio of the QSPCLK signal close to 50% when the reference clock is PCLKA multiplied by an odd
number, set the SFMDTY bit in the SFMSKC register to 1. With this setting, the rising edge of the QSPCLK output
signal is delayed by one-half PCLKA cycle to perform an interface operation equivalent to a duty ratio of 50%.
When the reference clock is PCLKA multiplied by an even number, the SFMDTY setting in the SFMSKC register is
ignored.
QSPCLK
(SFMDTY = 0)
QSPCLK
(SFMDTY = 1)
QSSL
SIOnOE
(internal signal)
QIOn
(out)
MSB
QIOn
(in)
LSB
MSB
LSB
n = 0, 1, 2, 3
Figure 37.9
Example correction of the QSPCLK signal duty ratio using the SFMDTY bit, when PCLKA is
multiplied by 3
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37.5.3
37. Quad Serial Peripheral Interface (QSPI)
Minimum High-Level Width for the QSSL Signal
Between adjacent SPI bus cycles, the QSSL signal must be held high (inactive) for a sufficient time to satisfy the deselect
time required by the serial flash. The minimum high-level width of the QSSL output signal is selectable as the reference
cycle multiplied by an integer from 1 to 16 in the SFMSW[3:0] bits in the SFMSSC register.
37.5.4
QSSL Signal Setup Time
When the QSPCLK signal first rises after the QSSL signal is driven low, the QSSL signal setup time can be configured to
satisfy the serial flash requirements. The setup time can be selectable as 0.5 QSPCLK or 1.5 QSPCLK in the SFMSLD
bit in the SFMSSC register.
The SFMSLD setting in the SFMSSC register is also used to the allocate a setup time from the output of the serial data
output enable signal (QIO0OE, QIO1OE, QIO2OE, or QIO3OE) until the first rising edge of the QSPCLK signal. Set a
value that meets the most constrained timing condition for your application.
QSPCLK
QSSL
SIOnOE
(internal signal)
QIOn
(out)
MSB
LSB
QIOn
(in)
MSB
LSB
n = 0, 1, 2, 3
Figure 37.10
37.5.5
Setup time adjustment for the QSSL signal using the SFMSLD bit
QSSL Signal Hold Time
When the QSSL signal is driven high after the last rising edge of the QSPCLK signal, the QSSL signal hold time can be
configured to satisfy the device requirements. The hold time is selectable as 0.5 QSPCLK or 1.5 QSPCLK in the
SFMSHD bit in the SFMSSC register.
QSPCLK
QSSL
(SFMSHD = 0)
SIOnOE
(internal signal)
QIOn
(out)
MSB
QIOn
(in)
LSB
MSB
LSB
n = 0, 1, 2, 3
Figure 37.11
Hold time adjustment for the QSSL signal using the SFMSHD bit
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37.5.6
37. Quad Serial Peripheral Interface (QSPI)
Hold Time of the Serial Data Output Enable
The buffer output enable of the QIO0, QIO1, QIO2, or QIO3 pin can be extended by 1 QSPCLK using the SFMOEX bit
in the SFMSMD register. The target extension signals include only the output enable signals QIO0E, QIO1OE, QIO2OE,
and QIO3OE. They do not include the output data signals QIO0O, QIO1O, QIO2O, or QIO3O.
QSPCLK
QSSL
SIOnOE
(internal signal)
QIOn
(out)
MSB
LSB
QIOn
(in)
MSB
LSB
n = 0, 1, 2, 3
Dummy cycles
(set by SFMSDC.SFMDN[3:0])
Figure 37.12
37.5.7
Hold time adjustment for output enable using the SFMOEX bit
Setup Time for Serial Data Output
When a command or address is transmitted to the serial flash, the setup time begins on serial data output and ends when
the QSPCLK signal rises. If this setup time is insufficient, it can be extended by 1 PCLKA using the SFMOSW bit in the
SFMSMD register. When SFMOSW is 1, the low-level width of QSPCLK during serial data transmission is extended by
1 PCLKA while data is being output from the QSPI. This function has no effect on serial data reception.
PCLKA
QSPCLK
QSSL
(SFMSHD = 0)
SIOnOE
(internal signal)
QIOn
(out)
MSB
QIOn
(in)
LSB
MSB
LSB
n = 0, 1, 2, 3
Figure 37.13
Setup time adjustment for serial data output using the SFMOSW bit
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37.5.8
37. Quad Serial Peripheral Interface (QSPI)
Hold Time for Serial Data Output
When a command or address is transmitted to the serial flash, the hold time begins on the rising edge of QSPCLK and
ends when the serial data makes another transmission. If this hold time is insufficient, it can be extended by 1 PCLKA
using the SFMOHW bit in the SFMSMD register. When SFMOSW is 1, the high-level width of QSPCLK during serial
data transmission is extended by 1 PCLKA while data is being output from the QSPI. This function has no effect on
serial data reception.
PCLKA
QSPCLK
QSSL
(SFMSHD = 0)
SIOnOE
(internal signal)
QIOn
(out)
MSB
LSB
QIOn
(in)
MSB
LSB
n = 0, 1, 2, 3
Figure 37.14
37.5.9
Hold time adjustment for serial data output using the SFMOHW bit
Serial Data Receiving Latency
The serial flash outputs data in synchronization with the falling edge of the QSPCLK signal. The QSPI receives that data
in synchronization with the falling edge of the subsequent QSPCLK signal. The delay from when the serial flash starts
outputting data until the QSPI receives that data is called the receiving latency. The QSPI adds a latency adjustment cycle
immediately before the first data reception cycle in the SPI bus cycle. From the serial flash side, this is seen as an
increase in the number of data reception cycles. This added latency adjustment cycle is not generated in the SPI bus cycle
without the accompanying data reception.
QSPCLK
QSSL
MCU pins
QIOn
(out)
QIOn
(in)
MSB
LSB
MSB
LSB
Receiving latency
Internal data
sampling
timing
Internal
data input
MSB
LSB
n = 0, 1, 2, 3
Figure 37.15
Receiving latency
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37.6
37. Quad Serial Peripheral Interface (QSPI)
SPI Instruction Set Used for Flash Access
37.6.1
SPI Instructions That Are Automatically Generated
When the serial flash is accessed, an SPI bus cycle using one of the instructions described in Table 37.4 to Table 37.8 is
automatically generated based on the settings in the SFMAS[1:0] bits in the SFMSAC register and in the SFMSMD
register.
Table 37.4
SPI instructions automatically generated when SFMAS[1:0] = 00b
Instruction format
Instruction
code
Address
bytes
Dummy
cycles
Data bytes
Remarks
Read
03h*1
1
—
1 to ∞
Required: SFMRM[2:0] = 000, A8 = 0
0Bh*1
1
—
1 to ∞
Required: SFMRM[2:0] = 000, A8 = 1
Note 1.
If the SFMSMD.SFMCCE bit is set to 1, the SFMSIC.SFMCIC[7:0] setting is used as an instruction code.
Table 37.5
SPI instructions automatically generated when SFMAS[1:0] = 01b
Instruction format
Instruction
code
Address
bytes
Dummy
cycles
Data bytes
Remarks
Read
03h*1
2
—
1 to ∞
Required: SFMRM[2:0] = 000
Note 1.
If the SFMSMD.SFMCCE bit is set to 1, the SFMSIC.SFMCIC[7:0] setting is used as an instruction code.
Table 37.6
SPI instructions automatically generated when SFMAS[1:0] = 10b
Instruction format
Instruction
code
Address
bytes
Dummy
cycles
Data bytes
Remarks
Read
03h*1
3
—
1 to ∞
Required: SFMRM[2:0] = 000
Fast Read
0Bh*1
3
8*2
1 to ∞
Selectable: SFMRM[2:0] = 001
Fast Read Dual Output
3Bh*1
3
8*2
1 to ∞
Selectable: SFMRM[2:0] = 010
Fast Read Dual I/O
BBh*1
3
4*2
1 to ∞
Selectable: SFMRM[2:0] = 011
Fast Read Quad Output
6Bh*1
3
8*2
1 to ∞
Selectable: SFMRM[2:0] = 100
Fast Read Quad I/O
EBh*1
3
6*2
1 to ∞
Selectable: SFMRM[2:0] = 101
Write Enable
06h
—
—
—
Selectable: ENEX4B[1:0] = 10
Exit 4-Byte Mode
E9h
—
—
—
Selectable: ENEX4B[1:0] = 01,10
Note 1.
Note 2.
If the SFMSMD.SFMCCE bit is set to 1, the SFMSIC.SFMCIC[7:0] setting is used as an instruction code.
The number of dummy cycles is configurable in the SFMSDC.SFMDN[3:0].
Table 37.7
SPI instructions automatically generated when SFMAS[1:0] = 11b and SFM4BC = 0
Instruction format
Instruction
code
Address
bytes
Dummy
cycles
Data bytes
Remarks
Read
03h*1
4
—
1 to ∞
Required: SFMRM[2:0] = 000
Fast Read
0Bh*1
4
8*2
1 to ∞
Selectable: SFMRM[2:0] = 001
Fast Read Dual Output
3Bh*1
4
8*2
1 to ∞
Selectable: SFMRM[2:0] = 010
Fast Read Dual I/O
BBh*1
4
4*2
1 to ∞
Selectable: SFMRM[2:0] = 011
Fast Read Quad Output
6Bh*1
4
8*2
1 to ∞
Selectable: SFMRM[2:0] = 100
Fast Read Quad I/O
EBh*1
4
6*2
1 to ∞
Selectable: SFMRM[2:0] = 101
Write Enable
06h
—
—
—
Selectable: ENEX4B[1:0] = 10
Enter 4-Byte Mode
B7h
—
—
—
Selectable: ENEX4B[1:0] = 01,10
Note 1.
Note 2.
If the SFMSMD.SFMCCE bit is set to 1, the SFMSIC.SFMCIC[7:0] setting is used as an instruction code.
The number of dummy cycles is configurable in the SFMSDC.SFMDN[3:0].
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Table 37.8
37. Quad Serial Peripheral Interface (QSPI)
SPI instructions automatically generated when SFMAS[1:0] = 11b and SFM4BC = 1
Instruction format
Instruction
code
Address
bytes
Dummy
cycles
Data bytes
Remarks
Read
13h*1
4
—
1 to ∞
Required: SFMRM[2:0] = 000
Fast Read
0Ch*1
4
8*2
1 to ∞
Selectable: SFMRM[2:0] = 001
Fast Read Dual Output
3Ch*1
4
8*2
1 to ∞
Selectable: SFMRM[2:0] = 010
Fast Read Dual I/O
BCh*1
4
4*2
1 to ∞
Selectable: SFMRM[2:0] = 011
Fast Read Quad Output
6Ch*1
4
8*2
1 to ∞
Selectable: SFMRM[2:0] = 100
Fast Read Quad I/O
ECh*1
4
6*2
1 to ∞
Selectable: SFMRM[2:0] = 101
Write Enable
06h
—
—
—
Selectable: ENEX4B[1:0] = 10
Enter 4-Byte Mode
B7h
—
—
—
Selectable: ENEX4B[1:0] = 01,10
Note 1.
Note 2.
If the SFMSMD.SFMCCE bit is set to 1, the SFMSIC.SFMCIC[7:0] setting is used as an instruction code.
The number of dummy cycles is configurable in the SFMSDC.SFMDN[3:0].
37.6.2
Standard Read Instruction
The standard Read instruction is a common read instruction supported by most serial flash devices. When an SPI bus
cycle starts, the serial flash select signal is asserted, and the instruction code (03h/13h)*1 is output. Next, an address with
a width of 1 to 4 bytes, specified in the SFMAS[1:0] bits in the SFMSAC register, is transmitted. Data is then received.
This standard Read instruction is selected in the initial QSPI settings.
Note 1. Many 4-Kb serial flash devices have an address field not larger than 1 byte (A7-A0) to minimize the overhead,
and to receive A8 information from bit [3] of the Read instruction code. To support these devices, the QSPI only
outputs A8 (address bit 8) to bit [3] of the standard Read instruction code when an address width of 1 byte is
specified (SFMAS[1:0] = 00). This means that 0Bh might be output instead of 03h as the standard Read
instruction code. This code duplicates the Fast Read instruction code. However, for most of the 2-Kb or smaller
serial flash devices with an address width of 1 byte, bit [3] of a command is designed to be excluded from
decoding as a don’t care bit, so such a Read instruction code is recognized correctly as the standard Read
instruction code. In rare cases, some serial flash devices allow bit [3] to be decoded. When such a serial flash is
connected, configure your application to avoid access resulting in A8 = 1.
Instruction (03h or 0Bh)
n-bit (1 to 4 bytes) address
8-bit data
8-bit data
QSPCLK
QSSL
QIO0
A8
n-1 n-2 n-3
3
2
1
0
When SFMAS [1:0] = 00b
QIO1
QIO2
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
High or low
QIO3
Figure 37.16
Standard Read bus cycle
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37.6.3
37. Quad Serial Peripheral Interface (QSPI)
Fast Read Instruction
The Fast Read instruction is a read instruction that supports a higher communication clock speed than the standard Read
instruction. When an SPI bus cycle starts, the serial flash select signal is asserted, and the instruction code (0Bh/0Ch) is
output. Next, an address with a width of 1 to 4 bytes, specified in the SFMAS[1:0] bits in SFMSAC, and a certain
number of dummy cycles, specified in the SFMSDC register, are transmitted. Data is then received.
The first 2 dummy cycles are used to select or deselect the XIP mode. When the XIP mode is selected, the same
instruction is applied to the next SPI bus cycle, and the instruction code transmission of the next SPI bus cycle is skipped.
For details on the XIP mode, see section 37.8, XIP Control.
Switching to the Fast Read instruction is controlled in the SFMSMD register.
Instruction (0Bh)
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit data
QSPCLK
QSSL
Mode
QIO0
n-1 n-2 n-3
3
2
1
0
1
0
QIO1
7
QIO2
6
5
4
3
2
1
0
2
1
0
High or low
QIO3
Figure 37.17
Fast Read bus cycle
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit data
8-bit data
QSPCLK
QSSL
Mode
QIO0
n-1 n-2 n-3
3
2
1
0
1
0
QIO1
7
QIO2
6
5
4
3
2
1
0
7
6
5
4
3
High or low
QIO3
Figure 37.18
Note:
Fast Read bus cycle in XIP mode
To use the Fast Read instruction, a serial flash device that supports Fast Read transfers is required.
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37.6.4
37. Quad Serial Peripheral Interface (QSPI)
Fast Read Dual Output Instruction
The Fast Read Dual Output instruction is a read instruction that uses two signal lines to receive data. When the SPI bus
cycle starts, the serial flash select signal is asserted. The instruction code (3Bh/3Ch) and an address with a width of 1 to
4 bytes, specified in the SFMAS[1:0] bits in the SFMSAC register, are transmitted from the QIO0 pin. Next, a certain
number of dummy cycles, specified in the SFMSDC register, is generated. Data is then received through the QIO0 and
QIO1 pins. Even bit data is received from the QIO0 pin and odd bit data is received from the QIO1 pin.
The first 2 dummy cycles are used to select or deselect the XIP mode. When the XIP mode is selected, the same
instruction used this time is applied to the next SPI bus cycle, and the instruction code transmission of the next SPI bus
cycle is skipped. For details on the XIP mode, see section 37.8, XIP Control.
Switching to Fast Read Dual Output is controlled in the SFMSMD register.
Instruction (3Bh)
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit data
8-bit data
QSPCLK
QSSL
Mode
QIO0
n-1 n-2 n-3
3
2
1
0
1
0
QIO1
QIO2
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
High or low
QIO3
Figure 37.19
Fast Read Dual Output bus cycle
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit data
8-bit data
8-bit data
8-bit data
QSPCLK
QSSL
Mode
QIO0
n-1 n-2 n-3
3
2
1
0
1
QIO1
QIO2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
High or low
QIO3
Figure 37.20
Note:
Fast Read Dual Output bus cycle in XIP mode
To use the Fast Read Dual Output instruction, a serial flash device that supports Fast Read Dual Output transfers
is required.
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37.6.5
37. Quad Serial Peripheral Interface (QSPI)
Fast Read Dual I/O Instruction
The Fast Read Dual I/O instruction is a read instruction that uses two signal lines to transmit an address and receive data.
When the SPI bus cycle starts, the serial flash select signal is asserted, and the instruction code (BBh/BCh) is output from
the QIO0 pin. Next, an address with a width of 1 to 4 bytes, specified in the SFMAS[1:0] bits in the SFMSAC register, is
transmitted through the QIO0 and QIO1 pins, and a certain number of dummy cycles, specified in the SFMSDC register,
is generated. Data is then is received through the QIO0 and QIO1 pins. Address and dummy cycle transmission and data
reception are performed through the QIO0 pin for even bits and through the QIO1 pin for odd bits.
The first 2 dummy cycles are used to select or deselect the XIP mode. When the XIP mode is selected, the same
instruction used this time is applied to the next SPI bus cycle, and the instruction code transmission is skipped for the
next SPI bus cycle. For details on the XIP mode, see section 37.8, XIP Control.
Switching to Fast Read Dual I/O is controlled in the SFMSMD register.
Instruction (BBh)
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit data
8-bit data
8-bit data
QSPCLK
QSSL
Mode
QIO0
n-2 n-4 n-6 n-8
6
4
2
0
2
0
6
4
2
0
6
4
2
0
6
4
2
0
QIO1
n-1 n-3 n-5 n-7
7
5
3
1
3
1
7
5
3
1
7
5
3
1
7
5
3
1
QIO2
High or low
QIO3
Figure 37.21
Fast Read Dual I/O bus cycle
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit data
8-bit data
8-bit data
8-bit data
8-bit data
QSPCLK
QSSL
Mode
QIO0
n-2 n-4 n-6 n-8
6
4
2
0
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
QIO1
n-1 n-3 n-5 n-7
7
5
3
1
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
QIO2
High or low
QIO3
Figure 37.22
Note:
Fast Read Dual I/O bus cycle in XIP mode
To use the Fast Read Dual I/O instruction, a serial flash device that supports Fast Read Dual I/O transfers is
required.
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37.6.6
37. Quad Serial Peripheral Interface (QSPI)
Fast Read Quad Output Instruction
The Fast Read Quad Output instruction is a read instruction that uses four signal lines to receive data. When the SPI bus
cycle starts, the serial flash select signal is asserted. The instruction code (6Bh/6Ch) and an address with a width of 1 to
4 bytes, specified in the SFMAS[1:0] bits in the SFMSAC register, are output from the QIO0 pin. Next, a certain number
of dummy cycles, specified in the SFMDN[3:0] bits in the SFMSMD register, are generated. Data is then received
through the QIO0, QIO1, QIO2, and QIO3 pins.
The first 2 dummy cycles are used to select or deselect the XIP mode. When the XIP mode is selected, the same
instruction used this time is applied to the next SPI bus cycle, and the instruction code transmission of the next SPI bus
cycle is skipped. For details on the XIP mode, see section 37.8, XIP Control.
Switching to Fast Read Quad Output is controlled in the SFMSMD register.
Instruction (6Bh)
n-bit (1 to 4 bytes) address
8-bit
data
Dummy cycles
8-bit
data
8-bit
data
8-bit
data
QSPCLK
QSSL
Mode
QIO0
4
0
4
0
4
0
4
0
QIO1
5
1
5
1
5
1
5
1
QIO2
6
2
6
2
6
2
6
2
QIO3
7
3
7
3
7
3
7
3
Figure 37.23
n-1 n-2 n-3
3
2
1
0
1
0
Fast Read Quad Output bus cycle
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
QSPCLK
QSSL
Mode
QIO0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
QIO1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
QIO2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
QIO3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Figure 37.24
Note:
37.6.7
n-1 n-2 n-3
3
2
1
0
1
0
Fast Read Quad Output bus cycle in XIP mode
To use Fast Read Quad Output, a serial flash that supports Fast Read Quad Output transfer is required.
Fast Read Quad I/O Instruction
The Fast Read Quad I/O instruction is a read instruction that uses four signal lines to transmit an address and receive
data. When the SPI bus cycle starts, the serial flash select signal is asserted, and the instruction code (EBh/ECh) is
output. Next, an address with a width of 1 to 4 bytes, specified in the SFMAS[1:0] bits in the SFMSAC register, is
transmitted through the QIO0, QIO1, QIO2, and QIO3 pins, and a certain number of dummy cycles, specified in the
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37. Quad Serial Peripheral Interface (QSPI)
SFMDN[3:0] bits in the SFMSMD register, is generated. Data is then received through the QIO0, QIO1, QIO2, and
QIO3 pins.
The first 2 dummy cycles are used to select or deselect the XIP mode. When the XIP mode is selected, the same
instruction used this time is applied to the next SPI bus cycle, and the instruction code transmission of the next SPI bus
cycle is skipped. For details on the XIP mode, see section 37.8, XIP Control.
Switching to Fast Read Quad I/O is controlled in the SFMSMD register.
Instruction (EBh)
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
QSPCLK
QSPCLK
QSSL
QSSL
Mode
QIO0
QIO0
n-4 n-8 n-12 n-16 12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
n-3 n-7 n-11 n-15 13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
n-2 n-6 n-10 n-14 14
10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
n-1 n-5 n-9 n-13 15
11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
QIO1
QIO1
QIO2
QIO2
QIO3
QIO3
Figure 37.25
Fast Read Quad I/O bus cycle
n-bit (1 to 4 bytes) address
Dummy cycles
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
8-bit
data
QSPCLK
QSSL
Mode
QIO0
n-4 n-8 n-12 n-16 12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
QIO1
n-3 n-7 n-11 n-15 13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
QIO2
n-2 n-6 n-10 n-14 14
10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
QIO3
n-1 n-5 n-9 n-13 15
11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Figure 37.26
Note:
Fast Read Quad I/O bus cycle in XIP mode
To use the Fast Read Quad I/O instruction, a serial flash device that supports Fast Read Quad I/O transfers is
required.
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37.6.8
37. Quad Serial Peripheral Interface (QSPI)
Enter 4-Byte Mode Instruction
The Enter 4-Byte Mode instruction sets the serial flash address width to 4 bytes. When the SPI bus cycle starts, the serial
flash select signal is asserted, and the instruction code (B7h) is output.
Instruction (B7h)
QSPCLK
QSSL
QIO0
QIO1
Figure 37.27
Note:
Enter 4-Byte Mode bus cycle
The Enter 4-Byte Mode instruction is issued regardless of whether the serial flash is in 3- or 4-byte mode.
37.6.9
Exit 4-Byte Mode Instruction
The Exit 4-Byte Mode instruction sets the serial flash address width to 3 bytes. When the SPI bus cycle starts, the serial
flash select signal is asserted, and the instruction code (E9h) is output.
Instruction (E9h)
QSPCLK
QSSL
QIO0
QIO1
Figure 37.28
Note:
Exit 4-Byte Mode bus cycle
The Exit 4-Byte Mode instruction is issued regardless of whether the serial flash is in 3- or 4-byte mode.
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37.6.10
37. Quad Serial Peripheral Interface (QSPI)
Write Enable Instruction
The Write Enable instruction enables changing of the serial flash address width. When the SPI bus cycle starts, the serial
flash select signal is asserted, and the instruction code (06h) is output.
Instruction (06h)
QSPCLK
QSSL
QIO0
QIO1
Figure 37.29
37.7
Write Enable bus cycle
SPI Bus Cycle Arrangement
37.7.1
Flash Read Based on Individual Conversion
ROM read internal bus cycles are individually converted to SPI bus cycles on a one-to-one basis. When a ROM read bus
cycle is detected, the QSSL signal is asserted, and an SPI bus cycle starts. When data is received from the serial flash, the
QSSL signal is deasserted, and the SPI bus cycle is complete.
When another ROM read bus cycle is detected, the QSSL signal is reasserted after ensuring the minimum high-level
width of the QSSL signal is reached. Then another SPI bus cycle starts.
Instruction
(read)
24-bit address
8-bit data x2
Instruction
(read)
24-bit address
8-bit data x2
QSPCLK
QSSL
QIO0
Instruction
A23-A16
A15-A8
QIO1
Figure 37.30
A7-A0
Instruction
D7-D0
A23-A16
A15-A8
D15-D8
A7-A0
D7-D0
D15-D8
Successive data read operations based on individual conversion
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37.7.2
37. Quad Serial Peripheral Interface (QSPI)
Flash Read Using the Prefetch Function
In operations such as the CPU instruction execution and block data transfer, data is often read in ascending order from
contiguous flash addresses. Serial flash provides the ability to repeat data reception without reissuing an instruction code
and address. However, if bus cycles issued by the MCU are individually converted, the SPI bus cycles are separated from
each other, resulting in a failure to take advantage of this feature of the serial flash. The QSPI contains a prefetch
function to ensure the use of this capability.
To enable the prefetch function, set the SFMPFE bit in the SFMSMD register to 1. When the prefetch function is
enabled, data is received continuously and stored in the buffer, without waiting for another flash read request. When the
MCU performs a flash read operation, an address check is made. If an address match is confirmed, the data in the buffer
is passed to the MCU. If an address mismatch is found, the data in the buffer is discarded, and a new SPI bus cycle is
issued.
The buffer for prefetching is 18 bytes long. When this buffer is full, the SPI bus cycle is ended. When the buffer data is
read to create free space, a new SPI bus cycle is automatically started to resume prefetching.
The prefetch function allows for efficient transfer operations when data is read in ascending order from contiguous
addresses, as in instruction fetch and block data transfer.
Instruction
(read)
24-bit address
8-bit data x2
8-bit data x2
8-bit data x2
QSPCLK
QSSL
Instruction
QIO0
A23-A16
A15-A8
QIO1
D7-D0
Figure 37.31
37.7.3
A7-A0
D15-D8
D7-D0
D15-D8
D7-D0
D15-D8
D7-D0
D15-D8
D7-D0
Successive data read operations using the prefetch function
Halt of Prefetching
If a ROM read bus cycle for reading from another address occurs during a serial transfer for prefetching, the unnecessary
serial transfer being made is halted and a new SPI bus cycle is started. Usually, such a halt of serial transfer occurs on
data reception byte boundaries. However, if the SFMPAE bit in the SFMSMD register is set to 1, the halt can occur on
locations other than byte boundaries. To use this function, the serial flash device must support halts that are not on byte
boundaries.
37.7.4
Direct Specification of Prefetch Destination
When the SFMPFE bit is set and the QSPI receives internal bus write access to the QSPI window area, the system
obtains it as a prefetch address and starts to prefetch. Internal bus write access to the QSPI window area can only be used
to obtain prefetch address data. Writes to serial flash cannot be performed.
Combining this function with the prefetch state polling function described in section 37, Prefetch State Polling, can
reduce the load on the internal bus when data is read from a low-speed serial flash.
Note:
When writing to the QSPI window area to indicate a prefetch destination, write to the first byte of the address
where prefetching is to be started. Writes to the QSPI window area with a data size of 2 bytes or more return an
ERROR response.
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37.7.5
37. Quad Serial Peripheral Interface (QSPI)
Prefetch State Polling
Reading data from a low-speed serial flash increases system load, because the internal bus enters a wait state until the
SPI reception bus cycle is complete. The prefetch state polling function is provided to reduce this load.
The PFOFF bit in the SFMSST register indicates the state of the prefetch function, and the PFCNT[4:0] bits in the
SFMSST register indicate the number of data bytes already prefetched. This allows the prefetch status to be determined
with a single CPU operation.
//
// copy 1K byte (32bit x 256 word) data from serial flash to SDRAM
//
unsigned long *sptr;
// pointer for the serial flash
unsigned long *dptr;
// pointer for the SDRAM
int i;
SFMSMD |= 0x0040;
// set SFMPFE bit to enable prefetch
*( (volatile unsigned char *) sptr ) = 0; // make the TAG valid to start prefetch
for ( i = 0 ; i < 256 ; i++ ){
while ( ( SFMSST & 0x00FF ) < 0x04 ){}; // waiting for 4-byte data to be received
*(dptr++) = *(sptr++);
}
Note:
When executing a polling program, place the program outside of the serial flash or enable the instruction cache.
If the polling program is executed when the program is on the serial flash or is executed without using the
instruction cache, the prefetch target frequently switches to an instruction code. This eliminates the effect of
polling, and an infinite loop can result because the prefetch buffer is not filled.
37.7.6
Flash Read Using the SPI Bus Cycle Extension Function
If the SFMSE[1:0] bits in the SFMSMD register are set to a value other than 00b, the QSPI waits for the next flash read,
suspending the SPI bus cycle, while stopping the QSPCLK signal and holding the QSSL signal low even after data is
obtained from the serial flash.
If the address of the next flash read is contiguous in ascending order, the toggling of the QSPCLK signal is restarted to
continue reception of subsequent data. If the address of the next flash read is not contiguous in ascending order, the
QSSL signal is driven high once to end the SPI bus cycle being suspended. A new SPI bus cycle is then started.
When data is read intermittently from ascending order contiguous addresses, this function enables an efficient transfer
operation to be performed by reducing the overhead for instruction code and address transmission.
The SPI bus cycle extension time is selectable in the SFMSE[1:0] bits in the SFMSMD register. When the specified
extension time elapses, the QSSL signal returns to the high level to automatically end the SPI bus cycle being suspended.
If the SFMSE[1:0] bits are set to 11b, QSSL is extended infinitely. This increases the power consumption of the serial
flash, so the system must be designed accordingly.
Instruction
(read)
24-bit address
8-bit data x2
8-bit data x2
8-bit data x2
QSPCLK
QSSL
QIO0
Instruction
A23-A16
A15-A8
QIO1
Figure 37.32
A7-A0
D7-D0
D15-D8
D7-D0
D15-D8
D7-D0
D15-D8
Successive data read operations using the SPI bus cycle extension
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37.8
37. Quad Serial Peripheral Interface (QSPI)
XIP Control
Some serial flash devices allow latencies to be reduced by skipping instruction code reception for flash reads. This
instruction code skip function is selected in mode data received during the dummy cycle period of the previous serial bus
cycle.
In the dummy cycle of the Fast Read instructions, the QSPI controls the XIP mode of the serial flash by using the serial
data signal to send the mode data set in the SFMXD[7:0] bits in the SFMSDC register during the first 2 cycles, as shown
in Figure 37.33.
The mode data to enable the XIP mode differs for each serial flash. Accordingly, set the appropriate mode data in the
SFMXD[7:0] bits.
Address
Dummy
Address
Dummy
Address
Dummy
QSPCLK
QSSL
Mode
Figure 37.33
37.8.1
Mode
QIO0
12
8
4
0
4
0
6
4
2
0
2
0
QIO1
13
9
5
1
5
1
7
5
3
1
3
1
QIO2
14
10
6
2
6
2
QIO3
15
11
7
3
7
3
Extended SPI protocol
- Fast Read Quad I/O
Extended SPI protocol
- Fast Read Dual I/O
Quad SPI protocol
Dual SPI protocol
Mode
3
2
1
0
1
0
Extended SPI protocol
- Fast Read Quad Output
- Fast Read Dual Output
- Fast Read
XIP mode control data
Selecting the XIP Mode
To select the XIP mode, specify the XIP mode configuration for the serial flash device in the SFMXD[7:0] bits in the
SFMSDC register, and set the SFMXEN bit to 1. In the dummy cycle of the next Fast Read instruction, the mode data
specified in the SFMXD[7:0] bits is transferred to the serial flash device. From that point, the XIP mode is enabled in
both the serial flash controller and the serial flash device. To confirm completion of the XIP mode select procedure, read
1 from the SFMXST bit in the SFMSDC register.
Note:
37.8.2
Set the SFMXD[7:0] bits in the SFMSDC register to the XIP mode setting data specified for the actual serial flash
device. The XIP mode of the serial flash controller is only enabled in the SFMXEN bit, regardless of the
SFMXD[7:0] setting in the SFMSDC register.
Releasing the XIP Mode
To release the XIP mode, specify the release configuration for the serial flash in the SFMXD[7:0] bits in the SFMSDC
register, and clear the SFMXEN bit to 0. In the dummy cycle of the next Fast Read instruction, the mode data specified in
the SFMXD[7:0] bits is transferred to the serial flash during the first two-cycle period. From that point, the XIP mode is
disabled in both the QSPI and the serial flash device. To confirm completion of the XIP mode release procedure, read 0
from the SFMXST bit in the SFMSDC register
Note:
Set the SFMXD[7:0] bits in the SFMSDC register to the XIP mode setting data specified for the actual serial flash
device. The XIP mode of the serial flash controller is only disabled in the SFMXEN bit, regardless of the
SFMXD[7:0] setting in the SFMSDC register.
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37.9
37. Quad Serial Peripheral Interface (QSPI)
QIO2 and QIO3 Pin States
The QIO2 and QIO3 pin states depend on the serial interface read mode specified in the SFMRM[2:0] bits in the
SFMSMD register.
Table 37.9
QIO2 and QIO3 pin states
SFMSMD.SFMRM[2:0] bits
111
QIO2 pin state*1
QIO3 pin state*2
Remarks
Input or output as a serial data
signal (standby level is Hi-Z)
Input or output as serial data
signal (standby level is Hi-Z)
Fast Read Quad I/O
Output SFMWPL bit variable of
SFMPMD register (initial output
variable is low level)
Output high level
Fast Read Dual I/O
Setting prohibited
110
101
100
011
010
Note 1.
Note 2.
Fast Read Quad Output
Fast Read Dual Output
001
Fast Read
000
Read (Initial State)
The serial flash can also use the QIO2 pin for the WP function.
The serial flash can also use the QIO3 pin for the HOLD or RESET function.
37.10 Direct Communication Mode
37.10.1
About Direct Communication
The QSPI can read the serial flash contents by automatically converting a ROM read bus cycle to an SPI bus cycle.
However, serial flash devices have many different functions in addition to memory data read, including ID information
read, erase, programming, and status information read. There is no standardized instruction set for using these functions,
and more functions are being added rapidly by different vendors to different devices. It is difficult to support these
functions by hardware control.
The QSPI flexibly supports these serial flash devices by providing a means for software to directly communicate with the
serial flash, so that software can create any SPI bus cycle required.
37.10.2
Using Direct Communication Mode
To communicate directly with serial flash, transition to direct communication mode by setting the DCOM bit in the
SFMCMD register to 1. While direct communication mode is selected, ordinary flash read operation is disabled. For
ordinary flash access after direct communication, terminate direct communication mode by setting the DCOM bit in the
SFMCMD register to 0.
Note:
If the QSPI is set to the XIP mode, you must terminate the XIP mode before starting direct communication mode.
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37.10.3
37. Quad Serial Peripheral Interface (QSPI)
Generating the SPI Bus Cycle during Direct Communication
The SPI bus cycle in direct communication starts on the first access to the SFMCOM port and ends with a write to the
SFMCMD register, after a series of I/O operations is performed through the SFMCOM port. At that point, a write to the
SFMCOM port is converted to a one-byte transmission to the SPI bus, and a read from the SFMCOM port is converted to
a one-byte reception from the SPI bus.
During the period from the first access to the SFMCOM port to the last write operation to the SFMCMD register, the
serial flash select signal is held active to notify the serial flash that a series of SPI bus cycles is in progress.
Note:
In direct communication mode, all writes to registers other than SFMCMD (including SFMSMD, SFMSSC,
SFMSKC, SFMSST, SFMCST, SFMSIC, SFMSAC, SFMSDC, SFMSPC, and SFMPMD) are disabled. With this
circuit configuration, writing to a register area other than the SFMCOM port terminates the SPI bus cycle.
However, do not write to a register area other than SFMCMD as a way to terminate the SPI bus cycle. This
operation is not guaranteed as a normal function.
The following is an example program for direct communication.
//### CAUTION! ### This code must be outside the serial flash that is going to be controlled.
// Define specific instruction codes of the target serial flash device.
#define Instruction_FREAD 0x0B // Fast Read
#define Instruction_RDSR 0x05 // Read Status register
#define Instruction_RDID 0x9F // Read Identification
#define Instruction_WREN 0x06 // Write Enable
#define Instruction_CERA 0xC7 // Chip Erase
unsigned char mfid, mtype, mcap, data, temp;
SFMCMD = 0x01; // Enable direct operation
// Get the device identification assigned by JEDEC.
SFMCOM = Instruction_RDID; // put “Read Identification” instruction (open SPI bus cycle)
mfid = (unsigned char) SFMCOM; // get “Manufacturer Identification”
mtype = (unsigned char) SFMCOM; // get “Memory Type”
mcap = (unsigned char) SFMCOM; // get “Memory Capacity”
SFMCMD = 0x01h; // close SPI bus cycle
// Get one byte from the address 0x012345h.
SFMCOM = Instruction_FREAD; // put “Fast Read” instruction (open SPI bus cycle)
SFMCOM = 0x01; // put upper byte of the address 0x012345
SFMCOM = 0x23; // put middle byte of the target address 0x012345
SFMCOM = 0x45; // put lower byte of the target address 0x012345
temp = (unsigned char) SFMCOM; // get one byte dummy code for FAST READ transaction
data = (unsigned char) SFMCOM; // get the data
SFMCMD = 0x01; // close SPI bus cycle
// Erase All contents.
SFMCOM = Instruction_WREN; // put “Write Enable” instruction (open SPI bus cycle)
SFMCMD = 0x01; // close SPI bus cycle
SFMCOM = Instruction_CERA; // put “Chip Erase” instruction (open SPI bus cycle)
SFMCMD = 0x01; // close SPI bus cycle
SFMCOM = Instruction_RDSR; // put “Read Status Register” instruction (open SPI bus cycle)
while (SFMCOM & 0x01){}; // Polling “Write Progress Bit” until completion
SFMCMD = 0x01; // close SPI bus cycle
SFMCMD = 0x00; // Disable direct operation
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37. Quad Serial Peripheral Interface (QSPI)
Instruction
(read)
ID byte-1
ID byte-2
ID byte-3
D7-D0
D7-D0
D7-D0
QSPCLK
QSSL
SIO0OE
(internal signal)
Instruction
QIO0
QIO1
(1)
SFMCMD = 01h;
(2)
(3)
(4)
SFMCOM = Instruction_RDID;
mfid = (unsigned char) SFMCOM;
mtype = (unsigned char)
SFMCOM;
mcap = (unsigned char) SFMCOM;
SFMCMD = 01h;
SFMCMD = 00h;
(5)
(6)
(7)
Figure 37.34
Note:
// Enable direct operation
// Get the device identification assigned by JEDEC
// Put “Read Identification” instruction (open the transaction)
// Get ID byte-1 “Manufacturer Identification”
// Get ID byte-2 “Memory Type”
// Get ID byte-3 “Memory Capacity”
// Close the transaction
// Disable direct operation
Example of direct communication timing for ID read
When Extended SPI protocol is used in direct communication mode, the standard Read or Fast Read instruction
must be used to reference the contents of the serial flash. The QSPI does not support Fast Read Dual Output,
Fast Read Dual I/O, Fast Read Quad Output, or Fast Read Quad I/O transfers in this configuration. When these
high-speed read operations are required, use ordinary flash access.
37.11 Operation
37.11.1
Procedure for Changing Settings in Multiple Control Registers
The settings of the QSPI control registers can be changed dynamically during system operation. However, when the
settings of multiple control registers are changed sequentially, an SPI bus cycle might occur before all of the registers are
updated. The register setting sequence must be carefully designed so that the SPI bus timing specification is satisfied at
all stages of register setting changes.
//
// Making QSPCLK faster
//
SFMSMD = 0x0041; // SFMPAE: 0 SFMPFE: 1 SFMSE:00 SFMRM:01 (prefetch enable fast read)
SFMSSC = 0x04; // SFMSLD: 0 SFMSHD: 0 SFMSW:4 (minimum QSSL high width = 5 sck)
SFMSKC = 0x00; // SFMDTY: 0 SFMDV: 0 (1/2 mode) ### switch clock speed last ###
//
// Making QSPCLK slower
//
SFMSKC = 0x06; // SFMDTY: 0 SFMDV:6 (1/8 mode) ### switch clock speed first ###
SFMSSC = 0x01; // SFMSLD: 0 SFMSHD:0 SFMSW: 1 (minimum QSSL high width = 2 sck)
SFMSMD = 0x0040; // SFMPAE: 0 SFMPFE:1 SFMSE: 00 SFMRM:00 (prefetch enable, standard read)
37.12 Interrupts
When the EROMR bit in the SFMCST register is set to 1, the QSPI requests an interrupt. The EROMR bit is set to 1
when a ROM read access is detected in direct communication mode. Interrupt requests are retained until the EROMR bit
is cleared by a 0 write. For details, see section 14, Interrupt Controller Unit (ICU).
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37. Quad Serial Peripheral Interface (QSPI)
37.13 Usage Notes
37.13.1
Settings for the Module-Stop Function
QSPI operation can be disabled or enabled using Module Stop Control Register B (MSTPCRB). The QSPI is initially
stopped after reset. Releasing the module-stop state enables access to the registers. For details, see section 11, Low
Power Modes.
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38. Cyclic Redundancy Check (CRC) Calculator
38.
Cyclic Redundancy Check (CRC) Calculator
38.1
Overview
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the data. The bit order of the
CRC calculation results can be switched for LSB- or MSB-first communication. Additionally, various CRC generation
polynomials are available for your application. The snoop function allows monitoring of reads from and writes to
specific addresses. This function is useful in applications that require the CRC code to be generated automatically in
certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer.
Table 38.1 lists the CRC calculator specifications and Figure 38.1 shows a block diagram.
Table 38.1
CRC calculator specifications
Parameter
Specifications for 8-bit data
Specifications for 32-bit data
Data size
8-bit
32-bit
Data for CRC calculation*1
CRC code generated for data in 8n-bit units
(where n is a whole number)
CRC code generated for data in 32n-bit units
(where n is a whole number)
CRC processor unit
Operation executed on 8 bits in parallel
Operation executed on 32 bits in parallel
CRC generating polynomial
One of three generating polynomials selectable
[8-bit CRC]
X8 + X2 + X + 1 (CRC-8)
[16-bit CRC]
X16 + X15 + X2 + 1 (CRC-16)
X16 + X12 + X5 + 1 (CRC-CCITT).
One of two generating polynomials selectable
[32-bit CRC]
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10
+ X8 + X7 + X5 + X4 + X2 + X + 1 (CRC-32)
X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20
+ X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8
+ X6 + 1 (CRC-32C).
CRC calculation switching
The bit order of CRC calculation results can be switched for LSB- or MSB-first communication
Module-stop function
Module-stop state can be set to reduce power consumption
CRC snoop
Monitor reads from and writes to a certain
register address
Note 1.
—
The circuit cannot divide data used in CRC calculations. Write data in 8-bit or 32-bit units.
Data bus
CRCDOR/
CRCDOR_HA/
CRCDOR_BY
CRC code
generation
circuit
CRCCR0
CRC snoop block
CRCSAR
Control signal
CRCDIR/
CRCDIR_BY
=?
CRCCR1
Address bus
Figure 38.1
CRC calculator block diagram
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38.2
38. Cyclic Redundancy Check (CRC) Calculator
Register Descriptions
38.2.1
CRC Control Register 0 (CRCCR0)
Address(es): CRC.CRCCR0 4007 4000h
b7
b6
b5
b4
b3
DORCL
R
LMS
—
—
—
0
0
0
0
0
Value after reset:
b2
b1
b0
GPS[2:0]
0
0
0
Bit
Symbol
Bit name
b2 to b0
GPS[2:0]
CRC Generating Polynomial
Switching
b5 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
LMS
CRC Calculation Switching
0: Generate CRC for LSB-first communication
1: Generate CRC for MSB-first communication.
R/W
b7
DORCLR
CRCDOR/CRCDOR_HA/CR
CDOR_BY Register Clear
1: Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register.
This bit is read as 0.
W*1
Note 1.
Description
b2
0
0
0
0
1
0
0
1
1
0
R/W
b0
0: Do not calculate
1: 8-bit CRC-8 (X8 + X2 + X + 1)
0: 16-bit CRC-16 (X16 + X15 + X2 + 1)
1: 16-bit CRC-CCITT (X16 + X12 + X5 + 1)
0: 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +
X10 + X8 + X7 + X5 + X4 + X2 + X + 1)
1 0 1: 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 +
X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1)
Other: Do not calculate.
R/W
This bit must always be set to 1 when writing to this register.
DORCLR bit (CRCDOR/CRCDOR_HA/CRCDOR_BY)
Write 1 to the DORCLR bit to clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register to 0000_0000h. This bit is
read as 0. Only 1 can be written.
LMS bit (CRC Calculation Switching)
The LMS bit selects the bit order of generated CRC code. Transmit the lower-order byte of the CRC code first for LSBfirst communication and the higher-order byte first for MSB-first communication. For details on transmitting and
receiving the CRC code, see section 38.3, Operation.
GPS[2:0] bits (CRC Generating Polynomial Switching)
The GPS[2:0] bits select the CRC generating polynomial.
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38.2.2
38. Cyclic Redundancy Check (CRC) Calculator
CRC Control Register 1 (CRCCR1)
Address(es): CRC.CRCCR1 4007 4001h
b7
b6
CRCSE CRCS
N
WR
Value after reset:
0
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
CRCSWR
Snoop-On-Write/Read Switch
0: Snoop-on-read
1: Snoop-on-write.
R/W
b7
CRCSEN
Snoop Enable
0: Disabled
1: Enabled.
R/W
CRCSWR bit (Snoop-On-Write/Read Switch)
The CRCSWR bit selects the direction of the access in the address monitoring function. When the bit is set to 0 (initial
value), the CRC snoop operation to read a specific register address is enabled. When the bit is set to 1, the CRC snoop
operation to write to a specific register address is enabled.
CRCSEN bit (Snoop Enable)
When the CRCSEN bit is set to 1, CRC snoop operation is enabled. When the bit is set to 0, CRC snoop operation is
disabled.
38.2.3
CRC Data Input Register (CRCDIR/CRCDIR_BY)
Address(es): CRC.CRCDIR/CRCDIR_BY 4007 4004h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CRCDIR is a 32-bit read/write register to write data to, for CRC-32 or CRC-32C calculation. CRCDIR_BY is an 8-bit
read/write register to write data to, for CRC-8, CRC-16, or CRC-CCITT calculation.
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38.2.4
38. Cyclic Redundancy Check (CRC) Calculator
CRC Data Output Register (CRCDOR/CRCDOR_HA/CRCDOR_BY)
Address(es): CRC.CRCDOR/CRCDOR_HA/CRCDOR_BY 4007 4008h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CRCDOR is a 32-bit read/write register for CRC-32 or CRC-32C. CRCDOR_HA is a 16-bit read/write register for CRC16 or CRC-CCITT. CRCDOR_BY is an 8-bit read/write register for CRC-8. Because its initial value is 0000 0000h,
rewrite the CRCDOR/CRCDOR_HA/CRCDOR_BY register to perform the calculations using a value other than the
initial value.
Data written to the CRCDIR/CRCDIR_BY register is CRC-calculated, and the result is stored in the
CRCDOR/CRCDOR_HA/CRCDOR_BY register. If the CRC code is calculated following the transferred data and the
result is 0000 0000h, there is no CRC error.
When an 8-bit CRC (X8 + X2 + X + 1 polynomial) is in use, the valid CRC code is obtained in CRCDOR_BY.
When a 16-bit CRC (X16 + X15 + X2 + 1 or X16 + X12 + X5 + 1 polynomial) is in use, the valid CRC code is obtained in
CRCDOR_HA.
38.2.5
Snoop Address Register (CRCSAR)
Address(es): CRC.CRCSAR 4007 400Ch
Value after reset:
b15
b14
—
—
0
0
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CRCSA[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
CRCSA[13:0]
Register Snoop Address
These bits store the TDR or RDR address in the SCI module to
snoop
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CRCSA[13:0] bits (Register Snoop Address)
The CRCSA[13:0] bits specify the lower 14 bits of the register address monitored by the CRC snoop operation. Only the
following addresses can be used for the CRCSA[13:0] bits:
4007 0003h: SCI0.TDR, 4007 0005h: SCI0.RDR
4007 0023h: SCI1.TDR, 4007 0025h: SCI1.RDR
4007 0043h: SCI2.TDR, 4007 0045h: SCI2.RDR
4007 0063h: SCI3.TDR, 4007 0065h: SCI3.RDR
4007 0083h: SCI4.TDR, 4007 0085h: SCI4.RDR
4007 00A3h: SCI5.TDR, 4007 00A5h: SCI5.RDR
4007 00C3h: SCI6.TDR, 4007 00C5h: SCI6.RDR
4007 00E3h: SCI7.TDR, 4007 00E5h: SCI7.RDR
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38. Cyclic Redundancy Check (CRC) Calculator
4007 0103h: SCI8.TDR, 4007 0105h: SCI8.RDR
4007 0123h: SCI9.TDR, 4007 0125h: SCI9.RDR
4007 000Fh: SCI0.FTDRL, 4007 0011h: SCI0.FRDRL
4007 002Fh: SCI1.FTDRL, 4007 0031h: SCI1.FRDRL
4007 004Fh: SCI2.FTDRL, 4007 0051h: SCI2.FRDRL
4007 006Fh: SCI3.FTDRL, 4007 0071h: SCI3.FRDRL
4007 008Fh: SCI4.FTDRL, 4007 0091h: SCI4.FRDRL
4007 00AFh: SCI5.FTDRL, 4007 00B1h: SCI5.FRDRL
4007 00CFh: SCI6.FTDRL, 4007 00D1h: SCI6.FRDRL
4007 00EFh: SCI7.FTDRL, 4007 00F1h: SCI7.FRDRL
4007 010Fh: SCI8.FTDRL, 4007 0111h: SCI8.FRDRL
4007 012Fh: SCI9.FTDRL, 4007 0131h: SCI9.FRDRL.
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38.3
38. Cyclic Redundancy Check (CRC) Calculator
Operation
38.3.1
Basic Operation
The CRC calculator generates CRC codes for use in LSB- or MSB-first transfers.
The following examples illustrate the CRC code generation for input data (F0h) using the 16-bit CRC-CCITT-generating
polynomial (X16 + X12 + X5 + 1). In these examples, the value of the CRC Data Output Register (CRCDOR_HA) is
cleared before CRC calculation.
When an 8-bit CRC (with the polynomial X8 + X2 + X + 1) is in use, the valid bits of the CRC code are obtained in
CRCDOR_BY. When a 32-bit CRC is in use, the valid bits of the CRC code are obtained in CRCDOR.
1. Write 83h to CRC Control Register 0 (CRCCR0)
CRCCR0
7
1
0
CRCDOR_HA
15
0
0
0
0
0
1
1
0
0
0
0
0
0
0
8
7
0
0
8
7
1
1
0
0
0
0
0
0
0
0
clear CRCDOR/CRCDOR_HA/CRCDOR_BY
2. Write F0h to the CRC Data Input Register (CRCDIR_BY)
CRCDIR_BY
7
1
1
1
CRCDOR_HA
15
0
1
0
0
0
1
0
1
1
1
0
1
1
0
0
0
0
1
1
1
1
CRC code generation
3. Read the calculation result in the CRC Data Output Register (CRCDOR_HA)
CRC code = F78Fh
4. 8-bit serial transmission (LSB-first)
CRC code
7
1
1
1
F
Figure 38.2
1
0
1
1
7
0
7
1
1
Data
0
0
8
0
1
1
1
F
0
7
1
1
0
1
1
F
1
0
0
0
0
Output
0
LSB-first data transmission
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38. Cyclic Redundancy Check (CRC) Calculator
1. Write C3h to CRC Control Register 0 (CRCCR0)
CRCCR0
7
1
1
CRCDOR_HA
15
0
0
0
0
0
1
1
0
0
0
0
0
0
0
8
7
0
0
8
7
1
0
0
0
0
0
0
0
0
0
clear CRCDOR/CRCDOR_HA/CRCDOR_BY
2. Write F0h to the CRC Data Input Register (CRCDIR_BY)
CRCDIR_BY
7
1
1
1
CRCDOR_HA
15
0
1
0
0
0
1
0
1
1
0
1
1
1
0
0
0
1
1
1
1
1
CRC code generation
3. Read the calculation result in the CRC Data Output Register (CRCDOR_HA)
CRC code = EF1Fh
4. 8-bit serial transmission (MSB-first)
CRC code
Data
7
Output
1
1
1
1
F
Figure 38.3
0
0
0
0
0
7
0
1
1
1
E
0
1
1
1
F
0
7
1
0
0
0
0
1
1
1
1
1
1
F
MSB-first data transmission
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38. Cyclic Redundancy Check (CRC) Calculator
1. 8-bit serial reception (LSB-first)
CRC code
Data
0 7
7
1
1
1
1
0
1
F
1
1
1
7
0
0 7
0
0
0
1
1
8
1
1
1
1
F
1
1
0
0
F
0
0
Input
0
2. Write 83h to CRC Control Register 0 (CRCCR0)
CRCCR0
CRCDOR_HA
7
0
1
0
0
0
0
0
1
1
15
0
0
0
0
0
0
0
8
7
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
clear CRCDOR/CRCDOR_HA/CRCDOR_BY
3. Write F0h to the CRC Data Input Register (CRCDIR_BY)
CRCDIR_BY
CRCDOR_HA
7
1
0
1
1
1
0
0
0
0
15
1
1
1
1
0
1
1
8
7
1
1
8
7
1
0
CRC code generation
4. Write 8Fh to the CRC Data Input Register (CRCDIR_BY)
CRCDOR_HA
CRCDIR_BY
7
1
0
0
0
1
1
1
0
15
1
0
0
0
0
0
0
0
0
8
7
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
CRC code generation
5. Write F7h to the CRC Data Input Register (CRCDIR_BY)
CRCDIR_BY
CRCDOR_HA
7
1
0
1
1
1
0
1
1
1
15
0
0
0
0
CRC code generation
6. Read the calculation result in the CRC Data Output Register (CRCDOR_HA)
CRC code = 0000h no error
Figure 38.4
LSB-first data reception
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38. Cyclic Redundancy Check (CRC) Calculator
1. 8-bit serial reception (MSB-first)
CRC code
Data
0 7
7
Input
1
1
1
1
0
0
F
0
0
07
1
1
0
1
0
1
1
E
1
1
0
0
0
F
0
1
1
1
1
1
1
F
2. Write C3h to CRC Control Register 0 (CRCCR0)
CRCCR0
CRCDOR_HA
7
0
1
1
0
0
0
0
1
1
15
0
0
0
0
0
0
0
8
7
0
0
8
7
1
0
0
0
0
0
0
0
0
0
clear CRCDOR/CRCDOR_HA/CRCDOR_BY
3. Write F0h to the CRC Data Input Register (CRCDIR_BY)
CRCDIR_BY
CRCDOR_HA
7
1
0
1
1
1
0
0
0
0
15
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
CRC code generation
4. Write EFh to the CRC Data Input Register (CRCDIR_BY)
CRCDOR_HA
CRCDIR_BY
7
0
1
1
1
0
1
1
1
1
15
0
0
0
8
7
1
0
8
7
0
0
0
CRC code generation
5. Write 1Fh to the CRC Data Input Register (CRCDIR_BY)
CRCDIR_BY
CRCDOR_HA
7
0
0
0
0
1
1
1
1
1
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CRC code generation
6. Read the calculation result in the CRC Data Output Register (CRCDOR_HA)
CRC code = 0000h no error
Figure 38.5
MSB-first data reception
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38.3.2
38. Cyclic Redundancy Check (CRC) Calculator
CRC Snoop
The CRC snoop function monitors the reads from and writes to a specified I/O register address and performs a CRC
calculation on the data read from and written to the register address automatically. Because the CRC snoop recognizes
the writes to and reads from a specific register address as a trigger to automatically perform a CRC calculation, writing
data to the CRCDIR_BY register is not required. All I/O register addresses specified in section 38.2.5, Snoop Address
Register (CRCSAR) are subject to the CRC snoop. The CRC snoop is useful in monitoring the writes to the serial
transmit buffer, and the reads from the serial receive buffer.
To use this function, write a target I/O register address to the CRCSA13 to CRCSA0 bits in the CRCSAR register, and set
the CRCSEN bit in the CRCCR1 register to 1. Then, set the CRCSWR bit in the CRCCR1 register to 1 to enable
snooping on the writes to the target address, or set the CRCSWR bit in the CRCCR1 register to 0 to enable snooping on
the reads from the target address.
When both the CRCSEN and CRCSWR bits are set to 1 and data is written to a target I/O register address in a bus master
module (including the CPU, DMAC, and DTC), the CRC calculator stores the data in the CRCDIR_BY register and
performs CRC calculation. Similarly, when the CRCSEN bit is set to 1 and the CRCSWR bit to 0, and data is read from
a target I/O register address in a bus master module (including the CPU, DMAC, and DTC), the CRC calculator stores
the data in the CRCDIR_BY register and performs a CRC calculation.
CRC calculation is performed 1 byte at a time. When the target I/O register address is accessed in words (16 bits) or long
words (32 bits), a CRC code is generated on the lower byte (1 byte) of data.
38.4
38.4.1
Usage Notes
Settings for the Module-Stop Function
CRC calculator operation can be disabled or enabled using Module Stop Control Register C (MSTPCRC). The CRC
calculator is initially stopped after reset. Releasing the module-stop state enables access to the registers. For details, see
section 11, Low Power Modes.
38.4.2
Note on Transmission
The transmission sequence for the CRC code differs depending on whether transmission is LSB-first or MSB-first.
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38. Cyclic Redundancy Check (CRC) Calculator
When transmitting 32-bit data (for operation on 8 bits in parallel)
1. CRC code
After specifying the method for generation calculation, write data to CRCDIR in the order (1), (2), (3), and (4).
7
0
(1)
CRCDIR
7
0
(2)
CRCDIR
7
0
(3)
CRCDIR
7
0
(4)
CRCDIR
CRC code generation
8 7
15
0
CRC code (L)
CRC code (H)
CRCDOR
2. Transmit data
(i) When transmission is LSB-first
CRC code
7
07
(H)
0 7
(L)
07
(4)
07
(3)
(ii) When transmission is MSB-first
7
Output
Figure 38.6
0
(1)
Output
CRC code
07
(1)
07
(2)
07
(2)
0 7
(3)
0 7
(4)
07
(H)
0
(L)
LSB-first and MSB-first data transmission
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39. Serial Sound Interface Enhanced (SSIE)
39.
Serial Sound Interface Enhanced (SSIE)
39.1
Overview
The Serial Sound Interface Enhanced (SSIE) can transmit and receive audio data to and from various devices that support
different audio data formats, such as I2S, monaural, and TDM.
39.2
Features
Table 39.1
SSIE specifications
Parameter
Description
Number of channels
One channel, SSIE0
Communication mode
Master/slave
Transmission/reception (SSIE0 full-duplex communication or half-duplex
communication).
Communication format
I2S format
Monaural format
TDM format.
Serial data
MSB first
Data can be left-justified or right-justified.
Data delay (1 clock cycle) or no delay selectable for the period from SSILRCK/SSIFS
to SSITXD0/SSIRXD0/SSIDATA0
System word length: 8, 16, 24, 32, 48, 64, 128, or 256 bits
Data word length: 8, 16, 18, 20, 22, 24, or 32 bits
Padding polarity: Low or high.
In master mode
Two clock sources available (AUDIO_CLK/GPT output (GTIOC1A))
Clock source division ratio: 1/1, 1/2, 1/4, 1/6, 1/8, 1/12, 1/16, 1/24, 1/32, 1/48, 1/64,
1/96, and 1/128.
Supply/stop is selectable while communication is halted.
In master/slave mode
Polarity (rising edge or falling edge) selectable
LR clock/frame
synchronization
(SSILRCK/SSIFS)
In master mode
Polarity (low level or high level) selectable
Supply/stop is selectable while communication is halted.
Transmit data
(SSITXD0/SSIDAT
A0) and receive
data
(SSIRXD0/SSIDAT
A0)
Transmission
Muting method (transmission of transmit FIFO data or transmission of data fixed to 0)
selectable.
FIFO
Capacity
Transmit FIFO/receive FIFO: 4 bytes × 32 stages.
Data alignment
Data alignment method (left-justification or right-justification) selectable for the data
transfer between FIFO and shift register.
Interrupt output
Communication error/idle mode
Receive data full
Transmit data empty.
Bit clock
(SSIBCK)
Interrupt
Low power consumption function
Whether to supply the audio clock selectable in master mode.
Module stop function
Module stop state can be set to reduce power consumption.
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39. Serial Sound Interface Enhanced (SSIE)
The following table lists and defines the terms used for the communication formats that SSIE can use.
Table 39.2
Definition of terms
Term
Definition
Start trigger
First edge of the signal on the SSILRCK/SSIFS pin when the signal is set to the value specified in LRCKP to
enable communication
Frame boundary
Point where SSIE starts transferring the first data of a frame or the point where SSIE ends transferring the
last data of the frame
Frame word number
Number of sound channels per frame
System word length
Number of bits per channel
Data word length
Number of significant bits per channel
Control bits for
communication formats
SSICR register: FRM, DWL, SWL, LRCKP, SPDP, SDTA, PDTA, and DEL bits
SSIFCR register: BSW bit
SSIOFR register: OMOD bit
SSISCR register: TDES[4:0] and RDFS[4:0] bits.
I2S format, Start trigger: LRCK falling edge (LRCKP = 0)
Frame boundary
Frame boundary
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
L channel
R channel
Start trigger
padding
D07 D06 D01 D00
padding
Data word length
D17 D16 D11 D10
Data word length
System word length
System word length
1 frame
Figure 39.1
Definition of communication format
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39.3
39. Serial Sound Interface Enhanced (SSIE)
Block Diagram
Figure 39.2 and Figure 39.3 show a block diagram of SSIE.
Peripheral bus
Interrupt
Control
circuit
SSIFTDR
(32-stage FIFO)
Registers:
SSICR
SSISR
SSIFCR
SSIFSR
SSIOFR
SSISCR
SSIFRDR
(32-stage FIFO)
Serial audio device
SSITXD0
MSB
Shift register
LSB
SSIRXD0
MSB
Shift register
LSB
AUDIO_CLK
Serial clock control
SSIBCK0
Divider
SSILRCK0/
SSIFS0
[Legend]
SSICR:
SSISR:
SSIFCR:
SSIFSR:
SSIOFR:
SSIFTDR:
SSIFRDR:
SSISCR:
Figure 39.2
Bit counter
GTIOC1A
GPT32EH1
Control Register
Status Register
FIFO Control Register
FIFO Status Register
Audio Format Register
Transmit FIFO Data Register
Receive FIFO Data Register
Status Control Register
SSIE block diagram (SSIE0) for full-duplex communication
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39. Serial Sound Interface Enhanced (SSIE)
Peripheral bus
Interrupt
Control
circuit
SSIFTDR
(32-stage FIFO)
Registers:
SSICR
SSISR
SSIFCR
SSIFSR
SSIOFR
SSISCR
SSIFRDR
(32-stage FIFO)
Serial audio device
SSIDATA0
MSB
Shift register
MSB
LSB
Shift register
LSB
AUDIO_CLK
Serial clock control
SSIBCK0
SSILRCK0/
SSIFS0
[Legend]
SSICR:
SSISR:
SSIFCR:
SSIFSR:
SSIOFR:
SSIFTDR:
SSIFRDR:
SSISCR:
Figure 39.3
GTIOC1A
Divider
Bit counter
GPT32EH1
Control Register
Status Register
FIFO Control Register
FIFO Status Register
Audio Format Register
Transmit FIFO Data Register
Receive FIFO Data Register
Status Control Register
SSIE block diagram (SSIE0) for half-duplex communication
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39. Serial Sound Interface Enhanced (SSIE)
Figure 39.4 shows the clock configuration of SSIE.
AUDIO_MCK (Audio clock)
GTIOC1A
1
AUDIO_CLK
Divider
0
BCK (Bit clock)
1
SSIFCR.AUCKE
SSICR.CKDV[3:0]
SSICR.CKS
Sampling clock
Operating clock
Polarity
selection
0
SSICR.MST
SSICR.BCKP
Slave BCK
Output enable
SSIBCK
Master BCK
[Legend]
SSICR:
SSISR:
SSIFCR:
SSIFSR:
SSIOFR:
SSIFTDR:
SSIFRDR:
SSISCR:
Figure 39.4
39.4
Control Register
Status Register
FIFO Control Register
FIFO Status Register
Audio Format Register
Transmit FIFO Data Register
Receive FIFO Data Register
Status Control Register
SSIE clock configuration
Register Descriptions
39.4.1
Control Register (SSICR)
Address(es): SSIE0.SSICR 4004 E000h
b31
b30
—
CKS
0
0
0
0
0
b15
b14
b13
b12
b11
—
MST
0
0
Value after reset:
Value after reset:
b29
b28
b27
b26
b25
b24
IIEN
—
FRM[1:0]
0
0
0
0
0
0
0
0
0
0
0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
SDTA
PDTA
DEL
MUEN
—
TEN
REN
0
0
0
0
0
0
0
TUIEN TOIEN RUIEN ROIEN
BCKP LRCKP SPDP
0
0
0
Bit
Symbol
Bit name
b0
REN
b1
TEN
Transmission and Reception
Enable*2
b2
—
Reserved
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b23
b22
b21
b20
0
b18
DWL[2:0]
CKDV[3:0]
0
b19
0
0
b17
b16
SWL[2:0]
Description
R/W
00: Disables transmission and reception
01: Enables reception (starts reception)
10: Enables transmission (starts transmission)
11: Enables transmission and reception (starts transmission and
reception).
This bit is read as 0. The write value should be 0.
R/W
R/W
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39. Serial Sound Interface Enhanced (SSIE)
Bit
Symbol
Bit name
Description
R/W
b3
MUEN
Mute Enable
0: Disables muting on the next frame boundary
1: Enables muting on the next frame boundary.
R/W
b7 to b4
CKDV[3:0]
Selects Bit Clock Division
Ratio*1
b7
R/W
b8
DEL
Selects Serial Data Delay*1
0: Delay of 1 cycle of SSIBCK between SSILRCK/SSIFS and
SSITXD0/SSIRXD0/SSIDATA0
1: No delay between SSILRCK/SSIFS and
SSITXD0/SSIRXD0/SSIDATA0
In the monaural format, this bit controls the waveform of
SSILRCK/SSIFS.
For details, see section 39.5.2, Monaural Format.
R/W
b9
PDTA
Selects Placement Data
Alignment*1
0: Left-justifies placement data (SSIFTDR, SSIFRDR)
1: Right-justifies placement data (SSIFTDR, SSIFRDR).
R/W
b10
SDTA
Selects Serial Data Alignment
*1
0: Transmits and receives serial data first and then padding bits
1: Transmit and receives padding bits first and then serial data.
R/W
b11
SPDP
Selects Serial Padding
Polarity*1
0: Padding data is at a low level
1: Padding data is at a high level.
R/W
b12
LRCKP
Selects the Initial Value and
Polarity of LR Clock/Frame
Synchronization Signal*1
0: The initial value is at a high level
The start trigger for a frame is synchronized with a falling edge
of SSILRCK/SSIFS
1: The initial value is at a low level
The start trigger for a frame is synchronized with a rising edge
of SSILRCK/SSIFS.
R/W
b13
BCKP
Selects Bit Clock Polarity*1
0: SSILRCK/SSIFS and SSITXD0/SSIRXD0/SSIDATA0 change
at a falling edge (SSILRCK/SSIFS and SSIRXD0/SSIDATA0
are sampled at a rising edge of SSIBCK)
1: SSILRCK/SSIFS and SSITXD0/SSIRXD0/SSIDATA0 change
at a rising edge (SSILRCK/SSIFS and SSIRXD0/SSIDATA0
are sampled at a falling edge of SSIBCK).
R/W
b14
MST
Master Enable*1
0: Slave-mode communication
1: Master-mode communication.
R/W
b15
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b18 to b16
SWL[2:0]
Selects System Word Length
*1
b18
R/W
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0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b4
b16
0: AUDIO_MCK
1: AUDIO_MCK/2
0: AUDIO_MCK/4
1: AUDIO_MCK/8
0: AUDIO_MCK/16
1: AUDIO_MCK/32
0: AUDIO_MCK/64
1: AUDIO_MCK/128
0: AUDIO_MCK/6
1: AUDIO_MCK/12
0: AUDIO_MCK/24
1: AUDIO_MCK/48
0: AUDIO_MCK/96
1: Setting prohibited
0: Setting prohibited
1: Setting prohibited.
0: 8 bits
1: 16 bits
0: 24 bits
1: 32 bits
0: 48 bits
1: 64 bits
0: 128 bits
1: 256 bits.
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Bit
Symbol
39. Serial Sound Interface Enhanced (SSIE)
Bit name
Length*1
b21 to b19
DWL[2:0]
Selects Data Word
b23, b22
FRM[1:0]
Selects Frame Word Number
*1
Description
R/W
b21
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b19
0: 8 bits
1: 16 bits
0: 18 bits
1: 20 bits
0: 22 bits
1: 24 bits
0: 32 bits
1: Setting prohibited.
R/W
Communication format (SSIOFR.OMOD[1:0])
FRM[1:0]
I2S (00b)
Monaural (10b)
TDM (01b)
00b
2
1
Setting prohibited
01b
Setting prohibited
Setting prohibited
4
10b
6
11B
8
b24
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b25
IIEN
Idle Mode Interrupt Output
Enable
0: Disables idle mode interrupt output
1: Enables idle mode interrupt output.
R/W
b26
ROIEN
Receive Overflow Interrupt
Output Enable
0: Disables receive overflow interrupt output
1: Enables receive overflow interrupt output.
R/W
b27
RUIEN
Receive Underflow Interrupt
Output Enable
0: Disables receive underflow interrupt output
1: Enables receive underflow interrupt output.
R/W
b28
TOIEN
Transmit Overflow Interrupt
Output Enable
0: Disables transmit overflow interrupt output
1: Enables transmit overflow interrupt output.
R/W
b29
TUIEN
Transmit Underflow Interrupt
Output Enable
0: Disables transmit underflow interrupt output
1: Enables transmit underflow interrupt output.
R/W
b30
CKS
Selects an Audio Clock for
Master-mode Communication
*1
0: Selects the AUDIO_CLK input
1: Selects the GTIOC1A (GPT output).
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Writing to these bits while SSIE is in a communication state (SSISR.IIRQ = 0) is prohibited. If the value of these bits is changed
by rewriting, subsequent operation is unpredictable.
If the TEN bit or REN bit is rewritten, make sure that the SSISR.IIRQ bit is in the desired status. If the value of the TEN or REN
bit is changed by rewriting, subsequent operation is unpredictable. For example, when transmission or reception is enabled,
check that SSISR.IIRQ is 0. When transmission or reception is disabled, check that SSISR.IIRQ is 1.
With this register, select an audio clock, control interrupt requests, select data formats, and set an operation mode.
TEN and REN bits (Transmission and Reception Enable)
The TEN and REN bits enable/disable transmission and reception. When 1 is written to one of these bits, the
corresponding communication operation starts in synchronization with a start trigger by the SSILRCK/SSIFS signal. For
details, see section 39.8.2 to section 39.8.4. When 0 is written to this bit, the current communication operation stops at
the next frame boundary. To use SSIE for both transmission and reception, always write 1 to these bits together. When
stopping the communication using SSIE, always disable both transmission and reception (write 0 to the TEN and REN
bits).
If you want to stop SSIE before a frame boundary is reached, perform a software reset procedure.
MUEN bit (Mute Enable)
The MUEN bit sets/clears the mute function for the data output from the SSITXD0/SSIDATA0 pin. When this bit is set
to 1 in the middle of a frame, the SSITXD0/SSIDATA0 output changes to 0 at the next frame boundary. When this bit is
set to 0 in the middle of a frame, the SSITXD0/SSIDATA0 output changes to the data of transmit FIFO data register at
the next frame boundary. Note that this bit controls data only. Status flags and interrupt signals are normally generated.
Changing the value of this bit must be performed only after setting the communication format to be used.
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39. Serial Sound Interface Enhanced (SSIE)
System word length: 16 bits (SSICR.SWL[2:0] = 001b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b), MUEN: Enables muting (MUEN = 0 1)
Other control bits of communication format are at their initial values.
MUEN
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIDATA0
L channel
Padding
D07 D06 D05
R channel
D17 D16
Padding
D10
Padding
Data
One frame
Valid from the next frame boundary after three cycles
of SSIBCK.
Mute function is enabled.
System word length: 16 bits (SSICR.SWL[2:0] = 001b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b), MUEN: Disables muting (MUEN = 1 0)
Other control bits of communication format are at their initial values.
MUEN
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIDATA0
R channel
Data + padding
D07 D06
One frame
Valid from the next frame boundary after three cycles
of SSIBCK.
Figure 39.5
Mute function is disabled.
Transmit data with the mute function set
CKDV[3:0] bits (Selects Bit Clock Division Ratio)
The CKDV[3:0] bits set the division ratio of the bit clock based on AUDIO_MCK in master-mode communication (MST
= 1). In slave-mode communication (MST = 0), setting of these bits is invalid.
Writing to this bit must be performed when the supply of AUDIO_MCK is stopped. For details about the timing, see the
detailed description of the AUCKE bit in SSIFCR.
At 1/2 division
AUDIO_MCK
Bit clock
(SSIBCK)
AUDIO_MCK × two cycles
At 1/4 division
AUDIO_MCK
Bit clock
(SSIBCK)
AUDIO_MCK × four cycles
Figure 39.6
Sampling frequencies in master-mode communication
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39. Serial Sound Interface Enhanced (SSIE)
DEL bit (Selects Serial Data Delay)
The DEL bit sets whether or not there will be a delay between SSILRCK/SSIFS and SSITXD0/SSIRXD0/SSIDATA0.
For the I2S or TDM format, set the DEL bit to 0. When the monaural format is used, setting of this bit changes the high
period width of SSILRCK/SSIFS. For details, see section 39.5.2, Monaural Format. When using a compatible
communication format, specify a setting of this bit that enables communication.
When DEL = 0
(with delay)
One frame
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Serial data
One cycle of SSIBCK
When DEL = 1
(without delay)
Serial data
One cycle of SSIBCK
One cycle of SSIBCK
One frame
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.7
Serial data
Serial data
Setting of delay in serial data
PDTA bit (Selects Placement Data Alignment)
The PDTA bit sets how to align the placement data. With the setting of data word length as 32 bits (SSICR.DWL[2:0] =
110b), this bit is invalid.
At transmission, see Figure 39.8.
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39. Serial Sound Interface Enhanced (SSIE)
First transmission data
Second transmission data
Third transmission data
Fourth transmission data
SSIFTDR
DWL[2:0]
PDTA = 0 (left-justify)
000 (8 bits)
7
7
7
7
001 (16 bits)
15
15
15
15
010 to 100
18bit : X = 17
20bit : X = 19
22bit : X = 21
24bit : X = 23
X
X
X
X
110 (32 bits)
31
31
31
31
0
0
0
0
PDTA = 1 (right-justify)
Invalid
Invalid
Invalid
Invalid
0
0
0
0
Invalid
Invalid
Invalid
Invalid
0
0
0
0
Invalid
Invalid
Invalid
Invalid
Setting prohibited
7
7
7
7
Setting prohibited
15
15
15
15
Invalid
Invalid
Invalid
Invalid
X
X
X
X
0
0
0
0
Setting prohibited
0
0
0
0
Transmission shift register
0
0
0
0
Invalid
Invalid
Invalid
Invalid
0
0
0
0
X
X
X
X
Invalid
Invalid
Invalid
Invalid
0
0
0
0
Invalid
Invalid
Invalid
Invalid
31
31
31
31
0
0
0
0
111
(Setting prohibited)
Figure 39.8
Alignment of placement data at transmission
At reception, see Figure 39.9.
First transmission data
Second transmission data
Third transmission data
Fourth transmission data
SSIFRDR
DWL[2:0]
Receive shift register
000 (8 bits)
Invalid
Invalid
Invalid
Invalid
001 (16 bits)
Invalid
Invalid
Invalid
Invalid
010 to 100
18bit : X = 17
20bit : X = 19
22bit : X = 21
24bit : X = 23
Invalid
Invalid
Invalid
Invalid
110 (32 bits)
31
31
31
31
X
X
X
X
7
7
7
7
15
15
15
15
PDTA = 0 (left-justify)
0
0
0
0
7
7
7
7
0
0
0
0
15
15
15
15
0
0
0
0
X
X
X
X
0
0
0
0
31
31
31
31
0
0
0
0
Invalid
Invalid
Invalid
Invalid
0
0
0
0
Setting prohibited
Invalid
Invalid
Invalid
Invalid
0
0
0
0
PDTA = 1 (right-justify)
Setting prohibited
Invalid
Invalid
Invalid
Invalid
0
0
0
0
Invalid
Invalid
Invalid
Invalid
X
X
X
X
0
0
0
0
Setting prohibited
111
(Setting prohibited)
Figure 39.9
Alignment of placement data at reception
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39. Serial Sound Interface Enhanced (SSIE)
SDTA bit (Selects Serial Data Delay)
The SDTA bit sets how to align the serial data and padding bits. For communication without padding bits, this bit is
invalid.
System word length: 16 bits (SSICR.SWL[2:0] = 001b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Data alignment: data → padding (SDTA = 0)
Other control bits of communication format are at their initial values.
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIRXD0/
SSIDATA0
D07 D06 D01 D00
R channel
Padding
D17 D16 D11 D10
8 bits (padding)
Padding
System word length: 16 bits (SSICR.SWL[2:0] = 001b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Data alignment: padding → data (SDTA = 1)
Other control bits of communication format are at their initial values.
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
L channel
R channel
D11 D10
D07 D06 D01 D00
8 bits (padding)
Figure 39.10
D17 D16 D11 D10
8 bits (padding)
Alignment setting of serial data with padding bits
SPDP bit (Selects Serial Padding Polarity)
The SPDP bit sets the polarity of padding bits.
System word length: 16 bits (SSICR.SWL[2:0] = 001b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Padding polarity: 0 output (SPDP = 0), Alignment: data → padding (SDTA = 0)
Other control bits of communication format are at their initial values.
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIRXD0/
SSIDATA0
D07
D06
R channel
D01
D00
Padding
D17
D16
D11
D10
8 bits (padding)
8 bits (padding)
System word length: 16 bits (SSICR.SWL[2:0] = 001b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Padding polarity: 1 output (SPDP = 1), Alignment: data → padding (SDTA = 0)
Other control bits of communication format are at their initial values.
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIRXD0/
SSIDATA0
D07
Padding
Figure 39.11
D06
R channel
D01
D00
D17
8 bits (padding)
D16
D11
D10
8 bits (padding)
Padding bit polarity
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39. Serial Sound Interface Enhanced (SSIE)
LRCKP bit (Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal)
The LRCKP bit sets the initial value and polarity of SSILRCK/SSIFS. Set this bit according to the communication
format to be used in SSIE. See section Table 39.3, Initial output value and polarity of SSILRCK/SSIFS pin. For the
slave-mode communication (MST = 0), only the start trigger is used.
Writing to these bits must be performed when the LR clock supply to the SSILRCK/SSIFS pin is stopped. For details
about the output of LR clock, see the detailed description of the LRCONT bit in SSIOFR.
Table 39.3
Initial output value and polarity of SSILRCK/SSIFS pin
Communication Format
Expected Initial State
Setting Value of LRCKP
I2S
High
0
Monaural
Low
1
TDM
Low
1
Note:
When the format to be used is compatible with the I2S, monaural, or TDM format, specify the settings to enable communication
with the respective formats.
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
LR clock polarity: L channel = Low, R channel = High (LRCKP = 0)
Other control bits of communication format are at their initial values.
One frame
One system word
One system word
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
L channel
D11
D10
D07
D06
R channel
D01
D00
D17
D16
D11
D10
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
LR clock polarity: L channel = High, R channel = Low (LRCKP = 1)
Other control bits of communication format are at their initial values.
One frame
One system word
One system word
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.12
L channel
D11
D10
D07
D06
R channel
D01
D00
D17
D16
D11
D10
LR clock/frame synchronization polarity setting
BCKP bit (Selects Bit Clock Polarity)
The BCKP bit sets the bit clock polarity.
Writing to this bit must be performed when the supply of AUDIO_MCK is stopped. For details about the timing, see the
detailed description of the AUCKE bit in section 39.4.3, FIFO Control Register (SSIFCR).
Table 39.4
Bit clock polarity (1 of 2)
Communication
Master/Slave
Timing
BCKP = 0
BCKP = 1
Reception
Slave
At SSILRCK/SSIFS sampling
SSIBCK rising edge
SSIBCK falling edge
Master/slave
At SSIRXD0/SSIDATA0 sampling
SSIBCK rising edge
SSIBCK falling edge
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Table 39.4
39. Serial Sound Interface Enhanced (SSIE)
Bit clock polarity (2 of 2)
Communication
Master/Slave
Timing
BCKP = 0
BCKP = 1
Transmission
Master
At change of SSILRCK/SSIFS output
SSIBCK falling edge
SSIBCK rising edge
Master/slave
At change of SSITXD0/SSIDATA0 output
SSIBCK falling edge
SSIBCK rising edge
MST bit (Master Enable)
The MST bit sets the master-/slave-mode communication.
Writing to this bit must be performed when the supply of AUDIO_MCK is stopped. For details about the timing, see the
detailed description of the AUCKE bit in section 39.4.3, FIFO Control Register (SSIFCR).
SWL[2:0] bits (Selects System Word Length)
The SWL[2:0] bits set the number of bits in one system word. Padding bits are sent and received in relation with one data
word set in DWL[2:0]. See Table 39.11 for details.
Writing to these bits must be performed when the LR clock supply to the SSILRCK/SSIFS pin is stopped. For details
about the output of LR clock, see the detailed description of the LRCONT bit in section 39.4.7, Audio Format Register
(SSIOFR).
DWL[2:0] bits (Selects Data Word Length)
The DWL[2:0] bits set the number of bits in one data word. The data word length (number of bits per data word) must
not exceed the system word length (number of bits per system word). For details, see Table 39.11.
FRM[1:0] bits (Selects Frame Word Number)
The FRM[1:0] bits set the frame word number in individual communication formats.
Writing to these bits must be performed when the LR clock supply to the SSILRCK/SSIFS pin is stopped. For details
about the output of LR clock, see the detailed description of the LRCONT bit in SSIOFR.
TDM format (OMOD[1:0] = 01b)
FRM[1:0] = 01b: Frame word 4
One frame
System word
System word
System word
System word
FRM[1:0] = 10b: Frame word 6
One frame
System word
System word
System word
System word
System word
System word
FRM[1:0] = 11b: Frame word 8
One frame
System word
Figure 39.13
System word
System word
System word
System word
System word
System word
System word
Frame word number
IIEN bit (Idle Mode Interrupt Output Enable)
The IIEN bit enables/disables the output of idle mode interrupts. By enabling this bit (set it to 1), an interrupt is output at
a rising edge of SSISR.IIRQ = 1. An interrupt is also output when this bit is changed from 0 to 1 while SSISR.IIRQ = 1.
ROIEN bit (Receive Overflow Interrupt Output Enable)
The ROIEN bit enables/disables the output of receive overflow interrupts. By enabling this bit (set it to 1), an interrupt is
output at a rising edge of SSISR.ROIRQ = 1. An interrupt is also output when this bit is changed from 0 to 1 while
SSISR.ROIRQ = 1.
RUIEN bit (Receive Underflow Interrupt Output Enable)
The RUIEN bit enables/disables the output of receive underflow interrupts. By enabling this bit (set it to 1), an interrupt
is output at a rising edge of SSISR.RUIRQ = 1. An interrupt is also output when this bit is changed from 0 to 1 while
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39. Serial Sound Interface Enhanced (SSIE)
SSISR.RUIRQ = 1.
TOIEN bit (Transmit Overflow Interrupt Output Enable)
The TOIEN bit enables/disables the output of transmit overflow interrupts. By enabling this bit (set it to 1), an interrupt
is output at a rising edge of SSISR.TOIRQ = 1. An interrupt is also output when this bit is changed from 0 to 1 while
SSISR.TOIRQ = 1.
TUIEN bit (Transmit Underflow Interrupt Output Enable)
The TUIEN bit enables/disables the output of transmit underflow interrupts. By enabling this bit (set it to 1), an interrupt
is output at a rising edge of SSISR.TUIRQ = 1. An interrupt is also output when this bit is changed from 0 to 1 while
SSISR.TUIRQ = 1.
CKS bit (Selects an Audio Clock for Master-mode Communication)
The CKS bit sets the audio clock in master-mode communication (MST = 1). In slave-mode communication (MST = 0),
setting of this bit is invalid.
Writing to this bit must be performed when the supply of AUDIO_MCK is stopped. For details about the timing, see the
detailed description of the AUCKE bit in SSIFCR.
39.4.2
Status Register (SSISR)
Address(es): SSIE0.SSISR 4004 E004h
b31
b30
—
—
0
0
0
0
0
b15
b14
b13
b12
—
—
—
0
0
0
Value after reset:
Value after reset:
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
IIRQ
—
—
—
—
—
—
—
—
—
0
1
0
0
0
0
0
0
0
0
0
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
TUIRQ TOIRQ RUIRQ ROIRQ
Bit
Symbol
Bit name
Description
R/W
b24 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25
IIRQ
Idle Mode Status Flag
0: In the communication state
1: In the idle state.
R
b26
ROIRQ
Receive Overflow Error Status
Flag
0: No receive overflow error is generated
1: A receive overflow error is generated.
R/W
b27
RUIRQ
Receive Underflow Error Status
Flag
0: No receive underflow error is generated
1: A receive underflow error is generated.
R/W
b28
TOIRQ
Transmit Overflow Error Status
Flag
0: No transmit overflow error is generated
1: A transmit overflow error is generated.
R/W
b29
TUIRQ
Transmit Underflow Error Status
flag
0: No transmit underflow error is generated
1: A transmit underflow error is generated.
R/W
b31, b30
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
This register is configured with status flags that indicate SSIE operational state.
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39. Serial Sound Interface Enhanced (SSIE)
IIRQ bit (Idle Mode Status Flag)
The IIRQ is a status flag that indicates the idle state. It indicates whether SSIE is in an idle state or a communication
state.
For details, see Figure 39.14 and Figure 39.15.
Communication format: I2S, Data word length: 8 bits, System word length: 8 bits
Other control bits of the communication format are at their initial values.
Two cycles
Two cycles
PCLKB
SSICR.TEN
Three cycles
SSICR.REN
Data enough for one frame
SSIFTDR
IIRQ
Data not enough for one frame
Transmission
starts from the
Three cycles next start trigger
one cycle
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIDATA0
D07 D06
R channel
D00 D17 D16
One system word
D10
One system word
One frame
Figure 39.14
IIRQ setting timing (transmission)
Transmitter (dedicated to transmission)
[Clearing condition]
While transmission was enabled (SSICR.TEN = 1 and SSICR.REN = 0), the transmit data for a transmission frame was
written to the SSIFTDR register, and a start trigger was generated by the SSILRCK/SSIFS signal.
[Clearing timing]
1 SSIBCK cycle + 2 PCLKB cycles after generation of the start trigger that is the clearing condition.
[Setting condition]
While transmission and reception were disabled (SSICR.TEN = 0 and SSICR.REN = 0), transmission of one frame was
complete.
[Setting timing]
2 PCLKB cycles after the end of transmission (at a frame boundary) that is the setting condition.
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39. Serial Sound Interface Enhanced (SSIE)
Communication format: I2S, Data word length: 8 bits, System word length: 8 bits
Other control bits of the communication format are at their initial values.
two cycles
two cycles
PCLKB
SSICR.REN
IIRQ
Reception starts
from the next one
three cycles start trigger
cycle
SSIBCK
SSILRCK/
SSIFS
L channel
SSIRXD0/
SSIDATA0
D07 D06
R channel
D00 D17 D16
One system word
D10
One system word
One frame
Figure 39.15
IIRQ setting timing (reception)
Receiver (dedicated to reception)
[Clearing condition]
While reception was enabled (SSICR.TEN = 0 and SSICR.REN = 01, a start trigger was generated by the
SSILRCK/SSIFS signal.
[Clearing timing]
1 SSIBCK cycle + 2 PCLKB cycles after generation of the start trigger that is the clearing condition.
[Setting condition]
While transmission and reception were disabled (SSICR.TEN = 0 and SSICR.REN = 0), reception of one frame was
complete.
[Setting timing]
2 PCLKB cycles after the end of reception (at a frame boundary) that is the setting condition.
Transceiver (transmission and reception)
[Clearing condition]
While transmission and reception were enabled (SSICR.TEN = 1 and SSICR.REN = 1), the transmit data for a
transmission frame was written to the SSIFTDR register, and a start trigger is generated by the SSILRCK/SSIFS signal.
[Clearing timing]
1 SSIBCK cycle + 2 PCLKB cycles after generation of the start trigger that is the clearing condition.
[Setting condition]
While transmission and reception were disabled (SSICR.TEN = 0 and SSICR.REN = 0), transmission of one frame was
complete.
[Setting timing]
2 PCLKB cycles after the end of transmission (at a frame boundary) that is the setting condition.
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39. Serial Sound Interface Enhanced (SSIE)
ROIRQ bit (Receive Overflow Error Status Flag)
The ROIRQ is a status flag that indicates a receive overflow error. This flag is set by automatic determination but it must
be cleared by register access. This flag indicates that received data is supplied at a higher rate than requested. Data is not
transferred from the Receive Shift Register to SSIFRDR where a receive overflow error is generated. For the procedure
to recover from the overflow error, see section 39.8.6, Error Handling. This flag is not cleared by a Receive FIFO Data
Register Reset (SSIFCR.RFRST).
[Priority order for setting and clearing]
Setting is prioritized.*1
[Clearing condition]
When either of the following operations is done:
1. Writing 0 to this bit after reading 1 from this bit.*2
2. Enabling communication (changing SSICR.REN from 0 to 1).
[Clearing timing]
Clearing timing corresponding to the specified clearing condition:
1. When 0 is written to this bit after reading 1 from this bit (same as the timing in Figure 39.19).
2. 1 PCLKB cycle after writing 1 to SSICR.REN.*3
Note 1. This bit is cleared by a software reset (SSIFCR.SSIRST = 1). Software reset has priority over all the specified
clearing conditions.
Note 2. After reading 1 from this bit, this bit is cleared when one of the following three conditions is met:
- A software reset (SSIFCR.SSIRST = 1) is done
- After 1 has been read, writing of 0 is complete
- 1 PCLKB cycle passes after 1 has been written to SSICR.REN.
Note 3. After communication is enabled (by changing the value of SSICR.REN bit from 0 to 1), the reception error flags
(RUIRQ and ROIRQ in the SSISR register) are cleared. If, however, the SSISR register is read continuously, the
cleared status of the reception error flags might be unable to be read.
[Setting condition]
At completion of receiving new data while SSIFRDR is full.
[Setting timing]
3 PCLKB cycles after reception is complete.
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39. Serial Sound Interface Enhanced (SSIE)
: Unread receive data
: Receive data that has been read
Break point of a frame
SSIBCK
SSILRCK/
SSIFS
SSIRXD0/
SSIDATA0
D10
...
D11
D10
D07
D06
...
...
D11
D10
D07
D06
D05
D04
Receive shift
register
Retained internal
register
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Period to set ROIRQ
Three cycles
Three cycles
Read
Read
Reception
possible
PCLKB
SSIFRDR.0
SSIFRDR.1
SSIFRDR.2
.
.
.
SSIFRDR.29
SSIFRDR.30
SSIFRDR.31
ROIRQ
Figure 39.16
ROIRQ setting timing
RUIRQ bit (Receive Underflow Error Status Flag)
The RUIRQ is a status flag that indicates a receive underflow error. This flag is set by automatic determination but it
must be cleared by register access. This flag indicates that SSIFRDR is read while it is empty. Data read from SSIFRDR
where a receive underflow error is generated is invalid. See section 39.8.6, Error Handling for the error recovery
procedure. This flag is not cleared by a Receive FIFO Data Register Reset (SSIFCR.RFRST). Note, however, that this
flag is not set even if the SSIFRDR register is read while the Receive FIFO Data Register is reset (by setting
SSIFCR.RFRST to 1).
[Priority order for setting and clearing]
Setting is prioritized.*1
[Clearing condition]
When either of the following operations is done:
1. Writing 0 to this bit after reading 1 from this bit.*2
2. Enabling communication (changing SSICR.REN from 0 to 1).
[Clearing timing]
Clearing timing corresponding to the specified clearing condition:
1. When 0 is written to this bit after reading 1 from this bit (same as the timing in Figure 39.19).
2. 1 PCLKB cycle after writing 1 to SSICR.REN.*3
Note 1. This bit is cleared by a software reset (SSIFCR.SSIRST = 1). Software reset has priority over all the specified
clearing conditions.
Note 2. After reading 1 from this bit, this bit is cleared when one of the following three conditions is met:
- A software reset (SSIFCR.SSIRST = 1) is done
- After 1 has been read, writing of 0 is complete
- 1 PCLKB cycle passes after 1 has been written to SSICR.REN.
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39. Serial Sound Interface Enhanced (SSIE)
Note 3. After communication is enabled (by changing the value of SSICR.REN bit from 0 to 1), the reception error flags
(RUIRQ and ROIRQ in the SSISR register) are cleared. If, however, the SSISR register is read continuously, the
cleared status of the reception error flags might be unable to be read.
[Setting condition]
Reading from SSIFRDR while it is empty.
[Setting timing]
At completion of reading from SSIFRDR. See Figure 39.17.
: Unread receive data
: Receive data that has been read
: Initial data
frame boundary
SSIBCK
SSILRCK/
SSIFS
SSIRXD0/
SSIDATA0
D00
D17
D16
D15
D14
D13
D12
D11
D10
D07
D06
D05
D04
D03
Receive shift register
Retained internal register
0
[7:0]
[7:0]
Three cycles
Three cycles
Period to set RUIRQ
1st
read
2nd
read
3rd
read
PCLKB
SSIFRDR.0
0
SSIFRDR.1
[7:0]
0
SSIFRDR.2
.
.
.
[7:0]
0
0
0
SSIFRDR.29
0
SSIFRDR.30
0
SSIFRDR.31
0
RUIRQ
Figure 39.17
RUIRQ setting timing
TOIRQ bit (Transmit Overflow Error Status Flag)
The TOIRQ is a status flag that indicates a transmit overflow error. This flag is set by automatic determination but it must
be cleared by register access. This flag indicates that an attempt has been made to write data to the SSIFTDR register
when the register is full of data. The data writing that causes a transmit overflow is ignored. For the procedure to recover
from the overflow error, see section 39.8.6, Error Handling. This flag is not cleared by a Transmit FIFO Data Register
Reset (SSIFCR.TFRST).
[Priority order for setting and clearing]
Setting is prioritized.*1
[Clearing condition]
When either of the following operations is done:
(1) Writing 0 to this bit after reading 1 from this bit.*2
(2) Enabling communication (changing SSICR.TEN from 0 to 1).
[Clearing timing]
Clearing timing corresponding to the specified clearing condition:
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39. Serial Sound Interface Enhanced (SSIE)
(1) When 0 is written to this bit after reading 1 from this bit (same as the timing in Figure 39.19).
(2) 1 PCLKB cycle after writing 1 to SSICR.TEN.*3
Note 1. This bit is cleared by a software reset (SSIFCR.SSIRST = 1). Software reset has priority over all the specified
clearing conditions.
Note 2. After reading 1 from this bit, this bit is cleared when one of the following three conditions is met:
- A software reset (SSIFCR.SSIRST = 1) is done
- After 1 has been read, writing of 0 is complete
- 1 PCLKB cycle passes after 1 has been written to SSICR.TEN.
Note 3. After communication is enabled (by changing the value of SSICR.TEN bit from 0 to 1), the transmission error
flags (TOIRQ and TUIRQ in the SSISR register) are cleared. If, however, the SSISR register is read continuously,
the cleared status of the transmission error flags might be unable to be read.
[Setting condition]
An attempt was made to write data to the SSIFTDR register when the register is full of data.
[Setting timing]
At completion of writing to SSIFTDR. For details, see Figure 39.18.
: Data transferred to shift register
: Data not transferred to shift register
: Data not written
1st
write
2nd
write
3rd
write
Period to set TOIRQ
4th
write
5th
write
6th
write
7th
write
8th
write
9th
write
Three
cycles
PCLKB
SSIFTDR.0
SSIFTDR.1
SSIFTDR.2
SSIFTDR.3
SSIFTDR.4
SSIFTDR.5
SSIFTDR.6
SSIFTDR.7
SSIFTDR.8
(Omission)
SSIFTDR.26
SSIFTDR.27
SSIFTDR.28
SSIFTDR.29
SSIFTDR.30
SSIFTDR.31
TOIRQ
SSIBCK
SSILRCK/
SSIFS
Transmit shift
register
SSITXD0/
SSIDATA0
Break point of one frame
Figure 39.18
TOIRQ setting timing
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39. Serial Sound Interface Enhanced (SSIE)
TUIRQ bit (Transmit Underflow Error Status flag)
The TUIRQ is a status flag that indicates a transmit underflow error. This flag is set by automatic determination but it
must be cleared by register access. This flag indicates that writing the serial data required for a frame to SSIFTDR did
not catch up with transmission of the frame. Even if this flag is cleared after it has been set, the SSITXD0/SSIDATA0
output remains to be 0. To output the data written to the Transmit FIFO Data Register (SSIFTDR) to the
SSITXD0/SSIDATA0 pin, follow the communication stop procedure in Figure 39.56 and error-handling procedure in
Figure 39.57. For the procedure to recover from an error, see section 39.8.6, Error Handling. This flag is not cleared by a
Reset Of Transmit FIFO Data Register (by the SSIFCR.TFRST signal).
[Priority order for setting and clearing]
Setting is prioritized.*1
[Clearing condition]
When either of the following operations is done:
1. Writing 0 to this bit after reading 1 from this bit.*2
2. Enabling communication (changing SSICR.TEN from 0 to 1).
[Clearing timing]
Clearing timing corresponding to the specified clearing condition:
1. When 0 is written to this bit after reading 1 from this bit.
2. 1 PCLKB cycle after writing 1 to SSICR.TEN.*3
PCLKB
TUIRQ
Read 1
Write 0
PCLKB
SSICR.TEN
TUIRQ
Figure 39.19
TUIRQ clearing timing
Note 1. This bit is cleared by a software reset (SSIFCR.SSIRST = 1). Software reset has priority over all the specified
clearing conditions.
Note 2. After reading 1 from this bit, this bit is cleared when one of the following three conditions is met:
- A software reset (SSIFCR.SSIRST = 1) is done
- After 1 has been read, writing of 0 is complete
- 1 PCLKB cycle passes after 1 has been written to SSICR.TEN.
Note 3. After communication is enabled (by changing the value of SSICR.TEN bit from 0 to 1), the transmission error
flags (TOIRQ and TUIRQ in the SSISR register) are cleared. If, however, the SSISR register is read continuously,
the cleared status of the transmission error flags might be unable to be read.
[Setting condition]
When the communication continues over a frame boundary, the transmit data required for the next frame has not been
written to SSIFTDR. For details, see Figure 39.20 and Figure 39.21.
[Setting timing]
3 PCLKB cycles after the frame boundary. For details, see Figure 39.20.
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39. Serial Sound Interface Enhanced (SSIE)
SSICR.DEL = 0 (with delay)
frame boundary
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIDATA0
Serial data
Writing should be completed
before three cycles of SSIBCK. Three cycles
PCLKB
SSISR.IIRQ
SSICR.TEN
SSIFSR.TDC
Data not enough
for one frame
Data enough for one frame
TUIRQ
SSICR.DEL = 1 (without delay)
frame boundary
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIDATA0
Serial data
Writing should be completed
Three cycles
before three cycles of SSIBCK.
PCLKB
SSISR.IIRQ
SSICR.TEN
SSIFSR.TDC
Data not enough
for one frame
Data enough for one frame
TUIRQ
Figure 39.20
TUIRQ setting timing (when communication continues)
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39. Serial Sound Interface Enhanced (SSIE)
When SSICR.DEL = 0 (with delay)
frame boundary
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIDATA0
Serial data
Writing should be completed
before 3 cycles of SSIBCK
3 cycles
PCLKB
SSISR.IIRQ
2 cycles
SSICR.TEN
SSIFSR.TDC
Data not enough for one frame
TUIRQ
When SSICR.DEL = 1 (without delay) frame boundary
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIDATA0
Serial data
Writing should be completed
before 3 cycles of SSIBCK.
3 cycles
PCLKB
SSISR.IIRQ
SSICR.TEN
2 cycles
SSIFSR.TDC
Data not enough for one frame
TUIRQ
Figure 39.21
TUIRQ setting timing (when communication stops)
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39.4.3
39. Serial Sound Interface Enhanced (SSIE)
FIFO Control Register (SSIFCR)
Address(es): SSIE0.SSIFCR 4004 E010h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
AUCKE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSIRS
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
BSW
—
—
—
—
—
—
—
TIE
RIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
TFRST RFRST
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RFRST
Receive FIFO Data Register
Reset *1
0: Clears a receive data FIFO reset condition
1: Sets a receive data FIFO reset condition.
R/W
b1
TFRST
Transmit FIFO Data Register
Reset*1
0: Clears a transmit data FIFO reset condition
1: Sets a transmit data FIFO reset condition.
R/W
b2
RIE
Receive Data Full Interrupt
Output Enable
0: Disables receive data full interrupts
1: Enables receive data full interrupts.
R/W
b3
TIE
Transmit Data Empty Interrupt
Output Enable
0: Disables transmit data empty interrupts
1: Enables transmit data empty interrupts.
R/W
b10 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b11
BSW
Byte Swap Enable*1
0: Disables byte swap
1: Enables byte swap.
R/W
b15 to b12
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
SSIRST
Software Reset
0: Clears a software reset condition
1: Sets a software reset condition.
R/W
b30 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
AUCKE
AUDIO_MCK Enable in Mastermode Communication *1
0: Disables supply of AUDIO_MCK
1: Enables supply of AUDIO_MCK.
R/W
Note 1.
Writing to these bits while SSIE is in a communication state (SSISR.IIRQ = 0) is prohibited. If the value of these bits is changed
by rewriting, subsequent operation is unpredictable.
This register sets a software reset, byte swap, and enable/disable of interrupt requests.
RFRST bit (Receive FIFO Data Register Reset)
The RFRST bit sets a software reset of the Receive FIFO Data Register (SSIFRDR). Writing 1 to this bit initializes the
internal state related to SSIFRDR. The register bits subject to the software reset triggered by this bit are indicated by
shading in Table 39.5. Because this bit is not automatically cleared after it has been set, write 0 to this bit to release the
register bits from the software reset. After writing 0 to this bit, be sure to check that this bit is 0 before starting the next
procedural step.
This bit is subject to the software reset by the SSIRST bit. Because the software reset by the SSIRST bit has priority over
the reset by this bit, setting this bit is ignored when the SSIRST bit is set.
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Table 39.5
39. Serial Sound Interface Enhanced (SSIE)
Bits subject to software reset by the RFRST bit
+0
Symbol
SSICR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+0
—
CKS
TUI
EN
TOI
EN
RUI
EN
ROI
EN
IIEN
—
FRM[1:0]
+2
—
MS
T
BCK
P
LRC
KP
SPD
P
SDT
A
PDT
A
DEL
—
—
TUI
RQ
TOI
RQ
RUI
RQ
ROI
RQ
IIRQ
—
—
—
—
Address
(BASE+)
00h
+1
DWL[2:0]
CKDV[3:0]
SWL[2:0]
MU
EN
—
TEN
RE
N
—
—
—
—
—
SSISR
04h
+0
+2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSIFCR
10h
+0
AUC
KE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSI
RST
+2
—
—
—
—
BS
W
—
—
—
—
—
—
—
TIE
RIE
TFR
ST
RFR
ST
+0
—
—
TDC[5:0]
—
—
—
—
—
—
—
TDE
+2
—
—
RDC[5:0]
—
—
—
—
—
—
—
RDF
—
—
SSIFSR
SSIFTDR
14h
18h
+0
FTDR[31:16]
+2
FTDR[15:0]
FRDR[31:16]
SSIFRDR
1ch
+0
SSIOFR
20h
+0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+2
—
—
—
—
—
—
BCK
AST
P
LRC
ON
T
—
—
—
—
—
—
+0
—
—
—
—
—
—
—
—
—
—
—
—
—
+2
—
—
—
—
—
—
+2
SSISCR
24h
FRDR[15:0]
TDES[4:0]
OMOD[1:0]
—
—
—
RDFS[4:0]
TFRST bit (Transmit FIFO Data Register Reset)
The TFRST bit sets a software reset of the Transmit FIFO Data Register (SSIFTDR). Writing 1 to this bit initializes the
internal state related to SSIFTDR. The register bits subject to the software reset triggered by this bit are indicated by
shading in Table 39.6. Because this bit is not automatically cleared after it has been set, write 0 to this bit to release the
register bits from the software reset. After writing 0 to this bit, be sure to check that this bit is 0 before starting the next
procedural step.
This bit is subject to a software reset by the SSIRST bit. Because the software reset by the SSIRST bit has priority over
the reset by this bit, setting this bit is ignored when the SSIRST bit is set.
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Table 39.6
39. Serial Sound Interface Enhanced (SSIE)
Bits subject to software reset by the TFRST bit
+0
Symbol
SSICR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+0
—
CKS
TUI
EN
TOI
EN
RUI
EN
ROI
EN
IIEN
—
FRM[1:0]
+2
—
MS
T
BCK
P
LRC
KP
SPD
P
SDT
A
PDT
A
DEL
—
—
TUI
RQ
TOI
RQ
RUI
RQ
ROI
RQ
IIRQ
—
—
—
—
Address
(BASE+)
00h
+1
DWL[2:0]
CKDV[3:0]
SWL[2:0]
MU
EN
—
TEN
RE
N
—
—
—
—
—
SSISR
04h
+0
+2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSIFCR
10h
+0
AUC
KE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSI
RST
+2
—
—
—
—
BS
W
—
—
—
—
—
—
—
TIE
RIE
TFR
ST
RFR
ST
SSIFSR
SSIFTDR
14h
18h
+0
—
—
TDC[5:0]
—
—
—
—
—
—
—
TDE
+2
—
—
RDC[5:0]
—
—
—
—
—
—
—
RDF
—
—
+0
FTDR[31:16]
+2
FTDR[15:0]
FRDR[31:16]
SSIFRDR
1ch
+0
SSIOFR
20h
+0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+2
—
—
—
—
—
—
BCK
AST
P
LRC
ON
T
—
—
—
—
—
—
+0
—
—
—
—
—
—
—
—
—
—
—
—
—
+2
—
—
—
—
—
—
+2
SSISCR
24h
FRDR[15:0]
TDES[4:0]
OMOD[1:0]
—
—
—
RDFS[4:0]
RIE bit (Receive Data Full Interrupt Output Enable)
The RIE bit enables/disables output of receive data full interrupts. Use a receive data full interrupt as an interrupt to
trigger data reading from the receive FIFO data register. Write 1 to this bit after specifying the setting condition for
receive data full interrupt (by using the SSISCR.RDFS[4:0] bit). Figure 39.22 shows the timing of generating the receive
data full interrupt.
PCLKB
DMAC busy state
SSIFCR.RIE
SSIFSR.RDF
Holding interrupt by
DMAC busy state
Receive data full
interrupt
Read access to SSIFRDR
Figure 39.22
Read access to SSIFRDR
Read access to SSIFRDR
Timing of receive data full interrupt
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39. Serial Sound Interface Enhanced (SSIE)
TIE bit (Transmit Data Empty Interrupt Output Enable)
The TIE bit enables/disables the output of transmit data empty interrupts. Use a transmit data empty interrupt as an
interrupt to trigger data writing to the transmit FIFO data register. Write 1 to this bit after specifying the setting condition
for Transmit Data Empty Interrupt (by using the SSISCR.TDES[4:0] bit). Figure 39.23 shows the timing of generating
the Transmit Data Empty Interrupt.
PCLKB
DMAC busy state
SSIFCR.TIE
SSIFSR.TDE
Holding interrupt by
DMAC busy state
Transmit data empty
interrupt
Write access to SSIFTDR
Figure 39.23
Write access to SSIFTDR
Write access to SSIFTDR
Timing of transmit data empty interrupt
BSW bit (Byte Swap Enable)
The BSW bit enables/disables the byte swap of register access for the Transmit FIFO Data Register (SSIFTDR) and the
Receive FIFO Data Register (SSIFRDR). This bit is valid only with 16-bit access or 32-bit access to SSIFTDR and
SSIFRDR. For details, see Figure 39.24.
Word write access (BSW = 0)
Byte0
Byte1
Byte2
Word write access (BSW = 1)
Byte3
Byte0
Byte1
Byte2
Byte3
Write data
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
SSIFTDR
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
Halfword write access (BSW = 0)
Byte0
Write data
31
Halfword write access (BSW = 1)
Byte1
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
SSIFTDR
15
Byte0
31
... 8 7 ... 0
15
Word read access (BSW = 0)
Byte0
Byte1
Byte1
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
Byte2
... 8 7 ... 0
Word read access (BSW = 1)
Byte3
Byte0
Byte1
Byte2
Byte3
SSIFRDR
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
Read data
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
Halfword read access (BSW = 0)
SSIFRDR
Byte0
31
Byte1
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
Read data
Figure 39.24
Halfword read access (BSW = 1)
15
... 8 7 ... 0
Byte0
31
Byte1
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
15
... 8 7 ... 0
Operation example of byte swap
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39. Serial Sound Interface Enhanced (SSIE)
SSIRST bit (Software Reset)
The SSIRST bit sets a software reset of SSIE. Writing 1 to this bit initializes the internal state of SSIE. The register bits
subject to the software reset triggered by this bit are indicated by the shading in Table 39.7. Because this bit is not
automatically cleared after it has been set, write 0 to this bit to release the register bits from the software reset. After
writing 0 to this bit, be sure to check that this bit is 0 before starting the next procedural step.
To stop communication of SSIE immediately, after turning off the peripheral functions, write 1 to this bit. Initialization
by a software reset is performed without any relation to the bit clock.
Table 39.7
Bits subject to software reset by the SSIRST bit
+0
Symbol
SSICR
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+0
—
CKS
TUI
EN
TOI
EN
RUI
EN
ROI
EN
IIEN
—
FRM[1:0]
+2
—
MS
T
BCK
P
LRC
KP
SPD
P
SDT
A
PDT
A
DEL
—
—
TUI
RQ
TOI
RQ
RUI
RQ
ROI
RQ
IIRQ
—
—
—
—
Address
(BASE+)
00h
+1
31
DWL[2:0]
SWL[2:0]
MU
EN
—
TEN
RE
N
—
—
—
—
—
CKDV[3:0]
SSISR
04h
+0
+2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSIFCR
10h
+0
AUC
KE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSI
RST
+2
—
—
—
—
BS
W
—
—
—
—
—
—
—
TIE
RIE
TFR
ST
RFR
ST
+0
—
—
TDC[5:0]
—
—
—
—
—
—
—
TDE
+2
—
—
RDC[5:0]
—
—
—
—
—
—
—
RDF
—
—
SSIFSR
14h
SSIFTDR
18h
SSIFRDR
SSIOFR
SSISCR
1ch
20h
24h
+0
FTDR[31:16]
+2
FTDR[15:0]
+0
FRDR[31:16]
+2
FRDR[15:0]
+0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+2
—
—
—
—
—
—
BCK
AST
P
LRC
ON
T
—
—
—
—
—
—
+0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+2
—
—
—
—
—
—
TDES[4:0]
OMOD[1:0]
—
—
RDFS[4:0]
AUCKE bit (AUDIO_MCK Enable in Master-mode Communication)
The AUCKE bit enables/disables the supply to AUDIO_MCK while in master-mode communication (MST = 1).
Changing the value of this bit must be performed only after specifying the settings related to AUDIO_MCK (by using the
CKS, MST, BCKP, and CKDV bits in the SSICR register).
PCLKB
AUCKE
3 cycles of
AUDIO_MCK
3 cycles of
AUDIO_MCK
AUDIO_MCK
(before controlled by AUCKE)
AUDIO_MCK
Figure 39.25
Stop/resume of AUDIO_MCK
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Note:
39. Serial Sound Interface Enhanced (SSIE)
In slave-mode communication (SSICR.MST = 0), SSIE needs supply of SSIBCK. To stop BCK on the master
side, make sure that SSIE is in the idle state (SSISR.IIRQ = 1). If BCK is stopped before SSIE becomes idle, take
the procedure to start communication in Figure 39.52 or wait for an idle state by taking the procedure to resume
communication in Figure 39.58.
In master-mode communication (SSICR.MST = 1), SSIE operates with the audio clock (AUDIO_MCK). To stop
SSIE completely, make sure that SSIE is in the idle state (SSISR.IIRQ = 1) and then, write 0 to SSIFCR.ADCKE.
If 0 is written to SSIFCR.ADCKE before SSIE becomes idle, take the procedure to start communication in Figure
39.52.
Figure 39.26 and Figure 39.27 show the timings of signal operation in the period from setting this bit to 1 to the output to
the SSIBCK pin.
PCLKB
SSIFCR.AUCKE
(Internal register)
GTIOC1A or
AUDIO_CLK
Synchronization
signal of AUCKE
Synchronization
It becomes effective
when Low.
AUDIO_MCK
BCK
BCK output enable
(Internal register)
BCKP = 0
(Falling operation of master BCK)
BCK output enable
(Internal register)
BCKP = 1
(Rising operation of master BCK)
SSIBCK
output
Figure 39.26
Timing diagram for the operation from system reset to start of master-mode communication
PCLKB
SSIFCR.AUCKE
(Internal register)
GTIOC1A or
AUDIO_CLK
Synchronization
signal of AUCKE
Synchronization
It becomes
effective when Low.
AUDIO_MCK
Master BCK
(dividing 1)
Master BCK
(dividing 2: ex. 1)
Master BCK
(dividing 2: ex. 1)
BCK output enable
(Internal register)
SSIBCK output
Figure 39.27
Note:
When the clock of dividing
frequency is set, an internal
counter when AUDIO_MCK
is stopped maintains the
value. The restart wave form
is different because it
restarts from the stopping
counter value.
Because this signal is H of the previous communication state, H does not depend on BCKP.
This signal outputs the above-mentioned master BCK.
Timing diagram for the operation from stop of communication to start of master-mode
communication
If the supply of AUDIO_MCK stops, the value of the SSIBCK pin is held. Therefore, the SSIBCK signal might stop
at the H (high level) state.
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39.4.4
39. Serial Sound Interface Enhanced (SSIE)
FIFO Status Register (SSIFSR)
Address(es): SSIE0.SSIFSR 4004 E014h
b31
b30
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
—
—
0
0
Value after reset:
Value after reset:
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
TDE
0
0
0
0
0
0
0
0
1
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
RDF
0
0
0
0
0
0
0
0
TDC[5:0]
RDC[5:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RDF
Receive Data Full Flag
0: The size of received data in SSIFRDR is not more than the
value of SSISCR.RDFS[4:0]
1: The size of received data in SSIFRDR is not less than the
value of SSISCR.RDFS[4:0] plus one.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13 to b8
RDC[5:0]
Number of Receive FIFO Data
Indication Flag
Number of receive FIFO data indication flag
R
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
TDE
Transmit Data Empty Flag
0: The free space of SSIFTDR is not more than the value of
SSISCR.TDES[4:0]
1: The free space of SSIFTDR is not less than the value of
SSISCR.TDES[4:0] plus one.
R/W
b23 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b29 to b24
TDC[5:0]
Number of Transmit FIFO Data
Indication Flag
Number of transmit FIFO data indication flag
R
b31, b30
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SSIFSR register is configured with status flags that indicate the status of the transmit FIFO data register and the
receive FIFO data register.
RDF bit (Receive Data Full Flag)
The RDF bit indicates that the Receive FIFO Data Register (SSIFRDR) has unread received data not less than the
amount set with the SSISCR.RDFS[4:0] bit plus one. This flag is set by automatic determination, but it must be cleared
by register access.
[Priority order for setting and clearing]
Clearing is prioritized.
[Clearing condition]
Either of the following two:*1
1. Writing 0 to this bit after reading 1 from this bit (CPU operation).*2
2. Last access (DTC/DMAC operation) to read data from SSIFRDR by an interrupt routine using the DTC and
DMAC.
[Clearing timing]
Clearing timing corresponding to the specified clearing condition:
1. When 0 is written to this bit after reading 1 from this bit (same as the timing in Figure 39.19).
2. After the PCLKB cycle in which the last access instruction is issued to read data from SSIFRDR by an interrupt
routine using the DTC and DMAC.
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39. Serial Sound Interface Enhanced (SSIE)
Note 1. These bits are cleared by a software reset (SSIFCR.SSIRST = 1) and Receive FIFO Data Register Reset
(SSIFCR.RFRST = 1). Reset conditions available for these bits are the software reset and Receive FIFO Data
Register Reset in addition to the specified clearing conditions.
Note 2. After reading 1 from this bit, this bit is cleared when one of the following four conditions is met:
- A software reset is done (SSIFCR.SSIRST = 1)
- A receive FIFO data register reset is done (SSIFCR.RFRST = 1)
- After 1 has been read, writing of 0 is complete
- Last access is performed to read data from SSIFRDR by an interrupt routine using the DTC and DMAC.
[Setting condition]
SSIFRDR has data that is not less than the amount set with the SSISCR.RDFS[4:0] bit plus one.
[Setting timing]
At completion of transfer from the shift register that results in SSIFRDR having data that is not less than the amount set
with the SSISCR.RDFS[4:0] bit plus one.
1 read
0 write
FIFO
read
FIFO
read
FIFO
read
FIFO
read
DTC/DMAC
last access
Transfer shift
register
PCLKB
15 (It sets one with sixteen data stored)
SSISCR.RDFS[4:0]
Write point of
receive FIFO
20
Read point of
receive FIFO
Receive FIFO
data full number
21
0
1
2
3
4
20
19
18
17
16
5
15
16
RDF
Figure 39.28
Timing diagram for setting and clearing RDF
RDC[5:0] bits (Number of Receive FIFO Data Indication Flag)
The RDC[5:0] bits indicate the number of valid data that are stored in the Receive FIFO Data Register (SSIFRDR). With
this flag as 0h, there is no received data. With 20h, the register is filled with received data and there is no free space.
TDE bit (Transmit Data Empty Flag)
The TDE bit indicates that the Transmit FIFO Data Register (SSIFTDR) has free space not less than the amount set with
the SSIFCR.TTRG bit plus one. This flag is set by automatic determination but it must be cleared by register access.
[Priority order for setting and clearing]
Clearing is prioritized.*1
[Clearing condition]
Either of the following two:
1. Writing 0 to this bit after reading 1 from this bit (CPU operation).*2
2. Last access (DTC/DMAC operation) to write data to SSIFTDR by an interrupt routine using the DTC and DMAC.
[Clearing timing]
Clearing timing corresponding to the specified clearing condition:
(1) When 0 is written to this bit after reading 1 from this bit (same as the timing in Figure 39.19).
(2) Last access (DTC/DMAC operation) to write data to SSIFTDR by an interrupt routine using the DTC and DMAC.
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39. Serial Sound Interface Enhanced (SSIE)
Note 1. This bit is cleared by a software reset (SSIFCR.SSIRST = 1) and transmit FIFO data register reset
(SSIFCR.TFRST = 1). The software reset and transmit FIFO data register reset have priority over all the
specified clearing conditions.
Note 2. After reading 1 from this bit, this bit is cleared when one of the following four conditions is met:
- A software reset is done (SSIFCR.SSIRST = 1)
- A transmit FIFO data register reset is done (SSIFCR.TFRST = 1)
- After 1 has been read, writing of 0 is complete
- Last access is performed to write data to SSIFTDR by an interrupt routine using the DTC and DMAC.
[Setting condition]
SSIFTDR has free space that is not less than the amount set with the SSIFCR.TTRG bit plus one.
[Setting timing]
While operating on PCLKB, SSIFTDR is found to have free space that is not less than “size set in the
SSISCR.TDES[4:0] bits + 1.”
one read
zero write
FIFO
write
FIFO
write
FIFO
write
FIFO
write
DTC/DMAC Transfer
last access shift register
PCLKB
15 (It sets one with sixteen empty states.)
SSISCR.TDES[4:0]
Write point of
transmit FIFO
12
13
Read point of
transmit FIFO
14
15
16
17
0
Transmit FIFO data
empty number
20
19
1
18
17
16
15
16
TDE
Figure 39.29
Timing diagram for setting and clearing TDE
TDC[5:0] bits (Number of Transmit FIFO Data Indication Flag)
The TDC[5:0] bits indicate the number of valid data that are stored in the Transmit FIFO Data Register (SSIFTDR). With
this flag as 0h, there is no data to be transmitted. With 20h, there is no space to write data.
39.4.5
Transmit FIFO Data Register (SSIFTDR)
Address(es): SSIE0.SSIFTDR 4004 E018h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
SSIFTDR [31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
SSIFTDR [15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
SSIFTDR[31:0]
Transmit FIFO Data
Transmit FIFO data
W
The SSIFTDR register stores data to be serially transmitted. 0 is returned when this register is read.
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39. Serial Sound Interface Enhanced (SSIE)
When you use this register for transmission, specify data writing to this register as the DTC/DMAC operation that is
triggered by a transmit data empty interrupt. Determine the access size to this register according to the data word length
to be communicated in Table 39.8.
Table 39.8
Register access restriction to FIFOs
Access Size
SSICR.DWL[2:0]
Data Word Length
Byte
Halfword
Word
000b
8
√
—
—
001b
16
—
√
—
010b
18
—
—
√
011b
20
—
—
√
100b
22
—
—
√
101b
24
—
—
√
110b
32
—
—
√
111b
Setting prohibited
—
—
—
Figure 39.30 shows register access to the transmit FIFO data register.
Word access
Byte0
SSIFTDR
31
Byte1
Byte2
Byte3
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
Halfword access
Byte0
SSIFTDR
31
Byte1
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
Byte access
Byte0
SSIFTDR
Figure 39.30
31
. . . 24 23 . . . 16 15 . . . 8 7 . . . 0
Example of register access to the transmit FIFO data register
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39. Serial Sound Interface Enhanced (SSIE)
Figure 39.31 shows the configurations and operation examples of the Transmit FIFO Data Register and Transmit Shift
Register. The configurations are for storing data to FIFO and are not related with communication.
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
SSIFTDR.0
SSIFTDR.1
SSIFTDR.2
SSIFTDR.3
SSIFTDR.4
SSIFTDR.5
SSIFTDR.6
・
・
・
SSIFTDR.26
SSIFTDR.27
SSIFTDR.28
SSIFTDR.29
SSIFTDR.30
SSIFTDR.31
Write access: +1 →
Completion of transfer to shift register +1→
[31:0]
Transmit shift
register
Transmit bit 31
Valid data
Write pointer(WP)
Invalid data
Read pointer(RP)
write write write write write write write write write write
write write write write
PCLKB
SSIFTDR.0
1
0
0
SSIFTDR.1
33
2
0
SSIFTDR.2
3
0
SSIFTDR.3
34
35
4
0
5
SSIFTDR.5
0
6
SSIFTDR.6
0
7
SSIFTDR.7
0
8
SSIFTDR.8
0
9
(omission)
0
SSIFTDR.4
SSIFTDR.26
0
27
SSIFTDR.27
0
28
SSIFTDR.28
0
29
SSIFTDR.29
0
30
0
SSIFTDR.30
0
SSIFTDR.31
WP
31
0
1
3
...
33
31
0
RP
WP - RP
32
2
0
1
2
32
1 2 3
3
...
14
15
14 13
...
...
33
30 31 32
2
1
34
35
33
0
36
34
1
2
35
1
Completion
of transfer to
shift register
Figure 39.31
Configuration of the transmit FIFO data register and transmit shift register, and FIFO operation
example
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39.4.6
39. Serial Sound Interface Enhanced (SSIE)
Receive FIFO Data Register (SSIFRDR)
Address(es): SSIE0.SSIFRDR 4004 E01Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
SSIFRDR [31:16]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
SSIFRDR [15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
SSIFRDR[31:0]
Receive FIFO Data
Receive FIFO data.
R
When you use the SSIFRDR register for reception, specify data reading from this register as the DTC/DMAC operation
that is triggered by a receive data full interrupt. Determine the access size to this register according to the data word
length to be communicated in Table 39.8.
Register access to the Receive FIFO Data Register is same as for the Transmit FIFO Data Register.
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39. Serial Sound Interface Enhanced (SSIE)
Figure 39.32 shows the configurations and operation examples of the receive FIFO data register and receive shift
register.
Receive shift
register
Divider
Receive at bit 0
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
SSIFRDR.0
SSIFRDR.1
SSIFRDR.2
SSIFRDR.3
SSIFRDR.4
SSIFRDR.5
SSIFRDR.6
・・・
SSIFRDR.26
SSIFRDR.27
SSIFRDR.28
SSIFRDR.29
SSIFRDR.30
SSIFRDR.31
Write pointer(WP)
Read pointer(RP)
read read
Valid data
Invalid data
← Completion of transfer from shift register: +1
← Read access: +1
read read read read read read read read read read read read read
PCLKB
SSIFRDR.0
0
1
0
SSIFRDR.1
33
2
34
0
SSIFRDR.2
3
SSIFRDR.3
0
4
SSIFRDR.4
0
5
SSIFRDR.5
0
6
SSIFRDR.6
0
7
SSIFRDR.7
0
8
SSIFRDR.8
0
9
(omission)
0
SSIFRDR.26
0
27
SSIFRDR.27
0
28
SSIFRDR.28
0
29
0
SSIFRDR.29
30
0
SSIFRDR.30
0
SSIFRDR.31
WP
0
1 2
32
...
0
RP
WP - RP
31
0
1 2
30 31
1
...
32
34
2
3
30 31 30
29
...
...
30
31
32
33
34
2
1
0
1
0
Completion of
transfer from
shift register
Figure 39.32
Configuration of the transmit FIFO data register and transmit shift register, and FIFO operation
example
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39.4.7
39. Serial Sound Interface Enhanced (SSIE)
Audio Format Register (SSIOFR)
Address(es): SSIE0.SSIOFR 4004 E020h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
OMOD[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
BCKAS LRCON
TP
T
0
0
0
Bit
Symbol
Bit name
b1, b0
OMOD[1:0]
Audio Format Select*3, *4
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
LRCONT
Whether to Enable LRCK/FS
Continuation*1, *2
0: Disables LRCK/FS continuation
1: Enables LRCK/FS continuation.
R/W
b9
BCKASTP
Whether to Enable Stopping
BCK Output When SSIE is in
Idle Status*1, *2
0: Always outputs BCK to the SSIBCK pin
1: Automatically controls output of BCK to the SSIBCK pin.
R/W
b31 to b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Description
0
R/W
00: I2S format
01: TDM format
10: Monaural format
11: Setting prohibited.
R/W
This bit is valid only in master-mode communication (SSICR.MST = 1). The setting is invalid in slave-mode communication
(SSICR.MST = 0).
The BCKASTP and LRCONT bits must not be set to 1 together.
While SSIE is communicating (SSISR.IIRQ = 0), writing to these bits is prohibited. If the value of these bits is changed by
writing, subsequent operation is unpredictable.
If the communication format of the other-party device is compatible with a communication format of SSIE, specify and use the
communication format that enables communication with the other-party device.
The SSIOFR register is used to set an audio format (which involves the settings of communication format, LR
clock/frame synchronization continuation mode, and BCK output stop).
OMOD[1:0] bits (Audio Format Select)
The OMOD[1:0] bits set an audio format. Writing to these bits must be performed when the LR clock supply to the
SSILRCK/SSIFS pin is stopped. For details about the output of LR clock, see the detailed description of the LRCONT
bit in reference 39.4.7.
LRCONT bit (Whether to Enable LRCK/FS Continuation)
The LRCONT bit enables or disables the output from the SSILRCK/SSIFS pin when the communication mode is mastermode communication (SSICR.MST = 1) and SSIE is in the idle state (SSISR.IIRQ = 1).
Even in the idle state, a signal can output from the SSILRCK/SSIFS pin when this bit is set to 1 (to enable LR
clock/frame synchronization continuation) in master mode (SSICR.MST = 1).
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39. Serial Sound Interface Enhanced (SSIE)
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b), LRCK continuation: Disabled (LRCONT = 0b)
Other control bits of communication format are at their initial values.
PCLKB
SSICR.TEN/
SSICR.REN
2 cycles of SSIBCK
2 cycles of SSIBCK
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIRXD0/
SSIDATA0
R channel
D07 D06 D01 D00 D17 D16 D11 D10
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b), LRCK continuation: Enabled (LRCONT = 1b)
Other control bits of communication format are at their initial values.
PCLKB
SSISR.TEN/
SSISR.REN
2 cycles of
SSIBCK
Communication starts at the
break point of a frame
2 cycles of SSIBCK
Communication halts at the
frame boundary
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.33
R channel
D07 D06 D01 D00 D17 D16 D11 D10
Example of LR clock/frame synchronization continuation operation
BCKASTP bit (Whether to Enable Stopping BCK Output When SSIE is in Idle Status)
The BCKASTP bit turns on or off the function to output BCK to the SSIBCK pin according to the communication shown
in Figure 39.34 and Figure 39.35 in master-mode communication (SSICR.MST = 1).
Changing the value of this bit must be performed only after setting the communication format to be used.
This bit must be used in the following way:
Write 0 to the BCKASTP bit, and then start communication. During the communication, write 1 to the BCKASTP bit.
By this operation, the bit clock output to the SSIBCK pin stops automatically when the communication stops. To resume
the communication, set SSIE to the idle state (SSICR.IIRQ = 1), enable the supply of AUDIO_MCK (SSIFCR.AUCKE
= 1), and then write 0 to the BCKASTP bit.
When the communication mode is master-mode communication (SSICR.MST = 1) and SSIE is in the idle state
(SSICR.IIRQ = 1):
Table 39.9
BCKASTP bit status and SSIBCK pin output
BCKASTP Bit
SSIBCK Pin Output Status
0
Output
1
Stopped
Note:
The BCKASTP bit cannot be used when the other-party device (which is a slave) requires the clock output from the SSIBCK pin
before and during communication. In such a case, use the BCKASTP bit to stop the clock only after communication. For the
timing of enabling the clock stop function, see Figure 39.34.
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39. Serial Sound Interface Enhanced (SSIE)
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
BCK Output Stop Enable: Refer to timing chart, Communication mode: Master-mode communication (SSICR.MST = 1)
BCK Polarity: Falling edge (SSICR.BCKP = 0), Other control bits of communication format are at their initial values.
PCLKB
SSICR.TEN/
SSICR.REN
SSISR.IIRQ
BCKASTP
3 cycles of BCK
3 cycles of BCK
BCK
SSIBCK
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
BCK Output Stop Enable: Refer to timing chart, Communication mode: Master-mode communication (SSICR.MST = 1)
BCK Polarity: Rising edge (SSICR.BCKP = 1), Other control bits of communication format are at their initial values.
PCLKB
SSICR.TEN/
SSICR.REN
SSISR.IIRQ
BCKASTP
3 cycles of BCK
3 cycles of BCK
BCK
SSIBCK
Figure 39.34
Example operation of the BCKASTP bit (idle state)
When the communication mode is master-mode communication (SSICR.MST = 1) and the BCK output stop function is
enabled (BCKASTP = 1):
Details of the BCK output to the SSIBCK pin are as follows:
Output start timing: BCK is output in appropriate timing so that a valid edge is generated when the LR clock/frame
synchronization signal shifts to a valid value.
Output stop timing: 1 to 1.5 clock cycles after a frame boundary.
For details about the timings, see the timing diagram in Figure 39.35.
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39. Serial Sound Interface Enhanced (SSIE)
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
BCK output stop enable: Auto control (BCKASTP = 1b), Communication mode: Master-mode communication (SSICR.MST = 1),
BCK polarity: Falling edge (SSICR.BCKP = 0), LRCK continuation: Disable (LRCONT = 0),
Delay between LR clock and SSITXD0/SSIRXD0/SSIDATA0: Exist (SSICR.DEL = 0)
Other control bits of communication format are at their initial values .
PCLKB
SSICR.TEN/
SSICR.REN
3 cycles of
SSIBCK
2 cycles of
PCLKB
3 cycles of
SSIBCK
SSISR.IIRQ
2 cycles of
PCLKB
2 cycles of
BCK
BCK
SSIBCK
1 cycle
of BCK
Clock output stops after 1 cycle of BCK
since the last data transferred
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIRXD0/
SSIDATA0
R channel
D07 D06 D01 D00 D17 D16 D11 D10
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
BCK output stop enable: Auto control (BCKASTP = 1b), Communication mode: Master-mode communication (SSICR.MST = 1),
BCK polarity: Rising edge (SSICR.BCKP = 1), LRCK continuation: Disable (LRCONT = 0),
Delay between LR clock and SSITXD0/SSIRXD0/SSIDATA0: Exist (SSICR.DEL = 0)
Other control bits of communication format are at their initial values .
PCLKB
SSICR.TEN/
SSICR.REN
3 cycles of
SSIBCK
3 cycles of
SSIBCK
2 cycles of
PCLKB
SSISR.IIRQ
2 cycles of
PCLKB
2 cycles of
BCK
BCK
Clock output stops after 1.5 cycles of
BCK since the last data transferred
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.35
R channel
D07 D06 D01 D00 D17 D16 D11 D10
Example operation of the BCKASTP bit (communication operation with BCKASTP = 1)
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39.4.8
39. Serial Sound Interface Enhanced (SSIE)
Status Control Register (SSISCR)
Address(es): SSIE0.SSISCR 4004 E024h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
TDES[4:0]
0
0
0
0
0
RDFS[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
RDFS[4:0]
RDF Setting Condition
Select*1
b4
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b12 to b8
TDES[4:0]
TDE Setting Condition
Select*1
b12
R/W
b31 to b13
—
Reserved
These bits are read as 0. The write value should be 0.
Note 1.
b0
0 0 0 0 0: SSIFRDR has one stage or more data size
0 0 0 0 1: SSIFRDR has two stages or more data size (snip)
1 1 1 1 0: SSIFRDR has thirty-one stages or more data size
1 1 1 1 1: SSIFRDR has thirty-two stages or more data size.
b8
0 0 0 0 0: SSIFTDR has one stage or more free space
0 0 0 0 1: SSIFTDR has two stages or more free space (snip)
1 1 1 1 0: SSIFTDR has thirty-one stages or more free space
1 1 1 1 1: SSIFTDR has thirty-two stages or more free space.
R/W
Writing to these bits while SSIE is in a communication state (SSISR.IIRQ = 0) is prohibited. If written, the operation performed
immediately after writing is not guaranteed.
RDFS[4:0] bits (RDF Setting Condition Select)
The RDFS[4:0] bits set the setting condition of the Receive Data Full Flag (RDF).
TDES[4:0] bits (TDE Setting Condition Select)
The TDES[4:0] bits set the setting condition of the Transmit Data Empty Flag (TDE).
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39.5
39. Serial Sound Interface Enhanced (SSIE)
Communication Formats
SSIE supports three communication formats. Table 39.10 shows supported communication formats.
Table 39.10
Supported communication formats
Communication Format
SSIOFR.OMOD[1:0]
I2S format
00
TDM format
01
Monaural format
10
The following describes the serial data structure shared by communication formats. A serial data structure is defined by
the system word length (set in SSICR.SWL[2:0]) and the data word length (set in SSICR.DWL[2:0]). If the data word
length is shorter than the system word length, padding bits are transferred in the serial data. For details, see Figure 39.36.
System word length: 16 bits (SSICR.SWL[2:0] = 001b),
Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Other control bits of communication format are at their initial values.
Dxy
x: System word number in one frame
y: Data word number in one system word
SSIBCK
SSILRCK/
SSIFS
L channel
SSITXD0/
SSIRXD0/
SSIDATA0
D07
R channel
D06 D01
D00
D17 D16
D11
D10
8 bits
Example of padding bit transfer (I2S format: system word length > data word length)
Figure 39.36
Table 39.11 lists the number of padding bits to be transferred with each combination of system word length
(SSICR.SWL[2:0]) and data word length (SSICR.DWL[2:0]). “-” indicates that the setting is prohibited.
Table 39.11
Number of padding bits
SSICR.DWL[2:0]
000b
001b
010b
011b
100b
101b
110b
111b
SSICR.SWL[2:0]
System Word
Length
8
16
18
20
22
24
32
Setting
prohibited
000b
8
0
—
—
—
—
—
—
—
001b
16
8
0
—
—
—
—
—
—
010b
24
16
8
6
4
2
0
—
—
011b
32
24
16
14
12
10
8
0
—
100b
48
40
32
30
28
26
24
16
—
101b
64
56
48
46
44
42
40
32
—
110b
128
120
112
110
108
106
104
96
—
111b
256
248
240
238
236
234
232
224
—
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39. Serial Sound Interface Enhanced (SSIE)
I2S Format
39.5.1
The I2S format is a communication format used for connection with I2S-compatible serial devices. With this format
setting (SSIOFR.OMOD[1:0] = 00b), one frame is configured with two system words, one for the channel L and the
other for channel R. The SSILRCK/SSIFS signals are at a low level for the channel L and at a high level for the channel
R. Set the polarity of the signals with the SSICR.LRCKP bit. Figure 39.37 shows the I2S format without padding. See
Figure 39.36 for the format with padding.
System word length: 8 bits (SSICR.SWL[2:0] = 000b),
Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Other control bits of communication format are at their initial values.
One frame
System word
System word
SSIBCK
SSILRCK/
SSIFS
Start
trigger
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.37
L channel
R channel
D07 D06 D01 D00 D17 D16 D11 D10
I2S format (without padding: system word length = data word length)
For the state of external pins when SSIE is in the idle state, see reference 39.7.1.
Note:
SSIE has the SSILRCK/SSIFS pin, which indicates the synchronization of communication. When SSIE is in slave
mode (SSICR.MST = 0), the communication format that SSIE uses must match that of the other-party device to
communicate. SSIE uses the signal input by the SSILRCK/SSIFS pin only as a trigger to start communication.
39.5.2
Monaural Format
The monaural format is a communication format used for connection with monaural-compatible serial devices. When the
monaural format is specified (SSIOFR.OMOD[1:0] = 10b) for use, one frame consists of one system word. Also, a rising
edge of the SSILRCK/SSIFS signal indicates a communication start trigger. Figure 39.38 and Figure 39.39 respectively
show the monaural formats without and with padding.
System word length: 8 bits (SSICR.SWL[2:0] = 000b),
Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Number of frame words: One word (SSICR.FRM[1:0] = 00b),
BCK polarity: Rising edge (BCKP = 1)
Other control bits of communication format are at their initial values.
One frame
One frame
System word
System word
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.38
Start
trigger
D07 D06 D01 D00 D07 D06 D01 D00 D07
Short frame in monaural format (without padding: system word length = data word length)
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39. Serial Sound Interface Enhanced (SSIE)
System word length: 16 bits (SSICR.SWL[2:0] = 001b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Number of frame words: One word (SSICR.FRM[1:0] = 00b), BCK polarity: Rising edge (BCKP = 1)
Other control bits of the communication format are at their initial values.
One frame
One frame
System word
System word
SSIBCK
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Start
trigger
D07 D06 D01 D00
D07 D06 D01 D00
D07
8 bits
Figure 39.39
Short frame in monaural format (with padding: system word length > data word length)
The monaural formats supported by SSIE consist of short frames and long frames. See reference 39.5.2.1 and reference
39.5.2.2 for the difference between these two frames.
For the state of external pins state when SSIE is in the idle state, see reference 39.7.1.
Note:
SSIE has the SSILRCK/SSIFS pin, which indicates the synchronization of communication. When SSIE is in slave
mode (SSICR.MST = 0), the communication format SSIE uses must match that of the other-party device to
communicate. SSIE uses the signal input by the SSILRCK/SSIFS pin only as a trigger to start communication.
39.5.2.1
Short frame
When a short frame is used (SSICR.DEL = 0), the SSILRCK/SSIFS signal indicating the start of serial data is set to high
level only for 1 cycle of SSIBCK. Data transfer starts at the falling edge of the signal.
39.5.2.2
Long frame
When a long frame is used (SSICR.DEL = 1), the SSILRCK/SSIFS signal indicating the start of serial data is set to high
level only for 2 cycles of SSIBCK. See Figure 39.40. Data transfer starts at the rising edge of the signal.
System word length: 8 bits (SSICR.SWL[2:0] = 000b),
Data word length: 8 bits (SSICR.DWL[2:0] = 000b),
Number of frame words: One word (SSICR.FRM[1:0] = 00b)
Delay of transfer data: No delay (SSICR.DEL = 1)
BCK polarity: Rising edge (BCKP = 1)
Other control bits of communication format are at their initial values.
One frame
One frame
System word
System word
SSIBCK
Figure 39.40
SSILRCK/
SSIFS
Start trigger
SSITXD0/
SSIRXD0/
SSIDATA0
D07 D06
D00 D07 D06
D00 D07
Long frame in monaural format (without padding)
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39.5.3
39. Serial Sound Interface Enhanced (SSIE)
TDM Format
The TDM format is a communication format used for connection with TDM-compatible multi-channel devices. With this
format setting (SSIOFR.OMOD[1:0] = 01b), one frame is configured with four to eight system words set with the
SSICR.FRM[1:0] bits. With this format, the SSILRCK/SSIFS signal is at a high level for the first one system word and at
a low level for the rest. The pulse generated on the SSILRCK/SSIFS signal is defined as the SYNC pulse and its rising
edge indicates the start of one frame. Figure 39.41 and Figure 39.42 show the TDM formats without and with padding,
respectively.
System word length: 8 bits (SSICR.SWL[2:0] = 000b), Data word length: 8 bits
(SSICR.DWL[2:0] = 000b), Number of frame words: Four words (SSICR.FRM[1:0] = 01b)
Other control bits of communication format are at their initial values.
One frame
System word
System word
System word
System word
SSIBCK
SSILRCK/
SSIFS
Start trigger
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.41
D07 D06 D01 D00 D17 D16 D11 D10 D27 D26 D21 D20 D37 D36 D31 D30 D07
TDM format (without padding: system word length = data word length)
System word length: 16 bits (SSICR.SWL[2:0] = 001b), Data word length: 8 bits (SSICR.DWL[2:0] = 000b), Number of frame words: Four words
(SSICR.FRM[1:0] = 01b)
Other control bits of communication format are at their initial values.
One frame
System word
System word
System word
System word
SSIBCK
SSILRCK/
SSIFS
Start trigger
SSITXD0/
SSIRXD0/
SSIDATA0
D07
D06
D01
D00
D17
D16
D11
D10
D27
D26
D21
D20
D37
D36
D31
D30
D07
8 bits
Figure 39.42
TDM format (with padding: system word length > data word length)
For the state of external pins when SSIE is in the idle state, see reference 39.7.1.
Note:
SSIE has the SSILRCK/SSIFS pin, which indicates the synchronization of communication. When SSIE is in slave
mode (SSICR.MST = 0), the communication format that SSIE uses must match that of the other-party device to
communicate. SSIE uses the signal input by the SSILRCK/SSIFS pin only as a trigger to start communication.
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39.6
39. Serial Sound Interface Enhanced (SSIE)
Communication Modes
SSIE supports the following communication modes. Table 39.13 lists the control bits that are not available with each
communication mode. See reference 39.6.1 to reference 39.6.5 for details of these communication modes.
Table 39.12
Communication modes
Communication Mode
SSICR.MST Bit
SSICR.REN Bit
SSICR.TEN Bit
Slave-mode transmission
0
0
1
Slave-mode reception
0
1
0
Slave-mode transmission and
reception
0
1
1
Master-mode transmission
1
0
1
Master-mode reception
1
1
0
Master-mode transmission and
reception
1
1
1
Table 39.13
Control bits that cannot be used in each communication mode
Communication Mode
Control Bit
Slave-mode
Reception
Slave-mode
Transmission
Slave-mode
Transmission
and
Reception
SSICR.CKS
Invalid
Invalid
Invalid
Available
Available
Available
SSICR.CKDV
Invalid
Invalid
Invalid
Available
Available
Available
SSICR.MUEN
Invalid
Available
Available
Invalid
Available
Available
SSICR.TEN
Invalid
Available
Available
Invalid
Available
Available
SSICR.REN
Available
Invalid
Available
Available
Invalid
Available
Master-mode
Reception
Master-mode
Transmission
Master-mode
Transmission
and
Reception
SSIFCR.AUCKEN
Invalid
Invalid
Invalid
Available
Available
Available
SSIFCR.TIE
Invalid
Available
Available
Invalid
Available
Available
SSIFCR.RIE
Available
Invalid
Available
Available
Invalid
Available
SSIFCR.TFRST
Invalid
Available
Available
Invalid
Available
Available
SSIFCR.RFRST
Available
Invalid
Available
Available
Invalid
Available
SSIOFR.BCKASTP
Invalid
Invalid
Invalid
Available
Available
Available
SSIOFR.LRCONT
Invalid
Invalid
Invalid
Available
Available
Available
SSIOFR.OMOD
Available
Available
Available
Available
Available
Available
SSISCR.TDES[4:0]
Invalid
Available
Available
Invalid
Available
Available
SSISCR.RDFS[4:0]
Available
Invalid
Available
Available
Invalid
Available
“Invalid” means it has no effect on operation. Writing is possible.
39.6.1
Slave-mode Communication
SSIE operates in slave mode with SSICR.MST = 0. The SSIBCK and SSILRCK/SSIFS signals to be used for serial-data
communication must be supplied from an external device. If these signals do not match the communication format set for
SSIE, operation is not guaranteed.
39.6.2
Master-mode Communication
SSIE operates in master mode with SSICR.MST = 1. The SSIBCK and SSILRCK/SSIFS signals to be used for serialdata communication must be internally generated from the audio clock. These signals use the format according to the
setting of SSIE. If the communication format that the slave device uses does not match the communication format set for
SSIE, the operation is unpredictable.
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39.6.3
39. Serial Sound Interface Enhanced (SSIE)
Transmission
SSIE transmits serial data to the other-party device when the SSICR.TEN bit is 1 and the SSICR.REN bit is 0. If the
communication format that the other-party device uses does not match the communication format set for SSIE, the
operation is unpredictable.
39.6.4
Reception
SSIE receives serial data from the other-party device when the SSICR.TEN bit is 0 and the SSICR.REN bit is 1. If the
communication format that the other-party device uses does not match the communication format set for SSIE, the
operation is unpredictable.
39.6.5
Transmission and Reception
SSIE transmits and receives serial data to and from the other-party device when the SSICR.TEN bit is 1 and the
SSICR.REN bit is 1. If the communication format the other-party device uses does not match the communication format
set for SSIE, the operation is unpredictable.
39.7
Operation
SSIE has the following two main operation states. Figure 39.43 shows the SSIE state transition.
Idle state (SSISR.IIRQ = 1)
Communication state (SSISR.IIRQ = 0).
Reset
Idle state*1
SSICR.TEN = 1 or
SSICR.REN = 1
SSICR.TEN = 0 or
SSICR.REN = 0
Communication
state*2
Note 1. See reference 39.8.1 for details of the idle state.
Note 2. See reference 39.8.2 for details of the communication state.
Figure 39.43
SSIE state transition
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39.7.1
39. Serial Sound Interface Enhanced (SSIE)
Idle State
In this state, communication of SSIE is halted. If, however, the SSICR.MST bit is 1, the output of BCK and LR
clock/frame synchronization signals to external pins can be controlled according to the settings of the
SSIOFR.BCKASTP and SSIOFR.LRCONT bits. This function is common to all formats. For details, see Table 39.14.
Table 39.14
Output from external pins in the idle state
Output from Pins
SSICR.MST
SSIOFR.BCKASTP
SSIOFR.LRCONT
0
—
—
1
0
0
1
0
1
1
1
0
1
1
1
SSIBCK
SSILRCK/SSIFS
SSITXD0/SSIDATA0
Stop
Stop
Stop
Supply
Stop
Stop
Supply
Supply
Stop
Stop
Stop
Stop
Stop
Supply
Stop
In the I2S format, the control bits of communication format are at their initial values other than the following.
(Operation at SSICR.BCKP = 0: Falling edge, SSISR.IIRQ = 1)
PCLKB
SSIOFR.LRCONT
Synchronization One cycle
start
Synchronization One cycle Frame boundary waiting
stop
BCK
SSILRCK/SSIFS
L channel
One frame
In the I2S format, the control bits of communication format are at their initial values other than the following.
(Operation at SSICR.BCKP = 1: Rising edge, SSISR.IIRQ = 1)
PCLKB
SSIOFR.LRCONT
Synchronization One cycle
start
Synchronization One cycle Frame boundary waiting
stop
BCK
SSILRCK/SSIFS
L channel
One frame
Figure 39.44
Note:
Example of disabling LR clock/frame synchronization continuation by SSIOFR.LRCONT
To stop the output to the SSILRCK/SSIFS pin with SSIOFR.LRCONT when SSIE is in the idle state in mastermode communication (SSICR.MST = 1), note that the output stops when the value of the SSIOFR.LRCONT bit is
changed from 1 to 0. Make sure that the other-party device is not affected.
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39. Serial Sound Interface Enhanced (SSIE)
In the I2S format, the control bits of communication format are at their initial values other than the following.
(Operation at SSICR.BCKP = 0: Falling edge, SSISR.IIRQ = 1)
PCLKB
SSIOFR.BCKASTP
Synchronization
Synchronization
BCK
SSIBCK
In the I2S format, the control bits of communication format are at their initial values other than the following.
(Operation at SSICR.BCKP = 1: Rising edge, SSISR.IIRQ = 1)
PCLKB
SSIOFR.BCKASTP
Synchronization
Synchronization
BCK
SSIBCK
Figure 39.45
Note:
Example of stopping SSIBCK with SSIOFR.BCKASTP
To stop the output to the SSIBCK pin with SSIOFR.BCKASTP in master-mode communication (SSICR.MST = 1)
and while SSIE is in the idle state, note that the output stops when the value of the SSIOFR.BCKASTP bit is
changed from 0 to 1. So, make sure that the other-party device is not affected.
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39.7.2
39. Serial Sound Interface Enhanced (SSIE)
Communication States
In this state, SSIE is in communication. Figure 39.46 shows the transitions of communication states and Table 39.15 lists
the conditions for transition. If the transition condition is not satisfied, the state does not transit.
Operation idle
state
communication
Data
communication
detail
Padding
communication
idle
Data
communication
Padding
communication
Communication state
Condition 1
Data
communication
Condition 4
Reset
Idle
Condition 5
Condition 3
Condition 6
Condition 2
Figure 39.46
Table 39.15
Padding
communication
Communication state transition
Condition for communication state transition
Condition
Number
Condition for Transition
1
Writing SSICR.TEN = 1 or SSICR.REN = 1 while SSICR.SDTA = 0 or in the setting without padding bits.
2
Writing SSICR.TEN = 1 or SSICR.REN = 1 while SSICR.SDTA = 1 and in the setting with padding bits.
3
The following three conditions are all met:
SSICR.TEN = 1 or SSICR.REN = 1
In the setting with padding bits
The last bit of the data words has been transferred.
4
Both the following two conditions are met:
SSICR.SDTA = 1 or without padding bits
While SSICR.TEN = 0 and SSICR.REN = 0, the last bit of the data words in a frame has been transferred.
5
Transfer of the last padding bit is complete while SSICR.TEN = 1 or SSICR.REN = 1
6
Both the following two conditions are met:
SSICR.SDTA = 0 and with padding bits
While SSICR.TEN = 0 and SSICR.REN = 0, the last padding bit has been transferred.
See Table 39.11 for the setting with/without padding bits.
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39.7.2.1
39. Serial Sound Interface Enhanced (SSIE)
Data communication state
In this state, SSIE is in communication. Data of the data word length set with the SSICR.DWL[2:0] bits is transmitted,
received, or transmitted and received.
State Transition in the Setting without Padding Bits
During communication (SSISR.IIRQ = 0), SSIE is in data communication for the entire time. By disabling transmission
and reception (SSICR.TEN = 0, SSICR.REN = 0), SSIE transits to the idle state. For details, see Figure 39.47 and Figure
39.48.
I2S format
Other control bits of communication format are at their initial values .
PCLKB
SSICR.TEN
BCK
Communication
state
Data communication
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.47
Communication
data
Communication data
of one frame
Communication
data
Continuation of the data communication
I2S format
Other control bits of communication format are at their initial values.
PCLKB
SSICR.TEN/
SSICR.REN
BCK
Operation state
Data communication
Idle
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.48
Communication
data
Communication data
of one frame
Halt from the data communication (without padding bits)
State Transition in the Setting with Padding Bits
When SSIE ends the transfer of the last bit of a data word during communication (SSISR.IIRQ = 0), SSIE transitions
from the data communication state to the padding communication state in Figure 39.49. Except in the status with
SSICR.SDTA = 1 and with transmission and reception disabled (SSICR.TEN = 0 and SSICR.REN = 0), SSIE transitions
from the data communication state to the idle state when it stops communication in Figure 39.51.
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39. Serial Sound Interface Enhanced (SSIE)
I2S format,
Data word length: 20 bits,
System word length: 24 bits
Other control bits of communication format are at their initial values.
PCLKB
SSICR.TEN
BCK
Communication
state
Data communication
Padding communication
Data communication
Communication data
Padding bit
Communication data
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.49
Transition from data communication to padding communication
I2S format
Data alignment: Padding ? data
Other control bits of communication format are at their
initial values.
Data
communication
Padding
communication
PCLKB
SSICR.TEN/
SSICR.REN
BCK
Operation state
Idle
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.50
Communication data
Communication
data
Communication
data
Halt from data communication (with padding bits)
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39.7.2.2
39. Serial Sound Interface Enhanced (SSIE)
Padding communication
In this state, SSIE is during communication. The padding bits set with the SSICR.SWL[2:0] bits and SSICR.DWL[2:0]
bits are transmitted, received, or transmitted and received.
State Transition in the Setting with Padding Bits
When SSIE ends transfer of the last padding bit during communication (SSISR.IIRQ = 0), SSIE transitions to the data
communication state in Figure 39.49. If SSIE is in the status with SSICR.SDTA = 0 and transmission and reception
disabled (SSICR.TEN = 0 and SSICR.REN = 0), SSIE transitions from the padding communication state to the idle state
when it stops communication in Figure 39.51.
I2S format, Data word length: 20 bits, System word length: 24 bits,
Transmission enabled → disabled,
Other control bits of communication format are at their initial values.
PCLKB
SSICR.TEN/
SSICR.REN
BCK
Operation state
Data
communication
Padding communication
Communicaiton
data
Padding bits
Idle
SSILRCK/
SSIFS
SSITXD0/
SSIRXD0/
SSIDATA0
Figure 39.51
39.8
Halt from the padding communication
Communication Operation
Figure 39.52 shows the communication flow of SSIE.
Start of setting
Start communication
Transmission/reception/
transmission and reception
Resume
communication
Halt communication
SSIE stops
Figure 39.52
SSIE communication operation
The procedure of each operation is described from reference 39.8.1 to reference 39.8.7.
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39.8.1
39. Serial Sound Interface Enhanced (SSIE)
Start Communication
This section describes how to start communication of SSIE. Figure 39.53 shows the procedure to start communication.
Be sure to follow the procedure. See reference 39.8.2 for transmission operation and reference 39.8.3 for reception
operation.
Start of setting
System reset cleared
PCLKB clock supply to SSIE
Master-mode transmission?
Set if the product has the PCLKB clock.
No
Yes
BCK setting
(SSICR.MST = 0, BCKP)
BCK setting
(SSICR.MST = 1, CKS, BCKP, CKDV[3:0])
AUDIO_MCK supply enabled
(SSIFCR.AUCKE = 1)
Initialization of FIFOs
(SSIFCR.TFRST and RFRST)
Writing transmit data to FIFO
(Writing to SSIFTDR)
Setting of interrupt handling operation
(ICU/DTC/DMAC)
Setting of communication format *1
(See the lists on the right)
Interrupt output enabled
(See the lists on the right)
For transmission operation, it is possible to preliminarily write
necessary data in one frame unit. Clear the TDE flag after
completing the writing. Writing is not required when
communication is all done using DMAC/DTC.
・Setting of DMAC/DTC
Transfer mode: block transfer
Transfer data: One frame data
・At transmission
Number of transfers: [all transfer frames] - [initially written frames]
・At reception
Number of transfers: [all transfer frames] - [one frame]
・SSICR register: FRM, DWL, SWL, LRCKP, SPDP, SDTA,
PDTA, DEL
・SSIFCR register: BSW
・SSIOFR register: OMOD
・SSISCR register: TDES, RDFS
・SSICR register: TUIEN, TOIEN, RUIEN, ROIEN
・SSIFCR register: TIE,RIE
Communication enabled
(Writing 1 to SSICR.TEN and REN)
Communication starts
Note 1. Set SSICR.MUEN, SSIOFR.BCKASTP, and SSIOFR.LRCONT after completing the setting of the
communication format.
Figure 39.53
Procedure to start communication (CPU operation procedure)
SSIE can perform continuous communication based on interrupts by the DTC/DMAC. For transmission, write 1 to
SSIFCR.TIE, SSICR.TUIEN, and SSICR.TOIEN. For reception, write 1 to SSIFCR.RIE, SSICR.RUIEN, and
SSICR.ROIEN.
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39.8.2
39. Serial Sound Interface Enhanced (SSIE)
Transmission
The transmission procedure in Figure 39.54 must be followed throughout a transmission operation.
After transmission is enabled (SSICR.TEN = 1 and SSICR.REN = 0), SSIE starts transmission when a start trigger is
generated by SSILRCK/SSIFS with the serial data for at least a frame contained in the Transmit FIFO Data Register
(SSIFTDR). SSIE outputs a transmit data empty interrupt to the DTC/DMAC according to the TDE setting condition
(SSISCR.TDES[4:0]) and the status of Transmit Data Empty Interrupt Enable (SSIFCR.TIE) bit specified in the
communication start procedure. This interrupt requests writing to the Transmit FIFO Data Register (SSIFTDR). In the
communication start procedure, specify writing to the Transmit FIFO Data Register (SSIFTDR) as the DTC/DMAC
operation in response to the Transmit Data Empty Interrupt. With this setting, SSIE can continuously transmit data not
through the CPU. The Transmit Data Empty Interrupt is generated when the free space size of Transmit FIFO Data
Register reaches the value set in SSISCR.TDES[4:0]. The number of times of writing must be specified in accordance
with the free space size of the Transmit FIFO Data Register indicated by the Transmit Data Empty Interrupt. If an error
occurs, perform the error-handling procedure as instructed in the communication stop procedure.
Transmission starts
Wait for interrupts
Yes
Communication error
generated?
(ICU)
No
Number of set
writing times completed?
(DTC/DMAC)
No
Yes
DTC/DMAC process
completed?
(ICU)
No
Yes
Communication halt
Figure 39.54
Note:
Transmission procedure
The communication flow defined in SSIE uses the DTC/DMAC. If you do not use the DTC/DMAC, perform polling
of the value 1 of SSIFSR.TDE to write data to SSIFTDR. The number of times data is written to SSIFTDR by
detecting the value 1 in SSIFSR.TDE, must be in accordance with the free space size of the Transmit FIFO Data
Register specified by SSISCR.TDES[4:0]. After as much transmit data as the free space size is written to
SSIFTDR, the SSIFSR.TDE flag must be cleared. Continuous transmission is enabled by repeating data writing.
If the SSIFSR.TDE flag is not cleared, the flag is not cleared automatically.
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39.8.3
39. Serial Sound Interface Enhanced (SSIE)
Reception
The reception procedure in Figure 39.55 must be followed throughout a reception operation.
After reception is enabled (SSICR.TEN = 0 and SSICR.REN = 1), SSIE starts reception when a start trigger is generated
by SSILRCK/SSIFS. SSIE outputs a receive data full interrupt to the DTC/DMAC according to the RDF Setting
Condition Select (SSISCR.RDFS[4:0]) and the status of Receive Data Full Interrupt Enable (SSIFCR.RIE) bit specified
in the communication start procedure. This interrupt requests data reading from the Receive FIFO Data Register
(SSIFRDR). In the communication start procedure, specify reading from the Receive FIFO Data Register (SSIFRDR) as
the DTC/DMAC operation in response to the receive data full interrupt. With this setting, SSIE can continuously read
data not through the CPU. The receive data full interrupt is generated when data as much as the capacity of Receive FIFO
Data Register has been stored. The number of times of reading must be specified in accordance with the data size of the
Receive FIFO Data Register indicated by the receive data full interrupt. If an error occurs, perform the error-handling
procedure as instructed in the communication stop procedure.
Reception starts
Wait for interrupts
Yes
Communication error
generated?
(ICU)
No
Number of set
reading times completed?
(DTC/DMAC)
No
Yes
DTC/DMA process
completed?
(ICU)
Yes
No
Communication halt
Figure 39.55
Note:
39.8.4
Reception procedure
The communication flow defined in SSIE uses the DTC/DMAC. If you do not use the DTC/DMAC, perform polling
of the value 1 of SSIFSR.RDF to read data from SSIFRDR. The number of times of reading data from SSIFRDR
by detecting the value 1 of SSIFSR.RDF must be in accordance with the receive data storage capacity of the
Receive FIFO Data Register specified in SSISCR.RDFS[4:0]. After the received data is read from SSIFRDR, the
SSIFSR.RDF flag must be cleared. Continuous reception is enabled by repeating data reading. If the
SSIFSR.RDF flag is not cleared, the flag is not cleared automatically.
Transmission and Reception
After transmission and reception are enabled (SSICR.TEN = 1 and SSICR.REN = 1), SSIE starts transmission and
reception when a start trigger is generated by SSILRCK/SSIFS with the serial data for at least a frame contained in the
Transmit FIFO Data Register (SSIFTDR). SSIE can continuously transmit and receive data by performing the
procedures described in reference 39.8.2 and reference 39.8.3, respectively. For the procedure to stop transmission and
reception, see reference 39.8.5.
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39.8.5
39. Serial Sound Interface Enhanced (SSIE)
Halt Communication
This section describes how to halt communication of SSIE. Figure 39.56 shows the procedure to halt communication. Be
sure to follow the procedure.
Communication
After writing TEN = 0 and REN = 0,
communication halts at the break
point of a frame.
Disabling transmission and reception
(SSICR.TEN = 0 and REN = 0)
Stop interrupt handling
(ICU/DTC/DMAC)
Disable interrupt output
(SSIFCR.TIE = 0 and RIE = 0)
Communication halted
Communication error
generated?
Yes
Error handling
No
Resume
communication of SSIE?
Yes
Process to resume
communication
No
Master-mode communication?
Yes
No
Stop PCLKB of SSIE
Stop AUDIO_MCK
(SSIFCR.AUCKE = 0)
Set if the product has PCLKB clock.
SSIE stops
Figure 39.56
Procedure to halt communication (CPU operation procedure)
To halt the communication of SSIE, supply of the following clocks is required until the SSISR.IIRQ bit indicates an idle
state:
Input clock from the SSIBCK pin when SSICR.MST = 0
AUDIO_MCK when SSICR.MST = 1.
To resume the communication of SSIE in the previous setting, see reference 39.8.7.
Note:
When communication of SSIE is halted according to the procedure to halt communication shown in Figure 39.56,
resume the communication according to the procedure to resume communication shown in Figure 39.58.
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39.8.6
39. Serial Sound Interface Enhanced (SSIE)
Error Handling
SSIE has the following four errors:
Transmit underflow error
Transmit overflow error
Receive underflow error
Receive overflow error.
When an underflow error or overflow error is generated, SSIE needs to be restarted. Follow the procedure to halt
communication in Figure 39.56 and the error-handling procedure in Figure 39.57.
Error handling
Clear interrupt status flag
(SSISR register)
Review operation of DTC/DMAC
Review of ICU process
Error handling
completed
Figure 39.57
Error-handling procedure
Four error operations are described as follows. When the Interrupt Output Enable bit of the SSICR register is enabled and
the error flags are set, an error interrupt is generated. See the descriptions of flags in reference 39.4.2 for the setting
conditions of the error flags.
(1)
Transmit Underflow Error
If a transmit underflow error occurs, review the number of times of writing data to the transmit FIFO data register
(SSIFTDR) in response to a transmit data empty interrupt. After a transmit underflow error occurs, SSIE outputs 0s as
data. To normally output the serial data written to the Transmit FIFO Data Register (SSIFTDR) to the
SSITXD0/SSIDATA0 pin, follow the procedure to halt communication in Figure 39.56 and the error-handling procedure
in Figure 39.57. After this error occurs, serial data is consumed as usual. If you resume communication, write the serial
data from the beginning.
(2)
Transmit Overflow Error
If a transmit overflow error occurs, review the number of times of writing data to the Transmit FIFO Data Register
(SSIFTDR) in response to transmit data empty interrupts. The serial data written to the Transmit FIFO Data Register
(SSIFTDR) that caused the transmit overflow error becomes invalid. This error can occur regardless of whether a
transmission operation is being done. To recover from the error, follow the procedure to halt communication in Figure
39.56 and the error-handling procedure in Figure 39.57. When you resume communication, deal with the invalid serial
data appropriately.
(3)
Receive Underflow Error
If a receive underflow error occurs, review the number of times of reading data from the Receive FIFO Data Register
(SSIFRDR) in response to receive data full interrupts. The values read from the Receive FIFO Data Register (SSIFRDR)
that caused the receive underflow error are undefined. This error can occur regardless of whether a reception operation is
being done. To recover from the error, follow the procedure to halt communication in Figure 39.56 and the errorhandling procedure in Figure 39.57.
(4)
Receive Overflow Error
If a receive overflow error occurs, review the number of times of reading data from the Receive FIFO Data Register
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39. Serial Sound Interface Enhanced (SSIE)
(SSIFRDR) in response to receive data full interrupts. The receive data that caused the receive overflow error cannot be
stored in the Receive FIFO Data Register (SSIFRDR). To recover from the error, follow the procedure to halt
communication in Figure 39.56 and the error-handling procedure in Figure 39.57.
39.8.7
Resume Communication
When you resume the communication using SSIE, follow the communication resume procedure in Figure 39.58. The
communication resume procedure is designed with the assumption that you resume the communication that is stopped by
the communication stop procedure without changing any settings. If you want to change the clock and slave/master
settings, follow the communication start procedure in Figure 39.53. For details about the transmission operation and
reception operation after starting communication, see reference 39.8.2 and reference 39.8.3, respectively.
Process to resume
communication
Enable ICU process
(idle mode interrupt)
Setting of interrupt output
(SSICR register)
TUIEN = 0, TOIEN = 0,
RUIEN = 0, ROIEN = 0, IIEN = 1
Wait for entering idle state
Idle mode interrupt
generated?
(ICU process)
No
Yes
Initialization of FIFO
(SSIFCR.TFRST and RFRST)
Writing transmit data to FIFO
(Writing to SSIFTDR)
Setting of interrupt handling
(ICU/DMAC/DTC)
Enable interrupt output
(write 1 to necessary bits in the right list)
For transmission operation, it is possible to preliminarily write necessary data in
one frame unit.
Clear the TDE flag after completing the writing.
Writing is not required when communication is all done using the DMAC/DTC.
・Setting of the DMAC/DTC
Transfer mode: block transfer
Transfer data: One frame
・At transmission
Number of transfers: [all transfer frames] - [initially written frames]
・At reception
Number of transfers: [all transfer frames] - [one frame]
・SSICR register
TUIEN = 1, TOIEN = 1, RUIEN = 1, ROIEN = 1, and IIEN = 0
・SSIFCR register
TIE and RIE
Enable communication
(write 1 to SSICR.TEN and REN)
Communication starts
Figure 39.58
Procedure to resume communication (CPU operation procedure)
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39.9
39. Serial Sound Interface Enhanced (SSIE)
Interrupts
Table 39.16 lists the interrupt sources. Set enable/disable of interrupt output of each source with the TUIEN, TOIEN,
RUIEN, ROIEN, and IIEN bits in the SSICR register, and the TIE and RIE bits in the SSIFCR register.
Table 39.16
SSIE interrupt sources
DMAC/DTC
activation
Channel
Interrupt source
Description
Interrupt flag
SSIE0
SSIE0_SSIF
SSISR.TUIRQ
SSISR.TOIRQ
SSISR.RUIRQ
SSISR.ROIRQ
SSISR.IIRQ
SSIE0_SSIRXI
Receive data full interrupt
SSIFSR.RDF
Possible
SSIE0_SSITXI
Transmit data empty interrupt
SSIFSR.TDE
Possible
39.9.1
Transmit underflow interrupt
Transmit overflow interrupt
Receive underflow interrupt
Receive overflow interrupt
Idle interrupt.
Not possible
SSIE0_SSIF Interrupt
This interrupt source combines five interrupts. Enable the output of the necessary interrupts before using SSIE. The five
interrupts are operated by using the flags assigned to individual interrupts and the interrupt output enable bits. To clear an
interrupt, set the interrupt enable to 0 or clear the interrupt flag to 0.
PCLKB
Interrupt enable
Interrupt flag
SSIE0_SSIF
interrupt
Figure 39.59
Timing Diagram of the common interrupt source, SSIE0_SSIF
Transmit underflow interrupt
As the transmit underflow interrupt, SSISR.TUIRQ is output while SSICR.TUIEN = 1. When you use SSIE for
transmission, enable the output of this interrupt (SSICR.TUIRQ = 1). If this interrupt occurs, follow the instructions in
the procedure to halt communication in Figure 39.56 and the error-handling procedure in Figure 39.57.
Transmit overflow interrupt
As the transmit overflow interrupt, SSISR.TOIRQ is output while SSICR.TOIRQ = 1. When you use SSIE for
transmission, enable the output of this interrupt (SSICR.TOIRQ = 1). If this interrupt occurs, follow the instructions in
the procedure to halt communication in Figure 39.56 and the error-handling procedure in Figure 39.57.
Receive underflow interrupt
As the receive underflow interrupt, SSISR.RUIRQ is output while SSICR.RUIRQ = 1. When you use SSIE for reception,
enable the output of this interrupt (SSICR.RUIRQ = 1). If this interrupt occurs, follow the instructions in the procedure to
halt communication in Figure 39.56 and the error-handling procedure in Figure 39.57.
Receive overflow interrupt
As the receive overflow interrupt, SSISR.ROIRQ is output while SSICR.ROIRQ = 1. When you use SSIE for reception,
enable the output of this interrupt (SSICR.ROIRQ = 1). If this interrupt occurs, follow the instructions in the procedure to
halt communication in Figure 39.56 and error-handling procedure in Figure 39.57.
Idle mode interrupt
As the idle mode interrupt, SSISR.IIRQ is output while SSICR.IIEN = 1. This interrupt is used to make sure that
communication has stopped fully.
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39.9.2
39. Serial Sound Interface Enhanced (SSIE)
SSIE0_SSITXI Interrupt [Full-duplex communication]
The transmit data empty interrupt is a pulse interrupt that is output when the following condition is met:
SSIFCR.TIE = 1 and SSIFSR.TDE = 1
SSIE operation: When the value of SSIFSR.TDE changes from 0 to 1 while the value of SSIFCR.TIE is 1
CPU instruction: When the value of SSIFCR.TIE changes from 0 to 1 while the value of SSIFSR.TDE is 1
This interrupt is subject to the interrupt suppression function. If an interrupt condition for this interrupt occurs when the
DTC/DMAC is busy (when the DTC/DMAC cannot accept interrupts), the interrupt suppression function holds the
output of this interrupt. The held interrupt will be output after the DTC/DMAC is enabled to accept interrupts. For
details, see Figure 39.60.
PCLKB
Interrupt enable
Interrupt flag
Interrupt
busy state
Interrupt is
internally held
SSIE0_SSITXI
interrupt
Figure 39.60
39.9.3
SSIE0_SSITXI interrupt timing diagram
SSIE0_SSIRXI Interrupt
The receive data full interrupt is a pulse interrupt that is output when the following condition is met:
SSIFCR.RIE = 1 and SSIFSR.RDF = 1
SSIE operation: When the value of SSIFSR.RDF changes from 0 to 1 while the value of SSIFCR.RIE is 1
CPU instruction: When the value of SSIFCR.RIE changes from 0 to 1 while the value of SSIFSR.RDE is 1
This interrupt is subject to the interrupt suppression function. If an interrupt condition for this interrupt occurs when the
DTC/DMAC is busy (when the DTC/DMAC cannot accept interrupts), the interrupt suppression function holds the
output of this interrupt. The held interrupt is output after the DTC/DMAC is enabled to accept interrupts. The behavior of
this interrupt is the same as the behavior shown in Figure 39.60.
39.10 Software Resets
SSIE has three software reset bits to reset its states:
SSIE software reset (SSIFCR.SSIRST)
Transmit FIFO data register reset (SSIFCR.TFRST)
Receive FIFO data register reset (SSIFCR.RFRST).
This section describes the procedures for the three types of software resets.
39.10.1
(1)
Software Reset Procedure
SSIE Software Reset
For the SSIE Software Reset bit (SSIFCR.SSIRST), follow the procedure shown in Figure 39.61. After a reset, the same
setting is applied when it is resumed. To change the settings of clocks and slave/master mode, follow the procedure to
start communication in Figure 39.53. See reference 39.8.2 and reference 39.8.3 respectively for transmission and
reception after communication is resumed.
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39. Serial Sound Interface Enhanced (SSIE)
Software reset
processing
Stop peripheral functions coordinated with
SSIE
(ICU/DTC/DMAC)
Disable interrupt output
(Write 0 to SSIFCR.TIE and RIE)
Software reset
(SSIFCR.SSIRST)
Writing transmit data to FIFO
(Writing to SSIFTDR)
Resetting interrupt handling
(ICU/DTC/DMAC)
Enable interrupt output
(Write 1 to SSIFCR.TIE and RIE)
Stop peripheral IPs that are cooperating with SSIE.
Otherwise, they will be asynchronously cleared by
software reset.
Write 0 to release software reset because this bit is
not cleared to 0 by the automatic operation after
writing 1 to this bit. After completing the writing of 0 to
this bit and confirming that this bit became 0, start the
next processing.
For transmission operation, it is possible to
preliminarily write the necessary data in one frame
unit.
Clear the TDE flag after completing the writing.
Writing is not required when communication is all
done using DMAC/DTC.
· Setting of the DMAC/DTC
Transfer mode: block transfer
Transfer data: data of one frame
· At transmission
Number of transfers: [all transfer frames] - [initially written frames]
· At reception
Number of transfers: [all transfer frames] - [one frame].
Enable communication
(Write 1 to SSICR.TEN and REN)
Start
communication
Figure 39.61
(2)
Software reset procedure (CPU operation procedure)
Transmit FIFO data register reset
To perform a Transmit FIFO Data Register reset, follow the instructions in the procedure to start communication shown
in Figure 39.53 and the procedure to resume communication as shown in Figure 39.58.
(3)
Receive FIFO data register reset
To perform a Receive FIFO Data Register Reset, follow the instructions in the procedure to start communication shown
in Figure 39.53 and the procedure to resume communication as shown in Figure 39.58.
39.11 Notes
39.11.1
39.11.1.1
Notes for Slave-mode Communication
ADCKE control
In slave-mode communication (SSICR.MST = 0), SSIE needs the supply of SSIBCK. To stop BCK on the master side,
make sure that SSIE is in the idle state (SSISR.IIRQ = 1). If BCK is stopped before SSIE becomes idle, follow the
procedure to start communication in Figure 39.53 or wait for an idle state by using the procedure to resume
communication as shown in Figure 39.58.
39.11.1.2
SSILRCK/SSIFS pin
SSIE has the SSILRCK/SSIFS pin, which indicates the synchronization of communication. When SSIE is in slave mode
(SSICR.MST = 0), the communication format that SSIE uses must match that of the other-party device to communicate.
SSIE uses the signal input by the SSILRCK/SSIFS pin only as a trigger to start communication.
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39.11.2
39.11.2.1
39. Serial Sound Interface Enhanced (SSIE)
Notes for Master-mode Communication
ADCKE control
In master-mode communication (SSICR.MST = 1), SSIE operates with the audio clock (AUDIO_MCK). To stop SSIE
completely, make sure that SSIE is in the idle state (SSISR.IIRQ = 1) and then write 0 to SSIFCR.ADCKE.
39.11.2.2
LRCONT control
To stop the output to the SSILRCK/SSIFS pin with SSIOFR.LRCONT when SSIE is in the idle state in master-mode
communication (SSICR.MST = 1), note that the output stops when the value of the SSIOFR.LRCONT bit is changed
from 1 to 0. Make sure that the other-party device is not affected. For details, see Figure 39.44.
39.11.2.3
BCKASTP control
To stop the output to the SSIBCK pin with SSIOFR.BCKASTP in master-mode communication (SSICR.MST = 1) and
while SSIE is in the idle state, note that the output stops when the value of the SSIOFR.BCKASTP bit is changed from 0
to 1. So, make sure that the other-party device is not affected. For details, see Figure 39.45.
The BCKASTP bit cannot be used when the other-party device (which is a slave) requires the clock output from the
SSIBCK pin before and during communication.
39.11.3
39.11.3.1
Notes for Communication Flow
When an error interrupt is generated
SSIE has the following four errors:
Transmit underflow error
Transmit overflow error
Receive underflow error
Receive overflow error.
When an underflow error or overflow error is generated, SSIE needs to be restarted. Follow the procedure to halt
communication in Figure 39.56 and the error-handling procedure in Figure 39.57.
(1)
Transmit Underflow Error
If a transmit underflow error occurs, review the number of times that data is written to the Transmit FIFO Data Register
(SSIFTDR) in response to a transmit data empty interrupt. After a transmit underflow error occurs, SSIE outputs 0s as
data. To normally output the serial data written to the Transmit FIFO Data Register (SSIFTDR) to the
SSITXD0/SSIDATA0 pin, follow the procedure to halt communication as shown in Figure 39.56 and the error-handling
procedure in Figure 39.57. After this error occurs, serial data is consumed as usual. If you resume communication, write
the serial data from the beginning.
(2)
Transmit Overflow Error
If a transmit overflow error occurs, review the number of times data is written to the Transmit FIFO Data Register
(SSIFTDR) in response to transmit data empty interrupts. The serial data written to the Transmit FIFO Data Register
(SSIFTDR) that caused the transmit overflow error becomes invalid. This error can occur regardless of whether a
transmission operation is being done. To recover from the error, follow the procedure to halt communication as shown in
Figure 39.56 and the error-handling procedure in Figure 39.57. When you resume communication, deal with the invalid
serial data appropriately.
(3)
Receive Underflow Error
If a receive underflow error occurs, review the number of times that data is read from the Receive FIFO Data Register
(SSIFRDR) in response to receive data full interrupts. The values read from the Receive FIFO Data Register (SSIFRDR)
that caused the receive underflow error are undefined. This error can occur regardless of whether a reception operation is
being done. To recover from the error, follow the procedure to halt communication as shown in Figure 39.56 and the
error-handling procedure in Figure 39.57.
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(4)
39. Serial Sound Interface Enhanced (SSIE)
Receive Overflow Error
If a receive overflow error occurs, review the number of times that data is read from the Receive FIFO Data Register
(SSIFRDR) in response to receive data full interrupts. The receive data that caused the receive overflow error cannot be
stored in the receive FIFO Data Register (SSIFRDR). To recover from the error, follow the procedure to halt
communication shown in Figure 39.56 and the error-handling procedure in Figure 39.57.
39.11.3.2
Transmit data empty interrupt
The communication flow defined in SSIE uses the DTC/DMAC. If you do not use the DTC/DMAC, perform polling of
the value 1 of SSIFSR.TDE to write data to SSIFTDR. The number of times that data is written to SSIFTDR on detecting
1 in SSIFSR.TDE must be in accordance with the free space size of the transmit FIFO data register specified by
SSISCR.TDES[4:0]. After as much transmit data as the free space size is written to SSIFTDR, the SSIFSR.TDE flag
must be cleared. Continuous transmission is enabled by repeating data writing. If the SSIFSR.TDE flag is not cleared, the
flag is not cleared automatically.
39.11.3.3
Receive data full interrupt
The communication flow defined in SSIE uses the DTC/DMAC. If you do not use the DTC/DMAC, perform polling of
the value 1 of SSIFSR.RDF to read data from SSIFRDR. The number of times that data is read from SSIFRDR on
detecting 1 in SSIFSR.RDF must be in accordance with the receive data storage capacity of the receive FIFO data
register specified by SSISCR.RDFS[4:0]. After received data is read from SSIFRDR, the SSIFSR.RDF flag must be
cleared. Continuous reception is enabled by repeating data reading. If the SSIFSR.RDF flag is not cleared, the flag is not
cleared automatically.
39.11.3.4
Switching transfer modes
1. For state transition from transmission, reception, and transmission and reception, disable transmission and reception
(SSICR.TEN = 0, SSICR.REN = 0).
2. Confirm it is in the idle state (SSISR.IIRQ = 1).
3. In the idle state, set the SSICR.TEN bit and the SSICR.REN bit again and resume transfer.
39.11.3.5
Resume communication after halting SSIE
When communication of SSIE is halted according to the procedure to halt communication in Figure 39.56, resume
communication according to the procedure to resume communication in Figure 39.58.
39.11.4
39.11.4.1
Write Access Restriction
SSICR register
If the TEN bit or REN bit is rewritten, make sure that the SSISR.IIRQ bit is in the desired status. If the value of the TEN
or REN bit is changed by rewriting, subsequent operation is unpredictable. For example, when transmission or reception
is enabled, check that SSISR.IIRQ is 0; when transmission or reception is disabled, check that SSISR.IIRQ is 1.
(1)
TEN Bit and REN Bit
These bits enable/disable transmission and reception. When 1 is written to one of these bits, the corresponding
communication operation starts in synchronization with a start trigger by the SSILRCK/SSIFS signal. For details, see
reference 39.8.2, reference 39.8.3, and reference 39.8.4. When 0 is written to this bit, the current communication
operation stops at the next frame boundary. To use SSIE for both transmission and reception, always write 1 to these bits
together. When stopping the communication using SSIE, always disable both transmission and reception (write 0 to the
TEN and REN bits).
39.11.4.2
(1)
SSISR register
Clearing TUIRQ and TOIRQ
After communication is enabled (by changing the value of SSICR.TEN bit from 0 to 1), the transmission error flags
(TOIRQ and TUIRQ in the SSISR register) are cleared. If, however, the SSISR register is read continuously, the cleared
status of the transmission error flags might be unable to be read.
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(2)
39. Serial Sound Interface Enhanced (SSIE)
Clearing RUIRQ and ROIRQ
After communication is enabled (by changing the value of SSICR.REN bit from 0 to 1), the reception error flags
(RUIRQ and ROIRQ in the SSISR register) are cleared. If, however, the SSISR register is read continuously, the cleared
status of the reception error flags might be unable to be read.
39.11.4.3
Communication state
Writing to the bits with the shaded area in Table 39.17 is prohibited. If written, the operation performed immediately
after the writing is not guaranteed.
Table 39.17
Bits protected from writing during communication
+0
Symbol
SSICR
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
+0
—
CKS
TUI
EN
TOI
EN
RUI
EN
ROI
EN
IIEN
—
FRM[1:0]
+2
—
MS
T
BCK
P
LRC
KP
SPD
P
SDT
A
PDT
A
DEL
—
—
TUI
RQ
TOI
RQ
RUI
RQ
ROI
RQ
IIRQ
—
—
—
—
Address
(BASE+)
00h
+1
31
DWL[2:0]
CKDV[3:0]
SWL[2:0]
MU
EN
—
TEN
RE
N
—
—
—
—
—
SSISR
04h
+0
+2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSIFCR
10h
+0
AUC
KE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SSI
RST
+2
—
—
—
—
BS
W
—
—
—
—
—
—
—
TIE
RIE
TFR
ST
RFR
ST
—
—
—
—
—
—
—
TDE
—
—
—
—
—
—
—
RDF
—
—
SSIFSR
14h
+0
—
—
TDC[5:0]
+2
—
—
RDC[5:0]
SSIFTDR
18h
+0
FTDR[31:16]
+2
FTDR[15:0]
+0
FRDR[31:16]
+2
FRDR[15:0]
SSIFRDR
SSIOFR
SSISCR
1ch
20h
24h
+0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+2
—
—
—
—
—
—
BCK
AST
P
LRC
ON
T
—
—
—
—
—
—
+0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+2
—
—
—
—
—
—
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OMOD[1:0]
—
—
RDFS[4:0]
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40. Sampling Rate Converter (SRC)
40.
Sampling Rate Converter (SRC)
40.1
Overview
The Sampling Rate Converter (SRC) is used to convert the sampling rate of data produced by various audio decoders,
including WMA, MP3, and AAC. Both 16-bit stereo and monaural data are supported. The sampling rate of the input
signal can be one of the following (in kHz): 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48. The sampling rate of the output
signal can be one of the following (in kHz): 8, 16, 32, 44.1, or 48. Independent FIFOs are provided for input and output.
In a typical application, a DMA controller can be used to transfer PCM audio data from the SRAM (for example) to the
SRC. Sample-converted audio data from the SRC can then be transferred using the DMA Controller to the SSIE
interface, from where it can be transmitted to an external audio codec.
Table 40.1 shows the SRC specifications and Figure 40.1 shows a block diagram.
Table 40.1
SRC specifications
Parameter
Specifications
Data size
16 bits (stereo/monaural)
Sampling rates
Input
Selectable to 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48 kHz
Output
Selectable to 8*1, 16*1, 32, 44.1, or 48 kHz
Processing capacity
Maximum of 7.7 μs for one sample output interval (PCLKB = 60 MHz, 462 clocks)
SNR
80 db or higher
Interrupt sources
Five
Input FIFO empty, output FIFO full, output FIFO overflow, output FIFO underflow, and
conversion end
DMA transfer sources
Two
Input FIFO empty and output FIFO full
Module-stop function
Module-stop state can be set to reduce power consumption
Note 1.
Only when input of 44.1 kHz is selected.
SRCFCTR
Internal peripheral bus
SRCID
Coefficient data
Input FIFO
32 bits × 8 stages
FIR filter
SRCOD
SRCIDCTRL
SRCODCTRL
SRCCTRL
SRCSTAT
Output FIFO
32 bits × 16 stages
SRC_IDEI
SRC_ODFI
SRC_OVFI
SRC_UDFI
SRC_CEFI
Interrupt request/DMA transfer request
I/O controller
SRCFCTR:
SRCID:
SRCOD:
SRCIDCTRL:
Figure 40.1
Filter Coefficient Table
Input Data Register
Output Data Register
Input Data Control Register
SRCODCTRL: Output Data Control Register
SRCCTRL:
Control Register
SRCSTAT:
Status Register
SRC block diagram
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40.2
40. Sampling Rate Converter (SRC)
Register Descriptions
40.2.1
Input Data Register (SRCID)
Address(es): SRC.SRCID 4004 DFF0h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The SRCID register is a 32-bit write-only register used to input the data before sampling rate conversion. All the bits are
read as 0. The data input to SRCID is stored in the 8-stage input FIFO. When the number of data units in the input FIFO
is 8, writing to SRCID has no effect.
For stereo data, bits [31:16] are for Lch data, and bits [15:0] are for Rch data. For monaural data, data in bits [31:16] is
valid, and data in bits [15:0] is invalid.
The data subject to sampling rate conversion is aligned differently depending on the IED setting in SRCIDCTRL. Table
40.2 shows the correspondence between the IED setting and data alignment.
Table 40.2
Data alignment before sampling rate conversion
IED
Lch[15:8]
Lch[7:0]
Rch[15:8]
Rch[7:0]
0
SRCID[31:24]
SRCID[23:16]
SRCID[15:8]
SRCID[7:0]
1
SRCID[23:16]
SRCID[31:24]
SRCID[7:0]
SRCID[15:8]
40.2.2
Output Data Register (SRCOD)
Address(es): SRC.SRCOD 4004 DFF4h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The SRCOD register is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the
16-stage output FIFO is read through SRCOD. When the output FIFO is empty after the start of conversion, the value
previously read is read again.
The data in SRCOD is aligned differently depending on the OCH and OED settings in SRCODCTRL. Table 40.3 shows
the correspondence between the OCH and OED settings and data alignment in SRCOD.
Table 40.3
OCH
0
Data alignment in SRCOD (1 of 2)
OED
SRCOD[31:24]
SRCOD[23:16]
SRCOD[15:8]
SRCOD[7:0]
Rch[7:0]*1
Rch[15:8]*1
0
Lch[15:8]
Lch[7:0]
Rch[15:8]*1
1
Lch[7:0]
Lch[15:8]
Rch[7:0]*1
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Table 40.3
40. Sampling Rate Converter (SRC)
Data alignment in SRCOD (2 of 2)
OCH
OED
SRCOD[31:24]
SRCOD[23:16]
SRCOD[15:8]
SRCOD[7:0]
1*2
0
Rch[15:8]
Rch[7:0]
Lch[15:8]
Lch[7:0]
1
Rch[7:0]
Rch[15:8]
Lch[7:0]
Lch[15:8]
Note 1.
Note 2.
When processing monaural data, the data in these bits is invalid. Discard the invalid data after reading from SRCOD in 32-bit
units.
When processing monaural data, the data in these bits is invalid.
40.2.3
Input Data Control Register (SRCIDCTRL)
Address(es): SRC.SRCIDCTRL 4004 DFF8h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
—
IED
IEN
—
—
—
—
—
—
IFTRG[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
0
Bit
Symbol
Bit name
b1, b0
IFTRG[1:0]
Input FIFO Data Triggering Number
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
IEN
Input FIFO Empty Interrupt Enable
0: Disable input FIFO empty interrupts
1: Enable input FIFO empty interrupts.
R/W
b9
IED
Input Data Endian *1
0: Little endian
1: Big endian.
R/W
b15 to b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Description
b0
R/W
R/W
b1 b0
0
0
1
1
0: 0
1: 2
0: 4
1: 6.
Only rewrite this bit while the SRCCTRL.SRCEN bit is 0.
The SRCIDCTRL register is a 16-bit read/write register that specifies the endian format of input data, enables or disables
the interrupt requests, and specifies the triggering number of data units.
IFTRG[1:0] bits (Input FIFO Data Triggering Number)
The IFTRG[1:0] bits specify the data unit count at which the IINT flag in the Status Register (SRCSTAT) is set to 1.
When the number of data units stored in the input FIFO is equal to or less than the specified triggering number, the IINT
flag is set to 1.
IEN bit (Input FIFO Empty Interrupt Enable)
The IEN bit enables or disables the issuing of the input FIFO empty interrupt request when the number of data units in
the input FIFO is equal to or less than the triggering number specified in the IFTRG[1:0] bits, resulting in the IINT flag
in the Status Register (SRCSTAT) setting to 1.
IED bit (Input Data Endian)
The IED bit specifies the endian format of the input data.
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40.2.4
40. Sampling Rate Converter (SRC)
Output Data Control Register (SRCODCTRL)
Address(es): SRC.SRCODCTRL 4004 DFFAh
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
OCH
OED
OEN
—
—
—
—
—
—
OFTRG[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
0
0
Bit
Symbol
Bit name
b1, b0
OFTRG[1:0]
Output FIFO Data Trigger
Number
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
OEN
Output FIFO Full Interrupt
Enable
0: Disable output FIFO full interrupts
1: Enable output FIFO full interrupts.
R/W
b9
OED
Output Data Endian
0: Little endian
1: Big endian.
R/W
b10
OCH
Output Data Channel Exchange
*1
0: Do not exchange channels (use same order as data input)
1: Exchange channels (use opposite order from data input).
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Description
b0
R/W
R/W
b1 b0
0
0
1
1
0: 1
1: 4
0: 8
1: 12.
Only rewrite this bit while the SRCCTRL.SRCEN bit is 0.
The SRCODCTRL register is a 16-bit read/write register that specifies whether to exchange the channels for the output
data, specifies the endian format of output data, enables or disables the interrupt requests, and specifies the triggering
number of data units.
OFTRG[1:0] bits (Output FIFO Data Trigger Number)
The OFTRG[1:0] bits specify the data unit count at which the OINT flag in the Status Register (SRCSTAT) is set to 1.
When the number of data units in the output FIFO becomes equal to or greater than the specified triggering number, the
OINT flag is set to 1.
OEN bit (Output FIFO Full Interrupt Enable)
The OEN bit enables or disables issuing of the output FIFO full interrupt request when the number of data units in the
output FIFO becomes equal to or greater than the number specified in the OFTRG[1:0] bits, resulting in the OINT flag in
the Status Register (SRCSTAT) setting to 1.
OED bit (Output Data Endian)
The OED bit specifies the endian format of the output data.
OCH bit (Output Data Channel Exchange)
The OCH bit specifies whether to exchange the channels for the Output Data Register (SRCOD). Do not set this bit to 1
when processing monaural data.
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40.2.5
40. Sampling Rate Converter (SRC)
Control Register (SRCCTRL)
Address(es): SRC.SRCCTRL 4004 DFFCh
b15
b14
FICRA
E
—
0
0
Value after reset:
b13
b12
b11
CEEN SRCEN UDEN
0
0
b10
b9
b8
OVEN
FL
CL
0
0
0
0
b7
b6
b5
b4
IFS[3:0]
0
0
0
b3
b2
—
0
0
b1
b0
OFS[2:0]
0
0
Bit
Symbol
Bit name
b2 to b0
OFS[2:0]
Output Sampling Rate
b3
—
Reserved
b7 to b4
IFS[3:0]
Input Sampling Rate
b8
CL
Internal Work Memory Clear
Writing 1 to this bit clears the input FIFO, output FIFO, input
buffer memory, intermediate memory, and accumulator
R/W
b9
FL
Internal Work Memory Flush
Writing 1 to this bit starts conversion of the sampling rate for all
data in the input FIFO, input buffer memory, and intermediate
memory (flush processing)
R/W
b10
OVEN
Output FIFO Overflow Interrupt
Enable
0: Disable output FIFO overflow interrupts
1: Enable output FIFO overflow interrupts.
R/W
b11
UDEN
Output FIFO Underflow Interrupt
Enable
0: Disable output FIFO underflow interrupts
1: Enable output FIFO underflow interrupts.
R/W
b12
SRCEN
Module Enable
0: Disable SRC module operation
1: Enable SRC module operation.*2
R/W
b13
CEEN
Conversion End Interrupt
Enable
0: Disable conversion end interrupts
1: Enable conversion end interrupts.
R/W
b14
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b15
FICRAE
Filter Coefficient Table Access
Enable
0: Disable reads to and writes from filter coefficient table RAM
1: Enable reads to and writes from filter coefficient table RAM.
R/W
Note 1.
Note 2.
Description
0
b2
R/W
R/W
b0
0 0 0: 44.1 kHz
0 0 1: 48.0 kHz
0 1 0: 32.0 kHz
0 1 1: Setting prohibited
1 0 0: 8.0 kHz*1
1 0 1: 16.0 kHz.*1
Other settings are prohibited.
This bit is read as 0. The write value should be 0.
b7
R/W
R/W
b4
0 0 0 0: 8.0 kHz
0 0 0 1: 11.025 kHz
0 0 1 0: 12.0 kHz
0 0 1 1: Setting prohibited
0 1 0 0: 16.0 kHz
0 1 0 1: 22.05 kHz
0 1 1 0: 24.0 kHz
0 1 1 1: Setting prohibited
1 0 0 0: 32.0 kHz
1 0 0 1: 44.1 kHz
1 0 1 0: 48.0 kHz.
Other settings are prohibited.
Only valid when the IFS[3:0] bits are 1001b.
When SRCEN = 1, do not change the settings of the following bits:
IED bit in SRCIDCTRL, OED and OCH bits in SRCODCTRL, OFS[2:0], IFS[3:0], and FICRAE bits in SRCCTRL.
The SRCCTRL register is a 16-bit read/write register that enables or disables access to the Filter Coefficient Table,
module operations, and interrupt requests, and specifies flush processing, clear processing of the internal work memory,
and the input and output sampling rates.
OFS[2:0] bits (Output Sampling Rate)
The OFS[2:0] bits specify the output sampling rate.
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40. Sampling Rate Converter (SRC)
IFS[3:0] bits (Input Sampling Rate)
The IFS[3:0] bits specify the input sampling rate.
CL bit (Internal Work Memory Clear)
Writing 1 to the CL bit clears the input FIFO, output FIFO, input buffer memory, intermediate buffer memory, and
accumulator, and then clears the CL bit to 0. This bit is read as 0. Even if SRCEN is 0, writing 1 to this bit clears the
processing.
FL bit (Internal Work Memory Flush)
Writing 1 to the FL bit initiates flush processing by starting the conversion of the sampling rate of all the data in the input
FIFO, input buffer memory, and intermediate memory. This bit is read as 0. When SRCEN is 0, writing 1 to this bit does
not trigger flush processing.
In addition, when 1 is written to the FL bit while the number of data units in the input buffer memory is less than the
values shown in Table 40.6, valid output data cannot be received. The internal work memory is cleared without
triggering the flush processing.
OVEN bit (Output FIFO Overflow Interrupt Enable)
The OVEN bit enables or disables the issuing of the output FIFO overflow interrupt request when the OVF flag in the
Status Register (SRCSTAT) is set to 1.
When OVEN = 1, conversion processing stops until the OVF flag is cleared by the CPU accessing SRCSTAT when the
output FIFO overflow interrupt is generated. Writing of conversion results to the output FIFO also stops.
When OVEN = 0, the OVF flag automatically clears when the output FIFO has space, and conversion processing can be
continued.
UDEN bit (Output FIFO Underflow Interrupt Enable)
The UDEN bit enables or disables the issuing of the output FIFO underflow interrupt request when the output FIFO is
read and the UDF flag in the Status Register (SRCSTAT) is set to 1 while the number of data units in the output FIFO is
zero.
SRCEN bit (Module Enable)
The SRCEN bit enables or disables SRC operation. Writing 1 to these bits while SRCEN is 0 clears the internal work
memory.
CEEN bit (Conversion End Interrupt Enable)
The CEEN bit enables or disables issuing of a conversion end interrupt request when the CEF flag in the Status Register
(SRCSTAT) is set to 1 after flush processing is complete and all the output data is read.
FICRAE bit (Filter Coefficient Table Access Enable)
The FICRAE bit enables or disables access to the filter coefficient table RAM. After flush processing is complete, the
number of output data units obtained as a result of the conversion can be calculated using the following formulas:
Number of output data units − 1
Output sampling rate
Number of output data units =
=
Number of input data units × n − 1
Input sampling rate × n
(Number of input data units × n − 1) ×
Output sampling rate
Input sampling rate × n
+1
The value of n can be obtained from Table 40.4. The number of input data units must be equal to or greater than the
values in Table 40.5.
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Table 40.4
40. Sampling Rate Converter (SRC)
Sampling rate settings and value of n
OFS[2:0] setting
(output sampling rate
[kHz])
IFS[3:0] setting (input sampling rate [kHz])
0000b
(8.0)
0001b
(11.025)
0010b
(12.0)
0100b
(16.0)
0101b
(22.05)
0110b
(24.0)
1000b
(32.0)
1001b
(44.1)
1010b
(48.0)
000b (44.1)
6
4
4
3
2
2
3
—
1
001b (48.0)
6
4
4
3
2
2
3
1
—
010b (32.0)
4
8
4
2
4
2
—
2
1
100b (8.0)
—
—
—
—
—
—
—
1
—
101b (16.0)
—
—
—
—
—
—
—
1
—
Conversion processing does not start, and so output data is not obtained until the specified number of data units are input.
The minimum number of input data units necessary for obtaining the first output data depends on the IFS and OFS bit
settings. Table 40.5 shows the relation between the settings in the IFS and OFS bits and the number of initial input data
required. Table 40.6 shows the relation between the settings in the IFS and OFS bits and the number of initial input data
required for processing.
Table 40.5
Relation between sampling rate settings and number of initial input data units required
OFS[2:0] setting
(output sampling rate
[kHz])
IFS[3:0] setting (input sampling rate [kHz])
0000b
(8.0)
0001b
(11.025)
0010b
(12.0)
0100b
(16.0)
0101b
(22.05)
0110b
(24.0)
1000b
(32.0)
1001b
(44.1)
1010b
(48.0)
000b (44.1)
38
40
40
43
48
48
43
—
63
001b (48.0)
38
40
40
43
48
48
43
32
—
010b (32.0)
40
37
40
48
40
48
—
48
63
100b (8.0)
—
—
—
—
—
—
—
63
—
101b (16.0)
—
—
—
—
—
—
—
63
—
Table 40.6
Relation between sampling rate settings and number of input data units required for flush
processing
OFS[2:0] setting
(output sampling rate
[kHz])
IFS[3:0] setting (input sampling rate [kHz])
0000b
(8.0)
0001b
(11.025)
0010b
(12.0)
0100b
(16.0)
0101b
(22.05)
0110b
(24.0)
1000b
(32.0)
1001b
(44.1)
000b (44.1)
27
24
24
22
16
16
22
—
1
001b (48.0)
27
24
24
22
16
16
22
32
—
010b (32.0)
24
29
24
16
24
16
—
16
1
100b (8.0)
—
—
—
—
—
—
—
1
—
101b (16.0)
—
—
—
—
—
—
—
1
—
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40.2.6
40. Sampling Rate Converter (SRC)
Status Register (SRCSTAT)
Address(es): SRC.SRCSTAT 4004 DFFEh
b15
b14
b13
b12
b11
b10
OFDN[4:0]
0
Value after reset:
0
0
b9
b8
b7
IFDN[3:0]
0
0
0
0
0
0
b6
b5
b4
b3
b2
b1
b0
—
CEF
FLF
UDF
OVF
IINT
OINT
0
0
0
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
OINT
Output FIFO Full Interrupt
Request Flag
0: Number of data units in output FIFO has not become equal to
or greater than specified triggering number
1: Number of data units in output FIFO has become equal to or
greater than specified triggering number.
R/(W)
*1
b1
IINT
Input FIFO Empty Interrupt
Request Flag
0: Number of data units in input FIFO has not become equal to
or smaller than specified triggering number
1: Number of data units in input FIFO has become equal to or
smaller than specified triggering number.
R/(W)
*1
b2
OVF
Output FIFO Overflow Interrupt
Request Flag
0: No output FIFO overflow occurred
1: Output FIFO overflow occurred.
R/(W)
*1
b3
UDF
Output FIFO Underflow Interrupt
Request Flag
0: No output FIFO underflow occurred
1: Output FIFO underflow occurred.
R/(W)
*1
b4
FLF
Flush Processing Status Flag
0: Flush processing complete
1: Flush processing in progress.
R
b5
CEF
Conversion End Flag
0: Not all output data read
1: All output data read.
R/(W)
*1
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10 to b7
IFDN[3:0]
Input FIFO Data Count
Indicates the number of data units in the input FIFO.
R
b15 to b11
OFDN[4:0]
Output FIFO Data Count
Indicates the number of data units in the output FIFO.
R
Note 1.
Only 0 can be written after having read as 1.
The SRCSTAT register is a 16-bit read/write register that indicates the number of data units in the input and output
FIFOs, whether the various interrupt sources were generated, and the flush processing status.
OINT flag (Output FIFO Full Interrupt Request Flag)
The OINT flag indicates that the number of data units in the output FIFO has become equal to or greater than the
triggering number specified in the OFTRG[1:0] bits in the Output Data Control Register (SRCODCTRL).
[Setting condition]
When the number of data units in the output FIFO becomes equal to or greater than the specified triggering number.
[Clearing conditions]
Writing 0 to the OINT flag after reading it as 1
When the last DMA transfer is executed
Writing 1 to the SRCCTRL.CL bit
Writing 1 to the SRCCTRL.SRCEN bit while it is 0.
IINT flag (Input FIFO Empty Interrupt Request Flag)
The IINT flag indicates that the number of data units in the input FIFO has become equal to or smaller than the triggering
number specified in the IFTRG[1:0] bits in the Input Data Control Register (SRCIDCTRL).
[Setting conditions]
When the number of data units in the input FIFO becomes equal to or smaller than the specified triggering number
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40. Sampling Rate Converter (SRC)
Writing 1 to the SRCCTRL.CL bit
Writing 1 to the SRCCTRL.SRCEN bit while it is 0.
[Clearing conditions]
Writing 0 to the IINT flag after reading is as 1
When the last DMA transfer is executed.
OVF flag (Output FIFO Overflow Interrupt Request Flag)
The OVF flag indicates that the sampling rate conversion for the next data completes when the output FIFO is full. The
conversion stops until the OVF flag is cleared.
[Setting condition]
When the sampling rate conversion for the next data completes when the output FIFO is full.
[Clearing conditions]
Writing 0 to the OVF flag after reading it as 1 while the SRCCTRL.OVEN bit is 1
When the number of data units in the output FIFO decreases after reading SRCOD while the SRCCTRL.OVEN bit
is 0
Writing 1 to the SRCCTRL.CL bit
Writing 1 to the SRCCTRL.SRCEN bit while it is 0.
UDF flag (Output FIFO Underflow Interrupt Request Flag)
The UDF flag indicates that the output FIFO is read when the number of data units in the output FIFO is zero.
[Setting condition]
When the output FIFO is read while the number of data units in the output FIFO is zero.
[Clearing conditions]
Writing 0 to the UDF flag after reading it as 1
Writing 1 to the SRCCTRL.CL bit
Writing 1 to the SRCCTRL.SRCEN bit while it is 0.
FLF flag (Flush Processing Status Flag)
The FLF flag indicates whether flush processing is in progress or not.
[Setting condition]
Writing 1 to the SRCCTRL.FL bit.
When flush processing is not in progress, however, FLF does not set to 1.
[Clearing conditions]
When flush processing completes
Writing 1 to the SRCCTRL.CL bit
Writing 1 to the SRCCTRL.SRCEN bit while it is 0.
CEF flag (Conversion End Flag)
The CEF flag indicates that all the output data is read after flush processing completes.
[Setting condition]
When the number of data units in the output FIFO is zero on completion of flush processing.
[Clearing conditions]
Writing 0 to the CEF flag after reading it as 1.
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40. Sampling Rate Converter (SRC)
Writing 1 to the SRCCTRL.CL bit
Writing 1 to the SRCCTRL.SRCEN bit while it is 0.
IFDN[3:0] bits (Input FIFO Data Count)
The IFDN[3:0] bits indicate the number of data units in the input FIFO.
OFDN[4:0] bits (Output FIFO Data Count)
The OFDN[4:0] bits indicate the number of data units in the output FIFO.
40.2.7
Filter Coefficient Table n (SRCFCTRn) (n = 0 to 5551)
Address(es): SRCRAM.SRCFCTR0 to 5551 4004 8000h to 4004 D6BFh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
x
x
x
Value after reset:
b21
b20
b19
b18
b17
b16
x
x
x
b3
b2
b1
b0
x
x
x
x
SRCFCOE[21:16]
SRCFCOE[15:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b21 to b0
SRCFCOE[21:0]
Filter Coefficient Table
Stores the filter coefficient value.
R/W
b31 to b22
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
SRCFCTR0 to SRCFCTR5551 are 32-bit read/write SRAM modules that store the filter coefficients to be used for
sampling rate conversion. This SRAM can be read from and written to through the peripheral bus only when the
FICRAE bit is 1 and the SRCEN bit is 0 in SRCCTRL. Bits [31:22] are reserved and are read as 0, and their write values
should be 0. Bits [21:0] are used for storage of the filter coefficient values, whose initial values are undefined.
40.3
40.3.1
Operation
Initial Settings
Figure 40.2 shows an example flow for the initial settings. After the module-stop state is released, the filter coefficient
data stored in the flash and other areas must be transferred to the Filter Coefficient Table (SRCFCTR) before the SRC
conversion starts. When a filter coefficient value is already stored in the Filter Coefficient Table, skip this transfer and set
the required parameters to start the conversion.
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Start initial settings
Settings for transfer of coefficient data
(FICRAE = 1, SRCEN = 0)
40. Sampling Rate Converter (SRC)
Register
Bit
SRCCTRL
FICRAE
Filter Coefficient Table access enable
SRCEN
Module enable
Register
Bit
Parameters to be set
SRCCTRL
CEEN
Enabling/disabling of the SRC_CEFI
interrupt
UDEN
Enabling/disabling of the SRC_UDFI
interrupt
OVEN
Enabling/disabling of the SRC_OVFI
interrupt
IFS[3:0]
Input sampling rate
OFS[2:0]
Output sampling rate
IED
Input data endianness
IEN
Enabling/disabling of the SRC_IDEI
interrupt
IFTRG[1:0]
Input FIFO triggering number
Transfer of coefficient data
(transfer from flash to SRCFCTR)
Parameter settings
(FICRAE = 0, SRCEN = 0)
Transfer operation enabled
(SRCEN = 1)
SRCIDCTRL
Initial settings complete
SRCODCTRL
Figure 40.2
40.3.2
Parameters to be set
OCH
Exchanging of output data channels
OED
Output data endianness
OEN
Enabling/disabling of the SRC_ODFI
interrupt
OFTRG[1:0]
Output FIFO triggering number
Example flow for initial settings
Data Input
Figure 40.3 shows an example flow for data input.
Start data input
Read the IINT flag in SRCSTAT
IINT = 1?
No
Yes
Write the data to be converted to
SRCID and clear the IINT flag
in SRCSTAT
Has all the data
been input?
No
Yes
Set the FL bit in SRCCTRL to 1
(flush processing is started)
Data input complete
Figure 40.3
Data input flow
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(1)
40. Sampling Rate Converter (SRC)
When issuing interrupts to the CPU
1. Set the IEN bit in SRCIDCTRL to 1.
2. When the IINT flag in SRCSTAT is set to 1, the IDEI interrupt request is issued. In the interrupt processing routine,
read the IINT flag and confirm that it is 1, write data to SRCID, and write 0 to the IINT flag. Then return from the
interrupt processing routine.
3. Repeat step 2 until all the data is input, and write 1 to the FL bit in SRCCTRL.
(2)
When using interrupts to activate the DMAC
1. Assign the SRC_IDEI interrupt of the SRC to one channel of the DMAC.
2. Set the IEN bit in SRCIDCTRL to 1.
3. When the IINT flag in SRCSTAT is set to 1, the SRC_IDEI interrupt request is issued, activating the DMAC. When
data is written to the SRCID register using DMA transfer, and when the number of data units in the input FIFO
exceeds the triggering number specified in the IFTRG[1:0] bits in SRCIDCTRL, the IINT flag in SRCSTAT clears
to 0.
4. Repeat step 3 until all the data is input, and write 1 to the FL bit in SRCCTRL.
(3)
When using SSIE interface interrupts to activate the DMAC to transfer input data from the
SSIE interface
1. Assign the SSIE interface to one channel of the DMAC as a DMA transfer request source. Set SSIFRDR of the
SSIE interface as a transfer source and SRCID of the SRC as a transfer destination, and set the SSIE interface to
enable reception operation.
2. When the RDF bit in SSIFSR is set to 1, the SSIE interface issues an interrupt request, activating the DMAC. The
DMAC then reads data from SSIFRDR and writes the data to SRCID.
3. Repeat step 2 until all the data is input, and write 1 to the FL bit in SRCCTRL.
Note:
The input FIFO has eight stages. The number of data units that can be transferred (the empty space in the FIFO)
when an SRC_IDEI interrupt request is issued depends on the settings in the IFTRG[1:0] bits in SRCIDCTRL.
Because the input FIFO is not equipped with a function to prevent or detect overflow, the transferred data is
destroyed when overflow occurs. To prevent this, take the settings in the IFTRG[1:0] bits in SRCCTRL into
consideration when setting the number of data units to be continuously transferred by the DMA.
40.3.3
Data Output
Figure 40.4 shows an example flow for data output.
Start data output
Read the OINT flag in SRCSTAT
OINT = 1?
No
Yes
Read the converted data
from SRCOD and clear the OINT flag
in SRCSTAT
Flush processing
started?
No
Yes
Read the CEF flag in SRCSTAT
CEF = 1?
No
Yes
Data output completed
Figure 40.4
Data output flow
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(1)
40. Sampling Rate Converter (SRC)
When issuing interrupts to the CPU
1. Set the OEN bit in SRCODCTRL to 1.
2. When the OINT flag in SRCSTAT is set to 1, the SRC_ODFI interrupt request is issued. In the interrupt processing
routine, read the OINT flag and confirm that it is 1, read data from SRCOD, and write 0 to the OINT flag. Then,
return from the interrupt processing routine.
3. After flush processing starts, repeat step 2 until the CEF flag in SRCSTAT is read as 1.
(2)
When using interrupts to activate the DMAC
1. Assign the SRC_ODFI interrupt of the SRC to one channel of the DMAC.
2. Set the OEN bit in SRCODCTRL to 1.
3. When the OINT flag in SRCSTAT is set to 1, the SRC_ODFI interrupt request is issued, activating the DMAC.
When data is read from SRCOD using DMA transfer, and when the number of data units in the output data FIFO
becomes equal to or less than the triggering number specified in the OFTRG[1:0] bits, the OINT flag in SRCSTAT
clears to 0.
4. After flush processing starts, repeat step 3 until the FLF flag in SRCSTAT is read as 0.
(3)
When using SSIE interface interrupts to activate the DMAC to transfer output data to the SSIE
interface
1. Set the OVEN bit in SRCCTRL to 0 to disable SRC_OVFI interrupt request generation.
2. Assign the SSIE interface to one channel of the DMAC as a DMA transfer request source. Set SRCID of the SRC as
a transfer source and SSIFTDR of the SSIE interface as a transfer destination, and set the SSIE interface to enable
transmission operation.
3. When the TDE bit in SSIFSR is set to 1, the SSIE interface issues an interrupt request, activating the DMAC. The
DMAC then reads data from SRCOD and writes the data to SSIFTDR.
4. After the flush processing starts, repeat step 3 until the CEF flag in SRCSTAT is read as 1.
Note 1. The output FIFO has 16 stages. The conversion stops when no data is read and an overflow occurs in the output
FIFO. Even in an overflow state, data can be read from the output FIFO, but the procedure to restart conversion
might be required depending on the settings. For details, see the OVEN bit in SRCCTRL.
Note 2. When the number of data units in the output FIFO is zero, incorrect data is read. To prevent this, take the settings
of the OFTRG[1:0] bits into consideration when setting the number of data units to be continuously transferred by
the DMAC.
40.4
Interrupts
The SRC interrupt sources include:
Input FIFO empty (SRC_IDEI)
Output FIFO full (SRC_ODFI)
Output FIFO overflow (SRC_OVFI)
Output FIFO underflow (SRC_UDFI)
Conversion end (SRC_CEFI).
Table 40.7 lists the interrupt request types and generation conditions.
Table 40.7
Interrupt requests and generation conditions (1 of 2)
Interrupt request
Abbreviation Interrupt condition
DMAC activation
Input FIFO empty
SRC_IDEI
IINT = 1, IEN = 1, and SRCEN = 1
Possible
Output FIFO full
SRC_ODFI
OINT = 1, OEN = 1, and SRCEN = 1
Possible
Output FIFO overflow
SRC_OVFI
OVF = 1, OVEN = 1, and SRCEN = 1
Not possible
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Table 40.7
40. Sampling Rate Converter (SRC)
Interrupt requests and generation conditions (2 of 2)
Interrupt request
Abbreviation Interrupt condition
DMAC activation
Output FIFO underflow
SRC_UDFI
UDF = 1, UDEN = 1, and SRCEN = 1
Not possible
Conversion end
SRC_CEFI
CEF = 1, CEEN = 1, and SRCEN = 1
Not possible
When an interrupt condition is satisfied, the CPU executes the interrupt exception handling routine. Clear the interrupt
source flags during this routine.
The SRC_IDEI and SRC_ODFI interrupts can activate the DMAC. If the DMAC is activated, the interrupts from the
SRC are not sent to the CPU.
Do not clear the IINT and OINT flags through a write by the CPU (writing 0 after reading 1) during the DMA transfer.
40.5
40.5.1
Usage Notes
Notes on Accessing Registers
The following writes to SRCCTRL require 3 cycles of the peripheral clock (PCLKB) for the values to be updated in
SRCSTAT:
Writes of 1 to the FL bit in SRCCTRL, for the FLF flag in SRCSTAT to set
Writes of 1 to the CL bit in SRCCTRL, for each bit in SRCSTAT to initialize
Writes of 1 to the SRCEN bit in SRCCTRL while the SRCEN bit is 0, for each bit in SRCSTAT to initialized.
However, because the CPU executes any subsequent instruction without waiting for the completion of writes to a
register, the updated state of SRCSTAT cannot be correctly read by an instruction immediately after the write instruction
to SRCCTRL. To check the updated state of SRCSTAT, perform a dummy read of SRCCTRL or SRCSTAT after the
instruction used to write to SRCCTRL.
40.5.2
Notes on Flush Processing
When 1 is written to the FL bit in the SRC Control Register (SRCCTRL), the SRC continues conversion processing by
adding 0-data to the input data endpoint. Because of this, only execute flush processing when the audio data endpoint is
input and there is no subsequent data.
To perform conversion again after flush processing, clear the internal work memory in either of the following ways.
Write 1 to the CL bit in SRCCTRL
Write 0 and then 1 to the SRCEN bit in SRCCTRL.
40.5.3
Notes on DMAC or DTC Transfer
When the DMAC or DTC is used for data transfer to the I/O data registers (SRCID and SRCOD), do not clear the IINT
and OINT flags in the Status Register (SRCSTAT) through the CPU (writing 0 after reading 1) during transfer by the
DMAC or DTC.
40.5.4
Notes on SRC Operation
Do not access the Filter Coefficient Table while the SRC is operating (SRCCTRL.SRCEN = 1).
40.5.5
Settings for the Module-Stop Function
SRC operation can be disabled or enabled using Module Stop Control Register C (MSTPCRC). The SRC module is
initially stopped after reset. Releasing the module-stop state enables access to the registers. For details, see section 11,
Low Power Modes.
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41. SD/MMC Host Interface (SDHI)
41.
SD/MMC Host Interface (SDHI)
41.1
Overview
The Secure Digital Host Interface (SDHI) and MultiMediaCard (MMC) Interface provide the functionality required to
connect a variety of external memory cards with the MCU. The SDHI supports both 1-bit and 4-bit buses for connecting
different memory cards that support SD, SDHC, and SDXC formats. When developing host devices that are compliant
with the SD Specifications, you must comply with the SD Host/Ancillary Product License Agreement (SD HALA).
The MMC interface supports 1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84B451) device access. This interface also provides backward compatibility and support for high-speed SDR transfer
modes.
Table 41.1 lists the SD/MMC Host Interface specifications and Figure 41.1 shows a block diagram.
Table 41.1
SD/MMC Host Interface specifications
Interface
Parameter
Specifications
SD
SD bus interface
Compatible with SD memory card and SDIO card
Transfer bus mode selectable from 4-bit wide bus mode or 1-bit default bus
mode
Compatible with SD, SDHC, and SDXC formats.
SD and MMC shared
SDHI clock frequency
The SDHI clock is generated by dividing PCLKA by 2n (n = 1 to 9)
Error check functions
CRC7 (command/response), CRC16 (transfer data)
Interrupt sources
Card access interrupt (SDHI_MMCn_ACCS), SDIO access interrupt
(SDHI_MMCn_SDIO), Card detection interrupt (SDHI_MMCn_CARD)
(n = 0 to 1)
DMA transfer sources
DMAC and DTC triggerable by the SBFAI interrupt
SD buffer is read and write accessible using the DMAC
Other functions
Card detect function
Write protect support.
Transfer bus mode selectable from 1-bit, 4-bit, or 8-bit
Backward compatible mode or high-speed SDR mode selectable
Other functions
e.MMC device access supported
DMA Interface
Interrupt Request
RST
CLK
Host interface
Module Clock
(PCLKA)
SD/MMC interface
MMC bus interface
Transfer modes
Internal peripheral bus
MMC
SD/MMC
interface
SD
Card
/MMC
SD buffer
(512 bytes × 2)
Figure 41.1
SD/MMC Host Interface block diagram
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Table 41.2
41. SD/MMC Host Interface (SDHI)
SDHI I/O pins
Channel
Pin name
I/O
Description
Ch 0
SD0CLK
Output
SDHI clock
Ch 1
SD0CMD
I/O
Command output, response input
SD0DAT0
I/O
Data 0 (DAT0)
SD0DAT1
I/O
Data 1 (DAT1), SDIO interrupt
SD0DAT2
I/O
Data 2 (DAT2), SDIO Read wait
SD0DAT3
I/O
Data 3 (DAT3), SD Card detect
SD0DAT4
I/O
MMC Data 4 (DAT4)
SD0DAT5
I/O
MMC Data 5 (DAT5)
SD0DAT6
I/O
MMC Data 6 (DAT6)
SD0DAT7
I/O
MMC Data 7 (DAT7)
SD0CD
Input
SD card detection
SD0WP
Input
SD card write protection
SD1CLK
Output
SDHI clock
SD1CMD
I/O
Command output, response input
SD1DAT0
I/O
Data 0 (DAT0)
SD1DAT1
I/O
Data 1 (DAT1), SDIO interrupt
SD1DAT2
I/O
Data 2 (DAT2), SDIO Read wait
SD1DAT3
I/O
Data 3 (DAT3), SD Card detect
SD1DAT4
I/O
MMC Data 4 (DAT4)
SD1DAT5
I/O
MMC Data 5 (DAT5)
SD1DAT6
I/O
MMC Data 6 (DAT6)
SD1DAT7
I/O
MMC Data 7 (DAT7)
SD1CD
Input
SD card detection
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41.2
41. SD/MMC Host Interface (SDHI)
Register Descriptions
41.2.1
Command Type Register (SD_CMD)
Address(es): SDHI0.SD_CMD 4006 2000h, SDHI1.SD_CMD 4006 2400h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
Value after reset:
CMD12AT[1:0] TRSTP CMDR CMDTP
W
0
Value after reset:
0
0
0
0
RSPTP[2:0]
0
0
ACMD[1:0]
0
0
0
CMDIDX[5:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
CMDIDX[5:0]
Command Index Field
Value Select
These bits configure the command index field value. The examples
shown include the bit values for the ACMD[1:0] bits.
R/W
b7
b0
0 0 0 0 0 1 1 0: CMD6
0 0 0 1 0 0 1 0: CMD18
0 1 0 0 1 1 0 1: ACMD13.
b7, b6
ACMD[1:0]
Command Type Select
b7 b6
b10 to b8
RSPTP[2:0]
Response Type Select*1
b10
b11
CMDTP
Data Transfer Select*2
0: Do not include data transfer (bc, bcr, or ac) in command
1: Include data transfer (adtc) in command.
R/W
b12
CMDRW
Data Transfer Direction
Select*3
0: Write (SD/MMC Host Interface → SD card/MMC)
1: Read (SD/MMC Host Interface ← SD card/MMC).
R/W
b13
TRSTP
Block Transfer Select*3
0: Single block transfer
1: Multiple blocks transfer.
R/W
b15, b14
CMD12AT[1:0]
CMD12 Automatic Issue
Select*4
b15 b14
R/W
b31 to b16
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
R/W
0 0: CMD
0 1: ACMD.
Other settings are prohibited.
b8
0 0 0: Normal mode
Depending on the command, the response type and
transfer method are selected in the ACMD[1:0] and
CMDIDX[5:0] bits. At this time, the values for b15 to b11
in this register are invalid.
0 1 1: Extended mode and no response
1 0 0: Extended mode and R1, R5, R6, or R7 response
1 0 1: Extended mode and R1b response
1 1 0: Extended mode and R2 response
1 1 1: Extended mode and R3 or R4 response.
Other settings are prohibited.
0 0: Automatically issue CMD12 during multiblock transfer
0 1: Do not automatically issue CMD12 during multiblock
transfer.
Other settings are prohibited.
R/W
Some commands cannot be used in normal mode.
The CMDTP bit is only valid when the RSPTP[2:0] bits are 011b, 100b, 101b, 110b, or 111b.
Bits CMDRW and TRSTP are only valid when the RSPTP[2:0] bits are 011b, 100b, 101b, 110b, or 111b, and the CMDTP bit is
1.
The CMD12AT[1:0] bits are only valid when the RSPTP[2:0] bits are 011b, 100b, 101b, 110b, or 111b, and the TRSTP bit is 1.
The command type and response type are set in the SD_CMD register. The command type and transfer mode must be set
when the RSPTP[2:0] bits are 011b, 100b, 101b, 110b, or 111b. The sequence starts when a value is written to this
register. See Table 41.8 and Table 41.9 for setting examples. Do not write to the SD_CMD register when the
SD_INFO2.CBSY flag is 1.
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41.2.2
41. SD/MMC Host Interface (SDHI)
SD Command Argument Register (SD_ARG)
Address(es): SDHI0.SD_ARG 4006 2008h, SDHI1.SD_ARG 4006 2408h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
—
—
These bits specify command format[39:8] (argument)
R/W
The SD_ARG register is used for setting the argument field value. Set the SD_ARG register before setting the SD_CMD
register. The argument field value of the automatically issued CMD12 is 0000 0000h regardless of the SD_ARG register
value.
41.2.3
SD Command Argument Register 1 (SD_ARG1)
Address(es): SDHI0.SD_ARG1 4006 200Ch, SDHI1.SD_ARG1 4006 240Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
—
—
These bits specify command format[39:24] (argument)
R/W
b31 to b16
—
Reserved
These bits are read as 0
R
The SD_ARG1 register is used for setting the argument field value. Set the SD_ARG1 register before setting the
SD_CMD register. The argument field value of the automatically issued CMD12 is 0000 0000h regardless of the
SD_ARG1 register value.
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41.2.4
41. SD/MMC Host Interface (SDHI)
Data Stop Register (SD_STOP)
Address(es): SDHI0.SD_STOP 4006 2010h, SDHI1.SD_STOP 4006 2410h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
SEC
—
—
—
—
—
—
—
STP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
STP
Transfer Stop
Data transfer stops when this bit is set to 1
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
SEC
Block Count Register Value Select
*1
0: Disable SD_SECCNT register value
1: Enable SD_SECCNT register value.
R/W
b31 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Do not rewrite this bit when the SD_INFO2.CBSY flag is 1.
The SD_STOP register stops data transfer. During a multiblock transfer sequence, the SD_SECCNT register value
(number of blocks to be transferred) can be set to valid or invalid by setting the SD_STOP register.
STP bit (Transfer Stop)
When the STP bit is set to 1 during a multiple block transfer, CMD12 is issued to halt the transfer through the SDHI.
However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued.
Although continued buffer access is possible even after STP is set to 1, the buffer access error bit (ILR or ILW) in
SD_INFO2 is set accordingly.
When STP is set to 1 during the transfer for a single block write, the access end flag sets when SD_BUF becomes empty,
and CMD12 is not issued. If SD_BUF does contain data, the access end flag sets on completion of the reception of the
busy state without CMD12 being issued.
When STP is set to 1 during transfer for a single block read, the access end flag sets immediately after the STP bit is set,
and CMD12 is not issued.
When STP is set to 1 during reception of the busy state after an R1b response, the access end flag sets on completion of
reception of the busy state without CMD12 being issued.
When STP is set to 1 after a command sequence is complete, CMD12 is not issued and the access end flag does not set.
Set STP to 1 after the response end flag sets.
Set STP to 0 after the access end flag sets.
SEC bit (Block Count Register Value Select)
When SD_CMD is set in the following section to start the command sequence while the SEC bit is set to 1, CMD12 is
automatically issued to stop multiblock transfer with the number of blocks set in SD_SECCNT.
CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)
SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer)
When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically
issued.
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41.2.5
41. SD/MMC Host Interface (SDHI)
Block Count Register (SD_SECCNT)
Address(es): SDHI0.SD_SECCNT 4006 2014h, SDHI1.SD_SECCNT 4006 2414h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When performing a multiblock transfer, SD_SECCNT is a read/write register used to set the number of blocks to be
transferred. For example, when the register value is 0000 0001h, 1 block is transferred. When the register value is
0000 FFFFh, 65,535 blocks are transferred, and when the register value is FFFF FFFFh, 4,294,967,295 blocks are
transferred. Do not set this register to 0000 0000h. Do not rewrite the SD_SECCNT register when the SD_INFO2.CBSY
flag is 1.
41.2.6
SD Card Response Register 10 (SD_RSP10), SD Card Response Register 32
(SD_RSP32), SD Card Response Register 54 (SD_RSP54)
Address(es): SDHI0.SD_RSP10 4006 2018h, SDHI1.SD_RSP10 4006 2418h, SDHI0.SD_RSP32 4006 2020h, SDHI1.SD_RSP32 4006 2420h
SDHI0.SD_RSP54 4006 2028h, SDHI1.SD_RSP54 4006 2428h
Value after reset:
Value after reset:
41.2.7
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SD Card Response Register 1 (SD_RSP1), SD Card Response Register 3
(SD_RSP3), SD Card Response Register 5 (SD_RSP5)
Address(es): SDHI0.SD_RSP1 4006 201Ch, SDHI1.SD_RSP1 4006 241Ch, SDHI0.SD_RSP3 4006 2024h, SDHI1.SD_RSP3 4006 2424h,
SDHI0.SD_RSP5 4006 202Ch, SDHI1.SD_RSP5 4006 242Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
—
—
These bits store the response from the SD card/MMC
R
b31 to b16
—
Reserved
These bits are read as 0
R
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41.2.8
41. SD/MMC Host Interface (SDHI)
SD Card Response Register 76 (SD_RSP76)
Address(es): SDHI0.SD_RSP76 4006 2030h, SDHI1.SD_RSP76 4006 2430h
b31
b30
b29
b28
b27
b26
b25
b24
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
0
0
0
0
0
0
Value after reset:
Value after reset:
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b23 to b0
—
—
These bits store the response from the SD card/MMC
R
b31 to b24
—
Reserved
These bits are read as 0
R
41.2.9
SD Card Response Register 7 (SD_RSP7)
Address(es): SDHI0.SD_RSP7 4006 2034h, SDHI1.SD_RSP7 4006 2434h
Value after reset:
Value after reset:
Bit
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Symbol
Bit name
Description
R/W
b7 to b0
—
—
These bits store the response from the SD card/MMC
R
b31 to b8
—
Reserved
These bits are read as 0
R
SD_RSP10, SD_RSP32, SD_RSP54, SD_RSP1, SD_RSP3, SD_RSP5, SD_RSP76, and SD_RSP7 are read-only
registers that store the response from the SD card/MMC. Depending on the type of response from the SD card/MMC, the
SD/MMC Host Interface divides and stores the response among the four registers.
Table 41.3 lists the correspondence between the response type and its storage destination.
Table 41.3
Correspondence between response type and storage destination
Response
type
SD_RSP10
register
SD_RSP32
register
SD_RSP54
register
SD_RSP1
register
SD_RSP3
register
SD_RSP5
register
SD_RSP76
register
SD_RSP7
register
R1
[39:8]
—
[39:8]*1
—
—
—
—
—
—
—
—
—
—
R1b
[39:8]
—
[39:8]*1
R2
[39:8]
[71:40]
[103:72]
—
—
—
[127:104]
—
R3
[39:8]
—
—
—
—
—
—
—
R4
[39:8]
—
—
—
—
—
—
—
R5
[39:8]
—
—
—
—
—
—
—
R6
[39:8]
—
—
—
—
—
—
—
R7
[39:8]
—
—
—
—
—
—
—
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Note 1.
41. SD/MMC Host Interface (SDHI)
The responses for CMD18 and CMD25 are stored in registers SD_RSP10 and SD_RSP54. Therefore, even if the SD_RSP10
register is overwritten with the response for the automatically issued CMD12, the response for CMD18 or CMD25 can be
confirmed by reading the SD_RSP54 register.
41.2.10
SD Card Interrupt Flag Register 1 (SD_INFO1)
Address(es): SDHI0.SD_INFO1 4006 2038h, SDHI1.SD_INFO1 4006 2438h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
RSPEN
D
0
0
0
0
0
0
0*1
Value after reset:
Value after reset:
SDD3M SDD3I SDD3R SDWP
ON
N
M
MON
x
0
0
x
—
SDCD SDCDI SDCDR ACEND
MON
N
M
0
x
0
0
0*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RSPEND
Response End Detection Flag
0: Response end not detected
1: Response end detected.
R(/W)*2
b1
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2
ACEND
Access End Detection Flag
0: Access end not detected
1: Access end detected.
R(/W)*2
b3
SDCDRM
SDnCD Removal Flag
0: SD card/MMC removal not detected by the SDnCD pin
1: SD card/MMC removal detected by the SDnCD pin.
R(/W)*2
b4
SDCDIN
SDnCD Insertion Flag
0: SD card/MMC insertion not detected by the SDnCD pin
1: SD card/MMC insertion detected by the SDnCD pin.
R(/W)*2
b5
SDCDMON
SDnCD Pin Monitor Flag
0: SDnCD pin level is high*3
1: SDnCD pin level is low.*3
R
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
SDWPMON*4
SD0WP Pin Monitor Flag
0: SD0WP pin level is high
1: SD0WP pin level is low.
R
b8
SDD3RM
SDnDAT3 Removal Flag
0: SD card/MMC removal not detected by the SDnDAT3 pin
1: SD card/MMC removal detected by the SDnDAT3 pin.
R(/W)*2
b9
SDD3IN
SDnDAT3 Insertion Flag
0: SD card/MMC insertion not detected by the SDnDAT3 pin
1: SD card/MMC insertion detected by the SDnDAT3 pin.
R(/W)*2
b10
SDD3MON
SDnDAT3 Pin Monitor Flag
0: SDnDAT3 pin level is low
1: SDnDAT3 pin level is high.
R
b31 to b11
—
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Reserved
The value is initialized by a reset and also on a reset triggered by the SOFT_RST.SDRST flag.
The flag does not change even if set to 1. Writing 0 changes the flag value to 0.
The flag changes when the pin level continues for the period set in the SD_OPTION.CTOP[3:0] bits or longer.
The SDWPMON bit is supported only by SDHI0 (SD0WP). Bit [7] is reserved in SHDI1.
The SD_INFO1 register indicates the detection of a response end or access end for a command sequence. The
SD_INFO1 register also indicates the detection SD card/MMC insertion/removal and the write protection status.
During a multiblock transfer sequence, if CMD12 or CMD52 (SDIO abort) is issued, the ACEND flag is set to 1, but the
RSPEND flag remains set to 0.
If the command sequence is stopped because of a communication error or timeout, the ACEND flag or RSPEND flag is
set to 1.
After a reset is canceled, the SDD3MON bit, SDD3IN flag, and SDD3RM flag values are changed in accordance with
the status of the SDnDAT3 (n = 0, 1) pin, and their values are changed when data is being transferred in wide bus mode.
These 3 bits are used only for SD card. Set the flags to be cleared to 0. Set the flags that are not being cleared to 1.
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41. SD/MMC Host Interface (SDHI)
RSPEND flag (Response End Detection Flag)
The RSPEND flag indicates that a response end was detected.
[Setting conditions]
When reception of the response is complete
When transmission of a command without response is complete
When reception of the busy state after R1b response is complete
When reception of the response to CMD52 that was issued by setting the C52PUB bit to 1 is complete for the
transfer of multiple block read
When reception of the response to CMD52 that was issued by setting the C52PUB bit to 1 is complete for the
transfer of multiple block write
This bit is set when a command sequence is halted because of a communications error or timeout.
[Clearing conditions]
When 0 is written to RSPEND
When a command without data is issued.
Note:
When a command is issued in absence of data transfer, the RSPEND flag becomes 1 after the command
sequence ends.
ACEND flag (Access End Detection Flag)
The ACEND flag indicates that an access end was detected.
[Setting conditions]
When read access to the buffer is complete for the transfer of a single block read
When read access to the buffer for the last block of data is complete for the transfer of a multiple block read
When read access to the buffer and reception of the response to CMD12 are completed for the transfer of a multiple
block read with automatic issuing of CMD12
When reception of the busy state after a reception of the CRC status is complete for transfer of a single block write
When reception of the busy state after a reception of the CRC status of the last block of data is complete for the
transfer of a multiple block write
When reception of the response busy state for CMD12 is complete for the transfer of a multiple block write with
automatic issuing of CMD12
When reception of the response to CMD12 that was issued by setting the STP bit to1 is complete for transfer of a
multiple block read
When reception of the response busy state for CMD12 that was issued by setting the STP bit to 1 is complete for the
transfer of a multiple block write
When reception of the response to CMD52 that was issued by setting the IOABT bit to 1 is complete for transfer of
a multiple block read
When reception of the response to CMD52 that was issued by setting the IOABT bit to1 is complete for transfer of
a multiple block write
This bit is set when a command sequence is halted because of a communications error or timeout.
[Clearing conditions]
When 0 is written to ACEND
When the access end bit is set to 1.
Note:
The ACEND flag becomes 1 after the command sequence ends.
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41. SD/MMC Host Interface (SDHI)
SDCDRM flag (SDnCD Removal Flag)
The SDCDRM flag indicates that SDnCD was removed.
[Setting condition]
After a change in SDnCD from 0 to 1, Mcycle elapsed with SDnCD held at 1.
[Clearing conditions]
When 0 is written to SDCDRM.
Note:
Mcycle is set in bits [3:0] in SD_OPTION.
SDCDIN flag (SDnCD Insertion Flag)
The SDCDIN flag indicates that SDnCD was inserted.
[Setting condition]
After a change in SDnCD from 1 to 0, Mcycle elapsed with SDnCD held at 0.
[Clearing conditions]
When 0 is written to SDCDIN.
Note:
Mcycle is set in bits [3:0] in SD_OPTION.
SDD3RM flag (SDnDAT3 Removal Flag)
The SDD3RM flag indicates that SDnDAT3 was removed.
[Setting condition]
After a change in SDnDAT3 from 1 to 0, 2 cycles of PCLKA elapsed with SDnDAT3 held at 0.
[Clearing condition]
When 0 is written to SDD3RM.
SDD3IN flag (SDnDAT3 Insertion Flag)
The SDD3IN flag indicates that SDnDAT3 was inserted.
[Setting condition]
After a change in SDnDAT3 from 0 to 1, 2 cycles of PCLKA elapsed with SDnDAT3 held at 1.
[Clearing condition]
When 0 is written to SDD3IN.
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41.2.11
41. SD/MMC Host Interface (SDHI)
SD Card Interrupt Flag Register 2 (SD_INFO2)
Address(es): SDHI0.SD_INFO2 4006 203Ch, SDHI1.SD_INFO2 4006 243Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
ILA
CBSY
SD_CLK_
CTRLEN
—
—
—
BWE
BRE
ILR
ILW
DTO
ENDE
0*1
0*1
1*1
0
0
0
0*1
0*1
0*1
0*1
0*1
0*1
Value after reset:
Value after reset:
SDD0M RSPTO
ON
x
0*1
CRCE CMDE
0*1
0*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
CMDE
Command Error Detection Flag
0: Command error not detected
1: Command error detected.
R/W*1
b1
CRCE
CRC Error Detection Flag
0: CRC error not detected
1: CRC error detected.
R/W*1
b2
ENDE
End Bit Error Detection Flag
0: End bit error not detected
1: End bit error detected.
R/W*1
b3
DTO
Data Timeout Detection Flag
0: Data timeout not detected
1: Data timeout detected.
R/W*1
b4
ILW
SD_BUF0 Illegal Write Access
Detection Flag
0: Illegal write access to the SD_BUF0 register not detected R/W*1
1: Illegal write access to the SD_BUF0 register detected.
b5
ILR
SD_BUF0 Illegal Read Access
Detection Flag
0: Illegal read access to the SD_BUF0 register not detected R/W*1
1: Illegal read access to the SD_BUF0 register detected.
b6
RSPTO
Response Timeout Detection
Flag
0: Response timeout not detected
1: Response timeout detected.
R/W*1
b7
SDD0MON
SDHI_D0 Pin Status Flag
0: SDnDAT0 pin is low
1: SDnDAT0 pin is high.
R
b8
BRE
SD_BUF0 Read Enable Flag
0: Disable read access to the SD_BUF0 register
1: Enable read access to the SD_BUF0 register.
R/W*1
b9
BWE
SD_BUF0 Write Enable Flag
0: Disable write access to the SD_BUF0 register
1: Enable write access to the SD_BUF0 register.
R/W*1
b12 to b10 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13
SD_CLK_CT
RLEN
SD_CLK_CTRL Write Enable
Flag
0: SD/MMC bus (CMD and DAT lines) is busy, so write
access to the SD_CLK_CTRL.CLKEN and CLKSEL[7:0]
bits is disabled
1: SD/MMC bus (CMD and DAT lines) is not busy, so write
access to the SD_CLK_CTRL.CLKEN and CLKSEL[7:0]
bits is enabled.
R
b14
CBSY
Command Sequence Status
Flag
0: Command sequence complete
1: Command sequence in progress (busy).
R
b15
ILA
Illegal Access Error Detection
Flag
0: Illegal access error not detected
1: Illegal access error detected.
R/W*1
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b16 —
Note 1.
The flag does not change even if set to 1. Writing 0 changes the flag value to 0.
The SD_INFO2 register indicates the status of the SD buffer and the status of the SD card/MMC. Set the flags to be
cleared to 0. Set the flags that are not being cleared to 1.
CMDE flag (Command Error Detection Flag)
The CMDE flag indicates that a command error was detected. The command sequence stops when a command error
occurs. When the SDIO_MODE.C52PUB bit is set to 1 and CMD52 is automatically issued, if a communication error or
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41. SD/MMC Host Interface (SDHI)
response timeout occurs, the command sequence is not completed. Perform the error processing shown in section
41.3.12, IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Read) or section 41.3.13, IO_RW_EXTENDED
Command (SD: CMD53/Multiple Block Write), and complete the command sequence.
[Setting conditions]
The command index of the transmitted command differs from the command index of the received response
The command index of a command issued within a command sequence differs from the command index of the
received response.
[Clearing condition]
When 0 is written to CMDE.
CRCE flag (CRC Error Detection Flag)
The CRCE flag indicates that a CRC error was detected. The command sequence stops when a CRC error occurs. When
the SDIO_MODE.C52PUB bit is set to 1 and CMD52 is automatically issued, if a communication error or response
timeout occurs, the command sequence is not completed. Perform the error processing shown in section 41.3.12,
IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Read) or section 41.3.13, IO_RW_EXTENDED
Command (SD: CMD53/Multiple Block Write), and complete the command sequence.
[Setting conditions]
When an error occurs in the CRC status
When a CRC error occurs in the read data
When a CRC error occurs in the response
A CRC error in the response to a command issued within a command sequence.
[Clearing condition]
When 0 is written to CRCE.
ENDE flag (End Bit Error Detection Flag)
The ENDE flag indicates that an end bit error was detected. The command sequence is stopped when an end bit error
occurs. When the SDIO_MODE.C52PUB bit is set to 1 and CMD52 is automatically issued, if a communication error or
response timeout occurs, the command sequence is not completed. Perform the error processing shown in section
41.3.12, IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Read) or section 41.3.13, IO_RW_EXTENDED
Command (SD: CMD53/Multiple Block Write), and complete the command sequence.
[Setting conditions]
When an error occurs in the response length (and the end bit is not detected)
When an error occurs in the read data length (and the end bit is not detected among the valid bits)
When an error occurs in the CRC status length (and the end bit is not detected)
An error in the length of a response to a command issued within a command sequence, for example when the end bit
is not detected.
[Clearing condition]
When 0 is written to ENDE.
DTO flag (Data Timeout Detection Flag)
The DTO flag indicates that a data timeout was detected. The command sequence stops when a data timeout occurs.
[Setting conditions]
After R1b response, the busy state (SDnDAT0 = 0) continues for longer than Ncycle
After CRC status, the busy state (SDnDAT0 = 0) continues for longer than Ncycle
After write data, the CRC status is not received though Ncycle has elapsed
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41. SD/MMC Host Interface (SDHI)
After read command, read data is not received though a time longer than Ncycle has elapsed
After CMD12 is issued within a command sequence, the busy state (SDnDAT0 = 0) continues for longer than
Ncycle
After the reception of read data, read data for the next block are not received though a time longer than Ncycle has
elapsed
After release of the read wait state, read data for the next block are not received though a time longer than Ncycle
has elapsed.
Note:
Ncycle is set in bits [7:4] in SD_OPTION.
[Clearing condition]
When 0 is written to DTO.
ILW flag (SD_BUF0 Illegal Write Access Detection Flag)
The ILW flag indicates that an SD_BUF0 illegal write access was detected.
[Setting conditions]
When data is written to SD_BUF0 while it is not in the data read/write command state
When data is written to SD_BUF0 while SD_BUF is full
When data is written to SD_BUF0 while an error occurs in the CRC status or CRC status length
When data is written to SD_BUF0 while a busy state after the CRC status continues for longer than Ncycle.
Note:
Ncycle is set in bits [7:4] in SD_OPTION.
[Clearing condition]
When 0 is written to ILW.
ILR flag (SD_BUF0 Illegal Read Access Detection Flag)
The ILR flag indicates that an SD_BUF0 illegal read access was detected.
[Setting conditions]
When SD_BUF is empty while SD_BUF0 is read
When data with a CRC error or END error is read from SD_BUF0.
[Clearing condition]
When 0 is written to ILR.
RSPTO flag (Response Timeout Detection Flag)
The RSPTO flag indicates that a response timeout was detected. The command sequence is stopped when a response
timeout occurs. When the SDIOMD.C52PUB bit is set to 1 and CMD52 is automatically issued, if a communication
error or response timeout occurs, the command sequence is not completed. Perform the error processing shown in section
41.3.12, IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Read) or section 41.3.13, IO_RW_EXTENDED
Command (SD: CMD53/Multiple Block Write), and complete the command sequence.
[Setting condition]
When a response is not received though a time longer than 640 cycles of SD/MMC clock has elapsed (including a
response to a command issued within a command sequence).
[Clearing condition]
When 0 is written to RSPTO.
SDD0MON flag (SDHI_D0 Pin Status Flag)
The SDD0MON flag indicates the status of the SDHI_D0 pin. If the data timeout (DTO) is set but the response timeout
(RSPTO) is not set after the Erase command is issued, the end of the Erase sequence (SDD0MON = 1) is confirmed by
polling DAT0.
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41. SD/MMC Host Interface (SDHI)
If a communication error or timeout occurs during a write sequence, the DAT0 bit might retain the value 0.
While the SD/MMC clock is stopped, the DAT0 bit retains the value before the clock is stopped.
BRE flag (SD_BUF0 Read Enable Flag)
The BRE flag indicates that SD_BUF0 is enabled for reading.
[Setting conditions]
When data set in SD_SIZE is stored in SD_BUF0 at single block transfer
When data set in SD_SIZE is stored in either bank 1 or bank 2 of SD_BUF0 at multiple block transfer.
[Clearing conditions]
When 0 is written to BRE
Reading of a block of data from SD_BUF0 by DMA transfer.
When data is read from SD_BUF0 by the CPU, clear BRE, then read the amount of data specified in SD_SIZE.
Even if a CRC error or an END error occurs while block data is read, data is stored in SD_BUF0 and BRE is set.
BWE flag (SD_BUF0 Write Enable Flag)
The BWE flag indicates that SD_BUF0 is enabled for writing.
[Setting conditions]
When SD_BUF0 is empty at single block transfer
When either bank 1 or bank 2 of SD_BUF0 is empty at multiple block transfer.
[Clearing conditions]
When 0 is written to BWE
Writing of a block of data to SD_BUF0 by DMA transfer.
When data is written to SD_BUF0 by the CPU, clear BWE, and then write the amount of data specified in SD_SIZE.
SD_CLK_CTRLEN flag (SD_CLK_CTRL Write Enable Flag)
When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the
SD_CLK_CTRLEN bit is set to 0. The SD_CLK_CTRLEN bit is set to 1 after 8 cycles of SDCLK have elapsed after the
CBSY bit clears to 0 on completion of the command sequence.
ILA flag (Illegal Access Error Detection Flag)
The ILA flag indicates that an illegal access error was detected.
[Setting conditions]
Writing of data to SD_CMD within a command sequence (CBSY = 1)
When SD_CMD[11] = 1 (command with data transfer) and SD_CMD[7:0] = 0000 1100b (CMD12) are set in
SD_CMD.
[Clearing condition]
When 0 is written to ILA.
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41.2.12
41. SD/MMC Host Interface (SDHI)
SD INFO1 Interrupt Mask Register (SD_INFO1_MASK)
Address(es): SDHI0.SD_INFO1_MASK 4006 2040h, SDHI1.SD_INFO1_MASK 4006 2440h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
RSPEN
DM
0
0
0
0
0
0
0
0
0
0
1
Value after reset:
Value after reset:
SDD3I SDD3R
NM
MM
1
1
SDCDI SDCDR ACEND
NM
MM
M
1
1
1
Bit
Symbol
Bit name
Description
R/W
b0
RSPENDM
Response End Interrupt
Request Mask
0: Do not mask response end interrupt request
1: Mask response end interrupt request.
R/W
b1
—
Reserved
This bit is read as 0 and cannot be modified
R
b2
ACENDM
Access End Interrupt Request
Mask
0: Do not mask access end interrupt request
1: Mask access end interrupt request.
R/W
b3
SDCDRMM
SDnCD Removal Interrupt
Request Mask
0: Do not mask SD card/MMC removal interrupt request by the
SDnCD pin
1: Mask SD card/MMC removal interrupt request by the SDnCD
pin.
R/W
b4
SDCDINM
SDnCD Insertion Interrupt
Request Mask
0: Do not mask SD card/MMC insertion interrupt request by the
SDnCD pin
1: Mask SD card/MMC insertion interrupt request by the SDnCD
pin.
R/W
b7 to b5
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
b8
SDD3RMM
SDnDAT3 Removal Interrupt
Request Mask
0: Do not mask SD card/MMC removal interrupt request by the
SDnDAT3 pin
1: Mask SD card/MMC removal interrupt request by the
SDnDAT3 pin.
R/W
b9
SDD3INM
SDnDAT3 Insertion Interrupt
Request Mask
0: Do not mask SD card/MMC insertion interrupt request by the
SDnDAT3 pin
1: Mask SD card/MMC insertion interrupt request by the
SDnDAT3 pin.
R/W
b31 to b10
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
The SD_INFO1_MASK register enables or disables interrupt requests from the status flags in the SD_INFO1 register.
See Table 41.5, Interrupt sources, for details on the relationship between the status flags and the requested interrupt
source.
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41.2.13
41. SD/MMC Host Interface (SDHI)
SD INFO2 Interrupt Mask Register (SD_INFO2_MASK)
Address(es): SDHI0.SD_INFO2_MASK 4006 2044h, SDHI1.SD_INFO2_MASK 4006 2444h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
ILAM
—
—
—
—
—
ILWM
DTOM
ENDE
M
1
0
0
0
1
0
1
1
1
Value after reset:
Value after reset:
BWEM BREM
1
1
—
0
RSPTO ILRM
M
1
1
CRCE CMDE
M
M
1
1
Bit
Symbol
Bit name
Description
R/W
b0
CMDEM
Command Error Interrupt
Request Mask
0: Do not mask command error interrupt request
1: Mask command error interrupt request.
R/W
b1
CRCEM
CRC Error Interrupt Request
Mask
0: Do not mask CRC error interrupt request
1: Mask CRC error interrupt request.
R/W
b2
ENDEM
End Bit Error Interrupt Request
Mask
0: Do not mask end bit detection error interrupt request
1: Mask end bit detection error interrupt request.
R/W
b3
DTOM
Data Timeout Interrupt Request
Mask
0: Do not mask data timeout interrupt request
1: Mask data timeout interrupt request.
R/W
b4
ILWM
SD_BUF0 Register Illegal Write
Interrupt Request Mask
0: Do not mask illegal write detection interrupt request for the
SD_BUF0 register
1: Mask illegal write detection interrupt request for the SD_BUF0
register.
R/W
b5
ILRM
SD_BUF0 Register Illegal Read
Interrupt Request Mask
0: Do not mask illegal read detection interrupt request for the
SD_BUF0 register
1: Mask illegal read detection interrupt request for the SD_BUF0
register.
R/W
b6
RSPTOM
Response Timeout Interrupt
Request Mask
0: Do not mask response timeout interrupt request
1: Mask response timeout interrupt request.
R/W
b7
—
Reserved
This bit is 0 when read and cannot be modified.
R
b8
BREM
BRE Interrupt Request Mask
0: Do not mask read enable interrupt request for the SD buffer
1: Mask read enable interrupt request for the SD buffer.
R/W
b9
BWEM
BWE Interrupt Request Mask
0: Do not mask write enable interrupt request for the SD_BUF0
R/W
register
1: Mask write enable interrupt request for the SD_BUF0 register.
b10
—
Reserved
This bit is read as 0
R
b11
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b14 to b12
—
Reserved
These bits are read as 0
R
b15
ILAM
Illegal Access Error Interrupt
Request Mask
0: Do not mask illegal access error interrupt request
1: Mask illegal access error interrupt request.
R/W
b31 to b16
—
Reserved
These bits are read as 0. The write value should be 0.
R
Note 1.
When the SD_INFO2_MASK.BWEM bit is 0 or the SD_INFO2_MASK.BREM bit is 0, set the SD_DMAEN.DMAEN bit to 0.
When the SD_DMAEN.DMAEN bit is 1, set the SD_INFO2_MASK.BWEM bit to 1 and the SD_INFO2_MASK.BREM bit to 1.
The SD_INFO2_MASK register enables or disables interrupt requests from the status flags in the SD_INFO2 register.
See Table 41.5 for details on the relationship between the status flags and the requested interrupt source.
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41.2.14
41. SD/MMC Host Interface (SDHI)
SD Clock Control Register (SD_CLK_CTRL)
Address(es): SDHI0.SD_CLK_CTRL 4006 2048h, SDHI1.SD_CLK_CTRL 4006 2448h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
CLKCT CLKEN
RLEN
0
0
CLKSEL[7:0]
0
0
1
0
0
Bit
Symbol
Bit name
Description
b7 to b0
CLKSEL[7:0]
SDHI Clock Frequency
Select*1
b7
b8
CLKEN
SD/MMC Clock Output
Control*1
0: Disable SD/MMC clock output (fix SDnCLK signal low)
1: Enable SD/MMC clock output.
R/W
b9
CLKCTRLEN
SD/MMC Clock Output
Automatic Control Select
0: Disable automatic control of SD/MMC clock output
1: Enable automatic control of SD/MMC clock output.
R/W
b31 to b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
R/W
R/W
b0
0 0 0 0 0 0 0 0: PCLKA/2
0 0 0 0 0 0 0 1: PCLKA/4
0 0 0 0 0 0 1 0: PCLKA/8
0 0 0 0 0 1 0 0: PCLKA/16
0 0 0 0 1 0 0 0: PCLKA/32
0 0 0 1 0 0 0 0: PCLKA/64
0 0 1 0 0 0 0 0: PCLKA/128
0 1 0 0 0 0 0 0: PCLKA/256
1 0 0 0 0 0 0 0: PCLKA/512.
Other settings are prohibited.
Bits CLKSEL[7:0] and CLKEN cannot be write accessed when the SD_INFO2.SD_CLK_CTRLEN flag is 0.
The SDCLKCTRL register controls the SD/MMC clock frequency settings and output. Set the CLKEN bit to 1 before
writing to the SD_CMD register to start a command sequence. Do not write to the SDCLKCTRL register when the
SD_INFO2.SD_CLK_CTRLEN flag is 0.
CLKCTRLEN bit (SD/MMC Clock Output Automatic Control Select)
The CLKCTRLEN bit enables or disables the automatic control function for SD/MMC clock output, which causes the
SD/MMC clock to output only within a command sequence.
The timing with which SD/MMC clock output starts and stops is as follows:
SD/MMC clock output starts after writing to SD_CMD
SD/MMC clock output stops when 8 cycles of SD/MMC clock have elapsed after the end of the command
sequence.
In addition, SD/MMC clock is fixed to 0 while CLKEN of SD_CLK_CTRL is 0, regardless of the value of this bit.
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41.2.15
41. SD/MMC Host Interface (SDHI)
Transfer Data Length Register (SD_SIZE)
Address(es): SDHI0.SD_SIZE 4006 204Ch, SDHI1.SD_SIZE 4006 244Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
LEN[9:0]
1
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b9 to b0
LEN[9:0]
Transfer Data Size Setting
These bits specify the transfer data size*1
R/W
b31 to b10
—
Reserved
These bits are read as 0. The write value should be 0.
R
Note 1.
Do not rewrite these bits when the SD_INFO2.CBSY flag is 1.
The SD_SIZE register sets the transfer data size.
LEN[9:0] bits (Transfer Data Size Setting)
When using single block transfer, the transfer data size can be set in the LEN[9:0] bits from 1 byte to 512 bytes. When
CMD12 is automatically issued during a multiblock transfer sequence (CMD18 and CMD25), the transfer data size can
only be set to 512 bytes. When CMD12 is not automatically issued during a multiblock transfer sequence, the transfer
data size can be set to 32, 64, 128, 256, or 512 bytes. However, a 32-, 64-, 128-, or 256-byte multiblock read transfer can
only be performed during an SDIO multiblock transfer (CMD53). Do not set these bits to 0 when using a command that
includes data transfer.
41.2.16
SD Card Access Control Option Register (SD_OPTION)
Address(es): SDHI0.SD_OPTION 4006 2050h, SDHI1.SD_OPTION 4006 2450h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
WIDTH
—
WIDTH
8
—
—
—
—
TOUTM
ASK
0*2
1
0*2
0
0
0
0
0*2
TOP[3:0]
1*2
Bit
Symbol
Bit name
Description
b3 to b0
CTOP[3:0]
Card Detection Time Counter
*1
b3
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b0
1*2
0 0 0 0: PCLKA × 210
0 0 0 1: PCLKA × 211
0 0 1 0: PCLKA × 212
0 0 1 1: PCLKA × 213
0 1 0 0: PCLKA × 214
0 1 0 1: PCLKA × 215
0 1 1 0: PCLKA × 216
0 1 1 1: PCLKA × 217.
CTOP[3:0]
1*2
0*2
1*2
1*2
1*2
0*2
R/W
b3
b0
1 0 0 0: PCLKA × 218
1 0 0 1: PCLKA × 219
1 0 1 0: PCLKA × 220
1 0 1 1: PCLKA × 221
1 1 0 0: PCLKA × 222
1 1 0 1: PCLKA × 223
1 1 1 0: PCLKA × 224
1 1 1 1: Setting prohibited.
R/W
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Bit
41. SD/MMC Host Interface (SDHI)
Symbol
Bit name
Description
Counter*1
R/W
b7 to b4
TOP[3:0]
Timeout
b8
TOUTMASK
Timeout Mask
0: Activate timeout
1: Inactivate timeout (do not set RSPTO and DTO bits of
SD_INFO2 or E6 to E0 bits of SDERRSTS2).
When timeout occurs because of an inactivated timeout,
execute a software reset to terminate the command
sequence.
R/W
b12 to b9
—
Reserved
These bits are read as 0
R
b13
WIDTH8*2
Bus Width
See bit 15 WIDTH bit
R/W
b14
—
Reserved
This bit is read as 1
R
b15
R/W
WIDTH
Bus
b31 to b16
—
Reserved
b4
b7
0 0 0 0: SDHI clock × 213
0 0 0 1: SDHI clock × 214
0 0 1 0: SDHI clock × 215
0 0 1 1: SDHI clock × 216
0 1 0 0: SDHI clock × 217
0 1 0 1: SDHI clock × 218
0 1 1 0: SDHI clock × 219
0 1 1 1: SDHI clock × 220.
Width*2
b15
Note 1.
Note 2.
b7
R/W
b4
1 0 0 0: SDHI clock × 221
1 0 0 1: SDHI clock × 222
1 0 1 0: SDHI clock × 223
1 0 1 1: SDHI clock × 224
1 1 0 0: SDHI clock × 225
1 1 0 1: SDHI clock × 226
1 1 1 0: SDHI clock × 227
1 1 1 1: Setting prohibited.
b13
0 1: 8-bit width
0 0: 4-bit width
1 0: 1-bit width
1 1: 1-bit width.
For 1-byte write transfers, set 4-bit or 1-bit width. Do not set 8bit width.
These bits are read as 0
R
Do not rewrite these bits when the SD_INFO2.CBSY flag is 1.
The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0.
The SD bus width and timeout counter are set in the SD_OPTION register.
41.2.17
SD Error Status Register 1 (SD_ERR_STS1)
Address(es): SDHI0.SD_ERR_STS1 4006 2058h, SDHI1.SD_ERR_STS1 4006 2458h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
0
0
—
Value after reset:
x
CRCTK RDCR RSPCR RSPCR
E
CE
CE1
CE0
CRCTK[2:0]
0*3
1*3
0*3
0*3
0*3
0*3
0*3
CRCLE RDLEN RSPLE RSPLE CMDE1 CMDE0
NE
E
NE1
NE0
0*3
0*3
0*3
0*3
0*3
0*3
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
CMDE0
Command Error Flag 0
0: No error exists in command index field value of a command*1
response
1: Error exists in command index field value of a command*1
response.
R
b1
CMDE1
Command Error Flag 1
0: No error exists in command index field value of a command*2
response
1: Error exists in command index field value of a command*2
response (with SD_CMD.CMDIDX[5:0] setting, an error that
occurs with CMD12 issue is indicated in the CMDE0 flag).
R
b2
RSPLENE0
Response Length Error Flag
0
0: No error exists in command*1 response length
1: Error exists in command*1 response length.
R
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Bit
41. SD/MMC Host Interface (SDHI)
Symbol
Bit name
Description
R/W
command*2
b3
RSPLENE1
Response Length Error Flag
1
0: No error exists in
response length
1: Error exists in command*2 response length (with
SD_CMD.CMDIDX[5:0] setting, an error that occurs with
CMD12 issue is indicated in the RSPLENE0 flag).
b4
RDLENE
Read Data Length Error Flag 0: No read data length error occurred
1: Read data length error occurred.
R
b5
CRCLENE
CRC Status Token Length
Error Flag
0: No CRC status token length error occurred
1: CRC status token length error occurred.
R
b7, b6
—
Reserved
These bits are read as 0
R
R
command*1
b8
RSPCRCE0
Response CRC Error Flag 0
response
0: No CRC error detected in
1: CRC error detected in command*1 response.
R
b9
RSPCRCE1
Response CRC Error Flag 1
0: No CRC error detected in command*2 response (with
SD_CMD.CMDIDX[5:0] setting, an error that occurs with
CMD12 issue is indicated in the RSPCRCE0 flag)
1: CRC error detected in command*2 response.
R
b10
RDCRCE
Read Data CRC Error Flag
0: No CRC error detected in read data
1: CRC error detected in read data.
R
b11
CRCTKE
CRC Status Token Error Flag 0: No error detected in CRC status token
1: Error detected in CRC status token.
R
b14 to b12
CRCTK[2:0]
CRC Status Token
These bits store the CRC status token value (normal value is
010b)
R
b15
—
Reserved
This bit is read as 0
R
b31 to b16
—
Reserved
These bits are read as undefined
R
Note 1.
Note 2.
Note 3.
CMD other than CMD12 when automatic issuing is enabled for multiple block transfer by the setting in SD_CMD, CMD12 when
the STP bit in SD_STOP is set to 1, or CMD52 when the C52PUB or IOABT bit in SDIO_MODE is set to 1.
CMD12 when automatic issuing is enabled for multiple block transfer by the setting in SD_CMD, CMD12 when the STP bit in
SD_STOP is set to 1, or CMD52 when the C52PUB or IOABT bit in SDIO_MODE is set to 1.
The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0.
The SD_ERR_STS1 register indicates the CRC status token, CRC error, end bit error, and command error.
41.2.18
SD Error Status Register 2 (SD_ERR_STS2)
Address(es): SDHI0.SD_ERR_STS2 4006 205Ch, SDHI1.SD_ERR_STS2 4006 245Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
CRCBS CRCTO RDTO BSYTO BSYTO RSPTO RSPTO
1
0
1
0
YTO
0*4
0*4
0*4
0*4
0*4
0*4
Bit
Symbol
Bit name
b0
RSPTO0
Response Timeout Flag 0 0: After command*1 was issued, response was received in less than
640 cycles of the SD/MMC clock
1: After command*1 was issued, response was not received in 640 or
more cycles of the SD/MMC clock.
R
b1
RSPTO1
Response Timeout Flag 1 0: After command*2 was issued, response was received in less than
640 cycles of the SD/MMC clock
1: After command*2 was issued, response was not received after 640
or more cycles of the SD/MMC clock (with SD_CMD.CMDIDX[5:0]
setting, an error that occurs with CMD12 issue is indicated in the
RSPTO0 flag).
R
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0*4
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41. SD/MMC Host Interface (SDHI)
Bit
Symbol
Bit name
Description
R/W
b2
BSYTO0
Busy Timeout Flag 0
0: After R1b response was received, SD/MMC was released from the
busy state during the specified period*3
1: After R1b response was received, SD/MMC was in the busy state
after the specified period*3 elapsed.
R
b3
BSYTO1
Busy Timeout Flag 1
0: After CMD12 was automatically issued, SD/MMC was released
from the busy state during the specified period*3
1: After CMD12 was automatically issued, SD/MMC was in the busy
state after the specified period*3 elapsed (with
SD_CMD.CMDIDX[5:0] setting, an error that occurs with CMD12
issue is indicated in the BSYTO0 flag).
R
b4
RDTO
Read Data Timeout Flag
When a read command is issued, this flag is set to 1 when read data
is not received after the specified period*3 elapses.
When read data is received, this flag is set to 1 when the next block of
read data is not received after the specified period*3 elapses.
When the SD/MMC exits the read wait state, this flag is set to 1 when
the next block of read data is not received after the specified period*3
elapses.
R
b5
CRCTO
CRC Status Token
Timeout Flag
0: After CRC data was written to the SD card/MMC, a CRC status
token was received during the specified period*3
1: After CRC data was written to the SD card/MMC, a CRC status
token was not received after the specified period*3 elapsed.
R
b6
CRCBSYTO
CRC Status Token Busy
Timeout Flag
0: After a CRC status token was received, the SD/MMC was released
from the busy state during the specified period*3
1: After a CRC status token was received, the SD/MMC was in the
busy state after the specified period*3 elapsed.
R
b31 to b7
—
Reserved
These bits are read as 0
R
Note 1.
Note 2.
Note 3.
Note 4.
CMD other than CMD12 when automatic issuing is enabled for multiple block transfer by the setting in SD_CMD, CMD12 when
the STP bit in SD_STOP is set to 1, or CMD52 when the C52PUB or IOABT bit in SDIO_MODE is set to 1.
CMD12 when automatic issuing is enabled for multiple block transfer by the setting in SD_CMD, CMD12 when the STP bit in
SD_STOP is set to 1, or CMD52 when the C52PUB or IOABT bit in SDIO_MODE is set to 1.
Set the SD_OPTION.TOP[3:0] bits to select the number of n cycles.
The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0.
The SD_ERR_STS2 register indicates the timeout status.
41.2.19
SD Buffer Register (SD_BUF0)
Address(es): SDHI0.SD_BUF0 4006 2060h, SDHI1.SD_BUF0 4006 2460h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
When writing to the SD card, write data is written to this register. When reading from the SD card, read data is read from
this register. This register is internally connected to two 512-byte buffers.
If both buffers are not empty when executing multiple block read, the SD card/MMC clock is stopped to suspend
receiving data. When one of the buffers is empty, the SD card/MMC clock is supplied to resume receiving data.
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41.2.20
41. SD/MMC Host Interface (SDHI)
SDIO Mode Control Register (SDIO_MODE)
Address(es): SDHI0.SDIO_MODE 4006 2068h, SDHI1.SDIO_MODE 4006 2468h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
RWRE
Q
—
INTEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
C52PU IOABT
B
0
0
Bit
Symbol
Bit name
Description
R/W
b0
INTEN
SDIO Interrupt Acceptance
Enable*1
0: Disable SDIO interrupt acceptance
1: Enable SDIO interrupt acceptance.
R/W
b1
—
Reserved
This bit is read as 0
R
b2
RWREQ
Read Wait Request
0: Allow SD/MMC to exit read wait state
1: Request for SD/MMC to enter read wait state.
R/W
b7 to b3
—
Reserved
These bits are read as 0
R
b8
IOABT
SDIO Abort
If this bit is set to 1 during multiblock transfer triggered by CMD53,
R/W
CMD52 is immediately issued, and the command sequence is aborted
b9
C52PUB
SDIO None Abort
If this bit is set to 1 during multiblock transfer triggered by CMD53,
CMD52 is issued after the transfer process is complete, and the
command sequence is complete
R/W
b31 to b10
—
Reserved
These bits are read as 0
R
Note 1.
Do not rewrite this bit when the SD_INFO2.CBSY flag is 1.
The SDIO_MODE register controls reception of the SDIO interrupt, CMD52 issuance during multiblock transfer, and
the read wait request. Do not set bits C52PUB and IOABT to 1 at the same time.
RWREQ bit (Read Wait Request)
When RWREQ is set to 1 in the CMD53 (multiple block) read sequence, the block transfer enters the read wait state
between blocks.
[Read wait state releasing]
The read wait state is released, when RWREQ is cleared to 0 in the read wait state
When IOABT is set to 1 in the read wait state, RWREQ is automatically cleared to 0 after CMD52 is issued, and
then the read wait state is released
When C52PUB and RWREQ are set to 1 simultaneously in the CMD53 (multiple block) read sequence, the read
wait state is not automatically released. Therefore, after the CMD52 response is received, clear RWREQ. You must
set RWREQ and C52PUB simultaneously.
When RWREQ is set to 1 while the last block in the CMD53 (multiple block) read sequence is transferred, the read wait
state is not entered and RWREQ is automatically cleared to 0 by setting access end. Set RWREQ to 1 after the response
end flag sets.
IOABT bit (SDIO Abort)
When the IOABT bit is set to 1 in a CMD53 (multiple block) sequence, the CMD53 sequence is halted and CMD52 is
issued. However, if a command sequence is halted because of a communication error or timeout, CMD52 is not issued.
Although continued buffer access is possible even after IOABT is set to 1, the buffer access error bit (ILR or ILW) in
SD_INFO2 is set accordingly. Set SD_ARG before setting IOABT to 1.
When IOABT is set to 1 during the transfer for a single block write, the access end flag sets when SD_BUF0 becomes
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41. SD/MMC Host Interface (SDHI)
empty, and CMD52 is not issued. If SD_BUF0 contains data, the access end flag sets on the completion of reception of
the busy state without CMD52 being issued.
When IOABT is set to 1 during transfer for single block read, the access end flag sets immediately after IOABT is set,
and CMD52 is not issued.
When IOABT is set to 1 during reception of the busy state after an R1b response, the access end flag sets on completion
of reception of the busy state without CMD52 being issued.
When IOABT is set to 1 after a command sequence is complete, CMD52 is not issued and the access end flag does not
set.
Set IOABT to 1 after the response end flag sets.
Set IOABT to 0 after the access end flag sets.
C52PUB bit (SDIO None Abort)
When the C52PUB bit is set to 1 in the CMD53 (multiple block) write sequence, CMD52 is automatically issued
between blocks if SD_BUF0 becomes empty. C52PUB is automatically cleared to 0 after the reception of the response to
CMD52 is complete. Additionally, if C52PUB is set to 1 while the last block is being transferred, CMD52 is not issued.
In this case, C52PUB is automatically cleared to 0 after the access end flag is set to 1.
When C52PUB and RWREQ are set to 1 in the CMD53 (multiple block) read sequence, the block transfer enters the read
wait state between blocks and CMD52 is automatically issued. C52PUB is automatically cleared to 0 after the reception
of the response to CMD52 is complete. Additionally, if C52PUB is set to 1 while the last block is being transferred,
CMD52 is not issued. In this case, C52PUB is automatically cleared to 0 after the access end flag is set to 1.
If C52PUB is set to 1 in the CMD53 (multiple block) read sequence, you must set RWREQ to 1 in addition to C52PUB.
Set SD_ARG before setting C52PUB to 1.
Set C52PUB to 1 after the response end flag sets.
41.2.21
SDIO Interrupt Flag Register (SDIO_INFO1)
Address(es): SDHI0.SDIO_INFO1 4006 206Ch, SDHI1.SDIO_INFO1 4006 246Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
IOIRQ
0
0
0
0
0
0
0
0
0
0
0
x
x
0
Value after reset:
EXWT EXPUB
52
0
Value after reset:
0
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
IOIRQ
SDIO Interrupt Status Flag
0: No SDIO interrupt detected
1: SDIO interrupt detected.
R(/W)*1
b2, b1
—
Reserved
The read value is undefined. The write value should be 1.
R/W
b13 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
EXPUB52
EXPUB52 Status Flag
Indicates the status of the EXPUB52
R(/W)*1
b15
EXWT
EXWT Status Flag
Indicates the status of the EXWT
R(/W)*1
b31 to b16
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1.
Only 0 can be written to clear the bit.
The SDIO_INFO1 register indicates the status of the SDIO card access. Set the flags to be cleared to 0. Set the flags that
are not being cleared to 1.
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41. SD/MMC Host Interface (SDHI)
IOIRQ flag (SDIO Interrupt Status Flag)
The IOIRQ flag indicates that an SDIO interrupt occurred.
[Setting condition]
When SDIO interrupt from an SDIO card is received while INTEN in SDIO_MODE is set to 1.
[Clearing condition]
When 0 is written to IOIRQ.*1
Note 1. Before clearing this bit, access the SDIO card to negate the SDIO interrupt signal from the SDIO card. If the
interrupt signal is not negated, this bit can be set again.
EXPUB52 flag (EXPUB52 Status Flag)
The EXPUB52 flag indicates the EXPUB52 status.
[Setting conditions]
While the last block in the CMD53 (multiple block) sequence is transferred, C52PUB in SDIO_MODE is set to 1
While C52PUB is set to 1 in the CMD53 (multiple block) write sequence, the last block is transferred.
[Clearing condition]
When 0 is written to EXPUB52.
EXWT flag (EXWT Status Flag)
The EXWT flag indicates the EXWT status.
[Setting condition]
While the last block in the CMD53 (multiple block) read sequence is transferred, RWREQ in SDIO_MODE is set to
1.
[Clearing condition]
When 0 is written to EXWT.
41.2.22
SDIO INFO1 Interrupt Mask Register (SDIO_INFO1_MASK)
Address(es): SDHI0.SDIO_INFO1_MASK 4006 2070h, SDHI1.SDIO_INFO1_MASK 4006 2470h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
IOIRQ
M
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Value after reset:
EXWT EXPUB
M
52M
1
Value after reset:
1
Bit
Symbol
Bit name
Description
R/W
b0
IOIRQM
IOIRQ Interrupt Mask Control
0: Do not mask IOIRQ interrupts
1: Mask IOIRQ interrupts.
R/W
b2, b1
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b13 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
EXPUB52M
EXPUB52 Interrupt Request
Mask Control
0: Do not mask EXPUB52 interrupt requests
1: Mask EXPUB52 interrupt requests.
R/W
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41. SD/MMC Host Interface (SDHI)
Bit
Symbol
Bit name
Description
R/W
b15
EXWTM
EXWT Interrupt Request Mask
Control
0: Do not mask EXWT interrupt requests
1: Mask EXWT interrupt requests.
R/W
b31 to b16
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SDIO_INFO1_MASK register enables or disables interrupt requests from the status flags in the SDIO_INFO1
register. See Table 41.5, Interrupt sources for details on the relationship between the status flags and the requested
interrupt source.
41.2.23
DMA Mode Enable Register (SD_DMAEN)
Address(es): SDHI0.SD_DMAEN 4006 21B0h, SDHI1.SD_DMAEN 4006 25B0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMAE
N
—
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
b0
—
Reserved
Enable *1, *2
Description
R/W
This bit is read as 0
R
0: Disable use of DMA transfer to access SD_BUF0 register
1: Enable use of DMA transfer to access SD_BUF0 register.
R/W
b1
DMAEN
DMA Transfer
b3, b2
—
Reserved
These bits are read as 0
R
b4
—
Reserved
This bit is read as 1
R
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7, b6
—
Reserved
These bits are read as 0
R
b9, b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b11, b10
—
Reserved
These bits are read as 0
R
b12
—
Reserved
This bit is read as 1
R
b31 to b13
—
Reserved
These bits are read as 0
R
Note 1. Do not rewrite this bit when the SD_INFO2.CBSY bit is 1.
Note 2. When the SD_INFO2_MASK.BWEM bit is 0 or the SD_INFO2_MASK.BREM bit is 0, set the
SD_DMAEN.DMAEN bit to 0. When the SD_DMAEN.DMAEN bit is 1, set the SD_INFO2_MASK.BWEM bit to 1
and the SD_INFO2_MASK.BREM bit to 1.
The SD_DMAEN register enables or disables DMA transfers.
DMAEN bit (DMA Transfer Enable)
When using DMA transfer to access the SD buffer, set the DMAEN bit to 1 before setting the SD_CMD register.
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41.2.24
41. SD/MMC Host Interface (SDHI)
Software Reset Register (SOFT_RST)
Address(es): SDHI0.SOFT_RST 4006 21C0h, SDHI1.SOFT_RST 4006 25C0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDRST
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
SDRST
Software Reset Control
0: Reset SD/MMC Host Interface software
1: Cancel reset of SD/MMC Host Interface software.
R/W
b2, b1
—
Reserved
These bits are read as 1
R
b31 to b3
—
Reserved
These bits are read as 0
R
Table 41.4 lists the bits and flags initialized by SD/MMC Host Interface software reset.
Table 41.4
Bits and flags initialized by SD/MMC Host Interface software reset
Register
Bit/flag
SD_STOP
SEC
SD_INFO1
RSPEND, ACEND
SD_INFO2
CMDE, CRCE, ENDE, DTO, ILW, ILR, RSPTO, SDD0MON, BRE, BWE, SD_CLK_CTRLEN, ILA
SD_CLK_CTRL
CLKEN
SD_OPTION
CTOP[3:0], TOP[3:0], WIDTH
Bits b8 and b13 in the SD_OPTION register are also initialized by the SDHI software reset.
SD_ERR_STS1
CMDE0, CMDE1, RSPLENE0, RSPLENE1, RDLENE, CRCLENE, RSPCRCE0, RSPCRCE1, RDCRCE,
CRCTKE, CRCTK[2:0]
SD_ERR_STS2
RSPTO0, RSPTO1, BSYTO0, BSYTO1, RDTO, CRCTO, CRCBSYTO
SDIO_INFO1
IOIRQ, EXPUB52, EXWT
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41.2.25
41. SD/MMC Host Interface (SDHI)
SD Interface Mode Setting Register (SDIF_MODE)
Address(es): SDHI0.SDIF_MODE 4006 21CCh, SDHI1.SDIF_MODE 4006 25CCh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
NOCH
KCR
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
NOCHKCR
CRC Check Mask
CRC check mask bit for MMC test commands. Set when CRC16 or CRC
status value check is not executed.
0: Enable CRC check
1: Disable CRC Check (ignore CRC16 valued when reading and ignore
CRC status value when writing).
R/W
b31 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
NOCHKCR bit (CRC Check Mask)
The NOCHKCR bit is used for MMC test commands. This bit is set when CRC16 or CRC status value check is not
executed.
41.2.26
Swap Control Register (EXT_SWAP)
Address(es): SDHI0.EXT_SWAP 4006 21E0h, SDHI1.EXT_SWAP 4006 25E0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
BRSW BWSW
P
P
0
0
Bit
Symbol
Bit name
b0
—
Reserved
This bit is read as 0 and cannot be modified
R
b1
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2
—
Reserved
This bit is read as 0 and cannot be modified
R
b4, b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
—
Reserved
This bit is read as 0 and cannot be modified
R
b6
BWSWP
SD_BUF0 Swap Write*1
0: Normal write operation
1: Swap the byte endian order before writing to SD_BUF0 register.
R/W
b7
BRSWP
SD_BUF0 Swap Read*1
0: Normal read operation
1: Swap the byte endian order before reading SD_BUF0 register.
R/W
b10 to b8
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
b12, b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14, b13
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
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Description
R/W
Page 1368 of 1734
S5D5 User’s Manual
Bit
Symbol
41. SD/MMC Host Interface (SDHI)
Bit name
Description
R/W
b15
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b31 to b16
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
Note 1.
Do not rewrite this bit when the SD_INFO2.CBSY flag is 1.
The EXT_SWAP register selects whether or not the byte endian order is swapped when accessing the SD_BUF0 register.
See section 41.3.1 for details on the differences in accessing the SD_BUF0 register based on the EXT_SWAP register
value.
41.3
Operation
41.3.1
SD/MMC Interface
When data is read from the SD card/MMC, the process is as follows:
1. The SD/MMC Host Interface receives data from the SD card/MMC through the SDnDAT signal (see Figure 41.2
and Figure 41.3).
2. The received data is stored in SD_BUF of the MMC Host Interface (see Figure 41.4).
3. The data stored in SD_BUF is read from SD_BUF0 (see Figure 41.5).
When data is written to the SD card/MMC, the specified procedure is reversed.
When accessing SD_BUF0, pay attention to the transfer order in SDnDAT and the store order in SD_BUF. If required,
you can change the byte endian of the data read from or written to SD_BUF0 using the SDSWAP register. See Figure
41.6.
SDnDAT0
S
Start
Figure 41.2
7
0 15
8 23
Byte 0
Byte 1
16 31
Byte 2
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
Stop
Byte 3
SDnDAT in 1-bit width mode
SDnDAT3 S
7
3 15 11 23 19 31 27
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT2 S
6
2 14 10 22 18 30 26
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT1 S
5
1 13 9 21 17 29 25
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT0 S
4
0 12 8 20 16 28 24
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
Start Byte 0 Byte 1 Byte 2 Byte 3
Figure 41.3
24
Stop
SDnDAT in 4-bit width mode
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41. SD/MMC Host Interface (SDHI)
SDnDAT7 S
7 15 23 31 39 47 55 63
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT6 S
6 14 22 30 38 46 54 62
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT5 S
5 13 21 29 37 45 53 61
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT4 S
4 12 20 28 36 44 52 60
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT3 S
3 11 19 27 35 43 51 59
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT2 S
2 10 18 26 34 42 50 58
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT1 S
1
9 17 25 33 41 49 57
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
SDnDAT0 S
0
8 16 24 32 40 48 56
CRC16 CRC16
(15)
(14)
CRC16 CRC16
E
(1)
(0)
Start
Figure 41.4
Byte Byte Byte Byte Byte Byte Byte Byte
0
1
2
3
4
5
6
7
Stop
SDnDAT in 8-bit width mode
Word
LSB
31 30 29 28 27 26 25 24
0
23
Byte 3
23
Byte 7
15
16
23
Byte 511
8
7
6
5
Byte 1
8
7
6
5
Byte 5
16
3
2
1
0
4
3
2
1
0
2
1
0
Byte 4
15
Byte 510
4
Byte 0
15
Byte 6
31 30 29 28 27 26 25 24
127
16
Byte 2
31 30 29 28 27 26 25 24
1
Figure 41.5
MSB
8
7
6
5
Byte 509
4
3
Byte 508
SD_BUF store data
ꞏ 32-bit access, in the case where the data in SD_BUF0 are read without the bytes being swapped (EXT_SWAP: SDBRSWAP = 0)
bit 31
SD_BUF0
31
bit 0
30
29
28
27
26
25
24
23
Byte (4N+3)
ꞏꞏꞏ
16
15
Byte (4N+2)
ꞏꞏꞏ
8
7
6
5
Byte (4N+1)
4
3
2
1
26
25
0
Byte (4N)
ꞏ 32-bit access, in the case where the data in SD_BUF0 are read with the bytes being swapped (EXT_SWAP: SDBRSWAP = 1)
bit 31
SD_BUF0
7
bit 0
6
5
4
3
2
Byte (4N)
Figure 41.6
1
0
15
ꞏꞏꞏ
Byte (4N+1)
8
23
ꞏꞏꞏ
Byte (4N+2)
16
31
30
29
28
27
24
Byte (4N+3)
Read from SD_BUF0
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41.3.2
41. SD/MMC Host Interface (SDHI)
Card Detect/Write Protect
41.3.2.1
Card detect
The SD/MMC Host Interface has two types of card detect functions.
(1)
Card detect with SDnCD (n = 0, 1)
Figure 41.7 shows the timing for card detect using SDnCD. SDnCD is connected to the card socket and pulled up on the
host device. The resistance of the pull-up resistor is determined by the specification of the SD/MMC host device.
(2)
Card insertion
SDnCD is pulled down when a card is inserted. At this point, if SDnCD is pulled down for the Mcycle period (set in
SD_OPTION), SDCDIN in SD_INFO1 is set to 1. It is cleared by writing 0.
(3)
Card removal
SDnCD is pulled up when a card is removed. At this point, if SDnCD is pulled up for the Mcycle period (set in
SD_OPTION), SDCDRM in SD_INFO1 is set to 1. It is cleared by writing 0.
SDnCD
Without card
Card
detect
With card
Mcycle
SDnCD Card Insertion (SDCDIN)
Card
detect
Mcycle
Clear
SDnCD Card Removal (SDCDRM)
Figure 41.7
(4)
Without card
Clear
Example of card detect with SDnCD
SD card detect with SDnDAT3 (n = 0, 1)
Figure 41.8 shows the timing when the SD card is detected with SDnDAT3. In addition, SDnDAT3 is pulled down by the
host device, and the resistance value for pulling down is determined by the specification of the SD host device.
(5)
Card insertion
When an SD card is inserted, SDnDAT3 is pulled up and SDD3IN in SD_INFO1 is set to 1. It is cleared by writing 0.
(6)
Card removal
When an SD card is removed, SDnDAT3 is pulled down and SDD3RM in SD_INFO1 is set to 1. It is cleared by writing
0.
SDnDAT3
Without card
Card
detected
Without card
2 PCLKA
SDnDAT3 Card Insertion (SDD3IN)
SDnDAT3 Card Removal (SDD3RM)
Figure 41.8
Card
detected
Without card
2 PCLKA
Clear
Clear
SD card detect with SDnDAT3
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41.3.2.2
41. SD/MMC Host Interface (SDHI)
Write protect
The SD/MMC Host Interface has two types of write protect functions.
(1)
Write protect with SD0WP
SD0WP is connected to the card socket and pulled up or pulled down by the card insertion. The selection of pulling up or
pulling down and the resistance value is determined by the specification of the SD host device. When the SD0WP state is
reflected to SDWPMON in SD_INFO1, the write protect state is set after the SD card is inserted.
(2)
Write protect with command
The internal write protection of the card and the lock/unlock operation of the card are realized by the command.
41.3.3
41.3.3.1
Interrupt Request and DMA Transfer Request
Interrupts
Table 41.5 lists the SDHI interrupt sources. The SDHI requests an interrupt when:
The status flags in registers SD_INFO1, SD_INFO2, and SDIO_INFO1 set to 1
The associated bits in the SD_INFO1_MASK, SD_INFO2_MASK, and SDIO_INFO1_MASK registers are 0.
When clearing the status flags in registers SD_INFO1, SD_INFO2, and SDIO_INFO1, write 0 to the status flags to be
cleared, and write 1 to the status flags that are not being cleared.
Table 41.5
Interrupt sources
Status flag register
Interrupt sources
Register symbol
Card Access Interrupt SD_INFO1
(CACI)
SD_INFO2
Interrupt mask register
Bit symbol
Register symbol
Bit symbol
Ch 0
Ch 1
ACEND
SD_INFO1_MASK
ACENDM
SDHI_MM
C0_ACCS
SDHI_MM
C1_ACCS
SDHI_MM
C0_SDIO
SDHI_MM
C1_SDIO
SDHI_MM
C0_CARD
SDHI_MM
C1_CARD
RSPEND
ILA
RSPENDM
SD_INFO2_MASK
SDIO_INFO1
Card Detect Interrupt
(CDETI)
SD_INFO1
BWEM
BRE
BREM
RSPTO
RSPTOM
ILR
ILRM
ILW
ILWM
DTO
DTOM
ENDE
ENDEM
CRCE
CRCEM
EXWT
CMDEM
SDIO_INFO1_MASK
EXPUB52
SDD3IN
EXWTM
EXPUB52M
IOIRQ
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ILAM
BWE
CMDE
SDIO Access
Interrupt
(SDACI)
Interrupt name
IOIRQM
SD_INFO1_MASK
SDD3INM
SDD3RM
SDD3RMM
SDCDIN
SDCDINM
SDCDRM
SDCDRMM
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41.3.3.2
41. SD/MMC Host Interface (SDHI)
DMA transfer requests (SDHI_MMCn_ODMSDBREQ, n = 0 to 1)
The SD/MMC Host Interface has two types of DMA transfer requests.
(1)
SD_BUF write DMA transfer request
When the BWE bit in SD_INFO2 is set to 1 while the DMAEN bit in SD_DMAEN is set to 1, the SD_BUF
write DMA transfer request is asserted
The SD_BUF write DMA transfer request is negated when the last data in one block (based on the transfer data
size set in SD_SIZE) is transferred. The SD_BUF write DMA transfer request is also negated by clearing the
SDRST bit in SOFT_RST to 0 or setting the STP bit in SD_STOP to 1. However, if a communications error or
timeout occurs at the DMA transfer, the SD_BUF write DMA transfer request is not negated.
The BWE bit in SD_INFO2 is cleared after the transfer of the last data in one block following a request for
writing to SD_BUF by DMA transfer
The number of DMA transfers must be n x one block (n = integer, one block = the transfer data size set in
SD_SIZE)
When the IOABT bit in SDIO_MODE is set to 1, the SD_BUF write DMA transfer request is negated
The DMA transfer request is also negated by clearing the DMAEN bit to 0. However, the DMA transfer request
is asserted again when the DMAEN bit is set to 1 before writing to SD_CMD.
Because the BWE bit in SD_INFO2 is not cleared in response to setting of the STP/IOABT bit, or to a
communications error or timeout, clear the bit to 0 before issuing the next command. The next request to write to
SD_BUF by DMA transfer is not issued while the BWE bit is set.
(2)
SD_BUF read DMA transfer request
When the BRE bit in SD_INFO2 is set to 1 while the DMAEN bit in the SD_DMAEN register is set to 1, the
SD_BUF read DMA transfer request is asserted
The SD_BUF read DMA transfer request is negated when the last data in one block (based on the transfer data
size set in SD_SIZE) is transferred. The SD_BUF read DMA transfer request is also negated by clearing the
SDRST bit in SOFT_RST to 0 or setting the STP bit in SD_STOP to 1. However, if a communications error or
timeout occurs at the DMA transfer, the SD_BUF read DMA transfer request is not negated.
The BRE bit in SD_INFO2 is cleared after the transfer of the last data in one block following a request to write
to SD_BUF by DMA transfer
The number of DMA transfers must be n x one block (n = integer, one block = the transfer data size set in
SD_SIZE)
When the IOABT bit in SDIO_MODE is set to 1, the SD_BUF read DMA transfer request is negated
The DMA transfer request is also negated by clearing the DMAEN bit to 0. However, the DMA transfer request
is asserted again when the DMAEN bit is set to 1 before writing to SD_CMD.
Because the BRE bit in SD_INFO2 is not cleared in response to setting of the STP/IOABT bit or in response to
a communications error or timeout, clear the bit to 0 before issuing the next command. The next request to write
to SD_BUF by DMA transfer is not issued while the BRE bit is set.
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41.3.4
41. SD/MMC Host Interface (SDHI)
Communication Errors and Timeouts
When a communication error or timeout error occurs, depending on the type of error, the associated status flag in the
SD_INFO2 register is set to 1. Also, depending on the source of the error, the associated flag in the SD_ERR_STS1 or
SD_ERR_STS2 register is set to 1.
The status flags in SD_ERR_STS1 and SD_ERR_STS2 registers clear to 0 by writing to the SD_CMD register, or by
setting the SOFT_RST.SDRST bit to 0.
Table 41.6
Communication errors
Communication
error
Interrupt flag register
Error status register
Register symbol
Bit symbol
Register symbol
Bit symbol
This occurs when...
End bit error
SD_INFO2
ENDE
SD_ERR_STS1
CRCLENE
The CRC status token length is in error
RDLENE
The read data length is in error
RSPLENE1
The response length is in error*1
RSPLENE0
The response length is in error*2
CRCTKE
The CRC status token is in error
RDCRCE
There is a CRC error in the read data
RSPCRCE1
There is a CRC error in the response*1
RSPCRCE0
There is a CRC error in the response*2
CMDE1
The command index field value for the
transmitted command and received
response do not match*1
CMDE0
The command index field value for the
transmitted command and received
response do not match*2
CRC error
Command error
Note 1.
Note 2.
CRCE
CMDE
CMD12 when automatic issuing is enabled for multiple block transfer by the setting in SD_CMD, CMD12 when the STP bit in
SD_STOP is set to 1, or CMD52 when the C52PUB or IOABT bit in SDIO_MODE is set to 1.
CMD other than CMD12 when automatic issuing is enabled for multiple block transfer by the setting in SD_CMD, CMD12 when
the STP bit in SD_STOP is set to 1, or CMD52 when the C52PUB or IOABT bit in SDIO_MODE is set to 1.
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Table 41.7
41. SD/MMC Host Interface (SDHI)
Timeouts
Interrupt flag register
Error status register
Timeout
Register symbol
Bit symbol
Register symbol
Bit symbol
This occurs when...
Response
timeout
SD_INFO2
RSPTO
SD_ERR_STS2
RSPTO1
A response is not received even after a minimum
of 640 SDHI clock cycles elapse*1
RSPTO0
A response is not received even after a minimum
of 640 SDHI clock cycles elapse*2
CRCBSYTO
After the CRC status token is received, the SDHI
is busy for at least the period set*3
CRCTO
After the write data is transmitted, the CRC status
token is not received even after at least the
period set*3 elapses
RDTO
After the read command is issued, the read data
is not received even after at least the period set*3
elapses
Data
timeout
(excluding
response
timeout)
DTO
After the read data is received, the next block
read data is not received even after at least the
period set*3 elapses
After the SDHI exits the read wait state, the next
block read data is not received even after at least
the period set*3 elapses
Note 1.
Note 2.
Note 3.
BSYTO1
After CMD12 is issued during the command
sequence, the SDHI is busy for at least the period
set*3
BSYTO0
After the R1b response is received, the SDHI is
busy for at least the period set*3 (a command
other than CMD12 is issued during the command
sequence)
CMD12 when automatic issuing is enabled for multiple block transfer by the setting in SD_CMD, CMD12 when the STP bit in
SD_STOP is set to 1, or CMD52 when the C52PUB or IOABT bit in SDIO_MODE is set to 1.
CMD other than CMD12 when automatic issuing is enabled for multiple block transfer by the setting in SD_CMD, CMD12 when
the STP bit in SD_STOP bit is set to 1, or CMD52 when the C52PUB or IOABT bit in SDIO_MODE is set to 1.
The period is set in the SD_OPTION.TOP[3:0] bits.
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41.3.5
41. SD/MMC Host Interface (SDHI)
Command without Data Transfer (SD/MMC)
Figure 41.9 and Figure 41.10 show example flows.
Clear flag register
Set control register. See 41.4.5
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_ARG, Argument)
W (SD_CMD, Command)
Issue command without response and data
Response end
Flag clear
W (SD_INFO1, 0x0000 FFFE)
W (register name, value): Write to register
R (register name): Read from register
Figure 41.9
Example flow of command without response and data
Clear flag register
Set control register.
See 41.4.5.
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_ARG, Argument)
W (SD_CMD, Command)
Issue command without data
Error (communications error or timeout)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
Error processing (clear the interrupt flag register)
R (SD_RSP10)
Flag clear
Response check
W (register name, value): Write to register
R (register name): Read from register
Figure 41.10
Example flow of command without data
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41.3.5.1
41. SD/MMC Host Interface (SDHI)
Operation for command without data transfer
The following legend is used for the description of register read/write.
W (register name, value): Write to the register
R (register name): Read from the register
The operation is described in the following section.
(1)
Command without response and data
a. Flag register clear
First, clear the bits in the flag register (SD_INFO1 and SD_INFO2).
b. Control register set
Set the SD/MMC clock and interrupt masking (SD_CLK_CTRL, SD_INFO1_MASK, and SD_INFO2_MASK).
c. Command issue
Set CMD argument in SD_ARG and write to SD_CMD.
Accordingly, CMD is issued, and the operation is started.
d. Flag clear
When transmission of a command is complete, RSPEND (response end) in SD_INFO1 is set to 1 to generate an
interrupt. Clear RSPEND to 0.
(2)
Command without data
a. Flag register clear
First, clear the bits in the flag register (SD_INFO1 and SD_INFO2).
b. Control register set
Set the SD/MMC clock and interrupt masking (SD_CLK_CTRL, SD_INFO1_MASK, and SD_INFO2_MASK).
c. Command issue
Set CMD argument in SD_ARG and write to the SD_CMD.
Accordingly, CMD is issued, and the operation is started.
d. Flag clear
When a response is received, RSPEND (response end) in SD_INFO1 is set to 1 to generate an interrupt. Clear
RSPEND to 0.
e. Read a response from SD_RSP10. Additionally, perform error processing (clear the interrupt flag register) if a
communication error or timeout occurs.
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41.3.6
41. SD/MMC Host Interface (SDHI)
Single Block Read (SD/MMC)
Figure 41.11 shows an example flow of a single block read operation.
Clear flag register
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_SIZE, Transfer data size)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
Set control register
See 41.4.5.
W (SD_ARG, Argument)
W (SD_CMD, 0x0000 0011)
Issue CMD17
(single-block read)
Error (communications error or timeout)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
R (SD_RSP10)
W (SD_INFO1_MASK, 0x0000 FFFB)
W (SD_INFO2_MASK, 0x0000 7E80)
Flag clear
Response check
Enable the access end interrupt
Enable the BRE interrupt
Error (communications error or timeout)
BRE or error
W (SD_INFO2, 0x0000 FEFF)
Flag clear
R (SD_BUF0)
(amount of data specified by SD_SIZE)
Read data
Access end
Error processing (clear the interrupt flag
register)
W (SD_INFO1, 0x0000 FFFB)
Flag clear
W (register name, value): Write to register
R (register name): Read from register
Figure 41.11
Example flow of single block read operation
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41.3.6.1
41. SD/MMC Host Interface (SDHI)
Single block read operation
The operation of the single block read is described as follows:
a. Flag register clear
First, clear the bits in the flag register (SD_INFO1 and SD_INFO2).
b. Control register set
Set the SD/MMC clock, transfer data size, interrupt mask (SD_CLK_CTRL, SD_SIZE, SD_INFO1_MASK, and
SD_INFO2_MASK).
c. Command issue (CMD17)
Set CMD17 argument in SD_ARG and write 0x0000 0011 to SD_CMD. CMD17 is issued and the single block
read operation is started.
d. Response check
On receiving the response, RSPEND (response end) in SD_INFO1 is set to 1 to generate an interrupt. Clear
RSPEND to 0 and read the response from SD_RSP10. If the result of the response decoding is an error, the
command sequence can be halted by setting the STP bit in SD_STP or the IOABT bit in SDIO_MODE to 1. In
addition, this causes CMD12 and CMD52 to not be issued. If the ACEND bit (access end) in SD_INFO1 is set,
halting the command sequence also leads to the generation of an interrupt.
e. Data receive from SD card/MMC and data read
Write 0x0000 FFFB to SD_INFO1_MASK to enable the access end interrupt. In addition, write 0x0000 7E80 to
SD_INFO2_MASK to enable the BRE interrupt. When the data received from the SD card/MMC is complete,
the BRE bit in SD_INFO2 is set to 1 to generate an interrupt. Clear the BRE bit to 0 and read the amount of data
specified in SD_SIZE from SD_BUF0.
A communication error or timeout might be generated if data is being received while the reading of SD_BUF0 is
in progress.
f. Operation complete
When the data read from SD_BUF0 is complete, ACEND (access end) in SD_INFO1 is set to 1 to generate an
interrupt. Clear ACEND to 0 to end the single block read operation.
Additionally, perform error processing (clear the interrupt flag register) if a communication error or timeout
occurs.
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41.3.7
41. SD/MMC Host Interface (SDHI)
Single Block Write (SD/MMC)
Figure 41.12 shows an example flow of a single block write operation.
Clear flag register
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_SIZE, Transfer data size)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_ARG, Argument)
W (SD_CMD, 0x0000 0018)
Set control register
See 41.4.5.
Issue CMD24 (single-block write)
Error (communications error or timeout)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
R (SD_RSP10)
W (SD_INFO1_MASK, 0x0000 FFFB)
W (SD_INFO2_MASK, 0x0000 7D80)
Flag clear
Response check
Enable the access end interrupt
Enable the BWE interrupt
BWE
W (SD_INFO2, 0x0000 FDFF)
Flag clear
W (SD_BUF0, data)
(amount of data specified by SD_SIZE)
Write data
Error (communications error or timeout)
Error processing (clear the interrupt
flag register)
Access end or error
W (SD_INFO1, 0x0000 FFFB)
Flag clear
W (register name, value): Write to register
R (register name): Read from register
Figure 41.12
Example of single block write operation
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41.3.7.1
41. SD/MMC Host Interface (SDHI)
Single block write operation
The operation of the single block write is described as follows:
a. Flag register clear
First, clear the bits in the flag register (SD_INFO1 and SD_INFO2).
b. Control register set
Set the SD/MMC clock, transfer data size, interrupt mask (SD_CLK_CTRL, SD_SIZE, SD_INFO1_MASK, and
SD_INFO2_MASK).
c. Command issue (CMD24)
Set CMD24 argument in SD_ARG and write 0x0000 0018 to SD_CMD. CMD24 is issued and the single block
write operation is started.
d. Response check
On receiving the response, RSPEND (response end) in SD_INFO1 is set to 1 to generate an interrupt. Clear
RSPEND to 0 and read the response from SD_RSP10. If the result of response decoding is an error, the
command sequence can be halted by setting the STP bit in SD_STP or the IOABT bit in SDIO_MODE to 1. In
addition, this causes CMD12 and CMD52 to not be issued. If the ACEND bit (access end) in SD_INFO is set,
halting the command sequence also leads to the generation of an interrupt.
e. Data write and data transmit to SD card/MMC
Write 0x0000 FFFB to SD_INFO1_MASK to enable the access end interrupt. In addition, write 0x0000 7D80 to
SD_INFO2_MASK to enable the BWE interrupt. When SD_BUF0 is ready for the data to be written, the BWE
bit in SD_INFO2 is set to 1 to generate an interrupt. Clear the BWE bit to 0 and write the amount of data
specified in SD_SIZE to SD_BUF0. When the data write to SD_BUF0 is complete, data is transmitted to the SD
card. Then, the CRC status and busy state are received from the SD card/MMC.
However, a communications error or timeout might be generated if data is being transmitted after writing to
SD_BUF0.
f. Operation complete
When the CRC status and busy state are received from the SD card/MMC, ACEND (access end) in SD_INFO1
is set to 1 to generate an interrupt. Clear the ACEND bit to 0 to end the single block write operation.
In addition, perform error processing (clear the interrupt flag register) if a communication error or timeout
occurs.
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41.3.8
41. SD/MMC Host Interface (SDHI)
Multiple Block Read (SD/MMC)
Figure 41.13 shows an example flow of a multiple block read operation.
Clear flag register
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_SIZE, 0x0000 0200)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_STOP, 0x0000 0100)
W (SD_SECCNT, number of transfer blocks)
W (SD_ARG, Argument)
W (SD_CMD, 0x0000 0012)
Error (communications error or timeout)
Set control register
See 41.4.5.
Issue CMD18 (multiple-block read)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
R (SD_RSP54)
W (SD_INFO1_MASK, 0x0000 FFFB)
W (SD_INFO2_MASK, 0x0000 7E80)
Error (communications error or timeout)
Flag clear
Response check
Enable the access end interrupt
Enable the BRE interrupt
BRE or error
W (SD_INFO2, 0x0000 FEFF)
R (SD_BUF0)
(amount of data specified by SD_SIZE)
All block read completed?
N
Flag clear
Read data
Number of blocks set in
SD_SECCNT
Y
Access end
W (SD_INFO1, 0x0000 FFFB)
Error processing (clear the interrupt
flag register)
R (SD_RSP10)
Flag clear
Response check
W (register name, value): Write to register
R (register name): Read from register
Figure 41.13
Example of multiple block read operation
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41.3.8.1
41. SD/MMC Host Interface (SDHI)
Multiple block read operation
The operation of the multiple block read is described as follows:
a. Flag register clear
First, clear the bits in the flag register (SD_INFO1 and SD_INFO2).
b. Control register set
Set the SD/MMC clock, transfer data size, interrupt mask (SD_CLK_CTRL, SD_SIZE, SD_INFO1_MASK, and
SD_INFO2_MASK).
Set SEC in SD_STOP to 1, and set the number of transfer blocks in SD_SECCNT.
c. Command issue (CMD18)
Set CMD18 argument in SD_ARG and write 0x0000 0012 to SD_CMD. CMD18 is issued and the multiple
block read operation is started.
d. Response check
On receiving the response, RSPEND (response end) in SD_INFO1 is set to 1 to generate an interrupt. Clear
RSPEND to 0 and read the response from SD_RSP54. If the result of response decoding is an error, the
command sequence can be halted by setting the STP bit in SD_STP to 1. Setting the STP bit to 1 also causes
CMD12 to be issued and the response received. If the command sequence is halted because the access end
interrupt is enabled, an interrupt is generated when the ACEND bit (access end) bit in SD_INFO1 is set to 1 on
completion of response reception. Clear the ACEND bit to 0 and read the response.
e. Data receive from SD card/MMC and data read
Write 0x0000 FFFB to SD_INFO1_MASK to enable the access end interrupt. In addition, write 0x0000 7E80 to
SD_INFO2_MASK to enable the BRE interrupt. When reception of one-block of data from the SD card/MMC is
complete, the BRE bit in SD_INFO2 is set to 1 to generate an interrupt. Clear the BRE bit to 0 and read the
amount of data specified in SD_SIZE from SD_BUF0. Doing this repeats the transfer of the number of blocks
set in SD_SECCNT. However, a communication error or timeout might be generated if data is being received
while reading of SD_BUF0 is in progress. CMD12 is automatically issued to stop a multiblock transfer with the
number of blocks that is set to SD_SECCNT, and the response is received. At this point, CMD12 argument is
automatically set to 0x0000 0000.
f. Operation complete
When all-block data read and the CMD12 response received are completed, ACEND (access end) in SD_INFO1
is set to 1 to generate an interrupt. Clear ACEND to 0 to read the response. This is the end of a multiple block
read operation. In addition, perform error processing (clear the interrupt flag register) if a communication error
or timeout occurs.
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41.3.9
41. SD/MMC Host Interface (SDHI)
Multiple Block Write (SD/MMC Using Internal Timer)
Figure 41.14 shows an example flow of a multiple block write using the internal timer.
Clear flag register
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_SIZE, 0x0000 0200)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_STOP, 0x0000 0100)
W (SD_SECCNT, number of transfer blocks)
W (SD_ARG, Argument)
W (SD_CMD, 0x0000 0019)
Set control register
See 41.4.5.
Issue CMD25 (multiple-block write)
Error (communications error or timeout)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
R (SD_RSP54)
W (SD_INFO1_MASK, 0x0000 FFFB)
W (SD_INFO2_MASK, 0x0000 7D80)
Flag clear
Response check
Enable the access end interrupt
Enable the BWE interrupt
Error (communications error or timeout)
BWE or error
W (SD_INFO2, 0x0000 FDFF)
Flag clear
W (SD_BUF0, data)
(amount of data specified by SD_SIZE)
Write data
All block write completed?
N
Number of blocks set in SD_SECCNT
Y
Error (communications error or timeout)
Access end or error
W (SD_INFO1, 0x0000 FFFB)
Error processing (clear the interrupt
flag register)
R (SD_RSP10)
Flag clear
Response check
W (register name, value): Write to register
R (register name): Read from register
Figure 41.14
Example of multiple block write operation using internal timer
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41.3.9.1
41. SD/MMC Host Interface (SDHI)
Multiple block write operation using internal timer
The operation of a multiple block write is described as follows:
a. Flag register clear
First, clear the bits in the flag register (SD_INFO1 and SD_INFO2).
b. Control register set
Set the SD/MMC clock, transfer data size, interrupt mask (SD_CLK_CTRL, SD_SIZE, SD_INFO1_MASK, and
SD_INFO2_MASK).
Set the SEC bit in SD_STOP to 1, and set the number of transfer blocks in SD_SECCNT.
c. Command issue (CMD25)
Set the CMD25 argument in SD_ARG and write 0x0000 0019 to SD_CMD. CMD25 is issued and the multiple
block write operation is started.
d. Response check
On receiving the response, the RSPEND bit (response end) in SD_INFO1 is set to 1 to generate an interrupt.
Clear the RSPEND bit to 0 and read the response from SD_RSP54. If the result of response decoding is an error,
the command sequence can be halted by setting the STP bit in SD_STP to 1. Setting the STP bit to 1 also causes
CMD12 to be issued and the response is received. If the command sequence is halted because the access end
interrupt is enabled, an interrupt is generated by when the ACEND bit (access end) bit in SD_INFO1 is set to 1
on completion of response reception. Clear the ACEND bit to 0 and read the response.
e. Data write and data transmit to SD card/MMC
Write 0x0000 FFFB to SD_INFO1_MASK to enable the access end interrupt. In addition, write 0x0000 7D80 to
SD_INFO2_MASK to enable the BWE interrupt. When SD_BUF0 is ready for the data to be written, the BWE
bit in the SD_INFO2 resister is set to 1 to generate an interrupt. Clear the BWE bit to 0 and write the amount of
data specified in SD_SIZE to SD_BUF0. When the data write to SD_BUF0 is complete, data is transmitted to
the SD card/MMC. The CRC status and busy state are received from the SD card/MMC. This repeats the transfer
of the number of blocks set in SD_SECCNT. However, a communication error or timeout might be generated if
data is being received while writing to SD_BUF0 is in progress. CMD12 is automatically issued to stop
multiblock transfer with the number of blocks set in SD_SECCNT and the response is received. At this point,
CMD12 argument is automatically set to 0x0000 0000.
f. Operation complete
When all-block data transmit and the CRC status receive are completed, the ACEND bit (access end) in
SD_INFO1 is set to 1 to generate an interrupt. Clear the ACEND bit to 0 to read the response. This is the end of
a multiple block write operation. Additionally, perform error processing (clear the interrupt flag register) if a
communications error or timeout occurs.
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41.3.10
41. SD/MMC Host Interface (SDHI)
Multiple Block Write (MMC using external timer)
Figure 41.15 shows an example flow of a multiple block write using an external timer.
Clear flag register
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_SIZE, 0x0000 0200)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_STOP, 0x0000 0100)
W (SD_SECCNT, number of transfer blocks)
W (SD_ARG, Argument)
W (SD_CMD, 0x0000 6C36)
Set control register
See 41.4.5.
Issue CMD54 (multiple-block write)
Error (communications error or timeout)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
Flag clear
R (SD_RSP54)
Response check
Enable the access end interrupt
Enable the BWE interrupt
Set Timeout mask
External Timer start
W (SD_INFO1_MASK, 0x0000 FFFB)
W (SD_INFO2_MASK, 0x0000 7D80)
W (SD_OPTION, (TOUTMASK = 1))
Y
Error (communications error)?
N
Timeout by
external timer
BWE or error
W (SD_INFO2, 0x0000 FDFF)
Flag clear
W (SD_BUF0, data)
(amount of data specified by SD_SIZE)
Write data
All block write completed?
Y
N
Number of blocks set in SD_SECCNT
Access end or error
Software reset
W (SD_INFO1, 0x0000 FFFB)
Flag clear
Error processing (clear the interrupt
flag register)
W (register name, value): Write to register
R (register name): Read from register
Figure 41.15
Example of multiple block write operation using external timer
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41.3.10.1
41. SD/MMC Host Interface (SDHI)
Multiple block write operation using external timer
The operation of a multiple block write is described as follows:
a. Flag register clear
First, clear the bits in the flag register (SD_INFO1 and SD_INFO2).
b. Control register set
Set the MMC clock, transfer data size, interrupt mask (SD_CLK_CTRL, SD_SIZE, SD_INFO1_MASK, and
SD_INFO2_MASK).
Set the SEC bit in SD_STOP to 1, and set the number of transfer blocks in SD_SECCNT.
c. Command issue (CMD54)
Set CMD54 Argument in SD_ARG and write 0x0000 6C36 to SD_CMD. CMD54 is issued and the multiple
block write operation is started.
d. Response check
On receiving the response, the RSPEND bit (response end) in SD_INFO1 is set to 1 to generate an interrupt.
Clear the RSPEND bit to 0 and read the response from SD_RSP54. If the result of the response decoding is an
error, the command sequence can be halted by setting the STP bit in SD_STP to 1. Setting the STP bit to 1 also
causes CMD12 to be issued and the response is received. If the command sequence is halted because the access
end interrupt is enabled, an interrupt is generated by when the ACEND bit (access end) bit in SD_INFO1 is set to
1 on completion of the response reception. Clear the ACEND bit to 0 and read the response.
e. Data write and data transmit to MMC
Write 0x0000 FFFB to SD_INFO1_MASK to enable the access end interrupt, write 0x0000 7D80 to
SD_INFO2_MASK to enable the BWE interrupt, and set 1 to TOUTMASK of SD_OPTION to deactivate the
timeout. In addition, start the external timer. When SD_BUF0 is ready for the data to be written, the BWE bit in
the SD_INFO2 resister is set to 1 to generate an interrupt. Clear the BWE bit to 0 and write the amount of data
specified in SD_SIZE to SD_BUF0. When the data write to SD_BUF0 is complete, data is transmitted to the
MMC. The CRC status and busy state are received from the MMC. Doing this repeats the transfer of the number
of blocks set in SD_SECCNT. However, a communication error or timeout might be generated if data is being
received while writing to SD_BUF0 is in progress.
f. Operation complete
When all-block data transmit and the CRC status receive are completed, the ACEND bit (access end) in
SD_INFO1 is set to 1 to generate an interrupt. Clear the ACEND bit to 0 to read the response. This is the end of
a multiple block write operation. Additionally, perform error processing (clear the interrupt flag register) if a
communications error or timeout occurs when receiving a response. Execute software reset if a timeout by the
external timer occurs when transmitting data.
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41.3.11
41. SD/MMC Host Interface (SDHI)
IO_RW_DIRECT Command (SD: CMD52)
Figure 41.16 shows an example flow of an IO_DIRECT command (CMD52) operation.
Clear flag register
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SDIO_MODE, 0x0000 0001)
W (SDIO_INFO1_MASK, 0x0000 FFFE)
W (SD_ARG, Argument)
W (SD_CMD, 0x0000 0034)
Error (communications error or timeout)
Set control register
See 41.4.5.
Issue CMD52 (IO_RW_DIRECT command)
Response end or error
Flag clear
W (SD_INFO1, 0x0000 FFFE)
Error processing (clear the interrupt
flag register)
R (SD_RSP10)
Response check
W (register name, value): Write to register
R (register name): Read from register
Figure 41.16
41.3.12
Example of IO_RW_DIRECT command (CMD52) operation
IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Read)
Figure 41.17 shows an example flow for a CMD53 multiple block read operation.
Clear flag register
W (SD_CLK_CTRL, SD/MMC clock)
W (SD_SIZE, 0x0000 0200)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_STOP, 0x0000 0100)
W (SD_SECCNT, number of transfer blocks)
W (SDIO_MODE, 0x0000 0001)
W (SDIO_INFO1_MASK, 0x0000 3FFE)
W (SD_ARG, Argument)
W (SD_CMD, 0x0000 7C35)
Error (communications error or timeout)
Set control register
See 41.4.5.
Issue CMD53 (multiple-block read)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
R (SD_RSP10)
W (SD_INFO1_MASK, 0x0000 FFFB)
Flag clear
Response check
Enable the access end interrupt
Enable the BWE interrupt
W (SD_INFO2_MASK, 0x0000 7E80)
A
Error (communications error or timeout)
From C52PUB
BRE or error
W (SD_INFO2, 0x0000 FEFF)
Flag clear
R (SD_BUF0)
(amount of data specified by SD_SIZE)
Read data
All block read completed?
Number of blocks set in SD_SECCNT
N
Y
Error (communications error or timeout)
Error processing (clear the interrupt
flag register)
B
From IOABT
Access end or error
W (SD_INFO1, 0x0000 FFFB)
Flag clear
CMD53
completed
W (register name, value): Write to register
R (register name): Read from register
Figure 41.17
Example of IO_RW_EXTENDED command (CMD53) for multiple block read operation
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41. SD/MMC Host Interface (SDHI)
Figure 41.18 shows an example flow when CMD52 (SDIO abort) is issued during a CMD53 multiple block read.
IOABT start
W (SD_INFO2_MASK, 0x0000 FFFB)
W (SD_ARG, Argument)
W (SDIO_MODE, 0x0000 0101)
B
W (register name, value): Write to register
Figure 41.18
Flow when CMD52 (SDIO abort) is issued during a CMD53 multiple block read
Figure 41.19 shows an example flow when CMD52 (SDIO none abort) is issued at a CMD53 multiple block read while
the SDHI is in the read wait state.
RWREQ & C52PUB start
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_ARG, Argument)
W (SDIO_MODE, 0x0000 0205)
Error (communications error or timeout)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
Flag clear
R (SD_RSP10)
Response
check
Issue CMD52?
Error processing (clear the interrupt
flag register)
Release of the read wait state
Y
Response end, error flags
RWREQ clear
N
W (SDIO_MODE, 0x0000 0001)
W (SD_INFO1_MASK, 0x0000 FFFB)
W (SD_INFO2_MASK, 0x0000 7E80)
Access end and error
(Clear the interrupt flag register)
Access end, error flags
A
W (register name, value): Write to register
R (register name): Read from register
Figure 41.19
Flow when CMD52 (SDIO no abort) is issued during a CMD53 multiple block read while the SD
Host Interface is in read wait state
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41.3.13
41. SD/MMC Host Interface (SDHI)
IO_RW_EXTENDED Command (SD: CMD53/Multiple Block Write)
Figure 41.20 shows an example flow for a CMD53 multiple block write.
Clear flag register
W (SD_CLK_CTRL, SD clock)
W (SD_SIZE, 0x0000 0200)
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK,0x0000 7F80)
W (SD_STOP, 0x0000 0100)
W (SD_SECCNT,
number of transfer blocks)
W (SDIO_MODE, 0x0000 0001)
W (SDIO_INFO1_MASK, 0x0000 BFFE)
W (SD_ARG, Argument)
W (SD_CMD, 0x0000 6C35)
Set control register
See 41.4.5.
Issue CMD53 (multiple-block write)
Error (communications error or timeout)
Response end or error
W (SD_INFO1, 0x0000 FFFE)
R (SD_RSP10)
W (SD_INFO1_MASK, 0x0000 FFFB)
W (SD_INFO2_MASK, 0x0000 7D80)
Flag clear
Response check
Enable the access end interrupt
Enable the BWE interrupt
A
Error (communications error or timeout)
From C52PUB
BWE or error
W (SD_INFO2, 0x0000 FDFF)
Flag clear
W (SD_BUF0, data)
(amount of data specified by SD_SIZE)
Write data
All block write completed?
Number of blocks set in SD_SECCNT
N
Y
B
From IOABT
Error (communications error or timeout)
Access end or error
Error processing (clear the interrupt
flag register)
W (SD_INFO1, 0x0000 FFFB)
Flag clear
CMD53 completed
W (register name, value): Write to register
R (register name): Read from register
Figure 41.20
Example of IO_RW_EXTENDED command during a CMD53 multiple block write operation
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41. SD/MMC Host Interface (SDHI)
Figure 41.21 shows an example flow when CMD52 (SDIO abort) is issued at CMD53 multiple block write.
IOABT start
W (SD_INFO2_MASK, 0x0000 FFFB)
W (SD_ARG, Argument)
W (SDIO_MODE, 0x0000 0101)
B
W (register name, value): Write to register
Figure 41.21
Flow when CMD52 (SDIO Abort) is issued during a CMD53 multiple block write
Figure 41.22 shows an example flow when CMD52 (SDIO none abort) is issued at CMD53 multiple block write.
C52PUB start
W (SD_INFO1_MASK, 0x0000 FFFE)
W (SD_INFO2_MASK, 0x0000 7F80)
W (SD_ARG, Argument)
W (SDIO_MODE, 0x0000 0201)
Error (communications error or timeout)
Response end or error
Error processing (clear the interrupt
flag register)
IOABT set
Response end, error flags
W (SD_INFO1, 0x0000 FFFE)
Flag clear
R (SD_RSP10)
Response
check
Issue CMD52?
Y
N
SDIO abort
W (SDIO_MODE, 0x0000 0001)
Access end and error
W (SD_INFO1_MASK, 0x0000 FFFB)
W (SD_INFO2_MASK, 0x0000 7D80)
(Clear the interrupt flag register)
Access end, error flags
A
W (register name, value): Write to register
R (register name): Read from register
Figure 41.22
Flow when CMD52 (SDIO no abort) is issued during a CMD53 multiple block write
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41.3.14
41.3.14.1
41. SD/MMC Host Interface (SDHI)
DMA Transfer (SD/MMC)
SD_BUF DMA transfer
Figure 41.23 shows an example flow for SD_BUF DMA read when CMD18 multiple block read is issued.
Clear flag register
Set control register
W (SD_DMAEN, 0x0000 0002)
Set control register
See 41.4.5.
SD_BUF DMA transfer enabled
Issue CMD18
(multiple-block read command)
Error (communications error or timeout)
Response end or error
Flag clear
Response check
Set DMA controller
Error (communications error or timeout)
Access end or error
Flag clear
Response check
W (SD_DMAEN, 0x0000 0000)
Error processing (clear the interrupt flag register)
(SD_BUF DMA transfer disabled)
SD_BUF DMA transfer disabled
Set DMA controller
W (register name, value): Write to register
Figure 41.23
Example of SD_BUF_DMA read operation
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41. SD/MMC Host Interface (SDHI)
Figure 41.24 shows an example flow for SD_BUF DMA write when CMD25 multiple block write is issued.
Clear flag register
Set control register
W (SD_DMAEN, 0x0000 0002)
Set control register
See 41.4.5.
SD_BUF DMA transfer enabled
Issue CMD25
(multiple-block write command)
Error (communications error or timeout)
Response end or error
Flag clear
Response check
Set DMA controller
Error (communications error or timeout)
Access end or error
Flag clear
Response check
W (SD_DMAEN, 0x0000 0000)
Error processing (clear the interrupt flag register)
(SD_BUF DMA transfer disabled)
SD_BUF DMA transfer disabled
Set DMA controller
W (register name, value): Write to register
Figure 41.24
Example of SD_BUF_DMA write operation
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41.3.15
41. SD/MMC Host Interface (SDHI)
Example of SD_CMD Register Setting
Table 41.8 and Table 41.9 list the SD_CMD register setting.
Table 41.8
Example SD_CMD register settings for SD (1 of 2)
Type
Commamd
Example SD_CMD register setting
CMD
CMD0
0000 0000h
CMD2
0000 0002h
CMD3
0000 0003h
CMD4
0000 0004h
CMD5
0000 0705h or 0000 0005h
CMD6
0000 1C06h or 0000 0006h
CMD7
0000 0007h
CMD8
0000 0408h or 0000 0008h
CMD9
0000 0009h
CMD10
0000 000Ah
CMD11
0000 040Bh or 0000 000Bh
CMD12
0000 000Ch
CMD13
0000 000Dh
CMD15
0000 000Fh
CMD16
0000 0010h
CMD17
0000 0011h
CMD18
0000 0012h
CMD20
0000 0514h or 0000 0014h
CMD24
0000 0018h
CMD25
0000 0019h
CMD27
0000 001Bh
CMD28
0000 001Ch
CMD29
0000 001Dh
CMD30
0000 001Eh
CMD32
0000 0020h
CMD33
0000 0021h
CMD38
0000 0026h
CMD42
0000 002Ah
CMD52
0000 0434h or 0000 0034h
CMD53
Remark
When the card is placed in a deselected state, the response
timeout flag sets because there is no response.
With automatic CMD12
With automatic CMD12
0000 1C35h
Single read
0000 0C35h
Single write
0000 7C35h
Multiple read
0000 6C35h
Multiple write
0000 S0035h
The value on the left can be set for both single and multiple
operations. However, the CF39 bit in SD_ARG must be set
as follows.
Read: 0, Write: 1
CMD55
0000 0037h
CMD56
0000 0038h
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Table 41.8
41. SD/MMC Host Interface (SDHI)
Example SD_CMD register settings for SD (2 of 2)
Type
Commamd
Example SD_CMD register setting
ACMD
ACMD6
0000 0046h
ACMD13
0000 004Dh
ACMD22
0000 0056h
ACMD23
0000 0057h
Table 41.9
ACMD41
0000 0069h
ACMD42
0000 006Ah
ACMD51
0000 0073h
Remark
Example SD_CMD register settings for MMC (1 of 2)
Type
Command
Example SD_CMD register setting
CMD
CMD0
0000 0000h
Remark
CMD1
0000 0701h
CMD2
0000 0002h
CMD3
0000 0003h
CMD4
0000 0004h
CMD5
0000 0505h
CMD6
0000 0506h
With response busy
0000 0406h
Without response busy
CMD7
0000 0007h
When the card is placed in a deselected state, the response
timeout flag sets because there is no response
CMD8
0000 1C08h
CMD9
0000 0009h
CMD10
0000 000Ah
CMD12
0000 000Ch
CMD13
0000 000Dh
CMD14
0000 1C0Eh
CMD15
0000 000Fh
Required setting: SD_IFMODE = 0000 0100h (CRC check
is invalid)
CMD16
0000 0010h
CMD17
0000 0011h
CMD18
0000 7C12h
Pre-defined
CMD19
0000 0C13h
Required setting: SD_IFMODE = 0000 0100h (CRC check
is invalid)
CMD21
0000 1C15h
DDR mode is inhibited
CMD23
0000 0017h
CMD24
0000 0018h
CMD25
0000 6C19h
CMD26
0000 0C1Ah
CMD27
0000 001Bh
CMD28
0000 001Ch
CMD29
0000 001Dh
CMD30
0000 001Eh
CMD31
0000 1C1Fh
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Table 41.9
41. SD/MMC Host Interface (SDHI)
Example SD_CMD register settings for MMC (2 of 2)
Type
Command
Example SD_CMD register setting
Remark
CMD
CMD35
0000 0423h
-
CMD36
0000 0424h
-
CMD38
0000 0026h
-
CMD39
0000 0427h
-
41.4
CMD40
0000 0428h
-
CMD42
0000 002Ah
-
CMD49
0000 0C31h
-
CMD53
0000 7C35h
-
CMD54
0000 6C36h
-
CMD55
0000 0037h
-
CMD56
0000 0038h
-
Usage Notes
41.4.1
SD_BUF Illegal Write Access (SD/MMC)
When writing data to SD_BUF0 after a single block write or multi block write command is issued, data of the size
specified in SD_SIZE must be written.
If data exceeding the size specified in SD_SIZE is written, the ERR4 bit in SD_INFO2 is set to 1. In addition, the data
written to SD_BUF0 might not be transmitted and the SD_CLK_CTRLEN bit in SD_INFO2 is held at the value of 0. If
this occurs, clearing the SDRST bit in SOFT_RST to 0 and then restoring its value to 1 clears the SD_CLK_CTRLEN bit
to 1.
However, this does not apply to the single byte or three bytes when the SD_SIZE setting is odd, or to the fraction of bytes
when the SD_SIZE setting is even (the 2 bytes that are not in a 4-byte unit), because the portion of dummy data writing
is regarded as excess data and ignored.
41.4.2
Block Number Constraint for Multiple Block Read (SD)]
When performing a multiple block read of one or two blocks, depending on the timing with which the SD card response
register is read, the response value might not be read properly. To prevent this, do one of the following:
1. When receiving one or two blocks of data, use single block reading.
2. Read the response to CMD18 from SD_RSP54.
41.4.2.1
Mechanism of incorrect reading
Figure 41.25 shows the processing flows of the SDHI (hardware) operation and software operation when a multiple
block read is performed on two blocks. As shown in the incorrect operation in Figure 41.25, when an interrupt is
generated on reception of the CMD18 response and the timing with which the SD card response register (SD_RSP10) is
read by the interrupt is delayed, the data during the CMD12 response reception or the CMD12 response might be read.
This problem does not occur for multiple block reads of three or more blocks, because CMD12 is not issued until the
block of data is read. The problem also does not occur for multiple block writes, because the CMD25 response is read
before the block of data is sent.
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41. SD/MMC Host Interface (SDHI)
SDHI
(hardware) operation
Software operation
CMD18 issuance
processing
Issue CMD18
Receive response to
CMD18
Receive block data
Interrupt
Interrupt
Receive block data
+
Issue CMD12
Interrupt
Receive response to
CMD12
Interrupt
SDHI
(hardware) operation
Issue CMD18
Read the SD card
response register
(CMD18)
Receive response to
CMD18
Block data read 1
Receive block data
Block data read 2
Receive block data
+
Issue CMD12
Read the SD card
response register
(CMD12)
Receive response to
CMD12
Normal read
Figure 41.25
41.4.3
Software operation
CMD18 issuance
processing
Interrupt
X
Read the SD card
response register (?)
Illegal read
Multiple block read operation flow chart (two blocks)
Automatic Control of SD/MMC Clock Output (SD/MMC)
In the SD Card/MMC standard, 74 cycles of SD/MMC clock must be output before the initialization of the card. For this
reason, use automatic control of SD/MMC clock output after 74 cycles of SD/MMC clock are output. In addition, if
automatic control of SD/MMC clock output is in use, SD/MMC clock output is stopped on completion of the sequence
for a communications error or timeout. When state transitions within the SD card/MMC are necessary after the
completion of the sequence, release automatic control of the SD/MMC clock output and restart the supply of the
SD/MMC clock to the SD card/MMC.
41.4.4
Control of the C52PUB Setting for Multiple Block Write (SD)
If the C52PUB bit in SDIO_MODE is set to 1 during a sequence of multiple block writes because of CMD53, CMD52 is
not issued until SD_BUF becomes empty. For this reason, set the C52PUB bit after suspending writing to SD_BUF by
using one of the following procedures, as appropriate:
(a)
When DMA transfer is not in use
1. Before setting the C52PUB bit, suspend writing to SD_BUF by setting SD_INFO2 to disable BWE interrupts.
2. Set the C52PUB bit in SDIO_MODE to 1 (so that CMD52 is issued when SD_BUF becomes empty).
3. After the RSPEND interrupt processing in SD_INFO1 due to the issuing of CMD52 is complete, restart writing to
SD_BUF by setting SD_INFO2 to enable BWE interrupts.
(b)
When DMA transfer is in use
1. Every time a DMA transfer of the value set in SD_SIZE n blocks (where n = 1, 2,....) proceeds, suspend writing to
SD_BUF by DMA transfer before the C52PUB bit is set.
2. Set the C52PUB bit in SDIO_MODE to 1 so that CMD52 is issued when SD_BUF becomes empty.
3. After the RSPEND interrupt processing in SD_INFO1 due to the issuing of CMD52 is complete, restart writing to
SD_BUF by DMA transfer.
41.4.5
Notes on SD_CLK_CTRL Register Settings (SD/MMC)
When the SD_CLK_CTRLEN bit in SD_INFO2 is 0, SD_CLK_CTRL cannot be written to. Before writing to
SD_CLK_CTRL, you must check that the SD_CLK_CTRLEN bit in SD_INFO2 is 1.
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41.4.6
41. SD/MMC Host Interface (SDHI)
Specification Limitations
1. The Suspend/Resume operation of the SDIO is not supported.
2. The SPI bus is not supported (SD/MMC).
3. The shared bus and 8-bit SD bus of the embedded SDIO are not supported.
4. Stream transfer of MMC is not supported.
5. High Priority Interrupt (HPI) of MMC is not supported.
6. Boot Operation/Alternative Boot Operation of MMC is not supported.
7. Open-ended multiple block transfer of MMC is not supported.
41.4.7
STP Bit Setting during Multiple Block Read (SD/MMC)
During the execution of a multiple block read with automatic CMD12 execution by setting the SEC bit in SD_STOP to 1,
even if the STP bit in SD_STOP is set to 1 to forcibly stop the execution, the command sequence might not stop,
depending on the timing of setting of the STP bit.
To avoid this, when setting the STP bit in SD_STOP to 1 during multiple block transfer, clear the SEC bit in SD_STOP
to 0 at the same time. Even when the SD_CLK_CTRLEN bit in SD_INFO2 is 0, change the SEC bit from 1 to 0.
When the command sequence does not stop because the SEC bit was not cleared to 0, the command sequence can be
stopped by clearing the SDRST bit in SOFT_RST to 0.
When forcibly terminating the CMD53 multiple block transfer through the IOABT bit in SDIO_MODE, you must leave
the SEC bit in SD_STOP as 1.
41.4.8
Register Setting Notes
1. All registers in section 41.2, Register Descriptions are accessed in 32-bit access-only.
2. When setting registers, set them after the I/O Port Register setting.
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42. Parallel Data Capture Unit (PDC)
42.
Parallel Data Capture Unit (PDC)
42.1
Overview
The MCU provides one Parallel Data Capture Unit (PDC). The PDC communicates with external I/O devices, including
image sensors, and transfers parallel data such as image output from the external I/O device through the DTC or DMAC
to the on-chip SRAM and the external address spaces (the CS and SDRAM areas). Table 42.1 lists the PDC
specifications, Figure 42.1 shows a block diagram, and Table 42.2 lists the I/O pins.
Table 42.1
PDC specifications
Parameter
Specifications
Capture range
Any amount of parallel data within the following ranges in the vertical and
horizontal directions:
Vertical direction: 1 to 4095 lines
Horizontal direction: 4 to 4095 bytes.
Parallel transfer clock (PIXCLK)
Operating frequency: 1 to 27 MHz*1
Interrupt sources
Startup of DTC or DMAC
Frame end and receive data ready interrupts can start DTC or DMAC
Parallel transfer clock output (PCKO)
Operating frequency: 1 to 30 MHz*2
Clock source: Peripheral module clock B (PCLKB)
Frequency division ratio: Selectable from 2, 4, 6, 8, 10, 12, 14, and 16.
Other functions
Receive data ready
Frame end
Overrun
Underrun
Error in the setting for the number of lines
Error in setting for the number of bytes per line.
PDC reset function
Selectable active polarity for VSYNC and HSYNC signals
Monitoring of VSYNC and HSYNC signals
Endian order selectable.
Module-stop function
Module-stop state can be set to reduce power consumption
Internal bus interface
Internal peripheral bus 5
Note 1.
Note 2.
Set the frequency of the parallel data transfer clock (PIXCLK) to a value less than that of 0.6 × PCLKB (peripheral module
clock).
The operating frequency is 30 MHz when peripheral module clock B (PCLKB) frequency is 60 MHz and the frequency division
ratio is 2.
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42. Parallel Data Capture Unit (PDC)
PDC_PCDFI
PDC_PCFEI
PDC_PCERI
Interrupt
controller
PCCR0
PCCR1
HCR
PCMONR
PCDR register
VSYNC
HSYNC
Interface
controller
22-stage FIFO
(32-bit size)
PCDR
PIXCLK
Internal peripheral bus 5
PCSR
Bus interface controller
VCR
PIXD7 to
PIXD0
PCKO
Figure 42.1
Table 42.2
Prescaler
Peripheral module clock B
(PCLKB)
PDC block diagram
PDC I/O pins
Pin name
I/O
Description
PIXCLK
Input
Parallel transfer clock
VSYNC
Input
Vertical synchronization signal
HSYNC
Input
Horizontal synchronization signal
PIXD7 to PIXD0
Input
8-bit data
PCKO
Output
Output for the parallel transfer clock
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42.2
42. Parallel Data Capture Unit (PDC)
Register Descriptions
42.2.1
PDC Control Register 0 (PCCR0)
Address(es): PDC.PCCR0 4009 4000h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
EDS
OVIE
FEIE
DFIE
PRST
HPS
VPS
PCKE
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
PCKDIV[2:0]
0
0
PCKOE HERIE VERIE UDRIE
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PCKE
PIXCLK Input Enable
0: Disable PIXCLK input
1: Enable PIXCLK input.
R/W
b1
VPS
VSYNC Signal Polarity Select
0: Set VSYNC signal to active-high
1: Set VSYNC signal to active-low.
R/W
b2
HPS
HSYNC Signal Polarity Select
0: Set HSYNC signal to active-high
1: Set HSYNC signal to active-low.
R/W
b3
PRST
PDC Reset
0: Do not apply PDC reset
1: Reset PDC.
R/(W)
*1
b4
DFIE
Receive Data Ready Interrupt Enable
0: Disable receive data ready interrupt requests
1: Enable receive data ready interrupt requests.
R/W
b5
FEIE
Frame End Interrupt Enable
0: Disable frame end interrupt requests
1: Enable frame end interrupt requests.
R/W
b6
OVIE
Overrun Interrupt Enable
0: Disable overrun interrupt requests
1: Enable overrun interrupt requests.
R/W
b7
UDRIE
Underrun Interrupt Enable
0: Disable underrun interrupt requests
1: Enable underrun interrupt requests.
R/W
b8
VERIE
Vertical Line Number Setting Error Interrupt
Enable
0: Disable vertical line number setting error interrupt
requests
1: Enable vertical line number setting error interrupt
requests.
R/W
b9
HERIE
Horizontal Byte Number Setting Error
Interrupt Enable
0: Disable horizontal byte number setting error
interrupt requests
1: Enable horizontal byte number setting error
interrupt requests.
R/W
b10
PCKOE
PCKO Output Enable
0: Disable PCKO output (fix to high level)
1: Enable PCKO output.
R/W
b13 to b11
PCKDIV[
2:0]
PCKO Frequency Division Ratio Select
b13 b11
R/W
b14
EDS
Endian Select
0: Little endian
1: Big endian.
R/W
b31 to b15
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note 1.
0 0 0: PCLKB/2
0 0 1: PCLKB/4
0 1 0: PCLKB/6
0 1 1: PCLKB/8
1 0 0: PCLKB/10
1 0 1: PCLKB/12
1 1 0: PCLKB/14
1 1 1: PCLKB/16.
Only 1 can be written to this bit.
Only set the PCCR0 register while the PCE bit in the PCCR1 register is 0.
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42. Parallel Data Capture Unit (PDC)
PCKE bit (PIXCLK Input Enable)
The PCKE bit enables or disables input through the PIXCLK pin. Set this bit to 1 before enabling reception. After
enabling input through the PIXCLK pin, use the PRST bit to initialize the PDC.
Disable reception operations before setting this bit to 0.
VPS bit (VSYNC Signal Polarity Select)
The VPS bit selects the active polarity of the VSYNC signal.
HPS bit (HSYNC Signal Polarity Select)
The HPS bit selects the active polarity of the HSYNC signal.
PRST bit (PDC Reset)
The PRST bit initializes the internal status of the PDC and the PDC registers targeted by reset. See section 42.3.11, Reset
State, for the target registers. Set the PCKE bit to 1 before resetting the PDC.
When 1 is written to the PRST bit, initialization starts in synchronization with the PIXCLK. After initialization
completes, the PRST bit clears to 0. After a PDC reset, ensure that the PIXCLK pin has an input signal. Also, after 1 is
written to the PRST bit, do not proceed to the next step until after verifying that the bit has returned to 0.
For consecutive PDC resets, wait for at least 1 PIXCLK cycle after verifying that the PRST bit has returned to 0.
DFIE bit (Receive Data Ready Interrupt Enable)
The DFIE bit enables or disables the generation of receive data ready interrupt requests.
FEIE bit (Frame End Interrupt Enable)
The FEIE bit enables or disables the generation of frame end interrupt requests.
OVIE bit (Overrun Interrupt Enable)
The OVIE bit enables or disables the generation of overrun interrupt requests.
UDRIE bit (Underrun Interrupt Enable)
The UDRIE bit enables or disables the generation of underrun interrupt requests.
VERIE bit (Vertical Line Number Setting Error Interrupt Enable)
The VERIE bit enables or disables the generation of vertical line number setting error interrupt requests.
HERIE bit (Horizontal Byte Number Setting Error Interrupt Enable)
The HERIE bit enables or disables the generation of horizontal byte number setting error interrupt requests.
PCKOE bit (PCKO Output Enable)
The PCKOE bit enables or disables an output from the PCKO. When the PCKOE bit is cleared to 0 during a low output
of PCKO, it might cause a high output on clearing, resulting in corruption of the duty cycle.
PCKDIV[2:0] bits (PCKO Frequency Division Ratio Select)
The PCKDIV[2:0] bits select the frequency division ratio of the PCKO. The PCKO output is a clock signal derived by
dividing the PCLKB clock signal by a value from 2 to 16, based on the setting in the PCKDIV[2:0] bits. The PCKO
operating frequency, the resulting PCLKB division, must fall within the range from 1 to 30 MHz.
EDS bit (Endian Select)
The EDS bit selects the endian order for the captured data.
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42.2.2
42. Parallel Data Capture Unit (PDC)
PDC Control Register 1 (PCCR1)
Address(es): PDC.PCCR1 4009 4004h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PCE
PDC Operation Enable
0: Disable reception operation
1: Enable reception operation.
R/W
b31 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
PCE bit (PDC Operation Enable)
The PCE bit enables or disables reception operation. When the PCE bit is set to 1 during assertion of the VSYNC signal,
the PDC starts reception operation from the next valid edge of the VSYNC signal.
Only clear the PCE bit to 0 while reception or continued reception operations are stopped, including for the frame end
interrupt. For more on continued reception, see section 42.3.6, Continued Reception Operations at Frame End.
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42.2.3
42. Parallel Data Capture Unit (PDC)
PDC Status Register (PCSR)
Address(es): PDC.PCSR 4009 4008h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
HERF
VERF
UDRF
OVRF
FEF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
FEMPF FBSY
1
0
Bit
Symbol
Bit name
Description
R/W
b0
FBSY
Frame Busy Flag
0: Reception operations are stopped
1: Reception operations are ongoing.
R
b1
FEMPF
FIFO Empty Flag
0: FIFO is not empty
1: FIFO is empty.
R
b2
FEF
Frame End Flag
0: No frame end occurred
1: Frame end occurred.
R/(W)
*1
b3
OVRF
Overrun Flag
0: No FIFO overrun occurred
1: FIFO overrun occurred.
R/(W)
*1
b4
UDRF
Underrun Flag
0: No underrun occurred
1: Underrun occurred.
R/(W)
*1
b5
VERF
Vertical Line Number Setting Error Flag
0: No vertical line number setting error occurred
1: Vertical line number setting error occurred.
R/(W)
*1
b6
HERF
Horizontal Byte Number Setting Error Flag
0: No horizontal byte number setting error occurred
1: Horizontal byte number setting error occurred.
R/(W)
*1
b31 to b7
—
Reserved
These bits are read as 0. The write value should be 0. R
Note 1.
Only 0 can be written to these flags, to clear them after they are read as 1.
FBSY flag (Frame Busy Flag)
The FBSY flag indicates the state of PDC operations.
[Setting condition]
On detection of the valid edge of the VSYNC signal after the enabling of reception operations.
[Clearing conditions]
On reception of one frame of data in accordance with the settings in the VCR and HCR registers*1
When an overrun, underrun, vertical line number setting error, or horizontal byte number setting error occurs
When the PCCR1.PCE bit is 0.
Note 1. This flag is 0 during continued reception operations.
FEMPF flag (FIFO Empty Flag)
The FEMPF flag indicates the state of the FIFO when a vertical line number setting error or a horizontal byte number
setting error occurs. It clears to 0 following an overrun and is undefined following an underrun.
[Setting conditions]
On reading of the PCDR register while the FIFO is empty
On detection of a valid edge of the VSYNC signal
On PDC reset.
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42. Parallel Data Capture Unit (PDC)
[Clearing condition]
On storage of the data captured in the FIFO.
FEF flag (Frame End Flag)
The FEF flag indicates the end of a frame.
[Setting condition]
Reception of one frame of data in accordance with the settings in the VCR and HCR registers.*1
[Clearing conditions]
On PDC reset
On writing 0 to the flag after it is read as 1.
Note 1. For continued reception operations, this flag is set to 1 on their completion.
OVRF flag (Overrun Flag)
The OVRF flag indicates the occurrence of an overrun.
[Setting condition]
When receive data arrives while the FIFO is full.
[Clearing conditions]
On PDC reset
On writing 0 to the flag after it is read as 1.
UDRF flag (Underrun Flag)
The UDRF flag indicates the occurrence of an underrun.
[Setting condition]
On reading of the PCDR register while the FIFO is empty.
[Clearing conditions]
On PDC reset
On writing 0 to the flag after it is read as 1.
VERF flag (Vertical Line Number Setting Error Flag)
The VERF flag indicates an error in the setting for the number of lines.
[Setting condition]
When the VSYNC signal is negated because fewer lines were captured than the value in the VCR register.
[Clearing conditions]
On PDC reset
On writing 0 to the flag after it is read as 1.
HERF flag (Horizontal Byte Number Setting Error Flag)
The HERF flag indicates an error in the number of bytes in a line.
[Setting condition]
When the HSYNC signal is negated because fewer bytes in a line were captured than the value in the HCR register.
[Clearing conditions]
On PDC reset
On writing 0 to the flag after it is read as 1.
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42.2.4
42. Parallel Data Capture Unit (PDC)
PDC Pin Monitor Register (PCMONR)
Address(es): PDC.PCMONR 4009 400Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSYNC VSYNC
0
0
Bit
Symbol
Bit name
Description
R/W
b0
VSYNC
VSYNC Signal Status Flag
0: VSYNC signal level is low
1: VSYNC signal level is high.
R
b1
HSYNC
HSYNC Signal Status Flag
0: HSYNC signal level is low
1: HSYNC signal level is high.
R
b31 to b2
—
Reserved
These bits are read as 0.
R
VSYNC flag (VSYNC Signal Status Flag)
The VSYNC flag indicates the state of the VSYNC signal.
HSYNC flag (HSYNC Signal Status Flag)
The HSYNC flag indicates the state of the HSYNC signal.
42.2.5
PDC Receive Data Register (PCDR)
Address(es): PDC.PCDR 4009 4010h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The FIFO is mapped to the 4-byte
PCDR register and four bytes of data are read from the PCDR register at a time. The receive data ready flag sets for every
32 bytes of received data, and this also results in a receive data ready interrupt if the DFIE bit in the PCCR0 register is set
to 1. When a receive data ready interrupt is generated, read the PCDR register eight times. Figure 42.2 shows a schematic
view of the PCDR register.
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42. Parallel Data Capture Unit (PDC)
Internal peripheral bus 5
PCDR register
VSYNC
22-stage FIFO
(32-bit size)
Interface
controller
HSYNC
PCDR
PIXCLK
PIXD7 to
PIXD0
Figure 42.2
Schematic view of PCDR register
For the format of the captured data, either big or little endian can be selected in the EDS bit of the PCCR0 register. Figure
42.3 shows the data arrangements for the endian formats.
Big Endian
Read from
the PCDR register
Little Endian
31
0
31
0
First time
Byte 0
Byte 1
Byte 2
Byte 3
Byte 3
Byte 2
Byte 1
Byte 0
Second time
Byte 4
Byte 5
Byte 6
Byte 7
Byte 7
Byte 6
Byte 5
Byte 4
nth*1 time
Byte 4(n-1)
Byte 4(n-1) + 1 Byte 4(n-1) + 2 Byte 4(n-1) + 3
Byte 4(n-1) + 3 Byte 4(n-1) + 2 Byte 4(n-1) + 1
Byte 4(n-1)
Note 1. n = Number of reads of the PCDR register
Figure 42.3
Endian formats
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42.2.6
42. Parallel Data Capture Unit (PDC)
Vertical Capture Register (VCR)
Address(es): PDC.VCR 4009 4014h
b31
b30
b29
b28
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
0
0
0
0
Value after reset:
Value after reset:
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
0
0
0
0
0
VSZ[11:0]
VST[11:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b11 to b0
VST[11:0]
Vertical Capture Start Line Position
These bits specify the number of the line where
capture is to start
R/W
b15 to b12
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b27 to b16
VSZ[11:0]
Vertical Capture Size
These bits specify the number of lines to be captured
b31 to b28
—
Reserved
These bits are read as 0. The write value should be 0. R/W
R/W
For the relationship between the VCR register setting and the capture range, see section 42.3.3, VCR and HCR Register
Settings and the Capture Range. Only set the VCR register while the PCE bit in the PCCR1 register is 0.
VST[11:0] bits (Vertical Capture Start Line Position)
The VST[11:0] bits specify the number of the line where the capture is to start. To set the first line, set these bits to 000h;
to set the 4095th line, set them to FFEh. The VST[11:0] setting must be within the range from 000h to FFEh and, in
combination with the VSZ[11:0] setting, satisfy the following relationship:
Setting range of the VST[11:0] bits: 1 ≤ VST[11:0] + VSZ[11:0] ≤ FFFh.
VSZ[11:0] bits (Vertical Capture Size)
The VSZ[11:0] bits specify the number of lines to be captured. To set one line, set these bits to 001h; to set 4095 lines, set
them to FFFh. The VSZ[11:0] setting must be within the range from 001h to FFFh and, in combination with the
VST[11:0] setting, satisfy the following relationship:
Setting range of the VSZ[11:0] bits: 1 ≤ VST[11:0] + VSZ[11:0] ≤ FFFh.
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42.2.7
42. Parallel Data Capture Unit (PDC)
Horizontal Capture Register (HCR)
Address(es): PDC.HCR 4009 4018h
b31
b30
b29
b28
—
—
—
—
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
0
0
0
0
Value after reset:
Value after reset:
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
0
0
0
0
0
HSZ[11:0]
HST[11:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b11 to b0
HST[11:0]
Horizontal Capture Start Byte Position
These bits specify the horizontal position in bytes
where capture is to start
R/W
b15 to b12
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b27 to b16
HSZ[11:0]
Horizontal Capture Size
These bits specify the number of bytes to be captured
horizontally
b31 to b28
—
Reserved
These bits are read as 0. The write value should be 0. R/W
R/W
For the relationship between the HCR register setting and the capture range, see section 42.3.3, VCR and HCR Register
Settings and the Capture Range. Only set the HCR register while the PCE bit in the PCCR1 register is 0.
HST[11:0] bits (Horizontal Capture Start Byte Position)
The HST[11:0] bits specify the horizontal position in bytes where the capture is to start. To set the first byte, set these bits
to 000h; to set the 4092th byte, set them to FFBh. The HST[11:0] setting must be within the range from 000h to FFBh
and, in combination with the HSZ[11:0] setting, satisfy the following relationship:
Setting range of the HST[11:0] bits: 1 ≤ HST[11:0] + HSZ[11:0] ≤ FFFh.
HSZ[11:0] bits (Horizontal Capture Size)
The HSZ[11:0] bits specify the number of bytes to be captured per line. To set four bytes, set these bits to 004h; to set
4095 bytes, set them to FFFh. The HSZ[11:0] setting must be within the range from 004h to FFFh and, in combination
with the HST[11:0] setting, satisfy the following relationship:
Setting range of the HSZ[11:0] bits: 1 ≤ HST[11:0] + HSZ[11:0] ≤ FFFh.
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42.3
42. Parallel Data Capture Unit (PDC)
Operation
42.3.1
Transfer Formats
The PDC supports the four transfer formats shown in Figure 42.4 to Figure 42.7. The format is determined by the settings
in the VPS and HPS bits in the PCCR0 register.
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
PIXD valid period
Figure 42.4
PIXD valid period
PIXD valid period
PDC transfer format when VPS = 0 and HPS = 0
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
PIXD valid period
Figure 42.5
PIXD valid period
PIXD valid period
PDC transfer format when VPS = 1 and HPS = 0
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
PIXD valid period
Figure 42.6
PIXD valid period
PIXD valid period
PDC transfer format when VPS = 0 and HPS = 1
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42. Parallel Data Capture Unit (PDC)
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
PIXD valid period
PIXD valid period
PDC transfer format when VPS = 1 and HPS = 1
Figure 42.7
42.3.2
PIXD valid period
Transfer Timing
Figure 42.8 and Table 42.3 show the timing of transfers by the PDC.
t VACT
t VBL
t VBP
t HACT
t HBL
t VFP
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
Figure 42.8
Table 42.3
PDC transfer timing when VPS = 0 and HPS = 0
PDC transfer timing when VPS = 0 and HPS = 0
Parameter
Symbol
Min*1
Max
Unit
Vertical blanking period
tVBL
128
-
PIXCLK
Vertical backporch
tVBP
10
-
PIXCLK
Horizontal valid period
tHACT
4
4095
PIXCLK
Horizontal blanking period
tHBL
128
-
PIXCLK
Vertical frontporch
tVFP
10
-
PIXCLK
Vertical valid period
tVACT
1
4095
Line
Note 1.
The minimum values are that the lowest the PDC is capable of achieving. Operation at these values cannot guarantee the
avoidance of overruns, the vertical line number setting errors, or the horizontal byte number setting errors.
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42.3.3
42. Parallel Data Capture Unit (PDC)
VCR and HCR Register Settings and the Capture Range
Figure 42.9 and Figure 42.10 show the relationship between the settings in the VCR and HCR registers and the capture
range.
t VBP
1
2
4094 4095
Capture range
4095× 4095
1
2
4095 (VCR.VSZ = FFFh)
t VACT
4094 4095
tVFP
4095 (HCR.HSZ = FFFh)
t HACT
Figure 42.9
tHBL
Settings in the VCR and HCR registers and the capture range when VCR = 0FFF 0000h and HCR =
0FFF 0000h
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42. Parallel Data Capture Unit (PDC)
t VBP
1
2
3
1282
4095
1
2
3
1282
4095
1
2
3
1282
4095
Capture range
1280 × 480
VGA (YUV422)
1
2
3
2 (VCR.VST = 002h)
t VACT
480 (VCR.VSZ = 1E0h)
1282
4095
2 (HCR.HST = 002h) 1280 (HCR.HSZ = 500h)
1
2
3
4094 4095
t VFP
t HACT
Figure 42.10
t HBL
Settings in the VCR and HCR registers and the capture range when VCR = 01E0 0002h and HCR =
0500 0002h
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42.3.4
42. Parallel Data Capture Unit (PDC)
Reception Operation
Figure 42.11 shows an example of reception operations when receive data ready interrupts (to start the DTC or DMAC)
and frame end interrupts are in use.
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
(4)
PCCR1.PCE
(3)
(1)
PCSR.FBSY
PCSR.FEMPF
Receive data ready interrupt
(2)
PCSR.FEF
Figure 42.11
(3)
(4)
Example of reception operations
This section describes the actual operations at the times indicated by (1), (2), (3), and (4) in Figure 42.11.
When a valid edge of the VSYNC signal is detected after the PCE bit in the PCCR1 register is set to 1, the FEMPF flag
in the PCSR register is set to 1, and the FIFO is initialized. Concurrently, the FBSY flag in the PCSR register is set to 1
and reception operations start.
When data within the capture range set in the VCR and HCR registers is received, the data is stored in the FIFO. The
PDC generates a receive data ready interrupt every time it receives 32 bytes of data, and the interrupt starts the transfer of
the captured data by the DTC or DMAC to the on-chip SRAM or an external address space. The FIFO is likely to
overrun if reading of the PCDR register takes more time than reception of the data. Check the OVRF flag in the PCSR
register to verify an overrun.
After the reception of the last byte of data is complete, the FBSY flag in the PCSR register clears to 0 and the FEF flag in
the PCSR register is set to 1 so that a receive data ready interrupt and frame end interrupt are generated.
The FEMPF flag in the PCSR register is polled by the frame end interrupt, after which the program must verify the
completion of data transfer by the DTC or DMAC. After the PCE bit in the PCCR1 register is cleared to 0, the FEF flag
in the PCSR register also clears to 0, and the reception of one frame of data is complete.
If the FEF flag in the PCSR register is set to 1 before the PCE bit in the PCCR1 register is set to 1, valid edges of the
VSYNC signal are not detected, and reception operations are not started. Clear the FEF flag in the PCSR register to 0 to
start the data reception operations.
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42.3.5
42. Parallel Data Capture Unit (PDC)
Operation during Horizontal Blanking Period
If the horizontal blanking period begins but the number of received data bytes has not reached 32 bytes since the previous
receive data ready, the count of the received data bytes is retained and carried over to the next valid period. Figure 42.12
shows an example of operation during the horizontal blanking period.
Number of writes to the FIFO
16
0
16
32
PIXCLK
VSYNC
HSYNC
16 bytes
16 bytes
PIXD7 to
PIXD0
PCSR.FBSY
PCSR.FEMPF
Receive data ready interrupt
PCSR.FEF
Figure 42.12
42.3.6
Example operation during horizontal blanking period
Continued Reception Operations at Frame End
When the last of the data is received but fewer than 32 bytes of data have been received since the previous receive data
ready, the PDC continues to receive data until the number reaches 32, in an operation called continued reception. When
continued reception ends, the PDC generates a receive data ready interrupt and a frame end interrupt. Always input
PIXCLK during continued reception. If the data stored in the FIFO is read during this operation, the values are
undefined. Figure 42.13 shows an example operation at frame end.
Number of writes to the FIFO
16
0
20
25
30
32
PIXCLK
VSYNC
HSYNC
16 bytes
PIXD7 to
PIXD0
PCSR.FBSY
PCSR.FEMPF
Receive data ready interrupt
PCSR.FEF
Figure 42.13
Example of continued reception operations at frame end
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42.3.7
42. Parallel Data Capture Unit (PDC)
Error Detection
The PDC provides error detection capabilities, enabling software to respond to errors during reception operations. Table
42.4 summarizes the conditions for each type of error and the interrupt flags that are set in response.
Table 42.4
Error detection
Error factor
Conditions for error detection
Interrupt flag
full*1
Operation example
Overrun
Receive data arrives while the FIFO is
PCSR.OVRF
Figure 42.14
Underrun
PCDR register is read while the FIFO is empty
PCSR.UDRF
Figure 42.15
Vertical line number error
VSYNC signal is negated when the number of captured lines
is less than the value set in the VCR register
PCSR.VERF
Figure 42.16
Horizontal byte number
error
HSYNC signal is negated when the number of bytes
captured in a line is less than the value set in the HCR
register
PCSR.HERF
Figure 42.17
Note 1.
This includes data reception during continued reception operations.
When an error is detected, the PDC sets the associated interrupt flag to 1 to stop reception operations. While the interrupt
flag is 1, the PDC does not detect the valid edges of the VSYNC signal and does not start reception operations. Clear all
the error source interrupt flags to 0 to start reception operations.
When an error occurs, data stored in the FIFO is disabled.
Write to the FIFO
attempted while FIFO is full
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
PCSR.FBSY
PCSR.FEMPF
Receive data ready interrupt
PCSR.OVRF
PCSR.UDRF
Figure 42.14
Operation when an overrun is detected
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42. Parallel Data Capture Unit (PDC)
Read from the PCDR register
attempted while the FIFO is empty
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
PCSR.FBSY
PCSR.FEMPF
Undefined
Receive data ready interrupt
PCSR.OVRF
PCSR.UDRF
Figure 42.15
Operation when an underrun is detected
VSYNC signal is negated because fewer
lines were captured than the value in the
VCR register
Waveform that would be expected
from the setting in the VCR register
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
PCSR.FBSY
PCSR.FEMPF
Receive data ready interrupt
PCSR.FEF
PCSR.VERF
Figure 42.16
Operation when a vertical line number setting error is detected
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42. Parallel Data Capture Unit (PDC)
HSYNC signal is negated because fewer
bytes in the line were captured than the
value in the HCR register
Waveform that would be expected
from the setting in the HCR register
PIXCLK
VSYNC
HSYNC
PIXD7 to
PIXD0
PCSR.FBSY
PCSR.FEMPF
Receive data ready interrupt
PCSR.FEF
PCSR.HERF
Figure 42.17
42.3.8
Operation when a horizontal byte number setting error is detected
Initial Settings
Figure 42.18 shows an example flow for initial settings. For a description of how to set up the input and output ports and
the Interrupt Controller Unit (ICU), see the descriptions provided in the sections on the relevant blocks.
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42. Parallel Data Capture Unit (PDC)
Start of initialization
Set the input/output ports
Set the Interrupt Controller Unit
No
PCCR1.PCE = 0
[1]
[1] Disable PDC operation.
Set the PCCR0 register
(PCKOE, PCKDIV)
[2]
PCCR0.PCKE = 1
[3]
[2] Set the frequency division rate for the PCKO signal
and enable or disable an output of the PCKO signal.
(Set as required.)
[3] Enable PIXCLK input.
PCCR0.PRST = 1
[4]
[4] Reset the PDC.
Set the VCR and HCR registers
[5]
[5] Set the vertical and horizontal capture ranges.
Set the PCCR0 register
(VPS, HPS, DFIE, FEIE,
OVIE, UDRIE, VERIE,
HERIE, EDS)
[6]
[6] Set the polarity of the VSYNC and HSYNC signals
(VPS, HPS).
Enable or disable interrupts
(DFIE, FEIE, OVIE, UDRIE, VERIE, HERIE).
Set the endian order (EDS).
PCCR0.PRST == 0
Yes
End of initialization
Figure 42.18
Example flow for initial PDC settings
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42.3.9
42. Parallel Data Capture Unit (PDC)
Operation Flows
Figure 42.19 shows an example operation flow when the receive data ready interrupt (to start the DTC or DMAC) and
frame end interrupt are in use. For a description on how to set up the DTC or DMAC, see section 17, DMA Controller
(DMAC), and section 18, Data Transfer Controller (DTC).
Main Routine
DTC/DMAC
Completion of initial settings
and data reception
Set the DTC or DMAC
Completion of the
DTC or DMAC setting
[1]
No
PCCR1.PCE = 1
[2]
Transfer the data in the
PCDR register to the
destination address.
Receive data
[1]
DTC or DMAC setup:
Set the DTC or DMAC based on the size of the
captured image.
[2]
Enabling of PDC operation:
Set the PCE bit in the PCCR1 register to 1 to enable
PDC operation.
[3]
Data reception:
Receive the data from the external I/O and wait for
generation of a receive data ready interrupt (DTC/DMAC
startup) or a frame end interrupt.
[4]
Transfer by the DTC or DMAC:
Transfer the data in the PCDR register to the destination
address in response to a receive data ready interrupt
(DTC/DMAC startup).
Read the PCDR register in 4-byte access and transfer
32 bytes of data per receive data ready
interrupt.
[5]
Frame end interrupt:
Read the FEMPF flag in the PCSR register and verify
completion of the DTC or DMAC transfer.
If an underrun occurs during DTC or DMAC transfer,
the FEMPF flag may not set. When an underrun occurs,
clear the FEF flag and branch to the appropriate error
processing routine.
[6]
Completion of data reception:
After completion of the transfer, clear the PCE bit in the
PCCR1 register to 0, and then clear the FEF flag in the
PCSR register to 0. This completes handling of the
frame end interrupt and data reception.
Start of frame end
interrupt
No
[5]
No
PCSR.FEMPF == 1?
[5]
Yes
PCCR1.PCE = 0
[6]
Clear PCSR.FEF
flag to 0
Clear PCSR.FEF
flag to 0
Completion of frame
end interrupt
Completion of data
reception
Figure 42.19
[4]
[3]
Interrupt processing
Yes
Request for DTC or
DMAC startup?
Yes
Start of data reception
PCSR.UDRF == 1?
[1]
Start of error
processing
Example operation flow
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42. Parallel Data Capture Unit (PDC)
Figure 42.20 shows an example of the operation flow when responding to an error interrupt.
Start of error processing
No
PCCR1.PCE = 0
[1]
Disable DTC or DMAC transfer
[2]
PCSR.OVRF == 1?
[1]
Disabling the PDC operation:
Clear the PCE bit in the PCCR1 register to 0 to
disable PDC operation.
[2]
Disabling the DTC or DMAC transfer:
Disable the transfer of the DTC or DMAC.
[3]
Overrun flag check:
Read the PCSR register to check the state of
the OVRF flag. If the flag is set, overrun error
handling proceeds, and the flag is then cleared.
[4]
Underrun flag check:
Read the PCSR register to check the state of
The UDRF flag. If the flag is set, underrun error
handling proceeds, and the flag is then cleared.
[5]
Checking the vertical line setting error flag:
Read the PCSR register to check the state of
the VERF flag. If the flag is set, vertical line
setting error handling proceeds, and the flag
is then cleared.
[6]
Checking the horizontal byte setting error flag:
Read the PCSR register to check the status of
the HERF flag. If the flag is set, horizontal byte
setting error handling proceeds, and the flag
is then cleared.
[3]
Yes
Overrun error processing*1
Clear PCSR.OVRF flag to 0
No
PCSR.UDRF == 1?
[4]
Yes
Underrun error processing*1
Clear PCSR.UDRF flag to 0
No
PCSR.VERF == 1?
[5]
Yes
Vertical line setting error processing*1
Clear PCSR.VERF flag to 0
No
PCSR.HERF == 1?
Yes
Horizontal byte setting error processing*1
Clear PCSR.HERF flag to 0
[6]
Note 1. Processing for each type of error is defined
by the user, so the user needs to prepare
error processing for each.
Note 2. If the CPU, DTC, or DMAC reads the PCDR
register after an error interrupt occurs in
response to an interrupt source other than
an underrun, an underrun may occur.
If an underrun occurs on completion of error
processing, run the error processing again
and clear the UDRF flag.
Since underruns still require detection after
error processing, do not disable the
underrun interrupt before the error
processing.
Completion of error processing*2
Completion of data reception
Figure 42.20
Example error processing flow
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42.3.10
42. Parallel Data Capture Unit (PDC)
Interrupt Sources
The PDC interrupt sources include:
Receive data ready
Frame end
Overrun
Underrun
Vertical line number setting error
Horizontal byte number setting error.
The PDC can start the DTC or DMAC in response to a receive data ready interrupt request for the transfer of data.
Table 42.5 summarizes the PDC interrupt sources. When an interrupt condition listed in Table 42.5 is satisfied, the
associated interrupt is generated. For receive data ready interrupts, the program can clear the interrupt source flag by
reading the PCDR register. For the frame end interrupts, clear the FEF flag in the PCSR register. For an overrun,
underrun, vertical line number setting error, or horizontal byte number setting error, the program must check the flags to
identify the error source flag, because their interrupt vectors are allocated to the same address by PDC_PCERI. After
identifying the source, the program must clear the associated error interrupt source flag (OVRF, UDRF, VERF, or HERF)
in the PCSR register.
When the DTC or DMAC module is to handle the data transfer, first select the module. After enabling the module for
transfers, set up the PDC. For information on setting up the DTC and DMAC, see section 17, DMA Controller (DMAC),
and section 18, Data Transfer Controller (DTC).
On completion of the output, the request flag clears automatically. An interrupt request signal retained internally can also
be cleared by setting the associated interrupt enable bit (the DFIE bit in the PCCR0 register) to 0.
Table 42.5
PDC interrupt sources
Interrupt source
Abbreviation
Interrupt conditions
DTC/DMAC
activation
Receive Data Ready
PDC_PCDFI
Receive data ready occurs while the DFIE bit in the PCCR0 register is 1
Possible
Frame End
PDC_PCFEI
Frame end occurs while the FEIE bit in the PCCR0 register is 1
Impossible
Errors
PDC_PCERI
An overrun occurs while the OVIE bit in the PCCR0 register is 1
An underrun occurs while the UDRIE bit in the PCCR0 register is 1
A vertical line number setting error occurs while the VERIE bit in the
PCCR0 register is 1
A horizontal byte number setting error occurs while the HERIE bit in the
PCCR0 register is 1.
Impossible
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42.3.11
42. Parallel Data Capture Unit (PDC)
Reset State
The PDC has two types of resets: a PDC reset (writing 1 to PCCR0.PRST bit) and other resets.
Other resets include:
RES pin reset
Power-on reset
Voltage monitor reset 0
Voltage monitor reset 1
Voltage monitor reset 2
Deep Software Standby reset
Independent watchdog timer reset
Watchdog timer reset
Software reset
SRAM parity error reset
SRAM ECC error reset
Illegal instruction reset
Oscillation stop detection reset
Bus master MPU error reset
Bus slave MPU error reset
Stack pointer error reset
Watchdog timer reset in reset sequence.
Table 42.6 shows the register states following the two types of resets.
Table 42.6
Register states on reset
PDC register
PDC reset
Other resets
PCCR0
Retained
Reset
PCCR1
Retained
Reset
PCSR
Reset
Reset
PCMONR
Retained
Reset
PCDR
Retained
Reset
VCR
Retained
Reset
HCR
Retained
Reset
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42.4
42.4.1
42. Parallel Data Capture Unit (PDC)
Usage Notes
Settings for the Module-Stop Function
PDC operation can be disabled or enabled using the MSTPC2 bit in Module Stop Control Register C (MSTPCRC). The
PDC is initially stopped (MSTPC2 =1) after reset. Releasing the module-stop state enables access to the registers. For
details, see section 11, Low Power Modes.
42.4.2
Constraints on the Low Power Function
When reducing PDC power consumption by using the low power function, set the PCE bit in the PCCR1 register to 0 to
disable reception operations, and set the PCKE bit in the PCCR0 register to 0 to disable the input through the PIXCLK
pin. Use the low power function after these settings are complete.
If the PCKOE bit in the PCCR0 register is set to 1, set it to 0 to stop the output of the PCKO signal, in addition to
disabling input through the PIXCLK pin in PCKE. Use the low power function after these settings are complete.
42.4.3
Constraints on Error Interrupts
When an error interrupt occurs, the DTC or DMAC might still be transmitting parallel data, depending on its operation
state. Because of this, the error interrupt processing routine must prohibit data transmission by the DTC or DMAC
immediately after prohibiting PDC operation (PCCR1.PCE = 0).
42.4.4
Constraints on Using the DTC
When the DTC is used with the receive data ready interrupt, set the DISEL bit in the MRB register to 0 and the SZ bit in
the MRA register to 10b.
The maximum number of blocks that the DTC can transfer in block transfer mode is 65,536. If 32 bytes are transferred
per block transfer, this represents a total of up to 2,097,152 bytes. If more data is to be transferred, set up the DTC again
during the horizontal blanking period. For details, see section 18, Data Transfer Controller (DTC).
42.4.5
Constraints on Using the DMAC
When the DMAC is used with the receive data ready interrupt, set the SZ bit in the DMTMD register to 10b, and
configure the DESL[8:0] bits in the DELSRn register (n = 0 to 7) appropriately.
The maximum number of blocks that the DMAC can transfer in block transfer mode is 65,536. If 32 bytes are transferred
per block transfer, this represents a total of up to 2,097,152 bytes. If more data is to be transferred, set up the DMAC
again during the horizontal blanking period. For details, see section 14, Interrupt Controller Unit (ICU) and section 17,
DMA Controller (DMAC).
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43. Boundary Scan
43.
Boundary Scan
43.1
Overview
The boundary scan function provides a serial I/O interface based on the JTAG (Joint Test Action Group), IEEE Std.
1149.1, and IEEE Standard Test Access Port, and Boundary Scan Architecture. Table 43.1 lists the boundary scan
specifications, Figure 43.1 shows a block diagram, and Table 43.2 lists the I/O pins.
Table 43.1
Boundary scan specifications
Parameter
Specifications
Execution condition
Boundary scan must be executed when the RES pin is driven low
Test modes
BYPASS mode
EXTEST mode
SAMPLE/PRELOAD mode
CLAMP mode
HIGHZ mode
IDCODE mode.
JTBSR:
Boundary Scan Register
Pxx
Pxx
BSR
BSR
BSR
Logic
JTIDR:
ID Code Register (32-bit)
TDI
JTBPR:
Bypass Register (1-bit)
Selector
BSR
Selector
BSR
BSR
TDO
Decoder
TCK
TMS
Figure 43.1
Table 43.2
TAP
controller
JTIR:
Instruction Register (4-bit)
Boundary scan function block diagram
Boundary scan I/O pins
Pin name
I/O
Description
TCK
Input
Test clock input pin.
Clock signal for boundary scan. The input clock duty cycle is 50% when the boundary scan
function is used.
TMS
Input
Test mode select pin
TDI
Input
Test data input pin
TDO
Output
Test data output pin
Note:
This MCU does not support the TRST pin for the JTAG interface.
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43.2
43. Boundary Scan
Register Descriptions
Table 43.3 lists the boundary scan registers.
Table 43.3
Boundary scan registers
Register name
Symbol
Value after reset
Instruction Register
JTIR
Eh
ID Code Register
JTIDR
0838 D447h
Bypass Register
JTBPR
Undefined
Boundary Scan Register
JTBSR
Undefined
Usage notes for the boundary scan registers:
Instructions can be input to the Instruction Register (JTIR) through the TDI pin by serial transfer
The Bypass Register (JTBPR), which is a 1-bit register, is connected between the TDI and TDO pins in BYPASS
mode
The Boundary Scan Register (JTBSR), which is configured according to the BSDL description, is connected
between the TDI and TDO pins when test data is being shifted in.
Table 43.4 shows the availability of serial transfer for the registers.
Table 43.4
Serial transfer for registers
Register name
Serial input
Serial output
Instruction Register (JTIR)
Available
Available
ID Code Register (JTIDR)
Available
Available
Bypass Register (JTBPR)
Available
Available
Boundary Scan Register (JTBSR)
Available
Available
43.2.1
Instruction Register (JTIR)
b3
b2
b1
b0
TS[3:0]
Value after reset:
1
1
1
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
TS[3:0]
Test Bit Set
The command configuration for these bits is shown in Table 43.5
—
Table 43.5
Command configuration
TS3
TS2
TS1
TS0
Instruction
0
0
0
0
EXTEST
0
0
0
1
SAMPLE/PRELOAD
0
0
1
1
IDCODE (Renesas code)
0
1
0
1
CLAMP
0
1
1
0
HIGHZ
1
1
1
1
BYPASS
Other settings
Reserved
JTAG instructions can be transferred to the JTIR register by serial input from the TDI pin. The JTIR register is initialized
when a power-on reset occurs, or when the TAP controller is in the Test-Logic-Reset state.
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43.2.2
43. Boundary Scan
ID Code Register (JTIDR)
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
DID[31:0]
Value after reset:
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
0
1
1
1
DID[31:0]
Value after reset:
1
1
0
1
0
1
0
0
0
Bit
Symbol
Bit name
Description
R/W
b31 to b0
DID[31:0]
Device ID
These bits store the fixed value that indicates the device IDCODE
—
JTIDR data is output from the TDO pin when the IDCODE instruction is executed. After a reset release, the IDCODE of
JTIDR changes into the Arm® debug code. See the ARM® CoreSight™ SoC-400 Technical Reference Manual (ARM
DDI 0480F).
43.2.3
Bypass Register (JTBPR)
JTBPR is a 1-bit register and is connected between the TDI and TDO pins when the JTIR register is set to BYPASS
mode. The JTBPR register cannot be read from or written to by the CPU.
43.2.4
Boundary Scan Register (JTBSR)
JTBSR is a shift register used for controlling the external input and output pins of the MCU, and is distributed across the
pads. To apply the JTBSR register in boundary-scan testing, issue the EXTEST, SAMPLE/PRELOAD, CLAMP, and
HIGHZ instructions. The BSDL file describes the associations between the JTBSR bits and the MCU pins. The value
after reset is undefined.
43.3
Operation
During a reset, the JTAG ports, TCK, TMS, TDI, and TDO, are assigned as default pin functions. The TCK, TMS, and
TDI pins are pulled up by the pull-up resistors. Boundary scan testing can be executed after the setup time elapses, when
POR is negated, and RES is driven low.
43.3.1
TAP Controller
Figure 43.2 shows the state transition diagram of the TAP controller. All transitions are controlled by the TMS signal.
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1
43. Boundary Scan
Test-logic-reset
0
Run-test/idle
0
1
1
Select-DR
0
0
1
1
Capture-DR
Capture-IR
0
0
Shift-DR
0
Shift-IR
1
1
Exit1-IR
0
0
Pause-IR
0
1
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
(1)
1
0
Pause-DR
43.3.2
0
1
Exit1-DR
Figure 43.2
1
Select-IR
0
Update-IR
1
0
State transition diagram of TAP controller
Commands
BYPASS
The BYPASS instruction drives the Bypass Register (JTBPR). This instruction shortens the shift path, facilitating the
transfer of serial data to the other LSIs on a printed circuit board at higher speeds. While this instruction is being
executed, the test circuit has no effect on the system circuits.
The Bypass Register (JTBPR) is connected between the TDI and TDO pins. Bypass operation is initiated from the ShiftDR operation. The TDO is low in the first clock cycle in the Shift-DR state. In the subsequent clock cycles, the TDI
signal is output on the TDO pin.
(2)
EXTEST
The EXTEST instruction is used to test external circuits when the MCU is installed on the printed circuit board. If this
instruction is executed, the output pins are used to output test data (specified in the SAMPLE/PRELOAD instruction)
from the Boundary Scan Register (JTBSR) to the print circuit board, and the input pins are used to input the test result.
(3)
SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction is used to input data from the internal circuits of the MCU to the Boundary Scan
Register (JTBSR), output data from the scan path, and reload the data to the scan path. While this instruction is executed,
the input signals are directly input to the MCU and output signals are also directly output to the external circuits. The
MCU system circuit is not affected by this instruction.
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43. Boundary Scan
In SAMPLE operation, the Boundary Scan Register (JTBSR) latches a snapshot of the data transferred from the input
pins to the internal circuit, or data transferred from the internal circuit to the output pins. The latched data is read from
the scan path. The JTBSR register latches the data snapshot on the rising edge of the TCK pin in the Capture-DR state.
The data snapshot is only transferred from the internal circuit to the output pins during a reset.
In PRELOAD operation, the initial value is written from the scan path to the parallel output latch of the Boundary Scan
Register (JTBSR) prior to the EXTEST instruction execution. If EXTEST is executed without executing this PRELOAD
operation, undefined values are output from the beginning of the EXTEST sequence to the end (transfer to the output
latch). In the EXTEST instruction, output parallel latches are always output to the output pins.
(4)
IDCODE
When the IDCODE instruction is selected, the ID Code Register (JTIDR) value is output to the TDO pin in the Shift-DR
state of the TAP controller. In this case, the JTIDR register value is output LSB-first. During this instruction execution,
the test circuit does not affect the system circuit.
(5)
CLAMP
When the CLAMP instruction is selected, the output pins output the Boundary Scan Register (JTBSR) value that was
specified in the SAMPLE/PRELOAD instruction in advance. While the CLAMP instruction is selected, the status of the
JTBSR register is maintained regardless of the TAP controller state.
The Bypass Register (JTBPR) is connected between the TDI and TDO pins, leading to the same operation as when the
BYPASS instruction is selected.
(6)
HIGHZ
When the HIGHZ instruction is selected, all output pins enter a high-impedance state. While the HIGHZ instruction is
selected, the status of Boundary Scan Register (JTBSR) is maintained regardless of the state of the TAP controller.
The Bypass Register (JTBPR) is connected between the TDI and TDO pins, leading to the same operation as when the
BYPASS instruction is selected.
43.4
Usage Notes
The boundary scan function is subject to the following constraints:
The boundary scan must be executed when the RES pin is driven low
Serial data input/output is in LSB order, as shown in Figure 43.3.
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43. Boundary Scan
TDI
JTIR, JTIDR
Bit [31]
Bit [30]
Shift register
Serial data input/output in
LSB order
Bit [1]
Bit [0]
TDO
Figure 43.3
Serial data input/output
The following pins cannot be boundary-scanned:
Power supply pins (VCC, VCL, VCL0, VSS, VBATT, AVCC0, AVSS0, VCC_USB, and VSS_USB)
Analog reference pins (VREFH0, VREFL0, VREFH, VREFL)
Clock pins (EXTAL, XTAL, XCIN, and XCOUT)
Reset signal (RES)
USB-dedicated pins (USB_DP, USB_DM)
The boundary-scan pins (TCK, TMS, TDI, and TDO).
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44.
44. Secure Cryptographic Engine (SCE7)
Secure Cryptographic Engine (SCE7)
The MCU incorporates a Secure Cryptographic Engine (SCE7) module to provide security functions. The module
consists of an access management circuit, encryption engine, and random number generator. In combination with the
Renesas Synergy Software Package (SSP) Crypto library, the SCE7 can prevent eavesdropping (confidentiality),
falsification of information (integrity), and impersonation (authenticity).
The SCE7 module can only be used with the SSP Crypto library. For details, see the Crypto Framework and the SCE
Crypto Driver sections in the Renesas Synergy™ Software Package (SSP) User’s Manual.
44.1
Overview
Table 44.1 shows the SCE7 specifications and Figure 44.1 shows the block diagram.
Table 44.1
SCE7 specifications (1 of 2)
Parameter
Description
Access control
Access management circuit
In case of irregular access to the SCE7 due to a falsified program or runaway execution of a program, this
circuit blocks all subsequent accesses and stops the output of data from the SCE7.
Encryption engine
Advanced Encryption Standard (AES): Compliant with NIST FIPS PUB 197 algorithm
Key sizes: 128, 192, or 256 bits
Block size: 128 bits
Chaining modes
ECB, CBC, CTR: Compliant with NIST SP 800-38A
GCM: Compliant with NIST SP 800-38D
XTS: Compliant with NIST SP 800-38E.
GCTR
Throughput for 128-bit data
11 PCLKB cycles for 128-bit key
15 PCLKB cycles for 256-bit key*1.
AES-GCM
AES-GCM is realized by combining AES-GCTR and GHASH.
Triple Data Encryption Standard (3DES)
192-bit key length
Operates on a fixed 8-byte block of data
Used in legacy Secure Socket Layer (SSL) and Transport Layer Security (TLS) protocols
Throughput for 64-bit data
16 PCLKB cycles for 56-bit key.
Alleged RC4 (ARC4)
2048-bit key length
Throughput for 128-bit data
16 PCLKB cycles for 2048-bit key.
Key management
Wrapped keys are only valid within the SCE7.
Generation of random
numbers
128-bit true random number generator
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Table 44.1
44. Secure Cryptographic Engine (SCE7)
SCE7 specifications (2 of 2)
Parameter
Description
Signature generation
and verification
RSA
Support for 1024-bit and 2048-bit key sizes
Signature generation, signature verification, public-key encryption, private-key decryption.
DSA
Support for DSA key sizes:
(1024-bit, 160-bit)
(2048-bit, 224-bit)
(2048-bit, 256-bit).
Signature generation, signature verification.
ECC
Support for curve P-192, P-224, P-256, and P-384
Signature generation, signature verification
Scalar multiplication.
Message digest
computation
HASH
SHA1, SHA224, SHA256, and MD5.
Unique ID
An ID unique to the MCU (unique ID) is accessible from the access management circuit through the
dedicated bus
Combining the unique ID with the key generation information prevents illicit copying of data to another MCU.
Privileged mode
The privileged mode signal is connected to the access management circuit and is used to limit control of the
SCE7 module to privileged mode only.
Low power
consumption
Setting of the module-stop state is possible.
Note 1.
This does not include the overhead for calling functions of the SSP Crypto library.
SCE 7
Bus interface
Internal peripheral bus
Random num ber generator
Encryption engine
Access
M anagem ent
Circuit
AES
(128 / 192 / 256 bits)
G H ASH
RSA
DSA
HASH
ECC
Privileged m ode signal
Figure 44.1
Unique ID
SCE7 block diagram
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44.2
44. Secure Cryptographic Engine (SCE7)
Operation
44.2.1
Encryption Engine
The encryption engine performs the following operation in hardware (see Figure 44.2):
Plaintext to ciphertext encryption
Ciphertext to plaintext decryption.
Encryption
SCE7
Plaintext
Ciphertext
Access
management
circuit
Encryption
engine
Decryption
SCE7
Ciphertext
Plaintext
Figure 44.2
Access
management
circuit
Encryption
engine
Encryption and decryption processes by encryption engine
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44.2.2
44. Secure Cryptographic Engine (SCE7)
Encryption and Decryption
To encrypt or decrypt data:
1. Input the data to encrypt or decrypt in the SCE7.
The SCE7 converts the plaintext data to ciphertext or ciphertext data to plaintext.
2. Read the converted data.
The encryption engine has an input buffer and an output buffer, enabling encryption/decryption to proceed in parallel
with data input/output. Figure 44.3 shows the encryption engine timing.
Block-1
(32 bits × 4)
Internal
peripheral bus
Block-2
(32 bits × 4)
Block-1
(32 bits × 4)
W1 W1 W1 W1 W2 W2 W2 W2
Input buffer
W1
R1
R1
R1
R1 W3 W3 W3 W3
W2
Output buffer
W3
R1
State of the
encryption engine
Encryption
Block-3
(32 bits × 4)
Encryption
R2
Encryption
11 cycles or 15 cycles
Figure 44.3
44.3
44.3.1
Encryption and decryption timing (AES)
Usage Notes
Software Standby Mode
When Software Standby mode is entered while the encryption engine is processing, proper processing cannot be resumed
after exiting Software Standby mode. Software Standby mode should therefore be entered while the encryption engine is
not running.
44.3.2
Settings for the Module-Stop Function
SCE7 operation can be disabled or enabled using Module Stop Control Register C (MSTPCRC). The SCE7 module is
initially stopped after reset. Releasing the module-stop state enables access to the registers.
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45.
12-Bit A/D Converter (ADC12)
45.1
Overview
45. 12-Bit A/D Converter (ADC12)
The MCU provides two 12-bit successive approximation A/D converter (ADC12) units. In unit 0, up to 13 analog input
channels are selectable. In unit 1, up to 9 analog input channels, the temperature sensor output, and internal reference
voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-, 10-, and 8-bit conversion,
making it possible to optimize the trade-off between speed and resolution in generating a digital value.
ADC12 features include:
13 channels (unit 0), 9 channels (unit 1)
PCLKB = 60 MHz (maximum)
PCLKC = 60 MHz (maximum)
Analog channels: AN000 to AN007, AN016 to AN020 (unit 0), AN100 to AN102, AN105 to AN107, AN116 to
AN118 (unit 1)
Resolution: 12-bit, 10-bit, 8-bit
Dedicated sample-and-hold circuit embedded.
The ADC12 supports the following operating modes:
Single scan mode for converting analog inputs of arbitrarily selected channels in ascending order of channel number
Continuous scan mode for sequentially converting analog inputs of arbitrarily selected channels continuously in
ascending order of channel number
Group scan mode for arbitrarily dividing the analog inputs of channels into two groups (A and B) and converting the
analog input of the selected channel for each group in ascending order of channel number.
In group scan mode, you can start group A and group B A/D conversion at different times by individually selecting their
scan start conditions. In addition, when a priority control operation for group A is set, the ADC12 accepts group A scan
starting during group B A/D conversion, suspending group B conversion. This allows you to assign higher priority to
A/D conversion start for group A.
In double-trigger mode, the analog input of an arbitrarily selected channel is converted in single scan mode or group scan
mode (group A), and the data converted by the first and second A/D conversion start triggers are stored in different
registers, providing duplexing of A/D-converted data.
Self-diagnosis is performed once at the beginning of each scan, and one of the three voltage values generated in the
ADC12 is A/D-converted.
The temperature sensor output and the internal reference voltage are selectable at the same time as the analog input of the
channel. First A/D conversion is performed for the analog input of the channel, next the temperature sensor output, and
then the internal reference voltage.
The ADC12 provides a compare function (Window A and Window B). This compare function specifies the upper
reference value for Window A and lower reference value for Window B, and outputs an interrupt request when the A/Dconverted value of the selected channel meets the comparison conditions.
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45. 12-Bit A/D Converter (ADC12)
Table 45.1 lists the ADC12 specifications and Table 45.2 list the functions. Figure 45.1 shows a block diagram of
ADC12 unit 0 and Figure 45.2 shows a block diagram of ADC12 unit 1. Table 45.3 lists the I/O pins.
Table 45.1
ADC12 specifications (1 of 2)
Parameter
Specifications
Number of units
Two units, 0 and 1
Input channels
Unit 0: Up to 13 channels
Unit 1: Up to 9 channels
Extended analog
function
Temperature sensor output, internal reference voltage
A/D conversion method
Successive approximation method
Resolution
12 bits, selectable to 12-bit, 10-bit, or 8-bit conversion
Conversion time
0.4 µs/channel, when A/D conversion clock PCLKC (ADCLK) is operating at 60 MHz
(See Table 55.35 and Table 55.36 about the condition)
A/D conversion clock
Peripheral module clock PCLKB*1 and A/D conversion clock PCLKC (ADCLK)*1 can be set with the
following division ratios:
PCLKB to PCLKC (ADCLK) frequency ratios = 1:1, 2:1, 4:1, 8:1, 1:2, 1:4
Data registers
22 registers for analog input (13 for unit 0, 9 for unit 1), one for A/D-converted data duplication in doubletrigger mode in each unit, and 2 for A/D-converted data duplication in extended operation in doubletrigger mode in each unit
One register for temperature sensor output
One register for internal reference voltage
One register for self-diagnosis
Storing of A/D conversion results in A/D data registers
8-, 10-, and 12-bit accuracy output for A/D conversion results
A/D-converted value addition mode, in which the sum of all A/D conversion results are stored in the A/D
data registers as the conversion accuracy bit count + 2 bits*4
Double-trigger mode (selectable in single scan and group scan modes):
The first unit of A/D-converted analog-input data on one selected channel is stored in the data register for
the channel, and the second unit is stored in the duplexing register
Extended operation in double-trigger mode (available for specific triggers):
A/D-converted analog-input data on one selected channel is stored in the duplexing register provided for
the associated trigger.
Operating modes
Single scan mode:
- A/D conversion is performed only once on the analog inputs of arbitrarily selected channels, on the
temperature sensor output, and on the internal reference voltage
Continuous scan mode:
- A/D conversion is performed repeatedly on the analog inputs of arbitrarily selected channels, on the
temperature sensor output, and on the internal reference voltage
Group scan mode:
- Analog inputs of arbitrarily selected channels, the temperature sensor output, and the internal reference
voltage are divided into group A and group B, and A/D conversion of the analog input selected on a group
basis is performed only once.
- The scan start conditions can be independently selected for group A and group B, allowing A/D
conversion of group A and group B to be started independently.
Group scan mode (when group A is given priority):
- If a group A trigger is input during A/D conversion on group B, the A/D conversion on group B stops and
A/D conversion is processed on group A.
- Restart (rescan) of group B conversion after completion of group A conversion can be set.
Conditions for A/D
conversion start
Software trigger
Synchronous triggers from the Event Link Controller (ELC)
Asynchronous triggering by the external trigger pins, ADTRG0 (unit 0) and ADTRG1 (unit 1).
Functions
Dedicated sample-and-hold function with optional constant sampling and 3 channels in units 0 and 1
Variable sampling state count
Self-diagnosis of ADC12
Selectable A/D-converted value addition mode or average mode
Analog input disconnection detection function (discharge and precharge functions)
Double-trigger mode (duplication of A/D conversion data)
Switching function for 8-, 10-, and 12-bit conversion*2
Automatic clear function for A/D data registers
Digital comparison of values in the comparison and data registers, and between values in the data
registers
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Table 45.1
45. 12-Bit A/D Converter (ADC12)
ADC12 specifications (2 of 2)
Parameter
Specifications
Interrupt sources and
ELC events
ELC interface
Scan can be started by a trigger from the ELC
ADC12i_ADI: A/D scan end interrupt
ADC12i_GBADI: A/D scan end interrupt for group B
ADC12i_CMPAI: Window A compare match
ADC12i_CMPBI: Window B compare match
ADC12i_WCMPM: compare match
ADC12i_WCMPUM: compare mismatch.
Bus interface
Bus clock synchronized with peripheral clock (PCLKB), maximum frequency = 60 MHz
Reference voltage
Unit 0:
VREFH0 is the high potential reference voltage.
VREFL0 is the low potential reference voltage.
Unit 1:
VREFH is the high potential reference voltage.
VREFL is the low potential reference voltage.
Module-stop function
Module-stop state can be set to reduce power consumption*3
i = 0 for unit 0, and i = 1 for unit 1.
Note 1.
Note 2.
Note 3.
Note 4.
Peripheral module clock, PCLKB is specified in the SCKDIVCR.PCKB[2:0] bits, and the A/D conversion clock, ADCLK is
specified in the SCKDIVCR.PCKC[2:0] bits in units 0 and 1.
Changing the A/D conversion accuracy also changes the A/D conversion time. For details, see section 45.3.6, Analog Input
Sampling and Scan Conversion Time.
For details, see section 11, Low Power Modes.
The number of extended bits for addition varies with the A/D conversion accuracy and the number of addition times. A 2-bit
extension is up to 4 times conversion (3 times addition) when the A/D conversion accuracy is 8, 10, or 12 bits. A 4-bit extension
is 16 times conversion (15 times addition) when the A/D conversion accuracy is 12 bits.
Table 45.2
ADC12 functions
Parameter
Unit 0 (ADC120)
Unit 1 (ADC121)
Analog input channel
AN000 to AN007,
AN016 to AN020
Internal reference voltage
Temperature sensor output
AN100 to AN102,
AN105 to AN107,
AN116 to AN118
Internal reference voltage
Temperature sensor output
Software
Software trigger
Enabled
Enabled
External trigger
Trigger input pin
ADTRG0
ADTRG1
Synchronous trigger
(trigger from ELC)
ELC trigger
ELC_AD00, ELC_AD01
ELC_AD10, ELC_AD11
AN000 to AN002
AN100 to AN102
Interrupt
ADC120_ADI
ADC120_GBADI
ADC120_CMPAI
ADC120_CMPBI
ADC121_ADI
ADC121_GBADI
ADC121_CMPAI
ADC121_CMPBI
Output to ELC
ADC120_ADI
ADC120_WCMPM
ADC120_WCMPUM
ADC121_ADI
ADC121_WCMPM
ADC121_WCMPUM
Module-stop function settings*1, *2
MSTPCRD.MSTPD16 bit
MSTPCRD.MSTPD15 bit
Conditions for A/D
conversion start
Channel-dedicated
sample-and-hold
function
Note 1.
Note 2.
Target channel
For details, see section 11, Low Power Modes.
Wait for 1 μs or longer to start A/D conversion after release from the module-stop state.
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45. 12-Bit A/D Converter (ADC12)
AVCC0
AVSS0
D/A
VREFH0
VREFL0
Successive approximation
register
Bus interface
A/D data registers
A/D control registers
Power generator
(for self-diagnosis)
Internal reference voltage
Interrupt requests
(ADC120_ADI, ADC120_GBADI,
ADC120_CMPAI,ADC120_CMPBI)
Temperature sensor output
AN020
AN016
Comparator
Analog multiplexer
AN007
AN006
AN005
AN004
AN003
AN002
Sample-and-hold
circuit
AN001
Sample-and-hold
circuit
AN000
Sample-and-hold
circuit
Figure 45.1
+
Sample-and-hold
circuit
-
Event output to the ELC
(ADC120_ADI, ADC120_WCMPM,
ADC120_WCMPUM)
Control circuit (including
decoder)
Synchronous trigger
(ELC_AD00, ELC_AD01)
Asynchronous trigger
(ADTRG0)
ADC12 unit 0 block diagram
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45. 12-Bit A/D Converter (ADC12)
AVCC0
AVSS0
D/A
VREFH
VREFL
Successive approximation
register
Bus interface
A/D data registers
A/D control registers
Power generator
(for self-diagnosis)
Internal reference voltage
Interrupt requests
(ADC121_ADI, ADC121_GBADI, ADC121_CMPAI,
ADC121_CMPBI)
Temperature sensor output
AN118
AN117
Comparator
Analog multiplexer
AN116
AN107
AN105
AN102
Sample-and-hold
circuit
AN101
Sample-and-hold
circuit
AN100
Sample-and-hold
circuit
+
Sample-and-hold
circuit
-
Event output to the ELC
(ADC121_ADI, ADC121_WCMPM,
ADC121_WCMPUM)
Control circuit (including
decoder)
Synchronous trigger
(ELC_AD10, ELC_AD11)
Asynchronous trigger
(ADTRG1)
Figure 45.2
Table 45.3
ADC12 unit 1 block diagram
ADC12 I/O pins
Unit
Pin name
I/O
Function
Unit 0
AVCC0
Input
Analog block power supply pin
AVSS0
Input
Analog block power supply ground pin
Unit 1
VREFH0
Input
Reference power supply pin
VREFL0
Input
Reference power supply ground pin
AN000 to AN007,
AN016 to AN020
Input
Analog input pins 0 to 7 and 16 to 20
ADTRG0
Input
External trigger input pin for starting A/D conversion, active-low
AVCC0
Input
Analog block power supply pin
AVSS0
Input
Analog block power supply ground pin
VREFH
Input
Reference power supply pin for ADC12 unit 1 and DAC
VRELF
Input
Reference power supply ground pin for ADC12 unit 1 and DAC
AN100 to AN102,
AN105 to AN107,
AN116 to AN118
Input
Analog input pins 0 to 2, 5 to 7, and 16 to 18
ADTRG1
Input
External trigger input pin for starting A/D conversion, active-low
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45.2
45. 12-Bit A/D Converter (ADC12)
Register Descriptions
45.2.1
A/D Data Registers y (ADDRy), A/D Data Duplexing Register (ADDBLDR),
A/D Data Duplexing Register A (ADDBLDRA), A/D Data Duplexing Register B
(ADDBLDRB), A/D Temperature Sensor Data Register (ADTSDR),
A/D Internal Reference Voltage Data Register (ADOCDR)
The data registers include:
ADDRy registers (y = 0 to 7, 16 to 20 in unit 0 and y = 0 to 2, 5 to 7, 16 to 18 in unit 1): 16-bit read-only registers
for storing the A/D conversion results
ADDBLDR register: 16-bit read-only register for storing the A/D conversion results in response to the second
trigger in double-trigger mode
ADDBLDRA and ADDBLDRB registers: 16-bit read-only registers for storing the A/D conversion results in
response to the respective triggers during extended operation in double-trigger mode
ADTSDR register: 16-bit read-only register for storing the A/D conversion result of the temperature sensor output
ADOCDR register: 16-bit read-only register for storing the A/D result of the internal reference voltage.
The following conditions determine the formats for data in these registers:
The setting in the A/D Data Register Format Select bit (ADCER.ADRFMT) (flush-left or flush-right setting)
The setting in the A/D Conversion Accuracy Specify bits (ADCER.ADPRC[1:0]) (8-, 10-, or 12-bit setting).
This section describes the data formats for these conditions in different modes.
(1)
When A/D-converted value addition/average mode is not selected
The data formats for each condition are as follows:
Settings for flush-right data with 12-bit accuracy
Address(es): ADC120.ADDR0 4005 C020h to ADC120.ADDR7 4005 C02Eh,
ADC120.ADDR16 4005 C040h to ADC120.ADDR20 4005 C048h,
ADC120.ADDBLDR 4005 C018h, ADC120.ADDBLDRA 4005 C084h, ADC120.ADDBLDRB 4005 C086h,
ADC120.ADTSDR 4005 C01Ah, ADC120.ADOCDR 4005 C01Ch,
ADC121.ADDR0 4005 C220h to ADC121.ADDR2 4005 C224h,
ADC121.ADDR5 4005 C22Ah to ADC121.ADDR7 4005 C22Eh,
ADC121.ADDR16 4005 C240h to ADC121.ADDR18 4005 C244h,
ADC121.ADDBLDR 4005 C218h, ADC121.ADDBLDRA 4005 C284h, ADC121.ADDBLDRB 4005 C286h,
ADC121.ADTSDR 4005 C21Ah, ADC121.ADOCDR 4005 C21Ch
Value after reset:
b15
b14
b13
b12
—
—
—
—
0
0
0
0
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
AD[11:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b11 to b0
AD[11:0]
Converted Value 11 to 0
12-bit A/D-converted value
R
b15 to
b12
—
Reserved
These bits are read as 0
R
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45. 12-Bit A/D Converter (ADC12)
Settings for flush-right data with 10-bit accuracy
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
AD[9:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b9 to b0
AD[9:0]
Converted Value 9 to 0
10-bit A/D-converted value
R
b15 to
b10
—
Reserved
These bits are read as 0
R
Settings for flush-right data with 8-bit accuracy
Value after reset:
Bit
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Symbol
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
AD[7:0]
0
0
0
0
0
Bit name
Description
R/W
b7 to b0
AD[7:0]
Converted Value 7 to 0
8-bit A/D-converted value
R
b15 to b8
—
Reserved
These bits are read as 0
R
Settings for flush-left data with 12-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
AD[11:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0
R
b15 to b4
AD[11:0]
Converted Value 11 to 0
12-bit A/D-converted value
R
Settings for flush-left data with 10-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
AD[9:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b5 to b0
—
Reserved
These bits are read as 0
R
b15 to b6
AD[9:0]
Converted Value 9 to 0
10-bit A/D-converted value
R
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45. 12-Bit A/D Converter (ADC12)
Settings for flush-left data with 8-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
AD[7:0]
Value after reset:
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
These bits are read as 0
R
b15 to b8
AD[7:0]
Converted Value 7 to 0
8-bit A/D-converted value
R
(2)
When A/D-converted value average mode is selected
A/D-converted value average mode can be selected when 2 or 4 times is specified in A/D-converted value addition
mode. When A/D-converted value average mode is selected, this register indicates the mean of the A/D-converted values
on the specified channel. The value is stored in the A/D data register based on the setting in the A/D Data Register
Format Select bit in the same way as for normal A/D conversion.
(3)
When A/D-converted value addition mode is selected
For 8-, 10-, or 12-bit accuracy (ADPRC bit setting), 1, 2, 3 or 4 times can be selected for A/D-converted value addition.
16 times can also be selected for addition mode, but only with 12-bit accuracy selected. In addition mode, this register
indicates the value that is obtained by adding the A/D-converted values on a specific channel. The sum of conversion
results is retained in the A/D data register as a 2-bit-extended value of the specified conversion accuracy. The value is
stored in the A/D data register based on the setting in the A/D Data Register Format Select bit in the same way as in the
case of normal A/D conversion.
When converting 1, 2, 3, or 4 times in addition mode with 8-, 10-, or 12-bit accuracy specified, the conversion result is
stored in the A/D data register as a 2-bit-extended value of the specified accuracy.
When converting 16 times in addition mode with 12-bit accuracy specified, the conversion result is stored in the A/D
data register as a 4-bit-extended value of the specified accuracy.
The data formats for each condition are as follows:
Settings for flush-right data with 12-bit accuracy in A/D-converted value addition mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
AD[15:0]*1
Value after reset:
—
—
0
0
AD[13:0]*2
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
AD[15:0]*1
Added Value 15 to 0
16 -bit sum of A/D conversion results
R
Bit
Symbol
Bit name
Description
R/W
b13 to b0
AD[13:0]*2
Added Value 13 to 0
14-bit sum of A/D conversion results
R
b15, b14
—
Reserved
These bits are read as 0
R
Note 1.
Note 2.
Used when a value of 16 conversion times is specified in A/D-converted value addition mode.
Used when a value of 1, 2, 3, or 4 conversion times is specified in A/D-converted value addition mode.
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45. 12-Bit A/D Converter (ADC12)
Settings for flush-right data with 10-bit accuracy in A/D-converted value addition mode
Value after reset:
b15
b14
b13
b12
—
—
—
—
0
0
0
0
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
AD[11:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b11 to b0
AD[11:0]
Added Value 11 to 0
12-bit sum of A/D conversion results
R
b15 to
b12
—
Reserved
These bits are read as 0
R
Settings for flush-right data with 8-bit accuracy in A/D-converted value addition mode
Value after reset:
Bit
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
Symbol
Bit name
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
AD[9:0]
0
0
0
0
0
0
Description
R/W
b9 to b0
AD[9:0]
Added Value 9 to 0
10-bit sum of A/D conversion results
R
b15 to
b10
—
Reserved
These bits are read as 0
R
Settings for flush-left data with 12-bit accuracy in A/D-converted value addition mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
0
0
AD[15:0]*1
AD[13:0]*2
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
AD[15:0]*1
Added Value 15 to 0
16 -bit sum of A/D conversion results
R
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0
R
b15 to b2
AD[13:0]*2
Added Value 13 o 0
14-bit sum of A/D conversion results
R
Note 1.
Note 2.
Used when a value of 16 conversion times is specified in A/D-converted value addition mode.
Used when a value of 1, 2, 3, or 4 conversion times is specified in A/D-converted value addition mode.
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45. 12-Bit A/D Converter (ADC12)
Settings for flush-left data with 10-bit accuracy in A/D-converted value addition mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
AD[11:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0
R
b15 to b4
AD[11:0]
Added Value 11 to 0
12-bit sum of A/D conversion results
R
Settings for flush-left data with 8-bit accuracy in A/D-converted value addition mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
AD[9:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
—
Reserved
These bits are read as 0
R
b15 to b6
AD[9:0]
Added Value 9 to 0
10-bit sum of A/D conversion results
R
45.2.2
A/D Self-Diagnosis Data Register (ADRD)
ADRD is a 16-bit read-only register that holds the A/D conversion results based on the self-diagnosis of the ADC12. In
addition to the AD[11:0] bits indicating the A/D-converted value, it includes the self-diagnosis status bit (DIAGST).
The following conditions determine the formats for data in this registers:
The setting in the A/D Data Register Format Select bit (ADCER.ADRFMT) (flush-left or flush-right setting)
The setting in the A/D Conversion Accuracy Specify bits (ADCER.ADPRC[1:0]) (8-, 10-, or 12-bit setting).
The A/D-converted value addition and average modes cannot be applied to the A/D self-diagnosis function. For details
on self-diagnosis, see section 45.2.11, A/D Control Extended Register (ADCER). This section describes the data formats
for each condition.
Settings for flush-right data with 12-bit accuracy
b15
b14
DIAGST[1:0]
Value after reset:
0
0
b13
b12
—
—
0
0
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
AD[11:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b11 to b0
AD[11:0]
Converted Value 11 to 0
12-bit A/D-converted value
R
b13, b12
—
Reserved
These bits are read as 0
R
b15, b14
DIAGST[1:0]
Self-Diagnosis Status
b15 b14
R
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Aug 30, 2019
0 0: Self-diagnosis not executed after power-on
0 1: Self-diagnosis was executed using the 0 V voltage
1 0: Self-diagnosis was executed using the reference power
supply*1 voltage x 1/2
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 45.2.11, A/D Control
Extended Register (ADCER).
Page 1444 of 1734
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Note 1.
45. 12-Bit A/D Converter (ADC12)
The reference voltage refers to VREFH0 for unit 0 and to VREFH for unit 1.
Settings for flush-right data with 10-bit accuracy
b15
b14
DIAGST[1:0]
0
Value after reset:
0
b13
b12
b11
b10
—
—
—
—
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
AD[9:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b9 to b0
AD[9:0]
Converted Value 9 to 0
10-bit A/D-converted value
R
b13 to b10 —
Reserved
These bits are read as 0
R
b15, b14
Self-Diagnosis Status
b15 b14
R
Note 1.
DIAGST[1:0]
0 0: Self-diagnosis not executed after power-on
0 1: Self-diagnosis was executed using the 0 V voltage
1 0: Self-diagnosis was executed using the reference power
supply*1 voltage x 1/2
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 45.2.11, A/D Control
Extended Register (ADCER).
The reference voltage refers to VREFH0 for unit 0 and to VREFH for unit 1.
Settings for flush-right data with 8-bit accuracy
b15
b14
DIAGST[1:0]
Value after reset:
0
0
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
AD[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
AD[7:0]
Converted Value 7 to 0
8-bit A/D-converted value
R
b13 to b8
—
Reserved
These bits are read as 0
R
b15, b14
DIAGST[1:0]
Self-Diagnosis Status
b15 b14
R
Note 1.
0 0: Self-diagnosis not executed after power-on
0 1: Self-diagnosis was executed using the 0 V voltage
1 0: Self-diagnosis was executed using the reference power
supply*1 voltage x 1/2
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 45.2.11, A/D Control
Extended Register (ADCER).
The reference voltage refers to VREFH0 for unit 0 and to VREFH for unit 1.
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45. 12-Bit A/D Converter (ADC12)
Settings for flush-left data with 12-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
AD[11:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
—
—
0
0
b1
b0
DIAGST[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
DIAGST[1:0]
Self-Diagnosis Status
b1 b0
R
b3, b2
—
Reserved
These bits are read as 0
R
b15 to b4
AD[11:0]
Converted Value 11 to 0
12-bit A/D-converted value
R
Note 1.
0 0: Self-diagnosis not executed after power-on
0 1: Self-diagnosis using the voltage of 0 V was executed
1 0: Self-diagnosis using the voltage of reference power supply*1 ×
1/2 was executed
1 1: Self-diagnosis using the voltage of reference power supply*1
was executed.
For details on self-diagnosis, see section 45.2.11, A/D Control
Extended Register (ADCER).
The reference voltage refers to VREFH0 for unit 0 and to VREFH for unit 1.
Settings for flush-left data with 10-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
AD[9:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
b5
b4
b3
b2
—
—
—
—
0
0
0
0
b1
b0
DIAGST[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
DIAGST[1:0]
Self-Diagnosis Status
b1 b0
R
b5 to b2
—
Reserved
These bits are read as 0
R
b15 to b6
AD[9:0]
Converted Value 9 to 0
10-bit A/D-converted value
R
Note 1.
0 0: Self-diagnosis not executed after power-on
0 1: Self-diagnosis was executed using the 0 V voltage
1 0: Self-diagnosis was executed using the reference power
supply*1 × 1/2 voltage
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 45.2.11, A/D Control
Extended Register (ADCER).
The reference voltage refers to VREFH0 for unit 0 and to VREFH for unit 1.
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45. 12-Bit A/D Converter (ADC12)
Settings for flush-left data with 8-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
AD[7:0]
0
Value after reset:
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
—
—
—
—
—
—
0
0
0
0
0
0
b1
b0
DIAGST[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
DIAGST[1:0]
Self-Diagnosis Status
b1 b0
R
b7 to b2
—
Reserved
These bits are read as 0
R
b15 to b8
AD[7:0]
Converted Value 7 to 0
8-bit A/D-converted value
R
Note 1.
0 0: Self-diagnosis not executed after power-on
0 1: Self-diagnosis was executed using the 0 V voltage
1 0: Self-diagnosis was executed using the reference power
supply*1 × 1/2 voltage
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 45.2.11, A/D Control
Extended Register (ADCER).
The reference voltage refers to VREFH0 for unit 0 and to VREFH for unit 1.
45.2.3
A/D Control Register (ADCSR)
Address(es): ADC120.ADCSR 4005 C000h, ADC121.ADCSR 4005 C200h
b15
ADST
b14
b12
ADCS[1:0]
0
Value after reset:
b13
0
0
b11
b10
b9
—
0
0
b8
b7
TRGE EXTRG DBLE
0
0
0
0
b6
b5
GBADI
E
—
0
0
b4
b3
b2
b1
b0
0
0
DBLANS[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
DBLANS[4:0]
Double Trigger Channel
Select
These bits select one analog input channel for double-triggered
operation. The setting is only valid in double-trigger mode.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
GBADIE
Group B Scan End
Interrupt and ELC Event
Enable
0: Disable ADC12i_GBADI interrupt generation on group B scan
completion
1: Enable ADC12i_GBADI interrupt generation on group B scan
completion.
Group B scan only works in group scan mode.
R/W
b7
DBLE
Double Trigger Mode
Select
0: Deselect double-trigger mode
1: Select double-trigger mode.
R/W
b8
EXTRG
Trigger Select *1
0: Start A/D conversion by a synchronous trigger (ELC)
1: Start A/D conversion by the asynchronous trigger (ADTRGi).
R/W
b9
TRGE
Trigger Start Enable
0: Disable A/D conversion to be started by the synchronous or
asynchronous trigger
1: Enable A/D conversion to be started by the synchronous or
asynchronous trigger.
R/W
b12 to b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14, b13
ADCS[1:0]
Scan Mode Select
b14 b13
R/W
b15
ADST
A/D Conversion Start
0: Stop A/D conversion process
1: Start A/D conversion process.
R/W
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0
0
1
1
0: Single scan mode
1: Group scan mode
0: Continuous scan mode
1: Setting prohibited.
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45. 12-Bit A/D Converter (ADC12)
i = 0 for unit 0, and i = 1 for unit 1.
Note 1.
To start A/D conversion using an external pin (asynchronous trigger), after a high-level signal is input to the external pin
(ADTRG0 in unit 0; ADTRG1 in unit 1), write 1 to both the TRGE and EXTRG bits in ADCSR and drive the external pin signals
low. With these settings, the scan conversion process starts on detection of the falling edge of ADTRG0 in unit 0 and ADTRG1
in unit 1. For this configuration, the pulse width of the low-level input must be at least 1.5 PCLKB clock cycles.
DBLANS[4:0] bits (Double Trigger Channel Select)
The DBLANS[4:0] bits select one of the channels for A/D conversion data duplication in double-trigger mode. The A/D
conversion results from the specified analog input channel are stored in A/D Data Register y when conversion is started
by the first trigger, and in the A/D Data Duplexing Register when conversion is started by the second trigger. Table 45.4
shows the channel selection settings for double-triggered operation.
A/D-converted value addition/average mode can be set with double-trigger mode for the channel selected in the
DBLANS[4:0] bits by using the ADADS0 and ADADS1 registers. In double-trigger mode, the channels selected in the
ADANSA0 and ADANSA1 registers are invalid, and the channel selected in the DBLANS[4:0] bits is A/D-converted
instead.
When double-trigger mode is used in group scan mode, double-trigger control is only applied to group A and not to
group B. This means that the multi-channel analog input, temperature sensor output, and internal reference voltage can
be selected for group B even in double-trigger mode.
Only set the DBLANS[4:0] bits while the ADST bit is 0. Do not set them at the same time that you write 1 to the ADST
bit.
To enter the A/D-converted value addition/average mode when in double-trigger mode, set the channel selected in the
DBLANS[4:0] bits in the ADANSA0 and ADANSA1 registers.
Table 45.4
Relationship between DBLANS bit settings and double-trigger enabled channels
Unit 0
DBLANS[4:0]
Unit 1
Duplication channel
DBLANS[4:0]
Duplication channel
00000
AN000
00000
AN100
00001
AN001
00001
AN101
00010
AN002
00010
AN102
00011
AN003
00011
—
00100
AN004
00100
—
00101
AN005
00101
AN105
00110
AN006
00110
AN106
00111
AN007
00111
AN107
Unit 0
DBLANS[4:0]
Unit 1
Duplication channel
DBLANS[4:0]
Duplication channel
10000
AN016
10000
AN116
10001
AN017
10001
AN117
10010
AN018
10010
AN118
10011
AN019
10011
—
10100
AN020
10100
—
Note:
A/D-converted data from the self-diagnosis function, temperature sensor output, and internal reference voltage cannot be used
in double-trigger mode. Settings other than those listed in Table 45.4 are prohibited.
GBADIE bit (Group B Scan End Interrupt and ELC Event Enable)
The GBADIE bit enables or disables group B scan end interrupt (ADC12i_GBADI (i = 0, 1)) in group scan mode.
DBLE bit (Double Trigger Mode Select)
The DBLE bit selects or deselects double-trigger mode. Double-trigger mode can only be operated by the synchronous
trigger (ELC) selected in the ADSTRGR.TRSA[5:0] bits.
Double-trigger operation is as follows:
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45. 12-Bit A/D Converter (ADC12)
1. The ADC12i_ADI (i = 0, 1) interrupt is not output on completion of the first conversion but on the completion of
the second conversion.
2. The A/D conversion results from the duplication channel (selected in DBLANS[4:0]) started by the first trigger are
stored in A/D Data Register y and those started by the second trigger are stored in the A/D Data Duplexing Register.
When DBLE is set, selecting double-trigger mode, the channels specified in the ADANSA0 and ADANSA1 registers are
invalid. Double-trigger mode is deselected by setting DBLE to 0. Setting DBLE to 1 again enables the same doubletrigger operation described in 1. and 2. for the first time scanning with the first trigger.
Do not select double-trigger mode in continuous scan mode. Additionally, do not select double-trigger mode for
conversion of the temperature sensor output or internal reference voltage except for group B scan in group scan mode.
Software triggering cannot be set in double-trigger mode. Always clear the ADST bit to 0 before setting the DBLE bit. In
other words, do not set the DBLE bit at that same time as writing 1 to the ADST bit.
EXTRG bit (Trigger Select)
The EXTRG bit selects the synchronous or asynchronous trigger as the trigger for starting A/D conversion.
TRGE bit (Trigger Start Enable)
The TRGE bit enables or disables A/D conversion by the synchronous and asynchronous triggers. In group scan mode,
set this bit to 1.
ADCS[1:0] bits (Scan Mode Select)
The ADCS[1:0] bits select the scan mode.
In single scan mode, A/D conversion is performed for the analog inputs up to a maximum of 13 channels in unit 0, and 9
channels in unit 1, and selected in the ADANSA0 and ADANSA1 registers in ascending order of the channel number.
When 1 cycle of A/D conversion completes for all the selected channels, the scan conversion stops. When the
temperature sensor output or internal reference voltage is selected, A/D conversion of the designated analog input
channels is followed by A/D conversion of the temperature sensor output and the internal reference voltage, in that order.
In continuous scan mode, while the ADCSR.ADST bit is 1, A/D conversion is performed for the analog inputs selected
in the ADANSA0 and ADANSA1 registers in ascending order of channel number, and when 1 cycle of A/D conversion
completes for all the selected channels, A/D conversion is repeated from the first channel. If the ADCSR.ADST bit is set
to 0 during continuous scan, A/D conversion stops even if scanning is in progress. When the temperature sensor output or
internal reference voltage is selected, A/D conversion of the designated analog input channels is followed by A/D
conversion of the temperature sensor output and the internal reference voltage, in that order.
In group scan mode, scanning is started by the synchronous trigger (ELC) selected in the TRSA[5:0] bits in ADSTRGR.
A/D conversion is performed on the group A analog inputs, up to the maximum channels selected in the ADANSA0 and
ADANSA1 registers, in ascending order of channel number. When 1 cycle of A/D conversion completes for all the
selected channels, A/D conversion stops. On the same trigger, A/D conversion is also performed on the group B analog
inputs, up to the maximum channels selected in the ADANSB0 and ADANSB1 registers, in ascending order of channel
number. When 1 cycle of A/D conversion completes for all the selected channels, A/D conversion stops. If the
conversion processes in group A and group B occur at the same time, those conversions cannot be controlled separately.
In this case, set the group A Priority Control Setting bit (ADGSPCR.PGS) in the A/D Group Scan Priority Control
Register (ADGSPCR) to 1 to give priority to group A conversion. When the temperature sensor output or internal
reference voltage is selected, A/D conversion of the designated analog input channels is followed by A/D conversion of
the temperature sensor output and the internal reference voltage, in that order.
In group scan mode, select different channels and triggers for group A and group B. Clear the ADST bit to 0 before
setting the ADCS[1:0] bits. In other words, do not set the ADCS[1:0] bits at the same time, while writing 1 to the ADST
bit.
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Table 45.5
45. 12-Bit A/D Converter (ADC12)
Selectable targets for A/D conversion depending on scan and double-trigger mode settings
Targets for A/D conversion
Analog input
(including
group A)
Analog input
(group B)
Temperature
sensor output
Internal
reference
voltage
Scan mode setting
Double-trigger
mode setting
Self-diagnosis
Single scan
DBLE = 0
-
DBLE = 1
-
(1 ch only)
-
-
-
DBLE = 0
-
DBLE = 1
-
-
-
-
-
DBLE = 0
DBLE = 1
-
(1 ch only)
Continuous scan
Group scan
: Selectable. -: Not selectable.
ADST bit (A/D Conversion Start)
The ADST bit starts or stops the A/D conversion process. Before setting the ADST bit to 1, set the A/D conversion clock,
conversion mode, and analog input for the conversion target.
[Setting conditions]
1 is written by software
The synchronous trigger (ELC) selected in the ADSTRGR.TRSA[5:0] bits is detected when ADCSR.EXTRG is 0
and ADCSR.TRGE is 1
The synchronous trigger (ELC) selected in the ADSTRGR.TRSB[5:0] bits is detected when ADCSR.TRGE is set to
1 in group scan mode
The asynchronous trigger is detected when the ADCSR.TRGE and ADCSR.EXTRG bits are set to 1 and the
ADSTRGR.TRSA[5:0] bits are set to 000000b
When group A priority control operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit
= 1), the ADGSPCR.GBRP bit is set to 1, and A/D conversion of group B starts each time.
[Clearing conditions]
0 is written by software
The A/D conversion of all the selected channels, the temperature sensor output or the internal reference voltage
completes in single scan mode
Group A scan completes in group scan mode
Group B scan completes in group scan mode
When group A priority control operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit
= 1), the ADGSPCR.GBRP bit is set to 1, and scanning of group B completes each time.
Note:
Note:
When group A priority control operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b, do not set the ADST bit
to 1.
When group A priority control operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit
= 1) and ADGSPCR.GBRP bit = 1, do not set the ADST bit to 0. When forcing A/D conversion to terminate, follow
the procedure for clearing the ADST bit.
If the single scan continuous function is used (ADGSPCR.GBRP = 1) when the group priority operation mode is
enabled (ADCSR.ADCS[1:0] = 01b and ADGSPCR.PGS = 1), the ADST bit is retained to 1.
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45.2.4
45. 12-Bit A/D Converter (ADC12)
A/D Channel Select Register A0 (ADANSA0)
Address(es): ADC120.ADANSA0 4005 C004h, ADC121.ADANSA0 4005 C204h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
ANSA07 to ANSA00
A/D Conversion Channels Select
0: Do not select associated input channel
1: Select associated input channel.
R/W
b15 to b8
-
Reserved.
These bits are read as 0. The write value should be 0.
R/W
ANSAn bits (n = 00 to 07) (A/D Conversion Channels Select)
The ADANSA0.ANSAn bits select or deselect the analog input channels for A/D conversion for AN000 to AN007 (unit
0) and AN100 to AN102 and AN105 to AN107 (unit 1). The channels and the number of channels can be set arbitrarily.
In unit 0, the ANSA00 bit is associated with AN000 and the ANSA07 bit with AN007. In unit 1, the ANSA00 bit is
associated with AN100 and the ANSA07 bit with AN107.
In double-trigger mode, the channel selected in the ADANSA0 register is invalid, and the channel selected in the
ADCSR.DBLANS[4:0] bits is selected in group A instead.
In group scan mode, do not select the channels specified in A/D Channel Select Register B0 (ADANSB0) and A/D
Channel Select Register B1 (ADANSB1).
Only set the ADANSA0 register while the ADCSR.ADST bit is 0.
45.2.5
A/D Channel Select Register A1 (ADANSA1)
Address(es): ADC120.ADANSA1 4005 C006h, ADC121.ADANSA1 4005 C206h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
ANSA2 ANSA1 ANSA1 ANSA1 ANSA1
0
9
8
7
6
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
ANSA20 to ANSA16
A/D Conversion Channels
Select
0: Do not select associated input channel
1: Select associated input channel.
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
ANSAn bits (n = 16 to 20) (A/D Conversion Channels Select)
The ADANSA1.ANSAn bits select or deselect the analog input channels for A/D conversion for AN016 to AN020 (unit
0) and AN116 to AN118 (unit 1). The channels and the number of channels can be set arbitrarily. In unit 0, the ANSA16
bit is associated with AN016 and the ANSA20 bit with AN020. In unit 1, the ANSA16 bit is associated with AN116, and
the ANSA18 bit with AN118.
In double-trigger mode, the ANSA1[15:0] bits are invalid, and the channel selected in the ADCSR.DBLANS[15:0] bits
is selected in group A instead.
In group scan mode, do not select the channels specified in A/D Channel Select Register B0 (ADANSB0) and A/D
Channel Select Register B1 (ADANSB1).
Only set the ADANSA1 register while the ADCSR.ADST bit is 0.
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45.2.6
45. 12-Bit A/D Converter (ADC12)
A/D Channel Select Register B0 (ADANSB0)
Address(es): ADC120.ADANSB0 4005 C014h, ADC121.ADANSB0 4005 C214h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
ANSB07 to ANSB00
A/D Conversion Channels
Select
0: Do not select associated input channel
1: Select associated input channel.
R/W
b15 to b8
-
Reserved
These bits are read as 0. The write value should be 0.
R/W
ANSBn bits (n = 00 to 07) (A/D Conversion Channels Select)
The ADANSB0.ANSBn bits select the analog input channels for A/D conversion for AN000 to AN007 (unit 0) and
AN100 to AN102 and AN105 to AN107 (unit 1) in group B in group scan mode. The ADANSB0 register is only used for
group scan mode, not for any other modes. Exclude the channels specified in group A (the channels associated with
group A, selected in the ADANSA0 and ADANSA1 registers and the ADCSR.DBLANS[4:0] bits in double-trigger
mode), both the selected channels and the number of channels to be set.
In unit 0, the ANSB00 bit is associated with AN000 and the ANSB07 bit with AN007. In unit 1, the ANSB00 bit is
associated with AN100 and the ANSB07 bit with AN107.
Only set the ADANSB0 register while the ADCSR.ADST bit is 0.
45.2.7
A/D Channel Select Register B1 (ADANSB1)
Address(es): ADC120.ADANSB1 4005 C016h, ADC121.ADANSB1 4005 C216h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
ANSB2 ANSB1 ANSB1 ANSB1 ANSB1
0
9
8
7
6
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
ANSB20 to ANSB16
A/D Conversion Channels
Select
0: Do not select the associated input channel
1: Select the associated input channel.
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
ANSBn bits (n = 16 to 20) (A/D Conversion Channels Select)
The ADANSB1.ANSBn bits select the analog input channels for A/D conversion for AN016 to AN020 (unit 0) and
AN116 to AN118 (unit 1) in group B in group scan mode. The ADANSB1 register is only used for group scan mode, not
for any other modes. Exclude the channels specified in group A (the channels associated with group A, selected in the
ADANSA0 and ADANSA1 registers and the ADCSR.DBLANS[4:0] bits in double-trigger mode), both the selected
channels and the number of channels to be set.
In unit 0, the ANSB16 bit is associated with AN016, and the ANSB20 bit is associated with AN020. In unit 1, the
ANSB16 bit is associated with AN116, and the ANSB18 bit is associated with AN118.
Only set the ADANSB1 register bits while the ADST bit is 0.
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45.2.8
45. 12-Bit A/D Converter (ADC12)
A/D-Converted Value Addition/Average Channel Select Register 0 (ADADS0)
Address(es): ADC120.ADADS0 4005 C008h, ADC121.ADADS0 4005 C208h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
ADS07 ADS06 ADS05 ADS04 ADS03 ADS02 ADS01 ADS00
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
ADS07 to ADS00
A/D-Converted Value
Addition/Average Channel
Select
0: Do not select associated input channel
1: Select associated input channel.
R/W
b15 to b8
-
Reserved
These bits are read as 0. The write value should be 0.
R/W
ADSn bits (n = 00 to 07) (A/D-Converted Value Addition/Average Channel Select)
When the ADSn bit with the same number as the A/D-converted channel selected in the ANSAn bits (n = 00 to 07) in
ADANSA0 or the ADCSR.DBLANS[4:0] bits and the ANSBn bits (n = 00 to 07) in ADANSB0 is set to 1, A/D
conversion of the analog input of the selected channels is performed successively 1 to 16 times, as specified in the
ADC[2:0] bits in ADADC. When the ADADC.AVEE bit is 0, the value obtained by addition (integration) is stored in the
A/D data register. When the ADADC.AVEE bit is 1, the mean value of the results obtained by addition (integration) is
stored in the A/D data register. In the A/D-converted channels for which addition or average mode is not selected, a
normal one-time conversion is executed, and the conversion result is stored in the A/D data register.
In unit 0, the ADS00 bit is associated with AN000, and the ADS07 bit is associated with AN007. In unit 1, the ADS00
bit is associated with AN100, and the ADS07 bit is associated with AN107.
Only set the ADADS0 register bits while the ADCSR.ADST bit is 0.
45.2.9
A/D-Converted Value Addition/Average Channel Select Register 1 (ADADS1)
Address(es): ADC120.ADADS1 4005 C00Ah, ADC121.ADADS1 4005 C20Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
ADS20 ADS19 ADS18 ADS17 ADS16
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
ADS20 to ADS16
A/D-Converted Value
Addition/Average Channel
Select
0: Do not select associated input channel
1: Select associated input channel.
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
ADSn bits (n = 16 to 20) (A/D-Converted Value Addition/Average Channel Select)
When the ADSn bit with the same number as the A/D-converted channel selected in the ANSAn bits (n = 16 to 20) in
ADANSA1 or ADCSR.DBLANS[4:0] bits and ANSBn bits (n = 16 to 18) in ADANSB1 is set to 1, A/D conversion of
the analog input of the selected channels is performed successively 1 to 16 times, as specified in the ADC[2:0] bits in
ADADC. When the ADADC.AVEE bit is 0, the value obtained by addition (integration) is stored in the A/D data
register. When the ADADC.AVEE bit is 1, the mean value of the results obtained by addition (integration) is stored in the
A/D data register. For A/D-converted channels for which addition/average mode is not selected, a normal one-time
conversion is executed, and the conversion result is stored in the A/D data register.
In unit 0, the ADS16 bit is associated with AN016 and the ADS20 bit with AN020. In unit 1, the ADS16 bit is associated
with AN116 and the ADS18 bit with AN118.
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45. 12-Bit A/D Converter (ADC12)
Only set the ADADS1 register while the ADCSR.ADST bit is 0.
Figure 45.3 shows a scanning operation sequence in which both the ADADS0.ADS02 and ADS06 bits are set to 1.
In this example, addition mode is selected (ADADS.AVEE = 0), the time conversion is set to 4 (ADADC.ADC[1:0] =
11b), and the AN000 to AN006 channels are selected (ADANSA0.ANSA0[15:0] = 007Fh) in continuous scan mode
(ADCSR.ADCS[1:0] = 10b). The conversion process begins with AN000. The AN002 conversion is performed
successively 4 times, and the added (integrated) value is returned to A/D data register ADDR2. Next, the AN003
conversion process starts. The AN006 conversion is performed successively 4 times and the added (integrated) value is
returned to the A/D data register ADDR6. After conversion of AN006, the conversion operation is once again performed
in the same sequence from AN000.
Continuous
conversion count
4 times
3 times
2 times
1 time
AN002
AN006
AN002
AN002
AN006
AN002
AN002
AN006
AN002
AN000 AN001 AN002 AN003 AN004 AN005 AN006 AN000 AN001 AN002 • • •
Conversion in progress
Figure 45.3
Scan conversion sequence with ADADC.ADC[2:0] = 011b, ADADS0.ADS02 = 1, and ADS06 = 1
45.2.10
A/D-Converted Value Addition/Average Count Select Register (ADADC)
Address(es): ADC120.ADADC 4005 C00Ch, ADC121.ADADC 4005 C20Ch
b7
b6
b5
b4
b3
AVEE
—
—
—
—
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
b2 to b0
ADC[2:0]
Count Select
b6 to b3
—
Reserved
b7
Note 1.
Note 2.
AVEE
Average Mode Enable
b2
b1
b0
ADC[2:0]
0
0
0
Description
b2
R/W
b0
0 0 0: 1-time conversion (no addition; same as normal conversion)
0 0 1: 2-time conversion (one addition)
0 1 0: 3-time conversion (two additions)
0 1 1: 4 time conversion (three additions)
1 0 1: 16-time conversion (15 additions).
Other settings are prohibited.
These bits are read as 0. The write value should be 0.
R/W
R/W
mode*1
R/W
0: Disable average
1: Enable average mode.*2
When average mode is deselected by setting the ADADC.AVEE bit to 0, set the addition count to 1, 2, 3, 4 or 16-times. 16-time
conversion can only be used with 12-bit accuracy selected.
When average mode is selected by setting the ADADC.AVEE bit to 1, set the addition count to 1-, 2-, or 4-time conversion. Do
not set the addition count to 3- or 16-time conversion (ADC[2:0] = 010b or 101b).
ADC[2:0] bits (Count Select)
The ADC[2:0] bits set the count for all channels for which A/D conversion and addition/average mode are selected,
including the channels selected in double-trigger mode in the ADCSR.DBLANS[4:0] bits. The count also applies to A/D
conversion of the temperature sensor output and internal reference voltage.
When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the count to 3-time conversion
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45. 12-Bit A/D Converter (ADC12)
(ADADC.ADC[2:0] = 010b). Additionally, the combination of 16-time conversion (ADADC.ADC[2:0] = 101b) with a
conversion accuracy setting of 8 or 10 bits (ADCER.ADPRC[1:0] = 10b or 01b) is a prohibited setting, as described in
section 45.2.2.
Only set the ADC[2:0] bits while the ADCSR.ADST bit is 0. When self-diagnosis is executed (ADCER.DIAGM = 1), do
not set the ADC[2:0] bits to any value other than 000b. When the conversion accuracy is 8 or 10 bits
(ADCER.ADPRC[1:0] = 10b or 01b), do not set the ADC[2:0] bits to 101b.
AVEE bit (Average Mode Enable)
The AVEE bit selects addition or average mode for all channels for which A/D conversion and addition/average mode
are selected, including the channels selected in double-trigger mode in the ADCSR.DBLANS[4:0] bits, temperature
sensor output, and internal reference voltage.
When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to 3-time conversion
(ADADC.ADC[2:0] = 010b).
Only set the AVEE bits while the ADCSR.ADST bit is 0.
45.2.11
A/D Control Extended Register (ADCER)
Address(es): ADC120.ADCER 4005 C00Eh, ADC121.ADCER 4005 C20Eh
b15
b14
b13
b12
ADRFM
T
—
—
—
0
0
0
0
Value after reset:
b11
b10
DIAGM DIAGL
D
0
0
b9
b8
DIAGVAL[1:0]
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
ACE
—
—
ADPRC[1:0]
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2, b1
ADPRC[1:0]
A/D Conversion Accuracy Specify
b2 b1
R/W
b4, b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
ACE
A/D Data Register Automatic Clearing
Enable
0: Disable automatic clearing
1: Enable automatic clearing.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b9, b8
DIAGVAL[1:0]
Self-Diagnosis Conversion Voltage
Select
b9 b8
R/W
b10
DIAGLD
Self-Diagnosis Mode Select
0: Select rotation mode for self-diagnosis voltage
1: Select fixed mode for self-diagnosis voltage.
R/W
b11
DIAGM
Self-Diagnosis Enable
0: Disable ADC12 self-diagnosis
1: Enable ADC12 self-diagnosis.
R/W
b14 to b12 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
A/D Data Register Format Select
0: Select flush-right for the A/D data register format
1: Select flush-left for the A/D data register format.
R/W
Note 1.
ADRFMT
0
0
1
1
0
0
1
1
0: 12-bit accuracy
1: 10-bit accuracy
0: 8-bit accuracy
1: Setting prohibited.
0: Setting prohibited when self-diagnosis is enabled
1: 0 V
0: Reference power supply voltage*1 x 1/2
1: Reference power supply voltage.*1
The reference voltage refers to VREFH0 for unit 0 and to VREFH for unit 1.
ADPRC[1:0] bits (A/D Conversion Accuracy Specify)
The ADPRC[1:0] bits set the A/D conversion accuracy to 8-, 10-, or 12-bit accuracy. Changing the A/D conversion
accuracy also changes the bit width of valid data stored in the result register and the A/D conversion time. For details, see
section 45.3.6, Analog Input Sampling and Scan Conversion Time.
Only set the ADPRC[1:0] bits while the ADCSR.ADST bit is 0.
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45. 12-Bit A/D Converter (ADC12)
ACE bit (A/D Data Register Automatic Clearing Enable)
The ACE bit enables or disables automatic clearing (all 0s) of ADDRy, ADRD, ADDBLDR, ADDBLDRA,
ADDBLDRB, ADTSDR, or ADOCDR registers after any of these registers is read by the CPU, DTC, or DMAC.
Automatic clearing of the A/D data registers enables detection of failures that do not update the A/D data registers.
DIAGVAL[1:0] bits (Self-Diagnosis Conversion Voltage Select)
The DIAGVAL[1:0] bits select the voltage value used in self-diagnosis fixed voltage mode. For details, see the
ADCER.DIAGLD bit description.
Do not execute self-diagnosis by setting the ADCER.DIAGLD bit to 1 when the ADCER.DIAGVAL[1:0] bits are set to
00b.
DIAGLD bit (Self-Diagnosis Mode Select)
The DIAGLD bit selects whether the three voltage values are rotated, or fixed voltage is used in self-diagnosis. Setting
this bit to 0 allows conversion of the voltages in rotation mode where 0 V, the reference power supply × 1/2, and the
reference power supply are converted, in that order. After reset, when the self-diagnosis voltage rotation mode is
selected, self-diagnosis is executed from 0 V. The fixed voltage specified in the ADCER.DIAGVAL[1:0] bits is
converted when self-diagnosis fixed voltage mode is selected. In self-diagnosis voltage rotation mode, the self-diagnosis
voltage value does not return to 0 when scan conversion completes. When scan conversion restarts, rotation starts at the
voltage value following the previous value. If fixed mode is switched to rotation mode, rotation starts at the fixed voltage
value.
Only set the DIAGLD bit while the ADCSR.ADST bit is 0.
DIAGM bit (Self-Diagnosis Enable)
The DIAGM bit enables or disables self-diagnosis. Self-diagnosis is used to detect a failure of the ADC12. In selfdiagnosis mode, one of the internally generated voltage values (0, the reference power supply × 1/2, or the reference
power supply) is converted. When conversion completes, information on the converted voltage and the conversion result
is stored in the A/D Self-Diagnosis Data Register (ADRD). ADRD can be read by software to determine whether the
conversion result falls within the normal range (normal) or not (abnormal). Self-diagnosis is executed once at the
beginning of each scan, and one of the three voltages is converted. When the double-trigger mode is set (ADCSR.DBLE
= 1), always deselect self-diagnosis (DIAGM = 0). When self-diagnosis is selected in group scan mode, self-diagnosis is
executed separately on group A and group B.
Only set the DIAGM bit while the ADCSR.ADST bit is 0.
ADRFMT bit (A/D Data Register Format Select)
The ADRFMT bit specifies flush-right or flush-left for the data to be stored in ADDRy, ADDBLDR, ADDBLDRA,
ADDBLDRB, ADTSDR, ADOCDR, ADCMPDR0/1, ADWINLLB, ADWINULB, or ADRD.
Only set the ADRFMT bit the ADCSR.ADST bit is 0.
45.2.12
A/D Conversion Start Trigger Select Register (ADSTRGR)
Address(es): ADC120.ADSTRGR 4005 C010h, ADC121.ADSTRGR 4005 C210h
Value after reset:
b15
b14
—
—
0
0
b13
b12
b11
b10
b9
b8
TRSA[5:0]
0
0
0
0
0
0
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
0
0
TRSB[5:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
TRSB[5:0]
A/D Conversion Start Trigger Select
for Group B
These bits specify the A/D conversion start trigger for
group B in group scan mode.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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45. 12-Bit A/D Converter (ADC12)
Bit
Symbol
Bit name
Description
R/W
b13 to b8
TRSA[5:0]
A/D Conversion Start Trigger Select
These bits specify the A/D conversion start trigger in
single scan mode and continuous mode. In group scan
mode, the A/D conversion start trigger for group A is
selected.
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
TRSB[5:0] bits (A/D Conversion Start Trigger Select for Group B)
The TRSB[5:0] bits select the trigger to start scanning of the analog input selected in group B. The TRSB[5:0] bits must
only be set in group scan mode and are not used in any other scan mode. For the scan conversion start trigger for group
B, setting a software trigger or an asynchronous trigger is prohibited. In group scan mode, set the TRSB[5:0] bits to a
value other than 000000b, and set the ADCSR.TRGE bit to 1.
When group A is given priority in group scan mode, setting the ADGSPCR.GBRP bit to 1 allows group B to
continuously operate in single scan mode. When setting the ADGSPCR.GBRP bit to 1, set the TRSB[5:0] bits to 3Fh.
The issuance period for a conversion trigger must be more than or equal to the actual scan conversion time (tSCAN). If
the issuance period is less than tSCAN, A/D conversion by the trigger might have no effect.
When the trigger from a module operated at 120 MHz (GPT) is selected as an A/D conversion start trigger, a delay for
synchronization processing occurs. For details, see section 45.3.6, Analog Input Sampling and Scan Conversion Time.
Table 45.6 lists the A/D conversion startup sources selected in the TRSB[5:0] bits.
TRSA[5:0] bits (A/D Conversion Start Trigger Select)
The TRSA[5:0] bits select the trigger to start A/D conversion in single scan mode and continuous scan mode. In group
scan mode, the trigger to start scanning of the analog input selected in group A is selected. When scanning is executed in
group scan mode or double-trigger mode, setting a software trigger or an asynchronous trigger is prohibited.
When using a synchronous trigger (ELC) as the A/D conversion start source, set the TRGE bit in ADCSR to 1 and the
EXTRG bit in ADCSR to 0.
When using the asynchronous trigger (ADTRGn), set the TRGE bit in ADCSR to 1 and the EXTRG bit in ADCSR to 1.
The software trigger (ADCSR.ADST) is enabled regardless of the settings in the ADCSR.TRGE bit, the
ADCSR.EXTRG bit, or the TRSA[5:0] bits. The issuance period for a conversion trigger must be more than or equal to
the actual scan conversion time (tSCAN). If the issuance period is less than tSCAN, A/D conversion by the trigger might
have no effect.
When the trigger from a module operated at 120 MHz (GPT) is selected as an A/D conversion start trigger, a delay period
for synchronization processing occurs. For details, see section 45.3.6, Analog Input Sampling and Scan Conversion
Time.
Table 45.7 lists the A/D conversion start sources selected in the TRSA[5:0] bits.
Table 45.6
Selection of A/D conversion start sources in the TRSB[5:0] bits
Source
Remarks
Trigger source deselected state
TRSB[5]
TRSB[4]
TRSB[3]
TRSB[2]
TRSB[1]
TRSB[0]
1
1
1
1
1
1
ELC_ADC00 (unit 0),
ELC_ADC10 (unit 1)
ELC
0
0
1
0
0
1
ELC_ADC01 (unit 0),
ELC_ADC11 (unit 1)
ELC
0
0
1
0
1
0
ELC_ADC00/ELC_ADC01 (unit 0)
ELC_ADC10/ELC_ADC11 (unit 1)
ELC
0
0
1
0
1
1
Table 45.7
Selection of A/D activation sources in the TRSA[5:0] bits (1 of 2)
Source
Trigger source deselected state
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Remarks
TRSA[5]
TRSA[4]
TRSA[3]
TRSA[2]
TRSA[1]
TRSA[0]
1
1
1
1
1
1
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Table 45.7
45. 12-Bit A/D Converter (ADC12)
Selection of A/D activation sources in the TRSA[5:0] bits (2 of 2)
Source
Remarks
TRSA[5]
TRSA[4]
TRSA[3]
TRSA[2]
TRSA[1]
TRSA[0]
ADTRGn
Input pin for the
trigger
0
0
0
0
0
0
ELC_ADC00 (unit 0), ELC_ADC10
(unit 1)
ELC
0
0
1
0
0
1
ELC_ADC01 (unit 0), ELC_ADC11 (unit
1)
ELC
0
0
1
0
1
0
ELC_ADC00/ELC_ADC01 (unit 0)
ELC_ADC10/ELC_ADC11 (unit 1)
ELC
0
0
1
0
1
1
45.2.13
A/D Conversion Extended Input Control Register (ADEXICR)
Address(es): ADC120.ADEXICR 4005 C012h, ADC121.ADEXICR 4005 C212h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
—
—
—
—
OCSB
TSSB
OCSA
TSSA
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b1
b0
OCSAD TSSAD
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TSSAD
Temperature Sensor Output A/DConverted Value Addition/Average
Mode Select
0: Do not select addition/average mode for temperature
sensor output
1: Select addition/average mode for temperature sensor
output.
R/W
b1
OCSAD
Internal Reference Voltage A/DConverted Value Addition/Average
Mode Select
0: Do not select addition/average mode for internal
reference voltage
1: Select addition/average mode for internal reference
voltage.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
TSSA
Temperature Sensor Output A/D
Conversion Select
0: Disable A/D conversion of temperature sensor output
1: Enable A/D conversion of temperature sensor output.
R/W
b9
OCSA
Internal Reference Voltage A/D
Conversion Select
0: Disable A/D conversion of internal reference voltage
1: Enable A/D conversion of internal reference voltage.
R/W
b10
TSSB
Temperature Sensor Output A/D
Conversion Select for Group B
Selection for group B in group scan mode.
0: Disable A/D conversion of temperature sensor output
1: Enable A/D conversion of temperature sensor output.
R/W
b11
OCSB
Internal Reference Voltage A/D
Conversion Select for Group B
Selection for group B in group scan mode.
0: Disable A/D conversion of internal reference voltage
1: Enable A/D conversion of internal reference voltage.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b12 —
TSSAD bit (Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select)
When the TSSAD bit is set to 1, A/D conversion of the temperature sensor output is selected and performed successively
the number of times specified in the ADC[2:0] bits in ADADC. The maximum addition count differs depending on the
conversion accuracy (see section 45.2.2, A/D Self-Diagnosis Data Register (ADRD)). When the ADADC.AVEE bit is 0,
the value obtained by addition (integration) is returned to the A/D Temperature sensor Data Register (ADTSDR). When
the ADADC.AVEE bit is 1, the mean value is returned to ADTSDR.
Only set the TSSAD bit while the ADCSR.ADST bit is 0.
OCSAD bit (Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select)
When the OCSAD bit is set to 1, A/D conversion of the internal reference voltage is selected and performed successively
for the number of times specified in the ADC[2:0] bits in ADADC. The maximum addition count differs depending on
the conversion accuracy (see 45.2.2 A/D Self-Diagnosis Data Register (ADRD)). When the ADADC.AVEE bit is 0, the
value obtained by addition (integration) is returned to the A/D Internal Reference Voltage Data Register (ADOCDR).
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45. 12-Bit A/D Converter (ADC12)
When the ADADC.AVEE bit is 1, the mean value is returned to ADOCDR.
Only set the OCSAD bit while the ADCSR.ADST bit is 0.
TSSA bit (Temperature Sensor Output A/D Conversion Select)
The TSSA bit selects A/D conversion of the temperature sensor output for group A in single scan mode, continuous scan
mode, or group scan mode. When A/D conversion of the temperature sensor output is selected and performed, set the
ADCSR.DBLE bit to 0.
Only set the TSSA bit while the ADCSR.ADST bit is 0.
OCSA bit (Internal Reference Voltage A/D Conversion Select)
The OCSA bit selects A/D conversion of the internal reference voltage for group A in single scan mode, continuous scan
mode, or group scan mode. When A/D conversion of the internal reference voltage is selected and performed, set the
ADCSR.DBLE bit to 0.
Only set the OCSA bit while the ADCSR.ADST bit is 0. In addition, wait for 400 ns or more after the OCSA bit is set to
1 before starting A/D conversion.
TSSB bit (Temperature Sensor Output A/D Conversion Select for Group B)
The TSSB bit selects A/D conversion of the temperature sensor output for group B in group scan mode.
Only set the TSSB bit while the ADCSR.ADST bit is 0. Do not set the TSSB bit to 1 while the TSSA bit is 1.
OCSB bit (Internal Reference Voltage A/D Conversion Select for Group B)
The OCSB bit selects A/D conversion of the internal reference voltage for group B in group scan mode.
Only set the OCSB bit while the ADCSR.ADST bit is 0. Do not set the OCSB bit to 1 while the OCSA bit is 1.
Moreover, start the A/D conversion after waiting for 400 ns or more after the OCSB bit is set to 1.
45.2.14
A/D Sampling State Register n (ADSSTRn) (n = 00 to 07, L, T, O)
Address(es): ADC120.ADSSTR00 4005 C0E0h to ADC120.ADSSTR07 4005 C0E7h,
ADC120.ADSSTRL 4005 C0DDh, ADC120.ADSSTRT 4005 C0DEh, ADC120.ADSSTRO 4005 C0DFh,
ADC121.ADSSTR00 4005 C2E0h to ADC121.ADSSTR03 4005 C2E3h,
ADC121.ADSSTR05 4005 C2E5h to ADC121.ADSSTR07 4005 C2E7h,
ADC121.ADSSTRL 4005 C2DDh, ADC121.ADSSTRT 4005 C2DEh, ADC121.ADSSTRO 4005 C2DFh
b7
b6
b5
b4
b3
b2
b1
b0
0
1
1
SST[7:0]
Value after reset:
0
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b7 to b0
SST[7:0]
Sampling Time Setting
These bits set the sampling time in the range from 5 to 255 states
R/W
The ADSSTRn register sets the sampling time for the analog input. If one state is 1 ADCLK (A/D conversion clock)
cycle and the ADCLK clock is 60 MHz, one state is 16.7 ns. The initial value is 11 states. The sampling time can be
adjusted if the impedance of the analog input signal source is too high to secure sufficient sampling time, or if the
ADCLK clock is slow.
Only set the SST[7:0] bits while the ADCSR.ADST bit is 0.
The lower limit of the sampling time setting depends on the frequency ratio, as follows:
If the frequency ratio of PCLKB to PCLKC(ADCLK) = 1:1, 2:1, 4:1, or 8:1, the sampling time must be set to a
value of more than 5 states
If the frequency ratio of PCLKB to PCLKC(ADCLK) = 1:2 or 1:4, the sampling time must be set to a value of more
than 6 states.
Table 45.8 shows the relationship between the A/D Sampling State Register and the associated channels.
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45. 12-Bit A/D Converter (ADC12)
For details, see section 45.3.6, Analog Input Sampling and Scan Conversion Time.
Table 45.8
Relationship between A/D sampling state register and associated channels
Associated channels
Bit name
Unit 0
Unit 1
ADSSTR00.SST[7:0] bits*1
AN000
AN100
ADSSTR01.SST[7:0] bits
AN001
AN101
ADSSTR02.SST[7:0] bits
AN002
AN102
ADSSTR03.SST[7:0] bits
AN003
-
ADSSTR04.SST[7:0] bits
AN004
-
ADSSTR05.SST[7:0] bits
AN005
AN105
ADSSTR06.SST[7:0] bits
AN006
AN106
ADSSTR07.SST[7:0] bits
AN007
AN107
ADSSTRL.SST[7:0] bits
AN016 to AN020
AN116 to AN118
ADSSTRT.SST[7:0] bits
Temperature sensor output
Temperature sensor output
ADSSTRO.SST[7:0] bits
Internal reference voltage
Internal reference voltage
Note 1.
When the self-diagnosis function is selected, the sampling time set in the ADSSTR00.SST[7:0] bits is applied.
45.2.15
A/D Sample and Hold Circuit Control Register (ADSHCR)
Address(es): ADC120.ADSHCR 4005 C066h, ADC121.ADSHCR 4005 C266h
Value after reset:
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
b10
b9
b8
b7
b6
b5
SHANS[2:0]
0
0
b4
b3
b2
b1
b0
0
0
0
SSTSH[7:0]
0
0
0
0
1
1
Bit
Symbol
Bit name
Description
R/W
b7 to b0
SSTSH[7:0]
Channel-Dedicated Sample-and-Hold
Circuit Sampling Time Setting
Sampling time (4 to 255 states)
R/W
b10 to b8
SHANS[2:0]
Channel-Dedicated Sample-and-Hold
Circuit Bypass Select
Select whether to use or bypass channel-dedicated
sample-and-hold circuits for AN000 to AN002 (unit 0)
and AN100 to AN102 (unit 1).
0: Bypass the circuits
1: Use the circuits.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
SSTSH[7:0] bits (Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting)
The SSTSH[7:0] bits set the sampling time for the channel-dedicated sample-and-hold circuits. If one state is 1 ADCLK
(A/D conversion clock) cycle and the ADCLK clock is 60 MHz, one state is 16.7 ns. The initial value is 24 states. The
sampling time can be adjusted if the impedance of the analog input signal source is too high to secure sufficient sampling
time, or if the ADCLK clock is slow.
Only set the SSTSH[7:0] bits while the ADCSR.ADST bit is 0. The sampling time must be set to a value that is 4 states
or more and 255 or less.
SHANS[2:0] bits (Channel-Dedicated Sample-and-Hold Circuit Bypass Select)
The SHANS[2:0] bits select whether to use or bypass the channel-dedicated sample-and-hold circuits for AN000 to
AN002 (unit 0) and AN100 to AN102 (unit 1). In unit 0, the SHANS[0] bit is associated with AN000, the SHANS[1] bit
with AN001, and the SHANS[2] bit with AN002. In unit 1, the SHANS[0] bit is associated with AN100, the SHANS[1]
bit with AN101, and the SHANS[2] bit with AN102.
If any channel from among AN000 to AN002 (unit 0) or AN100 to AD102 (unit 1) is selected for group B while
operation is in group scan mode under group A priority control, use this setting to bypass the dedicated sample-and-hold
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45. 12-Bit A/D Converter (ADC12)
circuit of the channel.
Only set the SHANS[2:0] bits while the ADCSR.ADST bit is 0 and the ADSHMSR.SHMD bit is 0.
45.2.16
A/D Sample and Hold Operation Mode Selection Register (ADSHMSR)
Address(es): ADC120.ADSHMSR 4005 C07Ch, ADC121.ADSHMSR 4005 C27Ch
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
SHMD
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SHMD
Sampling Operation Selection
0: Disable continuous sampling function
1: Enable continuous sampling function.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
SHMD bit (Sampling Operation Selection)
Setting SHMD to 1 enables the constant sampling function of the channel-dedicated sample-and-hold selected in the
ADSHCR.SHANS[2:0] bits. Only set the SHMD bit while the ADCSR.ADST bit is 0.
When the sampling function is enabled, the sample-and-hold circuit operates sampling while the ADC12 is not
operating, and it operates holding while the ADC12 is operating.
Note:
The ADCSR.ADST bit must become 1 after a time of 400 ns or more elapses after the SHMD bit is set to 1 (when
the permissible signal source impedance is 1 kΩ). The sampling period of the sample-and-hold circuit must be
400 ns or more (when the permissible signal source impedance is 1 kΩ).
45.2.17
A/D Disconnection Detection Control Register (ADDISCR)
Address(es): ADC120.ADDISCR 4005 C07Ah, ADC121.ADDISCR 4005 C27Ah
Value after reset:
b7
b6
b5
b4
—
—
—
PCHG
0
0
0
0
b3
b2
b1
b0
ADNDIS[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
ADNDIS[3:0]
Disconnection Detection Assist
Setting
b3 to b0
0000: The disconnection detection assist function is
disabled
0001: Setting prohibited
Others: The number of states for the discharge or
precharge period.
R/W
b4
PCHG
PCHG Precharge/Discharge Select
0: Discharge
1: Precharge.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The ADDISCR register selects either precharge or discharge, and the period of precharge or discharge for the A/D
disconnection detection assist function.
Only set the ADDISCR register when the ADCSR.ADST bit is 0. If any of the following functions are used, the
disconnection detection assist function must be disabled:
The temperature sensor
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45. 12-Bit A/D Converter (ADC12)
The internal reference voltage
A/D Self-diagnosis.
ADNDIS[3:0] bits (Disconnection Detection Assist Setting)
The ADNDIS[3:0] bits specify the period of precharge or discharge. When ADNDIS[3:0] = 0000b, the disconnection
detection assist function is disabled. Setting the ADNDIS[3:0] bits to 0001b is prohibited. Except when ADNDIS[3:0] =
0000b or 0001b, the specified value indicates the number of states for the period of precharge or discharge. When the
ADNDIS[3:0] bits are set to any values other than 0000b or 0001b, the disconnection detection assistance function is
enabled.
PCHG bit (PCHG Precharge/Discharge Select)
Setting the PCHG bit to 1 selects precharge, and setting the PCHG bit to 0 selects discharge.
45.2.18
A/D Group Scan Priority Control Register (ADGSPCR)
Address(es): ADC120.ADGSPCR 4005 C080h, ADC121.ADGSPCR 4005 C280h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
GBRP
—
—
—
—
—
—
—
—
—
—
—
—
—
GBRSC
N
PGS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
PGS
group A Priority Control Setting*1
0: Operate without group A priority control
1: Operate with group A priority control.
R/W
b1
GBRSCN
Group B Restart Setting
Enabled only when PGS = 1. Reserved when PGS = 0.
0: Do not restart group B scanning after it is stopped by group
A priority control
1: Restart group B scanning after it is stopped by group A
priority control.
R/W
b14 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
GBRP
Group B Single Scan Continuous
Start*2
Enabled only when PGS = 1. Reserved when PGS = 0.
0: Do not continuously activate single scan for group B
1: Continuously activate single scan for group B.
R/W
Note 1. The ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode) before setting PGS to 1. Operation is not
guaranteed if these bits are set to any other value.
Note 2. When the GBRP bit is set to 1, single scan is performed continuously for group B regardless of the setting in the
GBRSCN bit.
PGS bit (group A Priority Control Setting*1)
Set the PGS bit to 1 to give priority to operation on group A. The ADCSR.ADCS[1:0] bits must be set to 01b (group scan
mode) before setting the PGS bit to 1. Operation is not guaranteed if the bits are set to any other value.
When the PGS bit is set to 0, a clear operation must be performed by software as described in section 45.6.2, Constraints
on Stopping A/D Conversion. When the PGS bit is set to 1, use the settings described in section 45.3.4.3, Operation with
group A priority control.
GBRSCN bit (Group B Restart Setting)
The GBRSCN bit controls the restarting of scan operation on group B when operation on group A is given priority. If a
scan operation on group B is stopped by a group A trigger input with the GBRSCN bit set to 1, the scan operation is
restarted on completion of group A conversion. Also, if a group B trigger is input during A/D conversion on group A, the
scan operation on group B is restarted on completion of group A conversion.
When the GBRSCN bit is set to 0, triggers input during A/D conversion are ignored. Only set the GBRSCN bit while the
ADCSR.ADST bit is 0.
The setting in the GBRSCN bit is valid when the PGS bit is 1.
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45. 12-Bit A/D Converter (ADC12)
GBRP bit (Group B Single Scan Continuous Start*2)
Set the GBRP bit to perform a single scan operation continuously on group B. Setting the GBRP bit to 1 starts a single
scan on group B. On completion of the scan, another single scan on group B starts automatically. If a group B conversion
stops because of an operation on group A, group A operation takes priority, and single scan on group B restarts
automatically on completion of the group A conversion.
Disable group B trigger input before setting the GBRP bit to 1. Setting the GBRP bit to 1 invalidates the setting in the
GBRSCN bit. Only set the GBRP bit while the ADCSR.ADST is 0.
The setting in the GBRP bit is valid when the PGS bit is 1.
45.2.19
A/D Compare Function Control Register (ADCMPCR)
Address(es): ADC120.ADCMPCR 4005 C090h, ADC121.ADCMPCR 4005 C290h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
—
CMPAE
—
CMPBE
—
—
—
—
—
—
—
CMPAB[1:0]
0
0
0
0
0
0
0
0
0
0
0
CMPAI WCMP CMPBI
E
E
E
0
Value after reset:
0
0
0
0
Bit
Symbol
Bit name
b1, b0
CMPAB[1:0]
Window A/B Composite
Conditions Setting
b8 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b9
CMPBE
Compare Window B
Operation Enable
0: Disable compare Window B operation.
Disable ADC12i_WCMPM and ADC12i_WCMPUM outputs.
1: Enable compare Window B operation.
R/W
b10
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b11
CMPAE
Compare Window A
Operation Enable
0: Disable compare Window A operation.
Disable ADC12i_WCMPM and ADC12i_WCMPUM outputs.
1: Enable compare Window A operation.
R/W
b12
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b13
CMPBIE
Compare B Interrupt
Enable
0: Disable ADC12i_CMPBI interrupt when comparison conditions
(Window B) are met
1: Enable ADC12i_CMPBI interrupt when comparison conditions
(Window B) are met.
R/W
b14
WCMPE
Window Function Setting
0: Disable window function.
Window A and Window B operate as a comparator to compare the
single value on the lower side with the A/D conversion result.
1: Enable window function.
Window A and Window B operate as a comparator to compare the
two values on the upper and lower sides with the A/D conversion
result.
R/W
b15
CMPAIE
Compare A Interrupt
Enable
0: Disable ADC12i_CMPAI interrupt when comparison conditions
(Window A) are met
1: Enable ADC12i_CMPAI interrupt when comparison conditions
(Window A) are met.
R/W
Note:
Description
b0
R/W
b1 b0
0 0: Output ADC12i_WCMPM when Window A OR Window B comparison conditions are met; otherwise, output
ADC12i_WCMPUM
0 1: Output ADC12i_WCMPM when Window A EXOR Window B
comparison conditions are met; otherwise, output
ADC12i_WCMPUM
1 0: Output ADC12i_WCMPM when Window A AND Window B
comparison conditions are met; otherwise, output
ADC12i_WCMPUM
1 1: Setting prohibited.
These bits are valid when both Window A and Window B are enabled
(CMPAE = 1 and CMPBE = 1).
R/W
i = 0: unit 0, i = 1: unit 1.
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45. 12-Bit A/D Converter (ADC12)
CMPAB[1:0] bits (Window A/B Composite Conditions Setting)
The CMPAB[1:0] bits are valid when both Window A and Window B are enabled (CMPAE = 1 and CMPBE = 1) in
single scan mode. These bits specify the compare function match/mismatch event output conditions and monitoring
conditions of ADWINMON.MONCONB.
Only set the CMPAB[1:0] bits while the ADCSR.ADST bit is 0.
CMPBE bit (Compare Window B Operation Enable)
The CMPBE bit enables or disables the compare Window B operation. Set the CMPBE bit while the ADCSR.ADST bit
is 0.
Set this bit to 0 before setting the following registers:
A/D Channel Select Registers, ADANSA0, ADANSA1, ADANSB0, and ADANSB1
OCSB, TSSB, OCSA, or TSSA bits in the A/D Conversion Extended Input Control Register (ADEXICR)
CMPCHB[5:0] bits in the Window B Channel Select Register (ADCMPBNSR).
CMPAE bit (Compare Window A Operation Enable)
The CMPAE bit enables or disables the compare Window A operation. Set the CMPAE bit while the ADCSR.ADST bit
is 0.
Set this bit to 0 before setting the following registers:
A/D Channel Select Registers,ADANSA0, ADANSA1, ADANSB0, and ADANSB1
OCSB, TSSB, OCSA, or TSSA bits in the A/D Conversion Extended Input Control Register (ADEXICR)
Window A Channel Select Registers 0 and 1 (ADCMPANSR0 and ADCMPANSR1)
Window A Extended Input Select Register (ADCMPANSER).
CMPBIE bit (Compare B Interrupt Enable)
The CMPBIE bit enables or disables the ADC12i_CMPBI (i = 0, 1) interrupt output when the comparison conditions
(Window B) are met.
WCMPE bit (Window Function Setting)
The WCMPE bit enables or disables the window function. Set the WCMPE bit while the ADCSR.ADST bit is 0.
CMPAIE bit (Compare A Interrupt Enable)
The CMPAIE bit enables or disables the ADC12i_CMPAI (i = 0, 1) interrupt output when the comparison conditions
(Window A) are met.
45.2.20
A/D Compare Function Window A Channel Select Register 0 (ADCMPANSR0)
Address(es): ADC120.ADCMPANSR0 4005 C094h, ADC121.ADCMPANSR0 4005 C294h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
CMPC CMPC CMPC CMPC CMPC CMPC CMPC CMPC
HA07 HA06 HA05 HA04 HA03 HA02 HA01 HA00
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CMPCHA07 to
CMPCHA00
Compare Window A Channel
Select
0: Disable compare function for associated input channel
1: Enable compare function for associated input channel.
In unit 0, bit [7] (CMPCHA07) is associated with AN007 and
bit 0 (CMPCHA00) with AN000.
In unit 1, bit [7] (CMPCHA07) is associated with AN107 and
bit 0 (CMPCHA00) with AN100.
R/W
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45. 12-Bit A/D Converter (ADC12)
Bit
Symbol
Bit name
Description
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPCHAn bits (n = 00 to 07) (Compare Window A Channel Select)
The compare function is enabled by writing 1 to the CMPCHAn bit with the same number as the A/D conversion channel
selected in the ADANSA0.ANSAn bits (n = 00 to 07) and the ADANSB0.ANSBn bits (n = 00 to 07).
Set the CMPCHAn bits while the ADCSR.ADST bit is 0.
45.2.21
A/D Compare Function Window A Channel Select Register 1 (ADCMPANSR1)
Address(es): ADC120.ADCMPANSR1 4005 C096h, ADC121.ADCMPANSR1 4005 C296h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
CMPC CMPC CMPC CMPC CMPC
HA20 HA19 HA18 HA17 HA16
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
CMPCHA20 to
CMPCHA16
Compare Window A Channel
Select
0: Disable compare function for associated input channel
1: Enable compare function for associated input channel.
In unit 0, bit [4] (CMPCHA20) is associated with AN020 and bit 0
(CMPCHA16) with AN016.
In unit 1, bit [2] (CMPCHA18) is associated with AN118 and bit 0
(CMPCHA16) with AN116.
R/W
b15 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPCHAn bits (n = 16 to 20) (Compare Window A Channel Select)
The compare function is enabled by writing 1 to the CMPCHAn bit with the same number as the A/D conversion channel
selected in the ADANSA1.ANSAn bits (n = 16 to 20) and the ADANSB1.ANSBn bits (n = 16 to 20).
Set the CMPCHAn bits while the ADCSR.ADST bit is 0.
45.2.22
A/D Compare Function Window A Extended Input Select Register
(ADCMPANSER)
Address(es): ADC120.ADCMPANSER 4005 C092h, ADC121.ADCMPANSER 4005 C292h
b7
Value after reset:
b6
b5
b4
b3
b2
—
—
—
—
—
—
0
0
0
0
0
0
b1
b0
CMPO CMPTS
CA
A
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CMPTSA
Temperature Sensor
Output Compare Select
0: Exclude the temperature sensor output from the compare Window
A target range
1: Include the temperature sensor output in the compare Window A
target range.
R/W
b1
CMPOCA
Internal Reference
Voltage Compare Select
0: Exclude the internal reference voltage from the compare Window A
target range.
1: Include the internal reference voltage in the compare Window A
target range.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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45. 12-Bit A/D Converter (ADC12)
CMPTSA bit (Temperature Sensor Output Compare Select)
The compare Window A function is enabled by setting the CMPTSA bit to 1 while the ADEXICR.TSSA bit or the
ADEXICR.TSSB bit is 1. Set the CMPTSA bit while the ADCSR.ADST bit is 0.
CMPOCA bit (Internal Reference Voltage Compare Select)
The compare Window A function is enabled by setting the CMPOCA bit to 1 while the ADEXICR.OCSA bit or the
ADEXICR.OCSB bit is 1. Set the CMPOCA bit while the ADCSR.ADST bit is 0.
45.2.23
A/D Compare Function Window A Comparison Condition Setting Register 0
(ADCMPLR0)
Address(es): ADC120.ADCMPLR0 4005 C098h, ADC121.ADCMPLR0 4005 C298h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC
HA07 HA06 HA05 HA04 HA03 HA02 HA01 HA00
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CMPLCHA07 to
CMPLCHA00
Compare Window A
Comparison Condition
Select
These bits set comparison conditions for channels, selected from
AN000 to AN007 (unit 0) and AN100 to AN102, AN105 to AN107
(unit 1), to which Window A comparison conditions are applied.
Comparison conditions are shown in Figure 45.4.
When window function is disabled (ADCMPCR.WCMPE = 0)
0: ADCMPDR0 value > A/D-converted value
1: ADCMPDR0 value < A/D-converted value.
R/W
When window function is enabled (ADCMPCR.WCMPE = 1)
0: A/D-converted value < ADCMPDR0 value, or
ADCMPDR1 value < A/D-converted value
1: ADCMPDR0 value < A/D-converted value < ADCMPDR1 value.
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPLCHAn bits (n = 00 to 07) (Compare Window A Comparison Condition Select)
The CMPLCHAn bits specify the comparison conditions for channels, selected from AN000 to AN007 (unit 0) and
AN100 to AN102, AN105 to AN107 (unit 1), to which Window A comparison conditions are applied. These bits can be
set for each analog input to be compared. In unit 0, CMPLCHA00 is associated with AN000 and CMPLCHA07 with
AN007. In unit 1, CMPLCHA00 is associated with AN100 and CMPLCHA07 with AN107. When the comparison result
of each analog input meets the set condition, the ADCMPSR0.CMPSTCHAn flag is set to 1, and a compare interrupt
(ADC12i_CMPAI (i = 0, 1)) is generated.
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45. 12-Bit A/D Converter (ADC12)
Comparison conditions when the window function is disabled
CMPLCHAn = 0
CMPLCHAn = 1
ADCMPDR0 value A/D converted value
Not met
ADCMPDR0 value < A/D converted value
Met
ADCMPDR0 value > A/D converted value
Met
ADCMPDR0 value A/D converted value
Not met
Comparison conditions when the window function is enabled
CMPLCHAn = 0
ADCMPDR1 value < A/D converted value
ADCMPDR0 value A/D converted value ADCMPDR1 value
A/D converted value < ADCMPDR0 value
Met
Not met
Met
CMPLCHAn = 1
ADCMPDR1 value A/D converted value
ADCMPDR0 value < A/D converted value < ADCMPDR1 value
A/D converted value ADCMPDR0 value
Figure 45.4
Not met
Met
Not met
Explanation of comparison conditions for compare function Window A
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45.2.24
45. 12-Bit A/D Converter (ADC12)
A/D Compare Function Window A Comparison Condition Setting Register 1
(ADCMPLR1)
Address(es): ADC120.ADCMPLR1 4005 C09Ah, ADC121.ADCMPLR1 4005 C29Ah
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
CMPLC CMPLC CMPLC CMPLC CMPLC
HA20 HA19 HA18 HA17 HA16
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
CMPLCHA20 to
CMPLCHA16
Compare Window A
Comparison Condition
Select
These bits set comparison conditions for channels, selected from
AN016 to AN020 (unit 0) and AN116 to AN118 (unit 1), to which
Window A comparison conditions are applied. Comparison
conditions are shown in Figure 45.4.
When window function is disabled (ADCMPCR.WCMPE = 0)
0: ADCMPDR0 value > A/D-converted value
1: ADCMPDR0 value < A/D-converted value.
R/W
When window function is enabled (ADCMPCR.WCMPE = 1)
0: A/D-converted value < ADCMPDR0 value, or
ADCMPDR1 value < A/D-converted value
1: ADCMPDR0 value < A/D-converted value < ADCMPDR1 value.
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPLCHAn bits (n = 16 to 20) (Compare Window A Comparison Condition Select)
The CMPLCHAn bits specify the comparison conditions for channels, selected from AN016 to AN020 (unit 0) and
AN116 to AN118 (unit 1) to which Window A comparison conditions are applied. These bits can be set for each analog
input to be compared. In unit 0, CMPLCHA16 is associated with AN016 and CMPLCHA20 with AN020. In unit 1,
CMPLCHA16 is associated with AN116 and CMPLCHA18 with AN118. When the comparison result of each analog
input meets the set condition, the ADCMPSR1.CMPSTCHAn flag is set to 1 and a compare interrupt (ADC12i_CMPAI
(i = 0, 1)) is generated.
45.2.25
A/D Compare Function Window A Extended Input Comparison Condition
Setting Register (ADCMPLER)
Address(es): ADC120.ADCMPLER 4005 C093h, ADC121.ADCMPLER 4005 C293h
Value after reset:
b7
b6
b5
b4
b3
b2
—
—
—
—
—
—
0
0
0
0
0
0
b1
b0
CMPLO CMPLT
CA
SA
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CMPLTSA
Compare Window A
Temperature Sensor
Output Comparison
Condition Select
Comparison conditions are shown in Figure 45.4.
When window function is disabled (ADCMPCR.WCMPE = 0)
0: ADCMPDR0 value > A/D-converted value
1: ADCMPDR0 value < A/D-converted value.
R/W.
When window function is enabled (ADCMPCR.WCMPE = 1)
0: A/D-converted value < ADCMPDR0 value, or
A/D-converted value > ADCMPDR1 value
1: ADCMPDR0 value < A/D-converted value < ADCMPDR1 value.
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45. 12-Bit A/D Converter (ADC12)
Bit
Symbol
Bit name
Description
R/W
b1
CMPLOCA
Compare Window A
Internal Reference
Voltage Comparison
Condition Select
Comparison conditions are shown in Figure 45.4.
When window function is disabled (ADCMPCR.WCMPE = 0)
0: ADCMPDR0 register value > A/D-converted value
1: ADCMPDR0 register value < A/D-converted value.
R/W
When window function is enabled (ADCMPCR.WCMPE = 1)
0: A/D-converted value < ADCMPDR0 register value, or
A/D-converted value > ADCMPDR1 register value
1: ADCMPDR0 register value < A/D-converted value < ADCMPDR1
register value.
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R
CMPLTSA bit (Compare Window A Temperature Sensor Output Comparison Condition Select)
The CMPLTSA bit specifies the comparison conditions when the temperature sensor output is the target for the Window
A comparison condition. When the temperature sensor output comparison result meets the set condition, the
ADCMPSER.CMPSTTSA flag is set to 1 and a compare interrupt (ADC12i_CMPAI (i = 0, 1)) is generated.
CMPLOCA bit (Compare Window A Internal Reference Voltage Comparison Condition Select)
The CMPLOCA bit specifies the comparison conditions when the internal reference voltage is the target for the Window
A comparison condition. When the internal reference voltage comparison result meets the set condition, the
ADCMPSER.CMPSTOCA flag is set to 1 and a compare interrupt (ADC12i_CMPAI) is generated.
45.2.26
A/D Compare Function Window A Lower-Side Level Setting Register
(ADCMPDR0), A/D Compare Function Window A Upper-Side Level Setting
Register (ADCMPDR1), A/D Compare Function Window B Lower-Side Level
Setting Register (ADWINLLB), A/D Compare Function Window B Upper-Side
Level Setting Register (ADWINULB)
Address(es): ADC120.ADCMPDR0 4005 C09Ch, ADC120.ADCMPDR1 4005 C09Eh,
ADC120.ADWINLLB 4005 C0A8h, ADC120.ADWINULB 4005 C0AAh,
ADC121.ADCMPDR0 4005 C29Ch, ADC121.ADCMPDR1 4005 C29Eh,
ADC121.ADWINLLB 4005 C2A8h, ADC121.ADWINULB 4005 C2AAh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
—
—
Reference value
R/W
The ADCMPDRy (y = 0,1) register specifies the reference data when the compare Window A function is used.
ADCMPDR0 sets the lower reference for Window A, and ADCMPDR1 sets the upper reference for Window A.
ADWINULB and ADWINLLB specify the reference data when the compare Window B function is used. ADWINLLB
sets the lower reference for Window B, and ADWINULB sets the upper reference for Window B. The ADCMPDRy,
ADWINULB, and ADWINLLB are read/write registers.
ADCMPDRy, ADWINULB, and ADWINLLB can be written to, even during A/D conversion. The reference data can be
dynamically changed by rewriting register values during A/D conversion.
Set these registers so that the upper reference is not less than the lower reference (ADCMPDR1 ADCMPDR0 and
ADWINULB ADWINLLB). ADCMPDR1 and ADWINULB are not used when the window function is disabled.
The lower and the upper references are changed when each register is written. For example, when the upper reference
value is changed and the lower reference value is being changed, the MCU compares the upper reference (after a
rewrite), and the lower reference (before a rewrite) with the A/D conversion result. (See Figure 45.5.) If the comparison
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45. 12-Bit A/D Converter (ADC12)
during the rewriting of these two references is erroneous, then rewrite these reference values when both ADCSR.ADST
and the associated compare window operation enable bit (ADCMPCR.CMPAE or ADCMPCR.CMPBE) is 0.
Write timing
ADCMPDR1/
ADWINULB
Write timing
ADCMPDR0/
ADWINLLB
Upper reference
(before rewrite)
Upper reference
(after rewrite)
Lower reference
(before rewrite)
A/D conversion 1
A/D conversion 2
Compare the reference
before rewrite
Figure 45.5
Lower reference
(after rewrite)
A/D conversion 3
Compare the upper reference
(after rewrite)
and the lower reference
(before rewrite)
Compare the reference after
rewrite
Comparison between upper and lower references before and after a rewrite
The ADCMPDRy, ADWINLLB, and ADWINULB registers use different formats depending on the following
conditions:
The value in the A/D Data Register Format Select bit (flush-right or flush-left)
The value in the A/D Conversion Accuracy Specify bit (12-bit, 10-bit, or 8-bit)
The value in the A/D-Converted Value Addition/Average Channel Select bits (A/D-converted value addition mode
selected or not selected).
The data formats for each condition are as follows:
(1)
When A/D-converted value addition mode is not selected
Flush-right data with 12-bit accuracy: Lower 12 bits ([11:0]) are valid
Flush-right data with 10-bit accuracy: Lower 10 bits ([9:0]) are valid
Flush-right data with 8-bit accuracy: Lower 8 bits ([7:0]) are valid
Flush-left data with 12-bit accuracy: Upper 12 bits ([15:4]) are valid
Flush-left data with 10-bit accuracy: Upper 10 bits ([15:6]) are valid
Flush-left data with 8-bit accuracy: Upper 8 bits ([15:8]) are valid.
(2)
When A/D-converted value addition mode is selected
Flush-right data with 12-bit accuracy: Lower 14 bits ([13:0]) are valid
Flush-right data with 10-bit accuracy: Lower 12 bits ([11:0]) are valid
Flush-right data with 8-bit accuracy: Lower 10 bits ([9:0]) are valid
Flush-left data with 12-bit accuracy: Upper 14 bits ([15:2]) are valid
Flush-left data with 10-bit accuracy: Upper 12 bits ([15:4]) are valid
Flush-left data with 8-bit accuracy: Upper 10 bits ([15:6]) are valid.
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45.2.27
45. 12-Bit A/D Converter (ADC12)
A/D Compare Function Window A Channel Status Register 0 (ADCMPSR0)
Address(es): ADC120.ADCMPSR0 4005 C0A0h, ADC121.ADCMPSR0 4005 C2A0h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
CMPST CMPST CMPST CMPST CMPST CMPST CMPST CMPST
CHA07 CHA06 CHA05 CHA04 CHA03 CHA02 CHA01 CHA00
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CMPSTCHA07 to
CMPSTCHA00
Compare Window A Flag
When Window A operation is enabled (ADCMPCR.CMPAE = 1b),
these bits indicate the comparison result of the channels,
selected from AN000 to AN007 (unit 0) and AN100 to AN102,
AN105 to AN107 (unit 1), to which Window A comparison
conditions are applied.
0: Comparison conditions are not met
1: Comparison conditions are met.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPSTCHAn flags (n = 00 to 07) (Compare Window A Flag)
The CMPSTCHAn flags indicate the comparison results for channels, selected from AN000 to AN007 (unit 0) and
AN100 to AN102, AN105 to AN107 (unit 1), to which Window A comparison conditions are applied. When a
comparison condition set in ADCMPLR0.CMPLCHAn is met at the end of A/D conversion, the associated
CMPSTCHAn flag is set to 1. When the ADCMPCR.CMPAIE bit is 1, a compare interrupt request (ADC12i_CMPAI (i
= 0, 1)) is generated when this flag is set to 1. In unit 0, CMPSTCHA00 is associated with AN000, and CMPSTCHA07
is associated with AN007. In unit 1, CMPSTCHA00 is associated with AN100, and CMPSTCHA07 is associated with
AN107.
Writing 1 to the CMPSTCHAn flags is invalid.
[Setting condition]
The condition set in ADCMPLR0.CMPLCHAn is met when ADCMPCR.CMPAE = 1.
[Clearing condition]
Writing 0 after reading 1.
45.2.28
A/D Compare Function Window A Channel Status Register1 (ADCMPSR1)
Address(es): ADC120.ADCMPSR1 4005 C0A2h, ADC121.ADCMPSR1 4005 C2A2h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
CMPST CMPST CMPST CMPST CMPST
CHA20 CHA19 CHA18 CHA17 CHA16
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
CMPSTCHA20 to
CMPSTCHA16
Compare Window A Flag
When Window A operation is enabled (ADCMPCR.CMPAE = 1),
these bits indicate the comparison result of channels to which
Window A comparison conditions are applied, selected from
AN016 to AN020 (unit 0) and AN116 to AN118 (unit 1).
0: Comparison conditions are not met
1: Comparison conditions are met.
R/W
b15 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPSTCHAn flags (n = 16 to 20) (Compare Window A Flag)
The CMPSTCHAn flags indicate the comparison results for channels to which Window A comparison conditions are
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45. 12-Bit A/D Converter (ADC12)
applied, selected from AN016 to AN020 (unit 0) and AN116 to AN118 (unit 1). When the comparison condition set in
ADCMPLR1.CMPLCHAn is met at the end of A/D conversion, the associated CMPSTCHAn flag is set to 1. When the
ADCMPCR.CMPAIE bit is 1, a compare interrupt request (ADC12i_CMPAI (i = 0, 1)) is generated when this flag is set
to 1. In unit 0, CMPSTCHA16 is associated with AN016 and CMPSTCHA20 with AN020. In unit 1, CMPSTCHA16 is
associated with AN116 and CMPSTCHA18 with AN118.
Writing 1 to the CMPSTCHAn flags is invalid.
[Setting condition]
The condition set in ADCMPLR1.CMPLCHAn is met when ADCMPCR.CMPAE = 1.
[Clearing condition]
Writing 0 after reading 1.
45.2.29
A/D Compare Function Window A Extended Input Channel Status Register
(ADCMPSER)
Address(es): ADC120.ADCMPSER 4005 C0A4h, ADC121.ADCMPSER 4005 C2A4h
b7
Value after reset:
b6
b5
b4
b3
b2
—
—
—
—
—
—
0
0
0
0
0
0
b1
b0
CMPST CMPST
OCA
TSA
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CMPSTTSA
Compare Window A
Temperature Sensor Output
Compare Flag
When Window A operation is enabled (ADCMPCR.CMPAE =
1), this bit indicates the temperature sensor output comparison
result.
0: Comparison conditions are not met
1: Comparison conditions are met.
R/W
b1
CMPSTOCA
Compare Window A Internal
Reference Voltage Compare
Flag
When Window A operation is enabled (ADCMPCR.CMPAE =
1), this bit indicates the internal reference voltage comparison
result.
0: Comparison conditions are not met
1: Comparison conditions are met.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPSTTSA flag (Compare Window A Temperature Sensor Output Compare Flag)
The CMPSTTSA flag indicates the temperature sensor output comparison result. When the comparison condition set in
ADCMPLER.CMPLTSA is met at the end of A/D conversion, this flag is set to 1. When the ADCMPCR.CMPAIE bit is
1, a compare interrupt request (ADC12i_CMPAI (i = 0, 1)) is generated when this flag is set to 1.
Writing 1 to the CMPSTTSA flag is invalid.
[Setting condition]
The condition set in ADCMPLER.CMPLTSA is met when ADCMPCR.CMPAE = 1.
[Clearing condition]
Writing 0 after reading 1.
CMPSTOCA flag (Compare Window A Internal Reference Voltage Compare Flag)
The CMPSTOCA flag indicates the internal reference voltage comparison result. When the comparison condition set in
ADCMPLER.CMPLOCA is met at the end of A/D conversion, this flag is set to 1. When the ADCMPCR.CMPAIE bit is
1, a compare interrupt request (ADC12i_CMPAI) is generated when this flag is set to 1.
Writing 1 to the CMPSTOCA flag is invalid.
[Setting condition]
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45. 12-Bit A/D Converter (ADC12)
The condition set in ADCMPLER.CMPLOCA is met when ADCMPCR.CMPAE = 1.
[Clearing condition]
Writing 0 after reading 1.
45.2.30
A/D Compare Function Window B Channel Select Register (ADCMPBNSR)
Address(es): ADC120.ADCMPBNSR 4005 C0A6h, ADC121.ADCMPBNSR 4005 C2A6h
b7
b6
CMPLB
—
0
0
Value after reset:
b5
b4
b3
b2
b1
b0
0
0
CMPCHB[5:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
CMPCHB[5:0]
Compare Window B Channel
Select
These bits select the channels to be compared with the
compare Window B conditions. The maximum channel is
AN020 in unit 0 and AN118 in unit 1.
R/W
b5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
b0
Unit 0
Unit 1
0 0 0 0: AN000 AN100
0 0 0 1: AN001 AN101
0 0 1 0: AN002 AN102
0 0 1 1: AN003
—
0 1 0 0: AN004
—
0 1 0 1: AN005 AN105
0 1 1 0: AN006 AN106
0 1 1 1: AN007 AN107
0 0 0 0: AN016 AN116
:
:
0 1 0 0 1 0: AN018 AN118
0 1 0 0 1 1: AN019
—
0 1 0 1 0 0: AN020
—
1 0 0 0 0 0: Temperature sensor
1 0 0 0 0 1: Internal reference voltage
1 1 1 1 1 1: Do no select.
Other settings are prohibited.
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
CMPLB
Compare Window B
Comparison Condition Setting
This bit sets comparison conditions for channels for Window B.
The comparison conditions are shown in Figure 45.6.
When window function is disabled (ADCMPCR.WCMPE = 0):
0: ADWINLLB value > A/D-converted value
1: ADWINLLB value < A/D-converted value.
When window function is enabled (ADCMPCR.WCMPE = 1):
0: A/D-converted value < ADWINLLB value, or
ADWINULB value < A/D-converted value
1: ADWINLLB value < A/D-converted value < ADWINULB
value.
R/W
CMPCHB[5:0] bits (Compare Window B Channel Select)
The CMPCHB[5:0] bits specify the channels to be compared with the compare Window B conditions, from AN000 to
AN007 and AN016 to AN020 (unit 0), AN100 to AN102, AN105 to AN107, and AN116 to AN118 (unit 1), the
temperature sensor, and the internal reference voltage. The compare Window B function is enabled by specifying the
hexadecimal number of the A/D conversion channel selected in the following bits:
Unit 0:
ADANSA0.ANSA00 to ANSA07 bits
ADANSA1.ANSA16 to ANSA20 bits
ADANSB0.ANSB00 to ANSB07 bits
ADANSB1.ANSB16 to ANSB20 bits.
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45. 12-Bit A/D Converter (ADC12)
Unit 1:
ADANSA0.ANSA00 to ANSA02 bits
ADANSA0.ANSA05 to ANSA07 bits
ADANSA1.ANSA16 to ANSA18 bits
ADANSB0.ANSB00 to ANSB02 bits
ADANSB0.ANSB05 to ANSB07 bits
ADANSB1.ANSB16 to ANSB18 bits.
Set the CMPCHB[5:0] bits while the ADCSR.ADST bit is 0.
CMPLB bit (Compare Window B Comparison Condition Setting)
The CMPLB bit specifies the comparison conditions for the channels for Window B. When the comparison result of an
analog input meets the set condition, the associated ADCMPBSR.CMPSTB flag is set to 1 and a compare interrupt
request (ADC12i_CMPBI) (i = 0, 1)) is generated.
Compare conditions when the window function is disabled
CMPLB = 0
CMPLB = 1
ADWINLLB value A/D converted value
Not met
ADWINLLB value < A/D converted value
Met
ADWINLLB value > A/D converted value
Met
ADWINLLB value A/D converted value
Not met
Compare conditions when the window function is enabled
CMPLB = 0
A/D converted value > ADWINULB value
ADWINLLB value A/D converted value ADWINULB value
A/D converted value < ADWINLLB value
Met
Not met
Met
CMPLB = 1
A/D converted value ADWINULB value
ADWINLLB value
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