User’s Manual
Cover
S124 Microcontroller Group
User’s Manual
Renesas Synergy™ Platform
Synergy Microcontrollers
S1 Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.30 Feb 2018
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorporation or any
other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims
any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits,
software, or information.
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involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas
Electronics products or technical information described in this document, including but not limited to, the product data,
drawings, charts, programs, algorithms, and application examples.
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(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be
used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for
printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a
finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from
the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product
that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the
power reaches the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes
in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during
power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input
pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit
state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows
internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is
generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only
released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an
external resonator or by an external oscillator while program execution is in progress, wait until the target clock
signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take
care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition
period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating
margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number,
implement a system-evaluation test for the given product.
Preface
1.
About this document
This manual describes the functions and electrical characteristics of the Renesas Synergy™ Microcontroller.
This manual is generally organized into an overview of the product, descriptions of the CPU, system control functions,
peripheral functions, electrical characteristics, and usage notes. This manual describes the product specification of the
microcontroller (MCU) superset. Depending on your product, some pins, registers, or functions might not exist. Address
space that store unavailable registers are reserved.
2.
Audience
This manual is written for system designers who are designing and programming applications using the Renesas Synergy
Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU.
3.
Renesas Publications
Renesas provides the following documents for the Renesas Synergy Microcontroller. Before using any of these
documents, visit www.renesas.com for the most up-to-date version of the document.
Component
Microcontrollers
Software
Tools & Kits,
Solutions
Document type
Description
Datasheet
Features, overview, and electrical characteristics of the MCU
User’s Manual: Microcontrollers
MCU specifications such as pin assignments, memory maps, peripheral
functions, electrical characteristics, timing diagrams, and operation
descriptions
Application Notes
Technical notes, board design guidelines, and software migration information
Technical Update (TU)
Preliminary reports on product specifications such as restriction and errata
Datasheet
Functional descriptions and specific performance data for software modules
that are included in Renesas Synergy Software Package (SSP)
User’s Manual: Software
API reference including SSP architecture and programming information
Application Notes
Project files, guidelines for software programming, and application examples
to develop embedded software applications
User’s Manual: Development Tools
User’s manual and quick start guide for developing embedded software
applications with Development Kit (DK), Starter Kit (SK), Promotion Kit (PK),
Target Board Kit (TB), Product Examples (PE), and Application Examples (AE)
User’s Manual: Software
Quick Start Guide
Application Notes
Project files, guidelines for software programming, and application examples
to develop embedded software applications
4.
Numbering Notation
The following numbering notation is used throughout this manual:
Example
Description
011b
Binary number. For example, the binary equivalent of the number 3 is 011b.
1Fh
Hexadecimal number. For example, the hexadecimal equivalent of the number 31 is described 1Fh. In
some cases, a hexadecimal number is shown with the prefix 0x, based on C/C++ formatting.
1234
Decimal number. Decimal numbers are generally shown without a suffix.
5.
Typographic Notation
The following typographic notation is used throughout this manual:
Example
Description
ICU.NMICR.NMIMD
Periods separate a function module symbol (ICU), register symbol (NMICR), and bit field symbol
(NMIMD)
ICU.NMICR
A period separates a function module symbol (ICU) and register symbol (NMICR)
NMICR.NMIMD
A period separates a register symbol (NMICR) and bit field symbol (NMIMD)
NFCLKSEL[1:0]
In a register bit name, the bit range enclosed in square brackets indicates the number of bits in the field
at this location. In this example, NFCLKSEL[1:0] represents a 2-bit field at the specified location in the
NMI Pin Interrupt Control Register (NMICR).
6.
Unit Prefix
The following unit prefixes are sometimes misleading. Those unit prefixes are described throughout this manual with the
following meaning:
Prefix
Description
b
Bit
B
Byte. This unit prefix is generally used for memory specification of the MCU and address space.
k
1000 = 103. k is also used to denote 1024 (210) but this unit prefix is used to denote 1000 (103)
throughout this manual.
K
1024 = 210. This unit prefix is used to denote 1024 (210) not 1000 (103) throughout this manual.
7.
Special Terms
The following terms have special meanings:
Term
Description
NC
Not connected pin. NC means the pin is not connected to the MCU.
Hi-Z
High impedance
8.
Register Description
Each register description includes both a register diagram that shows the bit assignments and a register bit table that
describes the content of each bit. The example of symbols used in these tables are described in the sections that follow.
The following is an example of a register description and associated bit field definition.
X.X.X
NMI Pin Interrupt Control Register (NMICR)
Address(es):
Value after reset:
(1)
ICU.NMICR 4000 6100h
b7
b6
NFLTE
N
—
0
0
b5
b4
NFCLKSEL[1:0]
0
0
b3
b2
b1
b0
—
—
—
NMIMD
0
0
0
0
(4)
(2)
(3)
(6)
(5)
Bit
Symbol
Bit name
Description
R/W
b0
NMIMD
NMI Detection Set
0: Falling edge
1: Rising edge.
R/W
b3 to b1 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5, b4
NFCLKSEL[1:0]
NMI Digital Filter Sampling Clock
Select
b5 b4
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
NFLTEN
NMI Digital Filter Enable
0: Disable the digital filter
1: Enable the digital filter.
R/W
0
0
1
1
0: PCLKB
1: PCLKB/8
0: PCLKB/32
1: PCLKB/64.
(1) Function module symbol, register symbol, and address assignment
Function module symbol, register symbol, and address assignment of this register are generally expressed. ICU.NMICR
4000 6100h means NMI Pin Interrupt Control Register (NMICR) of Interrupt Controller Unit (ICU) is assigned to
address 4000 6100h.
(2) Bit number
This number indicates the bit number. These bits are shown in order from b31 to b0 for a 32-bit register, from b15 to b0
for a 16-bit register, and from b7 to b0 for an 8-bit register.
(3) Value after reset
This symbol or number indicates the value of each bit after a reset. The value is shown in binary unless specified
otherwise.
0: Indicates that the value is 0 after a reset.
1: Indicates that the value is 1 after a reset.
x: Indicates that the value is undefined after a reset.
(4) Bit symbol
Bit symbol indicates the short name of the bit field. Reserved bit is expressed with a —.
(5) Bit name
Bit name indicates the full name of the bit field.
(6) R/W
The R/W column indicates access type: whether the bit field is read or write.
R/W: The bit field is read and write.
R/(W): The bit field is read and write. But writing to this bit field has some limitations. For details on the limitations,
see the description or notes of respective registers.
R: The bit field is read-only. Writing to this bit field has no effect.
W: The bit field is write-only. The read value is undefined.
9.
Abbreviations
Abbreviations used in this manual are shown in the following table:
Abbreviation
AES
Description
Advanced Encryption Standard
AHB
Advanced High-Performance Bus
AHB-AP
AHB Access Port
APB
Advanced Peripheral Bus
ARC
Alleged RC
ATB
Advanced Trace Bus
BCD
Binary Coded Decimal
BSDL
Boundary Scan Description Language
DES
Data Encryption Standard
DSA
Digital Signature Algorithm
ETB
Embedded Trace Buffer
ETM
Embedded Trace Macrocell
FLL
Frequency Locked Loop
FPU
Floating-Point Unit
GSM
Global System for Mobile communications
HMI
Human Machine Interface
IrDA
Infrared Data Association
LSB
Least Significant Bit
MSB
Most Significant Bit
NVIC
Nested Vector Interrupt Controller
PC
Program Counter
PFS
Port Function Select
PLL
Phase Locked Loop
POR
Power-On Reset
PWM
Pulse Width Modulation
RSA
Rivest Shamir Adleman
SHA
Secure Hash Algorithm
S/H
Sample and Hold
SP
Stack Pointer
SWD
Serial Wire Debug
SW-DP
Serial Wire-Debug Port
TRNG
True Random Number Generator
UART
Universal Asynchronous Receiver/Transmitter
10. Proprietary Notice
All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained
in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and
trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein,
no part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded,
translated, transmitted or distributed in any other medium for publication or distribution or for any commercial
enterprise, without prior written consent from Renesas.
Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.
CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium.
Magic Packet™ is a trademark of Advanced Micro Devices, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective
holders.
11. Feedback on the product
If you have any comments or suggestions about this product, go to https://www.renesas.com/en-eu/support/contact.html.
12. Feedback on content
If you have any comments on the document such as general suggestions for improvements, go to
https://www.renesas.com/en-eu/support/contact.html, and provide:
- The title of the Renesas Synergy document
- The document number
- If applicable, the page number(s) to which your comments refer
- A detailed explanation of your comments.
Contents
Features .................................................................................................................................................... 40
1.
2.
Overview ......................................................................................................................................... 41
1.1
Function Outline.................................................................................................................... 41
1.2
Block Diagram ...................................................................................................................... 44
1.3
Part Numbering..................................................................................................................... 45
1.4
Function Comparison............................................................................................................ 47
1.5
Pin Functions ........................................................................................................................ 48
1.6
Pin Assignments ................................................................................................................... 51
1.7
Pin Lists ................................................................................................................................ 55
CPU ................................................................................................................................................ 57
2.1
Overview............................................................................................................................... 57
2.1.1
CPU .............................................................................................................................. 57
2.1.2
Debug ........................................................................................................................... 57
2.1.3
Operating Frequency.................................................................................................... 57
2.2
MCU Implementation Options............................................................................................... 58
2.3
Trace Interface...................................................................................................................... 59
2.4
SWD Interface ...................................................................................................................... 59
2.5
Debug Mode ......................................................................................................................... 59
2.5.1
Debug Mode Definition ................................................................................................. 59
2.5.2
Debug Mode Effects ..................................................................................................... 60
2.5.2.1
Low power mode .................................................................................................. 60
2.5.2.2
Reset .................................................................................................................... 60
2.6
Programmers Model ............................................................................................................. 60
2.6.1
Address Spaces ........................................................................................................... 60
2.6.2
Cortex-M0+ Peripheral Address Map ........................................................................... 61
2.6.3
External Debug Address Map....................................................................................... 61
2.6.4
CoreSight ROM Table .................................................................................................. 61
2.6.4.1
ROM entries ......................................................................................................... 61
2.6.4.2
CoreSight component registers............................................................................ 62
2.6.5
DBGREG Module ......................................................................................................... 62
2.6.5.1
Debug Status Register (DBGSTR) ....................................................................... 63
2.6.5.2
Debug Stop Control Register (DBGSTOPCR) ..................................................... 63
2.6.5.3
DBGREG CoreSight component registers ........................................................... 64
2.6.6
2.7
OCDREG Module ......................................................................................................... 64
2.6.6.1
ID Authentication Code Register (IAUTH0 to 3)................................................... 64
2.6.6.2
MCU Status Register (MCUSTAT)........................................................................ 65
2.6.6.3
MCU Control Register (MCUCTRL) ..................................................................... 66
2.6.6.4
OCDREG CoreSight component registers ........................................................... 66
SysTick System Timer .......................................................................................................... 66
2.8
OCD Emulator Connection ................................................................................................... 67
2.8.1
DBGEN......................................................................................................................... 67
2.8.2
Unlock ID Code ............................................................................................................ 67
2.8.3
Restrictions on Connecting an OCD Emulator ............................................................. 67
2.8.3.1
Starting connection while in low power mode ...................................................... 67
2.8.3.2
Changing low power mode while in OCD mode................................................... 68
2.8.3.3
Modify the unlock ID code in OSIS....................................................................... 68
2.8.3.4
Connecting sequence and SWD authentication................................................... 68
2.9
3.
References ........................................................................................................................... 69
Operating Modes ............................................................................................................................ 70
3.1
Operating Mode Types and Selection .................................................................................. 70
3.2
Details of Operating Modes .................................................................................................. 70
3.2.1
Single-Chip Mode ......................................................................................................... 70
3.2.2
SCI Boot Mode ............................................................................................................. 70
3.3
Operating Mode Transitions ................................................................................................. 70
3.3.1
4.
Address Space................................................................................................................................ 71
4.1
5.
Address Space ..................................................................................................................... 71
Resets............................................................................................................................................. 72
5.1
Overview............................................................................................................................... 72
5.2
Register Descriptions............................................................................................................ 74
5.2.1
Reset Status Register 0 (RSTSR0) .............................................................................. 74
5.2.2
Reset Status Register 1 (RSTSR1) .............................................................................. 76
5.2.3
Reset Status Register 2 (RSTSR2) .............................................................................. 77
5.3
6.
Operating Mode Transitions as Determined by the Mode-Setting Pin ......................... 70
Operation .............................................................................................................................. 77
5.3.1
RES Pin Reset.............................................................................................................. 77
5.3.2
Power-On Reset ........................................................................................................... 78
5.3.3
Voltage Monitor Reset .................................................................................................. 78
5.3.4
Independent Watchdog Timer Reset............................................................................ 80
5.3.5
Watchdog Timer Reset................................................................................................. 80
5.3.6
Software Reset ............................................................................................................. 80
5.3.7
Determination of Cold/Warm Start................................................................................ 81
5.3.8
Determination of Reset Generation Source.................................................................. 81
Option-Setting Memory ................................................................................................................... 83
6.1
Overview............................................................................................................................... 83
6.2
Register Descriptions............................................................................................................ 83
6.2.1
Option Function Select Register 0 (OFS0) ................................................................... 83
6.2.2
Option Function Select Register 1 (OFS1) ................................................................... 86
6.2.3
Access Window Setting Control Register (AWSC) ...................................................... 88
6.2.4
Access Window Setting Register (AWS) ...................................................................... 88
6.2.5
OCD/Serial Programmer ID Setting Register (OSIS) ................................................... 89
6.3
Setting Option-Setting Memory............................................................................................. 90
6.3.1
Allocation of Data in Option-Setting Memory................................................................ 90
6.3.2
Setting Data for Programming Option-Setting Memory ................................................ 90
6.4
Usage Note........................................................................................................................... 91
6.4.1
7.
Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory
...................................................................................................................................... 91
Low Voltage Detection (LVD) .......................................................................................................... 92
7.1
Overview............................................................................................................................... 92
7.2
Register Descriptions............................................................................................................ 94
7.2.1
Voltage Monitor 1 Circuit Control Register 1 (LVD1CR1) ............................................. 94
7.2.2
Voltage Monitor 1 Circuit Status Register (LVD1SR) .................................................... 95
7.2.3
Voltage Monitor 2 Circuit Control Register 1 (LVD2CR1) ............................................. 95
7.2.4
Voltage Monitor 2 Circuit Status Register (LVD2SR) .................................................... 96
7.2.5
Voltage Monitor Circuit Control Register (LVCMPCR).................................................. 96
7.2.6
Voltage Detection Level Select Register (LVDLVLR).................................................... 97
7.2.7
Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0) ............................................. 98
7.2.8
Voltage Monitor 2 Circuit Control Register 0 (LVD2CR0) ............................................. 98
7.3
VCC Input Voltage Monitor ................................................................................................... 99
7.3.1
Monitoring Vdet0 .......................................................................................................... 99
7.3.2
Monitoring Vdet1 .......................................................................................................... 99
7.3.3
Monitoring Vdet2 .......................................................................................................... 99
7.4
Reset from Voltage Monitor 0 ............................................................................................. 100
7.5
Interrupt and Reset from Voltage Monitor 1........................................................................ 101
7.6
Interrupt and Reset from Voltage Monitor 2........................................................................ 102
7.7
Event Link Output ............................................................................................................... 104
7.7.1
8.
Interrupt Handling and Event Linking ......................................................................... 104
Clock Generation Circuit ............................................................................................................... 106
8.1
Overview............................................................................................................................. 106
8.2
Register Descriptions.......................................................................................................... 109
8.2.1
System Clock Division Control Register (SCKDIVCR) ............................................... 109
8.2.2
System Clock Source Control Register (SCKSCR).................................................... 110
8.2.3
Main Clock Oscillator Control Register (MOSCCR) ................................................... 111
8.2.4
Sub-clock Oscillator Control Register (SOSCCR) ...................................................... 112
8.2.5
Low-Speed On-Chip Oscillator Control Register (LOCOCR) ..................................... 112
8.2.6
High-Speed On-Chip Oscillator Control Register (HOCOCR) .................................... 113
8.2.7
Middle-Speed On-Chip Oscillator Control Register (MOCOCR) ................................ 114
8.2.8
Oscillation Stabilization Flag Register (OSCSF)......................................................... 115
8.2.9
Oscillation Stop Detection Control Register (OSTDCR) ............................................. 116
8.2.10
Oscillation Stop Detection Status Register (OSTDSR)............................................... 117
8.2.11
Main Clock Oscillator Wait Control Register (MOSCWTCR)...................................... 118
8.2.12
High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR) ...................... 119
8.2.13
Main Clock Oscillator Mode Oscillation Control Register (MOMCR).......................... 120
8.2.14
Sub-clock Oscillator Mode Control Register (SOMCR) .............................................. 120
8.2.15
Clock Out Control Register (CKOCR) ........................................................................ 121
8.2.16
LOCO User Trimming Control Register (LOCOUTCR) .............................................. 122
8.2.17
MOCO User Trimming Control Register (MOCOUTCR) ............................................ 122
8.2.18
HOCO User Trimming Control Register (HOCOUTCR) ............................................. 123
8.3
Main Clock Oscillator .......................................................................................................... 123
8.3.1
Connecting the Crystal Resonator.............................................................................. 123
8.3.2
External Clock Input ................................................................................................... 124
8.3.3
Notes on External Clock Input .................................................................................... 124
8.4
Sub-Clock Oscillator ........................................................................................................... 124
8.4.1
8.5
Oscillation Stop Detection Function.................................................................................... 124
8.5.1
Oscillation Stop Detection and Operation after Detection .......................................... 124
8.5.2
Oscillation Stop Detection Interrupts .......................................................................... 126
8.6
Internal Clock...................................................................................................................... 127
8.6.1
System Clock (ICLK) .................................................................................................. 127
8.6.2
Peripheral Module Clock (PCLKB, PCLKD) ............................................................... 127
8.6.3
FlashIF Clock (ICLK) .................................................................................................. 127
8.6.4
USB Clock (UCLK) ..................................................................................................... 128
8.6.5
CAN Clock (CANMCLK) ............................................................................................. 128
8.6.6
CAC Clock (CACCLK) ................................................................................................ 128
8.6.7
RTC-Dedicated Clock (RTCSCLK, RTCLCLK) .......................................................... 128
8.6.8
IWDT-Dedicated Clock (IWDTCLK) ........................................................................... 128
8.6.9
AGT-Dedicated Clock (AGTSCLK, AGTLCLK) .......................................................... 128
8.6.10
SysTick Timer-Dedicated Clock (SYSTICCLK) .......................................................... 128
8.6.11
Clock/Buzzer Output Clock (CLKOUT)....................................................................... 128
8.7
9.
Connecting 32.768-kHz Crystal Resonator ................................................................ 124
Usage Notes ....................................................................................................................... 128
8.7.1
Notes on Clock Generation Circuit ............................................................................. 128
8.7.2
Notes on Resonator.................................................................................................... 129
8.7.3
Notes on Board Design .............................................................................................. 129
8.7.4
Notes on Resonator Connect Pin ............................................................................... 129
Clock Frequency Accuracy Measurement Circuit (CAC) .............................................................. 130
9.1
Overview............................................................................................................................. 130
9.2
Register Descriptions.......................................................................................................... 131
9.2.1
CAC Control Register 0 (CACR0) .............................................................................. 131
9.2.2
CAC Control Register 1 (CACR1) .............................................................................. 132
9.2.3
CAC Control Register 2 (CACR2) .............................................................................. 133
9.2.4
CAC Interrupt Control Register (CAICR) .................................................................... 134
9.2.5
CAC Status Register (CASTR) ................................................................................... 135
9.2.6
CAC Upper-Limit Value Setting Register (CAULVR) .................................................. 135
9.2.7
CAC Lower-Limit Value Setting Register (CALLVR)................................................... 136
9.2.8
9.3
CAC Counter Buffer Register (CACNTBR) ................................................................ 136
Operation ............................................................................................................................ 136
9.3.1
Measuring Clock Frequency....................................................................................... 136
9.3.2
Digital Filtering of Signals on CACREF Pin ................................................................ 137
9.4
Interrupt Requests .............................................................................................................. 138
9.5
Usage Note......................................................................................................................... 138
9.5.1
10.
Settings for the Module-Stop State............................................................................. 138
Low Power Modes ........................................................................................................................ 139
10.1
Overview............................................................................................................................. 139
10.2
Register Descriptions.......................................................................................................... 142
10.2.1
Standby Control Register (SBYCR)............................................................................ 142
10.2.2
Module Stop Control Register A (MSTPCRA) ............................................................ 143
10.2.3
Module Stop Control Register B (MSTPCRB) ............................................................ 143
10.2.4
Module Stop Control Register C (MSTPCRC)............................................................ 144
10.2.5
Module Stop Control Register D (MSTPCRD)............................................................ 145
10.2.6
Operating Power Control Register (OPCCR) ............................................................. 146
10.2.7
Sub Operating Power Control Register (SOPCCR) ................................................... 147
10.2.8
Snooze Control Register (SNZCR)............................................................................. 148
10.2.9
Snooze End Control Register (SNZEDCR) ................................................................ 148
10.2.10
Snooze Request Control Register (SNZREQCR) ...................................................... 150
10.2.11
Flash Operation Control Register (FLSTOP).............................................................. 151
10.2.12
System Control OCD Control Register (SYOCDCR).................................................. 152
10.3
Reducing Power Consumption by Switching Clock Signals ............................................... 152
10.4
Module-Stop Function......................................................................................................... 152
10.5
Function for Lower Operating Power Consumption............................................................ 152
10.5.1
Setting Operating Power Control Mode...................................................................... 152
10.5.2
Operating Range ........................................................................................................ 154
10.6
Sleep Mode......................................................................................................................... 156
10.6.1
Transition to Sleep Mode............................................................................................ 156
10.6.2
Canceling Sleep Mode ............................................................................................... 157
10.7
Software Standby Mode ..................................................................................................... 157
10.7.1
Transition to Software Standby Mode ........................................................................ 157
10.7.2
Canceling Software Standby Mode ............................................................................ 158
10.7.3
Example of Software Standby Mode Application........................................................ 158
10.8
Snooze Mode...................................................................................................................... 159
10.8.1
Transition to Snooze Mode......................................................................................... 159
10.8.2
Canceling Snooze Mode ............................................................................................ 160
10.8.3
Return to Software Standby Mode ............................................................................. 160
10.8.4
Snooze Operation Example........................................................................................ 162
10.9
Usage Note......................................................................................................................... 166
10.9.1
Register Access.......................................................................................................... 166
11.
10.9.2
I/O Port States ............................................................................................................ 167
10.9.3
Module-Stop State of DTC ......................................................................................... 167
10.9.4
Internal Interrupt Sources ........................................................................................... 167
10.9.5
Transition to Low Power Modes ................................................................................. 167
10.9.6
Timing of WFI Instruction............................................................................................ 167
10.9.7
Writing WDT/IWDT Registers by DTC in Sleep Mode or Snooze Mode .................... 167
10.9.8
Oscillators in Snooze Mode........................................................................................ 167
10.9.9
Snooze Mode Entry by RXD0 Falling Edge................................................................ 168
10.9.10
Using SCI0 in Snooze Mode ...................................................................................... 168
10.9.11
Conditions of A/D Conversion Start in Snooze Mode................................................. 168
10.9.12
Conditions of CTSU in Snooze Mode......................................................................... 168
10.9.13
ELC Event in Snooze Mode ....................................................................................... 168
10.9.14
Module-Stop Function for ADC140............................................................................. 168
10.9.15
Module-Stop Function for an Unused Circuit.............................................................. 168
Register Write Protection .............................................................................................................. 170
11.1
Overview............................................................................................................................. 170
11.2
Register Descriptions.......................................................................................................... 170
11.2.1
12.
Protect Register (PRCR) ............................................................................................ 170
Interrupt Controller Unit (ICU) ....................................................................................................... 171
12.1
Overview............................................................................................................................. 171
12.2
Register Descriptions.......................................................................................................... 172
12.2.1
IRQ Control Register i (IRQCRi) (i = 0 to 7) ............................................................... 173
12.2.2
Non-Maskable Interrupt Status Register (NMISR)...................................................... 174
12.2.3
Non-Maskable Interrupt Enable Register (NMIER) .................................................... 176
12.2.4
Non-Maskable Interrupt Status Clear Register (NMICLR).......................................... 177
12.2.5
NMI Pin Interrupt Control Register (NMICR) .............................................................. 178
12.2.6
ICU Event Link Setting Register n (IELSRn) .............................................................. 179
12.2.7
SYS Event Link Setting Register (SELSR0)............................................................... 180
12.2.8
Wake Up Interrupt Enable Register (WUPEN) ........................................................... 180
12.3
Vector Table ....................................................................................................................... 182
12.3.1
Interrupt Vector Table................................................................................................. 182
12.3.2
Event Number............................................................................................................. 184
12.4
Interrupt Operation.............................................................................................................. 187
12.4.1
Detecting Interrupts .................................................................................................... 187
12.4.2
Selecting Interrupt Request Destinations ................................................................... 188
12.4.2.1
CPU interrupt request......................................................................................... 189
12.4.2.2
DTC activation.................................................................................................... 189
12.4.3
Digital Filter................................................................................................................. 189
12.4.4
External Pin Interrupts ................................................................................................ 190
12.5
Non-Maskable Interrupt Operation ..................................................................................... 190
12.6
Return from Low Power Modes .......................................................................................... 191
13.
12.6.1
Return from Sleep Mode ............................................................................................ 191
12.6.2
Return from Software Standby Mode ......................................................................... 191
12.6.3
Return from Snooze Mode ......................................................................................... 191
12.7
Using the WFI Instruction with Non-maskable Interrupt ..................................................... 192
12.8
Reference ........................................................................................................................... 192
Buses ............................................................................................................................................ 193
13.1
Overview............................................................................................................................. 193
13.2
Description of Buses........................................................................................................... 194
13.2.1
Main Buses................................................................................................................. 194
13.2.2
Slave Interface............................................................................................................ 194
13.2.3
Parallel Operation....................................................................................................... 194
13.2.4
Constraints ................................................................................................................. 194
13.3
13.3.1
Master Bus Control Register (BUSMCNT) .................................................. 195
13.3.2
Slave Bus Control Register (BUSSCNT) ....................................................... 195
13.4
Bus Error Monitoring Section.............................................................................................. 196
13.4.1
Error Type that Occurs by Bus ................................................................................... 196
13.4.2
Operation when a Bus Error Occurs........................................................................... 196
13.4.3
Conditions Leading to Illegal Address Access Errors................................................. 196
13.4.4
Timeout....................................................................................................................... 197
13.5
14.
Register Descriptions.......................................................................................................... 195
References ......................................................................................................................... 197
Data Transfer Controller (DTC)..................................................................................................... 198
14.1
Overview............................................................................................................................. 198
14.2
Register Descriptions.......................................................................................................... 199
14.2.1
DTC Mode Register A (MRA) ..................................................................................... 200
14.2.2
DTC Mode Register B (MRB) ..................................................................................... 200
14.2.3
DTC Transfer Source Register (SAR) ........................................................................ 201
14.2.4
DTC Transfer Destination Register (DAR) ................................................................. 202
14.2.5
DTC Transfer Count Register A (CRA) ...................................................................... 202
14.2.6
DTC Transfer Count Register B (CRB) ..................................................................... 203
14.2.7
DTC Control Register (DTCCR) ................................................................................. 203
14.2.8
DTC Vector Base Register (DTCVBR) ....................................................................... 204
14.2.9
DTC Module Start Register (DTCST) ......................................................................... 204
14.2.10
DTC Status Register (DTCSTS) ................................................................................. 205
14.3
Activation Sources .............................................................................................................. 205
14.3.1
14.4
Allocating Transfer Information and DTC Vector Table.............................................. 206
Operation ............................................................................................................................ 207
14.4.1
Transfer Information Read Skip Function................................................................... 210
14.4.2
Transfer Information Write-Back Skip Function.......................................................... 210
14.4.3
Normal Transfer Mode................................................................................................ 211
14.4.4
Repeat Transfer Mode................................................................................................ 212
14.4.5
Block Transfer Mode ................................................................................................. 213
14.4.6
Chain Transfer............................................................................................................ 214
14.4.7
Operation Timing ........................................................................................................ 215
14.4.8
Execution Cycles of DTC............................................................................................ 217
14.4.9
DTC Bus Mastership Release Timing ........................................................................ 217
14.5
DTC Setting Procedure....................................................................................................... 218
14.6
Examples of DTC Usage .................................................................................................... 218
14.6.1
Normal Transfer.......................................................................................................... 218
14.6.2
Chain Transfer............................................................................................................ 219
14.6.3
Chain Transfer when Counter = 0 .............................................................................. 221
14.7
Interrupt Source .................................................................................................................. 222
14.8
Event Link ........................................................................................................................... 222
14.9
Snooze Control Interface .................................................................................................... 222
14.10
Module-Stop Function......................................................................................................... 222
14.11
Usage Notes ....................................................................................................................... 223
14.11.1
15.
Event Link Controller (ELC) ......................................................................................................... 224
15.1
Overview............................................................................................................................. 224
15.2
Register Descriptions.......................................................................................................... 225
15.2.1
Event Link Controller Register (ELCR)....................................................................... 225
15.2.2
Event Link Software Event Generation Register n (ELSEGRn) (n = 0, 1).................. 225
15.2.3
Event Link Setting Register n (ELSRn) ...................................................................... 226
15.3
Operation ............................................................................................................................ 229
15.3.1
Relation between Interrupt Handling and Event Linking............................................. 229
15.3.2
Linking Events ............................................................................................................ 229
15.3.3
Example Procedure for Linking Events ...................................................................... 230
15.4
16.
Transfer Information Start Address ............................................................................ 223
Usage Notes ....................................................................................................................... 230
15.4.1
Linking DTC Transfer End Signals as Events ............................................................ 230
15.4.2
Setting the Clocks....................................................................................................... 230
15.4.3
Module Stop Function Setting .................................................................................... 230
15.4.4
ELC Delay Time ......................................................................................................... 230
I/O Ports........................................................................................................................................ 232
16.1
Overview............................................................................................................................. 232
16.2
Register Descriptions.......................................................................................................... 234
16.2.1
Port Control Register 1 (PCNTR1/PODR/PDR) ........................................................ 234
16.2.2
Port Control Register 2 (PCNTR2/EIDR/PIDR) .......................................................... 235
16.2.3
Port Control Register 3 (PCNTR3/PORR/POSR)....................................................... 236
16.2.4
Port Control Register 4 (PCNTR4/EORR/EOSR)....................................................... 237
16.2.5
Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY)
(m = 0 to 5; n = 00 to 15) ............................................................................................ 238
16.2.6
Write-Protect Register (PWPR) .................................................................................. 240
16.3
Operation ............................................................................................................................ 240
16.3.1
General I/O Ports........................................................................................................ 240
16.3.2
Port Function Select ................................................................................................... 240
16.3.3
Port Group Function for ELC ...................................................................................... 241
16.3.3.2
Behavior when event pulse is output to ELC...................................................... 242
Handling of Unused Pins .................................................................................................... 242
16.5
Usage Notes ....................................................................................................................... 243
16.5.1
Procedure for Specifying Pin Function ....................................................................... 243
16.5.2
Procedure to Use Port Group Input ............................................................................ 243
16.5.3
Port Output Data Register (PODR) Summary ............................................................ 243
16.5.4
Notes on Use of Analog Functions ............................................................................. 244
Peripheral Select Settings for each product ....................................................................... 244
Key Interrupt Function (KINT) ....................................................................................................... 249
17.1
Overview............................................................................................................................. 249
17.2
Register Descriptions.......................................................................................................... 251
17.2.1
Key Return Control Register (KRCTL) ....................................................................... 251
17.2.2
Key Return Flag Register (KRF)................................................................................. 251
17.2.3
Key Return Mode Register (KRM).............................................................................. 251
17.3
Operation ............................................................................................................................ 252
17.3.1
When Not Using Key Interrupt Flag (KRMD = 0)........................................................ 252
17.3.2
When Using Key Interrupt Flag (KRMD = 1) .............................................................. 252
17.4
18.
Behavior when ELC_PORT1 or 2 is input from ELC.......................................... 241
16.4
16.6
17.
16.3.3.1
Usage Note......................................................................................................................... 254
Port Output Enable for GPT (POEG) ............................................................................................ 255
18.1
Overview............................................................................................................................. 255
18.2
Register Descriptions.......................................................................................................... 256
18.2.1
18.3
POEG Group n Setting Register (POEGGn) (n = A, B).............................................. 256
Output-Disable Control Operation ...................................................................................... 257
18.3.1
Pin Input Level Detection Operation........................................................................... 258
18.3.1.1
19.
Digital filter.......................................................................................................... 258
18.3.2
Output-Disable Request from GPT............................................................................. 258
18.3.3
Output Disable Control on Detection of Stopped Oscillation ...................................... 258
18.3.4
Output Disable Control Using Registers..................................................................... 258
18.3.5
Release from Output Disable ..................................................................................... 258
18.4
Interrupt Source .................................................................................................................. 259
18.5
External Trigger Output to GPT .......................................................................................... 259
18.6
Usage Notes ....................................................................................................................... 260
18.6.1
Transition to Software Standby mode ........................................................................ 260
18.6.2
Specifying Pins Corresponding to GPT ...................................................................... 260
General PWM Timer (GPT) .......................................................................................................... 261
19.1
Overview............................................................................................................................. 261
19.2
Register Descriptions.......................................................................................................... 264
19.2.1
General PWM Timer Write-Protection Register (GTWP) ........................................... 266
19.2.2
General PWM Timer Software Start Register (GTSTR) ............................................. 266
19.2.3
General PWM Timer Software Stop Register (GTSTP) ............................................. 267
19.2.4
General PWM Timer Software Clear Register (GTCLR) ............................................ 267
19.2.5
General PWM Timer Start Source Select Register (GTSSR)..................................... 268
19.2.6
General PWM Timer Stop Source Select Register (GTPSR)..................................... 270
19.2.7
General PWM Timer Clear Source Select Register (GTCSR) ................................... 272
19.2.8
General PWM Timer Up Count Source Select Register (GTUPSR) .......................... 275
19.2.9
General PWM Timer Down Count Source Select Register (GTDNSR)...................... 277
19.2.10
General PWM Timer Input Capture Source Select Register A(GTICASR) ................ 280
19.2.11
General PWM Timer Input Capture Source Select Register B(GTICBSR) ................ 282
19.2.12
General PWM Timer Control Register (GTCR) .......................................................... 285
19.2.13
General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC) ....... 286
19.2.14
General PWM Timer I/O Control Register (GTIOR) ................................................... 288
19.2.15
General PWM Timer Interrupt Output Setting Register (GTINTAD)........................... 292
19.2.16
General PWM Timer Status Register (GTST) ............................................................ 293
19.2.17
General PWM Timer Buffer Enable Register (GTBER).............................................. 296
19.2.18
General PWM Timer Counter (GTCNT) ..................................................................... 298
19.2.19
General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F)............... 298
19.2.20
General PWM Timer Cycle Setting Register (GTPR)................................................. 299
19.2.21
General PWM Timer Cycle Setting Buffer Register (GTPBR).................................... 299
19.2.22
General PWM Timer Dead Time Control Register (GTDTCR)................................... 300
19.2.23
General PWM Timer Dead Time Value Register U (GTDVU) .................................... 300
19.2.24
Output Phase Switching Control Register (OPSCR) ................................................. 301
19.3
Operation ............................................................................................................................ 303
19.3.1
Basic Operation .......................................................................................................... 303
19.3.1.1
Counter operation............................................................................................... 303
19.3.1.2
Waveform output by compare match ................................................................. 308
19.3.1.3
Input capture function......................................................................................... 311
19.3.2
Buffer Operation ......................................................................................................... 313
19.3.2.1
GTPR register buffer operation .......................................................................... 313
19.3.2.2
Buffer operation for GTCCRA and GTCCRB ..................................................... 316
19.3.3
PWM Output Operating Mode .................................................................................... 321
19.3.3.1
Saw-wave PWM mode ....................................................................................... 321
19.3.3.2
Saw-wave one-shot pulse mode ........................................................................ 323
19.3.3.3
Triangle-wave PWM mode 1 (32-bit transfer at trough) ..................................... 326
19.3.3.4
Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) ..................... 329
19.3.3.5
Triangle-wave PWM mode 3 (64-bit transfer at trough) ..................................... 331
19.3.4
Automatic Dead Time Setting Function ...................................................................... 333
19.3.5
Count Direction Changing Function............................................................................ 337
19.3.6
Function of Output Duty 0% and 100% ...................................................................... 338
19.3.7
19.3.7.1
Hardware start operation.................................................................................... 340
19.3.7.2
Hardware stop operation .................................................................................... 341
19.3.7.3
Hardware clear operation ................................................................................... 344
19.3.8
Synchronized Operation ............................................................................................. 347
19.3.8.1
Synchronized operation by software .................................................................. 347
19.3.8.2
Synchronized operation by hardware................................................................. 349
19.3.9
PWM Output Operation Examples ............................................................................. 351
19.3.10
Phase Counting Function ........................................................................................... 357
19.3.11
Output Phase Switching (GPT_OPS)......................................................................... 364
19.4
19.3.11.1
Input selection and synchronization of external input signal .............................. 367
19.3.11.2
Input sampling .................................................................................................... 368
19.3.11.3
Input phase decode............................................................................................ 368
19.3.11.4
Output selection control...................................................................................... 368
19.3.11.5
Output selection control (group output disable function) .................................... 369
19.3.11.6
ELC output ......................................................................................................... 370
19.3.11.7
GPT_OPS start operation setting flow ............................................................... 371
Interrupt Sources ................................................................................................................ 371
19.4.1
Interrupt Sources ........................................................................................................ 371
19.4.2
DTC Activation............................................................................................................ 374
19.5
Operations Linked by ELC.................................................................................................. 374
19.5.1
Event Signal Output to ELC........................................................................................ 374
19.5.2
Event Signal Inputs from ELC .................................................................................... 374
19.6
Noise Filter Function........................................................................................................... 374
19.7
Protection Function............................................................................................................. 375
19.7.1
Write-Protection for Registers .................................................................................... 375
19.7.2
Disabling of Buffer Operation ..................................................................................... 375
19.7.3
GTIOC Pin Output Negate Control ............................................................................. 376
19.8
Initialization Method of Output Pins .................................................................................... 377
19.8.1
Pin Settings after Reset.............................................................................................. 377
19.8.2
Pin Initialization Due to Error during Operation .......................................................... 378
19.9
20.
Hardware Count Start/Count Stop and Clear Operation ............................................ 340
Usage Notes ....................................................................................................................... 378
19.9.1
Settings for the Module-Stop State............................................................................. 378
19.9.2
Settings of GTCCRn during Compare Match Operation (n = A to F) ......................... 378
19.9.3
Setting the Range for GTCNT Counter ...................................................................... 379
19.9.4
GTCNT Counter Start/Stop ........................................................................................ 379
19.9.5
Priority Order of Each Event....................................................................................... 379
Asynchronous General Purpose Timer (AGT) .............................................................................. 381
20.1
Overview............................................................................................................................. 381
20.2
Register Descriptions.......................................................................................................... 383
20.2.1
AGT Counter Register (AGT) ..................................................................................... 383
20.2.2
AGT Compare Match A Register (AGTCMA) ............................................................. 383
20.2.3
AGT Compare Match B Register (AGTCMB) ............................................................. 384
20.2.4
AGT Control Register (AGTCR) ................................................................................. 384
20.2.5
AGT Mode Register 1 (AGTMR1) .............................................................................. 386
20.2.6
AGT Mode Register 2 (AGTMR2) .............................................................................. 387
20.2.7
AGT I/O Control Register (AGTIOC) .......................................................................... 388
20.2.8
AGT Event Pin Select Register (AGTISR).................................................................. 389
20.2.9
AGT Compare Match Function Select Register (AGTCMSR) ................................... 389
20.2.10
AGT Pin Select Register (AGTIOSEL) ....................................................................... 390
20.3
20.3.1
Reload Register and Counter Rewrite Operation ....................................................... 390
20.3.2
Reload Register and Compare Register A/B Rewrite Operation................................ 392
20.3.3
Timer Mode ................................................................................................................ 393
20.3.4
Pulse Output Mode..................................................................................................... 394
20.3.5
Event Counter Mode................................................................................................... 395
20.3.6
Pulse Width Measurement Mode ............................................................................... 396
20.3.7
Pulse Period Measurement Mode .............................................................................. 397
20.3.8
Compare Match function ............................................................................................ 398
20.3.9
Output Settings for Each Mode .................................................................................. 399
20.3.10
Standby Mode ............................................................................................................ 401
20.3.11
Interrupt Sources ........................................................................................................ 401
20.3.12
Event Signal Output to ELC........................................................................................ 402
20.4
21.
Operation ............................................................................................................................ 390
Usage Notes ....................................................................................................................... 402
20.4.1
Count Operation Start and Stop Control..................................................................... 402
20.4.2
Access to Counter Register........................................................................................ 402
20.4.3
When Changing Mode................................................................................................ 403
20.4.4
Digital Filter................................................................................................................. 403
20.4.5
How to Calculate Event Number, Pulse Width, and Pulse Period.............................. 403
20.4.6
When Count is Forcibly Stopped by TSTOP Bit ......................................................... 403
20.4.7
When Selecting AGT0 Underflow as Count Source ................................................... 403
20.4.8
Reset of I/O Register .................................................................................................. 404
20.4.9
When Selecting PCLKB, PCLKB/8, or PCLKB/2 as Count Source ............................ 404
20.4.10
When Selecting AGTLCLK or AGTSCLK as Count Source ....................................... 404
Realtime Clock (RTC) ................................................................................................................... 405
21.1
Overview............................................................................................................................. 405
21.2
Register Descriptions.......................................................................................................... 406
21.2.1
64-Hz Counter (R64CNT)........................................................................................... 407
21.2.2
Second Counter (RSECCNT)/Binary Counter 0 (BCNT0).......................................... 407
21.2.3
Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1)............................................ 408
21.2.4
Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2) ................................................ 409
21.2.5
Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3)................................... 410
21.2.6
Day Counter (RDAYCNT) ........................................................................................... 410
21.2.7
Month Counter (RMONCNT) ...................................................................................... 411
21.2.8
Year Counter (RYRCNT) ............................................................................................ 411
21.2.9
Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register (BCNT0AR) ... 412
21.2.10
Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR) ..... 413
21.2.11
Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register (BCNT2AR).......... 414
21.2.12
Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register
(BCNT3AR) ................................................................................................................ 415
21.2.13
Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register
(BCNT0AER) .............................................................................................................. 416
21.2.14
Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register
(BCNT1AER) .............................................................................................................. 417
21.2.15
Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register
(BCNT2AER) .............................................................................................................. 418
21.2.16
Year Alarm Enable Register (RYRAREN)/
Binary Counter 3 Alarm Enable Register (BCNT3AER) ............................................. 418
21.2.17
RTC Control Register 1 (RCR1) ................................................................................. 419
21.2.18
RTC Control Register 2 (RCR2) ................................................................................. 420
21.2.19
RTC Control Register 4 (RCR4) ................................................................................. 424
21.2.20
Frequency Register (RFRH/RFRL) ............................................................................ 424
21.2.21
Time Error Adjustment Register (RADJ)..................................................................... 425
21.3
Operation ............................................................................................................................ 425
21.3.1
Outline of Initial Settings of Registers after Power On ............................................... 425
21.3.2
Clock and Count Mode Setting Procedure ................................................................. 426
21.3.3
Setting the Time ......................................................................................................... 426
21.3.4
30-Second Adjustment ............................................................................................... 427
21.3.5
Reading 64-Hz Counter and Time.............................................................................. 428
21.3.6
Alarm Function ........................................................................................................... 429
21.3.7
Procedure for Disabling Alarm Interrupt ..................................................................... 429
21.3.8
Time Error Adjustment Function................................................................................. 430
21.3.8.1
Automatic adjustment......................................................................................... 430
21.3.8.2
Adjustment by software ...................................................................................... 431
21.3.8.3
Procedure to change the mode of adjustment ................................................... 431
21.3.8.4
Procedure to stop adjustment ............................................................................ 432
21.4
Interrupt Sources ................................................................................................................ 432
21.5
Event Link Output ............................................................................................................... 433
21.5.1
21.6
Interrupt Handling and Event Linking ......................................................................... 433
Usage Notes ....................................................................................................................... 433
21.6.1
Register Writing during Counting................................................................................ 433
21.6.2
Use of Periodic Interrupts ........................................................................................... 434
21.6.3
RTCOUT (1-Hz/64-Hz) Clock Output ......................................................................... 434
21.6.4
Transitions to Low Power Modes after Setting Registers........................................... 434
21.6.5
Notes when Writing to and Reading from Registers................................................... 435
22.
21.6.6
Changing the Count Mode.......................................................................................... 435
21.6.7
Initialization Procedure when the Realtime Clock is not used .................................... 435
Watchdog Timer (WDT) ................................................................................................................ 437
22.1
Overview............................................................................................................................. 437
22.2
Register Descriptions.......................................................................................................... 438
22.2.1
WDT Refresh Register (WDTRR)............................................................................... 438
22.2.2
WDT Control Register (WDTCR)................................................................................ 439
22.2.3
WDT Status Register (WDTSR) ................................................................................. 441
22.2.4
WDT Reset Control Register (WDTRCR)................................................................... 442
22.2.5
WDT Count Stop Control Register (WDTCSTPR)...................................................... 443
22.2.6
Option Function Select Register 0 (OFS0) ................................................................. 443
22.3
Operation ............................................................................................................................ 443
22.3.1
22.3.1.1
Register start mode ............................................................................................ 443
22.3.1.2
Auto start mode .................................................................................................. 445
22.3.2
Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers ............... 446
22.3.3
Refresh Operation ...................................................................................................... 447
22.3.4
Reset Output .............................................................................................................. 448
22.3.5
Interrupt Sources ........................................................................................................ 448
22.3.6
Reading the Down-Counter Value.............................................................................. 448
22.3.7
Association between Option Function Select Register 0 (OFS0) and
WDT Registers ........................................................................................................... 449
22.4
Link Operation by ELC........................................................................................................ 449
22.5
Usage Notes ....................................................................................................................... 449
22.5.1
23.
Count Operation in each Start Mode .......................................................................... 443
ICU Event Link Setting Register n (IELSRn) Setting .................................................. 449
Independent Watchdog Timer (IWDT) .......................................................................................... 450
23.1
Overview............................................................................................................................. 450
23.2
Register Descriptions.......................................................................................................... 451
23.2.1
IWDT Refresh Register (IWDTRR)............................................................................. 451
23.2.2
IWDT Status Register (IWDTSR) ............................................................................... 452
23.2.3
Option Function Select Register 0 (OFS0) ................................................................. 453
23.3
Operation ............................................................................................................................ 455
23.3.1
Auto Start Mode.......................................................................................................... 455
23.3.2
Refresh Operation ...................................................................................................... 456
23.3.3
Status Flags................................................................................................................ 457
23.3.4
Reset Output .............................................................................................................. 458
23.3.5
Interrupt Sources ........................................................................................................ 458
23.3.6
Reading the Down-counter Value............................................................................... 458
23.4
Link Operation by ELC........................................................................................................ 458
23.5
Usage Notes ....................................................................................................................... 459
23.5.1
Refresh Operations .................................................................................................... 459
23.5.2
24.
Clock Division Ratio Setting ....................................................................................... 459
USB 2.0 Full-Speed Module (USBFS) .......................................................................................... 460
24.1
Overview............................................................................................................................. 460
24.2
Register Descriptions.......................................................................................................... 462
24.2.1
System Configuration Control Register (SYSCFG) .................................................... 462
24.2.2
System Configuration Status Register 0 (SYSSTS0) ................................................. 463
24.2.3
Device State Control Register 0 (DVSTCTR0) ........................................................... 464
24.2.4
CFIFO Port Register (CFIFO/CFIFOL)....................................................................... 464
24.2.5
CFIFO Port Select Register (CFIFOSEL)................................................................... 466
24.2.6
CFIFO Port Control Register (CFIFOCTR)................................................................. 467
24.2.7
Interrupt Enable Register 0 (INTENB0) ...................................................................... 468
24.2.8
BRDY Interrupt Enable Register (BRDYENB)............................................................ 469
24.2.9
NRDY Interrupt Enable Register (NRDYENB) ........................................................... 470
24.2.10
BEMP Interrupt Enable Register (BEMPENB) ........................................................... 470
24.2.11
SOF Output Configuration Register (SOFCFG) ......................................................... 471
24.2.12
Interrupt Status Register 0 (INTSTS0)........................................................................ 471
24.2.13
BRDY Interrupt Status Register (BRDYSTS) ............................................................. 473
24.2.14
NRDY Interrupt Status Register (NRDYSTS) ............................................................. 474
24.2.15
BEMP Interrupt Status Register (BEMPSTS) ............................................................. 474
24.2.16
Frame Number Register (FRMNUM).......................................................................... 475
24.2.17
USB Request Type Register (USBREQ) .................................................................... 475
24.2.18
USB Request Value Register (USBVAL) .................................................................... 476
24.2.19
USB Request Index Register (USBINDX) .................................................................. 476
24.2.20
USB Request Length Register (USBLENG)............................................................... 477
24.2.21
DCP Configuration Register (DCPCFG)..................................................................... 477
24.2.22
DCP Maximum Packet Size Register (DCPMAXP).................................................... 478
24.2.23
DCP Control Register (DCPCTR)............................................................................... 479
24.2.24
Pipe Window Select Register (PIPESEL)................................................................... 481
24.2.25
Pipe Configuration Register (PIPECFG) .................................................................... 481
24.2.26
Pipe Maximum Packet Size Register (PIPEMAXP).................................................... 483
24.2.27
PIPEn Control Registers (PIPEnCTR) (n = 4 to 7) ..................................................... 484
24.2.28
PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 4 and 5) ................... 489
24.2.29
PIPEn Transaction Counter Register (PIPEnTRN) (n = 4 and 5) ............................... 490
24.2.30
USB Module Control Register (USBMC) .................................................................... 491
24.2.31
BC Control Register 0 (USBBCCTRL0) ..................................................................... 491
24.2.32
USB Clock Selection Register (UCKSEL) .................................................................. 492
24.3
Operation ............................................................................................................................ 493
24.3.1
System Control ........................................................................................................... 493
24.3.1.1
Setting data to USBFS related registers ............................................................ 493
24.3.1.2
Controlling USBFS data bus registers................................................................ 493
24.3.1.3
Example of USBFS power supply connection.................................................... 493
24.3.1.4
24.3.2
Interrupt Sources ........................................................................................................ 500
24.3.3
Interrupt Descriptions ................................................................................................. 503
24.3.3.1
BRDY interrupt ................................................................................................... 503
24.3.3.2
NRDY interrupt ................................................................................................... 505
24.3.3.3
BEMP interrupt ................................................................................................... 506
24.3.3.4
Device state transition interrupt.......................................................................... 507
24.3.3.5
Control transfer stage transition interrupt ........................................................... 508
24.3.3.6
Frame update interrupt....................................................................................... 509
24.3.3.7
VBUS interrupt ................................................................................................... 509
24.3.3.8
Resumed interrupt.............................................................................................. 510
24.3.4
Pipe Control................................................................................................................ 510
24.3.4.1
Pipe control register switching procedures......................................................... 510
24.3.4.2
Transfer types .................................................................................................... 511
24.3.4.3
Endpoint number ................................................................................................ 511
24.3.4.4
Maximum packet size setting ............................................................................. 511
24.3.4.5
Transaction counter for PIPE4 and PIPE5 in the receiving direction ................. 511
24.3.4.6
Response PID .................................................................................................... 512
24.3.4.7
Data PID sequence bit ....................................................................................... 512
24.3.4.8
Response PID = NAK function ........................................................................... 512
24.3.4.9
Auto response mode .......................................................................................... 512
24.3.4.10
OUT-NAK mode ................................................................................................. 513
24.3.4.11
Null auto response mode ................................................................................... 513
24.3.5
FIFO Buffer Memory................................................................................................... 513
24.3.6
FIFO Buffer Clearing .................................................................................................. 514
24.3.7
FIFO Port Functions ................................................................................................... 514
24.3.8
Control Transfers Using DCP ..................................................................................... 515
24.3.8.1
Control transfers................................................................................................. 515
24.3.9
Bulk Transfers (PIPE4 and PIPE5)............................................................................. 516
24.3.10
Interrupt Transfers (PIPE6 and PIPE7) ...................................................................... 516
24.3.11
Pipe Schedule ............................................................................................................ 516
24.3.11.1
24.3.12
24.4
Transfer schedule............................................................................................... 516
Battery Charging Detection Processing...................................................................... 517
24.3.12.1
25.
Example of USB External Connection Circuit .................................................... 496
Processing.......................................................................................................... 517
Usage Note......................................................................................................................... 519
24.4.1
Settings for the Module-Stop State............................................................................. 519
24.4.2
Clear of Interrupt Status Register after Software Standby mode ............................... 519
24.4.3
Clear of Interrupt Status Register after Setting the Port Function .............................. 519
Serial Communications Interface (SCI)......................................................................................... 520
25.1
Overview............................................................................................................................. 520
25.2
Register Descriptions.......................................................................................................... 523
25.2.1
Receive Shift Register (RSR) ..................................................................................... 523
25.2.2
Receive Data Register (RDR) .................................................................................... 523
25.2.3
Receive 9-bit Data Register (RDRHL)........................................................................ 523
25.2.4
Receive FIFO Data Register H, L, HL (FRDRH, FRDRL, FRDRHL).......................... 524
25.2.5
Transmit Data Register (TDR) .................................................................................... 525
25.2.6
Transmit 9-Bit Data Register (TDRHL) ....................................................................... 525
25.2.7
Transmit FIFO Data Register H, L, HL (FTDRH, FTDRL, FTDRHL).......................... 526
25.2.8
Transmit Shift Register (TSR) .................................................................................... 527
25.2.9
Serial Mode Register (SMR) for Non-Smart Card Interface mode
(SCMR.SMIF = 0) ...................................................................................................... 527
25.2.10
Serial Mode Register for Smart Card Interface Mode (SMR_SMCI)
(SCMR.SMIF = 1) ...................................................................................................... 528
25.2.11
Serial Control Register (SCR) for Non-Smart Card Interface Mode
(SCMR.SMIF = 0) ...................................................................................................... 530
25.2.12
Serial Control Register for Smart Card Interface Mode (SCR_SMCI)
(SCMR.SMIF = 1) ...................................................................................................... 532
25.2.13
Serial Status Register (SSR) for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) ................................................................................. 533
25.2.14
Serial Status Register for Non-Smart Card Interface and FIFO Mode
(SSR_FIFO) (SCMR.SMIF = 0 and FCR.FM = 1) ..................................................... 536
25.2.15
Serial Status Register for Smart Card Interface Mode (SSR_SMCI)
(SCMR.SMIF = 1) ...................................................................................................... 539
25.2.16
Smart Card Mode Register (SCMR)........................................................................... 541
25.2.17
Bit Rate Register (BRR) ............................................................................................. 542
25.2.18
Modulation Duty Register (MDDR) ............................................................................. 550
25.2.19
Serial Extended Mode Register (SEMR) .................................................................... 553
25.2.20
Noise Filter Setting Register (SNFR).......................................................................... 554
25.2.21
I2C Mode Register 1 (SIMR1)..................................................................................... 555
25.2.22
I2C Mode Register 2 (SIMR2)..................................................................................... 555
25.2.23
I2C Mode Register 3 (SIMR3)..................................................................................... 556
25.2.24
I2C Status Register (SISR) ......................................................................................... 558
25.2.25
SPI Mode Register (SPMR)........................................................................................ 558
25.2.26
FIFO Control Register (FCR)...................................................................................... 560
25.2.27
FIFO Data Count Register (FDR) ............................................................................... 561
25.2.28
Line Status Register (LSR) ......................................................................................... 562
25.2.29
Compare Match Data Register (CDR) ........................................................................ 562
25.2.30
Data Compare Match Control Register (DCCR)......................................................... 563
25.2.31
Serial Port Register (SPTR) ....................................................................................... 564
25.3
Operation in Asynchronous Mode ...................................................................................... 565
25.3.1
Serial Data Transfer Format ....................................................................................... 565
25.3.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ....... 567
25.3.3
Clock.......................................................................................................................... 568
25.3.4
Double-Speed Operation and Frequency of 6 Times the Bit Rate ............................. 569
25.3.5
CTS and RTS Functions............................................................................................. 569
25.3.6
Address Match (receive data match detection) Function ........................................... 569
25.3.7
SCI Initialization in Asynchronous Mode .................................................................... 572
25.3.8
Serial Data Transmission in Asynchronous mode...................................................... 574
25.3.9
Serial Data Reception in Asynchronous Mode ........................................................... 579
25.4
Multi-Processor Communication Function .......................................................................... 586
25.4.1
Multi-Processor Serial Data Transmission ................................................................. 588
25.4.2
Multi-Processor Serial Data Reception....................................................................... 591
25.5
Operation in Clock Synchronous Mode .............................................................................. 596
25.5.1
Clock........................................................................................................................... 597
25.5.2
CTS and RTS Functions............................................................................................. 597
25.5.3
SCI Initialization in Clock Synchronous Mode ........................................................... 598
25.5.4
Serial Data Transmission in Clock Synchronous Mode.............................................. 600
25.5.5
Serial Data Reception in Clock Synchronous Mode................................................... 604
25.5.6
Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode
.................................................................................................................................... 610
25.6
Operation in Smart Card Interface mode............................................................................ 612
25.6.1
Example Connection .................................................................................................. 612
25.6.2
Data Format (Except in Block Transfer Mode) ........................................................... 613
25.6.3
Block Transfer Mode .................................................................................................. 615
25.6.4
Receive Data Sampling Timing and Reception Margin .............................................. 615
25.6.5
Initialization of the SCI................................................................................................ 616
25.6.6
Serial Data Transmission (Except in Block Transfer mode) ....................................... 618
25.6.7
Serial Data Reception (Except in Block Transfer Mode) ............................................ 620
25.6.8
Clock Output Control .................................................................................................. 622
25.7
Operation in Simple IIC mode............................................................................................. 623
25.7.1
Generation of Start, Restart, and Stop Conditions ..................................................... 624
25.7.2
Clock Synchronization ................................................................................................ 625
25.7.3
SDA Output Delay ..................................................................................................... 626
25.7.4
SCI Initialization in Simple IIC Mode .......................................................................... 627
25.7.5
Operation in Master Transmission in Simple IIC mode ............................................. 627
25.7.6
Master Reception in Simple IIC Mode ....................................................................... 630
25.8
Operation in Simple SPI mode .......................................................................................... 632
25.8.1
States of Pins in Master and Slave Modes................................................................. 632
25.8.2
SS Function in Master mode ...................................................................................... 633
25.8.3
SS Function in Slave mode ........................................................................................ 633
25.8.4
Relationship between Clock and Transmit/Receive Data........................................... 633
25.8.5
SCI Initialization in Simple SPI Mode ......................................................................... 634
25.8.6
Transmission and Reception of Serial Data in Simple SPI Mode............................... 634
25.9
Bit Rate Modulation Function.............................................................................................. 634
25.10
Interrupt Sources ................................................................................................................ 635
25.10.1
Buffer Operations for SCIn_TXI and SCIn_RXI Interrupts (non-FIFO selected) ........ 635
25.10.2
Buffer Operations for SCIn_TXI and SCIn_RXI Interrupts (FIFO selected) ............... 635
25.10.3
Interrupts in Asynchronous, Clock Synchronous, and Simple SPI Modes ................. 635
25.10.4
Interrupts in Smart Card Interface Mode .................................................................... 637
25.10.5
Interrupts in Simple IIC Mode ..................................................................................... 638
25.11
Event Linking ...................................................................................................................... 638
25.12
Noise Cancellation Function ............................................................................................... 639
25.13
Usage Notes ....................................................................................................................... 640
25.13.1
Settings for the Module-Stop State............................................................................. 640
25.13.2
SCI Operations during Low Power State.................................................................... 640
25.13.3
Break Detection and Processing ................................................................................ 645
25.13.4
Mark State and Production of Breaks......................................................................... 646
25.13.5
Receive Error Flags and Transmit Operations in Clock Synchronous and Simple SPI
Modes......................................................................................................................... 646
25.13.6
Restrictions on Clock Synchronous Transmission in Clock Synchronous and Simple SPI
Modes......................................................................................................................... 646
25.13.7
Restrictions on Using DTC ......................................................................................... 647
25.13.8
Notes on Starting Transfer ......................................................................................... 648
25.13.9
External Clock Input in Clock Synchronous and Simple SPI Modes .......................... 648
25.13.10 Limitations on Simple SPI mode................................................................................. 648
26.
I2C Bus Interface (IIC)................................................................................................................... 650
26.1
Overview............................................................................................................................. 650
26.2
Register Descriptions.......................................................................................................... 652
26.2.1
I2C Bus Control Register 1 (ICCR1) ........................................................................... 652
26.2.2
I2C Bus Control Register 2 (ICCR2) ........................................................................... 654
26.2.3
I2C Bus Mode Register 1 (ICMR1) ............................................................................. 657
26.2.4
I2C Bus Mode Register 2 (ICMR2) ............................................................................. 658
26.2.5
I2C Bus Mode Register 3 (ICMR3) ............................................................................. 659
26.2.6
I2C Bus Function Enable Register (ICFER)................................................................ 661
26.2.7
I2C Bus Status Enable Register (ICSER) ................................................................... 662
26.2.8
I2C Bus Interrupt Enable Register (ICIER) ................................................................. 663
26.2.9
I2C Bus Status Register 1 (ICSR1)............................................................................. 665
26.2.10
I2C Bus Status Register 2 (ICSR2)............................................................................. 667
26.2.11
I2C Bus Wakeup Unit Register (ICWUR).................................................................... 670
26.2.12
Reserved (ICWUR2)................................................................................................... 671
26.2.13
Slave Address Register Ly (SARLy) (y = 0 to 2) ........................................................ 671
26.2.14
Slave Address Register Uy (SARUy) (y = 0 to 2) ....................................................... 672
26.2.15
I2C Bus Bit Rate Low-Level Register (ICBRL)............................................................ 672
26.2.16
I2C Bus Bit Rate High-Level Register (ICBRH) .......................................................... 673
26.2.17
I2C Bus Transmit Data Register (ICDRT) ................................................................... 674
26.2.18
I2C Bus Receive Data Register (ICDRR) ................................................................... 674
26.2.19
I2C Bus Shift Register (ICDRS) .................................................................................. 675
26.3
Operation ............................................................................................................................ 675
26.3.1
Communication Data Format...................................................................................... 675
26.3.2
Initial Settings ............................................................................................................. 676
26.3.3
Master Transmit Operation......................................................................................... 677
26.3.4
Master Receive Operation.......................................................................................... 680
26.3.5
Slave Transmit Operation........................................................................................... 685
26.3.6
Slave Receive Operation............................................................................................ 688
26.4
SCL Synchronization Circuit ............................................................................................... 690
26.5
SDA Output Delay Function................................................................................................ 690
26.6
Digital Noise Filter Circuits.................................................................................................. 691
26.7
Address Match Detection.................................................................................................... 692
26.7.1
Slave-Address Match Detection ................................................................................. 692
26.7.2
Detection of General Call Address ............................................................................. 694
26.7.3
Device-ID Address Detection ..................................................................................... 695
26.7.4
Host Address Detection.............................................................................................. 696
26.8
Wakeup Function................................................................................................................ 697
26.8.1
Normal Wakeup Mode 1............................................................................................. 698
26.8.2
Normal Wakeup Mode 2............................................................................................. 701
26.8.3
Command Recovery Mode and EEP Response Mode (Special Wakeup Modes) ..... 703
26.8.4
Precautions for WFI Instruction Execution ................................................................. 706
26.9
Automatic Low-Hold Function for SCL................................................................................ 706
26.9.1
Function to Prevent Wrong Transmission of Transmit Data....................................... 706
26.9.2
NACK Reception Transfer Suspension Function ....................................................... 707
26.9.3
Function to Prevent Failure to Receive Data.............................................................. 708
26.10
Arbitration-Lost Detection Functions................................................................................... 709
26.10.1
Master Arbitration-Lost Detection (MALE Bit)............................................................. 709
26.10.2
Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) .......... 711
26.10.3
Slave Arbitration-Lost Detection (SALE Bit) ............................................................... 712
26.11
Start, Restart, and Stop Condition Issuing Function........................................................... 713
26.11.1
Issuing a Start Condition ............................................................................................ 713
26.11.2
Issuing a Restart Condition ........................................................................................ 713
26.11.3
Issuing a Stop Condition............................................................................................. 715
26.12
Bus Hanging ....................................................................................................................... 716
26.12.1
Timeout Function........................................................................................................ 716
26.12.2
Extra SCL Clock Cycle Output Function..................................................................... 717
26.12.3
IIC Reset and Internal Reset ...................................................................................... 718
26.13
SMBus Operation ............................................................................................................... 718
26.13.1
SMBus Timeout Measurement ................................................................................... 718
26.13.2
Packet Error Code (PEC) ........................................................................................... 719
26.13.3
SMBus Host Notification Protocol (Notify ARP Master Command) ............................ 720
26.14
Interrupt Sources ................................................................................................................ 720
26.14.1
Buffer Operation for IICn_TXI and IICn_RXI Interrupts .............................................. 721
26.15
State of Registers when Issuing Each Condition................................................................ 721
26.16
Event Link Output ............................................................................................................... 722
26.16.1
26.17
27.
Interrupt Handling and Event Linking ......................................................................... 722
Usage Notes ....................................................................................................................... 722
26.17.1
Settings for the Module-Stop State............................................................................. 722
26.17.2
Notes on Starting Transfer ......................................................................................... 722
Controller Area Network (CAN) Module........................................................................................ 723
27.1
Overview............................................................................................................................. 723
27.2
Register Descriptions.......................................................................................................... 725
27.2.1
Control Register (CTLR)............................................................................................. 725
27.2.2
Bit Configuration Register (BCR)................................................................................ 728
27.2.3
Mask Register k (MKRk) (k = 0 to 7) .......................................................................... 730
27.2.4
FIFO Received ID Compare Registers 0 and 1 (FIDCR0 and FIDCR1) .................... 730
27.2.5
Mask Invalid Register (MKIVLR) ................................................................................ 732
27.2.6
Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31, m = 0 to 7) ..... 732
27.2.7
Mailbox Interrupt Enable Register (MIER).................................................................. 736
27.2.8
Mailbox Interrupt Enable Register for FIFO Mailbox Mode (MIER_FIFO).................. 737
27.2.9
Message Control Register for Transmit (MCTL_TXj) (j = 0 to 31) .............................. 738
27.2.10
Message Control Register for Receive (MCTL_RXj) (j = 0 to 31)............................... 740
27.2.11
Receive FIFO Control Register (RFCR) ..................................................................... 741
27.2.12
Receive FIFO Pointer Control Register (RFPCR) ...................................................... 743
27.2.13
Transmit FIFO Control Register (TFCR)..................................................................... 744
27.2.14
Transmit FIFO Pointer Control Register (TFPCR)...................................................... 745
27.2.15
Status Register (STR)................................................................................................. 746
27.2.16
Mailbox Search Mode Register (MSMR) .................................................................... 748
27.2.17
Mailbox Search Status Register (MSSR).................................................................... 748
27.2.18
Channel Search Support Register (CSSR) ................................................................ 749
27.2.19
Acceptance Filter Support Register (AFSR)............................................................... 750
27.2.20
Error Interrupt Enable Register (EIER)....................................................................... 751
27.2.21
Error Interrupt Factor Judge Register (EIFR) ............................................................. 752
27.2.22
Receive Error Count Register (RECR) ....................................................................... 754
27.2.23
Transmit Error Count Register (TECR)....................................................................... 754
27.2.24
Error Code Store Register (ECSR)............................................................................. 755
27.2.25
Time Stamp Register (TSR)........................................................................................ 756
27.2.26
Test Control Register (TCR) ....................................................................................... 756
27.3
Operation Modes ................................................................................................................ 758
27.3.1
CAN Reset Mode........................................................................................................ 758
27.3.2
CAN Halt Mode........................................................................................................... 759
27.3.3
CAN Sleep Mode........................................................................................................ 760
27.3.4
CAN Operation Mode (Excluding Bus-Off State)........................................................ 760
27.3.5
CAN Operation Mode (Bus-Off State) ........................................................................ 761
27.4
28.
Data Transfer Rate Configuration....................................................................................... 762
27.4.1
Clock Setting .............................................................................................................. 762
27.4.2
Bit Time Setting .......................................................................................................... 762
27.4.3
Data Transfer Rate ..................................................................................................... 762
27.5
Mailbox and Mask Register Structure................................................................................. 763
27.6
Acceptance Filtering and Masking Functions ..................................................................... 764
27.7
Reception and Transmission .............................................................................................. 766
27.7.1
Reception ................................................................................................................... 766
27.7.2
Transmission .............................................................................................................. 768
27.8
Interrupt .............................................................................................................................. 769
27.9
Usage Notes ....................................................................................................................... 770
27.9.1
Settings for the Module-Stop State............................................................................. 770
27.9.2
Settings for the Operating Clock................................................................................. 770
Serial Peripheral Interface (SPI) ................................................................................................... 771
28.1
Overview............................................................................................................................. 771
28.2
Register Descriptions.......................................................................................................... 774
28.2.1
SPI Control Register (SPCR) ..................................................................................... 774
28.2.2
SPI Slave Select Polarity Register (SSLP)................................................................. 776
28.2.3
SPI Pin Control Register (SPPCR)............................................................................. 776
28.2.4
SPI Status Register (SPSR) ....................................................................................... 777
28.2.5
SPI Data Register (SPDR/SPDR_HA) ....................................................................... 779
28.2.6
SPI Bit Rate Register (SPBR) .................................................................................... 781
28.2.7
SPI Data Control Register (SPDCR) .......................................................................... 782
28.2.8
SPI Clock Delay Register (SPCKD) ........................................................................... 782
28.2.9
SPI Slave Select Negation Delay Register (SSLND) ................................................. 783
28.2.10
SPI Next-Access Delay Register (SPND)................................................................... 784
28.2.11
SPI Control Register 2 (SPCR2) ................................................................................ 784
28.2.12
SPI Command Registers 0 (SPCMD0)....................................................................... 785
28.3
Operation ............................................................................................................................ 787
28.3.1
Overview of SPI Operations ....................................................................................... 787
28.3.2
Controlling the SPI Pins.............................................................................................. 788
28.3.3
SPI System Configuration Examples.......................................................................... 789
28.3.3.1
Single master and single slave with the MCU as a master ................................ 789
28.3.3.2
Single master and single slave with the MCU as a slave................................... 790
28.3.3.3
Single master and multi-slave with the MCU as a master.................................. 790
28.3.3.4
Single master and multi-slave with the MCU as a slave .................................... 791
28.3.3.5
Multi-master and multi-slave with the MCU as a master .................................... 792
28.3.3.6
Master and slave in clock synchronous mode with the MCU as a master ......... 793
28.3.3.7
Master and slave in clock synchronous mode with the MCU as slave............... 794
28.3.4
Data Format................................................................................................................ 794
28.3.4.1
Operation when parity is disabled (SPCR2.SPPE = 0) ...................................... 795
28.3.4.2
28.3.5
Transfer Formats ........................................................................................................ 802
28.3.5.1
CPHA = 0 ........................................................................................................... 802
28.3.5.2
CPHA = 1 ........................................................................................................... 803
28.3.6
Data Transfer Modes.................................................................................................. 804
28.3.6.1
Full-duplex synchronous serial communications (SPCR.TXMD = 0) ................. 804
28.3.6.2
Transmit-only operations (SPCR.TXMD = 1) ..................................................... 805
28.3.7
Transmit Buffer Empty and Receive Buffer Full Interrupts ......................................... 805
28.3.8
Error Detection ........................................................................................................... 807
28.3.8.1
Overrun errors .................................................................................................... 808
28.3.8.2
Parity errors........................................................................................................ 809
28.3.8.3
Mode fault errors ................................................................................................ 810
28.3.8.4
Underrun errors .................................................................................................. 810
28.3.9
Initializing SPI ............................................................................................................. 811
28.3.9.1
Initialization by clearing the SPE bit ................................................................... 811
28.3.9.2
Initialization by system reset .............................................................................. 811
28.3.10
SPI Operation ............................................................................................................. 811
28.3.10.1
Master mode operation ...................................................................................... 811
28.3.10.2
Slave mode operation ........................................................................................ 817
28.3.11
Clock Synchronous Operation.................................................................................... 820
28.3.11.1
Master mode operation ...................................................................................... 820
28.3.11.2
Slave mode operation ........................................................................................ 822
28.3.12
Loopback Mode .......................................................................................................... 823
28.3.13
Self-Diagnosis of Parity Bit Function .......................................................................... 824
28.3.14
Interrupt Sources ........................................................................................................ 825
28.4
Event Link Operation .......................................................................................................... 826
28.4.1
Receive Buffer Full Event Output ............................................................................... 826
28.4.2
Transmit Buffer Empty Event Output.......................................................................... 827
28.4.3
Mode Fault, Underrun, Overrun, or Parity Error Event Output ................................... 827
28.4.4
SPI Idle Event Output ................................................................................................. 827
28.4.5
Transmission-Complete Event Output........................................................................ 827
28.5
29.
When parity is enabled (SPCR2.SPPE = 1)....................................................... 798
Usage Notes ....................................................................................................................... 828
28.5.1
Settings for the Module-Stop State............................................................................. 828
28.5.2
Restrictions on Low Power Function .......................................................................... 828
28.5.3
Restrictions on Starting Transfer ................................................................................ 828
28.5.4
Restrictions on Mode Fault, Underrun, Overrun, or Parity Error Event Output .......... 828
28.5.5
Constraints on the SPRF and SPTEF Flags .............................................................. 828
Cyclic Redundancy Check (CRC) Calculator................................................................................ 829
29.1
Overview............................................................................................................................. 829
29.2
Register Descriptions.......................................................................................................... 830
29.2.1
CRC Control Register 0 (CRCCR0) ........................................................................... 830
29.2.2
CRC Control Register 1 (CRCCR1) ........................................................................... 830
29.2.3
CRC Data Input Register (CRCDIR/CRCDIR_BY)..................................................... 831
29.2.4
CRC Data Output Register (CRCDOR/CRCDOR_HA/CRCDOR_BY) ...................... 831
29.2.5
Snoop Address Register (CRCSAR) .......................................................................... 832
29.3
29.3.1
Basic Operation .......................................................................................................... 832
29.3.2
CRC Snoop ................................................................................................................ 835
29.4
30.
Operation ............................................................................................................................ 832
Usage Notes ....................................................................................................................... 836
29.4.1
Settings for the Module-Stop State............................................................................. 836
29.4.2
Note on Transmission................................................................................................. 836
14-Bit A/D Converter (ADC14)...................................................................................................... 837
30.1
Overview............................................................................................................................. 837
30.2
Register Descriptions.......................................................................................................... 840
30.2.1
A/D Data Registers y (ADDRy), A/D Data Duplexing Register (ADDBLDR),
A/D Data Duplexing Register A (ADDBLDRA), A/D Data Duplexing Register B
(ADDBLDRB), A/D Temperature Sensor Data Register (ADTSDR),
A/D Internal Reference Voltage Data Register (ADOCDR) ........................................ 840
30.2.2
A/D Self-Diagnosis Data Register (ADRD)................................................................. 843
30.2.3
A/D Control Register (ADCSR)................................................................................... 846
30.2.4
A/D Channel Select Register A0 (ADANSA0) ............................................................ 849
30.2.5
A/D Channel Select Register A1 (ADANSA1) ............................................................ 850
30.2.6
A/D Channel Select Register B0 (ADANSB0) ............................................................ 850
30.2.7
A/D Channel Select Register B1 (ADANSB1) ............................................................ 851
30.2.8
A/D-Converted Value Addition/Average Channel Select Register 0 (ADADS0) ......... 851
30.2.9
A/D-Converted Value Addition/Average Channel Select Register 1 (ADADS1) ......... 853
30.2.10
A/D-Converted Value Addition/Average Count Select Register (ADADC).................. 853
30.2.11
A/D Control Extended Register (ADCER) .................................................................. 854
30.2.12
A/D Conversion Start Trigger Select Register (ADSTRGR) ....................................... 856
30.2.13
A/D Conversion Extended Input Control Register (ADEXICR)................................... 857
30.2.14
A/D Sampling State Register n (ADSSTRn) (n = 00 to 10, L, T, O) ........................... 858
30.2.15
A/D Disconnection Detection Control Register (ADDISCR) ....................................... 859
30.2.16
A/D Group Scan Priority Control Register (ADGSPCR) ............................................. 860
30.2.17
A/D Compare Function Control Register (ADCMPCR) .............................................. 861
30.2.18
A/D Compare Function Window A Channel Select Register 0 (ADCMPANSR0) ....... 863
30.2.19
A/D Compare Function Window A Channel Select Register 1 (ADCMPANSR1) ....... 863
30.2.20
A/D Compare Function Window A Extended Input Select Register (ADCMPANSER).....
.................................................................................................................................... 864
30.2.21
A/D Compare Function Window A Comparison Condition Setting Register 0
(ADCMPLR0).............................................................................................................. 864
30.2.22
A/D Compare Function Window A Comparison Condition Setting Register 1
(ADCMPLR1).............................................................................................................. 866
30.2.23
A/D Compare Function Window A Extended Input Comparison Condition Setting Register (ADCMPLER) ........................................................................................................ 866
30.2.24
A/D Compare Function Window A Lower-Side Level Setting Register (ADCMPDR0), A/D
Compare Function Window A Upper-Side Level Setting Register (ADCMPDR1), A/D
Compare Function Window B Lower-Side Level Setting Register (ADWINLLB), A/D
Compare Function Window B Upper-Side Level Setting Register (ADWINULB) ....... 867
30.2.25
A/D Compare Function Window A Channel Status Register 0 (ADCMPSR0)............ 869
30.2.26
A/D Compare Function Window A Channel Status Register1 (ADCMPSR1)............. 869
30.2.27
A/D Compare Function Window A Extended Input Channel Status Register
(ADCMPSER)............................................................................................................. 870
30.2.28
A/D Compare Function Window B Channel Select Register (ADCMPBNSR)............ 871
30.2.29
A/D Compare Function Window B Status Register (ADCMPBSR)............................. 872
30.2.30
A/D Compare Function Window A/B Status Monitor Register (ADWINMON) ............ 873
30.2.31
A/D High-Potential/Low-Potential Reference Voltage Control Register
(ADHVREFCNT)......................................................................................................... 874
30.3
Operation ............................................................................................................................ 875
30.3.1
Scanning Operation.................................................................................................... 875
30.3.2
Single Scan Mode ...................................................................................................... 875
30.3.2.1
Basic operation................................................................................................... 875
30.3.2.2
Channel selection and self-diagnosis................................................................. 876
30.3.2.3
A/D conversion of temperature sensor output/internal reference voltage .......... 877
30.3.2.4
A/D conversion in double trigger mode .............................................................. 878
30.3.2.5
Extended operations when double trigger mode is selected.............................. 879
30.3.3
Continuous Scan Mode .............................................................................................. 880
30.3.3.1
Basic operation................................................................................................... 880
30.3.3.2
Channel selection and self-diagnosis................................................................. 881
30.3.4
Group Scan Mode ...................................................................................................... 882
30.3.4.1
Basic operation................................................................................................... 882
30.3.4.2
A/D conversion in double trigger mode .............................................................. 883
30.3.4.3
Operation under group A priority control ............................................................ 884
30.3.5
Compare Function for Windows A and B ................................................................... 892
30.3.5.1
Compare function windows A and B .................................................................. 892
30.3.5.2
Event output of compare function....................................................................... 893
30.3.5.3
Restrictions on the compare function ................................................................. 895
30.3.6
Analog Input Sampling and Scan Conversion Time ................................................... 895
30.3.7
Usage Example of A/D Data Register Automatic Clearing Function .......................... 898
30.3.8
A/D-Converted Value Addition/Average Mode ........................................................... 898
30.3.9
Disconnection Detection Assist Function ................................................................... 898
30.3.10
Starting A/D Conversion with Asynchronous Trigger ................................................. 900
30.3.11
Starting A/D Conversion with Synchronous Trigger from Peripheral Module............. 900
30.4
Interrupt Sources and DTC Transfer Requests .................................................................. 901
30.4.1
30.5
Interrupt Requests ...................................................................................................... 901
Event Link Function ............................................................................................................ 901
30.5.1
Event Output to the ELC............................................................................................. 901
30.5.2
ADC14 Operation through an event from the ELC ..................................................... 902
31.
30.6
Selecting Reference Voltage .............................................................................................. 902
30.7
A/D Conversion Procedure when Selecting Internal Reference Voltage
as High-Potential Reference Voltage.................................................................................. 902
30.8
Usage Notes ....................................................................................................................... 903
30.8.1
Notes on Reading Data Registers .............................................................................. 903
30.8.2
Notes on Stopping A/D Conversion............................................................................ 903
30.8.3
A/D Conversion Restart Timing and Termination Timing ........................................... 904
30.8.4
Constraints on Scan End Interrupt Handling .............................................................. 904
30.8.5
Settings for the Module-Stop State............................................................................. 904
30.8.6
Constraints on Entering the Low Power States .......................................................... 905
30.8.7
Error in Absolute Accuracy When Disconnection Detection Assistance is in Use...... 905
30.8.8
ADHSC Bit Rewriting Procedure ................................................................................ 905
30.8.9
Operating Modes and Status Bits............................................................................... 905
30.8.10
Notes on Board Design .............................................................................................. 905
30.8.11
Noise Reduction ......................................................................................................... 905
30.8.12
Port Setting when Using the ADC14 Input ................................................................. 906
30.8.13
Relationship between the A/D Converter and ACMPLP............................................. 906
30.8.14
Notes on Canceling Software Standby Mode............................................................. 906
12-Bit D/A Converter (DAC12)...................................................................................................... 907
31.1
Overview............................................................................................................................. 907
31.2
Register Descriptions.......................................................................................................... 908
31.2.1
D/A Data Register 0 (DADR0) .................................................................................... 908
31.2.2
D/A Control Register (DACR) ..................................................................................... 908
31.2.3
DADR0 Format Select Register (DADPR).................................................................. 909
31.2.4
D/A A/D Synchronous Start Control Register (DAADSCR) ........................................ 909
31.2.5
D/A VREF Control Register (DAVREFCR)................................................................. 910
31.3
Operation ............................................................................................................................ 910
31.3.1
32.
Minimizing Interference between D/A and A/D Conversion........................................ 911
31.4
Event Link Operation Setting Procedure ............................................................................ 913
31.5
Usage Notes on Event Link Operation ............................................................................... 913
31.6
Usage Notes ....................................................................................................................... 913
31.6.1
Settings for the Module-Stop Function ....................................................................... 913
31.6.2
DAC12 Operation in Module-Stop State..................................................................... 913
31.6.3
DAC12 Operation in Software Standby Mode ............................................................ 913
31.6.4
Constraint on Usage when Interference Reduction between D/A and A/D
Conversion Is Enabled ............................................................................................... 913
Temperature Sensor (TSN)........................................................................................................... 914
32.1
Overview............................................................................................................................. 914
32.2
Register Descriptions.......................................................................................................... 914
32.2.1
Temperature Sensor Calibration Data Register H (TSCDRH) .................................... 914
32.2.2
Temperature Sensor Calibration Data Register L (TSCDRL) ..................................... 915
32.3
Using the Temperature Sensor........................................................................................... 915
33.
34.
32.3.1
Preparation for Using the Temperature Sensor.......................................................... 915
32.3.2
Procedures for Using the Temperature Sensor.......................................................... 916
Low-Power Analog Comparator (ACMPLP).................................................................................. 917
33.1
Overview............................................................................................................................. 917
33.2
Register Descriptions.......................................................................................................... 919
33.2.1
ACMPLP Mode Setting Register (COMPMDR).......................................................... 919
33.2.2
ACMPLP Filter Control Register (COMPFIR)............................................................. 920
33.2.3
ACMPLP Output Control Register (COMPOCR)........................................................ 920
33.3
Operation ............................................................................................................................ 921
33.4
Noise Filter.......................................................................................................................... 923
33.5
ACMPLP Interrupts............................................................................................................. 924
33.6
ELC Event Output............................................................................................................... 924
33.7
Interrupt Handling and ELC Linking.................................................................................... 925
33.8
Comparator Pin Output....................................................................................................... 925
33.9
Usage Notes ....................................................................................................................... 925
33.9.1
Settings for the Module-Stop State............................................................................. 925
33.9.2
Relationship between ADC14 and ACMPLP.............................................................. 925
Capacitive Touch Sensing Unit (CTSU) ........................................................................................ 926
34.1
Overview............................................................................................................................. 926
34.2
Register Descriptions.......................................................................................................... 928
34.2.1
CTSU Control Register 0 (CTSUCR0) ....................................................................... 928
34.2.2
CTSU Control Register 1 (CTSUCR1) ....................................................................... 929
34.2.3
CTSU Synchronous Noise Reduction Setting Register (CTSUSDPRS) .................... 930
34.2.4
CTSU Sensor Stabilization Wait Control Register (CTSUSST) .................................. 931
34.2.5
CTSU Measurement Channel Register 0 (CTSUMCH0)............................................ 932
34.2.6
CTSU Measurement Channel Register 1 (CTSUMCH1)............................................ 934
34.2.7
CTSU Channel Enable Control Register 0 (CTSUCHAC0)........................................ 935
34.2.8
CTSU Channel Enable Control Register 1 (CTSUCHAC1)........................................ 935
34.2.9
CTSU Channel Enable Control Register 2 (CTSUCHAC2)........................................ 936
34.2.10
CTSU Channel Enable Control Register 3 (CTSUCHAC3)........................................ 936
34.2.11
CTSU Channel Transmit/Receive Control Register 0 (CTSUCHTRC0)..................... 937
34.2.12
CTSU Channel Transmit/Receive Control Register 1 (CTSUCHTRC1)..................... 937
34.2.13
CTSU Channel Transmit/Receive Control Register 2 (CTSUCHTRC2)..................... 938
34.2.14
CTSU Channel Transmit/Receive Control Register 3 (CTSUCHTRC3)..................... 938
34.2.15
CTSU High-Pass Noise Reduction Control Register (CTSUDCLKC) ........................ 939
34.2.16
CTSU Status Register (CTSUST)............................................................................... 939
34.2.17
CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register
(CTSUSSC) ................................................................................................................ 940
34.2.18
CTSU Sensor Offset Register 0 (CTSUSO0) ............................................................. 941
34.2.19
CTSU Sensor Offset Register 1 (CTSUSO1) ............................................................. 942
34.2.20
CTSU Sensor Counter (CTSUSC) ............................................................................. 944
34.2.21
CTSU Reference Counter (CTSURC) ........................................................................ 944
34.2.22
34.3
Operation ............................................................................................................................ 945
34.3.1
Principles of Measurement Operation ........................................................................ 945
34.3.2
Measurement Modes.................................................................................................. 947
34.3.2.1
Initial settings flow .............................................................................................. 947
34.3.2.2
Status counter .................................................................................................... 948
34.3.2.3
Self-capacitance single scan mode operation.................................................... 949
34.3.2.4
Self-capacitance multiscan mode operation....................................................... 951
34.3.2.5
Mutual capacitance full scan mode operation .................................................... 953
34.3.3
34.4
35.
Functions Common to Multiple Modes ....................................................................... 956
34.3.3.1
Sensor stabilization wait time and measurement time ....................................... 956
34.3.3.2
Interrupts ............................................................................................................ 957
Usage Notes ....................................................................................................................... 958
34.4.1
Measurement Result Data (CTSUSC and CTSURC Counters) ................................. 958
34.4.2
Software Trigger ......................................................................................................... 958
34.4.3
External Trigger .......................................................................................................... 959
34.4.4
Notes on Forcing Operation Stop ............................................................................... 959
34.4.5
TSCAP Pin ................................................................................................................. 959
34.4.6
Notes on Measurement Operation (CTSUCR0.CTSUSTRT Bit = 1).......................... 959
Data Operation Circuit (DOC) ....................................................................................................... 960
35.1
Overview............................................................................................................................. 960
35.2
Register Descriptions.......................................................................................................... 961
35.2.1
DOC Control Register (DOCR)................................................................................... 961
35.2.2
DOC Data Input Register (DODIR)............................................................................. 962
35.2.3
DOC Data Setting Register (DODSR) ........................................................................ 962
35.3
Operation ............................................................................................................................ 962
35.3.1
Data Comparison Mode.............................................................................................. 962
35.3.2
Data Addition Mode .................................................................................................... 963
35.3.3
Data Subtraction Mode............................................................................................... 963
35.4
Interrupt Request and Event Link Output ........................................................................... 964
35.5
Usage Note......................................................................................................................... 964
35.5.1
36.
CTSU Error Status Register (CTSUERRS) ................................................................ 945
Settings for the Module-Stop State............................................................................. 964
SRAM............................................................................................................................................ 965
36.1
Overview............................................................................................................................. 965
36.2
Register Descriptions......................................................................................................... 965
36.2.1
SRAM Parity Error Operation After Detection Register (PARIOAD)........................... 965
36.2.2
SRAM Protection Register (SRAMPRCR).................................................................. 966
36.2.3
Trace Control (for the MTB)........................................................................................ 966
36.2.4
CoreSight™ (for MTB)................................................................................................ 966
36.3
Operation ............................................................................................................................ 967
36.3.1
Parity Calculation Function......................................................................................... 967
36.3.2
SRAM Error Source.................................................................................................... 968
36.3.3
Access Cycle .............................................................................................................. 968
36.4
37.
Usage Note......................................................................................................................... 969
36.4.1
Instruction Fetch from the SRAM Area....................................................................... 969
36.4.2
Store Buffer of SRAM ................................................................................................. 969
Flash Memory ............................................................................................................................... 970
37.1
Overview............................................................................................................................. 970
37.2
Memory Structure ............................................................................................................... 971
37.3
Operating Modes Associated with the Flash Memory ........................................................ 972
37.3.1
37.4
ID Code Protection ..................................................................................................... 973
Overview of Functions ........................................................................................................ 973
37.4.1
Configuration Area Bit Map ........................................................................................ 975
37.4.2
Startup Area Select .................................................................................................... 975
37.4.3
Protection with the Access Window............................................................................ 976
37.5
Programming Commands................................................................................................... 977
37.6
Suspend Operation............................................................................................................. 977
37.7
Protection............................................................................................................................ 977
37.8
Serial Programming Mode .................................................................................................. 977
37.8.1
SCI Boot Mode ........................................................................................................... 977
37.9
Using a Serial Programmer ................................................................................................ 978
37.10
Self-Programming............................................................................................................... 978
37.10.1
Overview..................................................................................................................... 978
37.10.2
Background Operation................................................................................................ 979
37.11
Reading the Flash Memory................................................................................................. 979
37.11.1
Reading the Code Flash Memory............................................................................... 979
37.11.2
Reading the Data Flash Memory................................................................................ 979
37.12
Usage Notes ....................................................................................................................... 979
37.12.1
Erase Suspended Area .............................................................................................. 979
37.12.2
Suspension with Erase Suspend Commands ............................................................ 979
37.12.3
Constraint on Additional Writes .................................................................................. 979
37.12.4
Reset during Programming and Erasing .................................................................... 980
37.12.5
Non-maskable Interrupt Disabled during Programming and Erasing ......................... 980
37.12.6
Location of Interrupt Vectors during Programming and Erasing................................. 980
37.12.7
Programming and Erasing in Low-Speed Operating Mode ........................................ 980
37.12.8
Abnormal Termination during Programming and Erasing .......................................... 980
37.12.9
Actions Prohibited during Programming and Erasing................................................. 980
38.
AES Engine................................................................................................................................... 981
39.
True Random Number Generator (TRNG) ................................................................................... 982
40.
Internal Voltage Regulator ............................................................................................................ 983
40.1
Overview............................................................................................................................. 983
40.2
Operation ............................................................................................................................ 983
41.
Electrical Characteristics............................................................................................................... 984
41.1
Absolute Maximum Ratings ................................................................................................ 985
41.2
DC Characteristics.............................................................................................................. 987
41.2.1
Tj/Ta Definition ........................................................................................................... 987
41.2.2
I/O VIH, VIL ................................................................................................................ 987
41.2.3
I/O IOH, IOL................................................................................................................ 989
41.2.4
I/O VOH, VOL, and Other Characteristics .................................................................. 990
41.2.5
I/O Pin Output Characteristics of Low Drive Capacity ................................................ 992
41.2.6
I/O Pin Output Characteristics of Middle Drive Capacity ............................................ 994
41.2.7
P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity ........................ 997
41.2.8
IIC I/O Pin Output Characteristics .............................................................................. 999
41.2.9
Operating and Standby Current................................................................................ 1000
41.2.10
VCC Rise and Fall Gradient and Ripple Frequency ................................................. 1007
41.3
AC Characteristics ............................................................................................................ 1008
41.3.1
Frequency................................................................................................................. 1008
41.3.2
Clock Timing............................................................................................................. 1010
41.3.3
Reset Timing ............................................................................................................ 1012
41.3.4
Wakeup Time ........................................................................................................... 1013
41.3.5
NMI and IRQ Noise Filter ......................................................................................... 1016
41.3.6
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing ............................. 1017
41.3.7
CAC Timing .............................................................................................................. 1018
41.3.8
SCI Timing................................................................................................................ 1019
41.3.9
SPI Timing ................................................................................................................ 1026
41.3.10
IIC Timing ................................................................................................................. 1032
41.3.11
CLKOUT Timing ....................................................................................................... 1034
41.4
USB Characteristics.......................................................................................................... 1035
41.4.1
USBFS Timing.......................................................................................................... 1035
41.4.2
USB External Supply ................................................................................................ 1036
41.5
ADC14 Characteristics ..................................................................................................... 1037
41.6
DAC12 Characteristics ..................................................................................................... 1047
41.7
TSN Characteristics.......................................................................................................... 1048
41.8
OSC Stop Detect Characteristics ..................................................................................... 1048
41.9
POR and LVD Characteristics .......................................................................................... 1049
41.10
CTSU Characteristics ....................................................................................................... 1052
41.11
Comparator Characteristics .............................................................................................. 1053
41.12
Flash Memory Characteristics .......................................................................................... 1054
41.12.1
Code Flash Memory Characteristics ........................................................................ 1054
41.12.2
Data Flash Memory Characteristics ......................................................................... 1055
41.12.3
Serial Wire Debug (SWD)......................................................................................... 1057
Appendix 1. Port States in Each Processing Mode ............................................................................. 1059
Appendix 2. Package Dimensions ....................................................................................................... 1061
Appendix 3. I/O Registers.................................................................................................................... 1067
3.1
Peripheral Base Addresses .............................................................................................. 1067
3.2
Access Cycles .................................................................................................................. 1068
3.3
Register Descriptions........................................................................................................ 1070
Revision History .................................................................................................................................... 1095
Features
S124 Microcontroller Group
User’s Manual
Ultra-low power 32-MHz Arm® Cortex®-M0+ microcontroller, 128-KB code flash memory, 16-KB SRAM, Capacitive
Touch Sensing Unit, 14-bit A/D Converter, 12-bit D/A Converter, security and safety features.
Features
■ Arm Cortex-M0+ Core
Armv6-M architecture
Maximum operating frequency: 32 MHz
Debug and Trace: DWT, BPU, CoreSight™ MTB-M0+
CoreSight Debug Port: SW-DP
■ Memory
128-KB code flash memory
4-KB data flash memory (100,000 erase/write cycles)
Up to 16-KB SRAM
128-bit unique ID
■ Connectivity
USB 2.0 Full-Speed Module (USBFS)
- On-chip transceiver with voltage regulator
- Compliant with USB Battery Charging Specification 1.2
Serial Communications Interface (SCI) × 3
- UART
- Simple IIC
- Simple SPI
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 2
CAN module (CAN)
■ Analog
14-Bit A/D Converter (ADC14)
12-Bit D/A Converter (DAC12)
Low-Power Analog Comparator (ACMPLP) × 2
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-Bit (GPT32)
General PWM Timer 16-Bit (GPT16) × 6
Asynchronous General-Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
■ Safety
SRAM Parity Error Check
Flash Area Protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) Calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO Readback Level Detection
Register Write Protection
Main Oscillator Stop Detection
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■ System and Power Management
Low-power modes
Realtime Clock (RTC)
Event Link Controller (ELC)
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection with voltage settings
■ Security and Encryption
AES128/256
True Random Number Generator (TRNG)
■ Human Machine Interface (HMI)
Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
Main clock oscillator (MOSC)
(1 to 20 MHz when VCC = 2.4 to 5.5 V)
(1 to 8 MHz when VCC = 1.8 to 5.5 V)
(1 to 4 MHz when VCC = 1.6 to 5.5 V)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO)
(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)
(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)
(24, 32 MHz when VCC = 1.6 to 5.5 V)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
Independent watchdog timer OCO (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
■ General Purpose I/O Ports
Up to 51 input/output pins
- Up to 3 CMOS input
- Up to 48 CMOS input/output
- Up to 6 input/output 5 V tolerant
- Up to 16 pins high current (20 mA)
■ Operating Voltage
VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
Ta = –40°C to +85°C
- 36-pin LGA (4 mm × 4 mm, 0.5 mm pitch)
Ta = –40°C to +105°C
- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
- 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch)
- 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch)
- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)
- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)
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1.
1. Overview
Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit MCUs that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
Based on the energy-efficient Arm Cortex®-M0+ core, the MCU is particularly well suited for cost-sensitive and lowpower applications with the following features:
128-KB code flash memory
16-KB SRAM
Capacitive Touch Sensing Unit (CTSU)
14-bit A/D Converter (ADC14)
12-bit D/A Converter (DAC12)
Security features.
1.1
Function Outline
Table 1.1
Arm core
Feature
Functional description
Arm Cortex-M0+
Maximum operating frequency: up to 32 MHz
Arm Cortex-M0+:
- Revision: r0p1-00rel0
- Armv6-M architecture profile
- Single-cycle integer multiplier.
SysTick timer
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2
Memory
Feature
Functional description
Code flash memory
Maximum 128 KB code flash memory. See section 37, Flash Memory.
Data flash memory
4 KB data flash memory. See section 37, Flash Memory.
Option-setting memory
The option-setting memory determines the state of the MCU after a reset. See section 6,
Option-Setting Memory.
SRAM
On-chip high-speed SRAM with even parity bit. See section 36, SRAM.
Table 1.3
System (1 of 2)
Feature
Functional description
Operating mode
Two operating modes:
Single-chip mode
SCI boot mode.
See section 3, Operating Modes.
Reset
9 types of resets:
RES pin reset
Power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
Software reset.
See section 5, Resets.
Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin and the
detection level can be selected using a software program. See section 7, Low Voltage
Detection (LVD).
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Table 1.3
1. Overview
System (2 of 2)
Feature
Functional description
Clock
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
Independent watchdog timer on-chip oscillator
Clock out support.
See section 8, Clock Generation Circuit.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) is used to check the system clock
frequency with a reference clock signal by counting the number of pulses of the system clock
to be measured. The reference clock can be provided externally through a CACREF pin or
internally from various on-chip oscillators.
Event signals can be generated when the clock does not match or measurement ends.
This feature is particularly useful in implementing a fail-safe mechanism for home and
industrial automation applications.
See section 9, Clock Frequency Accuracy Measurement Circuit (CAC).
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module and DMAC module. The ICU also controls NMI interrupts. See section 12, Interrupt
Controller Unit (ICU).
Key interrupt function (KINT)
A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 17, Key Interrupt Function
(KINT).
Low Power Mode
Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes. See section 10, Low Power Modes.
Register Write Protection
The Register Write Protection function protects important registers from being overwritten due
to software errors. See section 11, Register Write Protection.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The
refresh-permitted period can be set to refresh the counter and used as the condition to detect
when the system runs out of control. See section 22, Watchdog Timer (WDT).
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the
timer operates with an independent, dedicated clock source, it is particularly useful in returning
the MCU to a known state as a fail safe mechanism when the system runs out of control. The
watchdog timer can be triggered automatically on reset, underflow, or refresh error, or by a
refresh of the count value in the registers. See section 23, Independent Watchdog Timer
(IWDT).
Table 1.4
Event Link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 15, Event Link Controller (ELC).
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when
activated by an interrupt request. See section 14, Data Transfer Controller (DTC).
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Table 1.6
1. Overview
Timers
Feature
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with 1 channel and a 16-bit timer with 6
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or
the up- and down-counter. In addition, PWM waveforms for controlling brushless DC motors
can be generated. The GPT can also be used as a general-purpose timer. See section 19,
General PWM Timer (GPT).
Port Output Enable for GPT (POEG)
Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 18, Port Output Enable for GPT (POEG).
Asynchronous General Purpose
Timer (AGT)
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
output, external pulse width or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and they can be accessed with the AGT
register. See section 20, Asynchronous General Purpose Timer (AGT).
Realtime Clock (RTC)
The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are used by switching register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 21, Realtime Clock (RTC).
Table 1.7
Communication interfaces
Feature
Functional description
Serial Communications Interface
(SCI)
The Serial Communication Interface (SCI) is configurable to five asynchronous and
synchronous serial interfaces:
Asynchronous interfaces (UART and asynchronous communications interface adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 25, Serial Communications Interface (SCI).
I2C Bus interface (IIC)
The MCU has a two-channel I2C bus interface (IIC).
The IIC module conforms with and provides a subset of the NXP I2C bus (Inter-Integrated
Circuit bus) interface functions. See section 26, I2C Bus Interface (IIC).
Serial Peripheral Interface (SPI)
The MCU includes two independent channels of the Serial Peripheral Interface (SPI). The SPI
channels are capable of high-speed, full-duplex synchronous serial communications with
multiple processors and peripheral devices. See section 28, Serial Peripheral Interface (SPI).
Controller Area Network (CAN)
Module
The Controller Area Network (CAN) module provides functionality to receive and transmit data
using a message-based protocol between multiple slaves and masters in electromagnetically
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 27, Controller Area Network (CAN) Module.
USB 2.0 Full-Speed Module (USBFS)
The MCU incorporates a USB 2.0 Full-Speed module (USBFS). The USBFS is a USB
controller that is equipped to operate as a device controller. The module supports full-speed
and low-speed transfer as defined in the Universal Serial Bus Specification 2.0. The module
has an internal USB transceiver and supports all of the transfer types defined in the Universal
Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of 5 pipes. PIPE0 and
PIPE4 to PIPE7 can be assigned any endpoint number based on the peripheral devices used
for communication or based on the user system.
The MCU supports revision 1.2 of the battery charging specification. Because the MCU can be
powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply
3.3 V. See section 24, USB 2.0 Full-Speed Module (USBFS).
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Table 1.8
1. Overview
Analog
Feature
Functional description
14-bit A/D Converter (ADC14)
The MCU incorporates up to one unit of a 14-bit successive approximation A/D converter. Up
to 18 analog input channels are selectable. Temperature sensor output and internal reference
voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit
and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution
in generating a digital value. See section 30, 14-Bit A/D Converter (ADC14).
12-bit D/A Converter (DAC12)
The MCU includes a 12-bit D/A converter with an output amplifier. See section 31, 12-Bit D/A
Converter (DAC12).
Temperature Sensor (TSN)
The on-chip Temperature Sensor can be used to determine and monitor the die temperature
for reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC14 for conversion and can be further used by the end
application. See section 32, Temperature Sensor (TSN).
Low-Power Analog Comparator
(ACMPLP)
Analog comparators can be used to compare a reference input voltage and analog input
voltage. The comparison result can be read by software and also be output externally. The
reference input voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin or
from the internal reference voltage (Vref) generated internally in the MCU.
The ACMPLP response speed can be set before starting an operation. Setting high-speed
mode decreases the response delay time, but increases current consumption. Setting lowspeed mode increases the response delay time, but decreases current consumption. See
section 33, Low-Power Analog Comparator (ACMPLP).
Table 1.9
Human machine interfaces
Feature
Functional description
Capacitive Touch Sensing Unit
(CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed with an electrical insulator so that a finger does
not come into direct contact with the electrode. See section 34, Capacitive Touch Sensing Unit
(CTSU).
Table 1.10
Data processing
Feature
Functional description
Cyclic Redundancy Check (CRC)
Calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB first or MSB first
communication. Additionally, various CRC generation polynomials are available. The snoop
function allows monitoring reads from and writes to specific addresses. This function is useful
in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See
section 29, Cyclic Redundancy Check (CRC) Calculator.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) is used to compare, add, and subtract 16-bit data. See
section 35, Data Operation Circuit (DOC).
Table 1.11
Security
Feature
Functional description
AES
See section 38, AES Engine
True Random Number Generator
(TRNG)
See section 39, True Random Number Generator (TRNG)
1.2
Block Diagram
Figure 1.1 shows the block diagram of the MCU superset. Individual devices within the group may have a subset of the
features.
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1. Overview
Memories
Arm Cortex-M0+
128/64 KB Code
Flash
System
Clocks
POR/LVD
4 KB Data Flash
NVIC
16 KB SRAM
System Timer
MOSC/SOSC
Reset
(H/M/L) OCO
Mode Control
DMA
Test and DBG I/F
Power Control
DTC
CAC
Interrupt
Controller Unit
KINT
Timers
Communication Interfaces
GPT32 × 1
GPT16 × 6
SCI × 3
AGT × 2
IIC × 2
RTC
SPI × 2
Register Write
Protection
Human Machine Interfaces
CTSU
CAN × 1
USBFS
with BC1.2
WDT/IWDT
Event Link
Data Processing
Analogs
ELC
CRC
ADC14
TSN
Security
DOC
DAC12
ACMPLP × 2
AES + TRNG
Figure 1.1
1.3
Block diagram
Part Numbering
Figure 1.2 shows how to read the product part number, memory capacity, and package types. Table 1.12 shows a list of
products.
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S124 User’s Manual
1. Overview
R 7 F S1 2 4 7 7 3 A 0 1 C F M # A A 1
Product identification code
Packing, terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
FM: LQFP 64 pins
FL: LQFP 48 pins
LM: LGA 36 pins
NB: QFN 64 pins
NE: QFN 48 pins
NF: QFN 40 pins
Quality ID
Software ID
Operating temperature
2: -40° C to 85° C
3: -40° C to 105° C
Code flash memory size
6: 64 KB
7: 128 KB
Feature set
7: Superset
Group name
24: S124 Group, Arm Cortex-M0+, 32 MHz
Series name
1: Ultra low power
Renesas Synergy family
Flash memory
Renesas microcontroller
Renesas
Figure 1.2
Table 1.12
Part numbering scheme
Product list
Product part number
Orderable part number
Package code
Code flash
Data flash
SRAM
128 KB
4 KB
16 KB
R7FS124773A01CFM
R7FS124773A01CFM#AA1
PLQP0064KB-C
R7FS124773A01CNB
R7FS124773A01CNB#AC1
PWQN0064LA-A
Operating
temperature
–40 to +105°C
–40 to +105°C
R7FS124773A01CFL
R7FS124773A01CFL#AA1
PLQP0048KB-B
–40 to +105°C
R7FS124773A01CNE
R7FS124773A01CNE#AC1
PWQN0048KB-A
–40 to +105°C
R7FS124773A01CNF
R7FS124773A01CNF#AC1
PWQN0040KC-A
–40 to +105°C
R7FS124772A01CLM
R7FS124772A01CLM#AC1
PWLG0036KA-A
R7FS124763A01CFM
R7FS124763A01CFM#AA1
PLQP0064KB-C
R7FS124763A01CFL
R7FS124763A01CFL#AA1
PLQP0048KB-B
–40 to +105°C
R7FS124762A01CLM
R7FS124762A01CLM#AC1
PWLG0036KA-A
–40 to +85°C
Note:
–40 to +85°C
64 KB
–40 to +105°C
Earlier products with orderable part number suffix AA0 and AC0 have a restriction in AES functions. If AES
functions are required for your application, refer to the products with orderable part number suffix AA1 or AC1.
For details on the differences of AES functions between AA0/AC0 and AA1/AC1 products, see Technical Update
(TN-SY*-A024A/E). Contact your Renesas sales representative for additional information.
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1.4
1. Overview
Function Comparison
Table 1.13
Function comparison
R7FS124773A01CFM/
R7FS124763A01CFM/
R7FS124773A01CNB/
Parts number
R7FS124773A01CFL/
R7FS124763A01CFL/
R7FS124773A01CNE
Pin count
64
48
Package
LQFP/QFN
LQFP/QFN
R7FS124773A01CNF
Code flash memory
128/64 KB
Data flash memory
4 KB
SRAM
CPU clock
KINT
5
ELC
Yes
DTC
Yes
Timers
GPT32
5
4
1
GPT16
6
6
4
4
AGT
2
2
2
2
12
11
RTC
Yes
WDT/IWDT
Yes
SCI
3
IIC
2
SPI
2
CAN
Yes
USBFS
ADC14
Yes
18
14
DAC12
1
ACMPLP
2
TSN
Data processing
LGA
Yes
8
DMA
HMI
QFN
32 MHz
Event link
Analog
36
4 KB
ICU
Communication
40
16 KB
Parity
System
R7FS124772A01CLM/
R7FS124762A01CLM
Yes
CTSU
31
23
17
13
KINT
8
5
5
4
CRC
DOC
Security
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Yes
Yes
AES and TRNG
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1.5
1. Overview
Pin Functions
Table 1.14
Pin functions (1 of 3)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply. Connect this pin
to VSS by a 0.1-μF capacitor. The capacitor should be placed close to the
pin.
VCL
Input
Connect this pin to the VSS pin by the smoothing capacitor used to stabilize
the internal power supply. Place the capacitor close to the pin.
Clock
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input through
the EXTAL pin.
XCIN
Input
XCOUT
Output
Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
CLKOUT
Output
Clock output pin.
Operating mode control
MD
Input
Pins for setting the operating mode. The signal levels on these pins must
not be changed during operation mode transition at the time of release from
the reset state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this signal
goes low.
CAC
CACREF
Input
Measurement reference clock input pin.
On-chip debug
SWDIO
I/O
Serial Wire debug Data Input/Output pin.
SWCLK
Input
Serial Wire Clock pin.
NMI
Input
Non-maskable interrupt request pin.
IRQ0 to IRQ7
Input
Maskable interrupt request pins.
GTETRGA,
GTETRGB
Input
External trigger input pin.
GTIOC0A to
GTIOC6A,
GTIOC0B to
GTIOC6B
I/O
Input capture, Output Compare, or PWM output pin.
GTIU
Input
Hall sensor input pin U.
GTIV
Input
Hall sensor input pin V.
GTIW
Input
Hall sensor input pin W.
GTOUUP
Output
Three-phase PWM output for BLDC motor control (positive U phase).
Interrupt
GPT
AGT
GTOULO
Output
Three-phase PWM output for BLDC motor control (negative U phase).
GTOVUP
Output
Three-phase PWM output for BLDC motor control (positive V phase).
GTOVLO
Output
Three-phase PWM output for BLDC motor control (negative V phase).
GTOWUP
Output
Three-phase PWM output for BLDC motor control (positive W phase).
GTOWLO
Output
Three-phase PWM output for BLDC motor control (negative W phase).
AGTEE0,
AGTEE1
Input
External event input enable.
AGTIO0, AGTIO1 I/O
RTC
External event input and pulse output.
AGTO0, AGTO1
Output
Pulse output.
AGTOA0,
AGTOA1
Output
Output compare match A output.
AGTOB0,
AGTOB1
Output
Output compare match B output.
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock.
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Table 1.14
1. Overview
Pin functions (2 of 3)
Function
Signal
I/O
Description
SCI
SCK0, SCK1,
SCK9
I/O
Input/output pins for the clock (clock synchronous mode).
RXD0, RXD1,
RXD9
Input
Input pins for received data (asynchronous mode/clock synchronous
mode).
TXD0, TXD1,
TXD9
Output
Output pins for transmitted data (asynchronous mode/clock synchronous
mode).
CTS0_RTS0,
CTS1_RTS1,
CTS9_RTS9
I/O
Input/Output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active-low.
SCL0, SCL1,
SCL9
I/O
Input/output pins for the IIC clock (simple IIC).
SDA0, SDA1,
SDA9
I/O
Input/output pins for the IIC data (simple IIC).
SCK0, SCK1,
SCK9
I/O
Input/output pins for the clock (simple SPI).
MISO0, MISO1,
MISO9
I/O
Input/output pins for slave transmission of data (simple SPI).
MOSI0, MOSI1,
MOSI9
I/O
Input/output pins for master transmission of data (simple SPI).
SS0, SS1, SS9
Input
Chip-select input pins (simple SPI), active-low.
IIC
SPI
CAN
USBFS
Analog power supply
ADC14
DAC12
SCL0, SCL1
I/O
Input/output pins for clock.
SDA0, SDA1
I/O
Input/output pins for data.
RSPCKA,
RSPCKB
I/O
Clock input/output pin.
MOSIA, MOSIB
I/O
Inputs or outputs data output from the master.
MISOA, MISOB
I/O
Inputs or outputs data output from the slave.
SSLA0, SSLB0
I/O
Input or output pin for slave selection.
SSLA1 to SSLA3,
SSLB1 to SSLB3
Output
Output pin for slave selection.
CRX0
Input
Receive data.
CTX0
Output
Transmit data.
VSS_USB
Input
Ground pins.
VCC_USB_LDO
Input
Power supply pin for USB LDO regulator.
VCC_USB
I/O
Input: Power supply pin for USB transceiver.
Output: USB LDO regulator output pin. This pin should be connected to an
external capacitor.
USB_DP
I/O
D+ I/O pin of the USB on-chip transceiver. This pin should be connected to
the D+ pin of the USB bus.
USB_DM
I/O
D– I/O pin of the USB on-chip transceiver. This pin should be connected to
the D– pin of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin. This pin should be connected to VBUS
of the USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a function controller.
AVCC0
Input
Analog block power supply pin
AVSS0
Input
Analog block power supply ground pin
VREFH0
Input
Reference power supply pin
VREFL0
Input
Reference power supply ground pin
AN000 to AN010,
AN016 to AN022
Input
Input pins for the analog signals to be processed by the A/D converter.
ADTRG0
Input
Input pins for the external trigger signals that start the A/D conversion,
active-low.
DA0
Output
Output pins for the analog signals to be processed by the D/A converter.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 49 of 1104
S124 User’s Manual
Table 1.14
1. Overview
Pin functions (3 of 3)
Function
Signal
I/O
Description
ACMPLP
VCOUT
Output
Comparator output pin.
CMPREF0,
CMPREF1
Input
Reference voltage input pins.
CMPIN0,
CMPIN1
Input
Analog voltage input pins.
TS00 to TS28,
TS30, TS31
Input
Capacitive touch detection pins (touch pins).
TSCAP
-
Secondary power supply pin for the touch driver.
KINT
KR00 to KR07
Input
Key interrupt input pins.
I/O ports
P000 to P004,
P010 to P015
I/O
General-purpose input/output pins.
P100 to P113
I/O
General-purpose input/output pins.
P200
Input
General-purpose input pin.
P201, P204 to
P206, P212,
P213
I/O
General-purpose input/output pins.
P214, P215
Input
General-purpose input pins.
P300 to P304
I/O
General-purpose input/output pins.
P400 to P403,
P407 to P411
I/O
General-purpose input/output pins.
P500 to P502
I/O
General-purpose input/output pins.
CTSU
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 50 of 1104
S124 User’s Manual
1.6
1. Overview
Pin Assignments
Figure 1.3
P100
P101
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110
P109
P108/SWDIO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Figure 1.3 to Figure 1.8 show the pin assignments.
P500
49
32
P300/SWCLK
P501
50
31
P301
P502
51
30
P302
P015
52
29
P303
P014
53
28
P304
P013
54
27
P200
P012
55
26
P201/MD
AVCC0
56
25
RES
AVSS0
57
24
P204
P011/VREFL0
58
23
P205
P010/VREFH0
59
22
P206
P004
60
21
VCC_USB_LDO
P003
61
20
VCC_USB
P002
62
19
USB_DP
P001
63
18
USB_DM
P000
64
17
VSS_USB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P400
P401
P402
P403
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
R7FS1247x3A01CFM
Pin assignment for LQFP 64-pin (top view)
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 51 of 1104
33
34
35
36
37
38
39
40
41
42
43
44
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110
P109
P108/SWDIO
45
46
47
P100
P101
1. Overview
48
S124 User’s Manual
P500
P501
P502
P015
P014
P013
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P004
P003
P002
P001
49
32
50
31
58
23
59
22
60
21
61
20
62
19
63
18
P300/SWCLK
P301
P302
P303
P304
P200
P201/MD
RES
P204
P205
P206
VCC_USB_LDO
VCC_USB
USB_DP
USB_DM
51
30
52
29
53
28
54
27
55
26
P000
64
17
VSS_USB
24
16
15
14
13
12
11
10
9
8
7
6
5
4
3
25
P400
P401
P402
P403
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
1
57
2
R7FS1247x3A01CNB
56
Figure 1.4
Pin assignment for QFN 64-pin (top view)
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 52 of 1104
P100
P101
P102
P103
P104
VSS
VCC
P112
P111
P110
P109
P108/SWDIO
35
34
33
32
31
30
29
28
27
26
25
1. Overview
36
S124 User’s Manual
P500
37
24
P300/SWCLK
P015
38
23
P301
P014
39
22
P302
P013
40
21
P200
P012
41
20
P201/MD
AVCC0
42
19
RES
AVSS0
43
18
P206
P011/VREFL0
44
17
VCC_USB_LDO
P010/VREFH0
45
16
VCC_USB
P002
46
15
USB_DP
P001
47
14
USB_DM
P000
48
13
VSS_USB
12
P408
P407
10
11
VCC
P409
7
P213/XTAL
9
6
VSS
8
5
P214/XCOUT
P212/EXTAL
4
P215/XCIN
3
VCL
P400
2
25
26
27
28
29
30
31
32
33
P102
P103
P104
VSS
VCC
P112
P111
P110
P109
P108/SWDIO
34
35
P100
P101
36
Pin assignment for LQFP 48-pin (top view)
P500
P015
P014
P013
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P002
P001
37
24
38
23
44
17
45
16
46
15
47
14
P300/SWCLK
P301
P302
P200
P201/MD
RES
P206
VCC_USB_LDO
VCC_USB
USB_DP
USB_DM
39
22
40
21
41
20
P000
48
13
VSS_USB
18
12
11
10
9
8
7
6
5
19
P400
P401
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P409
P408
P407
4
R7FS1247x3A01CNE
3
43
2
42
1
Figure 1.5
P401
1
R7FS1247x3A01CFL
Figure 1.6
Pin assignment for QFN 48-pin (top view)
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 53 of 1104
21
22
23
24
25
26
P102
P103
P104
P112
P111
P110
P109
P108/SWDIO
27
28
29
P100
P101
1. Overview
30
S124 User’s Manual
P015
P014
P013
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P001
31
20
32
19
37
14
38
13
39
12
P300/SWCLK
P301
P200
P201/MD
RES
VCC_USB_LDO
VCC_USB
USB_DP
USB_DM
33
18
34
17
P000
40
11
VSS_USB
35
16
10
9
8
7
6
5
4
3
1
15
P400
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P408
P407
2
R7FS1247x3A01CNF
36
Figure 1.7
Pin assignment for QFN 40-pin (top view)
R7FS1247x2A01CLM
Figure 1.8
A
B
6
P015
P100
5
P014
4
C
D
E
F
P112
P111
P108
/SWDIO
P300
/SWCLK
6
P013
P101
P110
P200
VCC_USB
_LDO
5
AVCC0
P012
P102
P109
P201/MD VCC_USB
4
3
AVSS0
P011
/VREFL0
P103
P213
/XTAL
RES
USB_DP
3
2
P010
/VREFH0
P000
P400
P212
/EXTAL
P407
USB_DM
2
1
VCL
P215
/XCIN
P214
/XCOUT
VSS
VCC
VSS_USB
1
A
B
D
E
F
C
Pin assignment for LGA 36-pin (top view, pad side down)
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 54 of 1104
S124 User’s Manual
Pin Lists
-
-
P402
4
-
-
-
-
P403
5
3
3
2
A1
6
4
4
3
B1
XCIN
P215
7
5
5
4
C1
XCOUT
P214
8
6
6
5
D1
VSS
9
7
7
6
D3
XTAL
P213
10
8
8
7
D2
EXTAL
P212
AGTEE1
VCC
Interrupt
-
SCK0_B/
SCK1_B
SCL0_A
TS20
IRQ0
CTX0_B CTS0_RT SDA0_A
S0_B/
SS0_B/
TXD1_B/
MOSI1_B/
SDA1_B
TS19
IRQ5
CRX0_B
RXD1_B/
MISO1_B/
SCL1_B
TS18
IRQ4
CTS1_RT
S1_B/
SS1_B
TS17
GTIOC6A
_A
GTETRG GTIOC6B
A_B
_A
CTSU
-
AGTIO1_
D
DAC12, ACMPLP
3
P400
ADC14
P401
CACREF_
C
GTIOC3A
_B
SPI
-
HMI
IIC
C2
-
Analogs
SCI
1
USBFS,CAN
1
2
Communication Interfaces
RTC
1
2
GPT_OPS, POEG
1
2
AGT
LGA36
I/O ports
QFN40
Power, System,
Clock, Debug,
CAC
Timers
QFN48
LQFP48
LQFP64, QFN64
Pin number
GPT
1.7
1. Overview
VCL
GTETRG
A_D
TXD1_A/
MOSI1_A/
SDA1_A
IRQ2
GTETRG
B_D
RXD1_A/
MISO1_A/
SCL1_A
IRQ3
11
9
9
8
E1
12
-
-
-
-
P411
AGTOA1 GTOVUP GTIOC6A
_B
_B
TXD0_B/
MOSI0_B/
SDA0_B
MOSIA_B
TS07
IRQ4
13
-
-
-
-
P410
AGTOB1 GTOVLO GTIOC6B
_B
_B
RXD0_B/
MISO0_B/
SCL0_B
MISOA_B
TS06
IRQ5
14
10
10
-
-
P409
GTOWUP GTIOC5A
_B
_B
TXD9_A/
MOSI9_A/
SDA9_A
TS05
IRQ6
15
11
11
9
-
P408
GTOWLO GTIOC5B
_B
_B
RXD9_A/
MISO9_A/
SCL9_A
TS04
IRQ7
16
12
12
10
E2
P407
17
13
13
11
F1
18
14
14
12
F2
19
15
15
13
F3
20
16
16
14
F4
VCC_US
B
VCC_US
B_LDO
RTCOUT USB_VBU CTS0_RT SDA0_B
S
S0_D/
SS0_D
SSLB3_A ADTRG0_
B
TS03
RXD0_D/ SDA1_A
MISO0_D/
SCL0_D
SSLB1_A
TS01
IRQ0
TXD0_D/ SCL1_A
MOSI0_D/
SDA0_D/
CTS9_RT
S9_A/
SS9_A
SSLB0_A
TSCAP_A
IRQ1
VSS_USB
USB_DM
USB_DP
21
17
17
15
F5
22
18
18
-
-
23
-
-
-
-
CLKOUT_
A
P205
AGTO1
24
-
-
-
-
CACREF_
A
P204
AGTIO1_
A
25
19
19
16
E3
RES
26
20
20
17
E4
MD
27
21
21
18
E5
P200
28
-
-
-
-
P304
GTIOC1A
_B
29
-
-
-
-
P303
GTIOC1B
_B
P206
GTIU_A
GTIV_A
GTIOC4A
_B
GTIW_A GTIOC4B
_B
SCK0_D/
SCK9_A
SCL0_B RSPCKB_
A
TS00
P201
NMI
TS02
30
22
22
-
-
P302
GTOUUP GTIOC4A
_A
_A
SSLB3_B
TS08
IRQ5
31
23
23
19
-
P301
GTOULO GTIOC4B
_A
_A
SSLB2_B
TS09
IRQ6
32
24
24
20
F6
SWCLK
P300
GTOUUP GTIOC0A
_C
_A
SSLB1_B
33
25
25
21
E6
SWDIO
P108
GTOULO GTIOC0B
_C
_A
34
26
26
22
D4
CLKOUT_
B
P109
GTOVUP GTIOC1A
_A
_A
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
CTX0_A
CTS9_RT
S9_B/
SS9_B
SSLB0_B
TXD9_B/
MOSI9_B/
SDA9_B
MOSIB_B
TS10
Page 55 of 1104
S124 User’s Manual
1. Overview
MISOB_B
RSPCKB_
B
36
28
28
24
D6
P111
GTIOC3A
_A
SCK0_C/
SCK9_B
37
29
29
25
C6
P112
GTIOC3B
_A
TXD0_C/
MOSI0_C/
SDA0_C
38
-
-
-
-
P113
39
30
30
-
-
VCC
40
31
31
-
-
VSS
41
-
-
-
-
P107
Interrupt
CRX0_A CTS0_RT
S0_C/
SS0_C/
RXD9_B/
MISO9_B/
SCL9_B
HMI
CTSU
GTOVLO GTIOC1B
_A
_A
ADC14
SPI
IIC
USBFS,CAN
Analogs
DAC12, ACMPLP
P110
RTC
D5
Communication Interfaces
GPT
LGA36
23
GPT_OPS, POEG
QFN40
27
AGT
QFN48
27
I/O ports
LQFP48
35
Power, System,
Clock, Debug,
CAC
LQFP64, QFN64
Timers
SCI
Pin number
VCOUT
TS11
IRQ3
TS12
IRQ4
TSCAP_C
GTIOC0A
_B
42
-
-
-
-
P106
43
-
-
-
-
P105
GTETRG
A_C
44
32
32
26
-
P104
GTETRG
B_B
45
33
33
27
C3
P103
46
34
34
28
C4
P102
47
35
35
29
C5
48
36
36
30
49
37
37
50
-
-
KR07
GTIOC0B
_B
SSLA3_A
KR06
SSLA2_A
KR05/
IRQ0
RXD0_C/
MISO0_C/
SCL0_C
SSLA1_A
GTOWUP GTIOC2A
_A
_A
CTX0_C CTS0_RT
S0_A/
SS0_A
SSLA0_A
AGTO0
GTOWLO GTIOC2B
_A
_A
CRX0_C
P101
AGTEE0
GTETRG GTIOC5A
B_A
_A
TXD0_A/ SDA1_B MOSIA_A
MOSI0_A/
SDA0_A/
CTS1_RT
S1_A/
SS1_A
AN021
B6
P100
AGTIO0_ GTETRG GTIOC5B
A
A_A
_A
RXD0_A/ SCL1_B MISOA_A
MISO0_A/
SCL0_A/
SCK1_A
AN022
-
-
P500
AGTOA0
GTIU_B
GTIOC2A
_B
AN016
-
-
P501
AGTOB0
GTIV_B
GTIOC2B
_B
AN017
GTIW_B GTIOC3B
_B
AN018
SCK0_A
TS13
KR04/
IRQ1
CMPREF
1
TS14
KR03
RSPCKA_ AN020/
CMPIN1
A
ADTRG0_
A
TS15
KR02
CMPREF
0
TS16
KR01/
IRQ1
CMPIN0
TS26
KR00/
IRQ2
AN019
51
-
-
-
-
P502
52
38
38
31
A6
P015
AN010
53
39
39
32
A5
P014
AN009
54
40
40
33
B5
P013
AN008
55
41
41
34
B4
P012
AN007
56
42
42
35
A4
TS27
TS28
IRQ7
DA0
AVCC0
57
43
43
36
A3
AVSS0
58
44
44
37
B3
VREFL0
P011
AN006
TS31
59
45
45
38
A2
VREFH0
P010
AN005
TS30
60
-
-
-
-
P004
AN004
TS25
61
-
-
-
-
P003
AN003
TS24
62
46
46
-
-
P002
AN002
TS23
IRQ2
63
47
47
39
-
P001
AN001
TS22
IRQ7
64
48
48
40
B2
P000
AN000
TS21
IRQ6
Note:
IRQ3
Several pin names have the added suffix of _A, _B, _C, and _D. The suffix can be ignored when assigning
functionality.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 56 of 1104
S124 User’s Manual
2.
2. CPU
CPU
The MCU is based on the Arm® Cortex®-M0+ core.
2.1
Overview
2.1.1
CPU
Arm Cortex-M0+
Revision: r0p1-00rel0
Armv6-M architecture profile
Single-cycle integer multiplier.
SysTick timer
Driven by SYSTICCLK (LOCO) or ICLK.
See reference 1. and reference 2. in section 2.9 for details.
2.1.2
Debug
CoreSight™ MTB-M0+
Revision: r0p1-00rel0
Buffer size: 1 KB of 16-KB MTB SRAM.
Data Watchpoint Unit (DWT)
2 comparators for watchpoints.
Breakpoint Unit (BPU)
4 instruction comparators.
CoreSight Debug Access Port (DAP)
Serial Wire-Debug Port (SW-DP).
Debug Register Module (DBGREG)
Reset control
Halt control.
See reference 1. and reference 2. in section 2.9 for details.
2.1.3
Operating Frequency
CPU: maximum 32 MHz
Serial Wire Data (SWD) interface: maximum 12.5 MHz.
Figure 2.1 shows the block diagrams of the Cortex-M0+ core.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 57 of 1104
S124 User’s Manual
2. CPU
OCD Access
Trace/Debug Data
From: OCD Emulator (SWD)
From: System bus
Cortex-M0+ Integration
SWJ-DP
Cortex-M0+
CM0+ core
DAP IC
NVIC
APB-AP
DWT
MTB
SRAM
DBGREG
OCDREG
DBG I/F
BPU
To: System control
ROM Table
Bus Matrix
To: System bus
Figure 2.1
2.2
Cortex-M0+ block diagram
MCU Implementation Options
Table 2.1 shows the implementation options for the MCU and is based on the configurable options in reference 2.
Table 2.1
Implementation and configurable options (1 of 2)
Option
Implementation
Interrupts
32 external interrupts
Data endianness
Little-endian
SysTick timer
Included
SYST_CALIB = 4000 0147h
Bit[31] = 0
Reference clock provided
Bit[30] = 1
TERMS value is inexact
Bits[29:24] = 00h
Reserved
Bits[23:0] = 000147h TERM: (32768 × 10ms) - 1 / 32.768 kHz
= 326.66 decimal
= 327 with skew
= 000147h
Number of watchpoint comparators
2
Number of breakpoint comparators
4
Halting debug support
Not implemented
Multiplier
Fast
Single-cycle I/O port
Not included
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 58 of 1104
S124 User’s Manual
Table 2.1
2. CPU
Implementation and configurable options (2 of 2)
Option
Implementation
Wakeup interrupt controller
Not implemented
ICU can wake up CPU instead of WIC. See section 12, Interrupt Controller Unit (ICU) for
details.
Vector Table Offset Register
Implemented
Unprivileged/Privileged support
Implemented
Memory Protection Unit
Not included
Reset all registers
Not implemented
Instruction fetch width
Mostly 32-bit
MTB
Included
Debug port
Serial wire
Sleep mode power-saving
Sleep mode and other low power modes are implemented. See section 10, Low Power Modes
for details.
Note:
SCB.SCR.SLEEPDEEP bit is ignored.
Memory features
No memory attribute is used in the MCU
Event input/output
Not implemented
System reset request output
SYSRESETREQ bit in the Application Interrupt and Reset Control Register causes CPU reset
Auxiliary fault input, AUXFAULT
Not implemented
See reference 3. in section 2.9 for details.
2.3
Trace Interface
The MCU does not provide a dedicated trace output interface.
2.4
SWD Interface
Table 2.2 shows the SWD chip pins.
Table 2.2
SWD pins
Name
I/O
P/N
Width
Function
When not in use
SWCLK
Input
Pos.
1 bit
Serial Wire Data Clock Pin
Pull-up
SWDIO
I/O
Neg.
1 bit
Serial Wire Data I/O Pin
Pull-up
2.5
Debug Mode
2.5.1
Debug Mode Definition
In single chip mode, the debugger state of connection is defined as OCD mode, and the debugger state of non-connection
is defined as User mode.
Table 2.3 shows the CPU debug modes and conditions.
Table 2.3
CPU debug mode and conditions
Conditions
Mode
OCD connect
SWD authentication
Debug mode
Debug authentication
Not connected
—
User mode
Disabled
Connected
Failed
User mode
Disabled
Connected
Passed
OCD mode
Enabled
Note 1. OCD connect is determined by the CDBGPWRUPREQ bit output in the SWJ-DP register. The bit can only be
written by the OCD. However, the level of the bit can be confirmed by reading the DBGSTR.CDBGPWRUPREQ
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2. CPU
bit.
Note 2. Debug Authentication is defined by the Armv6-M Architecture. Enabled means that both invasive and noninvasive CPU debugging are permitted. Disabled means that both are not permitted.
2.5.2
Debug Mode Effects
This section describes the effects of debug mode, which occur both internally and externally to the CPU.
2.5.2.1
Low power mode
All CoreSight debug components can store the register settings even when the CPU enters Software Standby mode or
Snooze mode. However, AHB-AP cannot respond to On-Chip Debug (OCD) access in these low power modes. The
OCD must wait for cancellation of the low power mode to access the CoreSight debug components. To request low
power mode cancellation, the OCD can set the DBIRQ bit in the MCUCTRL register. For details, see section 2.6.6.3,
MCU Control Register (MCUCTRL).
2.5.2.2
Reset
In OCD mode, some resets depend on the CPU status and the DBGSTOPCR setting.
Table 2.4
Reset or interrupt and mode setting
Control in On-Chip Debug (OCD) mode
Reset or interrupt name
OCD break mode
RES pin reset
Same as user mode
OCD run mode
Power-on reset
Same as user mode
Independent Watchdog Timer reset/interrupt
Does not occur*1
Depends on DBGSTOPCR setting*2
Watchdog Timer reset/interrupt
Does not occur*1
Depends on DBGSTOPCR setting*2
Voltage monitor 0 reset
Depends on DBGSTOPCR setting*3
Voltage monitor 1 reset/interrupt
Depends on DBGSTOPCR setting*3
Voltage monitor 2 reset/interrupt
Depends on DBGSTOPCR setting*3
SRAM parity error reset/interrupt
Depends on DBGSTOPCR setting*3
Software reset
Same as user mode
Note:
Note 1.
Note 2.
Note 3.
2.6
2.6.1
In OCD break mode, the CPU is halted. In OCD run mode, the CPU is in OCD mode and the CPU is not halted.
The IWDT and WDT always stop in this mode.
The IWDT and WDT operation depends on the DBGSTOPCR setting.
The reset or interrupt masking depends on the DBGSTOPCR setting.
Programmers Model
Address Spaces
The MCU debug system has two CoreSight Access Ports (AP):
AHB-AP, which is connected to the CPU bus matrix and has the same access to the system address space as the
CPU
APB-AP, which has a dedicated address space (OCD address space) and is connected to the OCD register.
Figure 2.2 shows the block diagram of the AP connection and address spaces.
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SWD
Port 0
SWJ-DP
System address space
AHB-AP
DBGREG
DAP
IC
Port 1
OCD address space
APB-AP
OCDREG
Figure 2.2
SWD authentication block diagram
For debugging purpose, there are two register modules, DBGREG and OCDREG. DBGREG is located in the system
address space and can be accessed from the OCD emulator, the CPU, and other bus masters in the MCU. OCDREG is
located in the OCD address space and can only be accessed from the OCD tool. The CPU and other bus masters cannot
access the OCD registers.
2.6.2
Cortex-M0+ Peripheral Address Map
In the system address space, the Cortex-M0+ core has a Private Peripheral Bus (PPB) that can only be accessed from the
CPU and OCD emulator. Table 2.5 shows the address map of the MCU.
Table 2.5
Cortex-M0+ peripheral address map
Component name
Start address
End address
Note
DWT
E000 1000h
E000 1FFFh
See reference 2.
BPU
E000 2000h
E000 2FFFh
See reference 2.
SCS
E000 E000h
E000 EFFFh
See reference 2.
ROM Table
E00F F000h
E00F FFFFh
See section 2.6.4, CoreSight ROM Table and
reference 5.
2.6.3
External Debug Address Map
In the system address space, the Cortex-M0+ core has external debug components. These components can be accessed
from the CPU and other bus masters through the system bus. Table 2.6 shows the address map of the Cortex-M0+
external debug components.
Table 2.6
External debug address map
Component name
Start address
End address
Note
MTB (SRAM area)
2000 0000h
2000 3FFFh
MTB uses 1 KB of 16 KB as trace buffer
See reference 6.
MTB (SFR area)
4001 9000h
4001 9FFFh
See reference 6.
ROM table
4001 A000h
4001 AFFFh
See reference 6.
2.6.4
CoreSight ROM Table
The MCU contains two CoreSight ROM Tables. One ROM Table is the root that contains a list of external debug
components and a pointer to Arm components. The other ROM Table contains a list of Arm components.
2.6.4.1
ROM entries
Table 2.7 shows the first ROM Table that contains a pointer to the Arm system area and the user area component
information. Table 2.8 shows the second ROM Table that contains Arm system area component information. See
reference 5. and reference 6. for details.
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Table 2.7
2. CPU
ROM Table 1
#
Address
Access size
R/W
Value
Target module pointer
0
4001 A000h
32 bits
R
A00E5003h
Arm Cortex-M0+
Processor
1
4001 A004h
32 bits
R
FFFFF003h
MTB
2
4001 A008h
32 bits
R
00000000h
(End of entries)
Table 2.8
ROM Table 2
#
Address
Access size
R/W
Value
Target module pointer
0
E00F F000h
32 bits
R
FFF0F003h
SCS
1
E00F F004h
32 bits
R
FFF02003h
DWT
2
E00F F008h
32 bits
R
FFF03003h
BPU
3
E00F F00Ch
32 bits
R
00000000h
(End of entries)
2.6.4.2
CoreSight component registers
The CoreSight ROM Table lists the CoreSight component registers defined in the Arm CoreSight architecture. Table 2.9
shows the registers. See reference 5. for details of each register.
Table 2.9
CoreSight component registers in the CoreSight ROM Table
Name
Address
Access size
R/W
Initial value
DEVTYPE
E00F FFCCh
32 bit
R
00000001h
PID4
E00F FFD0h
32 bit
R
00000004h
PID5
E00F FFD4h
32 bit
R
00000000h
PID6
E00F FFD8h
32 bit
R
00000000h
PID7
E00F FFDCh
32 bit
R
00000000h
PID0
E00F FFE0h
32 bit
R
00000003h
PID1
E00F FFE4h
32 bit
R
00000030h
PID2
E00F FFE8h
32 bit
R
0000000Ah
PID3
E00F FFECh
32 bit
R
00000000h
CID0
E00F FFF0h
32 bit
R
0000000Dh
CID1
E00F FFF4h
32 bit
R
00000010h
CID2
E00F FFF8h
32 bit
R
00000005h
CID3
E00F FFFCh
32 bit
R
000000B1h
2.6.5
DBGREG Module
The DBGREG module controls the debug functionalities and is implemented as a CoreSight-compliant component.
Table 2.10 lists the DBGREG registers other than the CoreSight component registers.
Table 2.10
Non-CoreSight DBGREG registers
Name
DAP port
Address
Access size
R/W
Debug Status Register
DBGSTR
Port 0
4001 B000h
32 bits
R
Debug Stop Control Register
DBGSTOPCR
Port 0
4001 B010h
32 bits
R/W
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2. CPU
Debug Status Register (DBGSTR)
Address(es): DBG.DBGSTR 4001 B000h
b31
b30
b29
b28
CDBGPW CDBGPW
RUPACK RUPREQ
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b27 to b0
—
Reserved
These bits are read as 0
R
b28
CDBGPWRUPREQ
Debug power-up
request
0: OCD is not requesting debug power up
1: OCD is requesting debug power up.
R
b29
CDBGPWRUPACK
Debug power-up
acknowledge
0: Debug power-up request is not acknowledged
1: Debug power-up request is acknowledged.
R
b31, b30
—
Reserved
These bits are read as 0
R
2.6.5.2
Debug Stop Control Register (DBGSTOPCR)
Address(es): DBG.DBGSTOPCR 4001 B010h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
—
—
—
—
—
b18
b17
b16
—
—
—
—
—
—
—
DBGSTO
P_RPER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
DBGSTOP_LVD[2:0]
DBGSTO DBGSTO
P_WDT P_IWDT
1
1
Bit
Symbol
Bit name
Description
R/W
b0
DBGSTOP_IWDT
Mask bit for IWDT reset/
interrupt
0: Enable IWDT reset/interrupt
1: Mask IWDT reset/interrupt and stop WDT count when
CPU is in OCD break mode.
R/W
b1
DBGSTOP_WDT
Mask bit for WDT reset/
interrupt
0: Enable WDT reset/interrupt
1: Mask WDT reset/interrupt and stop WDT count when
CPU is in OCD break mode.
R/W
b15 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
DBGSTOP_LVD[2:0]
Mask bit for LVD0 reset
0: Enable LVD0 reset
1: Mask LVD0 reset.
R/W
b17
Mask bit for LVD1 reset/
interrupt
0: Enable LVD1 reset/interrupt
1: Mask LVD1 reset/interrupt.
R/W
b18
Mask bit for LVD2 reset/
interrupt
0: Enable LVD2 reset/interrupt
1: Mask LVD2 reset/interrupt.
R/W
b23 to b19
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b24
DBGSTOP_RPER
Mask bit for SRAM parity
error reset/interrupt
0: Enable SRAM parity error reset/interrupt
1: Mask SRAM parity error reset/interrupt.
R/W
b31 to b25
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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The Debug Stop Control Register (DBGSTOPCR) specifies the functional stop in OCD mode. All bits in the register are
regarded as 0 when the chip is not in OCD mode.
2.6.5.3
DBGREG CoreSight component registers
The DBGREG module provides the CoreSight component registers defined in the Arm CoreSight architecture. Table
2.11 lists these registers. See reference 5. in section 2.9 for details of each register.
Table 2.11
DBGREG CoreSight component registers
Name
Address
Access size
R/W
Initial value
PID4
4001 BFD0h
32 bits
R
00000004h
PID5
4001 BFD4h
32 bits
R
00000000h
PID6
4001 BFD8h
32 bits
R
00000000h
PID7
4001 BFDCh
32 bits
R
00000000h
PID0
4001 BFE0h
32 bits
R
00000005h
PID1
4001 BFE4h
32 bits
R
00000030h
PID2
4001 BFE8h
32 bits
R
0000001Ah
PID3
4001 BFECh
32 bits
R
00000000h
CID0
4001 BFF0h
32 bits
R
0000000Dh
CID1
4001 BFF4h
32 bits
R
000000F0h
CID2
4001 BFF8h
32 bits
R
00000005h
CID3
4001 BFFCh
32 bits
R
000000B1h
2.6.6
OCDREG Module
The OCDREG module controls the On-Chip Debug (OCD) Emulator functionalities. OCDREG is implemented as a
CoreSight-compliant component.
Table 2.12 lists the OCDREG registers other than the CoreSight component registers.
Table 2.12
Non-CoreSight OCDREG registers
Name
DAP port
Address
Access size
R/W
ID Authentication Code Register 0
IAUTH0
Port 1
8000 0000h
32 bits
W
ID Authentication Code Register 1
IAUTH1
Port 1
8000 0100h
32 bits
W
ID Authentication Code Register 2
IAUTH2
Port 1
8000 0200h
32 bits
W
ID Authentication Code Register 3
IAUTH3
Port 1
8000 0300h
32 bits
W
MCU Status Register
MCUSTAT
Port 1
8000 0400h
32 bits
R
MCU Control Register
MCUCTRL
Port 1
8000 0410h
32 bits
R/W
Note:
OCDREG is located in dedicated OCD address space. This address map is independent from the system
address map.
2.6.6.1
ID Authentication Code Register (IAUTH0 to 3)
Four authentication registers are provided for writing the 128-bit key. These registers must be written in sequential order
from IAUTH0 to IAUTH3. If the set of register writes is not compliant with this order, the result is unpredictable.
Only 32-bit writes are permitted. The initial value of the registers is all 1s. This means that SWD access is initially
permitted when ID code in the OSIS register has the initial value. See section 2.8.2, Unlock ID Code.
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Address(es): IAUTH0 8000 0000h
b31
b0
IAUTH0: AID 31-0 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH1 8000 0100h
b31
b0
IAUTH1: AID 63-32 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH2 8000 0200h
b31
b0
IAUTH2: AID 95-64 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): IAUTH3 8000 0300h
b31
b0
IAUTH3: AID 127-96 bits
Value after reset: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.6.6.2
MCU Status Register (MCUSTAT)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address(es): MCUSTAT 8000 0400h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
b0
Bit name
CPUST CPUSL AUTH
OPCLK EEP
1/0*1
1/0*1
0
Description
R/W
AUTH
0: Authentication failed
1: Authentication succeeded.
R
b1
CPUSLEEP
0: CPU is not in Sleep mode
1: CPU in Sleep mode.
R
b2
CPUSTOPCLK
0: CPU clock is not stopped. This indicates that the MCU is in
Normal mode or Sleep mode
1: CPU clock is stopped. This indicates that the MCU is in
Snooze mode or Software Standby mode.
R
b31 to b3
—
These bits are read as 0
R
Reserved
Note 1. Depends on the MCU status.
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2. CPU
MCU Control Register (MCUCTRL)
Address(es): MCUCTRL 8000 0410h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DBIRQ
—
—
—
—
—
—
—
EDBGR
Q
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
EDBGRQ
External Debug
Request
Writing 1 to the bit causes a CPU halt or debug monitor
exception.
0: Debug event not requested
1: Debug event requested.
When the EDBGRQ bit is set to 0 or the CPU is halted, the
EDBCRQ bit is cleared.
R/W
b7 to b1
—
Reserved
These bits are read as 0
R
b8
DBIRQ
Debug Interrupt
Request
Writing 1 to the bit wakes up the MCU from low power mode.
0: Debug interrupt not requested
1: Debug interrupt requested
The condition can be cleared by writing 0 to the DBIRQ bit.
R/W
b31 to b9
—
Reserved
These bits are read as 0.
R
Note:
Set DBIRQ and EDBGRQ to the same value.
2.6.6.4
OCDREG CoreSight component registers
OCDREG provides the CoreSight component registers defined in the Arm CoreSight architecture.
Table 2.13 lists these registers. See reference 5. in section 2.9 for details of each register.
Table 2.13
OCDREG CoreSight component registers
Name
Address
Access size
R/W
Initial value
PID4
8000 0FD0h
32 bits
R
00000004h
PID5
8000 0FD4h
32 bits
R
00000000h
PID6
8000 0FD8h
32 bits
R
00000000h
PID7
8000 0FDCh
32 bits
R
00000000h
PID0
8000 0FE0h
32 bits
R
00000004h
PID1
8000 0FE4h
32 bits
R
00000030h
PID2
8000 0FE8h
32 bits
R
0000000Ah
PID3
8000 0FECh
32 bits
R
00000000h
CID0
8000 0FF0h
32 bits
R
0000000Dh
CID1
8000 0FF4h
32 bits
R
000000F0h
CID2
8000 0FF8h
32 bits
R
00000005h
CID3
8000 0FFCh
32 bits
R
000000B1h
2.7
SysTick System Timer
The MCU has a SysTick system timer that provides a simple 24-bit down counter. The reference clock for the timer can
be selected as the CPU clock (ICLK) or SysTick timer clock (SYSTICCLK).
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See section 8, Clock Generation Circuit and reference 1.*1 for details.
Note 1. In the reference, the IMPLEMENTATION DEFINED external reference clock is SYSTICCLK (LOCO), and the
processor clock is ICLK.
2.8
OCD Emulator Connection
The MCU has a SWD authentication mechanism that checks access permission for debug and chip resources. To obtain
full debug functionality, a pass result of the authentication mechanism is required.
Figure 2.3 shows the block diagram of the authentication mechanism.
Emulator
Host PC
This MCU
OCD
Emulator
SWD
SWJ-DP
AHB-AP
APB-AP
To: CPU
Debug
To: CPU Bus
OCDREG
ID
Comparator
Option-Setting
Memory
IAUTH output
Compare
result
(Debug
enable)
Unlock ID
Figure 2.3
Authentication mechanism block diagram
An ID comparator is available in the MCU for authentication. The comparator compares 128-bit IAUTH output from the
OCDREG and 128-bit Unlock ID code from the option-setting memory. When the two outputs are identical, the CPU
Debug functions and system bus access from the OCD emulator are permitted.
2.8.1
DBGEN
After the OCD emulator gets access permission, the OCD emulator must set the DBGEN bit in the System Control OCD
Control Register (SYOCDCR). In addition, the OCD emulator must clear the DBGEN bit before disconnecting it. See
section 10, Low Power Modes for details.
2.8.2
Unlock ID Code
The unlock ID code is used for checking permission for debug and access to on-chip resources. If the unlock ID code
matches the 128-bit data written in the ID Authentication Registers 0 to 3, the SWD debugger obtains the access
permission. Unlock ID code is written in the OCD/Serial Programmer ID Setting Register (OSIS) in the option-setting
memory. The initial value of the unlock ID code is all 1s (FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFFh). See section
6, Option-Setting Memory for details.
2.8.3
Restrictions on Connecting an OCD Emulator
This section describes the restrictions on emulator access.
2.8.3.1
Starting connection while in low power mode
When starting a SWD connection from an OCD emulator, the MCU must be in Normal mode or Sleep mode. If the MCU
is in Software Standby or Snooze mode, the OCD emulator can cause the MCU to hang.
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2. CPU
Changing low power mode while in OCD mode
When the MCU is in OCD mode, the low power mode can be changed. However, system bus access from AHB-AP is
prohibited in Software Standby mode or Snooze mode. Only SWJ-DP, APB-AP and OCDREG can be accessed from the
OCD emulator in these modes. Table 2.14 shows the restrictions.
Table 2.14
Restrictions by mode
Active mode
Start OCD emulator
connection
Change low power
mode
Access AHB-AP and
system bus
Access APB-AP and
OCDREG
Normal
Yes
Yes
Yes
Yes
Sleep
Yes
Yes
Yes
Yes
Software Standby
No
Yes
No
Yes
Snooze
No
Yes
No
Yes
If system bus access is required in Software Standby or Snooze mode, use the MCUCTRL.DBIRQ bit in OCDREG. This
can wake up the MCU from these low power modes. Simultaneously, using the MCUCTRL.EDBGRQ bit in OCDREG,
the OCD emulator can wake up the MCU without starting CPU execution by using CPU break.
2.8.3.3
Modify the unlock ID code in OSIS
After modifying the unlock ID code in the OSIS, the OCD emulator must reset the MCU by asserting the RES pin or
setting the SYSRESETREQ bit of the Application Interrupt and Reset Control Register in the system control block to 1.
The modified unlock ID code is reflected after reset.
2.8.3.4
Connecting sequence and SWD authentication
Because the OCD emulator is protected by the SWD authentication mechanism, OCD might be required to input the ID
code to the authentication registers. The OSIS value in the option setting memory determines whether the code is
required. After negation of the reset, a 36 μs wait time is required before comparing the OSIS value at cold start.
(1)
When MSB of OSIS bit [127] = 0
The ID code is always mismatching and connection to the OCD is prohibited.
(2)
When OSIS is all 1s (default)
OCD authentication is not required and OCD can use the AHB-AP without authentication.
1. Connect the OCD emulator to the MCU through the SWD interface.
2. Set up SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in the SWJDP Control Status Register, then wait until CSDBGPWRUPACK in the same register is asserted.
3. Set up AHB-AP to access the system address space. AHB-AP is connected to the DAP bus port 0.
4. Start accessing the CPU debug resources using the AHB-AP.
(3)
When OSIS bits [127:126] = 10b
OCD authentication is required and the OCD must write the unlock code to the IAUTH registers 0 to 3 in the OCDREG
before using the AHB-AP.
1. Connect the OCD debugger to the MCU through the SWD interface.
2. Set up SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in SWJ-DP
Control Status Register, then wait until CSDBGPWRUPACK in the same register is asserted.
3. Set up APB-AP to access OCDREG. APB-AP is connected to the DAP bus port 1.
4. Write 128-bit ID code to IAUTH registers 0 to 3 in the OCDREG using APB-AP.
5. If the 128-bit ID code matches the OSIS value, AHB-AP is authorized to issue an AHB transaction. The
authorization result can be confirmed by the AUTH bit in the MCUSTAT register or DbgStatus bit in the AHB-AP
Control Status Word register.
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2. CPU
When DbgStatus bit is 1, the 128-bit ID code is a match with the OSIS value. AHB transfers are permitted.
When DbgStatus bit is 0, the 128-bit ID code is not a match with the OSIS value. AHB transfers are not
permitted.
6. Set up AHB-AP to access the system address space. AHB-AP is connected to the DAP bus port 0
7. Start accessing the CPU debug resources using the AHB-AP.
(4)
When OSIS bits [127:126] = 11b
OCD authentication is required and the OCD must write the unlock ID code to IAUTH registers 0 to 3 in OCDREG. The
connection sequence is the same when OSIS bits [127:126] is 10b except for ALeRASE.
When IAUTH0-3 are ALeRASE in ASCII code, the content of the code flash, data flash, and configuration area are
erased at once. See section 37, Flash Memory for details.
ALeRASE sequence is as follows:
1. Connect the OCD debugger to the MCU through the JTAG or SWD interface.
2. Set up SWJ-DP to access the DAP bus. In the setup, the OCD emulator must assert CDBGPWRUPREQ in the
SWJDP Control Status Register, and then wait until CSDBGPWRUPACK in the same register is asserted.
3. Set the APB-AP to access OCDREG. This APB-AP is connected to DAP bus port 1.
4. Write the 128-bit ID code to IAUTH registers 0 to 3 in the OCDREG using the APB-AP.
5. If the 128-bit ID code is ALeRASE in ASCII code (414C_6552_4153_45FF_FFFF_FFFF_FFFF_FFFFh), the
content of the code flash, data flash, and configuration area are erased. After that, the MCU transitions to Sleep
mode.
2.9
References
1. ARM®v6-M Architecture Reference Manual (ARM DDI 0419C)
2. ARM® Cortex®-M0+ Processor Technical Reference Manual (ARM DDI 0484C)
3. ARM® Cortex®-M0+ Devices Generic User Guide (ARM DUI 0662B)
4.
ARM® CoreSight™ SoC-400 Technical Reference Manual (ARM DDI 0480F)
5. ARM® CoreSight™ Architecture Specification (ARM IHI 0029D)
6.
ARM® CoreSight™ MTB-M0+ Technical Reference Manual (ARM DDI 0486B).
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3. Operating Modes
3.
Operating Modes
3.1
Operating Mode Types and Selection
Table 3.1 shows the selection of operating modes by the mode-setting pin. For details on each of the operating modes,
see section 3.2, Details of Operating Modes. Operation starts when the on-chip flash memory enabled, regardless of the
mode in which operation started.
Table 3.1
Selection of operating modes by the mode-setting pin
Mode-setting pin
MD
Operating mode
1
Single-chip mode
0
SCI boot mode
3.2
Details of Operating Modes
3.2.1
Single-Chip Mode
In single-chip mode, all I/O pins are available for use as input or output port, inputs or outputs for peripheral functions, or
as interrupt inputs. When a reset is released while the MD pin is high, the chip starts in single-chip mode and the on-chip
flash is enabled.
3.2.2
SCI Boot Mode
In this mode, the on-chip flash memory programming routine (SCI boot program), stored in a dedicated area within the
MCU, is used. The on-chip flash, including code flash memory and data flash memory, can be modified from outside the
MCU by using a universal asynchronous receiver/transmitter (SCI). For details, see section 37, Flash Memory. The chip
starts up in boot mode if the MD pin is held low on release from the reset state.
3.3
Operating Mode Transitions
3.3.1
Operating Mode Transitions as Determined by the Mode-Setting Pin
Figure 3.1 shows operating mode transitions determined by the settings of the MD pin.
Reset
RES pin or
POR occurs
- MD = 1 & Release RES pin
- Release POR
RES pin or
POR occurs
Single-chip mode
Figure 3.1
- MD = 0
- Release RES pin
SCI boot mode
Mode-setting pin level and operating mode
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4.
Address Space
4.1
Address Space
4. Address Space
The MCU supports a 4-GB linear address space ranging from 0000 0000h to FFFF FFFFh that can contain both program
and data. Figure 4.1 shows the memory map.
FFFF FFFFh
System for Cortex-M0+
E000 0000h
Reserved area*2
407F B1A0h
407F B19Ch
On-chip Flash
(Option-Setting Memory)
Reserved area*2
407F 0000h
407E 0000h
Flash I/O registers*1
Reserved area*2
4010 1000h
On-chip Flash (data Flash)
4010 0000h
Peripheral I/O registers
4000 0000h
Reserved area*2
2000 4000h
On-chip SRAM*1
2000 0000h
Reserved area*2
0101 0034h
0101 0008h On-chip Flash (Option-Setting Memory)
Reserved area*2
0002 0000h
On-chip Flash (program Flash)
(read only)*1, *3
0000 0000h
Note 1. The capacity of the flash or SRAM differs depending on the product.
Product
Address
128-KB product
0000 0000h to 0001_FFFFh
Note 2. Do not access reserved areas.
Note 3. Some regions are reserved for the option-setting memory. For details on the regions, see section 6, OptionSetting Memory.
Figure 4.1
Memory map
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5.
Resets
5.1
Overview
5. Resets
The MCU has 9 types of resets:
RES pin reset
Power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
Software reset.
Table 5.1 lists the reset names and sources.
Table 5.1
Reset names and sources
Reset name
Source
RES pin reset
Voltage input to the RES pin is driven low
Power-on reset
VCC rise (voltage detection VPOR)*1
Independent Watchdog Timer reset
IWDT underflow or refresh error
Watchdog Timer reset
WDT underflow or refresh error
Voltage monitor 0 reset
VCC fall (voltage detection Vdet0)*1
Voltage monitor 1 reset
VCC fall (voltage detection Vdet1)*1
Voltage monitor 2 reset
VCC fall (voltage detection Vdet2)*1
SRAM parity error reset
SRAM parity error detection
Software reset
Register setting (use the Arm® software reset bit AIRCR.SYSRESETREQ)
Note 1. For details on the voltages to be monitored (VPOR, Vdet0, Vdet1, and Vdet2), see section 7, Low Voltage
Detection (LVD) and section 41, Electrical Characteristics.
The internal state and pins are initialized by a reset. Table 5.2 and Table 5.3 list the targets initialized by resets.
Table 5.2
Reset detect flags initialized by each reset source
Reset source
Independent
watchdog timer
reset
Watchdog timer
reset
Flags to be initialized
RES pin reset
Power-on reset
Voltage monitor 0
reset
Power-On Reset Detect Flag (RSTSR0.PORF)
x
x
x
x
Voltage Monitor 0 Reset Detect Flag (RSTSR0.LVD0RF)
x
x
x
Independent Watchdog Timer Reset Detect Flag
(RSTSR1.IWDTRF)
x
x
Watchdog Timer Reset Detect Flag(RSTSR1.WDTRF)
x
x
Voltage Monitor 1 Reset Detect Flag (RSTSR0.LVD1RF)
x
x
Voltage Monitor 2 Reset Detect Flag(RSTSR0.LVD2RF)
x
x
Software Reset Detect Flag (RSTSR1.SWRF)
x
x
SRAM Parity Error Reset Detect Flag (RSTSR1.RPERF)
x
x
Cold Start/Warm Start Determination Flag (RSTSR2.CWSF)
x
x
x
x
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5. Resets
Reset source
Flags to be initialized
Voltage monitor 1
reset
Voltage monitor 2
reset
Software reset
SRAM parity error
reset
Power-On Reset Detect Flag (RSTSR0.PORF)
x
x
x
x
Voltage Monitor 0 Reset Detect Flag (RSTSR0.LVD0RF)
x
x
x
x
Independent Watchdog Timer Reset Detect Flag
(RSTSR1.IWDTRF)
x
x
x
x
Watchdog Timer Reset Detect Flag(RSTSR1.WDTRF)
x
x
x
x
Voltage Monitor 1 Reset Detect Flag (RSTSR0.LVD1RF)
x
x
x
x
Voltage Monitor 2 Reset Detect Flag(RSTSR0.LVD2RF)
x
x
x
x
Software Reset Detect Flag (RSTSR1.SWRF)
x
x
x
x
SRAM Parity Error Reset Detect Flag (RSTSR1.RPERF)
x
x
x
x
Cold Start/Warm Start Determination Flag (RSTSR2.CWSF)
x
x
x
x
Independent
watchdog timer
reset
Watchdog timer
reset
: Initialized to 0
x: Not initialized
Table 5.3
Module-related registers initialized by each reset source
Reset source
Registers to be initialized
RES pin reset
Power-on reset
Voltage monitor 0
reset
Registers related to the
watchdog timer
WDTRR, WDTCR, WDTSR,
WDTRCR, WDTCSTPR
Registers related to the voltage
monitor function 1
LVD1CR0, LVCMPCR.LVD1E,
LVDLVLR.LVD1LVL
LVD1CR1/LVD1SR
Registers related to the voltage
monitor function 2
LVD2CR0, LVCMPCR.LVD2E,
LVDLVLR.LVD2LVL
LVD2CR1/LVD2SR
SOSCCR
x
x
x
x
SOMCR
x
x
x
x
LOCOCR
LOCOUTCR
x
x
x
MOMCR
Register related to the SOSC
Register related to the LOCO
Register related to the MOSC
Register related to the realtime clock*1
x
x
x
x
x
Register related to the AGT
x
x
x
Pin state (except XCIN/XCOUT pin)
Pin state (XCIN/XCOUT pin)
x
x
x
x
Registers other than the above, CPU, and internal state
Voltage monitor 1
reset
Voltage monitor 2
reset
Software reset
SRAM parity error
reset
Reset source
Registers to be initialized
Registers related to the
watchdog timer
WDTRR, WDTCR, WDTSR,
WDTRCR, WDTCSTPR
Registers related to the voltage
monitor function 1
LVD1CR0, LVCMPCR.LVD1E,
LVDLVLR.LVD1LVL
x
x
x
x
LVD1CR1/LVD1SR
x
x
x
x
Registers related to the voltage
monitor function 2
LVD2CR0, LVCMPCR.LVD2E,
LVDLVLR.LVD2LVL
x
x
x
x
LVD2CR1/LVD2SR
x
x
x
x
SOSCCR
x
x
x
x
SOMCR
x
x
x
x
LOCOCR
LOCOUTCR
x
x
MOMCR
Register related to the SOSC
Register related to the LOCO
Register related to the MOSC
Register related to the realtime clock*1
x
x
x
x
Register related to the AGT
x
x
Pin state (except XCIN/XCOUT pin)
Pin state (XCIN/XCOUT pin)
x
x
x
x
Registers other than the above, CPU, and internal state
: Initialized, x: Not initialized
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5. Resets
Note 1. The RTC has a software reset. RCR1.RTCOS, CIE and RCR2.RTCOE, ADJ30, RESET are initialized by all
types of resets. For details on the target bits, see section 21, Realtime Clock (RTC).
The RTC is not initialized by any reset source. SOSC and LOCO can be selected as the clock source of RTC. The
following are the states of SOSC and LOCO when a reset occurs.
Table 5.4
States of SOSC when a reset occurs
Reset source
SOSC
Table 5.5
POR
Other
Enable or disable
Initialized to disable
Continue with the state before the reset occured
Drive capability
Initialized to normal mode
Continue with the state before the reset occured
XCIN/XCOUT
Initialized to general-purpose input
pins
Continue with the state before the reset occured
States of LOCO when a reset occurs
Reset source
POR/LVD0/LVD1/LVD2
LOCO
Enable or disable
Oscillation
Other
Initialized to enable
accuracy*1
Initialized to accuracy before trimming
by Power-on (accuracy: +/- 15%)
Continue the accuracy that was trimmed by
LOCOUTCR
Note 1. The LOCO User Trimming Control Register (LOCOUTCR) is reset by POR, LVD0, LVD1, and LVD2 resets,
returning the LOCO to the default oscillation accuracy. This can affect RTC accuracy if the RTC uses the LOCO
(with a user trimming value in LOCOUTCR) as the RTC source clock. To restore the pre-reset LOCO oscillation
accuracy, reload the required trimming value into LOCOUTCR after any of these resets.
When a reset is canceled, reset exception handling starts.
Table 5.6 lists the pin related to the reset function.
Table 5.6
Pin related to reset
Pin name
I/O
Function
RES
Input
Reset pin
5.2
Register Descriptions
5.2.1
Reset Status Register 0 (RSTSR0)
Address(es): SYSTEM.RSTSR0 4001 E410h
Value after reset:
b7
b6
b5
b4
—
—
—
—
0
0
0
0
b3
b2
b1
b0
LVD2R LVD1R LVD0R PORF
F
F
F
x*1
x*1
x*1
x*1
Bit
Symbol
Bit name
Description
R/W
b0
PORF
Power-On Reset Detect Flag
0: Power-on reset not detected
1: Power-on reset detected.
R(/W)*2
b1
LVD0RF
Voltage Monitor 0 Reset Detect Flag
0: Voltage monitor 0 reset not detected
1: Voltage monitor 0 reset detected.
R(/W)*2
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5. Resets
Bit
Symbol
Bit name
Description
R/W
b2
LVD1RF
Voltage Monitor 1 Reset Detect Flag
0: Voltage monitor 1 reset not detected
1: Voltage monitor 1 reset detected.
R(/W)*2
b3
LVD2RF
Voltage Monitor 2 Reset Detect Flag
0: Voltage monitor 2 reset not detected
1: Voltage monitor 2 reset detected.
R(/W)*2
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. The value after reset depends on the reset source.
Note 2. Only 0 can be written to clear the flag. The flag must be cleared by writing 0 after 1 is read.
PORF flag (Power-On Reset Detect Flag)
The PORF flag indicates that a power-on reset occurred.
[Setting condition]
When a power-on reset occurs.
[Clearing conditions]
When a reset listed in Table 5.2 occurs
When 1 is read and then 0 is written to PORF.
LVD0RF flag (Voltage Monitor 0 Reset Detect Flag)
The LVD0RF flag indicates that VCC voltage fell below Vdet0.
[Setting condition]
When a voltage monitor 0 reset occurs.
[Clearing conditions]
When a reset listed in Table 5.2 occurs
When 1 is read and then 0 is written to LVD0RF.
LVD1RF flag (Voltage Monitor 1 Reset Detect Flag)
The LVD1RF flag indicates that VCC voltage fell below Vdet1.
[Setting condition]
When a voltage monitor 1 reset occurs.
[Clearing conditions]
When a reset listed in Table 5.2 occurs
When LVD1RF is read as 1 and 0 is written to LVD1RF.
LVD2RF flag (Voltage Monitor 2 Reset Detect Flag)
The LVD2RF flag indicates that VCC voltage fell below Vdet2.
[Setting condition]
When a voltage monitor 2 reset occurs.
[Clearing conditions]
When a reset listed in Table 5.2 occurs
When 1 is read and then 0 is written to LVD2RF.
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5.2.2
5. Resets
Reset Status Register 1 (RSTSR1)
Address(es): SYSTEM.RSTSR1 4001 E0C0h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
—
—
—
—
—
—
—
RPERF
—
—
—
—
—
0
0
0
0
0
0
0
x*1
0
0
0
0
0
Value after reset:
b2
b1
b0
SWRF WDTR IWDTR
F
F
x*1
x*1
x*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
IWDTRF
Independent Watchdog Timer Reset
Detect Flag
0: Independent Watchdog Timer reset not detected
1: Independent Watchdog Timer reset detected.
R(/W)
*2
b1
WDTRF
Watchdog Timer Reset Detect Flag
0: Watchdog Timer reset not detected
1: Watchdog Timer reset detected.
R(/W)
*2
b2
SWRF
Software Reset Detect Flag
0: Software reset not detected
1: Software reset detected.
R(/W)
*2
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b8
RPERF
SRAM Parity Error Reset Detect Flag
0: SRAM parity error reset not detected
1: SRAM parity error reset detected.
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0. R/W
R(/W)
*2
Note 1. The value after reset depends on the reset source.
Note 2. Only 0 can be written to clear the flag. The flag must be cleared by writing 0 after 1 is read.
IWDTRF flag (Independent Watchdog Timer Reset Detect Flag)
The IWDTRF flag indicates that an independent watchdog timer reset occurs.
[Setting condition]
When an independent watchdog timer reset occurs.
[Clearing conditions]
When a reset listed in Table 5.2 occurs
When 1 is read and then 0 is written to IWDTRF.
WDTRF flag (Watchdog Timer Reset Detect Flag)
The WDTRF flag indicates that a watchdog timer reset occurs.
[Setting condition]
When a watchdog timer reset occurs.
[Clearing conditions]
When a reset listed in Table 5.2 occurs
When 1 is read and then 0 is written to WDTRF.
SWRF flag (Software Reset Detect Flag)
The SWRF flag indicates that a software reset occurs.
[Setting condition]
When a software reset occurs.
[Clearing conditions]
When a reset listed in Table 5.2 occurs
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5. Resets
When 1 is read and then 0 is written to SWRF.
RPERF flag (SRAM Parity Error Reset Detect Flag)
The RPERF flag indicates that an SRAM parity error reset occurs.
[Setting condition]
When an SRAM parity error reset occurs.
[Clearing conditions]
When a reset listed in Table 5.2 occurs
When 1 is read and then 0 is written to RPERF.
5.2.3
Reset Status Register 2 (RSTSR2)
Address(es): SYSTEM.RSTSR2 4001 E411h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
CWSF
0
0
0
0
0
0
0
x*1
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
CWSF
Cold/Warm Start Determination Flag
0: Cold start
1: Warm start.
R(/W)
*2
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. The value after reset depends on the reset source.
Note 2. Only 1 can be written to set the flag.
RSTSR2 determines whether a power-on reset caused the reset processing (cold start) or a reset signal input during
operation caused the reset processing (warm start).
CWSF flag (Cold/Warm Start Determination Flag)
The CWSF flag indicates the type of reset processing, either cold start or warm start. The CWSF flag is initialized by a
power-on reset. It is not initialized by a reset signal generated by the RES pin.
[Setting condition]
When 1 is written by software. Writing 0 to CWSF does not set it to 0.
[Clearing condition]
When a reset listed in Table 5.2 occurs.
5.3
5.3.1
Operation
RES Pin Reset
The RES pin generates this reset. When the RES pin is driven low, all the processing in progress is aborted and the MCU
enters a reset state. To successfully reset the MCU, the RES pin must be held low for the power supply stabilization time
specified for power-on.
When the RES pin is driven high from low, the internal reset is canceled after the post-RES cancellation wait time
(tRESWT) elapses, and the CPU starts the reset exception handling.
For details, see section 41, Electrical Characteristics.
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5.3.2
5. Resets
Power-On Reset
The power-on reset (POR) is an internal reset generated by the power-on reset circuit. If the RES pin is in a high level
state when power is supplied, a power-on reset is generated. After VCC exceeds VPOR and the specified power-on reset
time elapses, the internal reset is canceled and the CPU starts the reset exception handling. The power-on reset time is a
stabilization period of the external power supply and the MCU circuit. After a power-on reset is generated, the PORF
flag in the RSTSR0 is set to 1. The PORF flag is initialized by the RES pin reset.
The voltage monitor 0 reset is an internal reset generated by the voltage monitor circuit. If the Voltage Detection 0
Circuit Start (LVDAS) bit in the Option Function Select register 1 (OFS1) is 0 (voltage monitor 0 reset is enabled after a
reset) and VCC falls below Vdet0, the RSTSR0.LVD0RF flag is set to 1 and the voltage detection circuit generates
voltage monitor 0 reset. Clear the OFS1.LVDAS bit to 0 if the voltage monitor 0 reset is to be used.
After VCC exceeds Vdet0 and the voltage monitor 0 reset time (tLVD0) elapses, the internal reset is canceled and the
CPU starts the reset exception handling. The Vdet0 voltage detection level can be changed by the setting of the
VDSEL1[2:0] bits in the Option Function Select register 1 (OFS1).
Figure 5.1 shows examples of operation during a power-on reset and voltage monitor 0 reset.
Vdet0*1
*3
VCCmin.
VPOR
VCC
Power-on reset state
Voltage monitor 0 reset state
Voltage monitor 0 reset state
RES pin
POR Monitor
(active-low)
LVD0 enable/disable signal
(active-low)
Set by OFS1.LVDAS
Voltage detection 0 signal
(active-low)
Internal reset signal
(active-low)
RSTSR0.PORF
tLVD0*2
tLVD0*2
Cleared by user
programming
RES pin reset
RSTSR0.LVD0RF
Note:
Note 1.
Note 2.
Note 3.
Figure 5.1
5.3.3
For details on the electrical characteristics, see section 41, Electrical Characteristics.
Vdet0 shows a voltage monitor 0 reset detection level, and VPOR shows a power-on reset detection level, and
VCCmin shows minimum guaranteed voltage of MCU.
tLVD0 shows a time for voltage monitor 0 reset.
At power-on, VCC should have risen to the minimum guaranteed voltage before the POR reset is released.
Examples of operation during power-on and voltage monitor 0 resets
Voltage Monitor Reset
The voltage monitor 0 reset is an internal reset generated by the voltage monitor circuit. If the Voltage Detection 0
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5. Resets
Circuit Start (LVDAS) bit in the Option Function Select register 1 (OFS1) is 0 (voltage monitor 0 reset is enabled after a
reset) and VCC falls below Vdet0, the RSTSR0.LVD0RF flag becomes 1 and the voltage detection circuit generates
voltage monitor 0 reset. Clear the OFS1.LVDAS bit to 0 if the voltage monitor 0 reset is to be used. After VCC exceeds
Vdet0 and the voltage monitor 0 reset time (tLVD0) elapses, the internal reset is canceled and the CPU starts the reset
exception handling.
When the Voltage Monitor 1 Interrupt/Reset Enable bit (RIE) is set to 1 (enabling generation of a reset or interrupt by the
voltage detection circuit) and the Voltage Monitor 1 Circuit Mode Select bit (RI) is set to 1 (selecting generation of a
reset in response to detection of a low voltage) in Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0), the
RSTSR0.LVD1RF flag is set to 1 and the voltage detection circuit generates a voltage monitor 1 reset if VCC falls to or
below Vdet1.
Likewise, when the Voltage Monitor 2 Interrupt/Reset Enable bit (RIE) is set to 1 (enabling generation of a reset or
interrupt by the voltage detection circuit) and the Voltage Monitor 2 Circuit Mode Select bit (RI) is set to 1 (selecting
generation of a reset in response to detection of a low voltage) in Voltage Monitor 2 Circuit Control Register 0
(LVD2CR0), the RSTSR0.LVD2RF flag is set to 1 and the voltage detection circuit generates a voltage monitor 2 reset if
VCC falls to or below Vdet2.
Similarly, timing for release from the voltage monitor 1 reset state is selectable with the Voltage Monitor 1 Reset Negate
Select bit (RN) in the LVD1CR0. When the LVD1CR0.RN bit is 0 and VCC has fallen to or below Vdet1, the CPU is
released from the internal reset state and starts reset exception handling when the LVD1 reset time (tLVD1) elapses after
VCC rises above Vdet1. When the LVD1CR0.RN bit is 1 and VCC falls to or below Vdet1, the CPU is released from the
internal reset state and starts reset exception handling when the LVD1 reset time (tLVD1) elapses.
Likewise, timing for release from the voltage monitor 2 reset state is selectable by setting the Voltage Monitor 2 Reset
Negate Select bit (RN) in the LDV2CR0 register.
Detection levels Vdet1 and Vdet2 can be changed in the Voltage Detection Level Select Register (LVDLVLR).
Figure 5.2 shows examples of operation during voltage monitor 1 and 2 resets. For details on the voltage monitor 1 reset
and voltage monitor 2 reset, see section 7, Low Voltage Detection (LVD).
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5. Resets
Vdeti*1
VCC
RES pin
LVDi valid setting
LVCMPCR.LVDiE
Voltage detection i signal
(low is valid)
LVDiCR0.RN = 0
RES pin reset
RSTSR0.LVDiRF
tLVDi*2
Internal reset signal
LVDiCR0.RN = 1
RES pin reset
RSTSR0.LVDiRF
Internal reset signal
Note:
Note 1.
Note 2.
Figure 5.2
5.3.4
tLVDi*2
For details on the electrical characteristics, see section 41, Electrical Characteristics.
Vdeti indicates the detection level of a voltage monitor 1 reset and voltage monitor 2 reset (i = 1, 2).
tLVDi indicates the time for a voltage monitor 1 reset and voltage monitor 2 reset (i = 1, 2).
Examples of operation during voltage monitor 1 and voltage monitor 2 resets
Independent Watchdog Timer Reset
Independent watchdog timer reset is an internal reset generated by the Independent Watchdog Timer (IWDT). Output of
the independent watchdog timer reset from the IWDT can be selected by settings in the Option Function Select register 0
(OFS0).
When output of the independent watchdog timer reset is selected, the reset is generated if the IWDT underflows, or if
data is written when refresh operation is disabled. When the internal reset time (tRESW2) elapses after the independent
watchdog timer reset is generated, the internal reset is canceled and the CPU starts the reset exception handling.
For details on the independent watchdog timer reset, see section 23, Independent Watchdog Timer (IWDT).
5.3.5
Watchdog Timer Reset
The watchdog timer reset is an internal reset generated from the Watchdog Timer (WDT). Output of the watchdog timer
reset from the WDT can be selected by settings in the WDT Reset Control Register (WDTRCR) or Option Function
Select register 0 (OFS0).
When output of the watchdog timer reset is selected, a watchdog timer reset is generated if the WDT underflows, or if
data is written when refresh operation is disabled. When the internal reset time (tRESW2) elapses after the watchdog
timer reset is generated, the internal reset is canceled and the CPU starts the reset exception handling.
For details on the watchdog timer reset, see section 22, Watchdog Timer (WDT).
5.3.6
Software Reset
The software reset is an internal reset generated by software setting of the SYSRESETREQ bit in the AIRCR register in
the Arm core.
When the SYSRESETREQ bit is set to 1, a software reset is generated. When the internal reset time (tRESW2) elapses
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5. Resets
after the software reset is generated, the internal reset is canceled and the CPU starts the reset exception handling.
For details on the SYSRESETREQ bit, see the ARM® Cortex®-M0+ Technical Reference Manual.
5.3.7
Determination of Cold/Warm Start
Read the CWSF flag in RSTSR2 to determine the cause of reset processing. The flag indicates whether a power-on reset
caused the reset processing (cold start) or a reset signal input during operation caused the reset processing (warm start).
The CWSF flag is set to 0 when a power-on reset occurs (cold start), otherwise the flag is not set to 0. The flag is set to 1
when 1 is written to it through software. It is not set to 0 even when 0 is written.
Figure 5.3 shows an example of cold/warm start determination operation.
VPOR
VCC
RES pin
POR signal (Low is valid)
Not driven to 0 when a
low level is applied to
the RES pin
RSTSR2.CWSF flag
Set to 1 through programming
Figure 5.3
5.3.8
Example of cold/warm start determination operation
Determination of Reset Generation Source
Read RSTSR0 and RSTSR1 to determine which reset is used to execute the reset exception handling.
Figure 5.4 shows an example of the flow to identify a reset generation source. The reset flag must be written with 0 after
it is read as 1.
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5. Resets
Reset exception
handling
RSTSR1 00h
or
RSTSR0.LVD1RF = 1
or
RSTSR0.LVD2RF = 1
No
Yes
RSTSR0.
LVD0RF = 1
Yes
No
RSTSR0.
PORF = 1
No
Yes
Reset associated with
each bit of RSTSR1,
RSTSR0.LVD1RF, or
RSTSR0.LVD2RF*1
Note 1.
Figure 5.4
Voltage
monitor 0
reset
Power-on
reset
RES pin reset
If a reset associated with each bit of RSTSR1, RSTSR0.LVD1RF, or RSTSR0.LVD2RF occurs at the
same time, all reset flags are set to 1.
Example of reset generation source determination flow
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6. Option-Setting Memory
6.
Option-Setting Memory
6.1
Overview
The option-setting memory determines the state of the MCU after a reset. Option-setting memory is allocated to the
configuration setting area and the program flash area of the flash memory, and the available methods of setting are
different for the two areas.
Figure 6.1 shows the option-setting memory area.
Address*1
0101 0018h to 0101 0033h
OCD/Serial Programmer ID
Setting Register (OSIS)
0101 0010h to 0101 0013h
Access Window Setting Register
(AWS)
0101 0008h to 0101 000Bh
Access Window Setting Control
Register (AWSC)
0000 0404h to 0000 0407h
Option Function Select Register 1
(OFS1)
0000 0400h to 0000 0403h
Option Function Select Register 0
(OFS0)
Note 1.
Figure 6.1
6.2
Configuration setting area
Program ROM area
The option-setting memory must be allocate to the flash user area.
Option-setting memory area
Register Descriptions
6.2.1
Option Function Select Register 0 (OFS0)
Address(es): OFS0 0000 0400h
b31
b30
—
WDTST
PCTL
b29
—
b28
b27
b26
b25
b24
b23
WDTRS WDTRPSS[1:0] WDTRPES[1:0]
TIRQS
b22
b21
b20
b19
b18
b17
b16
WDTTOPS[1:0] WDTST
RT
WDTCKS[3:0]
—
The value set by the user*1
Value after reset:
b15
b14
b13
—
IWDTS
TPCTL
—
b12
b11
b10
b9
b8
b7
IWDTR IWDTRPSS[1:0] IWDTRPES[1:0]
STIRQS
b6
b5
IWDTCKS[3:0]
b4
b3
b2
b1
b0
IWDTTOPS[1:0] IWDTS
TRT
—
The value set by the user*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
When read, this bit returns the written value. The write
value should be 1.
R
b1
IWDTSTRT
IWDT Start Mode Select
0: Automatically activate IWDT after a reset (auto-start
mode)
1: Disable IWDT.
R
b3, b2
IWDTTOPS[1:0]
IWDT Timeout Period Select
b3 b2
R
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0
0
1
1
0: 128 cycles (007Fh)
1: 512 cycles (01FFh)
0: 1024 cycles (03FFh)
1: 2048 cycles (07FFh).
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6. Option-Setting Memory
Bit
Symbol
Bit name
Description
R/W
b7 to b4
IWDTCKS[3:0]
IWDT-Dedicated Clock
Frequency Division Ratio
Select
b7
R
b9, b8
IWDTRPES[1:0]
IWDT Window End Position
Select
b9 b8
R
b11, b10
IWDTRPSS[1:0]
IWDT Window Start Position
Select
b11 b10
R
b12
IWDTRSTIRQS
IWDT Reset Interrupt
Request Select
0: Enable non-maskable interrupt request or interrupt
request
1: Enable reset.
R
b13
—
Reserved
When read, this bit returns the value written by the user.
The write value should be 1.
R
b14
IWDTSTPCTL
IWDT Stop Control
0: Continue counting
1: Stop counting when in Sleep mode, Snooze mode, or
Software Standby mode.
R
b16, b15
—
Reserved
When read, these bits return the written value. The write
value should be 1.
R
b17
WDTSTRT
WDT Start Mode Select
0: Automatically activate WDT after a reset (auto-start
mode)
1: Stop WDT after a reset (register-start mode).
R
b19, b18
WDTTOPS[1:0]
WDT Timeout Period Select
b19 b18
R
b23 to b20
WDTCKS[3:0]
WDT Clock Frequency
Division Ratio Select
b23
b25, b24
WDTRPES[1:0]
WDT Window End Position
Select
b25 b24
R
b27, b26
WDTRPSS[1:0]
WDT Window Start Position
Select
b27 b26
R
b28
WDTRSTIRQS
WDT Reset Interrupt Request
Select
WDT Behavior Select:
0: NMI
1: Reset.
R
b29
—
Reserved
When read, these bits return the written value. The write
value should be 1.
R
b30
WDTSTPCTL
WDT Stop Control
0: Continue counting
1: Stop counting when entering Sleep mode.
R
b31
—
Reserved
When read, these bits return the written value. The write
value should be 1.
R
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b4
0 0 0 0: × 1
0 0 1 0: × 1/16
0 0 1 1: × 1/32
0 1 0 0: × 1/64
1 1 1 1: × 1/128
0 1 0 1: × 1/256.
Other settings are prohibited.
0
0
1
1
0
0
1
1
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (no window end position setting).
0: 25%
1: 50%
0: 75%
1: 100% (no window start position setting)
0: 1024 cycles (03FFh)
1: 4096 cycles (0FFFh)
0: 8192 cycles (1FFFh)
1: 16384 cycles (3FFFh).
R
b20
0 0 0 1: PCLKB divided by 4
0 1 0 0: PCLKB divided by 64
1 1 1 1: PCLKB divided by 128
0 1 1 0: PCLKB divided by 512
0 1 1 1: PCLKB divided by 2048
1 0 0 0: PCLKB divided by 8192
Other settings are prohibited.
0
0
1
1
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (No window end position setting).
0: 25%
1: 50%
0: 75%
1: 100% (No window start position setting).
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6. Option-Setting Memory
Note 1. The value in a blank product is FFFF FFFFh. It is set to the value written by your application.
IWDTSTRT bit (IWDT Start Mode Select)
The IWDTSTRT bit selects the mode in which the IWDT is activated after a reset (stopped state or activated state).
IWDTTOPS[1:0] bits (IWDT Timeout Period Select)
The IWDTTOPS[1:0] bits specify the timeout period, the time it takes for the down counter to underflow as 128, 512,
1024, or 2048 cycles of the frequency-divided clock set by the IWDTCKS[3:0] bits. The number of clock cycles that the
IWDT takes to underflow after a refresh operation is determined by the combination of the IWDTCKS[3:0] bits and
IWDTTOPS[1:0] bits.
For details, see section 23, Independent Watchdog Timer (IWDT).
IWDTCKS[3:0] bits (IWDT-Dedicated Clock Frequency Division Ratio Select)
The IWDTCKS[3:0] bits specify the division ratio of the prescaler for dividing the frequency of the clock for the IWDT
as 1/1, 1/16, 1/32, 1/64, 1/128, and 1/256. Using this setting combined with the IWDTTOPS[1:0] bit setting, the IWDT
counting period can be set from 128 to 524288 IWDT clock cycles.
For details, see section 23, Independent Watchdog Timer (IWDT).
IWDTRPES[1:0] bits (IWDT Window End Position Select)
The IWDTRPES[1:0] bits specify the position where the window for the down counter ends as 0%, 25%, 50%, or 75% of
the count value. The value of the window end position must be smaller than the value of the window start position,
otherwise only the value for the window start position is valid.
The counter values corresponding to the settings for the start and end positions of the window in the IWDTRPSS[1:0]
and IWDTRPES[1:0] bits, vary with the setting in the IWDTTOPS[1:0] bits.
For details, see section 23, Independent Watchdog Timer (IWDT).
IWDTRPSS[1:0] bits (IWDT Window Start Position Select)
The IWDTRPSS[1:0] bits specify the position where the window for the down counter starts as 25%, 50%, 75%, or
100% of the counted value. The point at which counting starts is 100% and the point at which an underflow occurs is 0%.
The interval between the window starts and ends positions becomes the period in which a refresh is possible. Refresh is
not possible outside this period.
For details, see section 23, Independent Watchdog Timer (IWDT).
IWDTRSTIRQS bit (IWDT Reset Interrupt Request Select)
The IWDTRSTIRQS bit selects the operation on an underflow of the down counter or generation of a refresh error. The
operation is selectable to an independent watchdog timer reset, a non-maskable interrupt request, or an interrupt request.
For details, see section 23, Independent Watchdog Timer (IWDT).
IWDTSTPCTL bit (IWDT Stop Control)
The IWDTSTPCTL bit selects whether to stop counting when entering Sleep mode, Snooze mode, or Software Standby
mode.
For details, see section 23, Independent Watchdog Timer (IWDT).
WDTSTRT bit (WDT Start Mode Select)
The WDTSTRT bit selects the mode in which the WDT is activated after a reset (stopped state or activated in auto-start
mode). When WDT is activated in auto-start mode, the OFS0 register setting for the WDT is valid.
WDTTOPS[1:0] bits (WDT Timeout Period Select)
The WDTTOPS[1:0] bits specify the timeout period, the time it takes for the down counter to underflow, as 1024, 4096,
8192, or 16384 cycles of the frequency-divided clock set in the WDTCKS[3:0] bits. The number of PCLKB cycles that
takes to underflow after a refresh operation is determined by a combination of the WDTCKS[3:0] and WDTTOPS[1:0]
bits.
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6. Option-Setting Memory
For details, see section 22, Watchdog Timer (WDT).
WDTCKS[3:0] bits (WDT Clock Frequency Division Ratio Select)
The WDTCKS[3:0] bits specify the division ratio of the prescaler for dividing the frequency of PCLKB as 1/4, 1/64,
1/128, 1/512, 1/2048, and 1/8192. Using this setting combined with the WDTTOPS[1:0] bit setting, the WDT counting
period can be set from 4096 to 134217728 PCLKB cycles.
For details, see section 22, Watchdog Timer (WDT).
WDTRPES[1:0] bits (WDT Window End Position Select)
The WDTRPES[1:0] bits specify the position where the window on the down counter ends as 0%, 25%, 50%, or 75% of
the counted value. The value of the window end position must be smaller than the value of the window start position,
otherwise only the value for the window start position is valid.
The counter values corresponding to the settings for the start and end positions of the window in the WDTRPSS[1:0] and
WDTRPES[1:0] bits vary with the setting of the WDTTOPS[1:0] bits.
For details, see section 22, Watchdog Timer (WDT).
WDTRPSS[1:0] bits (WDT Window Start Position Select)
The WDTRPSS[1:0] bits specify the position where the window for the down counter starts as 25%, 50%, 75%, or 100%
of the counted value. The point at which counting starts is 100% and the point at which an underflow occurs is 0%. The
interval between the positions where the window starts and ends becomes the period in which a refresh is possible.
Refresh is not possible outside this period.
For details, see section 22, Watchdog Timer (WDT).
WDTRSTIRQS bit (WDT Reset Interrupt Request Select)
The WDTRSTIRQS bit selects the operation on an underflow of the down-counter or generation of a refresh error. The
operation is selectable to a watchdog timer reset, a non-maskable interrupt request, or an interrupt request.
For details, see section 22, Watchdog Timer (WDT).
WDTSTPCTL bit (WDT Stop Control)
The WDTSTPCTL bit specifies whether to stop counting when entering Sleep mode.
For details, see section 22, Watchdog Timer (WDT).
6.2.2
Option Function Select Register 1 (OFS1)
Address(es): OFS1 0000 0404h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
b5
b4
b3
b2
b1
b0
LVDAS
—
—
The value set by the user*1
Value after reset:
b15
—
b14
b13
b12
HOCOFRQ1[2:0]
b11
—
b10
—
b9
b8
b7
b6
—
HOCO
EN
—
—
VDSEL1[2:0]
The value set by the user*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b2
LVDAS
Voltage Detection 0
Circuit Start
0: Enable voltage monitor 0 reset after a reset
1: Disable voltage monitor 0 reset after a reset.
R
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6. Option-Setting Memory
Bit
Symbol
Bit name
Description
R/W
b5 to b3
VDSEL1[2:0]
Voltage Detection 0
Level Select
b5
R
b7, b6
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b8
HOCOEN
HOCO Oscillation
Enable
0: Enable HOCO oscillation after a reset
1: Disable HOCO oscillation after a reset.
R
b11 to b9
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b14 to b12
HOCOFRQ1[2:0]
HOCO Frequency
Setting 1
b14
R
b31 to b15
—
Reserved
When read, these bits return the written value. The write value
should be 1.
b3
0 0 0: Selects 3.84 V
0 0 1: Selects 2.82 V
0 1 0: Selects 2.51 V
0 1 1: Selects 1.90 V
1 0 0: Selects 1.70 V.
Other settings are prohibited.
b12
0 0 0: 24 MHz
0 1 0: 32 MHz
1 0 0: 48 MHz
1 0 1: 64 MHz
Other settings are prohibited.
R
Note 1. The value in a blank product is FFFF FFFFh. It is set to the value written by your application.
LVDAS bit (Voltage Detection 0 Circuit Start)
The LVDAS bit selects whether the voltage monitor 0 reset is enabled or disabled after a reset.
VDSEL1[2:0] bits (Voltage Detection 0 Level Select)
The VDSEL1[2:0] bits select the voltage detection level of the voltage detection 0 circuit.
HOCOEN bit (HOCO Oscillation Enable)
The HOCOEN bit selects whether the HOCO oscillation is enabled or disabled after a reset. Setting the HOCOEN bit to
0 allows the HOCO oscillation to start before the CPU starts operation, which reduces the wait time for oscillation
stabilization.
Note:
When the HOCOEN bit is set to 0, the system clock source is not switched to HOCO. The system clock source is
only switched to HOCO by setting the clock source select bits (SCKSCR.CKSEL[2:0]). To use the HOCO clock,
set the OFS1.HOCOFRQ1 bit to an optimum value.
After a reset release, operation is in the low-voltage mode and therefore HOCOCR.HCSTP must be set immediately to 0.
HOCOFRQ1[2:0] bits (HOCO Frequency Setting 1)
The HOCOFRQ1[2:0] bits select the HOCO frequency after a reset as 24, 32, 48, or 64 MHz.
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6.2.3
6. Option-Setting Memory
Access Window Setting Control Register (AWSC)
Address(es): AWSC 0101 0008h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
The value set by the user
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
FSPR
—
—
—
—
—
BTFLG
—
—
—
—
—
—
—
—
The value set by the user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b8
BTFLG
Startup Area Select Flag
This bit specifies whether the address of the startup area is
exchanged for the boot swap function.
0: First 8-KB area (0000 0000h to 0000 1FFFh) and second 8-KB
area (0000 2000h to 0000 3FFFh) are exchanged
1: First 8-KB area (0000 0000h to 0000 1FFFh) and second 8-KB
area (0000 2000h to 0000 3FFFh) are not exchanged.
R
b13 to b9
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b14
FSPR
Protection of Access Window
and Startup Area Select
Function
This bit controls the programming/erase protection for the access
window, the Startup Area Select Flag (BTFLG), and the
temporary boot swap. When this bit is set to 0, it cannot be
changed to 1.
0: Executing the configuration setting command for programming
the access window (FAWE [11:0], FAWS [11:0] and the Startup
Area Select flag (BTFLG) is invalid.
1: Executing the configuration setting command for programming
the access window (FAWE [11:0], FAWS [11:0] and the Startup
Area Select flag (BTFLG) is valid.
R
b31 to b15
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
6.2.4
Access Window Setting Register (AWS)
Address(es): AWS 0101 0010h
b31
b30
b29
b28
—
—
—
—
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b4
b3
b2
b1
b0
FAWE[11:0]
The value set by the user
Value after reset:
b15
b14
b13
b12
—
—
—
—
b11
b10
b9
b8
b7
b6
b5
FAWS[11:0]
The value set by the user
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b11 to b0
FAWS[11:0]
Access Window Start Block
Address
These bits specify the start block address for the access window.
They do not represent the block number of the access window.
The access window is only valid in the program flash area.
The block address specifies the first address of the block and
consists of the address bits [21:10].
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6. Option-Setting Memory
Bit
Symbol
Bit name
Description
R/W
b15 to b12
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
b27 to b16
FAWE[11:0]
Access Window End Block
Address
These bits specify the end block address for the access window.
They do not represent the block number of the access window.
The access window is only valid in the program flash area. The
end block address for the access window is the next block to the
region acceptable for programming and erasure defined by the
access window. The block address specifies the first address of
the block and consists of the address bits [21:10].
R
b31 to b28
—
Reserved
When read, these bits return the written value. The write value
should be 1.
R
Issuing the program or erase command to an area outside the access window causes a command-locked state. The access
window is only valid in the program flash area. The access window provides protection in self-programming mode, serial
programming mode, and on-chip debug mode. The access window can be locked by the FSPR bit.
The access window is specified by both the FAWS bits and the FAWE bits. The following describes how to set the FAWS
bits and the FAWE bits.
FAWE = FAWS: The P/E command is allowed to execute in the full program flash area.
FAWE > FAWS: The P/E command is only allowed to execute in the window from the block pointed to by the FAWS bits
to the block one lower than the block pointed to by the FAWE bits.
FAWE < FAWS: The P/E command is not allowed to execute in the program flash area.
Address
P/E
…
Block 7
(FAWE = 007h)
Protected
area
Block 6
Access
Window
Block 5
Non-protected
area
Block 4
(FAWS = 004h)
Block 3
Block 2
Block 1
Protected
area
Block 0
Figure 6.2
6.2.5
Access window overview
OCD/Serial Programmer ID Setting Register (OSIS)
This register stores the ID for ID code protection of the OCD/serial programmer. When connecting the OCD/serial
programmer, write values so that the MCU can determine whether to permit the connection. Use this register to check
whether a code transmitted from the OCD/serial programmer matches the ID code in the option-setting memory.
When the ID codes match, connection of the OCD/serial programmer is permitted, if not, connection with the OCD/
serial programmer is not possible. The OSIS register must be set in 32-bit units.
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6. Option-Setting Memory
Address(es): OSIS 0101 0018h, OSIS 0101 0020h, OSIS 0101 0028h, OSIS 0101 0030h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b5
b4
b3
b2
b1
b0
The value set by the user
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
The value set by the user
Value after reset:
These fields hold the ID for use in ID authentication for the OCD/serial programmer.
ID code bit [127] and bit [126] determine whether ID code protection is enabled and the method of authentication to use
with the host. Table 6.1 shows how ID code determines the method of authentication.
Table 6.1
Specifications for ID code protection
Operating mode on
boot up
ID code
State of protection
Serial programming
mode (SCI boot mode)
FFh, …, FFh
(all bytes FFh)
Protection disabled
The ID code is not checked, ID code always matches,
and connection to programmer or on-chip debugger is
permitted.
Bit [127] = 1, bit [126] = 1,
and at least one of the 16
bytes is not FFh
Protection enabled
Matching ID code = Authentication is complete and
connection with the programmer or the on-chip
debugger is permitted.
Mismatching ID code = Transition to the ID code
protection wait state.
When the ID code sent from the programmer or the onchip debugger is “ALeRASE” in ASCII code
(414C_6552_4153_45FF_FFFF_FFFF_FFFF_FFFFh),
the content of the user flash (code and data) area, and
configuration area are erased.
However, forced erasure is not executed when the
FSPR bit is 0.
On-chip debug mode
(SWD boot mode)
6.3
6.3.1
Operations on connection to programmer or onchip debugger
Bit [127] = 1 and bit [126] = 0 Protection enabled
Matching ID code = Authentication is complete and
connection with the programmer or the on-chip
debugger is permitted.
Mismatching ID code = Transition to the ID code
protection wait state.
Bit [127] = 0
The ID code is not checked, the ID code is always mismatching, and connection to the programmer or the onchip debugger is prohibited.
Protection enabled
Setting Option-Setting Memory
Allocation of Data in Option-Setting Memory
Programming data is allocated to the addresses in the option-setting memory shown in Figure 6.1. The allocated data is
used by tools such as a flash programming software or an on-chip debugger.
Note:
6.3.2
Programming formats vary depending on the compiler. See the compiler manual for details.
Setting Data for Programming Option-Setting Memory
Allocating data according to the procedure described in section 6.3.1, Allocation of Data in Option-Setting Memory,
alone does not actually write the data to the option-setting memory. You must also follow one of the actions described in
this section.
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(1)
6. Option-Setting Memory
Changing the Option-Setting Memory by Self-Programming
Use the programming command to write data to the program flash area. Use the configuration setting command to write
data to the option-setting memory in the configuration setting area. In addition, use the startup area select function to
safely update the boot program that includes the option-setting memory.
For details of the programming command, the configuration setting command and the startup area select function, see
section 37, Flash Memory.
(2)
Debugging through an OCD or Programming by a Flash Writer
This procedure depends on the tool in use, see the tool manual for details. The MCU provides two setting procedures:
Read the data allocated as described in section 6.3.1, Allocation of Data in Option-Setting Memory, from an object
file or Motorola S-format file generated by the compiler, and write the data to the MCU.
Use the GUI interface of the tool to program the same data as allocated in section 6.3.1, Allocation of Data in
Option-Setting Memory.
6.4
6.4.1
Usage Note
Data for Programming Reserved Areas and Reserved Bits in the Option-Setting
Memory
When reserved areas and reserved bits in the option-setting memory are within the scope of programming, write 1 to all
bits of reserved areas and all reserved bits. If 0 is written to these bits, normal operation cannot be guaranteed.
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7. Low Voltage Detection (LVD)
7.
Low Voltage Detection (LVD)
7.1
Overview
The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin, and the detection level can be
selected using a software program. The LVD module consists of three separate voltage level detectors, voltage detection
0, 1, and 2, which measure the voltage level input to the VCC pin. LVD voltage detection registers allow your application
to configure detection of VCC changes at various voltage thresholds.
Each voltage level detector has a voltage monitor associated with it, for example voltage monitor 0, 1, and 2. Voltage
monitor registers are used to configure the LVD to trigger an interrupt, event link output, or reset when the thresholds are
crossed.
Table 7.1 lists the LVD specifications and Figure 7.1 shows a block diagram of voltage detection 0, 1, and 2. Figure 7.2
shows a block diagram of the voltage monitor 1 interrupt and reset circuit, and Figure 7.3 shows a block diagram of the
voltage monitor 2 interrupt and reset circuit.
Table 7.1
LVD specifications
Parameter
VCC
monitoring
Process upon
voltage
detection
Voltage monitor 0
Voltage monitor 1
Voltage monitor 2
Monitored
voltage
Vdet0
Vdet1
Vdet2
Detected
event
Voltage falls past Vdet0
Voltage rises or falls past Vdet1
Voltage rises or falls past Vdet2
Detection
voltage
Selectable from five different
levels using
OFS1.VDSEL1[2:0] bits
Selectable from 16 different levels
using LVDLVLR.LVD1LVL[4:0] bits
Selectable from four different
levels using
LVDLVLR.LVD2LVL[2:0] bits
Monitor flag
None
LVD1SR.MON flag: Monitors
whether voltage is higher or lower
than Vdet1
LVD2SR.MON flag: Monitors
whether voltage is higher or lower
than Vdet2
LVD1SR.DET flag: Vdet1 crossing
detection
LVD2SR.DET flag: Vdet2 crossing
detection
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Reset when Vdet0 > VCC
CPU restart after specified
time with VCC > Vdet0
Reset when Vdet1 > VCC
CPU restart timing selectable:
after specified time with VCC >
Vdet1 or Vdet1 > VCC
Reset when Vdet2 > VCC
CPU restart timing selectable:
after specified time with VCC >
Vdet2 or Vdet2 > VCC
No interrupt
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Non-maskable interrupt or
maskable interrupt selectable
Non-maskable interrupt or
maskable interrupt selectable
Interrupt request issued when
Vdet1 > VCC or VCC > Vdet1
Interrupt request issued when
Vdet2 > VCC or VCC > Vdet2
Available
Output of event signals on
detection of Vdet1 crossings
Available
Output of event signals on
detection of Vdet2 crossings
Reset
Interrupt
Event linking
None
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7. Low Voltage Detection (LVD)
OFS1.LVDAS
VCC
Voltage detection 0 reset signal
+
-
Level selection
Internal reference voltage
circuit
(for detecting Vdet0)
OFS1.VDSEL1[2:0]
Vdet0
LVCMPCR.LVD1E
LVD1CR0.CMPE
Voltage detection 1 signal
+
Internal reference voltage
(for detecting Vdet1)
Level selection
circuit
- Vdet1
LVDLVLR.LVD1LVL[4:0]
LVCMPCR.LVD2E
LVD2CR0.CMPE
Voltage detection 2 signal
+
Internal reference voltage
(for detecting Vdet2)
- Vdet2
Level selection
circuit
LVDLVLR.LVD2LVL[2:0]
Note:
Figure 7.1
See section 6, Option-Setting Memory.
Voltage detection 0, 1, and 2 block diagram
Voltage monitor 1
The setting of the LVD1SR.DET bit is 0
if 0 (undetected) is written in the program
Voltage detection 1
LVD1SR.MON
VCC
LVCMPCR.LVD1E
b1
LVD1CR0.CMPE
+
Internal reference
voltage
(for detection of
Vdet1)
Level
selection
Voltage
detection 1
signal
Fixed
period
negation
Edge
selection
circuit
LVDLVLR.LVD1LVL[4:0]
Voltage detection 1 signal is high when
the LVCMPCR.LVD1E bit is 0
(disabled)
LVD1CR0.RIE
LVD1CR0.RI
LVD1CR0.RN = 0
LVD1CR0.
RN = 1
LVD1SR.
DET
LVD1CR1.IDTSEL[1:0]
Voltage monitor 1
reset signal
(active-low)
Voltage monitor 1
non-maskable interrupt
signal
LVD1CR1.IRQSEL
Voltage monitor 1
interrupt signal
Event
Figure 7.2
Voltage monitor 1 interrupt/reset circuit block diagram
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7. Low Voltage Detection (LVD)
Voltage monitor 2
The setting of the LVD1SR.DET bit is 0
if 0 (undetected) is written by the program
Voltage detection 2
LVD2SR.MON
VCC
LVCMPCR.LVD2E
LVD2CR0.CMPE
b1
+
Fixed
period
negation
Voltage
detection 2
signal
-
Internal reference
voltage
Level
(for detection of
selection
Vdet2)
LVD2CR0.RIE
LVD2CR0.RI
LVD2CR0.RN = 0
Edge
selection
circuit
LVDLVLR.LVD2LVL[2:0]
Voltage detection 2 signal is high when the
setting of the LVCMPCR.LVD2E bit is 0
(disabled)
LVD2CR1.IDTSEL[1:0]
LVD2CR0.
RN = 1
LVD2SR.
DET
Voltage monitor 2
reset signal
(active-low)
Voltage monitor 2
non-maskable
interrupt signal
LVD2CR1.IRQSEL
Voltage monitor 2
interrupt signal
Event
Figure 7.3
7.2
Voltage monitor 2 interrupt/reset circuit block diagram
Register Descriptions
7.2.1
Voltage Monitor 1 Circuit Control Register 1 (LVD1CR1)
Address(es): SYSTEM.LVD1CR1 4001 E0E0h
Value after reset:
b7
b6
b5
b4
b3
b2
—
—
—
—
—
IRQSE
L
0
0
0
0
0
0
b1
b0
IDTSEL[1:0]
0
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
IDTSEL[1:0]
Voltage Monitor 1 Interrupt
Generation Condition Select
b1 b0
R/W
b2
IRQSEL
Voltage Monitor 1 Interrupt Type
Select
0: Non-maskable interrupt
1: Maskable interrupt*1.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: When VCC Vdet1 (rise) is detected
1: When VCC < Vdet1 (fall) is detected
0: When fall and rise are detected
1: Settings prohibited.
Note:
When enabling maskable interrupts, do not change the value of the NMIER.LVD1EN bit in the ICU from the reset
state.
Note 1. Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
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7.2.2
7. Low Voltage Detection (LVD)
Voltage Monitor 1 Circuit Status Register (LVD1SR)
Address(es): SYSTEM.LVD1SR 4001 E0E1h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MON
DET
0
0
0
0
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
DET
Voltage Monitor 1 Voltage Change
Detection Flag
0: Not detected
1: Vdet1 passage detected.
*Note:
R(/W)
b1
MON
Voltage Monitor 1 Signal Monitor Flag
0: VCC < Vdet1
1: VCC Vdet1 or MON is disabled.
R
b7 to b2
—
Reserved
These bits are read as 0. The write value should be
0.
R/W
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Note 1. Only 0 can be written to this bit. After writing 0 to this bit, 2 system clock cycles are required for the bit to be read
as 0.
DET flag (Voltage Monitor 1 Voltage Change Detection Flag)
The DET flag is enabled when the LVCMPCR.LVD1E bit is 1 (voltage detection 1 circuit enabled) and the
LVD1CR0.CMPE bit is 1 (voltage monitor 1 circuit comparison result output enabled).
Set the DET flag to 0 after LVD1CR0.RIE is set to 0 (disabled). LVD1CR0.RIE can be set to 1 (enabled) after 2 or more
PCLKB cycles have elapsed.
A wait time of 2 or more PCLKB cycles might be required, depending on the number of PCLKB cycles required to read
a given I/O register.
MON Flag (Voltage Monitor 1 Signal Monitor Flag)
The MON flag is enabled when the LVCMPCR.LVD1E bit is 1 (voltage detection 1 circuit enabled) and the
LVD1CR0.CMPE bit is 1 (voltage monitor 1 circuit comparison result output enabled).
7.2.3
Voltage Monitor 2 Circuit Control Register 1 (LVD2CR1)
Address(es): SYSTEM.LVD2CR1 4001 E0E2h
Value after reset:
b7
b6
b5
b4
b3
b2
—
—
—
—
—
IRQSE
L
0
0
0
0
0
0
b1
b0
IDTSEL
[1:0]
0
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
IDTSEL [1:0]
Voltage Monitor 2 Interrupt
Generation Condition Select
b1 b0
R/W
b2
IRQSEL
Voltage Monitor 2 Interrupt Type
Select
0: Non-maskable interrupt
1: Maskable interrupt*1.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: When VCC Vdet2 (rise) is detected
1: When VCC < Vdet2 (fall) is detected
0: When fall and rise are detected
1: Settings prohibited.
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Note 1. When enabling maskable interrupts, do not change the value of the NMIER.LVD1EN bit in the ICU from the reset
state.
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7.2.4
7. Low Voltage Detection (LVD)
Voltage Monitor 2 Circuit Status Register (LVD2SR)
Address(es): SYSTEM.LVD2SR 4001 E0E3h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MON
DET
0
0
0
0
0
0
1
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
DET
Voltage Monitor 2 Voltage Change
Detection Flag
0: Not detected
1: Vdet2 passage detected.
R(/W)
*1
b1
MON
Voltage Monitor 2 Signal Monitor
Flag
0: VCC < Vdet2
1: VCC Vdet2 or MON is disabled.
R
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register
Note 1. Only 0 can be written to this bit. After the 0 write, 2 system clock cycles are required for the bit to be read as 0.
DET flag (Voltage Monitor 2 Voltage Change Detection Flag)
The DET flag is enabled when the LVCMPCR.LVD2E bit is 1 (voltage detection 2 circuit enabled) and the
LVD2CR0.CMPE bit is 1 (voltage monitor 2 circuit comparison result output enabled).
Set the DET flag to 0 after LVD2CR0.RIE is set to 0 (disabled). LVD2CR0.RIE can be set to 1 (enabled) after 2 or more
PCLKB cycles have elapsed.
A wait time of 2 or more PCLKB cycles might be required, depending on the number of PCLKB cycles required to read
a given I/O register.
MON flag (Voltage Monitor 2 Signal Monitor Flag)
The MON flag is enabled when the LVCMPCR.LVD2E bit is 1 (voltage detection 2 circuit enabled) and the
LVD2CR0.CMPE bit is 1 (voltage monitor 2 circuit comparison result output enabled).
7.2.5
Voltage Monitor Circuit Control Register (LVCMPCR)
Address(es): SYSTEM.LVCMPCR 4001 E417h
b7
—
b6
LVD2E LVD1E
0
Value after reset:
b5
0
0
b4
b3
b2
b1
b0
—
—
—
—
—
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
LVD1E
Voltage Detection 1 Enable
0: Disable voltage detection 1 circuit
1: Enable voltage detection 1 circuit.
R/W
b6
LVD2E
Voltage Detection 2 Enable
0: Disable voltage detection 2 circuit
1: Enable voltage detection 2 circuit.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
LVD1E bit (Voltage Detection 1 Enable)
When using voltage detection 1 interrupt/reset or the LVD1SR.MON bit, set the LVD1E bit to 1. The voltage detection 1
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7. Low Voltage Detection (LVD)
circuit starts when td(E-A) elapses after the LVD1E bit value is changed from 0 to 1.
LVD2E bit (Voltage Detection 2 Enable)
When using voltage detection 2 interrupt/reset or the LVD2SR.MON bit, set the LVD2E bit to 1. The voltage detection 2
circuit starts when td(E-A) elapses after the LVD2E bit value is changed from 0 to 1.
7.2.6
Voltage Detection Level Select Register (LVDLVLR)
Address(es): SYSTEM.LVDLVLR 4001 E418h
b7
b6
b5
b4
b3
LVD2LVL[2:0]
Value after reset
0
0
b2
b1
b0
1
1
LVD1LVL[4:0]
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
LVD1LVL[4:0]
Voltage Detection 1 Level Select
(Standard voltage during drop in
voltage)
b4
R/W
b7 to b5
LVD2LVL[2:0]
Voltage Detection 2 Level Select
(Standard voltage during drop in
voltage)
b7
Note:
b0
0 0 0 0 0: 4.29 V (Vdet1_0)
0 0 0 0 1: 4.14 V (Vdet1_1)
0 0 0 1 0: 4.02 V (Vdet1_2)
0 0 0 1 1: 3.84 V (Vdet1_3)
0 0 1 0 0: 3.10 V (Vdet1_4)
0 0 1 0 1: 3.00 V (Vdet1_5)
0 0 1 1 0: 2.90 V (Vdet1_6)
0 0 1 1 1: 2.79 V (Vdet1_7)
0 1 0 0 0: 2.68 V (Vdet1_8)
0 1 0 0 1: 2.58 V (Vdet1_9)
0 1 0 1 0: 2.48 V (Vdet1_A)
0 1 0 1 1: 2.20 V (Vdet1_B)
0 1 1 0 0: 1.96 V (Vdet1_C)
0 1 1 0 1: 1.86 V (Vdet1_D)
0 1 1 1 0: 1.75 V (Vdet1_E)
0 1 1 1 1: 1.65 V (Vdet1_F).
Other settings are prohibited.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b5
0: 4.29 V (Vdet2_0)
1: 4.14 V (Vdet2_1)
0: 4.02 V (Vdet2_2)
1: 3.84 V (Vdet2_3)
0: Setting prohibited
1: Setting prohibited
0: Setting prohibited
1: Setting prohibited.
R/W
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
The contents of the LVDLVLR register can only be changed if the LVCMPCR.LVD1E and LVCMPCR.LVD2E bits
(voltage detection n circuit disable, n = 1, 2) are both 0. Do not set LVD detectors 1 and 2 to the same voltage detection
level.
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7.2.7
7. Low Voltage Detection (LVD)
Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0)
Address(es): SYSTEM.LVD1CR0 4001 E41Ah
b7
b6
b5
b4
b3
b2
b1
b0
RN
RI
—
—
—
CMPE
—
RIE
1
0
0
0
x
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
RIE
Voltage Monitor 1 Interrupt/Reset
Enable
0: Disable
1: Enable.
R/W
b1
—
Reserved
The read value is 0. The write value should be 0.
R/W
b2
CMPE
Voltage Monitor 1 Circuit
Comparison Result Output Enable
0: Disable voltage monitor 1 circuit comparison result output
1: Enable voltage monitor 1 circuit comparison result output.
R/W
b3
—
Reserved
The read value is undefined. The write value should be 1.
R/W
b5 to
b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
RI
Voltage Monitor 1 Circuit Mode
Select
0: Generate voltage monitor 1 interrupt on Vdet1 passage
1: Enable voltage monitor 1 reset when the voltage falls to and
below Vdet1.
R/W
b7
RN
Voltage Monitor 1 Reset Negate
Select
0: Negate after a stabilization time (tLVD1) when VCC > Vdet1 is
detected
1: Negate after a stabilization time (tLVD1) on assertion of the
LVD1 reset.
R/W
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
RIE bit (Voltage Monitor 1 Interrupt/Reset Enable)
The RIE bit enables or disables voltage monitor 1 interrupt and voltage monitor 1 reset. Set this bit to ensure that neither
a voltage monitor 1 interrupt nor a voltage monitor 1 reset is generated during programming or erasure of the flash
memory.
RN bit (Voltage Monitor 1 Reset Negate Select)
If the RN bit is to be set to 1 (negation follows a stabilization time on assertion of the LVD1 reset signal), set the
MOCOCR.MCSTP bit to 0 (the MOCO operates). Additionally, if a transition to software standby is to be made, the only
possible value for the RN bit is 0 (negation follows a stabilization time when VCC > Vdet1 is detected). Do not set the
RN bit to 1 (negation follows a stabilization time after assertion of the LVD1 reset signal) when this is the case.
7.2.8
Voltage Monitor 2 Circuit Control Register 0 (LVD2CR0)
Address(es): SYSTEM.LVD2CR0 4001 E41Bh
b7
b6
b5
b4
b3
b2
b1
b0
RN
RI
—
—
—
CMPE
—
RIE
1
0
0
0
x
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
RIE
Voltage Monitor 2 Interrupt/Reset
Enable
0: Disable
1: Enable.
R/W
b1
—
Reserved
The read value is 0. The write value should be 0.
R/W
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7. Low Voltage Detection (LVD)
Bit
Symbol
Bit name
Description
R/W
b2
CMPE
Voltage Monitor 2 Circuit
Comparison Result Output Enable
0: Disable voltage monitor 2 circuit comparison result
output
1: Enable voltage monitor 2 circuit comparison result
output.
R/W
b3
—
Reserved
The read value is undefined. The write value should be 1.
R/W
b5 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
RI
Voltage Monitor 2 Circuit Mode
Select
0: Generate voltage monitor 2 interrupt on Vdet2 passage
1: Enable voltage monitor 2 reset when the voltage falls to
and below Vdet2.
R/W
b7
RN
Voltage Monitor 2 Reset Negate
Select
0: Negate after a stabilization time (tLVD2) when VCC >
Vdet2 is detected
1: Negate after a stabilization time (tLVD2) on assertion of
the LVD2 reset.
R/W
Note:
Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
RIE bit (Voltage Monitor 2 Interrupt/Reset Enable)
The RIE bit enables or disables the voltage monitor 2 interrupt and voltage monitor 2 reset. Set this bit to ensure that
neither a voltage monitor 2 interrupt nor a voltage monitor 2 reset is generated during programming or erasure of the
flash memory.
RN bit (Voltage Monitor 2 Reset Negate Select)
If the RN bit is to be set to 1 (negation follows a stabilization time on assertion of the LVD2 reset signal), set the
MOCOCR.MCSTP bit to 0 (the MOCO operates). Additionally, if a transition to software standby is to be made, the only
possible value for the RN bit is 0 (negation follows a stabilization time when VCC > Vdet2 is detected). Do not set the
RN bit to 1 (negation follows a stabilization time on assertion of the LVD2 reset signal) when this is the case.
7.3
7.3.1
VCC Input Voltage Monitor
Monitoring Vdet0
The comparison results from voltage monitor 0 are not available for reading.
7.3.2
Monitoring Vdet1
Table 7.2 shows the procedure to set up monitoring against Vdet1. After the settings are complete, the comparison results
from voltage monitor 1 can be monitored with the LVD1SR.MON flag.
Table 7.2
Procedure to set up monitoring against Vdet1
Step
Monitoring the comparison results from voltage monitor 1
Setting the voltage
detection 1 circuit
Enabling output
7.3.3
1
Set LVCMPCR.LVD1E = 0 to disable voltage detection 1 before writing to LVDLVLR register.
2
Select the detection voltage by setting the LVDLVLR.LVD1LVL[4:0] bits.
3
Set LVCMPCR.LVD1E = 1 to enable voltage detection 1.
4
Wait for at least td(E-A) for the LVD operation stabilization time after LVD is enabled.
5
Set LVD1CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 1.
Monitoring Vdet2
Table 7.3 shows the procedure to set up monitoring against Vdet2. After the settings are complete, the comparison results
from voltage monitor 2 can be monitored with the LVD2SR.MON flag.
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Table 7.3
7. Low Voltage Detection (LVD)
Procedure to set up monitoring against Vdet2
Step
Monitoring the comparison results from voltage monitor 2
Setting the voltage
detection 2 circuit
Enabling output
7.4
1
Set LVCMPCR.LVD2E = 0 to disable voltage detection 2 before writing to the LVDLVLR register.
2
Select the detection voltage by setting the LVDLVLR.LVD2LVL[2:0] bits.
3
Set LVCMPCR.LVD2E = 1 to enable the voltage detection 2 circuit.
4
Wait for at least td(E-A) for the LVD operation stabilization time after LVD is enabled.
5
Set LVD2CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 2.
Reset from Voltage Monitor 0
When using the reset from voltage monitor 0, clear the OFS1.LVDAS bit to 0 to enable the voltage monitor 0 reset after
a reset). However, at boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS
bit.
Figure 7.4 shows an example of operations for a voltage monitor 0 reset.
*3
Vdet0*1
VPOR*1
External voltage VCC
Power-on reset state
Voltage-monitor 0 reset state
RES pin
POR detection signal
(active-low)
Set by OFS1.LVDAS
LVD0 enable/disable
signal (active-low)
Voltage detection 0
signal (active-low)
Internal reset signal
(active-low)
tPOR*2
RSTSR0.PORF
tLVD0*2
RES pin reset
RSTSR0.LVD0RF
Note:
Note 1.
Note 2.
Note 3.
Figure 7.4
For details of the electrical characteristics, see section 41, Electrical Characteristics.
VPOR indicates the detection level for a power-on reset and Vdet0 indicates the detection level for a voltage monitor 0
reset.
tPOR indicates the period of a power-on reset and tLVD0 indicates the period of a voltage monitor 0 reset.
At power-on, raise VCC to the minimum guaranteed voltage before releasing the POR reset.
Example of voltage monitor 0 reset operation
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7.5
7. Low Voltage Detection (LVD)
Interrupt and Reset from Voltage Monitor 1
An interrupt or reset can be generated in response to the comparison results from the voltage monitor 1 circuit.
Table 7.4 shows the procedure for setting bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so
that voltage monitor operates. Table 7.5 shows the procedure for setting bits related to the voltage monitor 1 interrupt and
voltage monitor 1 reset so that voltage monitor stops. Figure 7.5 shows an example of operations for a voltage monitor 1
interrupt. For the operation of the voltage monitor 1 reset, see Figure 5.2 in section 5, Resets.
When using the voltage monitor 1 circuit in Software Standby mode, set up the circuit with the following procedures.
(1)
Setting in Software Standby mode
When VCC > Vdet1 is detected, negate the voltage monitor 1 reset signal (LVD1CR0.RN = 0) following a
stabilization time.
Table 7.4
Procedure for setting bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so
that voltage monitoring operates
Voltage monitor 1 interrupt
(voltage monitor 1 ELC event output)
Step
Setting the voltage
detection 1 circuit
Setting the voltage
monitor 1 interrupt or
reset
Enabling output
Voltage monitor 1 reset
1
Set LVCMPCR.LVD1E = 0 to disable voltage detection 1 before writing to the LVDLVLR register.
2
Select the detection voltage by setting the LVDLVLR.LVD1LVL[3:0] bits.
3
Set LVCMPCR.LVD1E = 1 to enable the voltage detection 1 circuit.
4
Wait for at least td(E-A) for the LVD operation stabilization time after LVD is enabled*1.
5
Set LVD1CR0.RI = 0 to select the voltage monitor
1 interrupt.
Set LVD1CR0.RI = 1 to select the voltage
monitor 1 reset
Select the type of the reset negation by setting
the LVD1CR0.RN bit.
6
Select the timing of interrupt requests by setting
the LVD1CR1.IDTSEL[1:0] bits
Select the type of interrupt by setting the
LVD1CR1.IRQSEL bit.
—
7
Set LVD1SR.DET = 0.
8
Set LVD1CR0.RIE = 1 to enable the voltage monitor 1 interrupt or reset*2.
9
Set LVD1CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 1.
Note 1. Steps 5 to 8 can be performed during the wait time of step 4. For details of td(E-A), see section 41, Electrical
Characteristics.
Note 2. Step 8 is not required if only the ELC event signal is to be output.
Table 7.5
Procedure for setting bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so
that voltage monitoring stops
Step
Voltage monitor 1 interrupt (voltage monitor 1 ELC event output), voltage monitor 1 reset
Settings to stop
enabling of output
1
Set LVD1CR0.CMPE = 0 to disable output of the results of comparison by voltage monitor 1.
2
Set LVD1CR0.RIE = 0 to disable the voltage monitor 1 interrupt or reset*1.
Stopping the voltage
detection 1 circuit
3
Set LVCMPCR.LVD1E = 0 to disable the voltage detection 1 circuit.
Note 1. Step 2 is not required if only the ELC event signal is to be output.
If the voltage monitor 1 interrupt or reset setting is to be made again after it is used and stopped once, omit the following
steps in the procedures for stopping and setting, depending on the conditions:
Setting or stopping the voltage detection 1 circuit is not required if the settings for the voltage detection 1 circuit do
not change
Setting the voltage monitor 1 interrupt or reset is not required if the settings for the voltage monitor 1 interrupt or
voltage monitor 1 reset do not change.
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7. Low Voltage Detection (LVD)
Figure 7.5 shows an example of the voltage monitor 1 interrupt operation.
VCC
Vdet1
Lower limit on VCC voltage (VCCmin)*1
LVD1SR.MON
Set to 0 by software
LVD1SR.DET bit
LVD1CR1.IDTSEL[1:0] bits are
set to 10b (when drop and rise
are detected)
Voltage monitor 1
interrupt request
Set to 0 by software
LVD1SR.DET bit
LVD1CR1.IDTSEL[1:0] bits are
set to 00b (when rise is detected)
Voltage monitor 1
interrupt request
Set to 0 by software
LVD1SR.DET bit
LVD1CR1.IDTSEL[1:0] bits are
set to 01b (when drop is
detected)
Voltage monitor 1
interrupt request
Note 1. When the voltage monitor 0 reset is not in use, VCC VCCmin.
Figure 7.5
7.6
Voltage monitor 1 interrupt operation example
Interrupt and Reset from Voltage Monitor 2
An interrupt or reset can be generated in response to the comparison results from the voltage monitor 2 circuit.
Table 7.6 shows the procedure for setting bits related to the voltage monitor 2 interrupt and voltage monitor 2 reset so
that voltage monitor operates. Table 7.7 shows the procedure for setting bits related to the voltage monitor 2 interrupt and
voltage monitor 2 reset so that voltage monitor stops. Figure 7.6 shows an example of operations for a voltage monitor 2
interrupt. For the operation of the voltage monitor 2 reset, see Figure 5.2 in section 5, Resets.
When using the voltage monitor 2 circuit in Software Standby mode, set up the circuit with the following procedures.
(1)
Setting in Software Standby mode
When VCC > Vdet2 is detected, clear the LVDD2CR0.RN bit (LVD2CR0.RN = 0) following a stabilization time.
Table 7.6
Procedure for setting bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that
voltage monitor operates (1 of 2)
Voltage monitor 2 interrupt
(voltage monitor 2 ELC event output)
Step
Setting the voltage
detection 2 circuit
Voltage monitor 2 reset
1
Set LVCMPCR.LVD2E = 0 to disable voltage detection 2 before writing to the LVDLVLR register.
2
Select the detection voltage by setting the LVDLVLR.LVD2LVL[2:0] bits.
3
Set LVCMPCR.LVD2E = 1 to enable the voltage detection 2 circuit.
4
Wait for at least td(E-A) for the LVD operation stabilization time after LVD is enabled*1.
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Table 7.6
7. Low Voltage Detection (LVD)
Procedure for setting bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that
voltage monitor operates (2 of 2)
Voltage monitor 2 interrupt
(voltage monitor 2 ELC event output)
Step
Setting the voltage
monitor 2 interrupt or
reset
Enabling output
Voltage monitor 2 reset
5
Set LVD2CR0.RI = 0 to select the voltage monitor
2 interrupt.
Set LVD2CR0.RI = 1 to selecting the voltage
monitor 2 reset
Select the type of the reset negation by setting
the LVD2CR0.RN bit.
6
Select the timing of interrupt requests by setting
the LVD2CR1.IDTSEL[1:0] bits
Select the type of interrupt by setting the
LVD2CR1.IRQSEL bit.
—
7
Set LVD2SR.DET = 0.
8
Set LVD2CR0.RIE = 1 to enable the voltage monitor 2 interrupt or reset*2.
9
Set LVD2CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 2.
Note 1. Steps 5 to 8 can be performed during the wait time of step 4. For details of td(E-A), see section 41, Electrical
Characteristics.
Note 2. Step 8 is not required if only the ELC event signal is to be output.
Table 7.7
Procedure for setting bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that
voltage monitor stops
Step
Voltage monitor 2 interrupt (voltage monitor 2 ELC event output), voltage monitor 2 reset
Settings to stop
enabling of output
1
Set LVD2CR0.CMPE = 0 to disable output of the results of comparison by voltage monitor 2.
2
Set LVD2CR0.RIE = 0 to disable the voltage monitor 2 interrupt or reset*1.
Stopping the voltage
detection 1 circuit
3
Set LVCMPCR.LVD2E = 0 to disable the voltage detection 2 circuit.
Note 1. Step 2 is not required if only the ELC event signal is to be output.
If the voltage monitor 2 interrupt or reset setting is to be made again after it is used and stopped once, omit the following
steps in the procedures for stopping and setting, depending on the conditions:
Setting or stopping the voltage detection 2 circuit is not required if the settings for the voltage detection 2 circuit do
not change.
Setting the voltage monitor 2 interrupt or reset is not required if the settings for the voltage monitor 2 interrupt or
voltage monitor 2 reset do not change.
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7. Low Voltage Detection (LVD)
VCC
Vdet2
Lower limit on VCC voltage
(VCCmin)*1
LVD2SR.MON bit
Set to 0 by software
LVD2CR1.IDTSEL[1:0] bits are
set to 10b (when drop and rise
are detected)
LVD2SR.DET bit
Voltage monitor 2
interrupt request
Set to 0 by software
LVD2CR1.IDTSEL[1:0] bits are
set to 00b (when rise is
detected)
LVD2SR.DET bit
Voltage monitor 2
interrupt request
Set to 0 by software
LVD2CR1.IDTSEL[1:0] bits are
set to 01b (when drop is
detected)
LVD2SR.DET bit
Voltage monitor 2
interrupt request
Note 1. When the voltage monitor 0 reset is not in use, VCC VCCmin.
Figure 7.6
7.7
Example of voltage monitor 2 interrupt operation
Event Link Output
The LVD can output the event signals to the Event Link Controller (ELC).
(1)
Vdet1 Crossing Detection Event
The LVD outputs the event signal when it detects that the voltage has passed the Vdet1 voltage while both the voltage
detection 1 circuit and the voltage monitor 1 circuit comparison result output are enabled.
(2)
Vdet2 Crossing Detection Event
The LVD outputs the event signal when it detects that the voltage has passed the Vdet2 voltage while both the voltage
detection 2 circuit and the voltage monitor 2 circuit comparison result output are enabled.
When enabling the event link output function of the LVD, you must enable the LVD before enabling the LVD event link
function of the ELC. To stop the event link output function of the LVD, you must stop the LVD before disabling the LVD
event link function of the ELC.
7.7.1
Interrupt Handling and Event Linking
The LVD provides bits to individually enable or disable the voltage monitor 1 and 2 interrupts. When an interrupt source
is generated and the interrupt is enabled by the interrupt enable bit, the interrupt signal (LVD1CR0.RIE and
LVD2CR0.RIE) is output to the CPU.
On the other hand, as soon as an interrupt source is generated, the event link signal is output as the event signal to the
other module through the ELC regardless of the state of the interrupt enable bit.
It is possible to output voltage monitor 1 and 2 interrupts in Software Standby mode. The event signals for the ELC in
Software Standby mode are output as follows:
When a Vdet1/Vdet2 passage event is detected in Software Standby mode, event signals are not generated for the
ELC because the clock is not supplied in Software Standby mode. Because the Vdet1 and Vdet2 passage detection
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7. Low Voltage Detection (LVD)
flags are saved, when the clock supply resumes after returning from Software Standby mode, the event signals for
the ELC are output based on the state of the Vdet1 and Vdet2 detection flags.
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8. Clock Generation Circuit
8.
Clock Generation Circuit
8.1
Overview
Table 8.1 and Table 8.2 list the specifications of the clock generation circuit. Figure 8.1 shows the block diagram, and
Table 8.3 lists the I/O pins.
Table 8.1
Clock generation circuit specifications for the clock sources
Clock source
Description
Specification
Main clock oscillator (MOSC)
Resonator frequency
1 MHz to 20 MHz (up to 5.5 V)
1 MHz to 8 MHz (up to 2.4 V)
External clock input frequency
Up to 20 MHz
External resonator or additional circuit: ceramic resonator,
crystal
Available
Connection pins EXTAL, XTAL
Drive capability switching
Oscillation stop detection function
Sub-clock oscillator (SOSC)
Resonator frequency
32.768 kHz
External resonator or additional circuit: crystal resonator
Available
Connection pins: XCIN, XCOUT
Drive capability switching
High-speed on-chip oscillator
(HOCO)
Oscillation frequency
24/32/48/64 MHz
User trimming
Available
Middle-speed
on-chip oscillator (MOCO)
Oscillation frequency
8 MHz
User trimming
Available
Low-speed on-chip oscillator (LOCO)
Oscillation frequency
32.768 kHz
User trimming
Available
IWDT-dedicated on-chip oscillator
(IWDTLOCO)
Oscillation frequency
15 kHz
User trimming
No
External clock input for SWD
(SWCLK)
Input clock frequency
Up to 12.5 MHz
Table 8.2
Clock generation circuit specifications for the internal clocks (1 of 2)
Parameter
Clock Source
Clock Supply
Specification
System clock (ICLK)
MOSC/SOSC/HOCO/
MOCO/LOCO
CPU, DTC, FLASH, SRAM, FlashIF
Up to 32 MHz
Division ratios: 1/2/4/8/16/32/64
1 MHz to 32 MHz (P/E)
Peripheral module clock B
(PCLKB)
MOSC/SOSC/HOCO/
MOCO/LOCO
Peripheral module (CAC, ELC, I/O
Ports, POEG, RTC, WDT, IWDT,
SCI, IIC, CAN, SPI, CRC, GPT,
ADC14, DAC12, DOC, AES, TRNG,
KINT, AGT, USBFS, ACMPLP, and
CTSU)
Up to 32 MHz
Division ratios:1/2/4/8/16/32/64
Peripheral module clock D
(PCLKD)
MOSC/SOSC/HOCO/
MOCO/LOCO
Peripheral module (GPT count
clock, ADC14 conversion clock)
Up to 64 MHz
Division ratios: 1/2/4/8/16/32/64
USB clock (UCLK)
HOCO
USBFS
48 MHz
CAN clock (CANMCLK)
MOSC
CAN
1 MHz to 20 MHz
AGT clock
(AGTSCLK/AGTLCLK)
SOSC/LOCO
AGT
32.768 kHz
CAC Main clock
(CACMCLK)
MOSC
CAC
Up to 20 MHz
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Table 8.2
8. Clock Generation Circuit
Clock generation circuit specifications for the internal clocks (2 of 2)
Parameter
Clock Source
Clock Supply
Specification
CAC Sub clock
(CACSCLK)
SOSC
CAC
32.768 kHz
CAC LOCO clock
(CACLCLK)
LOCO
CAC
32.768 kHz
CAC MOCO clock
(CACMOCLK)
MOCO
CAC
8 MHz
CAC HOCO clock
(CACHCLK)
HOCO
CAC
24/32/48/64 MHz
CAC IWDTLOCO clock
(CACILCLK)
IWDTLOCO
CAC
15 kHz
RTC clock (RTCSCLK/
RTCLCLK)
SOSC/LOCO
RTC
32.768 kHz
IWDT clock (IWDTCLK)
IWDTLOCO
IWDT
15 kHz
SysTick Timer clock
(SYSTICCLK)
LOCO
SysTick Timer
32.768 kHz
Clock/buzzer output
(CLKOUT)
MOSC/SOSC/LOCO/
MOCO/HOCO
CLKOUT pin
Up to 16 MHz
Division ratios: 1/2/4/8/16/32/64/
128
Serial wire clock (SWCLK)
SWCLK pin
OCD
Up to 12.5 MHz
Note:
Restrictions on setting clock frequency: ICLK ≥ PCLKB, PCLKD ≥ PCLKB
Restrictions on clock frequency ratio: (N: integer, and up to 64)
ICLK:PCLKB = N: 1, ICLK:PCLKD = N:1 or 1:N
Minimum ICLK frequency is 1 MHz in Programming/Erasure (P/E) mode.
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8. Clock Generation Circuit
SCKDIVCR ICK[2:0]
CKSEL[2:0]
SCKSCR
Main clock
Sub-clock
oscillator
1/1
1/2
1/4
1/8
1/16
1/32
1/64
Oscillation
wait control
SCKDIVCR
PCKB[2:0]
PCKD[2:0]
Peripheral module clock
Sub-clock
High-speed
clock
High-speed on-chip
oscillator
24/32/48/64 MHz
System clock (ICLK)
To CPU, FLASH,
SRAM, and Flash IF
Selector
Frequency
divider
Selector
Selector
XCIN
XCOUT
Main clock
oscillator
Selector
XTAL
EXTAL
Selector
Oscillation
stop detection
circuit
PCLKB (Peripheral bus)
PCLKD (GPT, ADC14)
Oscillation
wait control
USB clock (UCLK)
To USBFS
Middle-speed
clock
Middle-speed on-chip
oscillator
8 MHz
Systic timer (SYSTICCLK)
Low-speed
clock
Low-speed on-chip
oscillator
32.768 kHz
AGT clock (AGTSCLK)
To AGT (AGTLCLK)
CKODIV[2:0]
CKOCR
CKOSEL
Selector
CKOCR
IWDT-dedicated
on-chip oscillator
15 kHz
Frequency
divider
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Clock/Buzzer output
(CLKOUT)
To CLKOUT pin
CAN clock (CANMCLK)
To CAN
IWDT clock (IWDTCLK)
To IWDT
IWDT low-speed
clock
CAC clock
To CAC
(CACILCLK)
(CACLCLK)
(CACMOCLK)
(CACHCLK)
(CACSCLK)
(CACMCLK)
RTC clock (RTCLCLK)
To RTC (RTCSCLK)
Serial wire clock (SWCLK)
To TAP controller
SWCLK pin
Figure 8.1
Clock generation circuit block diagram
Table 8.3
IClock generation circuit input/output pins
Pin name
I/O
Description
XTAL
Output
EXTAL
Input
XCIN
Input
XCOUT
Output
CLKOUT
Output
This pin is used to output the CLKOUT/BUZZER clock
SWCLK
Input
This pin is used to input from the SWD
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These pins are used to connect a crystal resonator. The EXTAL pin can also be
used to input an external clock. For details, section 8.3.2, External Clock Input.
These pins are used to connect a 32.768-kHz crystal resonator
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8.2
8. Clock Generation Circuit
Register Descriptions
8.2.1
System Clock Division Control Register (SCKDIVCR)
Address(es): SYSTEM.SCKDIVCR 4001 E020h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
—
—
—
—
—
0
0
0
0
0
1
0
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
0
0
0
0
0
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
0
0
0
0
0
ICK[2:0]
PCKB[2:0]
1
0
Bit
Symbol
Bit name
b2 to b0
PCKD[2:0]
Peripheral Module Clock D
(PCLKD) Select*2
0
Description
b2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
b0
0:
1:
0:
1:
0:
1:
0:
×1/1
×1/2
×1/4
×1/8
×1/16
×1/32
×1/64.
PCKD[2:0]
1
0
0
R/W
R/W
Other settings are prohibited.
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b10 to b8
PCKB[2:0]
Peripheral Module Clock B
(PCLKB) Select*1
b10
0
0
0
0
1
1
1
0
0
1
1
0
0
1
b8
0:
1:
0:
1:
0:
1:
0:
×1/1
×1/2
×1/4
×1/8
×1/16
×1/32
×1/64.
R/W
Other settings are prohibited.
b23 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b26 to b24
ICK[2:0]
System Clock (ICLK) Select
*1, *2
b26
0
0
0
0
1
1
1
0
0
1
1
0
0
1
b24
0:
1:
0:
1:
0:
1:
0:
×1/1
×1/2
×1/4
×1/8
×1/16
×1/32
×1/64.
R/W
Other settings are prohibited.
b31 to b27
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note 1. The association between the frequencies of the system clock (ICLK) and the peripheral module clocks (PCLKB)
should be ICLK:PCLKB = N:1 (N: integer)
If a setting is written where ICLK < PCLKB, the write is ignored.
Note 2. The association between the frequencies of the system clock (ICLK) and the peripheral module clocks (PCLKD)
should be ICLK:PCLKD = N:1 or 1:N (N: integer).
The SCKDIVCR register selects the frequencies of the system clock (ICLK) and peripheral module clock (PCLKB,
PCLKD).
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8. Clock Generation Circuit
PCKD[2:0] bits (Peripheral Module Clock D (PCLKD) Select*2)
The PCKD[2:0] bits select the frequency of peripheral module clock D (PCLKD).
PCKB[2:0] bits (Peripheral Module Clock B (PCLKB) Select*1)
The PCKB[2:0] bits select the frequency of peripheral module clock B (PCLKB).
ICK[2:0] bits (System Clock (ICLK) Select *1, *2)
The ICK[2:0] bits select the frequency of the system clock for the CPU and DTC.
8.2.2
System Clock Source Control Register (SCKSCR)
Address(es): SYSTEM.SCKSCR 4001 E026h
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
b2 to b0
CKSEL[2:0]
Clock Source Select
b2
b1
b0
CKSEL[2:0]
0
0
1
Description
b2
0
0
0
0
1
0
0
1
1
0
b0
0:
1:
0:
1:
0:
R/W
R/W
HOCO
MOCO
LOCO
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC).
Other settings are prohibited.
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SCKSCR register selects the clock source for the system clock.
CKSEL[2:0] bits (Clock Source Select)
The CKSEL[2:0] bits select the source for the following modules:
System clock (ICLK)
Peripheral module clocks (PCLKB and PCLKD).
The bits select from one of the following sources:
Low-speed on-chip oscillator (LOCO)
Middle-speed on-chip oscillator (MOCO)
High-speed on-chip oscillator (HOCO)
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC).
Transitions to clock sources that are not in operation are prohibited.
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8. Clock Generation Circuit
Main Clock Oscillator Control Register (MOSCCR)
Address(es): SYSTEM.MOSCCR 4001 E032h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
MOSTP
0
0
0
0
0
0
0
1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
operating*1
b0
MOSTP
Main Clock Oscillator Stop
0: Main clock oscillator is
1: Main clock oscillator is stopped.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. MOMCR register must be set before setting MOSTP to 0.
The MOSCCR register controls the main clock oscillator.
MOSTP bit (Main Clock Oscillator Stop)
The MOSTP bit starts or stops the main clock oscillator.
The main clock oscillator can be started by setting the MOSTP bit to operate. When changing the value of the MOSTP
bit, execute subsequent instructions only after reading the bit to check that the value is updated.
When using the main clock, the Main Clock Oscillator Mode Oscillation Control Register (MOMCR) and the Main
Clock Oscillator Wait Control Register (MOSCWTCR) must be set before setting MOSTP to 0. When the
MOSCCR.MOSTP bit is modified for the main clock to run, only use the main clock after confirming that the
OSCSF.MOSCSF bit is set to 1.
A fixed stabilization wait time is required after setting the main clock oscillator to start operation. A fixed wait time is
also required for oscillation to stop after stopping the main clock oscillator.
The following restrictions apply when starting and stopping operation:
After stopping the main clock oscillator, confirm that the OSCSF.MOSCSF bit is 0 before restarting the main clock
oscillator
Confirm that the main clock oscillator operates and that the OSCSF.MOSCSF bit is 1 before stopping the main
clock oscillator
Regardless of whether the main clock oscillator is selected as the system clock, confirm that the OSCSF.MOSCSF
bit is set to 1 before executing a WFI instruction to place the MCU in Software Standby mode.
When a transition to Software Standby mode is to follow the setting to stop the main clock oscillator, confirm that
the OSCSF.MOSCSF bit is cleared to 0 before executing the WFI instruction.
Writing 1 to MOSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 011b (System clock source = MOSC).
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8. Clock Generation Circuit
Sub-clock Oscillator Control Register (SOSCCR)
Address(es): SYSTEM.SOSCCR 4001 E480h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
SOSTP
0
0
0
0
0
0
0
1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
oscillator*1
b0
SOSTP
Sub-Clock Oscillator Stop
0: Operate the sub-clock
1: Stop the sub-clock oscillator.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. The SOMCR register must be set before setting SOSTP to 0.
The SOSCCR register controls the sub-clock oscillator.
SOSTP bit (Sub-Clock Oscillator Stop)
The SOSTP bit starts or stops the sub-clock oscillator. When changing the value of the SOSTP bit, execute subsequent
instructions after reading the bit to check that the value is updated. Use the SOSTP bit when using the sub-clock
oscillator as the source for a peripheral module, for example RTC. When using the sub-clock oscillator, set the Sub-clock
Oscillator Mode Control Register (SOMCR) before setting SOSTP to 0.
After setting SOSTP to 0, only use the sub-clock oscillator after the sub-clock oscillation stabilization wait time
(tSUBOSCOWT) elapses. A fixed stabilization wait time is required after selecting the sub-clock operation with the
SOSTP bit. A fixed wait time is also required for oscillation to stop.
The following restrictions apply when starting and stopping the operation:
After stopping the sub-clock oscillator, allow a stop interval of at least 5 SOSC clock cycles before restarting it
Confirm that the sub-clock oscillator is stable when stopping the sub-clock oscillator
Regardless of whether the sub-clock oscillator is selected as the system clock, confirm that the sub-clock oscillation
is stable before executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting to stop the sub-clock oscillator, wait for at least
3 SOSC clock cycles before executing the WFI instruction.
Writing 1 to SOSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 100b (system clock source = SOSC).
8.2.5
Low-Speed On-Chip Oscillator Control Register (LOCOCR)
Address(es): SYSTEM.LOCOCR 4001 E490h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
LCSTP
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
LCSTP
LOCO Stop
0: Operate the LOCO clock
1: Stop the LOCO clock.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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The LOCOCR register controls the LOCO.
LCSTP bit (LOCO Stop)
The LCSTP bit starts or stops the LOCO.
After setting the LCSTP bit to start the LOCO clock, only use the clock after the LOCO clock-oscillation stabilization
wait time (tLOCOWT) elapses. A fixed stabilization wait time is required after setting the LOCO clock to start operation.
A fixed wait time is also required after setting the LOCO clock to stop.
The following restrictions apply when starting and stopping the oscillator:
After stopping the LOCO clock, allow a stop interval of at least 5 LOCO clock cycles before restarting it
Confirm that LOCO oscillation is stable before stopping the LOCO clock
Regardless of whether the LOCO clock is selected as the system clock, confirm that LOCO oscillation is stable
before executing a WFI instruction to place the MCU in Software Standby mode.
When a transition to Software Standby mode is to follow the setting to stop the LOCO clock, wait for at least 3
LOCO clock cycles before executing the WFI instruction.
Writing 1 to LOSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 010b (system clock source = LOCO).
8.2.6
High-Speed On-Chip Oscillator Control Register (HOCOCR)
Address(es): SYSTEM.HOCOCR 4001 E036h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
HCSTP
0
0
0
0
0
0
0
0/1*1
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
HCSTP
HOCO Stop
0: Operate the HOCO
1: Stop the HOCO clock.
R/W*3
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
Note 1.
Note 2.
Note 3.
Note 4.
clock*2, *4
Writing to OPCCR.OPCM[1:0] is prohibited while HOCOCR.HCSTP = 0 and OSCSF.HOCOSF = 0 (HOCO is in
stabilization wait counting).
The HCSTP bit value after a reset is 0 when the OFS1.HOCOEN bit is 0. It is 1 when the OFS1.HOCOEN bit is 1.
If the operating frequency of HOCO is 48 MHz, VCC must be more than 1.8 V (VCC ≥ 1.8 V) when operating the
HOCO.
If the operating frequency of HOCO is 64 MHz, VCC must be more than 2.4 V (VCC ≥ 2.4 V) when operating the
HOCO.
Writing HCSTP is prohibited while OPCCR.OPCMTSF = 1 or SOPCCR.SOPCMTSF = 1 (during transition of
operating power control mode) or FLSTOP.CFLSTOPF = 1 (during transition of flash).
If you are using the HOCO (HCSTP = 0), set the OFS1.HOCOFRQ1 bit to an optimum value.
During low-voltage mode, HOCOCR.HCSTP must always be 0.
The HOCOCR register controls the HOCO.
HCSTP bit (HOCO Stop)
The HCSTP bit starts or stops the HOCO. For the HOCO to operate, the High-Speed On-Chip Oscillator Wait Control
Register (HOCOWTCR) must also be set.
After setting the HCSTP bit to 0 to start the HOCO clock, confirm that the OSCSF.HOCOSF is set to 1 before using the
clock. When OFS1.HOCOEN is set to 1, confirm that OSCSF.HOCOSF is also set to 1 before using the HOCO clock. A
fixed stabilization wait time is required after setting the HOCO clock to start operation. A fixed wait time is also required
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8. Clock Generation Circuit
after setting the HOCO clock to stop.
The following restrictions apply when starting and stopping the operation:
After stopping the HOCO, confirm that the OSCSF.HOCOSF bit is 0 before restarting the HOCO.
Confirm that the HOCO operates and that the OSCSF.HOCOSF bit is 1 before stopping the HOCO.
Regardless of whether the HOCO clock is selected as the system clock, confirm that the OSCSF.HOCOSF bit is set
to 1 before executing a WFI instruction to place the MCU in Software Standby mode.
When a transition to Software Standby mode is to follow the setting of the HOCO to stop, confirm that the
OSCSF.HOCOSF bit is cleared to 0 after setting the HOCO and before executing the WFI instruction.
Writing 1 to HCSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 000b (system clock source = HOCO).
8.2.7
Middle-Speed On-Chip Oscillator Control Register (MOCOCR)
Address(es): SYSTEM.MOCOCR 4001 E038h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
MCSTP
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
MCSTP
MOCO Stop
0: Operate the MOCO clock
1: Stop the MOCO clock.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The MOCOCR register controls the MOCO.
MCSTP bit (MOCO Stop)
The MCSTP bit starts or stops the MOCO.
After setting MCSTP to 0, use the MOCO clock only after the MOCO clock oscillation stabilization time (tMOCOWT)
elapses. A fixed stabilization wait time is required after setting the MOCO clock to start operation. A fixed wait time is
also required for oscillation to stop after setting the MOCO clock to stop operation.
The following restrictions apply when starting and stopping the oscillator:
After stopping the MOCO clock, allow a stop interval of at least 5 MOCO clock cycles before restarting it
Confirm that MOCO oscillation is stable before stopping the MOCO clock
Regardless of whether the MOCO clock is selected as the system clock, confirm that MOCO oscillation is stable
before executing a WFI instruction to place the MCU in Software Standby mode
When a transition to Software Standby mode is to follow the setting to stop the MOCO clock, wait for at least 3
MOCO clock cycles before executing the WFI instruction.
Writing 1 to MCSTP is prohibited under the following condition:
SCKSCR.CKSEL[2:0] = 001b (system clock source = MOCO).
Writing 1 to the MCSTP bit (stopping the MOCO) is prohibited if oscillation stop detection is enabled in the Oscillation
Stop Detection Control Register (OSTDCR.OSTDE).
Because the MOCO clock is used to measure the wait time for other oscillators, the MOCO clock oscillates while the
wait time for other oscillators is being measured, regardless of the setting of MOCOCR.MCSTP. Therefore, the MOCO
clock might be unintentionally supplied even if the MCSTP is set to stop.
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8.2.8
8. Clock Generation Circuit
Oscillation Stabilization Flag Register (OSCSF)
Address(es): SYSTEM.OSCSF 4001 E03Ch
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
MOSC
SF
—
—
HOCO
SF
0
0
0
0
0
0
0
0/1*1
Bit
Symbol
Bit name
Description
R/W
b0
HOCOSF
HOCO Clock Oscillation
Stabilization Flag
0: The HOCO clock is stopped or is not yet stable
1: The HOCO clock is stable, so is available for use as
the system clock.
R
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
MOSCSF
Main Clock Oscillation
Stabilization Flag
0: The main clock oscillator is stopped (MOSTP = 1) or is
not yet stable*2
1: The main clock oscillator is stable, so is available for
use as the system clock.
R
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. The value after reset depends on the OFS1.HOCOEN setting.
When OFS1.HOCOEN = 0, the value after reset of HOCOSF is 0.
When OFS1.HOCOEN = 1, the HOCOSF value is set to 0 immediately after reset is released, and the HOCOSF
value is set to 1 after the HOCO oscillation stabilization time elapses.
Note 2. This is true when an appropriate value is set in the Wait Control register for the given oscillator. If the wait time
value is not sufficient, the oscillation stabilization flag is set to 1 and supply of the clock signal to the internal
circuits starts before oscillation is stable.
The OSCSF register flags indicate the operating status of the counters in the oscillation stabilization wait circuits for the
individual oscillators. After oscillation starts, these counters measure the wait time until their associated oscillator output
clocks are supplied to the internal circuits. An overflow of a counter indicates that the clock supply is stable and available
for the associated circuit.
HOCOSF flag (HOCO Clock Oscillation Stabilization Flag)
The HOCOSF flag indicates the operating status of the counter that measures the wait time for the high-speed clock
oscillator (HOCO). When OFS1.HOCOEN is set to 1, confirm that OSCSF.HOCOSF is also set to 1 before using the
HOCO clock.
[Setting condition]
After the HOCO clock stops and the HOCOCR.HCSTP bit is set to 0, supply of the high-speed clock in the MCU
starts after the middle-speed clock cycles set in the HOCOWTCR.HSTS[2:0] bits are counted.
[Clearing condition]
When the HOCO clock is operating and then is deactivated because the HOCOCR.HCSTP bit is set to 1.
MOSCSF flag (Main Clock Oscillation Stabilization Flag)
The MOSCSF flag indicates the operating status of the counter that measures the wait time for the main clock oscillator.
[Setting condition]
After the main clock oscillator stops and the MOSCCR.MOSTP bit is set to 0, supply of the main clock in the MCU
starts after the middle-speed clock cycles set in the MOSCWTCR.MSTS[3:0] bits elapse.
[Clearing condition]
After the main clock oscillator is operating and then is deactivated because the MOSCCR.MOSTP bit is set to 1.
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8.2.9
8. Clock Generation Circuit
Oscillation Stop Detection Control Register (OSTDCR)
Address(es): SYSTEM.OSTDCR 4001 E040h
b7
b6
b5
b4
b3
b2
b1
b0
OSTDE
—
—
—
—
—
—
OSTDI
E
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
OSTDIE
Oscillation Stop Detection
Interrupt Enable
0: Disable oscillation stop detection interrupt (do not notify
the POEG)
1: Enable oscillation stop detection interrupt (notify the
POEG).
R/W
b6 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
OSTDE
Oscillation Stop Detection
Function Enable
0: Disable oscillation stop detection function
1: Enable oscillation stop detection function.
R/W
The OSTDCR register controls the oscillation-stop detection function.
OSTDIE bit (Oscillation Stop Detection Interrupt Enable)
The OSTDIE bit enables the oscillation stop detection function interrupt. It also controls whether oscillation stop
detection is sent to the POEG.
If the oscillation stop detection flag in the Oscillation Stop Detection Status Register (OSTDSR.OSTDF) requires
clearing, clear the OSTDIE bit to 0 before clearing OSTDF. Wait for at least 2 PCLKB cycles before setting the OSTDIE
bit to 1. A wait time longer than 2 PCLKB cycles might be required, depending on the number of cycles required to read
a given I/O register.
OSTDE bit (Oscillation Stop Detection Function Enable)
The OSTDE bit enables the oscillation stop detection function.
When the OSTDE bit is 1 (enabled), the MOCO stop bit (MOCOCR.MCSTP) is set to 0 and the MOCO operation starts.
The MOCO clock cannot be stopped while the oscillation stop detection function is enabled. Writing 1 to the
MOCOCR.MCSTP bit (MOCO stopped) is invalid.
When the oscillation stop detection flag in the Oscillation Stop Detection Status Register (OSTDSR.OSTDF) is 1 (main
clock oscillation stop detected), writing 0 to the OSTDE bit is invalid.
The OSTDE bit must be set to 0 before transitioning to Software Standby mode. To transition to Software Standby mode,
first set the OSTDE bit to 0 then execute the WFI instruction.
The following restrictions apply when using the oscillation stop detection function:
In low-speed mode, selecting division by 1, 2, 4, 8 for ICLK, PCLKB, and PCLKD is prohibited
In low-voltage mode, selecting division by 1, 2 for ICLK, PCLKB, and PCLKD is prohibited.
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8. Clock Generation Circuit
Oscillation Stop Detection Status Register (OSTDSR)
Address(es): SYSTEM.OSTDSR 4001 E041h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
OSTDF
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
OSTDF
Oscillation Stop Detection Flag
0: The main clock oscillation stop has not been detected
1: The main clock oscillation stop is detected.
R(/W)*1
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R
Note 1. This bit can only be set to 0.
The OSTDSR register indicates the status of the main clock oscillation stop detection.
OSTDF flag (Oscillation Stop Detection Flag)
The OSTDF flag indicates the main clock oscillator status. When this flag is 1, it indicates that the main clock oscillation
stop is detected. After this stop is detected, the OSTDF flag is not set to 0 even when oscillation is restarted. The OSTDF
flag is set to 0 by writing 0 after reading it as 1.
At least 3 ICLK cycles of wait time are required between writing 0 to OSTDF and reading OSTDF as 0. If the OSTDF
flag is set to 0 when the main clock oscillation is stopped, the OSTDF flag becomes 0 then returns to 1.
OSTDSR.OSTDF cannot be set to 0 under the following conditions:
SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC).
The OSTDF flag must be set to 0 after switching the clock source to sources other than the main clock oscillator.
[Setting condition]
The main clock oscillation is stopped when OSTDCR.OSTDE = 1 (oscillation stop detection function enabled).
[Clearing condition]
1 is read and then 0 is written when the SCKSCR.CKSEL[2:0] bits are not 011b (system clock is MOSC).
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8.2.11
8. Clock Generation Circuit
Main Clock Oscillator Wait Control Register (MOSCWTCR)
Address(es): SYSTEM.MOSCWTCR 4001 E0A2h
b7
b6
b5
b4
—
—
—
—
0
0
0
0
Value after reset:
b3
b2
b1
b0
MSTS[3:0]
0
Bit
Symbol
Bit name
b3 to b0
MSTS[3:0]
Main Clock Oscillator Wait
Time Setting
1
0
1
Description
b3
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
b0
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
R/W
Wait time = 2 cycles (0.25 μs)
Wait time = 1024 cycles (128 μs)
Wait time = 2048 cycles (256 μs)
Wait time = 4096 cycles (512 μs)
Wait time = 8192 cycles (1024 μs)
Wait time = 16384 cycles (2048 μs) (value after reset)
Wait time = 32768 cycles (4096 μs)
Wait time = 65536 cycles (8192 μs)
Wait time = 131072 cycles (16384 μs)
Wait time = 262144 cycles (32768 μs).
R/W
Other settings are prohibited.
Wait time is calculated at MOCO = 8 MHz (0.125 μs TYP.)
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R
MSTS[3:0] bits (Main Clock Oscillator Wait Time Setting)
Set the MSTS[3:0] bits to select the oscillation stabilization wait time for the main clock oscillator.
Specify a time period longer than or equal to the stabilization time recommended by the oscillator manufacturer. When
the main clock is input externally, set these bits to 0000b because the oscillation stabilization time is not required.
The wait time set by the MSTS[3:0] bits is counted using the MOCO clock. The MOCO clock automatically oscillates
when necessary, regardless of the value of the MOCOCR.MCSTP bit. After the specified wait time elapses, supply of the
main clock starts internally in the MCU, and the OSCSF.MOSCSF flag is set to 1. If the specified wait time is short,
supply of the main clock starts before oscillation of the clock becomes stable.
Only rewrite the MOSCWTCR register when the MOSCCR.MOSTP bit is 1 and the OSCSF.MOSCSF flag is 0. Do not
rewrite this register under any other conditions.
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8.2.12
8. Clock Generation Circuit
High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR)
Address(es): SYSTEM.HOCOWTCR 4001 E0A5h
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
Value after reset:
b2
b1
b0
HSTS[2:0]
1
Bit
Symbol
Bit name
b2 to b0
HSTS[2:0]
HOCO wait time setting
0
1
Description
b2
R/W
b0
1 0 1:
Wait time = 245 cycles (29.13 μs)
When HOCO operating frequency is 24 MHz or 32
MHz, and the operation power control mode is
other than low voltage mode.
Wait time = 287 cycles (35.875 μs)
When HOCO operating frequency is 48 MHz and
operation power control mode is other than low
voltage mode.
Wait time = 679 cycles (84.88 μs) (value after
reset)
When operation power control mode is low voltage
mode.
1 1 0:
Wait time = 541 cycles (67.63 μs)
When HOCO operating frequency is 64 MHz
R/W
Other settings are prohibited.
Wait time is calculated at MOCO = 8 MHz (0.125 μs TYP.)
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R
HOCOWTCR controls the wait time until output of the signal from the high-speed clock oscillator to the internal circuits
starts. Only write to HOCOWTCR when the HOCOCR.HCSTP bit is 1 or the OSCSF.HOCOSF flag is 1. Do not write to
this register under any other conditions.
HSTS[2:0] bits (HOCO wait time setting)
The oscillation stabilization wait circuit measures the wait time and controls the clock supply in the MCU. by counting
the number of middle-speed clock cycles set in the HOCOWTCR register.
When the high-speed clock oscillator starts, the oscillation stabilization wait circuit starts counting the number of
middle-speed clock cycles set in the HOCOWTCR register. The MCU clock supply is disabled until counting of the set
number of cycles is complete. After counting completes, supply of the clock signal in the MCU starts and the
OSCSF.HOCOSF flag is set to 1.
The oscillation stabilization wait circuit continues to count the middle-speed clock cycles regardless of the
MOCOCR.MCSTP setting. Hardware automatically controls the running and stopping of the middle-speed oscillator for
wait time measurement.
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8.2.13
8. Clock Generation Circuit
Main Clock Oscillator Mode Oscillation Control Register (MOMCR)
Address(es): SYSTEM.MOMCR 4001 E413h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
MOSEL
—
—
MODR
V1
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
MODRV1
Main Clock Oscillator Drive
Capability 1 Switching
0: 10 MHz to 20 MHz
1: 1 MHz to 10 MHz.
R/W
b5, b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
MOSEL
Main Clock Oscillator Switching
0: Resonator
1: External clock input.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note:
Note:
The EXTAL/XTAL pins are also used as ports. In the initial state, the pin is set as a port.
The MOSTP bit must be 1 (MOSC is stopped) before changing this register.
MODRV1 bit (Main Clock Oscillator Drive Capability 1 Switching)
The MODRV1 bit switches the drive capability of the main clock oscillator.
MOSEL bit (Main Clock Oscillator Switching)
The MOSEL bit switches the source for the main clock oscillator.
8.2.14
Sub-clock Oscillator Mode Control Register (SOMCR)
Address(es): SYSTEM.SOMCR 4001 E481h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
—
SODRV[1:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
b1, b0
SODRV[1:0]
Sub-Clock Oscillator Drive
Capability Switching
b7 to b2
—
Reserved
0
b0
0
Description
b1 b0
0
0
1
1
0:
1:
0:
1:
R/W
R/W
Normal Mode
Low Power Mode 1
Low Power Mode 2
Low Power Mode 3.
These bits are read as 0. The write value should be 0.
R/W
This register must be modified when SOSCCR.SOSTP is 1 (SOSC is stopped).
SODRV[1:0] bits (Sub-Clock Oscillator Drive Capability Switching)
The SODRV[1:0] bits switch the drive capability of the sub-clock oscillator.
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8. Clock Generation Circuit
Clock Out Control Register (CKOCR)
Address(es): SYSTEM.CKOCR 4001 E03Eh
b7
b6
CKOEN
0
Value after reset:
b5
b4
CKODIV[2:0]
0
0
b3
b2
—
0
0
b1
b0
CKOSEL[2:0]
0
Bit
Symbol
Bit name
b2 to b0
CKOSEL[2:0]
Clock Out Source Select
0
0
Description
b2
0
0
0
0
1
0
0
1
1
0
b0
0:
1:
0:
1:
0:
R/W
R/W
HOCO
MOCO
LOCO
MOSC
SOSC
Other settings are prohibited.
b3
—
Reserved
b6 to b4
CKODIV[2:0]
Clock Out input frequency
Division Select
b7
CKOEN
Clock Out Enable
This bit is read as 0. The write value should be 0.
b6
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b4
0:
1:
0:
1:
0:
1:
0:
1:
×1
/2
/4
/8
/16
/32
/64
/128
0: Clock Out disable
1: Clock Out enable.
R/W
R/W
R/W
CKOSEL[2:0] bits (Clock Out Source Select)
The CKOSEL[2:0] bits specify the HOCO, MOCO, LOCO, MOSC, SOSC clock as the source clock to be output from
the CLKOUT pin. When changing the CLKOUT source clock, set the CKOEN bit to 0.
CKODIV[2:0] bits (Clock Out input frequency Division Select)
The CKODIV[2:0] bits specify the clock division ratio. Set the CKOEN bit to 0 when changing the division ratio. The
division ratio of the output clock frequency must be set to a value no higher than the characteristics of the CLKOUT pin
output frequency. For details on the characteristics of the CLKOUT pin, see section 41, Electrical Characteristics.
CKOEN bit (Clock Out Enable)
The CKOEN bit enables output from the CLKOUT pin.
When this bit is set to 1, the selected clock is output. When this bit is set to 0, low is output. When changing this bit,
confirm that the clock out source clock selected in the CKOSEL[2:0] bits is stable. Otherwise, a glitch might be
generated in the output.
Clear this bit before entering Software Standby mode if the selecting clock out source clock is stopped in that mode.
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8. Clock Generation Circuit
LOCO User Trimming Control Register (LOCOUTCR)
Address(es): SYSTEM.LOCOUTCR 4001 E492h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
LOCOUTRM[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
LOCOUTRM[7:0]
LOCO User Trimming
b7
R/W
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127
These bits are added to the original LOCO trimming bits.
MCU operation is not guaranteed when LOCOUTCR is set to a value that causes the LOCO frequency to be outside of
the specification range. When LOCOUTCR is modified, the frequency stabilization time corresponds to the frequency
stabilization time at the start of MCU operation. When the ratio of the LOCO frequency and the other oscillation
frequency is an integer value, changing the LOCOUTCR value is prohibited.
8.2.17
MOCO User Trimming Control Register (MOCOUTCR)
Address(es): SYSTEM.MOCOUTCR 4001 E061h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
MOCOUTRM[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
MOCOUTRM[7:0]
MOCO User Trimming
b7
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127
These bits are added to the original MOCO trimming bits.
R/W
MCU operation is not guaranteed when MOCOUTCR is set to a value that causes the MOCO frequency to be outside of
the specification range. When MOCOUTCR is modified, the frequency stabilization wait time corresponds to the
frequency stabilization wait time at the start of the MCU operation. When the ratio of the MOCO frequency and the other
oscillation frequency is an integer value, changing the MOCOUTCR value is prohibited.
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8. Clock Generation Circuit
HOCO User Trimming Control Register (HOCOUTCR)
Address(es): SYSTEM.HOCOUTCR 4001 E062h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
HOCOUTRM[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
HOCOUTRM[7:0]
HOCO User Trimming
b7
R/W
R/W
b0
1 0 0 0 0 0 0 0: -128
1 0 0 0 0 0 0 1: -127
1 0 0 0 0 0 1 0: -126
…
1 1 1 1 1 1 1 1: -1
0 0 0 0 0 0 0 0: Center Code
0 0 0 0 0 0 0 1: +1
…
0 1 1 1 1 1 0 1: +125
0 1 1 1 1 1 1 0: +126
0 1 1 1 1 1 1 1: +127
These bits are added to the original HOCO trimming bits.
MCU operation is not guaranteed when HOCOUTCR is set to a value that causes the HOCO frequency to be outside of
the specification range. When HOCOUTCR is modified, the frequency stabilization wait time corresponds to the
frequency stabilization wait time at the start of the MCU operation.
When UCKSEL.UCKSELC = 1, writing any other value except 00h to HOCOUTCR is prohibited. For UCKSEL
register, see section 24, USB 2.0 Full-Speed Module (USBFS).
8.3
Main Clock Oscillator
To supply the clock signal to the main clock oscillator, use one of the following ways:
Connect an oscillator
Connect the input of an external clock signal.
8.3.1
Connecting the Crystal Resonator
Figure 8.2 shows an example of connecting a crystal resonator. A damping resistor (Rd) can be added, if required.
Because the resistor values vary according to the resonator and the oscillation drive capability, use values recommended
by the resonator manufacturer. If the manufacturer recommends using an external feedback resistor (Rf), insert an Rf
between EXTAL and XTAL by following the instructions.
When connecting a resonator to supply the clock, the frequency of the resonator must be in the frequency range of the
resonator for the main clock oscillator as described in Table 8.1.
C L1
EXTAL
Rf
XTAL
Rd
Figure 8.2
C L2
Example of crystal resonator connection
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8. Clock Generation Circuit
External Clock Input
Figure 8.3 shows an example of connecting an external clock input. To operate the oscillator with an external clock
signal, set the MOMCR.MOSEL bit to 1. The XTAL pin becomes high impedance.
EXTAL
External clock input
XTAL
Figure 8.3
8.3.3
Hi-Z
Equivalent circuit for external clock
Notes on External Clock Input
The frequency of the external clock input can only be changed while the main clock oscillator is stopped. Do not change
the frequency of the external clock input when the setting of the main clock oscillator stop bit (MOSCCR.MOSTP) is 0.
8.4
Sub-Clock Oscillator
The only way of supplying the clock signal to the sub-clock oscillator is by connecting a crystal oscillator.
8.4.1
Connecting 32.768-kHz Crystal Resonator
To supply a clock to the sub-clock oscillator, connect a 32.768-kHz crystal resonator as shown in Figure 8.4. A damping
resistor (Rd) can be added, if necessary. Because the resistor values vary according to the resonator and the oscillation
drive capability, use values recommended by the resonator manufacturer. If the resonator manufacturer recommends the
use of an external feedback resistor (Rf), insert an Rf between XCIN and XCOUT by following the instructions. When
connecting a resonator to supply the clock, the frequency of the resonator must be in the frequency range of the resonator
for the sub-clock oscillator as described in Table 8.1.
C1
X C IN
Rf
XCOUT
Rd
Figure 8.4
8.5
8.5.1
C2
Connection example of 32.768-kHz crystal resonator
Oscillation Stop Detection Function
Oscillation Stop Detection and Operation after Detection
The oscillation stop detection function detects the main clock oscillator stop. When oscillation stop is detected, the
system clock switches as follows:
If an oscillation stop is detected with SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC), the system
clock source switches to the MOCO clock.
An oscillation stop detection interrupt request can be generated when an oscillation stop is detected. In addition, the
General PWM Timer (GPT) output can be forced to a high-impedance state on detection.
The main clock oscillation stop is detected when the input clock remains at 0 or 1 for a certain period, for example, when
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a malfunction occurs in the main clock oscillator. See section 41, Electrical Characteristics.
Switching between the main clock oscillator and MOCO clock is controlled by the oscillation stop detection flag
(OSTDSR.OSTDF).
OSTDF controls the switched clock as follows:
SCKSCR.CKSEL[2:0] = 011b (system clock source = MOSC):
When OSTDF changes from 0 to 1, the clock source is switched to the MOCO
When OSTDF changes from 1 to 0, the clock source is switched to MOSC again.
To switch the clock source to the main clock again after the oscillation stop detection, set the CKSEL[2:0] bits to a clock
source other than the main clock and clear the OSTDF flag to 0. Also, check that the OSTDF flag is not 1, then set the
CKSEL[2:0] bits to the main clock after the specified oscillation stabilization time elapses.
After a reset release, the main clock oscillator is stopped and the oscillation stop detection function is disabled. To enable
the oscillation stop detection function, activate the main clock oscillator and write 1 to the oscillation stop detection
function enable bit (OSTDCR.OSTDE) after a specified oscillation stabilization time elapses.
The oscillation stop detection function detects when the main clock is stopped by an external cause. Therefore, the
oscillation stop detection function must be disabled before the main clock oscillator is stopped by software or a transition
is made to Software Standby mode.
The oscillation stop detection function switches the following clocks to the MOCO clock (when system clock is MOSC):
All clocks that can be selected as the MOSC except CLKOUT
The system clock (ICLK) frequency during the MOCO operation (when system clock is MOSC) is specified by the
MOCO oscillation frequency and the division ratio set by the system clock select bits (SCKDIVCR.ICK[2:0]).
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Example of re-returning when CKSEL[2:0] = 011b (selecting the main clock
oscillator) after an oscillation stop is detected
Start (Oscillation stop is detected)
Switch to clock sources other than MOSC
Example: Switch to SCKSCR.CKSEL[2:0] = 001b
(selecting the MOCO)
Set OSTDCR.OSTDIE = 0
Read OSTDSR.OSTDF = 1
Yes
Set OSTDSR.OSTDF = 0
OSTDSR.OSTDF = 0
No
Try again?
Yes
Wait for the specified oscillation setting time
Switch to SCKSCR.CKSEL[2:0] = 011b
(selecting the main clock oscillator)
End
Note:
Figure 8.5
8.5.2
No
On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation circuit
must be removed from the system to allow oscillation to resume.
Flow of recovery on detection of oscillator stop
Oscillation Stop Detection Interrupts
An oscillation stop detection interrupt (MOSC_STOP) is generated when the oscillation stop detection flag
(OSTDSR.OSTDF) is 1 and the oscillation stop detection interrupt enable bit in the Oscillation Stop Detection Control
Register (OSTDCR.OSTDIE) is 1 (enabled). The Port Output Enable for GPT (POEG) is notified of the main clock
oscillator stop. On receiving the notification, the POEG sets the Oscillation Stop Detection Flag in the POEG Group n
Setting Register (POEGGn.OSTPF) to 1 (n = A, B).
After the oscillation stop is detected, wait at least 10 PCLKB clock cycles before writing to the POEGGn.OSTPF flag.
When the OSTDSR.OSTDF flag requires clearing, do so after clearing the oscillation stop detection interrupt enable bit
in the Oscillation Stop Detection Control Register (OSTDCR.OSTDIE). Wait at least 2 PCLKB clock cycles before
setting the OSTDCR.OSTDIE bit to 1 again. A longer PCLKB wait time might be required, depending on the number of
cycles required to read a given I/O register.
The oscillation stop detection interrupt is a non-maskable interrupt. Because non-maskable interrupts are disabled in the
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initial state after a reset release, enable non-maskable interrupts through software before using oscillation stop detection
interrupts. For details, see section 12, Interrupt Controller Unit (ICU).
8.6
Internal Clock
Clock sources for the internal clock signals include:
Main clock oscillator
Sub-clock oscillator
HOCO clock
MOCO clock
LOCO clock
Dedicated clock for the IWDT.
The following internal clocks are produced from these sources.
Operating clock of the CPU, DTC, Flash, and SRAM — System clock (ICLK)
Operating clocks of peripheral modules — PCLKB and PCLKD
Operating clock of the Flash IF— ICLK
Operating clock for the CAN — CANMCLK
Operating clock for the USBFS — UCLK
Operating clocks for the CAC — CACCLK
Operating clock for the RTC LOCO clock — RTCLCLK
Operating clock for the RTC sub clock — RTCSCLK
Operating clock for the IWDT — IWDTCLK
Operating clock for the AGT LOCO clock — AGTLCLK
Operating clock for the AGT sub clock — AGTSCLK
Operating clock for the SysTick timer — SYSTICCLK
Clock for external pin output — CLKOUT.
For details of the registers used to set the frequencies of the internal clocks, see section 8.6.1, System Clock (ICLK).
If the value of any of these bits is changed, subsequent operation is at the frequency determined by the new value.
8.6.1
System Clock (ICLK)
The system clock, ICLK, is the operating clock for the CPU, DTC, Flash, FlashIF, and SRAM.
The ICLK frequency is specified by the ICK[2:0] bits in SCKDIVCR, the CKSEL[2:0] bits in SCKSCR, and the
HOCOFRQ1[2:0] bits in OFS1.
8.6.2
Peripheral Module Clock (PCLKB, PCLKD)
The peripheral module clocks, PCLKB and PCLKD, are the operating clocks for the peripheral modules.
The frequency of the given clock is specified in the following bits:
PCKB[2:0] and PCKD[2:0] in SCKDIVCR
CKSEL[2:0] in SCKSCR
HOCOFRQ1[2:0] in OFS1.
8.6.3
FlashIF Clock (ICLK)
The flash interface clock, ICLK, is the operating clock for the flash memory interface. In addition to reading from the
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data flash, ICLK is used for the programming and erasure of the code flash and data flash.
8.6.4
USB Clock (UCLK)
The USB clock, UCLK, is an operating clock for the USBFS module. A 48-MHz clock must be supplied to the USBFS
module. When the USBFS module is used, the setting must be 48 MHz for the UCLK clock. The UCLK frequency is
specified by HOCOFRQ1[2:0] bits in OFS1.
8.6.5
CAN Clock (CANMCLK)
The CAN clock, CANMCLK, is an operating clock for the CAN module. CANMCLK is generated by the main clock
oscillator.
8.6.6
CAC Clock (CACCLK)
The CAC clock, CACCLK, is an operating clock for the CAC. CACCLK is generated by the following oscillators:
Main clock oscillator
Sub-clock oscillator
High-speed clock oscillator (HOCO)
Middle-speed clock oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator.
8.6.7
RTC-Dedicated Clock (RTCSCLK, RTCLCLK)
The RTC-dedicated clocks, RTCSCLK and RTCLCLK, are the operating clocks for the RTC. RTCSCLK is generated by
the sub-clock oscillator, and RTCLCLK is generated by the LOCO clock.
8.6.8
IWDT-Dedicated Clock (IWDTCLK)
The IWDT-dedicated clock, IWDTCLK, is the operating clock for the IWDT. IWDTCLK is internally generated by the
IWDT-dedicated on-chip oscillator.
8.6.9
AGT-Dedicated Clock (AGTSCLK, AGTLCLK)
The AGT-dedicated clocks, AGTSCLK and AGTLCLK, are the operating clocks for the AGT. AGTSCLK is generated
by the sub-clock oscillator, and AGTLCLK is generated by the LOCO clock.
8.6.10
SysTick Timer-Dedicated Clock (SYSTICCLK)
The SysTick timer-dedicated clock, SYSTICCLK, is the operating clock for the SYSTICCLK. SYSTICCLK is
generated by the LOCO clock.
8.6.11
Clock/Buzzer Output Clock (CLKOUT)
The CLKOUT is output externally from the CLKOUT pin for the clock or buzzer output. CLKOUT is output to the
CLKOUT pin when CKOCR.CKOEN is set to 1. Only change the value in CKODIV[2:0] or CKOSEL[2:0] bits in
CKOCR when the CKOCR.CKOEN bit is 0.
The CLKOUT clock frequency is specified in the following bits:
CKODIV[2:0] or CKOSEL[2:0] in CKOCR
HOCOFRQ1[2:0] in OFS1.
8.7
8.7.1
Usage Notes
Notes on Clock Generation Circuit
The frequencies of the system clock (ICLK) and peripheral module clock (PCLKB and PCLKD), flash interface clock
(ICLK) supplied to each module change according to the settings of SCKDIVCR. Each frequency must meet the
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following conditions:
Select each frequency that is within the operation-guaranteed range of the clock cycle time (tcyc) specified in the AC
characteristics. See section 41, Electrical Characteristics.
The frequencies must not exceed the ranges listed in Table 8.2.
The peripheral modules operate on the PCLKB. As a result, the operating speed of modules such as the timer and
SCI is different before and after the frequency is changed.
The system clock (ICLK), peripheral module clock (PCLKB and PCLKD), and flash interface clock (ICLK) must
be set according to Table 8.2.
To ensure correct processing after the clock frequency changes, first modify the relevant Clock Control register to change
the frequency, then read the value from the register, and finally perform the subsequent processing.
8.7.2
Notes on Resonator
Because various resonator characteristics relate closely to your board design, adequate evaluation is required before use.
See the resonator connection example in Figure 8.4. The circuit constants for the resonator depend on the resonator to be
used and the stray capacitance of the mounting circuit. Therefore, consult the resonator manufacturer when determining
the circuit constants. The voltage to be applied between the resonator pins must be within the absolute maximum rating.
8.7.3
Notes on Board Design
When using a crystal resonator, place the resonator and its load capacitors as close to the XTAL and EXTAL pins as
possible. Other signal lines should be routed away from the oscillation circuit as shown in Figure 8.6 to prevent
electromagnetic induction from interfering with correct oscillation.
Prohibited
Signal A
Signal B
Prohibited
MCU
CL2
XTAL
EXTAL
CL1
Figure 8.6
8.7.4
Signals routing in board design for oscillation circuit (applies to the sub-clock oscillator for the
main clock oscillator)
Notes on Resonator Connect Pin
When the main clock is not used, the EXTAL and XTAL pins can be used as general ports P212 and P213. When they are
used as the general ports, the main clock must be stopped (MOSCCR.MOSTP should be set to 1).
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9. Clock Frequency Accuracy Measurement Circuit (CAC)
9.
Clock Frequency Accuracy Measurement Circuit (CAC)
9.1
Overview
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement
target clock) within the time generated by the clock to be used as a measurement reference (measurement reference
clock), and determines the accuracy depending on whether the number of pulses is within the allowable range. When
measurement completes or the number of pulses within the time generated by the measurement reference clock is not
within the allowable range, an interrupt request is generated.
Table 9.1 lists the CAC features and Figure 9.1 shows the block diagram.
Table 9.1
CAC specifications
Parameter
Description
Measurement target clocks
Frequency can be measured for:
Main clock
Sub clock
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B (PCLKB).
Measurement reference clocks
Frequency can be referenced to:
External clock input to the CACREF pin
Main clock
Sub clock
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B (PCLKB).
Selectable function
Digital filter
Interrupt sources
Measurement end
Frequency error
Overflow.
Module-stop function
Module-stop state can be set to reduce power consumption
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DFS[1:0]
CACREFE
CACREF pin
DFS[1:0]
Digital filter
RSCS[2:0]
RCDS[1:0]
EDGES[1:0]
Frequency
dividing circuit
1/32
Reference
signal
generation
clock select
circuit
FMCS[2:0]
Main clock
Sub clock
HOCO clock
MOCO clock
LOCO clock
IWDTCLK clock
Peripheral module clock B
(PCLKB)
1/128
RPS
1/1024
1/8192
Valid edge signal
TCSS[1:0]
Frequency
measurement
clock
Frequency
dividing circuit
Frequency
measurement
clock select
circuit
1/4
1/8
CFME
Count source
clock
16-bit counter
Overflow interrupt request
1/32
CACNTBR
Interrupt control
circuit
CAULVR
CALLVR
Measurement end interrupt
request
Frequency error interrupt
request
High-Speed Analog
Comparator
CFME: Bit in CACR0
CACREFE, FMCS[2:0], TCSS[1:0], EDGES[1:0]: Bits in CACR1
RPS, RSCS[2:0], RCDS[1:0], DFS[1:0]: Bits in CACR2
CAICR: CAC Interrupt Control Register
CASTR: CAC Status Register
CAULVR: CAC Upper-Limit Value Setting Register
CALLVR: CAC Lower-Limit Value Setting Register
CACNTBR: CAC Counter Buffer Register
Figure 9.1
Edge detection
circuit
CAICR
CASTR
Internal peripheral bus
CAC block diagram
Table 9.2 shows the pin configuration of the CAC.
Table 9.2
CAC pin configuration
Pin name
I/O
Function
CACREF
Input
Measurement reference clock input pin
9.2
Register Descriptions
9.2.1
CAC Control Register 0 (CACR0)
Address(es): CAC.CACR0 4004 4600h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
CFME
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CFME
Clock Frequency Measurement Enable
0: Clock frequency measurement is disabled
1: Clock frequency measurement is enabled.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CFME bit (Clock Frequency Measurement Enable)
The CFME bit enables clock frequency measurement. Read the CFME bit to confirm that the bit value has changed.
Additional write accesses are ignored before the change is complete.
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9. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Control Register 1 (CACR1)
Address(es): CAC.CACR1 4004 4601h
b7
b6
EDGES[1:0]
Value after reset:
0
0
b5
b4
b3
TCSS[1:0]
0
0
b2
b1
b0
CACRE
FE
FMCS[2:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CACREFE
CACREF Pin Input Enable
0: Disable CACREF pin input
1: Enable CACREF pin input.
R/W
b3 to b1
FMCS[2:0]
Measurement Target Clock Select
b3
R/W
b5, b4
TCSS[1:0]
Measurement Target Clock
Frequency Division Ratio Select
b5 b4
R/W
b7, b6
EDGES[1:0]
Valid Edge Select
b7 b6
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b1
0: Main clock
1: Sub clock
0: HOCO clock
1: MOCO clock
0: LOCO clock
1: Peripheral module clock (PCLKB)
0: IWDTCLK clock
1: Setting prohibited.
0: No division
1: ×1/4 clock
0: ×1/8 clock
1: ×1/32 clock.
0: Rising edge
1: Falling edge
0: Both rising and falling edges
1: Setting prohibited.
Note 1. Set the CACR1 register when the CACR0.CFME bit is 0.
CACREFE bit (CACREF Pin Input Enable)
The CACREFE bit enables the CACREF pin input.
FMCS[2:0] bits (Measurement Target Clock Select)
The FMCS[2:0] bits select the measurement target clock whose frequency is to be measured.
TCSS[1:0] bits (Measurement Target Clock Frequency Division Ratio Select)
The TCSS[1:0] bits select the division ratio of the measurement target clock.
EDGES[1:0] bits (Valid Edge Select)
The EDGES[1:0] bits select the valid edge for the reference signal.
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9.2.3
9. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Control Register 2 (CACR2)
Address(es): CAC.CACR2 4004 4602h
b7
Value after reset:
b6
b5
b4
DFS[1:0]
RCDS[1:0]
0
0
0
0
b3
b2
b1
b0
RSCS[2:0]
0
0
RPS
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPS
Reference Signal Select
0: CACREF pin input
1: Internal clock (internally generated signal).
R/W
b3 to b1
RSCS[2:0]
Measurement Reference Clock
Select
b3
R/W
b5, b4
RCDS[1:0]
Measurement Reference Clock
Frequency Division Ratio Select
b5 b4
R/W
b7, b6
DFS[1:0]
Digital Filter Select
b7 b6
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b1
0: Main clock
1: Sub clock
0: HOCO clock
1: MOCO clock
0: LOCO clock
1: Peripheral module clock (PCLKB)
0: IWDTCLK clock
1: Setting prohibited.
0: ×1/32 clock
1: ×1/128 clock
0: ×1/1024 clock
1: ×1/8192 clock.
0 0: Disable digital filtering
0 1: Use sampling clock for the digital filter as the frequency
measuring clock
1 0: Use sampling clock for the digital filter as the frequency
measuring clock divided by 4
1 1: Use sampling clock for the digital filter as the frequency
measuring clock divided by 16.
Note 1. Set the CACR2 register when the CACR0.CFME bit is 0.
RPS bit (Reference Signal Select)
The RPS bit selects whether to use the CACREF pin input or an internal clock (internally generated signal) as the
reference signal.
RSCS[2:0] bits (Measurement Reference Clock Select)
The RSCS[2:0] bits select the reference clock for measurement.
RCDS[1:0] bits (Measurement Reference Clock Frequency Division Ratio Select)
The RCDS[1:0] bits select the division ratio of the reference clock when an internal reference clock is selected (RPS =
1). When RPS = 0 (CACREF pin is used as the reference clock source), the reference clock is not divided.
DFS[1:0] bits (Digital Filter Select)
Setting the DFS[1:0] bits enables or disables the digital filter and selects its sampling clock.
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9.2.4
9. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Interrupt Control Register (CAICR)
Address(es): CAC.CAICR 4004 4603h
b7
—
Value after reset:
b6
b5
b4
OVFFC MENDF FERRF
L
CL
CL
0
0
0
0
b3
—
0
b2
b1
b0
OVFIE MENDI FERRI
E
E
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FERRIE
Frequency Error Interrupt Request
Enable
0: Disable frequency error interrupt request
1: Enable frequency error interrupt request.
R/W
b1
MENDIE
Measurement End Interrupt
Request Enable
0: Disable measurement end interrupt request
1: Enable measurement end interrupt request.
R/W
b2
OVFIE
Overflow Interrupt Request Enable 0: Disable overflow interrupt request
1: Enable overflow interrupt request.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
FERRFCL
FERRF Clear
When 1 is written to this bit, the FERRF flag is cleared. This
bit is read as 0.
R/W
b5
MENDFCL
MENDF Clear
When 1 is written to this bit, the MENDF flag is cleared. This
bit is read as 0.
R/W
b6
OVFFCL
OVFF Clear
When 1 is written to this bit, the OVFF flag is cleared. This bit
is read as 0.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
FERRIE bit (Frequency Error Interrupt Request Enable)
The FERRIE bit enables the frequency error interrupt request.
MENDIE bit (Measurement End Interrupt Request Enable)
The MENDIE bit enables the measurement end interrupt request.
OVFIE bit (Overflow Interrupt Request Enable)
The OVFIE bit enables the overflow interrupt request.
FERRFCL bit (FERRF Clear)
Setting the FERRFCL bit to 1 clears the FERRF flag.
MENDFCL bit (MENDF Clear)
Setting the MENDFCL bit to 1 clears the MENDF flag.
OVFFCL bit (OVFF Clear)
Setting the OVFFCL bit to 1 clears the OVFF flag.
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9.2.5
9. Clock Frequency Accuracy Measurement Circuit (CAC)
CAC Status Register (CASTR)
Address(es): CAC.CASTR 4004 4604h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
OVFF MENDF FERRF
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FERRF
Frequency Error Flag
0: Clock frequency is within the allowable range
1: Clock frequency has deviated beyond the allowable range
(frequency error).
R
b1
MENDF
Measurement End Flag
0: Measurement is in progress
1: Measurement ended.
R
b2
OVFF
Overflow Flag
0: The counter has not overflowed
1: The counter overflowed.
R
b7 to b3
—
Reserved
These bits are read as 0.
R
FERRF flag (Frequency Error Flag)
The FERRF flag indicates a deviation of the clock frequency from the set value (frequency error).
[Setting condition]
The clock frequency is outside the allowable range defined by the CAULVR and CALLVR registers.
[Clearing condition]
1 is written to the FERRFCL bit.
MENDF flag (Measurement End Flag)
The MENDF flag indicates the end of measurement.
[Setting condition]
Measurement ends.
[Clearing condition]
1 is written to the MENDFCL bit.
OVFF flag (Overflow Flag)
The OVFF flag indicates that the counter overflowed.
[Setting condition]
The counter overflows.
[Clearing condition]
1 is written to the OVFFCL bit.
9.2.6
CAC Upper-Limit Value Setting Register (CAULVR)
Address(es): CAC.CAULVR 4004 4606h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CAULVR is a 16-bit read/write register that specifies the upper value of the allowable range. When the counter value
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9. Clock Frequency Accuracy Measurement Circuit (CAC)
rises above the value specified in this register, a frequency error is detected. Write to this register when the
CACR0.CFME bit is 0.
The counter value stored in CACNTBR can vary depending on the difference between the phases of the digital filter and
edge-detection circuit, and the signal on the CACREF pin. Ensure that this setting allows an adequate margin.
9.2.7
CAC Lower-Limit Value Setting Register (CALLVR)
Address(es): CAC.CALLVR 4004 4608h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CALLVR is a 16-bit read/write register that specifies the lower value of the allowable range. When the counter value
falls below the value specified in this register, a frequency error is detected. Write to this register when the
CACR0.CFME bit is 0.
The counter value stored in CACNTBR can vary depending on the difference between the phases of the digital filter and
edge-detection circuit, and the signal on the CACREF pin. Ensure that this setting allows an adequate margin.
9.2.8
CAC Counter Buffer Register (CACNTBR)
Address(es): CAC.CACNTBR 4004 460Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CACNTBR is a 16-bit read-only register that retains the measurement result.
9.3
9.3.1
Operation
Measuring Clock Frequency
The CAC measures the clock frequency using the CACREF pin input or an internal clock as a reference. Figure 9.2
shows an operating example of the CAC.
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CACREF pin or
internal clock
1
0
CFME bit in CACR0
1
0
9. Clock Frequency Accuracy Measurement Circuit (CAC)
0 is written to
CFME bit.
1 is written to
CFME bit.
Counter value
FFFFh
Counter is
cleared by writing
0 to CFME bit.
After 1 is written to CFME bit, counting
starts at the first valid edge.
CAULVR
CALLVR
0000h
Time
CACNTBR
FERRF flag in CASTR
(frequency error flag)
1
0
MENDF flag in CASTR
(measurement end flag)
1
0
0000h
7FFFh
BFFFh
1 is written to MENDFCL
bit in CAICR.
(1)
(2)
(3)
(4)
3FFFh
1 is written to FERRFCL
bit in CAICR.
1 is written to FERRFCL
bit in CAICR.
1 is written to MENDFCL
bit in CAICR.
1 is written to MENDFCL
bit in CAICR.
(5)
(6)
When the CACREF pin input is used as a reference:
In CACR1: CACREFE bit = 1, EDGES[1:0] bits = 00b
CAULVR register = AAAAh, CALLVR register = 5555h
When the internal clock is used as a reference:
In CACR1: CACREFE bit = 0, EDGES[1:0] bits = 00b
CAULVR register = AAAAh, CALLVR register = 5555h
Figure 9.2
CAC operating example
1. Before writing 1 to CACR0.CFME, set CACR1 and CACR2 to define the measurement target clock and
measurement reference clock. Writing 1 to the CACR0.CFME bit enables clock frequency measurement.
2. The timer starts counting up if the valid edge selected by the CACR1.EDGES[1:0] bits is input from the
measurement reference clock. The valid edge is a rising edge (CACR1.EDGES[1:0] = 00b) as shown in Figure 9.2.
3. When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of
CAULVR and CALLVR. If both CACNTBR ≤ CAULVR and CACNTBR ≥ CALLVR are true, only the MENDF
flag in CASTR is set to 1 because the clock frequency is correct. If the MENDIE bit in CAICR is 1, a measurement
end interrupt is generated.
4. When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of
CAULVR and CALLVR. If CACNTBR > CAULVR, the FERRF flag in CASTR is set to 1 because the clock
frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. The MENDF flag
in CASTR is set to 1 at the end of measurement. If the MENDIE bit in CAICR is 1, a measurement end interrupt is
generated.
5. When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of
CAULVR and CALLVR. If CACNTBR < CALLVR, the FERRF flag in CASTR is set to 1 because the clock
frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. The MENDF flag
in CASTR is set to 1 at the end of measurement. If the MENDIE bit in CAICR is 1, a measurement end interrupt is
generated.
6. When the CFME bit in CACR0 is 1, the counter value is transferred in CACNTBR and compared with the values of
CAULVR and CALLVR every time a valid edge is input. Writing 0 to the CFME bit in CACR0 clears the counter
and stops counting up.
9.3.2
Digital Filtering of Signals on CACREF Pin
The CACREF pin has a digital filter and levels on the CACREF pin are transmitted to the internal circuitry after three
consecutive matches at the selected sampling interval. The same level continues to be transmitted internally until the
level on the pin has three consecutive matches again. Enabling and disabling of the digital filter and its sampling clock
are selectable.
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9. Clock Frequency Accuracy Measurement Circuit (CAC)
The counter value transferred in CACNTBR might be in error by up to one cycle of the sampling clock because of the
difference between the phases of the digital filter and the signal input to the CACREF pin. When a frequency dividing
clock is selected as a count source clock, the counter value error is obtained by the following formula:
Counter value error = (1 cycle of the count source clock) / (1 cycle of the sampling clock)
9.4
Interrupt Requests
The CAC generates three types of interrupt request:
Frequency error interrupt
Measurement end interrupt
Overflow interrupt.
When an interrupt source is generated, the corresponding status flag becomes 1. Table 9.3 provides information on the
CAC interrupt requests.
Table 9.3
CAC interrupt requests
Interrupt request
Interrupt enable bit
Status flag
Interrupt source
Frequency error
interrupt
CAICR.FERRIE
CASTR.FERRF
The result of comparing CACNTBR with CAULVR and CALLVR
is either CACNTBR > CAULVR or CACNTBR < CALLVR
Measurement end
interrupt
CAICR.MENDIE
CASTR.MENDF
Valid edge is input from the CACREF pin or internal clock
Measurement end interrupt does not occur at the first valid
edge after writing 1 to the CACR0.CFME bit.
Overflow interrupt
CAICR.OVFIE
CASTR.OVFF
The counter overflows
9.5
9.5.1
Usage Note
Settings for the Module-Stop State
The Module Stop Control Register C (MSTPCRC) can enable or disable CAC operation. The CAC is stopped after a
reset. The registers become accessible on release from the module-stop state. For details, see section 10, Low Power
Modes.
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10. Low Power Modes
10.
Low Power Modes
10.1
Overview
The MCU has several functions for reducing power consumption, such as setting clock dividers, stopping modules,
selecting power control mode in Normal mode, and transitioning to low power modes.
Table 10.1 lists the specifications of functions to reduce power consumption. Table 10.2 lists the conditions to transition
to low power modes, the states of the CPU and peripheral modules, and the method for canceling each mode. After a
reset, the MCU enters the program execution state, but only the DTC and SRAM operate.
Table 10.1
Specifications of low power mode functions
Parameter
Specification
Reducing power consumption by
switching clock signals
The frequency division ratio can be selected independently for the system clock (ICLK), peripheral
module clock (PCLKB and PCLKD)*1
Module stop
Functions can be stopped independently for each peripheral module
Low power modes
Sleep mode
Software Standby mode
Snooze mode.
Power control modes
Power consumption can be reduced in Normal, Sleep, and Snooze mode by selecting an
appropriate operating power control mode according to the operating frequency and voltage.
Five operating power control modes are available:
- High-speed mode
- Middle-speed mode
- Low-speed mode
- Low-voltage mode
- Subosc-speed mode.
Note 1. For details, see section 8, Clock Generation Circuit.
Table 10.2
Operating conditions of each low power mode (1 of 2)
Parameter
Sleep mode
Software Standby mode
Snooze mode*1
Transition condition
WFI instruction while
SBYCR.SSBY = 0
WFI instruction while
SBYCR.SSBY = 1
Snooze request in
Software Standby mode.
SNZCR.SNZE = 1
Canceling method
All interrupts.
Any reset available in the
mode.
Interrupts shown in Table
10.3. Any reset available in
the mode.
Interrupts shown in Table
10.3. Any reset available in
the mode.
State after cancellation by an interrupt
Program execution state
(interrupt processing)
Program execution state
(interrupt processing)
Program execution state
(interrupt processing)
State after cancellation by a reset
Reset state
Reset state
Reset state
Main clock oscillator
Selectable
Stop
Selectable*2
Sub-clock oscillator
Selectable
Selectable
Selectable
High-speed on-chip oscillator
Selectable
Stop
Selectable
Middle-speed on-chip oscillator
Selectable
Stop
Selectable
Low-speed on-chip oscillator
Selectable
Selectable
Selectable
IWDT-dedicated on-chip oscillator
Selectable*4
Selectable*4
Selectable*4
Oscillation stop detection function
Selectable
Operation prohibited
Operation prohibited
Selectable
Selectable*3
Selectable
Clock/buzzer output function
CPU
Stop (Retained)
Stop (Retained)
Stop (Retained)
SRAM
Operating
Stop (Retained)
Selectable
Flash memory
Operating
Stop (Retained)
Stop (Retained)
Data Transfer Controller (DTC)
Selectable
Stop (Retained)
Selectable
USB 2.0 Full-Speed Module (USBFS)
Selectable
Stop (Retained)*5
Operation prohibited*5
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Table 10.2
10. Low Power Modes
Operating conditions of each low power mode (2 of 2)
Parameter
Sleep mode
Software Standby mode
Snooze mode*1
Watchdog Timer (WDT)
Selectable*4
Stop (Retained)
Stop (Retained)
Independent Watchdog Timer (IWDT)
Selectable*4
Selectable*4
Selectable*4
Realtime clock (RTC)
Selectable
Selectable
Selectable
Asynchronous General Purpose Timer
(AGTn, n = 0, 1)
Selectable
Selectable*6
Selectable*6
14-Bit A/D Converter (ADC14)
Selectable
Stop (Retained)
Selectable*10
12-Bit D/A Converter (DAC12)
Selectable
Stop (Retained)
Selectable
Capacitive Touch Sensing Unit (CTSU)
Selectable
Stop (Retained)
Selectable
Data Operation Circuit (DOC)
Selectable
Stop (Retained)
Selectable
Serial Communications Interface (SCI0)
Selectable
Stop (Retained)
Selectable*9
Serial Communications Interface
(SCIn, n = 1, 9)
Selectable
Stop (Retained)
Operation prohibited
I2C Bus Interface (IIC0)
Selectable
Selectable
Operation prohibited
I2C Bus Interface (IIC1)
Selectable
Stop (Retained)
Operation prohibited
Event Link Controller (ELC)
Selectable
Stop (Retained)
Selectable*7
Low-Power Analog Comparator (ACMPLP0)
Selectable
Selectable*8
Selectable*8
Low-Power Analog Comparator (ACMPLP1)
Selectable
Selectable*8
Selectable*8
NMI, IRQn (n = 0 to 7) pin interrupt
Selectable
Selectable
Selectable
Key Interrupt Function (KINT)
Selectable
Selectable
Selectable
Low voltage detection (LVD)
Selectable
Selectable
Selectable
Power-on reset circuit
Operating
Operating
Operating
Other peripheral modules
Selectable
Stop (Retained)
Operation prohibited
I/O Ports
Operating
Retained
Operating
Note:
Selectable means that operating or not operating can be selected by the control registers.
Stop (Retained) means that the contents of the internal registers are retained but the operations are suspended.
Operation prohibited means that the function must be stopped before entering Software Standby mode.
Otherwise, proper operation is not guaranteed in Snooze mode.
Note 1. All modules whose module-stop bits are 0 start as soon as PCLKs are supplied after entering Snooze mode. To
avoid an increasing power consumption in Snooze mode, set the module-stop bit of modules that are not
required in Snooze mode to 1 before entering Software Standby mode.
Note 2. When using SCI0 in Snooze mode, the MOSCCR.MOSTP bit must be 1.
Note 3. Stopped when the clock output source select bits (CKOCR.CKOSEL[2:0]) are set to a value other than 010b
(LOCO) and 100b (SOSC).
Note 4. In IWDT-dedicated on-chip oscillator and IWDT, operating or stopping is selected by setting the IWDT Stop
Control bit (IWDTSTPCTL) in the Option Function Select Register 0 (OFS0) in IWDT auto start mode. In WDT,
operating or stopping is selected by setting the WDT Stop Control bit (WDTSTPCTL) in the Option Function
Select Register 0 (OFS0) in WDT auto start mode
Note 5. Detection of USBFS resumption is possible.
Note 6. AGT0 operation is possible when 100b (LOCO) or 110b (SOSC) is selected by the AGT0.AGTMR1.TCK[2:0] bits.
AGT1 operation is possible when 100b (LOCO), 110b (SOSC), or 101 (Underflow event signal from AGT0) is
selected by the AGT1.AGTMR1.TCK[2:0] bits.
Note 7. Event lists the restrictions described in section 10.9.13, ELC Event in Snooze Mode.
Note 8. Only VCOUT function is permitted. The VCOUT pin operates when ACMPLP uses no digital filter. For details on
digital filter, see section 33, Low-Power Analog Comparator (ACMPLP).
Note 9. Serial communication modes of SCI0 is only in asynchronous mode.
Note 10. When using the 14-bit A/D Converter in Snooze mode, the ADCMPCR.CMPAE or ADCMPCR.CMPBE bit must
be 1.
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Table 10.3
10. Low Power Modes
Available interrupt sources to transition to Normal mode from Snooze mode and Software Standby
mode
Interrupt source
Name
NMI
Software Standby mode
Snooze mode
Yes
Yes
Port
PORT_IRQn (n = 0 to 7)
Yes
Yes
LVD
LVD_LVD1
Yes
Yes
LVD_LVD2
Yes
Yes
IWDT
IWDT_NMIUNDF
Yes
Yes
USBFS
USBFS_USBR
Yes
Yes
RTC
RTC_ALM
Yes
Yes
RTC_PRD
Yes
Yes
KINT
KEY_INTKR
Yes
Yes
AGT1
AGT1_AGTI
Yes
Yes*3
AGT1_AGTCMAI
Yes
Yes
AGT1_AGTCMBI
Yes
Yes
ACMPLP
ACMP_LP0
Yes
Yes
IIC0
IIC0_WUI
Yes
No
ADC140
ADC140_WCMPM
No
Yes with SELSR0*1, *3
ADC140_WCMPUM
No
Yes with SELSR0*1, *3
SCI0_AM
No
Yes with SELSR0*1, *2
SCI0_RXI_OR_ERI
No
Yes with SELSR0*1, *2
DTC
DTC_COMPLETE
No
Yes with SELSR0*1, *3
DOC
DOC_DOPCI
No
Yes with SELSR0*1
CTSU
CTSU_CTSUFN
No
Yes with SELSR0*1
SCI0
Note 1. To use the interrupt request as a trigger for exiting Snooze mode, the request must be selected by SELSR0. See
section 12, Interrupt Controller Unit (ICU). When a trigger selected by SELSR0 occurs after executing a WFI
instruction and during the transition from Normal mode to Software Standby mode, the request can be accepted
depends on the timing of the occurrence.
Note 2. Only one of either SCI0_AM or SCI0_RXI_OR_ERI can be selected.
Note 3. The event that is enabled by the SNZEDCR register must not be used.
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10. Low Power Modes
SBYCR.SSBY = 0
Reset state
Sleep mode
WFI instruction*1
RES pin = High*2
SNZCR.SNZE = 1
All interrupts
Snooze mode
Interrupt shown in Table 10.3
Normal mode
(Program execution state)*3
Snooze end condition
shown in Table 10.8
Snooze requests
shown in Table 10.6
WFI instruction*1
SBYCR.SSBY = 1
Software Standby mode
Interrupt shown in Table 10.3
Low power mode (Program stopped state)
Note 1.
Note 2.
Note 3.
When an interrupt that acts as a trigger for cancel is received during a transition to the program stopped state after the execution of a WFI
instruction, the MCU executes interrupt exception handling instead of a transition to low power mode.
The MOCO is the source of the operating clock following a transition from the reset state to Normal mode.
The transition to Normal mode is made from an interrupt in Sleep mode, Software Standby mode, or Snooze mode. The clock source is
the same as before entering the low power mode.
Figure 10.1
10.2
Mode transitions
Register Descriptions
10.2.1
Standby Control Register (SBYCR)
Address(es): SYSTEM.SBYCR 4001 E00Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
SSBY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b14 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
SSBY
Software Standby
0: Sleep mode
1: Software Standby mode.
R/W
SSBY bit (Software Standby)
The SSBY bit specifies the transition destination after a WFI instruction is executed.
When the SSBY bit is set to 1, the MCU enters Software Standby mode after execution of a WFI instruction. When the
MCU returns to Normal mode from Software Standby mode by an interrupt, SSBY bit remains 1. The SSBY bit can be
cleared by writing 0 to the SSBY bit.
While the OSTDCR.OSTDE bit is 1, setting of SSBY bit is ignored. Even if SSBY bit is 1, the MCU enters Sleep mode
on execution of a WFI instruction.
While the FENTRYR.FENTRY0 bit 1 or the FENTRYR.FENTRYD bit is 1, setting of SSBY bit is ignored. Even if
SSBY bit is 1, the MCU enters Sleep mode on execution of a WFI instruction.
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10.2.2
10. Low Power Modes
Module Stop Control Register A (MSTPCRA)
Address(es): SYSTEM.MSTPCRA 4001 E01Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
MSTPA
22
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
Symbol
Bit name
Description
b21 to b0
—
Reserved
These bits are read as 1. The write value should be 1. R/W
R/W
b22
MSTPA22
Data Transfer Controller
Module Stop*1
Target module: DTC
0: Cancel the module-stop state
1: Enter the module-stop state.
b31 to b23
—
Reserved
These bits are read as 1. The write value should be 1. R/W
R/W
Note 1. When rewriting the MSTPA22 bit from 0 to 1, disable the DTC before setting the MSTPA22 bit.
10.2.3
Module Stop Control Register B (MSTPCRB)
Address(es): MSTP.MSTPCRB 4004 7000h
b31
b30
MSTPB MSTPB
31
30
Value after reset:
Value after reset:
b29
b28
b27
b26
b25
b24
b23
b22
—
—
—
—
—
—
—
—
—
MSTPB
22
b21
b20
b19
b18
MSTPB MSTPB
19
18
b17
b16
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
MSTPB
11
—
—
—
—
—
—
MSTPB
2
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MSTPB MSTPB
9
8
1
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b2
MSTPB2
Controller Area Network
0 Module Stop*1
Target module: CAN0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b7 to b3
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b8
MSTPB8
I2C Bus Interface 1
Module Stop
Target module: IIC1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b9
MSTPB9
I2C Bus Interface 0
Module Stop
Target module: IIC0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b10
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b11
MSTPB11
Universal Serial Bus 2.0
Full Speed Interface
Module Stop*2
Target module: USBFS
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b17 to b12
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
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10. Low Power Modes
Bit
Symbol
Bit name
Description
R/W
b18
MSTPB18
Serial Peripheral
Interface 1 Module Stop
Target module: SPI1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b19
MSTPB19
Serial Peripheral
Interface 0 Module Stop
Target module: SPI0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b21, b20
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b22
MSTPB22
Serial Communication
Interface 9 Module Stop
Target module: SCI9
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b29 to b23
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b30
MSTPB30
Serial Communication
Interface 1 Module Stop
Target module: SCI1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b31
MSTPB31
Serial Communication
Interface 0 Module Stop
Target module: SCI0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
Note 1. The MSTPB2 bit must be written while the oscillation of the clock controlled by this bit is stable. To enter Software
Standby mode after writing this bit, wait for 2 CAN clock (CANMCLK) cycles after writing, then execute a WFI
instruction.
Note 2. To enter Software Standby mode after writing the MSTPB11 bit, wait for 2 USB clock (UCLK) cycles after writing,
then execute a WFI instruction.
10.2.4
Module Stop Control Register C (MSTPCRC)
Address(es): MSTP.MSTPCRC 4004 7004h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MSTPC
31
—
—
MSTPC
28
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
1
b15
—
Value after reset:
MSTPC MSTPC
14
13
1
1
1
—
—
—
—
—
—
—
—
—
MSTPC
3
1
1
1
1
1
1
1
1
1
1
MSTPC MSTPC
1
0
1
1
Bit
Symbol
Bit name
Description
R/W
b0
MSTPC0
Clock Frequency
Accuracy Measurement
Circuit Module Stop*1
Target module: CAC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b1
MSTPC1
Cyclic Redundancy
Check Calculator Module
Stop
Target module: CRC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b2
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b3
MSTPC3
Capacitive Touch
Target module: CTSU
Sensing Unit Module Stop 0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b12 to b4
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b13
MSTPC13
Data Operation Circuit
Module Stop
Target module: DOC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b14
MSTPC14
Event Link Controller
Module Stop
Target module: ELC
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
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10. Low Power Modes
Bit
Symbol
Bit name
Description
R/W
b27 to b15
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b28
MSTPC28
Random Number
Generator Module Stop*2
Target module: TRNG
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b30, b29
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b31
MSTPC31
AES Module Stop
Target module: AES
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
Note 1. The MSTPC0 bit must be written while the oscillation of the clock to be controlled by this bit is stable. To enter
Software Standby mode after writing this bit, wait for 2 cycles of the slowest clock from the clocks output by the
oscillators, then execute a WFI instruction.
Note 2. Set the MSTPC28 bit to 0 once at the beginning of the program to initialize the unused circuit even if the TRNG is
not used in this MCU. See section 10.9.15, Module-Stop Function for an Unused Circuit.
10.2.5
Module Stop Control Register D (MSTPCRD)
Address(es): MSTP.MSTPCRD 4004 7008h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
MSTPD
29
—
—
—
—
—
—
—
—
MSTPD
20
—
—
—
MSTPD
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
MSTPD
14
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
MSTPD MSTPD
6
5
1
1
—
1
MSTPD MSTPD
3
2
1
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b2
MSTPD2
Asynchronous General
Purpose Timer 1 Module
Stop*1
Target module: AGT1
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b3
MSTPD3
Asynchronous General
Purpose Timer 0 Module
Stop*2
Target module: AGT0
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b4
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b5
MSTPD5
General PWM Timer 320
Module Stop
Target module: GPT320
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b6
MSTPD6
General PWM Timer 166 to
161 Module Stop
Target module: GPT166 to GPT161
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b13 to b7
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b14
MSTPD14
Port Output Enable for GPT
Module Stop
Target module: POEG
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b15
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b16
MSTPD16
14-Bit A/D Converter Module
Stop
Target module: ADC140
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b19 to b17
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
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10. Low Power Modes
Bit
Symbol
Bit name
Description
R/W
b20
MSTPD20
12-Bit D/A Converter Module
Stop
Target module: DAC12
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b28 to b21
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b29
MSTPD29
Low-Power Analog Comparator
Module Stop
Target module: ACMPLP
0: Cancel the module-stop state
1: Enter the module-stop state.
R/W
b31, b30
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
Note 1. When the count source is sub-clock oscillator or LOCO, AGT1 counting does not stop even if MSTPD2 is set to 1.
If the count source is the sub-clock oscillator or LOCO, this bit must be set to 1 except when accessing the AGT1
registers.
Note 2. When the count source is sub-clock oscillator or LOCO, AGT0 counting does not stop even if MSTPD3 is set to 1.
If the count source is the sub-clock oscillator or LOCO, this bit must be set to 1 except when accessing the AGT0
registers.
10.2.6
Operating Power Control Register (OPCCR)
Address(es): SYSTEM.OPCCR 4001 E0A0h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
OPCM
TSF
—
—
OPCM[1:0]
0
0
0
0
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
OPCM[1:0]
Operating Power Control Mode Select
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
OPCMTSF
Operating Power Control Mode
Transition Status Flag
0: Transition completed
1: During transition.
R
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: High-speed mode
1: Middle-speed mode
0: Low-voltage mode*1
1: Low-speed mode.
Note 1. HOCOCR.HCSTP must always be 0.
The OPCCR register is used to reduce power consumption in Normal mode, Sleep mode and Snooze mode. Power
consumption can be reduced according to the operating frequency and operating voltage used by the OPCCR setting.
For the procedure to change the operating power control modes, see section 10.5, Function for Lower Operating Power
Consumption.
OPCM[1:0] bits (Operating Power Control Mode Select)
The OPCM[1:0] bits select the operating power control mode in Normal mode, Sleep mode and Snooze mode.
Table 10.4 shows the relationship between the operating power control modes, the OPCM[1:0] and SOPCM bits settings.
Writing to OPCCR.OPCM[1:0] is prohibited while HOCOCR.HCSTP and OSCSF.HOCOSF are 0 (The oscillation of
the HOCO clock has not yet become stable).
OPCMTSF flag (Operating Power Control Mode Transition Status Flag)
The OPCMTSF flag indicates the switching control state when the operating power control mode is switched. This flag
becomes 1 when the OPCM bit is written, and 0 when mode transition completed. Read this flag and confirm that it is 0
before proceeding.
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10.2.7
10. Low Power Modes
Sub Operating Power Control Register (SOPCCR)
Address(es): SYSTEM.SOPCCR 4001 E0AAh
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
SOPC
MTSF
—
—
—
SOPC
M
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
SOPCM
Sub Operating Power Control Mode Select
0: Other than subosc-speed mode
1: Subosc-speed mode.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should
be 0.
R/W
b4
SOPCMTSF
Sub Operating Power Control Mode
Transition Status Flag
0: Transition completed
1: During transition.
R
b7 to b5
—
Reserved
These bits are read as 0. The write value should
be 0.
R/W
The SOPCCR register is used to reduce power consumption in Normal mode, Sleep mode and Snooze mode. Setting this
register initiates entry to and exit from subosc-speed mode. Subosc-speed mode is available only when using the subclock oscillator or LOCO without dividing the frequency.
For the procedure to change operating power control modes, see section 10.5, Function for Lower Operating Power
Consumption.
SOPCM bit (Sub Operating Power Control Mode Select)
The SOPCM bit selects the operating power control mode in Normal mode, Sleep mode and Snooze mode. Setting this
bit to 1 allows transition to subosc-speed mode. Setting this bit to 0 allows a return to the operating mode (operating
mode set by OPCCR.OPCM[1:0]) before the transition to subosc-speed mode.
Table 10.4 shows the relationship between the operating power control modes, the OPCM[1:0] and SOPCM bits settings.
SOPCMTSF flag (Sub Operating Power Control Mode Transition Status Flag)
The SOPCMTSF flag indicates the switching control state when the sub operating power control mode is switched. This
flag becomes 1 when the SOPCM bit is written, and 0 when mode transition completed. Read this flag and confirm that
it is 0 before proceeding.
Table 10.4 shows each operating power control mode.
Table 10.4
Operating power control mode
Operating power control mode
OPCM[1:0] bits
SOPCM bit
Power consumption
High-speed mode
00b
0
Middle-speed mode
01b
0
Low-voltage mode
10b
0
Low-speed mode
11b
0
Subosc-speed mode
xxb
1
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10.2.8
10. Low Power Modes
Snooze Control Register (SNZCR)
Address(es): SYSTEM.SNZCR 4001 E092h
b7
b6
b5
b4
b3
b2
SNZE
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b1
b0
SNZDT RXDRE
CEN
QEN
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RXDREQEN
RXD0 Snooze Request Enable
0: Ignore RXD0 falling edge in Software Standby mode
1: Detect RXD0 falling edge in Software Standby mode.
R/W
b1
SNZDTCEN
DTC Enable in Snooze mode
Enable DTC operation in Snooze mode:
0: Disable DTC operation
1: Enable DTC operation.
R/W
b6 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
SNZE
Snooze mode Enable
0: Disable Snooze mode
1: Enable Snooze mode.
R/W
RXDREQEN bit (RXD0 Snooze Request Enable)
The RXDREQEN bit specifies whether to detect a falling edge of the RXD0 pin in Software Standby mode. This bit is
only available when SCI0 is operating in asynchronous mode. To detect a falling edge of the RXD0 pin, set this bit
before entering Software Standby mode. When this bit is set to 1, a falling edge of the RXD0 pin in Software Standby
mode causes the MCU to enter Snooze mode.
SNZDTCEN bit (DTC Enable in Snooze mode)
The SNZDTCEN bit specifies whether to use the DTC and SRAM in Snooze mode. To use the DTC and SRAM in
Snooze mode, set this bit to 1 before entering Software Standby mode. When this bit is set to 1, the DTC can be activated
by setting IELSRn (ICU event link setting register n).
SNZE bit (Snooze mode Enable)
The SNZE bit specifies whether to enable a transition from Software Standby mode to Snooze mode. To use Snooze
mode, set this bit to 1 before entering Software Standby mode. When this bit is set to 1, a trigger as shown in Table 10.6
in Software Standby mode causes the MCU to enter Snooze mode. After the MCU transfers from Software Standby
mode or Snooze mode to Normal mode, clear the SNZE bit once then set it before re-entering Software Standby mode.
For details, see section 10.8, Snooze Mode.
10.2.9
Snooze End Control Register (SNZEDCR)
Address(es): SYSTEM.SNZEDCR 4001 E094h
b7
Value after reset:
b6
b5
SCI0U
MTED
—
—
0
0
0
b4
b3
b2
b1
b0
AD0UM AD0MA DTCNZ DTCZR AGTUN
TED
TED
RED
ED
FED
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
AGTUNFED
AGT1 Underflow Snooze End Enable
0: Disable the snooze end request
1: Enable the snooze end request.
R/W
b1
DTCZRED
Last DTC Transmission Completion Snooze
End Enable
0: Disable the snooze end request
1: Enable the snooze end request.
R/W
b2
DTCNZRED
Not Last DTC Transmission Completion
Snooze End Enable
0: Disable the snooze end request
1: Enable the snooze end request.
R/W
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10. Low Power Modes
Bit
Symbol
Bit name
Description
R/W
b3
AD0MATED
ADC140 Compare Match Snooze End Enable
0: Disable the snooze end request
1: Enable the snooze end request.
R/W
b4
AD0UMTED
ADC140 Compare Mismatch Snooze End
Enable
0: Disable the snooze end request
1: Enable the snooze end request.
R/W
b6, b5
—
Reserved
These bits are read as 0. The write value
should be 0.
R/W
b7
SCI0UMTED
SCI0 Address Mismatch Snooze End Enable
0: Disable the snooze end request
1: Enable the snooze end request.
R/W
To use a trigger shown in Table 10.8 as a condition to switch from Snooze mode to Software Standby mode, set the
associated bit in the SNZEDCR register to 1.
The event that is used to return to Normal mode from Snooze mode listed in Table 10.3 must not be enabled by
SNZEDCR.
AGTUNFED bit (AGT1 Underflow Snooze End Enable)
The AGTUNFED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by an AGT1
underflow. For details of the condition of the trigger, see section 20, Asynchronous General Purpose Timer (AGT).
DTCZRED bit (Last DTC Transmission Completion Snooze End Enable)
The DTCZRED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by completion
of the last DTC transmission, that is, CRA or CRB registers in the DTC is 0. For details of the condition of the trigger,
see section 14, Data Transfer Controller (DTC).
DTCNZRED bit (Not Last DTC Transmission Completion Snooze End Enable)
The DTCNZRED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by
completion of each DTC transmission, that is, CRA or CRB registers in the DTC is not 0. For details of the condition of
the trigger, see section 14, Data Transfer Controller (DTC).
AD0MATED bit (ADC140 Compare Match Snooze End Enable)
The AD0MATED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by an
ADC140 event when a conversion result matches the expected data. For details of the condition of the trigger, see section
30, 14-Bit A/D Converter (ADC14).
AD0UMTED bit (ADC140 Compare Mismatch Snooze End Enable)
The AD0UMTED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by an
ADC140 event when the conversion result does not match the expected data. For details of the condition of the trigger,
see section 30, 14-Bit A/D Converter (ADC14).
SCI0UMTED bit (SCI0 Address Mismatch Snooze End Enable)
The SCI0UMTED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by an SCI0
event when an address received in Software Standby mode does not match the expected data. For details of the condition
of the trigger, see section 25, Serial Communications Interface (SCI). Only set this bit to 1 when SCI0 is operating in
asynchronous mode.
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10. Low Power Modes
Snooze Request Control Register (SNZREQCR)
Address(es): SYSTEM.SNZREQCR 4001 E098h
b31
—
Value after reset:
Value after reset:
b30
b29
b28
SNZRE SNZRE SNZRE
QEN30 QEN29 QEN28
b27
b26
—
—
b25
b24
b23
SNZRE SNZRE SNZRE
QEN25 QEN24 QEN23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
SNZRE
QEN17
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE SNZRE
QEN7 QEN6 QEN5 QEN4 QEN3 QEN2 QEN1 QEN0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SNZREQEN0
Snooze Request Enable 0
Enable IRQ0 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b1
SNZREQEN1
Snooze Request Enable 1
Enable IRQ1 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b2
SNZREQEN2
Snooze Request Enable 2
Enable IRQ2 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b3
SNZREQEN3
Snooze Request Enable 3
Enable IRQ3 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b4
SNZREQEN4
Snooze Request Enable 4
Enable IRQ4 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b5
SNZREQEN5
Snooze Request Enable 5
Enable IRQ5 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b6
SNZREQEN6
Snooze Request Enable 6
Enable IRQ6 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b7
SNZREQEN7
Snooze Request Enable 7
Enable IRQ7 pin snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b16 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b17
SNZREQEN17
Snooze Request Enable 17
Enable Key Interrupt snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b22 to b18
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b23
SNZREQEN23
Snooze Request Enable 23
Enable ACMPLP0 snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b24
SNZREQEN24
Snooze Request Enable 24
Enable RTC alarm snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b25
SNZREQEN25
Snooze Request Enable 25
Enable RTC period snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b27, b26
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28
SNZREQEN28
Snooze Request Enable 28
Enable AGT1 underflow snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
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Bit
Symbol
Bit name
Description
R/W
b29
SNZREQEN29
Snooze Request Enable 29
Enable AGT1 compare match A snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b30
SNZREQEN30
Snooze Request Enable 30
Enable AGT1 compare match B snooze request:
0: Disable the snooze request
1: Enable the snooze request.
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
The SNZREQCR register controls which trigger causes the MCU to switch from Software Standby mode to Snooze
mode. If a trigger is selected as a request to cancel Software Standby mode by setting the WUPEN register, see section
12, Interrupt Controller Unit (ICU), the MCU enters Normal mode when the trigger is generated while the associated bit
of the SNZREQCR is 1. The setting of the WUPEN register always has higher priority than the setting of the
SNZREQCR register. For details, see section 10.8, Snooze Mode and section 12, Interrupt Controller Unit (ICU).
10.2.11
Flash Operation Control Register (FLSTOP)
Address(es): SYSTEM.FLSTOP 4001 E09Eh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
FLSTP
F
—
—
—
FLSTO
P
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FLSTOP
Selecting ON/OFF of the Flash
Memory Operation
0: Code flash and data flash memory operates
1: Code flash and data flash memory stops.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
FLSTPF
Flash Memory Operation Status Flag
0: Transition completed
1: During transition (from the flash-stop-status to flashoperating-status or flash-operating-status to flash-stopstatus).
R
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
FLSTOP bit (Selecting ON/OFF of the Flash Memory Operation)
The FLSTOP bit enables or disables flash memory. The FLSTOP bit must be written in a program executing in the
SRAM. To use an interrupt when the FLSTOP bit is 1, be sure to place the interrupt vector in the SRAM. Set this bit to 0
when low voltage mode is not selected.
Note 1. When changing the value of the FLSTOP bit from 1 to 0 to start flash memory operation, ensure the FLSTPF flag
is 0 and OSCSF.HOCOSF is 1 before restarting access to the flash memory. After that, instructions can be
executed in the code flash memory.
Note 2. Writing to FLSTOP.FLSTOP is prohibited while HOCOCR.HCSTP and OSCSF.HOCOSF are 0 (HOCO is in
stabilization wait counting).
FLSTPF flag (Flash Memory Operation Status Flag)
The FLSTPF flag indicates the status of the transition from the flash-stop-status to flash-operating-status or from the
flash-operating-status to the flash-stop-status. When the transition completes, the flag is read as 0. When using flash
memory again after stopping it once, make sure that the FLSTPF flag is 0 before proceeding.
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10.2.12
10. Low Power Modes
System Control OCD Control Register (SYOCDCR)
Address(es): SYSTEM.SYOCDCR 4001 E40Eh
b7
b6
b5
b4
b3
b2
b1
b0
DBGEN
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
DBGEN
Debugger Enable bit
0: On-chip debugger is disabled
1: On-chip debugger is enabled.
Set to 1 first in on-chip debug mode.
R/W
DBGEN bit (Debugger Enable bit)
DBGEN bit enables the on-chip debug mode. This bit must be set to 1 first in the on-chip debugger mode.
[Setting condition]
Writing 1 to the bit when the debugger is connected.
[Clearing condition]
Power-on reset is generated
Writing 0 to the bit.
10.3
Reducing Power Consumption by Switching Clock Signals
When the SCKDIVCR.ICK[2:0], PCKB[2:0], and PCKD[2:0] bits are set, the clock frequency changes. The CPU, DTC,
Flash, and SRAM use the operating clock specified by the ICK[2:0] bits.
Peripheral modules use the operating clock specified by the PCKB[2:0] and PCKD[2:0] bits.
The flash memory interface uses the operating clock specified by the ICK[2:0] bits.
For details, see section 8, Clock Generation Circuit.
10.4
Module-Stop Function
The module-stop function can be set for each on-chip peripheral module.
When the MSTPmi bit (m = A to D; i = 31 to 0) in MSTPCRA to MSTPCRD is set to 1, the specified module stops
operating and enters the module-stop state, but the CPU continues to operate independently. Clearing the MSTPmi bit to
0 cancels the module-stop state, allowing the module to resume operation at the end of the bus cycle.
The internal states of modules are retained in the module-stop state.
After a reset is canceled, all modules other than the DTC is placed in the module-stop state. Do not access the module
while the corresponding MSTPmi bit is 1, otherwise the read/write data or the operation of the module is not guaranteed.
Also, do not set 1 to the MSTPmi bit while the corresponding module is accessed.
10.5
Function for Lower Operating Power Consumption
By selecting an appropriate operating power consumption control mode according to the operating frequency and
operating voltage, power consumption can be reduced in Normal mode, Sleep mode and Snooze mode.
10.5.1
Setting Operating Power Control Mode
Make sure that the operating condition such as the voltage range and the frequency range is always within the specified
range before and after switching the operating power control modes.
This section provides example procedures for switching operating power control modes.
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Table 10.5
10. Low Power Modes
Available oscillators in each mode
Oscillator
Mode
High-speed onchip oscillator
Middle-speed onchip oscillator
Low-speed onchip oscillator
Main clock
oscillator
Sub-clock
oscillator
IWDT-dedicated
on-chip oscillator
High-speed
Available
Available
Available
Available
Available
Available
Middle-speed
Available
Available
Available
Available
Available
Available
Low-voltage
Available
Available
Available
Available
Available
Available
Low-speed
Available
Available
Available
Available
Available
Available
Subosc-speed
N/A
N/A
Available
N/A
Available
Available
(1)
Switching from a higher power mode to a lower power mode
Example 1: From high-speed mode to low-speed mode:
(Operation in high-speed mode)
↓
Change the oscillator to what is used in low-speed mode. Set the frequency of each clock lower than the maximum
operating frequency in low-speed mode.
↓
Turn off the oscillator that is not required in low-speed mode
↓
Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed)
↓
Set the OPCCR.OPCM bit to 11b (low-speed mode)
↓
Confirm that OPCCR.OPCMTSF flag is 0 (indicates transition completed)
↓
(Operation in low-speed mode)
Example 2: From high-speed mode to subosc-speed mode
(Operation in high-speed mode)
↓
Switch the clock source to sub-clock oscillator. Turn off HOCO, MOCO, and main oscillator
↓
Confirm that all clock sources other than the sub-clock oscillator are stopped
↓
Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed)
↓
Set the SOPCCR.SOPCM bit to 1 (subosc-speed mode)
↓
Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed)
↓
(Operation in subosc-speed mode)
(2)
Switching from a lower power mode to a higher power mode
Example 1: From subosc-speed mode to high-speed mode
(Operation in subosc-speed mode)
↓
Confirm that the SOPCCR.SOPCMTSF flag is 0 (indicates transition completed)
↓
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10. Low Power Modes
Set SOPCCR.SOPCM bit to 0 (high-speed mode)
↓
Confirm that SOPCCR.SOPCMTSF flag is 0 (indicates transition completed)
↓
Turn on the oscillator needed in high-speed mode
↓
Set the frequency of each clock to lower than the maximum operating frequency for high-speed mode
↓
(Operation in high-speed mode)
Example 2: From low-speed mode to high-speed mode
(Operation in low-speed mode)
↓
Confirm that OPCCR.OPCMTSF flag is 0 (indicates transition completed)
↓
Set the OPCCR.OPCM bit to 00b (high-speed mode)
↓
Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed)
↓
Turn on any oscillator needed in high-speed mode
↓
Set the frequency of each clock to lower than the maximum operating frequency for high-speed mode
↓
(Operation in high-speed mode)
10.5.2
Operating Range
High-speed mode
The maximum operating frequency during flash read is 32 MHz for ICLK. The operating voltage range is 2.4 to 5.5 V
during flash read. However, for ICLK, the maximum operating frequency during flash read is 16 MHz when the
operating voltage is 2.4 V or larger and smaller than 2.7 V.
During flash programming/erasure, the operating frequency range is 1 to 32 MHz and the operating voltage range is 2.7
to 5.5 V.
Figure 10.2 shows the operating voltages and frequencies in high-speed mode.
VCC
[V]
VCC
[V]
5.5
5.5
P/E
except P/E
2.7
2.7
2.4
2.4
1.8
1.8
1.6
1.6
0.032768
Figure 10.2
1
4
8
12
16
32
ICLK
[MHz]
0.032768
1
4
8
12
16
32
ICLK
[MHz]
Operating voltages and frequencies in high-speed mode
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10. Low Power Modes
Middle-speed mode
The power consumption of this mode is lower than that of high-speed mode under the same conditions.
The maximum operating frequency during flash read is 12 MHz for ICLK. The operating voltage range is 1.8 to 5.5 V
during flash read. However, for ICLK, the maximum operating frequency during flash read is 8 MHz when the operating
voltage is 1.8 V or larger and smaller than 2.4 V.
During flash programming/erasure, the operating frequency range is 1 to 12 MHz and the operating voltage range is 1.8
to 5.5 V. The maximum operating frequency during flash programming/erasure is 8 MHz when the operating voltage is
1.8 V or larger and smaller than 2.4 V.
Figure 10.3 shows the operating voltages and frequencies in middle-speed mode.
VCC
[V]
VCC
[V]
5.5
5.5
2.7
2.7
except P/E
2.4
2.4
1.8
1.8
1.6
1.6
0.032768
Figure 10.3
1
4
8
12
16
32
ICLK
[MHz]
P/E
0.032768
1
4
8
12
16
32
ICLK
[MHz]
Operating voltages and frequencies in middle-speed mode
Low-voltage mode
After a reset is canceled, operation is started from this mode.
The maximum operating frequency during flash read is 4 MHz for ICLK. The operating voltage range is 1.6 to 5.5 V
during flash read.
During flash programming/erasure, the operating frequency range is 1 to 4 MHz and the operating voltage range is 1.8 to
5.5 V.
Figure 10.4 shows the operating voltages and frequencies in low voltage mode.
VCC
[V]
VCC
[V]
5.5
5.5
2.7
2.7
P/E
except P/E
2.4
2.4
1.8
1.8
1.6
1.6
0.032768
Figure 10.4
1
4
8
12
16
32
ICLK
[MHz]
0.032768
1
4
8
12
16
32
ICLK
[MHz]
Operating voltages and frequencies in low voltage mode
Low-speed mode
The maximum operating frequency during flash read is 1 MHz for ICLK. The operating voltage range is 1.8 to 5.5 V
during flash read.
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10. Low Power Modes
P/E operations for flash memory are prohibited.
Figure 10.5 shows the operating voltages and frequencies in low-speed mode.
VCC
[V]
VCC
[V]
5.5
5.5
2.7
2.7
except P/E
2.4
2.4
1.8
1.8
1.6
1.6
0.032768
Figure 10.5
1
4
8
12
16
32
ICLK
[MHz]
P/E is prohibited
0.032768
1
4
8
12
16
32
ICLK
[MHz]
Operating voltages and frequencies in low-speed mode
Subosc-speed mode
The maximum operating frequency during flash read is 37.6832 kHz for ICLK. The operating voltage range is 1.8 to 5.5
V during flash read. P/E operations for flash memory are prohibited.
Using the oscillators other than the sub-clock oscillator or low-speed on-chip oscillator is prohibited.
Figure 10.6 shows the operating voltages and frequencies in subosc-speed mode.
VCC
[V]
VCC
[V]
5.5
5.5
2.7
except
2.7
P/E
2.4
2.4
1.8
1.8
1.6
1.6
10.6
10.6.1
4
8
12
16
32
ICLK
[MHz]
2
83
76 8
03 6
0. 327 28
0 5
0. 278
0
0.
2
83
76 8
03 6
0. 327 28
0 5
0. 278
0
0.
Figure 10.6
1
P/E is prohibited
1
4
8
12
16
32
ICLK
[MHz]
Operating voltages and frequencies in subosc-speed mode
Sleep Mode
Transition to Sleep Mode
When a WFI instruction is executed while SBYCR.SSBY bit is 0, the MCU enters Sleep mode. In this mode, the CPU
stops operating but the contents of its internal registers are retained. Other peripheral functions do not stop. Available
resets or interrupts in Sleep mode cause the MCU to cancel Sleep mode. All interrupt sources are available. If using an
interrupt to cancel Sleep mode, you must set the associated IELSRn register before executing a WFI instruction. For
details, see section 12, Interrupt Controller Unit (ICU).
Counting by IWDT stops when the MCU enters Sleep mode while the IWDT is in auto-start mode and the
OFS0.IWDTSTPCTL bit is 1 (IWDT stops in Sleep mode, Software Standby mode or Snooze mode).
Counting by IWDT continues when the MCU enters Sleep mode while the IWDT is in auto-start mode and the
OFS0.IWDTSTPCTL bit is 0 (IWDT does not stop in Sleep mode, Software Standby mode or Snooze mode).
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Counting by WDT stops when the MCU enters Sleep mode while the WDT is in auto-start mode and the
OFS0.WDTSTPCTL bit is 1 (WDT stops in Sleep mode). Similarly, counting by WDT stops when the MCU enters
Sleep mode while the WDT is in register start mode and the WDTCSTPR.SLCSTP bit in is 1 (WDT stops in Sleep
mode).
Counting by WDT continues when the MCU enters Sleep mode while the WDT is in auto-start mode and the OFS0.
WDTSTPCTL bit is 0 (WDT does not stop in Sleep mode). Similarly, counting by WDT continues when the MCU enters
Sleep mode while the WDT is in register start mode and the WDTCSTPR.SLCSTP bit is 0 (WDT does not stop in Sleep
mode).
10.6.2
Canceling Sleep Mode
Sleep mode is canceled by any interrupt, RES pin reset, a power-on reset, a voltage monitor reset, an SRAM parity error
reset, or a reset caused by an IWDT or a WDT underflow.
1. Canceling by an interrupt
When an available interrupt request is generated, Sleep mode is canceled and the MCU starts interrupt handling.
2. Canceling by RES pin reset
When RES pin is driven low, the MCU enters the reset state. Make sure to keep RES pin low for the time period
specified in section 41, Electrical Characteristics. When RES pin is driven high after the specified time period, the
CPU starts the reset exception handling.
3. Canceling by IWDT reset
Sleep mode is canceled by an internal reset generated by an IWDT underflow and the MCU starts the reset
exception handling. However, IWDT stops in Sleep mode and an internal reset for canceling Sleep mode is not
generated in the following conditions:
OFS0.IWDTSTRT = 0 and OFS0.IWDTSTPCTL = 1.
4. Canceling by WDT reset
Sleep mode is canceled by an internal reset generated by a WDT underflow and the MCU starts the reset exception
handling. However, WDT stops in Sleep mode even when counting in Normal mode and an internal reset for
canceling Sleep mode is not generated in the following conditions:
OFS0.WDTSTRT = 0 (auto-start mode) and OFS0.WDTSTPCTL = 1
OFS0.WDTSTRT = 1 (register start mode) and WDTCSTPR.SLCSTP = 1.
5. Canceling by other resets available in Sleep mode
Sleep mode is canceled by other resets and the MCU starts the reset exception handling.
Note:
10.7
10.7.1
For details of proper setting for interrupt, see section 12, Interrupt Controller Unit (ICU).
Software Standby Mode
Transition to Software Standby Mode
When a WFI instruction is executed while SBYCR.SSBY bit is 1, the MCU enters Software Standby mode. In this mode,
the CPU, most of the on-chip peripheral functions and oscillators stop. However, the contents of the CPU internal
registers and SRAM data, the states of on-chip peripheral functions and the I/O Ports are retained. Software Standby
mode allows a significant reduction in power consumption because most of the oscillators stops in this mode. Table 10.2
shows the status of each on-chip peripheral functions and oscillators. Available resets or interrupts in Software Standby
mode cause the MCU to cancel Software Standby mode. See Table 10.3 for available interrupt sources and section 12.2.8
Wake Up Interrupt Enable Register (WUPEN) for information on how to wake up the MCU from Software Standby
mode. If using an interrupt to cancel Software Standby mode, you must set the associated IELSRn register before
executing a WFI instruction. For details, see section 12, Interrupt Controller Unit (ICU).
Clear the DTCST.DTCST bit to 0 before executing WFI instruction except when using DTC in Snooze mode. If DTC is
required in Snooze mode, set the DTCST.DTCST bit to 1 before executing a WFI instruction.
Counting by IWDT stops when the MCU enters Software Standby mode while the IWDT is in auto-start mode and the
OFS0.IWDTSTPCTL bit is 1 (IWDT stops in Sleep mode, Software Standby mode and Snooze mode). Counting by
IWDT continues if the MCU enters Software Standby mode while the IWDT is in auto-start mode and the
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10. Low Power Modes
OFS0.IWDTSTPCTL bit is 0 (IWDT does not stop in Sleep mode, Software Standby mode and Snooze mode).
WDT stops counting when the MCU enters Software Standby mode.
Do not enter Software Standby mode while OSTDCR.OSTDE = 1 (oscillation stop detection function is enabled). To
enter Software Standby mode, execute a WFI instruction after disabling the oscillation stop detection function
(OSTDCR.OSTDE = 0). If executing a WFI instruction while OSTDCR.OSTDE = 1, the MCU enters Sleep mode even
when SBYCR.SSBY = 1. In addition, do not enter Software Standby mode while the flash memory performs a
programming or erasing procedure. To enter Software Standby mode, execute a WFI instruction after the programming
or erasing procedure completes.
10.7.2
Canceling Software Standby Mode
Software Standby mode is canceled by an available interrupt shown in Table 10.3, RES pin reset, a power-on reset, a
voltage monitor reset, or a reset caused by an IWDT underflow.
The oscillators that operate before the transition to Software Standby mode restart. After all the oscillators are stabilized,
the MCU returns to Normal mode from Software Standby mode. See section 12.2.8 Wake Up Interrupt Enable Register
(WUPEN) for information on how to wake up the MCU from Software Standby mode.
You can cancel Software Standby mode from any of the following ways:
1. Canceling by an interrupt
When an available interrupt request (for available interrupts, see Table 10.3) is generated, an oscillator that operates
before the transition to Software Standby mode restarts. After all the oscillators are stabilized, the MCU returns to
Normal mode from Software Standby mode and starts the interrupt handling.
2. Canceling by a RES pin reset
When RES pin is driven low, the MCU enters the reset state, and the oscillators whose default status is operating,
start the oscillation. Be sure to keep the RES pin low for the time period specified in section 41, Electrical
Characteristics. When the RES pin is driven high after the specified time period, the CPU starts the reset exception
handling.
3. Canceling by a power-on reset
Software Standby mode is canceled by a power-on reset and the MCU starts the reset exception handling.
4. Canceling by a voltage monitor reset
Software Standby mode is canceled by a voltage monitor reset from the voltage detection circuit and the MCU starts
the reset exception handling.
5. Canceling by IWDT reset
Software Standby mode is canceled by an internal reset generated by an IWDT underflow and the MCU starts the
reset exception handling. However, IWDT stops in Software Standby mode and an internal reset for canceling
Software Standby mode is not generated in the following condition:
OFS0.IWDTSTRT = 0 and OFS0.IWDTSTPCTL = 1.
10.7.3
Example of Software Standby Mode Application
Figure 10.7 shows an example of entry to Software Standby mode on detection of a falling edge of the IRQn pin, and exit
from Software Standby mode by a rising edge of the IRQn pin.
In this example, an IRQn pin interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge)
in Normal mode, and the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge). Follow that, the SBYCR.SSBY bit is set
to 1 and a WFI instruction is executed. As a result, entry to Software Standby mode completes and exit from Software
Standby mode is initiated by a rising edge of the IRQn pin.
Setting the ICU is also required to exit Software Standby mode. For details, see section 12, Interrupt Controller Unit
(ICU). The oscillation stabilization time in Figure 10.7 is specified in section 41, Electrical Characteristics.
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10. Low Power Modes
Oscillator
ICLK
IRQn pin
IRQMD[1:0]
01b
10b
SBYCR.SSBY
IRQ exception handling
IRQMD[1:0] = 10b
SBYCR.SSBY = 1
Oscillation
settling time
WFI instruction
Figure 10.7
10.8
IRQ exception handling
Software Standby Mode
Example of Software Standby mode application
Snooze Mode
10.8.1
Transition to Snooze Mode
Figure 10.8 shows snooze mode entry configuration. When the snooze control circuit receives a snooze request in
Software Standby mode, the MCU transfers to Snooze mode. In this mode, some peripheral modules operate without
waking up the CPU. The peripheral modules that can operate in Snooze mode are shown in Table 10.2, Operating
conditions of each low power mode. DTC operation in Snooze mode can also be selected by setting the
SNZCR.SNZDTCEN bit.
ICU
Snooze Control Circuit
WUPEN.bn
1
Wakeup request
Interrupt request
0
PAD (RXD0)
n = 0 to 7, 17, 23 to 25, 28 to 30
ELC
SNZCR.b7
SNZREQCR.bn
Control
SYSTEM_SNZREQ
(Snooze entry)
ELSRx
Event control
Snooze request
SNZCR.b0
Noise filter
+
Edge detect
SCI0
rxd
Figure 10.8
Snooze mode entry configuration
Table 10.6 shows the snooze requests to switch from Software Standby mode to Snooze mode. To use the listed snooze
requests as a trigger to switch to Snooze mode, the associated SNZREQENn bit of the SNZREQCR register or
RXDREQEN bit of the SNZCR register must be set before entering Software Standby mode. Do not enable multiple
snooze requests at the same time.
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Table 10.6
10. Low Power Modes
Available snooze requests to switch to Snooze mode
Control Register
Snooze request
Register
Bit
PORT_IRQn (n = 0 to 7)
SNZREQCR
SNZREQENn (n = 0 to 7)
KEY_INTKR
SNZREQCR
SNZREQEN17
ACMP_LP0
SNZREQCR
SNZREQEN23
RTC_ALM
SNZREQCR
SNZREQEN24
RTC_PRD
SNZREQCR
SNZREQEN25
AGT1_AGTI
SNZREQCR
SNZREQEN28
AGT1_AGTCMAI
SNZREQCR
SNZREQEN29
AGT1_AGTCMBI
SNZREQCR
SNZREQEN30
RXD0 falling edge
SNZCR
RXDREQEN*1
Note 1. RXDREQEN bit must not be set to 1 unless in asynchronous mode.
10.8.2
Canceling Snooze Mode
Snooze mode is canceled by an interrupt request that is available in Software Standby mode or any reset. Table 10.3
shows the requests that can be used to exit each mode. After canceling the Snooze mode, the MCU enters Normal mode
and proceeds with exception processing for the given interrupt or reset. The action triggered by the interrupt requests,
that is selected by SELSR0, cancels Snooze mode. Interrupt canceling Snooze mode must be selected by IELSRn (n = 0
to 31) to link to the NVIC for the corresponding interrupt handling. See section 12, Interrupt Controller Unit (ICU) for
the setting of SELSR0 and IELSRn.
WFI
instruction
Trigger
detection
Interrupt
request
High
Standby cancel
signal
Low
Snooze end
signal
Low power mode
Oscillator
for system clock
Low
Normal
mode*3
Software
Standby
mode
Oscillates
Oscillation
stopped
*1
Snooze mode
*2
Normal mode*4
Oscillates
Wait for oscillation accuracy stabilization
Note 1.
Note 2.
Note 3.
Note 4.
Figure 10.9
10.8.3
Transition time from Software Standby mode to Snooze mode.
Transition time from Snooze mode to Normal mode.
Enable Snooze mode (SNZCR.SNZE = 1) immediately before switching to Software Standby mode.
Be sure to disable Snooze mode (SNZCR.SNZE = 0) immediately after returning to Normal mode.
When interrupt request signal is generated in Snooze mode
Return to Software Standby Mode
Table 10.7 shows the snooze end request that can be used as triggers to return to Software Standby mode. The snooze end
requests are available only in Snooze mode. If the requests are generated when the MCU is not in Snooze mode, they are
ignored. When multiple requests are selected, each of the requests invokes the switching to Software Standby mode from
Snooze mode.
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10. Low Power Modes
Table 10.8 shows the snooze end conditions that consist of the snooze end requests and the conditions of the peripheral
modules. CTSU, SCI0, ADC140, and DTC can keep the MCU in Snooze mode until they complete the operation.
However, an AGT1 underflow as a trigger to return to Software Standby mode cancels Snooze mode without waiting for
the completion of SCI0 operation.
Figure 10.10 shows the timing chart for the transition from Snooze mode to Software Standby mode. This mode
transition occurs according to which snooze end requests are set in the SNZEDCR register. A snooze request is cleared
automatically after it is returned to Software Standby mode.
Table 10.7
Available snooze end requests (triggers to return to Software Standby mode)
Enable/Disable control
Snooze end request
Register
Bit
AGT1 underflow or measurement complete (AGT1_AGTI)
SNZEDCR
b0
DTC transfer completion (DTC_COMPLETE)
SNZEDCR
b1
Not DTC transfer completion (DTC_TRANSFER)
SNZEDCR
b2
ADC140 window A/B compare match (ADC140_WCMPM)
SNZEDCR
b3
ADC140 window A/B compare mismatch (ADC140_WCMPUM)
SNZEDCR
b4
SCI0 address mismatch (SCI0_DCUF)
SNZEDCR
b7
Table 10.8
Snooze end conditions
Operating module when a
snooze end request occurs
DTC
ADC140
Snooze end request
AGT1 underflow
Other than AGT1 underflow
The MCU transfers to the Software Standby mode
after all of the modules listed to the left complete
operation.
The MCU transfers to the Software Standby mode
after all of the modules listed to the left complete
operation.
CTSU
SCI0
The MCU transfers to the Software Standby mode
immediately after a snooze end request is
generated.
Other than above
The MCU transfers to the Software Standby mode immediately after a snooze end request is
generated.
Note:
If the DTC is used to activate the ADC140, CTSU, or SCI, the MCU transitions to software standby mode after a
snooze end request is generated.
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10. Low Power Modes
WFI
instruction
Trigger
detection
Standby release
signal
Low
Snooze end
signal
Low power mode
Oscillator
for system clock
Normal
mode*2
Software
Standby
mode
Oscillates
Oscillation
stopped
*1
Snooze mode
Oscillates
Software Standby mode
Oscillation stopped
Wait for oscillation accuracy stabilization
Note 1.
Note 2.
Figure 10.10
10.8.4
Transition time from Software Standby mode to Snooze mode.
Enable Snooze mode (SNZCR.SNZE = 1) immediately before switching to Software Standby mode.
When interrupt request signal is not generated in Snooze mode
Snooze Operation Example
Figure 10.11 shows an example setting for using ELC in Snooze mode.
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10. Low Power Modes
Start Snooze mode setting
Setting for ELC in Snooze mode
MSTPCRC.MSTPC14 = 0
Cancel module stop state of ELC
ELSRx.ELS = 10h
Snooze entry (SYSTEM_SNZREQ)
signal is linked to modules
ELCR.ELCON = 1
ELC function enabled
Setting for Snooze cancel
SELSR0.SELS = xxh
Select event number on Table 12.4 as
the source of canceling Snooze mode
IELSRy.DTCE = 0
IELSRy.IELS = 0Bh
Select canceling Snooze mode as the
interrupt request
Setting for Snooze end
SNZEDCR.bm = 1
Enable Snooze end request m
Setting for Snooze request
WUPEN.bn = 0
SNZREQCR.bn = 1
Disable Wakeup request n
Enable Snooze request n
SNZCR.b7 = 1
(SNZE = 1)
Enable Snooze mode
Complete Snooze mode
setting
WFI instruction
Enter Software Standby mode
Software Standby mode
Snooze request?
No
Yes
Snooze mode
SYSTEM_SNZREQ
by way of ELC
module operating
SELS event
SELS event or
Snooze end request?
Snooze end request
Snooze End
Interrupt for
canceling Snooze mode
Normal mode
Figure 10.11
Setting example of using ELC in Snooze mode
The MCU can transmit and receive data in SCI0 asynchronous mode without CPU intervention. When using the SCI0 in
Snooze mode, use one of the following operating modes:
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10. Low Power Modes
High-speed mode
Middle-speed mode
Low-speed mode.
Do not use low voltage mode or subosc-speed mode. Table 10.9 and Table 10.10 show the maximum transfer rate of
SCI0 in Snooze mode. When using the SCI0 in Snooze mode, the following settings must be used:
BGDM = 0
ABCS = 0
ABCSE = 0.
See section 25, Serial Communications Interface (SCI) for information on these bits.
High-speed mode, Middle-speed mode, Low-speed mode
Table 10.9
HOCO: ± 1.0% (Ta = -20 to 85°C)
Maximum division ratio of ICLK,
PCLKB, and PCLKD
(Unit: bps)
HOCO frequency
24 MHz
32 MHz
48 MHz
1
9600*1
9600*4
—
64 MHz
2
9600*2
9600*5
4800
2400
4
9600*3
9600*6
4800
2400
8
4800
4800
4800
2400
16
4800
4800
4800
2400
32
2400
2400
2400
2400
64
2400
2400
2400
2400
Note 1. SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 3Dh, SCI0.MDDR = CEh must be used for
9600 bps.
Note 2. SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 1Eh, SCI0.MDDR = CEh must be used for 9600
bps.
Note 3. SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 0Dh, SCI0.MDDR = BAh must be used for 9600
bps.
Note 4. SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 3Eh, SCI0.MDDR = 9Dh must be used for 9600
bps.
Note 5. SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 32h, SCI0.MDDR = FEh must be used for 9600
bps.
Note 6. SCI0.SMR.CKS[1:0] = 00b, SCI0.SEMR.BRME = 1, SCI0.BRR = 18h, SCI0.MDDR = F9h must be used for 9600
bps.
High-speed mode, Middle-speed mode, Low-speed mode
Table 10.10
HOCO: ± 1.5% (Ta = -40 to -20°C), HOCO: ± 2.0% (Ta = 85 to 105°C)
Maximum division ratio of ICLK,
PCLKB, and PCLKD
(Unit: bps)
HOCO frequency
24 MHz
32 MHz
48 MHz
64 MHz
1
2400
2400
-
-
2
2400
2400
2400
1200
4
2400
2400
2400
1200
8
2400
2400
2400
1200
16
2400
2400
2400
1200
32
1200
1200
1200
1200
64
1200
1200
1200
1200
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10. Low Power Modes
Figure 10.12 shows an example setting for using the SCI0 in Snooze mode entry.
Start Snooze mode setting
Setting for SCI0 in Snooze mode
MSTPCRB.MSTPB31 = 0
Cancel module stop state of SCI0
Set SCI0
Set as asynchronous UART receive mode
SCKSCR.CKSEL = 0h
The clock source must be HOCO
MOCOCR.MCSTP = 1
MOSCCR.MOSTP =1
Stop MOCO and the main clock oscillator
MSTPCRC.MSTPC0 = 1
Enter module stop state of CAC
Hold the communications line in the mark
state before entering Software Standby
mode
RXD0 = 1
Setting for Snooze cancel
Select SCI0_RXI_OR_ERI event as the
source of canceling Snooze mode
SELSR0.SELS = 72h
IELSRy.DTCE = 0
IELSRy.IELS = 0Bh
Select canceling Snooze mode as the
interrupt request
SNZEDCR.b7 = 1
(SCI0UMTED = 1)
Enable Snooze end request by SCI0
Address Mismatch
Setting for Snooze end
Setting for AGT1 to avoid Snooze mode by
a noise on the RXD0 pin
MSTPCRD.MSTPD2 = 0
Cancel module stop state of AGT1
Set as a timer to avoid Snooze mode by a
noise on the RXD0 pin
Set AGT1
SNZEDCR.b0 = 1
(AGTUNFED = 1)
Enable Snooze end request by AGT1
Underflow
SNZCR.b0 = 1
(RXDREQEN) = 1
Detect RXD0 falling edge in Software
Standby mode as a request to transition to
Snooze mode
Setting for Snooze request
SNZCR.b7 = 1
(SNZE = 1)
Enable Snooze mode
Complete Snooze mode setting
WFI instruction
Enter Software Standby mode
Software Standby mode
Snooze request?
No
Yes
Snooze mode
SCI0 receive data
is completed before
AGT1 underflow?
Yes
SELS event or
Snooze end request?
No
AGT1 underflow
SELS event
(Receive data full or Receive error)
Snooze end request
(Address Mismatch)
Snooze End
Interrupt for
canceling Snooze mode
Normal mode
Figure 10.12
Setting example of using SCI0 in Snooze mode entry
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10.9
Usage Note
10.9.1
(1)
10. Low Power Modes
Register Access
Do not write to registers listed in this section in any of the following conditions:
[Registers]
All registers with a peripheral name of “SYSTEM”.
[Conditions]
OPCCR.OPCMTSF = 1 or SOPCCR.SOPCMTSF = 1 (during transition of the operating power control mode)
Time period from executing a WFI instruction to returning to Normal mode
FENTRYR.FENTRY0 = 1 or FENTRYR.FENTRYD = 1 (flash P/E mode, data flash P/E mode)
FLSTOP.FLSTPF = 1 (during transition).
(2)
Valid setting of the clock related registers
Table 10.11 and Table 10.12 show the valid setting of the clock related registers in each operating power control mode.
Do not write any value other than the valid setting, otherwise it is ignored. Additionally, each register has some
prohibited settings under certain conditions other than the operating power control modes. See section 8, Clock
Generation Circuit for other conditions of each register.
Table 10.11
Valid setting of clock related registers (1)
Valid setting
SCKSCR
CKSEL[2:0]
CKOCR
CKOSEL[2:0]
Mode
SCKDIVCR
ICK[2:0]
HOCOCR
HCSTP
MOCOCR
MCSTP
LOCOCR
LCSTP
MOSCCR
MOSTP
SOSCCR
SOSTP
High-speed
Middle-speed
Low-voltage
Low-speed
000b (HOCO)
001b (MOCO)
010b (LOCO)
011b (MOSC)
100b (SOSC)
000b (1/1)
001b (1/2)
010b (1/4)
011b (1/8)
100b (1/16)
101b (1/32)
110b (1/64)
0 (operating)
1 (stop)
0 (operating)
1 (stop)
0 (operating)
1 (stop)
0 (operating)
1 (stop)
0 (operating)
1 stop
Subosc-speed
010b (LOCO)
100b (SOSC)
000b (1/1)
1 (stop)
1 (stop)
0 (operating)
1 (stop)
1 (stop)
0 (operating)
1 (stop)
Table 10.12
Valid setting of clock-related registers (2)
Valid setting
Operating oscillator
SOPCCR
SOPCM
OPCCR
OPCM[1:0]
High-speed on-chip oscillator
0
00b, 01b, 10b, 11b
0, 1
00b, 01b, 10b, 11b
Middle-speed on-chip oscillator
Main clock oscillator
Low-speed on-chip oscillator
Sub-clock oscillator
IWDT-dedicated on-chip oscillator
(3)
Do not write to registers listed in this section for the following condition:
[Registers]
SCKSCR, OPCCR.
[Condition]
SOPCCR.SOPCM = 1 (subosc-speed mode).
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(4)
10. Low Power Modes
Do not write to registers listed in this section by DTC:
[Registers]
MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD.
(5)
Do not write to registers listed in this section in Snooze mode. They must be set before
entering Software Standby mode:
[Registers]
SNZCR, SNZEDCR, SNZREQCR.
(6)
Do not set the FLSTOP.FLSTOP bit to 1 in any of the following conditions:
[Conditions]
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 00b (high-speed mode)
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 01b (middle-speed mode)
SOPCCR.SOPCM = 0, OPCCR.OPCM[1:0] = 11b (low-speed mode)
SOPCCR.SOPCM = 1 (subosc-speed mode).
(7)
Write access to registers listed in this section is invalid when PRCR.PRC1 bit is 0:
[Registers]
SBYCR, SNZCR, SNZEDCR, SNZREQCR, FLSTOP, OPCCR, SOPCCR.
10.9.2
I/O Port States
The I/O port states in Software Standby mode and Snooze mode, unless modifying in Snooze mode, are the same before
entering the modes. Therefore, the supply current is not reduced while the output signals are held high.
10.9.3
Module-Stop State of DTC
Before writing 1 to MSTPCRA.MSTPA22, clear the DTCST.DTCST bit of the DTC to 0. For details, see section 14,
Data Transfer Controller (DTC).
10.9.4
Internal Interrupt Sources
Interrupts do not operate in the module-stop state. If setting the module-stop bit while an interrupt request is generated, a
CPU interrupt source or a DTC startup source cannot be cleared. For this reason, make sure you disable the
corresponding interrupts before setting the module-stop bits.
10.9.5
Transition to Low Power Modes
Because the MCU does not support wakeup by event, do not enter low power modes (Sleep mode or Software Standby
mode) by executing a WFE instruction. Also, do not set the SLEEPDEEP bit of the System Control Register in the
Cortex®-M0+ core because the MCU does not support low power modes by SLEEPDEEP.
10.9.6
Timing of WFI Instruction
It is possible for the WFI instruction to be executed before I/O register writes are complete, in which case operation
might not be as intended. This can happen if the WFI is placed immediately after a write to an I/O register. To avoid this
problem, it is recommended that you read back the register that was written to confirm that the write has completed.
10.9.7
Writing WDT/IWDT Registers by DTC in Sleep Mode or Snooze Mode
Do not write registers in WDT or IWDT by DTC while WDT or IWDT stops by entering Sleep mode or Snooze mode.
10.9.8
Oscillators in Snooze Mode
Oscillators that stop by entering Software Standby mode automatically restart when a trigger to switch to Snooze mode is
generated. The MCU does not enter Snooze mode until all the oscillators stabilize. If in Snooze mode, make sure to
disable oscillators that are not required in Snooze mode before entering Software Standby mode, otherwise it takes
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10. Low Power Modes
longer to transition from Software Standby mode to Snooze mode.
10.9.9
Snooze Mode Entry by RXD0 Falling Edge
When the SNZCR.RXDREQEN bit is 1, noise on the RXD0 pin might cause the MCU transition from Software Standby
mode to Snooze mode. Any subsequent RXD0 data can be received in Snooze mode by a noise on the RXD0 pin. If the
MCU does not receive RXD0 data after the noise, an interrupt such as SCI0_ERI or SCI0_RXI, and an address mismatch
event is not generated and the MCU stays in Snooze mode. To avoid this, an AGT1 underflow interrupt must be used to
return to Software Standby mode or Normal mode when using SCI0 in Snooze mode. However, do not use the AGT1
underflow as a source to return to Software Standby mode during an SCI communication. This causes the SCI0 to stop
the operation in a half-finished state.
10.9.10
Using SCI0 in Snooze Mode
When using SCI0 in Snooze mode, a wakeup request other than an AGT1 underflow must not be used.
When using SCI0 in Snooze mode, the following conditions must be satisfied:
The clock source must be HOCO
MOCO and the main clock oscillator must stop before entering Software Standby mode
The RXD0 pin must be kept high before entering Software Standby mode
A transition to Software Standby mode must not occur during an SCI communication
The MSTPCRC.MSTPC0 bit must be 1 before entering Software Standby mode.
10.9.11
Conditions of A/D Conversion Start in Snooze Mode
A/D converter can be triggered by only ELC in Snooze mode. Software trigger or ADTRG0 pin must not be used.
10.9.12
Conditions of CTSU in Snooze Mode
The CTSU can only be started by the ELC in Snooze mode.
10.9.13
ELC Event in Snooze Mode
Available events in Snooze mode are listed in this section. Do not use any event other than those listed. If starting
peripheral modules for the first time after entering Snooze mode, Event Link Setting Register (ELSRn) must set a
Snooze mode entry event (SYSTEM_SNZREQ) as the trigger.
Snooze mode entry (SYSTEM_SNZREQ)
DTC transfer end (DTC_DTCEND)
ADC140 window A/B compare match (ADC140_WCMPM)
ADC140 window A/B compare mismatch (ADC140_WCMPUM)
Data operation circuit interrupt (DOC_DOPCI).
10.9.14
Module-Stop Function for ADC140
When entering the Software Standby mode, it is recommended that you set the ADC140 module-stop state to reduce
power consumption. In this case, the ADC140 can be available in Snooze mode by releasing the ADC140 module-stop
using the DTC. Similarly, set the module-stop state using the DTC before returning to Software Standby mode from
Snooze mode.
10.9.15
Module-Stop Function for an Unused Circuit
A circuit that is not used in User mode might not be reset and might operate in an unstable state because the clocks are
not supplied during an MCU reset. Therefore, the supply current can be increased to a value greater than that stated in
this User’s Manual by up to 600 A when the MCU transitions to Low-speed mode or Software Standby mode.
Perform the following procedure as shown in Figure 10.13 during the initial setting of the MCU to initialize the unused
circuit.
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10. Low Power Modes
Turn the power on
Release the protection of the Protect Register
PRCR.PRC1 = 1
Release from the module-stop state
MSTPCRC.MSTPC28 = 0
Wait for 3 PCLKB cycles
for example: dummy = PORT1.PODR.BYTE;
while (dummy != PORT1.PODR.BYTE) { }
Transition to the module-stop state
MSTPCRC.MSTPC28 = 1
Set the Protect Register
PRCR.PRC1 = 0
End
Figure 10.13
Example of initial setting flow for an unused circuit
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11. Register Write Protection
11.
Register Write Protection
11.1
Overview
The Register Write Protection function protects important registers from being overwritten due to software errors. The
registers to be protected are set with the Protect Register (PRCR).
Table 11.1 lists the association between the PRCR bits and the registers to be protected.
Table 11.1
Association between PRCR bits and registers to be protected
PRCR bit
Register to be protected
PRC0
Registers related to the Clock Generation Circuit:
SCKDIVCR, SCKSCR, MOSCCR, HOCOCR, MOCOCR, CKOCR, OSTDCR, OSTDSR, MOCOUTCR,
HOCOUTCR, MOSCWTCR, MOMCR, SOSCCR, SOMCR, LOCOCR, LOCOUTCR, HOCOWTCR
PRC1
Registers related to the low power modes:
SBYCR, SNZCR, SNZEDCR, SNZREQCR, FLSTOP, OPCCR, SOPCCR, SYOCDCR
PRC3
Registers related to the LVD:
LVD1CR1, LVD1SR, LVD2CR1, LVD2SR, LVCMPCR, LVDLVLR, LVD1CR0, LVD2CR0
11.2
Register Descriptions
11.2.1
Protect Register (PRCR)
Address(es): SYSTEM.PRCR 4001 E3FEh
b15
b14
b13
b12
b11
b10
b9
b8
PRKEY[7:0]
Value after reset:
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
PRC3
—
PRC1
PRC0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Function
R/W
b0
PRC0
Protect Bit 0
Enables writing to the registers related to the clock generation circuit:
0: Write disabled
1: Write enabled.
R/W
b1
PRC1
Protect Bit 1
Enables writing to the registers related to the low power modes:
0: Write disabled
1: Write enabled.
R/W
b2
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b3
PRC3
Protect Bit 3
Enables writing to the registers related to the LVD:
0: Write disabled
1: Write enabled.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
PRKEY[7:0]
PRC Key Code
These bits control the write access to the PRCR register. To modify the
PRCR register, write A5h to the 8 higher-order bits and the desired value
to the 8 lower-order bits as a 16-bit unit.
W*1
Note 1. Write data is not retained. Always reads 00h.
PRCi bits (Protect Bit i) (i = 0, 1, 3)
The PRCi bits enable or disable writing to the protected registers as described in Table 11.1. Setting the PRCi bits to 1 or
0 enables or disables writing, respectively.
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12. Interrupt Controller Unit (ICU)
12.
Interrupt Controller Unit (ICU)
12.1
Overview
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller/
Data Transfer Control (NVIC/DTC) module. The ICU also controls non-maskable interrupts.
Table 12.1 lists the ICU specifications and Figure 12.1 shows the block diagram.
Table 12.1
ICU specifications
Parameter
Interrupts
Nonmaskable
interrupts*2
Description
Peripheral function
interrupts
Interrupts from peripheral modules
Number of sources: 128 (select factor within event list numbers 9 to 137)
External pin interrupts
Interrupt detection on low level*4, falling edge, rising edge, rising and falling edges. One of
these detection methods can be set for each source.
Digital filter function supported
8 sources, with interrupts from IRQ0 to IRQ7 pins.
DTC control
The DTC can be activated by interrupt sources*1
Interrupt sources for
NVIC
32 sources
NMI pin interrupt
Interrupt from the NMI pin
Interrupt detection on falling edge or rising edge
Digital filter function supported.
Oscillation stop
detection interrupt*3
Interrupt on detecting that the main oscillation has stopped
WDT underflow/refresh
error*3
Interrupt on an underflow of the down-counter or occurrence of a refresh error
IWDT underflow/refresh
error*3
Interrupt on an underflow of the down-counter or occurrence of a refresh error
Voltage monitor 1
interrupt*3
Voltage monitor interrupt of low voltage detection 1 (LVD_LVD1)
Voltage monitor 2
interrupt*3
Voltage monitor interrupt of low voltage detection 2 (LVD_LVD2)
RPEST
Interrupt on SRAM parity error
Return from low power mode
Sleep mode: return is initiated by non-maskable interrupts or any other interrupt source.
Software Standby mode: return is initiated by non-maskable interrupts. Interrupt can be
selected by the WUPEN Register.
Snooze mode: return is initiated by non-maskable interrupts. Interrupt can be selected with
the SELSR0 and WUPEN registers.
See section 12.2.7, SYS Event Link Setting Register (SELSR0) and section 12.2.8, Wake Up
Interrupt Enable Register (WUPEN).
Note 1. For the DTC activation sources, see Table 12.4, Event table.
Note 2. Non-maskable interrupts can be enabled only once after a reset release.
Note 3. These non-maskable interrupts can also be used as event signals.
When used as interrupts, do not change the value of the NMIER register from the reset state.
To enable voltage monitor 1 and voltage monitor 2 interrupts, set the LVD1CR1.IRQSEL and LVD2CR1.IRQSEL
bits to 1.
Note 4. Low level is not canceled if you do not clear it when it is detected once.
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12. Interrupt Controller Unit (ICU)
Interrupt Controller
SRAM Parity error
IWDT underflow/refresh error
WDT underflow/refresh error
Oscillation stop detection interrupt
NMI
SR
Voltage monitor 2 interrupt
Voltage monitor 1 interrupt
Low Voltage Detection
Digital
filter
NMI pin
Clock
Generation
Circuit
Clock restoration request
Clock restoration
determination
Detection
NFCL NFLT
KSEL EN
NMI
MD
NMI
CLR
NMI
ER
CPU
Clock restoration enable level
WUPEN
Non-maskable interrupt request
Module data bus
IRQ7
IRQ
MD
Digital
filter
Detection
DTCE
Wakeup signal
Canceling snooze mode
(Generated from the output of SELSR0)
NVIC
IRQ0
FCLK FLT
SEL EN
SELSR0
Peripheral
Module
Interrupt request
IELSRn
Control
Destination switchover
to CPU
DTC activation
request
Interrupt
source
DTC
NMISR:
NMIER:
NMICLR:
NMIMD:
NFCLKSEL:
NFLTEN:
IRQMD:
Figure 12.1
IR
DTC
activation
control
DTC
DTC response
Switching the interrupt status and the transfer destination
Non-Maskable Interrupt Status Register
Non-Maskable Interrupt Enable Register
Non-Maskable Interrupt Status Clear Register
NMI Detection Set (NMICR.NMIMD)
NMI Digital Filter Sampling Clock Select
(NMICR.NFCLKSEL)
NMI Digital Filter Enable (NMICR.NFLTEN)
IRQi Detection Sense Select
(IRQCRi.IRQMD (i = 0 to 7))
FCLKSEL:
FLTEN:
SELSR0:
WUPEN:
IELSRn:
IR:
DTCE:
IRQi Digital Filter Sampling Clock Select
(IRQCRi.FCLKSEL (i = 0 to 7))
IRQi Digital Filter Enable (IRQCRi.FLTEN (i = 0 to 7))
SYS Event Link Setting Register 0
Wake Up Interrupt Enable Register
ICU Event Link Setting Register (n = 0 to 31)
Interrupt Status Flag (IELSRn.IR)
DTC Activation Enable (IELSRn.DTCE)
Interrupt Controller Unit block diagram
Table 12.2 lists the input/output pins of the ICU.
Table 12.2
Interrupt Controller Unit configuration pins
Pin name
I/O
Description
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ7
Input
External interrupt request pins
12.2
Register Descriptions
This chapter does not describe the Arm® NVIC internal registers. For information on these registers, see the ARM®
Cortex®-M0+ Processor Technical Reference Manual (ARM DDI 0484C).
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12. Interrupt Controller Unit (ICU)
IRQ Control Register i (IRQCRi) (i = 0 to 7)
Address(es): ICU.IRQCR0 4000 6000h, ICU.IRQCR1 4000 6001h, ICU.IRQCR2 4000 6002h, ICU.IRQCR3 4000 6003h,
ICU.IRQCR4 4000 6004h, ICU.IRQCR5 4000 6005h, ICU.IRQCR6 4000 6006h, ICU.IRQCR7 4000 6007h
b7
b6
FLTEN
—
0
0
Value after reset:
b5
b4
FCLKSEL[1:0]
0
0
b3
b2
b1
—
—
IRQMD[1:0]
0
0
0
b0
0
Bit
Symbol
Bit name
b1, b0
IRQMD[1:0]
IRQi Detection Sense Select
Description
b3, b2
—
Reserved
b5, b4
FCLKSEL[1:0]
IRQi Digital Filter Sampling Clock
Select
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
FLTEN
IRQi Digital Filter Enable
0: Digital filter is disabled
1: Digital filter is enabled.
R/W
b1 b0
0
0
1
1
0:
1:
0:
1:
R/W
R/W
Falling edge
Rising edge
Rising and falling edges
Low level.
These bits are read as 0. The write value should be 0.
b5 b4
0
0
1
1
0:
1:
0:
1:
R/W
R/W
PCLKB
PCLKB/8
PCLKB/32
PCLKB/64.
IRQCRi register changes must satisfy the following:
1. For a CPU interrupt or DTC trigger:
Change the IRQCRi register setting before setting the target IELSRn (n = 0 to 31).
You can only change the register values when the IELSRn.IELS[7:0] bits are 00h.
2. For a wakeup enable signal:
Change the IRQCRi register setting before setting the target WUPEN.IRQWUPENi (i = 0 to 7).
You can only change the register values when the target WUPEN.IRQWUPENi is 0.
IRQMD[1:0] bits (IRQi Detection Sense Select)
The IRQMD[1:0] bits set the detection sensing method for the external pin interrupt sources IRQi. For more information
on the settings, see section 12.4.4, External Pin Interrupts.
FCLKSEL[1:0] bits (IRQi Digital Filter Sampling Clock Select)
The FCLKSEL[1:0] bits select the digital filter sampling clock for the external pin interrupt request pins IRQi, selectable
to:
PCLKB (every cycle)
PCLKB/8 (once every eight cycles)
PCLKB/32 (once every 32 cycles)
PCLKB/64 (once every 64 cycles.
For details of the digital filter, see section 12.4.3, Digital Filter.
FLTEN bit (IRQi Digital Filter Enable)
The FLTEN bits enable the digital filter used for the external pin interrupt sources IRQi. The digital filter is enabled
when the IRQCRi.FLTEN bit is 1, and disabled when the IRQCRi.FLTEN bit is 0. The IRQi pin level is sampled at the
clock cycle specified with the IRQCRi.FCLKSEL[1:0] bits. When the sampled level matches three times, the output
level from the digital filter changes. For details of the digital filter, see section 12.4.3, Digital Filter.
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12. Interrupt Controller Unit (ICU)
Non-Maskable Interrupt Status Register (NMISR)
Address(es): ICU.NMISR 4000 6140h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
RPEST NMIST OSTST
0
0
0
b5
b4
—
—
0
0
b3
b2
b1
b0
LVD2S LVD1S WDTST IWDTS
T
T
T
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IWDTST
IWDT Underflow/Refresh Error Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b1
WDTST
WDT Underflow/Refresh Error Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b2
LVD1ST
Voltage Monitor 1 Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b3
LVD2ST
Voltage Monitor 2 Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b5, b4
—
Reserved
These bits are read as 0.
R
b6
OSTST
Oscillation Stop Detection Interrupt Status
Flag
0: Interrupt not requested for main oscillation stop
1: Interrupt requested for main oscillation stop.
R
b7
NMIST
NMI Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b8
RPEST
SRAM Parity Error Interrupt Status Flag
0: Interrupt not requested
1: Interrupt requested.
R
b15 to b9
—
Reserved
These bits are read as 0.
R
The NMISR register monitors the status of non-maskable interrupt sources. Writes to the NMISR register are ignored.
The setting in the Non-Maskable Interrupt Enable Register (NMIER) does not affect the status flags in this register.
Before the end of the non-maskable interrupt handler, check that all of the bits in this register are set to 0 to confirm that
no other NMI requests are generated during handler processing.
IWDTST flag (IWDT Underflow/Refresh Error Status Flag)
The IWDTST flag indicates the IWDT underflow/refresh error interrupt request. It is read-only and is cleared by the
NMICLR.IWDTCLR bit.
[Setting condition]
When the IWDT underflow/refresh error interrupt is generated and this interrupt source is enabled.
[Clearing condition]
When 1 is written to the NMICLR.IWDTCLR bit.
WDTST flag (WDT Underflow/Refresh Error Status Flag)
The WDTST flag indicates the WDT underflow/refresh error interrupt request. It is read-only and is cleared by the
NMICLR.WDTCLR bit.
[Setting condition]
When the WDT underflow/refresh error interrupt is generated.
[Clearing condition]
When 1 is written to the NMICLR.WDTCLR bit.
LVD1ST flag (Voltage Monitor 1 Interrupt Status Flag)
The LVD1ST flag indicates the request for voltage monitor 1 interrupt. It is read-only and is cleared by the
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12. Interrupt Controller Unit (ICU)
NMICLR.LVD1CLR bit.
[Setting condition]
When the voltage monitor 1 interrupt is generated while this interrupt is enabled at its source.
[Clearing condition]
When 1 is written to the NMICLR.LVD1CLR bit.
LVD2ST flag (Voltage Monitor 2 Interrupt Status Flag)
The LVD2ST flag indicates the request for voltage monitor 2 interrupt. It is read-only and is cleared by the
NMICLR.LVD2CLR bit.
[Setting condition]
When the voltage monitor 2 interrupt is generated and this interrupt source is enabled.
[Clearing condition]
When 1 is written to the NMICLR.LVD2CLR bit.
OSTST flag (Oscillation Stop Detection Interrupt Status Flag)
The OSTST flag indicates the oscillation stop detection interrupt request. It is read-only and is cleared by the
NMICLR.OSTCLR bit.
[Setting condition]
When the main oscillation stop detection interrupt is generated.
[Clearing condition]
When 1 is written to the NMICLR.OSTCLR bit.
NMIST flag (NMI Status Flag)
The NMIST flag indicates the NMI pin interrupt request. It is read-only and is cleared by the NMICLR.NMICLR bit.
[Setting condition]
When an edge specified by the NMICR.NMIMD bit is input to the NMI pin.
[Clearing condition]
When 1 is written to the NMICLR.NMICLR bit.
RPEST flag (SRAM Parity Error Interrupt Status Flag)
The RPEST flag indicates the SRAM parity error interrupt request.
[Setting condition]
When an interrupt is generated in response to an SRAM parity error.
[Clearing condition]
When 1 is written to the NMICLR.RPECLR bit.
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12.2.3
12. Interrupt Controller Unit (ICU)
Non-Maskable Interrupt Enable Register (NMIER)
Address(es): ICU.NMIER 4000 6120h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
RPEEN NMIEN OSTEN
0
0
0
b5
b4
—
—
0
0
b3
b2
b1
b0
LVD2E LVD1E WDTE IWDTE
N
N
N
N
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IWDTEN
IWDT Underflow/Refresh Error Interrupt
Enable
0: Disabled
1: Enabled.
*1, *2
WDT Underflow/Refresh Error Interrupt
Enable
0: Disabled
1: Enabled.
*1, *2
Voltage Monitor 1 Interrupt Enable
0: Disabled
1: Enabled.
*1, *2
0: Disabled
1: Enabled.
*1, *2
b1
b2
b3
WDTEN
LVD1EN
LVD2EN
Voltage Monitor 2 Interrupt Enable
R/(W)
R/(W)
R/(W)
R/(W)
b5, b4
―
Reserved
These bits are read as 0. The write value should be 0. R/W
b6
OSTEN
Oscillation Stop Detection Interrupt
Enable
0: Disabled
1: Enabled.
*1, *2
NMI Pin Interrupt Enable
0: Disabled
1: Enabled.
*1
0: Disabled
1: Enabled.
*1, *2
b7
b8
b15 to b9
NMIEN
RPEEN
―
SRAM Parity Error Interrupt Enable
Reserved
R/(W)
R/(W)
R/(W)
These bits are read as 0. The write value should be 0. R/W
Note 1. You can write 1 to this bit only once after reset. Subsequent write accesses are invalid. Writing 0 to this bit is
invalid.
Note 2. Do not write 1 to this bit when the source is used as an event signal.
IWDTEN bit (IWDT Underflow/Refresh Error Interrupt Enable)
The IWDTEN bit enables the IWDT underflow/refresh error interrupt as an NMI trigger.
WDTEN bit (WDT Underflow/Refresh Error Interrupt Enable)
The WDTEN bit enables the WDT underflow/refresh error interrupt as an NMI trigger.
LVD1EN bit (Voltage Monitor 1 Interrupt Enable)
The LVD1EN bit enables the voltage monitor 1 interrupt as an NMI trigger.
LVD2EN bit (Voltage Monitor 2 Interrupt Enable)
The LVD2EN bit enables the voltage monitor 2 interrupt as an NMI trigger.
OSTEN bit (Oscillation Stop Detection Interrupt Enable)
The OSTEN bit enables the main oscillation stop detection interrupt as an NMI trigger.
NMIEN bit (NMI Pin Interrupt Enable)
The NMIEN bit enables the NMI pin interrupt as an NMI trigger.
RPEEN bit (SRAM Parity Error Interrupt Enable)
The RPEEN bit enables the SRAM parity error interrupt as an NMI trigger.
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12.2.4
12. Interrupt Controller Unit (ICU)
Non-Maskable Interrupt Status Clear Register (NMICLR)
Address(es): ICU.NMICLR 4000 6130h
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
Value after reset:
b8
b7
b6
RPECL NMICL OSTCL
R
R
R
0
0
0
b5
b4
—
—
0
0
b3
b2
b1
b0
LVD2C LVD1C WDTCL IWDTC
LR
LR
R
LR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IWDTCLR
IWDT Clear
0: No effect
1: Clear the NMISR.IWDTST flag.
R/(W)*1
b1
WDTCLR
WDT Clear
0: No effect
1: Clear the NMISR.WDTST flag.
R/(W)*1
b2
LVD1CLR
LVD1 Clear
0: No effect
1: Clear the NMISR.LVD1ST flag.
R/(W)*1
b3
LVD2CLR
LVD2 Clear
0: No effect
1: Clear the NMISR.LVD2ST flag.
R/(W)*1
b5, b4
—
Reserved
The write value should be 0.
R/(W)*1
b6
OSTCLR
OST Clear
0: No effect
1: Clear the NMISR.OSTST flag.
R/(W)*1
b7
NMICLR
NMI Clear
0: No effect
1: Clear the NMISR.NMIST flag.
R/(W)*1
b8
RPECLR
SRAM Parity Error Clear
0: No effect
1: Clear the NMISR.RPEST flag.
R/(W)*1
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/(W)*1
Note 1. Only write 1 to this bit.
IWDTCLR bit (IWDT Clear)
Writing 1 clears the NMISR.IWDTST flag. This bit is read as 0.
WDTCLR bit (WDT Clear)
Writing 1 clears the NMISR.WDTST flag. This bit is read as 0.
LVD1CLR bit (LVD1 Clear)
Writing 1 clears the NMISR.LVD1ST flag. This bit is read as 0.
LVD2CLR bit (LVD2 Clear)
Writing 1 clears the NMISR.LVD2ST flag. This bit is read as 0.
OSTCLR bit (OST Clear)
Writing 1 clears the NMISR.OSTST flag. This bit is read as 0.
NMICLR bit (NMI Clear)
Writing 1 clears the NMISR.NMIST flag. This bit is read as 0.
RPECLR bit (SRAM Parity Error Clear)
Writing 1 clears the NMISR.RPEST flag. This bit is read as 0.
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12. Interrupt Controller Unit (ICU)
NMI Pin Interrupt Control Register (NMICR)
Address(es): ICU.NMICR 4000 6100h
b7
b6
NFLTE
N
—
0
0
Value after reset:
b5
b4
NFCLKSEL[1:0]
0
0
b3
b2
b1
b0
—
—
—
NMIMD
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
NMIMD
NMI Detection Set
0: Falling edge
1: Rising edge.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b5, b4
NFCLKSEL[1:0]
NMI Digital Filter Sampling Clock
Select
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
NFLTEN
NMI Digital Filter Enable
0: Disabled
1: Enabled.
R/W
b5 b4
0
0
1
1
0:
1:
0:
1:
R/W
PCLKB
PCLKB/8
PCLKB/32
PCLKB/64.
Change the NMICR register settings before enabling NMI pin interrupts, that is, before setting NMIER.NMIEN to 1.
NMIMD bit (NMI Detection Set)
The NMIMD bit selects the detection sensing method for NMI pin interrupts.
NFCLKSEL[1:0] bits (NMI Digital Filter Sampling Clock Select)
The NFCLKSEL[1:0] bits select the digital filter sampling clock for NMI pin interrupts, selectable to:
PCLKB (every cycle)
PCLKB/8 (once every eight cycles)
PCLKB/32 (once every 32 cycles)
PCLKB/64 (once every 64 cycles).
For details of the digital filter, see section 12.4.3, Digital Filter.
NFLTEN bit (NMI Digital Filter Enable)
The NFLTEN bit enables the digital filter used for the NMI pin interrupt. The filter is enabled when NFLTEN is 1, and
disabled when NFLTEN is 0. The NMI pin level is sampled at the clock cycle specified in NMIFLTC.NFCLKSEL[1:0].
When the sampled level matches three times, the output level from the digital filter changes. For details of the digital
filter, see section 12.4.3, Digital Filter.
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12.2.6
12. Interrupt Controller Unit (ICU)
ICU Event Link Setting Register n (IELSRn)
Address(es): ICU.IELSR0 4000 6300h, ICU.IELSR1 4000 6304h, ICU.IELSR2 4000 6308h, ICU.IELSR3 4000 630Ch……
……ICU.IELSR28 4000 6370h, ICU.IELSR29 4000 6374h, ICU.IELSR30 4000 6378h, ICU.IELSR31 4000 637Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
DTCE
—
—
—
—
—
—
—
IR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
IELS[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
IELS[7:0]
ICU Event Link Select
b7
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
IR
Interrupt Status Flag
0: No interrupt request generated
1: An interrupt request generated.
*1
b0
00000000: Disable interrupts to the associated NVIC or DTC
module.
00000001 to 10001001: Event signal number to be linked.
Other settings are prohibited. For details, see Table 12.4.
R/(W)
b23 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b24
DTCE
DTC Activation Enable
0: Disabled
1: Enabled.
R/W
b31 to b25
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note:
This register requires halfword or word access.
Note 1. Writing 1 to the IR flag is prohibited.
The IELSRn register selects the IRQ source used by NVIC. For details, see Table 12.4. IELSRn, where n = 0 to 31,
corresponds to the NVIC-IRQ input source numbers 0 to 31.
IELS[7:0] bits (ICU Event Link Select)
The IELS[7:0] bits link an event signal to the associated NVIC or DTC module.
IR flag (Interrupt Status Flag)
The IR status flag indicates an individual interrupt request from the event specified in IELS[7:0].
[Setting condition]
When an interrupt request is received from the associated peripheral module or IRQi pin.
[Clearing conditions]
When 0 is written to the IR flag. DTCE must be set to 0 before writing 0 to the IR flag.
To clear the IR flag:
1. Negate the input interrupt signal.
2. Read access the peripheral once and wait for 2 clock cycles of the target module clock PCLKB or PCLKD.
3. Clear the IR flag by writing 0.
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12. Interrupt Controller Unit (ICU)
DTCE bit (DTC Activation Enable)
When the DTCE bit is set to 1, the associated event is selected as the source for DTC activation.
[Setting condition]
When 1 is written to the DTCE bit.
[Clearing conditions]
When the specified number of transfers is complete. For chain transfer, when the specified number of transfers for
the last chain transfer is complete
When 0 is written to the DTCE bit.
12.2.7
SYS Event Link Setting Register (SELSR0)
Address(es): ICU.SELSR0 4000 6200h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
SELS[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
SELS[7:0]
SYS Event Link Select
b7
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
b0
00000000: Disable event output to the associated low-power
mode module
00000001 to 10001001: Event signal number to be linked.
Other settings are prohibited. For details, see Table 12.4.
R/W
Note 1. This register requires halfword access.
The SELSR0 register selects the events that wake up the CPU from Snooze mode. You can only use the events listed in
Table 12.4 checked under “Canceling Snooze mode using SELSR0”. Events specified in this register are defined as
ICU_SNZCANCEL (0Bh) in Table 12.4. When 0Bh is set in IELSRn.IELS, an SELSR0 event interrupt occurs.
12.2.8
Wake Up Interrupt Enable Register (WUPEN)
Address(es): ICU.WUPEN 4000 61A0h
b31
b30
b29
b28
b27
IIC0WU AGT1C AGT1C AGT1U USBFS
PEN BWUPE AWUPE DWUPE WUPEN
Value after reset:
Value after reset:
b26
—
b25
b24
b23
RTCPR RTCAL ACMPL
DWUPE MWUPE P0WUP
N
N
EN
N
N
N
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b22
b21
b20
b19
b18
b17
b16
LVD2W LVD1W KEYWU IWDTW
UPEN UPEN
PEN
UPEN
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
IRQWUPEN[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
IRQWUPEN[7:0]
IRQ Interrupt Software
Standby Returns Enable
0: Software standby returns by IRQ interrupt disabled
1: Software standby returns by IRQ interrupt enabled.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
IWDTWUPEN
IWDT Interrupt Software
Standby Returns Enable
0: Software Standby returns by IWDT interrupt disabled
1: Software Standby returns by IWDT interrupt enabled.
R/W
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12. Interrupt Controller Unit (ICU)
Bit
Symbol
Bit name
Description
R/W
b17
KEYWUPEN
Key Interrupt Software
Standby Returns Enable
0: Software Standby returns by KEY interrupt disabled
1: Software Standby returns by KEY interrupt enabled.
R/W
b18
LVD1WUPEN
LVD1 Interrupt Software
Standby Returns Enable
0: Software Standby returns by LVD1 interrupt disabled
1: Software Standby returns by LVD1 interrupt enabled.
R/W
b19
LVD2WUPEN
LVD2 Interrupt Software
Standby Returns Enable
0: Software Standby returns by LVD2 interrupt disabled
1: Software Standby returns by LVD2 interrupt enabled.
R/W
b22 to b20
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b23
ACMPLP0WUPEN
ACMPLP0 Interrupt
Software Standby Returns
Enable
0: Software Standby returns by ACMPLP0 interrupt
disabled
1: Software Standby returns by ACMPLP0 interrupt
enabled.
R/W
b24
RTCALMWUPEN
RTC Alarm Interrupt
Software Standby Returns
Enable
0: Software Standby returns by RTC alarm interrupt
disabled
1: Software Standby returns by RTC alarm interrupt
enabled.
R/W
b25
RTCPRDWUPEN
RTC Period Interrupt
Software Standby Returns
Enable
0: Software Standby returns by RTC period interrupt
disabled
1: Software Standby returns by RTC period interrupt
enabled.
R/W
b26
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b27
USBFSWUPEN
USBFS Interrupt Software
Standby Returns Enable
0: Software Standby returns by USBFS interrupt
disabled
1: Software standby returns by USBFS interrupt
enabled.
R/W
b28
AGT1UDWUPEN
AGT1 Underflow Interrupt
Software Standby Returns
Enable
0: Software Standby returns by AGT1 underflow
interrupt disabled
1: Software Standby returns by AGT1 underflow
interrupt enabled.
R/W
b29
AGT1CAWUPEN
AGT1 Compare Match A
Interrupt Software Standby
Returns Enable
0: Software Standby returns by AGT1 compare match A
interrupt disabled
1: Software Standby returns by AGT1 compare match A
interrupt enabled.
R/W
b30
AGT1CBWUPEN
AGT1 Compare Match B
Interrupt Software Standby
Returns Enable
0: Software Standby returns by AGT1 compare match B
interrupt disabled
1: Software Standby returns by AGT1 compare match B
interrupt enabled.
R/W
b31
IIC0WUPEN
IIC0 Address Match
Interrupt Software Standby
Returns Enable
0: Software Standby returns by IIC0 address match
interrupt disabled
1: Software Standby returns by IIC0 address match
interrupt enabled.
R/W
The bits in this register control whether the associated interrupt can wake up the CPU from Software Standby mode.
IRQWUPEN[7:0] bits (IRQ Interrupt Software Standby Returns Enable)
The IRQWUPEN[7:0] bits enable the use of IRQn interrupts to cancel Software Standby mode.
IWDTWUPEN bit (IWDT Interrupt Software Standby Returns Enable)
The IWDTWUPEN bit enables the use of IWDT interrupts to cancel Software Standby mode.
KEYWUPEN bit (Key Interrupt Software Standby Returns Enable)
The KEYWUPEN bit enables the use of Key interrupts to cancel Software Standby mode.
LVD1WUPEN bit (LVD1 Interrupt Software Standby Returns Enable)
The LVD1WUPEN bit enables the use of LVD1 interrupts to cancel Software Standby mode.
LVD2WUPEN bit (LVD2 Interrupt Software Standby Returns Enable)
The LVD2WUPEN bit enables the use of LVD2 interrupts to cancel Software Standby mode.
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12. Interrupt Controller Unit (ICU)
ACMPLP0WUPEN bit (ACMPLP0 Interrupt Software Standby Returns Enable)
The ACMPLP0WUPEN bit enables the use of ACMPLP0 interrupts to cancel Software Standby mode.
RTCALMWUPEN bit (RTC Alarm Interrupt Software Standby Returns Enable)
The RTCALMWUPEN bit enables the use of RTC alarm interrupts to cancel Software Standby mode.
RTCPRDWUPEN bit (RTC Period Interrupt Software Standby Returns Enable)
The RTCPRDWUPEN bit enables the use of RTC period interrupts to cancel Software Standby mode.
USBFSWUPEN bit (USBFS Interrupt Software Standby Returns Enable)
The USBFSWUPEN bit enables the use of USBFS interrupts to cancel Software Standby mode.
AGT1UDWUPEN bit (AGT1 Underflow Interrupt Software Standby Returns Enable)
The AGT1UDWUPEN bit enables the use of the AGT1 underflow interrupts to cancel Software Standby mode.
AGT1CAWUPEN bit (AGT1 Compare Match A Interrupt Software Standby Returns Enable)
The AGT1CAWUPEN bit enables the use of AGT1 compare match A interrupts to cancel Software Standby mode.
AGT1CBWUPEN bit (AGT1 Compare Match B Interrupt Software Standby Returns Enable)
The AGT1CBWUPEN bit enables the use of AGT1 compare match B interrupts to cancel Software Standby mode.
IIC0WUPEN bit (IIC0 Address Match Interrupt Software Standby Returns Enable)
The IIC0WUPEN bit enables the use of IIC0 interrupts to cancel Software Standby mode.
12.3
Vector Table
The ICU detects two types of interrupts:
Maskable interrupts
Non-maskable interrupts.
Interrupt priorities are set up in the Arm NVIC. For information on these registers, see the NVIC chapter of the ARM®
Cortex®-M0+ Processor Technical Reference Manual (ARM DDI 0484C).
12.3.1
Interrupt Vector Table
Table 12.3 describes the interrupt vector table. The interrupt vector addresses conform to the NVIC specifications.
Table 12.3
Interrupt vector table (1 of 2)
Exception
number
IRQ number
Vector offset Source
Description
0
—
000h
Arm
Initial stack pointer
1
—
004h
Arm
Initial program counter (reset vector)
2
—
008h
Arm
Non-maskable Interrupt (NMI)
3
—
00Ch
Arm
Hard Fault
4
—
010h
Arm
Reserved
5
—
014h
Arm
Reserved
6
—
018h
Arm
Reserved
7
—
01Ch
Arm
Reserved
8
—
020h
Arm
Reserved
9
—
024h
Arm
Reserved
10
—
028h
Arm
Reserved
11
—
02Ch
Arm
Supervisor call (SVCall)
12
—
030h
Arm
Reserved
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Table 12.3
12. Interrupt Controller Unit (ICU)
Interrupt vector table (2 of 2)
Exception
number
IRQ number
Vector offset Source
Description
13
—
034h
Arm
Reserved
14
—
038h
Arm
Pendable request for system service (PendableSrvReq)
15
—
03Ch
Arm
System tick timer (SysTick)
16
0
040h
ICU.IELSR0
Event selected in the ICU.IELSR0 register
17
1
044h
ICU.IELSR1
Event selected in the ICU.IELSR1 register
18
2
048h
ICU.IELSR2
Event selected in the ICU.IELSR2 register
19
3
04Ch
ICU.IELSR3
Event selected in the ICU.IELSR3 register
20
4
050h
ICU.IELSR4
Event selected in the ICU.IELSR4 register
21
5
054h
ICU.IELSR5
Event selected in the ICU.IELSR5 register
22
6
058h
ICU.IELSR6
Event selected in the ICU.IELSR6 register
23
7
05Ch
ICU.IELSR7
Event selected in the ICU.IELSR7 register
24
8
060h
ICU.IELSR8
Event selected in the ICU.IELSR8 register
25
9
064h
ICU.IELSR9
Event selected in the ICU.IELSR9 register
26
10
068h
ICU.IELSR10
Event selected in the ICU.IELSR10 register
27
11
06Ch
ICU.IELSR11
Event selected in the ICU.IELSR11 register
28
12
070h
ICU.IELSR12
Event selected in the ICU.IELSR12 register
29
13
074h
ICU.IELSR13
Event selected in the ICU.IELSR13 register
30
14
078h
ICU.IELSR14
Event selected in the ICU.IELSR14 register
31
15
07Ch
ICU.IELSR15
Event selected in the ICU.IELSR15 register
32
16
080h
ICU.IELSR16
Event selected in the ICU.IELSR16 register
33
17
084h
ICU.IELSR17
Event selected in the ICU.IELSR17 register
34
18
088h
ICU.IELSR18
Event selected in the ICU.IELSR18 register
35
19
08Ch
ICU.IELSR19
Event selected in the ICU.IELSR19 register
36
20
090h
ICU.IELSR20
Event selected in the ICU.IELSR20 register
37
21
094h
ICU.IELSR21
Event selected in the ICU.IELSR21 register
38
22
098h
ICU.IELSR22
Event selected in the ICU.IELSR22 register
39
23
09Ch
ICU.IELSR23
Event selected in the ICU.IELSR23 register
40
24
0A0h
ICU.IELSR24
Event selected in the ICU.IELSR24 register
41
25
0A4h
ICU.IELSR25
Event selected in the ICU.IELSR25 register
42
26
0A8h
ICU.IELSR26
Event selected in the ICU.IELSR26 register
43
27
0ACh
ICU.IELSR27
Event selected in the ICU.IELSR27 register
44
28
0B0h
ICU.IELSR28
Event selected in the ICU.IELSR28 register
45
29
0B4h
ICU.IELSR29
Event selected in the ICU.IELSR29 register
46
30
0B8h
ICU.IELSR30
Event selected in the ICU.IELSR30 register
47
31
0BCh
ICU.IELSR31
Event selected in the ICU.IELSR31 register
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12.3.2
12. Interrupt Controller Unit (ICU)
Event Number
The following table lists heading details for Table 12.4, which describes each event number.
Parameter
Description
Interrupt request source
Name of the generation source for the interrupt request.
Name
Name of the interrupt.
Connect to NVIC
“” indicates the interrupt can be used as a CPU interrupt.
Invoke DTC
“” indicates the interrupt can be used to request DTC activation.
Canceling Snooze mode
“” indicates the interrupt can be used to request a return from Snooze mode.
Canceling Software Standby mode
“” indicates the interrupt can be used to request a return from Software Standby mode.
Table 12.4
Event table (1 of 4)
IELSRn
Invoke DTC
Canceling
Snooze
Canceling
Software
Standby
PORT_IRQ2
04h
PORT_IRQ3
05h
PORT_IRQ4
06h
PORT_IRQ5
07h
PORT_IRQ6
08h
PORT_IRQ7
Name
Connect to
NVIC
PORT_IRQ0
02h
PORT_IRQ1
03h
Event
number
Interrupt request source
01h
Port
09h
DTC
DTC_COMPLETE
*4
0Bh
ICU
ICU_SNZCANCEL
0Ch
FCU
FCU_FRDYI
0Dh
LVD
LVD_LVD1
LVD_LVD2
0Eh
0Fh
MOSC
MOSC_STOP
10h
Low power mode
SYSTEM_SNZREQ
11h
AGT0
AGT0_AGTI
12h
AGT0_AGTCMAI
13h
AGT0_AGTCMBI
AGT1_AGTI
15h
AGT1_AGTCMAI
16h
AGT1_AGTCMBI
IWDT_NMIUNDF
14h
AGT1
17h
IWDT
18h
WDT
WDT_NMIUNDF
19h
RTC
RTC_ALM
1Ah
RTC_PRD
1Bh
RTC_CUP
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Table 12.4
12. Interrupt Controller Unit (ICU)
Event table (2 of 4)
IELSRn
Name
Connect to
NVIC
Invoke DTC
ADC140_ADI
1Dh
ADC140_GBADI
1Eh
ADC140_CMPAI
1Fh
ADC140_CMPBI
20h
ADC140_WCMPM
*4
21h
ADC140_WCMPUM
*4
Event
number
Interrupt request source
1Ch
ADC140
22h
ACMPLP
23h
24h
USBFS
25h
26h
ACMP_LP1
USBFS_USBI
USBFS_USBR
IIC0_RXI
27h
IIC0_TXI
28h
IIC0_TEI
29h
IIC0_EEI
2Ah
IIC0_WUI
IIC1_RXI
2Ch
IIC1_TXI
2Dh
IIC1_TEI
2Eh
IIC1_EEI
CTSU_CTSUWR
30h
CTSU_CTSURD
31h
CTSU_CTSUFN
*4
KEY_INTKR
*1
*4
2Fh
32h
IIC1
CTSU
KINT
33h
DOC
DOC_DOPCI
34h
CAC
CAC_FERRI
35h
CAC_MENDI
36h
CAC_OVFI
37h
CAN0_ERS
38h
CAN0_RXF
39h
CAN0_TXF
3Ah
CAN0_RXM
3Bh
CAN0_TXM
IOPORT_GROUP1
*2
IOPORT_GROUP2
*2
ELC_SWEVT0
* 3
ELC_SWEVT1
* 3
3Ch
CAN0
I/O Ports
3Dh
3Eh
ELC
3Fh
40h
POEG_GROUP0
POEG
POEG_GROUP1
GPT0_CCMPA
43h
GPT0_CCMPB
44h
GPT0_CMPC
45h
GPT0_CMPD
46h
GPT0_OVF
47h
GPT0_UDF
41h
42h
GPT320
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Canceling
Software
Standby
2Bh
IIC0
ACMP_LP0
Canceling
Snooze
*1
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Table 12.4
12. Interrupt Controller Unit (ICU)
Event table (3 of 4)
IELSRn
Name
Connect to
NVIC
Invoke DTC
GPT1_CCMPA
49h
GPT1_CCMPB
4Ah
GPT1_CMPC
4Bh
GPT1_CMPD
4Ch
GPT1_OVF
4Dh
GPT1_UDF
GPT2_CCMPA
4Fh
GPT2_CCMPB
50h
GPT2_CMPC
51h
GPT2_CMPD
52h
GPT2_OVF
53h
GPT2_UDF
GPT3_CCMPA
55h
GPT3_CCMPB
56h
GPT3_CMPC
57h
GPT3_CMPD
58h
GPT3_OVF
59h
GPT3_UDF
GPT4_CCMPA
5Bh
GPT4_CCMPB
5Ch
GPT4_CMPC
5Dh
GPT4_CMPD
5Eh
GPT4_OVF
5Fh
GPT4_UDF
Event
number
Interrupt request source
48h
GPT161
4Eh
54h
5Ah
60h
GPT162
GPT163
GPT164
GPT5_CCMPA
61h
GPT5_CCMPB
62h
GPT5_CMPC
63h
GPT5_CMPD
64h
GPT5_OVF
65h
GPT5_UDF
GPT6_CCMPA
67h
GPT6_CCMPB
68h
GPT6_CMPC
69h
GPT6_CMPD
6Ah
GPT6_OVF
6Bh
GPT6_UDF
66h
GPT165
GPT166
6Ch
GPT
GPT_UVWEDGE
6Dh
SCI0
SCI0_RXI
6Eh
SCI0_TXI
6Fh
SCI0_TEI
70h
SCI0_ERI
71h
SCI0_AM
72h
SCI0_RXI_OR_ERI
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Canceling
Snooze
Canceling
Software
Standby
*4
*4
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Table 12.4
12. Interrupt Controller Unit (ICU)
Event table (4 of 4)
IELSRn
Name
Connect to
NVIC
Invoke DTC
SCI1_RXI
74h
SCI1_TXI
75h
SCI1_TEI
76h
SCI1_ERI
SCI1_AM
SCI9_RXI
79h
SCI9_TXI
7Ah
SCI9_TEI
7Bh
SCI9_ERI
7Ch
SCI9_AM
SPI0_SPRI
7Eh
SPI0_SPTI
7Fh
SPI0_SPII
80h
SPI0_SPEI
81h
SPI0_SPTEND
SPI1_SPRI
83h
SPI1_SPTI
84h
SPI1_SPII
85h
SPI1_SPEI
86h
SPI1_SPTEND
AES
AES_WRREQ
AES_RDREQ
TRNG
TRNG_RDREQ
Event
number
Interrupt request source
73h
SCI1
77h
78h
7Dh
82h
87h
SCI9
SPI0
SPI1
88h
89h
Note 1.
Note 2.
Note 3.
Note 4.
12.4
Canceling
Snooze
Canceling
Software
Standby
Only supported when KRCTL.KRMD is 1.
Only the first edge detection is valid.
Only interrupts after DTC transfer are supported.
Using SELSR0.
Interrupt Operation
The ICU performs the following functions:
Detecting interrupts
Enabling and disabling interrupts
Selecting interrupt request destinations such as CPU interrupt or DTC activation.
12.4.1
Detecting Interrupts
External pin interrupt requests are detected in either:
Edges (falling edge, rising edge, or rising and falling edges) of the interrupt signal
Level (low level) of the interrupt signal.
Set the IRQMD[1:0] bits in the IRQCRi register to select the detection mode for the IRQi pins. For interrupt sources
associated with peripheral module, see section 12.3.2, Event Number. Events must be accepted by the NVIC before an
interrupt occurs and is accepted by the CPU.
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12. Interrupt Controller Unit (ICU)
ICU
CPU : NVIC
IELSRn
Event
factor
Select of event factor
Interrupt
source
Set by S/W interrupt
IR
Set
Reset
pending
Set
Reset
Enable register
Clear by S/W
Figure 12.2
Automatically cleared by
the interrupt completion
Interrupt path of the ICU and CPU (NVIC)
Operations during an interrupt:
When a non-software interrupt is generated:
The IELSRn.IR flag and Interrupt Set/Clear-Pending register (NVIC) are set.
When a software interrupt is generated:
Set the Interrupt Set-Pending register.
When an interrupt is complete:
Clear the IELSRn.IR flag with software.
The Interrupt Set/Clear Pending register clears automatically.
When interrupts are enabled:
1. Set the Interrupt Set-Enable register.
2. Set the IELSRn.IELS bits as the interrupt source.
3. Specify the operation settings for the event source.
When interrupts are disabled:
1. Disable the settings for the event source.
2. Clear the IELSRn.IELS bits (IELSRn.IELS = 00h). Clear the IELSRn.IR flag as required.
3. Clear the Interrupt Clear-Enable register. Clear the Interrupt Clear-Pending register as required.
When polling for interrupts:
1. Set the Interrupt Clear-Enable register (disabling interrupts).
2. Set the IELSRn.IELS bits (selecting the source).
3. Specify the operation settings for the event source.
4. Poll the Interrupt Set-Pending register.
5. When polling is no longer required, follow the procedure for clearing an interrupt when it is complete.
12.4.2
Selecting Interrupt Request Destinations
The interrupt output destination, CPU or DTC, can be independently selected for each interrupt source. The available
destinations are fixed for each interrupt, as described in Table 12.4.
Note:
Do not use an interrupt request destination setting that is not indicated by a in the event list (Table 12.4).
If you select the CPU or DTC in the IELSRn register, setting the same interrupt factor in any other IELSRn register is
prohibited.
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12. Interrupt Controller Unit (ICU)
If the DTC is selected as the destination for requests from an IRQi pin, you must set the IRQMD[1:0] bits in IRQCRi for
that interrupt to select edge detection.
12.4.2.1
CPU interrupt request
When IELSRn.DTCE = 0, the event specified in the IELSRn register is output to the NVIC.
Set the IELSRn.IELS bits to the target event and the IELSRn.DTCE bit to 0.
12.4.2.2
DTC activation
When IELSRn.DTCE = 1, the event specified in the IELSRn register is output to the DTC. Use the following procedure:
1. Set the IELSRn.IELS bits to the target event and the IELSRn.DTCE bit to 1.
2. Set the DTC module activation bit (DTCST.DTCST) to 1.
Table 12.5 shows operation when the DTC is the request destination.
Table 12.5
Operation when DTC is activated
Interrupt
request
destination
DISEL*1
Remaining
transfer
operations
DTC*3
1
0
Operation per
request
IR*2
≠0
DTC transfer →
CPU interrupt
Cleared on interrupt acceptance by
the CPU
DTC
=0
DTC transfer →
CPU interrupt
Cleared on interrupt acceptance by
the CPU
The IELSRn.DTCE bit is cleared
and the CPU becomes the
destination
≠0
DTC transfer
Cleared at the start of DTC data
transfer after reading DTC transfer
data
DTC
=0
DTC transfer →
CPU interrupt
Cleared on interrupt acceptance by
the CPU
The IELSRn.DTCE bit is cleared
and the CPU becomes the
destination
Interrupt request destination
after transfer
Note 1. Set the interrupt request mode for the DTC in the DTC.MRB.DISEL bit.
Note 2. When the IELSRn.IR flag is 1, an interrupt request (DTC activation request) that is generated again is ignored.
Note 3. For chain transfer, DTC transfer continues until the last chain transfer ends. The DISEL bit state and the
remaining transfer count determine whether a CPU interrupt is generated, the IELSRn.IR flag clear timing, and
the interrupt request destination after transfer. See Table 14.3, Chain transfer conditions in section 14, Data
Transfer Controller (DTC).
12.4.3
Digital Filter
A digital filter function is provided for the external interrupt request pins (IRQi, i = 0 to 7) and NMI pin interrupt. It
samples input signals on the filter sampling clock (PCLKB) and removes any signal with a pulse width less than 3
sampling cycles.
To use the digital filter for an IRQi pin:
1. Set the sampling clock cycle to PCLKB, PCLKB/8, PCLKB/32, or PCLKB/64 with the IRQCRi.FCLKSEL[1:0]
bits (i = 0 to 7).
2. Set the IRQCRi.FLTEN bit (i = 0 to 7) to 1 (digital filter enabled).
To use the digital filter for the NMI pin:
1. Set the sampling clock cycle to PCLKB, PCLKB/8, PCLKB/32, or PCLKB/64 with the NMICR.NFCLKSEL[1:0]
bits.
2. Set the NMICR.NFLTEN bit to 1 (digital filter enabled).
Figure 12.3 shows an example of digital filter operation.
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12. Interrupt Controller Unit (ICU)
Sampling clock
for digital filter
IRQCRi.FLTEN bit*1
Pulses removed
The level matches
three times
IRQi pin*1
The level matches
three times
IRQi_d*1
(internal F/F)
Digital filter enabled
Disabled
Enabled
Operation example with IRQCRi.IRQMD[1:0] = 11b (low)
Note 1. i = 0 to 7
Figure 12.3
Digital filter operation example
Before entering Software Standby mode, disable the digital filters by clearing the IRQCRi.FLTEN and NMICR.NFLTEN
bits. The clock of the ICU stops in Software Standby mode. On exiting Software Standby mode, you can enable the
digital filters again.
The circuit detects the edge by comparing the state before standby to the state after standby release. If the input changes
during Software Standby mode, an incorrect edge might be detected.
12.4.4
External Pin Interrupts
To use external pin interrupts:
1. Clear the IRQCRi.FLTEN bit (i = 0 to 7) to 0 (digital filter disabled).
2. Specify or confirm the I/O port settings.
3. Set the IRQMD[1:0] bits, FCLKSEL[1:0] bits, and FLTEN bit of the IRQCRi register.
4. Select the IRQ pin as follows:
If the IRQ pin is to be used for CPU interrupt requests, set the IELSRn.IELS bits and the IELSRn.DTCE bit to 0
If the IRQ pin is to be used for DTC activation, set the IELSRn.IELS bits and the IELSRn.DTCE bit to 1.
12.5
Non-Maskable Interrupt Operation
The following sources can trigger a non-maskable interrupt:
NMI pin interrupt
Oscillation stop detection interrupt
WDT underflow/refresh error interrupt
IWDT underflow/refresh error interrupt
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
SRAM parity error interrupt.
Non-maskable interrupts can only be used with the CPU, not to activate the DTC. Non-maskable interrupts take
precedence over all other interrupts. The non-maskable interrupt states can be verified in the Non-Maskable Interrupt
Status Register (NMISR). Confirm that all bits in the NMISR are 0 before returning from the NMI handler.
Non-maskable interrupts are disabled by default. To use non-maskable interrupts, use the following procedure:
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12. Interrupt Controller Unit (ICU)
To use the NMI pin:
1. Clear the NMICR.NFLTEN bit to 0 (digital filter disabled).
2. Set the NMIMD bit, NFCLKSEL[1:0] bits, and NFLTEN bit of NMICR register.
3. Write 1 to the NMICLR.NMICLR bit to clear the NMISR.NMIST flag to 0.
4. Enable the non-maskable interrupt by writing 1 to the associated bit in the Non-Maskable Interrupt Enable Register
(NMIER).
After 1 is written to the NMIER register, subsequent write access to the NMIEN bit in NMIER is ignored. When an NMI
interrupt is enabled, it can be disabled only by a reset.
12.6
Return from Low Power Modes
Table 12.4, Event table lists the interrupt sources you can use to exit Sleep mode or Software Standby mode. For more
information, see section 10, Low Power Modes. Sections 12.6.1 to 12.6.3 describe how to use interrupts to return from
Sleep, Software Standby, and Snooze modes.
12.6.1
Return from Sleep Mode
To return from Sleep mode in response to an interrupt:
1. Select the CPU as the interrupt request destination.
2. Enable the interrupt in the NVIC.
To return from Sleep mode in response to a non-maskable interrupt, enable the given interrupt request in the NMIER
register.
12.6.2
Return from Software Standby Mode
The ICU can return from Software Standby mode using a non-maskable interrupt or an interrupt selected in the WUPEN
register. See section 12.2.8, Wake Up Interrupt Enable Register (WUPEN).
To return from Software Standby mode:
1. Select the interrupt source that enables return from Software Standby:
For non-maskable interrupts, use the NMIER register to enable the given interrupt request
For maskable interrupts, use the WUPEN register to enable the given interrupt request.
2. Select the CPU as the interrupt request destination.
3. Enable the interrupt in the NVIC.
Interrupt requests through the IRQ pins that do not satisfy these conditions are not detected while the clock is stopped in
Software Standby mode.
12.6.3
Return from Snooze Mode
The ICU can return from Snooze mode using the interrupts provided for this mode.
To return from Snooze mode to Normal mode:
1. Use either of the following methods to select the event that you want to trigger a return from Snooze mode to
Normal mode:
Set the event that you want to trigger a return from Snooze mode to Normal mode in SELSR0.SEL and set the
value 0Bh (ICU_SNZCANCEL) in IELSRn.IELS
Set the event that you want to trigger a return from Snooze mode to Normal mode in IELSRn.IELS.
2. Select the CPU as the interrupt destination.
3. Enable the interrupt in the NVIC.
Interrupt requests through the IRQ pins that do not satisfy these conditions are not detected while the clock is stopped in
Snooze mode.
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Note:
12.7
12. Interrupt Controller Unit (ICU)
In Snooze mode, a clock is supplied to the ICU. If an event selected in IELSRn is detected, the CPU can
acknowledge the interrupt after returning to Normal mode from Software Standby mode.
Using the WFI Instruction with Non-maskable Interrupt
Whenever a WFI instruction is executed, confirm that all status flags in the NMISR register are 0.
12.8
Reference
ARM® Cortex®-M0+ Processor Technical Reference Manual (ARM DDI 0484C).
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13.
Buses
13.1
Overview
13. Buses
Table 13.1 lists the bus specifications, Figure 13.1 shows the bus configuration, and Table 13.2 lists the addresses
assigned for each bus.
Table 13.1
Bus specifications
Bus type
Main bus
Slave
Interface
Description
System bus (CPU)
Connected to CPU
Connected to on-chip memory and Internal peripheral bus.
DMA bus
Connected to DTC
Connected to on-chip memory and Internal peripheral bus.
Memory bus 1
Connected to code flash memory
Memory bus 4
Connected to SRAM0
Internal peripheral bus 1
Connected to system control related to peripheral modules
Connected to flash memory (in P/E) and data flash memory.
Internal peripheral bus 3
Connected to peripheral modules (CAC, ELC, I/O Ports, POEG, RTC, WDT, IWDT, SCI,
IIC, CAN, SPI, CRC, GPT, ADC14, DAC12, and DOC)
Connected to Secure IPs.
Internal peripheral bus 5
Connected to peripheral modules (KINT, AGT, USBFS, ACMPLP, and CTSU)
CM0+
DTC
System bus
DMA bus
Code flash
memory
Figure 13.1
Table 13.2
SRAM0
Data flash
memory
Internal
peripheral
Bus configuration
Addresses assigned for each bus
Address
Bus
Area
0000 0000h to 01FF FFFFh
Memory bus 1
Code flash memory
2000 0000h to 2000 3FFFh
Memory bus 4
SRAM0
4000 0000h to 4001 FFFFh
Internal peripheral bus 1
Peripheral I/O registers
4004 0000h to 4007 FFFFh
Internal peripheral bus 3
4008 0000h to 400B FFFFh
Internal peripheral bus 5
400C 0000h to 400D FFFFh
Internal peripheral bus 3
Secure IPs
4010 0000h to 407F FFFFh
Internal peripheral bus 1
Flash memory (in P/E*1) and data flash memory
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13. Buses
Note 1. P/E = Programming/Erasure
13.2
Description of Buses
13.2.1
Main Buses
The main bus for the CPU consists of the system bus and DMA bus. System bus and DMA bus are connected to the
following:
Code flash memory
SRAM0
Data flash memory
Internal peripheral bus.
The system bus is used for instruction code and data code access to the CPU.
Different master and slave transfer combinations can proceed simultaneously. In addition, requests for bus access from
masters other than the DTC are not accepted during reads of transfer control information for the DTC.
13.2.2
Slave Interface
For connections from the main bus to the slave interface, see the slave interface in Table 13.1, Bus specifications.
Bus access from the system bus and DMA bus are arbitrated. The arbitration method is selectable as either fixed priority
or round-robin. For more information, see section 13.3.2.
Different master and slave transfer combinations can proceed simultaneously.
13.2.3
Parallel Operation
Parallel operations are possible when different bus masters request access to different slave modules. Figure 13.2 shows
an example of parallel operations. In this example, the CPU uses the instruction and operand buses for simultaneous
access to the flash and SRAM, respectively. Additionally, the DTC simultaneously uses the DMA bus for access to a
peripheral bus during access to the flash and SRAM by the CPU.
Flash/SRAM access
CPU system
Flash
Flash
Flash
SRAM
SRAM
SRAM
SRAM
Peripheral bus access
DTC
Figure 13.2
13.2.4
(1)
Peripheral bus
Example of parallel operations
Constraints
Endianness Constraint
Memory space must be little-endian to execute code on the Cortex®-M0+ core.
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13.3
13. Buses
Register Descriptions
13.3.1
Master Bus Control Register (BUSMCNT)
Address(es): BUS.BUSMCNTSYS 4000 4008h, BUS.BUSMCNTDMA 4000 400Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
IERES
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
b14 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b15
IERES
Ignore Error Responses
0: A bus error is reported
1: A bus error is not reported.
Note:
R/W
R/W
Changing reserved bits from the initial value of 0 is prohibited. Operation during the change is not guaranteed.
IERES bit (Ignore Error Responses)
This bit, when set, disables the AHB-Lite protocol error response.
Table 13.3 shows the registers associated with each bus type.
Table 13.3
Associations between bus types and registers
Bus type
Master Bus Control Register
Slave Bus Control Register
System bus (CPU)
BUSMCNTSYS
-
DMA bus
BUSMCNTDMA
-
Memory bus 1
-
BUSSCNTFLI
Memory bus 4
-
BUSSCNTRAM0
Internal peripheral bus 1, 3, 5
-
BUSSCNTPnB [n=0,2,4]
13.3.2
Slave Bus Control Register (BUSSCNT)
Address(es): BUS.BUSSCNTFLI 4000 4100h, BUS.BUSSCNTRAM0 4000 410Ch, BUS.BUSSCNTP0B 4000 4114h,
BUS.BUSSCNTP2B 4000 4118h, BUS.BUSSCNTP4B 4000 4120h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
Value after reset:
b5
b4
ARBMET[1:0]
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
R/W
b5, b4
ARBMET[1:0]
Arbitration Method
Specifies the group priorities:
R/W
b5 b4
0 0: fixed priority
0 1: round-robin
1 0: Setting prohibited
1 1: Setting prohibited.
b15 to b6
Note:
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Changing reserved bits from the initial value of 0 is prohibited. Operation during the change is not guaranteed.
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13. Buses
ARBMET[1:0] bits (Arbitration Method)
These bits specify the arbitration method, with priority defined for all bus masters. For fixed priority, see Table 13.4. For
round-robin, see Table 13.5. For the associations between bus types and registers, see Table 13.3.
Table 13.4
Fixed priority (ARBMET[1:0] = 00b)
Slave Bus Control Register
Slave interface
Priority
BUSSCNTFLI
Memory bus 1
Memory bus 3 > System bus (CPU)
BUSSCNTRAM0
Memory bus 4
DMA bus > System bus (CPU)
BUSSCNTPnB [n = 0,2,4]
Internal peripheral bus 1, 3, 5
DMA bus > System bus (CPU)
Table 13.5
Round-robin priority (ARBMET[1:0] = 01b)
Slave Bus Control Register
Slave interface
Priority*1
BUSSCNTFLI
Memory bus 1
Memory bus 3 System bus (CPU)
BUSSCNTRAM0
Memory bus 4
DMA bus System bus (CPU)
BUSSCNTPnB [n = 0,2,4]
Internal peripheral bus 1, 3, 5
DMA bus System bus (CPU)
Note 1. Round-robin priority is denoted by .
13.4
Bus Error Monitoring Section
The monitoring system monitors each individual area, and whenever it detects an error, it returns the error to the
requesting master IP using the AHB-Lite protocol.
13.4.1
Error Type that Occurs by Bus
Two types of error can occur on each bus:
Illegal address access
Timeout.
Table 13.6 lists the address ranges where access leads to illegal address access errors. The reserved area in the slave does
not trigger an illegal address access error.
13.4.2
Operation when a Bus Error Occurs
When a bus error occurs, operation is not guaranteed and the error is returned to the requesting master IP.
Note:
DTC does not receive bus errors. If the DTC accesses the bus, the transfer continues.
13.4.3
Conditions Leading to Illegal Address Access Errors
Table 13.6 lists the address spaces for each bus that trigger illegal address access errors.
Table 13.6
Conditions leading to illegal address access errors (1 of 2)
Master bus
CPU
Address
Slave bus name
System
DMA
0000 0000h to 01FF FFFFh
Memory bus 1
-
-
0200 0000h to 1FFF FFFFh
Reserved
E
E
2000 0000h to 2000 3FFFh
Memory bus 4
-
-
2000 4000h to 3FFF FFFFh
Reserved
E
E
4000 0000h to 4001 FFFFh
Peripheral bus 1
-
-
4002 0000h to 4003 FFFFh
Reserved
E
E
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Table 13.6
13. Buses
Conditions leading to illegal address access errors (2 of 2)
Master bus
CPU
Address
Slave bus name
System
DMA
4004 0000h to 4007 FFFFh
Peripheral bus 3
-
-
4008 0000h to 400B FFFFh
Peripheral bus 5
-
-
400C 0000h to 400D FFFFh
Peripheral bus 3
-
-
400E 0000h to 400F FFFFh
Reserved
E
E
4010 0000h to 407F FFFFh
Peripheral bus 1
-
-
4080 0000h to DFFF FFFFh
Reserved
E
E
E000_0000h to FFFF_FFFFh
System for Cortex-M0+
-
E
Note:
Note:
Note:
13.4.4
E indicates the path where an illegal address access error occurs.
— indicates the path where an illegal address access error did not occur.
The bus module detects an access error resulting from access to reserved area, for example if no area is
assigned for the slave.
0200 0000h to 1FFF FFFFh: Access error detection.
0000 0000h to 01FF FFFFh: Memory bus 1 no access error detection.
Timeout
For some peripheral modules, a timeout error occurs with the module-stop function. When there is no response from the
slave for a certain time period, a timeout error is detected. A timeout error is returned to the requesting master IP using
the AHB-Lite error response protocol.
13.5
References
1. ARM® Cortex®-M0+ Devices Generic User Guide (ARM DUI 0662B)
2. ARM® AMBA® 3 AHB-Lite Protocol v1.0 Specification (ARM IHI 0033A).
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14. Data Transfer Controller (DTC)
14.
Data Transfer Controller (DTC)
14.1
Overview
The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when activated by an interrupt
request. Table 14.1 lists the DTC specifications and Figure 14.1 shows the block diagram.
Table 14.1
DTC specifications
Parameter
Description
Transfer modes
Normal transfer mode
A single activation leads to a single data transfer.
Repeat transfer mode
A single activation leads to a single data transfer.
The transfer address returns to the start address after the number of data transfers reaches the
specified repeat size.
The maximum number of repeat transfers is 256 and the maximum data transfer size is 256 ×
32 bits (1024 bytes).
Block transfer mode
A single activation leads to a transfer of a single block.
The maximum block size is 256 × 32 bits = 1024 bytes.
Transfer channel
Channel transfer can be associated with the interrupt source is possible (transferred by a DTC
activation request from the ICU)
Multiple data units can be transferred on a single activation source (chain transfer)
Chain transfers selectable to either executed when the counter is 0, or always executed.
Transfer space
4 GB area from 0000 0000h to FFFF FFFFh except reserved areas.
Data transfer units
Single data unit: 1 byte (8 bits), 1 halfword (16 bits), 1 word (32 bits)
Single block size: 1 to 256 data units.
CPU interrupt source
An interrupt request can be generated to the CPU on a DTC activation interrupt
An interrupt request can be generated to the CPU after a single data transfer
An interrupt request can be generated to the CPU after data transfer of a specified volume.
Event link function
An event link request is generated after one data transfer (for block, after one block transfer)
Read skip
Transfer information read skip can be executed
Write-back skip
When the transfer source or destination address is specified as fixed, a write-back skip is
executed
Module-stop function
Module-stop state can be set
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14. Data Transfer Controller (DTC)
CPU
Non-maskable interrupt request
Interrupt request
NVIC
DTC
Interrupt
controller
MRA
MRB
CRA
Register
control
CRB
SAR
DAR
Activation request
Activation
control
DTC internal bus
Vector number
DTC response
DTCCR
Snooze control
signals
DTCVBR
DTCST
DTC_
DTCEND
System
Bus interface
DTC
response
control
DTCSTS
ELC
DMA Bus
Internal peripheral bus 1
System bus
DMA Bus
MRA:
MRB:
CRA:
CRB:
SAR:
DAR:
Figure 14.1
Code flash
DTC Mode Register A
DTC Mode Register B
DTC Transfer Count Register A
DTC Transfer Count Register B
DTC Transfer Source Register
DTC Transfer Destination Register
FCU
E2P
DTCCR:
DTCVBR:
DTCST:
DTCSTS:
SRAM0
Transfer
information
Internal
peripheral buses
DTC Control Register
DTC Vector Base Register
DTC Module Start Register
DTC Status Register
DTC block diagram
See Overview in section 12, Interrupt Controller Unit (ICU) for the connections between the DTC and NVIC in the CPU.
14.2
Register Descriptions
The MRA, MRB, SAR, DAR, CRA, and CRB are all DTC internal registers that cannot be directly accessed from the
CPU. Values to be set in these DTC internal registers are placed in the SRAM area as transfer information. When an
activation request is generated, the DTC reads the transfer information from the SRAM area and sets it in its internal
registers. After the data transfer ends, the internal register contents are written back to the SRAM area as transfer
information.
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14.2.1
14. Data Transfer Controller (DTC)
DTC Mode Register A (MRA)
Address(es): (inaccessible directly from the CPU. See section 14.3.1)
b7
b6
b5
MD[1:0]
x
Value after reset:
x
b4
SZ[1:0]
x
b3
b2
SM[1:0]
x
x
x
b1
b0
—
—
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as undefined. The write value should be 0. —
b3, b2
SM[1:0]
Transfer Source Address
Addressing Mode
b3 b2
—
b5, b4
SZ[1:0]
DTC Data Transfer Size
b5 b4
—
b7, b6
MD[1:0]
DTC Transfer Mode Select
b7 b6
—
0 0: Address in the SAR register is fixed
(write-back to SAR is skipped)
0 1: Address in the SAR register is fixed
(write-back to SAR is skipped)
1 0: SAR value is incremented after data transfer
(+1 when SZ[1:0] bits = 00b, +2 when SZ[1:0] bits =
01b, +4 when SZ[1:0] bits = 10b)
1 1: SAR value is decremented after data transfer
(-1 when SZ[1:0] bits = 00b, –2 when SZ[1:0] bits = 01b,
-4 when SZ[1:0] bits = 10b).
0
0
1
1
0
0
1
1
0: Byte (8-bit) transfer
1: Halfword (16-bit) transfer
0: Word (32-bit) transfer
1: Setting prohibited.
0: Normal transfer mode
1: Repeat transfer mode
0: Block transfer mode
1: Setting prohibited.
The MRA register cannot be accessed directly from the CPU. The CPU can access SRAM area (transfer information (n)
start address + 03h) and DTC transfer it automatically from and to the MRA register. See section 14.3.1, Allocating
Transfer Information and DTC Vector Table.
14.2.2
DTC Mode Register B (MRB)
Address(es): (inaccessible directly from the CPU. See section 14.3.1)
b7
CHNE
x
Value after reset:
b6
b5
CHNS DISEL
x
x
b4
DTS
x
b3
b2
DM[1:0]
x
x
b1
b0
—
—
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as undefined. The write value should be 0.
—
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14. Data Transfer Controller (DTC)
Bit
Symbol
Bit name
Description
R/W
b3, b2
DM[1:0]
Transfer Destination
Address Addressing Mode
b3 b2
—
b4
DTS
DTC Transfer Mode Select
0: Transfer destination is the repeat or block area
1: Transfer source is the repeat or block area.
—
b5
DISEL
DTC Interrupt Select
0: An interrupt request to the CPU is generated when specified
data transfer is complete
1: An interrupt request to the CPU is generated each time DTC
data transfer is performed.
—
b6
CHNS
DTC Chain Transfer Select
0: Chain transfer is continuous
1: Chain transfer occurs only when the transfer counter changes
from 1 to 0 or 1 to CRAH.
—
b7
CHNE
DTC Chain Transfer Enable
0: Chain transfer is disabled
1: Chain transfer is enabled.
—
0 0: Address in the DAR register is fixed
(Write-back to DAR is skipped.)
0 1: Address in the DAR register is fixed
(Write-back to DAR is skipped.)
1 0: DAR value is incremented after data transfer
(+1 when MRA.SZ[1:0] bits = 00b, +2 when SZ[1:0] bits =
01b, +4 when SZ[1:0] bits = 10b)
1 1: DAR value is decremented after data transfer
(-1 when MRA.SZ[1:0] bits = 00b, -2 when SZ[1:0] bits = 01b,
-4 when SZ[1:0] bits = 10b)
The MRB register cannot be accessed directly from the CPU. The CPU can access the SRAM area (transfer information
(n) start address + 02h) and DTC transfer it automatically from and to the MRB register. See section 14.3.1, Allocating
Transfer Information and DTC Vector Table.
DTS bit (DTC Transfer Mode Select)
The DTS bit specifies whether the transfer source or destination is the repeat or block area in repeat or block transfer
mode.
CHNS bit (DTC Chain Transfer Select)
The CHNS bit selects the chain transfer condition. When CHNE is 0, the CHNS setting is ignored. For details on the
conditions for chain transfer, see Table 14.3, Chain transfer conditions.
When the next transfer is chain transfer, completion of the specified number of transfers is not determined, the activation
source flag is not cleared, and an interrupt request to the CPU is not generated.
CHNE bit (DTC Chain Transfer Enable)
The CHNE bit enables chain transfer. The chain transfer condition is selected by the CHNS bit. For details on chain
transfer, see section 14.4.6, Chain Transfer.
14.2.3
DTC Transfer Source Register (SAR)
Address(es): (inaccessible directly from the CPU. See section 18.3.1)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The SAR sets the transfer source start address and cannot be accessed directly from the CPU. The CPU can access the
SRAM area (transfer information (n) start address + 04h) and DTC transfer it automatically from and to the SAR register.
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14. Data Transfer Controller (DTC)
See section 14.3.1, Allocating Transfer Information and DTC Vector Table.
Note:
Misalignment is prohibited for DTC transfers.
14.2.4
DTC Transfer Destination Register (DAR)
Address(es): (inaccessible directly from the CPU. See section 18.3.1)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The DAR sets the transfer destination start address and cannot be accessed directly from the CPU. The CPU can access
the SRAM area (transfer information (n) start address + 08h) and DTC transfer it automatically from and to the DAR
register. See section 14.3.1, Allocating Transfer Information and DTC Vector Table. Bit [0] must be 0 when
MRA.SZ[1:0] = 01b, and bit [1] and bit [0] must be 0 when MRA.SZ[1:0] = 10b.
Note:
Misalignment is prohibited for DTC transfers.
14.2.5
DTC Transfer Count Register A (CRA)
Address(es): (inaccessible directly from the CPU. See section 14.3.1)
Normal transfer mode
CRA
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Repeat transfer mode/block transfer mode
CRAH
Value after reset:
CRAL
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Symbol
Register name
Description
R/W
CRAL
Transfer Counter A Lower Register
Set transfer count
—
CRAH
Transfer Counter A Upper Register
Note:
Note:
—
The function depends on the transfer mode.
Set CRAH and CRAL to the same value in repeat transfer mode and block transfer mode.
CRA cannot be accessed directly from the CPU. The CPU can access the SRAM area (transfer information (n) start
address + 0Eh) and DTC transfer it automatically from and to the CRA register. See section 14.3.1, Allocating Transfer
Information and DTC Vector Table.
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(1)
14. Data Transfer Controller (DTC)
Normal Transfer mode (MRA.MD[1:0] bits = 00b)
The CRA functions as a 16-bit transfer counter in normal transfer mode. The transfer count is 1, 65535, and 65536 when
the set value is 0001h, FFFFh, and 0000h, respectively. The CRA value is decremented (-1) at each data transfer.
(2)
Repeat Transfer mode (MRA.MD[1:0] bits = 01b)
In repeat transfer mode, the CRAH register holds the transfer count and the CRAL register functions as an 8-bit transfer
counter. The transfer count is 1, 255, and 256 when the set value is 01h, FFh, and 00h, respectively. The CRAL value is
decremented (-1) at each data transfer. When it reaches 00h, the CRAH value is transferred to CRAL.
(3)
Block Transfer mode (MRA.MD[1:0] bits = 10b)
In block transfer mode, the CRAH register holds the block size and the CRAL register functions as an 8-bit block size
counter. The transfer count is 1, 255, and 256 when the set value is 01h, FFh, and 00h, respectively. The CRAL value is
decremented (-1) at each data transfer. When it reaches 00h, the CRAH value is transferred to CRAL.
14.2.6
DTC Transfer Count Register B (CRB)
Address(es): (inaccessible directly from the CPU. See section 14.3.1)
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
The CRB sets the block transfer count for block transfer mode. The transfer count is 1, 65535, and 65536 when the set
value is 0001h, FFFFh, and 0000h, respectively. The CRB value is decremented (-1) when the final data of a single block
size is transferred. When normal transfer mode or repeat transfer mode is selected, this register is not used and the set
value is ignored.
The CRB cannot be accessed directly from the CPU. The CPU can access the SRAM area (transfer information (n) start
address + 0Ch) and DTC transfer it automatically from and to the CRB register. See section 14.3.1, Allocating Transfer
Information and DTC Vector Table.
14.2.7
DTC Control Register (DTCCR)
Address(es): DTC.DTCCR 4000 5400h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
RRS
—
—
—
—
0
0
0
0
1
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b4
RRS
DTC Transfer Information
Read Skip Enable
0: Transfer information read is not skipped.
1: Transfer information read is skipped when vector numbers match.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RRS bit (DTC Transfer Information Read Skip Enable)
The RRS bit enables skipping of transfer information reads when vector numbers match.
The DTC vector number is compared with the vector number in the previous activation process. When these vector
numbers match and the RRS bit is set to 1, DTC data transfer is performed without reading the transfer information.
However, when the previous transfer is chain transfer, the transfer information is read regardless of the value of the RRS
bit.
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14. Data Transfer Controller (DTC)
When the transfer counter (CRA register) becomes 0 during the previous normal transfer and when the transfer counter
(CRB register) becomes 0 during the previous block transfer, the transfer information is read regardless of the RRS bit
value.
14.2.8
DTC Vector Base Register (DTCVBR)
Address(es): DTC.DTCVBR 4000 5404h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Bit name
Description
R/W
b31 to b0
DTC Vector Base Address
Set the DTC Vector Base Address (lower 10 bits should be 0)
R/W
The DTCVBR sets the base address for calculating the DTC vector table address, which can be set in the range of 0000
0000h to FFFF FFFFh (4-GB) in 1-KB units.
14.2.9
DTC Module Start Register (DTCST)
Address(es): DTC.DTCST 4000 540Ch
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
DTCST
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DTCST
DTC Module Start
0: DTC module stop
1: DTC module start.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
DTCST bit (DTC Module Start)
Set the DTCST bit to 1 to enable the DTC to accept transfer requests. When this bit is set to 0, transfer requests are no
longer accepted. If this bit is set to 0 during a data transfer, the accepted transfer request is active until the processing
completes.
The DTCST bit must be set to 0 before making a transition to the module-stop state or Software Standby mode without
Snooze mode transition.
For details on these transitions, see section 14.10, Module-Stop Function, and section 10, Low Power Modes.
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14.2.10
14. Data Transfer Controller (DTC)
DTC Status Register (DTCSTS)
Address(es): DTC.DTCSTS 4000 540Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
ACT
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
VECN[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
VECN[7:0]
DTC-Activating Vector
Number Monitoring
These bits indicate the vector number for the activation source
when a DTC transfer is in progress.
The value is only valid if a DTC transfer is in progress (the value of
the ACT flag is 1).
R
b14 to b8
—
Reserved
These bits are read as 0. Writing to these bits has no effect.
R
b15
ACT
DTC Active Flag
0: DTC transfer operation is not in progress
1: DTC transfer operation is in progress.
R
VECN[7:0] bits (DTC-Activating Vector Number Monitoring)
While transfer by the DTC is in progress, these bits indicate the vector number associated with the activation source for
the transfer. The value read from the VECN[7:0] bits is valid if the value of the ACT flag is 1, indicating a DTC transfer
in progress, and invalid if the value of the ACT flag is 0, indicating no DTC transfer is in progress.
ACT flag (DTC Active Flag)
This flag indicates the state of the DTC transfer operation.
[Setting condition]
When the DTC is activated by a transfer request.
[Clearing condition]
When transfer by the DTC, in response to a transfer request, is complete.
14.3
Activation Sources
The DTC is activated by an interrupt request. Setting the ICU.IELSRn.DTCE bit of the ICU to 1 enables activation of the
DTC by the associated interrupt. The number of selector output n by ICU.IELSR is defined as the interrupt vector
number, where n = 0 to 31. For an enabled interrupt, the specific DTC interrupt source associated with each interrupt
vector number n is selected by ICU.IELSRn.IELS[7:0], where n = 0 to 31.
For the setup of ICU.IELSRn.IELS[7:0] (n = 0 to 31), see Table 12.4, Event table in section 12, Interrupt Controller Unit
(ICU). For activation by software, see section 15.2.2, Event Link Software Event Generation Register n (ELSEGRn) (n =
0, 1).
The interrupt vector number is equivalent to the DTC vector table number. After the DTC accepts an activation request,
it does not accept another activation request until transfer for that single request completes, regardless of the priority of
the requests. When multiple activation requests are generated during a DTC transfer, a request with the highest priority
on completion of the transfer is accepted. When multiple activation requests are generated while the DTC module start
bit (DTCST.DTCST) is 0, the DTC accepts the request with the highest priority at the time when the bit is subsequently
set to 1. The small interrupt vector number has high priority.
The DTC performs the following operations at the start of a single data transfer, or for a chain transfer, after the last of
the consecutive transfers:
On completion of a specified round of data transfer, the ICU.IELSRn.DTCE bit is set to 0, and an interrupt request
is sent to the CPU
If the MRB.DISEL bit is 1, an interrupt request is sent to the CPU on completion of a data transfer
For other transfers, the ICU.IELSRn.IR bit of the activation source is set to 0 at the start of the data transfer.
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14.3.1
14. Data Transfer Controller (DTC)
Allocating Transfer Information and DTC Vector Table
The DTC reads the start address of the transfer information associated with each activation source from the vector table
and reads the transfer information starting at that address.
The vector table must be located so that the lower 10 bits of the base address (start address) are 0. Use the DTC Vector
Base Register (DTCVBR) to set the base address of the DTC vector table. Transfer information is allocated in the SRAM
area. In the SRAM area, the start address of the transfer information n with vector number n must be 4n added to the base
address in the vector table.
Figure 14.2 shows the relationship between the DTC vector table and transfer information. Figure 14.3 shows the
allocation of transfer information in the SRAM area.
Upper: DTCVBR
Lower: Vector number 4
DTC vector table
Transfer information (1)
DTC vector address
Transfer information (1)
start address
+4
Transfer information (2)
start address
Transfer information (2)
:
:
:
+4(n-1)
Transfer information (n)
start address
:
:
:
4 bytes
Transfer information (n)
4 bytes
Figure 14.2
DTC vector table and transfer information
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14. Data Transfer Controller (DTC)
Allocation of transfer information
Lower address
Start address
3
2
1
MRA
MRB
0
Reserved (0)
Transfer information
per transfer
(4 words (16 bytes))
SAR
DAR
Chain
transfer
CRA
MRA
CRB
MRB
Reserved (0)
Transfer information for
the second transfer in
chain transfer mode
(4 words (16 bytes))
SAR
DAR
CRA
CRB
4 bytes
Figure 14.3
14.4
Allocation of transfer information in the SRAM area
Operation
The DTC transfers data according to the transfer information. Storage of the transfer information in the SRAM area is
required before a DTC operation. When the DTC is activated, it reads the DTC vector associated with the vector number.
The DTC reads the transfer information from the transfer information store address referenced by the DTC vector then
transfers the data. After the data transfer, the DTC writes back the transfer information. Storing the transfer information
in the SRAM area allows data transfer of any number of channels.
There are three transfer modes:
Normal transfer mode
Repeat transfer mode
Block transfer mode.
The DTC specifies a transfer source address in the SAR register and a transfer destination address in the DAR register.
The values of these registers are incremented, decremented, or address-fixed independently after the data transfer.
Table 14.2 lists the DTC transfer modes.
Table 14.2
DTC transfer modes
Transfer mode
Data size transferred on single transfer
request
Increment or decrement of
memory address
Settable transfer
count
Normal transfer mode
1 byte (8 bit), 1 halfword (16 bit), 1 word (32 bit)
Incremented/decremented by
1, 2, or 4 or address fixed
1 to 65536
Repeat transfer mode*1
1 byte (8 bit), 1 halfword (16 bit), 1 word (32 bit)
Incremented/decremented by
1, 2, or 4 or address fixed
1 to 256*3
Block transfer mode*2
Block size specified in CRAH
(1 to 256 bytes, 1 to 256 halfwords (2 to 512
bytes), 1 to 256 words (4 to 1024 bytes))
Incremented/decremented by
1, 2, or 4 or address fixed
1 to 65536
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14. Data Transfer Controller (DTC)
Note 1. Set the transfer source or transfer destination as the repeat area.
Note 2. Set the transfer source or transfer destination as the block area.
Note 3. After a data transfer of the specified count, the initial state is restored and operation restarts.
Setting the MRB.CHNE bit to 1 allows multiple transfers or chain transfer on a single activation source. It also enables a
chain transfer when the specified data transfer is complete.
Figure 14.4 shows the operation flowchart of the DTC. Table 14.3 lists the chain transfer conditions. The combination of
control information for the second and subsequent transfers are omitted in this table.
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14. Data Transfer Controller (DTC)
Start
Match and
RRS bit = 1
Compare vector
numbers. Match?
Mismatch or RRS bit = 0
Read DTC vector
Next transfer
Read transfer
information
Update transfer
information start address
Yes
CHNE bit = 1?
Yes
No
CHNS bit = 0
No
Yes
MD[1:0] bits = 01b?
(Repeat transfer mode?)
No
Last data transfer?
(Transfer counter = 1?)*1
Yes
Last data transfer?
(Transfer counter = 1?)*1
No
Yes
No
Yes
DISEL bit = 1?
No
Clear the ICU.IELSRn.IR
bit
Transfer data
Transfer data
Transfer data
Transfer data
Write transfer information
Write transfer information
Write transfer information
Write transfer information
Clear the ICU.IELSRn.DTCE bit.
An interrupt to the CPU is
generated
End
Figure 14.4
An interrupt to the CPU
is generated
Note 1. Counter value before starting data transfer.
DTC operation flowchart
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Table 14.3
14. Data Transfer Controller (DTC)
Chain transfer conditions
Second transfer*3
First transfer
CHNE
bit
CHNS
bit
DISEL
bit
Transfer
counter*1,*2
CHNE
bit
CHNS
bit
DISEL
bit
Transfer
counter*1,*2
0
—
0
Other than (1 → 0)
—
—
—
—
Ends after the first
transfer
0
—
0
(1 → 0)
—
—
—
—
0
—
1
—
—
—
—
—
Ends after the first
transfer with an interrupt
request to the CPU
1
0
—
—
0
—
0
Other than (1 → 0)
Ends after the second
transfer
0
—
0
(1 → 0)
0
—
1
—
Ends after the second
transfer with an interrupt
request to the CPU
DTC transfer
1
1
0
Other than (1 → *)
—
—
—
—
Ends after the first
transfer
1
1
—
(1 → *)
0
—
0
Other than (1 → 0)
Ends after the second
transfer
0
—
0
(1 → 0)
0
—
1
—
Ends after the second
transfer with an interrupt
request to the CPU
—
—
—
—
1
1
1
Other than (1 → *)
Ends after the first
transfer with an interrupt
request to the CPU
Note 1. The transfer counters used depend on the transfer modes as follows:
Normal transfer mode — CRA register
Repeat transfer mode — CRAL register
Block transfer mode — CRB register
Note 2. On completion of a data transfer, the counters operate as follows:
1 → 0 in normal and block transfer modes
1 → CRAH in repeat transfer mode
(1 → *) in the table indicates both of these two operations, depending on the mode.
Note 3. Chain transfer can be selected for the second or subsequent transfers. The conditions for the combination of the
second transfer and CHNE bit = 1 is omitted.
14.4.1
Transfer Information Read Skip Function
Reading of vector addresses and transfer information can be skipped through the setting in the DTCCR.RRS bit. When a
DTC activation request is generated, the current DTC vector number is compared with the DTC vector number in the
previous activation process. When these vector numbers match and the RRS bit is set to 1, DTC data transfer is
performed without reading the vector address and transfer information. However, when the previous transfer is a chain
transfer, the vector address and transfer information are read. Additionally, when the transfer counter (CRA register)
becomes 0 during the previous normal transfer, and when the transfer counter (CRB register) becomes 0 during the
previous block transfer, transfer information is read regardless of the value of the RRS bit. Figure 14.12 shows an
example of a transfer information read skip.
To update the vector table and transfer information, set the RRS bit to 0, update the vector table and transfer information,
then set the RRS bit to 1. The retained vector number is discarded by setting the RRS bit to 0. The updated DTC vector
table and transfer information are read in the next activation process.
14.4.2
Transfer Information Write-Back Skip Function
When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to address fixed, a part of the transfer information is not
written back. Table 14.4 lists the transfer information write-back skip conditions and associated registers. The CRA and
CRB registers are written back, and the write-back of the MRA and MRB registers is skipped.
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Table 14.4
14. Data Transfer Controller (DTC)
Transfer information write-back skip conditions and associated registers
MRA.SM[1:0] bits
MRB.DM[1:0] bits
b3
b2
b3
b2
SAR register
DAR register
0
0
0
0
Skip
Skip
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
Skip
Write-back
0
0
1
1
0
1
1
0
0
1
1
1
1
0
0
0
Write-back
Skip
1
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
Write-back
Write-back
1
0
1
1
1
1
1
0
1
1
1
1
14.4.3
Normal Transfer Mode
This mode allows a 1-byte (8 bit), 1-halfword (16 bit), 1-word (32 bit) data transfer on a single activation source. The
transfer count can be set to 1 to 65536. Transfer source addresses and transfer destination addresses can be independently
set to increment, decrement, or fixed. This mode enables an interrupt request to the CPU to be generated at the end of a
specified-count transfer.
Table 14.5 lists register functions in normal transfer mode, and Figure 14.5 shows the memory map of normal transfer
mode.
Table 14.5
Register functions in normal transfer mode
Register
Description
Value written back by writing transfer information
SAR
Transfer source address
Increment, decrement, or fixed*1
DAR
Transfer destination address
Increment, decrement, fixed*1
CRA
Transfer counter A
CRA - 1
CRB
Transfer counter B
Not updated
Note 1. Write-back operation is skipped in address-fixed mode.
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14. Data Transfer Controller (DTC)
Transfer destination data area
Transfer source data area
SAR
Data 1
Data 2
Figure 14.5
14.4.4
Transfer 6
times
(transfer 1 data
per each event)
DAR
Data 1
Data 2
Data 3
Data 3
Data 4
Data 4
Data 5
Data 5
Data 6
Data 6
Memory map of normal transfer mode (MRA.SM[1:0] = 10b, MRB.DM[1:0] = 10b, CRA=0006h)
Repeat Transfer Mode
This mode allows a 1-byte, 1-halfword, or 1-word data transfer on a single activation source. Transfer source or transfer
destination for the repeat area must be specified in the MRB.DTS bit. The transfer count can be set from 1 to 256. When
the specified-count transfer is complete, the initial value of the address register specified in the repeat area is restored, the
initial value of the transfer counter is restored and transfer is repeated. The other address register is incremented or
decremented continuously or remains unchanged.
When the transfer counter CRAL decrements to 00h in repeat transfer mode, the CRAL value is updated to the value set
in the CRAH register. As a result, the transfer counter does not become 00h, which disables interrupt requests to the CPU
when the MRB.DISEL bit is set to 0. An interrupt request to the CPU is generated when the specified data transfer
completes.
Table 14.6 lists the register functions in repeat transfer mode, and Figure 14.6 shows the memory map of repeat transfer
mode.
Table 14.6
Register functions in repeat transfer mode
Value written back by writing transfer information
Register
Description
When CRAL is not 1
When CRAL is 1
SAR
Transfer source
address
Increment, decrement, fixed*1
When the MRB.DTS bit is 0
Increment, decrement, or fixed*1
When the MRB.DTS bit is 1
SAR register initial value
DAR
Transfer destination
address
Increment, decrement, or fixed*1
When the MRB.DTS bit is 0
DAR register initial value
When the MRB.DTS bit is 1
Increment/decrement/fixed*1
CRAH
Retains transfer
counter
CRAH
CRAH
CRAL
Transfer counter A
CRAL - 1
CRAH
CRB
Transfer counter B
Not updated
Not updated
Note 1. Write-back is skipped in address-fixed mode.
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14. Data Transfer Controller (DTC)
Transfer destination data area
Transfer source data area
(set to repeat area)
SAR
Data 1
Data 2
Transfer 8
times
(transfer 1 data
per each event)
Data 1
DAR
Data 2
Data 3
Data 3
Data 4
Data 4
Data 1
Data 2
Data 3
Data 4
Figure 14.6
14.4.5
Memory map of repeat transfer mode when the transfer source is a repeat area (MRA.SM[1:0] =
10b, MRB.DM[1:0] =10b, CRAH=04h)
Block Transfer Mode
This mode allows single-block data transfer on a single activation source. Transfer source or transfer destination for the
block area must be specified in the MRB.DTS bit. The block size can be set from 1 to 256 bytes, 1 to 256 halfwords (2 to
512 bytes), or 1 to 256 words (4 to 1024 bytes). When transfer of the specified block is complete, the initial values of the
block size counter CRAL and the address register (the SAR register when the MRB.DTS bit = 1 or the DAR register
when the DTS bit = 0) specified in the block area are restored. The other address register is incremented or decremented
continuously or remains unchanged.
The transfer count (block count) can be set from 1 to 65536. This mode enables an interrupt request to the CPU to be
generated at the end of the specified-count block transfer.
Table 14.7 lists the register functions in block transfer mode, and Figure 14.7 shows a memory map for block transfer
mode.
Table 14.7
Register functions in block transfer mode
Register
Description
Value written back by writing transfer information
SAR
Transfer source address
(When MRB.DTS bit is 0)
Increment, decrement, or fixed*1
(When MRB.DTS bit is 1)
SAR register initial value
DAR
Transfer destination address
(When MRB.DTS bit is 0)
DAR register initial value
(When MRB.DTS bit is 1)
Incremen, decrement, or fixed*1
CRAH
Retains block size
CRAH
CRAL
Block size counter
CRAH
CRB
Block transfer counter
CRB - 1
Note 1. Write-back is skipped in address-fixed mode.
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14. Data Transfer Controller (DTC)
Transfer source data area
SAR
First block
Transfer destination data area
(set to block area)
Transfer
Block area
DAR
nth block
Figure 14.7
14.4.6
Memory map of block transfer mode
Chain Transfer
Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single activation source. If the
MRB.CHNE is set to 1 and CHNS to 0, an interrupt request to the CPU is not generated on completion of the specified
number of rounds of transfer or by setting the MRB.DISEL bit to 1. An interrupt request is sent to the CPU each time
DTC data transfer is performed. Data transfer has no effect on the ICU.IELSRn.IR bit of the activation source.
The SAR, DAR, CRA, CRB, MRA, and MRB registers can be set independently of each other to define the data transfer.
Figure 14.8 shows a chain transfer operation.
Data area
Transfer source data (1)
DTC vector table
Transfer information
allocated in the RAM
Transfer destination data (1)
DTC vector
address
Transfer information start
address
Transfer information
CHNE bit = 1
Transfer information
CHNE bit = 0
Transfer source data (2)
Transfer destination data (2)
Figure 14.8
Chain transfer operation
Writing 1 to the MRB.CHNE and CHNS bits enables chain transfer to be performed only after completion of the
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14. Data Transfer Controller (DTC)
specified data transfer. In repeat transfer mode, chain transfer is performed after completion of the specified data transfer.
For details on chain transfer conditions, see Table 14.3, Chain transfer conditions.
14.4.7
Operation Timing
Figure 14.9 to Figure 14.12 are timing diagrams that show the minimum number of execution cycles.
System clock
ICU.IELSRn.IR
DTC activation request
DTC access
R
Vector read Transfer information
read
Figure 14.9
W
Data
Transfer information
transfer
write
Example (1) of DTC operation timing in normal transfer and repeat transfer modes
System clock
ICU.IELSRn.IR
DTC activation request
DTC access
Vector read
Figure 14.10
Transfer information
read
Data transfer
Transfer information
write
Example (2) of DTC operation timing in block transfer mode when the block size = 4)
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System clock
ICU.IELSRn.IR
DTC activation request
DTC access
R
Vector read Transfer information
read
Figure 14.11
W
Data
transfer
R
Transfer
information
write
Transfer information
read
W
Data
transfer
Transfer
information
write
Example (3) of DTC operation timing for chain transfer
System clock
ICU.IELSRn.IR
(2)
(1)
DTC activation request
Read skip enable
R
DTC access
Vector read Transfer information
read
W
Data Transfer information
write
transfer
RR
W
Data Transfer information
transfer
write
Note: When activation sources (vector numbers) of (1) and (2) are the same and the RRS bit = 1, the transfer information read for request
(2) is skipped.
Figure 14.12
Example of operation when a transfer data read skip is executed with the vector, transfer data,
and transfer destination data on the SRAM, and the transfer source data on the peripheral module
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14.4.8
14. Data Transfer Controller (DTC)
Execution Cycles of DTC
Table 14.8 lists the execution cycles of single data transfer of the DTC.
For the order of the execution states, see section 14.4.7, Operation Timing.
Table 14.8
Execution cycles of DTC
Data transfer
Transfer information write
Read
Write
Internal
operation
3 × Ci+1*2
Cr + 1
Cw + 1
2
Repeat
Cr + 1
Cw + 1
Block*5
P × Cr
P × Cw
Transfer
Mode
Vector read
Normal
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Cv + 1
0*1
Transfer information read
4 × Ci + 1
0*1
2 × Ci+1*3 Ci*4
0*1
When transfer information read is skipped.
When neither SAR nor DAR is set to address-fixed mode.
When SAR or DAR is set to address-fixed mode.
When SAR and DAR are set to address-fixed mode.
When the block size is 2 or more. If the block size is 1, the cycle number for normal transfer is applied.
P: Block size (initial settings of CRAH and CRAL)
Cv: Cycles for access to vector transfer information storage destination
Ci: Cycles for access to transfer information storage destination address
Cr: Cycles for access to data read destination
Cw: Cycles for access to data write destination
The unit is system clocks (ICLK) for “+ 1” in the Vector read, Transfer information read, and Data transfer read columns and “2” in
the Internal operation column.
Cv, Ci, Cr, and Cw vary depending on the corresponding access destination. For the number of cycles for respective access
destinations, see section 36, SRAM and section 37, Flash Memory.
The frequency ratio of the system clock and peripheral clock is also taken into consideration.
The DTC response time is the time from when the DTC activation source is detected until DTC transfer starts.
Table 14.8 does not include the time until DTC data transfer starts after the DTC activation source becomes active.
14.4.9
DTC Bus Mastership Release Timing
The DTC does not release the bus mastership during transfer data read. Before the transfer data is read or written, the bus
is arbitrated according to the priority determined by the bus master arbitrator. For bus arbitration, see section 13, Buses.
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14.5
14. Data Transfer Controller (DTC)
DTC Setting Procedure
Before using the DTC, set the DTC Vector Base Register (DTCVBR). Figure 14.13 shows the procedure to set the DTC.
Start
Set the ICU.IELSRn.IELS[7:0] bits to 0 to disable the interrupt in
the NVIC and provide the following settings.
Set the DTCCR.RRS bit to 0
[1]
Set transfer information
(MRA, MRB, SAR, DAR, CRA, and CRB)
[2]
Set transfer information start addresses in
the DTC vector table
[3]
Set the DTCCR.RRS bit to 1
[4]
Set the ICU.IELSRn.DTCE bit to 1.
Set the ICU.IELSRn.IELS as interrupt source.
The interrupt should be enabled in the NVIC.
Set the enable bit for
an activation source interrupt
[5]
[6]
[1] Set the DTCCR.RRS bit to 0 to reset the transfer information
read skip flag. After that, the transfer information read is not
skipped while the DTC is activated. You must make this
setting when the transfer information is updated.
[2] Allocate transfer information (MRA, MRB, SAR, DAR, CRA,
and CRB) in the data area. For setting transfer information,
see section 14.2, Register Descriptions. For how to allocate
transfer information, see section 14.3.1, Allocating Transfer
Information and DTC Vector Table.
[3] Set the transfer information start addresses in the DTC vector
table. For how to set the DTC vector table, see section
14.3.1, Allocating Transfer Information and DTC Vector Table.
[4] Set the DTCCR.RRS bit to 1 to enable skipping of the second
and subsequent transfer information read cycles for
continuous DTC activation from the same interrupt source.
The RRS bit can be set to 1, but if this is set during DTC
transfer, it becomes valid from the next transfer.
[5] Set the ICU.IELSRn.DTCE bit to 1. Set ICU.IELSRn.IELS as
interrupt sources that trigger DTC. The interrupt must be
enabled in the NVIC. See the Table 12.4, Event table.
[6] Set the enable bit for the activation source interrupts to 1.
When a source interrupt is generated, the DTC is activated.
For the setting of the interrupt source enable bit, see the
setting for the modules that are to be the activation sources.
Setting for each activation
source
Common setting
for DTC
[7] Set the DTC module start bit (DTCST.DTCST) to 1.
Set the DTCST.DTCST bit to 1
[7]
Note:
End
Figure 14.13
14.6
14.6.1
The DTCST.DTCST bit can be set even if the
setting for the activation sources are not
completed.
DTC setting procedure
Examples of DTC Usage
Normal Transfer
This section provides an example of DTC usage and its application in the reception of 128 bytes of data from an SCI.
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(1)
14. Data Transfer Controller (DTC)
Transfer information setting
In the MRA register, select a fixed source address (MRA.SM[1:0] bits = 00b), normal transfer mode (MRA.MD[1:0] bits
= 00b), and byte-sized transfer (MRA.SZ[1:0] bits = 00b). In the MRB register, specify incrementation of the destination
address (MRB.DM[1:0] bits = 10b) and single data transfer by a single interrupt (MRB.CHNE bit = 0 and MRB.DISEL
bit = 0). The MRB.DTS bit can be set to any value. Set the RDR register address of the SCI in the SAR register, the start
address of the SRAM area for data storage in the DAR register, and 128 (0080h) in the CRA register. The CRB register
can be set to any value.
(2)
DTC vector table setting
The start address of the transfer information for the RXI interrupt is set in the vector table for the DTC.
(3)
ICU setting and DTC module activation
Set the ICU.IELSRn.DTCE bit to 1 and set ICU.IELSRn.IELS as the SCI interrupt. The interrupt must be enabled in the
NVIC. Set the DTCST.DTCST bit to 1.
(4)
SCI setting
Enable the RXI interrupt by setting the SCR.RIE bit in the SCI to 1. If a reception error occurs during the SCI receive
operation, reception stops. To manage this, use settings that allow the CPU to accept receive error interrupts.
(5)
DTC transfer
Every time a reception of 1 byte by the SCI is complete, an RXI interrupt is generated to activate the DTC. The DTC
transfers the received byte from the RDR of the SCI to SRAM, after which the DAR register is incremented and the CRA
register is decremented.
(6)
Interrupt handling
After 128 rounds of data transfer are complete and the value in the CRA register becomes 0, an RXI interrupt request is
generated for the CPU. Complete the process in the handling routine for this interrupt.
14.6.2
Chain Transfer
This section provides an example of chain transfer by the DTC and describes its use in the output of pulses by the
General PWM Timer (GPT). You can use chain transfer to transfer PWM timer compare data and change the period of
the PWM timer for the GPT.
For the first of the chain transfers, normal transfer mode is specified for transfer to the GPTm.GTCCRC register (m =
320, 161 to 166). For the second transfer, normal transfer mode is specified for transfer to the GPTm.GTCCRE registers.
For the third transfer of the chained transfer, Normal Transfer mode for transfer to the GPTm.GTPBR registers is
specified. This is because clearing of the activation source and generation of an interrupt on completion of the specified
number of transfers are restricted to the third of the chain transfers, that is, transfers while MRB.CHNE bit = 0.
The following example shows how to use the counter overflow interrupt with the GPT320.GTPR register as an activating
source for the DTC.
(1)
First transfer information setting
Set up transfer to the GPT320.GTCCRC registers:
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] bits = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] bits = 00b) and word-sized transfer (MRA.SZ[1:0] bits =
10b).
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] bits = 00b) and set up chain transfer
(MRB.CHNE bit = 1 and MRB.CHNS bit = 0).
4. Set the SAR to the first address of the data table.
5. Set the DAR register to the address of the GPT320.GTCCRC register.
6. Set the CRAH and CRAL registers to the size of the data table. The CRB register can be set to any value.
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14. Data Transfer Controller (DTC)
Second transfer information setting
Set up for transfer to the GPT320.GTCCRE registers.
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] bits = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] bits = 00b) and word-sized transfer (MRA.SZ[1:0] bits =
10b).
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] bits = 00b) and set up chain transfer
(MRB.CHNE bit = 1, MRB.CHNS bit = 0).
4. Set the SAR register to the first address of the data table.
5. Set the DAR register to the address of the GPT320.GTCCRE register.
6. Set the CRAH and CRAL registers to the size of the data table. The CRB register can be set to any value.
(3)
Third transfer information set
Set up transfer to the GPT320.GTPBR registers.
1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] bits = 10b).
2. Set the transfer to normal transfer mode (MRA.MD[1:0] bits = 00b) and word-sized transfer (MRA.SZ[1:0] bits =
10b)
3. In the MRB register, select the destination address as fixed (MRB.DM[1:0] bits = 00b) and set up single data
transfer per interrupt (MRB.CHNE bit = 0, MRB.DISEL bit = 0). The MRB.DTS bit can be set to any value.
4. Set the SAR register to the first address of the data table.
5. Set the DAR register to the address of the GPT320.GTPBR registers.
6. Set the CRA register to the size of the data table. The CRB register can be set to any value.
(4)
Transfer information assignment
Place the transfer information for use in the transfer to the GPT320.GTPBR immediately after the transfer control
information for use in the GPT320.GTCCRC and GPT320.GTCCRE registers.
(5)
DTC vector table
In the DTC vector table, set the address where the transfer control information for use in transfer to the
GPT320.GTCCRC and GPT320.GTCCRE registers starts.
(6)
ICU setting and DTC module activation
1. Set the ICU.IELSRn.DTCE bit associated with the GPT320 counter overflow interrupt.
2. Set the ICU.IELSRn.IELS[7:0] bits to 70(46h) for the GPT320 counter overflow.
3. Set the DTCST.DTCST bit to 1.
(7)
GPT setting
1. Set the GPT320.GTIOR register so that the GTCCRA and GTCCRB registers operate as output compare registers.
2. Set the default PWM timer compare values in the GPT320.GTCCRA and GPT320.GTCCRB registers and the next
PWM timer compare values in the GPT320.GTCCRC and GPT320.GTCCRE registers.
3. Set the default PWM timer period values in the GPT320.GTPR register and the next PWM timer period values in
the GPT320.GTPBR register.
4. Set 1 to the output bit in PmnPFS.PDR, and set 00011b to the peripheral select bits in PmnPFS.PSEL[4:0].
(8)
GPT activation
Set the GPT320.GTSTR.CSTRT bits to 1 to start the GPT320.GTCNT counter.
(9)
DTC transfer
Every time a GPT320 counter overflow is generated with the GPT320.GTPR register, the next PWM timer compare
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14. Data Transfer Controller (DTC)
values are transferred to the GPT320.GTCCRC and GPT320.GTCCRE registers. The setting for the next PWM timer
period is transferred to the GPT320.GTPBR register.
(10) Interrupt handling
After the specified rounds of data transfer are complete, for example when the value in the CRA register for GPT transfer
becomes 0, a GPT320 counter overflow interrupt request is issued for the CPU. Complete the process for this interrupt in
the handling routine.
14.6.3
Chain Transfer when Counter = 0
The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and information
in the first data transfer is repeatedly changed in the second transfer. Chain transfer enables transfers to be repeated 256
times or more.
The following procedure shows an example of configuring a 128-KB input buffer, where the input buffer is set so that its
lower address starts with 0000h. Figure 14.14 shows a chain transfer when the counter = 0.
1. Set the normal transfer mode to input data for the first data transfer. Set the following:
a. Transfer source address = fixed.
b. CRA register = 0000h (65,536) times.
c. MRB.CHNE bit = 1 (chain transfer is enabled).
d. MRB.CHNS bit = 1 (chain transfer is performed only when the transfer counter is 0).
e. MRB.DISEL bit = 0 (an interrupt request to the CPU is generated when the specified data transfer completes).
2. Prepare the upper 8-bit address of the start address at every 65,536 times of the transfer destination address for the
first data transfer in different area such as the flash. For example, when setting the input buffer to 20 0000h to
21 FFFFh, prepare 21h and 20h.
3. For the second data transfer:
a. Set the repeat transfer mode (source side: repeat area) to reset the transfer destination address of the first data
transfer.
b. Specify the upper 8 bits of the DAR register in the first transfer information area for the transfer destination.
c. Set the MRB.CHNE bit = 0 (chain transfer is disabled).
d. Set the MRB.DISEL bit = 0 (an interrupt request to the CPU is generated when the specified data transfer
completes).
e. When setting the input buffer to 20 0000h to 21 FFFFh, also set the transfer counter to 2.
4. The first data transfer is performed by an interrupt 65,536 times. When the transfer counter of the first data transfer
becomes 0, the second data transfer starts. Set the upper 8 bits of the transfer source address of the first data transfer
to 21h. The lower 16 bits of the transfer destination address and the transfer counter of the first data transfer is
0000h.
5. In succession, the first data transfer is performed by an interrupt 65,536 times as specified for the first data transfer.
When the transfer counter of the first data transfer becomes 0, the second data transfer starts. Set the upper 8 bits of
the transfer source address of the first data transfer to 20h. The lower 16 bits of the transfer destination address and
the transfer counter of the first data transfer is 0000h.
6. Steps 4 and 5 are repeated indefinitely. Because the second data transfer is in repeat transfer mode, no interrupt
request to the CPU is generated.
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14. Data Transfer Controller (DTC)
Input circuit
Transfer information allocated in
the on-chip memory space
Input buffer
First data transfer
transfer information
Chain transfer
(counter = 0)
Second data transfer
transfer information
Upper 8 bits of DAR
Figure 14.14
14.7
Chain transfer when counter = 0
Interrupt Source
When the DTC completes data transfer of the specified count or when data transfer with the MRB.DISEL set to 1 is
complete, a DTC activation source generates an interrupt to the CPU. Interrupts to the CPU are controlled according to
the settings in the NVIC and ICU.IELSRn.IELS[7:0] bits. See section 12, Interrupt Controller Unit (ICU). For priority of
DTC activation source, the small interrupt vector number is of high priority. The priority of interrupts to the CPU is
determined by the NVIC priority.
14.8
Event Link
The DTC is capable of producing an event link request on completion of one transfer request.
14.9
Snooze Control Interface
To return to Software Standby mode from Snooze mode through the DTC, set the SYSTEM.SNZEDCR.DTCZRED or
SYSTEM.SNZEDCR.DTCNZRED bit to 1. See section 10.8.3, Return to Software Standby Mode.
SYSTEM.SNZEDCR.DTCZRED enables or disables a snooze end request on completion of the last DTC transmission,
detected on DTC transmission completion of CRA and CRB are 0.
SYSTEM.SNZEDCR.DTCNZRED enables or disables a snooze end request on a not last DTC transmission completion,
detected on DTC transmission completion of CRA and CRB are not 0.
14.10 Module-Stop Function
Before transitioning to the module-stop function or Software Standby mode without Snooze mode transition, set the
DTCST.DTCST bit to 0, then see information described in the following sections. The DTC is available in Snooze mode
by setting the SYSTEM.SNZCR.SNZDTCEN bit to 1. See section 10, Low Power Modes.
(1)
Module-stop function
Writing 1 to the MSTPCRA.MSTPA22 bit enables the module-stop function of the DTC. If the DTC transfer is in
progress at the time, 1 is written to the MSTPCRA.MSTPA22 bit. The transition to the module-stop state proceeds after
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14. Data Transfer Controller (DTC)
DTC transfer ends. While the MSTPCRA.MSTPA22 bit is 1, accessing the DTC registers is prohibited.
Writing 0 to the MSTPCRA.MSTPA22 bit releases the DTC from the module-stop state.
(2)
Software Standby mode
Use the settings described in section 10.7.1, Transition to Software Standby Mode.
If DTC transfer operations are in progress at the time the WFI instruction is executed, the transition to Software Standby
mode follows the completion of the DTC transfer.
When the snooze control circuit receives a snooze request in Software Standby mode, the MCU transfers to Snooze
mode. See section 10.8.1, Transition to Snooze Mode. DTC operation in Snooze mode can be selected in the
SYSTEM.SNZCR.SNZDTCEN bit. If DTC operation is enabled in Snooze mode, before transitioning to Software
Standby mode, set the DTCST.DTCST bit to 1. To return to Software Standby mode through DTC, set
SYSTEM.SNZEDCR.DTCZRED or SYSTEM.SNZEDCR.DTCNZRED to 1. See section 10.8.3, Return to Software
Standby Mode. The DTC activation request from the ICU is stopped during Software Standby mode but not during
Snooze mode.
(3)
Constraints on module-stop function
For the WFI instruction and the register setting procedure, see section 10, Low Power Modes.
To perform a DTC transfer after returning from a low-power mode without Snooze mode transition, set the
DTCST.DTCST bit to 1 again.
To use a request that is generated in Software Standby mode as an interrupt request to the CPU but not as a DTC
activation request, specify the CPU as the interrupt request destination as described in section 12.4.2, Selecting Interrupt
Request Destinations, then execute the WFI instruction. If DTC operation is enabled in Snooze mode, do not use the
module-stop function of the DTC.
14.11 Usage Notes
14.11.1
Transfer Information Start Address
You must set multiples of 4 for the transfer information start addresses in the vector table. Otherwise, such addresses are
accessed with their lowest 2 bits regarded as 00b.
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15.
15.1
15. Event Link Controller (ELC)
Event Link Controller (ELC)
Overview
The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to
connect them to different modules, allowing direct link without CPU intervention.
Table 15.1 lists the ELC specifications and Figure 15.1 shows a block diagram of the ELC.
Table 15.1
ELC specifications
Parameter
Description
Event link function
108 types of event signals can be directly connected to modules. The ELC can generate
ELC event signal, and events that activate the DTC.
Module-stop function
Module-stop state can be set
Internal peripheral bus
ELC
ELSEGR0, 1
ELCR
ELSRn
DTC
Event control
PORT_IRQn
(n = 0 to 7)
GPT
DTC
ADC14
LVD
DAC12
SYSTEM_SNZREQ
Port 1/2
MOSC_STOP
CTSU
Peripheral module
Port 1/2
ELSEGR0,1:
ELCR:
ELSRn:
Figure 15.1
Event Link Software Event Generation Register
Event Link Control Register
Event Link Setting Register n
ELC block diagram when n = 0 to 3, 8, 9, 12, 14, 15, 18
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15.2
15. Event Link Controller (ELC)
Register Descriptions
15.2.1
Event Link Controller Register (ELCR)
Address(es): ELC.ELCR 4004 1000h
b7
b6
b5
b4
b3
b2
b1
b0
ELCON
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
ELCON
All Event Link Enable
0: ELC function disabled
1: ELC function enabled.
R/W
The ELCR register controls the ELC operation.
15.2.2
Event Link Software Event Generation Register n (ELSEGRn) (n = 0, 1)
Address(es): ELC.ELSEGR0 4004 1002h, ELC.ELSEGR1 4004 1004h
b7
b6
b5
b4
b3
b2
b1
b0
WI
WE
—
—
—
—
—
SEG
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
SEG
Software Event Generation
0: Normal operation
1: Software event is generated.
W
b5 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
WE
SEG Bit Write Enable
0: Write to SEG bit disabled
1: Write to SEG bit enabled.
R/W
b7
WI
ELSEGR Register Write Disable
0: Write to ELSEGR register enabled
1: Write to ELSEGR register disabled.
W
SEG bit (Software Event Generation)
When 1 is written to this bit while the WE bit is 1, a software event is generated. This bit is read as 0. When 1 is written
to this bit, data is not stored. The WE bit must be set to 1 before writing to this bit.
A software event can trigger a linked DTC event.
WE bit (SEG Bit Write Enable)
The SEG bit can only be written when the WE bit is 1. Clear the WI bit before writing to this bit.
[Setting condition]
If 1 is written to this bit while the WI bit is 0, this bit becomes 1.
[Clearing condition]
If 0 is written to this bit while the WI bit is 0, this bit becomes 0.
WI bit (ELSEGR Register Write Disable)
The ELSEGR register can only be written when the WI bit is 0. This bit is read as 1. The WI bit must be set to 0 before
setting the WE or SEG bit.
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15.2.3
15. Event Link Controller (ELC)
Event Link Setting Register n (ELSRn) *1
Address(es): ELC.ELSR0 4004 1010h, ELC.ELSR1 4004 1014h, ELC.ELSR2 4004 1018h, ELC.ELSR3 4004 101Ch, ELC.ELSR8 4004 1030h,
ELC.ELSR9 4004 1034h, ELC.ELSR12 4004 1040h, ELC.ELSR14 4004 1048h, ELC.ELSR15 4004 104Ch, ELC.ELSR18 4004 1058h
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
ELS[7:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
ELS[7:0]
Event Link Select
b7
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
b0
00000000: Event output disabled for the associated
peripheral module
00000001 to 10000110: Number setting for the event signal
to be linked.
Other settings are prohibited.
R/W
Note 1. n = 0 to 3, 8, 9, 12, 14, 15, 18
The ELSRn register specifies an event signal to be linked to for each peripheral module. Table 15.2 shows the association
between the ELSRn register and the peripheral modules. Table 15.3 shows the associations between the event signal
names set in the ELSRn register and the signal numbers.
Table 15.2
Associations between the ELSRn register and peripheral functions
Register name
Peripheral function (module)
Event name
ELSR0
GPT (A)
ELC_GPTA
ELSR1
GPT (B)
ELC_GPTB
ELSR2
GPT (C)
ELC_GPTC
ELSR3
GPT (D)
ELC_GPTD
ELSR8
ADC14A
ELC_AD00
ELSR9
ADC14B
ELC_AD01
ELSR12
DAC12
ELC_DA0
ELSR14
PORT 1
ELC_PORT1
ELSR15
PORT 2
ELC_PORT2
ELSR18
CTSU
ELC_CTSU
Table 15.3
Associations between event signal names set in ELSRn.ELS bits and signal numbers (1 of 4)
Event number
Interrupt request
source
Name
Description
01h
Port
PORT_IRQ0*1
External pin interrupt 0
02h
PORT_IRQ1*1
External pin interrupt 1
03h
PORT_IRQ2*1
External pin interrupt 2
04h
PORT_IRQ3*1
External pin interrupt 3
05h
PORT_IRQ4*1
External pin interrupt 4
06h
PORT_IRQ5*1
External pin interrupt 5
07h
PORT_IRQ6*1
External pin interrupt 6
08h
PORT_IRQ7*1
External pin interrupt 7
DTC_DTCEND*3
DTC transfer end
0Ah
DTC
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Table 15.3
15. Event Link Controller (ELC)
Associations between event signal names set in ELSRn.ELS bits and signal numbers (2 of 4)
Event number
Interrupt request
source
Name
Description
0Dh
LVD
LVD_LVD1
Voltage monitor 1 interrupt
LVD_LVD2
Voltage monitor 2 interrupt
0Eh
0Fh
MOSC
MOSC_STOP
Main clock oscillation stop
10h
Low Power Mode
SYSTEM_SNZREQ*2, *3
Snooze entry
11h
AGT0
AGT0_AGTI
AGT interrupt
12h
AGT0_AGTCMAI
Compare match A
13h
AGT0_AGTCMBI
Compare match B
AGT1_AGTI
AGT interrupt
14h
AGT1
15h
AGT1_AGTCMAI
Compare match A
16h
AGT1_AGTCMBI
Compare match B
17h
IWDT
IWDT_NMIUNDF
IWDT underflow
18h
WDT
WDT_NMIUNDF
WDT underflow
1Ah
RTC
RTC_PRD
Periodic interrupt
1Ch
ADC140
ADC140_ADI
A/D scan end interrupt
20h
ADC140_WCMPM*3
Compare match
21h
ADC140_WCMPUM*3
Compare mismatch
ACMPLP
ACMP_LP0
Low-power analog comparator interrupt 0
ACMP_LP1
Low-power analog comparator interrupt 1
IIC0
IIC0_RXI
Receive data full
27h
IIC0_TXI
Transmit data empty
28h
IIC0_TEI
Transmit end
29h
IIC0_EEI
Transfer error
22h
23h
26h
2Bh
IIC1_RXI
Receive data full
2Ch
IIC1
IIC1_TXI
Transmit data empty
2Dh
IIC1_TEI
Transmit end
2Eh
IIC1_EEI
Transfer error
33h
DOC
DOC_DOPCI*3
Data operation circuit interrupt
3Ch
I/O Ports
IOPORT_GROUP1
Port 1 event
IOPORT_GROUP2
Port 2 event
ELC_SWEVT0
Software event 0
ELC_SWEVT1
Software event 1
3Dh
3Eh
ELC
3Fh
42h
GPT0_CCMPA
Compare match A
43h
GPT0_CCMPB
Compare match B
44h
GPT0_CMPC
Compare match C
45h
GPT0_CMPD
Compare match D
46h
GPT0_OVF
Overflow
47h
GPT0_UDF
Underflow
48h
GPT320
GPT1_CCMPA
Compare match A
49h
GPT161
GPT1_CCMPB
Compare match B
4Ah
GPT1_CMPC
Compare match C
4Bh
GPT1_CMPD
Compare match D
4Ch
GPT1_OVF
Overflow
4Dh
GPT1_UDF
Underflow
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Table 15.3
15. Event Link Controller (ELC)
Associations between event signal names set in ELSRn.ELS bits and signal numbers (3 of 4)
Event number
Interrupt request
source
Name
Description
4Eh
GPT162
GPT2_CCMPA
Compare match A
4Fh
GPT2_CCMPB
Compare match B
50h
GPT2_CMPC
Compare match C
51h
GPT2_CMPD
Compare match D
52h
GPT2_OVF
Overflow
GPT2_UDF
Underflow
GPT3_CCMPA
Compare match A
55h
GPT3_CCMPB
Compare match B
56h
GPT3_CMPC
Compare match C
57h
GPT3_CMPD
Compare match D
58h
GPT3_OVF
Overflow
GPT3_UDF
Underflow
GPT4_CCMPA
Compare match A
5Bh
GPT4_CCMPB
Compare match B
5Ch
GPT4_CMPC
Compare match C
5Dh
GPT4_CMPD
Compare match D
5Eh
GPT4_OVF
Overflow
GPT4_UDF
Underflow
GPT5_CCMPA
Compare match A
61h
GPT5_CCMPB
Compare match B
62h
GPT5_CMPC
Compare match C
63h
GPT5_CMPD
Compare match D
64h
GPT5_OVF
Overflow
65h
GPT5_UDF
Underflow
GPT6_CCMPA
Compare match A
53h
54h
GPT163
59h
5Ah
GPT164
5Fh
60h
66h
GPT165
GPT166
67h
GPT6_CCMPB
Compare match B
68h
GPT6_CMPC
Compare match C
69h
GPT6_CMPD
Compare match D
6Ah
GPT6_OVF
Overflow
6Bh
GPT6_UDF
Underflow
GPT
GPT_UVWEDGE
UVW edge event
SCI0
SCI0_RXI*4
Receive data full
6Eh
SCI0_TXI*4
Transmit data empty
6Fh
SCI0_TEI
Transmit end
70h
SCI0_ERI*4
Receive error
71h
SCI0_AM
Address match event
SCI1_RXI
Receive data full
74h
SCI1_TXI
Transmit data empty
75h
SCI1_TEI
Transmit end
76h
SCI1_ERI
Receive error
77h
SCI1_AM
Address match event
6Ch
6Dh
73h
SCI1
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Table 15.3
15. Event Link Controller (ELC)
Associations between event signal names set in ELSRn.ELS bits and signal numbers (4 of 4)
Event number
Interrupt request
source
Name
Description
78h
SCI9
SCI9_RXI
Receive data full
SCI9_TXI
Transmit data empty
79h
7Ah
SCI9_TEI
Transmit end
7Bh
SCI9_ERI
Receive error
7Ch
SCI9_AM
Address match event
7Dh
SPI0_SPRI
Receive buffer full
7Eh
SPI0
SPI0_SPTI
Transmit buffer empty
7Fh
SPI0_SPII
Idle
80h
SPI0_SPEI
Error
81h
SPI0_SPTEND
Transmission completed event
SPI1_SPRI
Receive buffer full
83h
SPI1_SPTI
Transmit buffer empty
84h
SPI1_SPII
Idle
85h
SPI1_SPEI
Error
86h
SPI1_SPTEND
Transmission completed event
82h
Note 1.
Note 2.
Note 3.
Note 4.
SPI1
Only pulse (edge detection) is supported.
ELSR8, 9, 14, 15, and ELSR18 can select this event.
This event can occur in Snooze mode.
This event is not supported in FIFO mode.
15.3
Operation
15.3.1
Relation between Interrupt Handling and Event Linking
Event number for an event link is the same as that for the associated interrupt source. For information on generating
event signals, see the explanation in the chapter for each event source module.
15.3.2
Linking Events
When an event occurs and that event is already set as a trigger in the Event Link Setting Register (ELSRn), the associated
module is activated. The operation of the module must be set up in advance. Table 15.4 lists the operations of modules
when an event occurs.
Table 15.4
Module operations when event occurs
Module
Operations when event occurs
GPT
ADC14
Starts A/D conversion
DAC12
Starts D/A conversion
I/O Ports
Change pin output based on the EORR (reset) or EOSR (set)
Latch pin state to EIDR
The following ports can be used for the ELC:
PORT 1
PORT 2.
CTSU
Starts measurement operation
DTC
Starts DTC data transfer
Start counting
Stop counting
Clear counting
Up counting
Down counting
Input capture.
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15.3.3
15. Event Link Controller (ELC)
Example Procedure for Linking Events
To link events:
1. Set the operation of the module for which an event is to be linked.
2. Set the appropriate ELSRn register for the module to be linked.
3. Set the ELCR.ELCON bit to 1 to enable linkage of all events.
4. Configure the module from which an event is output and activate the module. The link between the two modules is
now active.
To stop event linkage of independent modules, set 00000000b in the ELSRn.ELS[7:0] bits associated with the modules.
To stop linkage of all events, set the ELCR.ELCON bit to 0.
If the event link output from the RTC is to be used, set the ELC after the RTC, such as for initialization and time setting.
Unintended events can be generated if the RTC settings are made after the ELC settings.
15.4
Usage Notes
15.4.1
Linking DTC Transfer End Signals as Events
When linking the DTC transfer end signals as events, do not set the same peripheral module as the DTC transfer
destination and event link destination. If set, the peripheral module might be started before DTC transfer to the peripheral
module is complete.
15.4.2
Setting the Clocks
To link events, you must enable the ELC and the related modules. The modules cannot operate if the related modules are
in the module-stop state or in the specific low power mode in which the module is stopped (Software Standby mode).
Some modules can perform in Snooze mode. For more information, see Table 15.3 and section 10, Low Power Modes.
15.4.3
Module Stop Function Setting
ELC operation can be disabled or enabled using the Module Stop Control Register C (MSTPCRC). After a reset, the
ELC is disabled. The ELCON bit must be set to 0 before ELC operation is disabled using the Module Stop Control
Register. For more information, see Table 15.3 and section 10, Low Power Modes.
15.4.4
ELC Delay Time
In Figure 15.2, module A uses ELC and accesses module B through the ELC. There is a delay time in the ELC between
module A and module B. See Table 15.5.
If the clock domains on both module A and B are the same, the delay time is 0. However, if the clock domains are
different, the ELC has some delays. The delay time is defined by the slower clock frequency between module A and
module B.
Delay time
Event source
Event destination
Module A
Module B
Clock = clock_A
Figure 15.2
ELC
Clock = clock_B
ELC delay time
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Table 15.5
15. Event Link Controller (ELC)
ELC delay time
Clock domain
Clock frequency
ELC delay time
clock_A = clock_B
clock_A = clock_B
0 cycle
clock_A clock_B
clock_A = clock_B
1 cycle to 2 cycles
clock_A > clock_B
1 cycle to 2 cycles of B
clock_A < clock_B
1 cycle to 2 cycles of A
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16.
I/O Ports
16.1
Overview
16. I/O Ports
The pins of the I/O Ports operate as general I/O port pins, I/O pins for peripheral modules, interrupt input pins, analog
I/O, or port group function for ELC.
All pins operate as input pins immediately after a reset, and pin functions are switched by register settings. The setting of
each pin is specified by the registers for the corresponding I/O Ports and peripheral modules.
Figure 16.1 shows the I/O Ports registers connection diagram.
PCR
Peripheral output
enable
1
PDR
0
DSCR, NCODR
Peripheral output
1
0
EOSR
POSR
ELC
Internal peripheral bus
PODR
PORR
EORR
PSEL
PMR
Edge detect
ELC
EOF, EOR
Peripheral input/
interrupt
EIDR
PIDR
Read control
ISEL
ASEL
Analog
input or output
Figure 16.1
Note:
I/O Ports Registers connection diagram
This figure shows a basic configuration of ports. The configuration differs partially depending on ports.
The configuration of the I/O Ports differ depending on the package. Table 16.1 shows the specifications of I/O Ports, and
Table 16.2 lists the port functions.
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Table 16.1
16. I/O Ports
Specifications of I/O Ports
Package
Package
Number
of pins
Port
64 pins
48 pins
PORT0
P000 to P004, P010
to P015
11 P000 to P002,
P010 to P015
PORT1
P100 to P113
14 P100 to P104,
P108 to P112
PORT2
P200, P201, P204 to
P206, P212 to P215
9 P200, P201,
P206, P212 to
P215
PORT3
P300 to P304
PORT4
PORT5
Package
Number
of pins
Package
Number
of pins
40 pins
8 P000, P010 to
P015
7
10 P100 to P103,
P108 to P112
9
7 P200, P201, P212
to P215
6 P200, P201,
P212 to P215
6
5 P300 to P302
3 P300, P301
2 P300
1
P400 to P403, P407
to P411
9 P400, P401,
P407 to P409
5 P400, P407, P408
3 P400, P407
2
P500 to P502
3 P500
1 N/A
0 N/A
0
Total of pins
Table 16.2
51
Total of pins
9 P000, P001, P010
to P015
Number
of pins
36 pins
10 P100 to P104,
P108 to P112
35
Total of pins
29
Total of pins
Functions of I/O Ports
Port
Port Name
Open Drain
Output
Function
Input Pull-up
Function
Drive Capacity
Switching
5-V Tolerant
PORT0
P000 to P004, P010 to P015
—
low/middle
—
PORT1
P100, P101, P104, P109, P110,
P112
low/middle
—
P102, P103, P105 to P108,
P111, P113
—
low/middle
—
P200, P214, P215
—
—
—
—
P201
—
low/middle
—
P204
low/middle
—
P205, P206
low/middle
PORT2
P212, P213
—
—
PORT3
P300 to P304
—
low/middle
—
PORT4
P400, P401, P407
low/middle
P402, P408 to P411
low/middle
—
P403
—
low/middle
—
P500 to P502
—
low/middle
—
PORT5
25
: Available
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16.2
16. I/O Ports
Register Descriptions
16.2.1
Port Control Register 1 (PCNTR1/PODR/PDR)
Address(es): PORT0.PCNTR1 4004 0000h, PORT1.PCNTR1 4004 0020h, PORT2.PCNTR1 4004 0040h, PORT3.PCNTR1 4004 0060h,
PORT4.PCNTR1 4004 0080h, PORT5.PCNTR1 4004 00A0h
PORT0.PODR 4004 0000h, PORT1.PODR 4004 0020h, PORT2.PODR 4004 0040h, PORT3.PODR 4004 0060h,
PORT4.PODR 4004 0080h, PORT5.PODR 4004 00A0h
PORT0.PDR 4004 0002h, PORT1.PDR 4004 0022h, PORT2.PDR 4004 0042h, PORT3.PDR 4004 0062h, PORT4.PDR 4004 0082h,
PORT5.PDR 4004 00A2h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR PODR
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PDR15 PDR14 PDR13 PDR12 PDR11 PDR10 PDR09 PDR08 PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
PDRn
Pmn Direction
0: Input (functions as an input pin)
1: Output (functions as an output pin).
R/W
b31 to b16
PODRn
Pmn Output Data
0: Low output
1: High output.
R/W
m = 0 to 5
n = 00 to 15
The Port Control Register 1 (PCNTR1) is a 32-bit and 16-bit read/write register that controls the port direction and port
output data. PODR bits [31:16] in PCNTR1 and PDR bits [15:0] in PCNTR1 are accessed in 16-bit units.
The PDRn bit selects the input or output direction for individual pins on the associated port when the pins are configured
as general I/O pins. Each pin on port m is associated with a PORTm.PCNTR1.PDRn bit. I/O direction can be specified in
1-bit units. Bits associated with non-existent port m are reserved. When writing, write 1 as output to these bits. The bit of
a non-existent pin is also reserved. A reserved bit is read as 0. The write value should be 0. P200, P214, P215 are input
only, so PORT2.PCNTR1.b0, b14, b15 are reserved.
The PODRn bit holds data to be output from the pins used for general I/O. The bits of non-existent port m are reserved.
Write 0 to these bits. The bit of a non-existent pin is reserved. A reserved bit is read as 0. The write value should be 0. A
reserved bit is read as 0. P200, P214, P215 are input only, so PORT2.PCNTR1.PODR00, PODR14, and PODR15 bits are
reserved.
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16.2.2
16. I/O Ports
Port Control Register 2 (PCNTR2/EIDR/PIDR)
Address(es): PORT0.PCNTR2 4004 0004h, PORT1.PCNTR2 4004 0024h, PORT2.PCNTR2 4004 0044h, PORT3.PCNTR2 4004 0064h,
PORT4.PCNTR2 4004 0084h, PORT5.PCNTR2 4004 00A4h
PORT1.EIDR 4004 0024h, PORT2.EIDR 4004 0044h, PORT0.PIDR 4004 0006h, PORT1.PIDR 4004 0026h, PORT2.PIDR 4004 0046h,
PORT3.PIDR 4004 0066h, PORT4.PIDR 4004 0086h, PORT5.PIDR 4004 00A6h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
EIDR15 EIDR14 EIDR13 EIDR12 EIDR11 EIDR10 EIDR09 EIDR08 EIDR07 EIDR06 EIDR05 EIDR04 EIDR03 EIDR02 EIDR01 EIDR00
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PIDR15 PIDR14 PIDR13 PIDR12 PIDR11 PIDR10 PIDR09 PIDR08 PIDR07 PIDR06 PIDR05 PIDR04 PIDR03 PIDR02 PIDR01 PIDR00
Value after reset:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b15 to b0
PIDRn
Pmn State
0: Low level
1: High level.
R
b31 to b16
EIDRn
Port Event Input Data*1
When the ELC_PORTx occurs:
0: Low input
1: High input.
R
m = 0 to 5
n = 00 to 15
x = 1 and 2
Note 1. Supported for PORT1 and PORT2.
The Port Control Register 2 (PCNTR2) provides read access to the Pmn state and the port event input data in 32-bit or
16-bit access. PIDRn bits [15:0] in PCNTR2 and EIDRn bits [31:16] in PCNTR2 provide Pmn state and port event input
data respectively, and are accessed in 16-bit units. Bits associated with non-existent pins are reserved. Reserved bit is
read as undefined.
The PIDRn bits reflect the individual pin states of the port, regardless of the values set in PmnPFS.PMR and
PORTm.PCNTR1.PDRn. The state of the pin that is used for the I/O port function cannot be reflected in PIDRn when
one of the following functions is enabled:
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
Analog function (ASEL = 1)
Capacitive Touch Sensing Unit (CTSU)
USB 2.0 Full-Speed Module (USBFS).
The EIDRn bits latch the pin state when an ELC_PORTx signal occurs from the ELC. The pin states can only be input
into EIDRn when PmnPFS.PMR = 0 and PORTm.PCNTR1.PDRn = 0. When PmnPFS.ASEL bit is set to 1, the
associated pin state cannot be reflected in EIDRn.
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16.2.3
16. I/O Ports
Port Control Register 3 (PCNTR3/PORR/POSR)
Address(es): PORT0.PCNTR3 4004 0008h, PORT1.PCNTR3 4004 0028h, PORT2.PCNTR3 4004 0048h, PORT3.PCNTR3 4004 0068h,
PORT4.PCNTR3 4004 0088h, PORT5.PCNTR3 4004 00A8h
PORT0.PORR 4004 0008h, PORT1.PORR 4004 0028h, PORT2.PORR 4004 0048h, PORT3.PORR 4004 0068h,
PORT4.PORR 4004 0088h, PORT5.PORR 4004 00A8h, PORT0.POSR 4004 000Ah, PORT1.POSR 4004 002Ah,
PORT2.POSR 4004 004Ah, PORT3.POSR 4004 006Ah, PORT4.POSR 4004 008Ah, PORT5.POSR 4004 00AAh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR PORR
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Value after reset:
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
POSR
15
POSR
14
POSR
13
POSR
12
POSR
11
POSR
10
POSR
09
POSR
08
POSR
07
POSR
06
POSR
05
POSR
04
POSR
03
POSR
02
POSR
01
POSR
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
POSRn
Pmn Output Set
0: No affect to output
1: High output.
W
b31 to b16
PORRn
Pmn Output Reset
0: No affect to output
1: Low output.
W
m = 0 to 5
n = 00 to 15
Note:
Note:
When EORRn or EOSRn is set, writing to PODRn, PORRn, and POSRn is prohibited.
Do not set PORRn and POSRn at the same time.
The Port Control Register 3 (PCNTR3) is a 32-bit and 16-bit write register that controls the setting or resetting of the port
output data. PORR bits [31:16] in PCNTR3 and POSR bits [15:0] in PCNTR3 are accessed in 16-bit units.
The POSR bit changes the PODR based on POSR being set when a software write occurs. For example, for P100, when
PORT1.POSR00 = 1, PORT1.PODR00 outputs 1. The bits of non-existent port m are reserved. Write 0 to these bits. The
bit of non-existent pin is reserved. The write value should always be 0. P200, P214, and P215 are input only, so
PORT2.PCNTR3.b0, b14, and b15 are reserved.
The PORR bit changes the PODR based on PORR being reset when a software write occurs. For example, for P100,
when PORT1.PORR00 = 1, PORT1.PODR00 outputs 0. The bits of non-existent port m are reserved. Write 0 to these
bits. The bit of non-existent pin is reserved. The write value should always be 0. P200, P214 and P215 are input only, so
PORT2.PCNTR3.b16, b30, and b31 are reserved.
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16. I/O Ports
Port Control Register 4 (PCNTR4/EORR/EOSR)
Address(es): PORT1.PCNTR4 4004 002Ch, PORT2.PCNTR4 4004 004Ch
PORT1.EORR 4004 002Ch, PORT2.EORR 4004 004Ch
PORT1.EOSR 4004 002Eh, PORT2.EOSR 4004 004Eh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR EORR
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Value after reset:
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
EOSR
15
EOSR
14
EOSR
13
EOSR
12
EOSR
11
EOSR
10
EOSR
09
EOSR
08
EOSR
07
EOSR
06
EOSR
05
EOSR
04
EOSR
03
EOSR
02
EOSR
01
EOSR
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
EOSRn
Pmn Event Output Set
When the ELC_PORTx occurs:
0: No affect to output
1: High output.
R/W
b31 to b16
EORRn
Pmn Event Output Reset
When the ELC_PORTx occurs:
0: No affect to output
1: Low output.
R/W
m = 1, 2
n = 00 to 15
x = 1 and 2
Note:
Note:
When EORRn or EOSRn is set, writing to PODRn, PORRn, and POSRn is prohibited.
Do not set EORRn and EOSRn at the same time.
The Port Control Register 4 (PCNTR4) is a 32-bit and 16-bit read/write register that controls the setting or resetting of
the port output data by event input from the ELC. EORR bits [31:16] in PCNTR4 and EOSR bits [15:0] in PCNTR4 are
accessed in 16-bit units.
The EOSR bit changes the PODR based on EOSR being set when an ELC_PORTx occurs. For example, for P100 if
PORT1.EOSR00 is set to 1 when the ELC_PORTx occurs, PORT1.PODR00 outputs 1. The bits of non-existent port m
are reserved. When writing, write 0 to these bits. The bit of non-existent pin is reserved. The write value should always
be 0. P200, P214, and P215 are input only, so PORT2.PCNTR4.b0, b14, and b15 are reserved.
The EORR bit changes the PODR based on EORR being reset when an ELC_PORTx occurs. For example, for P100 if
PORT1.EORR00 is set to 1 when the ELC_PORTx occurs, PORT1.PODR00 outputs 0. The bits of non-existent port m
are reserved. When writing, write 0 to these bits. The bit of non-existent pin is reserved. The write value should always
be 0. P200, P214, and P215 are input only, so PORT2.PCNTR4.b16, b30, and b31 are reserved.
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16. I/O Ports
Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY)
(m = 0 to 5; n = 00 to 15)
Address(es): PFS.P000PFS 4004 0800h to PFS.P004PFS 4004 0810h, PFS.P010PFS 4004 0828h to PFS.P015PFS 4004 083Ch,
PFS.P100PFS 4004 0840h to PFS.P113PFS 4004 0874h,
PFS.P200PFS 4004 0880h to PFS.P201PFS 4004 0884h, PFS.P204PFS 4004 0890h to PFS.P206PFS 4004 0898h,
PFS.P212PFS 4004 08B0h to PFS.P215PFS 4004 08BCh,
PFS.P300PFS 4004 08C0h to PFS.P304PFS 4004 08D0h,
PFS.P400PFS 4004 0900h to PFS.P403PFS 4004 090Ch, PFS.P407PFS 4004 091Ch to PFS.P411PFS 4004 092Ch,
PFS.P500PFS 4004 0940h to PFS.P502PFS 4004 0948h,
PFS.P000PFS_HA 4004 0802h to PFS.P004PFS_HA 4004 0812h, PFS.P010PFS_HA 4004 082Ah to PFS.P015PFS_HA 4004 083Eh,
PFS.P100PFS_HA 4004 0842h to PFS.P113PFS_HA 4004 0876h, PFS.P200PFS_HA 4004 0882h to PFS.P201PFS_HA 4004 0886h,
PFS.P204PFS_HA 4004 0892h to PFS.P206PFS_HA 4004 0896h, PFS.P212PFS_HA 4004 08B2h to PFS.P215PFS_HA 4004 08BEh,
PFS.P300PFS_HA 4004 08C2h to PFS.P304PFS_HA 4004 08D2h, PFS.P400PFS_HA 4004 0902h to PFS.P403PFS_HA 4004 090Eh,
PFS.P407PFS_HA 4004 091Eh to PFS.P411PFS_HA 4004 092Eh, PFS.P500PFS_HA 4004 0942h to PFS.P502PFS_HA 4004 094Ah,
PFS.P000PFS_BY 4004 0803h to PFS.P004PFS_BY 4004 0813h, PFS.P010PFS_BY 4004 082Bh to PFS.P015PFS_BY 4004 083Fh,
PFS.P100PFS_BY 4004 0843h to PFS.P113PFS_BY 4004 0877h, PFS.P200PFS_BY 4004 0883h to PFS.P201PFS_BY 4004 0887h,
PFS.P204PFS_BY 4004 0893h to PFS.P206PFS_BY 4004 0897h, PFS.P212PFS_BY 4004 08B3h to PFS.P215PFS_BY 4004 08BFh,
PFS.P300PFS_BY 4004 08C3h to PFS.P304PFS_BY 4004 08D3h, PFS.P400PFS_BY 4004 0903h to PFS.P403PFS_BY 4004 090Fh,
PFS.P407PFS_BY 4004 091Fh to PFS.P411PFS_BY 4004 092Fh, PFS.P500PFS_BY 4004 0943h to PFS.P502PFS_BY 4004 094Bh
b31
b30
b29
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
PMR
0
0
0
0
0
0
0
0
0*2
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
PCR
—
PDR
PIDR
PODR
0
0*2
0
0
x
0
PSEL[4:0]
ASEL
ISEL
EOF
EOR
—
DSCR
—
—
—
NCOD
R
0
0
0
0
0
0*2
0
0
0
0
Value after reset:
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
PODR
Port Output Data
0: Low output
1: High output.
R/W
b1
PIDR
Pmn State
0: Low level
1: High level.
R
b2
PDR
Port Direction
0: Input (functions as an input pin)
1: Output (functions as an output pin).
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
PCR
Pull-up Control
0: Disables an input pull-up
1: Enables an input pull-up.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
NCODR
N-Channel Open Drain Control
0: CMOS output
1: NMOS open-drain output.
R/W
b9 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b10
DSCR
Port Drive Capability
0: Low drive
1: Middle drive.
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b13, b12
EOF/EOR
Event on Falling/Event on
Rising *1
b13 b12
R/W
b14
ISEL
IRQ Input Enable
0: Not used as an IRQn input pin
1: Used as an IRQn input pin.
R/W
b15
ASEL
Analog Input Enable
0: Used other than as an analog pin
1: Used as analog pin.
R/W
b16
PMR
Port Mode Control
0: Uses the pin as a general I/O pin
1: Uses the pin as an I/O port for peripheral functions.
R/W
b23 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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0
0
1
1
0: Don’t care
1: Detect rising edge
0: Detect falling edge
1: Detect both edge.
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16. I/O Ports
Bit
Symbol
Bit name
Description
R/W
b28 to b24
PSEL[4:0]
Peripheral Select
These bits select the peripheral function. For individual pin
functions, see associated tables in this chapter.
R/W
b31 to b29
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. Supported for PORT1 and PORT2.
Note 2. The initial value of P108, P201 and P300 is not 0000 0000h.
P108 is 0001 0010h, P201 is 0000 0010h, and P300 is 0001 0010h.
The Port mn Pin Function Select Register (PmnPFS) is a 32-bit, 16-bit, and 8-bit read/write register that controls the
selection of the port mn function which is set by 32-bit units. PmnPFS_HA bits [15:0] in PmnPFS are accessed in 16-bit
units and PmnPFS_BY bits [7:0] are accessed in 8-bit units.
The PDR/PIDR/PODR bits serve the same function as the PCNTR. When these bits are read, the PCNTR value is read.
The PCR bit is set when an input pull-up resistor is enabled or disabled for the individual pins of the port. When a pin is
in the input state with the corresponding bit in PmnPFS.PCR set to 1, the pull-up resistor connected to the pin is enabled.
When a pin is set as an external bus pin, a general port output pin, or a peripheral function output pin, the pull-up resistor
for the pin is disabled regardless of the settings of PCR. The pull-up resistor is also disabled in the reset state. The bit of
a non-existent pin is reserved. A reserved bit is read as 0. The write value should be 0.
The NCODR bit is set when an output type is selected for the pins of the port. The bit of a non-existent pin is reserved.
When writing, write 0 as CMOS output. The bit of a non-existent pin is also reserved. A reserved bit is read as 0. The
write value should be 0.
The DSCR bit is set when the drive capacity of the port is switched. The bit that corresponds to a pin whose drive
capacity is fixed is readable and writable, but the drive capacity cannot be changed. The bit of a non-existent pin is
reserved. A reserved bit is read as 0. The write value should be 0.
The EOR and EOF bits are set when the edge detection way is selected for the port group input signal. These bits support
the rising, falling, or both edge detections. While the EOR/EOF bits are set to 01b, 10b, or 11b, the input enable of the I/
O cell is asserted. Following that, the event pulse is input from the external pin, and GPIO outputs the event pulse to the
ELC. The bit of a non-existent pin is reserved. A reserved bit is read as 0. The write value should be 0.
The ISEL bit is set when a pin is used as an IRQ input pin. This setting can be used with the combination of the
peripheral function, although IRQn (external pin interrupt) of the same number should not be enabled by two or more
pins.
The ASEL bit is set when a pin is used as an analog pin. When the pin is set as an analog pin by the ASEL bit:
1. Select the general I/O port using the Port Mode Control bit (PmnPFS.PMR).
2. Disable the pull up resistor with the Pull Up Control bit (PmnPFS.PCR).
3. Specify the input using the Port Direction bit (PmnPFS.PDR). The pin state cannot be read at this point.
The PmnPFS register is protected by the Write-Protect Register (PWPR). Modify the register after releasing the
protection.
The ISEL bit to an unspecified IRQn is reserved. The ASEL bit to an unspecified analog input/output is reserved.
The PMR bit is set when the pin function of the port is specified. The bit of a non-existent pin is reserved. When writing,
write 0 as the general I/O port to this bit. The bit of a non-existent pin is also reserved. A reserved bit is read as 0. The
write value should be 0.
The PSEL[4:0] bits select the assigned peripheral function.
For details of the Peripheral Select Settings for each product, see section 16.6, Peripheral Select Settings for each
product.
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16.2.6
16. I/O Ports
Write-Protect Register (PWPR)
Address(es): PMISC.PWPR 4004 0D03h
b7
b6
B0WI PFSWE
Value after reset:
1
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
PFSWE
PmnPFS Register Write
Enable
0: Writing to the PmnPFS register is disabled
1: Writing to the PmnPFS register is enabled.
R/W
b7
B0WI
PFSWE Bit Write Disable
0: Writing to the PFSWE bit is enabled
1: Writing to the PFSWE bit is disabled.
R/W
PFSWE bit (PmnPFS Register Write Enable)
Writing to the PmnPFS register is enabled only when the PFSWE bit is set to 1. To set the PFSWE bit to 1, write 1 to the
PFSWE bit after writing 0 to the B0WI bit.
B0WI bit (PFSWE Bit Write Disable)
Writing to the PFSWE bit is enabled only when the B0WI bit is set to 0.
16.3
16.3.1
Operation
General I/O Ports
All pins except P108 and P300 operate as general I/O input ports after reset. General I/O ports are organized as 16 bits
per port and can be accessed per port by the Port Control Registers (PCNTRn, where n=1 to 4), or per individual pin by
the Pin Function Select Registers. For details of these registers, see section 16.2, Register Descriptions.
Each port has the following bits:
Port Direction bit (PDR), which selects input or output direction
Port Output Data bit (PODR), which holds data for output
Port Input Data bit (PIDR), which indicates the pin states
Event Input Data bit (EIDR), which indicates the pin state when an ELC_PORT1 or 2 signal occurs
Port Output Set bit (POSR), which indicates the output value when a software write occurs
Port Output Reset bit (PORR), which indicates the output value when a software write occurs
Event Output Set bit (EOSR), which indicates the output value when an ELC_PORT1 or 2 signal occurs
Event Output Reset bit (EORR), which indicates the output value when an ELC_PORT1 or 2 signal occurs.
16.3.2
Port Function Select
The Port Function Select provides the following configuration for each pin:
I/O configuration — Complementary or open drain output, pull-up control, and drive strength
General I/O port — Port direction, output data setting, and read input data
Alternate function — Configured function mapping to the pin.
Each pin is associated with the Pin Function Select Register (PmnPFS), which includes the corresponding PODR, PIDR,
and PDR bits as previously described. In addition, the PmnPFS register includes the following:
Pull-up resistor control bit in the PCR that turns the input pull-up MOS on or off
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16. I/O Ports
N-channel open drain control bit in the NCODR that selects the output type for each pin
Drive capacity control bits in the DSCR that select the drive capacity
Event on rising bit in the EOR to detect rising edges on the port input
Event on falling bit in the EOF to detect falling edges on the port input
IRQ input enable bit in the ISEL to specify an IRQ input pin
Analog input enable bit in the ASEL to specify an analog pin
Port mode control bit in the PMR to specify the pin function of each port
Port function select bits in PSEL[4:0] to select the associated peripheral function.
These configuration can be done by single-register access to the Pin Function Select Register. For details, see section 16,
Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 5; n = 00 to 15).
16.3.3
Port Group Function for ELC
In the MCU, PORT1 and PORT2 are assigned for the port group function.
16.3.3.1
Behavior when ELC_PORT1 or 2 is input from ELC
The MCU supports two functions when the ELC_PORT1 or ELC_PORT2 comes from the ELC.
(1)
Input to EIDR
For the GPI function (PDR = 0 and PMR = 0 in the PmnPFS register), when the ELC_PORT1 or 2 comes from the ELC,
the input enable of the I/O cell is asserted, and data from the external pins are read into the EIDR bit. See Figure 16.2.
For the GPO function (PDR = 1) or the peripheral mode (PMR = 1), 0 is input into the EIDR bit from the external pins.
ELC
ELC_PORT
1 or 2
EIDR
PAD
en
Figure 16.2
(2)
Event ports input data
Output from PODR by EOSR/EORR
When an ELC_PORT1 or 2 signal occurs, the data is output from the PODR to the external pin based on the EOSR/
EORR bit settings as follows:
If EOSR is set to 1, when the ELC_PORT1 or 2 signal occurs, the PODR register outputs 1 to the external pin.
Otherwise, when EOSR = 0, the PODR value is kept.
If EORR is set to 1, when the ELC_PORT1 or 2 signal occurs, the PODR register outputs 0 to the external pin.
Otherwise, when EORR = 0, the PODR value is kept.
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16. I/O Ports
EOSR
ELC
PODR
PAD
EORR
en
ELC_PORT1 or 2
Figure 16.3
Ports output data
16.3.3.2
Behavior when event pulse is output to ELC
Set the following to output the event pulse from the external pins to the ELC:
Set the EOR/EOF bit in the PmnPFS register. For details, see section 16.2.5, Port mn Pin Function Select Register
(PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 5; n = 00 to 15). When the EOR/EOF bits are set, the input enable
of the I/O cell is asserted.
Data from the external pin is the input. For example, for PORT1 when the data is input from P100 to P113, the data of
those 14 pins is organized by OR logic. Data from the 14 pins that are organized by OR logic is then formed into a oneshot pulse, which goes to the ELC. The operation of PORT2 is also the same as PORT1.
EOR
EOF
ELC
PAD
IOPORT_
GROUP1 or 2
Edge detect
From other PAD
Figure 16.4
16.4
Generation of event pulse
Handling of Unused Pins
Details on the handling of unused pins are given in Table 16.3, Handling of unused pins.
Table 16.3
Handling of unused pins (1 of 2)
Pin Name
Description
P201/MD
Use this as a mode pin
RES
Connect this pin to VCC by a resistor (pulling up)
USB_DP, USB_DM
Keep these pins open when both P914PFS.PMR and P915PFS.PMR bits are set to 1.
When P914PFS.PMR or P915PFS.PMR bit is set to 0, configure it in the same way as port 1 to 5.
P200/NMI
Connect this pin to VCC by a resistor (pulling up)
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Table 16.3
16. I/O Ports
Handling of unused pins (2 of 2)
Pin Name
Description
P212/EXTAL
When the main clock oscillator is not used, set the MOSCCR.MOSTP bit to 1 (general port P212). When this
pin is not used as port P212, it is configured in the same way as port 1 to 5.
P213/XTAL
When the main clock oscillator is not used, set the MOSCCR.MOSTP bit to 1 (general port P213). When this
pin is not used as port P213, it is configured in the same way as port 1 to 5. When the external clock is input
to the EXTAL pin, leave this pin open.
P215/XCIN
When the sub-clock oscillator is not used, set the SOSCCR.SOSTP bit to 1 (general port P215). When this
pin is not used as port P215, it is configured in the same way as port 1 to 5.
P214/XCOUT
When the sub-clock oscillator is not used, set the SOSCCR.SOSTP bit to 1 (general port P214). When this
pin is not used as port P214, it is configured in the same way as port 1 to 5.
P000 to P015
If the direction setting is for input (PCNTR1.PDRn = 0), the associated pin is connected to AVCC0 (pulled up)
by a resistor or to AVSS0 (pulled down) by a resistor*1
P1x to P5x
If the direction setting is for input (PCNTR1.PDRn = 0), the associated pin is connected to VCC (pulled up) by
a resistor or to AVSS0 (pulled down) by a resistor.*1, *2
If the direction setting is for output (PCNTR1.PDRn = 1), the pin is released.*1
Note 1. Clear the PmnPFS.PMR bit, the PmnPFS.ISEL bit, PmnPFS.PCR, and the PmnPFS.ASEL bit to 0.
Note 2. P108 and P300 are recommended for pulling up VCC (pulled up) through a resistor, because these pins are input
pull-up enabled from the initial value (PmnPFS.PCR=1).
16.5
16.5.1
Usage Notes
Procedure for Specifying Pin Function
Perform the following steps to specify the input/output pin functions.
1. Clear the B0WI bit in the PWPR register. This enables writing to the PFSWE bit in the PWPR register.
2. Set 1 to the PFSWE bit in the PWPR register. This enables writing to the PmnPFS register.
3. Clear the port mode control in the PMR for the target pin to 0 to select the general I/O port.
4. Specify the input/output function for the pin through the PSEL[4:0] bit settings in the PmnPFS register.
5. Set the PMR to 1 as necessary to switch to the selected input/output function for the pin.
6. Clear the PFSWE bit in the PWPR register. This disables writing to the PmnPFS register.
7. Set 1 to the B0WI bit in the PWPR register. This disables writing to the PFSWE bit in the PWPR register.
16.5.2
Procedure to Use Port Group Input
Perform the following steps to use the port group input (PORT1 and PORT2).
1. Set the ELSRx.ELS[7:0] bits to 00000000b to ignore the unexpected pulse. For more information, see section 15,
Event Link Controller (ELC).
2. Set the EOF/EOR bit of the PmnPFS register to specify the rising, falling or both edge detections.
3. Execute a dummy read or wait, for example 100 ns. Ignore the unexpected pulse that occurs depends on the initial
value of the external pin.
4. Set the ELSRx.ELS[7:0] bits to enable the event signals.
16.5.3
Port Output Data Register (PODR) Summary
This register outputs data as follows:
1. Output 0 if the PCNTR4.EORR is set to 1 when the ELC_PORT1 or 2 signal occurs.
2. Output 1 if the PCNTR4.EOSR is set to 1 when the ELC_PORT1 or 2 signal occurs.
3. Output 0 if the PCNTR3.PORR is set to 1.
4. Output 1 if the PCNTR3.POSR is set to 1.
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16. I/O Ports
5. Output 0 or 1 by setting the PCNTR1.PODR.
6. Output 0 or 1 by setting the PmnPFS.PODR.
Numbers in this list correspond to the priority for writing the PODR. For example, if (1) and (3) from the list above occur
at same time, the higher priority (1) is executed.
16.5.4
Notes on Use of Analog Functions
To use an analog function, set the corresponding bits in both the Port Mode Control bit (PMR) and Port Direction bit
(PDR) to 0 so that the pin acts as a general input port. Following that, set the Analog Input Enable bit in the Port mn Pin
Function Select Register (PmnPFS.ASEL) to 1.
16.6
Peripheral Select Settings for each product
This section provides the detail of Pin Function Select configuration by the PmnPFS register. Several pin names are
added suffix of _A, _B, _C, and _D. The suffix can be ignored when assigning functionality; however, it is prohibited to
assign the same function to the two or more pins simultaneously.
Table 16.4
PSEL[4:0]
bits settings
Register settings for input/output pin function (PORT0)
Pin
Function
P000
00000b (Value
after reset)
Hi-Z/SWD
Hi-Z
01100b
CTSU
ASEL bit
P001
P002
P003
P004
TS21
TS22
TS23
TS24
TS25
AN000
AN001
AN002
AN003
AN004
ISEL bit
IRQ6
IRQ7
IRQ2
—
IRQ3
DSCR bit
L/M
L/M
L/M
L/M
L/M
NCODR bit
—
—
—
—
—
PCR bit
64-pin product
48-pin product
40-pin product
36-pin product
P014
P015
PSEL[4:0]
bits settings
Pin
Function
P010
00000b (Value
after reset)
Hi-Z/SWD
Hi-Z
01100b
CTSU
ASEL bit
P011
P012
P013
TS30
TS31
—
—
—
TS28
AN005/
VREFH0
AN006/
VREFL0
AN007
AN008
AN009/
DA0
AN010
ISEL bit
—
—
—
—
—
IRQ7
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
NCODR bit
—
—
—
—
—
—
PCR bit
64-pin product
48-pin product
40-pin product
36-pin product
: Available
—: Setting prohibited
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Table 16.5
PSEL[4:0]
Bits Settings
00000b (Value
after reset)
16. I/O Ports
Register settings for input/output pin function (PORT1) (1)
Pin
Function
P100
Hi-Z/SWD
Hi-Z
P101
P102
P103
P104
P105
P106
P107
—
00001b
AGT
AGTIO0_A
AGTEE0
AGTO0
—
—
—
—
00010b
GPT
GTETRGA_A
GTETRGB_A
GTOWLO_A
GTOWUP_A
GTETRGB_B
GTETRGA_C
—
—
00011b
GPT
GTIOC5B_A
GTIOC5A_A
GTIOC2B_A
GTIOC2A_A
—
—
GTIOC0B_B
GTIOC0A_B
00100b
SCI
RXD0_A/
SCL0_A/
MISO0_A
TXD0_A/
SDA0_A/
MOSI0_A
SCK0_A
CTS0_RTS0_A RXD0_C/
/SS0_A
SCL0_C/
MISO0_C
—
—
—
00101b
SCI
SCK1_A
CTS1_RTS1_A —
/SS1_A
—
—
—
—
—
—
00110b
SPI
MISOA_A
MOSIA_A
RSPCKA_A
SSLA0_A
SSLA1_A
SSLA2_A
SSLA3_A
00111b
IIC
SCL1_B
SDA1_B
—
—
—
—
—
—
01000b
KINT
KR00
KR01
KR02
KR03
KR04
KR05
KR06
KR07
01001b
CLKOUT/
ACMPLP/RTC
—
—
—
—
—
—
—
—
01010b
CAC/ADC14
—
—
ADTRG0_A
—
—
—
—
—
01100b
CTSU
TS26
TS16
TS15
TS14
TS13
—
—
—
10000b
CAN
—
—
CRX0_C
CTX0_C
—
—
—
—
ASEL bit
AN022/
CMPIN0
AN021/
CMPREF0
AN020/
CMPIN1
AN019/
CMPREF1
—
—
—
—
ISEL bit
IRQ2
IRQ1
—
—
IRQ1
IRQ0
—
—
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
L/M
L/M
NCODR bit
—
—
—
—
—
PCR bit
64-pin product
48-pin product
40-pin product
36-pin product
: Available
—: Setting prohibited
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Table 16.6
PSEL[4:0]
bits settings
00000b (Value
after reset)
16. I/O Ports
Register settings for input/output pin function (PORT1) (2)
Pin
Function
P108
P109
Hi-Z/SWD
SWDIO
Hi-Z
P110
P111
P112
P113
00001b
AGT
—
—
—
—
—
—
00010b
GPT
GTOULO_C
GTOVUP_A
GTOVLO_A
—
—
—
00011b
GPT
GTIOC0B_A
GTIOC1A_A
GTIOC1B_A
GTIOC3A_A
GTIOC3B_A
—
00100b
SCI
—
—
CTS0_RTS0_C SCK0_C
/SS0_C
TXD0_C/
SDA0_C/
MOSI0_C
—
00101b
SCI
CTS9_RTS9_B TXD9_B/
/SS9_B
SDA9_B/
MOSI9_B
RXD9_B/
SCL9_B/
MISO9_B
SCK9_B
—
—
00110b
SPI
SSLB0_B
MOSIB_B
MISOB_B
RSPCKB_B
—
—
00111b
IIC
—
—
—
—
—
—
01000b
KINT
—
—
—
—
—
—
01001b
CLKOUT/
ACMPLP/RTC
—
CLKOUT_B
VCOUT
—
—
—
01010b
CAC/ADC14
—
—
—
—
—
—
01100b
CTSU
—
TS10
TS11
TS12
TSCAP_C
—
10000b
CAN
—
CTX0_A
CRX0_A
—
—
—
ASEL bit
—
—
—
—
—
—
ISEL bit
—
—
IRQ3
IRQ4
DSCR bit
L/M
L/M
L/M
L/M
L/M
L/M
NCODR bit
—
—
—
PCR bit
64-pin product
48-pin product
40-pin product
36-pin product
—
: Available
—: Setting prohibited
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Table 16.7
PSEL[4:0]
bits settings
00000b (Value
after reset)
16. I/O Ports
Register settings for input/output pin function (PORT2)
Pin
Function
P200
Hi-Z/SWD
Hi-Z
P201
P204
P205
P206
P212
P213
P214
P215
—
—
—
00001b
AGT
—
—
AGTIO1_A
AGTO1
—
AGTEE1
00010b
GPT
—
—
GTIW_A
GTIV_A
GTIU_A
GTETRGB_D GTETRGA_D —
—
00011b
GPT
—
—
GTIOC4B_B
GTIOC4A_B
—
—
—
—
—
00100b
SCI
—
—
SCK0_D
TXD0_D/
SDA0_D/
MOSI0_D
RXD0_D/
SCL0_D/
MISO0_D
—
—
—
—
00101b
SCI
—
—
SCK9_A
CTS9_RTS9_ —
A/SS9_A
RXD1_A/
SCL1_A/
MISO1_A
TXD1_A/
SDA1_A/
MOSI1_A
—
—
00110b
SPI
—
—
RSPCKB_A
SSLB0_A
SSLB1_A
—
—
—
—
00111b
IIC
—
—
SCL0_B
SCL1_A
SDA1_A
—
—
—
—
01001b
CLKOUT/
ACMPLP/RTC
—
—
—
CLKOUT_A
—
—
—
—
—
01010b
CAC/ADC14
—
—
CACREF_A
—
—
—
—
—
—
01100b
CTSU
—
—
TS00
TSCAP_A
TS01
—
—
—
—
ASEL bit
—
—
—
—
—
—
—
—
—
ISEL bit
NMI
—
—
IRQ1
IRQ0
IRQ3
IRQ2
—
—
DSCR bit
—
L/M
L/M
L/M
L/M
—
—
—
—
NCODR bit
—
—
—
—
PCR bit
—
—
—
64-pin product
48-pin product
40-pin product
36-pin product
: Available
—: Setting prohibited
Table 16.8
PSEL[4:0]
bits settings
Register settings for input/output pin function (PORT3)
Pin
Function
P300
P301
00000b (Value
after reset)
Hi-Z/SWD
SWCLK
Hi-Z
P302
P303
P304
00010b
GPT
GTOUUP_C
GTOULO_A
GTOUUP_A
—
—
00011b
GPT
GTIOC0A_A
GTIOC4B_A
GTIOC4A_A
GTIOC1B_B
GTIOC1A_B
00110b
SPI
SSLB1_B
SSLB2_B
SSLB3_B
—
—
01100b
CTSU
—
TS09
TS08
TS02
—
ASEL bit
—
—
—
—
—
ISEL bit
—
IRQ6
IRQ5
—
—
DSCR bit
L/M
L/M
L/M
L/M
L/M
NCODR bit
—
—
—
—
—
PCR bit
64-pin product
48-pin product
40-pin product
36-pin product
: Available
—: Setting prohibited
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Table 16.9
PSEL[4:0]
bits settings
16. I/O Ports
Register settings for input/output pin function (PORT4)
Pin
Function
P400
00000b (Value
after reset)
Hi-Z/SWD
Hi-Z
P401
P402
P403
P407
P408
P409
P410
P411
00001b
AGT
00010b
GPT
AGTIO1_D
—
—
—
—
—
—
AGTOB1
AGTOA1
—
GTETRGA_B —
—
—
GTOWLO_B
GTOWUP_B
GTOVLO_B
00011b
GTOVUP_B
GPT
GTIOC6A_A
GTIOC6B_A
GTIOC3A_B
—
GTIOC5B_B
GTIOC5A_B
GTIOC6B_B
GTIOC6A_B
00100b
SCI
SCK0_B
CTS0_RTS0_ —
B/SS0_B
—
CTS0_RTS0_ —
D/SS0_D
—
RXD0_B/
SCL0_B/
MISO0_B
TXD0_B/
SDA0_B/
MOSI0_B
00101b
SCI
SCK1_B
TXD1_B/
SDA1_B/
MOSI1_B
RXD1_B/
SCL1_B/
MISO1_B
CTS1_RTS1_ —
B/SS1_B
RXD9_A/
SCL9_A/
MISO9_A
TXD9_A/
SDA9_A/
MOSI9_A
—
—
00110b
SPI
—
—
—
—
SSLB3_A
—
—
MISOA_B
MOSIA_B
00111b
IIC
SCL0_A
SDA0_A
—
—
SDA0_B
—
—
—
—
01001b
CLKOUT/
ACMPLP/RTC
—
—
—
—
RTCOUT
—
—
—
—
01010b
CAC/ADC14
CACREF_C
—
—
—
ADTRG0_B
—
—
—
—
01100b
CTSU
TS20
TS19
TS18
TS17
TS03
TS04
TS05
TS06
TS07
10000b
CAN
—
CTX0_B
CRX0_B
—
—
—
—
—
—
10011b
USBFS
—
—
—
—
—
—
USB_VBUS
—
—
—
ASEL bit
—
—
—
—
—
—
—
—
—
ISEL bit
IRQ0
IRQ5
IRQ4
—
—
IRQ7
IRQ6
IRQ5
IRQ4
L/M
DSCR bit
L/M
L/M
L/M
NCODR bit
L/M
L/M
L/M
L/M
L/M
PCR bit
64-pin product
48-pin product
40-pin product
36-pin product
: Available
—: Setting prohibited
Table 16.10
PSEL[4:0]
Bits Settings
Register settings for input/output pin function (PORT5)
Pin
Function
P500
Hi-Z/SWD
Hi-Z
00001b
AGT
AGTOA0
AGTOB0
00010b
GPT
GTIU_B
GTIV_B
GTIW_B
00011b
GPT
GTIOC2A_B
GTIOC2B_B
GTIOC3B_B
01100b
CTSU
00000b (Value
after reset)
P501
P502
TS27
—
—
ASEL bit
AN016
AN017
AN018
ISEL bit
—
—
—
DSCR bit
L/M
L/M
L/M
NCODR bit
—
—
—
PCR bit
64-pin product
48-pin product
40-pin product
36-pin product
: Available
—: Setting prohibited
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17. Key Interrupt Function (KINT)
17.
Key Interrupt Function (KINT)
17.1
Overview
A key interrupt (KEY_INTKR) can be generated by setting the Key Return Mode Register (KRM) and inputting a rising
edge or falling edge to the key interrupt input pins, KR00 to KR07.
Table 17.1 shows the assignment for key interrupt detection. Table 17.2 shows the function configuration, and Figure
17.1 shows the block diagram.
Table 17.1
Assignment of key interrupt detection pins
Key Interrupt Mode Control n (n = 0-7)
Description
KRM0
Controls KR00 signal in 1-bit units
KRM1
Controls KR01 signal in 1-bit units
KRM2
Controls KR02 signal in 1-bit units
KRM3
Controls KR03 signal in 1-bit units
KRM4
Controls KR04 signal in 1-bit units
KRM5
Controls KR05 signal in 1-bit units
KRM6
Controls KR06 signal in 1-bit units
KRM7
Controls KR07 signal in 1-bit units
Table 17.2
Configuration of key interrupt function
Parameter
Configuration
Input
KR00 to KR07
Control registers
Key Return Control Register (KRCTL)
Key Return Mode Register (KRM)
Key Return Flag Register (KRF)
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17. Key Interrupt Function (KINT)
0
1
KR00
KREG
Filter
KRF0
KRM0
0
1
KRMD
0
KR01
Filter
1
KREG
0
KRF1
KRM1
1
KRMD
0
KR02
Filter
1
KREG
0
KRF2
KRM2
1
KRMD
0
KR03
Filter
1
KREG
0
KRF3
KRM3
1
KEY_INTKR
KRMD
0
KR04
Filter
1
KREG
0
KRF4
KRM4
1
KEY_INTKR mask signal
KRMD
0
KR05
Filter
1
KREG
0
KRF5
KRM5
1
KRMD
0
KR06
Filter
1
KREG
0
KRF6
KRM6
1
KRMD
0
KR07
Filter
1
KREG
0
KRF7
KRM7
1
KRMD
Figure 17.1
Key interrupt function block diagram
All key return factors are merged by the OR gate, and the key interrupt (KEY_INTKR) is the output of the AND gate to
mask the merged key return factor by the KEY_INTKR mask signal. When using KRFn (KRMD = 1), KEY_INTKR
mask signal is used as the output mask that is asserted by clearing KRFn.
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17.2
17. Key Interrupt Function (KINT)
Register Descriptions
17.2.1
Key Return Control Register (KRCTL)
Address(es): KINT.KRCTL 4008 0000h
b7
b6
b5
b4
b3
b2
b1
b0
KRMD
—
—
—
—
—
—
KREG
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
KREG
Selection of Detection Edge
(KR00 to KR07)
0: Falling edge
1: Rising edge.
R/W
b6 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
KRMD
Usage of Key Interrupt Flags
(KRF0 to KRF7)
0: Do not use key interrupt flags
1: Use key interrupt flags.
R/W
The KRCTL Register controls the usage of the key interrupt flags, KRF0 to KRF7, and sets the detection edge.
17.2.2
Key Return Flag Register (KRF)
Address(es): KINT.KRF 4008 0004h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
KRF7
KRF6
KRF5
KRF4
KRF3
KRF2
KRF1
KRF0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
KRFn
Key Interrupt Flag n
0: No key interrupt detected
1: Key interrupt detected.
R/W
n = 0 to 7
Note:
When KRMD = 0, setting the KRFn bit to 1 is prohibited.
When setting the KRFn bit to 1, the KRFn value does not change. To clear the KRFn bit, confirm the target bit is
1 before writing 0 to the bit, then write 1 to the other bits.
The KRF Register controls the key interrupt flags, KRF0 to KRF7.
17.2.3
Key Return Mode Register (KRM)
Address(es): KINT.KRM 4008 0008h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
KRM7
KRM6
KRM5
KRM4
KRM3
KRM2
KRM1
KRM0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
KRMn
Key Interrupt Mode Control n
0: Do not detect key interrupt signal
1: Detect key interrupt signal.
R/W
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17. Key Interrupt Function (KINT)
n = 0 to 7
Note:
The on-chip pull-up resistors can be applied by setting the corresponding key interrupt input pin in the pull-up
resistor. For details, see section 16, I/O Ports.
Key interrupts can be assigned by the PmnPFS.PSEL bits. For details, see section 16, I/O Ports.
An interrupt is generated when the target bit in the KRM register is set while a low level (KREG is set to 0) or a
high level (KREG is set to 1) is being input to the key interrupt input pin. To ignore this interrupt, set the KRM
register after disabling the interrupt handling.
The KRM register sets the key interrupt mode.
17.3
Operation
17.3.1
When Not Using Key Interrupt Flag (KRMD = 0)
A key interrupt (KEY_INTKR) is generated when the valid edge specified in the KREG bit is input to a key interrupt pin,
KR00 to KR07. To identify the channel to which the valid edge is input, read the port register and check the port level
after the key interrupt (KEY_INTKR) is generated.
The KEY_INTKR signal changes according to the input level of the key interrupt input pin, KR00 to KR07.
KRn
KEY_INTKR
Delay
time
Note:
n = 00 to 07
Figure 17.2
Delay
time
Key interrupt
When KRMD = 0 and KREG = 0
Operation of KEY_INTKR signal when key interrupt is input to a single channel
Figure 17.3 shows the operation when a valid edge is input to multiple key interrupt input pins. The KEY_INTKR signal
is set while a low level is being input to one pin, that is, when KREG is set to 0. Therefore, even if a falling edge is input
to another pin in this period, a key interrupt (KEY_INTKR) is not generated again. See [1] in Figure 17.3.
KR00
KR01
[1]
KEY_INTKR
Delay
time
Delay
time
Key interrupt
Figure 17.3
17.3.2
Delay
time
When KRMD = 0 and KREG = 0
Operation of KEY_INTKR signal when key interrupts are input to multiple channels
When Using Key Interrupt Flag (KRMD = 1)
A key interrupt (KEY_INTKR) is generated when the valid edge specified in the KREG bit is input to a key interrupt pin,
KR00 to KR07. To identify the channels to which the valid edge is input, read the Key Return Flag Register (KRF) after
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17. Key Interrupt Function (KINT)
the key interrupt (KEY_INTKR) is generated. If the KRMD bit is set to 1, clear the KEY_INTKR signal by clearing the
corresponding bit in the KRF Register.
As Figure 17.4 shows, only one interrupt is generated each time a falling edge is input to one channel, that is, when
KREG = 0, regardless of whether the KRFn bit is cleared before or after a rising edge is input.
(a) When KRF0 is cleared after a rising edge is input to the KR00 pin
KR00
KRF0
Cleared by
software
KEY_INTKR
Delay
time
Key interrupt
(b) When KRF0 is cleared before a rising edge is input to the KR00 pin
KR00
KRF0
Cleared by
software
KEY_INTKR
Delay
time
Key interrupt
Figure 17.4
When KRMD = 1 and KREG = 0
Basic operation of KEY_INTKR signal when key interrupt flag is used
The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 17.5. A falling edge is
also input to the KR01 and KR05 pins after a falling edge is input to the KR00 pin, that is, when KREG = 0. The KRF1
bit is set when the KRF0 bit is cleared. A key interrupt generates one clock, PCLKB, after the KRF0 bit is cleared. See
[1] in Figure 17.5. Also, after a falling edge is input to the KR05 pin, the KRF5 bit is set. See [2] in the figure when the
KRF1 bit is cleared. A key interrupt generates one clock, PCLKB, after the KRF1 bit is cleared. See [3] in the figure. It is
therefore possible to generate a key interrupt when a valid edge is input to multiple channels.
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17. Key Interrupt Function (KINT)
KR00
KR01
KR05
KRF0
Delay time
Cleared by software
[2]
KRF1
Cleared by software
Delay time
KRF5
Cleared by
software
Delay time
[1]
[3]
KEY_INTKR
Key interrupt
Key interrupt
Key interrupt
When KRMD = 1 and KREG = 0
Figure 17.5
17.4
Operation of KEY_INTKR signal when key interrupts are input to multiple channels
Usage Note
If the KEY_INTKR is used as the snooze request, the KRMD must be set to 0.
If the KEY_INTKR is used as the interrupt source for returning to Normal mode from Snooze and Software
Standby modes, the KRMD must be set to 1.
When the key interrupt function is assigned to a pin by the MPC, this pin input is always enabled in the Software
Standby mode, and if this pin level changes, the corresponding KRFn might be set. Therefore, a key interrupt might
occur after canceling the Software Standby mode.
To ignore changes to the key interrupt pin during software standby, clear the corresponding KRM bit before entering
Software Standby mode. After canceling Software Standby mode, clear the KRF before the corresponding KRM bit can
be set.
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18. Port Output Enable for GPT (POEG)
18.
Port Output Enable for GPT (POEG)
18.1
Overview
The Port Output Enable (POEG) can place the General PWM Timer (GPT) output pins in the output-disable state in one
of the following ways:
Input level detection of the GTETRGn (n = A, B) pins
Output-disable request from the GPT
Oscillation stop detection of the clock generation circuit
Register settings.
The GTETRGn pins can also be used as GPT external trigger input pins.
Table 18.1 lists the POEG specifications, Figure 18.1 shows the block diagram, and Table 18.2 lists the input pins.
Table 18.1
POEG specifications
Parameter
Description
Output-disable control by input level detection
The GPT output pins can be disabled when a GTETRGA and GTETRGB rising edge
or high level is sampled after polarity and filter selection
Output-disable request from the GPT
When the GTIOCA and GTIOCB pins are driven to an active level simultaneously, the
GPT generates an output-disable request to the POEG. Through reception of these
requests, the POEG can control whether the GTIOCA and GTIOCB pins are placed in
output disable.
Output-disable control through oscillation stop
detection
The GPT output pins can be disabled when clock generation circuit oscillation stops
Output-disable control through software
(registers)
The GPT output pins can be disabled by modifying the register settings
Interrupts
Allows output-disable control by input level detection
Allows output-disable request from the GPT.
External trigger output function to GPT
(count start, count stop, count clear, up-count,
down-count, or input capture function)
The GTETRGA and GTETRGB signals can be output to the GPT after polarity and
filter selection
Noise filtering
Three times sampling for every PCLKB/1, PCLKB/8, PCLKB/32, or PCLKB/128 can
be set for each input pin GTETRGA and GTETRGB
Positive or negative polarity can be selected for each input pin GTETRGA and
GTETRGB
Signal state after polarity and filter selection can be monitored.
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18. Port Output Enable for GPT (POEG)
Group B
POEG Group A
IOCF
IOCE
GTINTAD.GRPABH,
GTINTAD.GRPABL
Group A
Ch 0
Group B
Ch 6
POEG_GROUP0
S
GPT Ch 0
ICU
R
POEG_GROUP1
GPT
OPS
Ch 1
Ch 6
GTOUUP
GTOULO
GTOVUP
GTOVLO
GTOWUP
GTOWLO
OPSCR.
GRP[1:0]
OPSCR.
GODF
Oscillation
Stop Detector
OSTPF
OSC stop
detect
OSTPE
GTINTAD.
GRP[1:0]
GTIOR.
OADF[1:0]
GTIOR.
OBDF[1:0]
To ch 1
To ch 6
S
R
To ch 1
To ch 6
SSF
GTETRGB
GTIOC0B
GTIOC1A
GTIOC1B
GTIOC6A
PIDF
Digital filter
NFCS[1:0]
NFEN
INV
GTETRGA
GTIOC0A
To ch 1
To ch 6
PIDE
GTIOC6B
To ch 1
To ch 6
ST
Ch 0
Ch 1
Ch 6
Figure 18.1
Table 18.2
POEG block diagram
POEG input pins
Pin name
I/O
Description
GTETRGA
Input
GPT output pin output-disable request signal and GPT external trigger input pin A
GTETRGB
Input
GPT output pin output-disable request signal and GPT external trigger input pin B
18.2
Register Descriptions
18.2.1
POEG Group n Setting Register (POEGGn) (n = A, B)
Address(es): POEG.POEGGA 4004 2000h, POEG.POEGGB 4004 2100h
b31
b30
NFCS[1:0]
Value after reset:
Value after reset:
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
NFEN
INV
—
—
—
—
—
—
—
—
—
—
—
ST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
PIDE
SSF
0
0
0
0
0
0
0
0
0
0
0
OSTPE IOCE
0
0
OSTPF IOCF
0
PIDF
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIDF
Port Input Detection Flag
0: No output-disable request from the GTETRGn pin occurred
1: Output-disable request from the GTETRGn pin occurred.
R(/W)*1
b1
IOCF
Output-disable request from
GPT Detection Flag
0: No output-disable request from the GPT occurred
1: Output-disable request from the GPT occurred.
R(/W)*1
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18. Port Output Enable for GPT (POEG)
Bit
Symbol
Bit name
Description
R/W
b2
OSTPF
Oscillation Stop Detection
Flag
0: No output-disable request from the oscillation stop detection
occurred
1: Output-disable request from the oscillation stop detection
occurred.
R(/W)*1
b3
SSF
Software Stop Flag
0: No output-disable request from software occurred
1: Output-disable request from software occurred.
R/W
b4
PIDE
Port Input Detection Enable
0: Disable output-disable request from the GTETRGn pins
1: Enable output-disable request from the GTETRGn pins.
R/W*2
b5
IOCE
Output-disable request from
GPT Enable
0: Disable output-disable request from GPT interrupt
1: Enable output-disable request from GPT interrupt.
R/W*2
b6
OSTPE
Oscillation Stop Detection
Enable
0: Disable output-disable request from the oscillation stop
detection
1: Enable output-disable request from the oscillation stop
detection.
R/W*2
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
ST
GTETRGn Input Status Flag 0: GTETRGn input after filtering is 0
1: GTETRGn input after filtering is 1.
R
b27 to b17
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b28
INV
GTETRGn Input Reverse
0: GTETRGn Input
1: GTETRGn Input reversed.
R/W
b29
NFEN
Noise Filter Enable
0: Disable filtering noise
1: Enable filtering noise.
R/W
b31, b30
NFCS[1:0]
Noise Filter Clock Select
b1 b0
R/W
0 0: Sampling GTETRGn pin input level for three times in every
PCLKB
0 1: Sampling GTETRGn pin input level for three times in every
PCLKB/8
1 0: Sampling GTETRGn pin input level for three times in every
PCLKB/32
1 1: Sampling GTETRGn pin input level for three times in every
PCLKB/128.
Note 1. Only 0 can be written to clear the flag.
Note 2. Can be modified only once after a reset.
The POEGGA and POEGGB registers control the output-disable state of the GPT pins output, interrupts, and the
external trigger input to GPT. In the sections that follow, POEGGn represents all the POEGGA and POEGGB registers.
18.3
Output-Disable Control Operation
If any of the following conditions is satisfied, the GTIOCxA, GTIOCxB, and the 3-phase output for BLDC motor control
pins can be set to output disable. The state of output disable is controlled in the GPT. The output disable of the GTIOCxA
and GTIOCxB pins are set to the GTINTAD.GRP, GTIOR.OADF, and GTIOR.OBDF bits in the GPT. The output
disable of the 3-phase PWM output for BLDC motor control pins are set to the OPSCR.GRP and OPSCR.GODF bits in
GPT_OPS.
Input level or edge detection of the GTETRGA and GTETRGB pins
When POEGGn.PIDE is 1, the POEGGn.PIDF flag is set to 1.
Output-disable request from GPT
When POEGGn.IOCE is 1, the POEGGn.IOCF flag is set to 1 if the disable request is enabled in GTINTAD. The
GTINTAD.GRPABH and GTINTAD.GRPABL settings apply to the group selected in GPT register
GTINTAD.GRP[1:0] and OPSCR.GRP[1:0].
Oscillation stop detection for the clock generation circuit
When POEGGn.OSTPE is 1, the POEGGn.OSTPF flag is set to 1.
SSF Bit Setting
When POEGGn.SSF is set to 1, the PWM output is disabled.
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18.3.1
18. Port Output Enable for GPT (POEG)
Pin Input Level Detection Operation
If the input conditions set by POEGGn.PIDE, POEGGn.NFCS[1:0], POEGGn.NFEN and POEGGn.INV occur on the
GTETRGA and GTETRGB pins, the GPT output pins are placed in output disable.
18.3.1.1
Digital filter
Figure 18.2 shows the high level detection by the digital filter. When a high level corresponding to the POEGGn.INV
polarity setting is detected 3 times consecutively with the sampling clock selected by POEGGn.NFCS[1:0] and
POEGGn.NFEN, the detected level is recognized as high, and the GPT output pins are placed in output disable. If even
one low level is detected during this interval, the detected level is not recognized as high. In addition, in an interval
where the sampling clock is not being output, changes of the levels on the GTETRGA and GTETRGB pins are ignored.
1, 8, 32, 128 clock
PCLKB
Sampling clock
GTETRG input
GTIOCA
GTIOCB
(PCLKD)
When high level is sampled at all points
[1]
[2]
[3]
Flag set (GTETRGn received)
When low level is sampled at least once
[1]
[0]
[1]
Flag not set
Note:
Figure 18.2
18.3.2
Each channel output can be set by GPT setting.
Low level sampling can be set by POEGGn.INV setting.
Example of digital filter operation
Output-Disable Request from GPT
For details on the operation, see the GTIOC Pin Output Negate Control in section 19, General PWM Timer (GPT).
18.3.3
Output Disable Control on Detection of Stopped Oscillation
When the oscillation stop detection function in the clock generation circuit detects stopped oscillation while
POEGGn.OSTPE is 1, the GPT output pins are placed in output disable for each group.
18.3.4
Output Disable Control Using Registers
The GPT output pins can be directly controlled by writing to the software stop flag (POEGGn.SSF).
18.3.5
Release from Output Disable
The GPT output pins that are placed in output disable can be released from that state by either returning them to their
initial state with a reset or clearing all of the following:
POEGGn.PIDF flag
POEGGn.IOCF flag
POEGGn.OSTPF flag
POEGGn.SSF flag.
Writing 0 to the POEGGn.PIDF flag is ignored (the flag is not cleared) if the external input pins GTETRGA and
GTETRGB are not disabled and the POEGGn.ST bit is not set to 0.
Writing 0 to the POEGGn.IOCF flag is valid (the flag is cleared) only if all of the GTST.OABHF and GTST.OABLF
flags in GPT are set to 0.
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18. Port Output Enable for GPT (POEG)
Writing 0 to the POEGGn.OSTPF flag is ignored (the flag is not cleared) if the OSTDSR.OSTDF flag in the clock
generation circuit is not set to 0. In addition, when the flag set and release occur at the same time, the set takes
precedence.
Figure 18.3 shows the released timing from the output disable. The output disable is released at the beginning of the next
count cycle of the GPT after the flag is released.
GPT320.GTCNT value
GPT320.GTPR
GPT320.GTCCRA
PIDF, IOCF
OSTPF, SSF
Flag clear
GTIOC0A
GTIOC0B
Output-disable
Figure 18.3
18.4
Released timing of GPT pin output from output disable
Interrupt Source
The POEG generates an interrupt request for:
the output-disable control by the input level detection
the output-disable request from GPT.
Table 18.3 lists the conditions of interrupt request.
Table 18.3
Interrupt source and condition
Interrupt source
Symbol
Corresponding flag
Description
POEG Group A interrupt
POEG_GROUP0
POEGGA.IOCF
An output-disable request from GPT disable request is
generated.
POEGGA.PIDF
An output-disable request from the GTETRGA pin is
generated.
POEGGB.IOCF
An output-disable request from GPT disable request is
generated.
POEGGB.PIDF
An output-disable request from the GTETRGB pin is
generated.
POEG Group B interrupt
18.5
POEG_GROUP1
External Trigger Output to GPT
The POEG outputs the GTETRGA and GTETRGB signals as the GPT operation trigger signals for the following:
count start
count stop
count clear
up-count
down-count
input capture.
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18. Port Output Enable for GPT (POEG)
For the POEGG.INV polarity setting signal, when the same level is input 3 times continuously with the sampling clock
selected by the POEGGn.NFCS[1:0] and POEGGn.NFEN bits, that value is output. Also, the control register is the same
as that of the input level detection operation described in section 18.3.1, Pin Input Level Detection Operation. The state
after filtering can be monitored by POEGGn.ST.
Figure 18.4 shows the external trigger output timing to GPT.
8, 16, 128 clock
PCLKB
Sampling clock
GTETRGn pin
POEGGA.ST
(GTETRGA after filtering)
[1]
[1]
[2]
Note:
Figure 18.4
18.6
18.6.1
[1]
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[1]
Each channel output can be set by GPT setting.
Polarity can be reversed by POEGGn.INV setting.
External trigger output timing to GPT
Usage Notes
Transition to Software Standby mode
When the POEG is used, do not make a transition to Software Standby mode. In this mode, the POEG stops and therefore
output disable of the pins cannot be controlled.
18.6.2
Specifying Pins Corresponding to GPT
The POEG operates the output disable control only when a pin is associated with the GPT by setting the PmnPFS.PMR
and PmnPFS.PSEL bits. When the pin is specified as a general I/O pin, the POEG does not operate the output disable
control.
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19. General PWM Timer (GPT)
19.
General PWM Timer (GPT)
19.1
Overview
The MCU has one GPT32 channel and six GPT16 channels. Table 19.1 lists the GPT specifications, Table 19.2 shows
the GPT functions, and Figure 19.1 shows the block diagram.
Table 19.1
GPT specifications
Parameter
Description
Functions
Table 19.2
GPT32 (32 bits counter) × 1 channel, GPT16 (16 bits counter) × 6 channel
Up-counting or down-counting (saw waves) or up/down-counting (triangle waves) for each counter
Clock sources independently selectable for each channel
Two input/output pins per channel
Two output compare/input capture registers per channel
For the two output compare/input capture registers of each channel, four registers are provided as
buffer registers and are capable of operating as comparison registers when buffering is not in use.
In output compare operation, buffer switching can be at crests or troughs, enabling the generation of
laterally asymmetric PWM waveforms
Registers for setting up frame cycles in each channel (with capability for generating interrupts at
overflow or underflow)
Generation of dead times in PWM operation
Synchronous starting, stopping and clearing counters for arbitrary channels
Starting, stopping, clearing and up/down counters in response to a maximum of four ELC events
Starting, stopping, clearing and up/down counters in response to input level comparison
Starting, clearing, stopping and up/down counters in response to a maximum of two external triggers
Output pin disable function by detected short-circuits between output pins
PWM waveform for controlling brushless DC motors can be generated
Compare match A to D event, overflow/underflow event and input UVW edge event can be output to
the ELC
Enables the noise filter for input capture and input UVW.
GPT functions (1 of 2)
Parameter
GPT32, GPT16
Count clock
PCLKD
PCLKD/4
PCLKD/16
PCLKD/64
PCLKD/256
PCLKD/1024
Output compare/input capture registers (GTCCR)
GTCCRA
GTCCRB
Compare/buffer registers
GTCCRC
GTCCRD
GTCCRE
GTCCRF
Cycle setting register
GTPR
Cycle setting buffer registers
GTPBR
I/O pins
GTIOCA
GTIOCB
External trigger input pin*1
GTETRGA
GTETRGB
Counter clear sources
GTPR register compare match, input capture, input pin status, ELC
event input, and GTETRGn (n = A, B) pin input
Compare match output
Low output
Available
High output
Available
Toggle output
Available
Input capture function
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Table 19.2
19. General PWM Timer (GPT)
GPT functions (2 of 2)
Parameter
GPT32, GPT16
Automatic addition of dead time
Available
(no dead time buffer)
PWM mode
Available
Phase count function
Available
Buffer operation
Double buffer
One-shot operation
Available
DTC activation
All the interrupt sources
Brushless DC motor control function
Available
Interrupt sources
6 sources
GTCCRA compare match/input capture (GPTn_CCMPA)
GTCCRB compare match/input capture (GPTn_CCMPB)
GTCCRC compare match (GPTn_CMPC)
GTCCRD compare match (GPTn_CMPD)
GTCNT overflow (GTPR compare match) (GPTn_OVF)
GTCNT underflow (GPTn_UDF)
Note: n = 0 to 6
Event linking (ELC) function
Available
Noise filtering function
Available
Note 1. GTRETRGn connects to the POEG module before connecting to the GPT. Therefore, to use the GPT function,
supply a clock for POEG by clearing MSTPD bit [14].
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19. General PWM Timer (GPT)
GPT320
Control registers
Clock source
PCLKD
PCLKD/4
PCLKD/16
PCLKD/64
PCLKD/256
PCLKD/1024
GTWP
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GTDNSR
Cycle setting/
Cycle setting buffer registers
GTPBR
GTPR
External
trigger (after noise filtering)
GTETRGA
GTETRGB
Interrupt request signals
GPT0_CCMPA
GPT0_CCMPB
GPT0_CMPC
CPT0_CMPD
GPT0_UDF
GPT0_OVF
GTICASR
GTDTCR
GTICBSR
GTDVU
GTCR
GTUDDTYC
GTIOR
GTINTAD
GTST
GTBER
GPT161
GPT162
GPT163
GPT164
GPT165
GPT166
Counter (GTCNT)
Output disable request
Output compare
Output disable signals
I/O pins
GTIOCA
Comparator
GTIOCB
Input capture
GTCCRA
GTCCRB
GTCCRC
ELC event input
GTCCRD
GTCCRE
GTCCRF
Output compare/input capture registers
GPT161.GTIOCA output
GPT_OPS
I/O pins
GTIU / GTIV / GTIW
Three-phase PWM wave generator
for brushless DC motor
OPSCR
GTOUUP / GTOULO
GTOVUP / GTOVLO
GTOWUP / GTOWLO
Output disable signals
Input UVW edge event signal (to ICU/ELC)
GTWP
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GTDNSR
GTICASR
GTICBSR
GTCR
GTUDDTYC
GTIOR
GTINTAD
GTST
GTBER
: General PWM Timer Write-Protection Register
: General PWM Timer Software Start Register
: General PWM Timer Software Stop Register
: General PWM Timer Software Clear Register
: General PWM Timer Start Source Select Register
: General PWM Timer Stop Source Select Register
: General PWM Timer Clear Source Select Register
: General PWM Timer Up Count Source Select Register
: General PWM Timer Down Count Source Select Register
: General PWM Timer Input Capture Source Select Register A
: General PWM Timer Input Capture Source Select Register B
: General PWM Timer Control Register
: General PWM Timer Count Direction and Duty Setting Register
: General PWM Timer I/O Control Register
: General PWM Timer Interrupt Output Setting Register
: General PWM Timer Status Register
: General PWM Timer Buffer Enable Register
Figure 19.1
GTCNT
GTCCRA
GTCCRB
GTCCRC
GTCCRD
GTCCRE
GTCCRF
GTPR
GTPBR
GTDTCR
GTDVU
OPSCR
: General PWM Timer Counter
: General PWM Timer Compare Capture Register A
: General PWM Timer Compare Capture Register B
: General PWM Timer Compare Capture Register C
: General PWM Timer Compare Capture Register D
: General PWM Timer Compare Capture Register E
: General PWM Timer Compare Capture Register F
: General PWM Timer Cycle Setting Register
: General PWM Timer Cycle Setting Buffer Register
: General PWM Timer Dead Time Control Register
: General PWM Timer Dead Time Value Register U
: Output Phase Switching Control Register
GPT block diagram
Figure 19.2 shows the association between GPT channels and module names.
CH6
CH5
GPT166
GPT165
CH3
CH2
CH1
CH0
GPT163
GPT162
GPT161
GPT320
CH4
GPT164
GPT16
Figure 19.2
GPT32
Association between GPT channels and module names
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19. General PWM Timer (GPT)
Table 19.3 lists the I/O pins used in the GPT.
Table 19.3
GPT I/O pins
Channel
Pin name
I/O
Function
Common
GTETRGA
Input
External trigger input pin A (After noise filtering)
GTETRGB
Input
External trigger input pin B (After noise filtering)
GTIOC0A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC0B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT161
GTIOC1A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC1B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT162
GTIOC2A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC2B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC3A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC3B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT164
GTIOC4A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC4B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GPT165
GTIOC5A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC5B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIOC6A
I/O
GTCCRA register input capture input/output compare output/PWM output pin
GTIOC6B
I/O
GTCCRB register input capture input/output compare output/PWM output pin
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
Three-phase PWM output for BLDC motor control (positive U-phase)
GTOULO
Output
Three-phase PWM output for BLDC motor control (negative U-phase)
GTOVUP
Output
Three-phase PWM output for BLDC motor control (positive V-phase)
GPT320
GPT163
GPT166
GPT_OPS
19.2
GTOVLO
Output
Three-phase PWM output for BLDC motor control (negative V-phase)
GTOWUP
Output
Three-phase PWM output for BLDC motor control (positive W-phase)
GTOWLO
Output
Three-phase PWM output for BLDC motor control (negative W-phase)
Register Descriptions
Table 19.4 lists the registers in the GPT.
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Feb 5, 2018
Page 264 of 1104
S124 User’s Manual
Table 19.4
Module
symbol
GPT320,
GPT16n
GPT_OPS
19. General PWM Timer (GPT)
GPT registers
Register name
Register
symbol
Reset value
Address
Access
Size
General PWM Timer Write-Protection Register
GTWP
00000000h
4007 8000h + 0100h × m
32
General PWM Timer Software Start Register
GTSTR
00000000h
4007 8004h + 0100h × m
32
General PWM Timer Software Stop Register
GTSTP
FFFFFFFFh
4007 8008h + 0100h × m
32
General PWM Timer Software Clear Register
GTCLR
00000000h
4007 800Ch + 0100h × m
32
General PWM Timer Start Source Select Register
GTSSR
00000000h
4007 8010h + 0100h × m
32
General PWM Timer Stop Source Select Register
GTPSR
00000000h
4007 8014h + 0100h × m
32
General PWM Timer Clear Source Select Register
GTCSR
00000000h
4007 8018h + 0100h × m
32
General PWM Timer Up Count Source Select Register
GTUPSR
00000000h
4007 801Ch + 0100h × m
32
General PWM Timer Down Count Source Select Register
GTDNSR
00000000h
4007 8020h + 0100h × m
32
General PWM Timer Input Capture Source Select Register A
GTICASR
00000000h
4007 8024h + 0100h × m
32
General PWM Timer Input Capture Source Select Register B
GTICBSR
00000000h
4007 8028h + 0100h × m
32
General PWM Timer Control Register
GTCR
00000000h
4007 802Ch + 0100h × m
32
General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
00000001h
4007 8030h + 0100h × m
32
General PWM Timer I/O Control Register
GTIOR
00000000h
4007 8034h + 0100h × m
32
General PWM Timer Interrupt Output Setting Register
GTINTAD
00000000h
4007 8038h + 0100h × m
32
General PWM Timer Status Register
GTST
00008000h
4007 803Ch + 0100h × m
32
General PWM Timer Buffer Enable Register
GTBER
00000000h
4007 8040h + 0100h × m
32
General PWM Timer Counter
GTCNT
00000000h
4007 8048h + 0100h × m
32
General PWM Timer Compare Capture Register A
GTCCRA
FFFFFFFFh*1
4007 804Ch + 0100h × m
32
General PWM Timer Compare Capture Register B
GTCCRB
FFFFFFFFh*1
4007 8050h + 0100h × m
32
General PWM Timer Compare Capture Register C
GTCCRC
FFFFFFFFh*1
4007 8054h + 0100h × m
32
General PWM Timer Compare Capture Register E
GTCCRE
FFFFFFFFh*1
4007 8058h + 0100h × m
32
General PWM Timer Compare Capture Register D
GTCCRD
FFFFFFFFh*1
4007 805Ch + 0100h × m
32
General PWM Timer Compare Capture Register F
GTCCRF
FFFFFFFFh*1
4007 8060h + 0100h × m
32
General PWM Timer Cycle Setting Register
GTPR
FFFFFFFFh*1
4007 8064h + 0100h × m
32
General PWM Timer Cycle Setting Buffer Register
GTPBR
FFFFFFFFh*1
4007 8068h + 0100h × m
32
General PWM Timer Dead Time Control Register
GTDTCR
00000000h
4007 8088h + 0100h × m
32
General PWM Timer Dead Time Value Register U
GTDVU
FFFFFFFFh*1
4007 808Ch + 0100h × m
32
Output Phase Switching Control Register
OPSCR
00000000h
4007 8FF0h
32
m = 0 to 6, n = 1 to 6
Note 1. If the effective size of counter is 16-bit, the reset value is 0000FFFFh.
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S124 User’s Manual
19.2.1
19. General PWM Timer (GPT)
General PWM Timer Write-Protection Register (GTWP)
Address(es): GPT320.GTWP 4007 8000h
GPT16m.GTWP 4007 8000h + 0100h × m (m = 1 to 6)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
WP
0
0
0
0
0
0
0
0
PRKEY[7:0]
0
Value after reset:
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
WP
Register Write Disable
0: Write to the register is enabled
1: Write to the register is disabled.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b8
PRKEY[7:0]
GTWP Key Code
When A5h is written to these bits, write to the WP bit is
permitted.
These bits are read as 0.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b16 —
GTWP enables or disables writing to the registers to prevent accidental modification. The following is a list of write
enabled or disabled registers:
GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTICASR, GTIBCSR, GTCR, GTUDDTYC, GTIOR, GTINTAD,
GTST, GTBER, GTCNT, GTCCRA, GTCCRB, GTCCRC, GTCCRD, GTCCRE, GTCCRF, GTPR, GTPBR, GTDTCR,
GTDVU.
19.2.2
General PWM Timer Software Start Register (GTSTR)
Address(es): GPT320.GTSTR 4007 8004h
GPT16m.GTSTR 4007 8004h + 0100h × m (m = 1 to 6)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT CSTRT
6
5
4
3
2
1
0
0
0
0
0
0
0
0
GTSTR starts the GTCNT counter operation for each channel n (n = 0 to 6).
The GTSTR bit number represents the channel number. The GTSTR register for each channel is common. The GTCNT
counter starts for the associated channel that corresponds to the GTSTR bit number where 1 is written. Writing 0 has no
effect on the status of GTCNT counter and the value of GTSTR register.
For the association between GTSTR bit number and channel number, see Figure 19.2.
CSTRTn bit (Channel n GTCNT Count Start) (n = 0 to 6)
The CSTRTn bit starts channel n of the GTCNT counter operation. Writing to GTSTR.CSTRTn (n = 0 to 6) bit has no
effect unless GPTm.GTSSR.CSTRT bit is set to 1 (for GPT32, m = 320, for GPT16, m = 161 to 166).
The read data shows the counter status of each channel (GTCR.CST bit). Zero means the counter stops and 1 means the
counter is running.
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Feb 5, 2018
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19.2.3
19. General PWM Timer (GPT)
General PWM Timer Software Stop Register (GTSTP)
Address(es): GPT320.GTSTP 4007 8008h
GPT16m.GTSTP 4007 8008h + 0100h × m (m = 1 to 6)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP CSTOP
6
5
4
3
2
1
0
1
1
1
1
1
1
1
GTSTP stops the GTCNT counter operation for each channel n (n = 0 to 6).
The GTSTP bit number represents the channel number. The GTSTP register of each channel is common. The GTCNT
counter stops for the channel associated with the GTSTP bit number where 1 is written. Writing 0 has no effect on the
status of GTCNT counter and the value of GTSTP register.
For the association between GTSTP bit number and a channel number, see Figure 19.2.
CSTOPn bit (Channel n GTCNT Count Stop) (n = 0 to 6)
The CSTOPn bit stops channel n of the GTCNT counter operation. Writing to GTSTP.CSTOPn bit (n = 0 to 6) has no
effect unless GPTm.GTPSR.CSTOP bit is set to 1 (for GPT32, m = 320, for GPT16, m = 161 to 166).
The read data shows the counter status of each channel (invert of GTCR.CST bit). Zero means the counter is running and
1 means the counter stops.
19.2.4
General PWM Timer Software Clear Register (GTCLR)
Address(es): GPT320.GTCLR 4007 800Ch
GPT16m.GTCLR 4007 800Ch + 0100h × m (m = 1 to 6)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
CCLR
6
CCLR
5
CCLR
4
CCLR
3
CCLR
2
CCLR
1
CCLR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GTCLR is a write-only register and clears the GTCNT counter operation for each channel n (n = 0 to 6).
The GTCLR bit number represents the channel number. The GTCLR register for each channel is common. The GTCNT
counter is cleared for the channel associated with the GTCLR bit number where 1 is written. Writing 0 has no effect on
the status of GTCNT counter.
For the association between GTCLR bit number and a channel number, see Figure 19.2.
CCLRn bit (Channel n GTCNT Count Clear) (n = 0 to 6)
Channel n of the GTCNT counter value is cleared on writing 1 to this bit. This bit is read as 0.
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S124 User’s Manual
19.2.5
19. General PWM Timer (GPT)
General PWM Timer Start Source Select Register (GTSSR)
Address(es): GPT320.GTSSR 4007 8010h
GPT16m.GTSSR 4007 8010h + 0100h × m (m = 1 to 6)
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
SSELC SSELC SSELC SSELC
D
C
B
A
CSTRT
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Value after reset:
SSCBF SSCBF SSCBR SSCBR SSCAF SSCAF SSCAR SSCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
0
0
0
0
0
0
0
SSGTR SSGTR SSGTR SSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSGTRGAR
GTETRGA Pin Rising Input Source
Counter Start Enable
0: Disable counter start on the rising edge of GTETRGA
input
1: Enable counter start on the rising edge of GTETRGA
input.
R/W
b1
SSGTRGAF
GTETRGA Pin Falling Input Source
Counter Start Enable
0: Disable counter start on the falling edge of GTETRGA
input
1: Enable counter start on the falling edge of GTETRGA
input.
R/W
b2
SSGTRGBR
GTETRGB Pin Rising Input Source
Counter Start Enable
0: Disable counter start on the rising edge of GTETRGB
input
1: Enable counter start on the rising edge of GTETRGB
input.
R/W
b3
SSGTRGBF
GTETRGB Pin Falling Input Source
Counter Start Enable
0: Disable counter start on the falling edge of GTETRGB
input
1: Enable counter start on the falling edge of GTETRGB
input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
SSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Start Enable
0: Disable counter start on the rising edge of GTIOCA input
when GTIOCB input is 0
1: Enable counter start on the rising edge of GTIOCA input
when GTIOCB input is 0.
R/W
b9
SSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Start Enable
0: Disable counter start on the rising edge of GTIOCA input
when GTIOCB input is 1
1: Enable counter start on the rising edge of GTIOCA input
when GTIOCB input is 1.
R/W
b10
SSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Start Enable
0: Disable counter start on the falling edge of GTIOCA input
when GTIOCB input is 0
1: Enable counter start on the falling edge of GTIOCA input
when GTIOCB input is 0.
R/W
b11
SSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Start Enable
0: Disable counter start on the falling edge of GTIOCA input
when GTIOCB input is 1
1: Enable counter start on the falling edge of GTIOCA input
when GTIOCB input is 1.
R/W
b12
SSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Start Enable
0: Disable counter start on the rising edge of GTIOCB input
when GTIOCA input is 0
1: Enable counter start on the rising edge of GTIOCB input
when GTIOCA input is 0.
R/W
b13
SSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Start Enable
0: Disable counter start on the rising edge of GTIOCB input
when GTIOCA input is 1
1: Enable counter start on the rising edge of GTIOCB input
when GTIOCA input is 1.
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b14
SSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Start Enable
0: Disable counter start on the falling edge of GTIOCB input
when GTIOCA input is 0
1: Enable counter start on the falling edge of GTIOCB input
when GTIOCA input is 0.
R/W
b15
SSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Start Enable
0: Disable counter start on the falling edge of GTIOCB input
when GTIOCA input is 1
1: Enable counter start on the falling edge of GTIOCB input
when GTIOCA input is 1.
R/W
b16
SSELCA
ELC_GPTA Event Source Counter
Start Enable
0: Disable counter start on the ELC_GPTA event input
1: Enable counter start on the ELC_GPTA event input.
R/W
b17
SSELCB
ELC_GPTB Event Source Counter
Start Enable
0: Disable counter start on the ELC_GPTB event input
1: Enable counter start on the ELC_GPTB event input.
R/W
b18
SSELCC
ELC_GPTC Event Source Counter
Start Enable
0: Disable counter start on the ELC_GPTC event input
1: Enable counter start on the ELC_GPTC event input.
R/W
b19
SSELCD
ELC_GPTD Event Source Counter
Start Enable
0: Disable counter start on the ELC_GPTD event input
1: Enable counter start on the ELC_GPTD event input.
R/W
b30 to b20 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Start
Enable
0: Disable counter start by the GTSTR register
1: Enable counter start by the GTSTR register.
R/W
CSTRT
GTSSR sets the source to start the GTCNT counter.
SSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the rising edge of the GTETRGA pin input.
SSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the falling edge of the GTETRGA pin input.
SSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the rising edge of the GTETRGB pin input.
SSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the falling edge of the GTETRGB pin input.
SSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the rising edge of the GTIOCA pin input, when the GTIOCB input
is 0.
SSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the rising edge of the GTIOCA pin input, when the GTIOCB input
is 1.
SSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the falling edge of the GTIOCA pin input, when the GTIOCB input
is 0.
SSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the falling edge of the GTIOCA pin input, when the GTIOCB input
is 1.
SSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the rising edge of the GTIOCB pin input, when the GTIOCA input
is 0.
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19. General PWM Timer (GPT)
SSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the rising edge of the GTIOCB pin input, when the GTIOCA input
is 1.
SSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the falling edge of the GTIOCB pin input, when the GTIOCA input
is 0.
SSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable)
This bit enables or disables GTCNT counter start on the falling edge of the GTIOCB pin input, when the GTIOCA input
is 1.
SSELCm bit (ELC_GPTm Event Source Counter Start Enable) (m = A to D)
This bit enables or disables GTCNT counter start at the ELC_GPTm event input.
CSTRT bit (Software Source Counter Start Enable)
This bit enables or disables GTCNT counter start by GTSTR register.
19.2.6
General PWM Timer Stop Source Select Register (GTPSR)
Address(es): GPT320.GTPSR 4007 8014h
GPT16m.GTPSR 4007 8014h + 0100h × m (m = 1 to 6)
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PSELC PSELC PSELC PSELC
D
C
B
A
CSTOP
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Value after reset:
PSCBF PSCBF PSCBR PSCBR PSCAF PSCAF PSCAR PSCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
0
0
0
0
0
0
0
PSGTR PSGTR PSGTR PSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PSGTRGAR
GTETRGA Pin Rising Input Source
Counter Stop Enable
0: Disable counter stop on the rising edge of GTETRGA
input
1: Enable counter stop on the rising edge of GTETRGA
input.
R/W
b1
PSGTRGAF
GTETRGA Pin Falling Input Source
Counter Stop Enable
0: Disable counter stop on the falling edge of GTETRGA
input
1: Enable counter stop on the falling edge of GTETRGA
input.
R/W
b2
PSGTRGBR
GTETRGB Pin Rising Input Source
Counter Stop Enable
0: Disable counter stop on the rising edge of GTETRGB
input
1: Enable counter stop on the rising edge of GTETRGB
input.
R/W
b3
PSGTRGBF
GTETRGB Pin Falling Input Source
Counter Stop Enable
0: Disable counter stop on the falling edge of GTETRGB
input
1: Enable counter stop on the falling edge of GTETRGB
input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
PSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Stop Enable
0: Disable counter stop on the rising edge of GTIOCA input
when GTIOCB input is 0
1: Enable counter stop on the rising edge of GTIOCA input
when GTIOCB input is 0.
R/W
R01UM0003EU0130 Rev.1.30
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b9
PSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Stop Enable
0: Disable counter stop on the rising edge of GTIOCA input
when GTIOCB input is 1
1: Enable counter stop on the rising edge of GTIOCA input
when GTIOCB input is 1.
R/W
b10
PSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Stop Enable
0: Disable counter stop on the falling edge of GTIOCA input
when GTIOCB input is 0
1: Enable counter stop on the falling edge of GTIOCA input
when GTIOCB input is 0.
R/W
b11
PSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Stop Enable
0: Disable counter stop on the falling edge of GTIOCA input
when GTIOCB input is 1
1: Enable counter stop on the falling edge of GTIOCA input
when GTIOCB input is 1.
R/W
b12
PSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Stop Enable
0: Disable counter stop on the rising edge of GTIOCB input
when GTIOCA input is 0
1: Enable counter stop on the rising edge of GTIOCB input
when GTIOCA input is 0.
R/W
b13
PSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Stop Enable
0: Disable counter stop on the rising edge of GTIOCB input
when GTIOCA input is 1
1: Enable counter stop on the rising edge of GTIOCB input
when GTIOCA input is 1.
R/W
b14
PSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Stop Enable
0: Disable counter stop on the falling edge of GTIOCB input
when GTIOCA input is 0
1: Enable counter stop on the falling edge of GTIOCB input
when GTIOCA input is 0.
R/W
b15
PSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Stop Enable
0: Disable counter stop on the falling edge of GTIOCB input
when GTIOCA input is 1
1: Enable counter stop on the falling edge of GTIOCB input
when GTIOCA input is 1.
R/W
b16
PSELCA
ELC_GPTA Event Source Counter
Stop Enable
0: Disable counter stop at the ELC_GPTA event input
1: Enable counter stop at the ELC_GPTA event input.
R/W
b17
PSELCB
ELC_GPTB Event Source Counter
Stop Enable
0: Disable counter stop at the ELC_GPTB event input
1: Enable counter stop at the ELC_GPTB event input.
R/W
b18
PSELCC
ELC_GPTC Event Source Counter
Stop Enable
0: Disable counter stop at the ELC_GPTC event input
1: Enable counter stop at the ELC_GPTC event input.
R/W
b19
PSELCD
ELC_GPTD Event Source Counter
Stop Enable
0: Disable counter stop at the ELC_GPTD event input
1: Enable counter stop at the ELC_GPTD event input.
R/W
b30 to b20 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Stop
Enable
0: Disable counter stop by the GTSTP register
1: Enable counter stop by the GTSTP register.
R/W
CSTOP
GTPSR sets the source to stop the GTCNT counter.
PSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the rising edge of the GTETRGA pin input.
PSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the falling edge of the GTETRGA pin input.
PSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the rising edge of the GTETRGB pin input.
PSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the falling edge of the GTETRGB pin input.
PSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCA pin input, when the GTIOCB
input is 0.
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19. General PWM Timer (GPT)
PSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCA pin input, when the GTIOCB
input is 1.
PSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCA pin input, when the GTIOCB
input is 0.
PSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCA pin input, when the GTIOCB
input is 1.
PSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCB pin input, when the GTIOCA
input is 0.
PSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCB pin input, when the GTIOCA
input is 1.
PSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCB pin input, when the GTIOCA
input is 0.
PSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCB pin input, when the GTIOCA
input is 1.
PSELCm bit (ELC_GPTm Event Source Counter Stop Enable) (m = A to D)
This bit enables or disables the GTCNT counter stop at the ELC_GPTm event input.
CSTOP bit (Software Source Counter Stop Enable)
This bit enables or disables the GTCNT counter stop by the GTSTP register.
19.2.7
General PWM Timer Clear Source Select Register (GTCSR)
Address(es): GPT320.GTCSR 4007 8018h
GPT16m.GTCSR 4007 8018h + 0100h × m (m = 1 to 6)
b31
Value after reset:
b30
b29
b28
b27
b26
b25
b24
b22
b21
b20
b19
b18
b17
b16
CSELC CSELC CSELC CSELC
D
C
B
A
CCLR
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
CSCBF CSCBF CSCBR CSCBR CSCAF CSCAF CSCAR CSCAR
AH
AL
AH
AL
BH
BL
BH
BL
Value after reset:
b23
0
0
0
0
0
0
0
0
CSGTR CSGTR CSGTR CSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CSGTRGAR
GTETRGA Pin Rising Input Source
Counter Clear Enable
0: Disable counter clear on the rising edge of GTETRGA
input
1: Enable counter clear on the rising edge of GTETRGA
input.
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b1
CSGTRGAF
GTETRGA Pin Falling Input Source
Counter Clear Enable
0: Disable counter clear on the falling edge of GTETRGA
input
1: Enable counter clear on the falling edge of GTETRGA
input.
R/W
b2
CSGTRGBR
GTETRGB Pin Rising Input Source
Counter Clear Enable
0: Disable counter clear on the rising edge of GTETRGB
input
1: Enable counter clear on the rising edge of GTETRGB
input.
R/W
b3
CSGTRGBF
GTETRGB Pin Falling Input Source
Counter Clear Enable
0: Disable counter clear on the falling edge of GTETRGB
input
1: Enable counter clear on the falling edge of GTETRGB
input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
CSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Clear Enable
0: Disable counter clear on the rising edge of GTIOCA input
when GTIOCB input is 0
1: Enable counter clear on the rising edge of GTIOCA input
when GTIOCB input is 0.
R/W
b9
CSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Clear Enable
0: Disable counter clear on the rising edge of GTIOCA input
when GTIOCB input is 1
1: Enable counter clear on the rising edge of GTIOCA input
when GTIOCB input is 1.
R/W
b10
CSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Clear Enable
0: Disable counter clear on the falling edge of GTIOCA
input when GTIOCB input is 0
1: Enable counter clear on the falling edge of GTIOCA input
when GTIOCB input is 0.
R/W
b11
CSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Clear Enable
0: Disable counter clear on the falling edge of GTIOCA
input when GTIOCB input is 1
1: Enable counter clear on the falling edge of GTIOCA input
when GTIOCB input is 1.
R/W
b12
CSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Clear Enable
0: Disable counter clear on the rising edge of GTIOCB input
when GTIOCA input is 0
1: Enable counter clear on the rising edge of GTIOCB input
when GTIOCA input is 0.
R/W
b13
CSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Clear Enable
0: Disable counter clear on the rising edge of GTIOCB input
when GTIOCA input is 1
1: Enable counter clear on the rising edge of GTIOCB input
when GTIOCA input is 1.
R/W
b14
CSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Clear Enable
0: Disable counter clear on the falling edge of GTIOCB
input when GTIOCA input is 0
1: Enable counter clear on the falling edge of GTIOCB input
when GTIOCA input is 0.
R/W
b15
CSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Clear Enable
0: Disable counter clear on the falling edge of GTIOCB
input when GTIOCA input is 1
1: Enable counter clear on the falling edge of GTIOCB input
when GTIOCA input is 1.
R/W
b16
CSELCA
ELC_GPTA Event Source Counter
Clear Enable
0: Disable counter clear at the ELC_GPTA event input
1: Enable counter clear at the ELC_GPTA event input.
R/W
b17
CSELCB
ELC_GPTB Event Source Counter
Clear Enable
0: Disable counter clear at the ELC_GPTB event input
1: Counter clear is enabled at the ELC_GPTB event input.
R/W
b18
CSELCC
ELC_GPTC Event Source Counter
Clear Enable
0: Disable counter clear at the ELC_GPTC event input
1: Enable counter clear at the ELC_GPTC event input.
R/W
b19
CSELCD
ELC_GPTD Event Source Counter
Clear Enable
0: Disable counter clear at the ELC_GPTD event input
1: Enable counter clear at the ELC_GPTD event input.
R/W
b30 to b20 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31
Software Source Counter Clear
Enable
0: Disable counter clear by the GTCLR register
1: Enable counter clear by the GTCLR register.
R/W
CCLR
GTCSR sets the source to clear the GTCNT counter.
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19. General PWM Timer (GPT)
CSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the rising edge of the GTETRGA pin input.
CSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the falling edge of the GTETRGA pin input.
CSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the rising edge of the GTETRGB pin input.
CSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the falling edge of the GTETRGB pin input.
CSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the rising edge of the GTIOCA pin input, when the GTIOCB
input is 0.
CSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the rising edge of the GTIOCA pin input, when the GTIOCB
input is 1.
CSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCA pin input, when the GTIOCB
input is 0.
CSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCA pin input, when the GTIOCB
input is 1.
CSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the rising edge of the GTIOCB pin input, when the GTIOCA
input is 0.
CSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the rising edge of the GTIOCB pin input, when the GTIOCA
input is 1.
CSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCB pin input, when the GTIOCA
input is 0.
CSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCB pin input, when the GTIOCA
input is 1.
CSELCm bit (ELC_GPTm Event Source Counter Clear Enable) (m = A to D)
This bit enables or disables the GTCNT counter clear at the ELC_GPTm event input.
CCLR bit (Software Source Counter Clear Enable)
This bit enables or disables the GTCNT counter clear by the GTCLR register.
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19.2.8
19. General PWM Timer (GPT)
General PWM Timer Up Count Source Select Register (GTUPSR)
Address(es): GPT320.GTUPSR 4007 801Ch
GPT16m.GTUPSR 4007 801Ch + 0100h × m (m = 1 to 6)
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
USELC USELC USELC USELC
D
C
B
A
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Value after reset:
USCBF USCBF USCBR USCBR USCAF USCAF USCAR USCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
0
0
0
0
0
0
0
USGTR USGTR USGTR USGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
USGTRGAR
GTETRGA Pin Rising Input Source
Counter Count Up Enable
0: Disable counter count up on the rising edge of
GTETRGA input
1: Enable counter count up on the rising edge of
GTETRGA input.
R/W
b1
USGTRGAF
GTETRGA Pin Falling Input Source
Counter Count Up Enable
0: Disable counter count up on the falling edge of
GTETRGA input
1: Enable counter count up on the falling edge of
GTETRGA input.
R/W
b2
USGTRGBR
GTETRGB Pin Rising Input Source
Counter Count Up Enable
0: Disable counter count up on the rising edge of
GTETRGB input
1: Enable counter count up on the rising edge of
GTETRGB input.
R/W
b3
USGTRGBF
GTETRGB Pin Falling Input Source
Counter Count Up Enable
0: Disable counter count up on the falling edge of
GTETRGB input
1: Enable counter count up on the falling edge of
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
USCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Count Up Enable
0: Disable counter count up on the rising edge of GTIOCA
input when GTIOCB input is 0
1: Enable counter count up on the rising edge of GTIOCA
input when GTIOCB input is 0.
R/W
b9
USCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Count Up Enable
0: Disable counter count up on the rising edge of GTIOCA
input when GTIOCB input is 1
1: Enable counter count up on the rising edge of GTIOCA
input when GTIOCB input is 1.
R/W
b10
USCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Count Up Enable
0: Disable counter count up on the falling edge of GTIOCA
input when GTIOCB input is 0
1: Enable counter count up on the falling edge of GTIOCA
input when GTIOCB input is 0.
R/W
b11
USCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Count Up Enable
0: Disable counter count up on the falling edge of GTIOCA
input when GTIOCB input is 1
1: Enable counter count up on the falling edge of GTIOCA
input when GTIOCB input is 1.
R/W
b12
USCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Count Up Enable
0: Disable counter count up on the rising edge of GTIOCB
input when GTIOCA input is 0
1: Enable counter count up on the rising edge of GTIOCB
input when GTIOCA input is 0.
R/W
b13
USCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Count Up Enable
0: Disable counter count up on the rising edge of GTIOCB
input when GTIOCA input is 1
1: Enable counter count up on the rising edge of GTIOCB
input when GTIOCA input is 1.
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b14
USCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Count Up Enable
0: Disable counter count up on the falling edge of GTIOCB
input when GTIOCA input is 0
1: Enable counter count up on the falling edge of GTIOCB
input when GTIOCA input is 0.
R/W
b15
USCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Count Up Enable
0: Disable counter count up on the falling edge of GTIOCB
input when GTIOCA input is 1
1: Enable counter count up on the falling edge of GTIOCB
input when GTIOCA input is 1.
R/W
b16
USELCA
ELC_GPTA Event Source Counter
Count Up Enable
0: Disable counter count up at the ELC_GPTA event input
1: Enable counter count up at the ELC_GPTA event input.
R/W
b17
USELCB
ELC_GPTB Event Source Counter
Count Up Enable
0: Disable counter count up at the ELC_GPTB event input
1: Enable counter count up at the ELC_GPTB event input.
R/W
b18
USELCC
ELC_GPTC Event Source Counter
Count Up Enable
0: Disable counter count up at the ELC_GPTC event input
1: Enable counter count up at the ELC_GPTC event input.
R/W
b19
USELCD
ELC_GPTD Event Source Counter
Count Up Enable
0: Disable counter count up at the ELC_GPTD event input
1: Enable counter count up at the ELC_GPTD event input.
R/W
b31 to b20
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
GTUPSR sets the source to count up the GTCNT counter.
When at least 1 bit in the GTUPSR register is set to 1, the GTCNT counter is counted up by the source that is set to 1 in
this register. In this case, the count of the GTCNT counter set by GTCR.TPCS is not performed.
USGTRGAR bit (GTETRGA Pin Rising Input Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the rising edge of the GTETRGA pin input.
USGTRGAF bit (GTETRGA Pin Falling Input Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the falling edge of the GTETRGA pin input.
USGTRGBR bit (GTETRGB Pin Rising Input Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the rising edge of the GTETRGB pin input.
USGTRGBF bit (GTETRGB Pin Falling Input Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the falling edge of the GTETRGB pin input.
USCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable)
This bit enables or disables GTCNT counter count up on the rising edge of GTIOCA pin input, when GTIOCB input is 0.
USCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the rising edge of the GTIOCA pin input, when the
GTIOCB input is 1.
USCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 0.
USCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 1.
USCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 0.
USCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the rising edge of the GTIOCB pin input, when the
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19. General PWM Timer (GPT)
GTIOCA input is 1.
USCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 0.
USCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable)
This bit enables or disables the GTCNT counter count up on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 1.
USELCm bit (ELC_GPTm Event Source Counter Count Up Enable) (m = A to D)
This bit enables or disables the GTCNT counter count up at the ELC_GPTm event input.
19.2.9
General PWM Timer Down Count Source Select Register (GTDNSR)
Address(es): GPT320.GTDNSR 4007 8020h
GPT16m.GTDNSR 4007 8020h + 0100h × m (m = 1 to 6)
b31
Value after reset:
b30
b29
b28
b27
b26
b25
b24
b22
b21
b20
b19
b18
b17
b16
DSELC DSELC DSELC DSELC
D
C
B
A
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
DSCBF DSCBF DSCBR DSCBR DSCAF DSCAF DSCAR DSCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
b23
0
0
0
0
0
0
0
DSGTR DSGTR DSGTR DSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DSGTRGAR
GTETRGA Pin Rising Input Source
Counter Count Down Enable
0: Disable counter count down on the rising edge of
GTETRGA input
1: Enable counter count down on the rising edge of
GTETRGA input.
R/W
b1
DSGTRGAF
GTETRGA Pin Falling Input Source
Counter Count Down Enable
0: Disable counter count down on the falling edge of
GTETRGA input
1: Enable counter count down on the falling edge of
GTETRGA input.
R/W
b2
DSGTRGBR
GTETRGB Pin Rising Input Source
Counter Count Down Enable
0: Disable counter count down on the rising edge of
GTETRGB input
1: Enable counter count down on the rising edge of
GTETRGB input.
R/W
b3
DSGTRGBF
GTETRGB Pin Falling Input Source
Counter Count Down Enable
0: Disable counter count down on the falling edge of
GTETRGB input
1: Enable counter count down on the falling edge of
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
DSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
Counter Count Down Enable
0: Disable counter count down on the rising edge of
GTIOCA input when GTIOCB input is 0
1: Enable counter count down on the rising edge of
GTIOCA input when GTIOCB input is 0.
R/W
b9
DSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
Counter Count Down Enable
0: Disable counter count down on the rising edge of
GTIOCA input when GTIOCB input is 1
1: Enable counter count down on the rising edge of
GTIOCA input when GTIOCB input is 1.
R/W
b10
DSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
Counter Count Down Enable
0: Disable counter count down on the falling edge of
GTIOCA input when GTIOCB input is 0
1: Enable counter count down on the falling edge of
GTIOCA input when GTIOCB input is 0.
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b11
DSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
Counter Count Down Enable
0: Disable counter count down on the falling edge of
GTIOCA input when GTIOCB input is 1
1: Enable counter count down on the falling edge of
GTIOCA input when GTIOCB input is 1.
R/W
b12
DSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
Counter Count Down Enable
0: Disable counter count down on the rising edge of
GTIOCB input when GTIOCA input is 0
1: Enable counter count down on the rising edge of
GTIOCB input when GTIOCA input is 0.
R/W
b13
DSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
Counter Count Down Enable
0: Disable counter count down on the rising edge of
GTIOCB input when GTIOCA input is 1
1: Enable counter count down on the rising edge of
GTIOCB input when GTIOCA input is 1.
R/W
b14
DSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
Counter Count Down Enable
0: Disable counter count down on the falling edge of
GTIOCB input when GTIOCA input is 0
1: Enable counter count down on the falling edge of
GTIOCB input when GTIOCA input is 0.
R/W
b15
DSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
Counter Count Down Enable
0: Disable counter count down on the falling edge of
GTIOCB input when GTIOCA input is 1
1: Enable counter count down on the falling edge of
GTIOCB input when GTIOCA input is 1
R/W
b16
DSELCA
ELC_GPTA Event Source Counter
Count Down Enable
0: Disable counter count down at the ELC_GPTA event
input
1: Enable counter count down at the ELC_GPTA event
input
R/W
b17
DSELCB
ELC_GPTB Event Source Counter
Count Down Enable
0: Disable counter count down at the ELC_GPTB event
input
1: Enable counter count down at the ELC_GPTB event
input.
R/W
b18
DSELCC
ELC_GPTC Event Source Counter
Count Down Enable
0: Disable counter count down at the ELC_GPTC event
input
1: Enable counter count down at the ELC_GPTC event
input.
R/W
b19
DSELCD
ELC_GPTD Event Source Counter
Count Down Enable
0: Disable counter count down at the ELC_GPTD event
input
1: Enable counter count down at the ELC_GPTD event
input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b20 —
GTDNSR sets the source to count down the GTCNT counter.
When at least 1 bit in the GTDNSR register is set to 1, the GTCNT counter is counted down by the source that is set to 1
in this register. In this case, the count of the GTCNT counter set by GTCR.TPCS is not performed.
DSGTRGAR bit (GTETRGA Pin Rising Input Source Counter Count Down Enable)
This bit enables or disables the GTCNT counter count down on the rising edge of the GTETRGA pin input.
DSGTRGAF bit (GTETRGA Pin Falling Input Source Counter Count Down Enable)
This bit enables or disables the GTCNT counter count down on the falling edge of the GTETRGA pin input.
DSGTRGBR bit (GTETRGB Pin Rising Input Source Counter Count Down Enable)
This bit enables or disables the GTCNT counter count down on the rising edge of the GTETRGB pin input.
DSGTRGBF bit (GTETRGB Pin Falling Input Source Counter Count Down Enable)
This bit enables or disables the GTCNT counter count down on the falling edge of the GTETRGB pin input.
DSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down
Enable)
This bit enables or disables the GTCNT counter count down on the rising edge of the GTIOCA pin input, when the
GTIOCB input is 0.
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19. General PWM Timer (GPT)
DSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down
Enable)
This bit enables or disables the GTCNT counter count down on the rising edge of the GTIOCA pin input, when the
GTIOCB input is 1.
DSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down
Enable)
This bit enables or disables the GTCNT counter count down on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 0.
DSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down
Enable)
This bit enables or disables the GTCNT counter count down on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 1.
DSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down
Enable)
This bit enables or disables the GTCNT counter count down on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 0.
DSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down
Enable)
This bit enables or disables the GTCNT counter count down on the rising edge of GTIOCB pin input, when the GTIOCA
input is 1.
DSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down
Enable)
This bit enables or disables the GTCNT counter count down on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 0.
DSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down
Enable)
This bit enables or disables the GTCNT counter count down on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 1.
DSELCm bit (ELC_GPTm Event Source Counter Count Down Enable) (m = A to D)
This bit enables or disables the GTCNT counter count down at the ELC_GPTm event input.
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19.2.10
19. General PWM Timer (GPT)
General PWM Timer Input Capture Source Select Register A(GTICASR)
Address(es): GPT320.GTICASR 4007 8024h
GPT16m.GTICASR 4007 8024h + 0100h × m (m = 1 to 6)
b31
Value after reset:
b30
b29
b28
b27
b26
b25
b24
b22
b21
b20
b19
b18
b17
b16
ASELC ASELC ASELC ASELC
D
C
B
A
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
0
0
0
0
ASCBF ASCBF ASCBR ASCBR ASCAF ASCAF ASCAR ASCAR
AH
AL
AH
AL
BH
BL
BH
BL
0
Value after reset:
b23
0
0
0
0
0
0
0
ASGTR ASGTR ASGTR ASGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ASGTRGAR
GTETRGA Pin Rising Input Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the rising edge of
GTETRGA input
1: Enable GTCCRA input capture on the rising edge of
GTETRGA input.
R/W
b1
ASGTRGAF
GTETRGA Pin Falling Input Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the falling edge of
GTETRGA input
1: Enable GTCCRA input capture on the falling edge of
GTETRGA input.
R/W
b2
ASGTRGBR
GTETRGB Pin Rising Input Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the rising edge of
GTETRGB input
1: Enable GTCCRA input capture on the rising edge of
GTETRGB input.
R/W
b3
ASGTRGBF
GTETRGB Pin Falling Input Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the falling edge of
GTETRGB input
1: Enable GTCCRA input capture on the falling edge of
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
ASCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the rising edge of
GTIOCA input when GTIOCB input is 0
1: Enable GTCCRA input capture on the rising edge of
GTIOCA input when GTIOCB input is 0.
R/W
b9
ASCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the rising edge of
GTIOCA input when GTIOCB input is 1
1: Enable GTCCRA input capture on the rising edge of
GTIOCA input when GTIOCB input is 1.
R/W
b10
ASCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the falling edge of
GTIOCA input when GTIOCB input is 0
1: Enable GTCCRA input capture on the falling edge of
GTIOCA input when GTIOCB input is 0.
R/W
b11
ASCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the falling edge of
GTIOCA input when GTIOCB input is 1
1: Enable GTCCRA input capture on the falling edge of
GTIOCA input when GTIOCB input is 1.
R/W
b12
ASCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the rising edge of
GTIOCB input when GTIOCA input is 0
1: Enable GTCCRA input capture on the rising edge of
GTIOCB input when GTIOCA input is 0.
R/W
b13
ASCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the rising edge of
GTIOCB input when GTIOCA input is 1
1: Enable GTCCRA input capture on the rising edge of
GTIOCB input when GTIOCA input is 1.
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b14
ASCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the falling edge of
GTIOCB input when GTIOCA input is 0
1: Enable GTCCRA input capture on the falling edge of
GTIOCB input when GTIOCA input is 0.
R/W
b15
ASCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture on the falling edge of
GTIOCB input when GTIOCA input is 1
1: Enable GTCCRA input capture on the falling edge of
GTIOCB input when GTIOCA input is 1.
R/W
b16
ASELCA
ELC_GPTA Event Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture at the ELC_GPTA event
input
1: Enable GTCCRA input capture at the ELC_GPTA event
input.
R/W
b17
ASELCB
ELC_GPTB Event Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture at the ELC_GPTB event
input
1: Enable GTCCRA input capture at the ELC_GPTB event
input.
R/W
b18
ASELCC
ELC_GPTC Event Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture at the ELC_GPTC event
input
1: Enable GTCCRA input capture at the ELC_GPTC event
input.
R/W
b19
ASELCD
ELC_GPTD Event Source
GTCCRA Input Capture Enable
0: Disable GTCCRA input capture at the ELC_GPTD event
input
1: Enable GTCCRA input capture at the ELC_GPTD event
input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b20 —
GTICASR sets the source of input capture for GTCCRA.
ASGTRGAR bit (GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable)
This bit enables or disables the input capture for GTCCRA on the rising edge of the GTETRGA pin input.
ASGTRGAF bit (GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable)
This bit enables or disables the input capture for GTCCRA on the falling edge of the GTETRGA pin input.
ASGTRGBR bit (GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable)
This bit enables or disables the input capture for GTCCRA on the rising edge of the GTETRGB pin input.
ASGTRGBF bit (GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable)
This bit enables or disables the input capture for GTCCRA on the falling edge of the GTETRGB pin input.
ASCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture
Enable)
This bit enables or disables the input capture for GTCCRA on the rising edge of the GTIOCA pin input, when the
GTIOCB input is 0.
ASCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture
Enable)
This bit enables or disables the input capture for GTCCRA on the rising edge of the GTIOCA pin input, when the
GTIOCB input is 1.
ASCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture
Enable)
This bit enables or disables the input capture for GTCCRA on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 0.
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19. General PWM Timer (GPT)
ASCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture
Enable)
This bit enables or disables the input capture for GTCCRA on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 1.
ASCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture
Enable)
This bit enables or disables the input capture for GTCCRA on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 0.
ASCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture
Enable)
This bit enables or disables the input capture for GTCCRA on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 1.
ASCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture
Enable)
This bit enables or disables the input capture for GTCCRA on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 0.
ASCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture
Enable)
This bit enables or disables the input capture for GTCCRA on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 1.
ASELCm bit (ELC_GPTm Event Source Counter GTCCRA Input Capture Enable) (m = A to D)
This bit enables or disables the input capture for GTCCRA at the ELC_GPTm event input.
19.2.11
General PWM Timer Input Capture Source Select Register B(GTICBSR)
Address(es): GPT320.GTICBSR 4007 8028h
GPT16m.GTICBSR 4007 8028h + 0100h × m (m = 1 to 6)
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
BSCBF BSCBF BSCBR BSCBR BSCAF BSCAF BSCAR BSCAR
AH
AL
AH
AL
BH
BL
BH
BL
Value after reset:
0
0
0
0
0
0
0
0
—
—
—
—
0
0
0
0
b19
b18
b17
b16
BSELC BSELC BSELC BSELC
D
C
B
A
0
0
0
0
b3
b2
b1
b0
BSGTR BSGTR BSGTR BSGTR
GBF
GBR
GAF
GAR
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BSGTRGAR
GTETRGA Pin Rising Input Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the rising edge of
GTETRGA input
1: Enable GTCCRB input capture on the rising edge of
GTETRGA input.
R/W
b1
BSGTRGAF
GTETRGA Pin Falling Input Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the falling edge of
GTETRGA input
1: Enable GTCCRB input capture on the falling edge of
GTETRGA input.
R/W
b2
BSGTRGBR
GTETRGB Pin Rising Input Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the rising edge of
GTETRGB input
1: Enable GTCCRB input capture on the rising edge of
GTETRGB input.
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b3
BSGTRGBF
GTETRGB Pin Falling Input Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the falling edge of
GTETRGB input
1: Enable GTCCRB input capture on the falling edge of
GTETRGB input.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
BSCARBL
GTIOCA Pin Rising Input during
GTIOCB Value Low Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the rising edge of
GTIOCA input when GTIOCB input is 0
1: Enable GTCCRB input capture on the rising edge of
GTIOCA input when GTIOCB input is 0.
R/W
b9
BSCARBH
GTIOCA Pin Rising Input during
GTIOCB Value High Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the rising edge of
GTIOCA input when GTIOCB input is 1
1: Enable GTCCRB input capture on the rising edge of
GTIOCA input when GTIOCB input is 1.
R/W
b10
BSCAFBL
GTIOCA Pin Falling Input during
GTIOCB Value Low Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the falling edge of
GTIOCA input when GTIOCB input is 0
1: Enable GTCCRB input capture on the falling edge of
GTIOCA input when GTIOCB input is 0.
R/W
b11
BSCAFBH
GTIOCA Pin Falling Input during
GTIOCB Value High Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the falling edge of
GTIOCA input when GTIOCB input is 1
1: Enable GTCCRB input capture on the falling edge of
GTIOCA input when GTIOCB input is 1.
R/W
b12
BSCBRAL
GTIOCB Pin Rising Input during
GTIOCA Value Low Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the rising edge of
GTIOCB input when GTIOCA input is 0
1: Enable GTCCRB input capture on the rising edge of
GTIOCB input when GTIOCA input is 0.
R/W
b13
BSCBRAH
GTIOCB Pin Rising Input during
GTIOCA Value High Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the rising edge of
GTIOCB input when GTIOCA input is 1
1: Enable GTCCRB input capture on the rising edge of
GTIOCB input when GTIOCA input is 1.
R/W
b14
BSCBFAL
GTIOCB Pin Falling Input during
GTIOCA Value Low Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the falling edge of
GTIOCB input when GTIOCA input is 0
1: Enable GTCCRB input capture on the falling edge of
GTIOCB input when GTIOCA input is 0.
R/W
b15
BSCBFAH
GTIOCB Pin Falling Input during
GTIOCA Value High Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture on the falling edge of
GTIOCB input when GTIOCA input is 1
1: Enable GTCCRB input capture on the falling edge of
GTIOCB input when GTIOCA input is 1.
R/W
b16
BSELCA
ELC_GPTA Event Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture at the ELC_GPTA event
input
1: Enable GTCCRB input capture at the ELC_GPTA event
input.
R/W
b17
BSELCB
ELC_GPTB Event Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture at the ELC_GPTB event
input
1: Enable GTCCRB input capture at the ELC_GPTB event
input.
R/W
b18
BSELCC
ELC_GPTC Event Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture at the ELC_GPTC event
input
1: Enable GTCCRB input capture at the ELC_GPTC event
input.
R/W
b19
BSELCD
ELC_GPTD Event Source
GTCCRB Input Capture Enable
0: Disable GTCCRB input capture at the ELC_GPTD event
input
1: Enable GTCCRB input capture at the ELC_GPTD event
input.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b20 —
GTICBSR sets the source of input capture for GTCCRB.
BSGTRGAR bit (GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable)
This bit enables or disables the input capture for GTCCRB on the rising edge of the GTETRGA pin input.
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19. General PWM Timer (GPT)
BSGTRGAF bit (GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable)
This bit enables or disables the input capture for GTCCRB on the falling edge of the GTETRGA pin input.
BSGTRGBR bit (GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable)
This bit enables or disables the input capture for GTCCRB on the rising edge of GTETRGB pin input.
BSGTRGBF bit (GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable)
This bit enables or disables the input capture for GTCCRB on the falling edge of the GTETRGB pin input.
BSCARBL bit (GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture
Enable)
This bit enables or disables the input capture for GTCCRB on the rising edge of the GTIOCA pin input, when the
GTIOCB input is 0.
BSCARBH bit (GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture
Enable)
This bit enables or disables the input capture for GTCCRB on the rising edge of the GTIOCA pin input, when the
GTIOCB input is 1.
BSCAFBL bit (GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture
Enable)
This bit enables or disables the input capture for GTCCRB on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 0.
BSCAFBH bit (GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture
Enable)
This bit enables or disables the input capture for GTCCRB on the falling edge of the GTIOCA pin input, when the
GTIOCB input is 1.
BSCBRAL bit (GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture
Enable)
This bit enables or disables the input capture for GTCCRB on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 0.
BSCBRAH bit (GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture
Enable)
This bit enables or disables the input capture for GTCCRB on the rising edge of the GTIOCB pin input, when the
GTIOCA input is 1.
BSCBFAL bit (GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture
Enable)
This bit enables or disables the input capture for GTCCRB on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 0.
BSCBFAH bit (GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture
Enable)
This bit enables or disables the input capture for GTCCRB on the falling edge of the GTIOCB pin input, when the
GTIOCA input is 1.
BSELCm bit (ELC_GPTm Event Source Counter GTCCRB Input Capture Enable) (m = A to D)
This bit enables or disables the input capture for GTCCRB at the ELC_GPTm event input.
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Page 284 of 1104
S124 User’s Manual
19.2.12
19. General PWM Timer (GPT)
General PWM Timer Control Register (GTCR)
Address(es): GPT320.GTCR 4007 802Ch
GPT16m.GTCR 4007 802Ch + 0100h × m (m = 1 to 6)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
—
—
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
—
—
—
—
—
0
0
0
0
0
b24
b23
b22
b21
b20
b19
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
CST
0
0
0
0
0
0
0
0
0
0
0
TPCS[2:0]
b18
b17
b16
MD[2:0]
Bit
Symbol
Bit name
Description
R/W
b0
CST
Count Start
0: Stop count operation
1: Perform count operation.
R/W
b15 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Mode Select
b18
R/W
b23 to b19 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b26 to b24 TPCS[2:0]
Timer Prescaler Select
b26
R/W
b31 to b27 —
Reserved
These bits are read as 0. The write value should be 0.
b18 to b16 MD[2:0]
b16
0 0 0: Saw-wave PWM mode (single buffer or double
buffer possible)
0 0 1: Saw-wave one-shot pulse mode (fixed buffer
operation)
0 1 0: Setting prohibited
0 1 1: Setting prohibited
1 0 0: Triangle-wave PWM mode 1 (32-bit transfer at
trough) (single buffer or double buffer is possible)
1 0 1: Triangle-wave PWM mode 2 (32-bit transfer at crest
and trough) (single buffer or double buffer is
possible)
1 1 0: Triangle-wave PWM mode 3 (64-bit transfer at
trough) fixed buffer operation)
1 1 1: Setting prohibited.
0
0
0
0
1
1
0
0
1
1
0
0
b24
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64
0: PCLKD/256
1: PCLKD/1024.
R/W
GTCR controls GTCNT.
CST bit (Count Start)
The CST bit controls the GTCNT counter start and stop.
[Setting conditions]
GTSTR value where the channel number associated with the bit number is set to 1 with the GTSSR.CSTRT bit = 1
The ELC event input or the GTIOCA/GTIOCB/GTETRGn port input that are enabled by GTSSR for starting
counter source, occurs
1 is written by software directly.
[Clearing conditions]
GTSTP value where the channel number associated with the bit number is set to 1 with the GTSSR.CSTOP bit = 1
The ELC event input or the GTIOCA/GTIOCB/GTETRGn port input that are enabled by GTSSR for stopping
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19. General PWM Timer (GPT)
counter source, occurs
0 is written by software directly.
MD[2:0] bits (Mode Select)
The MD[2:0] bits select the GPT operating mode. The MD[2:0] bits must be set when the GTCNT operation is stopped.
TPCS[2:0] bits (Timer Prescaler Select)
The TPCS[2:0] bits select the clock for GTCNT. A clock prescaler can be selected independently for each channel. The
TPCS[2:0] bits should be set while the GTCNT operation is stopped.
19.2.13
General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC)
Address(es): GPT320.GTUDDTYC 4007 8030h
GPT16m.GTUDDTYC 4007 8030h + 0100h × m (m = 1 to 6)
b31
b30
b29
b28
b27
b26
OBDTY OBDTY
R
F
b25
OBDTY[1:0]
b22
b21
b20
b19
b18
OADTY OADTY
R
F
b17
b16
OADTY[1:0]
—
—
—
0
0
0
0
0
0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
UDF
UD
0
0
0
0
0
0
0
0
0
0
1
—
—
—
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
—
—
—
—
—
0
0
0
0
0
Value after reset:
b23
—
—
Value after reset:
b24
Bit
Symbol
Bit name
Description
R/W
b0
UD
Count Direction Setting
0: Count down on GTCNT
1: Count up on GTCNT.
R/W
b1
UDF
Forcible Count Direction
Setting
0: Do not force setting
1: Force setting.
R/W
b15 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b17, 16
OADTY[1:0]
GTIOCA Output Duty Setting
b17 b16
R/W
b18
OADTYF
Forcible GTIOCA Output Duty
Setting
0: Do not force setting
1: Force setting.
R/W
b19
OADTYR
GTIOCA Output Value
Selecting after Releasing
0%/100% Duty Setting
0: Apply output value set in 0%/100% duty to GTIOA[3:2]
function after releasing 0%/100% duty setting
1: Apply masked compare match output value to GTIOA[3:2]
function after releasing 0%/100% duty setting.
R/W
b23 to b20 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25, b24
OBDTY[1:0]
GTIOCB Output Duty Setting
b25 b24
R/W
b26
OBDTYF
Forcible GTIOCB Output Duty
Setting
0: Do not force setting
1: Force setting.
R/W
b27
OBDTYR
GTIOCB Output Value
Selecting after Releasing
0%/100% Duty Setting
0: Apply output value set in 0%/100% duty to GTIOB[3:2]
function after releasing 0%/100% duty setting
1: Apply masked compare match output value to GTIOB[3:2]
function after releasing 0%/100% duty setting.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b31 to b28 —
0
1
1
0
1
1
x: GTIOCA pin duty depends on compare match
0: GTIOCA pin duty 0%
1: GTIOCA pin duty 100%.
x: GTIOCB pin duty is depended on the compare match
0: GTIOCB pin duty 0%
1: GTIOCB pin duty 100%.
x: Don’t care
GTUDDTYC sets the direction in which the GTCNT counts (up-counting or down-counting) and sets the duty of the
GTIOCA/GTIOCB pin output.
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19. General PWM Timer (GPT)
Count Direction:
In saw-wave mode.
When the UD value is set to 0 during up-counting, the count direction changes at an overflow (the timing synchronous
with count clock after the GTCNT value becomes the GTPR value). When the UD value is set to 1 during downcounting, the count direction changes at an underflow (the timing synchronous with count clock after the GTCNT value
becomes 0).
When the UD value changes from 1 to 0 with the UDF bit being 0 and while counting stops, the counter starts upcounting and the count direction changes at an overflow (the timing synchronous with count clock after the GTCNT
value becomes the GTPR value). When the UD value changes from 0 to 1 with the UDF bit being 0 and while counting
stops, the counter starts down-counting and the count direction changes at an underflow (the timing synchronous with
count clock after the GTCNT value becomes 0).
When the UDF bit is set to 1 while counting stops, the UD bit value at that time is reflected in the count direction when
counting starts.
In triangle-wave mode.
When the UD value changes during counting, the count direction does not change. When the UD value changes while the
UDF bit is 0 and counting stops, the change is not reflected in the count direction when counting starts.
When the UDF bit is set to 1 while counting is stopped, the UD value at that time is reflected in the count direction when
counting starts.
UD bit (Count Direction Setting)
The UD bit sets the count direction (up-counting or down-counting) for GTCNT.
UDF bit (Forcible Count Direction Setting)
The UDF bit forcibly sets the count direction when GTCNT starts operation as the UD value. Only 0 should be written to
this bit during counter operation. When 1 is written to this bit while counting stops, this bit must be returned to 0 before
counting starts.
Output duty
In saw-wave mode.
When the OADTY/OBDTY value is changed during up-counting, the duty is reflected at an overflow (GTCNT =
GTPR). When the OADTY/OBDTY value is changed during down-counting, the duty is reflected at an underflow
(GTCNT = 0).
When the OADTY/OBDTY value is changed to 1 with the OADTYF/OBDTYF bit being 0 and while counting stops the
output duty is not reflected at the starting counter operation. When the count direction is up, the output duty is reflected
at an overflow (GTCNT = GTPR). When the count direction is down, the output duty is reflected at an underflow
(GTCNT = 0).
When the OADTY/OBDTY value is changed to 0 with the OADTYF/OBDTYF bit being 1 and while counting stops, the
output duty is reflected at starting counter operation.
In triangle-wave mode.
When the OADTY/OBDTY value is changed during counting, the duty is reflected at an underflow.
When the OADTY/OBDTY value is changed to 1 with the OADTYF/OBDTYF bit being 0 and while counting stops, the
output duty is not reflected at the starting counter operation. The output duty is reflected at an underflow.
When the OADTY/OBDTY value is changed to 0 with the OADTYF/OBDTYF bit being 1 and while counting stops, the
output duty is reflected at starting counter operation.
OmDTY[1:0] bits (GTIOCm Output Duty Setting) (m = A, B)
These bits set the output duty (0%, 100% or compare match control) of the GTIOCm pin.
OmDTYF bit (ForcibleGTIOCm Output Duty Setting) (m = A, B)
This bit forcibly sets the output duty cycle to the OmDTY setting. This bit must be set to 0 during counter operation.
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19. General PWM Timer (GPT)
When this bit is set to 1 while counting stops, this bit must be returned to 0 until the first period ends after the counter
starts.
OmDTYR bit (GTIOCm Output Value Selecting after Releasing 0%/100% Duty Setting) (m = A, B)
These bits select the value that is the object of output retained/toggled at cycle end, when the control changes from 0%/
100% duty setting to compare match for GTIOCm pin and GTIOR.GTIOm[3:2] are set to 00b (output retained at cycle
end) or GTIOR.GTIOm[3:2] are set to 11b (output toggled at cycle end).
GPT internally continues to perform the compare match operation in performing 0%/100% duty operation. When
OmDTYR bit is set to 1, the value of the compare match at cycle end is applied to GTIOR.GTIOm[3:2].
19.2.14
General PWM Timer I/O Control Register (GTIOR)
Address(es): GPT320.GTIOR 4007 8034h
GPT16m.GTIOR 4007 8034h + 0100h × m (m = 1 to 6)
b31
b30
NFCSB[1:0]
Value after reset:
b28
b27
b26
b25
NFBEN
—
—
OBDF[1:0]
b24
OBE
b23
b22
OBHLD OBDFL
T
b21
b20
b19
—
b18
b17
b16
GTIOB[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NFCSA[1:0]
0
Value after reset:
b29
0
NFAEN
—
—
OADF[1:0]
0
0
0
0
OAE
0
OAHLD OADFL
T
0
0
0
—
0
GTIOA[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
GTIOA[4:0]
GTIOCA Pin Function Select
See Table 19.5.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
OADFLT
GTIOCA Pin Output Value
Setting at the Count Stop
0: Output low on GTIOCA pin when counting stops
1: Output high on GTIOCA pin when counting stops.
R/W
b7
OAHLD
GTIOCA Pin Output Setting at
the Start/Stop Count
0: Set GTIOCA pin output level on counting start and stop
based on the register setting
1: Retain GTIOCA pin output level on counting start and stop.
R/W
b8
OAE
GTIOCA Pin Output Enable
0: Disable output
1: Enable output.
R/W
b10, b9
OADF[1:0]
GTIOCA Pin Disable Value
Setting
b10 b9
R/W
b12, b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13
NFAEN
Noise Filter A Enable
0: Disable noise filter for GTIOCA pin
1: Enable noise filter for GTIOCA pin.
R/W
b15, b14
NFCSA[1:0]
Noise Filter A Sampling Clock
Select
b15 b14
R/W
0 0: Output disable is prohibited
0 1: GTIOCA pin is set to Hi-Z when output disable is
performed
1 0: GTIOCA pin is set to 0 when output disable is
performed
1 1: GTIOCA pin is set to 1 when output disable is
performed.
0
0
1
1
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
b20 to b16 GTIOB[4:0]
GTIOCB Pin Function Select
See Table 19.5
R/W
b21
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b22
OBDFLT
GTIOCB Pin Output Value
Setting at the Count Stop
0: Output low on GTIOCB pin when counting stops
1: Output high on GTIOCB pin when counting stops.
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b23
OBHLD
GTIOCB Pin Output Setting at
the Start/Stop Count
0: Set GTIOCB pin output level on counting start and stop
based on the register setting
1: Retain GTIOCB pin output level on counting start and stop.
R/W
b24
OBE
GTIOCB Pin Output Enable
0: Disable output
1: Enable output.
R/W
b26, b25
OBDF[1:0]
GTIOCB Pin Disable Value
Setting
b26 b25
R/W
b28, b27
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b29
NFBEN
Noise Filter B Enable
0: Disable noise filter for GTIOCB pin
1: Enable noise filter for GTIOCB pin.
R/W
b31, b30
NFCSB[1:0]
Noise Filter B Sampling Clock
Select
b31 b30
R/W
0
0
1
1
0
0
1
1
0: Prohibit output disable
1: Set GTIOCB pin to Hi-Z on output disable
0: Set GTIOCB pin to 0 on output disable
1: Set GTIOCB pin to 1 on output disable.
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
GTIOR sets the functions of the GTIOCA and GTIOCB pins.
GTIOA[4:0] bits (GTIOCA Pin Function Select)
The GTIOA[4:0] bits select the GTIOCA pin function. For details, see Table 19.5.
OADFLT bit (GTIOCA Pin Output Value Setting at the Count Stop)
The OADFLT bit sets whether the GTIOCA pin outputs high or low when counting stops.
OAHLD bit (GTIOCA Pin Output Setting at the Start/Stop Count)
The OAHLD bit specifies whether the GTIOCA pin output level is retained or the level depends on the register setting
when counting starts or stops.
When the OAHLD bit is set to 0:
The value specified by b4 of the GTIOA[4:0] bits is output when counting starts
The value specified by the OADFLT bit is output when counting stops
If the OADFLT bit is modified while counting stops, it is immediately reflected in the output.
When the OAHLD bit is set to 1:
The output is retained when counting starts or stops.
OAE bit (GTIOCA Pin Output Enable)
The OAE bit disables or enables the GTIOCA pin output.
When GTCCRA register is used as the input capture register (at least one bit in the GTICASR register is set to 1), the
GTIOCA pin does not output independent of the OAE bit value.
OADF[1:0] bits (GTIOCA Pin Disable Value Setting)
The OADF[1:0] bits select the output value of the GTIOCA pin when output disable request occurs.
NFAEN bit (Noise Filter A Enable)
The NFAEN bit disables or enables the noise filter for input from the GTIOCA pin. Because changing the value of the bit
might lead to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the
GTIOR register before doing so.
NFCSA[1:0] bits (Noise Filter A Sampling Clock Select)
The NFCSA[1:0] bits set the sampling interval for the noise filter of the GTIOCA pin. When setting these bits, wait for 2
cycles of the selected sampling interval before setting the input capture function.
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19. General PWM Timer (GPT)
GTIOB[4:0] bits (GTIOCB Pin Function Select)
The GTIOB[4:0] bits select the GTIOCB pin function. For details, see Table 19.5.
OBDFLT bit (GTIOCB Pin Output Value Setting at the Count Stop)
The OBDFLT bit sets whether the GTIOCB pin outputs high or low when counting stops.
OBHLD bit (GTIOCB Pin Output Setting at the Start/Stop Count)
The OBHLD bit specifies whether the GTIOCB pin output level is retained or the level depends on the register setting
when counting starts or stops.
When the OBHLD bit is set to 0:
The value specified by bit [4] of the GTIOB[4:0] bits is output when counting starts
The value specified by the OBDFLT bit is output when counting stops
If the OBDFLT bit is modified while counting stops, it is immediately reflected in the output.
When the OBHLD bit is set to 1:
The output is retained when counting starts or stops.
OBE bit (GTIOCB Pin Output Enable)
The OBE bit disables or enables the GTIOCB pin output.
When GTCCRB register is used as the input capture register (at least one bit in the GTICBSR register is set to 1),
GTIOCB pin does not output independently of the OBE bit value.
OBDF[1:0] bits (GTIOCB Pin Disable Value Setting)
The OBDF[1:0] bits select the output value of the GTIOCB pin, when an output disable request occurs.
NFBEN bit (Noise Filter B Enable)
The NFBEN bit disables or enables the noise filter for input from the GTIOCB pin. Because changing the value of the bit
might lead to the internal generation of an unexpected edge, select the output compare function for the relevant pin in the
GTIOR register before doing so.
NFCSB[1:0] bits (Noise Filter B Sampling Clock Select)
The NFCSB[1:0] bits set the sampling interval for the noise filter of the GTIOCB pin. When setting these bits, wait for 2
cycles of the selected sampling interval before setting the input capture function.
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Table 19.5
19. General PWM Timer (GPT)
Settings of GTIOA[4:0] and GTIOB[4:0] bits
GTIOA/GTIOB[4:0] bits
Function
b4
b3
b2
b1
b0
b4
b3, b2
b1, b0
0
0
0
0
0
Initial output is low.
0
0
0
0
1
Output retained at
cycle end
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
High output at GTCCRA/GTCCRB compare match
0
0
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
High output at GTCCRA/GTCCRB compare match
0
1
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
High output at GTCCRA/GTCCRB compare match
1
0
0
1
1
Output toggled at GTCCRA/GTCCRB compare match
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
High output at GTCCRA/GTCCRB compare match
1
1
0
1
1
Output toggled at GTCCRA/GTCCRB compare match
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
High output at GTCCRA/GTCCRB compare match
1
1
1
1
1
Output toggled at GTCCRA/GTCCRB compare match
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Low output at cycle
end
High output at cycle
end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
Output toggled at
cycle end
Initial output is high.
Output retained at
cycle end
Low output at cycle
end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
High output at GTCCRA/GTCCRB compare match
Output toggled at GTCCRA/GTCCRB compare match
High output at cycle
end
Output toggled at
cycle end
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
Output retained at GTCCRA/GTCCRB compare match
Low output at GTCCRA/GTCCRB compare match
Note 1. The cycle end means an overflow (GTCNT changes from GTPR to 0 in up-counting) or underflow (GTCNT
changes from 0 to GTPR in down-counting). In this case, the GTCNT counter is cleared for saw waves and for
the trough (GTCNT changes from 0 to 1) for triangle waves.
Note 2. When the timing of a cycle end and the timing of a GTCCRA/GTCCRB compare match are the same in a
compare-match operation, the b3 and b2 settings are given priority in saw-wave PWM mode, and the b1 and b0
settings are given priority in any other mode.
Note 3. In event count operation where at least one bit in GTUPSR or GTDNSR is set to 1, the setting of b3 and b2 is
ignored.
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19.2.15
19. General PWM Timer (GPT)
General PWM Timer Interrupt Output Setting Register (GTINTAD)
Address(es): GPT320.GTINTAD 4007 8038h
GPT16m.GTINTAD 4007 8038h + 0100h × m (m = 1 to 6)
b31
—
b30
b29
GRPAB GRPAB
L
H
b28
b27
b26
—
—
—
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
GRP[1:0]
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
b23 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b25, b24
GRP[1:0]
Output Disable Source Select
b25 b24
0
0
1
1
R/W
0: Select Group A output disable request
1: Select Group B output disable request
0: Setting Prohibited
1: Setting Prohibited.
R/W
b28 to b26
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b29
GRPABH
Same Time Output Level High Disable
Request Enable
0: Disable same time output level high disable request R/W
1: Enable same time output level high disable request.
b30
GRPABL
Same Time Output Level Low Disable
Request Enable
0: Disable same time output level low disable request
1: Enable same time output level low disable request.
R/W
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
GTINTAD enables or disables interrupt requests and output disable requests.
GRP[1:0] bits (Output Disable Source Select)
The GRP[1:0] bits select the GTIOCA pin and GTIOCB pin output disable source. The output disable request to POEG
outputs to the group which is selected by GRP[1:0] bits when same time output level high or same time output level low
occurs based on the output disable request enable bit.
GTST.ODF shows the request of the output disable source group that is selected with the GRP[1:0] bits. GRP[1:0] bits
should be set when both GTIOR.OAE and GTIOR.OBE bits are 0.
GRPABH bit (Same Time Output Level High Disable Request Enable)
The GRPABH bit enables or disables the output disable request when the GTIOCA pin and GTIOCB pin output 1 at the
same time.
GRPABL bit (Same Time Output Level Low Disable Request Enable)
The GRPABL bit enables or disables the output disable request when the GTIOCA pin and GTIOCB pin output 0 at the
same time.
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19.2.16
19. General PWM Timer (GPT)
General PWM Timer Status Register (GTST)
Address(es): GPT320.GTST 4007 803Ch
GPT16m.GTST 4007 803Ch + 0100h × m (m = 1 to 6)
b31
—
b30
b29
OABLF OABHF
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
ODF
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TUCF
—
—
—
—
—
—
—
TCFE
TCFD
TCFC
TCFB
TCFA
1
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
TCFPU TCFPO TCFF
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TCFA
Input Capture/Compare Match
Flag A
0: No input capture/compare match of GTCCRA is generated
1: An input capture/compare match of GTCCRA is generated.
R/(W)*1
b1
TCFB
Input Capture/Compare Match
Flag B
0: No input capture/compare match of GTCCRB is generated
1: An input capture/compare match of GTCCRB is generated.
R/(W)*1
b2
TCFC
Input Compare Match Flag C
0: No compare match of GTCCRC is generated
1: A compare match of GTCCRC is generated.
R/(W)*1
b3
TCFD
Input Compare Match Flag D
0: No compare match of GTCCRD is generated
1: A compare match of GTCCRD is generated.
R/(W)*1
b4
TCFE
Input Compare Match Flag E
0: No compare match of GTCCRE is generated
1: A compare match of GTCCRE is generated.
R/(W)*1
b5
TCFF
Input Compare Match Flag F
0: No compare match of GTCCRF is generated
1: A compare match of GTCCRF is generated.
R/(W)*1
b6
TCFPO
Overflow Flag
0: No overflow (crest) occurred
1: An overflow (crest) occurred.
R/(W)*1
b7
TCFPU
Underflow Flag
0: No underflow (trough) occurred
1: An underflow (trough) occurred.
R/(W)*1
b14 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
TUCF
Count Direction Flag
0: GTCNT counter is counting down
1: GTCNT counter is counting up.
R
b23 to b16 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b24
Output Disable Flag
0: No output disable request is generated
1: An output disable request is generated.
R
b28 to b25 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b29
OABHF
Same Time Output Level High
Flag
0: GTIOCA pin and GTIOCB pin do not output 1 at the same
time
1: GTIOCA pin and GTIOCB pin output 1 at the same time.
R
b30
OABLF
Same Time Output Level Low
Flag
0: GTIOCA pin and GTIOCB pin do not output 0 at the same
time
1: GTIOCA pin and GTIOCB pin output 0 at the same time.
R
b31
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
ODF
Note 1. Only 0 can be written to this bit; do not write 1.
GTST indicates the status of the GPT.
TCFA flag (Input Capture/Compare Match Flag A)
The TCFA flag indicates the status of the input capture or compare match of GTCCRA.
[Setting conditions]
GTCNT = GTCCRA, when the GTCCRA register functions as a compare match register
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19. General PWM Timer (GPT)
GTCNT counter value is transferred to GTCCRA by the input capture signal when the GTCCRA register functions
as an input capture register.
[Clearing condition]
0 is written to this flag.
TCFB flag (Input Capture/Compare Match Flag B)
The TCFB flag indicates the status of the input capture or compare match of GTCCRB.
[Setting conditions]
GTCNT = GTCCRB, when the GTCCRB register functions as a compare match register
GTCNT counter value is transferred to GTCCRB by the input capture signal when the GTCCRB register functions
as an input capture register.
[Clearing condition]
0 is written to this flag.
TCFC flag (Input Compare Match Flag C)
The TCFC flag indicates the status of the compare match of GTCCRC.
[Setting condition]
GTCNT = GTCCRC.
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 01b, 10b, 11b (GTCCRC performs buffer operation).
TCFD flag (Input Compare Match Flag D)
The TCFD flag indicates the status of the compare match of GTCCRD.
[Setting condition]
GTCNT = GTCCRD.
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (Triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 10b, 11b (GTCCRD performs buffer operation).
TCFE flag (Input Compare Match Flag E)
The TCFE flag indicates the status of the compare match of GTCCRE.
[Setting condition]
GTCNT = GTCCRE.
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
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19. General PWM Timer (GPT)
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 01b, 10b, 11b (GTCCRE performs buffer operation).
TCFF flag (Input Compare Match Flag F)
The TCFF flag indicates the status of the compare match of GTCCRF.
[Setting condition]
GTCNT = GTCCRF.
[Clearing condition]
0 is written to this flag.
[Not comparing condition]
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRB[1:0] = 10b, 11b (GTCCRF performs buffer operation).
TCFPO flag (Overflow Flag)
The TCFPO flag indicates when an overflow or crest has occurred.
[Setting conditions]
In saw-wave mode, an overflow (GTCNT changes from GTPR to 0 in up count) has occurred
In triangle-wave mode, a crest (GTCNT changes from GTPR to GTPR-1) has occurred
In counting by hardware sources, an overflow (GTCNT changes from GTPR to 0 in up count) has occurred.
[Clearing condition]
0 is written to this flag.
TCFPU flag (Underflow Flag)
The TCFPU flag indicates when underflow or trough has occurred.
[Setting conditions]
In saw-wave mode, an underflow (GTCNT changes from 0 to GTPR in down count) has occurred
In triangle-wave mode, a crest (GTCNT changes from 0 to 1) has occurred
In counting by hardware sources, an underflow (GTCNT changes from 0 to GTPR in down count) has occurred.
[Clearing condition]
0 is written to this bit.
TUCF flag (Count Direction Flag)
The TUCF flag indicates the count direction of GTCNT.
In event count operation, this flag is set to 1 in up-counting and is set to 0 in down-counting.
ODF flag (Output Disable Flag)
The ODF flag shows the request of the output disable source group that is selected by the GRP[1:0] bits.
When output is disabled, the output disable control is not released within the same one cycle in which the output disable
request is negated. It is released in the next cycle.
OABHF flag (Same Time Output Level High Flag)
The OABHF flag indicates that the GTIOCA pin and GTIOCB pin output 1 at the same time.
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19. General PWM Timer (GPT)
When the GTIOCA pin or GTIOCB pin output 0, this flag returns to 0. This flag is read only. Writing 0 to clear the flag
is not allowed.
When an interrupt by the OABHF flag is enabled (GTINTAD.GRPABH = 1), the OABHF flag is output to POEG as the
output disable request.
[Setting condition]
GTIOCA pin and GTIOCB pin output 1 at the same time when both OAE bit and OBE bit are set to 1.
[Clearing conditions]
GTIOCA pin output value is different from the GTIOCB pin output value when both OAE bit and OBE bit are set to
1
GTIOCA pin and GTIOCB pin output 0 at the same time when both OAE bit and OBE bit are set to 1
At least either OAE bit or OBE bit is set to 0.
OABLF flag (Same Time Output Level Low Flag)
The OABLF flag indicates that GTIOCA pin and GTIOCB pin output 0 at the same time.
When the GTIOCA pin or GTIOCB pin output 1, this flag returns to 0. This flag is read only. Writing 0 to clear the flag
is not allowed.
When an interrupt by the OABLF flag is enabled (GTINTAD.GRPABL = 1), the OABLF flag is output to POEG as the
output disable request.
[Setting condition]
GTIOCA pin and GTIOCB pin output 0 at the same time when both OAE bit and OBE bit are set to 1.
[Clearing conditions]
GTIOCA pin output value is different from GTIOCB pin output value when both OAE bit and OBE bit are set to 1
GTIOCA pin and GTIOCB pin output 1 at the same time when both OAE bit and OBE bit are set to 1
At least either OAE bit or OBE bit is set to 0.
The compare-target signals to generate the OABHF/OABLF flag are the compare match outputs (PWM outputs) signals
before masked by the output disable function. When the output disable state is performed, a compare match is also
performed continuously in the GPT and the OABHF/OABLF flag is updated in association with the result of the
compared value.
19.2.17
General PWM Timer Buffer Enable Register (GTBER)
Address(es): GPT320.GTBER 4007 8040h
GPT16m.GTBER 4007 8040h + 0100h × m (m = 1 to 6)
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
—
—
—
—
—
—
—
—
—
CCRS
WT
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
b20
PR[1:0]
b19
b18
b17
b16
CCRB[1:0]
CCRA[1:0]
0
0
0
0
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
BD[1]
BD[0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BD[0]
GTCCR Buffer Operation Disable
0: Enable buffer operation
1: Disable buffer operation.
R/W
b1
BD[1]
GTPR Buffer Operation Disable
b15 to b2
—
Reserved
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R/W
These bits are read as 0. The write value should be 0.
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b17, b16
CCRA[1:0]
GTCCRA Buffer Operation
b17 b16
R/W
b19, b18
CCRB[1:0]
GTCCRB Buffer Operation
b19 b18
R/W
b21, b20
PR[1:0]
GTPR Buffer Operation
b21 b20
R/W
b22
CCRSWT
GTCCRA and GTCCRB Forcible
Buffer Operation
Writing 1 to this bit forces a buffer transfer of GTCCRA
and GTCCRB. This bit automatically returns to 0 after
writing 1. This bit is read as 0.
R/W
b31 to b23
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0 0: No buffer operation
0 1: Single buffer operation (GTCCRA ↔ GTCCRC)
1 x: Double buffer operation (GTCCRA ↔ GTCCRC ↔
GTCCRD).
0 0: No buffer operation
0 1: Single buffer operation (GTCCRB ↔ GTCCRE)
1 x: Double buffer operation (GTCCRB ↔ GTCCRE ↔
GTCCRF).
0 0: No buffer operation
0 1: Single buffer operation (GTPBR → GTPR)
1 x: Setting prohibited.
GTBER provides settings for the buffer operation and must be set while the GTCNT operation stops.
BD[0] bit (GTCCR Buffer Operation Disable)
The BD[0] bit disables the buffer operation using GTCCRA, GTCCRC, and GTCCRD combined and the buffer
operation using GTCCRB, GTCCRE, and GTCCRF combined.
When GTDTCR.TDE is 1 and when BD[0] is set to 0, GTCCRB does not perform buffer operation. The GTCCRB
register is automatically set to a compare match value for negative-phase waveform with dead time.
BD[1] bit (GTPR Buffer Operation Disable)
The BD[1] bit disables the buffer operation using GTPR and GTPBR combined.
CCRA[1:0] bits (GTCCRA Buffer Operation)
The CCRA[1:0] bits set the buffer operation with GTCCRA, GTCCRC, and GTCCRD combined. When the buffer
operation is restricted by the operating mode set in GTCR, the GTCR setting is given priority.*1
CCRB[1:0] bits (GTCCRB Buffer Operation)
The CCRB[1:0] bits set the buffer operation using GTCCRB, GTCCRE, and GTCCRF combined. When the buffer
operation is restricted by the operating mode set in GTCR, the GTCR setting is given priority.*1
PR[1:0] bits (GTPR Buffer Operation)
The PR[1:0] bits set the buffer operation with GTPR and GTPBR of the combined GPT.
CCRSWT bit (GTCCRA and GTCCRB Forcible Buffer Operation)
Writing 1 to the CCRSWT bit forces a buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0
after the writing of 1. This bit is read as 0.
This bit is valid only when counting stops with the compare match operation specified.
Note 1. The buffer operation mode is fixed in saw-wave one-shot pulse mode or triangle-wave PWM mode 3 (64-bit
transfer at trough).
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19.2.18
19. General PWM Timer (GPT)
General PWM Timer Counter (GTCNT)
Address(es): GPT320.GTCNT 4007 8048h
GPT16m.GTCNT 4007 8048h + 0100h × m (m = 1 to 6)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GTCNT is a 32-bit read/write counter for GPT320. For GPT16m (m = 1 to 6), GTCNT is a 16-bit register. GTCNT can
only be written to after counting stops. GTCNT must be accessed in 32-bit units. Access in 8-bit/16-bit units is
prohibited.
For GPT16m (m = 1 to 6), the upper 16 bits for access in a 32-bit unit are always read as 0000h, and writing to these bits
is ignored.
GTCNT must be set within the range of 0 ≤ GTCNT ≤ GTPR.
19.2.19
General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F)
Address(es): GPT320.GTCCRA 4007 804Ch
GPT320.GTCCRB 4007 8050h
GPT320.GTCCRC 4007 8054h
GPT320.GTCCRD 4007 805Ch
GPT320.GTCCRE 4007 8058h
GPT320.GTCCRF 4007 8060h
GPT16m.GTCCRA 4007 804Ch + 0100h × m (m = 1 to 6)
GPT16m.GTCCRB 4007 8050h + 0100h × m (m = 1 to 6)
GPT16m.GTCCRC 4007 8054h + 0100h × m (m = 1 to 6)
GPT16m.GTCCRD 4007 805Ch + 0100h × m (m = 1 to 6)
GPT16m.GTCCRE 4007 8058h + 0100h × m (m = 1 to 6)
GPT16m.GTCCRF 4007 8060h + 0100h × m (m = 1 to 6)
Value after
reset:*1
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note 1. For GPT16m (m = 1 to 6), value of the upper 16 bits after reset is 0000h.
GTCCRn registers are read/write registers. The effective size of GTCCRn is the same as GTCNT (16- or 32-bit). If the
effective size of GTCCRn is 16-bit, the upper 16 bits for access in a 32-bit unit are always read as 0000h, and writing to
these bits is ignored.
GTCCRA and GTCCRB are registers used for both the output compare and input capture.
GTCCRC and GTCCRE are compare match registers that can also function as buffer registers for GTCCRA and
GTCCRB.
GTCCRD and GTCCRF are compare match registers that can also function as buffer registers for GTCCRC and
GTCCRE (double-buffer registers for GTCCRA and GTCCRB).
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19.2.20
19. General PWM Timer (GPT)
General PWM Timer Cycle Setting Register (GTPR)
Address(es): GPT320.GTPR 4007 8064h
GPT16m.GTPR 4007 8064h + 0100h × m (m = 1 to 6)
Value after
reset:*1
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note 1. For GPT16m (m = 1 to 6), value of the upper 16 bits after reset is 0000h.
GTPR is a read/write register that sets the maximum count value of GTCNT. The effective size of GTPR is same as
GTCNT (16- or 32-bit). If the effective size of GTPR is 16-bit, the upper 16 bits for access in a 32-bit unit are always
read as 0000h, and writing to these bits is ignored.
For saw waves, the value of (GTPR + 1) is the cycle. For triangle waves, the value of (GTPR value 2) is the cycle.
19.2.21
General PWM Timer Cycle Setting Buffer Register (GTPBR)
Address(es): GPT320.GTPBR 4007 8068h
GPT16m.GTPBR 4007 8068h + 0100h × m (m = 1 to 6)
Value after
reset:*1
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note 1. For GPT16m (m = 1 to 6), value of the upper 16 bits after reset is 0000h.
GTPBR is a read/write register that functions as a buffer register for GTPR. The effective size of GTPBR is the same as
GTCNT (16- or 32-bit). If the effective size of GTPBR is 16-bit, the upper 16 bits for access in a 32-bit unit are always
read as 0000h, and writing to these bits is ignored.
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19.2.22
19. General PWM Timer (GPT)
General PWM Timer Dead Time Control Register (GTDTCR)
Address(es): GPT320.GTDTCR 4007 8088h
GPT16m.GTDTCR 4007 8088h + 0100h × m (m = 1 to 6)
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TDE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TDE
Negative-Phase Waveform Setting
0: Set GTCCRB without using GTDVU
R/W
1: Use GTDVU to set the compare match value for negativephase waveform with dead time automatically in GTCCRB.
b31 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
GTDTCR enables the automatic setting of a compare match value for negative-phase waveform with dead time.
GPT has a dead time control function and the GTDVU register is used for setting dead time value.
TDE bit (Negative-Phase Waveform Setting)
The TDE bit specifies whether to use GTDVU. When GTDVU is used, the compare match value for a negative-phase
waveform with dead time obtained by the compare match value of a positive-phase waveform (GTCCRA) and the dead
time value (GTDVU) is automatically set in GTCCRB.
The TDE bit setting is ignored in saw-wave PWM mode, and automatic setting does not take place.
The GTCCRB value is automatically set and has the following upper and lower limit values. If the obtained GTCCRB
value is not within the upper or lower limit, the following limit value is set in GTCCRB.
Triangle waves:
Upper limit value: GTPR 1
Lower limit value: 1 in up-counting, 0 in down-counting.
Saw-wave one-shot pulse mode:
Upper limit value: GTPR
Lower limit value: 0.
19.2.23
General PWM Timer Dead Time Value Register U (GTDVU)
Address(es): GPT320.GTDVU 4007 808Ch
GPT16m.GTDVU 4007 808Ch + 0100h x m (m = 1 to 6)
Value after
reset:*1
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note 1. For GPT16m (m = 1 to 6), value of the upper 16 bits after reset is 0000h.
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S124 User’s Manual
19. General PWM Timer (GPT)
GTDVU is a read/write register that sets the dead time for generating PWM waveforms with dead time. The effective
size of GTDVU is the same as GTCNT (16- or 32-bit). If the effective size of GTDVU is 16-bit, the upper 16 bits for
access in a 32-bit unit are always read as 0000h, and writing to these bits is ignored.
Setting a dead time value that exceeds the cycle is prohibited. The set value can be confirmed by reading from GTCCRB.
When GTDVU is used, writing to GTCCRB is prohibited. When this register is set to 0, waveforms without dead time
are output.
While GPT is running, changing the GTDVU values is prohibited. To change GTDVU to a new value, the GPT must be
stopped by the CST bit in the GTCR register. GTDVU must be accessed in 32-bit units. Access in 8-bit/16-bit units is
prohibited.
19.2.24
Output Phase Switching Control Register (OPSCR)
Address(es): GPT_OPS.OPSCR 4007 8FF0h
b31
b30
NFCS[1:0]
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
NFEN
—
—
GODF
—
GRP
—
—
ALIGN
—
INV
N
P
FB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
EN
—
W
V
U
—
WF
VF
UF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
UF
Input Phase Soft Setting
VF
These bits set the input phase from the software settings.
Setting these bits are valid when the OPSCR.FB bit = 1.
R/W
b1
b2
WF
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
U
Input U-Phase Monitor
R
b5
V
Input V-Phase Monitor
b6
W
Input W-Phase Monitor
These bits monitor the state of the input phase.
OPSCR.FB = 0: External inputs that are synchronized by
PCLKD are monitored by these bits
OPSCR.FB = 1: The OPSCR.U, OPSCR.V and OPSCR.W
bits can read the OPSCR.UF. OPSCR.VF, and OPSCR.WF
bits.
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b8
EN
Enable-Phase Output Control
0: Do not output (Hi-Z external pin)
1: Output*1.
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b16
FB
External Feedback Signal Enable
This bit selects the input phase from the software settings
and external input.
0: Select the external input
1: Select the soft setting (OPSCR.UF, VF, WF).
R/W
b17
P
Positive-Phase Output (P) Control
0: Level signal output
1: PWM signal output (PWM of GPT161).
R/W
b18
N
Negative-Phase Output (N) Control
0: Level signal output
1: PWM signal output (PWM of GPT161).
R/W
b19
INV
Invert-Phase Output Control
0: Positive logic (active-high) output
1: Negative logic (active-low) output.
R/W
b20
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b21
ALIGN
Input Phase Alignment
0: Input phase is aligned to PCLKD
1: Input phase is aligned PWM.
R/W
b23, b22
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b24
GRP
Output Disabled Source Selection
0: Select Group A output disable source
1: Select Group B output disable source.
R/W
R/W
R/W
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19. General PWM Timer (GPT)
Bit
Symbol
Bit name
Description
R/W
b25
—
b26
GODF
Reserved
This bit is read as 0. The write value should be 0.
R/W
Group Output Disable Function
0: This bit function is ignored
1: Group disable clears the OPSCR.EN bit*1.
R/W
b28, b27
b29
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
NFEN
External Input Noise Filter Enable
0: Do not use a noise filter to the external input
1: Use a noise filter to the external input.
R/W
b31, b30
NFCS[1:0]
External Input Noise Filter Clock
Selection
Noise filter sampling clock setting of the external input.
R/W
b31 b30
0
0
1
1
0: PCLKD/1
1: PCLKD/4
0: PCLKD/16
1: PCLKD/64.
Note 1. When OPSCR.GODF = 1 and signal value selected by the OPSCR.GRP bit is high, the OPSCR.EN bit is cleared
to 0.
The OPSCR register sets the output of the signal waveform required for brushless DC motor control.
UF, VF, WF bits (Input Phase Soft Setting)
These bits set the input phase from the software settings.
When OPSCR.FB bit is 1, these bits are valid. The set value of the UF/VF/WF takes the place of the U/V/W external
input.
U, V, W bits (Input Phase Monitor)
When OPSCR.FB bit is 0, external inputs that are synchronized by PCLKD, are monitored by these bits.
When OPSCR.FB bit is 1, the OPSCR.U, OPSCR.V, and OPSCR.W bits can read the OPSCR.UF, OPSCR.VF, and
OPSCR.WF bits.
EN bit (Enable-Phase Output Control)
The EN bit controls the output enable signal output phase (positive phase/reverse phase). When OPSCR.EN bit is 1, the
signal waveform is output.
When OPSCR.EN bit is 0, first set OPSCR.FB, OPSCR.UF/VF/WF (software setting is selected), OPSCR.P/N,
OPSCR.INV, OPSCR.RV, OPSCR.ALIGN, OPSCR.GRP, OPSCR.GODF, OPSCR.NFEN, OPSCR.NFCS. Then, set this
bit to 1. Also when OPSCR.GODF is 1 and the signal value selected by the OPSCR.GRP bit is high, the OPSCR.EN bit
is cleared to 0.
FB bit (External Feedback Signal Enable)
The FB bit selects the input phase from the software settings (OPSCR.UF, VF, WF) and external input such as a Hall
element.
P bit (Positive-Phase Output (P) Control)
The P bit selects one of the Level signal output (PWM of GPT161) or PWM signal output for the positive-phase output
(GTOUUP pin, GTOVUP pin, GTOWUP pin).
N bit (Negative-Phase Output (N) Control)
The N bit selects one of the Level signal output (PWM of GPT161) or PWM signal output for the negative-phase output
(GTOULO pin, GTOVLO pin, GTOWLO pin).
INV bit (Invert-Phase Output Control)
The INV bit selects one of the positive logic (active-high) output or negative logic (active-low) output for the output
phase.
ALIGN bit (Input Phase Alignment)
The ALIGN bit selects the PCLKD or PWM for the sampling of the input phase (input phase is specified in the
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19. General PWM Timer (GPT)
OPSCR.FB bit). When OPSCR.ALIGN bit is 0, input phase is aligned to PCLKD.
When PWM output is selected (OPSCR.P/N is 1) and the PCLKD input phase is aligned, the PWM pulse may be
short-pulsed.
When OPSCR.ALIGN bit is 1, input phase is aligned with PWM output.
Note:
Note:
GRP bit (Output Disabled Source Selection)
The GRP bit selects the output disable source A to B.
GODF bit (Group Output Disable Function)
When OPSCR.GODF is 1 and signal value selected by the OPSCR.GRP bit is high, the OPSCR.EN bit is cleared to 0.
When OPSCR.GODF bit is 0, this bit is ignored.
NFEN bit (External Input Noise Filter Enable)
The NFEN bit selects the noise filter for external input. When OPSCR.NFEN bit is 0, a noise filter to the external input
is not used. When OPSCR.NFEN bit is 1, a noise filter to the external input is used.
Note:
When this bit is switched, because an unintentional internal edge occurs, first set OPSCR.EN bit = 0.
NFCS[1:0] bits (External Input Noise Filter Clock Selection)
When OPSCR.NFEN bit is 1, noise filter sampling clock setting of the external input is enabled.
1. Set the NFCS.
2. Wait for 2 cycles.
3. Set the OPSCR.EN bit to 1.
19.3
Operation
19.3.1
Basic Operation
Each channel has a 32-bit timer that performs a periodic count operation using the count clock and hardware sources.
The count function provides both up-counting and down-counting. The GTPR controls the count cycle.
When the GTCNT counter value matches the value in GTCCRA or GTCCRB, the output from the corresponding pin
GTIOCA or GTIOCB can be changed. GTCCRA or GTCCRB can be used as an input capture register with hardware
resources.
GTCCRC and GTCCRD can function as buffer registers for GTCCRA. GTCCRE and GTCCRF can function as buffer
registers for GTCCRB.
19.3.1.1
(1)
Counter operation
Counter start/stop
The counter of each channel starts the count operation by setting GTCR.CST to 1 and stops the count operation by
setting GTCR.CST to 0.
The GTCR.CST bit value is changed by the following sources:
Writing to GTCR register
Writing 1 to the bit in GTSTR associated with the GPT channel number when the GTSSR.CSTRT bit set to 1
Writing 1 to the bit in GTSTP associated with the GPT channel number when the GTPSR.CSTOP bit set to 1
The hardware source selected in the GTSSR register
The hardware source selected in the GTPSR register.
(2)
Periodic count operation in up-counting by count clock
The GTCNT counter in each channel starts up-counting when the corresponding GTCR.CST bit is set to 1 with GTUPSR
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and GTDNSR registers set to 00000000h. When the GTCNT value changes from the GTPR value to 0 (overflow), the
GTST.TCFPO flag is set to 1. After GTCNT overflows, up-counting is resumed from 00000000h.
Figure 19.3 shows an example of a periodic count operation in up-counting.
GTCNT counter value
GPT320.GTPR register
0000 0000h
GTCR.CST bit
Time
Flag is cleared by software
GTST.TCFPO flag
Figure 19.3
Example of periodic count operation in up-counting by the count clock
Figure 19.4 shows an example for setting periodic count operation in up-counting.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.3, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction with the GTUDDTYC register.
(In Figure 19.3, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter. (In Figure 19.3, 0000 0000h is
set.)
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 19.4
(3)
Example for setting a periodic count operation in up-counting by the count clock
Periodic count operation in down-counting by count clock
The GTCNT counter in each channel can perform down-counting by setting GTUDDTYC.UD with GTUPSR and
GTDNSR registers set to 00000000h. When GTCNT changes from 0 to the GTPR value (underflow), GTST.TCFPU is
set to 1. After the GTCNT counter underflows, down-counting is resumed from the GTPR value.
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Figure 19.5 shows an example of periodic count operation in down-counting by the count clock.
GTCNT counter value
GTCNT counter is written by software.
GTPR register
0000 0000h
GTCR.CST bit
Time
Flag is cleared by software
GTST.TCFPU flag
Figure 19.5
Example of periodic count operation in down-counting by the count clock
Figure 19.6 shows an example for setting periodic count operation in down-counting by the count clock.
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.5, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction with the GTUDDTYC register.
(In Figure 19.5, after 10b is set in GTUDDTYC[1:0], 00b is set in
GTUDDTYC[1:0] (down-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
(In Figure 19.5, the GTPR value is set.)
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 19.6
(4)
Example for setting periodic count operation in down-counting by count clock
Event count operation in up-counting using hardware sources
The GTCNT counter in each channel can perform up-counting using hardware sources as set in GTUPSR.
When GTUPSR is set to enable, the count clock selected in GTCR.TPCS[2:0] and the count direction selected in
GTUDDTYC.UD are ignored. If up-counting and down-counting using hardware sources occur at the same time, the
GTCNT counter value does not change. The overflow behavior when up-counting using hardware sources is the same as
when up-counting by the count clock.
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When GTCR.CST bit is set to 1 to count up using hardware sources, the count operation is enabled. After GTCR.CST is
set to 1, the counter cannot count up for 1 clock cycle as specified by GTCR.TPCS[2:0] because the count operation is
synchronized by the count clock selected by GTCR.TPCS[2:0]. Set GTCR.TPCS[2:0] to 000b to count up with a 1
PCLKD delay after GTCR.CST is set to 1.
Figure 19.7 shows an example of a periodic count operation in up-counting by a hardware resource (rising edge of
GTETRGA pin).
PCLKD
GTETRGA
N
GTCNT
Figure 19.7
N+1
Example of periodic count operation in up-counting using hardware sources
Figure 19.8 shows an example for setting periodic count operation in down-counting by the count clock.
Set count source
Select the counting-up source with the GTUPSR register.
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 19.8
(5)
Example for setting an event count operation in up-counting using hardware sources
Event count operation in down-counting using hardware sources
The GTCNT counter in each channel can perform down-counting using hardware sources set in the GTDNSR.
When GTDNSR is set to enable, the count clock selected in GTCR.TPCS[2:0] and the count direction selected in
GTUDDTYC.UD are ignored. If up-counting and down-counting using hardware sources occur at the same time, the
GTCNT counter value does not change. The underflow behavior when down-counting using hardware sources is the
same as when down-counting by the count clock.
When GTCR.CST bit is set to 1 to count down using hardware sources, the count operation is enabled. After GTCR.CST
is set to 1, the counter cannot count down for 1 clock cycle as specified by GTCR.TPCS[2:0] because the count operation
is synchronized with the count clock selected by GTCR.TPCS[2:0]. Set GTCR.TPCS[2:0] to 000b to count down with a
1 PCLKD delay after GTCR.CST is set to 1.
Figure 19.9 shows an example of a periodic count operation in down-counting by a hardware resource (rising edge of
GTETRGA pin).
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PCLKD
GTETRGA
N+1
GTCNT
Figure 19.9
N
Example of event count operation in down-counting using hardware sources
Figure 19.10 shows an example for setting a periodic count operation in down-counting using a hardware resource.
Set count source
Select the counting-down source with the GTDNSR register.
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 19.10
(6)
Example for setting an event count operation in down-counting using hardware sources
Counter clear operation
The counter of each channel is cleared by following sources:
Writing 0 to GTCNT register
Writing 1 to the bit in GTCLR associated with the GPT channel number when the GTCSR.CCLR bit set to 1
The hardware source selected in GTCSR register.
Writing to the GTCNT register is prohibited during count operation. The GTCNT counter can be cleared both by writing
1 to the GTCLR and by the clear request of hardware sources, whether GTCNT is counting (GTCR.CST is 1) or not
(GTCR.CST is 0).
For saw waves selected by setting GTCR.MD[2:0] and the count direction flag showing down-counting (GTST.TUCF is
0), the GTCNT register is set to the value of the GTPR register when writing 1 to the GTCLR register and when clearing
by hardware sources are performed.
When not in saw waves mode and down-counting, the GTCNT register is set to 0 when writing 1 to the GTCLR register
and when clearing by hardware sources are performed.
In event count operation when at least 1 bit in the GTUPSR or GTDNSR is set to 1, after clear sources occur, both
writing to GTCLR register and clearing by hardware sources are performed immediately to synchronize with PCLKD.
If other settings are used, clear is synchronized with the counter clock selected by GTCR.TPCS[2:0].
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19.3.1.2
19. General PWM Timer (GPT)
Waveform output by compare match
Compare match means that the GTCNT counter value matches the value of GTCCRA or GTCCRB.
When a compare match occurs, the compare match flag is generated synchronously with the count clock including the
event count. At the same time, the GPT can output low, high, or toggle output from the corresponding GTIOCA or
GTIOCB output pin.
In addition, the GTIOCA or GTIOCB pin output can be low, high, or toggled at the cycle end which is determined by
GTPR.
The cycle end is:
For saw waves in up-counting – When GTCNT changes from the GTPR value to 0 (overflow)
For saw waves in down-counting – When GTCNT changes from 0 to GTPR value (underflow)
For saw waves – When the GTCNT counter is cleared
For triangle waves – When the GTCNT changes from 0 to 1 (trough).
(1)
Low output and high output
Figure 19.11 shows an example of low output and high output operation by a compare match of GTCCRA and
GTCCRB.
In this example, the GPT320.GTCNT counter performs up-counting, and settings are made so that high is output from
the GTIOC0A pin by a GPT320.GTCCRA compare match, and low is output from the GTOC0B pin by a
GPT320.GTCCRB compare match. The pin level does not change when the specified level and pin level match.
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
GPT320.GTCCRB register
Time
0000 0000h
No change
No change
GTIOC0A pin output
GTIOC0B pin output
No change
No change
[Setting examples]
GPT320.GTIOR.GTIOA[4:0] bits: Initial output is low, high output at compare match, output retained at cycle end
GPT320.GTIOR.GTIOB[4:0] bits: Initial output is high, low output at compare match, output retained at cycle end
Figure 19.11
Example of low output and high output operation
Figure 19.12 shows an example for setting low output and high output operation.
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Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.11, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.11, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.11, GTIOA[4:0] = 00010b, GTIOB[4:0] = 10001b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set compare match value
Set compare match values in the GTCCRA and GTCCRB registers.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 19.12
(2)
Example for setting low output and high output operation
Toggled output
Figure 19.13 and Figure 19.14 show examples of toggled output operation by compare matches of GTCCRA and
GTCCRB. In Figure 19.13, the GPT320.GTCNT counter performs up-counting, and settings are made so that the
GTIOC0A pin output by a GPT320.GTCCRA compare match and GTIOC0B pin output by a GPT320.GTCCRB
compare match are toggled.
In Figure 19.14, the GPT320.GTCNT counter performs up-counting, and settings are made so that the GTIOC0A output
is toggled by a compare match of GPT320.GTCCRA and the GTIOC0B output is toggled at the cycle end.
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GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRB register
GPT320.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
GTIOC0B pin output
[Setting examples]
GPT320.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end
GPT320.GTIOR.GTIOB[4:0] bits: Initial output is low, output toggled at compare match, output retained at cycle end
Figure 19.13
Example of toggled output operation (1)
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
0000 0000h
Time
GTIOC0A pin output
GTIOC0B pin output
[Setting examples]
GPT320.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end
GPT320.GTIOR.GTIOB[4:0] bits: Initial output is low, output retained at compare match, output toggled at cycle end
Figure 19.14
Example of toggled output operation (2)
Figure 19.15 shows an example for setting toggled output operation.
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Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.13 and Figure 19.14, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.13 and Figure 19.14, after 11b is set in GTUDDTYC[1:0],
01b is set in GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.13, GTIOA[4:0] = 10011b, GTIOB[4:0] = 00011b
in Figure 19.14, GTIOA[4:0] = 10011b, GTIOB[4:0] = 01100b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set compare match value
Set compare match values in the GTCCRA and GTCCRB registers.
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 19.15
Example for setting toggled output operation
19.3.1.3
Input capture function
The GTCNT counter value can be transferred to either GTCCRA or GTCCRB on detection of the hardware source that is
set in GTICASR and GTICBSR.
Figure 19.16 shows an example of the input capture function.
In this example, the GPT320.GTCNT counter performs up-counting by the count clock, and settings are made so that an
input capture is performed to GTICCRA at both edges of the GTIOC0A input pin and to GTICCRB on the rising edge of
the GTIOC0B input pin.
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GPT320.GTCNT counter value
GPT320.GTPR register
E400h
C154h
9682h
1100h
Time
0000 0000h
GTIOC0A pin input
GTIOC0B pin input
GPT320.GTCCRA register
1100h
GPT320.GTCCRB register
E400h
9682h
C154h
[Setting examples]
GTICASR setting input capture at both edges
GTICBSR setting input capture at the rising edge
Figure 19.16
Example of input capture operation
Figure 19.17 shows an example for setting an input capture operation with count operation by the count clock.
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Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.16, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.16, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Select input capture source
Select the input capture source in GTICASR and GTICBSR.
(In Figure 19.16, GTICASR = 0000 0F00h, GTICBSR = 0000 3000h.)
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 19.17
19.3.2
Example for setting input capture operation
Buffer Operation
The following buffer operations can be set with GTBER:
Buffer operation with GTPR and GTPBR combined
Buffer operation with GTCCRA, GTCCRC, and GTCCRD combined
Buffer operation with GTCCRB, GTCCRE, and GTCCRF combined.
19.3.2.1
GTPR register buffer operation
GTPBR can function as a buffer register for GTPR. The buffer transfer is performed at an overflow (during up-counting)
or an underflow (during down-counting) in saw-wave mode or in event count, and at a trough in triangle-wave mode.
In saw-wave mode or in event count, the buffer transfer is performed when the following counter clear operations occur
during counting:
Clear by hardware sources (the clear source is selected in GTCSR[23:0])
Clear by software (when GTCSR.CCLR bit is 1 and GTCLR[n] bit is set to 1, n = channel number).
Figure 19.18 to Figure 19.20 show examples of GTPR buffer operation and Figure 19.21 shows an example for setting
GTPR buffer operation.
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19. General PWM Timer (GPT)
GTCNT counter value
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GTPBR register
Register write
bbbb
Register write
cccc
Buffer transfer
at overflow
GTPR register
Figure 19.18
aaaa
Register write
Buffer transfer
at overflow
bbbb
Buffer transfer
at overflow
cccc
Example of GTPR buffer operation (saw waves in up-counting)
GTCNT counter value
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GTPBR register
aaaa
bbbb
Buffer transfer
at underflow
GTPR register
Figure 19.19
aaaa
Register write
cccc
Buffer transfer
at underflow
bbbb
Buffer transfer
at underflow
cccc
Example of GTPR buffer operation (saw waves in down-counting)
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19. General PWM Timer (GPT)
GTCNT counter value
cccc
bbbb
aaaa
0000 0000h
GTPBR register
Time
aaaa
bbbb
Buffer transfer at trough
GTPR register
Figure 19.20
cccc
Buffer transfer at trough
aaaa
bbbb
Buffer transfer at trough
cccc
Example of GTPR buffer operation (triangle waves)
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.18 and Figure 19.19, 000b (saw-wave PWM mode) is set,
and in Figure 19.20, 100b (triangle-wave PWM mode 1) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.18, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting). In Figure 19.19, after 10b is set in
GTUDDTYC[1:0], 00b is set in GTUDDTYC[1:0] (down-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set buffer operation
Set buffer operation with GTBER.PR[1:0]. (In Figure 19.18, Figure 19.19,
and Figure 19.20, PR[1:0] = 01b.)
Set buffer value
For buffer operation, set a value in one cycle after the current cycle in
GTPBR.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set a value in one cycle after the current cycle in
GTPBR.
Figure 19.21
Example for setting GTPR buffer operation
19.3.2.2
Buffer operation for GTCCRA and GTCCRB
GTCCRC can function as the GTCCRA buffer register and GTCCRD can function as the GTCCRC buffer register
(double-buffer register for GTCCRA). Similarly, GTCCRE can function as the GTCCRB buffer register and GTCCRF
can function as the GTCCRE buffer register (double-buffer register for GTCCRB).
To set GTCCRA or GTCCRB to function as a double buffer, set GTBER.CCRA[1:0] or GTBER.CCRB[1:0] to 10b or
11b. For single buffer operation, set 01b. To set GTCCRA or GTCCRB to not function as a buffer, set 00b.
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19. General PWM Timer (GPT)
When GTCCRA or GTCCRB functions as Output Compare Register
Buffer transfer has the following cases:
Buffer transfer by overflow or underflow
Buffer transfer is performed at an overflow (during up-counting) or an underflow (during down-counting) in sawwave mode or in event count operation. In triangle-wave mode, buffer transfer is performed at a trough (trianglewave PWM mode 1) or a crest and trough (triangle-wave PWM mode 2).
Buffer transfer by counter clear
In saw-wave mode or in event count operation, during counting, buffer transfer (which is the same as an overflow
during up-counting or an underflow during down-counting) is performed by the counter clear sources the same as in
the case of section 19.3.2.1, GTPR register buffer operation.
In triangle-wave mode, buffer transfer is not performed by the counter clear.
Forcible buffer transfer
When GTBER.CCRSWT bit is set to 1 while the count operation stops, the GTCCRA and the GTCCRB register
buffer transfer are performed forcibly in saw-wave mode, in event count operation and in triangle-wave mode.
Additionally buffer transfer from the GTCCRD register to temporary register A and from the GTCCRF register to
temporary register B are performed in saw-wave 1 shot pulse mode or triangle-wave PWM mode 3.
Figure 19.22 to Figure 19.24 show examples of GTCCRA and GTCCRB buffer operation and Figure 19.25 shows an
example for setting GTCCRA and GTCCRB buffer operation.
GPT320.GCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT320.GTCCRC register
bbbb
Register write
cccc
Buffer transfer
at overflow
GPT320.GTCCRA register
aaaa
Register write
bbbb
Buffer transfer
at overflow
Buffer transfer
at overflow
cccc
GTIOC0A pin output
Figure 19.22
Example of GTCCRA and GTCCRB buffer operation with output compare, saw waves in upcounting, high output at GTCCRA compare match, and low output at cycle end
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
Register write
cccc
GPT320.GTCCRD register
Buffer transfer at
trough
bbbb
GPT320.GTCCRC register
cccc
Buffer transfer at
trough
GPT320.GTCCRA register
Buffer transfer at
trough
aaaa
Buffer transfer at
trough
bbbb
cccc
GTIOC0A pin output
Figure 19.23
Example of GTCCRA and GTCCRB double buffer operation with output compare, triangle waves,
buffer operation at trough, output toggled at GTCCRA compare match, and output retained at
cycle end
GPT320.GTCNT counter value
GPT320.GTPR register
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT320.GTCCRF register
cccc
bbbb
Buffer transfer at
trough
GPT320.GTCCRE register
aaaa
GPT320.GTCCRB register
Register write
Register write
dddd
Buffer transfer at
crest
Buffer transfer at
trough
cccc
bbbb
dddd
Buffer transfer at
trough
Buffer transfer at
crest
Buffer transfer at
trough
aaaa
cccc
bbbb
Buffer transfer at
crest
Buffer transfer at
crest
dddd
GTIOC0B pin output
Figure 19.24
Example of GTCCRA and GTCCRB double buffer operation with output compare, triangle waves,
buffer operation at both troughs and crests, output toggled at GTCCRB compare match, and
output retained at cycle end
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.22, 000b (saw-wave PWM mode) is set, in Figure 19.23, 100b (triangle-wave PWM mode 1) is set, and
in Figure 19.24, 101b (triangle-wave PWM mode 2) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.22, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.22, GTIOA[4:0] = 00110b, in Figure 19.23, GTIOA[4:0] = 00011b, and in Figure 19.24, GTIOB[4:0] =
00011b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
(In Figure 19.22, CCRA[1:0] = 01b, in Figure 19.23, CCRA[1:0] = 1xb, and in Figure 19.24, CCRB[1:0] = 1xb.)
Set compare match value
Set the GTIOCA pin transition in GTCCRA and GTIOCB pin transition in the GTCCRB.
Set buffer value
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in one cycle after the current cycle (in saw-wave
mode or triangle-wave mode with buffer transfer at trough or crest) or half cycle after the current cycle (in trianglewave mode with buffer transfer at both trough and crest) in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in two cycles after the current cycle
(in saw-wave mode or triangle-wave mode with buffer transfer at trough or crest) or one cycle after the current cycle
(in triangle-wave mode with buffer transfer at both trough and crest) in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in one cycle after the current cycle (in
saw-wave mode or triangle-wave mode with buffer transfer at trough or crest) or half cycle after the current cycle (in
triangle-wave mode with buffer transfer at both trough and crest) in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in two cycles after the
current cycle (in saw-wave mode or triangle-wave mode with buffer transfer at trough or crest) or one cycle after the
current cycle (in triangle-wave mode with buffer transfer at both trough and crest) in GTCCRD and GTCCRF,
respectively.
Figure 19.25
(2)
Example for setting GTCCRA and GTCCRB buffer operation for output compare
When GTCCRA or GTCCRB functions as Input Capture Register
When an input capture is generated, the GTCNT counter value is transferred to GTCCRA and GTCCRB and the stored
GTCCRA and GTCCRB register values are transferred to the buffer registers. In input capture operation, the buffer
transfer is not performed by the counter clear.
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Figure 19.26 and Figure 19.27 show examples of GTCCRA and GTCCRB buffer operation and Figure 19.28 shows an
example for setting GTCCRA and GTCCRB buffer operation.
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
GTIOC0A pin input
GPT320.GTCCRA register
aaaa
Buffer transfer at input
capture
Buffer transfer at input
capture
aaaa
GPT320.GTCCRC register
Figure 19.26
bbbb
cccc
Buffer transfer at
input capture
bbbb
Example of GTCCRA and GTCCRB buffer operation with input capture at both edges of GTIOC0A
input, saw waves in up-counting, and GTCNT counter cleared at both edges of GTIOC0A input
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
GTIOC0B pin input
GPT320.GTCCRB register
aaaa
Buffer transfer at input
capture
GPT320.GTCCRE register
Figure 19.27
Buffer transfer at input
capture
aaaa
Buffer transfer at input
capture
GPT320.GTCCRF register
bbbb
Buffer transfer at input
capture
cccc
Buffer transfer at
input capture
bbbb
Buffer transfer at
input capture
aaaa
Example of GTCCRA and GTCCRB double buffer operation with input capture at both edges of
GTIOC0B input, saw waves in up-counting, and GTCNT counter cleared at both edges of
GTIOC0B input
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0] and count clear source with GTCSR.
(In Figure 19.26, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 0F00h, and in Figure
19.27, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 F000h.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.26, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Select input capture source
Select input capture source in the GTICASR register and GTICBSR register.
(In Figure 19.26, GTICASR = 0000 0F00h, and in Figure 19.27, GTICBSR = 0000 F000h.)
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
(In Figure 19.26, CCRA[1:0] = 01b, and in Figure 19.27, CCRB = 1xb.)
Start count operation
Set GTCR.CST to 1 to start count operation.
Figure 19.28
19.3.3
Example for setting GTCCRA and GTCCRB buffer operation for input capture
PWM Output Operating Mode
The GPT can output PWM waveforms to the GTIOCA pin or GTIOCB pin by a compare match between the GTCNT
counter and GTCCRA or GTCCRB.
By setting GTDTCR and GTDVU, the compare match value for a negative-phase waveform with dead time can
automatically be set to GTCCRB.
19.3.3.1
Saw-wave PWM mode
In saw-wave PWM mode, GTCNT performs saw-wave (half-wave) operation by setting the cycle in GTPR and a PWM
waveform is output to the GTIOCA or GTIOCB pin when a GTCCRA or GTCCRB compare match occurs. The pin
output value can be selected from low output, high output, or toggle output separately for a compare match and for the
cycle end according to the GTIOR setting
Figure 19.29 shows an example of saw-wave PWM mode operation, and Figure 19.30 shows an example for setting sawwave PWM mode.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT320.GTCCRC register
Register write
cccc
eeee
Buffer transfer
at overflow
GPT320.GTCCRA register
aaaa
Register write
GPT320.GTCCRE register
cccc
Register write
dddd
bbbb
Buffer transfer
at overflow
Buffer transfer
at overflow
eeee
Register write
Register write
ffff
Buffer transfer
at overflow
GPT320.GTCCRB register
Register write
dddd
Buffer transfer
at overflow
Buffer transfer
at overflow
ffff
GTIOC0A pin output
GTIOC0B pin output
Figure 19.29
Example of saw-wave PWM mode operation with up-counting, buffer operation, high output at
GTCCRA/GTCCRB compare match, and low output at cycle end
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]. (In Figure 19.29, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.29, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.29, GTIOA[4:0] = 00110b and GTIOB[4:0] = 00110b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER. (In Figure 19.29, CCRA[1:0] = 01b and CCRB[1:0] = 01b.)
Set compare match value
Set the GTIOCA pin transition in GTCCRA and GTIOCB pin transition in GTCCRB.
Set buffer value
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in one cycle after the current cycle in GTCCRC
and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in two cycles after the current cycle
in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in one cycle after the current cycle in GTCCRC
and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in two cycles after the current cycle
in GTCCRD and GTCCRF, respectively.
Figure 19.30
Example for setting saw-wave PWM mode
19.3.3.2
Saw-wave one-shot pulse mode
The saw-wave one-shot pulse mode is a mode in which the cycle is set in GTPR, the GTCNT counter performs saw-
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19. General PWM Timer (GPT)
wave (half-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of
GTCCRA or GTCCRB with buffer operation fixed.
Buffer operation in saw-wave one-shot pulse mode is different from the usual buffer operation. Buffer transfer is
performed from the following:
GTCCRC to GTCCRA at the cycle end
GTCCRE to GTCCRB at the cycle end
GTCCRD to temporary register A at the cycle end
GTCCRF to temporary register B at the cycle end
Temporary register A to GTCCRA at a GTCCRA compare match
Temporary register B to GTCCRB at a GTCCRB compare match.
The pin output value can be selected from low output, high output, or toggle output separately for a compare match and
the cycle end according to the GTIOR setting. When the GTBER.CCRSWT bit is set to 1 while count operation stops,
the buffer is transferred forcibly from the GTCCRD register to temporary register A and from the GTCCRF register to
temporary register B. By setting GTDTCR and GTDVU, a compare match value for a negative-phase waveform with
dead time can automatically be set to GTCCRB.
Figure 19.31 shows an example of saw-wave one-shot pulse mode operation, and Figure 19.32 shows an example for
setting saw-wave one-shot pulse mode.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT320.GTCCRD register
Register write
Register write
eeee
Buffer transfer
at overflow
Temporary register A
gggg
eeee
Register write
GPT320.GTCCRC register
Register write
Register write
dddd
Buffer transfer at
compare match
GPT320.GTCCRA register
Buffer transfer
at overflow
bbbb
Buffer transfer at
compare match
dddd
gggg
Register write
GPT320.GTCCRF register
Buffer transfer
at overflow
Buffer transfer
at overflow
eeee
Register write
Register write
ffff
Buffer transfer
at overflow
Temporary register B
hhhh
Register write
Register write
Register write
cccc
GPT320.GTCCRE register
Buffer transfer at
compare match
GPT320.GTCCRB register
ffff
aaaa
hhhh
Buffer transfer
at overflow
cccc
Buffer transfer at
compare match
Buffer transfer
at overflow
ffff
GTIOC0A pin output
GTIOC0B pin output
Figure 19.31
Example of saw-wave one-shot pulse mode operation with up-counting, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at GTCCRA/
GTCCRB compare match, and output retained at cycle end
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.31, 001b (saw-wave one-shot pulse mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.31, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0]
(up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.31, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer value
Set the GTIOCA pin transition immediately after the count start in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Set forcible buffer transfer
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly.
Set buffer value
Set the GTIOCA pin transition in one cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in one cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Figure 19.32
Example for setting saw-wave one-shot pulse mode
19.3.3.3
Triangle-wave PWM mode 1 (32-bit transfer at trough)
The triangle-wave PWM mode 1 is a mode in which the cycle is set in GTPR. The GTCNT counter performs trianglewave (full-wave) operation, and a PWM waveform is output to the GTIOCA or GTIOCB pin when a GTCCRA or
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19. General PWM Timer (GPT)
GTCCRB compare match occurs. Buffer transfer is performed at the trough. The pin output value can be selected from
low output, high output, or toggle output separately for a compare match and for the cycle end according to the GTIOR
setting.
By setting GTDTCR and GTDVU, a compare match value for a negative-phase waveform with dead time can
automatically be set to GTCCRB.
Figure 19.33 shows an example of a triangle-wave PWM mode 1 operation, and Figure 19.34 shows an example for
setting a triangle-wave PWM mode 1.
GPT320.GTCNT counter value
GPT320.GTPR register
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT320.GTCCRC register
Register write
dddd
Register write
ffff
Buffer transfer at
trough
GPT320.GTCCRA register
bbbb
Register write
GPT320.GTCCRE register
dddd
Register write
cccc
aaaa
ffff
Register write
eeee
Buffer transfer at
trough
GPT320.GTCCRB register
Buffer transfer at
trough
cccc
Buffer transfer at
trough
eeee
GTIOC0A pin output
GTIOC0B pin output
Figure 19.33
Example of triangle-wave PWM mode 1 operation with buffer operation, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at GTCCRA/
GTCCRB register compare match, and output retained at cycle end
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.33, 100b (triangle-wave PWM mode 1) is set.)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.33, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
(In Figure 19.33, CCRA[1:0] = 01b and CCRB[1:0] = 01b.)
Set compare match value
Set the GTIOCA pin and GTIOCB pin transitions in GTCCRA and GTCCRB,
respectively.
Set buffer value
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in one cycle
after the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in
two cycles after the current cycle in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in one cycle
after the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in
two cycles after the current cycle in GTCCRD and GTCCRF, respectively.
Figure 19.34
Example for setting triangle-wave PWM mode 1
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19.3.3.4
19. General PWM Timer (GPT)
Triangle-wave PWM mode 2 (32-bit transfer at crest and trough)
Similarly to triangle-wave PWM mode 1, in triangle-wave PWM mode 2 the cycle is set in GTPR. The GTCNT counter
performs triangle-wave (full-wave) operation, and a PWM waveform is output to the GTIOCA or GTIOCB pin when a
GTCCRA or GTCCRB compare match occurs. The buffer transfer is performed at both crests and troughs. The pin
output value can be selected from low output, high output, or toggle output separately for a compare match and for the
cycle end according to the GTIOR setting.
By setting GTDTCR and GTDVU, a compare match value for a negative-phase waveform with dead time can
automatically be set to GTCCRB.
Figure 19.35 shows an example of triangle-wave PWM mode 2 operation, and Figure 19.36 shows an example for setting
triangle-wave PWM mode 2.
GPT320.GTCNT counter value
GPT320.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
GPT320.GTCCRC register
GPT320.GTCCRA register
Register write
ffff
GPT320.GTCCRE register
dddd
hhhh
Buffer transfer at
trough
Register write
cccc
Buffer transfer at
crest
GPT320.GTCCRB register
aaaa
dddd
ffff
Register write
eeee
Register write
Buffer transfer at
crest
bbbb
Register write
Register write
eeee
Buffer transfer at
crest
hhhh
Register write
gggg
Buffer transfer at
trough
cccc
Buffer transfer at
crest
gggg
GTIOC0A pin output
GTIOC0B pin output
Figure 19.35
Example of triangle-wave PWM mode 2 operation with buffer operation, low output from the
GTIOC0A pin and high output from the GTIOC0B pin at count start, output toggled at GTCCRA/
GTCCRB compare match, and output retained at cycle end
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.35, 101b (triangle-wave PWM mode 2) is set.)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.35, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation
Set buffer operation with CCRA and CCRB in GTBER.
(In Figure 19.35, CCRA[1:0] = 01b and CCRB[1:0] = 01b.)
Set compare match value
Set the GTIOCA pin and GTIOCB pin transitions in GTCCRA and GTCCRB,
respectively.
Set buffer value
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in half cycle
after the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in
one cycle after the current cycle in GTCCRD and GTCCRF, respectively.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
For buffer operation, set the GTIOCA pin and GTIOCB pin transitions in half cycle
after the current cycle in GTCCRC and GTCCRE, respectively.
For double buffer operation, also set the GTIOCA pin and GTIOCB pin transitions in
one cycle after the current cycle in GTCCRD and GTCCRF, respectively.
Figure 19.36
Example for setting triangle-wave PWM mode 2
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19.3.3.5
19. General PWM Timer (GPT)
Triangle-wave PWM mode 3 (64-bit transfer at trough)
The triangle-wave PWM mode 3 is a mode in which the cycle is set in GTPR. The GTCNT counter performs trianglewave (full-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of
GTCCRA or GTCCRB with buffer operation fixed. Buffer operation in triangle-wave PWM mode 3 is different from the
usual buffer operation. Buffer transfer is performed from the following:
GTCCRC to GTCCRA at the trough
GTCCRE to GTCCRB at the trough
GTCCRD to temporary register A at the trough
GTCCRF to temporary register B at the trough
Temporary register A to GTCCRA at the crest
Temporary register B to GTCCRB at the crest.
The pin output value can be selected from low output, high output, or toggle output separately for a compare match and
for the cycle end according to the GTIOR setting.
By setting GTDTCR and GTDVU, a compare match value for a negative-phase waveform with dead time can
automatically be set to GTCCRB.
Figure 19.37 shows an example of triangle-wave PWM mode 3 operation, and Figure 19.38 shows an example for setting
triangle-wave PWM mode 3.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
hhhh
gggg
ffff
eeee
dddd
cccc
bbbb
aaaa
0000 0000h
Time
Register write
Register write
GPT320.GTCCRD register
hhhh
Buffer transfer at
trough
Temporary register A
hhhh
ffff
Register write
Register write
GPT320.GTCCRC register
dddd
Buffer transfer at
crest
GPT320.GTCCRA register
bbbb
Buffer transfer at
trough
dddd
ffff
Register write
Buffer transfer at
crest
hhhh
Register write
gggg
GPT320.GTCCRF register
Buffer transfer at
trough
eeee
Temporary register B
gggg
Register write
Register write
GPT320.GTCCRE register
cccc
Buffer transfer at
crest
GPT320.GTCCRB register
aaaa
eeee
Buffer transfer at
trough
cccc
Buffer transfer at
crest
gggg
GTIOC0A pin output
GTIOC0B pin output
Figure 19.37
Example of triangle-wave PWM mode 3 operation with low output from the GTIOC0A pin and high
output from the GTIOC0B pin at count start, output toggled at GTCCRA/GTCCRB compare match,
and output retained at cycle end
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.37, 110b (triangle-wave PWM mode 3) is set.)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.37, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer value
Set the GTIOCA pin transition immediately after the count start in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Set forcible buffer transfer
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly.
Set buffer value
Set the GTIOCA pin transition in one cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in one cycle after the current cycle in GTCCRC and
GTCCRD and the GTIOCB pin transition in GTCCRE and GTCCRF.
Figure 19.38
19.3.4
Example for setting triangle-wave PWM mode 3
Automatic Dead Time Setting Function
By setting GTDTCR, a compare match value for a negative waveform with dead time obtained by a compare match
value for a positive waveform (GTCCRA value) and specified dead time value (GTDVU value) can automatically be set
to GTCCRB.
The automatic dead time setting function can be used in saw-wave one-shot pulse mode and all the triangle PWM modes.
Writing to GTCCRB is prohibited when the automatic dead time setting function is used. Dead time setting beyond the
cycle is also prohibited. Values for automatic dead time setting can be read from GTCCRB. The automatic dead time
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19. General PWM Timer (GPT)
value setting to GTCCRB is performed at the next count clock cycle when registers that are used for calculating the
automatic dead time value are updated.
Figure 19.39 to Figure 19.42 show examples of automatic dead time setting function operation. Figure 19.43 and Figure
19.44 show the setting examples.
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
00000000h
Buffer transfer
at overflow
Time
Buffer transfer
at compare match
Buffer transfer
Buffer transfer
at overflow
at compare match
GPT320.GTCCRA register
GPT320.GTCCRB register
(Automatic setting)
GTCCRA - GTDVU
GTCCRA + GTDVU
GTCCRA
- GTDVU
GTCCRA + GTDVU
GTIOC0A pin output
GTDVU
GTIOC0B pin output
Figure 19.39
GTDVU
GTDVU
GTDVU
Example of automatic dead time setting function operation in saw-wave one-shot pulse mode,
up-counting, and active-high
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
00000000h
Buffer transfer
at underflow
Time
Buffer transfer
at compare match
Buffer transfer
Buffer transfer
at underflow at compare match
GPT320.GTCCRA register
GPT320.GTCCRB register
(Automatic setting)
GTCCRA + GTDVU
GTCCRA - GTDVU
GTCCRA
+ GTDVU
GTCCRA - GTDVU
GTIOC0A pin output
GTIOC0B pin output
Figure 19.40
GTDVU
GTDVU
GTDVU
GTDVU
Example of automatic dead time setting function operation in saw-wave one-shot pulse mode,
down-counting, and active-high
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GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
Time
00000000h
Buffer transfer at trough
Buffer transfer at trough
GPT320.GTCCRA register
GPT320.GTCCRB register
(Automatic setting)
GTCCRA - GTDVU
GTCCRA - GTDVU
GTIOC0A pin output
GTDVU
GTIOC0B pin output
Figure 19.41
GTDVU
GTDVU
GTDVU
Example of automatic compare-match value setting function with dead time in triangle-wave
PWM mode 1, and active-high
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
00000000h
Time
Buffer transfer
at trough
Buffer transfer
at crest
Buffer transfer
at trough
Buffer transfer
at crest
GPT320.GTCCRA register
GPT320.GTCCRB register
(Automatic setting)
GTCCRA - GTDVU
GTCCRA - GTDVU
GTCCRA - GTDVU
GTCCRA - GTDVU
GTIOC0A pin output
GTDVU
GTDVU
GTDVU
GTDVU
GTIOC0B pin output
Figure 19.42
Example of automatic compare-match value setting function with dead time in triangle-wave
PWM mode 2 or 3, and active-high
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]. (In Figure 19.39 and Figure 19.40, 001b (saw-wave one-shot pulse
mode) is set. In Figure 19.42, 110b (triangle-wave PWM mode 3) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.39, 01b is set after 11b is set in GTUDDTYC[1:0] (up count) In Figure 19.40, 00b is set after 10b is set in
GTUDDTYC[1:0] (down count).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.39, Figure 19.41, and Figure 19.42, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer value for compare match
Set the GTIOCA pin transition immediately after the count start in GTCCRC and GTCCRD.
Set forcible buffer transfer for compare match
Set GTBER.CCRSWT to 1 to transfer buffer register data forcibly to GTCCRA.
Set buffer value for compare match
Set the GTIOCA pin transition in one cycle after the current cycle in GTCCRC and GTCCRD.
Set automatic dead time setting function
Set GTDTCR.TDE to 1 to enable the automatic dead time setting function.
Set dead time value
Set the dead time value in GTDVU.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
Set the GTIOCA pin transition in one cycle after the current cycle in GTCCRC and GTCCRD.
Figure 19.43
Example for setting automatic dead time setting function in saw-wave one-shot pulse mode, and
triangle-wave PWM mode 3
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]. (In Figure 19.41, 100b (triangle-wave PWM mode 1) is set. In Figure
19.42, 101b (triangle-wave PWM mode 2) is set.)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
Set GTIOC pin function
Set the GTIOC pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR.
(In Figure 19.41 and Figure 19.42, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b.)
Enable GTIOC pin output
Set to enable the GTIOC pin output with OAE and OBE in GTIOR.
Set buffer operation for compare match
Set buffer operation with CCRA in GTBER.
Set compare match value
Set the GTIOCA pin transition in GTCCRA.
Set buffer value for compare match
For buffer operation, set the GTIOCA pin transition in one cycle after the current cycle (in triangle-wave PWM mode 1)
or half cycle after the current cycle (in triangle-wave PWM mode 2) in GTCCRC. For double buffer operation, also set
the GTIOCA pin transition in two cycles after the current cycle (in triangle-wave PWM mode 1) or one cycle after the
current cycle (in triangle-wave PWM mode 2) in GTCCRD.
Set automatic dead time setting function
Set GTDTCR.TDE to 1 to enable the automatic dead time setting function.
Set dead time value
Set the dead time value in GTDVU.
Start count operation
Set GTCR.CST to 1 to start count operation.
Set buffer value for each cycle
When the compare match register is used for buffer operation, set the GTIOCA pin transition in one cycle after the
current cycle (in triangle-wave PWM mode 1) or half cycle after the current cycle (in triangle-wave PWM mode 2) in
GTCCRC.
Figure 19.44
19.3.5
Example for setting automatic dead time setting function in triangle-wave PWM mode 1 or 2
Count Direction Changing Function
The count direction of the GTCNT counter can be changed by modifying the UD bit in GTUDDTYC.
In saw-wave mode, if the UD bit in GTUDDTYC is modified during count operation, the count direction is changed at an
overflow (when modified during up-counting) or an underflow (when modified during down-counting). If the
GTUDDTYC.UD bit is modified while the count operation stops and the GTUDDTYC.UDF bit is 0, the
GTUDDTYC.UD bit modification is not reflected at the start of counting and the count direction is changed at an
overflow or an underflow. If the UDF bit is set to 1 while the count operation stops, the GTUDDTYC.UD bit value at
that time is reflected at the start of counting.
In triangle-wave mode, the count direction does not change even though the UD bit in GTUDDTYC is modified during
the count operation. Similarly, even though the GTUDDTYC.UD bit is modified while the count operation stops and
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GTUDDTYC.UDF bit is 0, the GTUDDTYC.UD bit value is not reflected to the count operation. If the
GTUDDTYC.UDF bit is set to 1 while the count operation stops, the GTUDDTYC.UD bit value at that time is reflected
at the start of counting.
If the count direction changes during a saw-wave count operation, the GTPR value after the start of up-counting is
reflected in the count cycle during up-counting and the GTPR value before the start of down-counting is reflected during
down-counting.
Figure 19.45 shows an example of count direction changing function operation.
GTCNT counter value
bbbb
aaaa
0000 0000h
Time
Register write
GTUDDTYC.UD bit
(Count direction setting)
Up-counting
GTST.TUCF flag
(Count direction flag)
19.3.6
aaaa
Up-counting
Down-counting
Register write
bbbb
GTPBR register
Figure 19.45
Down-counting
Up-counting
Register write
GTPR register
Register write
Register write
aaaa
Up-counting
Register write
Register write
bbbb
Buffer transfer at
overflow
Buffer transfer at
overflow
bbbb
aaaa
Buffer transfer at
underflow
Buffer transfer at
underflow
Buffer transfer at
overflow
bbbb
Example of a count direction changing function operation during buffer operation
Function of Output Duty 0% and 100%
The output duty of the GTIOCA pin and the GTIOCB pin are set to 0% or 100% by changing the GTUDDTYC.OADTY
bit or GTUDDTYC.OBDTY bit.
In saw-wave mode, if the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified during the count
operation, the output duty setting is reflected at an overflow (when modified during up-counting) or an underflow (when
modified during down-counting). If the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified while
the count operation stops and the GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is 0, the output duty
modification is not reflected at the start of counting. The output duty changes at an overflow or an underflow. If the
GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is set to 1 while the count operation stops, the
GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit value at that time is reflected at the start of counting.
In triangle-wave mode, if the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified during the count
operation, the output duty setting is reflected an underflow.
If the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified while the count operation stops and the
GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is 0, the output duty modification is not reflected at the start
of counting. The output duty changes at an underflow. If the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit
is modified while the count operation stops and the GTUDDTYC.OADTYF or the GTUDDTYC.OBDTYF bit is 1, the
output duty modification is reflected at the start of counting.
In performing 0%/100% duty operation, GPT internally continues to:
Perform compare match operation
Set compare match flag
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Output interrupt
Perform buffer operation.
When the control is changed from 0% or 100% duty setting to compare match, the output value of GTIOCA pin at cycle
end is decided by GTIOR.GTIOA[3:2] and GTUDDTYC.OADTYR. The output value of GTIOCB pin at cycle end is
decided by GTIOR.GTIOB[3:2] and GTUDDTYC.OBDTYR.
When GTIOR.GTIOA[3:2] and GTIOR.GTIOB[3:2] are set to 01b, the output pins output low at cycle end. When
GTIOR.GTIOA[3:2] and GTIOR.GTIOB[3:2] are set to 10b, the output pins output high at cycle end.
GTUDDTYC.OADTYR selects the value that is the object of output retained/toggled at cycle end, when
GTIOR.GTIOm[3:2] are set to 00b (output retained at cycle end) or when GTIOR.GTIOm[3:2] are set to 11b (output
toggled at cycle end). Table 19.6 shows the values of GTIOCA/GTIOCB pin output at cycle end.
Table 19.6
Output values after releasing 0%/100% duty setting (m = A, B)
GTIOR.GTIOm[3:2]
Compare match value
at cycle end masked
by 0%/100% duty setting
GTUDDTYC.OmDTYR
in duty 0% setting
GTUDDTYC.OmDTYR
in duty 100% setting
0
1
0
1
00
(Output retained at cycle end)
0
0
0
1
0
1
0
1
1
1
01
(Low output at cycle end)
—
0
0
0
0
10
(High output at cycle end)
—
1
1
1
1
11
(Output toggled at cycle end)
0
1
1
0
1
1
1
0
0
0
Figure 19.46 shows an example of output duty 0% and 100% function operation.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
bbbb
aaaa
0000 0000h
Time
Register write
GTUDDTYC.OADTY
00b
Register write
Register write
11b
10b
00b
GTIOC0A pin output
GTIOC0B pin output
0%
100%
[Setting examples]
GPT320.GTIOR.GTIOA[4:0] bits:
00011b
initial output of low, output toggled at compare match, output retained at cycle end
GPT320.GTUDDTYC.OADTYR bit: 0b
Applied the value of duty 0%/100% output to GTIOA[3:2] bits function after 0%/100% duty
setting is released.
GPT320.GTIOR.GTIOB[4:0] bits: 00011b
initial output of low, output toggled at compare match, output retained at cycle end
GPT320.GTUDDTYC.OBDTYR bit: 1
Applied the value of masked compare match output to GTIOB[3:2] bits function after
0%/100% duty setting is released
Figure 19.46
19.3.7
Example of output duty 0% and 100% function
Hardware Count Start/Count Stop and Clear Operation
The GTCNT counter can be started, stopped, or cleared by the following hardware sources:
External trigger input
ELC event input
GTIOCA/GTIOCB pin input.
19.3.7.1
Hardware start operation
The GTCNT counter can be started by selecting a hardware source using GTSSR.
Figure 19.47 shows an example of a count start operation by a hardware source. Figure 19.48 shows the setting example.
GTCNT counter value
GTPR register
Count started at ELC_GPTA input
0000 0000h
Time
ELC_GPTA input
Figure 19.47
Example of count start operation by hardware source started at the input of the signal from the
ELC_GPTA event
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Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.47, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.47, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
(In Figure 19.47, 0000 0000h is set.)
Set hardware count start
Select a hardware source for starting count operation in GTSSR register.
(In Figure 19.47, GTSSR.SSELCA = 1)
Set hardware source operation
Set operation of the hardware source selected by GTSSR register and
start counting. (In Figure 19.47, the ELC_GPTA event input operation is
set.)
Figure 19.48
Example setting count start operation by hardware source
19.3.7.2
Hardware stop operation
The GTCNT counter can be stopped by selecting a hardware source using GTPSR.
Figure 19.49 shows an example of a count stop operation by a hardware source. Figure 19.50 shows the setting example.
In this example, the count operation stops at the edge of the ELC_GPTA input and restarts at the edges of the
ELC_GPTB event input.
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19. General PWM Timer (GPT)
GTCNT counter value
Count stopped at
ELC_GPTA input
Count started at
ELC_GPTB input
GTPR register
Software start
0000 0000h
Time
ELC_GPTA input
ELC_GPTB Input
Figure 19.49
Example of count stop operation by hardware source started by software, stopped at ELC_GPTA
input, and restarted at ELC_GPTB input
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.49, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.49, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
(In Figure 19.49, 0000 0000h is set.)
Set hardware count start
Select a hardware source for starting count operation in GTSSR register,
and wait for count start by the hardware source. (In Figure 19.49,
GTSSR.SSELCB = 1.)
Set hardware count stop
Select a hardware source for stopping count operation in GTPSR
register and wait for count stop by the hardware source. (In Figure 19.49,
GTPSR.PSELCA = 1.)
Set hardware source operation
Set operation of the hardware source selected in GTSSR register or
GTPSR register, and start or stop counting. (In Figure 19.49, ELC_GPTA
input operation and ELC_GPTB input operation are set.)
Figure 19.50
Example for setting count stop operation by hardware source
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Figure 19.51 shows an example of a count start/stop operation by a hardware source. Figure 19.52 shows the setting
example. In this example, the counter operates during the high-level periods of the external trigger input GTETRGA.
Count stopped at the falling Count started at the rising
edge of GTETRGA
edge of GTETRGA
GTCNT counter value
GTPR register
Count started at the rising
edge of GTETRGA
0000 0000h
Time
GTETRGA pin input
Figure 19.51
Example of count start/stop operation by hardware source started at rising edge of GTETRGA pin
input, and stopped at falling edge of GTETRGA pin input
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
(In Figure 19.51, 000b (saw-wave PWM mode) is set.)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
(In Figure 19.51, after 11b is set in GTUDDTYC[1:0], 01b is set in
GTUDDTYC[1:0] (up-counting).)
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in GTPR.
Set initial value for counter
Set the initial value in the GTCNT counter.
(In Figure 19.51, 0000 0000h is set.)
Set hardware count start
Select a hardware source for starting count operation with GTSSR
register and wait for count start by the hardware source.
(In Figure 19.51, GTSSR.SSGTRGAR = 1)
Set hardware count stop
Select a hardware source for stopping count operation with GTPSR
register and wait for count stop by the hardware source.
(In Figure 19.51, GTPSR.PSGTRGAF = 1.)
Set hardware source operation
Set operation of the hardware source selected in GTSSR or GTPSR and
start or stop counting.
(In Figure 19.51, the GTETRGA pin operation is set.)
Figure 19.52
Example for setting count start/stop operation by hardware source
19.3.7.3
Hardware clear operation
The GTCNT counter can be cleared by selecting a hardware source using GTCSR.
Note:
The GPTn_OVF/GPTn_UDF (n = 0 to 6) interrupt (overflow/underflow interrupt) is not generated when the
GTCNT counter is cleared by a hardware source or by software.
Figure 19.53 and Figure 19.54 show examples of the GTCNT counter clearing operation by a hardware source. Figure
19.55 shows the setting example. In this example, the GTCNT counter starts at the edge of the ELC_GPTA input, and the
counter stops/clears at the edge of the ELC_GPTB input.
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19. General PWM Timer (GPT)
GTCNT counter value
Count stopped/cleared at
ELC_GPTB input
Count started at
ELC_GPTA input
Clear by software (by writing 1 to
corresponding channel number bit of
GTCLR register)
Count started at
ELC_GPTA input
0000 0000h
Time
ELC_GPTA input
ELC_GPTB input
Figure 19.53
Examples of count clearing operation by hardware source in saw wave up-counting, started at
ELC_GPTA input, and stopped/cleared at ELC_GPTB input
GTCNT counter value
Count started at
ELC_GPTA input
Count stopped/cleared at
ELC_GPTB input
Count started at
ELC_GPTA input
GTPR register
0000 0000h
Clear by software (by writing 1 to
corresponding channel number bit
of GTCLR register)
Time
ELC_GPTA input
ELC_GPTB input
Figure 19.54
Examples of count clearing operation by hardware source in saw wave down-counting, started at
ELC_GPTA input, and stopped/cleared at ELC_GPTB input
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0].
In Figure 19.53 and Figure 19.54, 000b (saw-wave PWM mode) is set.
Set count direction
Select the count direction (up or down) with the GTUDDTYC register.
In Figure 19.53, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting). In
Figure 19.54, after 10b is set in GTUDDTYC[1:0], 00b is set in GTUDDTYC[1:0] (down-counting).
Select count clock
Select the count clock with GTCR.TPCS[2:0].
Set cycle
Set the cycle in the GTPR register.
Set initial value for counter
Set the initial value in the GTCNT counter.
In Figure 19.53, 0000 0000h is set. In Figure 19.54, the GTPR value is set.
Set hardware count start
Select a hardware source for starting count operation in GTSSR register and wait for count start by the
hardware source. In Figure 19.53 and Figure 19.54, GTSSR.SSELCA = 1.
Set hardware count stop
Select a hardware source for stopping count operation in GTPSR register and wait for count stop by
the hardware source. In Figure 19.53 and Figure 19.54, GTPSR.PSELCB = 1.
Set hardware count clear
Select a hardware source for clearing count operation in GTCSR register and wait for count clear by
the hardware source. In Figure 19.53 and Figure 19.54, GTCSR.CSELCB = 1.
Set hardware source operation
Set operation of the hardware source selected in GTSSR register, GTPSR Register or GTCSR
register and start, stop or clear counting.
In Figure 19.53 and Figure 19.54, the ELC_GPTA input and ELC_GPTB input are set.
Figure 19.55
Example for setting count clearing operation by hardware source
The GPTn_OVF/GPTn_UDF (n = 0 to 6) interrupt (overflow/underflow interrupt) is not generated when the counter is
cleared by a hardware source or by software.
Figure 19.56 shows the relationship between the counter clearing by a hardware source and the GPTn_OVF (n = 0 to 6)
interrupt.
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GTCNT counter value
19. General PWM Timer (GPT)
Counter cleared
at overflow
GTPR register
Counter cleared by
hardware source
Clear by software (by
writing 1 to corresponding
channel number bit of
GTCLR register)
0000 0000h
Time
Hardware source counter
clear signal
GPTn_OVF ( n = 0 to 6)
interrupt request
GPTn_OVF ( n = 0 to 6) interrupt not generated
Figure 19.56
19.3.8
Relationship between counter clearing by hardware source and GPTn_OVF (n = 0 to 6) interrupt
Synchronized Operation
Synchronized operation on channels such as a synchronized start, stop and clear operation can be performed.
19.3.8.1
Synchronized operation by software
The GTCNT counters can be started, stopped and cleared on multiple channels by setting the corresponding GTSTR,
GTSTP or GTCLR bits simultaneously to 1.
Count start with a phase difference is possible by setting the initial value in the GTCNT counter and setting the
corresponding GTSTR bits simultaneously to 1.
Figure 19.57 shows an example of a simultaneous start, stop and clear by software. Figure 19.58 shows an example of
phase start operation by software.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
0000 0000h
Time
GPT161.GTCNT counter
value
GPT161.GTPR register
Time
0000 0000h
GPT162.GTCNT counter value
GPT162.GTPR register
Time
0000 0000h
GPT163.GTCNT counter value
GPT163.GTPR register
Time
0000 0000h
Write 0000 000Fh in
GTSTR register
(count operation started
in channel 0/1/2/3)
Figure 19.57
Write 0000 000Fh in
GTSTP or GTCLR register
(count operation stopped or
cleared in channel 0/1/2/3)
Write 0000 000Fh in
GTSTR register
(count operation started
in channel 0/1/2/3)
Example of a simultaneous start, stop, and clear by software with the same count cycle (GTPR
register value)
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
GPT161.GTCNT counter value
GPT161.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
GPT162.GTCNT counter value
GPT162.GTPR register
cccc
bbbb
aaaa
Set initial value
Time
0000 0000h
GPT163.GTCNT counter value
GPT163.GTPR register
cccc
bbbb
aaaa
0000 0000h
Set initial value
Time
Write 0000 000Fh in GTSTR register.
(Start count operation in channel 0/1/2/3.)
Figure 19.58
Example of software phase start with the same count cycle (GTPR register value)
19.3.8.2
Synchronized operation by hardware
The GTCNT counters can be started simultaneously by the following hardware sources:
External trigger input
ELC event input.
Figure 19.59 shows an example of a simultaneous start, stop and clear operation by a hardware source. Figure 19.60
shows the setting example.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
0000 0000h
Time
GPT161.GTCNT counter value
GPT161.GTPR register
0000 0000h
Time
GPT162.GTCNT counter value
GPT162.GTPR register
0000 0000h
Time
GPT163.GTCNT counter value
GPT163.GTPR register
0000 0000h
ELC_GPTA input
Count operation of channel
0/1/2/3 started by
ELC_GPTA input.
Count operation of channel
0/1/2/3 stopped or cleared
by ELC_GPTB input.
Time
Count operation of channel
0/1/2/3 started by
ELC_GPTA input.
ELC_GPTB input
Figure 19.59
Example of a simultaneous start, stop and clear by hardware source with the same count cycle
(GTPR register value)
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19. General PWM Timer (GPT)
Set operating mode
Set the operating mode with GTCR.MD[2:0]
(In Figure 19.59, 000b (saw-wave PWM mode) is set)
Set count direction
Select the count direction (up or down) with the GTUDDTYC register
(In Figure 19.59, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting))
Select count clock
Select the count clock with GTCR.TPCS[2:0]
Set cycle
Set the cycle in the GTPR register
Set initial value for counter
Set the initial value in the GTCNT counter
(In Figure 19.59, 0000 0000h is set)
Set hardware count start
Select a hardware source for starting count operation with GTSSR register and wait for count start by
the hardware source.
(In Figure 19.59, GTSSR.SSELCA = 1)
Set hardware count stop
Select a hardware source for stopping count operation with GTPSR register and wait for count stop by
the hardware source
(In Figure 19.59, GTPSR.PSELCB = 1)
Set hardware count clear
Select a hardware source for clearing count operation with GTCSR register and wait for count clear by
the hardware source
(In Figure 19.59, GTCSR.CSELCB = 1)
Set hardware source operation
Set operation of the hardware source selected in GTSSR or GTPSR or GTCSR and start or stop or
clear counting
(In Figure 19.59, ELC_GPTA input and ELC_GPTB input are set)
Figure 19.60
19.3.9
(1)
Example for setting simultaneous start by hardware source
PWM Output Operation Examples
Synchronized PWM output
The GPT output 14 phases of linked PWM waveforms for a maximum of seven channels by multiple GPTs.
Figure 19.61 shows an example in which four channels perform synchronized operation in saw-wave PWM mode and
eight phases of PWM waveforms are output. The GTIOCA is set so that it outputs low as the initial value, high at a
GTCCRA compare match, and low at the cycle end. The GTIOCB is set so that it outputs low as the initial value, high at
a GTCCRB compare match, and low at the cycle end.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRB register
GPT320.GTCCRA register
GPT161.GTCNT counter
GPT161.GTPR register
GPT161.GTCCRB register
GPT161.GTCCRA register
GPT162.GTCNT counter
GPT162.GTPR register
GPT162.GTCCRB register
GPT162.GTCCRA register
GPT163.GTCNT counter
GPT163.GTPR register
GPT163.GTCCRB register
GPT163.GTCCRA register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2A pin output
GTIOC2B pin output
GTIOC3A pin output
GTIOC3B pin output
Figure 19.61
(2)
Example of synchronized PWM output
3-phase saw-wave complementary PWM output
Figure 19.62 shows an example in which three channels perform synchronized operation in saw-wave PWM mode and
3-phase complementary PWM waveforms are output. The GTIOCA pin is set so that it outputs low as the initial value,
high at a GTCCRA compare match, and low at the cycle end. The GTIOCB pin is set so that it outputs high as the initial
value, low at a GTCCRB compare match, and high at the cycle end.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRA register
= GPT320.GTCCRB register
GPT161.GTCNT counter
GPT161.GTPR register
GPT161.GTCCRA register
= GPT161.GTCCRB register
GPT162.GTCNT counter
GPT162.GTPR register
GPT162.GTCCRA register
= GPT162.GTCCRB register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2B pin output
GTIOC2A pin output
Figure 19.62
(3)
Example of 3-phase saw-wave complementary PWM output
3-phase saw-wave complementary PWM output with automatic dead time setting
Figure 19.63 shows an example in which three channels perform synchronized operation in saw-wave one-shot pulse
mode with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set
so that it outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the
cycle end. The GTIOCB pin is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare
match, and retains the output at the cycle end.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRD register
GPT320.GTCCRC register
GPT161.GTCNT counter
GPT161.GTPR register
GPT161.GTCCRD register
GPT161.GTCCRC register
GPT162.GTCNT counter
GPT162.GTPR register
GPT162.GTCCRD register
GPT162.GTCCRC register
GTIOC0A pin output
GTIOC0B pin output
GPT320.GTDVU
GPT320.GTDVU
GTIOC1A pin output
GTIOC1B pin output
GPT161.GTDVU
GPT161.GTDVU
GTIOC2A pin output
GTIOC2B pin output
GPT162.GTDVU
Figure 19.63
(4)
GPT162.GTDVU
Example of 3-phase saw-wave complementary PWM output with automatic dead time setting
3-phase triangle-wave complementary PWM output
Figure 19.64 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 1
and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set so that it outputs low as the initial
value, toggles the output at a GTCCRA compare match, and retains the output at the cycle end. The GTIOCB pin is set
so that it outputs high as the initial value, toggles the output at a GTCCRB compare match, and retains the output at the
cycle end.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRA register
GPT320.GTCCRB register
GPT161.GTCNT counter
GPT161.GTPR register
GPT161.GTCCRA register
GPT161.GTCCRB register
GPT162.GTCNT counter
GPT162.GTPR register
GPT162.GTCCRA register
GPT162.GTCCRB register
GTIOC0A pin output
GTIOC0B pin output
GTIOC1A pin output
GTIOC1B pin output
GTIOC2A pin output
GTIOC2B pin output
Figure 19.64
(5)
Example of 3-phase triangle-wave complementary PWM output
3-phase triangle-wave complementary PWM output with automatic dead time setting
Figure 19.65 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 1
with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA pin is set so
that it outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the
cycle end. The GTIOCB pin is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare
match, and retains the output at the cycle end.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRA register
GPT161.GTCNT counter
GPT161.GTPR register
GPT161.GTCCRA register
GPT162.GTCNT counter
GPT162.GTPR register
GPT162.GTCCRA register
GPT320.GTDVU
GPT320.GTDVU
GTIOC0A pin output
GTIOC0B pin output
GPT161.GTDVU
GTIOC1A pin output
GPT161.GTDVU
GTIOC1B pin output
GTIOC2A pin output
GPT162.GTDVU
GPT162.GTDVU
GTIOC2B pin output
Figure 19.65
(6)
Example of 3-phase triangle-wave complementary PWM output with automatic dead time setting
3-phase asymmetric triangle-wave complementary PWM output with automatic dead time
setting
Figure 19.66 shows an example in which three channels perform synchronized operation in triangle-wave PWM mode 3
with automatic dead time setting and 3-phase complementary PWM waveforms are output. The GTIOCA is set so that it
outputs low as the initial value, toggles the output at a GTCCRA compare match, and retains the output at the cycle end.
The GTIOCB is set so that it outputs high as the initial value, toggles the output at a GTCCRB compare match, and
retains the output at the cycle end.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter
GPT320.GTPR register
GPT320.GTCCRC register
GPT320.GTCCRD register
GPT161.GTCNT counter
GPT161.GTPR register
GPT161.GTCCRC register
GPT161.GTCCRD register
GPT162.GTCNT counter
GPT162.GTPR register
GPT162.GTCCRC register
GPT162.GTCCRD register
GPT320.GTDVU
GPT320.GTDVU
GTIOC0A pin output
GTIOC0B pin output
GPT161.GTDVU
GTIOC1A pin output
GPT161.GTDVU
GPT162.GTDVU
GTIOC1B pin output
GTIOC2A pin output
GPT162.GTDVU
GTIOC2B pin output
Figure 19.66
19.3.10
Example of 3-phase asymmetric triangle-wave complementary PWM output with automatic dead
time setting
Phase Counting Function
The phase difference between the GTIOCA and GTIOCB pin input is detected and the corresponding GTCNT counts up
or counts down. The detectable phase difference is available in any combination with the relationship between the edge
and the level of GTIOCA pin and GTIOCB pin input being set in the GTUPSR and GTDNSR registers. For details on
count operation, see section 19.3.1.1, Counter operation.
Figure 19.67 to Figure 19.76 show phase counting modes 1 to 5. Table 19.7 to Table 19.16 show conditions of upcounting or down-counting and list settings for the GTUPSR and GTDNSR registers.
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19. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 19.67
Table 19.7
Example of phase counting mode 1
Conditions of up-counting/down-counting in phase counting mode 1
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Up-counting
GTUPSR = 00006900h
GTDNSR = 00009600h
Low
Low
High
High
Down-counting
Low
High
Low
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 19.68
Example of phase counting mode 2 (A)
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Table 19.8
19. General PWM Timer (GPT)
Conditions of up-counting/down-counting in phase counting mode 2 (A)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 00000800h
GTDNSR = 00000400h
Low
Low
High
High
Up-counting
Don’t care
Low
High
Low
Down-counting
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Down-counting
Up-counting
Time
Figure 19.69
Table 19.9
Example of phase counting mode 2 (B)
Conditions of up-counting/down-counting in phase counting mode 2 (B)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 00000200h
GTDNSR = 00000100h
Low
Low
Down-counting
High
Don’t care
High
Low
High
Up-counting
Low
Don’t care
: Rising edge
: Falling edge
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19. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 19.70
Table 19.10
Example of phase counting mode 2 (C)
Conditions of up-counting/down-counting in phase counting mode 2 (C)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 00000A00h
GTDNSR = 00000500h
Low
Low
High
High
Down-counting
Up-counting
Don’t care
Low
High
Up-counting
Low
Down-counting
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 19.71
Example of phase counting mode 3 (A)
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Table 19.11
19. General PWM Timer (GPT)
Conditions of up-counting/down-counting in phase counting mode 3 (A)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 00000800h
GTDNSR = 00008000h
Low
Low
High
Up-counting
High
Down-counting
Low
Don’t care
High
Low
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Down-counting
Up-counting
Time
Figure 19.72
Table 19.12
Example of phase counting mode 3 (B)
Conditions of up-counting/down-counting in phase counting mode 3 (B)
GTIOCA pin input
Operation
Register setting
High
GTIOCB pin input
Down-counting
Low
Don’t care
GTUPSR = 00000200h
GTDNSR = 00002000h
Low
High
High
Low
High
Up-counting
Low
Don’t care
: Rising edge
: Falling edge
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19. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT counter
Up-counting
Down-counting
Time
Figure 19.73
Table 19.13
Example of phase counting mode 3 (C)
Conditions of up-counting/down-counting in phase counting mode 3 (C)
GTIOCA pin input
GTIOCB pin input
Operation
Register setting
High
Down-counting
Low
Don’t care
GTUPSR = 00000A00h
GTDNSR = 0000A000h
Low
High
Up-counting
High
Down-counting
Low
Don’t care
High
Up-counting
Low
Don’t care
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT Counter
Up-counting
Down-counting
Time
Figure 19.74
Example of phase counting mode 4
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Table 19.14
19. General PWM Timer (GPT)
Conditions of up-counting/down-counting in phase counting mode 4
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Up-counting
GTUPSR = 00006000h
GTDNSR = 00009000h
Low
Low
Don’t care
High
High
Down-counting
Low
High
Don’t care
Low
: Rising edge
: Falling edge
GTIOCA pin input
GTIOCB pin input
GTCNT
Up-counting
Time
Figure 19.75
Table 19.15
Example of phase counting mode 5 (A)
Conditions of up-counting/down-counting in phase counting mode 5 (A)
GTIOCA pin input
GTIOCB pin input
High
Operation
Register setting
Don’t care
GTUPSR = 00000C00h
GTDNSR = 00000000h
Low
Low
High
High
Up-counting
Don’t care
Low
High
Low
Up-counting
: Rising edge
: Falling edge
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19. General PWM Timer (GPT)
GTIOCA pin input
GTIOCB pin input
GTCNT
Up-counting
Time
Figure 19.76
Table 19.16
Example of phase counting mode 5 (B)
Conditions of up-counting/down-counting in phase counting mode 5 (B)
GTIOCA pin input
GTIOCB pin input
Operation
Register setting
High
Don’t care
Low
Up-counting
GTUPSR = 0000C000h
GTDNSR = 00000000h
Low
Don’t care
High
High
Up-counting
Low
Don’t care
High
Low
: Rising edge
: Falling edge
19.3.11
Output Phase Switching (GPT_OPS)
GPT_OPS provides a function for easy control of brushless DC motor operation using the Output Phase Switching
Control Register (OPSCR).
GPT_OPS outputs a PWM signal to be used for chopper control or level signal for each phase (U-positive phase/negative
phase, V-positive phase/negative phase, W-positive phase/negative phase) of the 6-phase motor control. This function
uses a soft setting value (OPSCR.UF, VF, WF) set by software or external signals detected by the Hall element, a PWM
waveform of GPT161.GTIOCA.
Figure 19.77 shows the GPT_OPS control flow conceptual diagram.
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19. General PWM Timer (GPT)
(1)
OPSCR.
UF/VF/WF
From hall element
GTIU
GTIV
GTIW
Synchronize
noise filter
Input select
Soft setting (UF/VF/WF)
(4)
PCLKD
sample
Input phase
PWM edge
sample
Hall sensor
input edge sample
(every PCLKD)
GPT_UVWEDGE
(Input U-phase)
(Input V-phase)
(Input W-phase)
PCLKD
OPS internal node name
(gtu_sync)
(gtv_sync)
(gtw_sync)
External input (U/V/W)
Input selection
selector
Input phase de-code
6-phase enable gen
(2)
OPS internal node name
(gtuup_en, gtulo_en)
(gtvup_en, gtvlo_en)
(gtwup_en, gtwlo_en)
(3)
Output select control
OPS internal node name
(gtuup_ren, gtulo_ren)
(gtvup_ren, gtvlo_ren)
(gtwup_ren, gtwlo_ren)
From GPT161.GTIOCA
PWM
To brushless DC motor
GTOUUP,
GTOULO,
GTOVUP,
GTOVLO,
GTOWUP,
GTOWLO
GPT clock
(PCLKD)
Figure 19.77
GPT_OPS control flow conceptual diagram
Figure 19.78 shows a 6-phase level signals output example of a GPT_OPS operation.
The GPT_UVWEDGE signal in Figure 19.78 is the hall sensor input edge to ELC output.
Input sel after “U-phase”
GTIU
Input sel after “V-phase”
GTIV
Input sel after “W-phase”
GTIW
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Figure 19.78
Register settings: OPSCR.ALIGN = 0, OPSCR.EN = 1, OPSCR.P = 0, OPSCR.N = 0, OPSCR.INV = 0
6-phase level output operation example
Figure 19.79 shows a 6-phase PWM output example of a GPT_OPS operation with chopper control.
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19. General PWM Timer (GPT)
GPT161 PWM
PWM
Input sel after “U-phase”
GTIU
Input sel after “V-phase”
GTIV
Input sel after “W-phase”
GTIW
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Figure 19.79
Register settings: OPSCR.ALIGN = 1, OPSCR.EN = 1, OPSCR.P = 1, OPSCR.N = 1, OPSCR.INV = 0
6-phase PWM output operation example with chopper control
Figure 19.80 shows an example of output disable control (6-phase PWM output operation).
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19. General PWM Timer (GPT)
GPT161 PWM
PWM
"U-phase" after input
selection
GTIU
"V-phase" after input
selection
GTIV
"W-phase" after input
selection
GTIW
Output enable
OPSCR.EN
Output Disabled Source
Select
OPSCR.GRP
Auto clear
Setting by software
00b (Group A output disable request)
Group output disable
OPSCR.GODF
Clear by software
Connected between
POEG group A and OPS
Output “U-phase (Up)”
GTOUUP
Output “U-phase (Lo)”
GTOULO
Output “V-phase (Up)”
GTOVUP
Output “V-phase (Lo)”
GTOVLO
Output “W-phase (Up)”
GTOWUP
Output “W-phase (Lo)”
GTOWLO
To ELC
GPT_UVWEDGE
1 pulse @ PCLKD
Note:
Register settings: OPSCR.P = 1, OPSCR.N = 1, OPSCR.INV = 0
Figure 19.80
Group output disable control operation example
19.3.11.1
Input selection and synchronization of external input signal
In the GPT_OPS control flow conceptual diagram shown in Figure 19.77, (1) is a selection of input phase from the
software settings and external input by the OPSCR.FB bit.
When OPSCR.FB bit is 0, select the external input. Enable the input signal after synchronization with the GPT clock
(PCLKD). After carrying out noise filtering (optional), set the external input to the input phase of PWM (PWM of
GPT161.GTIOCA) using falling edge sampling with OPSCR.ALIGN bit set to 1.
When OPSCR.FB bit is 1, select the soft setting (OPSCR.UF, VF, WF) with the value of the input phase of PWM (PWM
of GPT161.GTIOCA) using falling edge sampling with OPSCR.ALIGN bit set to 1.
When OPSCR.ALIGN bit is 0, GPT_OPS operates with the input phase of PCLKD synchronization with either
OPSCR.FB bit set to 0 or OPSCR.FB bit set to 1. However, there are cases where the PWM pulse width of the output U/
V/W phases (PWM output mode) of switch timing (just before/just after) is shortened.
Table 19.17 shows the input selection process and setting of the associated OPSCR bits.
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Table 19.17
19. General PWM Timer (GPT)
Input selection processing method
Register OPSCR
Selection of input phase sampling method
(U/V/W-phase)
Synchronization input/output selection
process (GPT_OPS internal node name)
1
External Input at PWM Falling Edge Sampling
(PCLKD Sync + Falling Edge Sample)
0
External Input at PCLKD Synchronization
Output (PCLKD Sync + Through mode)
Input Phase
Input U-Phase (gtu_sync)
Input V-Phase (gtv_sync)
Input W-Phase (gtw_sync)
1
Software Settings at PWM Falling Edge
Sampling (OPSCR.UF, VF, WF of Falling Edge
Sample)
0
Software Setting Value Selection
(= OPSCR.UF/VF/WF value) (= PCLKD
Synchronization)
FB bit
ALIGN bit
0
1
19.3.11.2
Input sampling
The OPSCR.U, V, W register indicates the PCLKD, and the sampling results of the input selected by the OPSCR.FB bit.
When OPSCR.FB bit is 0 and after synchronization with the GPT clock (PCLKD) and noise filtering (optional),
OPSCR.U, V, W register indicates the sampling results of the external input.
When OPSCR.FB bit is 1, OPSCR.U, V, W register is the value (OPSCR.UF, VF, WF) of the soft setting.
19.3.11.3
Input phase decode
In the GPT_OPS control flow conceptual diagram shown in Figure 19.77, (2) enables the 6-phase signals by decoding
the input phase selected by the OPSCR.FB bit. The 6-phase enable signal is used for internal processing of GPT_OPS.
Table 19.18 shows the decode table of input phase.
Table 19.18
Decode table of input phase
Input phase (U/V/W)
(GPT_OPS internal node name)
6-phase enable {U/V/W (Up/Lo)} by decoding input phase
(GPT_OPS internal node name)
Input UPhase
Input VPhase
Input WPhase
U-phase
(Up)
U-phase
(Lo)
V-phase
(Up)
V-phase
(Lo)
W-phase
(Up)
W-phase
(Lo)
(gtu_sync)
(gtv_sync)
(gtw_sync)
(gtuup_en)
(gtulo_en)
(gtvup_en)
(gtvlo_en)
(gtwup_en)
(gtwlo_en)
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
19.3.11.4
Output selection control
In the GPT_OPS control flow conceptual diagram in Figure 19.77, (3) presents the selection of the output waveform by
setting the OPSCR register bit.
For output selection, the following bits are relevant:
The OPSCR.EN bit controls whether to output the 6-phase output, or to stop
The OPSCR.P bit and OPSCR.N bit can choose from the level signal or PWM signal (chopper output) for the output
phase
The polarity of the output phase can be set to a positive logic or negative logic by the OPSCR. INV bit.
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19. General PWM Timer (GPT)
Table 19.19 and Table 19.20 show the output selection control method using the OPSCR register bit.
Table 19.19
Output selection control method (positive phase)
Enable-phase output
control
Positive-phase output
(P) control
Invert-phase output
control
Output port name (positive phase = up)
(output selection internal node allocation)
Register OPSCR.EN
Register OPSCR.P
Register OPSCR.INV
GTOUUP
GTOVUP
GTOWUP
0
x
x
0
Output Stop
(External pin: Hi-Z)
GPT_OPS → 0 output
1
0
0
Level signal
(gtuup_en)
(gtvup_en)
(gtwup_en)
Level Output Mode
(Positive phase)
(Positive logic)
1
0
1
Level signal
( ~gtuup_en)
( ~gtvup_en)
( ~gtwup_en)
Level Output Mode
(Positive phase)
(Negative logic)
1
1
0
PWM signal
(PWM & gtuup_en)
(PWM & gtvup_en)
(PWM & gtwup_en)
PWM Output Mode
(Positive phase)
(Positive logic)
1
1
1
PWM signal
(~(PWM & gtuup_en))
(~(PWM & gtvup_en))
(~(PWM & gtwup_en))
PWM Output Mode
(Positive phase)
(Negative logic)
Table 19.20
Mode
Output selection control method (negative phase)
Enable-phase output
control
Negative-phase output
(N) control
Invert-phase output
control
Output port name (negative phase = Lo)
(output selection internal node allocation)
Register OPSCR.EN
Register OPSCR.N
Register OPSCR.INV
GTOULO
GTOVLO
GTOWLO
0
x
x
0
Output Stop
(External pin: Hi-Z)
GPT_OPS → 0 output
1
0
0
Level signal
(gtulo_en)
(gtvlo_en)
(gtwlo_en)
Level Output Mode
(Negative phase)
(Positive logic)
1
0
1
Level signal
( ~gtulo_en)
( ~gtvlo_en)
( ~gtwlo_en)
Level Output Mode
(Negative phase)
(Negative logic)
1
1
0
PWM signal
(PWM & gtulo_en)
(PWM & gtvlo_en)
(PWM & gtwlo_en)
PWM Output Mode
(Negative phase)
(Positive logic)
1
1
1
PWM signal
(~(PWM & gtulo_en))
(~(PWM & gtvlo_en))
(~(PWM & gtwlo_en))
PWM Output Mode
(Negative phase)
(Negative logic)
19.3.11.5
Mode
Output selection control (group output disable function)
When OPSCR.GODF is 1 and the signal value selected by the OPSCR.GRP bit is high (output disable request), the
GPT_OPS output pins change to Hi-Z asynchronously and the OPSCR.EN bit is cleared to 0 by the output-disable
request signal synchronized with PCLKD.
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For the return, after clearing the output-disable request by software, set the OPSCR.EN to 1.
The timing of the OPSCR.EN bit cleared to 0 is 3 PCLKD cycles after generating the output-disable request. To perform
output disable control reliably, allow at least 4 PCLKD cycles after generating the output-disable request (by clearing the
output-disable request flag in POEG) until the output-disable request is terminated.
For an example of the operation of group output-disable control, see Figure 19.80.
19.3.11.6
ELC output
In the GPT_OPS control flow conceptual diagram shown in Figure 19.77, (5) outputs the hall sensor input signal edge to
the event link controller.
The hall sensor input edge signal is the logical OR of the rising and falling edge signals of each U-phase/V-phase/Wphase input sampled at PCLKD. That is, if the high period of each of the U-phase/V-phase/W-phase input is short in
duration, the hall sensor edge input signal is not output at that time.
When the OPSCR.FB bit is 0, the hall sensor input edge signal is the logical OR of the edge signals of the external input
phase sampled at PCLKD.
When OPSCR.FB bit is 1, the hall sensor input edge signal is the logical OR of the edge of the soft setting (OPSCR.UF,
VF, WF) sampled at PCLKD.
See Figure 19.78 to Figure 19.80 for examples of the output signal to the ELC.
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19.3.11.7
19. General PWM Timer (GPT)
GPT_OPS start operation setting flow
GPT161 operation mode setting
GPT161.GTIOCA set the PWM output operation mode of the saw-wave or triangle-wave.
For details, see section 19.3.3, PWM Output Operating Mode.
Counting of GPT161
Start the count operation of GPT161, and outputs a PWM waveform.
GPT_OPS input data set (only software setting is selected)
Set of software setting to OPSCR.UF, VF, and WF bits.
Noise filter settings of GPT_OPS external input (only external input is selected)
When using a noise filter, set the sampling clock of the noise filter by OPSCR.NFCS bit.
Then the noise filter is enabled if OPSCR.NFEN bit = 1.
GPT_OPS input phase selection setting/input phase alignment setting
Select the input phase from the external input or software setting by OPSCR.FB bit.
Select the alignment of the input phase by OPSCR.ALIGN bit.
Setting the GPT_OPS output phase
Set the level output/PWM output of the positive/negative phase output by OPSCR.P/OPSCR.N bit.
Set the positive logic/negative logic of the output phase by OPSCR.INV bit.
GPT_OPS setting the group output disable function
Set the selection of output disable source by OPSCR.GRP bit.
Perform the setting of on/off of the group output disable function by OPSCR.GODF bit.
GPT_OPS Working
Setting the OPSCR.EN bit = 1 outputs the 6-phase output to drive the brushless DC motor from the
GPT_OPS.
Figure 19.81
19.4
19.4.1
Example for setting of GPT_OPS start operation
Interrupt Sources
Interrupt Sources
The GPT provides the following interrupt sources:
GTCCR input capture/compare match
GTCNT counter overflow (GTPR compare match)/underflow.
Each interrupt source has its own status flag. When an interrupt source signal is generated, the corresponding status flag
in GTST is set to 1. The corresponding status flag in GTST can be cleared by writing 0. If flag set and flag clear occur at
the same time, flag clear takes priority over flag set. Those flags are automatically updated by internal state.
Table 19.21 lists the GPT interrupt sources.
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Table 19.21
19. General PWM Timer (GPT)
Interrupt sources
Channel
Name
Interrupt Source
0
GPT0_CCMPA
GPT0_CCMPB
1
2
3
4
5
6
Interrupt Flag
DTC Activation
GPT320.GTCCRA input capture/compare match
TCFA
Possible
GPT320.GTCCRB input capture/compare match
TCFB
Possible
GPT0_CMPC
GPT320.GTCCRC compare match
TCFC
Possible
GPT0_CMPD
GPT320.GTCCRD compare match
TCFD
Possible
GPT0_OVF
GPT320.GTCNT overflow (GPT320.GTPR compare match)
TCFPO
Possible
GPT0_UDF
GPT320.GTCNT underflow
TCFPU
Possible
GPT1_CCMPA
GPT161.GTCCRA input capture/compare match
TCFA
Possible
GPT1_CCMPB
GPT161.GTCCRB input capture/compare match
TCFB
Possible
GPT1_CMPC
GPT161.GTCCRC compare match
TCFC
Possible
GPT1_CMPD
GPT161.GTCCRD compare match
TCFD
Possible
GPT1_OVF
GPT161.GTCNT overflow (GPT161.GTPR compare match)
TCFPO
Possible
GPT1_UDF
GPT161.GTCNT underflow
TCFPU
Possible
GPT2_CCMPA
GPT162.GTCCRA input capture/compare match
TCFA
Possible
GPT2_CCMPB
GPT162.GTCCRB input capture/compare match
TCFB
Possible
GPT2_CMPC
GPT162.GTCCRC compare match
TCFC
Possible
GPT2_CMPD
GPT162.GTCCRD compare match
TCFD
Possible
GPT2_OVF
GPT162.GTCNT overflow (GPT162.GTPR compare match)
TCFPO
Possible
GPT2_UDF
GPT162.GTCNT underflow
TCFPU
Possible
GPT3_CCMPA
GPT163.GTCCRA input capture/compare match
TCFA
Possible
GPT3_CCMPB
GPT163.GTCCRB input capture/compare match
TCFB
Possible
GPT3_CMPC
GPT163.GTCCRC compare match
TCFC
Possible
GPT3_CMPD
GPT163.GTCCRD compare match
TCFD
Possible
GPT3_OVF
GPT163.GTCNT overflow (GPT163.GTPR compare match)
TCFPO
Possible
GPT3_UDF
GPT163.GTCNT underflow
TCFPU
Possible
GPT4_CCMPA
GPT164.GTCCRA input capture/compare match
TCFA
Possible
GPT4_CCMPB
GPT164.GTCCRB input capture/compare match
TCFB
Possible
GPT4_CMPC
GPT164.GTCCRC compare match
TCFC
Possible
GPT4_CMPD
GPT164.GTCCRD compare match
TCFD
Possible
GPT4_OVF
GPT164.GTCNT overflow (GPT164.GTPR compare match)
TCFPO
Possible
GPT4_UDF
GPT164.GTCNT underflow
TCFPU
Possible
GPT5_CCMPA
GPT165.GTCCRA input capture/compare match
TCFA
Possible
GPT5_CCMPB
GPT165.GTCCRB input capture/compare match
TCFB
Possible
GPT5_CMPC
GPT165.GTCCRC compare match
TCFC
Possible
GPT5_CMPD
GPT165.GTCCRD compare match
TCFD
Possible
GPT5_OVF
GPT165.GTCNT overflow (GPT165.GTPR compare match)
TCFPO
Possible
GPT5_UDF
GPT165.GTCNT underflow
TCFPU
Possible
GPT6_CCMPA
GPT166.GTCCRA input capture/compare match
TCFA
Possible
GPT6_CCMPB
GPT166.GTCCRB input capture/compare match
TCFB
Possible
GPT6_CMPC
GPT166.GTCCRC compare match
TCFC
Possible
GPT6_CMPD
GPT166.GTCCRD compare match
TCFD
Possible
GPT6_OVF
GPT166.GTCNT overflow (GPT166.GTPR compare match)
TCFPO
Possible
GPT6_UDF
GPT166.GTCNT underflow
TCFPU
Possible
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(1)
19. General PWM Timer (GPT)
GPTn_CCMPA interrupt (n = 0 to 6)
An interrupt request is generated under the following conditions:
When the GTCCRA register functions as a compare match register, the GTCNT counter value matches with the
GTCCRA register
When the GTCCRA register functions as an input capture register, the input-capture signal caused transfer of the
GTCNT counter value to the GTCCRA register.
(2)
GPTn_CCMPB interrupt (n = 0 to 6)
An interrupt request is generated under the following conditions:
When the GTCCRB register functions as a compare match register, the GTCNT counter value matches with the
GTCCRB register
When the GTCCRB register functions as an input capture register, the input-capture signal caused transfer of the
GTCNT counter value to the GTCCRB register.
(3)
GPTn_CMPC interrupt (n = 0 to 6)
An interrupt request is generated under the following condition:
When the GTCCRC register functions as a compare match register, the GTCNT counter value matches with the
GTCCRC register.
A compare match is not performed and therefore, an interrupt is not requested in the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 01b, 10b, 11b (buffer operation with the GTCCRC register).
(4)
GPTn_CMPD interrupt (n = 0 to 6)
An interrupt request is generated under the following condition:
When the GTCCRD register functions as a compare match register, the GTCNT counter value matches with the
GTCCRD register.
A compare match is not performed and therefore, an interrupt is not requested in the following conditions:
GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)
GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)
GTBER.CCRA[1:0] = 10b, 11b (buffer operation with the GTCCRD register).
(5)
GPTn_OVF interrupt (n = 0 to 6)
An interrupt request is generated in the following conditions:
In saw-wave mode, interrupt requests are enabled at overflows (when the GTCNT counter value changes from
GTPR to 0 during up-counting)
In triangle-wave mode, interrupt requests are enabled at crests (the GTCNT changes from GTPR to GTPR-1)
In counting by hardware sources, an overflow (GTCNT changes from GTPR to 0 in up count) has occurred.
(6)
GPTn_UDF interrupt (n = 0 to 6)
An interrupt request is generated in the following conditions.
In saw-wave mode, interrupt requests are enabled at underflows (when the GTCNT counter value changes from 0 to
GTPR during down-counting)
In triangle-wave mode, interrupt requests are enabled at troughs (the GTCNT changes from 0 to 1)
In counting by hardware sources, underflow (GTCNT changes from 0 to GTPR in down count) has occurred.
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Table 19.22
19. General PWM Timer (GPT)
Interrupt signals and interrupt status flags
Interrupt signal
Interrupt status flag
GPTn_UDF
GTST[7] (TCFPU)
GPTn_OVF
GTST[6] (TCFPO)
GPTn_CMPD
GTST[3] (TCFD)
GPTn_CMPC
GTST[2] (TCFC)
GPTn_CCMPB
GTST[1] (TCFB)
GPTn_CCMPA
GTST[0] (TCFA)
n = 0 to 6
19.4.2
DTC Activation
The DTC can be activated by the interrupt in each channel. For details, see section 12, Interrupt Controller Unit (ICU),
and section 14, Data Transfer Controller (DTC).
19.5
19.5.1
Operations Linked by ELC
Event Signal Output to ELC
The GPT can perform operation linked with another module set in advance when its interrupt request signal is used as an
event signal by the Event Link Controller (ELC).
The GPT has the following ELC event signals:
Generating of compare match A interrupt (GPTn_CCMPA)
Generating of compare match B interrupt (GPTn_CCMPB)
Generating of compare match C interrupt (GPTn_CMPC)
Generating of compare match D interrupt (GPTn_CMPD)
Generating of overflow interrupt (GPTn_OVF)
Generating of underflow interrupt (GPTn_UDF).
Note:
19.5.2
n = 0 to 6
Event Signal Inputs from ELC
The GPT can perform the following operations in response to a maximum of four events from the ELC.
Start counting, stop counting, clear counting
Up-counting, down counting
Input capture.
See section 19.3, Operation for detail on hardware resources.
19.6
Noise Filter Function
Each pin for use in input capture and hall sensor input to the GPT is equipped with a noise filter. The noise filter samples
input signals at the sampling clock and removes the pulses whose length is less than three sampling cycles.
The noise filter functionality includes enabling and disabling the noise filter for each pin and setting of the sampling
clock for each channel.
Figure 19.82 shows the timing of noise filtering.
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19. General PWM Timer (GPT)
Sampling clock
Noise filter enable/
disable register
Input capture input pin or
external trigger input pin
Eliminated
pulse
Matching
three times
Signal conveyed
internally
Noise filter disabled
Figure 19.82
Noise filter enabled
Timing of noise filtering
If noise filtering is enabled, the input capture operation or external trigger operation is performed on the edges of the
noise filtered signal after a delay of a minimum sampling interval × 2 + PCLKD. This is due to the noise filtering for the
input capture input or external trigger operation.
19.7
19.7.1
Protection Function
Write-Protection for Registers
To prevent registers from being accidentally modified, registers can be write-protected in channel units by setting
GTWP.WP. Write-protection can be set for the following registers:
GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTICASR, GTIBCSR, GTCR, GTUDDTYC, GTIOR, GTINTAD,
GTST, GTBER, GTCNT, GTCCRA, GTCCRB, GTCCRC, GTCCRD, GTCCRE, GTCCRF, GTPR, GTPBR, GTDTCR,
GTDVU.
19.7.2
Disabling of Buffer Operation
If the timing of the buffer register write is delayed relative to timing for the buffer transfer, buffer operation can be
suspended with the GTBER.BD setting. Specifically, buffer transfer can be temporarily disabled, even though a buffer
transfer condition is generated during buffer register write, by setting the corresponding GTBER.BD bit to 1 (buffer
operation disabled) before buffer register write and clearing the bit to 0 (buffer operation enabled) after completion of
writing to all the buffer registers.
Figure 19.83 shows an example of operation for disabling buffer operation.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
0000 0000h
Time
Register write timing is too late
for buffer transfer timing
Register write
GPT320.GTCCRF register
bbbb
cccc
Buffer transfer at trough
GPT320.GTCCRE register
aaaa
Buffer transfer at crest
bbbb
eeee
Buffer transfer at crest
cccc
Buffer transfer at trough
eeee
Buffer transfer at crest
aaaa
GPT320.GTCCRB register
dddd
Register write
Buffer transfer at crest
bbbb
cccc
GTBER.BD[0]
Set to 1 before
GPT320.GTCCRF
register is written
Set to 1 before
GPT320.GTCCRF
register is written
Cleared to 0 after
GPT320.GTCCRF
register is written
Buffer transfer not performed
when GTBDR.BD0[0] bit = 1
Figure 19.83
19.7.3
Cleared to 0 after
GPT320.GTCCRF
register is written
Cleared to 0 after
GPT320.GTCCRF
register is written
Set to 1 before
GPT320.GTCCRF
register is written
Set to 1 before
GPT320.GTCCRF
register is written
Cleared to 0 after
GPT320.GTCCRF
register is written
Example of operation for disabling buffer operation with triangle waves, double buffer operation,
and buffer transfer at both troughs and crests
GTIOC Pin Output Negate Control
For protection from system failure, the output disable control that changes the GTIOC pin output value forcibly is
provided for GTIOC pin output by the request of output disable from POEG. When the GTIOCA pin output value is the
same as the GTIOCB pin output value, output protection is required. GPT detects such a case and generates output
disable requests to POEG according to the setting of output disable request permission bits, such as
GTINTAD.GRPABH, GTINTAD.GRPABL. After the POEG receives output disable requests from each channel and
calculates external input using an OR operation, the POEG generates output disable requests to GPT.
One output disable signal (representing the common output disable request signal of the GTIOCA pin and the GTIOCB
pin) out of two output disable requests generated by the POEG is selected by setting GTINTAD.GRP[1:0]. The status of
the selected disable output request is monitored by reading the GTST.ODF bit. The output level during output disable is
set in accordance with GTIOR.OADF[1:0] bits for GTIOCA pin and GTIOR.OBDF[1:0] bits for GTIOCB pin.
The change to the output disable state is performed asynchronously by generating the output disable request from the
POEG. The release of the output disable state is performed at end of cycle by terminating the output disable request. The
timing of release of the output disable state is a minimum of 3 PCLKD cycles after terminating the output disable
request. In order to perform output disable control reliably, allow at least 4 PCLKD cycles after generating the output
disable request (by clearing the output disable request flag in POEG) until the output disable request is terminated.
When event count is performed or when the output disable state should be released immediately without waiting for end
of cycle, GTIOR.OADF[1:0] should be set to 00b (for GTIOCA pin) or GTIOR.OBDF[1:0] should be set to 00b (for
GTIOCB pin).
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19. General PWM Timer (GPT)
Figure 19.84 shows an example of the GTIOC pin output disable control operation.
GPT320.GTCNT counter value
GPT320.GTPR register
cccc
bbbb
aaaa
0000 0000h
Time
GPT320.GTCCRC register
bbbb
aaaa
Register write
cccc
Buffer transfer
at overflow
GPT320.GTCCRA register
Register write
Register write
Register write
bbbb
Buffer transfer
at overflow
Buffer transfer
at overflow
cccc
Negate control source
GTIOC0A pin output
GTIOC pin output low forcibly when the output
disable source is requested.
Figure 19.84
19.8
19.8.1
Example of GTIOC pin output disable control operation in saw-wave up-counting, buffer
operation, active level 1, high output at GTCCRA compare match, low output at cycle end, and
low output at output disable
Initialization Method of Output Pins
Pin Settings after Reset
The GPT registers are initialized at a reset. Start counting after selecting the port pin function with the PmnPFS register,
setting GTIOR.OAE and GTIOR.OBE bits, and outputting the GPT function to external pins.
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19. General PWM Timer (GPT)
GPT320.GTCNT counter value
GPT320.GTPR register
GPT320.GTCCRA register
GPT320.GTCCRB register
0000 0000h
Time
Hi-Z
GTIOC0A pin output
Hi-Z
GTIOC0B pin output
Reset is released. GTIOR.OAE and OBE bits Count operation starts.
are set.
Reset
GPT initialization settings
Count operation
[Setting examples]
GTIOR.GTIOA[4:0] bits: Initial output of low, output retained at cycle end, output toggled at compare match
GTIOR.GTIOB[4:0] bits: Initial output of high, output retained at cycle end, output toggled at compare match
Figure 19.85
19.8.2
Example of pin settings after reset
Pin Initialization Due to Error during Operation
If an error occurs during GPT operation, the following four types of pin processing can be performed before pin
initialization:
Set OAHLD and OBHLD bits in GTIOR to 1 and retain the outputs at count stop
Set OAHLD and OBHLD bits in GTIOR to 0, specify arbitrary output values at OADFLT and OBDFLT in GTIOR,
and output the arbitrary values at count stop
Set the pin to output an arbitrary value as a general output port by setting the PDR, PODR, and PmnPFS registers of
the I/O port in advance. Set the OAE and OBE bits in GTIOR to 0 and the control bit in PmnPFS.PMR that
corresponds to the pin to 0 to allow arbitrary values to be output from the pin set as a general output port when an
error occurs.
Drive the output to a high impedance state using the POEG function.
After the automatic dead time setting is made, clear the GTDTCR.TDE bit to 0 after counting stops. When counting
stops, only the values of registers that are changed by a GPT external source change. If counting is resumed, operation
continues from where it stopped. If counting is stopped, the registers must be initialized before counting starts.
19.9
Usage Notes
19.9.1
Settings for the Module-Stop State
The Module Stop Control register can enable or disable GPT operation. The GPT is stopped after a reset. The registers
become accessible on release from the module-stop state. For details, see section 10, Low Power Modes.
19.9.2
(1)
Settings of GTCCRn during Compare Match Operation (n = A to F)
When automatic dead time setting is made in triangle-wave PWM mode
The GTCCRA register must satisfy both of the following conditions:
GTDVU < GTCCRA
0 < GTCCRA < GTPR.
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(2)
19. General PWM Timer (GPT)
When automatic dead time setting is not made in triangle-wave PWM mode
The GTCCRA register must be set within the range of 0 < GTCCRA < GTPR. If GTCCRA = 0 or GTCCRA = GTPR is
set, a compare match occurs within the cycle only when GTCCRA is 0 or GTCCRA = GTPR is satisfied. When
GTCCRA > GTPR, no compare match occurs.
Similarly, GTCCRB must be set within the range of 0 < GTCCRB < GTPR. If GTCCRB = 0 or GTCCRB = GTPR is set,
a compare match occurs within the cycle only when GTCCRB is 0 or GTCCRB = GTPR is satisfied. When GTCCRB >
GTPR, no compare match occurs.
(3)
When automatic dead time setting is made in saw-wave one-shot pulse mode
The GTCCRC and GTCCRD registers must be set to satisfy the following restrictions. If the restrictions are not satisfied,
the correct output waveforms with secured dead time may not be obtained.
In up-counting: GTCCRC < GTCCRD, GTCCRC > GTDVU, GTCCRD < GTPR - GTDVU
In down-counting: GTCCRC > GTCCRD, GTCCRC < GTPR – GTDVU, GTCCRD > GTDVU.
(4)
When automatic dead time setting is not made in saw-wave one-shot pulse mode
The GTCCRC and GTCCRD registers must be set to satisfy the following restrictions. If the restrictions are not satisfied,
two compare matches do not occur and pulse output cannot be performed.
In up-counting: 0 < GTCCRC < GTCCRD < GTPR
In down-counting: GTPR > GTCCRC > GTCCRD > 0.
Similarly, GTCCRE and GTCCRF must be set to satisfy the following restrictions. If the restrictions are not satisfied,
two compare matches do not occur and pulse output cannot be performed.
In up-counting: 0 < GTCCRE < GTCCRF < GTPR
In down-counting: GTPR > GTCCRE > GTCCRF > 0.
(5)
In saw-wave PWM mode
The GTCCRA register should be set with the range of 0 < GTCCRA < GTPR. If GTCCRA = 0 or GTCCRA = GTPR is
set, a compare match occurs within the cycle only when GTCCRA = 0 or GTCCRA = GTPR is satisfied. If GTCCRA >
GTPR is set, no compare match occurs.
Similarly, GTCCRB should be set with the range of 0 < GTCCRB < GTPR. If GTCCRB = 0 or GTCCRB = GTPR is set,
a compare match occurs within the cycle only when GTCCRB = 0 or GTCCRB = GTPR is satisfied. If GTCCRB >
GTPR is set, no compare match occurs.
19.9.3
Setting the Range for GTCNT Counter
The GTCNT counter register should be set with the range of 0 ≤ GTCNT ≤ GTPR.
19.9.4
GTCNT Counter Start/Stop
The control timing of starting and stopping the GTCNT counter by the GTCR.CST bit synchronizes the count clock that
is selected in GTCR.TPCS[2:0]. When GTCR.CST is updated, the GTCNT counter starts/stops after a count clock that is
selected in GTCR.TPCS[2:0]. Therefore, an event generated before the GTCNT counter actually starts is ignored,
resulting in cases where an event is accepted or an interrupt occurs after GTCR.CST is set to 0.
19.9.5
(1)
Priority Order of Each Event
GTCNT register
Table 19.23 shows a priority order of events updating the GTCNT register.
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Table 19.23
19. General PWM Timer (GPT)
Priority order of sources updating GTCNT
Source of updating GTCNT
Priority Order
Writing by CPU (writing to GTCNT/GTCLR)
High
Clear by hardware sources set in GTCSR
Count up or down by hardware sources set in GTUPSR/GTDNSR
Low
Count operation
If up-counting and down-counting by hardware sources occur at the same time, the GTCNT counter value does not
change.
When there is a conflict between updating the GTCNT register and reading by the CPU, pre-update data is read.
(2)
GTCR.CST bit
When there is a conflict between starting/stopping by hardware sources set in the GTSSR/GTPSR registers and writing
by the CPU (writing to GTCR/GTSTR/GTSTP registers), the writing by CPU has a priority over the starting/stopping by
hardware sources.
When there is a conflict between starting by hardware sources set in the GTSSR register and stopping by hardware
sources set in GTPSR register, the GTCR.CST bit value does not change.
If there is a conflict between updating the GTCR.CST bit and reading by the CPU, pre-update data is read.
(3)
GTCCRm registers (m = A to F)
When there is a conflict between input capture/buffer transfer operation and writing to the GTCCRm registers, the
writing to GTCCRm registers has a priority over input capture/buffer transfer operation. When there is a conflict between
input capture and writing to the counter register by the CPU or updating the counter register by hardware sources, the
pre-update counter value is captured.
If there is a conflict between updating the GTCCRm registers and reading by the CPU, pre-update data is read.
(4)
GTPR registers
When there is a conflict between buffer transfer operation and the writing to the GTPR register, the writing to GTPR
register has a priority over buffer transfer operation.
If there is a conflict between updating GTPR register and reading by the CPU, pre-update data is read.
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20. Asynchronous General Purpose Timer (AGT)
20.
Asynchronous General Purpose Timer (AGT)
20.1
Overview
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width
or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down counter. The reload register and the down counter are allocated
to the same address, and can be accessed by accessing the AGT register.
Table 20.1 lists the AGT specifications and Figure 20.1 shows the block diagram. Table 20.2 lists the AGT pin
configuration.
Table 20.1
AGT specifications
Parameter
Operating modes
Description
Timer mode
The count source is counted
Pulse output mode
The count source is counted and the output is inverted at each underflow of the
timer
Event counter mode
An external event is counted
Pulse width
measurement mode
An external pulse width is measured
Pulse period
measurement mode
An external pulse period is measured
Count source (operating clock)*2
PCLKB, PCLKB/2, PCLKB/8, AGTLCLK/d, AGTSCLK/d, or underflow signal of
AGT0*1 selectable. (d = 1, 2, 4, 8, 16, 32, 64, or 128)
Interrupt/Event link function (output)
Underflow event signal or measurement complete event signal
When the counter underflows
When the measurement of the active width of the external input (AGTIOn)
completes in pulse width measurement mode
When the set edge of the external input (AGTIOn) is input in pulse period
measurement mode.
Compare match A event signal
When the values of AGT and AGTCMA matched (Compare match A
function enabled).
Compare match B event signal
When the values of AGT and AGTCMB matched (Compare match B
function enabled).
Recovery from Software Standby mode can be performed by an
AGT1_AGTI, AGT1_AGTCMAI, or AGT1_AGTCMBI.
Selectable functions
Compare match function
One or two of the compare match A register and compare match B register is
selectable.
Note 1. AGT0 cannot use it. AGT1 connects directly with underflow event signal from timer AGT0.
Note 2. Satisfy the frequency of the peripheral module clock (PCLKB) ≥ the frequency of the count source clock.
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20. Asynchronous General Purpose Timer (AGT)
Data bus
16-bit
reload
register
TCK[2:0]
AGTLCLK
= 100b
(LOCO clock for AGT)
AGTSCLK
(Sub clock for AGT) = 110b
CKS[2:0]
Prescaler
1, 2, 4, 8, 16
32, 64, 128
AGTLCLK or AGTSCLK after division
PCLKB
PCLKB/8
TCK[2:0]
= 000b
= 001b
16-bit
reload
register
TCMEA or
TCMEB = 1
AGT underflows
AGT underflows or
AGT is rewritten
TCMEA and
TCMEB = 0
= 011b
PCLKB/2
= 100b or 110b
Underflow event signal from AGT0*2
16-bit
reload
register
AGTCMA
AGTCMB
Comparison
circuit
Comparison
circuit
TIOGT[1:0]
= 00b
TMOD[2:0]
= other than
010b
TCMEA
TSTART
Event is counted during polarity = 01b
period specified for AGTEEn*1
TCMEB
AGT
counter
Underflow
event signal/
Measurement
complete event
signal
TIPF[1:0]
TMOD[2:0]
= 011b or 100b
One edge/
both edges
switching
Polarity
selection
TEDGPL
TEDGSEL
TMOD[2:0] = 001b
AGTIOn_A pin
Counter
control
circuit
TEDGSEL = 1
Toggle flip-flop
Q
AGTOAn pin
TOEA
TOPOLA = 1
Toggle flip-flop
Q
TOPOLB = 1
TOEB
CLR
Q
TOPOLA = 0
AGTOBn pin
Measurement
complete signal
Q
TEDGSEL = 0
TOE
Compare
match A event
signal
16-bit counter
= 010b
AGTOn pin
Compare
match B event
signal
= 101b
Event is always counted
Digital
filter
TCM TCM TUN TED
AF
BF
DF GF
CLR
Q
Toggle flip-flop
TOPOLB = 0
Q
CLR
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
CK
Write to AGTMR1 or AGTMR2 register
Write 1 to TSTOP
TSTART, TSTOP, TUNDF, TCMAF, TCMBF: Bits in AGTCR register
TEDGSEL, TOE, TIPF[1:0], TIOGT[1:0]: Bits in AGTIOC register
TMOD[2:0], TEDGPL, TCK[2:0]: Bits in AGTMR1 register
CKS[2:0]: Bits in AGTMR2 register
TCMEA, TOEA, TOPOLA, TCMEB, TOEB, TOPOLB: Bits in AGTCMSR register
Note 1.
Note 2.
Figure 20.1
Table 20.2
The polarity can be selected by the EEPS bit in the AGTISR register.
AGT0 cannot use it. AGT1 uses the underflow of AGT0.
AGT block diagram
AGT I/O pins
Pin name
I/O
Function
AGTEEn
Input
External event input for AGT
AGTIOn
Input/output
External event input and pulse output for AGT
AGTOn
Output
Pulse output for AGT
AGTOAn
Output
Output compare match A output for AGT
AGTOBn
Output
Output compare match B output for AGT
Channel number (n = 0, 1)
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20.2
20. Asynchronous General Purpose Timer (AGT)
Register Descriptions
20.2.1
AGT Counter Register (AGT)
Address(es): AGT0.AGT 4008 4000h, AGT1.AGT 4008 4100h
Value after reset:
Bit
b15 to b0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
16-bit counter and reload register
*1, *2
Setting Range
R/W
0000h to FFFFh
R/W
Note 1. When 1 is written to the TSTOP bit in the AGTCR register, the 16-bit counter is forcibly stopped and set to
FFFFh.
Note 2. When the TCK[2:0] bit setting in the AGTMR1 register is a value other than 001b (PCLKB/8) or 011b (PCLKB/2),
if the AGT register is set to 0000h, a request signal to the ICU, the DTC and the ELC is generated once
immediately after the count starts. The AGTOn and AGTIOn output is toggled.
When the AGT register is set to 0000h in event counter mode, regardless of the value of TCK[2:0] bits, a request
signal to the ICU, the DTC and the ELC is generated once immediately after the count starts.
In addition, the AGTOn output is toggled even during a period other than the specified count period. When the
AGT register is set to 0001h or more, a request signal is generated each time AGT underflows.
AGT is a 16-bit register. The write value is written to the reload register and the read value is read from the counter.
The states of the reload register and the counter change depending on the TSTART bit in the AGTCR register and
TCMEA/TCMEB bit in the AGTCMSR register. For details, see section 20.3.1, Reload Register and Counter Rewrite
Operation.
The AGT register can be set by a 16-bit memory manipulation instruction.
20.2.2
AGT Compare Match A Register (AGTCMA)
Address(es): AGT0.AGTCMA 4008 4002h, AGT1.AGTCMA 4008 4102h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
Description
Setting range
R/W
b15 to b0
16-bit compare match A data is stored.*1
0000h to FFFFh
R/W
Note 1. Set the AGTCMA register to FFFFh when Compare match A is not used.
The AGTCMA register is a read/write register to set a value for compare match with the AGT counter. The states of the
reload register and the compare register A change depending on the TSTART bit in the AGTCR register. For details, see
section 20.3.2, Reload Register and Compare Register A/B Rewrite Operation.
The AGTCMA register can be set by a 16-bit memory manipulation instruction.
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20.2.3
20. Asynchronous General Purpose Timer (AGT)
AGT Compare Match B Register (AGTCMB)
Address(es): AGT0.AGTCMB 4008 4004h, AGT1.AGTCMB 4008 4104h
Value after reset:
Bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
b15 to b0
16-bit compare match B data is
stored.*1
Setting range
R/W
0000h to FFFFh
R/W
Note 1. Set the AGTCMB register to FFFFh when Compare match B is not used.
The AGTCMB register is a read/write register to set a value for compare match with the AGT counter. The states of the
reload register and the compare register B change depending on the TSTART bit in the AGTCR register. For details, see
section 20.3.2, Reload Register and Compare Register A/B Rewrite Operation.
The AGTCMB register can be set by a 16-bit memory manipulation instruction.
20.2.4
AGT Control Register (AGTCR)
Address(es): AGT0.AGTCR 4008 4008h, AGT1.AGTCR 4008 4108h
b7
b6
b5
b4
TCMBF TCMAF TUNDF TEDGF
Value after reset:
0
0
0
0
b3
—
b2
b1
b0
TSTOP TCSTF TSTAR
T
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TSTART
AGT count start*2
0: Count stops
1: Count starts
R/W
b1
TCSTF
AGT count status flag*2
0: Count stops
1: Count in progress
R
b2
TSTOP
AGT count forced stop*1
0: Writing is invalid
1: The count is forcibly stopped
W
b3
—
Reserved
The read value is 0. The write value should be 0.
R/W
b4
TEDGF
Active edge judgment flag
0: No active edge received
1: Active edge received
R/(W)*3
b5
TUNDF
Underflow flag
0: No underflow
1: Underflow
R/(W)*3
b6
TCMAF
Compare match A flag
0: No match
1: Match
R/(W)*3
b7
TCMBF
Compare match B flag
0: No match
1: Match
R/(W)*3
Note 1. When 1 (count is forcibly stopped) is written to the TSTOP bit, TSTART and TCSTF bits are initialized at the
same time. The pulse output level is also initialized. The read value is 0.
Note 2. For notes on using TSTART and TCSTF bits, see section 20.4.1, Count Operation Start and Stop Control.
Note 3. Only 0 can be written to clear the flag.
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20. Asynchronous General Purpose Timer (AGT)
TSTART bit (AGT count start)
Count operation is started by writing 1 to the TSTART bit and stopped by writing 0. When the TSTART bit is set to 1
(count starts), the TCSTF bit is set to 1 (count in progress) in synchronization with the count source. Also, after 0 is
written to the TSTART bit, the TCSTF bit is set to 0 (count stops) in synchronization with the count source. For details,
see section 20.4.1, Count Operation Start and Stop Control.
TCSTF flag (AGT count status flag)
The TCSTF flag indicates the AGT count status.
[Setting condition]
When 1 is written to the TSTART bit (the TCSTF bit is set to 1 in synchronization with the count source).
[Clearing conditions]
When 0 is written to the TSTART bit (the TCSTF bit is set to 0 in synchronization with the count source)
When 1 is written to the TSTOP bit.
TSTOP bit (AGT count forced stop)
When 1 is written to this bit, the count is forcibly stopped. The read value is 0.
TEDGF flag (Active edge judgment flag)
The TEDGF flag indicates that an active edge was detected.
[Setting condition]
When the measurement of the active width of the external input (AGTIOn) is complete in pulse width measurement
mode
When the set edge of the external input (AGTIOn) is input in pulse period measurement mode.
[Clearing condition]
When 0 is written to this flag by software.
TUNDF flag (Underflow flag)
The TUNDF flag indicates that the counter underflowed.
[Setting condition]
When the counter underflows.
[Clearing condition]
When 0 is written to this flag by software.
TCMAF flag (Compare match A flag)
The TCMAF flag indicates that compare match A was detected.
[Setting condition]
When the value in the AGT register matches the value in the AGTCMA register.
[Clearing condition]
When 0 is written to this flag by software.
TCMBF flag (Compare match B flag)
The TCMBF flag indicates that compare match B was detected.
[Setting condition]
When the value in the AGT register matches the value in the AGTCMB register.
[Clearing condition]
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20. Asynchronous General Purpose Timer (AGT)
When 0 is written to this flag by software.
20.2.5
AGT Mode Register 1 (AGTMR1)
Address(es): AGT0.AGTMR1 4008 4009h, AGT1.AGTMR1 4008 4109h
b7
b6
—
Value after reset:
0
b5
b4
0
b2
TEDGP
L
TCK[2:0]
0
b3
0
0
b1
b0
TMOD[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
TMOD[2:0]
Operating mode*3
b2
R/W
b3
TEDGPL
Edge polarity*4
0: Single-edge
1: Both-edge
R/W
b6 to b4
TCK[2:0]
Count source*1, *2, *5
b6
R/W
b7
—
Reserved
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
b0
0 0 0: Timer mode
0 0 1: Pulse output mode
0 1 0: Event counter mode
0 1 1: Pulse width measurement mode
1 0 0: Pulse period measurement mode
Settings other than above are prohibited.
0
0
0
1
0
0
1
0
b4
0: PCLKB
1: PCLKB/8
1: PCLKB/2
0: Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register
1 0 1: Underflow event signal from AGT0*6
1 1 0: Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register.
Settings other than above are prohibited.
The read value is 0. The write value should be 0.
R/W
Write access to the AGTMR1 register initializes the output from pins AGTOn, AGTIOn, AGTOAn and AGTOBn of
AGT (n = 0, 1). For details on the output level at initialization, see the description of section 20.2.7, AGT I/O
Control Register (AGTIOC).
When event counter mode is selected, the external input (AGTIOn) is selected as the count source regardless of
the setting of TCK[2:0] bits.
Do not switch count sources during count operation. Count sources should be switched when both the TSTART
and TCSTF bits in the AGTCR register are set to 0 (count stops).
The operating mode can only be changed when the count is stopped while both the TSTART and TCSTF bits in
the AGTCR register are set to 0 (count stops). Do not change the operating mode during count operation.
The TEDGPL bit is only enabled in event counter mode.
To run AGT in Software Standby mode, select AGTLCLK or AGTSCLK.
AGT0 cannot use it (setting prohibited). AGT1 uses the underflow of AGT0.
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20.2.6
20. Asynchronous General Purpose Timer (AGT)
AGT Mode Register 2 (AGTMR2)
Address(es): AGT0.AGTMR2 4008 400Ah, AGT1.AGTMR2 4008 410Ah
Value after reset:
b7
b6
b5
b4
b3
LPM
—
—
—
—
0
0
0
0
0
b2
b1
b0
CKS[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CKS[2:0]
AGTLCLK or
AGTSCLK count
source clock frequency
division ratio*1, *2, *3
b2
R/W
b6 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
LPM
Low Power Mode
0: Normal mode
1: Low power mode
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1/1
1: 1/2
0: 1/4
1: 1/8
0: 1/16
1: 1/32
0: 1/64
1: 1/128
Note 1. Do not rewrite the CKS[2:0] bit during count operation. The CKS[2:0] bit must be rewritten when both the
TSTART and TCSTF bits in the AGTCR register are set to 0 (count stops).
Note 2. When count source is only AGTLCLK or AGTSCLK, the switch of CKS[2:0] is valid.
Note 3. Do not switch the TCK[2:0] bits in the AGTMR1 register when CKS[2:0] are not 000b. Switch the TCK[2:0] bits in
the AGTMR1 register after CKS[2:0] are set to 000b, and wait for 1 cycle of the count source.
LPM bit (Low Power Mode)
The LPM bit selects low power mode, which impacts access to certain AGT registers. Set this bit to 1 to operate in low
power. When this bit is 1, access to the following registers is prohibited:
AGT/AGTCMA/AGTCMB/AGTCR.
After this bit is switched from 1 to 0, the first access to the register is constrained as follows:
AGT: Read AGT register twice. Only the second reading of data is valid.
AGT, AGTCMA, AGTCMB, and AGTCR: Allow at least 2 cycles of the count source clock when writing to the
register.
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20.2.7
20. Asynchronous General Purpose Timer (AGT)
AGT I/O Control Register (AGTIOC)
Address(es): AGT0.AGTIOC 4008 400Ch, AGT1.AGTIOC 4008 410Ch
b7
Value after reset:
b6
b5
b4
b3
b2
b1
b0
TIOGT[1:0]
TIPF[1:0]
—
TOE
—
TEDGS
EL
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TEDGSEL
I/O polarity switch
Function varies depending on the operating mode (see Table 20.3 and
Table 20.4).
The TEDGSEL bit is used to switch the AGTOn output polarity and the
AGTIOn input/output edge and polarity. In pulse output mode, it controls
only polarity of the AGTOn output and AGTIOn output. The AGTOn
output and AGTIOn output are initialized when the AGTMR1 register is
written and the TSTOP bit of the AGTCR register is written with 1.
R/W
b1
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2
TOE
AGTOn output enable
0: AGTOn output disabled
1: AGTOn output enabled
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
filter*3
b5 b4
R/W
b7 b6
R/W
b5, b4
TIPF[1:0]
Input
b7, b6
TIOGT[1:0]
Count control*1, *2
0 0: No filter
0 1: Filter sampled at PCLKB
1 0: Filter sampled at PCLKB/8
1 1: Filter sampled at PCLKB/32
These bits are used to specify the sampling frequency of the filter for the
AGTIOn input. If the input to the AGTIOn pin is sampled and the value
matches three successive times, that value is taken as the input value.
0 0: Event is always counted
0 1: Event is counted during polarity period specified for AGTEEn.
Settings other than above are prohibited.
Note 1. When AGTEEn or the timer output signal is used, the polarity to count an event can be selected by the EEPS bit
in the AGTISR register.
Note 2. TIOGT[1:0] bits are only enabled in event counter mode.
Note 3. When event counter mode operation is performed during Software Standby mode, the digital filter function cannot
be used.
Table 20.3
AGTIOn I/O edge and polarity switching
Operating mode
Function
Timer mode
Not used
Pulse output mode
0: Output is started at high (initialization level: high)
1: Output is started at low (initialization level: low).
Event counter mode
0: Count at rising edge
1: Count at falling edge.
Pulse width measurement mode
0: Low-level width is measured.
1: High-level width is measured.
Pulse period measurement mode
0: Measure from one rising edge to the next rising edge
1: Measure from one falling edge to the next falling edge.
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Table 20.4
20. Asynchronous General Purpose Timer (AGT)
AGTOn output polarity switching
Operating mode
Function
All modes
0: Output is started at low (initialization level: low)
1: Output is started at high (initialization level: high).
20.2.8
AGT Event Pin Select Register (AGTISR)
Address(es): AGT0.AGTISR 4008 400Dh, AGT1.AGTISR 4008 410Dh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
EEPS
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
EEPS
AGTEEn polarity selection
0: An event is counted during the low-level period
1: An event is counted during the high-level period.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
20.2.9
AGT Compare Match Function Select Register (AGTCMSR)
Address(es): AGT0.AGTCMSR 4008 400Eh, AGT1.AGTCMSR 4008 410Eh
b7
—
Value after reset:
0
b6
b5
b4
TOPOL TOEB TCMEB
B
0
0
0
b3
—
b2
b1
b0
TOPOL TOEA TCMEA
A
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TCMEA
Compare match A register enable*1, *2
0: Disable compare match A register
1: Enable compare match A register.
R/W
b1
TOEA
AGTOAn output enable*1, *2
0: Disable AGTOAn output
1: Enable AGTOAn output.
R/W
b2
TOPOLA
AGTOAn polarity select*1, *2
0: Start AGTOAn output on low
1: Start AGTOAn output on high.
R/W
b3
—
Reserved
These bits are read as 0. The write value should be 0. R/W
enable*1, *2
0: Disable compare match B register
1: Enable compare match B register.
R/W
AGTOBn output enable*1, *2
0: Disable AGTOBn output
1: Enable AGTOBn output.
R/W
TOPOLB
AGTOBn polarity select*1, *2
0: Start AGTOBn output on low
1: Start AGTOBn output on high.
R/W
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
TCMEB
Compare match B register
b5
TOEB
b6
b7
Note 1. Do not rewrite the AGTCMSR register during count operation. Only rewrite the AGTCMSR register when both the
TSTART and TCSTF bits in the AGTCR register are set to 0 (count stops).
Note 2. Do not set 1 when in pulse width measurement mode or pulse period measurement mode.
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20.2.10
20. Asynchronous General Purpose Timer (AGT)
AGT Pin Select Register (AGTIOSEL)
Address(es): AGT0.AGTIOSEL 4008 400Fh, AGT1.AGTIOSEL 4008 410Fh
Value after reset:
Bit
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
TIES
—
—
—
—
0
0
0
0
0
0
0
0
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
TIES
AGTIOn Input Enable
0: Disable external event input during Software Standby
mode
1: Enable external event input during Software Standby
mode.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The AGTIOSEL Register sets the AGTIOn pin when using the AGTIOn in Software Standby mode. The AGTIOSEL
Register can be set by an 8-bit memory manipulation instruction.
TIES bit (AGTIOn Input Enable)
The TIES bit enables or disables an external event input.
20.3
20.3.1
Operation
Reload Register and Counter Rewrite Operation
Regardless of the operating mode, the timing of the rewrite operation to the reload register and the counter differs
depending on the value of the TSTART bit in the AGTCR register and of the TCMEA/TCMEB bit in the AGTCMSR
register. When the TSTART bit is 0 (count stops), the count value is directly written to the reload register and the counter.
When the TSTART bit is 1 (count starts) and the TCMEA bit and the TCMEB bit is 0 (compare match A/B register is
invalid), the value is written to the reload register in synchronization with the count source, and then to the counter in
synchronization with the next count source. When the TSTART bit is 1 (count starts) and the TCMEA bit or the TCMEB
bit is 1 (compare match A register or compare match B register is valid), the value is written to the reload register in
synchronization with the count source, and then to the counter in synchronization with the underflow of the counter.
Figure 20.2 and Figure 20.3 show the timing of rewrite operation with TSTART bit value and TCMEA/TCMEB bit
value.
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20. Asynchronous General Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register by a program
Write 1234h to AGT register by a program
Write 5678h to AGT register by a program
Register write clock
Count source
TSTART bit in AGTCR
register
TCMEB bit in AGTCMSR
register
TCMEA bit in AGTCMSR
register
AGT register
FFFFh
5678h
1234h
Reload register load signal
Reload register load clock
Counter load signal
Counter load clock
Figure 20.2
Reload register
FFFFh
AGT counter
FFFFh
5678h
5678h
1234h
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh 1234h 1233h 1232h 1231h 1230h
Timing of rewrite operation with TSTART and TCMEA or TCMEB bit values when compare match
A register or compare match B register is invalid
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20. Asynchronous General Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register by a program
Write 1234h to AGT register by a program
Write 5678h to AGT register by a program
Register write clock
Count source
TSTART bit in AGTCR
register
TCMEB bit in AGTCMSR
register
or
TCMEA bit in AGTCMSR
register
AGT register
FFFFh
5678h
1234h
Reload register load signal
Reload register load clock
Counter load signal
Counter load clock
Reload register
FFFFh
AGT counter
FFFFh
Figure 20.3
20.3.2
5678h
5678h
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh •••••
1234h
••••• 0002h 0001h 0000h 1234h1233h 1232h1231h
Timing of rewrite operation with TSTART and TCMEA or TCMEB bit values when compare match
A register or compare match B register is valid
Reload Register and Compare Register A/B Rewrite Operation
Regardless of the operating mode, the timing of the rewrite operation to compare register A/B depends on the value of
the TSTART bit in the AGTCR register. When the TSTART bit is 0 (count stops), the count value is directly written to
the reload register and compare register A/B. When the TSTART bit is 1 (count starts), the value is written to the reload
register in synchronization with the count source, and then to the compare register in synchronization with the underflow
of the counter.
Figure 20.4 shows the timing of rewrite operation with TSTART bit value for compare register A. Compare register B is
of the same timing as compare register A.
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20. Asynchronous General Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register by a program
Write 1234h to AGTCMA register by a program
Write 2345h to AGTCMA register by a program
Register write clock
Count source
TSTART bit in AGTCR
register
AGT counter
AGTCMA register
5678h
FFFFh
5677h 5676h 5675h 5674h 5673h 5672h 5671h 5670h 566Fh 566Eh
1234h
...
0000h 5678h 5677h
2345h
Reload register A load signal
Reload register A load clock
Compare register A load signal
Compare register A load clock
Reload register of
compare match A
FFFFh
Compare register A
FFFFh
1234h
2345h
1234h
2345h
Underflow signal
Figure 20.4
20.3.3
Timing of rewrite operation with TSTART bit value for compare register A
Timer Mode
In this mode, the AGT counter is decremented by the count source selected by TCK[2:0] bits in the AGTMR1 register.
In timer mode, the count value is decremented by 1 on each rising edge of the count source. When the count value
reaches 0000h and the next count source is input, an underflow occurs and an interrupt request is generated.
Figure 20.5 shows the operation example in timer mode.
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20. Asynchronous General Purpose Timer (AGT)
Count source
Reload register
Previous value
(0300h)
New value (1010h)
Counter reloading occurs
AGT counter
02FAh 02F9h 02F8h 02F7h 1010h 100Fh 100Eh •••••
••••• 0000h 1010h 100Fh 100Eh 100Dh 100Ch 100Bh
TUNDF bit in AGTCR
register
An underflow
occurs
Set to 0 by a
program
Underflow signal
Figure 20.5
20.3.4
Operation example in timer mode
Pulse Output Mode
In this mode, the counter is decremented by the count source selected by TCK[2:0] bits in the AGTMR1 register, and the
output level of pins AGTIOn and AGTOn pin is inverted each time an underflow occurs.
In pulse output mode, the count value is decremented by 1 on each rising edge of the count source. When the count value
reaches 0000h and the next count source is input, an underflow occurs and an interrupt request is generated.
In addition, a pulse can be output from the AGTIOn and AGTOn pins. The output level is inverted each time an
underflow occurs. The pulse output from the AGTOn pin can be stopped with the TOE bit in the AGTIOC register. The
output level can be selected with the TEDGSEL bit in the AGTIOC register.
Figure 20.6 shows the operation example in pulse output mode.
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20. Asynchronous General Purpose Timer (AGT)
Write 1 to TSTART bit in AGTCR register
by a program
Write 0002h to
AGT register by a
program
Write 0004h to
AGT register by a
program
Count source
TSTART bit in
AGTCR register
AGT register
FFFFh
Reload register
FFFFh
AGT counter
FFFFh
0002h
0004h
0002h
0002h
0004h
0001h 0000h 0002h 0001h 0000h 0002h 0001h 0000h 0002h 0001h 0004h 0003h 0002h 0001h 0000h 0004h 0003h
TEDGSEL bit in
AGTIOC register
0
AGTOn pin output
AGTIOn pin output
TUNDF bit in
AGTCR register
Set to 0 by a program
Underflow signal
Figure 20.6
20.3.5
Operation example in pulse output mode
Event Counter Mode
In this mode, the counter is decremented by an external event signal (count source) input to the AGTIOn pin. Different
periods for counting events can be set with the TIOGT[1:0] bits in the AGTIOC register and the AGTISR register. In
addition, the filter function for the AGTIOn input can be specified with TIPF[1:0] bits in the AGTIOC register. The
output from the AGTOn pin can be toggled even in event counter mode.
Figure 20.7 shows the operation example in event counter mode.
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20. Asynchronous General Purpose Timer (AGT)
Event counter mode is entered
TMOD[2:0] bits in
AGTMR1 register
010b
Event is counted at rising edge
00h
AGTIOC register
TSTART bit
in AGTCR register
Event input is started
Event input is completed
AGTIOn pin
event input
AGT counter
FFFFh
TUNDF bit in
AGTCR register
FFFEh FFFDh
0000h
FFFFh
FFFEh
Counter initial value is set
Set to 0 by a program
Underflow signal
Figure 20.7
Operation example 1 in event counter mode
Figure 20.8 shows an operation example for counting during the specified period in event counter mode (TIOGT[1:0]
bits in the AGTIOC register are set to 01b).
Timing example when the setting of operating mode is as follows :
AGTMR1 register: TMOD[2:0] = 010b (event counter mode)
AGTIOC register: TIOGT[1:0] = 01b (event is counted during specified period for external interrupt pin)
TIPF[1:0] = 00b (no filter)
TEDGSEL = 1 (count at rising edge)
AGTISR register: EEPS = 1 (high-level period is counted)
TSTART bit in AGTCR
register
Event input starts
*2
Event input to AGTIOn pin
*1
AGTEEn or
timer output signal
AGT counter
FFFFh
FFFEh
FFFDh
FFFCh
FFFBh
FFFAh
FFF9h
FFF8h
The counter initial value is set
Note 1.
Note 2.
To control synchronization, there is a delay of two cycles of the count source until count operation is affected, and there is a possibility that
counting start timing is shifted for one cycle due to the phase difference between the AGTEEn and the sampling clock.
Count operation may be performed for two cycles of the count source immediately after the count is started, depending on the previous
state before the count is stopped.
To disable the count for two cycles immediately after the count is started, write 1 to the TSTOP bit in the AGTCR register to initialize the
internal circuit, and then complete the operation settings before starting count operation.
Figure 20.8
20.3.6
Operation example 2 in event counter mode
Pulse Width Measurement Mode
In this mode, the pulse width of an external signal input to the AGTIOn pin is measured.
When the level specified by the TEDGSEL bit in the AGTIOC register is input to the AGTIOn pin, the counter is
decremented by the count source selected by TCK[2:0] bits in the AGTMR1 register. When the specified level on the
AGTIOn pin ends, the counter is stopped, the TEDGF bit in the AGTCR register is set to 1 (active edge received), and an
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20. Asynchronous General Purpose Timer (AGT)
interrupt request is generated. The measurement of pulse width data is performed by reading the count value while the
counter is stopped. Also, when the counter underflows during measurement, the TUNDF bit in the AGTCR register is set
to 1 (underflow) and an interrupt request is generated.
Figure 20.9 shows the operation example in pulse width measurement mode.
This example applies when the high-level width of the measurement pulse is measured (TEDGSEL bit in AGTIOC register = 1)
FFFFh
n = AGT register content
Measurement is started
Counter content (hex)
n
Underflow
Measurement
is stopped
Measurement
is stopped
Measurement
is started
0000h
Measurement
is started
Time
TSTART bit in
AGTCR register
Set to 1 by a program
Measurement pulse
input to AGTIOn pin
Underflow event signal/
Measurement complete event signal
TEDGF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
TUNDF bit in
AGTCR register
Set to 0 by a program
Figure 20.9
20.3.7
Operation example in pulse width measurement mode
Pulse Period Measurement Mode
In this mode, the pulse period of an external signal input to the AGTIOn pin is measured.
The counter is decremented by the count source selected by TCK[2:0] bits in the AGTMR1 register. When a pulse with
the period specified with the TEDGSEL bit in the AGTIOC register is input to the AGTIOn pin, the count value is
transferred to the read-out buffer on the rising edge of the count source. The value in the reload register is loaded to the
counter at the next rising edge. Simultaneously, the TEDGF bit in the AGTCR register is set to 1 (active edge received)
and an interrupt request is generated. The read-out buffer (AGT register) is read at this time and the difference from the
reload value (see section 20.4.5, How to Calculate Event Number, Pulse Width, and Pulse Period) is the period data of
the input pulse. The period data is retained until the read-out buffer is read. When the counter underflows, the TUNDF
bit in the AGTCR register is set to 1 (underflow) and an interrupt request is generated.
Figure 20.10 shows the operation example in pulse period measurement mode.
Only input pulses with a period longer than twice the period of the count source are measured. Also, the low-level and
high-level widths must be both longer than the period of the count source. If a pulse period shorter than these conditions
is input, the input might be ignored.
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20. Asynchronous General Purpose Timer (AGT)
Count source
TSTART bit
in AGTCR register
Measurement pulse input
Counter is reloaded
AGT counter
Content of read-out buffer
0300h
02FFh 02FEh 0300h 02FFh 02FEh 02FDh02FCh 02FBh 02FAh 02F9h 02F8h 02F7h 0300h 02FFh ••••
0300h
02FFh
02FEh
02FBh 02FAh 02F9h 02F8h
02F7h
•••• 0001h 0000h 0300h 02FFh 02FEh
••••
•••• 0001h 0000h 0300h 02FFh
Counter value is read*1
Read signal of counter
*2
02FEh
*2
02F7h
Read data
TEDGF bit in
AGTCR register
TUNDF bit in
AGTCR register
*3
*3
Set to 0 by a program*4
Underflow event signal/
Measurement complete event signal
Set to 0 by a program
*5
This example applies when the initial value of the AGT register is set to 0300h, the TEDGSEL bit in the AGTIOC register is set to 0, and the period
from one rising edge to the next edge of the measurement pulse is measured .
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Reading from the AGT register must be performed during the period from when the TEDGF bit is set to 1 (active edge received) until the
next active edge is input. The content of the read-out buffer is retained until the AGT register is read. If it is not read before the active edge
is input, the measurement result of the previous period is retained.
When the AGT register is read in pulse period measurement mode, the content of the read-out buffer is read.
When the active edge of the measurement pulse is input and then the set edge of an external pulse is input, the TEDGF bit in the AGTCR
register is set to 1 (active edge received).
To set to 0 by a program, write 0 to the TEDGF bit in the AGTCR register using an 8-bit memory manipulation instruction.
To set to 0 by a program, write 0 to the TUNDF bit in the AGTCR register using an 8-bit memory manipulation instruction.
Figure 20.10
20.3.8
Operation example in pulse period measurement mode
Compare Match function
This function detects matches between the content of the AGTCMA/AGTCMB register and the content of the AGT
register. This function is enabled when the TCMEA bit or the TCMEB bit in the AGTCMSR register is 1 (Compare
match A register or compare match B register is valid). The counter is decremented by the count source selected by
TCK[2:0] bits in the AGTMR1 register, and when the values of AGT and AGTCMA/AGTCMB match, the TCMAF/
TCMBF bit in the AGTCR register is set to 1, and an interrupt request is generated.
When the compare match function is enabled, the timing of the rewrite operation to the reload register and the counter
differs. See section 20.3.1, Reload Register and Counter Rewrite Operation for details. In addition, the output level of the
AGTOAn and AGTOBn pins is inverted by the match and by the underflow. The output level can be selected by the
TOPOLA/TOPOLB bit in the AGTCMSR register.
Figure 20.11 shows the operation example in compare match mode.
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20. Asynchronous General Purpose Timer (AGT)
n = AGT register content
m = Compare Match A register setting value
p = Compare Match B register setting value
FFFFh
Count starts
Counter content (hex)
Underflow
Underflow
n
Matched
Matched
m
Matched
Matched
p
Time
0000h
TSTART bit in
AGTCR register
Set to 1 by a program
AGTOAn pin
output
Output inverted by compare match
Output inverted by underflow
Output inverted by compare match
Output inverted by underflow
TCMAF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Compare match A
event signal
AGTOBn pin output
Output inverted by underflow
Output inverted by compare match
Output inverted by underflow
Output inverted by compare match
TCMBF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Compare match B
event signal
AGTOn pin output
Output inverted by underflow
Output inverted by underflow
TUNDF bit in
AGTCR register
Set to 0 by a program
Set to 0 by a program
Underflow
event signal
Figure 20.11
20.3.9
Operation example in compare match mode when TOPOLA = 0, TOPOLB = 0
Output Settings for Each Mode
Table 20.5 to Table 20.8 list the states of the AGTOn, AGTIOn, AGTOAn, and AGTOBn pins in each mode.
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Table 20.5
20. Asynchronous General Purpose Timer (AGT)
AGTOn pin setting
AGTIOC Register
Operating mode
TOE bit
TEDGSEL bit
AGTOn pin output
All modes
1
1
Inverted output
0
Normal output
0 or 1
Output disabled
0
Table 20.6
AGTIOn pin setting
AGTIOC Register
Operating mode
TEDGSEL bit
AGTIOn pin I/O
Timer mode
0 or 1
Input
(Not used)
Pulse output mode
1
Normal output
0
Inverted output
0 or 1
Input
Event counter mode
Pulse width measurement mode
Pulse period measurement mode
Table 20.7
AGTOAn pin setting
AGTCMSR Register
Operating mode
TOEA bit
TOPOLA bit
AGTOAn pin output
Timer mode
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(Not used)
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(Not used)
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(Not used)
0
0
Prohibited
Pulse output mode
Event counter mode
Pulse width measurement mode
Pulse period measurement mode
Table 20.8
AGTOBn pin setting (1 of 2)
AGTCMSR Register
Operating mode
TOEB bit
TOPOLB bit
AGTOBn pin output
Timer mode
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(Not used)
1
1
Inverted output
0
Normal output
0 or 1
Output disabled
(Not used)
Pulse output mode
0
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Table 20.8
20. Asynchronous General Purpose Timer (AGT)
AGTOBn pin setting (2 of 2)
AGTCMSR Register
Operating mode
TOEB bit
TOPOLB bit
AGTOBn pin output
Event counter mode
1
1
Inverted output
0
Normal output
0
0 or 1
Output disabled
(Not used)
0
0
Prohibited
Pulse width measurement mode
Pulse period measurement mode
20.3.10
Standby Mode
AGT can operate in Software Standby mode. Set it to Software Standby mode with count operation start (TSTART = 1,
TCSTF = 1).
Table 20.9 and Table 20.10 show the setting that can be used in Software Standby mode.
Table 20.9
Usable setting in Software Standby mode (AGT0)
Operating mode
TCK[2:0] bits of AGTMR1
Register
Operating clock
Resurgence factor of
CPU
Timer mode
100b or 110b
AGTLCLK or AGTSCLK
–
Pulse output mode
100b or 110b
AGTLCLK or AGTSCLK
–
Event counter mode
–
(invalid)
AGTIOn
–
Pulse width measurement mode
100b or 110b
AGTLCLK or AGTSCLK
–
Pulse period measurement mode
100b or 110b
AGTLCLK or AGTSCLK
–
Operating clock
Resurgence factor of
CPU
Table 20.10
Usable setting in Software Standby mode (AGT1)
Operating mode
TCK[2:0] Bits of AGTMR1
Register
Timer mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Compare match A/B
Pulse output mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Compare match A/B
Event counter mode
–
(invalid)
AGTIOn
Underflow
Compare match A/B
Pulse width measurement mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Active edge
Pulse period measurement mode
100b or 110b or 101b *1
AGTLCLK or AGTSCLK or
AGT0 underflow
Underflow
Active edge
Note:
Release of Software Standby mode is only AGT1.
Note 1. Only when AGT0 operates in Table 20.9.
20.3.11
Interrupt Sources
AGT has three interrupt sources for channels n (n = 0, 1) as listed in Table 20.11:
AGTn_AGTI
AGTn_AGTCMAI
AGTn_AGTCMBI
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Table 20.11
20. Asynchronous General Purpose Timer (AGT)
AGT interrupt sources
Name
Interrupt source
DTC activation
AGTn_AGTI
When the counter underflows
When the measurement of the active width of the external input (AGTIOn) is complete in
pulse width measurement mode
When the set edge of the external input (AGTIOn) is input in pulse period measurement
mode.
Possible
AGTn_AGTCMAI
When the values of AGT and AGTCMA match
Possible
AGTn_AGTCMBI
When the values of AGT and AGTCMB match
Possible
Channel number (n = 0, 1)
20.3.12
Event Signal Output to ELC
The AGT uses the Event Link Controller (ELC) to perform a link operation to a specified module using the interrupt
request signal as the event signal. The AGT outputs compare match A, compare match B, and underflow/measurement
complete signals as event signals. For details, see section 15, Event Link Controller (ELC).
20.4
20.4.1
Usage Notes
Count Operation Start and Stop Control
When an operating mode (see Table 20.1) other than the event counter mode is set, or the count source is set to other
than AGT0 underflow (TCK[2:0] = 101b):
After 1 (count starts) is written to the TSTART bit in the AGTCR register while the count stops, the TCSTF bit
in the AGTCR register remains 0 (count stops) for 3 cycles of the count source. Do not access the registers
associated with AGT*1 other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for 3
cycles of the count source. When the TCSTF bit is set to 0, the count stops. Do not access the registers
associated with AGT*1. other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TSTART bit from 0 to 1. See section 12, Interrupt Controller
Unit (ICU) for details.
Note 1. Registers associated with AGT: AGT, AGTCMA, AGTCMB, AGTCR, AGTMR1, AGTMR2, AGTIOC, AGTISR
and AGTCMSR
When the operating mode (see Table 20.1) is set to event counter mode, or the count source is set to AGT0
underflow (TCK[2:0] = 101b):
After 1 (count starts) is written to the TSTART bit in the AGTCR register while the count stops, the TCSTF bit
in the AGTCR register remains 0 (count stops) for 2 PCLKB cycles. Do not access the registers associated with
AGT*1 other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for 2
PCLKB cycles. When the TCSTF bit is set to 0, the count stops. Do not access the registers associated with
AGT*1 other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TSTART bit from 0 to 1. See section 12, Interrupt Controller
Unit (ICU) for details.
Note 1. Registers associated with AGT: AGT, AGTCMA, AGTCMB, AGTCR, AGTMR1, AGTMR2, AGTIOC, AGTISR
and AGTCMSR
20.4.2
Access to Counter Register
When TSTART and TCSTF bits in the AGTCR register are both 1 (count starts), allow at least 3 cycles of the count
source clock between writes when writing to the AGT register.
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20.4.3
20. Asynchronous General Purpose Timer (AGT)
When Changing Mode
The registers associated with AGT operating mode (AGTMR1, AGTMR2, AGTIOC, AGTISR, AGTCMSR and
AGTIOC) can be changed only when the count stops with both the TSTART and TCSTF bits set to 0 (count stops). Do
not change these registers during count operation.
When the registers associated with AGT operating mode are changed, the values of TEDGF, TUNDF, TCMAF, and
TCMBF bits are undefined. Before starting the count, write 0 to the following bits:
TEDGF
TUNDF
TCMAF
TCMBF.
20.4.4
Digital Filter
When using the digital filter, do not start the timer operation for 5 cycles of the digital filter clock after setting TIPF[1:0]
bits and when the TEDGSEL bit in the AGTIOC register changes.
20.4.5
How to Calculate Event Number, Pulse Width, and Pulse Period
In event counter mode, event number is expressed mathematically as follows:
Event number = initial value of counter [AGT register] - counter value of active event end
In pulse width measurement mode, pulse width is expressed mathematically as follows:
Pulse width = counter value of stopping measurement - counter value of next stopping measurement
In pulse period measurement mode, input pulse period is expressed mathematically as follows:
Period of input pulse = (initial value of counter [AGT register] - reading value of the read-out buffer) + 1
20.4.6
When Count is Forcibly Stopped by TSTOP Bit
After the counter is forcibly stopped by the TSTOP bit in the AGTCR register, do not access the following I/O registers
for one cycle of the count source:
AGT
AGTCMA
AGTCMB
AGTCR
AGTMR1
AGTMR2.
20.4.7
When Selecting AGT0 Underflow as Count Source
Operate the AGT according to the following procedures when selecting the underflow signal of AGT as the count source.
(1)
(2)
Procedure for starting operation
1.
Set AGT0 and AGT1.
2.
Start the count operation of AGT1.
3.
Start the count operation of AGT0.
Procedure for stopping operation
1.
Stop the count operation of AGT0.
2.
Stop the count operation of AGT1.
3.
Stop the count source clock of AGT1. Write 000b in AGT1.AGTMR1.TCK[2:0] bits.
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20.4.8
20. Asynchronous General Purpose Timer (AGT)
Reset of I/O Register
The I/O register of the AGT is not initialized by different types of resets. For details, see section 5, Resets.
20.4.9
When Selecting PCLKB, PCLKB/8, or PCLKB/2 as Count Source
When a reset is generated, the operation of AGT cannot be guaranteed. Set the registers associated with AGT again.
20.4.10
When Selecting AGTLCLK or AGTSCLK as Count Source
The MSTPD2 in MSTPCRD register must be set to 1 except when accessing the AGT1 registers. The MSTPD3 in the
MSTPCRD register must be set to 1 except when accessing the AGT0 registers. When a reset occurs while MSTPD2 or
MSTPD3 is 0, the operation of AGT1 or AGT0 cannot be guaranteed. Set the registers associated with AGT again.
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21. Realtime Clock (RTC)
21.
Realtime Clock (RTC)
21.1
Overview
The RTC has two counting modes, calendar count mode and binary count mode, that are used by switching register
settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates
for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count
mode can be used for calendars other than the Gregorian (Western) calendar.
The sub-clock oscillator or LOCO can be selected as the count source of the time counters. The RTC uses a 128-Hz clock
acquired by dividing the count source by a prescaler. Year, month, date, day-of-week, a.m./p.m. (in 12-hour mode), hour,
minute, second, or 32-bit binary is counted by 1/128 second.
Table 21.1 lists the RTC specifications, Figure 21.1 shows the block diagram, and Table 21.2 shows the pin configuration
of the RTC.
Table 21.1
RTC specifications
Parameter
Description
Count mode
Calendar count mode/binary count mode
Count
source*1
Sub-clock (XCIN) or LOCO
Clock and calendar
functions
Calendar count mode
Year, month, date, day of week, hour, minute, second are counted, BCD display
12 hours/24 hours mode switching function
30 seconds adjustment function (a number less than 30 is rounded down to 00 seconds, and 30 seconds or
more are rounded up to 1 minute)
Automatic adjustment function for leap years
Binary count mode
Count seconds in 32 bits, binary display
Common to both modes
Start/stop function
The sub-second digit is displayed in binary units (1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, or 64 Hz).
Clock error correction function
Clock (1-Hz/64-Hz) output
Interrupts
Alarm interrupt (RTC_ALM)
As an alarm interrupt condition, selectable for comparison with the following:
Calendar count mode: Year, month, date, day-of-week, hour, minute, or second can be selected
Binary count mode: Each bit of the 32-bit binary counter
Periodic interrupt (RTC_PRD)
2 seconds, 1 second, 1/2 second, 1/4 second, 1/8 second, 1/16 second, 1/32 second, 1/64 second, 1/128
second, or 1/256 second can be selected as an interrupt period.
Carry interrupt (RTC_CUP)
An interrupt is generated at either of the following conditions:
- When a carry from the 64-Hz counter to the second counter is generated.
- When the 64-Hz counter is changed and the R64CNT register is read at the same time.
Recovery from Software Standby mode can be performed by an alarm interrupt or periodic interrupt
Event link function
Periodic event output (RTC_PRD)
Note 1. Satisfy the frequency of the peripheral module clock (PCLKB) the frequency of the count source clock.
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21. Realtime Clock (RTC)
Internal peripheral bus
Realtime clock (RTC)
Bus interface
RCR2
XCIN
Sub-clock
oscillator
XCOUT
32.768 kHz
To each
function
Prescaler
128-Hz generation
Time counter 1-Hz/64-Hz output
128 Hz
for XCIN
RADJ
R64CNT
RSECCNT/
BCNT0
RHRCNT/
BCNT2
RMINCNT/
BCNT1
RDAYCNT
RWKCNT/
BCNT3
RMONCNT
RYRCNT
RCR4
128Hz generation
LOCO
RFRH/
RFRL
Figure 21.1
RTC block diagram
Table 21.2
RTC pin configuration
Pin name
XCIN
I/O
RMINAR/
BCNT1AR
RWKAR/
BCNT3AR
RMONAR/
BCNT1AER
RYRAREN/
BCNT3AER
Alarm comparison
RCR1
RSECAR/BCNT0AR:
RMINAR/BCNT1AR:
RHRAR/BCNT2AR:
RWKAR/BCNT3AR:
RDAYAR/BCNT0AER:
RMONAR/BCNT1AER:
RYRAR/BCNT2AER:
RYRAREN/BCNT3AER:
RTC_ALM
RTC_PRD
RTC_CUP
Event signal output
(RTC_PRD)
Second alarm register/Binary counter 0 alarm register
Minute alarm register/Binary counter 1 alarm register
Hour alarm register/Binary counter 2 alarm register
Day-of-week alarm register/Binary counter 3 alarm register
Date alarm register/Binary counter 0 alarm enable register
Month alarm register/Binary counter 1 alarm enable register
Year alarm register/Binary counter 2 alarm enable register
Year alarm enable register/Binary counter 3 alarm enable register
Function
Input
XCOUT
Output
RTCOUT
Output
21.2
RSECAR/
BCNT0AR
RHRAR/
BCNT2AR
RDAYAR/
BCNT0AER
RYRAR
BCNT2AER
Interrupt control
for LOCO
R64CNT:
64-Hz counter
RSECCNT/BCNT0: Second counter/Binary counter 0
RMINCNT/BCNT1: Minute counter/Binary counter 1
RHRCNT/BCNT2: Hour counter/Binary counter 2
RWKCNT/BCNT3: Day-of-week counter/Binary counter 3
RDAYCNT:
Date counter
RMONCNT:
Month counter
RYRCNT:
Year counter
RCR1:
RTC control register 1
RCR2:
RTC control register 2
RCR4:
RTC control register 4
RADJ:
Time error adjustment register
RFRH/RFRL:
Frequency Register
RTCOUT
Alarm function
Connect a 32.768-kHz crystal to these pins
This pin is used to output a 1-Hz/64-Hz waveform
Register Descriptions
Write or read from the RTC registers in accordance with section 21.6.5, Notes when Writing to and Reading from
Registers.
If the value in an RTC register after a reset is given as x (undefined bits) in the list, it is not initialized by a reset. When
RTC enters the reset state or a low power state during counting operations, for example, while the RCR2.START bit is 1,
the year, month, day of the week, date, hours, minutes, seconds, and 64-Hz counters continue to operate.
Note:
A reset generated while writing to a register might destroy the register value. In addition, do not allow the chip to
enter Software Standby mode immediately after setting any of these registers. For details, see section 21.6.4,
Transitions to Low Power Modes after Setting Registers.
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21.2.1
21. Realtime Clock (RTC)
64-Hz Counter (R64CNT)
Address(es): RTC.R64CNT 4004 4000h
Value after reset:
b7
b6
b5
b4
b3
—
F1HZ
F2HZ
F4HZ
F8HZ
0
x
x
x
x
b2
b1
b0
F16HZ F32HZ F64HZ
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
F64HZ
64 Hz
Indicate the state between 1 Hz and 64 Hz of the sub-second digit R
b1
F32HZ
32 Hz
R
b2
F16HZ
16 Hz
R
b3
F8HZ
8 Hz
R
b4
F4HZ
4 Hz
R
b5
F2HZ
2 Hz
R
b6
F1HZ
1 Hz
R
b7
—
Reserved
This bit is read as 0
R
The R64CNT counter is used in both calendar count mode and binary count mode. The 64-Hz counter (R64CNT)
generates the period for a second by counting up periods of the 128-Hz clock. The state in the sub-second range can be
confirmed by reading this counter.
This counter is set to 00h by an RTC software reset or an execution of a 30-second adjustment. To read this counter,
follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
21.2.2
(1)
Second Counter (RSECCNT)/Binary Counter 0 (BCNT0)
In calendar count mode:
Address(es): RTC.RSECCNT 4004 4002h
b7
b6
—
x
Value after reset:
b5
b4
b3
SEC10[2:0]
x
x
b2
b1
b0
SEC1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
SEC1[3:0]
1-Second Count
Counts from 0 to 9 every second. When a carry is generated, 1 is
added to the tens place.
R/W
b6 to b4
SEC10[2:0]
10-Second Count
Counts from 0 to 5 for 60-second counting
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RSECCNT counter is used for setting and counting the BCD-coded second value. It counts carries generated once
per second in the 64-Hz counter.
The setting range is decimal 00 to 59. The RTC cannot operate normally if any other value is set. Before writing to this
register, be sure to stop the count operation using the START bit in RCR2.
To read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
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(2)
21. Realtime Clock (RTC)
In binary count mode:
Address(es): RTC.BCNT0 4004 4002h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[7:0]
x
Value after reset:
x
x
x
x
x: Undefined
The BCNT0 counter is a read/write 32-bit binary counter b7 to b0 that performs count operation by a carry generated for
each second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START bit
in RCR2. To read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
21.2.3
(1)
Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1)
In calendar count mode:
Address(es): RTC.RMINCNT 4004 4004h
b7
b6
—
x
Value after reset:
b5
b4
b3
MIN10[2:0]
x
x
b2
b1
b0
MIN1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MIN1[3:0]
1-Minute Count
Counts from 0 to 9 every minute. When a carry is generated, 1 is
added to the tens place.
R/W
b6 to b4
MIN10[2:0]
10-Minute Count
Counts from 0 to 5 for 60-minute counting
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RMINCNT counter is used for setting and counting the BCD-coded minute value. It counts carries generated once
per minute in the second counter.
A value from 00 through 59 (in BCD) can be specified. If a value outside this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
(2)
In binary count mode:
Address(es): RTC.BCNT1 4004 4004h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[15:8]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT1 counter is a read/write 32-bit binary counter b15 to b8 that performs count operation by a carry generated
for each second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START
bit in RCR2. To read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
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21.2.4
(1)
21. Realtime Clock (RTC)
Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2)
In calendar count mode:
Address(es): RTC.RHRCNT 4004 4006h
Value after reset:
b7
b6
b5
—
PM
HR10[1:0]
x
x
x
b4
x
b3
b2
b1
b0
HR1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
HR1[3:0]
1-Hour Count
Counts from 0 to 9 once per hour. When a carry is generated, 1 is
added to the tens place.
R/W
b5, b4
HR10[1:0]
10-Hour Count
Counts from 0 to 2 once per carry from the ones place
R/W
b6
PM
PM
Time Counter Setting for a.m./p.m:
0: a.m.
1: p.m.
R/W
b7
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
The RHRCNT counter is used for setting and counting the BCD-coded hour value. It counts carries generated once per
hour in the minute counter. The specifiable time differs according to the setting in the hours mode bit (RCR2.HR24):
When the RCR2.HR24 bit is 0 – from 00 to 11 (in BCD)
When the RCR2.HR24 bit is 1 – from 00 to 23 (in BCD).
If a value outside this range is specified, the RTC does not operate correctly. Before writing to this register, be sure to
stop the count operation using the START bit in RCR2. The PM bit is only enabled when the RCR2.HR24 bit is 0.
Otherwise, the setting in the PM bit has no effect. To read this counter, follow the procedure in section 21.3.5, Reading
64-Hz Counter and Time.
(2)
In binary count mode:
Address(es): RTC.BCNT2 4004 4006h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[23:16]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT2 counter is a read/write 32-bit binary counter b23 to b16 that performs count operation by a carry generated
for each second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START
bit in RCR2. To read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
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21.2.5
(1)
21. Realtime Clock (RTC)
Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3)
In calendar count mode:
Address(es): RTC.RWKCNT 4004 4008h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
x
x
x
x
x
b2
b1
b0
DAYW[2:0]
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b2 to b0
DAYW[2:0]
Day-of-Week Counting
b2
R/W
b7 to b3
—
Reserved
Set these bits to 0. They are read as the set value.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: Sunday
1: Monday
0: Tuesday
1: Wednesday
0: Thursday
1: Friday
0: Saturday
1: Setting prohibited.
R/W
The RWKCNT counter is used for setting and counting in the coded day-of-week value. It counts carries generated once
per day in the hour counter. A value from 0 through 6 can be specified. If a value outside of this range is specified, the
RTC does not operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in
RCR2. To read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
(2)
In binary count mode:
Address(es): RTC.BCNT3 4004 4008h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNT[31:24]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT3 counter is a read/write 32-bit binary counter b31 to b24 that performs count operation by a carry generated
for each second of the 64-Hz counter. Before writing to this register, be sure to stop the count operation using the START
bit in RCR2. To read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
21.2.6
Day Counter (RDAYCNT)
Address(es): RTC.RDAYCNT 4004 400Ah
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
DATE10[1:0]
x
x
b2
b1
b0
DATE1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DATE1[3:0]
1-Day Count
Counts from 0 to 9 once per day. When a carry is generated, 1 is
added to the tens place.
R/W
b5, b4
DATE10[1:0]
10-Day Count
Counts from 0 to 3 once per carry from the ones place
R/W
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21. Realtime Clock (RTC)
Bit
Symbol
Bit name
Description
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RDAYCNT counter is used in calendar count mode. RDAYCNT is used for setting and counting the BCD-coded
date value. It counts carries generated once per day in the hour counter. The count operation depends on the month and
whether the year is a leap year. Leap years are determined according to whether the year counter (RYRCNT) value is
divisible by 400, 100, and 4.
A value from 01 through 31 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. When specifying a value, the range of specifiable days depends on the month and whether the year is a
leap year. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To read this
counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
21.2.7
Month Counter (RMONCNT)
Address(es): RTC.RMONCNT 4004 400Ch
Value after reset:
b7
b6
b5
b4
—
—
—
MON10
0
0
0
x
b3
b2
b1
b0
MON1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MON1[3:0]
1-Month Count
Counts from 0 to 9 once per month. When a carry is generated, 1
is added to the tens place.
R/W
b4
MON10
10-Month Count
Counts from 0 to 1 once per carry from the ones place.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RMONCNT counter is used in calendar count mode. RMONCNT is used for setting and counting the BCD-coded
month value. It counts carries generated once per month in the date counter.
A value from 01 through 12 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
21.2.8
Year Counter (RYRCNT)
Address(es): RTC.RYRCNT 4004 400Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
YR10[3:0]
x
x
x
b2
b1
b0
YR1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
YR1[3:0]
1-Year Count
Counts from 0 to 9 once per year. When a carry is generated, 1 is
added to the tens place.
R/W
b7 to b4
YR10[3:0]
10-Year Count
Counts from 0 to 9 once per carry from ones place. When a carry
is generated in the tens place, 1 is added to the hundreds place.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RYRCNT counter is used in calendar count mode. RYRCNT is used for setting and counting the BCD-coded year
value. It counts carries generated once per year in the month counter.
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21. Realtime Clock (RTC)
A value from 00 through 99 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. Before writing to this register, be sure to stop the count operation using the START bit in RCR2. To
read this counter, follow the procedure in section 21.3.5, Reading 64-Hz Counter and Time.
21.2.9
(1)
Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register
(BCNT0AR)
In calendar count mode:
Address(es): RTC.RSECAR 4004 4010h
b7
b6
ENB
b4
b3
SEC10[2:0]
x
Value after reset:
b5
x
b2
b1
b0
SEC1[3:0]
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
SEC1[3:0]
1 Second
Value for the ones place of seconds
R/W
b6 to b4
SEC10[2:0]
10 Seconds
Value for the tens place of seconds
R/W
b7
ENB
ENB
0: The register value is not compared with the RSECCNT counter value
1: The register value is compared with the RSECCNT counter value.
R/W
RSECAR is an alarm register associated with the BCD-coded second counter RSECCNT. When the ENB bit is set to 1,
the RSECAR value is compared with the RSECCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RSECAR
values from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. This register is set to 00h by an RTC software reset.
(2)
In binary count mode:
Address(es): RTC.BCNT0AR 4004 4010h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[7:0]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT0AR counter is a read/write alarm register associated with the 32-bit binary counter b7 to b0. This register is
set to 00h by an RTC software reset.
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21.2.10
(1)
21. Realtime Clock (RTC)
Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR)
In calendar count mode:
Address(es): RTC.RMINAR 4004 4012h
b7
b6
ENB
x
Value after reset:
b5
b4
b3
MIN10[2:0]
x
b2
b1
b0
MIN1[3:0]
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MIN1[3:0]
1 Minute
Value for the ones place of minutes
R/W
b6 to b4
MIN10[2:0]
10 Minutes
Value for the tens place of minutes
R/W
b7
ENB
ENB
0: The register value is not compared with the RMINCNT counter value
1: The register value is compared with the RMINCNT counter value.
R/W
RMINAR is an alarm register associated with the BCD-coded minute counter RMINCNT. When the ENB bit is set to 1,
the RMINAR value is compared with the RMINCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RMINAR
values from 00 through 59 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. This register is set to 00h by an RTC software reset.
(2)
In binary count mode:
Address(es): RTC.BCNT1AR 4004 4012h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[15:8]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT1AR counter is a read/write alarm register associated with the 32-bit binary counter from b15 to b8. This
register is set to 00h by an RTC software reset.
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21.2.11
(1)
21. Realtime Clock (RTC)
Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register (BCNT2AR)
In calendar count mode:
Address(es): RTC.RHRAR 4004 4014h
b7
b6
b5
ENB
PM
HR10[1:0]
x
x
Value after reset:
b4
x
x
b3
b2
b1
b0
HR1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
HR1[3:0]
1 Hour
Value for the ones place of hours
R/W
b5, b4
HR10[1:0]
10 Hours
Value for the tens place of hours
R/W
b6
PM
PM
Time Alarm Setting for a.m./p.m:
0: a.m.
1: p.m.
R/W
b7
ENB
ENB
0: The register value is not compared with the RHRCNT counter value
1: The register value is compared with the RHRCNT counter value.
R/W
RHRAR is an alarm register associated with the BCD-coded hour counter RHRCNT. When the ENB bit is set to 1, the
RHRAR value is compared with the RHRCNT value. From the following alarm registers, only those selected with the
ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The specifiable
time differs according to the setting in the hours mode bit (RCR2.HR24):
When the RCR2.HR24 bit is 0 – From 00 to 11 (in BCD)
When the RCR2.HR24 bit is 1 – From 00 to 23 (in BCD).
If a value outside of this range is specified, the RTC does not operate correctly. When the RCR2.HR24 bit is 0, be sure to
set the PM bit. When the RCR2.HR24 bit is 1, the setting in the PM bit has no effect. This register is set to 00h by an
RTC software reset.
(2)
In binary count mode:
Address(es): RTC.BCNT2AR 4004 4014h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[23:16]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT2AR counter is a read/write alarm register associated with the 32-bit binary counter b23 to b16. This register
is set to 00h by an RTC software reset.
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21.2.12
(1)
21. Realtime Clock (RTC)
Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register
(BCNT3AR)
In calendar count mode:
Address(es): RTC.RWKAR 4004 4016h
b7
b6
b5
b4
b3
ENB
—
—
—
—
x
x
x
x
x
Value after reset:
b2
b1
b0
DAYW[2:0]
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b2 to b0
DAYW[2:0]
Day-of-Week Setting
b2
R/W
b6 to b3
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RWKCNT counter value
1: The register value is compared with the RWKCNT counter value.
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: Sunday
1: Monday
0: Tuesday
1: Wednesday
0: Thursday
1: Friday
0: Saturday
1: Setting prohibited.
RWKAR is an alarm register associated with the coded day-of-week counter RWKCNT. When the ENB bit is set to 1,
the RWKAR value is compared with the RWKCNT value. From the following alarm registers, only those selected with
the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values all match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RWKAR
values from 0 through 6 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate
correctly. This register is set to 00h by an RTC software reset.
(2)
In binary count mode:
Address(es): RTC.BCNT3AR 4004 4016h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
BCNTAR[31:24]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT3AR counter is a read/write alarm register associated with the 32-bit binary counter b31 to b24. This register
is set to 00h by an RTC software reset.
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21.2.13
(1)
21. Realtime Clock (RTC)
Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register
(BCNT0AER)
In calendar count mode:
Address(es): RTC.RDAYAR 4004 4018h
b7
b6
ENB
—
x
x
Value after reset:
b5
b4
b3
DATE10[1:0]
x
x
b2
b1
b0
DATE1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
DATE1[3:0]
1 Day
Value for the ones place of days
R/W
b5, b4
DATE10[1:0]
10 Days
Value for the tens place of days
R/W
b6
—
Reserved
Set this bit to 0. It is read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RDAYCNT counter value
1: The register value is compared with the RDAYCNT counter value.
R/W
RDAYAR is an alarm register associated with the BCD-coded date counter RDAYCNT. When the ENB bit is set to 1, the
RDAYAR value is compared with the RDAYCNT value. From the following alarm registers, only those selected with the
ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RDAYAR
values from 01 through 31 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. This register is set to 00h by an RTC software reset.
(2)
In binary count mode:
Address(es): RTC.BCNT0AER 4004 4018h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[7:0]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT0AER register is a read/write register for setting the alarm enable associated with the 32-bit binary counter b7
to b0. The binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary
alarm register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt becomes 1.
This register is set to 00h by an RTC software reset.
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21.2.14
(1)
21. Realtime Clock (RTC)
Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register
(BCNT1AER)
In calendar count mode:
Address(es): RTC.RMONAR 4004 401Ah
b7
b6
b5
b4
ENB
—
—
MON10
x
x
x
x
Value after reset:
b3
b2
b1
b0
MON1[3:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
MON1[3:0]
1 Month
Value for the ones place of months
R/W
b4
MON10
10 Months
Value for the tens place of months
R/W
b6, b5
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RMONCNT counter value
1: The register value is compared with the RMONCNT counter value.
R/W
RMONAR is an alarm register associated with the BCD-coded month counter RMONCNT. When the ENB bit is set to 1,
the RMONAR value is compared with the RMONCNT value. From the following alarm registers, only those selected
with the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RMONAR
values from 01 through 12 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not
operate correctly. This register is set to 00h by an RTC software reset.
(2)
In binary count mode:
Address(es): RTC.BCNT1AER 4004 401Ah
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[15:8]
Value after reset:
x
x
x
x
x
x: Undefined
The BCNT1AER register is a read/write register for setting the alarm enable associated with the 32-bit binary counter
b15 to b8. The binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the
binary alarm register (BCNTAR[31:0]), and when all match, the IR flag associated with to the RTC_ALM interrupt
becomes 1. This register is set to 00h by an RTC software reset.
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21.2.15
(1)
21. Realtime Clock (RTC)
Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register
(BCNT2AER)
In calendar count mode:
Address(es): RTC.RYRAR 4004 401Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
YR10[3:0]
x
x
x
b2
b1
b0
YR1[3:0]
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b3 to b0
YR1[3:0]
1 Year
Value for the ones place of years
R/W
b7 to b4
YR10[3:0]
10 Years
Value for the tens place of years
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
RYRAR is an alarm register associated with the BCD-coded year counter RYRCNT. The RYRAR values from 00
through 99 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate correctly.
This register is set to 0000h by an RTC software reset.
(2)
In binary count mode:
Address(es): RTC.BCNT2AER 4004 401Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[23:16]
x
x
x
x
x
x: Undefined
The BCNT2AER register is a read/write register for setting the alarm enable associated with the 32-bit binary counter
b23 to b16. The binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the
binary alarm register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt
becomes 1. This register is set to 0000h by an RTC software reset.
21.2.16
(1)
Year Alarm Enable Register (RYRAREN)/
Binary Counter 3 Alarm Enable Register (BCNT3AER)
In calendar count mode:
Address(es): RTC.RYRAREN 4004 401Eh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
ENB
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
Set these bits to 0. They are read as the set value.
R/W
b7
ENB
ENB
0: The register value is not compared with the RYRCNT counter value
1: The register value is compared with the RYRCNT counter value.
R/W
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21. Realtime Clock (RTC)
When the ENB bit in RYRAREN is set to 1, the RYRAR value is compared with the RYRCNT value. From the
following alarm registers, only those selected with the ENB bits set to 1 are compared with the associated counters:
RSECAR
RMINAR
RHRAR
RWKAR
RDAYAR
RMONAR
RYRAREN.
When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1.This register is set to
00h by an RTC software reset.
(2)
In binary count mode:
Address(es): RTC.BCNT3AER 4004 401Eh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
ENB[31:24]
x
Value after reset:
x
x
x
x
x: Undefined
The BCNT3AER register is a read/write register for setting the alarm enable associated with the 32-bit binary counter
b31 to b24. The binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the
binary alarm register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt
becomes 1. This register is set to 00h by an RTC software reset.
21.2.17
RTC Control Register 1 (RCR1)
Address(es): RTC.RCR1 4004 4022h
b7
b6
b5
b4
PES[3:0]
x
Value after reset:
x
x
b3
b2
b1
b0
RTCOS
PIE
CIE
AIE
0
x
0
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
AIE
Alarm Interrupt Enable
0: An alarm interrupt request is disabled
1: An alarm interrupt request is enabled.
R/W
b1
CIE
Carry Interrupt Enable
0: A carry interrupt request is disabled
1: A carry interrupt request is enabled.
R/W
b2
PIE
Periodic Interrupt Enable
0: A periodic interrupt request is disabled
1: A periodic interrupt request is enabled.
R/W
b3
RTCOS
RTCOUT Output Select
0: RTCOUT outputs 1 Hz
1: RTCOUT outputs 64 Hz.
R/W
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21. Realtime Clock (RTC)
Bit
Symbol
Bit name
Description
R/W
b7 to b4
PES[3:0]
Periodic Interrupt Select
b7
R/W
b4
0 1 1 0: A periodic interrupt is generated every 1/256 second*1
0 1 1 1: A periodic interrupt is generated every 1/128 second
1 0 0 0: A periodic interrupt is generated every 1/64 second
1 0 0 1: A periodic interrupt is generated every 1/32 second
1 0 1 0: A periodic interrupt is generated every 1/16 second
1 0 1 1: A periodic interrupt is generated every 1/8 second
1 1 0 0: A periodic interrupt is generated every 1/4 second
1 1 0 1: A periodic interrupt is generated every 1/2 second
1 1 1 0: A periodic interrupt is generated every 1 second
1 1 1 1: A periodic interrupt is generated every 2 seconds.
No periodic interrupts are generated for other settings.
Note 1. When LOCO is selected (RCR4.RCKSEL = 1) while PES[3:0] = 0110b, a periodic interrupt is generated every 1/
128 second.
The RCR1 register is used in both calendar count mode and binary count mode. Bits AIE, PIE, and PES[3:0] are updated
synchronously with the count source. When the RCR1 register is modified, check that all the bits are updated before
proceeding.
AIE bit (Alarm Interrupt Enable)
This bit enables or disables alarm interrupt requests.
CIE bit (Carry Interrupt Enable)
This bit enables and disables interrupt requests when a carry to the RSECCNT/BCNT0 register occurs, or when a carry
to the 64-Hz counter (R64CNT) occurs while reading the 64-Hz counter.
PIE bit (Periodic Interrupt Enable)
This bit enables or disabled a periodic interrupt.
RTCOS bit (RTCOUT Output Select)
This bit selects the RTCOUT output period. The RTCOS bit must be rewritten while the count operation stops (the
RCR2.START bit is 0) and the RTCOUT output is disabled (the RCR2.RTCOE bit is 0). When the RTCOUT is output to
an external pin, the RCR2.RTCOE bit must be enabled. For details on controlling I/O ports, see section 16.5.1, Procedure
for Specifying Pin Function.
PES[3:0] bits (Periodic Interrupt Select)
These bits specify the period of the periodic interrupt. A periodic interrupt is generated with the period specified by these
bits.
21.2.18
(1)
RTC Control Register 2 (RCR2)
In calendar count mode:
Address(es): RTC.RCR2 4004 4024h
b7
CNTM
D
Value after reset:
x
b6
b5
b4
b3
b2
b1
b0
HR24 AADJP AADJE RTCOE ADJ30 RESET START
x
x
x
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
START
Start
0: Prescaler and time counter are stopped
1: Prescaler and time counter operate normally.
R/W
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21. Realtime Clock (RTC)
Bit
Symbol
Bit name
Description
R/W
b1
RESET
RTC Software Reset
In writing:
0: Writing is invalid
1: The prescaler and the target registers for RTC software
reset *1 are initialized.
In reading:
0: In normal time operation, or an RTC software reset has
completed
1: During an RTC software reset.
R/W
b2
ADJ30
30-Second Adjustment
In writing:
0: Writing is invalid
1: 30-second adjustment is executed.
In reading:
0: In normal time operation, or 30-second adjustment has
completed
1: During 30-second adjustment.
R/W
b3
RTCOE
RTCOUT Output Enable
0: RTCOUT output disabled
1: RTCOUT output enabled.
R/W
b4
AADJE
Automatic Adjustment Enable *2
0: Automatic adjustment is disabled
1: Automatic adjustment is enabled.
R/W
b5
AADJP
Automatic Adjustment Period
Select *2
0: The RADJ.ADJ[5:0] setting value is adjusted from the count
value of the prescaler every minute
1: The RADJ.ADJ[5:0] setting value is adjusted from the count
value of the prescaler every 10 seconds.
R/W
b6
HR24
Hours Mode
0: The RTC operates in 12-hour mode
1: The RTC operates in 24-hour mode.
R/W
b7
CNTMD
Count Mode Select
0: Calendar count mode
1: Binary count mode.
R/W
Note 1. R64CNT, RSECAR/BCNT0AR, RMINAR/BCNT1AR, RHRAR/BCNT2AR, RWKAR/BCNT3AR, RDAYAR/
BCNT0AER, RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RCR2.ADJ30,
RCR2.AADJE, RCR2.AADJP.
Note 2. When LOCO is selected, the setting of this bit is disabled.
The RCR2 register is related to hours mode, automatic adjustment function, enabling of RTCOUT output, 30-second
adjustment, RTC software reset, and controlling count operation.
START bit (Start)
This bit stops or restarts the prescaler or time counter operation.
The START bit is updated in synchronization with the next cycle of the count source. When the START bit is modified,
check that the bit is updated before proceeding.
RESET bit (RTC Software Reset)
This bit initializes the prescaler and registers to be reset by RTC software.
When 1 is written to the RESET bit, initialization starts in synchronization with the count source. When the initialization
completes, the RESET bit is automatically set to 0. Check that this bit is set to 0 before proceeding.
ADJ30 bit (30-Second Adjustment)
This bit is for the 30-second adjustment.
When 1 is written to the ADJ30 bit, the RSECCNT value of 30 seconds or less is rounded down to 00 second and the
value of 30 seconds or more is rounded up to 1 minute.
The 30-second adjustment is performed in synchronization with the count source. When 1 is written to this bit, the
ADJ30 bit is automatically set to 0 after the 30-second adjustment completes. If 1 is written to the ADJ30 bit, check that
the bit is set to 0 before proceeding. When the 30-second adjustment is performed, the prescaler and R64CNT are also
reset. The ADJ30 bit is set to 0 by an RTC software reset.
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21. Realtime Clock (RTC)
RTCOE bit (RTCOUT Output Enable)
This bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin.
Use the START bit to stop counting before changing the value of the RTCOE bit. Do not stop counting (write 0 to the
START bit) and change the value of the RTCOE bit at the same time.
When RTCOUT is to be output from an external pin, enable the RTCOE bit and set up the port control for the pin.
AADJE bit (Automatic Adjustment Enable)
This bit controls (enables or disables) automatic adjustment.
Set the plus–minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJE bit.
The AADJE bit is set to 0 by an RTC software reset.
AADJP bit (Automatic Adjustment Period Select)
This bit selects the automatic-adjustment period.
Set the plus–minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJP bit.
The AADJP bit is set to 0 by an RTC software reset.
HR24 bit (Hours Mode)
This bit specifies whether the RTC operates in 12- or 24-hour mode.
Use the START bit to stop counting before changing the value of the HR24 bit. Do not stop counting (write 0 to the
START bit) and change the value of the HR24 bit at the same time.
CNTMD bit (Count Mode Select)
This bit specifies whether the RTC count mode operates in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings. This bit is updated
synchronously with the count source, and its value is fixed before the RTC software reset is complete.
For details on initial settings, see section 21.3.1, Outline of Initial Settings of Registers after Power On.
(2)
In binary count mode:
Address(es): RTC.RCR2 4004 4024h
Value after reset:
b7
b6
CNTM
D
—
x
x
b5
b4
b3
AADJP AADJE RTCOE
x
x
0
b2
—
0
b1
b0
RESET START
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
START
Start
0: The 32-bit binary counter, 64-Hz counter, and prescaler are
stopped
1: The 32-bit binary counter, 64-Hz counter, and prescaler are
in normal operation.
R/W
b1
RESET
RTC Software Reset
In writing:
0: Writing is invalid
1: The prescaler and the target registers for RTC software
reset*1 are initialized.
In reading:
0: In normal time operation, or an RTC software reset has
completed
1: During an RTC software reset.
R/W
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21. Realtime Clock (RTC)
Bit
Symbol
Bit name
Description
R/W
b2
—
b3
RTCOE
Reserved
This bit is read as 0. The write value should be 0.
R/W
RTCOUT Output Enable
0: RTCOUT output disabled
1: RTCOUT output enabled.
R/W
b4
AADJE
Automatic Adjustment Enable *2
0: Automatic adjustment is disabled
1: Automatic adjustment is enabled.
R/W
b5
AADJP
Automatic Adjustment Period
Select *2
0: Adds or subtracts the RADJ.ADJ[5:0] bits from the
prescaler count value every 32 seconds
1: Adds or subtracts the RADJ.ADJ[5:0] bits from the
prescaler count value every 8 seconds.
R/W
b6
—
Reserved
This bit is undefined. The write value should be 0.
R/W
b7
CNTMD
Count Mode Select
0: The calendar count mode
1: The binary count mode.
R/W
Note 1. R64CNT, RSECAR/BCNT0AR, RMINAR/BCNT1AR, RHRAR/BCNT2AR, RWKAR/BCNT3AR, RDAYAR/
BCNT0AER, RMONAR/BCNT1AER, RYRAR/BCNT2AER, RYRAREN/BCNT3AER, RADJ, RCR2.ADJ30,
RCR2.AADJE, RCR2.AADJP
Note 2. When LOCO is selected, the setting of this bit is disabled.
START bit (Start)
This bit stops or restarts the prescaler or counter (clock) operation.
The START bit is updated in synchronization with the count source. When the START bit is modified, check that the bit
is updated before proceeding.
RESET bit (RTC Software Reset)
This bit initializes the prescaler and registers to be reset by RTC software.
When 1 is written to the RESET bit, initialization starts in synchronization with the count source. When the initialization
completes, the RESET bit is automatically set to 0. When 1 is written to the RESET bit, check that the bit is set to 0
before proceeding.
RTCOE bit (RTCOUT Output Enable)
This bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin.
Use the START bit to stop counting before changing the value of the RTCOE bit. Do not stop counting (write 0 to the
START bit) and change the value of the RTCOE bit at the same time. When an RTCOUT signal is to be output from an
external pin, enable the port control in addition to setting this bit.
AADJE bit (Automatic Adjustment Enable)
This bit controls (enables or disables) automatic adjustment.
Set the plus–minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJE bit. The AADJE bit is set to 0 by an RTC software reset.
AADJP bit (Automatic Adjustment Period Select)
This bit selects the automatic-adjustment period.
Correction period can be selected from 32 second units or 8 second units in binary count mode.
Set the plus–minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the
AADJP bit. The AADJP bit is set to 0 by an RTC software reset.
CNTMD bit (Count Mode Select)
This bit specifies whether the RTC count mode operates in calendar count mode or in binary count mode.
When setting the count mode, execute an RTC software reset and start again from the initial settings. This bit is updated
synchronously with the count source, and its value is fixed before the RTC software reset is complete.
For details on initial settings, see section 21.3.1, Outline of Initial Settings of Registers after Power On.
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21.2.19
21. Realtime Clock (RTC)
RTC Control Register 4 (RCR4)
Address(es): RTC.RCR4 4004 4028h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
RCKSE
L
0
0
0
0
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RCKSEL
Count Source Select
0: Sub-clock oscillator is selected
1: LOCO is selected.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The RCR4 register is used for selecting the count source. This function is used in both calendar count mode and binary
count mode. When the RCKSEL bit is set to 0, the time is counted with the sub-clock oscillator. When the bit is set to 1,
the time is counted with LOCO.
RCKSEL bit (Count Source Select)
This bit selects the count source from the sub-clock oscillator and LOCO.
The count source must be selected only once before making the initial settings of the RTC registers at power on.
21.2.20
Frequency Register (RFRH/RFRL)
Address(es): RTC.RFRH 4004 402Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RFC16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b0
RFC16
Reserved
Write 0 before writing to the RFRL register after a cold start
R/W
b15 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Address(es): RTC.RFRL 4004 402Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
RFC[15:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b15 to b0
RFC[15:0]
Frequency Comparison Value
Write 00FFh to this register when using the LOCO.
R/W
RFRL is a register for controlling the prescaler when LOCO is selected.
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21. Realtime Clock (RTC)
The RTC time counter operates on a 128-Hz clock signal as the base clock. Therefore, when LOCO is selected, LOCO is
divided by the prescaler to generate a 128-Hz clock signal. Set the frequency comparison value in the RFC[15:0] bits to
generate a 128-Hz clock from the LOCO frequency. Before first writing to RFC[15:0] after cold start, write 0000h to the
RFRH.
A value from 0007h through 01FFh can be specified as the frequency comparison value. If a value outside of this range
is specified, the RTC does not operate correctly. Before writing to this register, be sure to stop the count operation
through the setting of the START bit in RCR2. The operating frequency of the peripheral module clock and the LOCO
should be such that the peripheral module clock >= LOCO.
Calculation method of frequency comparison value:
RFC[15:0] = (LOCO clock frequency) / 128 - 1
When the LOCO frequency is 32.768 kHz, the RFRL register must be set to 00FFh.
21.2.21
Time Error Adjustment Register (RADJ)
Address(es): RTC.RADJ 4004 402Eh
b7
b6
b5
b4
PMADJ[1:0]
Value after reset:
x
x
b3
b2
b1
b0
x
x
ADJ[5:0]
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b5 to b0
ADJ[5:0]
Adjustment Value
These bits specify the adjustment value from the prescaler.
R/W
b7, b6
PMADJ[1:0]
Plus–Minus
b7 b6
R/W
0
0
1
1
0: Adjustment is not performed
1: Adjustment is performed by the addition to the prescaler
0: Adjustment is performed by the subtraction from the prescaler
1: Setting prohibited.
Adjustment is performed by the addition to or subtraction from the prescaler. If the automatic adjustment enable
(RCR2.AADJE) bit is 0, adjustment is performed when writing to the RADJ. If the RCR2.AADJE bit is 1, adjustment is
performed in the interval specified by the automatic adjustment period select (RCR2.AADJP) bit.
The current adjustment by software (disabling automatic adjustment) might be invalid if the subsequent adjustment value
is specified within 320 cycles of the count source after the register setting. To perform adjustment consecutively, wait for
320 cycles or more of the count source after the register setting, then specify the next adjustment value.
RADJ is updated in synchronization with the count source. When RADJ is modified, check that all the bits are updated
before continuing with further processing. This register is set to 00h by an RTC software reset. The setting of this register
is enabled only when the sub-clock oscillator is selected. When LOCO is selected, adjustment is not performed.
ADJ[5:0] bits (Adjustment Value)
These bits specify the adjustment value (the number of sub-clock cycles) from the prescaler.
PMADJ[1:0] bits (Plus–Minus)
These bits select whether the clock is set ahead or back depending on the error-adjustment value set in the ADJ[5:0] bits.
21.3
21.3.1
Operation
Outline of Initial Settings of Registers after Power On
On power on, process the initial settings for the clock setting, count mode setting, time error adjustment, time setting,
alarm, and interrupt control register.
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21. Realtime Clock (RTC)
Power on
Clock and count mode settings
Clock supply setting and count mode setting
Set the time
Time setting in the clock counter and initial
setting of the time error adjustment register
Initial setting of the alarm register
Set the alarm
Initial setting of the interrupt control register
Set the interrupt
Figure 21.2
21.3.2
Outline of initial settings after a power on
Clock and Count Mode Setting Procedure
Figure 21.3 shows how to set the clock and the count mode.
Select the count source
RCR4.RCKSEL bit setting
Supply 6 clocks of the count source
Supply 6 clocks of the clock selected by the
RCR4.RCKSEL bit
Set the START bit to 0
No
START = 0
Wait for the RCR2.START bit to become 0
Yes
No (LOCO)
RCKSEL = 0
Set frequency register
Yes (Sub-clock)
Select count mode
Execute RTC software reset
No
RESET = 0
RCR2.CNTMD bit setting*1
Write 1 to the RCR2.RESET bit
Wait for the RCR2.RESET bit to become 0
Yes
Note 1. This step is not necessary if the count mode is set concurrently with setting the START bit to 0.
Figure 21.3
21.3.3
Clock and count mode setting procedure
Setting the Time
Figure 21.4 shows how to set the time.
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Set the START bit to 0
No
Write 0 to the RCR2.START bit
Wait for the RCR2.START bit to become 0
START = 0
Yes
Write 1 to the RCR2.RESET bit*1
Execute an RTC software reset
No
Wait for the RCR2.RESET bit to become 0
RESET = 0
Yes
Set the year, month, day of the week,
date, hour, minute, and second/binary
counters 3 to 0
Settings in arbitrary order is possible
No (LOCO)
RCKSEL = 0
Yes (Sub-clock)
Set clock error
adjustment values
Set clock error adjustment values
Set the START bit to 1
No
Write 1 to the RCR2.START bit
Wait for the RCR2.START bit to become 1
START = 1
Yes
Note 1. This step is not required for the time-setting procedure because an RTC software reset is executed in
the clock setting procedure of the initial settings for the power supply.
Figure 21.4
21.3.4
Setting the time
30-Second Adjustment
Figure 21.5 shows how to execute a 30-second adjustment.
Clock is in operation
Set the RCR2.ADJ30 bit to 1
No
ADJ30 = 0
Execute 30-second adjustment while the clock is in operation
(the RCR2.START bit is 1)
Write 1 to the RCR2.ADJ30 bit
Wait for the RCR2.ADJ30 bit to become 0
Yes
Figure 21.5
30-second adjustment
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21.3.5
21. Realtime Clock (RTC)
Reading 64-Hz Counter and Time
Figure 21.6 shows how to read a 64-Hz counter and time.
(a) To read the time without using interrupt
Disable the NVIC carry interrupt request
Write 1 to the Interrupt Clear-Enable Register
corresponding to the RTC_CUP interrupt
Enable the RTC carry interrupt request
Write 1 to the RCR1.CIE bit
Clear the interrupt flag
Write 0 to the IELSRn.IR bit and write 1 to the
Interrupt Clear-Pending Register
corresponding to the RTC_CUP interrupt
Read the counter
Yes
Pending status = 1?
Read the counter again when the Interrupt
Set-pending Register corresponding to the
RTC_CUP interrupt is 1
No
(b) To read the time using interrupts
Clear the interrupt flag
Enable the NVIC carry interrupt request
Enable the RTC carry interrupt request
Clear the interrupt flag
Write 0 to the IELSRn.IR bit and write
1 to the Interrupt Clear-Pending
Register corresponding to the
RTC_CUP interrupt
Write 1 to the Interrupt Set-Enable Register
corresponding to the RTC_CUP interrupt
Write 1 to the RCR1.CIE bit
Write 0 to the IELSRn.IR bit and write 1
to the Interrupt Clear-Pending Register
corresponding to the RTC_CUP interrupt
Read the counter
Yes
Interrupt?
No
Disable the RTC carry interrupt
Write 0 to the RCR1.CIE bit*1
Note 1. Disable interrupts if necessary.
Figure 21.6
Reading time
If a carry occurs while the 64-Hz counter and time are read, the correct time is not obtained, therefore they must be read
again. The procedure for reading the time without using interrupts is shown in (a) in Figure 21.6, and the procedure using
carry interrupts is shown in (b). To keep the program simple, method (a) should be used in most cases.
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21.3.6
21. Realtime Clock (RTC)
Alarm Function
Figure 21.7 shows how to use the alarm function.
Disable the NVIC alarm interrupt request
Set alarm time
Enable the RTC alarm interrupt request
Wait for the completion of the alarm time
setting
Clear the interrupt flag
Enable the NVIC alarm interrupt request
Monitor alarm time
(wait for interrupt or check alarm flag)
Figure 21.7
Write 1 to the Interrupt Clear-Enable Register
corresponding to the RTC_ALM interrupt
Set alarm enable at the same time as or after the
alarm time setting
Write 1 to the RCR1.AIE bit
Wait for 200 µs or more
Write 0 to the IELSRn.IR bit and write 1 to the Interrupt
Clear-Pending Register corresponding to the RTC_ALM
interrupt, since the flag may have been set while the alarm
time was being set
Write 1 to the Interrupt Set-Enable Register
corresponding to the RTC_ALM interrupt
Wait for alarm interrupt or the Interrupt Active Bit
Register corresponding to the RTC_ALM interrupt to
become 1
Using the alarm function
In calendar count mode, an alarm can be generated by any one of year, month, date, day-of-week, hour, minute or second,
or any combination of those. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm
time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting.
In binary count mode, an alarm can be generated in any bit combination of 32 bits. Write 1 to the ENB bit of the alarm
enable register associated with the target bit of the alarm, and set the alarm time in the alarm register. For bits that are not
the target of the alarm, write 0 to the ENB bit of the alarm enable register.
When the counter and the alarm time match, the IELSRn.IR bit and Interrupt Set-Pending/Clear-Pending Register
associated with the RTC_ALM interrupt are set to 1. Alarm detection can be confirmed by reading the Interrupt SetPending Register associated with the RTC_ALM interrupt, but an interrupt should be used in most cases. If 1 is set in the
Interrupt Set-Enable Register and Interrupt Active Bit Register associated with the RTC_ALM interrupt, an alarm
interrupt is generated in the event of the alarm, enabling the alarm to be detected.
Writing 0 sets the IELSRn.IR bit associated with the RTC_ALM interrupt to 0. If interrupt is enabled, the Interrupt SetPending/Clear-Pending Register and Interrupt Active Bit Register associated with the RTC_ALM interrupt are cleared
automatically after exiting the interrupt handler. Otherwise, write 1 to the Interrupt Clear-Pending Register associated
with the RTC_ALM interrupt to clear it.
When the counter and the alarm time match in a low power state, the MCU returns from the low power state.
21.3.7
Procedure for Disabling Alarm Interrupt
Figure 21.8 shows the procedure for disabling an enabled alarm interrupt request.
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21. Realtime Clock (RTC)
Enable the alarm interrupt
The RCR1.AIE bit register has been set to 1
Disable the alarm interrupt request of
the NVIC
Write 0 to the Interrupt Clear-Enable Register
corresponding to the RTC_ALM interrupt
Disable the alarm interrupt request of
the RTC
Write 0 to the RCR1.AIE bit
No
AIE bit = 0
Wait for the RCR1.AIE bit to be cleared to 0
Yes
Clear the interrupt flag
Figure 21.8
21.3.8
Write 0 to the IELSRn.IR bit and write 1 to the
Interrupt Clear-Pending Register corresponding to
the RTC_ALM interrupt because the flag might have
been set before the RCR1.AIE bit becomes 0
Procedure for disabling alarm interrupt request
Time Error Adjustment Function
The time error adjustment function is used to correct errors (running fast or slow) in the time due to variation in the
precision of oscillation by the sub-clock oscillator. Because 32,768 cycles of the sub-clock oscillator constitute 1 second
of operation when the sub-clock oscillator is selected, the clock runs fast if the sub-clock frequency is high and slow if
the sub-clock frequency is low.
There are two types of time error adjustment functions:
Automatic adjustment
Adjustment by software.
Use the RCR2.AADJE bit to select automatic adjustment or adjustment by software.
21.3.8.1
Automatic adjustment
Enable automatic adjustment by setting the RCR2.AADJE bit to 1. Automatic adjustment is the addition or subtraction of
the value counted by the prescaler to or from the value in the RADJ register every time the adjustment period selected by
the RCR2.AADJP bit elapses.
(1)
Example 1 sub-clock oscillator running at 32.769 kHz
(a)
Adjustment procedure
When the sub-clock oscillator is running at 32.769 kHz, 1 second elapses in every 32,769 clock cycles. The RTC is
meant to run at 32,768 clock cycles, so the clock runs fast by 1 clock cycle every second. The time on the clock is fast by
60 clock cycles per minute, so adjustment can take the form of setting the clock back by 60 cycles every minute.
Register settings when RCR2.CNTMD = 0:
RCR2.AADJP = 0 (adjustment every minute)
RADJ.PMADJ[1:0] = 10b (adjustment is performed by the subtraction from the prescaler)
RADJ.ADJ[5:0] = 60 (3Ch).
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Example 2 sub-clock oscillator running at 32.766 kHz
(a)
Adjustment procedure
21. Realtime Clock (RTC)
When the sub-clock oscillator runs at 32.766 kHz, 1 second elapses in every 32,766 clock cycles. The RTC is meant to
run at 32,768 clock cycles, so the clock runs slow by 2 clock cycles every second. The time on the clock is slow by 20
clock cycles every 10 seconds, so adjustment can take the form of setting the clock forward by 20 cycles every 10
seconds.
Register settings when RCR2.CNTMD is 0 (calendar count mode):
RCR2.AADJP = 1 (adjustment every 10 seconds)
RADJ.PMADJ[1:0] = 01b (adjustment is performed by the addition to the prescaler)
RADJ.ADJ[5:0] = 20 (14h).
(3)
Example 3 sub-clock oscillator running at 32.764 kHz
(a)
Adjustment procedure
At 32.764 kHz, 1 second elapses on 32,764 clock cycles. Because the RTC operates for 32,768 clock cycles as 1 second,
the clock is delayed for 4 clock cycles per second. In 8 seconds, the delay is 32 clock cycles, therefore correction can be
made by setting the clock for 32 clock cycles every 8 seconds.
Register settings when the RCR2.CNTMD bit is 1 (binary count mode):
RCR2.AADJP = 1 (adjustment every 8 seconds)
RADJ.PMADJ[1:0] = 01b (adjustment is performed by the addition to the prescaler)
RADJ.ADJ[5:0] = 32 (20h).
21.3.8.2
Adjustment by software
Enable adjustment by software by setting the RCR2.AADJE bit to 0. Adjustment by software is the addition or
subtraction of the value counted by the prescaler to or from the value in the RADJ register at the time of execution of a
write instruction to the RADJ register.
(1)
Example 1 sub-clock oscillator running at 32.769 kHz
(a)
Adjustment procedure
When the sub-clock oscillator is running at 32.769 kHz, 1 second elapses every 32,769 clock cycles. The RTC is meant
to run at 32,768 clock cycles, so the clock runs fast by 1 clock cycle every second. The time on the clock is fast by 1
clock cycle per second, so adjustment can take the form of setting the clock back by 1 cycle every second.
(b)
Register settings
RADJ.PMADJ[1:0] = 10b (adjustment is performed by the subtraction from the prescaler)
RADJ.ADJ[5:0] = 1 (01h)
This is written to the RADJ register once per 1-second interrupt.
21.3.8.3
Procedure to change the mode of adjustment
When changing the mode of adjustment, change the value of the AADJE bit in RCR2 after setting the
RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
To change adjustment by software to automatic adjustment:
1. Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
2. Set the RCR2.AADJE bit to 1 (automatic adjustment is enabled).
3. Use the RCR2.AADJP bit to select the period of adjustment.
4. In RADJ, set the PMADJ[1:0] bits for addition or subtraction and the ADJ[5:0] bits to the value for use in time error
adjustment.
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21. Realtime Clock (RTC)
To change automatic adjustment to adjustment by software:
1. Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
2. Set the RCR2.AADJE bit to 0 (adjustment by software is enabled).
3. Proceed with the adjustment by setting the RADJ.PMADJ[1:0] bits for addition or subtraction and the
RADJ.ADJ[5:0] bits to the value for use in time error adjustment at the desired time. After that, the time is adjusted
every time a value is written to the RADJ register.
21.3.8.4
Procedure to stop adjustment
Stop the adjustment by setting the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
21.4
Interrupt Sources
The RTC has three interrupt sources and are listed in Table 21.3.
Table 21.3
RTC interrupt sources
Name
Interrupt sources
RTC_ALM
Alarm interrupt
RTC_PRD
Periodic interrupt
RTC_CUP
Carry interrupt
(1)
Alarm interrupt (RTC_ALM)
This interrupt is generated based on the comparison result between the alarm registers and RTC counters. For details, see
section 21.3.6, Alarm Function.
Because there is a possibility that the interrupt flag might be set to 1 when the settings of the alarm registers match the
clock counters, wait for the alarm time settings to be confirmed. Clear the IELSRn.IR bit and the Interrupt Set-Pending
Register associated with the RTC_ALM interrupt to 0 again after modifying values of the alarm registers. After the
interrupt flag for the alarm interrupt is set to 1 and the state is returned to mismatching of the alarm registers and clock
counters, the flag does not set again until there is another match or the values of the alarm registers are modified again.
Sequence for setting the alarm
Alarm-register settings
in progress
Wait until the alarm
time setting is
confirmed
Alarm registers
Clock counters
Interrupt flag
(the IELSRn.IR bit and the
Interrupt Set-Pending
Register corresponding to
the RTC_ALM interrupt *1)
Match while settings are being made
Flag clearing by
software
Alarm interrupt
accepted
Note 1. See the Interrupt Controller Unit section for details on the corresponding interrupt vector number .
Figure 21.9
(2)
Timing of the alarm interrupt (RTC_ALM)
Periodic interrupt (RTC_PRD)
This interrupt is generated at intervals of 2 seconds, 1 second, 1/2 second, 1/4 second, 1/8 second, 1/16 second, 1/32
second, 1/64 second, 1/128 second, or 1/256 second. The interrupt interval can be selected through the RCR1.PES[3:0]
bits.
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(3)
21. Realtime Clock (RTC)
Carry interrupt (RTC_CUP)
This interrupt is generated when a carry to the second counter/binary counter 0 occurred or a carry to the R64CNT
counter occurred during read access to the 64-Hz counter.
R64CNT
signal
64 Hz
Interrupt generated by the simultaneous
occurrence of the selected edge of the
64-Hz signal and register reading
1 Hz
An interrupt is generated by a
carry to the second counter/
binary counter 0
Interrupt
Detail
Rising edges of the R64CNT signals
are detected in the same way
64-Hz signal in R64CNT
Interrupt generated by the simultaneous occurrence of
the edge of the 64-Hz signal and reading of R64CNT
Detection of the selected edge of
the 64-Hz signal
Register reading by the CPU
R64CNT
Interrupt flag
(the IELSRn.IR bit and Interrupt
Set-Pending Register
corresponding to the RTC_CUP
interrupt)
Figure 21.10
21.5
Timing of the carry interrupt (RTC_CUP)
Event Link Output
The RTC generates periodic event output (RTC_PRD) event signal for the ELC that can be used to initiate operations by
other modules selected in advance.
The periodic event signal is output at the interval selected from 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2, 1, and 2
seconds by setting the RCR1.PES[3:0] bits.
The event generation period immediately after the event generation is selected, is not guaranteed.
Note:
21.5.1
If event linking from the RTC is used, only set the ELC after setting the RTC, for example, initialization and time
settings. Setting the RTC after the ELC can lead to output of unexpected event signals.
Interrupt Handling and Event Linking
The RTC has a bit to enable or disable periodic interrupts. An interrupt request signal is output for the CPU when an
interrupt source is generated while the associated enable bit is enabled.
In contrast, an event link output signal is sent to other modules as an event signal through the ELC when an interrupt
source is generated, regardless of the setting of the associated interrupt enable bit.
Note:
21.6
21.6.1
Although alarm and periodic interrupts can still be output during Software Standby mode, the periodic event
signals for the ELC are not output.
Usage Notes
Register Writing during Counting
The following registers must not be written to during counting, that is, while the RCR2.START bit = 1:
RSECCNT/BCNT0
RMINCNT/BCNT1
RHRCNT/BCNT2
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21. Realtime Clock (RTC)
RDAYCNT
RWKCNT/BCNT3
RMONCNT
RYRCNT
RCR1.RTCOS
RCR2.RTCOE
RCR2.HR24
RFRL.
The counter must be stopped before writing to any of the these registers.
21.6.2
Use of Periodic Interrupts
The procedure for using periodic interrupts is shown in Figure 21.11.
The generation and period of the periodic interrupt can be changed by setting the RCR1.PES[3:0] bits. However, because
the prescaler R64CNT and RSECCNT/BCNT0 are used to generate interrupts, the interrupt period is not guaranteed
immediately after setting the RCR1.PES[3:0] bits.
In addition, the stopping/restarting or resetting of the counter operation, reset by RTC software, and the 30-second
adjustment by changing the RCR2 value, affects the interrupt period. When the time error adjustment function is used,
the interrupt generation period after adjustment is added or subtracted based on the adjustment value.
Set the period and enable interrupt requests
The period
is not
guaranteed.
The first interrupt is generated
Interrupts
are
generated
with the
specified
period.
Set the RCR1.PES[3:0] bits and
write 1 to the RCR1.PIE bit
Confirm generation of the first periodic interrupt*1
The set period elapses
An interrupt is generated
Confirm generation of a periodic interrupt
Note 1. When an interrupt generation period changes while the periodic interrupt is used, an interrupt
might be generated at the completion of the setting. If the interrupt is generated immediately
after the setting, the period is not guaranteed for two interrupts including the current interrupt.
Figure 21.11
21.6.3
Using periodic interrupt function
RTCOUT (1-Hz/64-Hz) Clock Output
Stopping/restarting or resetting the counter operation, reset by RTC software, and the 30-second adjustment by changing
the RCR2 value, affects the period of RTCOUT (1-Hz/64-Hz) output. When the time error adjustment function is used,
the period of RTCOUT (1-Hz/64-Hz) output after adjustment is added or subtracted based on the adjustment value.
21.6.4
Transitions to Low Power Modes after Setting Registers
A transition to a low power state during writing to an RTC register might corrupt the value of the register. After setting
the register, confirm that the setting is in place before initiating a transition to a low power state.
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21.6.5
21. Realtime Clock (RTC)
Notes when Writing to and Reading from Registers
When reading a counter register such as the second counter after writing to the counter register, follow the
procedure in section 21.3.5, Reading 64-Hz Counter and Time
The value written to the count registers, alarm registers, year alarm enable register, bits RCR2.AADJE, AADJP, and
HR24, RCR4 register, or frequency register is reflected when four read operations are performed after writing
The values written to the RCR1.CIE, RCR1.RTCOS, and RCR2.RTCOE bits can be read immediately after writing
To read the value from the timer counter after returning from a reset or a period in Software Standby mode state,
wait for 1/128 second while the clock is operating (RCR2.START bit = 1)
After a reset is generated, write to the RTC register after 6 cycles of the count source clock have elapsed.
21.6.6
Changing the Count Mode
When changing the count mode (calendar/binary), set the RCR2.START bit to 0, stop the counting operation, then start it
again from the initial setting. For details on the initial setting, see section 21.3.1, Outline of Initial Settings of Registers
after Power On.
21.6.7
Initialization Procedure when the Realtime Clock is not used
Registers in the RTC are not initialized by a reset. Depending on the initial state, the generation of an unintentional
interrupt request or operation of the counter might lead to increased power consumption.
For applications that do not require a realtime clock, initialize the registers by following the initialization procedure
shown in Figure 21.12.
Alternatively, when the sub-clock oscillator is not used as the system clock or realtime clock, the counter can be stopped
by writing 0 (sub-clock oscillator is selected) to the RCR4.RCKSEL bit and stopping the sub-clock oscillator. To stop the
sub-clock oscillator, write 1 to the SOSCCR.SOSTP bit.
For details on the setting of the SOSCCR.SOSTP bit, see section 8, Clock Generation Circuit.
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21. Realtime Clock (RTC)
Select the count source
Supply 6 clocks of the count source
RCR4.RCKSEL bit setting
Supply 6 clocks of the clock selected by the
RCR4.RCKSEL bit
Clear the START bit to 0
No
START = 0
Wait for the RCR2.START bit to become 0
Yes
Select count mode
Execute RTC software reset
No
RESET = 0
RCR2.CNTMD bit setting*1
Write 1 to the RCR2.RESET bit
Wait for the RCR2.RESET bit to become 0
Yes
Disable interrupt requests
Write 0 to the RCR1.AIE, CIE, and PIE bits
Note 1. This step is not required if the count mode is set concurrently by setting the START bit to 0.
Figure 21.12
Initialization procedure
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22.
22. Watchdog Timer (WDT)
Watchdog Timer (WDT)
The watchdog timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when the counter underflows
because the system has run out of control and become unable to refresh the WDT. In addition, a non-maskable interrupt
or an interrupt can be generated by an underflow.
The refresh-permitted period can be set to refresh the counter and to detect when the system runs out of control.
22.1
Overview
Table 22.1 lists the WDT specifications and Figure 22.1 shows the block diagram.
Table 22.1
WDT specifications
Parameter
Specifications
Count source
Peripheral clock (PCLKB)
Clock division ratio
Divide by 4, 64, 128, 512, 2,048, or 8,192
Counter operation
Counting down using a 14-bit down-counter
Conditions for starting the counter Auto start mode: Counting automatically starts after a reset or after an underflow or refresh error
occurs
Register start mode: Counting is started by refresh operation (writing to the WDTRR register).
Conditions for stopping the
counter
Reset (the down-counter and other registers return to their initial values)
A counter underflows or a refresh error is generated.
Window function
Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods)
Watchdog timer
Reset sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Non-maskable interrupt/interrupt
sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Reading the counter value
The down-counter value can be read by the WDTSR register
Event link function (output)
Down-counter underflow event output
Refresh error event output.
Output signal (internal signal)
Reset output
Interrupt request output
Sleep mode count stop control output.
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22. Watchdog Timer (WDT)
Interrupt request (WDT_NMIUNDF)
WDT output
Clock frequency
divider
Interrupt control circuit
Reset control circuit
PCLKB/4
PCLKB/64
PCLKB
PCLKB/128
WDT control circuit
PCLKB/512
14-bit down-counter
WDTRR
WDTCR
WDTSR
Option function select register 0
(OFS0)
WDTRCR
WDTCSTPR
PCLKB/2048
PCLKB/8192
Count stop control output
in sleep mode
Event signal output
Internal peripheral bus
Figure 22.1
22.2
Clock control circuit
Event link controller
WDTRR: WDT Refresh Register
WDTCR: WDT Control Register
WDTSR: WDT Status Register
WDTRCR: WDT Reset Control Register
WDTCSTPR: WDT Stop Control Register
WDT block diagram
Register Descriptions
22.2.1
WDT Refresh Register (WDTRR)
Address(es): WDT.WDTRR 4004 4200h
Value after reset:
Bit
b7 to b0
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
Description
The down-counter is refreshed by writing 00h and then writing FFh to this register
R/W
R/W
The WDTRR register refreshes the down-counter of the WDT.
The down-counter of the WDT is refreshed by writing 00h and then writing FFh to WDTRR (refresh operation) within
the refresh-permitted period.
After the down-counter is refreshed, it starts counting down from the value selected by setting the WDT timeout period
select bits (OFS0.WDTTOPS[1:0]) in the Option Function Select Register 0 in auto start mode. In register start mode,
counting down starts from the value selected by setting the timeout period selection bits (WDTCR.TOPS[1:0]) in the
WDT Control Register.
When 00h is written, the read value is 00h, when a value other than 00h is written, the read value is FFh. For details of
the refresh operation, see section 22.3.3, Refresh Operation.
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22.2.2
22. Watchdog Timer (WDT)
WDT Control Register (WDTCR)
Address(es): WDT.WDTCR 4004 4202h
Value after reset:
b15
b14
—
—
0
0
b13
b12
b11
b10
RPSS[1:0]
—
—
RPES[1:0]
1
0
0
1
1
b9
b8
b7
b6
b5
b4
CKS[3:0]
1
1
1
1
1
b3
b2
b1
b0
—
—
TOPS[1:0]
0
0
1
1
Bit
Symbol
Bit name
Description
R/W
b1, b0
TOPS[1:0]
Timeout Period Selection
b1 b0
R/W
b3, b2
—
Reserved
These bits are read as 0 and cannot be modified
R/W
b7 to b4
CKS[3:0]
Clock Division Ratio Selection
b7
R/W
b9, b8
RPES[1:0]
Window End Position Selection
b9 b8
R/W
b11, b10
—
Reserved
These bits are read as 0 and cannot be modified
R/W
b13, b12
RPSS[1:0]
Window Start Position Selection
b13 b12
R/W
b15, b14
—
Reserved
These bits are read as 0 and cannot be modified
R/W
0
0
1
1
0: 1,024 cycles (03FFh)
1: 4,096 cycles (0FFFh)
0: 8,192 cycles (1FFFh)
1: 16,384 cycles (3FFFh).
b4
0 0 0 1: PCLKB/4
0 1 0 0: PCLKB/64
1 1 1 1: PCLKB/128
0 1 1 0: PCLKB/512
0 1 1 1: PCLKB/2048
1 0 0 0: PCLKB/8192.
Other settings are prohibited.
0
0
1
1
0
0
1
1
0: 75%
1: 50%
0: 25%
1: 0% (window end position is not specified).
0: 25%
1: 50%
0: 75%
1: 100% (window start position is not specified).
Some restrictions apply to writes to the WDTCR register. For details, see section 22.3.2, Controlling Writes to the
WDTCR, WDTRCR, and WDTCSTPR Registers.
In auto start mode, the settings in the WDTCR register are disabled, and the settings in the Option Function Select
Register 0 (OFS0) are enabled. The settings for the WDTCR register can also be made for the OFS0 register. For details,
see section 22.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
TOPS[1:0] bits (Timeout Period Selection)
The TOPS[1:0] bits select the timeout period, the period until the down-counter underflows, between 1,024, 4,096,
8,192, and 16,384 cycles, taking the divided clock specified by the CKS[3:0] bits as 1 cycle.
After the down-counter is refreshed, the combination of the CKS[3:0] and TOPS[1:0] bits determines the time (number
of PCLKB cycles) until the counter underflows.
Table 22.2 lists the relationship between the CKS[3:0] and TOPS[1:0] bit settings, the timeout period, and the number of
PCLKB cycles.
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Table 22.2
22. Watchdog Timer (WDT)
Timeout period settings
CKS[3:0] bits
TOPS[1:0] bits
b7
b6
b5
b4
b1
b0
Clock division ratio
Timeout period
(number of cycles)
Cycles of PCLKB clock
0
0
0
1
0
0
PCLKB/4
1024
4096
0
1
4096
16384
1
0
8192
32768
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
16384
65536
1024
65536
0
1
4096
262144
1
0
8192
524288
1
1
16384
1048576
0
0
1024
131072
0
1
4096
524288
1
0
8192
1048576
1
1
0
0
0
PCLKB/64
PCLKB/128
16384
2097152
1024
524288
1
4096
2097152
1
0
8192
4194304
1
1
16384
8388608
0
0
1024
2097152
0
1
4096
8388608
1
0
8192
16777216
1
1
16384
33554432
0
0
1024
8388608
0
1
4096
33554432
1
0
8192
67108864
1
1
16384
134217728
PCLKB/512
PCLKB/2048
PCLKB/8192
CKS[3:0] bits (Clock Division Ratio Selection)
The CKS[3:0] bits specify the division ratio of the clock used for the down-counter. The division ratio can be selected
from the peripheral clock (PCLKB) divided by 4, 64, 128, 512, 2048, and 8,192. Combined with the TOPS[1:0] bit
setting, a count period between 4,096 and 134,217,728 cycles of the PCLKB clock can be selected for the WDT.
RPES[1:0] bits (Window End Position Selection)
The RPES[1:0] bits specify the window end position that indicates the refresh-permitted period. 75%, 50%, 25%, or 0%
of the timeout period can be selected for the window end position. The selected window end position should be a value
less than the value for the window start position (window start position > window end position). If the window end
position is greater than the window start position, only the window start position setting is enabled.
RPSS[1:0] bits (Window Start Position Selection)
The RPSS[1:0] bits specify the window start position that indicates the refresh-permitted period. 100%, 75%, 50%, or
25% of the timeout period can be selected for the window end position. The window start position should be set to a
value greater than the value for the window end position. If the window start position is set to a value smaller than or
equal to the window end position, the window end position is set to 0%.
Table 22.3 lists the counter values for the window start and end positions and Figure 22.2 shows the refresh-permitted
period set by the RPSS[1:0], RPES[1:0], and TOPS[1:0] bits.
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Table 22.3
22. Watchdog Timer (WDT)
Relationship between timeout period and window start and end counter values
Timeout period
TOPS[1:0] bits
Window start and end counter value
Cycles
Counter value
100%
75%
50%
25%
0
0
1024
03FFh
03FFh
02FFh
01FFh
00FFh
0
1
4096
0FFFh
0FFFh
0BFFh
07FFh
03FFh
1
0
8192
1FFFh
1FFFh
17FFh
0FFFh
07FFh
1
1
16384
3FFFh
3FFFh
2FFFh
1FFFh
0FFFh
RPES[1:0] Bits
RPSS[1:0] Bits
b13
b12
1
b8
1
1
1
0
0
1
0
0
1
1
0
1
0
25
0
1
0
0
1
1
0
1
0
25
0
1
0
0
75
1
1
0
1
0
0
1
0
0
0
0
1
0
End
(%)
b9
1
1
Window
Start
(%)
0
Counting
started
100
25
50
75
75
50
75
50
50
25
25
50
75
Note: If window end setting window start setting, the window end setting
is set to 0%.
Figure 22.2
22.2.3
Underflow
0
100%
75%
50%
25%
0%
Refresh-permitted period
Refresh-prohibited period
RPSS[1:0] and RPES[1:0] bit settings and refresh-permitted period
WDT Status Register (WDTSR)
Address(es): WDT.WDTSR 4004 4204h
b15
b14
b13
b12
b11
b10
b9
b8
REFEF UNDFF
Value after reset:
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CNTVAL[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
CNTVAL[13:0]
Down-Counter Value
Value counted by the down-counter
R
b14
UNDFF
Underflow Flag
0: No underflow occurred
1: Underflow occurred.
R(/W)
*1
b15
REFEF
Refresh Error Flag
0: No refresh error occurred
1: Refresh error occurred.
R(/W)
*1
Note 1. Only 0 can be written to clear the flag.
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22. Watchdog Timer (WDT)
CNTVAL[13:0] bits (Down-Counter Value)
Read the CNTVAL[13:0] bits to confirm the value of the down-counter, but the read value might differ from the actual
count by 1.
UNDFF flag (Underflow Flag)
Read the UNDFF flag to confirm whether an underflow occurred in the down-counter. The value 1 indicates that the
down-counter underflowed. Write 0 to the UNDFF flag to set the value to 0. Writing 1 has no effect.
Clearing of the UNDFF flag takes (N+1) PCLKB cycles. In addition, clearing of this flag is ignored for (N+1) PCLKB
cycles after an underflow. N is specified by the WDTCR.CKS[3:0] bits as follows:
When WDTCR.CKS[3:0] = 0001b , N = 4
When WDTCR.CKS[3:0] = 0100b , N = 64
When WDTCR.CKS[3:0] = 1111b , N = 128
When WDTCR.CKS[3:0] = 0110b , N = 512
When WDTCR.CKS[3:0] = 0111b , N = 2048
When WDTCR.CKS[3:0] = 1000b , N = 8192.
REFEF flag (Refresh Error Flag)
Read the REFEF flag to confirm whether a refresh error occurred. The value 1 indicates that a refresh error occurred.
Write 0 to the REFEF flag to set the value to 0. Writing 1 has no effect.
Clearing of the REFEF flag takes (N+1) PCLKB cycles. In addition, clearing of this flag is ignored for (N+1) PCLKB
cycles after a refresh error. N is specified by the WDTCR.CKS[3:0] bits as follows:
When WDTCR.CKS[3:0] = 0001b , N = 4
When WDTCR.CKS[3:0] = 0100b , N = 64
When WDTCR.CKS[3:0] = 1111b , N = 128
When WDTCR.CKS[3:0] = 0110b , N = 512
When WDTCR.CKS[3:0] = 0111b , N = 2048
When WDTCR.CKS[3:0] = 1000b , N = 8192.
22.2.4
WDT Reset Control Register (WDTRCR)
Address(es): WDT.WDTRCR 4004 4206h
b7
b6
b5
b4
b3
b2
b1
b0
RSTIR
QS
—
—
—
—
—
—
—
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0 and cannot be modified.
R/W
b7
RSTIRQS
Reset Interrupt Request Selection
0: Non-maskable interrupt request or interrupt request output
is enabled
1: Reset output is enabled.
R/W
Some restrictions apply to writes to the WDTRCR register. For details, see section 22.3.2, Controlling Writes to the
WDTCR, WDTRCR, and WDTCSTPR Registers.
In auto start mode, the WDTRCR register settings are disabled, and the settings in the Option Function Select register 0
(OFS0) are enabled. The settings for the WDTCR register can also be made for the OFS0 register. For details, see section
22.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
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22.2.5
22. Watchdog Timer (WDT)
WDT Count Stop Control Register (WDTCSTPR)
Address(es): WDT.WDTCSTPR 4004 4208h
b7
b6
b5
b4
b3
b2
b1
b0
SLCST
P
—
—
—
—
—
—
—
1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0 and cannot be modified
R/W
b7
SLCSTP
Sleep-Mode Count Stop Control
0: Count stop is disabled
1: Count is stopped at a transition to Sleep mode.
R/W
The WDTCSTPR register controls whether to stop the WDT counter in a low power state. Some restrictions apply to
writes to the WDTCSTPR register. For details, see section 22.3.2, Controlling Writes to the WDTCR, WDTRCR, and
WDTCSTPR Registers.
In auto start mode, the WDTCSTPR register settings are disabled, and the settings in the Option Function Select register
0 (OFS0) are enabled. The settings for the WDTCSTPR register can also be made for the OFS0 register. For details, see
section 22.3.7, Association between Option Function Select Register 0 (OFS0) and WDT Registers.
SLCSTP bit (Sleep-Mode Count Stop Control)
The SLCSTP bit selects whether to stop counting on a transition to Sleep mode.
22.2.6
Option Function Select Register 0 (OFS0)
For details on the OFS0 register, see section 22.3.7, Association between Option Function Select Register 0 (OFS0) and
WDT Registers.
22.3
Operation
22.3.1
Count Operation in each Start Mode
The WDT has two start modes:
Auto start mode, in which counting automatically starts after a release from the reset state
Register start mode, in which counting is started with a refresh by writing to the register.
In auto start mode, counting automatically starts after a release from the reset state in according to the settings in the
Option Function Select register 0 (OFS0) in the Flash.
In register start mode, counting is started with a refresh by writing to the register after the respective registers are set after
a release from the reset state.
Select auto start mode or register start mode by setting the WDT start mode select bit (OFS0.WDTSTRT) in the OFS0
register.
When the auto start mode is selected, the settings in the WDT Control Register (WDTCR), WDT Reset Control Register
(WDTRCR), and WDT Count Stop Control Register (WDTCSTPR) are disabled, and the settings in the OFS0 register
are enabled.
When the register start mode is selected, the setting of the OFS0 register is disabled, and the settings of the WDT Control
Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT Count Stop Control Register (WDTCSTPR)
are enabled.
22.3.1.1
Register start mode
When the WDT start mode select bit (OFS0.WDTSTRT) is 1, register start mode is selected and the WDT Control
Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT Count Stop Control Register (WDTCSTPR)
are enabled.
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22. Watchdog Timer (WDT)
After the reset state is released, set the following to Sleep mode in the WDTCSTPR register:
Clock division ratio
Window start and end positions
Timeout period in the WDTCR register
Reset output or interrupt request output in the WDTRCR register
Counter stop control during transitions.
Refresh the down-counter to start counting down from the value set in the timeout period selection bits
(WDTCR.TOPS[1:0]).
After that, as long as the counter is refreshed in the permitted period, the value in the counter is reset each time the
counter is refreshed and counting down continues. The WDT does not output the reset signal as long as counting
continues. However, if the down-counter underflows because a runaway program makes refreshing of the down-counter
impossible, or because a refresh error occurs because an attempt is made to refresh outside the permitted period, the
WDT outputs a reset signal or a non-maskable interrupt request/interrupt request (WDT_NMIUNDF). Reset output or
interrupt request output can be selected by setting the WDT reset interrupt request select bit (WDTRCR.RSTIRQS).
Non-maskable interrupt requests or interrupt requests can be selected in the WDT underflow/refresh error interrupt
enable bit (NMIER.WDTEN).
Figure 22.3 shows an example of operation under the following conditions:
Register start mode (OFS0.WDTSTRT = 1)
Reset output is enabled (WDTRCR.RSTIRQS = 1)
The window start position is 75% (WDTCR.RPSS[1:0] = 10b)
The window end position is 25% (WDTCR.RPES[1:0] = 10b).
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22. Watchdog Timer (WDT)
Counter value
100%
Refreshprohibited
period
75%
Refreshpermitted
period
50%
25%
Refreshprohibited
period
0%
RES pin
Control
register
(WDTCR)
(1) Initial value
(2) Set value
(1)
(2)
Writing to the
register is valid
Refresh
the counter
(active-high)
(1)
Writing to the
register is invalid *1
Writing to the
register is valid
(2)
(1)
Writing to
the register
is invalid *1
(2)
Writing to the
register is valid
H
L
Counting starts
Counting starts
Underflow
Refresh error
flag
(active-high)
H
L
Underflow flag
(active-high)
H
L
Interrupt request
(WDT_NMIUNDF)
(active-high)
L
Reset output
from WDT
(active-high)
H
L
Counting starts
Refresh error
Refresh error
Status flag
cleared
Status flag
cleared
Note 1. See section 22.3.2, Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers.
Figure 22.3
Operation example in register start mode
22.3.1.2
Auto start mode
When the WDT start mode select bit (OFS0.WDTSTRT) in the Option Function Select register 0 (OFS0) is 0, auto start
mode is selected, the WDT Control Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT Count
Stop Control Register (WDTCSTPR) are disabled, and the settings in the OFS0 register are enabled.
Within the reset state, the setting values for the following in the Option Function Select Register 0 (OFS0) are set in the
WDT registers:
Clock division ratio
Window start and end positions
Timeout period
Reset output or interrupt request
Counter stop control on transitions to Sleep mode.
When the reset state is released, the down-counter automatically starts counting down from the value set in the WDT
timeout period select bits (OFS0.WDTTOPS[1:0]).
After that, as long as the counter is refreshed in the refresh-permitted period, the value in the counter is reset each time
the counter is refreshed and counting down continues. The WDT does not output the reset signal as long as counting
continues. However, if the down-counter underflows because a runaway program makes refreshing of the down-counter
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22. Watchdog Timer (WDT)
impossible, or because a refresh error occurs when an attempt is made to refresh outside the refresh-permitted period, the
WDT outputs the reset signal or non-maskable interrupt request/interrupt request (WDT_NMIUNDF).
After the reset signal or non-maskable interrupt request/interrupt request is generated, the counter reloads the timeout
period after counting for 1 cycle. The value of the timeout period is set in the down-counter and counting restarts. Reset
output or interrupt request output can be selected by setting the WDT reset interrupt request select bit
(OFS0.WDTRSTIRQS). Non-maskable interrupt request or interrupt request can be selected by setting the WDT
underflow/refresh error interrupt enable bit (NMIER.WDTEN).
Figure 22.4 shows an example of operation (non-maskable interrupt) under the following conditions:
Auto start mode (OFS0.WDTSTRT = 0)
Non-maskable interrupt request output is enabled (OFS0.WDTRSTIRQS = 0)
The window start position is 75% (WDTCR.RPSS[1:0] = 10b)
The window end position is 25% (WDTCR.RPES[1:0] = 10b).
Counter value
100%
Refreshprohibited
period
75%
50%
Refreshpermitted
period
25%
Refreshprohibited
period
0%
RES pin
Down-counter
control pin
Refresh
the counter
Active: High
H
L
Counting starts
Counting starts
Underflow
Refresh error
flag
Active: High
H
Underflow flag
Active: High
H
Interrupt request
(WDT_NMIUNDF)
Active: High
H
Reset output
from WDT
Active: High
Figure 22.4
22.3.2
Counting starts
Refresh error
Counting starts
Refresh error
Status flag
cleared
L
L
Status flag
cleared
L
L
Operation example in auto start mode
Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers
Writing to the WDT Control Register (WDTCR), WDT Reset Control Register (WDTRCR), or WDT Count Stop
Control Register (WDTCSTPR) is possible once between the release from the reset state and the first refresh operation.
After a refresh operation (counting starts) or a write to WDTCR, WDTRCR, or WDTCSTPR, the protection signal in the
WDT becomes 1 to protect WDTCR, WDTRCR, and WDTCSTPR against subsequent write attempts. This protection is
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22. Watchdog Timer (WDT)
released by a reset source of the WDT. With other reset sources, the protection is not released.
Figure 22.5 shows the control waveforms produced in response to writing to the WDTCR.
RES pin
Peripheral clock (PCLKB)
Data written to WDTCR
register
xxxxh
WDTCR register write
signal (internal signal)
WDTCR register
Writing disabled
33F3h (initial value)
Register
protection signal
(internal signal)
Writing is possible
Figure 22.5
22.3.3
3300h
00F3h
00F3h
00F3h
33F3h (initial value)
WDTCR register is protected
(writing-disabled period)
Control waveforms produced in response to writes to the WDTCR register
Refresh Operation
The down-counter is refreshed by writing the values 00h and FFh to the WDT Refresh Register (WDTRR). If a value
other than FFh is written after 00h, the down-counter is not refreshed. If an invalid value is written, correct refreshing is
resumes on a write of 00h and FFh to the WDTRR register.
Correct refreshing is also performed when a register other than WDTRR is accessed or when WDTRR is read between
writing 00h and writing FFh to WDTRR.
Writes to refresh the counter must be made within the refresh-permitted period and this is determined by writing FFh. For
this reason, correct refreshing is performed even when 00h is written outside the refresh-permitted period.
[Example write sequences that are valid for refreshing the counter]
00h → FFh
00h (n–1-th time) → 00h (nth time) → FFh
00h → access to another register or read from WDTRR → FFh.
[Example write sequences that are not valid for refreshing the counter]
23h (a value other than 00h) → FFh
00h → 54h (a value other than FFh)
00h→ AAh (00h and a value other than FFh) → FFh.
After FFh is written to the WDT Refresh Register (WDTRR), refreshing the down-counter requires up to 4 cycles of the
signal for counting. To meet this requirement, complete writing FFh to the WDTRR 4 count cycles before the downcounter underflows.
Figure 22.6 shows the WDT refresh operation waveforms when the clock division ratio is PCLKB/64.
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22. Watchdog Timer (WDT)
Peripheral clock
(PCLKB)
Data written to
WDTRR register
00h
54h
00h
FFh
WDTRR register
write signal
(internal signal)
WDTRR register
Valid
FFh
FFh
00h
FFh
Invalid
Refresh
synchronization
signal
Refresh signal
(after synchronization
with count cycle)
Counter value
00h
Refresh request
(n+1)h
(n)h
(n)h
(n-1)h
(n-1)h 0FFFh
Refreshing
Figure 22.6
22.3.4
WDT refresh operation waveforms when WDTCR.CKS[3:0] = 0100b, WDTCR.TOPS[1:0] = 01b
Reset Output
When the reset interrupt selection bit (WDTRCR.RSTIRQS) is set to 1 in register start mode or when the WDT reset
interrupt request select bit (OFS0.WDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 1 in auto
start mode, a reset signal is output for 1 count cycle when an underflow in the down-counter or a refresh error occurs.
In register start mode, the down-counter is initialized (all bits set to 0) and stopped in that state after output of the reset
signal. After the reset state is released and the program is restarted, the counter is set up again and counting down starts
again with a refresh. In auto start mode, counting down starts automatically after the reset state is released.
22.3.5
Interrupt Sources
When the reset interrupt selection bit (WDTRCR.RSTIRQS) is set to 0 in register start mode or when the WDT reset
interrupt request select bit (OFS0.WDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 0 in auto
start mode, an interrupt (WDT_NMIUNDF) signal is generated when an underflow in the counter or a refresh error
occurs. This interrupt can be used as a non-maskable interrupt or an interrupt. For details, see section 12, Interrupt
Controller Unit (ICU).
Table 22.4
WDT interrupt sources
Name
Interrupt source
DTC activation
WDT_NMIUNDF
Down-counter underflow
Refresh error
Not possible
22.3.6
Reading the Down-Counter Value
The WDT stores the counter value in the down-counter value (WDTSR.CNTVAL[13:0]) bits of the WDT Status
Register. Check these bits to obtain the counter value.
Figure 22.7 shows the processing for reading the WDT down-counter value when the clock division ratio is PCLKB/64.
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22. Watchdog Timer (WDT)
Peripheral clock
(PCLKB)
Refreshing
Counter value
(n+1)h
Bits WDTSR.CNTVAL
[13:0]
(n+1)h
(n)h
(n-1)h
(n)h
(n-1)h
(n-1)h
0FFFh
(n-1)h
0FFFh
WDTSR.CNTVAL
[13:0] read signal
(internal signal)
WDTSR.CNTVAL
[13:0] read data
Figure 22.7
22.3.7
xxxxh
(n+1)h
(n)h
(n)h
0FFFh
Read process for WDT down-counter value when WDTCR.CKS[3:0] = 0100b, WDTCR.TOPS[1:0] =
01b
Association between Option Function Select Register 0 (OFS0) and
WDT Registers
Table 22.5 lists the association between the Option Function Select Register 0 (OFS0) used in auto start mode and the
registers used in register start mode. Do not change the OFS0 register setting during WDT operation. For details on the
Option Function Select Register 0 (OFS0), see section 6.2.1, Option Function Select Register 0 (OFS0).
Table 22.5
Association between Option Function Select Register 0 (OFS0) and the WDT registers
Control target
Function
OFS0 register
(enabled in auto start mode)
OFS0.WDTSTRT = 0
Down-counter
Timeout period selection
OFS0.WDTTOPS[1:0]
WDT registers
(enabled in register start mode)
OFS0.WDTSTRT = 1
WDTCR.TOPS[1:0]
Clock division ratio selection
OFS0.WDTCKS[3:0]
WDTCR.CKS[3:0]
Window start position selection
OFS0.WDTRPSS[1:0]
WDTCR.RPSS[1:0]
Window end position selection
OFS0.WDTRPES[1:0]
WDTCR.RPES[1:0]
Reset output or interrupt
request output
Reset output or interrupt request
output selection
OFS0.WDTRSTIRQS
WDTRCR.RSTIRQS
Count stop
Sleep mode count stop control
OFS0.WDTSTPCTL
WDTCSTPR.SLCSTP
22.4
Link Operation by ELC
The WDT is capable of link operation for a specified module when interrupt request signal is used as an event signal by
the Event Link Controller (ELC). The event signal is output by the counter underflow or refresh error. An event signal is
output regardless of the setting of the reset interrupt request selection bit (WDTRCR.RSTIRQS) in register start mode or
auto start mode. An event signal can also be output when the next interrupt source is generated while the refresh error
flag (WDTSR.REFEF) or underflow flag (WDTSR.UNDFF) is 1. For details, see section 15, Event Link Controller
(ELC).
22.5
22.5.1
Usage Notes
ICU Event Link Setting Register n (IELSRn) Setting
Setting 18h to ICU Event Link Setting Register n (IELSRn.IELS[7:0]) is prohibited when enabling the WDT reset
assertion (OFS0.WDTRSTIRQS = 1 or WDTRCR.RSTIRQS = 1) or when enabling event link operation
(ELSRm.ELS[7:0] =18h).
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23. Independent Watchdog Timer (IWDT)
23.
Independent Watchdog Timer (IWDT)
23.1
Overview
The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to
prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt/
interrupt when a timer underflow occurs. Because the timer operates with an independent, dedicated clock source, it is
particularly useful in returning the MCU to a known state as a failsafe mechanism when the system runs out of control.
The watchdog timer can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value in
the registers.
The IWDT functions differ from those of the WDT as follows:
The divided IWDT-dedicated clock (IWDTCLK) is used as the count source (not affected by the PCLKB)
IWDT does not support register start mode
When transitioning to low power mode, the OFS0.IWDTSTPCTL bit can be used to select whether to stop the
counter or not.
Table 23.1 lists the IWDT specifications and Figure 23.1 shows a block diagram of the IWDT.
Table 23.1
IWDT specifications
Parameter
Count
source*1
Description
IWDT-dedicated clock (IWDTCLK)
Clock division ratio
Division by 1, 16, 32, 64, 128, or 256
Counter operation
Counting down using a 14-bit down-counter
Condition for starting the counter
Counting automatically starts after a reset
Conditions for stopping the
counter
Reset (the down-counter and other registers return to their initial values)
A counter underflows or a refresh error is generated (counting restarts automatically).
Window function
Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods)
Reset output sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Non-maskable interrupt/interrupt
sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error).
Reading the counter value
The down-counter value can be read by the IWDTSR register.
Event link function (output)
Down-counter underflow event output
Refresh error event output.
Output signal (internal signal)
Reset output
Interrupt request output
Sleep-mode count stop control output.
Auto start mode
Selecting the clock frequency division ratio after a reset (OFS0.IWDTCKS[3:0] bits)
Selecting the timeout period of the independent watchdog timer (OFS0.IWDTTOPS[1:0] bits)
Selecting the window start position in the independent watchdog timer (OFS0.IWDTRPSS[1:0]
bits)
Selecting the window end position in the independent watchdog timer (OFS0.IWDTRPES[1:0]
bits)
Selecting the reset output or interrupt request output (OFS0.IWDTRSTIRQS bit)
Selecting the down-count stop function at transition to Sleep mode, Software Standby mode, or
Snooze mode (OFS0.IWDTSTPCTL bit).
Note 1. Satisfy the frequency of the peripheral module clock (PCLKB) 4 × (the frequency of the count clock source after
division).
To use the IWDT, you must supply the IWDT-dedicated clock (IWDTCLK). The bus interface and registers operate with
PCLKB, and the 14-bit counter and control circuits operate with IWDTCLK.
Figure 23.1 shows a block diagram of the IWDT.
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23. Independent Watchdog Timer (IWDT)
Interrupt request (IWDT_NMIUNDF)
Interrupt control circuit
IWDT reset output
Reset control circuit
Clock
frequency
divider
IWDTCLK
IWDTCLK/16
IWDTCLK/32
IWDTCLK/64
IWDTCLK/128
IWDTCLK/256
IWDT control circuit
IWDTSR
Option function select register 0
(OFS0)
14-bit counter
Count stop control output
in Sleep mode, Snooze mode, or
Software Standby mode
IWDTRR
IWDTCLK
Clock control circuit
Event signal output
Event link controller
IWDTRR:
IWDTSR:
Internal peripheral bus
Figure 23.1
23.2
IWDT refresh register
IWDT status register
IWDT block diagram
Register Descriptions
23.2.1
IWDT Refresh Register (IWDTRR)
Address(es): IWDT.IWDTRR 4004 4400h
Value after reset:
Bit
b7 to b0
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
Description
The counter is refreshed by writing 00h and then writing FFh to this register
R/W
R/W
The IWDTRR register refreshes the down-counter of the IWDT. The down-counter of the IWDT is refreshed by writing
00h and then writing FFh to IWDTRR (refresh operation) within the refresh-permitted period. After the down-counter is
refreshed, it starts counting down from the value selected in the IWDT timeout period select bits
(OFS0.IWDTTOPS[1:0]) in the Option Function Select Register 0 (OFS0).
When 00h is written, the read value is 00h. When a value other than 00h is written, the read value is FFh. For details of
the refresh operation, see section 23.3.2, Refresh Operation.
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23.2.2
23. Independent Watchdog Timer (IWDT)
IWDT Status Register (IWDTSR)
Address(es): IWDT.IWDTSR 4004 4404h
b15
b14
b13
b12
b11
b10
b9
b8
REFEF UNDFF
Value after reset:
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CNTVAL[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
CNTVAL[13:0]
Counter Value
Value counted by the down-counter
R
b14
UNDFF
Underflow Flag
0: Underflow not occurred
1: Underflow occurred.
R/(W)*1
b15
REFEF
Refresh Error Flag
0: Refresh error not occurred
1: Refresh error occurred.
R/(W)*1
Note 1. Only 0 can be written to clear the flag.
CNTVAL[13:0] bits (Counter Value)
Read the CNTVAL[13:0] bits to confirm the value of the down-counter. The read value might differ from the actual
count by 1.
UNDFF flag (Underflow Flag)
Read the UNDFF flag to confirm whether an underflow occurred in the down-counter. The value 1 indicates that the
down-counter underflowed. Write 0 to the UNDFF flag to set the value to 0. Writing 1 has no effect.
Clearing of the UNDFF flag takes (N+2) IWDTCLK cycles and 2 PCLKB cycles. In addition, clearing of this flag is
ignored for (N+2) IWDTCLK cycles after an underflow. N is specified by the IWDTCKS[3:0] bits as follows:
When IWDTCKS[3:0] = 0000b , N = 1
When IWDTCKS[3:0] = 0010b , N = 16
When IWDTCKS[3:0] = 0011b , N = 32
When IWDTCKS[3:0] = 0100b , N = 64
When IWDTCKS[3:0] = 1111b , N = 128
When IWDTCKS[3:0] = 0101b , N = 256.
REFEF flag (Refresh Error Flag)
Read the REFEF flag to confirm whether a refresh error occurred. The value 1 indicates that a refresh error occurred.
Write 0 to the REFEF flag to set the value to 0. Writing 1 has no effect.
Clearing of the REFEF flag takes (N+2) IWDTCLK cycles and 2 PCLKB cycles. In addition, clearing of this flag is
ignored for (N+2) IWDTCLK cycles after a refresh error. N is specified by the IWDTCKS[3:0] bits as follows:
When IWDTCKS[3:0] = 0000b , N = 1
When IWDTCKS[3:0] = 0010b , N = 16
When IWDTCKS[3:0] = 0011b , N = 32
When IWDTCKS[3:0] = 0100b , N = 64
When IWDTCKS[3:0] = 1111b , N = 128
When IWDTCKS[3:0] = 0101b , N = 256.
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23.2.3
23. Independent Watchdog Timer (IWDT)
Option Function Select Register 0 (OFS0)
For information on the Option Function Select Register 0 (OFS0), see section 6.2.1, Option Function Select Register 0
(OFS0).
IWDTTOPS[1:0] bits (IWDT Timeout Period Select)
The IWDTTOPS[1:0] bits select the timeout period, the period until the down-counter underflows, from 128, 512, 1024,
or 2048 cycles, taking the divided clock specified by the IWDTCKS[3:0] bits as 1 cycle. After the down-counter is
refreshed, the combination of the IWDTCKS[3:0] and IWDTTOPS[1:0] bits determines the number of IWDTCLK
cycles until the counter underflows.
Table 23.2 lists the relationship between the IWDTCKS[3:0] and IWDTTOPS[1:0] bit settings, the timeout period, and
the number of IWDTCLK cycles.
Table 23.2
Timeout period settings
IWDTCKS[3:0] bits
b7
b6
b5
b4
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
0
IWDTTOPS[1:0] bits
0
1
0
1
1
b1
b0
Clock division ratio
IWDTCLK
Timeout period
(number of cycles)
Cycles of IWDTCLK
0
0
128
128
0
1
512
512
1
0
1024
1024
1
1
2048
2048
0
0
128
2048
0
1
512
8192
1
0
1024
16384
1
1
2048
32768
0
0
128
4096
0
1
512
16384
1
0
1024
32768
1
1
2048
65536
0
0
128
8192
0
1
512
32768
1
0
1024
65536
1
1
2048
131072
0
0
128
16384
0
1
512
65536
1
0
1024
131072
1
1
2048
262144
IWDTCLK/16
IWDTCLK/32
IWDTCLK/64
IWDTCLK/128
0
0
128
32768
0
1
IWDTCLK/256
512
131072
1
0
1024
262144
1
1
2048
524288
IWDTCKS[3:0] bits (IWDT-Dedicated Clock Frequency Division Ratio Select)
The IWDTCKS[3:0] bits specify the division ratio of the clock used for the down-counter. The division ratio can be
selected from the IWDT-dedicated clock (IWDTCLK) divided by 1, 16, 32, 64, 128, and 256. Combined with the
IWDTTOPS[1:0] bit setting, a count period between 128 and 524288 cycles of the IWDTCLK clock can be selected for
the IWDT.
IWDTRPES[1:0] bits (IWDT Window End Position Select)
The IWDTRPES[1:0] bits specify the window end position that indicates the refresh-permitted period. 75%, 50%, 25%,
or 0% of the timeout period can be selected for the window end position. The selected window end position should be a
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23. Independent Watchdog Timer (IWDT)
value smaller than the value for the window start position. If the window end position is greater than the window start
position, only the window start position setting is enabled.
IWDTRPSS[1:0] bits (IWDT Window Start Position Select)
The IWDTRPSS[1:0] bits specify the window start position that indicates the refresh-permitted period. 100%, 75%,
50%, or 25% of the timeout period can be selected for the window start position. The window start position should be a
value greater than the value for the window end position. If the window start position is smaller than or equal to the
window end position, the window end position is set to 0%.
Table 23.3 lists the counter values for the window start and end positions and Figure 23.2 shows the refresh-permitted
period set in the IWDTRPSS[1:0], IWDTRPES[1:0], and IWDTTOPS[1:0] bits.
Table 23.3
Relationship between timeout period and window start and end counter values
IWDTTOPS[1:0] bits
Timeout period
b1
b0
0
0
128
0
1
512
01FFh
1
0
1024
03FFh
1
1
2048
07FFh
07FFh
IWDTRPSS[1:0] bits
b13
1
1
0
0
b12
Cycles
Window start and end counter value
Counter value
007Fh
IWDTRPES[1:0] bits
End
(%)
b8
1
1
1
0
0
1
0
0
1
1
0
1
0
25
0
1
0
0
1
1
0
1
0
25
0
1
0
0
75
1
1
0
1
0
0
1
0
0
0
1
0
50%
25%
003Fh
001Fh
01FFh
017Fh
00FFh
007Fh
03FFh
02FFh
01FFh
00FFh
05FFh
03FFh
01FFh
Counting
started
Underflow
0
100
25
50
75
75
50
75
50
25
50
25
50
75
Note: If window end setting window start setting, the window end setting
is set to 0%.
Figure 23.2
75%
005Fh
Window
Start
(%)
b9
1
100%
007Fh
100%
75%
50%
25%
0%
Refresh-permitted period
Refresh-prohibited period
IWDTRPSS[1:0] and [IWDTRPES[1:0] bit settings and refresh-permitted period
IWDTRSTIRQS bit (IWDT Reset Interrupt Request Select)
The IWDTRSTIRQS bit specifies the behavior when an underflow or a refresh error occurred. The value 1 indicates that
reset output is selected. The value 0 indicates that a non-maskable interrupt or interrupt is selected.
IWDTSTPCTL bit (IWDT Stop Control)
The IWDTSTPCTL bit selects whether to stop counting on transition to Sleep mode, Snooze mode, or Software Standby
mode.
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23.3
23.3.1
23. Independent Watchdog Timer (IWDT)
Operation
Auto Start Mode
When the IWDT start mode select bit (OFS0.IWDTSTRT) in the Option Function Select Register 0 is 0, auto start mode
is selected, otherwise IWDT is disabled.
Within the reset state, the setting values for the following in the Option Function Select Register 0 (OFS0) are set in the
IWDT registers:
Clock division ratio
Window start and end positions
Timeout period
Reset output or interrupt request
Counter stop control on transitions to low power mode.
When the reset state is released, the counter automatically starts counting down from the value selected by the IWDT
timeout period select bits (OFS0.IWDTTOPS[1:0]).
After that, as long as the program continues normal operation and the counter is refreshed within the refresh-permitted
period, the value in the counter is reset each time the counter is refreshed and counting down continues. The IWDT does
not output the reset signal as long as this procedure continues. However, if the counter underflows because the program
crashed or because a refresh error occurs when an attempt is made to refresh outside the refresh-permitted period, the
IWDT asserts the reset signal or non-maskable interrupt request/interrupt request (IWDT_NMIUNDF).
After the reset signal or non-maskable interrupt request/interrupt request is generated, the counter reloads the timeout
period after counting for 1 cycle, and restarts the count. Reset output or interrupt request can be selected in the IWDT
reset interrupt request select bit (OFS0.IWDTRSTIRQS). Non-maskable interrupt request or interrupt request can be
selected in the IWDT underflow/refresh error interrupt enable bit (NMIER.IWDTEN).
Figure 23.3 shows an example of operation under the following conditions:
Auto start mode (OFS0.IWDTSTRT = 0)
Non-maskable interrupt request output is enabled (OFS0.IWDTRSTIRQS = 0)
The window start position is 75% (OFS0.IWDTRPSS[1:0] = 10b)
The window end position is 25% (OFS0.IWDTRPES[1:0] = 10b).
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23. Independent Watchdog Timer (IWDT)
Counter value
100%
75%
50%
25%
0%
Refreshprohibited period
Refreshpermitted period
Refreshprohibited period
RES pin
Refresh
the counter
Active: High
H
L
Counting starts
Counting starts
Underflow
Refresh error flag
Active: High
H
Underflow flag
Active: High
H
Interrupt request
(IWDT_NMIUNDF)
Active: High
Counting starts
Refresh error
Counting starts
Refresh error
Status flag
cleared
L
L
Status flag
cleared
H
L
Reset output
from IWDT
Active: High L
Figure 23.3
23.3.2
Operation example in auto start mode
Refresh Operation
The down-counter is refreshed by writing the values 00h and FFh to the IWDT Refresh Register (IWDTRR). If a value
other than FFh is written after 00h, the counter is not refreshed. If an invalid value is written, correct refreshing resumes
on a write of 00h and FFh to the IWDTRR.
When writes are made in the order of 00h (first time) → 00h (second time), and if FFh is written after that, the writing
order 00h → FFh is satisfied. Writes of 00h (n–1th time) → 00h (nth time) → FFh are valid, and the refresh is performed
correctly. Even when the first value written before 00h is not 00h, correct refreshing is performed as long as the operation
contains the write sequence 00h → FFh.
Correct refreshing is also performed when a register other than IWDTRR is accessed or IWDTRR is read between
writing 00h and writing FFh to IWDTRR.
[Example write sequences that are valid to refresh the counter]
00h → FFh
00h (n–1th time) → 00h (nth time) → FFh
00h → access to another register or read from IWDTRR → FFh.
[Example write sequences that are not valid to refresh the counter]
23h (a value other than 00h) → FFh
00h → 54h (a value other than FFh)
00h → AAh (00h and a value other than FFh) → FFh.
When 00h is written to IWDTRR outside the refresh-permitted period and when FFh is written to IWDTRR in the
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23. Independent Watchdog Timer (IWDT)
refresh-permitted period, the writing sequence is valid and refreshing completes.
After FFh is written to the IWDTRR register, refreshing the counter requires up to 4 cycles of the signal for counting (the
IWDT-dedicated clock frequency division ratio select bits (OFS0.IWDTCKS[3:0]) to determine how many cycles of the
IWDT-dedicated clock (IWDTCLK) make up 1 cycle for counting. To meet this requirement, complete writing FFh to
IWDTRR 4 count cycles before the end of the refresh-permitted period or a counter underflow. The value of the counter
can be checked using the counter bits (IWDTSR.CNTVAL[13:0]).
[Example refreshing timings]
When the window start position is set to 1FFFh, if 00h is written to IWDTRR before 1FFFh is reached (2002h, for
example), refreshing occurs if FFh is written to IWDTRR after the value of the IWDTSR.CNTVAL[13:0] bits
reaches 1FFFh
When the window end position is set to 1FFFh, refreshing occurs if 2003h (4 count cycles before 1FFFh) or a
greater value is read from the IWDTSR.CNTVAL[13:0] bits immediately after a write of 00h → FFh to IWDTRR
When the refresh-permitted period continues until count 0000h, refreshing can be performed immediately before an
underflow. In this case, if 0003h (4 count cycles before an underflow) or a greater value is read from the
IWDTSR.CNTVAL[13:0] bits immediately after a write of 00h → FFh to IWDTRR, no underflow occurs and
refreshing is performed.
Figure 23.4 shows the IWDT refresh-operation waveforms when PCLKB > IWDTCLK and the clock division ratio is
IWDTCLK.
Peripheral clock
(PCLKB)
IWDT-dedicated
clock (IWDTCLK)
Data written to
IWDTRR register
00h
54h
00h
FFh
IWDTRR register write
signal (internal signal)
IWDTRR register
Valid
FFh
00h
FFh
FFh
Invalid
Refresh
synchronization signal
Refresh signal
(after synchronization
with IWDTCLK)
Counter value
00h
Refresh request
(n+2)h
(n+1)h
(n)h
(n-1)h
(n-2)h
(n-3)h
3FFFh
Refreshing
Figure 23.4
23.3.3
IWDT refresh operation waveforms when OFS0.IWDTCKS[3:0] = 0000b, OFS0.IWDTTOPS[1:0] =
11b
Status Flags
The refresh error (IWDTSR.REFEF) and underflow (IWDTSR.UNDFF) flags retain the source of the reset signal output
or the source of the interrupt request from the IWDT. Therefore, after a release from the reset state or interrupt request
generation, read the IWDTSR.REFEF and UNDFF flags to check for the reset or interrupt source. For each flag, writing
0 clears the bit and writing 1 has no effect.
Leaving the status flags unchanged does not affect operation. If the flags are not cleared at the time of the next reset or
interrupt request from the IWDT, the earlier reset or interrupt source is cleared and the new reset or interrupt source is
written. After 0 is written to each flag, up to 3 IWDTCLK cycles and 2 PCLKB cycles are required before the value is
reflected.
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23.3.4
23. Independent Watchdog Timer (IWDT)
Reset Output
When the IWDT reset interrupt request select bit (OFS0.IWDTRSTIRQS) in the Option Function Select Register 0
(OFS0) is set to 1, a reset signal is output when an underflow in the counter or a refresh error occurs. Counting down
starts automatically after the reset output.
23.3.5
Interrupt Sources
When the IWDT reset interrupt request select bit (OFS0.IWDTRSTIRQS) in the Option Function Select Register 0
(OFS0) is set to 0, an interrupt (IWDT_NMIUNDF) signal is generated when an underflow in the counter or a refresh
error occurs. This interrupt can be used as a non-maskable interrupt or an interrupt. For details, see section 12, Interrupt
Controller Unit (ICU).
Table 23.4
IWDT interrupt source
Name
Interrupt source
DTC activation
IWDT_NMIUNDF
Down-counter underflow
Refresh error
Not possible
23.3.6
Reading the Down-counter Value
As the counter in IWDT-dedicated clock (IWDTCLK), the counter value cannot be read directly. The IWDT
synchronizes the counter value with the peripheral clock (PCLKB) and stores it in the down-counter value bits
(IWDTSR.CNTVAL[13:0]) of the IWDT status register. Check these bits to obtain the counter value indirectly. Reading
the counter value requires multiple PCLKB clock cycles (up to 4 clock cycles), and the read counter value might differ
from the actual counter value by a value of 1.
Figure 23.5 shows the processing for reading the IWDT counter value when PCLKB > IWDTCLK and the clock division
ratio is IWDTCLK.
Peripheral clock
(PCLKB)
IWDT-dedicated
clock (IWDTCLK)
Refreshing
(after synchronization with IWDTCLK)
Counter value
Bits
IWDTSR.CNTVAL
[13:0]
(n+1)h
(n+1)h
(n)h
(n-1)h
(n)h
(n-2)h
(n-1)h
3FFFh
(n-3)h
(n-2)h
(n-3)h
3FFEh
3FFFh
IWDTSR.CNTVAL
[13:0] read signal
(internal signal)
IWDTSR.CNTVAL
[13:0] read data
Figure 23.5
23.4
xxxxh
(n+1)h
(n)h
(n-2)h
3FFFh
Processing for reading IWDT counter value when OFS0.IWDTCKS[3:0] = 0000b,
OFS0.IWDTTOPS[1:0] = 11b
Link Operation by ELC
The IWDT is capable of link operation for a specified module when the interrupt request signal is used as an event signal
by the event link controller (ELC). The event signal is output by the counter underflow or refresh error.
An event signal is output regardless of the OFS0.WDTRSTIRQS bit. An event signal can also be output when the next
interrupt source while the refresh error flag (IWDTSR.REFEF) or underflow flag (IWDTSR.UNDFF) is 1. For details,
see section 15, Event Link Controller (ELC).
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23.5
23.5.1
23. Independent Watchdog Timer (IWDT)
Usage Notes
Refresh Operations
While configuring the refresh time, consider variations in the range of errors given the accuracy of PCLKB and
IWDTCLK. Set values that ensure refreshing is possible.
23.5.2
Clock Division Ratio Setting
Satisfy the frequency of the peripheral module clock (PCLKB) 4 (the frequency of the count clock source after
division).
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24. USB 2.0 Full-Speed Module (USBFS)
24.
USB 2.0 Full-Speed Module (USBFS)
24.1
Overview
The MCU incorporates a USB 2.0 Full-Speed module (USBFS) and supports revision 1.2 of the Battery Charging
specification.
The USBFS is a USB controller that operates as a device controller. The module supports full-speed and low-speed
transfers as defined in the Universal Serial Bus (USB) 2.0 Specification. The USBFS has an internal USB transceiver and
supports control transfers, bulk transfers, and interrupt transfers.
The USBFS has buffer memory for data transfers, providing a maximum of five pipes. PIPE4 to PIPE7 can be assigned
any endpoint number based on the peripheral devices or the communication requirements for your system.
Table 24.1 lists the USBFS specifications, Figure 24.1 shows the block diagram, and Table 24.2 lists the I/O pins.
Table 24.1
USBFS specifications
Parameter
Specifications
Features
USB Device Controller (UDC) and USB 2.0 transceiver supporting device controller (one
channel)
Self-power mode or bus power mode can be selected
Revision 1.2 of battery charging specification is supported
The USB LDO regulator is used to power the internal USB transceiver.
Full-speed transfer (12 Mbps) and low-speed transfer (1.5 Mbps) are supported
Control transfer stage control function
Device state control function
Auto response function for SET_ADDRESS request
SOF interpolation function.
Communication data transfer type
Control transfer
Bulk transfer
Interrupt transfer.
Pipe configuration
Buffer memory for USB communication
Up to five pipes can be selected, including the default control pipe
PIPE4 to PIPE7 can be assigned any endpoint number.
Transfer conditions that can be set for each pipe:
PIPE0: Control transfer with 64-byte single buffer
PIPE4 and PIPE5: Bulk transfer with 64-byte double buffer
PIPE6 and PIPE7: Interrupt transfer with 64-byte single buffer.
Others
Module-stop function
Module-stop state can be set to reduce power consumption
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Reception end function using transaction count
Function that changes the BRDY interrupt event notification timing (BFRE)
NAK setting function for response PID generated on transfer end (SHTNAK)
On-chip pull-up and pull-down resistors of USB_DP/USB_DM
HOCO clock that can be used as USB clock.
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24. USB 2.0 Full-Speed Module (USBFS)
VCC_USB_LDO
USB LDO
Regulator
VCC_USB
BC
control
Battery charging
controller
LINK core
Bus interface controller
Registers
USB device
controller
USB_DP
Interrupt
controller
USB_DM
USB protocol
engine
Internal peripheral bus
Registers
FIFO buffer
controller
Memory
controller
FIFO
controller
PCLKB
USB transceiver
USB clock (48 MHz)
Figure 24.1
USBFS block diagram
Table 24.2
USBFS pin configuration
USB clock control
1-port SRAM
(16-bit width)
USB clock (48 MHz)
PCLKB
Port
Pin name
I/O
Function
USBFS
USB_DP
I/O
D+ I/O pin for the USB on-chip transceiver.
Must be connected to the D+ pin of the USB bus.
USB_DM
I/O
D– I/O pin for the USB on-chip transceiver.
Must be connected to the D– pin of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin.
Must be connected to VBUS on the USB bus. The VBUS pin status (connected or
disconnected) can be detected.*1
VCC_USB
I/O
Input: USB transceiver input supply voltage.
Output: USB LDO regulator output supply voltage. This pin must be connected to an
external capacitor.
VCC_USB_LDO
Input
USB LDO regulator input supply voltage
VSS_USB
Input
USB ground pin
Common
Note 1. P407 is 5-V tolerant.
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24.2
24. USB 2.0 Full-Speed Module (USBFS)
Register Descriptions
24.2.1
System Configuration Control Register (SYSCFG)
Address(es): USBFS.SYSCFG 4009 0000h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
—
—
—
—
—
SCKE
—
CNEN
—
—
—
0
0
0
0
0
0
0
0
0
0
0
b4
b3
b2
b1
b0
—
—
USBE
0
0
0
DPRPU DMRP
U
0
0
Bit
Symbol
Bit name
Description
R/W
b0
USBE
USBFS Operation Enable
0: USBFS operation disabled
1: USBFS operation enabled.
R/W
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0: Line pull-up disabled
1: Line pull-up enabled.
R/W
Control*1
b3
DMRPU
D- Line Resistor
b4
DPRPU
D+ Line Resistor Control*1
0: Disable line pull-up
1: Enable line pull-up.
R/W
b5 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
CNEN
CNEN Single-ended
Receiver Enable
0: Single end receiver operation disabled
1: Single end receiver operation enabled.
R/W
b9
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10
SCKE
USB Clock Enable*2
0: Stop clock supply to the USB
1: Enable clock supply to the USB.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. Do not enable the DMRPU and DPRPU bits at the same time.
Note 2. After writing 1 to the SCKE bit, read it and confirm it is set to 1.
USBE bit (USBFS Operation Enable)
The USBE bit enables or disables operation of the USBFS.
Changing the USBE bit from 1 to 0 initializes the bits listed in Table 24.3. Only change this bit while the SCKE bit is 1.
Table 24.3
Registers initialized by writing 0 to SYSCFG.USBE bit
Register
Bit
SYSSTS0
LNST[1:0]
DVSTCTR0
RHST[2:0]
INTSTS0
DVSQ[2:0]
USBREQ
BREQUEST[7:0], BMREQUESTTYPE[7:0]
USBVAL
WVALUE[15:0]
USBINDX
WINDEX[15:0]
USBLENG
WLENTUH[15:0]
DMRPU bit (D- Line Resistor Control*1)
The DMRPU bit enables or disables pulling up the D- line.
When the DMRPU bit is set to 1, the bit forces a pull-up of the D– line to notify the USB host that it attached as a lowspeed device. Changing the DMRPU bit from 1 to 0 allows the USB to release the D– line, thereby notifying the USB
host that it detached.
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24. USB 2.0 Full-Speed Module (USBFS)
DPRPU bit (D+ Line Resistor Control*1)
The DPRPU bit enables or disables pulling up the D+ line.
When the DPRPU bit is set to 1, the bit forces a pull-up of the D+ line to notify the USB host that it attached. Changing
the DPRPU bit from 1 to 0 allows the USB to release the D+ line, thereby notifying the USB host that it detached.
CNEN bit (CNEN Single-ended Receiver Enable)
Setting the CNEN bit to 1 allows the USBFS to enable the single-ended receiver and set the LNST bit to monitor the
status of the D+ and D– lines.
The CNEN bit is used when the USBFS operates as a portable device for battery charging.
SCKE bit (USB Clock Enable*2)
The SCKE bit stops or enables supplying 48-MHz clock signal to the USBFS.
When this bit is 0, only SYSCFG can be read from and written to. No other USBFS-related registers can be read from or
written to.
24.2.2
System Configuration Status Register 0 (SYSSTS0)
Address(es): USBFS.SYSSTS0 4009 0004h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LNST[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
b0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
LNST[1:0]
USB Data Line Status Monitor
Indicates the status of the USB data lines, see Table 24.4
R
b15 to b2
—
Reserved
These bits are read as 0 and cannot be modified
R
LNST[1:0] bits (USB Data Line Status Monitor)
The LNST[1:0] bits indicate the state of the USB data lines (D+ and D– lines). For details, see Table 24.4.
The LNST[1:0] bits should be read after connection processing (SYSCFG.DPRPU bit = 1).
Table 24.4
Status of USB data bus lines (D+ Line, D– Line)
LNST[1:0] bits
During full-speed operation
During low-speed operation
00b
SE0
SE0
01b
J-State
K-State
10b
K-State
J-State
11b
SE1
SE1
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24.2.3
24. USB 2.0 Full-Speed Module (USBFS)
Device State Control Register 0 (DVSTCTR0)
Address(es): USBFS.DVSTCTR0 4009 0008h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
—
—
—
—
—
—
—
WKUP
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
b2
b1
b0
RHST[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
RHST[2:0]
USB Bus Reset Status
b2
R
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
WKUP
Wakeup Output
0: Remote wakeup signal is not output
1: Remote wakeup signal is output.
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b0
0 0 0: Communication speed not determined
0 0 1: USB bus reset in progress or low-speed connection
0 1 0: USB bus reset in progress or full-speed connection
RHST[2:0] bits (USB Bus Reset Status)
The RHST[2:0] bits indicate the status of the USB bus reset.
When the USBFS detects a USB bus reset, the RHST[2:0] bits indicate 010b if the DPRPU bit is 1 or 001b if the
DMRPU bit is 1, and a DVST interrupt is generated.
WKUP bit (Wakeup Output)
The WKUP bit enables or disables remote wakeup signals (resume signals) to the USB bus.
The USBFS controls the output timing of the remote wakeup signals. When this bit is set to 1, the USBFS sets this bit to
0 after outputting the K-state for 10 ms. The USB 2.0 specification specifies that the USB bus idle state must be kept for
5 ms or longer before a remote wakeup signal is sent. If the USB writes 1 to this bit immediately after detecting the
suspended state, the K-state is output after 2 ms.
Only write 1 to this bit when the device is in the suspended state (INTSTS0.DVSQ[2:0] bits = 1xxb) and the USB host
enables the remote wakeup signal. Do not stop the internal clock while this bit is 1, even in the suspended state
(SYSCFG.SCKE bit is 1).
24.2.4
CFIFO Port Register (CFIFO/CFIFOL)
(1) When the MBW bit is 1
Address(es): USBFS.CFIFO 4009 0014h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
FIFOPORT[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
(2) When the MBW bit is 0
Address(es): USBFS.CFIFOL 4009 0014h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
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24. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b15 to b0
FIFOPORT[15:0]
FIFO Port
The valid bits in a FIFO port register depend on the MBW setting
(CFIFOSEL.MBW) and BIGEND setting (CFIFOSEL.BIGEND) as
shown in Table 24.5 and Table 24.6
R/W
CFIFO is configured with:
A port register (CFIFO) that handles reading of data from the FIFO buffer and writing of data to the FIFO buffer
A port select register (CFIFOSEL) that selects the pipe assigned to the FIFO port
A port control register (CFIFOCTR).
CFIFO has the following constraints:
Access to the FIFO buffer for DCP control transfers is through the CFIFO port
There are two FIFO buffer states, one giving access rights to the CPU and the other to the serial interface engine
(SIE). When the SIE has access rights, the FIFO buffer cannot be accessed by the CPU.
The FIFO buffer cannot be accessed by the DTC.
FIFOPORT[15:0] bits (FIFO Port)
When the FIFOPORT[15:0] bit is accessed, the USBFS reads the received data from the FIFO buffer or writes the
transmit data to the FIFO buffer.
The FIFO port register can be accessed only when the FRDY bit in the port control register (CFIFOCTR) is 1. The valid
bits in the FIFO port register depend on the MBW and BIGEND settings in the port select register (CFIFOSEL). See
Table 24.5 and Table 24.6.
Table 24.5
Endian operation in 16-bit access
CFIFOSEL.BIGEND Bit
Bits 15 to 8
Bits 7 to 0
0
N + 1 data
N + 0 data
1
N + 0 data
N + 1 data
Table 24.6
Endian operation in 8-bit access
CFIFOSEL.BIGEND Bit
Bits 15 to 8
Bits 7 to 0
0
Access prohibited*1
N + 0 data
1
Access prohibited*1
N + 0 data
Note 1. Reading from or writing to an access-prohibited area is not allowed.
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24.2.5
24. USB 2.0 Full-Speed Module (USBFS)
CFIFO Port Select Register (CFIFOSEL)
Address(es): USBFS.CFIFOSEL 4009 0020h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
RCNT
REW
—
—
—
MBW
—
BIGEN
D
—
—
ISEL
—
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
b3
b2
b1
b0
CURPIPE[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
CURPIPE
[3:0]
CFIFO Port Access Pipe Specification
b3
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
ISEL
CFIFO Port Access Direction When
DCP is Selected
0: Reading from the buffer memory selected
1: Writing to the buffer memory selected.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
BIGEND
CFIFO Port Endian Control
0: Little endian
1: Big endian.
R/W
b9
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b10
MBW
CFIFO Port Access Bit Width
0: 8-bit width
1: 16-bit width.
R/W
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
REW
Buffer Pointer Rewind
0: The buffer pointer is not rewound
1: The buffer pointer is rewound.
R/W*1
b15
RCNT
Read Count Mode
0: The DTLN[8:0] bits are cleared when all received data
is read from the CFIFO.
In double buffer mode, the DTLN[8:0] bit value is
cleared when all data is read from only a single plane.
1: The DTLN[8:0] bits are decremented each time the
received data is read from the CFIFO.
R/W
b0
0 0 0 0: DCP (default control pipe)
0 1 0 0: Pipe 4
0 1 0 1: Pipe 5
0 1 1 0: Pipe 6
0 1 1 1: Pipe 7.
Other settings are prohibited.
Note 1. Only 0 can be read.
CURPIPE[3:0] bits (CFIFO Port Access Pipe Specification)
The CURPIPE[3:0] bits specify the pipe number to use for reading or writing data through the CFIFO port. After writing
to these bits, read them to check that the written value agrees with the read value before proceeding to the next process.s
During FIFO buffer access, even when an attempt is made to change the CURPIPE[3:0] setting, the current access setting
is retained until access is complete.
ISEL bit (CFIFO Port Access Direction When DCP is Selected)
After writing a new value to the ISEL bit with the DCP as the selected pipe, read this bit to check that the written value
agrees with the read value before proceeding to the next process. Set this bit and the CURPIPE[3:0] bits simultaneously.
MBW bit (CFIFO Port Access Bit Width)
The MBW bit specifies the bit width for accessing the CFIFO port.
When the selected pipe is receiving, set the CURPIPE[3:0] bits and MBW bits simultaneously. After a write to these bits
starts a data read from the FIFO buffer, do not change the bits until all the data is read. When you read the FIFO buffer,
read with the access size set in MBW.
When the selected pipe is transmitting, the bit width cannot be changed from 8-bit width to 16-bit width while data is
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24. USB 2.0 Full-Speed Module (USBFS)
written to the buffer memory.
An odd number of bytes can also be written through byte-access control even when 16-bit width is selected.
REW bit (Buffer Pointer Rewind)
The REW bit specifies whether to rewind the buffer pointer.
When the selected pipe is receiving, setting the REW bit to 1 while the FIFO buffer is being read allows re-reading of the
FIFO buffer from the first data. In double buffering, this setting enables re-reading of the currently-read FIFO buffer
plane from the first entry.
Do not set the REW bit to 1 while simultaneously changing the CURPIPE[3:0] bits. Before setting the REW bit to 1, be
sure to check that the FRDY bit is 1.
To rewrite to the FIFO buffer from the first data for the transmitting pipe, use the BCLR bit.
24.2.6
CFIFO Port Control Register (CFIFOCTR)
Address(es): USBFS.CFIFOCTR 4009 0022h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
BVAL
BCLR
FRDY
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
DTLN[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
DTLN[8:0]
Receive Data Length
Indicate the length of the received data. These bits indicate different
values depending on the setting of the RCNT bit in the port select
register. For details, see the description of the DTLN[8:0] bits shown
in this section.
R
b12 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13
FRDY
FIFO Port Ready
0: FIFO port access disabled
1: FIFO port access enabled.
R
b14
BCLR
CPU Buffer Clear
0: Does not operate
1: Clears the buffer memory on the CPU side.
R/W*1
b15
BVAL
Buffer Memory Valid Flag
0: Invalid
1: Writing ended.
R/W
Note 1. Only 0 can be read.
DTLN[8:0] bits (Receive Data Length)
The DTLN[8:0] bits indicate the length of the received data.
While the FIFO buffer is being read, the DTLN[8:0] bits indicate different values depending on the CFIFOSEL.RCNT
bit (n = 0, 1) value as follows:
RCNT = 0:
The USBFS sets the DTLN[8:0] bits to indicate the length of the received data until the CPU has read all the
received data from a single FIFO buffer plane.
While the PIPECFG.BFRE bit = 1, these bits retain the length of the received data until the BCLR bit is set to 1
even after all the data is read.
RCNT = 1:
The USBFS decrements the value indicated in the DTLN[8:0] bits each time data is read from the FIFO buffer. The
value is decremented by 1 when MBW = 0, and by 2 when MBW = 1.
The USBFS sets these bits to 0 when all the data is read from one FIFO buffer plane. However, in double buffer
mode, if data is received in one FIFO buffer plane before all the data is read from the other plane, the USBFS sets
these bits to indicate the length of the received data in the former plane when all the data is read from the latter
plane.
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24. USB 2.0 Full-Speed Module (USBFS)
FRDY bit (FIFO Port Ready)
The FRDY bit indicates whether the FIFO port can be accessed by the CPU.
In the following cases, the USBFS sets the FRDY bit to 1 but data cannot be read by the FIFO port because there is no
data to be read. In these cases, set the BCLR bit to 1 to clear the FIFO buffer, and enable transmission and reception of
the next data.
A zero-length packet is received when the FIFO buffer assigned to the selected pipe is empty
A short packet is received and the data is completely read while the PIPECFG.BFRE bit = 1.
BCLR bit (CPU Buffer Clear)
Set the BCLR bit to 1 to clear the FIFO buffer on the CPU for the selected pipe.
When double buffer mode is set for the FIFO buffer assigned to the selected pipe, the USBFS clears only one plane of the
FIFO buffer even when both planes are read-enabled.
When the DCP is the selected pipe, setting the BCLR bit to 1 allows the USBFS to clear the FIFO buffer regardless of
whether the CPU or SIE has access rights. To clear the buffer when the SIE has access rights, set the DCPCTR.PID[1:0]
bits to 00b (NAK response) before setting the BCLR bit to 1.
When the selected pipe is transmitting, if 1 is written to the BVAL flag and the BCLR bit simultaneously, the USBFS
clears the data that is already written, enabling transmission of a zero-length packet.
When the selected pipe is not the DCP, only write 1 to the BCLR bit while the FRDY bit in the FIFO port control register
is 1 (set by the USBFS).
BVAL flag (Buffer Memory Valid Flag)
Set the BVAL flag to 1 when data is completely written to the FIFO buffer on the CPU for the pipe selected in
CURPIPE[3:0].
When the selected pipe is transmitting, set this flag to 1 in the following cases:
To transmit a short packet, set this flag to 1 after data is written
To transmit a zero-length packet, set this flag to 1 before data is written to the FIFO buffer.
The USBFS then switches the FIFO buffer from the CPU to the SIE, enabling transmission.
When data of the maximum packet size is written for the pipe in continuous transfer mode, the USBFS sets the BVAL
flag to 1 and switches the FIFO buffer from the CPU to the SIE, enabling transmission.
Only write 1 to the BVAL flag while the FRDY bit is 1 (set by the USBFS). When the selected pipe is receiving, do not
set the BVAL flag to 1.
24.2.7
Interrupt Enable Register 0 (INTENB0)
Address(es): USBFS.INTENB0 4009 0030h
b15
b14
b13
b12
VBSE
RSME
SOFE
DVSE
0
0
0
0
Value after reset:
b11
b10
b9
b8
CTRE BEMPE NRDYE BRDYE
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
These bits are read as 0. The write value
should be 0.
R/W
b8
BRDYE
Buffer Ready Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b9
NRDYE
Buffer Not Ready Response Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
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24. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b10
BEMPE
Buffer Empty Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b11
CTRE
Control Transfer Stage Transition Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b12
DVSE
Device State Transition Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b13
SOFE
Frame Number Update Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b14
RSME
Resume Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b15
VBSE
VBUS Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
When a status flag in the INTSTS0 register is set to 1 and the associated interrupt request enable bit setting in the
INTENB0 register is 1, the USBFS issues a USBFS interrupt request.
Regardless of the INTENB0 register setting, the status flag in the INTSTS0 register is set to 1 in response to a state
change that satisfies the associated condition.
When an interrupt request enable bit in the INTENB0 register is switched from 0 to 1 while the associated status flag in
the INTSTS0 register is set to 1, a USBFS interrupt is requested.
24.2.8
BRDY Interrupt Enable Register (BRDYENB)
Address(es): USBFS.BRDYENB 4009 0036h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
PIPE7B PIPE6B PIPE5B PIPE4B
RDYE RDYE RDYE RDYE
0
0
0
0
b3
b2
b1
b0
—
—
—
PIPE0B
RDYE
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BRDYE
BRDY Interrupt Enable for PIPE0
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
PIPE4BRDYE
BRDY Interrupt Enable for PIPE4
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b5
PIPE5BRDYE
BRDY Interrupt Enable for PIPE5
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b6
PIPE6BRDYE
BRDY Interrupt Enable for PIPE6
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b7
PIPE7BRDYE
BRDY Interrupt Enable for PIPE7
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
BRDYENB enables or disables the INTSTS0.BRDY bit to be set to 1 when the BRDY interrupt is detected for each
pipe.
On detecting the BRDY interrupt for the pipe associated with the bit in BRDYENB to which 1 is set by software, the
USBFS sets 1 to the associated BRDYSTS.PIPEnBRDY bit (n = 0, 4 to 7) and the INTSTS0.BRDY bit. If
INTENB0.BRDYE = 1 at this time, the USBFS generates the BRDY interrupt request.
While at least one PIPEnBRDY bit indicates 1, the USBFS generates the BRDY interrupt request when the
corresponding interrupt enable bit in BRDYENB is modified from 0 to 1 by software.
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24.2.9
24. USB 2.0 Full-Speed Module (USBFS)
NRDY Interrupt Enable Register (NRDYENB)
Address(es): USBFS.NRDYENB 4009 0038h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
PIPE7N PIPE6N PIPE5N PIPE4N
RDYE RDYE RDYE RDYE
0
0
0
0
b3
b2
b1
b0
—
—
—
PIPE0N
RDYE
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0NRDYE
NRDY Interrupt Enable for PIPE0
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
PIPE4NRDYE
NRDY Interrupt Enable for PIPE4
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b5
PIPE5NRDYE
NRDY Interrupt Enable for PIPE5
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b6
PIPE6NRDYE
NRDY Interrupt Enable for PIPE6
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b7
PIPE7NRDYE
NRDY Interrupt Enable for PIPE7
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
NRDYENB enables or disables the INTSTS0.NRDY bit to be set to 1 when the NRDY interrupt is detected for each
pipe.
On detecting the NRDY interrupt for the pipe associated with the bit in NRDYENB to which 1 is set by software, the
USBFS sets 1 to the associated NRDYSTS.PIPEnNRDY bit (n = 0, 4 to 7) and the INTSTS0.NRDY bit. If
INTENB0.NRDYE is 1 at this time, the USBFS generates the NRDY interrupt request.
While at least one PIPEnNRDY bit indicates 1, the USBFS generates the NRDY interrupt request when the associated
interrupt enable bit in NRDYENB is modified from 0 to 1 by software.
24.2.10
BEMP Interrupt Enable Register (BEMPENB)
Address(es): USBFS.BEMPENB 4009 003Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
PIPE7B PIPE6B PIPE5B PIPE4B
EMPE EMPE EMPE EMPE
0
0
0
0
b3
b2
b1
b0
—
—
—
PIPE0B
EMPE
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BEMPE
BEMP Interrupt Enable for PIPE0
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
PIPE4BEMPE
BEMP Interrupt Enable for PIPE4
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b5
PIPE5BEMPE
BEMP Interrupt Enable for PIPE5
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b6
PIPE6BEMPE
BEMP Interrupt Enable for PIPE6
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b7
PIPE7BEMPE
BEMP Interrupt Enable for PIPE7
0: Interrupt output disabled
1: Interrupt output enabled.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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24. USB 2.0 Full-Speed Module (USBFS)
BEMPENB enables or disables the INTSTS0.BEMP bit to be set to 1 when the BEMP interrupt is detected for each pipe.
On detecting the BEMP interrupt for the pipe associated with the bit in BEMPENB to which 1 is set by software, the
USBFS sets 1 to the associated BEMPSTS.PIPEnBEMP bit (n = 0, 4 to 7) and the INTSTS0.BEMP bit. If
INTENB0.BEMPE = 1 at this time, the USBFS generates the BEMP interrupt request.
While at least one PIPEnBEMP bit in BEMPSTS indicates 1, the USBFS generates the BEMP interrupt request when the
associated interrupt enable bit in BEMPENB is modified from 0 to 1 by software.
24.2.11
SOF Output Configuration Register (SOFCFG)
Address(es): USBFS.SOFCFG 4009 003Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
BRDY
M
—
EDGES
TS
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Indicates 1 when the edge interrupt output signal is in
the middle of edge processing.
R
Monitor *1
b4
EDGESTS
Edge Interrupt Output Status
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
BRDYM
BRDY Interrupt Status Clear Timing
0: Software clears the status
1: The USBFS clears the status when data is read from
the FIFO buffer or data is written to the FIFO buffer.
R/W
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. Confirm that this bit is 0 before stopping the clock supply to the USBFS.
EDGESTS bit (Edge Interrupt Output Status Monitor)
The EDGESTS bit indicates 1 when the edge interrupt output signal is in the middle of edge processing. Confirm that
this bit is 0 before stopping the clock supply to the USBFS.
BRDYM bit (BRDY Interrupt Status Clear Timing)
The BRDYM bit specifies the timing for clearing the BRDY interrupt status for each pipe.
24.2.12
Interrupt Status Register 0 (INTSTS0)
Address(es): USBFS.INTSTS0 4009 0040h
b15
b14
VBINT RESM
Value after reset:
0
0
b13
b12
b11
b10
b9
SOFR
DVST
CTRT
BEMP
NRDY
0
0/1*1
0
0
0
b8
b7
b6
BRDY VBSTS
0
0*2
b5
b4
DVSQ[2:0]
0*3
0*3
b3
b2
VALID
0/1*3
0
b1
b0
CTSQ[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CTSQ[2:0]
Control Transfer Stage
b2
R
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b0
0 0 0: Idle or setup stage
0 0 1: Control read data stage
0 1 0: Control read status stage
0 1 1: Control write data stage
1 0 0: Control write status stage
1 0 1: Control write (no data) status stage
1 1 0: Control transfer sequence error.
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24. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b3
VALID
USB Request Reception
0: Setup packet is not received
1: Setup packet is received.
R/W*4
b6 to b4
DVSQ[2:0]
Device State
b6
R
b7
VBSTS
VBUS Input Status
0: USB_VBUS pin is low
1: USB_VBUS pin is high.
R
b8
BRDY
Buffer Ready Interrupt Status
0: BRDY interrupts are not generated
1: BRDY interrupts are generated.
R
b9
NRDY
Buffer Not Ready Interrupt
Status
0: NRDY interrupts are not generated
1: NRDY interrupts are generated.
R
b10
BEMP
Buffer Empty Interrupt Status
0: BEMP interrupts are not generated
1: BEMP interrupts are generated.
R
b11
CTRT
Control Transfer Stage
Transition Interrupt Status
0: Control transfer stage transition interrupts are not generated
1: Control transfer stage transition interrupts are generated.
R/W*4
b12
DVST
Device State Transition
Interrupt Status
0: Device state transition interrupts are not generated
1: Device state transition interrupts are generated.
R/W*4
b13
SOFR
Frame Number Refresh
Interrupt Status
0: SOF interrupts are not generated
1: SOF interrupts are generated.
R/W*4
b14
RESM
Resume Interrupt Status *5
0: Resume interrupts are not generated
1: Resume interrupts are generated.
R/W*4
b15
VBINT
VBUS Interrupt Status *5
0: VBUS interrupts are not generated
1: VBUS interrupts are generated.
R/W*4
b4
0 0 0: Powered state
0 0 1: Default state
0 1 0: Address state
0 1 1: Configured state
1 x x: Suspended state.
x: Don’t care
Note 1.
Note 2.
Note 3.
Note 4.
The value is 0 when the MCU is reset and 1 after a USB bus reset.
The value is 1 when the USB_VBUS pin is high and 0 when the USB_VBUS pin is low.
The value is 000b when the MCU is reset and 001b after a USB bus reset.
To clear the VBINT, RESM, SOFR, DVST, CTRT, or VALID bit, write 0 only to the bits to be cleared. Write 1 to
the other bits. Do not write 0 to the status bits indicating 0.
Note 5. A change in the status indicated by the VBINT and RESM bits can be detected even while the clock supply is
stopped (the SCKE bit is 0), and the interrupts are output when the corresponding interrupt enable bits are
enabled. Clear the status through software after enabling the clock supply.
DVSQ[2:0] bits (Device State)
The DVSQ[2:0] bits are initialized by a USB bus reset.
BRDY bit (Buffer Ready Interrupt Status)
The BRDY bit indicates the BRDY interrupt status.
The USBFS sets the BRDY bit to 1 when at least one PIPEnBRDY bit (n = 0, 4 to 7) is set to 1 from the PIPEBRDY bits.
These bits correspond to the BRDYENB.PIPEnBRDYE bits (n = 0, 4 to 7) to which 1 is set when the USBFS detects the
BRDY interrupt status in at least one pipe in the pipes for which the BRDY interrupt output is enabled by software.
For the conditions for PIPEnBRDY status assertion, see section 24.3.3.1, BRDY interrupt.
The USBFS sets the BRDY bit to 0 when 0 is written by software to all the PIPEnBRDY bits associated with the
PIPEnBRDYE bits that are set to 1. The BRDY bit cannot be set to 0 even if 0 is written to this bit by software.
NRDY bit (Buffer Not Ready Interrupt Status)
The USBFS sets the NRDY bit to 1 when at least one PIPEnNRDY bit (n = 0, 4 to 7) is set to 1 from the PIPENRDY
bits. These bits correspond to the PIPEnNRDYE bits (n = 0, 4 to 7) to which 1 is set when the USBFS detects the NRDY
interrupt status in at least one pipe in the pipes for which software enables the NRDY interrupt output.
For the conditions for PIPEnNRDY status assertion, see section 24.3.3.2, NRDY interrupt.
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24. USB 2.0 Full-Speed Module (USBFS)
The USBFS sets the NRDY bit to 0 when 0 is written by software to all the PIPEnNRDY bits that correspond to the
PIPEnNRDYE bits that are set to 1. The NRDY bit cannot be set to 0 even if 0 is written to this bit by software.
BEMP bit (Buffer Empty Interrupt Status)
The USBFS sets the BEMP bit to 1 when at least one PIPEnBEMP bit (n = 0, 4 to 7) is set to 1 in the PIPEnBEMP bits.
These bits correspond to the PIPEnBEMPE bits (n = 0, 4 to 7) to which 1 is set when the USBFS detects the BEMP
interrupt status in at least one pipe from the pipes for which the BEMP interrupt output is enabled by software.
For the conditions for PIPEnBEMP status assertion, see section 24.3.3.3, BEMP interrupt.
The USBFS sets the BEMP bit to 0 when 0 is written by software to all the PIPEnBEMP bits that correspond to the
PIPEnBEMPE bits that are set to 1. The BEMP bit cannot be set to 0 even if 0 is written to this bit by software.
CTRT bit (Control Transfer Stage Transition Interrupt Status)
The USBFS updates the value of the CTSQ[2:0] bits and sets the CTRT bit to 1 when detecting a change in the control
transfer stage.
When a control transfer stage transition interrupt is generated, clear the status before the USBFS detects the next control
transfer stage transition.
DVST bit (Device State Transition Interrupt Status)
The USBFS updates the DVSQ[2:0] value and sets the DVST bit to 1 when detecting a change in the device state.
When a device state transition interrupt is generated, clear the status before the USBFS detects the next device state
transition.
SOFR bit (Frame Number Refresh Interrupt Status)
The USBFS sets the SOFR bit to 1 when updating the frame number. A frame number refresh interrupt is detected every
1 ms.
The USBFS can detect an SOFR interrupt through the internal interpolation function even when a damaged SOF packet
is received from the USB host.
RESM bit (Resume Interrupt Status)
The USBFS sets the RESM bit to 1 when detecting the falling edge of the signal on the USB_DP pin in the suspended
state (DVSQ[2:0] = 1xxb).
VBINT bit (VBUS Interrupt Status)
The USBFS sets the VBINT bit to 1 when detecting a level change (high to low or low to high) in the USB_VBUS pin
input value. The USBFS sets the VBSTS bit to indicate the USB_VBUS pin input value. When the VBUS interrupt is
generated, use software to repeat the reading of the VBSTS bit until the same value is read three or more times to
eliminate chattering.
24.2.13
BRDY Interrupt Status Register (BRDYSTS)
Address(es): USBFS.BRDYSTS 4009 0046h
Value after reset:
Bit
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Symbol
Bit name
b0
PIPE0BRDY
BRDY Interrupt Status for
b3 to b1
—
Reserved
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PIPE0*2
b7
b6
b5
b4
PIPE7B PIPE6B PIPE5B PIPE4B
RDY
RDY
RDY
RDY
0
0
0
0
b3
b2
b1
b0
—
—
—
PIPE0B
RDY
0
0
0
0
Description
R/W
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
These bits are read as 0. The write value should be 0. R/W
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Bit
24. USB 2.0 Full-Speed Module (USBFS)
Symbol
Bit name
Description
R/W
PIPE4*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b4
PIPE4BRDY
BRDY Interrupt Status for
b5
PIPE5BRDY
BRDY Interrupt Status for PIPE5*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b6
PIPE6BRDY
BRDY Interrupt Status for PIPE6*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b7
PIPE7BRDY
BRDY Interrupt Status for PIPE7*2
0: Interrupts are not generated
1: Interrupts are generated.
R/W
*1
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0. R/W
Note 1. When the SOFCFG.BRDYM bit is set to 0, to clear the status indicated by the bits in BRDYSTS, write 0 only to
the bits to be cleared. Write 1 to the other bits.
Note 2. When the SOFCFG.BRDYM bit is set to 0, clear the BRDY interrupts before accessing the FIFO.
24.2.14
NRDY Interrupt Status Register (NRDYSTS)
Address(es): USBFS.NRDYSTS 4009 0048h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
PIPE7N PIPE6N PIPE5N PIPE4N
RDY
RDY
RDY
RDY
0
0
0
0
b3
b2
b1
b0
—
—
—
PIPE0N
RDY
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0NRDY
NRDY Interrupt Status for PIPE0
0: Interrupts are not generated
1: Interrupts are generated.
*1
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
PIPE4NRDY
NRDY Interrupt Status for PIPE4
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
b5
b6
b7
b15 to b8
PIPE5NRDY
PIPE6NRDY
PIPE7NRDY
—
NRDY Interrupt Status for PIPE5
NRDY Interrupt Status for PIPE6
NRDY Interrupt Status for PIPE7
Reserved
R/W
R/W
R/W
R/W
These bits are read as 0. The write value should be 0. R/W
Note 1. To clear the status indicated by the bits in NRDYSTS, write 0 only to the bits to be cleared. Write 1 to the other
bits.
24.2.15
BEMP Interrupt Status Register (BEMPSTS)
Address(es): USBFS.BEMPSTS 4009 004Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
b7
b6
b5
b4
PIPE7B PIPE6B PIPE5B PIPE4B
EMP
EMP
EMP
EMP
0
0
0
0
b3
b2
b1
b0
—
—
—
PIPE0B
EMP
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
PIPE0BEMP
BEMP Interrupt Status for PIPE0
0: Interrupts are not generated
1: Interrupts are generated.
*1
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24. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
PIPE4BEMP
BEMP Interrupt Status for PIPE4
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
0: Interrupts are not generated
1: Interrupts are generated.
*1
b5
PIPE5BEMP
b6
BEMP Interrupt Status for PIPE5
PIPE6BEMP
b7
BEMP Interrupt Status for PIPE6
PIPE7BEMP
b15 to b8
BEMP Interrupt Status for PIPE7
—
Reserved
R/W
R/W
R/W
R/W
R/W
These bits are read as 0. The write value should be 0. R/W
Note 1. To clear the status indicated by the bits in BEMPSTS, write 0 only to the bits to be cleared. Write 1 to the other
bits.
24.2.16
Frame Number Register (FRMNUM)
Address(es): USBFS.FRMNUM 4009 004Ch
Value after reset:
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
FRNM[10:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
FRNM[10:0]
Frame Number
Latest frame number
R
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
FRNM[10:0] bits (Frame Number)
The FRNM[10:0] bits indicate the latest frame number for the USBFS after the issuing of an SOF packet every 1 ms or
writing to the FRNM[10:0] bits at the SOF packet reception.
24.2.17
USB Request Type Register (USBREQ)
Address(es): USBFS.USBREQ 4009 0054h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
BREQUEST[7:0]
Value after reset:
Bit
0
0
0
Symbol
0
0
b4
b3
b2
b1
b0
0
0
BMREQUESTTYPE[7:0]
0
0
0
0
0
0
0
0
0
Bit name
Description
R/W
b7 to b0
BMREQUESTTYPE[7:0]
Request Type
These bits store the USB request bmRequestType value
R
b15 to b8
BREQUEST[7:0]
Request
These bits store the USB request bRequest value
R
USBREQ stores setup requests for control transfers.
The received values of bRequest and bmRequestType are stored.
USBREQ is initialized by a USB bus reset.
BMREQUESTTYPE[7:0] bits (Request Type)
The BMREQUESTTYPE[7:0] bits hold the value of the bmRequestType field of a USB request.
These bits indicate the value of the USB request data in the setup transactions for reception. Writing to these bits has no
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24. USB 2.0 Full-Speed Module (USBFS)
effect.
BREQUEST[7:0] bits (Request)
The BREQUEST[7:0] bits store the bRequest value of the USB request.
These bits indicate the value of the USB request data in setup transactions for reception. Writing to these bits has no
effect.
24.2.18
USB Request Value Register (USBVAL)
Address(es): USBFS.USBVAL 4009 0056h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WVALUE[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WVALUE[15:0]
Value
These bits store the USB request wValue value
R
The received value of wValue is stored in USBVAL. USBVAL is initialized by a USB bus reset.
WVALUE[15:0] bits (Value)
The WVALUE[15:0] bits store the wValue value of the USB request.
These bits indicate the value of the wValue field in USB requests received in setup transactions for reception. Writing to
the WVALUE[15:0] bits has no effect.
24.2.19
USB Request Index Register (USBINDX)
Address(es): USBFS.USBINDX 4009 0058h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WINDEX[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WINDEX[15:0]
Index
These bits store the USB request wIndex value
R
USBINDX stores setup requests for control transfers. The received value of wIndex is stored.
USBINDX is initialized by a USB bus reset.
WINDEX[15:0] bits (Index)
The WINDEX[15:0] bits hold the value of the wIndex field of a USB request.
These bits indicate the value of the wIndex field in USB requests received in setup transactions for reception. Writing to
the WINDEX[15:0] bits has no effect.
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24.2.20
24. USB 2.0 Full-Speed Module (USBFS)
USB Request Length Register (USBLENG)
Address(es): USBFS.USBLENG 4009 005Ah
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
WLENTUH[15:0]
0
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
WLENTUH[15:0]
Length
These bits store the USB request wLength value
R
USBLENG stores setup requests for control transfers. The received value of wLength is stored.
USBLENG is initialized by a USB bus reset.
WLENTUH[15:0] bits (Length)
The WLENTUH[15:0] bits hold the value of the wLength field of a USB request.
These bits indicate the value of the wLength field in USB requests received in setup transactions for reception. Writing to
the WLENTUH[15:0] bits has no effect.
24.2.21
DCP Configuration Register (DCPCFG)
Address(es): USBFS.DCPCFG 4009 005Ch
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
SHTNA
K
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
SHTNAK
Pipe Disabled at End of Transfer *1
0: Pipe continued at the end of transfer
1: Pipe disabled at the end of transfer.
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0. R/W
R/W
Note 1. Modify this bit while PID is NAK. Before changing this bit after modifying the DCPCTR.PID[1:0] bits for the DCP
from BUF to NAK, check that the DCPCTR.PBUSY bit is 0. However, if the USB changes the PID[1:0] bits to
NAK, checking the PBUSY bit through software is not required.
SHTNAK bit (Pipe Disabled at End of Transfer)
The SHTNAK bit specifies whether to modify PID to NAK upon the end of transfer when the selected pipe is receiving.
The SHTNAK bit is valid when the selected pipe is receiving.
When the SHTNAK bit is set to 1, the USBFS modifies the DCPCTR.PID[1:0] bits for the DCP to NAK on determining
the end of the transfer. The USB determines that the transfer has ended on the following condition:
A short packet (including a zero-length packet) is successfully received.
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24.2.22
24. USB 2.0 Full-Speed Module (USBFS)
DCP Maximum Packet Size Register (DCPMAXP)
Address(es): USBFS.DCPMAXP 4009 005Eh
Value after reset:
Bit
b6 to b0
b15
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
Symbol
MXPS[6:0]
Bit name
Maximum Packet
Size*1
b6
b5
b4
b3
b2
b1
b0
0
0
0
MXPS[6:0]
1
0
0
0
Description
R/W
These bits set the maximum amount of data (maximum packet size)
in payloads for the DCP.
R/W
b6
b0
0 0 0 1 0 0 0: 8 bytes
0 0 1 0 0 0 0: 16 bytes
0 0 1 1 0 0 0: 24 bytes
0 1 0 0 0 0 0: 32 bytes
0 1 0 1 0 0 0: 40 bytes
0 1 1 0 0 0 0: 48 bytes
0 1 1 1 0 0 0: 56 bytes
1 0 0 0 0 0 0: 64 bytes
1 0 0 1 0 0 0: 72 bytes
1 0 1 0 0 0 0: 80 bytes
1 0 1 1 0 0 0: 88 bytes
1 1 0 0 0 0 0: 96 bytes
1 1 0 1 0 0 0: 104 bytes
1 1 1 0 0 0 0: 112 bytes
1 1 1 1 0 0 0: 120 bytes.
Other settings are prohibited.
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. Modify the MXPS[6:0] bits while PID is NAK. Before modifying these bits after modifying the DCPCTR.PID[1:0]
bits for the DCP from BUF to NAK, check that the DCPCTR.PBUSY bit is 0. However, if the USB changes the
PID[1:0] bits to NAK, checking the PBUSY bit through software is not required. After modifying the MXPS[6:0]
bits and the DCP is set to the CURPIPE[3:0] bits in the port select register, clear the buffer by setting the BCLR
bit in the port control register to 1.
MXPS[6:0] bits (Maximum Packet Size*1)
The MXPS[6:0] bits specify the maximum amount of data (maximum packet size) in payloads for the DCP. The initial
value of the bits is 40h (64 bytes).
Ensure that the setting of the MXPS[6:0] bits is in compliance with the USB 2.0 Specification. Do not write to the FIFO
buffer or set PID = BUF while the setting of the MXPS[6:0] bits is 0.
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24.2.23
24. USB 2.0 Full-Speed Module (USBFS)
DCP Control Register (DCPCTR)
Address(es): USBFS.DCPCTR 4009 0060h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
BSTS
—
—
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
SQCLR SQSET SQMO PBUSY
N
0
0
1
0
b4
b3
b2
—
—
CCPL
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b2
CCPL
Control Transfer End Enable
0: Invalid
1: Completion of control transfer is enabled.
R/W
b4, b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: DCP is not used for the transaction
1: DCP is used for the transaction.
R
b6
SQMON
Sequence Toggle Bit Monitor
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set*2
0: Invalid
1: Specifies DATA1.
R/W*1
b8
SQCLR
Sequence Toggle Bit Clear*2
0: Invalid
1: Specifies DATA0.
R/W*1
b14 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
BSTS
Buffer Status
0: Buffer access is disabled
1: Buffer access is enabled.
R
0
0
1
1
0: NAK response
1: BUF response (depending on the buffer state)
0: STALL response
1: STALL response.
Note 1. This bit is read as 0.
Note 2. Write 1 to the SQSET and SQCLR bits while PID is NAK. Before changing these bits after modifying the PID[1:0]
bits for the DCP from BUF to NAK, check that the PBUSY bit is 0. However, if the USB changes the PID[1:0] bits
to NAK, checking the PBUSY bit through software is not required.
PID[1:0] bits (Response PID)
The PID[1:0] bits control the response type of the USBFS during control transfer.
The USBFS modifies the setting of the PID[1:0] bits as follows:
The USBFS modifies the PID[1:0] bits to NAK on receiving the setup packet. The USBFS sets the
INTSTS0.VALID bit to 1. The setting of the PID[1:0] bits cannot be modified until the VALID bit is set to 0 by
software.
The USBFS sets PID to STALL (11b) on receiving data of a size that exceeds the maximum packet size when the
PID[1:0] bits are set to BUF by software
The USBFS sets PID to STALL (1xb) on detecting the control transfer sequence error
The USBFS sets PID to NAK on detecting the USB bus reset.
The USBFS does not check the setting of the PID[1:0] bits while the SET_ADDRESS request is processed.
The PID[1:0] bits are initialized by a USB bus reset.
CCPL bit (Control Transfer End Enable)
Setting the CCPL bit to 1 enables the status stage of the control transfer to be completed.
When the CCPL bit is set to 1 by software while the corresponding PID[1:0] bits are set to BUF, the USBFS completes
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24. USB 2.0 Full-Speed Module (USBFS)
the control transfer status stage.
During control read transfer, the USBFS transmits the ACK handshake in response to the OUT transaction from the USB
host, and transmits the zero-length packet in response to the IN transaction from the USB host during control write or nodata control transfer. However, on detecting the SET_ADDRESS request, the USBFS operates in auto response mode
from the setup stage up to status stage completion, irrespective of the setting of the CCPL bit.
The USBFS modifies the CCPL bit from 1 to 0 on receiving a new setup packet. A value of 1 cannot be written to the
CCPL bit by software while the INTSTS0.VALID bit is 1. The CCPL bit is initialized by a USB bus reset.
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether DCP is used for the transaction when the USB changes the PID[1:0] bits from BUF to
NAK.
The USBFS modifies the PBUSY bit from 0 to 1 at the start of the USB transaction for the selected pipe, and modifies
the PBUSY bit from 1 to 0 on completion of one transaction.
Reading the PBUSY bit after PID is set to NAK by software allows you to check whether modification of the pipe
settings is possible.
For details, see section 24.3.4.1, Pipe control register switching procedures.
SQMON bit (Sequence Toggle Bit Monitor)
The SQMON bit indicates the expected value of the sequence toggle bit for the next transaction during the DCP transfer.
The USBFS allows the SQMON bit to toggle on successful completion of the transaction. However, the SQMON bit is
not allowed to toggle when a DATA-PID mismatch occurs during the transfer in the receiving direction.
The USBFS sets the SQMON bit to 1 (specifies DATA1 as the expected value) on successful reception of the setup
packet.
The USBFS does not reference the SQMON bit during the IN/OUT transaction of the status stage, and does not allow the
SQMON bit to toggle on normal completion.
SQSET bit (Sequence Toggle Bit Set*2)
The SQSET bit specifies DATA1 as the expected value of the sequence toggle bit for the next transaction during the DCP
transfer.
Do not set the SQCLR and SQSET bits to 1 simultaneously.
SQCLR bit (Sequence Toggle Bit Clear*2)
The SQCLR bit specifies DATA0 as the expected value of the sequence toggle bit for the next transaction during the
DCP transfer. The SQCLR bit indicates 0.
Do not set the SQCLR and SQSET bits to 1 simultaneously.
BSTS bit (Buffer Status)
The BSTS bit indicates whether DCP FIFO buffer access is enabled or disabled.
The meaning of the BSTS bit varies according to the CFIFOSEL.ISEL setting as follows:
When the ISEL bit = 0, the BSTS bit indicates whether the received data can be read from the buffer
When the ISEL bit = 1, the BSTS bit indicates whether the data to be transmitted can be written to the buffer.
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24.2.24
24. USB 2.0 Full-Speed Module (USBFS)
Pipe Window Select Register (PIPESEL)
Address(es): USBFS.PIPESEL 4009 0064h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
PIPESEL[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
PIPESEL[3:0]
Pipe Window Select
b3
R/W
b15 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
b0
0 0 0 0: No pipe selected
0 1 0 0: PIPE4
0 1 0 1: PIPE5
0 1 1 0: PIPE6
0 1 1 1: PIPE7.
Other settings are prohibited.
R/W
Set PIPE4 to PIPE7 using PIPESEL, PIPECFG, PIPEMAXP, PIPEnCTR, PIPEnTRE, and PIPEnTRN.
After selecting the pipe with the PIPESEL register, set the pipe functions using PIPECFG and PIPEMAXP. The
PIPEnCTR, PIPEnTRE, and PIPEnTRN registers can be set independently of the pipe selection in the PIPESEL register.
PIPESEL[3:0] bits (Pipe Window Select)
The PIPESEL[3:0] bits select the pipe number associated with PIPECFG and PIPEMAXP that are used for data writing
and reading.
Selecting a pipe number through the PIPESEL[3:0] bits allows writing to and reading from PIPECFG and PIPEMAXP
associated with the selected pipe number.
When PIPESEL[3:0] = 0000b, 0 is read from all of the bits in PIPECFG and PIPEMAXP. Writing to these bits is invalid.
24.2.25
Pipe Configuration Register (PIPECFG)
Address(es): USBFS.PIPECFG 4009 0068h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
DIR
0
0
0
TYPE[1:0]
—
—
—
BFRE
DBLB
—
SHTNA
K
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
EPNUM[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
EPNUM[3:0]
Endpoint Number*1
These bits specify the endpoint number for the
selected pipe.
Setting 0000b means an unused pipe.
R/W
b4
DIR
Transfer Direction*2 *3
0: Receiving direction
1: Transmitting direction.
R/W
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b7
SHTNAK
Pipe Disabled at End of
b8
—
Reserved
Transfer*1
Mode*2 *3
b9
DBLB
Double Buffer
b10
BFRE
BRDY Interrupt Operation
Specification*2 *3
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0: Pipe assignment continued at transfer end
1: Pipe assignment disabled at transfer end.
R/W
This bit is read as 0. The write value should be 0.
R/W
0: Single buffer
1: Double buffer.
R/W
0: BRDY interrupt on transmitting or receiving data
1: BRDY interrupt on completion of reading data.
R/W
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24. USB 2.0 Full-Speed Module (USBFS)
Bit
Symbol
Bit name
Description
R/W
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b15, b14
TYPE[1:0]
Transfer Type*1
PIPE4 and PIPE5
R/W
b15 b14
0
0
1
1
0: Pipe not used
1: Bulk transfer
0: Setting prohibited
1: Setting prohibited.
PIPE6 and PIPE7
b15 b14
0
0
1
1
0: Pipe not used
1: Setting prohibited
0: Interrupt transfer
1: Setting prohibited.
Note 1. Only set the TYPE[1:0], SHTNAK, and EPNUM[3:0] bits while PID is NAK. Before setting these bits, check that
the PIPEnCTR.PBUSY bit is 0, then change the PIPEnCTR.PID[1:0] bits for the selected pipe from BUF to NAK.
However, if the USB changes the PID[1:0] bits to NAK, checking the PBUSY bit through software is not required.
Note 2. Only set the BFRE, DBLB, and DIR bits while PID is NAK and before the pipe is selected in the CURPIPE[3:0]
bits in the port select register. Before setting these bits, check that the PIPEnCTR.PBUSY bit is 0, then change
the PIPEnCTR.PID[1:0] bits for the selected pipe from BUF to NAK. However, if the USB changes the PID[1:0]
bits to NAK, checking the PIPEnCTR.PBUSY bit through software is not required.
Note 3. To change the BFRE, DBLB, and DIR bits after completing USB communication on the selected pipe, write 1 and
then 0 to the PIPEnCTR.ACLRM bit continuously through software to clear the FIFO buffer assigned to the
selected pipe while the PID and CURPIPE[3:0] bits are in the state described in Note 2.
PIPECFG specifies the transfer type, buffer memory access direction, and endpoint numbers for PIPE4 to PIPE7. It also
selects single or double buffer mode, and whether to continue or disable pipe operation at the end of transfer.
EPNUM[3:0] bits (Endpoint Number*1)
The EPNUM[3:0] bits specify the endpoint number for the selected pipe. Setting 0000b means an unused pipe. Set these
bits so that the combination of the DIR and EPNUM[3:0] settings is different for two or more pipes (EPNUM[3:0] bits
can be set to 0000b for all pipes).
DIR bit (Transfer Direction*2 *3)
The DIR bit specifies the transfer direction for the selected pipe. When the DIR bit is set to 0 by software, the USBFS
uses the selected pipe in the receiving direction, and when software set the DIR bit to 1, the USBFS uses the selected
pipe in the transmitting direction.
SHTNAK bit (Pipe Disabled at End of Transfer*1)
The SHTNAK bit specifies whether to modify PID to NAK upon the end of transfer when the selected pipe is in the
receiving direction. The SHTNAK bit is valid when the selected pipe is PIPE4 and PIPE5 in the receiving direction.
When the SHTNAK bit is set to 1 by software for the selected pipe in the receiving direction, the USBFS modifies the
PIPEnCTR.PID[1:0] bits associated with the selected pipe to NAK on determining the end of the transfer. The USBFS
determines that the transfer has ended on any of the following conditions:
A short packet (including a zero-length packet) is successfully received
The transaction counter is used and the number of packets specified by the counter are successfully received.
DBLB bit (Double Buffer Mode*2 *3)
The DBLB bit selects either single or double buffer mode for the FIFO buffer used by the selected pipe. The DBLB bit is
valid when PIPE4 and PIPE5 are selected.
BFRE bit (BRDY Interrupt Operation Specification*2 *3)
The BFRE bit specifies the BRDY interrupt generation timing from the USBFS to the CPU for the selected pipe.
When the BFRE bit is set to 1 by software and the selected pipe is receiving, the USBFS detects the transfer completion
and generates the BRDY interrupt after reading the relevant packet.
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24. USB 2.0 Full-Speed Module (USBFS)
When the BRDY interrupt is generated as specified, write 1 to the BCLR bit in the port control register with software.
The FIFO buffer assigned to the selected pipe is not enabled for reception until 1 is written to the BCLR bit.
When the BFRE bit is set to 1 by software and the selected pipe is transmitting, the USBFS does not generate the BRDY
interrupt. For details, see section 24.3.3.1, BRDY interrupt.
TYPE[1:0] bits (Transfer Type*1)
The TYPE[1:0] bits select the transfer type for the pipe selected in the PIPESEL.PIPESEL[3:0] bits.
Before setting PID to BUF for the selected pipe (before starting USB communication using the selected pipe), set the
TYPE[1:0] bits to a value other than 00b.
24.2.26
Pipe Maximum Packet Size Register (PIPEMAXP)
Address(es): USBFS.PIPEMAXP 4009 006Ch
Value after reset:
Bit
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
Symbol
Bit name
b8 to b0
MXPS[8:0]
Maximum Packet
b15 to b9
—
Reserved
Size*2
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
MXPS[8:0]
0
0
0/1
*1
0
0
Description
R/W
PIPE4 and PIPE5:
8 bytes (008h), 16 bytes (010h),
32 bytes (020h), 64 bytes (040h)
(Bits [8:7] and [2:0] are not provided.)
PIPE6 and PIPE7:
1 byte (001h) to 64 bytes (040h)
(Bits [8:7] are not provided.)
R/W
These bits are read as 0. The write value should be 0.
R/W
Note 1. The value of these bits is 000h when no pipe is selected with the PIPESEL.PIPESEL[3:0] bits and 040h when a
pipe is selected.
Note 2. Only set the MXPS[8:0] bits while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port
select register. Before setting these bits, check that the PIPEnCTR.PBUSY bit is 0, then change the
PIPEnCTR.PID[1:0] bits for the selected pipe from BUF to NAK. However, if the USB changes the PID[1:0] bits to
NAK, checking the PBUSY bit through software is not required.
PIPEMAXP specifies the maximum packet size for PIPE4 to PIPE7.
MXPS[8:0] bits (Maximum Packet Size*2)
The MXPS[8:0] bits specify the maximum data payload (maximum packet size) for the selected pipe.
These bits must be set to the appropriate value for each transfer type based on the USB 2.0 Specification. While
MXPS[8:0] = 0, do not write to the FIFO buffer or set PID to BUF.
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24.2.27
24. USB 2.0 Full-Speed Module (USBFS)
PIPEn Control Registers (PIPEnCTR) (n = 4 to 7)
PIPEnCTR (n = 4 and 5)
Address(es): USBFS.PIPE4CTR 4009 0076h, USBFS.PIPE5CTR 4009 0078h
b15
b14
b13
b12
b11
BSTS
INBUF
M
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
ATREP ACLRM SQCLR SQSET SQMO PBUSY
N
M
0
0
0
0
0
0
b4
b3
b2
—
—
—
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: The relevant pipe is not used for the transaction
1: The relevant pipe is used for the transaction.
R
b6
SQMON
Sequence Toggle Bit
Confirmation
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set*2
0: Write disabled
1: Specifies DATA1.
R/W*1
b8
SQCLR
Sequence Toggle Bit
Clear*2
0: Write disabled
1: Specifies DATA0.
R/W*1
b9
ACLRM
Auto Buffer Clear Mode*3
0: Disabled
1: Enabled (all buffers are initialized).
R/W
b10
ATREPM
Auto Response Mode*2
0: Auto response is disabled
1: Auto response is enabled.
R/W
b13 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14
INBUFM
Transmit Buffer Monitor
0: There are no data to be transmitted in the buffer memory
1: There is data to be transmitted in the buffer memory.
R
b15
BSTS
Buffer Status
0: Buffer access by the CPU is disabled
1: Buffer access by the CPU is enabled.
R
0
0
1
1
0: NAK response
1: BUF response (depending on the buffer state)
0: STALL response
1: STALL response.
Note 1. Only 0 can be read.
Note 2. Only set the ATREPM bit or write 1 to the SQCLR or SQSET bit while PID is NAK. Before setting these bits,
check that the PBUSY bit is 0, then change the PID[1:0] bits for the selected pipe from BUF to NAK. However, if
the USB changes the PID[1:0] bits to NAK, checking the PBUSY bit through software is not required.
Note 3. Only set the ACLRM bit while PID[1:0] is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port
select register. Before setting this bit, check that the PBUSY bit is 0, then change the PID[1:0] bits for the
selected pipe from BUF to NAK. If the USB changes the PID[1:0] bits to NAK, checking the PBUSY bit through
software is not required.
PIPEnCTR can be set for any pipe selection in the PIPESEL register.
PID[1:0] bits (Response PID)
The PID[1:0] bits specify the response type for the next transaction on the selected pipe. The default setting of the
PID[1:0] bits is NAK. Modify the setting of the PID[1:0] bits to BUF to use the associated pipe for USBFS transfer.
Table 24.7 shows the basic operation of the USBFS (when there are no errors in the communication packets) based on
the PID[1:0] bit setting.
After changing the PID[1:0] setting of a pipe from BUF to NAK through software during USBFS communication, check
that the PBUSY bit is 1 to determine if USBFS transfer on the selected pipe has actually entered the NAK state. If the
USBFS changes the PID[1:0] bits to NAK, checking the PBUSY bit through software is not required.
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24. USB 2.0 Full-Speed Module (USBFS)
The USBFS changes the setting of the PID[1:0] bits in the following cases:
The USBFS sets PID to NAK on recognizing the completion of the transfer when the selected pipe is receiving and
the PIPECFG.SHTNAK bit for the selected pipe is set to 1 by software
The USBFS sets PID to STALL (11b) on receiving a data packet with a payload exceeding the maximum packet
size of the selected pipe
The USBFS sets PID to NAK on detecting a USB bus reset.
To specify each response type, set the PID[1:0] bits as follows:
To transition from NAK (00b) to STALL, set 10b
To transition from BUF (01b) to STALL, set 11b
To transition from STALL (11b) to NAK, set 10b and then 00b
To transition from STALL to BUF, transition to NAK and then BUF.
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether the selected pipe is currently used for the transaction.
The USBFS modifies the PBUSY bit from 0 to 1 at the start of the USBFS transaction for the selected pipe, and modifies
the PBUSY bit from 1 to 0 on completion of one transaction.
Reading the PBUSY bit after PID to NAK is set to NAK with software allows you to check whether modification of the
pipe settings is possible. For details, see section 24.3.4.1, Pipe control register switching procedures.
SQMON bit (Sequence Toggle Bit Confirmation)
The SQMON bit indicates the expected value of the sequence toggle bit for the next transaction of the relevant pipe. The
SQMON bit is not allowed to toggle when a DATA-PID mismatch occurs during the transfer in the receiving direction.
SQSET bit (Sequence Toggle Bit Set*2)
Setting the SQSET bit to 1 through software allows the USBFS to set DATA1 as the expected value of the sequence
toggle bit for the next transaction of the selected pipe. The USBFS sets the SQSET bit to 0.
SQCLR bit (Sequence Toggle Bit Clear*2)
Setting the SQCLR bit to 1 through software allows the USBFS to set DATA0 as the expected value of the sequence
toggle bit of the selected pipe. The USBFS sets the SQCLR bit to 0.
ACLRM bit (Auto Buffer Clear Mode*3)
The ACLRM bit enables or disables auto buffer clear mode for the selected pipe.
To completely delete the information in the FIFO buffer assigned to the selected pipe, write 1 and then 0 to the ACLRM
bit consecutively.
Table 24.8 shows the information cleared by writing 1 and 0 to the ACLRM bit consecutively and the cases in which
clearing the information is required.
ATREPM bit (Auto Response Mode*2)
The ATREPM bit enables or disables auto response mode for the selected pipe.
This bit can be set to 1 when the selected pipe is for bulk transfer. When the ATREPM bit is set to 1, the USBFS responds
to the token from the USB host as follows:
When the selected pipe is set for Bulk IN transfers (PIPECFG.TYPE[1:0] = 01b and PIPECFG.DIR bit = 1):
When the ATREPM bit = 1 and PID = BUF, the USB transmits a zero-length packet in response to the IN token
The USB updates (allows toggling of) the sequence toggle bit (DATA-PID) each time the USB receives ACK
from the USB host. In a single transaction, the IN token is received, a zero-length packet is transmitted, and
ACK is received). The USB does not generate the BRDY or BEMP interrupt.
When the selected pipe is for Bulk OUT transfer (PIPECFG.TYPE[1:0] = 01b and PIPECFG.DIR = 0):
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When the ATREPM bit = 1 and PID = BUF, the USB returns NAK in response to the OUT token and generates an
NRDY interrupt.
For USB communication in auto response mode, set the ATREPM bit to 1 while the FIFO buffer is empty. Do not write
to the FIFO buffer during USBFS communication in auto response mode.
INBUFM bit (Transmit Buffer Monitor)
The INBUFM bit indicates the FIFO buffer status for the selected pipe in the transmitting direction.
When the selected pipe is transmitting (the PIPECFG.DIR bit is 1), the USBFS sets the INBUFM bit to 1 when the CPU
completes writing data to at least one FIFO buffer plane.
The USBFS sets the INBUFM bit to 0 when it completes transmitting the data from the FIFO buffer plane to which all
the data is written. In double buffer mode (the PIPECFG.DBLB bit is 1), the USBFS sets the INBUFM bit to 0 when it
completes transmitting the data from the two FIFO buffer planes before the CPU completes writing data to one FIFO
buffer plane.
The INBUFM bit indicates the same value as the BSTS bit when the selected pipe is receiving (PIPECFG.DIR bit = 0).
BSTS bit (Buffer Status)
The BSTS bit indicates the FIFO buffer status for the selected pipe.
The meaning of the BSTS bit depends on the settings of PIPECFG.DIR and PIPECFG.BFRE as shown in Table 24.9.
Table 24.7
Operation of USBFS based on PID[1:0] bit setting
Transfer direction
(DIR bit)
Bits PID[1:0]
Transfer type
00b (NAK)
Bulk or interrupt
Operation does not
depend on the setting
Returns NAK in response to the token from the USB host
01b (BUF)
Bulk
Receiving direction
(DIR bit = 0)
Receives data and returns ACK in response to the OUT token from
the USB host if the FIFO buffer associated with the selected pipe is
ready for reception
Interrupt
Receiving direction
(DIR bit = 0)
Receives data and returns ACK in response to the OUT token from
the USB host if the FIFO buffer associated with the selected pipe is
ready for reception
Bulk or interrupt
Transmitting direction
(DIR bit = 1)
Transmits data in response to the token from the USB host if the
associated FIFO buffer is ready for transmission. Returns NAK if not
ready.
Bulk or interrupt
Operation does not
depend on the setting
Returns STALL in response to the token from the USB host
10b (STALL) or
11b (STALL)
Table 24.8
Operation of USBFS
Information cleared by USBFS by setting ACLRM = 1
No.
Information cleared by ACLRM bit manipulation
Cases in which clearing information is required
1
All the information in the FIFO buffer assigned to the selected pipe
(both FIFO buffer planes are cleared when double buffer mode is
selected)
When the pipe is to be initialized
2
Internal flags of the PIPECFG.BFRE bit
When the PIPECFG.BFRE setting is modified
3
FIFO buffer toggle control
When the PIPECFG.DBLB setting is modified
4
Internal flags of the transaction count
When the transaction count function is forcibly terminated
Table 24.9
Operation of BSTS bit (1 of 2)
DIR bit
BFRE bit
BSTS bit function
0
0
The received data can be read from the FIFO buffer.
The received data is completely read from the FIFO buffer.
0
1
The received data that can be read from the FIFO buffer is set to 1 by software after the
received data is completely read from the FIFO buffer
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Table 24.9
24. USB 2.0 Full-Speed Module (USBFS)
Operation of BSTS bit (2 of 2)
DIR bit
BFRE bit
BSTS bit function
1
0
The transmit data can be written to the FIFO buffer.
The transmit data is completely written to the FIFO buffer.
1
1
Setting prohibited
PIPEnCTR (n = 6 and 7)
Address(es): USBFS.PIPE6CTR 4009 007Ah, USBFS.PIPE7CTR 4009 007Ch
b15
b14
b13
b12
b11
b10
BSTS
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b9
b8
b7
b6
b5
ACLRM SQCLR SQSET SQMO PBUSY
N
0
0
0
0
0
b4
b3
b2
—
—
—
0
0
0
b1
b0
PID[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
PID[1:0]
Response PID
b1 b0
R/W
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
PBUSY
Pipe Busy
0: The relevant pipe is not used at the USB bus
1: The relevant pipe is used at the USB bus.
R
b6
SQMON
Sequence Toggle Bit
Confirmation
0: DATA0
1: DATA1.
R
b7
SQSET
Sequence Toggle Bit Set *2
0: Invalid
1: Specifies DATA1.
R/W
*1
b8
SQCLR
Sequence Toggle Bit
Clear *2
0: Invalid
1: Specifies DATA0.
R/W
*1
b9
ACLRM
Auto Buffer Clear Mode *2,*3
0: Auto buffer clear mode is disabled
1: Auto buffer clear mode is enabled (all buffers are initialized).
R/W
b14 to b10 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
Buffer Status
0: Buffer access is disabled
1: Buffer access is enabled.
R
BSTS
0 0: NAK response
0 1: BUF response (depending on the buffer state)
1 0: STALL response
1 1: STALL response.
Note 1. Only 0 can be read. Only 1 can be written.
Note 2. Write 1 to the SQCLR or SQSET bit while PID is NAK. Before setting these bits, check that the PBUSY bit is 0,
then change the PID[1:0] bits for the selected pipe from BUF to NAK. If the USB changes the PID[1:0] bits to
NAK, checking the PBUSY bit through software is not required.
Note 3. Only set the ACLRM bit while PID is NAK and before the pipe is selected in the CURPIPE[3:0] bits in the port
select register. Before setting this bit, check that the PBUSY bit is 0, then change the PID[1:0] bits for the
selected pipe from BUF to NAK. If the USB changes the PID[1:0] bits to NAK, checking the PBUSY bit through
software is not required.
PID[1:0] bits (Response PID)
The PID[1:0] bits specify the response type for the next transaction of the relevant pipe.
The default setting of the PID[1:0] bits is NAK. Change the PID[1:0] setting to BUF to use the selected pipe for USBFS
transfer. Table 24.7 shows the basic operation (when there are no errors in the transmitted and received packets) of the
USBFS depending on the PID[1:0] setting.
After changing the PID[1:0] setting from BUF to NAK through software during USBFS communication on the selected
pipe, check that the PBUSY bit is 1 to determine if USBFS transfer using the selected pipe has actually entered the NAK
state. If the USBFS changes the PID bits to NAK, checking the PBUSY bit through software is not required.
The USBFS changes the PID[1:0] setting in the following cases:
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24. USB 2.0 Full-Speed Module (USBFS)
The USBFS sets PID to NAK on completion of the transfer when the selected pipe is receiving and the
PIPECFG.SHTNAK bit for the selected pipe is set to 1 by software
The USBFS sets PID to STALL (11b) on receiving a data packet with a payload exceeding the maximum packet
size of the selected pipe
The USBFS sets PID to NAK on detecting a USB bus reset.
To specify each response type, set the PID[1:0] bits as follows:
To transition from NAK (00b) to STALL, set 10b
To transition from BUF (01b) to STALL, set 11b
To transition from STALL (11b) to NAK, set 10b and then 00b
To transition from STALL to BUF, transition to NAK and then BUF.
PBUSY bit (Pipe Busy)
The PBUSY bit indicates whether the selected pipe is currently used for the transaction.
The USBFS changes the PBUSY bit from 0 to 1 at the start of the USBFS transaction for the selected pipe, and changes
the PBUSY bit from 1 to 0 on completion of one transaction. Reading the PBUSY bit after PID is set to NAK by
software allows you to check whether changing the pipe setting is possible.
SQMON bit (Sequence Toggle Bit Confirmation)
The SQMON bit indicates the expected value of the sequence toggle bit for the next transaction of the selected pipe. The
USBFS toggles the SQMON bit on successful completion of the transaction. However, the USBFS does not toggle the
SQMON bit when a DATA-PID mismatch occurs during the transfer in the receiving direction.
SQSET bit (Sequence Toggle Bit Set)
Setting the SQSET bit to 1 through software allows the USBFS to set DATA1 as the expected value of the sequence
toggle bit for the next transaction of the selected pipe. The USBFS sets the SQSET bit to 0.
SQCLR bit (Sequence Toggle Bit Clear)
Setting the SQCLR bit to 1 through software allows the USBFS to set DATA0 as the expected value of the sequence
toggle bit for the next transaction of the selected pipe. The USBFS sets the SQCLR bit to 0.
ACLRM bit (Auto Buffer Clear Mode)
The ACLRM bit enables or disables auto buffer clear mode for the selected pipe. To completely delete the information in
the FIFO buffer assigned to the selected pipe, write 1 and then 0 to the ACLRM bit consecutively.
Table 24.10 shows the information cleared by writing 1 and 0 to the ACLRM bit consecutively and the cases in which
this processing is required.
BSTS bit (Buffer Status)
The BSTS bit indicates the FIFO buffer status for the selected pipe. The meaning of the BSTS bit depends on the
PIPECFG.DIR, PIPECFG.BFRE, and DnFIFOSEL.DCLRM settings, as shown in Table 24.9.
Table 24.10
Information cleared by USB by setting ACLRM bit to 1
No.
Information cleared by ACLRM bit manipulation
Cases in which clearing information is required
1
All the information in the FIFO buffer assigned to the selected
pipe
When the pipe is initialized
2
Internal flags of the PIPECFG.BFRE bit
When the PIPECFG.BFRE setting is modified
3
Internal flags of the transaction count
When the transaction count function is forcibly terminated
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24.2.28
24. USB 2.0 Full-Speed Module (USBFS)
PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 4 and 5)
Address(es): USBFS.PIPE4TRE 4009 009Ch, USBFS.PIPE5TRE 4009 00A0h
Value after reset:
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
b9
b8
TRENB TRCLR
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
b7 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
TRCLR
Transaction Counter Clear
0: Invalid
1: The current counter value is cleared.
R/W
b9
TRENB
Transaction Counter Enable
0: Transaction counter disabled
1: Transaction counter enabled.
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b10 —
Note:
Description
R/W
Only change each bit in PIPEnTRE while PID is NAK. Before setting these bits, check that the
PIPEnCTR.PBUSY bit is 0, then change the PIPEnCTR.PID[1:0] bits for the selected pipe from BUF to NAK. If
the USB changes the PID[1:0] bits to NAK, checking the PBUSY bit through software is not required.
TRCLR bit (Transaction Counter Clear)
When the TRCLR bit is set to 1, the USBFS clears the current value of the transaction counter associated with the
selected pipe and then sets the TRCLR bit to 0.
TRENB bit (Transaction Counter Enable)
The TRENB bit enables or disables the transaction counter.
For the pipe in the receiving direction, setting the TRENB bit to 1 after setting the total number of the packets to be
received in the PIPEnTRN.TRNCNT[15:0] bits through software allows the USBFS to control hardware as follows, on
having received the number of packets equal to the TRNCNT[15:0] setting.
While the PIPECFG.SHTNAK bit is 1, the USBFS changes the PID bits to NAK for the associated pipe on having
received the number of packets equal to the TRNCNT[15:0] setting
While the PIPECFG.BFRE bit is 1, the USBFS asserts the BRDY interrupt on having received the number of
packets equal to the TRNCNT[15:0] setting and then reading the last received data.
For the transmitting pipe, set the TRENB bit to 0. When the transaction counter is not used, set the TRENB bit to 0.
When the transaction counter is used, set the TRNCNT[15:0] bits before setting the TRENB bit to 1. Set the TRENB bit
to 1 before receiving the first packet to be counted by the transaction counter.
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24.2.29
24. USB 2.0 Full-Speed Module (USBFS)
PIPEn Transaction Counter Register (PIPEnTRN) (n = 4 and 5)
Address(es): USBFS.PIPE4TRN 4009 009Eh, USBFS.PIPE5TRN 4009 00A2h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
TRNCNT[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
TRNCNT[15:0]
Transaction Counter
When written to:
Specifies the total number of packets (number of
transactions) to be received in the associated PIPE.
When read from:
Indicates the specified number of transactions if the
PIPEnTRE.TRENB bit is 0.
Indicates the number of currently counted transactions if
the PIPEnTRE.TRENB bit is 1.
R/W
The PIPEnTRN registers retain their current setting during a USB bus reset.
TRNCNT[15:0] bits (Transaction Counter)
The USBFS increments the value of the TRNCNT[15:0] bits by one when all of the following conditions are satisfied on
receiving the packet:
The PIPEnTRE.TRENB bit is 1
(TRNCNT[15:0] set value ≠ current counter value + 1) on receiving the packet
The payload of the received packet aligns with the PIPEMAXP.MXPS[8:0] setting.
The USB sets the value of the TRNCNT[15:0] bits to 0 when any of the following conditions are satisfied:
All of the following conditions are satisfied:
The PIPEnTRE.TRENB bit is 1
(TRNCNT[15:0] set value = current counter value + 1) on receiving the packet
The payload of the received packet aligns with the PIPEMAXP.MXPS[8:0] setting.
All of the following conditions are satisfied:
The PIPEnTRE.TRENB bit is 1
The USBFS has received a short packet.
All of the following conditions are satisfied:
The PIPEnTRE.TRENB bit is 1
The PIPEnTRE.TRCLR bit is set to 1 by software.
For the transmitting pipe, set the TRNCNT[15:0] bits to 0. When the transaction counter is not used, set the
TRNCNT[15:0] bits to 0.
Setting the number of transactions to be transferred to the TRNCNT[15:0] bits is only enabled when the
PIPEnTRE.TRENB bit is 0. To modify the number of transactions to be transferred, set the TRCLR bit to 1 to clear the
current counter value before setting the PIPEnTRE.TRENB bit to 1.
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24.2.30
24. USB 2.0 Full-Speed Module (USBFS)
USB Module Control Register (USBMC)
Address(es): USBFS.USBMC 4009 00CCh
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
VDCEN
—
—
—
—
—
—
VDDUS
BE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
VDDUSBE
USB Reference Power Supply
Circuit On/Off Control
0: USB reference power supply circuit off
1: USB reference power supply circuit on.
R/W
b1
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b6 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
VDCEN
USB Regulator On/Off Control
0: USB regulator off
1: USB regulator on.
R/W
b15 to b8
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
VDDUSBE bit (USB Reference Power Supply Circuit On/Off Control)
The USB reference power supply circuit generates the reference voltage for battery charging. Set this bit to 1 when using
the battery charging function.
VDCEN bit (USB Regulator On/Off Control)
The VDCEN bit controls the USB regulator circuit. Set this bit to 1 when using the USB regulator circuit.
24.2.31
BC Control Register 0 (USBBCCTRL0)
Address(es): USBFS.USBBCCTRL0 4009 00B0h
b15
b14
b13
b12
b11
b10
—
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b9
b8
b7
PDDET CHGD BATCH
STS0 ETSTS GE0
0
0
0
b6
—
0
b5
b4
b3
b2
b1
b0
VDMS IDPSIN VDPSR IDMSIN IDPSR RPDM
RCE0
KE0
CE0
KE0
CE0
E0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RPDME0
D– Pin Pull-Down Control
0: Pull-down off
1: Pull-down on.
R/W
b1
IDPSRCE0
D+ Pin IDPSRC Output Control
0: Stop
1: 10 μA output.
R/W
b2
IDMSINKE0
D– Pin 0.6 V Input Detection
(Comparator and Sink) Control
0: Detection off
1: Detection on (comparator and sink current on).
R/W
b3
VDPSRCE0
D+ Pin VDPSRC (0.6 V) Output
Control
0: Stop
1: 0.6 V output.
R/W
b4
IDPSINKE0
D+ Pin 0.6 V Input Detection
(Comparator and Sink) Control
0: Detection off
1: Detection on (comparator and sink current on).
R/W
b5
VDMSRCE0
D– Pin VDMSRC (0.6 V) Output
Control
0: Stop
1: 0.6 V output.
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
BATCHGE0
BC (Battery Charger) Function Ch0
General Enable Control
0: Disabled
1: Enabled.
R/W
b8
CHGDETSTS0
D– Pin 0.6 V Input Detection Status*1
0: Not detected
1: Detected.
R
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Bit
24. USB 2.0 Full-Speed Module (USBFS)
Symbol
Bit name
b9
PDDETSTS0
D+ Pin 0.6 V Input Detection
b15 to b10
—
Reserved
Status*2
Description
R/W
0: Not detected
1: Detected.
R
These bits are read as 0. The write value should be 0. R/W
Note 1. Valid when IDMSINKE0 = 1.
Note 2. Valid when IDPSINKE0 = 1.
RPDME0 bit (D– Pin Pull-Down Control)
When using the battery charging function, set this bit to 1 to control the pull-down resistor of the D– pin.
IDPSRCE0 bit (D+ Pin IDPSRC Output Control)
When the IDPSRCE0 bit is set to 1, the current output is enabled on detection of the data pin connection and D+ pin pullup.
IDMSINKE0 bit (D– Pin 0.6 V Input Detection (Comparator and Sink) Control)
When the IDMSINKE0 bit is set to 1, the USBFS detects whether VDMSRC (0.6 V), output from the host to D– on
primary detection, is connected, or VDPSRC (0.6 V), output from the device to D+, is connected to D– by the host of the
device.
VDPSRCE0 bit (D+ Pin VDPSRC (0.6 V) Output Control)
When the VDPSRCE0 bit set to 1, output is enabled on primary detection and VDPSRC (0.6 V) is applied to D+.
IDPSINKE0 bit (D+ Pin 0.6 V Input Detection (Comparator and Sink) Control)
When the IDPSINKE0 bit is set to 1, the USBFS detects whether VDMSRC (0.6 V), output from the device to D– is
connected to D+ (DCP) by the host of the device.
VDMSRCE0 bit (D– Pin VDMSRC (0.6 V) Output Control)
When the VDMSRCE0 bit set to 1, output is enabled on secondary detection and VDMSRC (0.6 V) is applied to D–.
CHGDETSTS0 flag (D– Pin 0.6 V Input Detection Status*1)
The CHGDETSTS0 flag is set to 1 if the USBFS detects whether VDMSRC (0.6 V), output from the host to D– during
primary detection, is connected, or VDPSRC (0.6 V), output from the device to D+, is connected to D– by the host of the
device.
PDDETSTS0 flag (D+ Pin 0.6 V Input Detection Status*2)
The PDDETSTS0 flag is set to 1 if the USBFS detects whether VDMSRC (0.6 V) that is output from the device to D–
during secondary detection is connected to D+ (DCP) by the host of the device.
24.2.32
USB Clock Selection Register (UCKSEL)
Address(es): USBFS.UCKSEL 4009 00C4h
b15
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UCKSE
LC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
b14
Symbol
Bit name
b0
UCKSELC
USB Clock
b15 to b1
—
Reserved
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Selection*1
Description
R/W
0: High-speed on-chip oscillator clock (HOCO) not
selected as USB clock
1: High-speed on-chip oscillator clock (HOCO)
selected as USB clock.
R/W
These bits are read as 0. The write value should be 0. R/W
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24. USB 2.0 Full-Speed Module (USBFS)
Note 1. When UCKSELC = 1, the user trimming function cannot be used. For information on the user trimming function,
see section 8, Clock Generation Circuit.
24.3
Operation
24.3.1
System Control
This section describes the register settings required for initializing the USBFS module and controlling power
consumption.
24.3.1.1
Setting data to USBFS related registers
Setting the SYSCFG.USBE bit to 1 after starting the clock supply to the USBFS (SYSCFG.SCKE bit is 1) enables and
starts USBFS operation.
24.3.1.2
Controlling USBFS data bus registers
The USBFS has pull-up resistors for the D+ and D- lines. Pull up these lines by setting the SYSCFG.DPRPU and
SYSCFG.DMRPU bits.
Confirm that connection to the USB host is made, then set SYSCFG.DPRPU bit to 1 to pull up the D+ line (during fullspeed) or set SYSCFG.DMRPU bit to 1 to pull up D- line (during low-speed).
When SYSCFG.DPRPU (during full-speed) or SYSCFG.DMRPU (during low-speed) bit is set to 0 during
communication with the system, the USBFS disables the pull-up resistor of the USB data line, therefore notifying the
USBFS host of disconnection.
Table 24.11
Control settings for the USBFS data bus resistors
SYSCFG Register
DPRPU bit
DMRPU bit
D–
D+
Function
0
0
Open
Open
Not in use
1
0
Open
Pull-up
Full-speed
0
1
Pull-up
Open
Low-speed
—
—
Setting prohibited
Other settings
24.3.1.3
Example of USBFS power supply connection
Figure 24.2 shows an example of power supply connection when the USB regulator is not used. Figure 24.3 and
Figure 24.4 show examples of power supply connection when the USB regulator is used.
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24. USB 2.0 Full-Speed Module (USBFS)
Input the same voltage as VCC to
VCC_USB_LDO and VCC_USB
VCC_
USB_LDO
VCC 3.0 V to 3.6 V
USB LDO
Regulator
VCC_USB
BC
Control
USB_DP
0
USB_DM
VDCEN
0
VDDUSBE
USB Module Control Register (USBMC)
USBFS
USB
Transceiver
Figure 24.2
This MCU
Example of power supply connection when the USB LDO regulator is not used
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24. USB 2.0 Full-Speed Module (USBFS)
Input the same voltage as
VCC to VCC_USB_LDO
VCC 3.8 V to 5.5 V
VCC_USB_LDO
USB LDO
Regulator
*1
1.0µF
VCC_USB
BC
Control
USB_DP
1
USB_DM
VDCEN
1
VDDUSBE
USB Module Control Register (USBMC)
USBFS
USB
Transceiver
This MCU
Note 1. Make sure that the resistance of the connected wiring is 0.5 Ω or less to connect a capacitor of ESR ≤ 1 Ω.
Figure 24.3
Example of power supply connection when the USB LDO regulator is used (BC used)
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24. USB 2.0 Full-Speed Module (USBFS)
Input the same voltage as
VCC to VCC_USB_LDO
VCC_USB_LDO
USB LDO
Regulator
*1
1.0µF
VCC 4.0 V to 5.5 V
VCC_USB
BC
Control
USB_DP
1
USB_DM
VDCEN
0
VDDUSBE
USB Module Control Register (USBMC)
USBFS
USB
Transceiver
This MCU
Note 1. Make sure that the resistance of the connected wiring is 0.5 Ω or less to connect a capacitor of ESR ≤ 1 Ω.
Figure 24.4
Example of power supply connection when the USB LDO regulator is used (BC not used)
24.3.1.4
Example of USB External Connection Circuit
The host recognizes a USB device when one of the data lines is pulled up. The MCU can use switching of the internal
pull-up resistor for this. Also, bus-powered devices do not require external regulators because the MCU incorporates a
power supply in the USB-PHY. Figure 24.6 and Figure 24.8 show examples of external circuits for USB connection.
Figure 24.5 shows an example of functional connection of the USB connector in the self-powered state.
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24. USB 2.0 Full-Speed Module (USBFS)
External connection
MCU
USB_VBUS*1
1 M
100
0.1 µF
*2
USB
transceiver
RPU
RPU
VBUS
ZDRV
USB_DP
USB_DM
D+
D–
ZDRV
ZDRV: Output impedance
RPU: Pull-up resistor
Note 1. USB_VBUS is 5 V tolerant.
Note 2. Design the board so that the total VBUS capacitance
ranges from 1.0 to 10 µF.
Figure 24.5
Example device connection in self-powered state
Figure 24.6 shows an example of functional connection of the USB connector in bus-powered state.
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24. USB 2.0 Full-Speed Module (USBFS)
External connection
MCU
USB
B connector
Each system power
supply (3.3 V)
System power
supply (3.3 V)
Regulator
*2
VBUS
USB_VBUS*1
USB
transceiver
RPU
ZDRV
RPU
USB_DP
USB_DM
D+
D–
ZDRV
ZDRV : Output impedance
RPU: Pull-up resistor
Note 1. USB_VBUS is 5 V tolerant.
Note 2. Design the board so that the total VBUS capacitance
ranges from 1.0 to 10 µF.
Figure 24.6
Example device connection in bus-powered state 1
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24. USB 2.0 Full-Speed Module (USBFS)
External connection
MCU
USB
B connector
USB_VBUS*1
VBUS
USB
transceiver
RPU
ZDRV
RPU
USB_DP
USB_DM
D+
D–
ZDRV
ZDRV : Output impedance
RPU: Pull-up resistor
Note 1. USB_VBUS is 5 V tolerant.
Note 2. Design the board so that the total VBUS capacitance
ranges from 1.0 to 10 µF.
Figure 24.7
Example device connection in bus-powered state 2
The examples of external circuits given in this section are simplified circuits, and their operation in every system is not
guaranteed.
Figure 24.8 shows an example of functional connection of the USB connector with Battery Charging Rev 1.2 supported.
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24. USB 2.0 Full-Speed Module (USBFS)
External connection
Charging IC
supporting BC 1.2
MCU
SCL0
SDA0
SCL0
Charging battery
SDA0
USB_VBUS*3
*1, *4
VBUS
10 k
*2
USB
transceiver
100
USB
B connector
0.1 µF
RPU
RPU
VBUS
ZDRV
USB_DP
D+
USB_DM
D–
ZDRV
ZDRV: Output impedance
RPU: Pull-up resistor
Note 1. When Battery Charging Spec. Rev 1.2 is supported,
ensure that the VBUS wiring width is enough for at least
1.5 A (shown in bold lines).
Note 2. Use a resistor value such that the discharging time of
VBUS is within 500 ms.
Note 3. USB_VBUS is 5 V tolerant.
Note 4. Design the board so that the total VBUS capacitance
ranges from 1.0 to 10 µF.
Figure 24.8
24.3.2
Example of functional connection with Battery Charging Rev 1.2 supported
Interrupt Sources
Table 24.12 lists the interrupt sources in the USBFS.
When an interrupt generation condition is satisfied and the interrupt output is enabled using the associated interrupt
enable register, a USB interrupt request is issued to the Interrupt Controller Unit and a USB interrupt is generated. See
section 12, Interrupt Controller Unit (ICU).
Table 24.12
Interrupt sources (1 of 2)
Bit to be set
Name
Interrupt source
Status flag
VBINT
VBUS interrupt
When a change in the state of the USB_VBUS input pin is detected
(low to high or high to low)
INTSTS0.VBSTS
RESM
Resume interrupt
When a change in the state of the USB bus is detected in the
suspended state (J-state to K-state or J-state to SE0)
—
SOFR
Frame number
update interrupt
When an SOF packet with a different frame number is received.
—
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Table 24.12
24. USB 2.0 Full-Speed Module (USBFS)
Interrupt sources (2 of 2)
Bit to be set
Name
Interrupt source
Status flag
DVST
Device state
transition interrupt
When a device state transition is detected with any of the following
conditions:
- A USB bus reset detected
- Suspended state detected
- SET_ADDRESS request received
- SET_CONFIGURATION request received.
INTSTS0.DVSQ[2:0]
CTRT
Control transfer
stage transition
interrupt
When a stage transition is detected in control transfer with any of
the following conditions:
- Setup stage completed
- Control write transfer status stage transition
- Control read transfer status stage transition
- Control transfer completed
- A control transfer sequence error occurred.
INTSTS0.CTSQ[2:0]
BEMP
Buffer empty
interrupt
When transmission of all data in the buffer memory is complete and
the buffer becomes empty
When a packet larger than the maximum packet size is received.
BEMPSTS.PIPEnBEMP
NRDY
Buffer not ready
interrupt
When NAK is returned for an IN or OUT token while the PID bit =
BUF.
NRDYSTS.PIPEnNRDY
BRDY
Buffer ready
interrupt
When the buffer becomes ready (reading or writing is enabled).
BRDYSTS.PIPEnBRDY
Figure 24.9 shows the circuits related to the interrupts in the USBFS.
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24. USB 2.0 Full-Speed Module (USBFS)
USB bus reset detected
Set_Address detected
Set_Configuration
detected
Suspended state detected
Control Write Data Stage
USBFS_USBR
Control Read Data Stage
INTENB0
INTSTS0
Control Transfer End
VBSE
VBINT
Control Transfer Error
RSME
USBFS_USBI
RESM
Control Transfer Setup Receive
SOFE
SOFR
DVSE
DVST
Edge/level
detector
BEMP interrupt enable register
b7
b4
b0
CTRE
b7
CTRT
BEMPE
BEMP interrupt
status register
BEMP
NRDYE
b4
NRDY
b0
BRDYE
BRDY
NRDY interrupt enable register
b7
b4
b0
b7
NRDY interrupt
status register
b4
b0
BRDY interrupt enable register
b7
b4
b0
b7
BRDY interrupt
status register
b4
b0
Figure 24.9
Circuits related to interrupts in USBFS
Table 24.13 shows the interrupts generated in the USBFS.
Table 24.13
USBFS Interrupts
Interrupt name
Interrupt status flag
DTC activation
USBFS_USBI
VBUS interrupt, resume interrupt, frame number update interrupt, device state transition
interrupt, control transfer stage transition interrupt, buffer empty interrupt, buffer not ready
interrupt, buffer ready interrupt.
Not possible
USBFS_USBR
VBUS interrupt, resume interrupt.
Not possible
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24.3.3
24.3.3.1
24. USB 2.0 Full-Speed Module (USBFS)
Interrupt Descriptions
BRDY interrupt
The following sections describe the conditions in which the USBFS sets 1 to a corresponding bit in BRDYSTS. For this
condition, the USBFS generates a BRDY interrupt if software set 1 to the BRDYENB.PIPEnBRDYE bit that
corresponds to the pipe and 1 to the INTENB0.BRDYE bit.
The conditions for generating and clearing the BRDY interrupt depend on the settings of the SOFCFG.BRDYM bit and
PIPECFG.BFRE bit for each pipe as described in the following sections:
(1)
When the SOFCFG.BRDYM bit = 0 and the PIPECFG.BFRE bit = 0
With these settings, the BRDY interrupt indicates that the FIFO port is accessible.
On any of the following conditions, the USBFS generates an internal BRDY interrupt request trigger and sets 1 to the
BRDYSTS.PIPEnBRDY bit associated with the selected pipe.
(a)
For the transmitting pipe:
When the DIR bit is changed from 0 to 1 by software
When packet transmission is complete using the selected pipe while write-access from the CPU to the FIFO buffer
for the selected pipe is disabled (when the BSTS bit is read as 0)
When one FIFO buffer is empty on completion of writing data to the other FIFO buffer in double buffer mode
No request trigger is generated until completion of writing data to the currently-written FIFO buffer even if
transmission to the other FIFO buffer is complete
When 1 is written to the PIPEnCTR.ACLRM bit, that causes the FIFO buffer to transition from the write-disabled to
write-enabled state.
No request trigger is generated for the DCP during data transmission for control transfers.
(b)
For the receiving pipe:
When packet reception completes successfully therefore, enabling the FIFO buffer to be read while read-access
from the CPU to the FIFO buffer for the selected pipe is disabled (when the BSTS bit is read as 0).
No request trigger is generated for the transaction in which DATA-PID mismatch has occurred.
When one FIFO buffer is read-enabled on completion of reading data from the other FIFO buffer in double buffer
mode.
No request trigger is generated until completion of reading data from the currently-read FIFO buffer even when
reception by the other FIFO buffer completes.
The BRDY interrupt is not generated in the status stage of control transfers.
The PIPEnBRDY interrupt status of the pertinent pipe can be set to 0 by writing 0 to the corresponding PIPEnBRDY bit
through software. In this case, write 1 to the PIPEnBRDY bits for the other pipes.
Clear the BRDY status before accessing the FIFO buffer.
(2)
When the SOFCFG.BRDYM bit = 0 and the PIPECFG.BFRE bit = 1
With these settings, the USBFS generates a BRDY interrupt on completion of reading all data for a single transfer using
the pipe in the receiving direction, and sets 1 to the bit in BRDYSTS associated with the selected pipe.
On any of the following conditions, the USBFS determines that the last data for a single transfer is received.
When a short packet including a zero-length packet is received
When the PIPEn transaction counter register (PIPEnTRN) is used and the number of packets specified by the
PIPEnTRN.TRNCNT[15:0] bits are completely received.
When the selected data is completely read after any of the specified conditions is satisfied, the USBFS determines that all
data for a single transfer is completely read.
When a zero-length packet is received while the FIFO buffer is empty, the USBFS determines that all data for a single
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24. USB 2.0 Full-Speed Module (USBFS)
transfer is completely read when the FRDY bit in the FIFO port control register is 1 and the DTLN[8:0] bits are 0. In this
case, to start the next transfer, write 1 to the BCLR bit in the associated port control register through software. With these
settings, the USBFS does not detect a BRDY interrupt for the transmitting pipe.
The PIPEnBRDY interrupt status of the selected pipe can be set to 0 by writing 0 to the corresponding
BRDYSTS.PIPEnBRDY bit through software. In this case, write 1 to the PIPEnBRDY bits for the other pipes.
In this mode, do not modify the PIPECFG.BFRE bit setting until all data for a single transfer is processed. When
modification to the PIPECFG.BFRE bit is required before processing completes, clear all FIFO buffers for the selected
pipe with the PIPEnCTR.ACLRM bit.
(3)
When the SOFCFG.BRDYM bit = 1 and the PIPECFG.BFRE bit = 0
With these settings, the BRDYSTS.PIPEnBRDY values are linked to the BSTS bit setting for each pipe, that is, the
BRDY interrupt status bits (PIPEnBRDY) are set to 1 or 0 by the USB depending on the FIFO buffer status.
(a)
For the transmitting pipe
The BRDY interrupt status bits are set to 1 when the FIFO buffer is ready for write access, and are set to 0 when it is not
ready. However, the BRDY interrupt is not generated even when the DCP in the transmitting direction is ready for write
access.
(b)
For the receiving pipe
The BRDY interrupt status bits are set to 1 when the FIFO buffer is ready for read access, and are set to 0 when all data
are read (not ready for read access). When a zero-length packet is received while the FIFO buffer is empty, the selected
bit is set to 1 and the BRDY interrupt is continuously generated until BCLR = 1 is written by software.
With this setting, the PIPEnBRDY bit cannot be set to 0 by software. When the SOFCFG.BRDYM bit is set to 1, set all
PIPECFG.BFRE bits for all pipes to 0.
Figure 24.10 shows the timing of BRDY interrupt generation.
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24. USB 2.0 Full-Speed Module (USBFS)
(1) Example of zero-length packet reception or data packet reception when BFRE = 0 (single-buffer mode)
Data Packet
Token Packet
USB bus
ACK Handshake
Ready for reception
FIFO buffer status
Ready for read access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
A BRDY interrupt is generated because the
FIFO buffer becomes ready for read access*1
(2) Example of data packet reception when BFRE = 1 (single-buffer mode)
USB bus
Token Packet
Data Packet
ACK Handshake
Ready for reception
FIFO buffer status
Ready for read access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
The FIFO buffer becomes
ready for read access*1
A BRDY interrupt is generated
because the transfer has ended*2
(3) Example of packet transmission (single-buffer mode)
USB bus
Token Packet
Data Packet
ACK Handshake
Ready for transmission
FIFO buffer status
Ready for write access
BRDY interrupt
(BRDYSTS.PIPEnBRDY bit)
A BRDY interrupt is generated
because the FIFO buffer
becomes ready for write access
Packet transmitted by host device
Packet transmitted by a device
Note 1. The FIFO buffer becomes ready for read access when a packet is received while no data
remains unread in the FIFO buffer in the CPU.
Note 2. A transfer ends in any of the following conditions:
(1) When a short packet including a zero-length packet is received.
(2) When the number of packets specified in the transaction counter are received.
Figure 24.10
Timing of BRDY interrupt generation
The condition for which the USBFS clears the INTSTS0.BRDY bit depends on the SOFCFG.BRDYM bit setting. Table
24.14 shows the condition for clearing the BRDY bit.
Table 24.14
Condition for clearing BRDY bit
BRDYM bit
Condition for clearing BRDY bit
0
When all bits in BRDYSTS are set to 0 by software
1
When the BSTS bits for all pipes become 0
24.3.3.2
NRDY interrupt
On generating an internal NRDY interrupt request for the pipe whose PID bits are set to BUF by software, the USBFS
sets the associated PIPEnNRDY bit in NRDYSTS to 1. If the associated bit in NRDYENB is set to 1 by software, the
USBFS sets the INTSTS0.NRDY bit to 1 and generates a USB interrupt.
This section describes the conditions in which the USBFS generates the internal NRDY interrupt request for a given
pipe.
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The internal NRDY interrupt request is not generated during status stage execution of the control transfer.
(a)
For the transmitting pipe
When an IN token is received while there is no data to be transmitted in the FIFO buffer, the USBFS generates a NRDY
interrupt request at the reception of the IN token and sets the NRDYSTS.PIPEnNRDY bit to 1.
(b)
For the receiving pipe
When an OUT token is received while there is no space available in the FIFO buffer.
For the pipe for transfers in which an interrupt is generated, the USBFS generates an NRDY interrupt request when an
NAK handshake is transferred after the data following the OUT token is received, and sets the PIPEnNRDY bit to 1.
However, during retransmission (due to DATA-PID mismatch), the NRDY interrupt request is not generated. In addition,
if an error occurs in the DATA packet, the NRDY interrupt request is not generated.
Figure 24.11 shows the timing of NRDY interrupt generation.
(1) Example of data transmission (single-buffer mode)
IN Token Packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
NAK Handshake
Ready for write access (there is no data to be transmitted)
*1
A NRDY interrupt is generated
(2) Example of data reception: OUT token reception (single-buffer mode)
OUT Token Packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
Data Packet
NAK Handshake
Ready for read access (there is no space to receive data)
*1
A NRDY interrupt is generated
(3) Example of data reception: PING token reception (single-buffer mode)
PING Packet
USB bus
FIFO buffer status
NRDY interrupt
(NRDYSTS.PIPEnNRDY bit)
NAK Handshake
Ready for read access (there is no space to receive data)
*1
A NRDY interrupt is generated
Packet transmitted by host device
Packet transmitted by a device
Note 1. The value of the PIPEnNRDY bit changes to 1 only when the PIPEnPID[1:0] bits are set to 01b (BUF response).
Figure 24.11
Timing of NRDY interrupt generation
24.3.3.3
BEMP interrupt
On detecting a BEMP interrupt for the pipe whose PID bits are set to BUF by software, the USBFS sets the associated
BEMPSTS.PIPEnBEMP bit to 1. If the associated bit in BEMPENB is set to 1 by software, the USBFS sets the
INTSTS0.BEMP bit to 1 and generates a USB interrupt.
The following sections describe the conditions in which the USB generates an internal BEMP interrupt request.
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(1)
24. USB 2.0 Full-Speed Module (USBFS)
For the transmitting pipe
When the FIFO buffer of the associated pipe is empty on completion of transmission (including zero-length packet
transmission).
In single buffer mode, an internal BEMP interrupt request is generated simultaneously with the BRDY interrupt for the
pipe other than DCP.
The internal BEMP interrupt request is not generated on any of the following conditions:
When the CPU started to write data to the FIFO buffer of the CPU on completion of transmitting data from one
FIFO buffer in double buffer mode
When the buffer is cleared by setting the PIPEnCTR.ACLRM or the BCLR bit in the port control register to 1
When IN transfer (zero-length packet transmission) is performed during the control transfer status stage.
(2)
For the receiving pipe
When the successfully-received data packet size exceeds the specified maximum packet size. In this case, the USBFS
generates a BEMP interrupt request, sets the associated BEMPSTS.PIPEnBEMP bit to 1, discards the received data, and
modifies the setting of the PID[1:0] bits of the associated pipe to STALL (11b). The USBFS returns STALL response.
The internal BEMP interrupt request is not generated on any of the following conditions:
When a CRC error or a bit stuffing error is detected in the received data
When a setup transaction is performed:
Writing 0 to the BEMPSTS.PIPEnBEMP bit clears the status
Writing 1 to the BEMPSTS.PIPEnBEMP bit has no effect.
Figure 24.12 shows the timing of BEMP interrupt generation.
(1) Example of data transmission
USB bus
IN Token Packet
Data Packet
ACK Handshake
Ready for transmission
FIFO buffer status
Ready for write access
(there is no data to be
transmitted)
BEMP interrupt
(BEMPSTS.PIPEnBEMP bit)
A BEMP interrupt is generated
(2) Example of data reception
OUT Token Packet
USB bus
Data Packet (Maximum
Packet size over)
STALL Handshake
BEMP interrupt
(BEMPSTS.PIPEnBEMP bit)
A BEMP interrupt is generated
Packet transmitted by host device
Packet transmitted by a device
Figure 24.12
Timing of BEMP interrupt generation
24.3.3.4
Device state transition interrupt
Figure 24.13 is a diagram of device state transitions in the USBFS. The USBFS controls device state and generates
device state transition interrupts. However, recovery from the suspended state (resumed signal detection) is detected by
means of the resumed interrupt. The device state transition interrupts can be enabled or disabled individually using
INTENB0. The device state to which a transition is made can be confirmed using the INTSTS0.DVSQ[2:0] bits.
When a transition is made to the default state, a device state transition interrupt is generated after a USB bus reset is
detected.
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24. USB 2.0 Full-Speed Module (USBFS)
Suspended state detection
(DVST is set to 1)
Powered
state
(DVSQ = 000b)
Suspended
state
(DVSQ = 100b)
Resumed (RESM is set to 1)
USB bus reset detection
(DVST is set to 1)
USB bus reset detection
(DVST is set to 1)
Suspended state detection
(DVST is set to 1)
Default
state
(DVSQ = 001b)
Suspended
state
(DVSQ = 101b)
Resumed (RESM is set to 1)
SetAddress
execution
(Address = 0)
(DVST is set to 1)
(Address > 0)
SetAddress execution
(DVST is set to 1)
Suspended state detection
(DVST is set to 1)
Address
state
(DVSQ = 010b)
SetConfiguration
execution
(configuration value = 0)
(DVST is set to 1)
Suspended
state
(DVSQ = 110b)
Resumed (RESM is set to 1)
SetConfiguration execution
(configuration value 0)
(DVST is set to 1)
Suspended state detection
(DVST is set to 1)
Configured
state
(DVSQ = 011b)
Suspended
state
(DVSQ = 111b)
Resumed (RESM is set to 1)
Note:
For the transition indicated in solid line, the DVST bit is set to 1.
For the transition indicated in dashed line, the RESM bit is set to 1.
Figure 24.13
Device state transitions
24.3.3.5
Control transfer stage transition interrupt
Figure 24.14 is a diagram of control transfer stage transitions in the USBFS. The USBFS controls the control transfer
sequence and generates control transfer stage transition interrupts. The control transfer stage transition interrupts can be
enabled or disabled individually using INTENB0. The transfer stage to which a transition is made can be confirmed
using the INTSTS0.CTSQ[2:0] bits. Control transfer stage transition interrupts are generated.
This section describes control transfer sequence errors. When an error occurs, the DCPCTR.PID[1:0] bits are set to 1xb
(STALL response).
(1)
Control read transfer errors
An OUT token is received while no data is transferred for the IN token at the data stage
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An IN token is received at the status stage
A data packet with DATAPID = DATA0 is received at the status stage.
(2)
Control write transfer errors
An IN token is received while no ACK response is returned for the OUT token at the data stage
A data packet with DATAPID = DATA0 is received for the first data packet at the data stage
An OUT token is received at the status stage.
(3)
No data control transfers
An OUT token is received at the status stage.
At the control write transfer data stage, if the received data length exceeds the wLength value of the USB request, it
cannot be recognized as a control transfer sequence error. At the control read transfer status stage, packets other than
zero-length packets are received by an ACK response and the transfer ends normally.
When a CTRT interrupt occurs in response to a sequence error (INTSTS0.CTRT = 1), the CTSQ[2:0] = 110b value is
retained until the CTRT bit = 0 is written from the system (the interrupt status is cleared). Therefore, while CTSQ[2:0] =
110b is being held, the CTRT interrupt that ends the setup stage is not generated even when a new USB request is
received. The USBFS saves the setup stage completion status and generates a CTRT interrupt after software clears the
interrupt.
Setup token reception
Setup token reception
C TSQ = 110b
control transfer
sequence error
5
Error
detection
Error detection and setup token
reception are valid at all stages
in the box
Setup
token reception
C TSQ = 000b
setup stage
ACK
transm ission
1
C TSQ = 001b
control read
data stage
O UT token
2
C TSQ = 010b
control read
status stage
ACK
transm ission
4
C TSQ = 000b
idle stage
4
ACK
transm ission
1
C TSQ = 011b
control w rite
data stage
IN token
3
C TSQ = 100b
control w rite
status stage
1
C TSQ = 101b
no data control
status stage
ACK
transm ission
Note:
ACK
reception
ACK
reception
CTRT interrupts
1
Setup stage com pleted
2
Control read transfer status stage transition
3
Control write transfer status stage transition
4
Control transfer com pleted
5
Control transfer sequence error
Figure 24.14
Control transfer stage transitions
24.3.3.6
Frame update interrupt
The USBFS updates the frame number and generates an SOFR interrupt if it detects a new SOF packet during full-speed
operation.
24.3.3.7
VBUS interrupt
When the USB_VBUS pin level changes, a VBUS interrupt is generated. The level of the USB_VBUS pin can be
checked with the INTSTS0.VBSTS bit. Whether the host controller is connected or disconnected can be confirmed using
the VBUS interrupt. However, if the system is activated with the host controller connected, the first VBUS interrupt is
not generated because there is no change in the USB_VBUS pin level.
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24.3.3.8
24. USB 2.0 Full-Speed Module (USBFS)
Resumed interrupt
A resumed interrupt is generated when the device state is the suspended state and the USB bus state is changed from Jstate to K-state, or from J-state to SE0. Recovery from the suspended state is detected by means of the resumed interrupt.
24.3.4
Pipe Control
Table 24.15 lists the pipe settings for the USBFS. USBFS data transfer is performed through pipes that software has
associated with the endpoint. The USBFS has 5 pipes for data transfer.
Set each pipe appropriately based on your system specifications.
Table 24.15
Register
name
DCPCFG
PIPECFG
Pipe settings
Bit name
Setting
Remarks
TYPE
Specify the transfer type
PIPE4 to PIPE7: Can be set
BFRE
Select the BRDY interrupt mode
PIPE4 and PIPE5: Can be set
DBLB
Select double buffer mode
PIPE4 and PIPE5: Can be set
DIR
Select transfer direction
IN or OUT can be set
EPNUM
Endpoint number
PIPE4 to PIPE7: Can be set
Set a value other than 0000b when the pipe is used.
SHTNAK
Select disabled state for pipe
when transfer ends
PIPE4 and PIPE5: Can be set
DCPMAXP
PIPEMAXP
MXPS
Maximum packet size
Compliant with USB 2.0 Specification
DCPCTR
PIPEnCTR
BSTS
Buffer status
For the DCP, receive buffer status and transmit buffer status
are switched with the ISEL bit
INBUFM
IN buffer monitor
Available only for PIPE4 and PIPE5
ATREPM
Auto response mode
PIPE4 and PIPE5: Can be set
ACLRM
Auto buffer clear
PIPE4 to PIPE7: Can be set
SQCLR
Sequence clear
Clear the data toggle bit
SQSET
Sequence set
Set the data toggle bit
SQMON
Sequence monitor
Monitor the data toggle bit
PBUSY
Pipe busy status
-
PIPEnTRE
PIPEnTRN
24.3.4.1
PID
Response PID
See section 24.3.4.6, Response PID
TRENB
Transaction counter enable
PIPE4 and PIPE5: Can be set
TRCLR
Current transaction counter clear
PIPE4 and PIPE5: Can be set
TRNCNT
Transaction counter
PIPE4 and PIPE5: Can be set
Pipe control register switching procedures
Do not modify the following bits in the pipe control registers when USB communication is enabled (PID = BUF):
Bits in DCPCFG and DCPMAXP
SQCLR and SQSET bits in DCPCTR
Bits in PIPECFG and PIPEMAXP
ATREPM, ACLRM, SQCLR, and SQSET bits in PIPEnCTR
Bits in PIPEnTRE and PIPEnTRN.
To modify those bits when USB communication is enabled (PID = BUF) state, use the following procedure:
1. When a request to modify bits in the pipe control register occurs, modify the PID[1:0] bits associated with the pipe
to NAK.
2. Wait until the corresponding PBUSY bit is set to 0.
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24. USB 2.0 Full-Speed Module (USBFS)
3. Modify the bits in the pipe control register.
The following bits in the pipe control registers can be modified only when the selected pipe information is not set by the
CURPIPE[3:0] bits in CFIFOSEL:
Bits in DCPCFG and DCPMAXP
Bits in PIPECFG and PIPEMAXP.
To change pipe information, the CURPIPE[3:0] bits in the port select registers to a pipe other than the one to be
modified. For DCP, clear the buffer with the BCLR bit in the Port Control Register after the pipe information is changed.
24.3.4.2
Transfer types
The PIPECFG.TYPE[1:0] bits specify the transfer type for each pipe. The available transfer types are:
DCP — No setting is necessary (fixed at control transfer)
PIPE4 and PIPE5 — These should be set to bulk transfer
PIPE6 and PIPE7— These should be set to interrupt transfer.
24.3.4.3
Endpoint number
The PIPECFG.EPNUM[3:0] bits set the endpoint number for each pipe. The DCP is fixed at endpoint 0. The other pipes
can be set from endpoint 1 to endpoint 15:
DCP — No setting is necessary (fixed at endpoint 0)
PIPE4 to PIPE7 — Select and set the endpoint numbers from 1 to 15 so that the combination of the PIPECFG.DIR
bit and EPNUM[3:0] bits is unique.
24.3.4.4
Maximum packet size setting
The DCPMAXP.MXPS[6:0] bits and the PIPEMAXP.MXPS[8:0] bits specify the maximum packet size for each pipe.
DCP, PIPE4 and PIPE5 can be set to any of the maximum pipe sizes defined by the USB 2.0 Specification. For PIPE6
and PIPE7, 64 bytes are the upper limit of the maximum packet size. Set the maximum packet size as follows before
starting a transfer (PID = BUF):
DCP — Set 8, 16, 32, or 64
PIPE4 and PIPE5 — Set 8, 16, 32, or 64 for using bulk transfer
PIPE6 and PIPE7 — Set a value between 1 and 64.
24.3.4.5
Transaction counter for PIPE4 and PIPE5 in the receiving direction
When the specified number of transactions is complete in the data packet receiving direction, the USBFS recognizes that
the transfer has ended. Two transaction counters are provided:
The PIPEnTRN register that specifies the number of transactions to be executed.
The current counter that internally counts the number of executed transactions.
With the PIPECFG.SHTNAK bit set to 1, when the current counter value matches the specified number of transactions,
the associated PIPEnCTR.PID[1:0] bits are set to NAK and the subsequent transfer is disabled. The transactions can be
counted again from the beginning by initializing the current counter of the transaction counter function through the
PIPEnTRE.TRCLR bit. The data read from PIPEnTRN differs depending on the PIPEnTRE.TRENB setting as follows:
The TRENB bit = 0 — the specified transaction counter value can be read
The TRENB bit = 1 — the current counter value that indicates the internally counted number of executed
transactions can be read.
When working with the TRCLR bit, the following constraints apply:
If the transactions are counted and PID = BUF, the current counter cannot be cleared
If there is any data left in the buffer, the current counter cannot be cleared.
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24.3.4.6
24. USB 2.0 Full-Speed Module (USBFS)
Response PID
The PID[1:0] bits in DCPCTR and PIPEnCTR set the response PID for each pipe.
The following sections describe the USBFS operation with different response PID settings.
(1)
Response PID settings
The response PID specifies the response to transactions from the host:
NAK setting — the NAK response is returned in response to the generated transaction
BUF setting — the responses are made to transactions according to the status of the buffer memory
STALL setting — the STALL response is returned in response to the generated transaction.
Note:
For setup transactions, an ACK response is returned regardless of the PID[1:0] setting, and the USB request is
stored in the register.
The USBFS can write to the PID[1:0] bits, depending on the results of the transaction as described in the following
section:
(2)
When the response PID is set by hardware
NAK setting — PID = NAK is set and NAK is returned in response to the following transactions:
When the SETUP token is received normally (DCP only)
If the transaction counting ends or a short packet is received when the PIPECFG.SHTNAK bit is set to 1 for bulk
transfer.
BUF setting — there is no BUF writing by the USB.
STALL setting — PID = STALL is set and STALL is returned in response to the following transactions:
When a maximum packet size exceeded error is detected in the received data packet
When a control transfer sequence error is detected (DCP only).
24.3.4.7
Data PID sequence bit
The USBFS automatically toggles the sequence bit in the data PID when data is transferred successfully in the control
transfer data stage, bulk transfer, and interrupt transfer. The sequence bit of the next data PID to be transmitted can be
confirmed with the SQMON bit in DCPCTR and PIPEnCTR. When data is transmitted, the sequence bit switches at
ACK handshake reception. When data is received, the sequence bit switches at ACK handshake transmission. The
SQCLR and SQSET bits in DCPCTR and PIPEnCTR registers can be used to change the data PID sequence bit.
When the control transfer is used, the USBFS automatically sets the sequence bit when a stage transition is made.
DATA1 is returned when the setup stage ended. The sequence bit is not referenced and PID = DATA1 is returned in a
status stage. Therefore, software settings are not required.
For the ClearFeature request transmission or reception, software should set the data PID sequence bit.
24.3.4.8
Response PID = NAK function
The USBFS provides a function that disables pipe operation (PID response = NAK) when the final data packet of a
transaction is received (the USB automatically distinguishes this based on reception of a short packet or the transaction
counter) by setting the PIPECFG.SHTNAK bit to 1.
When the double buffer mode is used for the buffer memory, this function enables reception of data packets in transfer
units. If pipe operation is disabled, software should set the pipe to the enabled state again (PID response = BUF).
The response PID = NAK function can only be used for bulk transfers.
24.3.4.9
Auto response mode
For bulk transfer PIPE4 and PIPE5, when the PIPEnCTR.ATREPM bit is set to 1, a transition is made in auto response
mode. During an OUT transfer (PIPECFG.DIR bit is 0), OUT-NAK mode is entered, and during an IN transfer (DIR bit
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24. USB 2.0 Full-Speed Module (USBFS)
is 1), null auto response mode is entered.
24.3.4.10
OUT-NAK mode
For bulk OUT transfer pipes, NAK is returned in response to an OUT token and an NRDY interrupt is output when the
PIPEnCTR.ATREPM bit is set to 1. To make a transition from normal mode to OUT-NAK mode, specify OUT-NAK
mode while pipe operation is disabled (response PID = NAK) before enabling pipe operation (response PID = BUF).
After pipe operation is enabled, OUT-NAK mode becomes valid. If an OUT token is received immediately before pipe
operation is disabled, the token data is received and an ACK is returned to the host.
To transition from OUT-NAK mode to normal mode, cancel OUT-NAK mode while pipe operation is disabled (response
PID = NAK) before enabling pipe operation (response PID = BUF). In normal mode, reception of OUT data is enabled.
24.3.4.11
Null auto response mode
For bulk IN transfer pipes, zero-length packets are continuously transmitted when the PIPEnCTR.ATREPM bit is set to
1.
To transition from normal mode to null auto response mode, specify null auto response mode while pipe operation is
disabled (response PID = NAK) before enabling pipe operation (response PID = BUF). After pipe operation is enabled,
null auto response mode becomes valid. Before setting null auto response mode, check that PIPEnCTR.INBUFM = 0
because the mode can only be set when the buffer is empty. If the INBUFM bit is 1, empty the buffer with the
PIPEnCTR.ACLRM bit. Do not write data from the FIFO port while a transition to null auto response mode is made.
To transition from null auto response mode to normal mode, keep pipe operation disabled (response PID = NAK) for the
period of zero-length packet transmission (about 10 µs) before canceling null auto response mode. In normal mode, data
can be written from the FIFO port so packet transmission to the host is enabled by enabling pipe operation (response PID
= BUF).
24.3.5
FIFO Buffer Memory
The USBFS has FIFO buffer memory for data transfers and it manages the memory area used for each pipe. The FIFO
buffer memory has two states depending on whether the access right is assigned to the system (CPU side) or the USB
(SIE side).
(1)
Buffer status
Table 24.16 and Table 24.17 show the buffer status in the USBFS. The buffer memory status can be confirmed with the
BSTS bit in DCPCTR and the INBUFM bit in PIPEnCTR. The transfer direction for the buffer memory can be specified
in either PIPECFG.DIR bit or CFIFOSEL.ISEL bit (when DCP is selected). The INBUFM bit is valid for PIPE4 and
PIPE5 in the transmitting direction.
When a transmitting pipe uses the double buffer configuration, software can read the BSTS bit to monitor the buffer
memory status on the CPU side and the INBUFM bit to monitor the buffer memory status on the SIE side. When the
BEMP interrupt does not show the buffer empty status because write access to the FIFO port by the CPU is slow,
software can use the INBUFM bit to confirm the end of transmission.
Table 24.16
Buffer status indicated by BSTS bit
ISEL or DIR
BSTS
Buffer memory status
0 (receiving direction)
0
There is no received data or data is being received. Reading from the FIFO port is
disabled.
0 (receiving direction)
1
There is received data, or a zero-length packet is received. Reading from the FIFO port is
allowed.
Note:
When a zero-length packet is received, reading is not possible and the buffer
must be cleared.
1 (transmitting direction)
0
The transmission is not complete. Writing to the FIFO port is disabled.
1 (transmitting direction)
1
The transmission is complete. CPU write is allowed.
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Table 24.17
24. USB 2.0 Full-Speed Module (USBFS)
Buffer status indicated by INBUFM bit
DIR
INBUFM
Buffer memory status
0 (receiving direction)
Invalid
Invalid
1 (transmitting direction)
0
The transmission is complete.
There is no waiting data to be transmitted.
1 (transmitting direction)
1
The FIFO port has written data to the buffer.
There is data to be transmitted.
24.3.6
FIFO Buffer Clearing
Table 24.18 shows methods for clearing the FIFO buffer memory by the USBFS. The buffer memory can be cleared
using the BCLR bit in the Port Control Register, and the PIPEnCTR.ACLRM bit.
Either a single or double buffer configuration can be selected for PIPE4 and PIPE5, using the PIPECFG.DBLB bit.
Table 24.18
Buffer clearing methods
FIFO buffer clearing mode
Clearing buffer memory on CPU side
Auto buffer clear mode for discarding all
received packets
Register used
CFIFOCTR
PIPEnCTR
Bit used
BCLR
ACLRM
Clearing condition
Cleared by writing 1
1: Mode valid
0: Mode invalid
(1)
Auto buffer clear mode function
The USBFS discards all received data packets if the PIPEnCTR.ACLRM bit is set to 1. If a correct data packet is
received, the ACK response is returned to the host controller. The auto buffer clear mode function can only be set in the
buffer memory reading direction.
Setting the ACLRM bit to 1 and then to 0 clears the buffer memory of the selected pipe regardless of the access direction.
An access cycle of at least 100 ns is required for the internal hardware sequence processing time between ACLRM = 1
and ACLRM = 0.
24.3.7
FIFO Port Functions
Table 24.19 shows the settings for the FIFO port functions of the USBFS. In write access, writing data until the
maximum packet size is reached automatically enables transmission of the data. To enable transmission before the
maximum packet size is reached, set the BVAL bit in the port control register to end writing. To send a zero-length
packet, use the BCLR bit to clear the buffer and set the BVAL bit set to end writing.
In reading, reception of new packets is automatically enabled when all data is read. Data cannot be read when a zerolength packet is received (the DTLN[8:0] bits = 0) therefore, use the BCLR bit to clear the buffer. The length of the
received data can be confirmed with the DTLN[8:0] bits in the port control register.
Table 24.19
FIFO port function settings (1 of 2)
Register name
Bit name
CFIFOSEL
RCNT
Selects DTLN[8:0] read mode
REW
Buffer memory rewind (re-read, rewrite)
MBW
FIFO port access bit width
BIGEND
Selects FIFO port endian
ISEL
FIFO port access direction (only for DCP)
CURPIPE
Selects the current pipe
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Table 24.19
24. USB 2.0 Full-Speed Module (USBFS)
FIFO port function settings (2 of 2)
Register name
Bit name
Description
CFIFOCTR
BVAL
Ends writing to the buffer memory
BCLR
Clears the buffer memory on the CPU side
DTLN
Checks the length of received data
(1)
FIFO port selection
Table 24.20 shows the pipes that can be selected with the different FIFO ports. The pipe to be accessed must be selected
using the CURPIPE[3:0] bits in the Port Select Register. After a pipe is selected, software must check whether the written
value can be correctly read from the CURPIPE[3:0] bits. If the previous pipe number is read, it indicates that the USBFS
is modifying the pipe. Next, the software checks that the FRDY bit in the Port Control Register is 1.
In addition, software must specify the bus width to be accessed using the MBW bit in the port select register. The buffer
memory access direction conforms to the PIPECFG.DIR bit. Only for the DCP that the ISEL bit in the port select register
determines the direction.
Table 24.20
FIFO port access by pipe
Pipe
Access method
Port that can be used
DCP
CPU access
CFIFO port register
PIPE4 to PIPE7
CPU access
CFIFO port register
(2)
REW bit
It is possible to temporarily stop access to a pipe currently being accessed, access a different pipe, and then continue to
process for the first pipe again. Use the REW bit in the port select register for this processing.
If a pipe is selected in the CURPIPE[3:0] bits in the port select register with the REW bit set to 1, the pointer used for
reading from and writing to the buffer memory is reset. Reading or writing can be carried out from the first byte. If a pipe
is selected with 0 set for the REW bit, data can be read and written in continuation from the previous selection, without
the pointer being reset. To access the FIFO port, software must check that the FRDY bit in the port control register is 1
after selecting a pipe.
24.3.8
Control Transfers Using DCP
In the data stage of control transfers, data is transferred using the default control pipe (DCP).
The DCP buffer memory is a 64-byte single buffer and is a fixed area that is shared for both control reading and control
writing. The buffer memory can only be accessed through the CFIFO port.
24.3.8.1
(1)
Control transfers
Setup stage
The USBFS sends an ACK response for the correct setup packet targeted to the USBFS. The operation of the USBFS in
the setup stage is described as follows:
When receiving a new setup packet, the USBFS sets the following bits:
INTSTS0.VALID bit to 1
DCPCTR.PID[1:0] bits to NAK
DCPCTR.CCPL bit to 0.
When receiving a data packet after the setup packet, the USBF stores the request parameters in USBREQ, USBVAL,
USBINDX, and USBLENG. Perform response processing with respect to the control transfer after setting the VALID bit
to 0. When the VALID bit is 1, PID = BUF cannot be set, and the data stage cannot be terminated.
Using the function of the VALID bit, the USBFS can suspend the current processing request when receiving a new
request during a control transfer. The USBFS can then send a response to the newest request.
Additionally, the USB automatically detects the direction bit, that is, bit [8] of bmRequestType, and the request data
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24. USB 2.0 Full-Speed Module (USBFS)
length (wLength) of the received request. The USBFS also automatically distinguishes between control read transfer,
control write transfer, no-data control transfer, and control stage transitions. For an incorrect sequence, the sequence
error of the control transfer stage transition interrupt is generated, and software is notified of the error. For the stage
control of the USBFS, see Figure 24.14.
(2)
Data stage
Data transfers associated with received USB requests are performed using the DCP. Before accessing the DCP buffer
memory, specify the access direction using the CFIFOSEL.ISEL bit. If the transfer data is larger than the size of the DCP
buffer memory, perform data transfer using the BRDY interrupt for control write transfers and the BEMP interrupt for
control read transfers.
(3)
Status stage
Control transfers are terminated by setting the DCPCTR.CCPL bit to 1 while the DCPCTR.PID[1:0] bits are set to BUF.
After the specified settings are made, the USBFS automatically executes the status stage according to the data transfer
direction determined at the setup stage. The procedure is as follows:
For control read transfers:
A zero-length packet is received from the USB host and an ACK response is sent.
For control write transfers and no-data control transfers:
A zero-length packet is transmitted and an ACK response is received from the USB host.
(4)
Control transfer auto response function
The USBFS automatically responds to a correct SET_ADDRESS request. If any of the following errors occurs in the
SET_ADDRESS request, a response from software is necessary:
bmRequestType is not 00h — any transfer other than a control write transfer
wIndex is not 00h — request error
wLength is not 00h — any transfer other than a no-data control transfer
wValue is larger than 7Fh — request error
INTSTS0.DVSQ[2:0] are 011b (Configured state) — control transfer of a device state error.
For all requests other than the SET_ADDRESS request, a response is required from the associated software.
24.3.9
Bulk Transfers (PIPE4 and PIPE5)
The buffer memory usage (single or double buffer setting) can be selected for bulk transfers. The USBFS provides the
following functions for bulk transfers:
BRDY interrupt function (PIPECFG.BFRE bit, see section 24.3.3.1, (2) When the SOFCFG.BRDYM bit = 0 and
the PIPECFG.BFRE bit = 1)
Transaction count function (PIPEnTRE.TRENB, TRCLR, and PIPEnTRN.TRNCNT[15:0] bits, see section
24.3.4.5, Transaction counter for PIPE4 and PIPE5 in the receiving direction)
Response PID = NAK function (PIPECFG.SHTNAK bit, see section 24.3.4.8, Response PID = NAK function)
Auto response mode (PIPEnCTR.ATREPM bit, see section 24.3.4.9, Auto response mode).
24.3.10
Interrupt Transfers (PIPE6 and PIPE7)
The USBFS performs interrupt transfers based on the timing controlled by the host controller.
24.3.11
24.3.11.1
Pipe Schedule
Transfer schedule
This section describes the transfer scheduling within a frame of the USBFS. After the USBFS sends an SOF, the transfer
is performed in the sequence as described in this section.
1. Execution of periodic transfers
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24. USB 2.0 Full-Speed Module (USBFS)
A pipe is searched in the order of PIPE6 PIPE7, if there is a pipe for which an interrupt transfer transaction can
be generated, the transaction is generated.
2. Setup transactions for control transfers
The DCP is checked and if a setup transaction is possible, it is sent.
3. Execution of bulk transfers, control transfer data stages, and control transfer status stages
A pipe is searched in the order of DCP PIPE4 PIPE5, if there is a pipe for which a transaction is for a bulk
transfer, a control transfer data stage, or a control transfer status stage, the transaction is generated.
When a transaction is generated, processing moves to the next pipe transaction regardless of whether the response
from the peripheral device is ACK or NAK. If there is time for transfer within the frame, this step is repeated.
24.3.12
Battery Charging Detection Processing
It is possible to control the processing for data contact detection (D+ line contact check), primary detection (charger
detection), and secondary detection (charger verification), which are defined in the Battery Charging Specification. This
section describes the required operations for a function device and a host device, individually.
24.3.12.1
Processing
The following processing is required when operating the USBFS module as a portable device for battery charging:
1. Detect when the data lines (D+ and D–) made contact and start the processing for primary detection.
2. After primary detection starts, wait 40 ms for masking, then check the D– voltage level to confirm the primary
detection result.
3. If the charger is detected during primary detection, start the secondary detection.
4. After the secondary detection starts, wait 40 ms for masking, then check the D+ voltage level to confirm the
secondary detection result.
For step 1., after VBUS is detected using the VBINT bit and the VBSTS bit, wait for 300 to 900 ms by software, then set
the VDPSRCE0 and IDMSINKE0 bits in the USBBCCTRL0 register. You can also set the IDPSRCE0 bit and after a
change from high to low on the D+ line is detected using the LNST bits, clear the IDPSRCE0 bit and set the VDPSRCE0
and IDMSINKE0 bits. Set the VDPSRCE0 and IDMSINKE0 bits at the same time.*1
For step 2., set the VDPSRCE0 and IDMSINKE0 bits and wait 40 ms by software, and then use the CHGDETSTS0 bit to
verify the primary detection result.*2
For step 3., if the CHGDETSTS0 bit is set in step 2., verify that the charger is detected, then clear the VDPSRCE0 and
IDMSINKE0 bits, and set the VDMSRCE0 and IDPSINKE0 bits.
For step 4., set the VDMSRCE and IDPSINKE0 bits and wait for 40 ms by software, then use the PDDETSTS0 bit to
verify the secondary detection result.
Figure 24.15 shows the process flow.
Note 1. The Battery Charging Specification describes two ways to process data contact detection (D+/D– line contact
check). One method is to detect a change to logic low due to the pull-down resistor of the host device when the
D+ and D– lines make contact with the target, while the D+ line is held at logic high by applying a current of 7 to
13μA on the D+ line. The other method is to wait for 300 to 900 ms after VBUS is detected.
Note 2. During primary detection, when the voltage on the D– line is detected to be 0.25 to 0.4 V or above and 0.8 to 2.0
V or below, the target device is recognized as the host device for battery charging, that is, charging downstream
port. When using a PHY in which the CHGDETSTS0 bit only indicates that the voltage on the D– line is 0.25 to
0.4 V or above, add the processing to check that the voltage on D– line is 0.8 V to 2.0 V or below using the LNST
bits, as necessary.
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24. USB 2.0 Full-Speed Module (USBFS)
Detect VBUS
Set BATCHGE0 bit
Set CNEN bit
Data Contact Detection
(software waiting method)
Wait for min. 300 ms?
Yes
Data Contact
Detection
(hardware
detection
method)
Set RPDME0 bit
Set IDPSRCE0 bit
No
Use LNST[1:0] for
check
Is D+ low?
No
Yes
Clear RPDME0 bit
Clear IDPSRCE0 bit
Primary
Detection
Set VDPSRCE0 and
IDMSINKE0 bits
Wait for min 40 ms?
No
Yes
Read CHGDETSTS0 bit
CHGDETSTS0 = 1?
No
Yes
Target is SDP
Target is DCP or CDP
Clear VDPSRCE0 and
IDMSINKE0 bits
Secondary
Detection
Set VDMSRCE0 and
IDPSINKE0 bits
Wait for min. 40 ms?
No
Yes
Read PDDETSTS0 bit
PDDETSTS0 = 1?
Yes
No
Target is CDP
Target is DCP
Figure 24.15
Process flow for operating as portable device
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24.4
24.4.1
24. USB 2.0 Full-Speed Module (USBFS)
Usage Note
Settings for the Module-Stop State
The Module Stop Control Register B (MSTPCRB) can enable or disable operation of the USBFS. The USBSF is stopped
after a reset. The registers become accessible on release from the module-stop state. For details, see section 10, Low
Power Modes.
24.4.2
Clear of Interrupt Status Register after Software Standby mode
When the following conditions are met at the same time, the unexpected interrupt might occur because the input buffer is
always enabled in the Software Standby mode:
Enable the interrupt when the MCU is Normal mode
Prohibit the interrupt when the MCU is Software Standby mode
When the input level of pin which cancels the software standby is changed in Software Standby mode.
The interrupt flag is set to the interrupt status register in the specified condition. After canceling the Software Standby
mode, the unexpected interrupt can be propagated to the interrupt controller. Therefore, in the canceling sequence, the
INTSTS0 and INTSTS1 registers must be cleared.
24.4.3
Clear of Interrupt Status Register after Setting the Port Function
The input buffer is disabled before setting the port (PmnPFS.PSEL and PmnPFS.PMR) so the internal signal is fixed to
high or low. Therefore, the input buffer is enabled after setting the port, so the external pin state is propagated into the
chip. At this time, an unexpected interrupt might occur and the interrupt status such as INTSTS0 is set to 1, especially the
VBINT bit. To avoid malfunction, the INTSTS0 register must be cleared after setting the port.
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25.
25. Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
The Serial Communications Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:
Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter (ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol.
SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be
configured independently using an on-chip baud rate generator.
25.1
Overview
Table 25.1 lists the specifications of the SCI.
Table 25.1
SCI specifications (1 of 2)
Parameter
Description
Serial communication modes
Asynchronous
Clock synchronous
Smart card interface
Simple IIC
Simple SPI.
Transfer speed
Bit rate specifiable with the on-chip baud rate generator
Full-duplex communications
Transmitter: Continuous transmission possible using double-buffering
Receiver: Continuous reception possible using double-buffering
I/O pins
See Table 25.2
Data transfer
Selectable as LSB-first or MSB-first transfer
Interrupt sources
Transmit end, transmit data empty, receive data full, receive error, receive
data ready, and address match
Completion of generation of a start condition, restart condition, or stop
condition (for simple IIC mode)
Module-stop function
Module-stop state can be set for each channel
Snooze end request
Asynchronous mode
SCI0 address mismatch (SCI0_DCUF)
Data length
7, 8, or 9 bits
Transmission stop bit
1 or 2 bits
Parity
Even parity, odd parity, or no parity
Receive error detection
Parity, overrun, and framing errors
Hardware flow control
CTSn_RTSn pin can be used in controlling transmission/reception
Transmission/Reception
Selectable as either 1 stage register or 16 stage FIFO (only SCI0 supports
FIFO)
Address match
The interrupt request/event output can be issued when detecting a match
between received data and the value of compare match register
Address mismatch (SCI0
only) receive data
The snooze end request can be issued when detecting a mismatch between
the received data and the value of the Compare Match Register
Start-bit detection
Low level or falling edge is selectable
Break detection
Break detectable on framing error with SPTR register read
Clock source
An internal or external clock can be selected
Double-speed mode
Baud rate generator double-speed mode is selectable
Multi-processor
communications function
Serial communication between multiple processors
Noise cancellation
The signal paths from input on the RXDn pins incorporate digital noise filters
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Table 25.1
25. Serial Communications Interface (SCI)
SCI specifications (2 of 2)
Parameter
Clock synchronous
mode
Smart card interface
mode
Description
Data length
8 bits
Receive error detection
Overrun error
Clock source
An internal clock (Master mode) or external clock (Slave mode) can be
selected
Hardware flow control
CTSn_RTSn pin can be used in controlling transmission/reception
Transmission/Reception
Selectable as either 1 stage register or 16 stage FIFO (only SCI0 supports
FIFO)
Error processing
An error signal can be automatically transmitted when detecting a parity error
during reception
Data can be automatically retransmitted when receiving an error signal during
transmission
Simple IIC mode
Simple SPI mode
Data type
Both direct convention and inverse convention are supported
Transfer format
I2C bus format (MSB-first only)
Operating mode
Master (single-master operation only)
Transfer rate
Up to 400 kbps
Noise cancellation
The signal paths from input on the SCLn and SDAn pins incorporate digital
noise filters, and provide an adjustable interval for noise cancellation
Data length
8 bits
Detection of errors
Overrun error
Clock source
An internal clock (Master mode) or external clock (Slave mode) can be
selected
SS input pin function
Applying the high level to the SSn pin can cause the output pins to enter the
high impedance state
Clock settings
Four kinds of settings for clock phase and clock polarity are selectable
Bit rate modulation function
Correction of outputs from the on-chip baud rate generator can reduce errors
Event link function
Error (receive error or error signal detection) event output (SCIn_ERI*1)
Receive data full event output (SCIn_RXI*1, *2)
Transmit data empty event output (SCIn_TXI*1, *2)
Transmit end event output (SCIn_TEI*1, *2)
Address match event output (SCIn_AM*1)
Note 1. Channel number (n = 0, 1, 9)
Note 2. Using this event link function is prohibited when the FIFO is selected in asynchronous mode.
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25. Serial Communications Interface (SCI)
Bus Interface
S124 User’s Manual
Module Data Bus
RDRHL FRDRH*1
RDR
RXDn/SCLn/
MISOn
TDRHL
FTDRH*1
TDR
FTDRL*1
FRDRL*1
TSR
RSR
Parity addition
Match check
Parity check
TXDn/SDAn/
MOSIn
SCMR
SSR/SSR_SMCI/
SSR_FIFO*1
SCR/SCR_SMCI
SMR/SMR_SMCI
SEMR
SPMR
FCR*1
FDR*1
LSR*1
CDR
DCCR
SPTR
BRR
MDDR
Baud rate
generator
Clock
PCLKB
PCLKB/4
PCLKB/16
PCLKB/64
SCIn_TEI
SCIn_TXI (interrupt request)
SCIn_RXI (n = 0, 1, 9)
SCIn_ERI
SCIn_AM
Transmission
and reception
control
CTSn_RTSn/
SSn
SIMR1/2/3
SISR
SNFR
SCI0_DCUF
(snooze end request)
External Clock
SCKn
RSR:
Receive Shift Register
RDR:
Receive Data Register
TSR:
Transmit Shift Register
TDR:
Transmit Data Register
SMR/SMR_SMCI:Serial Mode Register
SCR/SCR_SMCI:Serial Control Register
SSR/SSR_SMCI/SSR_FIFO*1:Serial Status Register
SCMR:
Smart Card Mode Register
BRR:
Bit Rate Register
MDDR:
Modulation Duty Register
SEMR:
Serial Extended Mode Register
SPMR:
SPI Mode Register
SNFR:
Noise Filter Setting Register
SIMR1/2/3: I2C Mode Register 1/2/3
SISR:
I2C Status Register
Figure 25.1
Internal
Peripheral Bus
RDRHL:
FRDRH/L*1:
TDRHL:
FTDRH/L*1:
FCR*1:
FDR*1:
LSR*1:
CDR:
DCCR:
SPTR:
Note 1.
Receive 9-bit Data Register
Receive FIFO Data Register
Transmit 9-bit Data Register
Transmit FIFO Data Register
FIFO Control Register
FIFO Data Count Register
Line Status Register
Compare Match Data Register
Data Compare Match Control Register
Serial Port Register
SCI0 only
SCI block diagram
Table 25.2 lists the pin configuration of the SCI for the individual modes.
Table 25.2
SCI I/O pins (1 of 2)
Channel
Pin name
Input/Output
Function
SCI0
SCK0
Input/Output
SCI0 clock input/output
RXD0/SCL0/
MISO0
Input/Output
SCI0 receive data input
SCI0 IIC clock input/output
SCI0 slave transmit data input/output
TXD0/SDA0/
MOSI0
Input/Output
SCI0 transmit data output
SCI0 IIC data input/output
SCI0 master transmit data input/output
SS0/CTS0_RTS0
Input/Output
SCI0 chip select input, active-low
SCI0 transfer start control input/output, active-low
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Table 25.2
25. Serial Communications Interface (SCI)
SCI I/O pins (2 of 2)
Channel
Pin name
Input/Output
Function
SCI1
SCK1
Input/Output
SCI1 clock input/output
RXD1/SCL1/
MISO1
Input/Output
SCI1 receive data input
SCI1 IIC clock input/output
SCI1 slave transmit data input/output
TXD1/SDA1/
MOSI1
Input/Output
SCI1 transmit data output
SCI1 IIC data input/output
SCI1 master transmit data input/output
SS1/CTS1_RTS1
Input/Output
SCI1 chip select input, active-low
SCI1 transfer start control input/output, active-low
SCK9
Input/Output
SCI9 clock input/output
RXD9/SCL9/
MISO9
Input/Output
SCI9 receive data input
SCI9 IIC clock input/output
SCI9 slave transmit data input/output
TXD9/SDA9/
MOSI9
Input/Output
SCI9 transmit data output
SCI9 IIC data input/output
SCI9 master transmit data input/output
SS9/CTS9_RTS9
Input/Output
SCI9 chip select input, active-low
SCI9 transfer start control input/output, active-low
SCI9
25.2
Register Descriptions
25.2.1
Receive Shift Register (RSR)
RSR is a shift register that receives serial data input from the RXDn pin and converts it into parallel data. When one
frame of data is received, it is automatically transferred to the RDR register, RDRHL register, or receive FIFO. The RSR
register cannot be directly accessed by the CPU.
25.2.2
Receive Data Register (RDR)
Address(es): SCI0.RDR 4007 0005h, SCI1.RDR 4007 0025h, SCI9.RDR 4007 0125h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
RDR is an 8-bit register that stores received data. When one frame of serial data is received, the received serial data is
transferred from RSR to RDR, and the RSR register can receive more data. Because RSR and RDR function as a double
buffer, continuous received operations can be performed.
Read the RDR only once after a receive data full interrupt (SCIn_RXI) occurs.
Note:
If the next one frame of data is received before reading the received data from RDR, an overrun error occurs. The
CPU cannot write to the RDR.
25.2.3
Receive 9-bit Data Register (RDRHL)
Address(es): SCI0.RDRHL 4007 0010h, SCI1.RDRHL 4007 0030h, SCI9.RDRHL 4007 0130h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RDRHL is a 16-bit register that stores received data. Use this register when asynchronous mode and 9-bit data length are
selected.
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The lower 8 bits of RDRHL are the shadow register of RDR, for example access to RDRHL affects the RDR register.
Access to the RDRHL register is prohibited if 7-bit or 8-bit data length is selected.
After one frame of data is received, the received data is transferred from the RSR register to these registers, therefore
allowing the RSR register to receive more data.
The RSR and RDRHL registers have a double-buffered construction to enable continuous reception. RDRHL should be
read only when a receive data full interrupt (SCIn_RXI) request is issued. Note that an overrun error occurs when the
next frame of data is received before the received data is read from RDRHL. The CPU cannot write to the RDRHL
register. Bits [15:9] are fixed to 0. These bits are read as 0. The write value should be 0.
25.2.4
Receive FIFO Data Register H, L, HL (FRDRH, FRDRL, FRDRHL)
Receive FIFO Data Register H (FRDRH)
Address(es): SCI0.FRDRH 4007 0010h
Receive FIFO Data Register L (FRDRL)
Address(es): SCI0.FRDRL 4007 0011h
Receive FIFO Data Register HL (FRDRHL)
Address(es): SCI0.FRDRHL 4007 0010h
SCI0.FRDRHL
SCI0.FRDRH
SCI0.FRDRL
b15
b14
b13
b12
b11
b10
b9
—
RDF
ORER
FER
PER
DR
MPB
0
0
0
0
0
0
0
Value after reset:
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
RDAT[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
RDAT[8:0]
Serial Receive Data
Valid only in asynchronous mode (including multi-processor) or
clock synchronous mode, and with FIFO selected.
It can read serial receive data.
R
b9
MPB
Multi-Processor Bit Flag
Valid only in asynchronous mode with SMR.MP = 1 and FIFO
selected.
It can read multi-processor bit associated with serial receive data
(RDAT[8:0]):
0: Data transmission cycles
1: ID transmission cycles.
R
b10
DR
Receive Data Ready Flag
This flag is the same as SSR_FIFO.DR:
0: Receiving is in progress, or no received data remains in
FRDRH and FRDRL after a normal completion of received
data
1: Next receive data has not been received for a period after a
normal completion of received data.
R*1
b11
PER
Parity Error Flag
0: No parity error occurred at the first data of FRDRH and FRDRL R
1: A parity error has occurred at the first data of FRDRH and
FRDRL.
b12
FER
Framing Error Flag
0: No framing error occurred at the first data of FRDRH and
FRDRL
1: A framing error has occurred at the first data of FRDRH and
FRDRL.
R
b13
ORER
Overrun Error Flag
It is same as SSR_FIFO.ORER
0: No overrun error occurred
1: An overrun error has occurred.
R*1
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Bit
Symbol
Bit name
Description
R/W
b14
RDF
Receive FIFO Data Full Flag
It is same as SSR_FIFO.RDF
0: The amount of received data written in FRDRH and FRDRL
falls below the specified receive triggering number.
1: The amount of received data written in FRDRH and FRDRL is
equal to or greater than the specified receive triggering
number.
R*1
b15
—
Reserved
This bit is read as 0.
R
Note 1. If this flag is read, it is the same as a read of the SSR_FIFO register. Write 0 to the SSR_FIFO register to clear
the flag.
FRDRHL is a 16-bit register that consists of FRDRL and FRDRH.
FRDRH and FRDRL constitute a 16-stage FIFO register that stores serial receive data and related status information.
Software can read serial receive data and related status information. This register is valid only in asynchronous mode,
including multi-processor mode or clock synchronous mode.
The SCI completes a reception of one frame of serial data by transferring the received data from the Receive Shift
Register (RSR) into FRDRH and FRDRL for storage. Continuous reception is executed until 16 stages are stored. If data
is read when there is no received data in FRDRH and FRDRL, the value is undefined. When FRDRH and FRDRL are
full of received data, subsequent serial receive data is lost. The CPU can read from FRDRH and FRDRL but cannot write
to them.
Reading 1 from the RDF, ORER, or DR flags of the FRDRH register is the same as reading those bits from the
SSR_FIFO register. When writing 0 to clear the flag in the SSR_FIFO register after reading the FRDRH register, write 0
only in the cleared flag and write 1 otherwise.
When reading both the FRDRH and FRDRL registers, read in the order from FRDRH to FRDRL. The FRDRHL register
can be accessed in 16-bit units.
25.2.5
Transmit Data Register (TDR)
Address(es): SCI0.TDR 4007 0003h, SCI1.TDR 4007 0023h, SCI9.TDR 4007 0123h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
TDR is an 8-bit register that stores transmit data.
When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission.
The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data is
already written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue
transmission.
The CPU can read from or write to TDR at any time. Only write transmit data to TDR once after each instance of the
transmit data empty interrupt (SCIn_TXI).
25.2.6
Transmit 9-Bit Data Register (TDRHL)
Address(es): SCI0.TDRHL 4007 000Eh, SCI1.TDRHL 4007 002Eh, SCI9.TDRHL 4007 012Eh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TDRHL is a 16-bit register that stores transmit data. Use this register when asynchronous mode and 9-bit data length are
selected.
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The lower 8 bits of TDRHL are the shadow register of TDR for example, access to TDRHL affects the TDR register.
Access to the TDRHL register is prohibited if 7-bit or 8-bit data length is selected.
When empty space is detected in the TSR register, the transmit data stored in the TDRHL registers is transferred to TSR
and transmission is started.
The TSR and TDRHL registers have a double-buffered structure to support continuous transmission. When the next data
to be transmitted is stored in TDRHL after one frame of data is transmitted, the transmitting operation continues by
transferring to the TSR register.
The CPU can read and write to the TDRHL register. Bits [15:9] in TDRHL are fixed to 1. These bits are read as 1. The
write value should be 1.
Writing transmit data to the TDRHL register should be performed only once when a transmit data empty interrupt
(SCIn_TXI) request is issued.
25.2.7
Transmit FIFO Data Register H, L, HL (FTDRH, FTDRL, FTDRHL)
Transmit FIFO Data Register H (FTDRH)
Address(es): SCI0.FTDRH 4007 000Eh
Transmit FIFO Data Register L (FTDRL)
Address(es): SCI0.FTDRL 4007 000Fh
Transmit FIFO Data Register HL (FTDRHL)
Address(es): SCI0.FTDRHL 4007 000Eh
SCI0.FTDRHL
SCI0.FTDRH
SCI0.FTDRL
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
MPBT
1
1
1
1
1
1
1
Value after reset:
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
TDAT[8:0]
1
1
1
1
1
Bit
Symbol
Bit name
Description
R/W
b8 to b0
TDAT[8:0]
Serial Transmit Data
Valid only in asynchronous mode including multi-processor or
clock synchronous mode, and with FIFO selected.
It can write serial transmit data.
W
b9
MPBT
Multi-Processor Transfer Bit Flag
Valid only in asynchronous mode and SMR.MP = 1 and FIFO
selected.
Value of the multi-processor bit in the transmission frame:
0: Data transmission cycles
1: ID transmission cycles.
W
b15 to b10
—
Reserved
The write value should be 1.
W
FTDRHL is a 16-bit register that consists of FTDRH and FTDRL.
FTDRH and FTDRL constitute a 16-stage FIFO register that stores data for serial transmission and multi-processor
transfer bit. This register is valid only in asynchronous mode, including multi-processor mode or clock synchronous
mode.
When the SCI detects that the Transmit Shift Register (TSR) is empty, it transmits data written in the FTDRH and
FTDRL into TSR and starts serial transmission. Continuous serial transmission is executed until no transmit data is left
in FTDRH and FTDRL. When FTDR is full of transmit data, no more data can be written. If writing new data is
attempted, the data is ignored. The CPU can write to FTDRH and FTDRL but cannot read them.
When writing to both the FTDRH and FTDRL registers, write in the order from FTDRH to FTDRL.
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25. Serial Communications Interface (SCI)
MPBT bit (Multi-Processor Transfer Bit Flag)
Selects the multi processor bit of the transmit frame.
When FCR.FM = 1, SSR.MPBT is not valid.
25.2.8
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers
transmit data from TDR, TDRHL, or transmit FIFO to TSR, then sends the data to the TXDn pin. The CPU cannot
directly access the TSR.
25.2.9
Serial Mode Register (SMR) for Non-Smart Card Interface mode
(SCMR.SMIF = 0)
Address(es): SCI0.SMR 4007 0000h, SCI1.SMR 4007 0020h, SCI9.SMR 4007 0120h
b7
b6
b5
b4
b3
b2
CM
CHR
PE
PM
STOP
MP
0
0
0
0
0
0
Value after reset:
b1
b0
CKS[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKS[1:0]
Clock Select
b1 b0
R/W*4
b2
MP
Multi-Processor Mode
Valid only in asynchronous mode:
0: Multi-processor communications function is disabled
1: Multi-processor communications function is enabled.
R/W*4
b3
STOP
Stop Bit Length
Valid only in asynchronous mode:
0: 1 stop bit
1: 2 stop bits.
R/W*4
b4
PM
Parity Mode
Valid only when the PE bit is 1:
0: Selects even parity
1: Selects odd parity.
R/W*4
b5
PE
Parity Enable
Valid only in asynchronous mode:
When transmitting:
0: Parity bit addition is not performed
1: The parity bit is added.
When receiving:
0: Parity bit checking is not performed
1: The parity bit is checked.
R/W*4
b6
CHR
Character Length
Valid only in asynchronous mode*2.
Selects in combination with the CHR1 bit in SCMR.
R/W*4
0
0
1
1
0: PCLKB clock (n = 0)*1
1: PCLKB/4 clock (n = 1)*1
0: PCLKB/16 clock (n = 2)*1
1: PCLKB/64 clock (n = 3)*1.
CHR1CHR
0 0: Transmit/receive in 9-bit data length
0 1: Transmit/receive in 9-bit data length
1 0: Transmit/receive in 8-bit data length (initial value)
1 1: Transmit/receive in 7-bit data length*3.
b7
Note 1.
Note 2.
Note 3.
Note 4.
CM
Communication Mode
0: Asynchronous mode or simple IIC mode
1: Clock synchronous mode or simple SPI mode.
R/W*4
n is the decimal notation of the value of n in BRR, see section 25.2.17, Bit Rate Register (BRR).
In other than asynchronous mode, this bit setting is invalid and a fixed data length of 8 bits is used.
LSB-first is fixed and the MSB bit [7] in TDR is not transmitted in transmission.
Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
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The SMR register sets the communication format and clock source for the on-chip baud rate generator.
CKS[1:0] bits (Clock Select)
The CKS[1:0] bits select the clock source for the on-chip baud rate generator.
For the relationship between the settings of these bits and the baud rate, see section 25.2.17, Bit Rate Register (BRR).
MP bit (Multi-Processor Mode)
The MP bit disables or enables the multi-processor communications function. The settings of the PE bit and PM bit are
invalid in multi-processor mode.
STOP bit (Stop Bit Length)
The STOP bit selects the stop bit length in transmission.
In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the
start bit of the next transmit frame.
PM bit (Parity Mode)
The PM bit selects the parity mode (even or odd) for transmission and reception.
The setting of the PM bit is invalid in multi-processor mode.
PE bit (Parity Enable)
When the PE bit is set to 1, the parity bit is added to transmit data, and the parity bit is checked in reception.
Irrespective of the setting of the PE bit, the parity bit is not added or checked in multi-processor format.
CHR bit (Character Length)
The CHR bit selects the data length for transmission and reception in combination with the CHR1 bit in SCMR.
In modes other than asynchronous mode, a fixed data length of 8 bits is used.
CM bit (Communication Mode)
The CM bit selects the communication mode:
Asynchronous mode or simple IIC mode
Clock synchronous mode or simple SPI mode.
25.2.10
Serial Mode Register for Smart Card Interface Mode (SMR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SMR_SMCI 4007 0000h, SCI1.SMR_SMCI 4007 0020h, SCI9.SMR_SMCI 4007 0120h
Value after reset:
b7
b6
b5
b4
GM
BLK
PE
PM
0
0
0
0
b3
b2
b1
b0
BCP[1:0]
CKS[1:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKS[1:0]
Clock Select
b1 b0
R/W*2
b3, b2
BCP[1:0]
Base Clock Pulse
Selects the number of base clock cycles in combination with
the BCP2 bit in SCMR.
Table 25.3 lists the combinations of the SCMR.BCP2 bit and
SMR.BCP[1:0] bits.
R/W*2
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0 0: PCLKB clock (n = 0)*1
0 1: PCLKB/4 clock (n = 1)*1
1 0: PCLKB/16 clock (n = 2)*1
1 1: PCLKB/64 clock (n = 3)*1.
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25. Serial Communications Interface (SCI)
Bit
Symbol
Bit name
Description
R/W
b4
PM
Parity Mode
Valid only when the PE bit is 1:
0: Selects even parity
1: Selects odd parity.
R/W*2
b5
PE
Parity Enable
When this bit is set to 1, a parity bit is added to transmit data,
and the parity of received data is checked. Set this bit to 1 in
smart card interface mode.
R/W*2
b6
BLK
Block Transfer Mode
0: Non-block transfer mode operation
1: Block transfer mode operation.
R/W*2
b7
GM
GSM Mode
0: Normal mode operation
1: Non-GSM mode operation.
R/W*2
Note 1. n is the decimal notation of the value of n in BRR, see section 25.2.17, Bit Rate Register (BRR).
Note 2. Writable only when TE in SCR_SMCI = 0 and RE in SCR_SMCI = 0 (both serial transmission and reception are
disabled).
The SMR_SMCI register sets the communication format and clock source for the on-chip baud rate generator.
CKS[1:0] bits (Clock Select)
The CKS[1:0] bits select the clock source for the on-chip baud rate generator.
For the relationship between the settings of these bits and the baud rate, see section 25.2.17, Bit Rate Register (BRR).
BCP[1:0] bits (Base Clock Pulse)
The BCP[1:0] bits select the number of base clock cycles in a 1-bit data transfer time in smart card interface mode.
Set these bits in combination with the BCP2 bit in SCMR.
For details, see section 25.6.4, Receive Data Sampling Timing and Reception Margin.
Table 25.3
Combinations of SCMR.BCP2 bit and SMR_SMCI.BCP[1:0] bits
SCMR.BCP2 bit
SMR_SMCI.BCP[1:0] bits
Number of base clock cycles for 1-bit transfer period
0
0
0
93 clock cycles (S = 93)*1
0
0
1
128 clock cycles (S = 128)*1
0
1
0
186 clock cycles (S = 186)*1
0
1
1
512 clock cycles (S = 512)*1
1
0
0
32 clock cycles (S = 32)*1 (Initial Value)
1
0
1
64 clock cycles (S = 64)*1
1
1
0
372 clock cycles (S = 372)*1
1
1
1
256 clock cycles (S = 256)*1
Note 1. S is the value of S in BRR (see section 25.2.17, Bit Rate Register (BRR)).
PM bit (Parity Mode)
The PM bit selects the parity mode for transmission and reception (even or odd).
For details on the usage of this bit in smart card interface mode, see section 25.6.2, Data Format (Except in Block
Transfer Mode).
PE bit (Parity Enable)
Set the PE bit to 1.
The parity bit is added to transmit data before transmission, and the parity bit is checked in reception.
BLK bit (Block Transfer Mode)
Setting this bit to 1 enables block transfer mode operation.
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For details, see section 25.6.3, Block Transfer Mode.
GM bit (GSM Mode)
Setting this bit to 1 enables GSM mode operation.
In GSM mode, the SSR_SMCI.TEND flag set timing is moved forward to 11.0 ETU (elementary time unit = 1-bit
transfer time) from the start and the clock output control function is appended. For details, see section 25.6.6, Serial Data
Transmission (Except in Block Transfer mode) and section 25.6.8, Clock Output Control.
25.2.11
Serial Control Register (SCR) for Non-Smart Card Interface Mode
(SCMR.SMIF = 0)
Address(es): SCI0.SCR 4007 0002h, SCI1.SCR 4007 0022h, SCI9.SCR 4007 0122h
b7
b6
b5
b4
b3
b2
TIE
RIE
TE
RE
MPIE
TEIE
0
0
0
0
0
0
Value after reset:
b1
b0
CKE[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKE[1:0]
Clock Enable
Asynchronous mode:
R/W*1
b1 b0
0 0: On-chip baud rate generator.
The SCKn pin is available for use as an I/O port in
accord with the I/O port settings.
0 1: On-chip baud rate generator.
The clock with the same frequency as the bit rate is
output from the SCKn pin.
1 x: External clock.
The clock with a frequency 16 times the bit rate should be
input from the SCKn pin (when SEMR.ABCS bit is 0). Input
a clock signal with a frequency eight times the bit rate
when the SEMR.ABCS bit is 1.
Clock synchronous mode:
b1 b0
0 x: Internal clock.
The SCKn pin functions as the clock output pin.
1 x: External clock.
The SCKn pin functions as the clock input pin.
b2
TEIE
Transmit End Interrupt Enable
0: An SCIn_TEI interrupt request is disabled
1: An SCIn_TEI interrupt request is enabled.
R/W
b3
MPIE
Multi-Processor Interrupt Enable
Valid in asynchronous mode when SMR.MP = 1:
0: Non multi-processor reception
1: When data with the multi-processor bit set to 0 is
received, the data is not read, and setting the status flags
RDRF, ORER, and FER in SSR to 1 is disabled. When
data with the multiprocessor bit set to 1 is received, the
MPIE bit is automatically cleared to 0, and non multiprocessor reception is resumed.
R/W*3
b4
RE
Receive Enable
0: Serial reception is disabled
1: Serial reception is enabled.
R/W*2
b5
TE
Transmit Enable
0: Serial transmission is disabled
1: Serial transmission is enabled.
R/W*2
b6
RIE
Receive Interrupt Enable
0: SCIn_RXI and SCIn_ERI interrupt requests are disabled
1: SCIn_RXI and SCIn_ERI interrupt requests are enabled.
R/W
b7
TIE
Transmit Interrupt Enable
0: An SCIn_TXI interrupt request is disabled
1: An SCIn_TXI interrupt request is enabled.
R/W
x: Don’t care
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Note 1. Writable only when TE = 0 and RE = 0.
Note 2. 1 can only be written when TE = 0 and RE = 0, while the SMR.CM bit is 1. After setting TE or RE to 1, only 0 can
be written in TE and RE. While the SMR.CM bit is 0 and the SIMR1.IICM bit is 0, writing is enabled under any
condition.
Note 3. When writing a new value to a bit other than the MPIE bit of this register during multi-processor mode (SMR.MP
bit = 1), write 0 to MPIE bit using the store instruction to avoid accidentally setting the MPIE bit to 1 by read
modify write when using a bit manipulation instruction.
SCR sets control and the clock source selection for transmission and reception.
CKE[1:0] bits (Clock Enable)
The CKE[1:0] bits select the clock source and SCKn pin function.
TEIE bit (Transmit End Interrupt Enable)
The TEIE bit enables or disables an SCIn_TEI interrupt request.
An SCIn_TEI interrupt request is disabled by setting the TEIE bit to 0.
In simple IIC mode, the SCIn_TEI is allocated to the interrupt on completion of issuing a start, restart, or stop condition
(STIn). In this case, the TEIE bit can be used to enable or disable the STI.
MPIE bit (Multi-Processor Interrupt Enable)
When the MPIE bit is set to 1 and data with the multi-processor bit set to 0 is received, the data is not read and setting the
status flags RDRF, ORER, and FER in SSR/SSR_FIFO to 1 is disabled. When data with the multi-processor bit set to 1
is received, the MPIE is automatically cleared to 0, and non multi-processor reception resumes. For details, see section
25.4, Multi-Processor Communication Function.
When the received data includes the MPB bit in the SSR is set to 0, the received data is not transferred from the RSR to
the RDR, a receive error is not detected, and setting the flags ORER and FER to 1 is disabled.
When the received data includes the MPB bit is set to 1, the MPIE bit is automatically cleared to 0, the SCIn_RXI and
SCIn_ERI interrupt requests are enabled (if the RIE bit in SCR is set to 1), and the setting of the ORER and FER flags to
1 is enabled.
MPIE should be set to 0 if the multi-processor communications function is not used.
RE bit (Receive Enable)
The RE bit enables or disables serial reception.
When this bit is set to 1, serial reception starts by detecting the start bit in asynchronous mode or the synchronous clock
input in clock synchronous mode.
Note:
SMR should be set prior to setting the RE bit to 1 to designate the reception format.
When reception is halted by setting the RE bit to 0, the RDRF, ORER, FER, and PER flags in SSR are not affected and
the previous value is retained when non-FIFO is selected. When reception is halted by setting the RE bit to 0, the RDF,
ORER, FER, PER, and DR flags in SSR_FIFO are not affected and the previous value is retained when FIFO selected.
TE bit (Transmit Enable)
The TE bit enables or disables serial transmission. When this bit is set to 1, serial transmission starts by writing transmit
data to TDR.
Note:
SMR should be set prior to setting the TE bit to 1 to designate the transmission format.
RIE bit (Receive Interrupt Enable)
The RIE bit enables or disables SCIn_RXI and SCIn_ERI interrupt requests.
An SCIn_RXI or SCIn_ERI interrupt request is disabled by setting the RIE bit to 0.
An SCIn_ERI interrupt request can be canceled by reading 1 from the ORER, FER, or PER flag in SSR/SSR_FIFO then
setting the flag to 0, or setting the RIE bit to 0.
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25. Serial Communications Interface (SCI)
TIE bit (Transmit Interrupt Enable)
The TIE bit enables or disables SCIn_TXI interrupt request.
An SCIn_TXI interrupt request is disabled by setting the TIE bit to 0. This bit should be set to 1 while the TE bit is 1. Set
1 to TE and TIE at the same time before transfer starts, an SCIn_TXI interrupt is then generated.
25.2.12
Serial Control Register for Smart Card Interface Mode (SCR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SCR_SMCI 4007 0002h, SCI1.SCR_SMCI 4007 0022h, SCI9.SCR_SMCI 4007 0122h
b7
b6
b5
b4
b3
b2
TIE
RIE
TE
RE
MPIE
TEIE
0
0
0
0
0
0
Value after reset:
b1
b0
CKE[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
CKE[1:0]
Clock Enable
When GM in SMR_SMCI = 0:
R/W*1
b1 b0
0 0: Output disabled.
The SCKn pin is available for use as an I/O port
according to the I/O port settings.
0 1: Clock output
1 x: Setting prohibited.
When GM in SMR_SMCI = 1:
b1 b0
0 0: Output fixed low
x 1: Clock output
1 0: Output fixed high.
b2
TEIE
Transmit End Interrupt Enable
This bit should be 0 in smart card interface mode.
R/W
b3
MPIE
Multi-Processor Interrupt Enable
This bit should be 0 in smart card interface mode.
R/W
b4
RE
Receive Enable
0: Serial reception is disabled
1: Serial reception is enabled.
R/W*2
b5
TE
Transmit Enable
0: Serial transmission is disabled
1: Serial transmission is enabled.
R/W*2
b6
RIE
Receive Interrupt Enable
0: SCIn_RXI and SCIn_ERI interrupt requests are
disabled
1: SCIn_RXI and SCIn_ERI interrupt requests are
enabled.
R/W
b7
TIE
Transmit Interrupt Enable
0: An SCIn_TXI interrupt request is disabled
1: An SCIn_TXI interrupt request is enabled.
R/W
x: Don’t care
Note 1. Writable only when TE = 0 and RE = 0.
Note 2. 1 can be written only when TE = 0 and RE = 0. After setting TE or RE to 1, only 0 can be written in TE and RE.
SCR_SMCI sets transmission control, interrupt control and reception and clock source selection for transmission and
reception.
For details on interrupt requests, see section 25.10, Interrupt Sources.
CKE[1:0] bits (Clock Enable)
The CKE[1:0] bits control the clock output from the SCKn pin.
In GSM mode, clock output can be dynamically switched. For details, see section 25.6.8, Clock Output Control.
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25. Serial Communications Interface (SCI)
TEIE bit (Transmit End Interrupt Enable)
This bit should be 0 in smart card interface mode.
RE bit (Receive Enable)
The RE bit enables or disables serial reception.
When this bit is set to 1, serial reception starts by detecting the start bit.
Note:
SMR_SMCI should be set prior to setting the RE bit to 1 to designate the reception format.
If reception is halted by setting the RE bit to 0, the ORER, FER, and PER flags in SSR_SMCI are not affected and the
previous value is saved.
TE bit (Transmit Enable)
The TE bit enables or disables serial transmission.
When this bit is set to 1, serial transmission starts by writing transmit data to TDR.
Note:
SMR_SMCI should be set prior to setting the TE bit to 1 to designate the transmission format.
RIE bit (Receive Interrupt Enable)
The RIE bit enables or disables SCIn_RXI and SCIn_ERI interrupt requests.
An SCIn_RXI and SCIn_ERI interrupt request is disabled by setting the RIE bit to 0.
An SCIn_ERI interrupt request can be canceled by reading 1 from the ORER, FER, or PER flag in SSR_SMCI and then
setting the flag to 0, or setting the RIE bit to 0.
TIE bit (Transmit Interrupt Enable)
The TIE bit enables or disables SCIn_TXI interrupt request.
An SCIn_TXI interrupt request is disabled by setting the TIE bit to 0. This bit should be set to 1 while TE bit is 1. Set 1
to TE and TIE at same time before transfer starts, an SCIn_TXI interrupt is then generated.
25.2.13
Serial Status Register (SSR) for Non-Smart Card Interface and Non-FIFO Mode
(SCMR.SMIF = 0 and FCR.FM = 0)
Address(es): SCI0.SSR 4007 0004h, SCI1.SSR 4007 0024h, SCI9.SSR 4007 0124h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MPBT
Multi-Processor Bit Transfer
Sets the multi-processor bit for the transmission frame:
0: Data transmission cycles
1: ID transmission cycles.
R/W
b1
MPB
Multi-Processor
Value of the multi-processor bit in the reception frame:
0: Data transmission cycles
1: ID transmission cycles.
R
b2
TEND
Transmit End Flag
0: A character is transmitted
1: Character transfer is complete.
R
b3
PER
Parity Error Flag
0: No parity error occurred
1: A parity error occurred.
R/(W)*1
b4
FER
Framing Error Flag
0: No framing error occurred
1: A framing error occurred.
R/(W)*1
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Bit
Symbol
Bit name
Description
R/W
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: An overrun error occurred.
R/(W)*1
b6
RDRF
Receive Data Full Flag
0: No received data is in RDR register
1: Received data is in RDR register.
R/(W)*1
b7
TDRE
Transmit Data Empty Flag
0: Transmit data is in TDR register
1: No transmit data is in TDR register.
R/(W)*1
Note 1. Only 0 can be written to this bit to clear the flag after reading 1.
The SSR register provides the SCI status flag and transmission/reception multi-processor bits.
MPBT (Multi-Processor Bit Transfer)
The MPBT bit selects the multi-processor bit of the transmit frame.
MPB bit (Multi-Processor)
The MPB bit holds the value of the multi-processor bit in the reception frame. This bit does not change when the
SCR.RE bit is 0.
TEND flag (Transmit End Flag)
The TEND flag indicates completion of transmission.
[Setting conditions]
When the SCR.TE bit is set to 0 (serial transmission is disabled) and the FCR.FM bit is set to 0 (non-FIFO selected).
When the SCR.TE bit is set to 1, the TEND flag is not affected and retains the value 1.
When the TDR register is not updated at the time of transmission of the tail-end bit of a character being transmitted.
[Clearing conditions]
When transmit data is written to the TDR register while the SCR.TE bit is 1
When 0 is written to TDRE after reading TDRE = 1 while the SCR.TE bit is 1.
PER flag (Parity Error Flag)
The PER flag indicates that a parity error has occurred during reception in asynchronous mode and the reception ends
abnormally.
[Setting condition]
When a parity error is detected during reception in asynchronous mode and the state of address match function is
invalid (DCCR.DCME = 0).
Although received data when the parity error occurs is transferred to RDR, no SCIn_RXI interrupt request occurs.
When the PER flag is set to 1, the subsequent received data is not transferred to RDR.
[Clearing condition]
When 0 is written to PER after reading PER = 1 (after writing 0 to it, read the PER bit to verify that its value is 0).
When the RE bit in SCR is set to 0 (serial reception is disabled), the PER flag is not affected and retains its previous
value.
FER flag (Framing Error Flag)
The FER flag indicates that a framing error occurs during reception in asynchronous mode and the reception ends
abnormally.
[Setting condition]
When 0 is sampled as the stop bit during reception in asynchronous mode and the state of address match function is
invalid (DCCR.DCME = 0).
In 2-stop-bit mode, only the first stop bit is checked if it is 1 but the second stop bit is not checked. Although
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25. Serial Communications Interface (SCI)
received data when the framing error occurs is transferred to RDR, no SCIn_RXI interrupt request occurs. In
addition, when the FER flag is set to 1, the subsequent received data is not transferred to RDR.
[Clearing condition]
When 0 is written to FER after reading FER = 1 (after writing 0 to it, read the FER bit to verify that its value is 0).
When the RE bit in SCR is set to 0, the FER flag is not affected and retains its previous value.
ORER flag (Overrun Error Flag)
The ORER flag indicates that an overrun error occurs during reception and the reception ends abnormally.
[Setting condition]
When the next data is received before receive data is read from RDR that does not have a parity error and a framing
error.
In RDR, receive data prior to an overrun error occurrence is retained, but data received after the overrun error
occurrence is lost. When the ORER flag is set to 1, reception data is not forwarded to RDR register. In clock
synchronous mode, serial transmission and reception are stopped.
[Clearing condition]
When 0 is written to ORER after reading ORER = 1 (after writing 0 to it, read the ORER bit to verify that its value
is 0).
When the RE bit in SCR is set to 0, the ORER flag is not affected and retains its previous value.
RDRF flag (Receive Data Full Flag)
The RDRF flag indicates the presence of received data in the RDR register.
[setting condition]
When the reception ends normally, and receive data is forwarded from the RSR register to the RDR register.
[Clearing conditions]
When it is set to 0 after 1 is read
When the data is read from the RDR register.
Note:
Do not clear the RDRF flag by accessing the RDRF bit in SSR register unless communication is aborted.
TDRE flag (Transmit Data Empty Flag)
The TDRE flag indicates the presence of transmit data in the TDR register.
[setting conditions]
When the SCR.TE bit is 0
When data is transmitted from the TDR register to the TSR register.
[Clearing conditions]
When it is set to 0 after 1 is read
When the SCR.TE bit is 1, data is forwarded to the TDR register.
Note:
Do not clear the TDRE flag by accessing the TDRE bit in SSR register unless communication is aborted.
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25. Serial Communications Interface (SCI)
Serial Status Register for Non-Smart Card Interface and FIFO Mode
(SSR_FIFO) (SCMR.SMIF = 0 and FCR.FM = 1)
Address(es): SCI0.SSR_FIFO 4007 0004h
b7
b6
b5
b4
b3
b2
b1
b0
TDFE
RDF
ORER
FER
PER
TEND
—
DR
1
0
0
0
0
0
x
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
DR
Receive Data Ready Flag
0: Receiving is in progress, or no received data remains
in FRDRHL after normal receive completes (receive
FIFO is empty).
1: Next receive data is not received for a period after
normal receiving is complete, and when the amount of
data stored in the FIFO is equal to or less than the
receive triggering number.
R/(W)*1
b1
—
Reserved
The read value is undefined. The write value should be 1. R/W
b2
TEND
Transmit End Flag
0: A character is transmitted.
1: Character transfer is complete.
R/(W)*1
b3
PER
Parity Error Flag
0: No parity error occurred
1: A parity error has occurred.
R/(W)*1
b4
FER
Framing Error Flag
0: No framing error occurred
1: A framing error has occurred.
R/(W)*1
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: An overrun error has occurred.
R/(W)*1
b6
RDF
Receive FIFO Data Full Flag
0: The amount of receive data written in FRDRHL falls
below the specified receive triggering number
1: The amount of received data written in FRDRHL is
equal to or greater than the specified receive triggering
number.
R/(W)*1
b7
TDFE
Transmit FIFO Data Empty Flag
0: The amount of transmit data written in FTDRHL
exceeds the specified transmit triggering number
1: The amount of transmit data written in FTDRHL is
equal to or less than the specified transmit triggering
number.
R/(W)*1
Note 1. Only 0 can be written to this bit to clear the flag after reading 1.
The SSR_FIFO register provides SCI with FIFO mode status flags.
DR flag (Receive Data Ready Flag)
The DR flag indicates that the amount of data stored in the receive FIFO Data Register (FRDRHL) falls below the
specified receive triggering number, and that no subsequent data is received after 15 ETUs (Element Time Unit) from the
last stop bit in asynchronous mode. This flag is valid only in asynchronous mode, including multi-processor mode, and
when FIFO is selected.
In clock synchronous mode, this flag is not set to 1.
[Setting condition]
DR is set to 1 when FRDRHL contains less data than the specified receive triggering number, and no subsequent
data is received after 15 ETUs*1 from the last stop bit, and the SSR_FIFO.FER and SSR_FIFO.PER flags are 0.
[Clearing conditions]
DR is cleared to 0 when 1 is read from DR and 0 is written after all received data are read.
When the FCR.FM bit is switched from 0 to 1.
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25. Serial Communications Interface (SCI)
Note 1. This is equivalent to one and a half (1.5) frames in the 8-bit format with one stop bit (ETU).
Only when FIFO is selected in asynchronous mode including multi-processor mode, DR flag becomes 1 but not 1
in other operation modes.
TEND flag (Transmit End Flag)
The TEND flag indicates that FTDRHL does not contain valid data when transmitting the last bit of a serial character,
therefore transmission is halted.
[Setting condition]
TEND is set to 1 when FTDRHL does not contain transmit data when the last bit of a 1-byte serial character is
transmitted.
[Clearing conditions]
When transmit data is written in FTDRHL while the SCR.TE bit is 1
When 0 is written in TEND after 1 is read from TEND while the SCR.TE bit is 1
When the FCR.FM bit is switched from 0 to 1.
PER flag (Parity Error Flag)
The PER flag indicates whether there is a parity error in the data read from the FRDRHL register in asynchronous mode
when the address match function is disabled (DCCR.DCME = 0).
[Setting condition]
PER is set to 1 when data is received and a parity error is detected in the state of address match function that is
disabled (DCCR.DCME = 0).
[Clearing condition]
When 0 is written to PER after reading PER = 1.
The reception operation is continuous when receive data is stored to the FRDRHL register even when a parity error
occurs during reception.
When the SCR.RE bit is cleared, the PER flag is not affected and the previous state is kept.
FER flag (Framing Error Flag)
The FER flag indicates whether there is a framing error in the data read from the receive FIFO Data Register (FRDRHL)
in asynchronous mode when the address match function is disabled (DCCR.DCME = 0).
[Setting condition]
FER is set to 1 when 0 is sampled as the stop bit during reception in the state of the address match function is
disabled (DCCR.DCME = 0).
[Clearing condition]
When 0 is written to FER after reading FER = 1.
The reception operation is continuous when receive data is stored to the FRDRHL register even when a framing error
occurs during reception.
When the SCR.RE bit is cleared, the FER flag is not affected and the previous state is kept.
ORER flag (Overrun Error Flag)
The ORER flag indicates that receive operation abnormally stops due to occurrence of an overrun error.
[Setting condition]
ORER is set to 1 when the next serial reception completes while the receive FIFO is full of 16-byte received data.
[Clearing condition]
ORER is set to 0 when 0 is written after 1 is read from ORER.
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25. Serial Communications Interface (SCI)
Clearing the SCR.RE bit to 0 does not affect the ORER flag, which retains its previous state.
RDF flag (Receive FIFO Data Full Flag)
The RDF flag indicates that received data is transferred to the receive FIFO data register (FRDRHL), and the amount of
data in FRDRHL equals or exceeds the specified receive triggering number. However, when RTRG is set to 0, the RDF
flag is not set even when the amount of data in the receive FIFO is equal to 0.
[Setting condition]
RDF is set to 1 when the amount of receive data is equal to or greater than the specified receive triggering number
that is stored in FRDRHL*1 and the FIFO is not empty.
[Clearing conditions]
RDF is set to 0 after 1 is read from RDF and 0 is written
RDF is set to 0 when FRDRHL is read by the DTC but only when the block transfer is the last transmission
When the setting condition and clearing condition occur at the same time, the RDF flag is 0. Thereafter, when the
amount of data stored in the FRDRHL register is the same or greater than the RTRG value, RDF is set to 1 after 1
PCLKB.
Note:
Do not clear the RDF flags by accessing RDF bit in the SSR register before reading receive data unless
communication is aborted.
Note 1. Because the FRDRHL is a 16-stage FIFO register, the maximum amount of data that can be read when RDF is 1
is equivalent to the specified receive triggering number. If an attempt is made to read after all the data in
FRDRHL is read, the data is undefined.
TDFE flag (Transmit FIFO Data Empty Flag)
The TDFE flag indicates that data is transferred from the Transmit FIFO Data Register (FTDRHL) into the Transmit
Shift Register (TSR), the amount of data in FTDRHL has fallen below the specified transmit triggering number, and
writing of transmit data to FTDRHL is enabled.
[Setting conditions]
TDFE is set to 1 when the TE bit in SCR is 0
TDFE is set to 1 when the amount of transmit data written in FTDRHL is equal to or less than the specified transmit
triggering number*1.
[Clearing conditions]
TDFE is cleared to 0 when writing to FTDRHL is executed on the last transmission while the DTC is activated.
TDFE is cleared to 0 when 0 is written in the TDFE flag after reading TDFE = 1.
The setting conditions is given priority at TE = 0. When the setting condition and the clearing condition occur at the
same time, the TDFE flag is 0. After that, when the amount of data stored in the FTDRHL register is the same as or
greater than the TTRG value, TDFE is set to 1 after 1 PCLKB.
Note:
Do not clear the TDFE flags by accessing TDFE bit in the SSR register before writing transmit data unless
communication is aborted.
Note 1. Because the FTDRHL register is a 16-stage FIFO register, the maximum amount of data that can be written
when the TDFE flag is set to 1 is indicated in “16 - FDR.T[4:0]”. If more data is written, data is discarded.
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25. Serial Communications Interface (SCI)
Serial Status Register for Smart Card Interface Mode (SSR_SMCI)
(SCMR.SMIF = 1)
Address(es): SCI0.SSR_SMCI 4007 0004h, SCI1.SSR_SMCI 4007 0024h, SCI9.SSR_SMCI 4007 0124h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
Bit
Symbol
Bit name
Description
R/W
b0
MPBT
Multi-Processor Bit Transfer
This bit should be 0 in smart card interface mode
R/W
b1
MPB
Multi-Processor
This bit should be 0 in smart card interface mode
R
b2
TEND
Transmit End Flag
0: A character is being transmitted
1: Character transfer is completed.
R
b3
PER
Parity Error Flag
0: No parity error occurred
1: A parity error occurred.
R/(W)*
b4
ERS
Error Signal Status Flag
0: Low error signal not responded
1: Low error signal responded.
R/(W)*1
b5
ORER
Overrun Error Flag
0: No overrun error occurred
1: An overrun error occurred.
R/(W)*1
b6
RDRF
Receive Data Full Flag
0: No received data in RDR register
1: Received data in RDR register.
R/(W)*1
b7
TDRE
Transmit Data Empty Flag
0: Transmit data in TDR register
1: No transmit data in TDR register.
R/(W)*1
Note 1. Only 0 can be written to this bit to clear the flag after reading 1.
The SSR_SMCI register provides SCI with smart card interface mode status flags.
TEND flag (Transmit End Flag)
With no error signal from the receiving side, this flag is set to 1 when additional transfer data is ready to be transferred to
the TDR register.
[Setting conditions]
When the SCR_SMCI.TE bit = 0 (serial transmission is disabled).
When the SCR_SMCI.TE bit changes from 0 to 1, the TEND flag is not affected and retains the value 1.
When a specified period elapses after the latest transmission of 1 byte, the ERS flag is 0, and the TDR register is not
updated.
The set timing is determined by the following register settings:
When SMR_SMCI.GM = 0 and SMR_SMCI.BLK = 0, 12.5 ETU after the start of transmission
When SMR_SMCI.GM = 0 and SMR_SMCI.BLK = 1, 11.5 ETU after the start of transmission
When SMR_SMCI.GM = 1 and SMR_SMCI.BLK = 0, 11.0 ETU after the start of transmission
When SMR_SMCI.GM = 1 and SMR_SMCI.BLK = 1, 11.0 ETU after the start of transmission.
[Clearing conditions]
When transmit data is written to the TDR register while the SCR_SMCI.TE bit is 1
When 0 is written to TDRE after reading TDRE = 1 while the SCR_SMCI.TE bit is 1.
PER flag (Parity Error Flag)
The PER flag indicates that a parity error occurred during reception in asynchronous mode and the reception ended
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25. Serial Communications Interface (SCI)
abnormally.
[Setting condition]
When a parity error is detected during reception.
Although receive data is transferred to RDR when the parity error occurs, no SCIn_RXI interrupt request occurs.
When the PER flag is set to 1, the subsequent receive data is not transferred to RDR.
[Clearing condition]
When 0 is written to PER after reading PER = 1. After writing 0 to PER, read the flag to verify that its value is 0.
When the RE bit in SCR_SMCI is set to 0 (serial reception is disabled), the PER flag is not affected and kept its previous
value.
ERS flag (Error Signal Status Flag)
[Setting condition]
When a low error signal is sampled.
[Clearing condition]
When 0 is written to ERS after reading ERS = 1.
ORER flag (Overrun Error Flag)
The ORER flag indicates that an overrun error occurred during reception and the reception ends abnormally.
[Setting condition]
When the next data is received before received data is read from RDR that does not have a parity error. In RDR, the
data received before an overrun error occurred is saved, but data received after the error is lost. When the ORER
flag is set to 1, received data is not forwarded to the RDR register.
[Clearing condition]
When 0 is written to ORER after reading ORER = 1. After writing 0 to the ORER flag, read it to verify that its value
is 0.
When the RE bit in SCR_SMCI is set to 0, the ORER flag is not affected and keeps its previous value.
RDRF flag (Receive Data Full Flag)
The RDRF flag indicates the presence of receive data in the RDR register.
[Setting condition]
When the reception ends normally, and receive data is forwarded from the RSR register to the RDR register.
[Clearing conditions]
When it is set to 0 after 1 is read
When data is read from the RDR register.
Note:
Do not clear the RDRF flags by accessing RDRF bit in the SSR register unless communication is aborted.
TDRE flag (Transmit Data Empty Flag)
The TDRE flag indicates the presence of transmit data in the TDR register.
[Setting conditions]
When the SCR_SMCI.TE bit is 0
When data is transmitted from the TDR register to the TSR register.
[Clearing conditions]
When it is set to 0 after 1 is read
When the SCR_SMCI.TE bit is 1 and it forwards data to the TDR register.
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Feb 5, 2018
Page 540 of 1104
S124 User’s Manual
Note:
25. Serial Communications Interface (SCI)
Do not clear the TDRE flags by accessing TDRE bit in the SSR register unless communication is aborted.
25.2.16
Smart Card Mode Register (SCMR)
Address(es): SCI0.SCMR 4007 0006h, SCI1.SCMR 4007 0026h, SCI9.SCMR 4007 0126h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
BCP2
—
—
CHR1
SDIR
SINV
—
SMIF
1
1
1
1
0
0
1
0
Bit
Symbol
Bit name
Description
R/W
b0
SMIF
Smart Card Interface Mode Select
0: Non-smart card interface mode
(asynchronous mode, clock synchronous mode, simple
SPI mode, or simple IIC mode)
1: Smart card interface mode.
R/W*1
b1
—
Reserved
This bit is read as 1. The write value should be 1.
R/W
b2
SINV
Transmitted/Received Data Invert
0: TDR contents are transmitted as they are. Receive data is
stored as received in the RDR.
1: TDR contents are inverted before being transmitted.
Received data is stored in inverted form in the RDR.
This bit can be used in the following modes:
Smart card interface mode
Asynchronous mode (multi-processor mode)
Clock synchronous mode
Simple SPI mode.
Set this bit to 0 for operation in simple IIC mode.
R/W*1
b3
SDIR
Transmitted/Received Data
Transfer Direction*2
0: Transfer with LSB first
1: Transfer with MSB first.
This bit can be used in the following modes:
Smart card interface mode
Asynchronous mode (multi-processor mode)
Clock synchronous mode
Simple SPI mode.
Set this bit to 1 for operation in simple IIC mode.
R/W*1
b4
CHR1
Character Length 1
Only valid in asynchronous mode*2.
Selects in combination with the CHR bit in SMR.
R/W*1
CHR1 CHR
0
0
1
1
0: Transmit/receive in 9-bit data length
1: Transmit/receive in 9-bit data length
0: Transmit/receive in 8-bit data length (initial value)
1: Transmit/receive in 7-bit data length*3.
b6, b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
b7
BCP2
Base Clock Pulse 2
Selects the number of base clock cycles in combination with
the SMR_SMCI.BCP[1:0] bits.
Table 25.4 lists the combinations of the SCMR.BCP2 bit and
SMR_SMCI.BCP[1:0] bits.
R/W*1
Note 1. Writable only when TE in SCR/SCR_SMCI = 0 and RE in SCR/SCR_SMCI = 0 (both serial transmission and
reception are disabled).
Note 2. The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.
Note 3. LSB-first should be selected and the value of MSB bit [7] in TDR cannot be transmitted.
The SCMR register selects the smart card interface and communication format.
SMIF bit (Smart Card Interface Mode Select)
Setting the SMIF bit to 1 selects smart card interface mode. Setting it to 0 selects all other modes:
Asynchronous mode, including multi-processor mode
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 541 of 1104
S124 User’s Manual
25. Serial Communications Interface (SCI)
Clock synchronous mode
Simple SPI mode
Simple IIC mode.
SINV bit (Transmitted/Received Data Invert)
The SINV bit inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To
invert the parity bit, invert the PM bit in SMR or SMR_SMCI.
CHR1 bit (Character Length 1)
The CHR1 bit selects the data length of transmit/receive data in combination with the CHR bit in SMR.
A fixed data length of 8 bits is used in modes other than asynchronous mode.
BCP2 bit (Base Clock Pulse 2)
The BCP2 bit selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this
bit in combination with the SMR_SMCI.BCP[1:0] bits.
Table 25.4
Combinations of SCMR.BCP2 bit and SMR_SMCI.BCP[1:0] bits
SCMR.BCP2 bit
SMR_SMCI.BCP[1:0] bits
Number of base clock cycles for 1-bit transfer period
0
0
0
93 clock cycles (S = 93)*1
0
0
1
128 clock cycles (S = 128)*1
0
1
0
186 clock cycles (S = 186)*1
0
1
1
512 clock cycles (S = 512)*1
1
0
0
32 clock cycles (S = 32)*1 (Initial Value)
1
0
1
64 clock cycles (S = 64)*1
1
1
0
372 clock cycles (S = 372)*1
1
1
1
256 clock cycles (S = 256)*1
Note 1. S is the value of S in the Bit Rate Register (BRR), see section 25.2.17, Bit Rate Register (BRR).
25.2.17
Bit Rate Register (BRR)
Address(es): SCI0.BRR 4007 0001h, SCI1.BRR 4007 0021h, SCI9.BRR 4007 0121h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
BRR is an 8-bit register that adjusts the bit rate.
As each SCI channel has independent baud rate generator control, different bit rates can be set for each. Table 25.5 shows
the relationship between the setting (N) in the BRR and the bit rate (B) for asynchronous mode, multiprocessor transfer,
clock synchronous mode, smart card interface mode, simple SPI mode, and simple IIC mode.
The initial value of BRR is FFh. BRR can be read by the CPU, but can only be written to when the TE and RE bits in
SCR/SCR_SMCI are 0.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 542 of 1104
S124 User’s Manual
Table 25.5
25. Serial Communications Interface (SCI)
Relationship between N setting in BRR and bit rate B
SEMR settings
Mode
Asynchronous, multiprocessor
transfer
BGDM
bit
0
ABCS
bit
ABCSE
bit
0
BRR setting
0
PCLKB ×
N=
1
0
1
0
1
1
0
N=
N=
Don’t
care
Clock synchronous,
simple SPI
64 × 22n-1 × B
PCLKB × 106
–1
Error (%) = {
–1
Error (%) = {
–1
Error (%) = {
–1
Error (%) = {
B × 64 × 22n-1 × (N + 1)
– 1 } × 100
0
0
Don’t
care
Error
106
1
N=
N=
Smart card interface
N=
Simple IIC*1
N=
PCLKB × 106
32 ×
22n-1
×B
PCLKB × 106
16 ×
22n-1
×B
PCLKB × 106
12 × 22n-1 × B
PCLKB × 106
8 × 22n-1 × B
PCLKB × 106
S × 22n+1 × B
PCLKB × 106
64 × 22n-1 × B
PCLKB × 106
B × 32 × 22n-1 × (N + 1)
PCLKB × 106
B × 16 × 22n-1 × (N + 1)
PCLKB × 106
B × 12 × 22n-1 × (N + 1)
– 1 } × 100
– 1 } × 100
– 1 } × 100
–1
–1
Error (%) = {
PCLKB × 106
B × S × 22n+1 × (N + 1)
–1 } × 100
–1
B: Bit rate (bps).
N: BRR setting for on-chip baud rate generator (0 N 255).
PCLKB: Operating frequency (MHz).
n and S: Determined by the settings of the SMR/SMR_SMCI and SCMR registers as listed in Table 25.7 and Table 25.8.
Note 1. Adjust the bit rate so that the widths at high and low level of the SCL output in simple IIC mode satisfy the IIC
standard.
Table 25.6
Calculating widths at high and low level for SCL
Mode
SCL
Formula (result in seconds)
IIC
Width at high level
(minimum value)
(N+1) × 4 × 2
Width at low level
(minimum value)
(N+1) × 4 × 2
Table 25.7
1
2n-1
×7×
2n-1
×8×
PCLKB ×
6
10
1
PCLKB ×
6
10
Clock source settings (1 of 2)
SMR or SMR_SMCI.CKS[1:0] bit
setting
CKS[1:0] bits
Clock source
n
00
PCLKB clock
0
01
PCLKB/4 clock
1
10
PCLKB/16 clock
2
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 543 of 1104
S124 User’s Manual
Table 25.7
25. Serial Communications Interface (SCI)
Clock source settings (2 of 2)
SMR or SMR_SMCI.CKS[1:0] bit
setting
CKS[1:0] bits
Clock source
n
11
PCLKB/64 clock
3
Table 25.8
Base clock settings in smart card interface mode
SCMR.BCP2 bit setting
SMR_SMCI.BCP[1:0] bit setting
BCP2 bit
BCP[1:0] bits
Base clock cycles for 1-bit period
S
0
00
93 clock cycles
93
0
01
128 clock cycles
128
0
10
186 clock cycles
186
0
11
512 clock cycles
512
1
00
32 clock cycles
32
1
01
64 clock cycles
64
1
10
372 clock cycles
372
1
11
256 clock cycles
256
Table 25.9 and Table 25.10 list examples of BRR (N) settings in asynchronous mode. Table 25.11 lists the maximum bit
rate selectable for each operating frequency. Table 25.14 lists examples of BRR (N) settings in smart card interface
mode. Table 25.17 lists examples of BRR (N) settings in simple IIC mode.
In smart card interface mode, the number of base clock cycles S in a 1-bit data transfer time can be selected. For details,
see section 25.6.4, Receive Data Sampling Timing and Reception Margin. Table 25.12 and Table 25.14 list the maximum
bit rates with external clock input.
When either the asynchronous mode base clock select bit (ABCS) or the Baud Rate Generator Double-speed Mode select
bit (BGDM) in the Serial Extended Mode Register (SEMR) is set to 1 in asynchronous mode, the bit rate becomes twice
that as listed in Table 25.16. When both of those registers are set to 1, the bit rate becomes four times the listed value.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 544 of 1104
S124 User’s Manual
Table 25.9
25. Serial Communications Interface (SCI)
Examples of BRR settings for different bit rates in asynchronous mode (1)
Operating frequency PCLKB (MHz)
Bit rate
(bps)
8
9.8304
10
12
12.288
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
2
141
0.03
2
174
–0.26
2
177
–0.25
2
212
0.03
2
217
0.08
150
2
103
0.16
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
207
0.16
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
103
0.16
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
207
0.16
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
103
0.16
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
51
0.16
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
25
0.16
0
31
0.00
0
32
–1.36
0
38
0.16
0
39
0.00
19200
0
12
0.16
0
15
0.00
0
15
1.73
0
19
–2.34
0
19
0.00
31250
0
7
0.00
0
9
–1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
—
—
—
0
7
0.00
0
7
1.73
0
9
–2.34
0
9
0.00
Operating frequency PCLKB (MHz)
Bit rate
(bps)
14
16
17.2032
N
Error (%)
19.6608
n
N
Error (%)
n
N
Error (%)
110
2
248
–0.17
3
70
0.03
3
75
0.48
3
79
–0.12
3
86
0.31
150
2
181
0.16
2
207
0.16
2
223
0.00
2
233
0.16
2
255
0.00
300
2
90
0.16
2
103
0.16
2
111
0.00
2
116
0.16
2
127
0.00
600
1
181
0.16
1
207
0.16
1
223
0.00
1
233
0.16
1
255
0.00
1200
1
90
0.16
1
103
0.16
1
111
0.00
1
116
0.16
1
127
0.00
2400
0
181
0.16
0
207
0.16
0
223
0.00
0
233
0.16
0
255
0.00
4800
0
90
0.16
0
103
0.16
0
111
0.00
0
116
0.16
0
127
0.00
9600
0
45
–0.93
0
51
0.16
0
55
0.00
0
58
–0.69
0
63
0.00
19200
0
22
–0.93
0
25
0.16
0
27
0.00
0
28
1.02
0
31
0.00
31250
0
13
0.00
0
15
0.00
0
16
1.20
0
17
0.00
0
19
–1.70
38400
—
—
—
0
12
0.16
0
13
0.00
0
14
–2.34
0
15
0.00
Note:
n
18
n
N
Error (%)
n
N
Error (%)
In this example, SEMR.ABCS = 0, SEMR.ABCSE = 0, and SEMR.BGDM = 0. When either ABCS bit or BGDM bit
is set to 1, the bit rate doubles. When both ABCS = 1 and BGDM = 1, the bit rate increases four times.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 545 of 1104
S124 User’s Manual
Table 25.10
25. Serial Communications Interface (SCI)
Examples of BRR settings for various bit rates in asynchronous mode (2)
Operating frequency PCLKB (MHz)
20
25
30
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
3
88
–0.25
3
110
–0.02
3
132
0.13
150
3
64
0.16
3
80
0.47
3
97
–0.35
300
2
129
0.16
2
162
–0.15
2
194
0.16
600
2
64
0.16
2
80
0.47
2
97
–0.35
1200
1
129
0.16
1
162
–0.15
1
194
0.16
2400
1
64
0.16
1
80
0.47
1
97
–0.35
4800
0
129
0.16
0
162
–0.15
0
194
0.16
9600
0
64
0.16
0
80
0.47
0
97
–0.35
19200
0
32
–1.36
0
40
–0.76
0
48
–0.35
31250
0
19
0.00
0
24
0.00
0
29
0.00
38400
0
15
1.73
0
19
1.73
0
23
1.73
Note:
In this example, SEMR.ABCS = 0, SEMR.ABCSE = 0, and SEMR.BGDM = 0. When either ABCS bit or BGDM bit
is set to 1, the bit rate doubles. When both ABCS = 1 and BGDM = 1, the bit rate increases four times.
Table 25.11
Maximum bit rate for each operating frequency in asynchronous mode (1 of 2)
SEMR settings
PCLKB
(MHz)
BGDM
bit
ABCS
bit
ABCSE
bit
n
N
Maximum
bit rate
(bps)
8
0
0
0
0
0
250000
1
0
0
0
500000
1
0
0
0
0
1
0
0
0
1000000
Don’t
care
Don’t
care
1
0
0
1333333
0
0
0
0
0
307200
1
0
0
0
614400
0
0
0
0
9.8304
1
10
12
0
0
0
1228800
Don’t
care
1
0
0
1638400
0
0
0
0
0
312500
1
0
0
0
625000
0
0
0
0
1
0
0
0
1250000
Don’t
care
Don’t
care
1
0
0
1666666
0
0
0
0
0
375000
1
0
0
0
750000
0
0
0
0
1
0
0
0
1500000
Don’t
care
1
0
0
2000000
Don’t
care
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
BGDM
bit
ABCS
bit
ABCSE
bit
n
N
Maximum
bit rate
(bps)
17.2032
0
0
0
0
0
537600
1
0
0
0
1075200
0
0
0
0
1
0
0
0
2150400
Don’t
care
Don’t
care
1
0
0
2867200
0
0
0
0
0
562500
1
0
0
0
1125000
0
0
0
0
18
1
1
1
PCLKB
(MHz)
1
Don’t
care
1
SEMR settings
19.6608
1
0
0
0
2250000
Don’t
care
Don’t
care
1
0
0
3000000
0
0
0
0
0
614400
1
0
0
0
1228800
1
20
0
0
0
0
1
0
0
0
2457600
Don’t
care
Don’t
care
1
0
0
3276800
0
0
0
0
0
625000
1
0
0
0
1250000
1
Don’t
care
0
0
0
0
1
0
0
0
2500000
Don’t
care
1
0
0
3333333
Page 546 of 1104
S124 User’s Manual
Table 25.11
25. Serial Communications Interface (SCI)
Maximum bit rate for each operating frequency in asynchronous mode (2 of 2)
SEMR settings
PCLKB
(MHz)
BGDM
bit
ABCS
bit
ABCSE
bit
n
N
Maximum
bit rate
(bps)
12.288
0
0
0
0
0
384000
1
0
0
0
768000
1
0
0
0
0
1
0
0
0
1536000
Don’t
care
Don’t
care
1
0
0
2048000
0
0
0
0
0
437500
1
0
0
0
875000
1
0
0
0
0
1
0
0
0
1750000
Don’t
care
Don’t
care
1
0
0
2333333
0
0
0
0
0
500000
1
0
0
0
1000000
0
0
0
0
1
0
0
0
2000000
Don’t
care
1
0
0
2666666
14
16
1
Don’t
care
Table 25.12
SEMR settings
PCLKB
(MHz)
BGDM
bit
ABCS
bit
ABCSE
bit
n
N
Maximum
bit rate
(bps)
25
0
0
0
0
0
781250
1
0
0
0
1562500
0
0
0
0
1
0
0
0
3125000
Don’t
care
Don’t
care
1
0
0
4166666
0
0
0
0
0
937500
1
0
0
0
1875000
0
0
0
0
1
0
0
0
3750000
Don’t
care
1
0
0
5000000
1
30
1
Don’t
care
Maximum bit rate with external clock input in asynchronous mode
Maximum bit rate (bps)
PCLKB (MHz)
Table 25.13
External input clock (MHz)
SEMR.ABCS bit = 0
SEMR.ABCS bit = 1
8
2.0000
125000
250000
9.8304
2.4576
153600
307200
10
2.5000
156250
312500
12
3.0000
187500
375000
12.288
3.0720
192000
384000
14
3.5000
218750
437500
16
4.0000
250000
500000
17.2032
4.3008
268800
537600
18
4.5000
281250
562500
19.6608
4.9152
307200
614400
20
5.0000
312500
625000
25
6.2500
390625
781250
30
7.5000
468750
937500
BRR settings for different bit rates in clock synchronous and simple SPI modes (1 of 2)
Operating Frequency PCLKB (MHz)
8
Bit rate (bps)
10
16
20
n
N
n
N
n
N
250
3
124
—
—
3
249
500
2
249
—
—
3
1k
2
124
—
—
2
25
n
N
124
—
—
249
—
—
30
n
N
3
97
n
N
3
233
3
116
110
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 547 of 1104
S124 User’s Manual
Table 25.13
25. Serial Communications Interface (SCI)
BRR settings for different bit rates in clock synchronous and simple SPI modes (2 of 2)
Operating Frequency PCLKB (MHz)
8
Bit rate (bps)
10
16
20
25
30
n
N
n
N
n
N
n
N
n
N
n
N
2.5 k
1
199
1
249
2
99
2
124
2
155
2
187
5k
1
99
1
124
1
199
1
249
2
77
2
93
10 k
0
199
0
249
1
99
1
124
1
155
1
187
25 k
0
79
0
99
0
159
0
199
0
249
1
74
50 k
0
39
0
49
0
79
0
99
0
124
0
149
100 k
0
19
0
24
0
39
0
49
0
62
0
74
250 k
0
7
0
9
0
15
0
19
0
24
0
29
500 k
0
3
0
4
0
7
0
9
—
—
0
14
1M
0
1
0
3
0
4
—
—
—
—
0
1
—
—
0
2
0
0*1
—
—
—
—
0
0*1
2.5 M
0
0*1
5M
7.5 M
Space: Setting prohibited.
—: Can be set, but an error occurs.
Note 1. Continuous transmission or reception is impossible. After transmitting or receiving one frame of data, a 1-bit
period elapses before starting transmitting or receiving the next frame of data. The output of the synchronization
clock stops for a 1-bit period. For this reason, it takes 9 bits worth of time to transfer one frame (8 bits) of data,
and the average transfer rate is 8/9 times the bit rate.
Table 25.14
PCLKB (MHz)
Maximum bit rate with external clock input in clock synchronous and simple SPI modes
External input clock (MHz)
Maximum bit rate (Mbps)
8
1.3333
1.3333333
10
1.6667
1.6666667
12
2.0000
2.0000000
14
2.3333
2.3333333
16
2.6667
2.6666667
18
3.0000
3.0000000
20
3.3333
3.3333333
25
4.1667
4.1666667
30
5.0000
5.0000000
Table 25.15
BRR settings for different bit rates in smart card interface mode, n = 0, S = 372
Operating frequency PCLKB (MHz)
7.1424
10.00
10.7136
13.00
bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9600
0
0
0.00
0
1
-30
0
1
-25
0
1
-8.99
Operating frequency PCLKB (MHz)
14.2848
16.00
18.00
20.00
bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
9600
0
1
0.00
0
1
12.01
0
2
-15.99
0
2
-6.66
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 548 of 1104
S124 User’s Manual
25. Serial Communications Interface (SCI)
Operating frequency PCLKB (MHz)
25.00
30.00
bit rate (bps)
n
N
Error (%)
n
N
Error (%)
9600
0
3
-12.49
0
3
5.01
Table 25.16
Maximum bit rate for each operating frequency in smart card interface mode, S = 32
PCLKB (MHz)
Maximum bit rate (bps)
n
N
10.00
156250
0
0
10.7136
167400
0
0
13.00
203125
0
0
16.00
250000
0
0
18.00
281250
0
0
20.00
312500
0
0
25.00
390625
0
0
30.00
468750
0
0
Table 25.17
BRR settings for different bit rates in simple IIC mode
Operating frequency PCLKB (MHz)
8
10
Bit rate (bps)
n
10 k
0
25 k
0
0
4
50 k
k*1
N
16
Error (%)
n
N
Error (%)
n
N
Error (%)
24
0.0
0
30
0.8
1
12
-3.8
9
0.0
0
12
-3.8
1
4
0.0
0.0
0
5
4.2
1
2
-16.7
0
2
-16.7
0
3
-21.9
0
4
0.0
250 k
0
0
0.0
0
0
25
0
1
0.0
350 k
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
400
k*1
Operating frequency PCLKB (MHz)
20
25
30
Bit rate (bps)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
10 k
1
15
-2.3
1
19
-2.3
1
22
1.9
25 k
1
5
4.2
1
7
-2.3
1
8
4.2
50 k
1
2
4.2
1
3
-2.3
1
4
-6.3
100 k*1
0
6
-10.7
1
1
-2.3
1
2
-21.9
250 k
0
2
-6.7
0
2
4.2
0
3
-6.3
350 k
0
1
-10.7
0
1
11.6*2
0
2
-10.7
400 k*1
0
1
-21.9
0
1
-2.3*2
0
2
-21.9
Note 1. The bit rate of 100 kbps and 400 kbps indicates the set value at which the error is on the minus side.
Note 2. The minimum value of low width is smaller than 1.3 s which is the standard value of fast mode.
Table 25.18
Minimum widths at high and low level for SCL at different bit rates in simple IIC mode (1 of 2)
Operating frequency PCLKB (MHz)
8
10
Bit rate
(bps)
n
N
Min. Widths at
High/Low Level
for SCL (μs)
10 k
0
24
43.75/50.00
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
n
0
16
N
Min. Widths at
High/Low Level
for SCL (μs)
n
N
Min. Widths at
High/Low Level
for SCL (μs)
30
43.40/49.60
1
12
45.5/52.00
Page 549 of 1104
S124 User’s Manual
Table 25.18
25. Serial Communications Interface (SCI)
Minimum widths at high and low level for SCL at different bit rates in simple IIC mode (2 of 2)
Operating frequency PCLKB (MHz)
8
10
N
Min. Widths at
High/Low Level
for SCL (μs)
n
N
Min. Widths at
High/Low Level
for SCL (μs)
12
18.2/20.80
1
4
17.50/20.00
0
5
8.40/9.60
1
2
10.50/12.00
5.25/6.00
0
3
5.60/6.40
0
4
4.38/5.00
1.75/2.00
0
0
1.40/1.60
0
1
1.75/2.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
n
N
Min. Widths at
High/Low Level
for SCL (μs)
N
Min. Widths at
High/Low Level
for SCL (μs)
n
9
17.50/20.00
0
0
4
8.75/10.00
100 k
0
2
250 k
0
0
350 k
—
400 k
—
Bit rate
(bps)
n
25 k
0
50 k
16
Operating frequency PCLKB (MHz)
20
25
30
n
N
Min. Widths at
High/Low Level
for SCL (μs)
Bit rate
(bps)
n
N
Min. Widths at
High/Low Level
for SCL (μs)
10 k
1
15
44.80/51.20
1
19
44.80/51.20
1
22
42.93/49.60
25 k
1
5
16.80/19.20
1
7
17.92/20.48
1
8
16.80/19.20
50 k
1
2
8.40/9.60
1
3
8.96/10.24
1
4
9.33/10.66
100 k
0
6
4.90/5.60
1
1
4.48/5.12
1
2
5.60/6.40
250 k
0
2
2.10/2.40
0
2
1.68/1.92
0
3
1.86/2.13
350 k
0
1
1.40/1.60
0
1
1.12/1.28*1
0
2
1.40/1.60
1
1.12/1.28*1
0
2
1.40/1.60
400 k
0
1
1.40/1.60
0
Note 1. The minimum value of low width is smaller than 1.3 s which is the standard value of fast mode. The setting
values are the same as in Table 25.17.
25.2.18
Modulation Duty Register (MDDR)
Address(es): SCI0.MDDR 4007 0012h, SCI1.MDDR 4007 0032h, SCI9.MDDR 4007 0132h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
MDDR corrects the bit rate adjusted by the BRR register.
When the BRME bit in SEMR is set to 1, the bit rate generated by the on-chip baud rate generator is evenly corrected
according to the settings of MDDR (M/256). Table 25.19 lists the relationship between the MDDR setting (M) and the bit
rate (B).
The initial value of MDDR is FFh. Bit [7] in this register is fixed to 1. The CPU can read the MDDR register, but this
register is only writable when the TE and RE bits in SCR/SCR_SMCI are 0.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 550 of 1104
S124 User’s Manual
Table 25.19
25. Serial Communications Interface (SCI)
Relationship between MDDR setting (M) and bit rate (B) when bit rate modulation function is used
SEMR settings
Mode
Asynchronous,
multiprocessor
transfer
BGD
M bit
ABC
S bit
ABC
SE
bit
0
0
0
BRR setting
N=
1
0
1
0
1
1
0
N=
N=
Don’t
care
PCLKB × 106
64 × 22n-1 × (256/M) × B
–1
Error (%)
={
–1
Error (%)
={
–1
Error (%)
={
–1
Error (%)
={
PCLKB × 106
B × 64 × 22n-1 × (256/M) × (N + 1)
– 1 } × 100
0
0
Don’t
care
Error
PCLKB × 106
32 ×
Clock synchronous,
simple SPI*1
N=
16 ×
× (256/M) × B
12 × 22n-1 × (256/M) × B
PCLKB × 106
8 × 22n-1 × (256/M) × B
PCLKB × 106
S × 22n+1 × (256/M) × B
Simple IIC*2
N=
22n-1
PCLKB × 106
Smart card interface
N=
× (256/M) × B
PCLKB × 106
1
N=
22n-1
PCLKB × 106
64 × 22n-1 × (256/M) × B
PCLKB × 106
B × 32 × 22n-1 × (256/M) × (N + 1)
PCLKB × 106
B × 16 × 22n-1 × (256/M) × (N + 1)
PCLKB × 106
B × 12 × 22n-1 × (256/M) × (N + 1)
– 1 } × 100
– 1 } × 100
– 1 } × 100
–1
Error (%)
={
–1
PCLKB × 106
B × S × 22n+1 × (256/M) × (N + 1)
–1 } × 100
–1
B: Bit rate (bps).
M: MDDR setting (128 ≤ MDDR ≤ 255).
N: BRR setting for baud rate generator (0 ≤ N ≤ 255).
PCLKB: Operating frequency (MHz).
n and S: Determined by the settings of the SMR/SMR_SMCI and SCMR registers as listed in Table 25.8 and Table 25.9.
Bit Rate Register (BRR).
Note 1. Do not use this function in clock synchronous mode and in the highest speed settings in Simple SPI mode
(SMR.CKS[1:0] = 00b, SCR.CKE[1] = 0, and BRR = 0).
Note 2. Adjust the bit rate so that the widths at high and low level of the SCL output in Simple IIC mode satisfy the IIC
standard.
Table 25.20 and Table 25.21 list examples of N settings in BRR and M settings in MDDR in asynchronous mode.
Table 25.20
Examples of BRR and MDDR settings for different bit rates in asynchronous mode (1)
Operating frequency PCLKB (MHz)
8
9.8304
Bit rate
(bps)
M
BGDM
bit
Error
(%)
n
N
n
N
38400
0
5
236
0
0.03
0
57600
0
3
236
0
0.03
115200
0
1
236
0
230400
0
0
236
0
460800
0
0
236
1
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
16
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
7
(256)*1
0
0.00
0
10
173
1
–0.01
0
4
240
0
0.00
0
4
236
0
0.03
0.03
0
1
192
0
0.00
0
4
236
1
0.03
0.03
0
0
192
0
0.00
0
1
189
1
0.14
0.03
0
0
192
1
0.00
0
0
189
1
0.14
Page 551 of 1104
S124 User’s Manual
25. Serial Communications Interface (SCI)
Operating frequency PCLKB (MHz)
12
12.288
Bit rate
(bps)
n
N
38400
0
57600
115200
14
M
BGDM
bit
Error
(%)
BGDM
bit
Error
(%)
n
N
M
8
236
0
0.03
0
9
(256)*1
0
0.00
0
16
191
1
0.00
0
5
236
0
0.03
0
4
192
0
0.00
0
13
236
1
0.03
0
2
236
0
0.03
0
4
192
1
0.00
0
6
236
1
0.03
n
N
M
BGDM
bit
Error
(%)
230400
0
2
236
1
0.03
0
2
230
1
–0.17
0
2
202
1
–0.11
460800
0
0
157
1
–0.18
0
0
154
1
–0.26
0
0
135
1
0.14
Operating frequency PCLKB (MHz)
16
17.2032
18
Bit rate
(bps)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
38400
0
11
236
0
0.03
0
13
(256)*1
0
0.00
0
18
166
1
–0.01
57600
0
7
236
0
0.03
0
6
192
0
0.00
0
18
249
1
–0.01
115200
0
3
236
0
0.03
0
6
192
1
0.00
0
8
236
1
0.03
230400
0
1
236
0
0.03
0
3
219
1
–0.20
0
1
210
0
0.14
460800
0
1
236
1
0.03
0
1
219
1
–0.20
0
0
210
0
0.14
Note 1. In this example, the ABCS and ABCSE in SEMR are 0. SEMR.BRME = 0 (M = 256) disables the bit rate
modulation function.
Table 25.21
Examples of BRR and MDDR settings for different bit rates in asynchronous mode (2)
Operating frequency PCLKB (MHz)
19.6608
20
25
Bit Rate
(bps)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
n
N
M
BGDM
bit
Error
(%)
38400
0
15
(256)*1
0
0.00
0
10
173
0
–0.01
0
11
151
0
0.00
57600
0
9
240
0
0.00
0
9
236
0
0.03
0
7
151
0
0.00
115200
0
4
240
0
0.00
0
4
236
0
0.03
0
3
151
0
0.00
230400
0
1
192
0
0.00
0
4
236
1
0.03
0
1
151
0
0.00
460800
0
0
192
0
0.00
0
0
189
0
0.14
0
0
151
0
0.00
Operating frequency PCLKB (MHz)
30
Bit Rate
(bps)
n
N
M
BGDM
bit
Error
(%)
38400
0
36
194
1
0.01
57600
0
10
173
0
–0.01
115200
0
10
173
1
–0.01
230400
0
6
220
1
–0.09
460800
0
3
252
1
0.14
Note 1. In this example, the ABCS and ABCSE in SEMR are 0. SEMR.BRME = 0 (M = 256) disables the bit rate
modulation function.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 552 of 1104
S124 User’s Manual
25.2.19
25. Serial Communications Interface (SCI)
Serial Extended Mode Register (SEMR)
Address(es): SCI0.SEMR 4007 0007h, SCI1.SEMR 4007 0027h, SCI9.SEMR 4007 0127h
b7
b6
b5
RXDES BGDM NFEN
EL
Value after reset:
Bit
0
Symbol
0
0
b4
b3
b2
ABCS ABCSE BRME
0
0
0
b1
b0
—
—
0
0
Bit name
Description
R/W
b0, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b2
BRME
Bit Rate Modulation
Enable
0: Bit rate modulation function is disabled
1: Bit rate modulation function is enabled.
R/W*1
b3
ABCSE
Asynchronous Mode
Extended Base Clock
Select 1
Valid only in asynchronous mode with SCR.CKE[1] = 0:
0: Clock cycles for 1-bit period is decided with combination of BGDM and
ABCS in SEMR
1: Baud rate is 6 base clock cycles for 1-bit period.
R/W*1
b4
ABCS
Asynchronous Mode
Base Clock Select
Valid only in asynchronous mode:
0: Selects 16 base clock cycles for 1-bit period
1: Selects 8 base clock cycles for 1-bit period.
R/W*1
b5
NFEN
Digital Noise Filter
Function Enable
In asynchronous mode
0: Noise cancellation function for the RXDn input signal is disabled
1: Noise cancellation function for the RXDn input signal is enabled.
R/W*1
In Simple IIC mode:
0: Noise cancellation function for the SCLn and SDAn input signals is
disabled
1: Noise cancellation function for the SCLn and SDAn input signals is
enabled.
The NFEN bit should be 0 in any mode other than above.
b6
BGDM
Baud Rate Generator
Double-Speed Mode
Select
Valid only in asynchronous mode with SCR.CKE[1] = 0:
0: Baud rate generator outputs the clock with basic frequency
1: Baud rate generator outputs the clock with doubled frequency.
R/W*1
b7
RXDESEL
Asynchronous Start Bit
Edge Detection Select
Valid only in asynchronous mode:
0: A low level on the RXDn pin is detected as the start bit
1: A falling edge on the RXDn pin is detected as the start bit.
R/W*1
Note 1. Writable only when TE in SCR/SCR_SMCI = 0 and RE in SCR/SCR_SMCI = 0 (both serial transmission and
reception are disabled).
SEMR selects the clock source for 1-bit period in asynchronous mode.
BRME bit (Bit Rate Modulation Enable)
Enables or disables the bit rate modulation function. The bit rate generated by the on-chip baud rate generator is evenly
corrected when this function is enabled.
ABCSE bit (Asynchronous Mode Extended Base Clock Select 1)
The pulse number for a base clock at 1-bit period is 6 and the double-frequency clock is output from the baud rate
generator. When the bit rate is set to 6 while dividing the bus clock frequency, use this bit and set SMR.CKS[1:0] to 00b
and BRR to 0. Set this bit to 0 except in asynchronous mode.
ABCS bit (Asynchronous Mode Base Clock Select)
Selects the clock cycles for 1-bit period. Set this bit to 0 except in asynchronous mode.
NFEN bit (Digital Noise Filter Function Enable)
This bit enables or disables the digital noise filter function.
When the function is enabled:
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 553 of 1104
S124 User’s Manual
25. Serial Communications Interface (SCI)
Noise cancellation is applied to the RXDn input signal in asynchronous mode
Noise cancellation is applied to the SDAn and SCLn input signals in simple IIC mode.
In all other modes, set the NFEN bit to 0 to disable the digital noise filter function.
When the digital noise filter function is disabled, input signals are transferred as received.
BGDM bit (Baud Rate Generator Double-Speed Mode Select)
Selects the cycle of output clock for the baud rate generator.
This bit is valid when the on-chip baud rate generator is selected as the clock source (SCR.CKE[1] = 0) in asynchronous
mode (SMR.CM = 0). For the clock output from the baud rate generator, either single or doubled frequency can be
selected. The base clock is generated by the clock output from the baud rate generator. When the BGDM bit is set to 1,
the base clock cycle is halved and the bit rate is doubled.
Set this bit to 0 in modes other than asynchronous mode.
RXDESEL bit (Asynchronous Start Bit Edge Detection Select)
Selects the detection method of the start bit for reception in asynchronous mode. When a break occurs, data receiving
operation depends on the settings of this bit. Set this bit to 1 when reception must be stopped while a break occurs or
when reception must be started without keeping the RXDn pin input at high level for the period of one data frame or
longer after completion of the break.
Set this bit to 0 in modes other than asynchronous mode.
25.2.20
Noise Filter Setting Register (SNFR)
Address(es): SCI0.SNFR 4007 0008h, SCI1.SNFR 4007 0028h, SCI9.SNFR 4007 0128h
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
NFCS[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
NFCS[2:0]
Noise Filter Clock Select
In asynchronous mode, the standard setting for the base clock is as
follows.
R/W*1
b2
b0
0 0 0: The clock signal divided by 1 is used with the noise filter.
In simple IIC mode, the standard settings for the clock source of the
on-chip baud rate generator selected by the SMR.CKS[1:0] bits are
as follows:
b2
b0
0 0 1: The clock signal divided by 1 is used with the noise filter
0 1 0: The clock signal divided by 2 is used with the noise filter
0 1 1: The clock signal divided by 4 is used with the noise filter
1 0 0: The clock signal divided by 8 is used with the noise filter.
Other settings are prohibited.
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR/SCR_SMCI are 0 (serial reception and
transmission disabled).
The SNFR register sets the digital noise filter clock.
NFCS[2:0] bits (Noise Filter Clock Select)
The NFCS[2:0] bits select the sampling clock for the digital noise filter. To use the noise filter in asynchronous mode, set
these bits to 000b. In simple IIC mode, set the bits to a value in the range from 001b to 100b.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 554 of 1104
S124 User’s Manual
25. Serial Communications Interface (SCI)
I2C Mode Register 1 (SIMR1)
25.2.21
Address(es): SCI0.SIMR1 4007 0009h, SCI1.SIMR1 4007 0029h, SCI9.SIMR1 4007 0129h
b7
b6
b5
b4
b3
IICDL[4:0]
Value after reset:
0
0
0
0
0
b2
b1
b0
—
—
IICM
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICM
Simple IIC Mode Select
SMIF IICM
R/W*1
0
0: Asynchronous mode, multi-processor mode, or clock synchronous mode
1: Simple IIC mode
0: Smart card interface mode
1: Setting prohibited.
0
1
1
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7 to b3
IICDL[4:0]
SDA Delay Output Select
The following cycles are of the clock signal from the on-chip baud rate
generator:
R/W*1
b7
b3
0 0 0 0 0: No output delay
0 0 0 0 1: 0 to 1 cycle
0 0 0 1 0: 1 to 2 cycles
0 0 0 1 1: 2 to 3 cycles
0 0 1 0 0: 3 to 4 cycles
0 0 1 0 1: 4 to 5 cycles
1 1 1 1 0: 29 to 30 cycles
1 1 1 1 1: 30 to 31 cycles.
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (both serial transmission and
reception are disabled).
SIMR1 selects simple IIC mode and the number of delay stages for the SDAn output.
IICM bit (Simple IIC Mode Select)
In combination with the SMIF bit in SCMR, this bit selects the operating mode.
IICDL[4:0] bits (SDA Delay Output Select)
The IICDL[4:0] bits set a delay for output on the SDAn pin relative to the falling edge of the output on the SCLn pin.
The available delay settings range from no delay to 31 cycles, with the clock signal from the on-chip baud rate generator
as the base. The signal obtained by frequency-dividing PCLKB by the divisor set in SMR.CKS[1:0], is supplied as the
clock signal from the on-chip baud rate generator. Set these bits to 00000b unless operation is in simple IIC mode. In
simple IIC mode, set the bits to a value in the range from 00001b to 11111b.
I2C Mode Register 2 (SIMR2)
25.2.22
Address(es): SCI0.SIMR2 4007 000Ah, SCI1.SIMR2 4007 002Ah, SCI9.SIMR2 4007 012Ah
b7
Value after reset:
b6
b5
—
—
IICACK
T
b4
b3
b2
—
—
—
0
0
0
0
0
0
b1
b0
IICCSC IICINT
M
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICINTM
IIC Interrupt Mode Select
0: Use ACK/NACK interrupts
1: Use reception and transmission interrupts.
R/W*1
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Bit
Symbol
Bit name
Description
R/W
b1
IICCSC
Clock Synchronization
0: Do not synchronize with clock signal
1: Synchronize with clock signal.
R/W*1
b4 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
IICACKT
ACK Transmission Data
0: ACK transmission
1: NACK transmission and reception of ACK/NACK.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (serial reception and transmission
disabled).
SIMR2 selects how reception and transmission are controlled in simple IIC mode.
IICINTM bit (IIC Interrupt Mode Select)
The IICINTM bit selects the sources of interrupt requests in simple IIC mode.
IICCSC bit (Clock Synchronization)
Set the IICCSC bit to 1 if the internally generated SCL clock signal is to be synchronized when the SCLn pin is driven
low because a wait was inserted by another other device.
The SCL clock signal is not synchronized if the IICCSC bit is 0. The SCL clock signal is generated according to the rate
selected in the BRR regardless of the level being input on the SCLn pin.
Set the IICCSC bit to 1 except during debugging.
IICACKT bit (ACK Transmission Data)
Transmitted data contains ACK bits. Set this bit to 1 when ACK and NACK bits are received.
I2C Mode Register 3 (SIMR3)
25.2.23
Address(es): SCI0.SIMR3 4007 000Bh, SCI1.SIMR3 4007 002Bh, SCI9.SIMR3 4007 012Bh
b7
b6
IICSCLS[1:0]
Value after reset:
0
0
b5
b4
IICSDAS[1:0]
0
b3
b2
b1
b0
IICSTIF IICSTP IICRST IICSTA
REQ AREQ REQ
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICSTAREQ
Start Condition Generation
0: Do not generate start condition
1: Generate start condition.*1, *3, *5, *6
R/W
b1
IICRSTAREQ
Restart Condition
Generation
0: Do not generate restart condition
1: Generate restart condition.*2, *3, *5, *6
R/W
b2
IICSTPREQ
Stop Condition Generation
0: Do not generate stop condition
1: Generate stop condition.*2, *3, *5, *6
R/W
b3
IICSTIF
Issuing of Start, Restart, or
Stop Condition Completed
Flag
0: No requests made for generating conditions, or a condition is
being generated
1: Generation of start, restart, or stop condition complete.
When 0 is written to IICSTIF, it is set to 0.*4
R/W*4
b5, b4
IICSDAS[1:0]
SDA Output Select
b5 b4
R/W
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0
0
1
1
0: Serial data output
1: Generate start, restart, or stop condition
0: Output low on SDAn pin
1: Drive SDAn pin to high-impedance state.
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25. Serial Communications Interface (SCI)
Bit
Symbol
Bit name
Description
R/W
b7, b6
IICSCLS[1:0]
SCL Output Select
b7 b6
R/W
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
0
0
1
1
0: Serial clock output
1: Generate start, restart, or stop condition
0: Output low on SCLn pin
1: Drive SCLn pin to high-impedance state.
Only generate a start condition after checking the bus state and confirming that it is free.
Generate a restart or stop condition after checking the bus state and confirming that it is busy.
Do not set more than one of the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits to 1 at a given time.
Only write 0. When 1 is written, the value is ignored.
Execute the generation of a condition after the value of the IICSTIF flag is 0.
Do not write 0 to this bit while it is 1. Generation of a condition is suspended by writing 0 to this bit while it is 1.
IICSTAREQ bit (Start Condition Generation)
When a start condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b in addition to setting
the IICSTAREQ bit to 1.
[Setting condition]
Writing 1 to the bit.
[Clearing condition]
On completion of start condition generation.
IICRSTAREQ bit (Restart Condition Generation)
When a restart condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b in addition to
setting the IICRSTAREQ bit to 1.
[Setting condition]
Writing 1 to the bit.
[Clearing condition]
Completion of restart condition generation.
IICSTPREQ bit (Stop Condition Generation)
When a stop condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b in addition to setting
the IICSTPREQ bit to 1.
[Setting condition]
Writing 1 to the bit.
[Clearing condition]
Completion of stop condition generation.
IICSTIF flag (Issuing of Start, Restart, or Stop Condition Completed Flag)
After generating a condition, the IICSTIF flag indicates that the generation is complete. When using the IICSTAREQ,
IICRSTAREQ, or IICSTPREQ bit to cause generation of a condition, do so after setting the IICSTIF flag to 0.
When the IICSTIF flag is 1 while an interrupt request is enabled by setting the SCR.TEIE bit, an STI request is output.
[Setting condition]
On completion of a start, restart, or stop condition generation.
If this conflicts with any of the clearing conditions for the flag, the clearing condition takes precedence.
[Clearing conditions]
Writing 0 to the bit (after that, confirm that the IICSTIF flag is 0)
Writing 0 to the SIMR1.IICM bit when operation is not in simple IIC mode
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25. Serial Communications Interface (SCI)
Writing 0 to the SCR.TE bit.
IICSDAS[1:0] bits (SDA Output Select)
The IICSDAS[1:0] bits control output from the SDAn pin. Set the IICSDAS[1:0] and IICSCLS[1:0] bits to the same
value.
IICSCLS[1:0] bits (SCL Output Select)
The IICSCLS[1:0] bits control output from the SCLn pin. Set the IICSCLS[1:0] and IICSDAS[1:0] bits to the same
value.
I2C Status Register (SISR)
25.2.24
Address(es): SCI0.SISR 4007 000Ch, SCI1.SISR 4007 002Ch, SCI9.SISR 4007 012Ch
b7
Value after reset:
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
IICACK
R
0
0
x
x
0
x
0
0
Bit
Symbol
Bit name
Description
R/W
b0
IICACKR
ACK Reception Data Flag
0: ACK received
1: NACK received.
R
b1
—
Reserved
This bit is read as 0
R
b2
—
Reserved
The read value is undefined
R
b3
—
Reserved
This bit is read as 0
R
b5, b4
—
Reserved
The read values are undefined
R
b7, b6
—
Reserved
These bits are read as 0
R
SISR monitors state in simple IIC mode.
IICACKR flag (ACK Reception Data Flag)
Received ACK and NACK bits can be read from the IICACKR flag. This flag is updated on the rising edge of the SCL
clock for the ACK/NACK receiving bit.
25.2.25
SPI Mode Register (SPMR)
Address(es): SCI0.SPMR 4007 000Dh, SCI1.SPMR 4007 002Dh, SCI9.SPMR 4007 012Dh
b7
b6
CKPH CKPOL
Value after reset:
0
0
b5
b4
b3
b2
b1
b0
—
MFF
—
MSS
CTSE
SSE
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSE
SSn Pin Function Enable
0: Disable SSn pin function
1: Enable SSn pin function.
R/W*1
b1
CTSE
CTS Enable
0: Disable CTS function (RTS output function is enabled)
1: Enable CTS function.
R/W*1
b2
MSS
Master Slave Select
0: Transmit through TXDn pin and receive through RXDn pin (master
mode)
1: Receive through TXDn pin and transmit through RXDn pin (slave
mode).
R/W*1
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
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Bit
Symbol
Bit name
Description
R/W
b4
MFF
Mode Fault Flag
0: No mode fault error
1: Mode fault error.
R/W*2
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
CKPOL
Clock Polarity Select
0: Do not invert clock polarity
1: Invert clock polarity.
R/W*1
b7
CKPH
Clock Phase Select
0: Do not delay clock
1: Delay clock.
R/W*1
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (both serial transmission and
reception are disabled).
Note 2. Only write 0 to these bits to clear the flag.
SPMR selects the extension settings in asynchronous and clock synchronous modes.
SSE bit (SSn Pin Function Enable)
Set the SSE bit to 1 if the SSn pin is to be used to control transmission and reception in simple SPI mode. Set this bit to 0
in all other modes. Additionally, for usage in simple SPI mode, the SSn pin on the master side is not required to control
reception and transmission when master mode (SCR.CKE[1:0] = 00b and MSS = 0) is selected and there is a single
master. Therefore, the setting for the SSE bit is 0. Do not set both the SSE and CTSE bits to enabled as operation is the
same as that when these bits are set to 0.
CTSE bit (CTS Enable)
Set the CTSE bit to 1 if the SSn pin is to be used for inputting the CTS control signal to control transmission and
reception. The RTS signal is output when this bit is set to 0. Set this bit to 0 in smart card interface mode, simple SPI
mode, and simple IIC mode. Do not set both the CTSE and SSE bits to enabled as operation is the same as that when
these bits are set to 0.
MSS bit (Master Slave Select)
The MSS bit selects master or slave operation in simple SPI mode. The functions of the TXDn and RXDn pins are
reversed when this bit is set to 1, so that data is received through the TXDn pin and transmitted through the RXDn pin.
Set this bit to 0 in modes other than simple SPI mode.
MFF flag (Mode Fault Flag)
The MFF flag indicates mode fault errors. In a multi-master configuration, determine the mode fault error occurrence by
reading this flag.
[Setting condition]
Input on the SSn pin is at the low level during master operation in Simple SPI mode (SSE bit = 1 and MSS bit = 0).
[Clearing condition]
Writing 0 to the bit after it is read as 1.
CKPOL bit (Clock Polarity Select)
The CKPOL bit selects the polarity of the clock signal output through the SCKn pin. See Figure 25.70 for details.
Set the bit to 0 in other than simple SPI mode and clock synchronous mode.
CKPH bit (Clock Phase Select)
The CKPH bit selects the phase of the clock signal output through the SCKn pin. See Figure 25.70 for details.
Set the bit to 0 in other than simple SPI mode and clock synchronous mode.
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25.2.26
25. Serial Communications Interface (SCI)
FIFO Control Register (FCR)
Address(es): SCI0.FCR 4007 0014h
b15
b14
b13
b12
b11
RSTRG[3:0]
Value after reset:
1
1
1
b10
b9
b8
b7
RTRG[3:0]
1
1
0
0
b6
b5
b4
TTRG[3:0]
0
0
0
0
b3
b2
b1
DRES TFRST RFRST
0
0
0
0
b0
FM
0
Bit
Symbol
Bit name
Description
R/W
b0
FM
FIFO Mode Select
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode:
0: Non-FIFO mode.
Selects TDR/RDR or TDRHL/RDRHL for communication.
1: FIFO mode.
Selects FTDRHL/FRDRHL for communication.
R/W*1
b1
RFRST
Receive FIFO Data Register
Reset
Valid only in FCR.FM = 1:
0: Do not reset FRDRHL
1: Reset FRDRHL.
R/W
b2
TFRST
Transmit FIFO Data
Register Reset
Valid only in FCR.FM = 1:
0: Do not reset FTDRHL
1: Reset FTDRHL.
R/W
b3
DRES
Receive Data Ready Error
Select Bit
When detecting a receive data ready, the interrupt request is
selected:
0: Receive data full interrupt (SCIn_RXI)
1: Receive error interrupt (SCIn_ERI).
R/W
b7 to b4
TTRG[3:0]
Transmit FIFO Data Trigger
Number
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode:
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
b11 to b8
RTRG[3:0]
Receive FIFO Data Trigger
Number
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
b15 to b12
RSTRG[3:0]
RTS Output Active Trigger
Number Select
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode, while FCR.FM = 1, SPMR.CTSE = 0,
and SPMR.SSE = 0:
0000: Trigger number 0
:
1111: Trigger number 15.
R/W
Note 1. Writable only when TE = 0 and RE = 0.
FCR selects FIFO mode, reset FTDRHL/FRDRHL, selects the FIFO data trigger number for transmission or reception,
and selects the RTS output active trigger number.
FM bit (FIFO Mode Select)
When the FM bit is set to 1, FTDRHL and FRDRHL are selected for communication. When the FM bit is set to 0, TDR
and RDR or TDRHL and RDRHL are selected for communication.
RFRST bit (Receive FIFO Data Register Reset)
The FRDRHL register is reset when the RFRST bit is set to 1, and the number of receive data is reset to 0.
After writing 1, this bit is set to 0 after 1 PCLKB.
TFRST bit (Transmit FIFO Data Register Reset)
The FTDRHL register is reset when the TFRST bit is set to 1, and the transmit data count is reset to 0. After writing 1,
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25. Serial Communications Interface (SCI)
this bit is set to 0 after 1 PCLKB.
DRES bit (Receive Data Ready Error Select Bit)
On detecting a receive data ready error, the DRES bit selects the interrupt request from an SCIn_RXI interrupt request or
an SCIn_ERI interrupt request. Set the DRES bit to 1 when starting the DTC and reading the FRDRH and FRDRL
registers.
TTRG[3:0] bits (Transmit FIFO Data Trigger Number)
The TDFE flag is set to 1 when the amount of transmit data in the Transmit FIFO Data Register (FTDRHL) is equal to or
less than the specified transmit triggering number, and software can write data to FTDRHL. If SCR.TIE = 1, SCIn_TXI
interrupt request occurred.
RTRG[3:0] bits (Receive FIFO Data Trigger Number)
The RDF flag is set to 1 when the amount of receive data in the Receive FIFO Data Register (FRDRHL) is equal to or
greater than the specified receive triggering number, and software can read data from FRDRHL. If SCR.RIE = 1,
SCIn_RXI interrupt request occurred. When RSTRG is set to 0, the RDF flag is not set even when the amount of the data
in the receive FIFO is equal to 0. Additionally, an SCIn_RXI interrupt does not occur.
RSTRG[3:0] bits (RTS Output Active Trigger Number Select)
When the amount of receive data stored in the Receive FIFO Data Register (FRDRHL) is equal to or greater than the
specified receive triggering number, the RTS signal goes high. When RSTRG is set to 0, the RTS signal does not go high
even when the amount of data in the receive FIFO is equal to 0.
25.2.27
FIFO Data Count Register (FDR)
Address(es): SCI0.FDR 4007 0016h
Value after reset:
b15
b14
b13
—
—
—
0
0
0
b12
b11
b10
b9
b8
T[4:0]
0
0
0
0
0
b7
b6
b5
—
—
—
0
0
0
b4
b3
b2
b1
b0
0
0
R[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
R[4:0]
Receive FIFO Data Count
Valid only in asynchronous mode, including multi-processor, or clock
synchronous mode, when FCR.FM = 1.
Indicate the amount of receive data stored in FRDRHL.
R
b7 to b5
—
Reserved
These bits are read as 0.
R
b12 to b8
T[4:0]
Transmit FIFO Data Count
Valid only in asynchronous mode, including multi-processor, or clock
synchronous mode, when FCR.FM = 1.
Indicate the amount of non-transmit data stored in FTDRHL.
R
Reserved
These bits are read as 0.
R
b15 to b13 —
The FDR register indicates the amount of data stored in FRDRHL/FTDRHL.
R[4:0] bits (Receive FIFO Data Count)
The R[4:0] bits indicate the amount of receive data stored in FRDRHL. 00h means no receive data, and 10h means that
the maximum received data is stored in FRDRHL.
T[4:0] bits (Transmit FIFO Data Count)
The T[4:0] bits indicate the amount of non-transmitted data stored in FTDRHL. 00h means no transmit data, and 10h
means that all (maximum count) of the data to be transmitted is stored in FTDRHL.
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25. Serial Communications Interface (SCI)
Line Status Register (LSR)
Address(es): SCI0.LSR 4007 0018h
b15
b14
b13
—
—
—
0
0
0
Value after reset:
b12
b11
b10
b9
b8
PNUM[4:0]
0
0
0
b7
b6
b5
—
0
0
0
b4
b3
b2
FNUM[4:0]
0
0
0
0
0
b1
b0
—
ORER
0
0
Bit
Symbol
Bit name
Description
R/W
b0
ORER
Overrun Error Flag
Valid only in asynchronous mode, including multi-processor, or
clock synchronous mode, and when FIFO is selected:
0: No overrun error occurred
1: An overrun error has occurred.
R*1
b1
—
Reserved
This bit is read as 0.
R
b6 to b2
FNUM[4:0]
Framing Error Count
Indicates the amount of data with a framing error in the receive data
stored in the Receive FIFO Data Register (FRDRHL).
R
b7
—
Reserved
This bit is read as 0.
R
b12 to b8
PNUM[4:0]
Parity Error Count
Indicates the amount of data with a parity error among the receive
data stored in the Receive FIFO Data Register (FRDRHL).
R
b15 to b13
—
Reserved
These bits are read as 0.
R
Note 1. If this flag is 1, the read of SSR_FIFO register is not complete. Write 0 to SSR_FIFO.ORER to clear the flag.
The LSR register indicates the status of receive error.
ORER bit (Overrun Error Flag)
The ORER bit reflects the value in SSR_FIFO.ORER.
FNUM[4:0] bits (Framing Error Count)
The FNUM[4:0] value indicates the amount of data stored in the FRDRHL register with a framing error.
PNUM[4:0] bits (Parity Error Count)
The PNUM[4:0] value indicates the amount of data stored in the FRDRHL register with a parity error.
25.2.29
Compare Match Data Register (CDR)
Address(es): SCI0.CDR 4007 001Ah, SCI1.CDR 4007 003Ah, SCI9.CDR 4007 013Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
—
—
—
—
—
—
—
0
0
0
0
0
0
0
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
CMPD[8:0]
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b8 to b0
CMPD[8:0]
Compare Match Data
Compare data pattern for address match wakeup function.
R/W
b15 to b9
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The CDR register sets the address match function.
CMPD[8:0] bits (Compare Match Data)
The CMPD[8:0] bits set the data to be compared to receive data for the address match function, when address match
function is enabled (DCCR.DCME = 1).
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Three bit lengths are available:
MPD[6:0] with 7-bit length
CMPD[7:0] with 8-bit length
CMPD[8:0] with 9-bit length.
25.2.30
Data Compare Match Control Register (DCCR)
Address(es): SCI0.DCCR 4007 0013h, SCI1.DCCR 4007 0033h, SCI9.DCCR 4007 0133h
b7
b6
DCME IDSEL
Value after reset:
0
1
b5
b4
b3
b2
b1
b0
—
DFER
DPER
—
—
DCMF
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
DCMF
Data Compare Match Flag
0: Not matched
1: Matched.
R/(W)*1
b2, b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
DPER
Data Compare Match Parity
Error Flag
0: No parity error occurred
1: A parity error has occurred.
R/(W)*1
b4
DFER
Data Compare Match
Framing Error Flag
0: No framing error occurred
1: A framing error has occurred.
R/(W)*1
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
IDSEL
ID Frame Select
Valid only in asynchronous mode, including multi-processor:
0: Always compare data regardless of the MPB bit value
1: Compare data when the MPB bit = 1 (ID frame).
R/W
b7
DCME
Data Compare Match
Enable
Valid only in asynchronous mode, including multi-processor:
0: Address match function is disabled
1: Address match function is enabled.
R/W
Note 1. Only 0 can be written to this bit to clear the flag after reading 1.
The DCCR register controls the address match function.
DCMF flag (Data Compare Match Flag)
The DCMF flag indicates that the SCI detected a receive data match with the comparison data (CDR.CMPD).
[Setting condition]
On match of the comparison data (CDR.CMPD) with the receive data when DCCR.DCME = 1.
[Clearing condition]
When 0 is written after 1 is read from DCMF.
Clearing the RE bit to 0 in the Serial Control Register (SCR) does not affect the DCMF flag, which retains its previous
state.
DPER flag (Data Compare Match Parity Error Flag)
The DPER flag indicates that a parity error occurred on address match detection (receive data match detection).
[Setting condition]
When a parity error is detected in the frame where an address match is detected.
[Clearing conditions]
When 0 is written after 1 is read from DPER.
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25. Serial Communications Interface (SCI)
When the RE bit in SCR is set to 0 (serial reception is disabled), the DPER flag is not affected and retains its
previous value.
DFER flag (Data Compare Match Framing Error Flag)
The DFER flag indicates that a framing error occurs on address match detection (reception data match detection).
[Setting conditions]
When a stop bit of the frame in which an address match is detected is 0.
When in 2-stop mode, only the first bit of the stop bits is checked for a value of 1 (the second bit is not checked).
[Clearing conditions]
When 0 is written after 1 is read from DFER.
When the RE bit in SCR is set to 0 (serial reception is disabled), the DFER flag is not affected and retains its
previous value.
IDSEL bit (ID Frame Select)
The IDSEL bit selects whether to compare data regardless of the MPB bit value or to compare data only when MPB = 1
(ID frame), when the address match function is enabled.
DCME bit (Data Compare Match Enable)
The DCME bit selects whether the address match function (data compare match function) is used or not.
If the SCI detects a match to the comparison data (CDR.CMPD) with the receive data, DCME clears automatically, after
which, SCI operation mode is in receive mode without data compare match function. See section 25.3.6, Address Match
(receive data match detection) Function.
The write value should be 0 for any mode other than asynchronous mode.
25.2.31
Serial Port Register (SPTR)
Address(es): SCI0.SPTR 4007 001Ch, SCI1.SPTR 4007 003Ch, SCI9.SPTR 4007 013Ch
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SPB2I SPB2D RXDM
O
T
ON
0
1
1
Bit
Symbol
Bit name
Description
R/W
b0
RXDMON
Serial Input Data Monitor
The state of the RXDn pin:
0: RXDn pin is low
1: RXDn pin is high.
R
b1
SPB2DT
Serial Port Break Data
Select
The output level of TXDn pin is selected when SCR.TE = 0:
0: Output low on TXDn pin
1: Output high on TXDn pin.
R/W
b2
SPB2IO
Serial Port Break I/O
Selects whether the value of SPB2DT is output to TXDn pin:
0: Do not output value of SPB2DT bit on TXDn pin
1: Output value of SPB2DT bit on TXDn pin.
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
The SPTR register provides confirmation of the serial reception pin (RXDn pin) status and sets transmission pin (TXDn
pin) status.
This register can only be used in asynchronous mode.
The TXDn pin status is determined by the combination of SCR.TE, SPTR.SPB2IO, and SPTR.SPB2DT settings, as
shown in Table 25.22.
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Table 25.22
25. Serial Communications Interface (SCI)
TXDn pin status
Value of
SPTR.SPB2IO
Value of SCR.TE
Value of
SPTR.SPB2DT
TXDn pin status
0
0
x
Hi-Z (initial value)
0
1
0
Low level output
0
1
1
High level output
1
x
x
Serial transmit data is output
x: Don’t care.
Note:
Use the SPTR register in asynchronous mode only. Using this register in any other mode is not guaranteed.
25.3
Operation in Asynchronous Mode
Figure 25.2 shows the general format for asynchronous serial communications. One frame consists of a start bit (low
level), transmit or receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the
communications line is held in the mark state (high level) when not communicating.
The SCI monitors the communications line. When the SCI detects a low, it regards that as a start bit and starts serial
communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communications. Both the
transmitter and receiver have a double-buffered structure in addition to FIFO mode, so that data can be read or written
during transmission or reception, enabling continuous data transmission and reception.
Idle state
(mark state)
1
LSB
0
Serial data
1
MSB
D0
D1
D2
D3
D4
D5
D6
D7
Transmit/receive data
Start bit
7, 8 or 9 bits
1 bit
0/1
1
1
Parity bit
Stop bit
1 or 0 bit
1 or 2 bits
One unit of transfer data (character or frame)
Figure 25.2
25.3.1
Data format in asynchronous serial communications with 8-bit data, parity bit, and 2 stop bits
Serial Data Transfer Format
Table 25.23 lists the serial data transfer formats that can be used in asynchronous mode. Any of the 18 transfer formats
can be selected with the SMR and SCMR settings. For details on the multi-processor function, see section 25.4, MultiProcessor Communication Function.
Table 25.23
SCMR
setting
Serial transfer formats (asynchronous mode) (1 of 3)
SMR setting
Serial transfer format and frame length
CHR1
CHR
PE
MP
STOP
0
0
0
0
0
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2
3
S
9-bit data
4
5
6
7
8
9
10
11
12
13
STO
P
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Table 25.23
25. Serial Communications Interface (SCI)
Serial transfer formats (asynchronous mode) (2 of 3)
SCMR
setting
SMR setting
CHR1
CHR
PE
MP
STOP
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
—
Serial transfer format and frame length
0
0
0
0
0
0
0
0
0
0
1
1
2
S
3
4
5
6
7
8
9
10
11
12
9-bit data
STO
P
STO
P
S
9-bit data
P
STO
P
S
9-bit data
P
STO
P
S
8-bit data
STO
P
S
8-bit data
STO
P
STO
P
S
8-bit data
P
STO
P
S
8-bit data
P
STO
P
S
7-bit data
STO
P
S
7-bit data
STO
P
STO
P
S
7-bit data
P
STO
P
S
7-bit data
P
STO
P
S
9-bit data
13
0
1
STO
P
0
1
0
1
STO
P
0
1
0
1
STO
P
0
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Table 25.23
25. Serial Communications Interface (SCI)
Serial transfer formats (asynchronous mode) (3 of 3)
SCMR
setting
SMR setting
CHR1
CHR
PE
MP
STOP
0
0
—
1
1
1
0
1
0
1
1
1
1
—
—
—
—
Serial transfer format and frame length
1
1
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
S
9-bit data
MPB
STO
P
STO
P
S
8-bit data
MPB
STO
P
S
8-bit data
MPB
STO
P
S
7-bit data
MPB
STO
P
S
7-bit data
MPB
STO
P
0
1
STO
P
0
1
STO
P
S:
STOP:
P:
MPB:
Start bit
Stop bit
Parity bit
Multi-processor bit
25.3.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times*1 the bit rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Because receive data is sampled on the rising edge of the 8th pulse*1 of the base clock, data is latched at the middle of
each bit, as shown in Figure 25.3. The reception margin in asynchronous mode is determined by the following formula
(1):
M=
(0.5 -
1
) - (L - 0.5) F 2N
D - 0.5
N
(1 + F)
× 100 [%] ... Formula (1)
M: Reception margin
N: Ratio of bit rate to clock
N = 16 when ABCSE in SEMR = 0 and ABCS in SEMR = 0
N = 8 when ABCS in SEMR = 1, N = 6 when ABCSE in SEMR = 1
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 13)
F: Absolute value of clock frequency deviation
Assuming the values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the following formula:
M = {0.5 - 1/(2 × 16)} × 100 (%) = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
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Note 1. In this example, the ABCS bit in SEMR is 0 and ABCSE bit in SEMR is 0. When the ABCS bit is 1, and the
ABCSE bit is 0, a frequency of 8 times the bit rate is used as a base clock, and receive data is sampled on the
rising edge of the 4th pulse of the base clock.
When the ABCSE bit is 1, a sextuple frequency of a bit rate is used as a base clock, and receive data is sampled
on the rising edge of the 3rd pulse of the base clock.
16 clock pulses
8 clock pulses
0
7
15 0
7
15 0
Internal base clock
Receive data (RXDn)
D0
Start bit
D1
Synchronization
sampling timing
Data sampling
timing
Figure 25.3
25.3.3
Receive data sampling timing in asynchronous mode
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be
selected as the transfer clock of the SCI based on the CM setting in SMR and the CKE[1:0] setting in SCR.
When an external clock is input to the SCKn pin, the clock frequency must be 16 times the bit rate when ABCS in SEMR
= 0 or 8 times the bit rate when ABCS in SEMR = 1.
When the SCI uses its internal clock, the clock can be output from the SCKn pin. The frequency of the clock output in
this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data,
as Figure 25.4 shows.
SCKn
TXDn
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 25.4
Phase relationship between output clock and transmit data in asynchronous mode when
SMR.CHR = 0, PE = 1, MP = 0, and STOP = 1
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25.3.4
25. Serial Communications Interface (SCI)
Double-Speed Operation and Frequency of 6 Times the Bit Rate
When the Asynchronous Mode Base Clock Select (ABCS) bit in SEMR is set to 1 and eight pulses of the base clock for
a 1-bit period is selected, the SCI operates on the bit rate twice that when ABCS is set to 0. When the Baud Rate
Generator Double-speed Mode (BGDM) bit in SEMR is set to 1, the cycle of the base clock is half and the bit rate is
double that when BGDM is set to 0. When the CKE[1] bit in SCR is set to 0 and the on-chip baud rate generator is
selected, setting the ABCS and BGDM bits to 1 allows the SCI to operate at a bit rate four times that when the ABCS and
BGDM bits are set to 0. When the ABCSE bit in SEMR is set to 1, the number of basic clock pulses are 6 during a period
of 1 bit, and SCI operates at a bit rate 16/3 times that when SEMR.ABCS = 0, SEMR.BGDM = 0 and SMER.ABCSE =
0.
As shown by Formula (1) in section 25.3.2, Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode, the reception margin decreases when the ABCS bit or ABCSE bit in SEMR is set to 1. Therefore, if the target bit
rate can be obtained with ABCS or ABCSE set to 0, it is recommended that you use the SCI with ABCSE and ABCS set
to 0.
25.3.5
CTS and RTS Functions
The CTS function uses input on the CTSn_RTSn pin in transmission control. Setting the SPMR.CTSE bit to 1 enables
the CTS function. When the CTS function is enabled, driving the CTSn_RTSn pin low causes transmission to start.
Driving the CTSn_RTSn pin high while transmission is in progress does not affect transmission of the current frame.
In the RTS function that uses output on the CTSn_RTSn pin, a low level is output when reception becomes possible.
Conditions for output low level and high level are shown in this section.
[Conditions for low-level output]
(a)
Non-FIFO selected when all of the following conditions are satisfied
The value of the RE bit in the SCR is 1
Reception is not in progress
There is no receive data yet to be read
The ORER, FER, and PER flags in the SSR are all 0.
(b)
FIFO selected when all of the following conditions are satisfied
The value of the RE bit in the SCR is 1
When the amount of receive data written in FRDRHL is equal to or less than the specified receive triggering number
The ORER in the SSR_FIFO (ORER in the FRDRH) is 0.
[Conditions for high-level output]
(a)
Non-FIFO selected when all of the following conditions are satisfied
The conditions for low-level output are not satisfied
After reception is complete, if it is terminated with SCR.RE = 0 without reading the RDR register, then RTS
remains high. Read the SCR register for dummy after writing SCR.RE = 0.
(b)
FIFO selected when all of the following conditions are satisfied
The conditions for low-level output are not satisfied.
25.3.6
Address Match (receive data match detection) Function
The address match function can be used only in asynchronous mode.
If the DCCR.DCME is set to 1*4, when one frame of data is received, SCI compares that received data with the data set
in CDR.CMPD. If SCI detects a match to the comparison data (CDR.CMPD*3) with the received data, SCI can issue the
SCIn_RXI interrupt request.
If the SMR.MP bit is set to 0, comparison occurs only for valid data in receive format. In multi-processor mode
(SMR.MP bit = 1), if DCCR.IDSEL bit is set to 1, receive data where the MPB bit is 1 is subject to comparison for
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25. Serial Communications Interface (SCI)
address match. Receive data where the MPB bit is 0 is always treated as a mismatch.
If DCCR.IDSEL bit is set to 0, the SCI performs address match or mismatch regardless the value of the MPB bit of the
received data.
Until SCI detects a match to the comparison data (CDR.CMPD*3) with receive data, received data is skipped
(discarded), and the SCI cannot detect parity error or framing error.
When SCI detects the match, DCCR.DCME is automatically cleared, and DCCR.DCMF is set to 1.
If DCCR.IDSEL is set to 1, SCR.MPIE bit is automatically cleared. If DCCR.IDSEL is set to 0, the value of SCR.MPIE
bit is retained. If SCR.RIE is set to 1, the SCI issues an SCIn_RXI interrupt request. If the SCI detects a framing error in
the receive data for which a match is detected, DCCR.DFER is set to 1, and if the SCI detects a parity error in that frame,
DCCR.DPER is set to 1. The compared receive data is not stored in the RDR register*1, and SSR.RDRF remains 0.*2
After SCI detects a match, and DCCR.DCME is automatically cleared, it receives the next data continuously based on
the current register setting.
When the DCCR.DFER or DCCR.DPER flag is set, the address match is not performed. Before enabling the address
match function, set DCCR.DFER and DCCR.DPER flags to 0.
An example of the address match function is shown in Figure 25.5 and Figure 25.6.
Note 1. When FCR.FM = 1, this refers to the FRDRHL register.
Note 2. When FCR.FM = 1, this refers to the SSR_FIFO.RDF flag.
Note 3. This comparative target can select one length of 3 types: CMPD[6:0] with 7-bit length, CMPD[7:0] with 8-bit
length, and CMPD[8:0] with 9-bit length.
Note 4. Set the DCCR.DCME bit to 1 before receiving the start bit of the received frame that performs address matching.
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Data (ID1)
1
Data (Data1)
Start bit
0
Stop bit Start bit
D0
D1
D7
Parity
1
0
D0
D1
D7
Parity
SCIn_AM
SCI0_DCUF
DCME
DCMF flag
SCIn_RXI interrupt flag
(ICU.IELSRn.IR)
RDRF flag
DPER flag
DFER flag
RDR
If compare is
mismatched,
the flag is not set
Not stored to RDR, if CDR
setting value is
mismatched to receive
data
(a) Example of compare mismatched between receive data and CDR (8-bit length/parity/non multi-processor mode)
Data (ID2)
1
Data (Data2)
Start bit
0
Stop bit Start bit
D0
D1
D7
Parity
1
0
Stop bit Start bit
D0
D1
D7
Parity
1
0
SCIn_AM
SCI0_DCUF
DCME
DCMF flag
MPIE
Clear the Flag
SCIn_RXI interrupt flag
(ICU.IELSRn.IR)
RDRF flag
DFER flag
RDR
Data2
DCME = 0
If error occurs,
flag is set
Not stored to RDR, if CDR
setting value matched to
receive data
Non-address
match receive,
and
set to the flag
Stored
receive data
(b) Example of compare matched between receive data and CDR (8-bit length/parity/non multi-processor mode)
Figure 25.5
Example of address match (1) non multi-processor mode
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25. Serial Communications Interface (SCI)
Data (Data0)
1
Start bit
0
Data (ID1)
MPB
D0
D1
D7
0
Stop bit Start bit
1
0
MPB Stop bit Start bit
D0
D1
D7
1
1
SCIn_AM
SCI0_DCUF
DCME
DCMF flag
SCIn_RXI interrupt flag
(ICU.IELSRn.IR)
RDRF flag
DPER flag
DFER flag
RDR
The data by which MPB is 0
detects mismatched in SCI
If compare mismatched,
the flag is not set
Not stored to RDR, if CDR
setting value is
mismatched to receive
data
(a) Example of compare mismatched between receive data and CDR (8-bit length/IDSEL = 1/Multi-processor mode)
Data (ID2)
1
Start bit
0
Data (Data2)
MPB Stop bit Start bit
D0
D1
D7
1
1
0
Stop bit Start bit
D0
D1
D7
MPB
1
0
SCIn_AM
SCI0_DCUF
DCME
DCMF flag
MPIE
Clear the Flag
SCIn_RXI interrupt flag
(ICU.IELSRn.IR)
RDRF flag
DFER flag
RDR
Data2
DCME = 0
If error occurs,
the flag is set
Not stored to RDR, if CDR
setting value matched to
receive data
Non-address
match and non
multiprocessor, and
set to the flag
Stored
receive data
(b) Example of compare matched between receive data and CDR (8-bit length/IDSEL = 1/Multi-processor mode)
Figure 25.6
25.3.7
Example of address match (2) multi-processor mode
SCI Initialization in Asynchronous Mode
Before transmitting and receiving data, start by writing the initial value 00h to SCR and then continue through the SCI
procedure (select non-FIFO or FIFO) shown in Figure 25.7 and Figure 25.8. Whenever the operating mode or transfer
format is to be changed, SCR must be initialized before the change is made.
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25. Serial Communications Interface (SCI)
When the external clock is used in asynchronous mode, ensure that the clock signal is supplied during initialization.
Note:
Note:
Setting the SCR.RE bit to 0 initializes neither the ORER, FER, RDRF, RDF, PER, and DR flags in SSR/
SSR_FIFO nor RDR and RDRHL. When the TE bit is set to 0, the TEND flag for the selected FIFO buffer is not
initialized.
Switching the value of the SCR.TE bit from 1 to 0 or 0 to 1 while the SCR.TIE bit is 1 leads to the generation of an
SCIn_TXI interrupt request.
Start initialization
[1]
Set the FCR.FM bit to 0.
Set the SCR.TIE, RIE, TE, RE, and
TEIE bits to 0
[2]
Set the clock selection in SCR.
When the clock output is selected in asynchronous mode,
the clock is output immediately after SCR settings are made.
[3]
Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits to 0.
Step [3] can be skipped if the values have not changed from
the initial values.
[4]
Set data transmission/reception format in SMR, SCMR, and
SEMR.
[5]
Write a value corresponding to the bit rate to BRR.
This step is not necessary if an external clock is used.
[6]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not necessary if the BRME bit in SEMR
is set to 0 or an external clock is used.
Set the FCR.FM bit to 0
[1]
Set the SCR.CKE[1:0] bits
[2]
Set the SIMR1.IICM bit to 0
Set the SPMR.CKPH and CKPOL bits to 0
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[3]
[4]
Set a value in BRR
[5]
Set a value in MDDR
[6]
[7]
Make I/O port settings to enable input and output functions
as required for TXDn, RXDn, and SCKn pins.
Set the I/O port functions
[7]
[8]
Set the SCR.TE or RE bit to 1, and
set the SCR.TIE and RIE bits
[8]
Set the SCR.TE or RE bit to 1. Also set the SCR.TIE and
RIE bits.
Setting the TE and RE bits allows TXDn and RXDn to be
used.
Initialization completion
Figure 25.7
Example flow of SCI initialization in asynchronous mode with non-FIFO selected
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25. Serial Communications Interface (SCI)
Start initialization
[1]
Set the FCR.FM, TFRST, and RFRST bits to 1.
This is for setting to be empty in FIFO.
Set the FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0] bits.
[2]
Set the clock selection in SCR.
When the clock output is selected in asynchronous mode,
the clock is output immediately after SCR settings are made.
[3]
Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits to 0.
Step [3] can be skipped if the values have not changed from
the initial values.
Set the SCR.TIE, RIE, TE, RE, and
TEIE bits to 0
Set the FCR.FM, TFRST, and RFRST bits to 1
Set the FCR.TTRG[3:0], RTRG[3:0], and
RSTRG[3:0] bits
[1]
Set the SCR.CKE[1:0] bits
[2]
Set the SIMR1.IICM bit to 0
Set the SPMR.CKPH and CKPOL bits to 0
[3]
[4]
Set data transmission/reception format in SMR, SCMR, and
SEMR.
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[4]
[5]
Write a value corresponding to the bit rate to BRR.
This step is not necessary if an external clock is used.
Set a value in BRR
[5]
[6]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not necessary if the BRME bit in SEMR
is set to 0 or an external clock is used.
Set a value in MDDR
[6]
[7]
Set the FCR.TFRST and RFRST bits to 0.
[8]
Set the FCR.TFRST and RFRST bits to 0
[7]
Make I/O port settings to enable input and output functions
as required for TXDn, RXDn, and SCKn pins.
Set the I/O port functions
[8]
[9]
Set the SCR.TE or RE bit to 1, and
set the SCR.TIE and RIE bits
Set the SCR.TE or RE bit to 1. Also set the SCR.TIE and
RIE bits.
Setting the TE and RE bits allow TXDn and RXDn to be
used.
[9]
Initialization completion
Figure 25.8
25.3.8
(1)
Example flow of SCI initialization in asynchronous mode with FIFO selected
Serial Data Transmission in Asynchronous mode
Non-FIFO selected
Figure 25.9, Figure 25.10, and Figure 25.11 show examples of serial transmission in asynchronous mode.
In serial transmission, the SCI operates as described in this section. When the SCR.TE bit is set to 1, the high level for
one frame (preamble) is output to TXD.
1. The SCI transfers data from TDR*1 to TSR when data is written to TDR*1 in the SCIn_TXI interrupt handling
routine.
The SCIn_TXI interrupt request at the beginning of transmission is generated when the SCR.TE and SCR.TIE bits
are set to 1 simultaneously by a single instruction.
2. Transmission starts after the SPMR.CTSE bit is set to 0 (CTS function is disabled) or a low level on the
CTSn_RTSn pin causes data transfer from TDR*1 to TSR. If the TIE bit in SCR is 1, an SCIn_TXI interrupt request
is generated. Continuous transmission is possible by writing the next transmit data to TDR*1 in the SCIn_TXI
interrupt handling routine before transmission of the current transmit data is complete. When SCIn_TEI interrupt
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25. Serial Communications Interface (SCI)
requests are in use, set the SCR.TIE bit to 0 (SCIn_TXI interrupt requests are disabled) and the SCR.TEIE bit to 1
(an SCIn_TEI interrupt request is enabled) after the last of the data to be transmitted is written to the TDR*1 from
the handling routine for SCIn_TXI requests.
3. Data is sent from the TXDn pin in the following order:
Start bit
Transmit data
Parity bit or multi-processor bit (can be omitted depending on the format)
Stop bit.
4. The SCI checks for update of the TDR on output of the stop bit.
5. When TDR is updated, setting the SPMR.CTSE bit to 0 (CTS function is disabled) or a low level input on the
CTSn_RTSn pin causes transfer of the next transmit data from TDR*1 to TSR and transmission of the stop bit, after
which serial transmission of the next frame starts.
6. If TDR is not updated, the TEND flag in SSR is set to 1, the stop bit is sent, and the mark state is entered where 1 is
output. If the TEIE bit in SCR is 1, the TEND flag in SSR is set to 1 and an SCIn_TEI interrupt request is generated.
Note 1. Only write data to the TDRHL register when 9-bit data length is selected.
Figure 25.9, Figure 25.10, and Figure 25.11 show a sample flowchart for serial transmission in asynchronous mode.
Start bit
1
0
SCR.TE bit
Data
D0 D1
Parity bit Stop bit
D7 0/1 1
0
D0
D1
D7 0/1
1
0
1 frame
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Note 1.
Figure 25.9
Data written to TDR in
SCIn_TXI interrupt
handling routine
SCIn_TXI interrupt Data written to TDR in
request generated SCIn_TXI interrupt
handling routine
Data written to TDR in
SCIn_TXI interrupt
handling routine
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example operation for serial transmission in asynchronous mode (1) with 8-bit data, parity bit, 1
stop bit, CTS function not used, and at the beginning of transmission
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25. Serial Communications Interface (SCI)
CTSn_RTSn pin
Data
Start bit
1
0 D0 D1
SCR.TE bit
Parity bit
Stop bit
D7 0/1 1
0 D0 D1
D7 0/1 1
Idle state
(mark state)
0
1 frame
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Note 1.
Figure 25.10
Data written to TDR in
Data written to TDR
SCIn_TXI interrupt
in SCIn_TXI interrupt
handling routine
handling routine
SCIn_TXI interrupt
request generated
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example operation for serial transmission in asynchronous mode (2) with 8-bit data, parity bit, 1
stop bit, CTS function used, and at the beginning of transmission
Start bit
1
SCR.TE bit
Data
0 D0 D1
Parity bit
Stop bit
D7 0/1 1
1
Data written to TDR in
SCIn_TXI interrupt
handling routine
1 frame
Note 1.
D7 0/1 1
0 D0 D1
D7 0/1 1
Idle state
(mark state)
(TIE = 0)
SSR.TEND flag
SCIn_TXI interrupt
request generated
0 D0 D1
(TIE = 1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Figure 25.11
Data written to TDR in
SCIn_TXI interrupt handling
routine
Data written to TDR in SCIn_TXI
interrupt handling routine
(Set the TIE bit to 0 and the TEIE bit to
1 after writing the last data)
SCIn_TXI interrupt
request generated
SCIn_TEI interrupt
request generated
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example operation for serial transmission in asynchronous mode (3) with 8-bit data, parity bit, 1
stop bit, CTS function not used, and from the middle of transmission until transmission
completion
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25. Serial Communications Interface (SCI)
[1]
SCI Initialization:
Set data transmission.
After the TE bit in SCR is set to 1, 1 is output for a
frame (preamble), and transmission is enabled.
[2]
Transmit data write to TDR by an SCIn_TXI interrupt
request:
When transmit data is transferred from TDR to TSR,
a transmit data empty interrupt (SCIn_TXI) request is
generated.
Write transmit data to TDR once in the SCIn_TXI
interrupt processing routine.
[3]
Serial transmission continuation procedure:
To continue serial transmission write transmit data to
TDR once using an SCIn_TXI interrupt request.
Transmit data can also be written to TDR by
activating the DTC.
When SCIn_TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the
last of the data to be transmitted are written to the
TDR.
[4]
Break output at the end of serial transmission:
To output a break in serial transmission, after setting
the output state (low level output) of TXDn pin by
SPTR.SPB2IO and SPTR.SPB2DT bits, set the
SCR.TE bit to 0.
[1]
Initialization
Start transmission
SCIn_TXI interrupt
No
[2]
Yes
Write transmit data to TDR
All data transmitted?
No
[3]
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
SCIn_TEI interrupt
No
Yes
Break output
No
[4]
Yes
Set TXD port function
Note:
The TDR register becomes the TDRHL register
when 9-bit data length is selected.
Set bits TIE, TE, and TEIE in SCR to 0
End
Figure 25.12
(2)
Example flow of serial transmission in asynchronous mode with non-FIFO selected
FIFO selected
Figure 25.13 shows an example of a data format that is written to FTDRH and FTDRL in asynchronous mode.
Data is set to FTDRH and FTDRL that corresponds to the data length. Write 0 for unused bits. Write in order from
FTDRH to FTDRL.
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Data
Length
25. Serial Communications Interface (SCI)
Transmit data in FTDRH, FTDRL
Register
Setting
FTDRHL
FTDRH
SCMR.
CHR1
SMR.
CHR
b7
7 bits
1
8 bits
1
0
9 bits
FTDRL
b6
b5
b4
b3
b2
b1
b0
0
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
Don’t
care
—
—
—
—
—
—
—
b7
b6
—
b5
b4
b3
b2
b1
b0
7-bit transmit data
8-bit transmit data
9-bit transmit data
—: Invalid. The write value should be 0.
Figure 25.13
Data format written to FTDRH and FTDRL with FIFO selected
In serial transmission, the SCI operates as described in this section. When the TE bit is set to 1, the high level for one
frame (preamble) is output to TXD.
1. The SCI transfers data from FTDRL*1 to TSR when data is written to FTDRL*1 in the SCIn_TXI interrupt handling
routine.
The amount of data that can be written to FTDRL is 16 minus FDR.T[4:0] bytes. The SCIn_TXI interrupt request at
the beginning of transmission is generated when the TE and TIE bits in the SCR are set to 1 simultaneously by a
single instruction.
2. Transmission starts after the CTSE bit in SPMR is set to 0 (CTS function is disabled) and a low level on the
CTSn_RTSn pin causes data transfer from FTDRL*1 to TSR. When the amount of transmit data written in FTDRL
is equal to or less than the specified transmit triggering number, SSR_FIFO.TDFE is set to 1. If the TIE bit in SCR
is 1, an SCIn_TXI interrupt request is generated. Continuous transmission is possible by writing the next transmit
data to FTDRL*1 in the SCIn_TXI interrupt handling routine before transmission of the current transmit data is
complete. When SCIn_TEI interrupt requests are in use, set the SCR.TIE bit to 0 (an SCIn_TXI interrupt request is
disabled) and the SCR.TEIE bit to 1 (an SCIn_TEI interrupt request is enabled) after the last of the data to be
transmitted is written to the FTDRL*1 *2 from the handling routine for SCIn_TXI requests.
3. Data is sent from the TXDn pin in the following order:
a. Start bit
b. Transmit data
c. Parity bit or multi-processor bit (may be omitted depending on the format)
d. Stop bit.
4. The SCI checks whether non-transmitted data remains in FTDRL*3 or not on output of the stop bit.
5. When data is set to FTDRL*3, setting the CTSE bit in SPMR to 0 (CTS function is disabled) or a low-level input on
the CTSn_RTSn pin causes transfer of the next transmit data from FTDRL*1 to TSR and transmission of the stop
bit, after which serial transmission of the next frame starts.
6. If data is not set in FTDRL*3, the TEND flag in SSR_FIFO is set to 1, the stop bit is sent, and the mark state is
entered in which 1 is output. If the TEIE bit in SCR is 1 at this time, the TEND flag in SSR_FIFO is set to 1 and an
SCIn_TEI interrupt request is generated.
Note 1. Write data not to FTDRH and FTDRL but to the FTDRH and FTDRL registers when 9-bit data length is selected.
Note 2. Write data in order from FTDRH to FTDRL when 9-bit data length is selected.
Note 3. The SCI only checks for update to the FTDRL register and not the FTDRH register when 9-bit data length is
selected.
Figure 25.14 shows an example flow of serial transmission in asynchronous mode with FIFO selected.
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25. Serial Communications Interface (SCI)
Initialization
[1]
[1]
SCI initialization:
Set data transmission.
After the TE bit in SCR is set to 1, 1 is output for a frame
(preamble), and transmission is enabled.
[2]
Transmit data write to FTDRL*1 by an SCIn_TXI interrupt
request:
When transmit data is transferred from FTDRL to TSR,
when the amount of transmit data written in FTDRL is
equal to or less than the specified transmit triggering
number, a transmit data FIFO empty interrupt (SCIn_TXI)
request is generated. Write transmit data to FTDRL*1, *2
once in the SCIn_TXI interrupt handling routine.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write all transmit data to
FTDRL using an SCIn_TXI interrupt request and clear
the SSR_FIFO.TDFE flag to 0. The number of
transmission data it is possible to write in is 16 - (the
number of stored transmit FIFO data).
Transmit data can also be written to FTDRL by activating
the DTC. When writing the data to FTDRL by DTC, the
TDFE flag is cleared automatically, so do not write to the
TDFE flag.
When SCIn_TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last
of the data to be transmitted are written to the FTDRL.
[4]
Break output at the end of serial transmission:
To output a break in serial transmission, after setting the
output state (low-level output) of TXDn pin by
SPTR.SPB2IO and SPTR.SPB2DT bits, set the SCR.TE
bit to 0.
Start data transmission
SCIn_TXI interrupt
No
[2]
Yes
Write transmit data to FTDRL*1, *2
All transmit data
written to FTDRL*1, *2 register?
[3]
No
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt
Yes
Break output
No
Yes
[4]
Set TXD port functions
Note 1.
Set bits SCR.TE, TIE, and TEIE to 0
Note 2.
When data length is 9 bits, this refers to FTDRH and
FTDRL registers.
When data length is 9 bits, write in the order from
FTDRH to FTDRL.
End
Figure 25.14
25.3.9
(1)
Example flow of serial transmission in asynchronous mode with FIFO selected
Serial Data Reception in Asynchronous Mode
Non-FIFO selected
Figure 25.15 and Figure 25.16 show an example of the operation for serial data reception in asynchronous mode.
In serial data reception, the SCI operates as follows:
1. When the value of the RE bit in SCR becomes 1, the output signal on the CTSn_RTSn pin goes low.
2. When the SCI monitors the communications line and detects a start bit, it performs internal synchronization, stores
receive data in RSR, and checks the parity bit and stop bit.
3. If an overrun error occurs, the ORER flag in SSR is set to 1. If the RIE bit in SCR is 1, an SCIn_ERI interrupt
request is generated. Receive data is not transferred to RDR*1.
4. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR*1. If the RIE bit in
SCR is 1, an SCIn_ERI interrupt request is generated.
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25. Serial Communications Interface (SCI)
5. If a frame error is detected, the FER bit in the SSR is set to 1 and receive data is transferred to RDR*1. If the RIE bit
in the SCR is 1, an SCIn_ERI interrupt request is generated.
6. When reception finishes successfully, receive data is transferred to RDR*1. If the RIE bit in the SCR is 1, an
SCIn_RXI interrupt request is generated. Continuous reception is enabled by reading the receive data transferred to
RDR in this SCIn_RXI interrupt handling routine before reception of the next receive data is complete. Reading the
received data that is transferred to RDR causes the CTSn_RTSn pin to output low.
Note 1. Only read data in the RDRHL register when 9-bit data length is selected.
1
Data
Start bit
D0
0
D1
Parity Stop
bit
bit
D7
0/1
Data
Start bit
1
0
D0
D1
Parity Stop
bit
bit
D7
0/1
1
Idle state
(mark state)
0
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.FER flag
SCIn_RXI interrupt
request generated
RDR data read in SCIn_RXI
interrupt handling routine
SCIn_ERI interrupt request
generated by framing error
1 frame
Note 1.
Figure 25.15
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI operation for serial reception in asynchronous mode (1) when the RTS function
is not used, and with 8-bit data, parity bit, and 1 stop bit
1
Data
Start bit
0
D0
Parity Stop
bit
bit
D7
0/1
1
Data
Start bit
0
D0
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
Data
Start bit
0
D0
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.FER flag
SCIn_RXI interrupt
request generated
RDR data read in SCIn_RXI
interrupt handling routine
SCIn_ERI interrupt request
generated by framing error
Error flag is cleared
CTSn_RTSn pin
1 frame
Note 1.
Figure 25.16
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI operation for serial reception in asynchronous mode (2) when the RTS function
is used, and with 8-bit data, parity bit, and 1 stop bit
Table 25.24 lists the states of the flags in the SSR status register and receive data handling when a receive error is
detected.
If a receive error is detected, an SCIn_ERI interrupt request is generated but an SCIn_RXI interrupt request is not
generated. Data reception cannot be resumed while the receive error flag is 1. Accordingly, set the ORER, FER, and PER
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25. Serial Communications Interface (SCI)
bits to 0 before resuming reception. In addition, be sure to read the RDR (or the RDRHL) during overrun error
processing. When a reception is forced to terminate by setting the SCR.RE bit to 0 during operation, read the RDR or
RDRHL register because received data that is not read might be left in the RDR or RDRHL.
Figure 25.17 and Figure 25.18 show example flows of serial data reception.
Table 25.24
Flags in SSR Status Register and receive data handling
Flags in the SSR Status Register
ORER
FER
PER
Receive data
Receive error type
1
0
0
Lost
Overrun error
0
1
0
Transferred to RDR
Framing error
0
0
1
Transferred to RDR
Parity error
1
1
0
Lost
Overrun error + framing error
1
0
1
Lost
Overrun error + parity error
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
Lost
Overrun error + framing error + parity error
Note 1. Only read data in the RDRHL register when 9-bit data length is selected.
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25. Serial Communications Interface (SCI)
[1]
Initialization
[1]
Start data reception
Read ORER, PER, and FER flags in SSR
[2]
Yes
SSR.ORER flag = 1,
SSR.PER flag = 1, or
SSR.FER flag = 1
[3]
No
[2] [3] Receive error processing and break detection:
If a receive error occurs, an SCIn_ERI interrupt is
generated. An error is identified by reading the
ORER, PER, and FER flags in SSR. After
performing the appropriate error processing, be
sure to set the ORER, PER, and FER flags to 0.
Reception cannot be resumed if any of these flags
is set to 1. For a framing error, a break can be
detected by reading the value of the input port
corresponding to the RXDn pin.
Error processing
(Continued to next page)
No
SCI initialization:
Set data reception.
SCIn_RXI interrupt
[4]
Read the receive data in RDR once in the
SCIn_RXI interrupt handling routine.
[5]
Serial reception continuation procedure:
To continue serial reception, before the stop bit of
the current frame is received, read data from RDR
in the SCIn_RXI interrupt processing routine. The
RDR data can also be read by activating the DTC.
Yes*1
No
Read receive data in RDR*2
[4]
All data received?
[5]
Yes
Set bits RIE and RE in SCR to 0
Note 1.
Note 2.
Do not set 0 to RE before read RDR here.
The RDR register becomes the RDRHL register when 9-bit
data length is selected.
End
Figure 25.17
Example flow of serial reception in asynchronous mode with non-FIFO selected (1)
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25. Serial Communications Interface (SCI)
[3]
Error processing
No
SSR.ORER flag = 1
Yes
Overrun error processing
No
[6]
[ 6 ] Processing in response to an overrun error:
Read the RDR. In combination with step [ 7 ], this
makes correct reception of the next frame possible.
SSR.FER flag = 1
Yes
Break?
Yes
No
Framing error processing
No
Set RE bit in SCR to 0
SSR.PER flag = 1
Yes
Parity error processing
Set the SSR.ORER, PER,
and FER flags to 0
[7]
[ 7 ] Clearing the error flag:
Write 0 to the error flag.
Read the SSR.ORER, PER, and FER flags
[8]
[ 8 ] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
Note:
End
Figure 25.18
The RDR register becomes the RDRHL register
when 9-bit data length is selected.
Example flow of serial reception in asynchronous mode with non-FIFO selected (2)
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(2)
25. Serial Communications Interface (SCI)
FIFO selected
Figure 25.19 shows an example of a data format that is written to FRDRH and FRDRL in asynchronous mode.
In asynchronous mode, 0 is written to the MPB flag in the FRDRH register. Data that corresponds to the data length is
written to FRDRH and FRDRL. Unused bits are written as 0. Read in order from FRDRH to FRDRL. If software reads
FRDRL, SCI updates FER, PER and receive data (RDAT[8:0]) in the FRDRL register with the next data. The flags RDF,
ORER, and DR in FRDRH always reflect the associated flags in the SSR_FIFO register.
Data
Length
Receive data in FRDRH, FRDRL
Register
Setting
FRDRHL
FRDRH
SCMR.
CHR1
SMR.
CHR
b7
b6
7 bits
1
0
—
RDF
8 bits
1
1
—
0
Don’t
care
—
9 bits
Note:
b5
FRDRL
b4
b3
b2
b1
b0
ORER
FER
PER
DR
0
0
RDF
ORER
FER
PER
DR
0
0
RDF
ORER
FER
PER
DR
0
b7
b6
0
b5
b4
b3
b2
b1
b0
7-bit receive data
8-bit receive data
9-bit receive data
0 is always read for MPB flag (FRDRH[1])
When data length is 7 bits, 0 is always read for FRDRH[0] and FRDRL[7]
When data length is 8 bits, 0 is always read for FRDRH[0]
FRDRH[7] bit is read as an indefinite value.
Figure 25.19
Data format stored to FRDRH and FRDRL with FIFO selected
In serial data reception, the SCI operates as follows:
1. When the value of the RE bit in SCR becomes 1, the output signal on the CTSn_RTSn pin goes low.
2. When the SCI monitors the communications line and detects a start bit, it performs internal synchronization, stores
receive data in RSR, and checks the parity bit and stop bit.
3. If an overrun error occurs, the ORER flag in SSR_FIFO is set to 1. When the RIE bit in SCR is 1, an SCIn_ERI
interrupt request is generated. Receive data is not transferred to FRDRL*1.
4. If a parity error is detected, the PER flag and receive data are transferred to FRDRL*1. When the RIE bit is set to 1,
an SCIn_ERI interrupt request is generated.
5. If a frame error is detected, the FER flag and receive data are transferred to FRDRL*1. When a RIE bit is set to 1, an
SCIn_ERI interrupt request is generated.
6. After a frame error is detected and when SCI detects that the continuous receive data is for one frame, reception
stops.
7. When the amount of data stored in the receive FIFO data register (FRDRL) falls below the specified receive
triggering number, and the next data is not received after 15 ETUs from the last stop bit in asynchronous mode,
SSR_FIFO.DR is set to 1. When the RIE bit is 1 and the FCR.DRES bit is 0, SCI generates an SCIn_RXI interrupt
request. When the FCR.DRES bit is 1, SCI generates an SCIn_ERI interrupt request.
8. When reception finishes successfully, receive data is transferred to FRDRL*1. RDF is set to 1 when the amount of
receive data written to FRDRHL is equal to or greater than the specified receive triggering number. When the RIE
bit in SCR is 1, an SCIn_RXI interrupt request is generated. Continuous reception is enabled by reading the receive
data transferred to FRDRL*2 in this SCIn_RXI interrupt handling routine, before an overrun error occurs. If the
received data that is transferred to FRDRL*3 is less than the RTS trigger number, the CTSn_RTSn pin outputs low.
Note 1. Only read data in the FRDRH and FRDRL registers when 9-bit data length is selected.
Note 2. Read data in the order from FRDRH to FRDRL when 9-bit data length is selected.
Note 3. The SCI only checks for update to the FRDRL register and not to the FRDRH register when 9-bit data length is
selected.
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25. Serial Communications Interface (SCI)
[1]
Initialization
[1]
Start data reception
Read ORER*1, PER, FER, And DR*1
flags in SSR_FIFO
[2]
SSR_FIFO.ORER*1 flag = 1,
SSR_FIFO.PER flag = 1,
SSR_FIFO.FER flag = 1, or
DR*1flag = 1
Yes
[3]
Error processing
No
No
(Continued to next page)
SCIn_RXI interrupt
Yes
[2] [3] Receive error processing and break detection:
If a receive error occurs, an SCIn_ERI interrupt
is generated. A break can be detected by
reading the SPTR.RXDMON bit. An error is
identified by reading the ORER*1, PER, DR*1,
and FER flags in SSR_FIFO. After performing
the appropriate error processing, be sure to set
the ORER*1 flag to 0. Reception cannot be
resumed if ORER*1 flag is set to 1. The
reception operation is continuous, even when
FER = 1 or PER = 1 or DR*1 = 1.
[4]
Read the receive data in FRDRHL in the
SCIn_RXI interrupt handling routine. The
reception data stored in the FRDRHL register is
read until the number of stored data is at least
below the FCR.RTRG value. Confirm the
number of the reception data in the FIFO with
the FDR.R bits.
[5]
No
Read receive data in FRDRHL
[4]
All data received?
[5]
SCI initialization:
Set data reception.
Yes
Serial reception continuation procedure:
To continue serial reception, before an overrun
error occurs, read data from FRDRHL in the
SCIn_RXI interrupt handling routine and clear
RDF flag and DR flag to 0.
The FRDRHL data can also be read by
activating the DTC. The RDF flag is cleared
automatically in this case, so do not write to the
RDF flag.
Set bits RIE and RE in SCR to 0
Note 1.
End
Figure 25.20
Can be read by the FRDRHL.ORER and DR
flags.
Example flow of serial reception in asynchronous mode with FIFO selected (1)
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25. Serial Communications Interface (SCI)
[3]
Error processing
No
SSR_FIFO.ORER flag = 1
Yes
Overrun error processing
No
[6]
[ 6 ] Processing in response to an overrun error:
The FRDRHL register is read and a space is made in the
FRDRHL register.
SSR_FIFO.FER flag = 1
Yes
Yes
Break?
No
Framing error processing
Break flow
[8]
No
[ 7 ] When a break is detected, transfer of the receive data to FRDRHL
stops after the detection. When the break ends at
SEMR.RXDESEL = 0, the last stored data of FRDRHL is break
error frame (All 0 data).
SSR_FIFO.PER flag = 1
Yes
Parity error processing
No
[8]
SSR_FIFO.DR flag = 1
[ 8 ] Framing error processing / parity error processing:
All error occurrence data stored in the FRDRHL
register is read or write 1 to the FCR.RFRST bit and
empty the FRDRHL register.
[ 9 ] The reading of the reception data (when FCR.DRES is 1):
All reception data stored in the FRDRHL register is read.
Yes
Reception data reading in the
FRDRHL register
[9]
Set the SSR_FIFO.ORER, PER, DR, and
FER flags to 0
[10]
[10] Clearing the error flag:
Write 0 to the error flag.
Read the SSR_FIFO.ORER, PER, DR, and
FER flags
[11]
[11] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
End
Figure 25.21
25.4
Example flow of serial reception in asynchronous mode with FIFO selected (2)
Multi-Processor Communication Function
The multi-processor communication function enables the SCI to transmit and receive data between multiple processors
by sharing an asynchronous serial communication line that has an added multi-processor bit. In multi-processor
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25. Serial Communications Interface (SCI)
communication, a unique ID code is allocated to each receiving station. Serial communication cycles consist of an ID
transmission cycle to specify the receiving station and a data transmission cycle to transmit data to the specified
receiving station.
The multi-processor bit is used to distinguish between the ID transmission cycle and the data transmission cycle:
When the multi-processor bit is set to 1, the transmission cycle is the ID transmission cycle
When the multi-processor bit is set to 0, the transmission cycle is the data transmission cycle.
Figure 25.22 shows an example of communication between processors using a multi-processor format. First, a
transmitting station transmits communication data in which the multi-processor bit set to 1 is added to the ID code of the
receiving station. Next, the transmitting station transmits communication data in which the multi-processor bit set to 0 is
added to the transmit data. After receiving communication data with the multi-processor bit set to 1, the receiving station
compares the received ID with the ID of the receiving station itself. If the two match, the receiving station receives
communication data that is subsequently transmitted. If the received ID does not match with the ID of the receiving
station, the receiving station skips the communication data until it receives the data again in which the multi-processor
bit is set to 1.
(1)
Non-FIFO selected
To support this function, the SCI provides the MPIE bit in the SCR. When the MPIE bit is set to 1, the following are
disabled until the reception of data in which the multi-processor bit is set to 1:
Transfer of receive data from the RSR to the RDR (the RDRHL register when 9-bit data length is selected)
Detection of a receive error
Setting of the respective status flags RDRF, ORER and FER in SSR.
On receiving a reception character in which the multi-processor bit is set to 1, the MPBT bit in SSR is set to 1 and the
MPIE bit in SCR is automatically cleared, returning the SCI to a non multi-processor reception operation. During this
time, an SCIn_RXI interrupt is generated if the RIE bit in SCR is set.
When the multi-processor format is specified, the parity bit function is disabled. Apart from this, there is no difference
from operation in non multi-processor asynchronous mode. The clock used for the multi-processor communication is the
same as the clock used in non multi-processor asynchronous mode.
Transmitting
station
Communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
(MPB = 1)
Serial data
01h
AAh
(MPB = 1)
ID transmission cycle =
specification of a receiving station
(MPB = 0)
Data transmission cycle = data
transmission to the receiving
station specified by ID
MPB: Multi-processor bit
Figure 25.22
Example of communication using multi-processor format with transmission of data AAh to
receiving station A
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25. Serial Communications Interface (SCI)
FIFO selected
For data transmission, software must write data to FTDRHL.MPBT that corresponds to transmit data in FTDRHL.TDAT.
For data reception, the multi-processor bit that is part of the receive data is written to FRDRHL.MPB and receive data is
written to FRDRL.
When the MPIE bit is set to 1, the following are disabled until reception of data in which the multi-processor bit is set to
1:
Transfer of receive data from RSR to FRDRHL
Detection of a receive error
Break
Setting of the respective status flags RDF, ORER, and FER in SSR_FIFO.
On receiving an 8-bit character in which the multi-processor bit is set to 1, the MPB bit in FRDRHL is set to 1 and
receive data is written to FRDRHL.RDAT. The MPIE bit in SCR is automatically cleared, therefore returning to non
multi-processor reception operation. During this time, an SCIn_RXI interrupt is generated if the RIE bit in SCR is set.
When the multi-processor format is specified, the parity bit function is disabled. Apart from this, there is no difference
from operation in non multi-processor asynchronous mode and non-FIFO selected.
25.4.1
(1)
Multi-Processor Serial Data Transmission
Non-FIFO selected
Figure 25.23 shows an example flow of multi-processor data transmission. In the ID transmission cycle, the ID must be
transmitted with the MPBT bit in the SSR set to 1. In the data transmission cycle, the data must be transmitted with the
MPBT bit set to 0. The rest of the operations are the same as operations in asynchronous mode.
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25. Serial Communications Interface (SCI)
Initialization
[1]
Start data transmission
SCIn_TXI interrupt
[1]
SCI initialization:
Set data transmission.
After the TE bit in SCR is set to 1, 1 is output for a frame, and
transmission is enabled.
[2]
SCIn_TXI interrupt request:
When transmit data is transferred from TDR to TSR, A
transmit data empty interrupt (SCIn_TXI) request is
generated.
Set the MPBT bit in SSR to 0 or 1, and write transmit data to
TDR once in the SCIn_TXI interrupt processing routine.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write transmit data to TDR
once using an SCIn_TXI interrupt request.
Transmit data can also be written to TDR by activating the
DTC.
When SCIn_TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last of
the data to be transmitted are written to the TDR.
[4]
Break output at the end of serial transmission:
To output a break in serial transmission, after setting the
output state (Low level output) of TXDn pin by
SPTR.SPB2IO and SPTR.SPB2DT bits, set the TE bit in the
SCR to 0.
No
[2]
Yes
Set MPBT bit in SSR
Write transmit data to TDR
All transmit data
written to TDR register?
No
[3]
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt
Yes
Break output
No
[4]
Yes
Set TXD port functions
Set bits SCR.TE, TIE, and TEIE to 0
End
Figure 25.23
(2)
Example flow of multi-processor serial transmission with non-FIFO selected
FIFO selected
Figure 25.24 shows an example of data format that is written to FTDRH and FTDRL in multi-processor mode.
MPBT is set to 1 in FTDRH. Data is set to FTDRH and FTDRL with the correct data length. Write 0 for unused bits.
Write in order from FTDRH to FTDRL.
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25. Serial Communications Interface (SCI)
Transmit data in FTDRH, FTDRL
Register
Setting
FTDRHL
FTDRH
SCMR.
CHR1
SMR.
CHR
7 bits
1
0
—
—
—
—
8 bits
1
1
—
—
—
—
9 bits
0
Don’t
care
—
—
—
—
b7
b6
b5
b4
b3
FTDRL
b2
b1
b0
b7
—
—
MPBT
—
—
—
—
MPBT
—
—
—
MPBT
b6
b5
b4
b3
b2
b1
b0
7-bit transmit data
8-bit transmit data
9-bit transmit data
—: Invalid. The write value should be 0.
Figure 25.24
Data format written to FTDRH and FTDRL in multi-processor mode with FIFO selected
Figure 25.25 shows an example flow of multi-processor data transmission with FIFO selected. In the ID transmission
cycle, the ID must be transmitted with the MPBT bit in FTDRH set to 1. In the data transmission cycle, the data must be
transmitted with the MPBT bit set to 0. The rest of the operations are the same as operations in asynchronous mode with
non-FIFO selected.
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25. Serial Communications Interface (SCI)
Initialization
[1]
Start data transmission
SCIn_TXI interrupt
[1]
SCI initialization:
Set data transmission.
After the TE bit in SCR is set to 1, 1 is output for a frame,
and transmission is enabled.
[2]
Transmit data write to FTDRHL by an SCIn_TXI interrupt
request:
When transmit data is transferred from FTDRHL to TSR,
when the amount of receive data written in FTDRHL is
equal to or less than the specified transmit triggering
number, a transmit data FIFO empty interrupt (SCIn_TXI)
request is generated.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write transmit data and
MPBT to FTDRHL once using an SCIn_TXI interrupt
request.
Transmit data can also be written to FTDRHL by activating
the DTC.
When SCIn_TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last of
the data to be transmitted are written to the FTDRHL.
[4]
Break output at the end of serial transmission:
To output a break in serial transmission, after setting the
output state (Low level output) of TXDn pin by
SPTR.SPB2IO and SPTR.SPB2DT bits, set the TE bit in
the SCR to 0.
No
[2]
Yes
Write transmit data and MPBT
to FTDRHL
All transmit data
written to FTDRHL register?
[3]
No
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt
Yes
Break output
No
[4]
Yes
Set TXD port functions
Set bits SCR.TE, TIE, and TEIE to 0
End
Figure 25.25
25.4.2
(1)
Example flow of serial transmission in multi-processor mode with FIFO selected
Multi-Processor Serial Data Reception
Non-FIFO selected
Figure 25.27 and Figure 25.28 are example flows of multi-processor data reception. When the MPIE bit in SCR is set to
1, reading communication data is skipped until reception of communication data in which the multi-processor bit is set to
1. When communication data in which the multi-processor bit is set to 1 is received, the received data is transferred to
RDR (the RDRHL register when 9-bit data length is selected). During this time, the SCIn_RXI interrupt request is
generated. The rest of the operations are the same as operations in asynchronous mode.
Figure 25.26 shows an example operation for data reception.
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25. Serial Communications Interface (SCI)
Data (ID1)
1
Data (Data1)
Start bit
0
MPB Stop bit Start bit
D0
D1
D7
1
1
0
MPB
D0
D1
D7
0
Stop bit
1
1
Idle state
(mark state)
MPIE
SCIn_RXI interrupt flag
(IELSRn.IR*1)
RDR value
ID1
MPIE = 0
SCIn_RXI interrupt
request (multi-processor
interrupt) generated
RDR data read in
SCIn_RXI interrupt
handling routine
MPIE bit set to 1 again
when the received ID
does not match the ID of
the receiving station itself
SCIn_RXI interrupt
request not generated.
RDR retains the state.
(a) When the received ID does not match the ID of the receiving station itself
Data (ID2)
1
Data (Data2)
Start bit
0
MPB Stop bit Start bit
D0
D1
D7
1
1
0
MPB
D0
D1
D7
0
Stop bit
1
1
Idle state
(mark state)
MPIE
SCIn_RXI interrupt flag
(IELSRn.IR*1)
ID1
RDR value
MPIE = 0
ID2
SCIn_RXI interrupt
request (multi-processor
interrupt) generated
RDR data read in
SCIn_RXI interrupt
handling routine
Since the received ID matches
the ID of the receiving station
itself, reception continued and
data received in SCIn_RXI
interrupt handling routine
Data2
MPIE bit set to 1 again
(b) When the received ID matches the ID of the receiving station itself
Note 1.
Figure 25.26
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of SCI reception with 8-bit data, multi-processor bit, and 1 stop bit
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25. Serial Communications Interface (SCI)
Initialization
[1]
[1]
SCI initialization:
Set data reception.
[2]
ID reception cycle:
Set MPIE bit in SCR to 1 and wait for ID
reception.
[3]
SCI status confirmation and reception and
comparison of ID:
Read data in RDR*1 at the first SCIn_RXI
interrupt and compare it with the ID of the
receiving station itself. If the ID does not
match the ID of the receiving station itself, set
the MPIE bit to 1 again, and wait for another
SCIn_RXI interrupt request.
[4]
Data reception at an SCIn_RXI interrupt:
Read data in RDR*1 once in the SCIn_RXI
interrupt routine.
[5]
Receive error processing and break
detection:
If a receive error occurs, an error is identified
by reading ORER and FER flags in SSR.
After performing the appropriate error
processing be sure to set ORER and FER
flags to 0. Reception cannot resume if any of
these flags is set to 1. For a framing error, a
break can be detected by reading
SPTR.RXDMON bit.
Start data reception
Set MPIE bit in SCR to 1
[2]
Read ORER and FER flags in SSR
FER flag = 1 or ORER flag = 1
Yes
No
No
SCIn_RXI interrupt?
[3]
Yes
Read receive data in RDR
No
ID of receiving station itself?
Yes
Read ORER and FER flags in SSR
FER flag = 1 or ORER flag = 1
Yes
No
No
SCIn_RXI interrupt
[4]
Yes
Read receive data in RDR
No
[5]
All data received?
Error processing
Yes
Set RE and RIE bits in SCR to 0.
End
Figure 25.27
(Continued to next page)
Note 1.
The RDR register becomes the RDRHL register
when 9-bit data length is selected.
Example flow of multi-processor serial reception with non-FIFO selected (1)
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25. Serial Communications Interface (SCI)
[5]
Error processing
No
SSR.ORER flag = 1
Yes
Overrun error processing
No
[6]
[ 6 ] Processing in response to an overrun error:
Read the RDR*1. In combination with step [ 7 ],
this makes correct reception of the next frame
possible.
SSR.FER flag = 1
Yes
Break?
Yes
No
Framing error processing
Set the SSR.ORER, PER,
and FER flags to 0
[7]
[ 7 ] Clearing the error flag:
Write 0 to the error flag.
Read the SSR.ORER, PER, and FER flags
[8]
[ 8 ] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
End
Figure 25.28
(2)
Set RE bit in SCR to 0
Note 1.
The RDR register becomes the RDRHL register
when 9-bit data length is selected.
Example flow of multi-processor serial reception with non-FIFO selected (2)
FIFO selected
Figure 25.29 shows an example of a data format that is written to FRDRH and FRDRL in multi-processor mode.
In multi-processor mode, the MPB value that is a part of the receive data is written to the MPB flag in FRDRH. A value
of 0 is written to the PER flag in FRDRH. Data is written to FRDRH and FRDRL with the correct data length. Unused
bits are written with 0. Read in order from FRDRH to FRDRL. If software reads FRDRL, SCI updates FER, MPB and
receive data (RDAT[8:0]) in FRDRL with the next data. The flags RDF, ORER and DR in FRDRH always reflect the
associated flags in the SSR_FIFO register.
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25. Serial Communications Interface (SCI)
Receive data in FRDRH, FRDRL
Register
Setting
FRDRHL
FRDRH
SCMR.
CHR1
SMR.
CHR
b7
b6
7 bits
1
0
—
RDF
8 bits
1
1
—
0
Don’t
care
—
9 bits
Note:
b5
FRDRL
b4
b3
b2
b1
b0
ORER
FER
0
DR
MPB
0
RDF
ORER
FER
0
DR
MPB
0
RDF
ORER
FER
0
DR
MPB
b7
0
b6
b5
b4
b3
b2
b1
b0
7-bit receive data
8-bit receive data
9-bit receive data
When data length is 7 bits, 0 is always read for FRDRH[0] and FRDRL[7].
When data length is 8 bits, 0 is always read for FRDRH[0].
FRDRH[7] bit is read as an indefinite value.
Figure 25.29
Data format stored to FRDRH and FRDRL in multi-processor mode with FIFO selected
Figure 25.30 shows an example flow of multi-processor data reception with FIFO selected. When the MPIE bit in SCR is
set to 1, reading communication data is skipped until reception of communication data in which the multiprocessor bit is
set to 1. When communication data in which the multi-processor bit is set to 1 is received, the received data, MPB and
associated errors are transferred to FRDRHL. The MPIE bit in SCR is automatically cleared and non multi-processor
reception continues.
If a frame error occurs and the SSR_FIFO.FER flag is set to 1, SCI continues data reception. The rest of the operations
are the same as those in asynchronous mode with non-FIFO selected.
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25. Serial Communications Interface (SCI)
Initialization
[1]
[1]
SCI initialization:
Set data reception.
[2]
ID reception cycle:
Set the MPIE bit in SCR to 1 and wait for ID
reception.
[3]
SCI status confirmation and reception and
comparison of ID:
SCI stores first data (MPB = 1) and after that, all
received data are stored in FRDRHL.
RDF is set to 1 and At this time, an SCIn_RXI
interrupt request is generated, When the
amount of receive data which is equal to or
greater than the specified receive triggering
number are stored in FRDRHL.
When the amount of data stored in the receive
FIFO data register (FRDRHL) falls below the
specified receive triggering number and
received data is equal to or greater than 1, and
that no next data is received after the elapse of
15 ETUs from the last stop bit, SSR_FIFO.DR
is set to 1. At this time, an SCIn_RXI Interrupt
request is generated when FCR.DRES bit is 0.
Read data in FRDRHL at the first SCIn_RXI
interrupt, and compare it with the ID of the
receiving station itself.
If the ID does not match the ID of the receiving
station itself, it reads until the data with MPB =
1, and compares next ID. If it is not a data with
MPB = 1 in FRDRHL, it set the MPIE bit to 1
again, and wait for another SCIn_RXI interrupt
request.
[4]
Data reception at an SCIn_RXI interrupt:
Read data in FRDRHL once in the SCIn_RXI
interrupt routine.
[5]
Receive error processing and break detection:
If a receive error occurs, an error is identified by
reading the ORER and FER flags in SSR_FIFO.
After performing the appropriate error
processing, be sure to set the
SSR_FIFO.ORER and SSR_FIFO.FER flags to
0. Reception cannot resume if the ORER flag in
SSR_FIFO is set to 1. When framing error
occurs, a break can be detected by reading the
SPTR.RXDMON bit.
Start data reception
No
Set MPIE bit in SCR to 1.
[2]
SCIn_RXI interrupt?
[3]
Yes
Read Receive data and each flags in
FRDRHL*1.
FER flag = 1 or ORER flag = 1
Yes
No
No
ID of receiving station itself?
Yes
Yes
Receive data is still in FRDRHL?
No
No
SCIn_RXI interrupt?
[4]
Yes
Read Receive data and each flags in
FRDRHL*1.
FER flag = 1 or ORER flag = 1
Yes
No
No
All data received?
[5]
Error processing
Yes
(Same as Figure 25.28)
Set RE and RIE bits in SCR to 0.
End
Note 1.
Figure 25.30
25.5
If FRDRH and FRDRL are used instead of
FRDRHL, read in order from FRDRH to FRDRL.
Example flow of serial reception in multi-processor mode with FIFO selected
Operation in Clock Synchronous Mode
Figure 25.31 shows the data format for clock synchronous serial data communications.
In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in
transfer data consists of 8-bit data. In clock synchronous mode, no parity bit can be added.
In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data
reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is
output, the transmission line holds the last bit as output state. When SPMR.CKPH is 1 in slave mode, it holds the first bit
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25. Serial Communications Interface (SCI)
output state.
Within the SCI, the transmitter and receiver are independent units, enabling full-duplex communications by using a
common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data
can be written during transmission or the previous receive data can be read during reception, enabling continuous data
transfer.
However, it is not possible to do continuous transfer in the fastest bit rate setting (BRR = 00h and SMR.CKS[1:0] = 00b),
therefore when the FIFO is selected, this setting (BRR = 00h and SMR.CKS[1:0] = 00b) is not available.
One unit of transfer data (character or frame)
*1
*1
Synchronization
clock
LSB
Serial data
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Don't care
Note 1.
Figure 25.31
25.5.1
Bit 6
Bit 7
Don't care
Holds a high level except during continuous transfer.
Data format in clock synchronous serial communications (LSB first)
Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the
SCKn pin can be selected based on the SCR.CKE[1:0] setting.
When the SCI operates on an internal clock, the synchronization clock is output from the SCKn pin. Eight
synchronization clock pulses are output in the transfer of one character. When no transfer is performed the clock is held
high. However, when only data reception is performed while the CTS function is disabled, the synchronization clock
output starts at the same time when the SCR.RE bit is set to 1. The synchronization clock stops when it goes high*1 and
when an overrun error occurs, or when the SCR.RE bit is set to 0.
When only data reception is performed and the CTS function is enabled, the clock output does not start when the
SCR.RE bit set to 1 and the CTSn_RTSn pin input is high. The synchronization clock output starts when the SCR.RE bit
is set to 1 and the CTSn_RTSn pin input is low. Following that, when the CTSn_RTSn pin input is high on completion of
the frame reception, the synchronization clock output stops when it goes high. If the CTSn_RTSn pin input continues to
be low, the synchronization clock stops when it goes high*1 and when an overrun error occurs, or when the SCR.RE bit
is set to 0.
Note 1. The signal is held high while (SPMR.CKPH bit = 0 && SPMR.CKPOL bit = 0) or (SPMR.CKPH bit = 1 &&
SPMR.CKPOL bit = 1). It is held low while (SPMR.CKPH bit = 0 && SPMR.CKPOL bit = 1) or (SPMR.CKPH bit =
1 && SPMR.CKPOL bit = 0).
25.5.2
CTS and RTS Functions
In the CTS function, the CTSn_RTSn pin input controls the start of data reception or transmission when the clock source
is the internal clock. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled,
setting the CTSn_RTSn pin low causes data reception or transmission to start.
Setting the CTSn_RTSn pin high while the data transmission or reception is in progress does not affect transmission or
reception of the current frame.
In the RTS function, the CTSn_RTSn pin output is used to request the start of data reception or transmission when the
clock source is an external synchronizing clock. The CTSn_RTSn output goes low when serial communication becomes
possible. Conditions for output of CTSn_RTSn low and high are shown as follows:
[Conditions for low output]
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25. Serial Communications Interface (SCI)
Non-FIFO selected when all of the following conditions are satisfied
The value of the RE or TE bit in the SCR is 1
When serial communication is enabled
There is no received data available to be read when the SCR.RE bit is 1
Transmit data is written when the SCR.TE bit is 1 and SCR.CKE[1] bit is 0
ORER flag in SSR is 0.
(b)
FIFO selected when all of the following conditions are satisfied
The value of the RE or TE bit in the SCR is 1
When serial communication is enabled
The amount of receive data written in FRDRHL is less than the specified CTSn_RTSn output triggering number
when SCR.RE = 1
Data that has not been transmitted in FTDRHL is available when SCR.TE bit is 1 and SCR.CKE[1] bit is 0
Data is available before transmission in the TSR register when SCR.TE bit is 1 and SCR.CKE[1] bit is 1
The ORER in the SSR_FIFO is 0.
[Conditions for high output]
(a)
Non-FIFO selected when all of the following conditions are satisfied
The conditions for low output are not satisfied
After reception is complete, if it is terminated with SCR.RE = 0 without reading the RDR register, then RTS
remains high. Read the SCR register for dummy after writing SCR.RE = 0.
(b)
FIFO selected when all of the following conditions are satisfied
The conditions for low output are not satisfied.
25.5.3
SCI Initialization in Clock Synchronous Mode
Before transmitting and receiving data, start by writing the initial value 00h to the SCR then continue through the SCI
procedure given in the sections describing non-FIFO and FIFO selection in 25.5.2 CTS and RTS Functions. Anytime the
operating mode or transfer format is to be changed, the SCR must be initialized before the change can be made.
Note:
Note:
Setting the SCR.RE bit to 0 initializes neither the ORER, FER, RDRF, RDF, PER, and DR flags in SSR/
SSR_FIFO nor the RDR and RDRHL. When the TE bit is set to 0, the TEND flag for the selected FIFO buffer is
not initialized.
Switching the value of the SCR.TE bit from 1 to 0 or 0 to 1 when the SCR.TIE bit is 1 generates an SCIn_TXI
interrupt request.
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25. Serial Communications Interface (SCI)
Start initialization
Set the SCR.TIE, RIE, TE, RE, and
TEIE bits to 0
Set the FCR.FM bit to 0
[1]
Set the SCR.CKE[1:0] bits
[2]
Set the SIMR1.IICM bit to 0
Set the SPMR.CKPH and CKPOL bits
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[2]
Set the clock selection in SCR.
[3]
Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits.
Step [3] can be skipped if the values have not changed from
the initial values.
[4]
Set data transmission/reception format in SMR, SCMR, and
SEMR.
[5]
Write a value corresponding to the bit rate to BRR.
This step is not necessary if an external clock is used.
[6]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not necessary if the BRME bit in SEMR
is set to 0 or an external clock is used.
[7]
Set the I/O port to enable input and output functions as
required for the TXDn, RXDn, and SCKn pins.
[8]
Set the SCR.TE or RE bit to 1. Set the SCR.TIE and RIE bits
also.
Setting the TE and RE bits allows TXDn and RXDn to be
used.
[4]
[5]
Set a value in MDDR
[6]
Set the I/O port functions
[7]
Set the SCR.TE or RE bit to 1, and
set the SCR.TIE and RIE bits
[8]
Figure 25.32
Set the FCR.FM bit to 0.
[3]
Set a value in BRR
Initialization completion
[1]
Note:
In simultaneous transmit and receive operations, the TE and RE
bits in SCR should both be to 0 or set to 1 simultaneously.
Example flow of SCI initialization in clock synchronous mode with non-FIFO selected
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25. Serial Communications Interface (SCI)
Start initialization
Set the SCR.TIE, RIE, TE, RE, and
TEIE bits to 0
Set the FCR.FM, TFRST, and RFRST bits to 1
Set the FCR.TTRG[3:0], RTRG[3:0], and
RSTRG[3:0] bits
[1]
Set the SCR.CKE[1:0] bits
[2]
Set the SIMR1.IICM bit to 0
Set the SPMR.CKPH and CKPOL bits
[3]
Set the data transmission/reception format in
SMR, SCMR, and SEMR
[5]
Set a value in MDDR
[6]
Set the FCR.TFRST and RFRST bits to 0
[7]
Set the I/O port functions
[8]
Set the SCR.TE or RE bit to 1, and
set the SCR.TIE and RIE bits
[9]
Figure 25.33
25.5.4
(1)
Set the FCR.FM, TFRST, and RFRST bits to 1.
This is for setting to be empty in FIFO.
Set the FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0] bits.
[2]
Set the clock selection in SCR.
[3]
Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits.
Step [3] can be skipped if the values have not been changed
from the initial values.
[4]
Set the data transmission/reception format in SMR, SCMR,
and SEMR.
[5]
Write a value corresponding to the bit rate to BRR.
This step is not necessary if an external clock is used.
[6]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not necessary if the BRME bit in SEMR
is set to 0 or an external clock is used.
[7]
Set the FCR.TFRST and RFRST bits to 0.
[8]
Set the I/O port to enable input and output functions as
required for the TXDn, RXDn, and SCKn pins.
[9]
Set the SCR.TE or RE bit to 1. Set the SCR.TIE and RIE bits
also.
Setting the TE and RE bits allows TXDn and RXDn to be
used.
[4]
Set a value in BRR
Initialization completion
[1]
Note:
In simultaneous transmit and receive operations, the TE and RE
bits in SCR should both be to 0 or set to 1 simultaneously.
Example flow of SCI initialization in clock synchronous mode with FIFO selected
Serial Data Transmission in Clock Synchronous Mode
Non-FIFO selected
Figure 25.34, Figure 25.35, and Figure 25.36 show examples of serial transmission in clock synchronous mode.
In serial data transmission, the SCI operates as follows:
1. The SCI transfers data from TDR to TSR when data is written to TDR in the SCIn_TXI interrupt handling routine.
The SCIn_TXI interrupt request at the beginning of transmission is generated when the TE bit is set to 1 but only
after the TIE bits in the SCR are also set to 1 or when these two bits are set to 1 simultaneously by a single
instruction.
2. After transferring data from TDR to TSR, the SCI starts transmission. When the SCR.TIE bit is set to 1, an
SCIn_TXI interrupt request is generated. Continuous transmission is enabled by writing the next transmit data to
TDR in this SCIn_TXI interrupt handling routine before transmission of the current transmit data finishes. When
SCIn_TEI interrupt requests are in use, set the SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last of the data
to be transmitted is written to the TDR from the handling routine for SCIn_TXI requests.
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25. Serial Communications Interface (SCI)
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is
specified and in synchronization with the input clock when the use of an external clock is specified. Output of the
clock signal is suspended until the input CTS signal is low while the CTSE bit in SPMR is 1.
4. The SCI checks for update to the TDR on output of the last bit.
5. When TDR is updated, the next transmit data is transferred from TDR to TSR, and serial transmission of the next
frame starts.
6. If TDR is not updated, set the SSR.TEND flag to 1. The TXDn pin retains the output state of the last bit. If the TEIE
bit in SCR is 1, an SCIn_TEI interrupt request is generated and the SCKn pin is held high.
Figure 25.34 shows an example flow of serial data transmission.
Transmission does not start while a receive error flag (ORER, FER, or PER in SSR) is set to 1. Be sure to set the receive
error flags to 0 before starting transmission.
Note:
Setting the RE bit in SCR to 0 does not clear the receive error flags.
Synchronization clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
Bit 0
SCR.TE bit
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
Data written to TDR in SCIn_TXI
interrupt handling routine
SCIn_TXI
interrupt
request
generated
SCIn_TXI
interrupt
request
generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
SCIn_TXI interrupt
request generated
Data written to TDR in SCIn_TXI
interrupt handling routine
1 frame
Note 1.
Figure 25.34
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of serial data transmission in clock synchronous mode when the CTS function is not
used at the beginning of transmission
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25. Serial Communications Interface (SCI)
CTSn_RTSn pin
Synchronization clock
Bit 0
Serial data
Bit 1
Bit 7
Bit 0
SCR.TE bit
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SSR.TEND flag
SCIn_TXI interrupt
request generated
SCIn_TXI interrupt
Request generated
SCIn_TXI interrupt
request generated
Data written to TDR in
SCIn_TXI interrupt handling
routine
Data written to TDR in
SCIn_TXI interrupt
handling routine
Data written to TDR in
SCIn_TXI interrupt
handling routine
1 frame
Note 1.
Figure 25.35
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of serial data transmission in clock synchronous mode when the CTS function is used
at the beginning of transmission
Synchronization
clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 7
(TIE = 1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
(TIE = 0)
SSR.TEND flag
SCIn_TXI
interrupt request
generated
Data written to TDR in
SCIn_TXI interrupt
handling routine
SCIn_TXI
interrupt
request
generated
Data written to TDR in SCIn_TXI
interrupt handling routine
(Set the TIE bit to 0 and the TEIE
bit to 1 after writing the last data)
SCIn_TEI
interrupt request
generated
1 frame
Note 1.
Figure 25.36
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of serial data transmission in clock synchronous mode from the middle of transmission
until transmission completion
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25. Serial Communications Interface (SCI)
[1]
Initialization
Start transmission
SCIn_TXI interrupt
No
[1]
SCI initialization:
Set data transmission.
[2]
Writing transmit data write to TDR by an SCIn_TXI
interrupt request:
When transmit data is transferred from TDR to TSR, a
transmit data empty interrupt (SCIn_TXI) request is
generated.
Transmit data is written to TDR once from the handling
routine for SCIn_TXI requests.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write transmit data to
TDR upon accepting a transmit data empty interrupt
(SCIn_TXI) request. Transmit data can also be written to
TDR by activating the DTC by the SCIn_TXI interrupt
request.
When SCIn_TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last
of the data to be transmitted is written to the TDR.
[2]
Yes
Write transmit data to TDR
All data transmitted?
No
[3]
Yes
Set the TIE bit in SCR to 0, and
set the TEIE bit in SCR to 1
SCIn_TEI interrupt
No
Yes
Set bits TIE, TE, and TEIE in SCR to 0
End
Note:
When the external clock is in use (the value of the SCR.CKE[1:0] bits is 10b or 11b), the rising edge on the SCK pin for
the last bit sets the SSR.TEND flag to 1. Setting the SCR.TE bit to 0 immediately after this may lead to insufficient
received-data hold time on the receiver side.
Figure 25.37
(2)
Example flow of serial transmission in clock synchronous mode with non-FIFO selected
FIFO selected
Figure 25.34 shows an example of serial transmission in clock synchronous mode with FIFO selected.
In serial data transmission, the SCI operates as follows:
1. The SCI transfers data from FTDRL*1 to TSR when data is written to FTDRL*1 in the SCIn_TXI interrupt handling
routine. The amount of data that can be written to FTDRL is 16 minus FDR.T[4:0] bytes. The SCIn_TXI interrupt
request at the beginning of transmission is generated when the TE bit in SCR is set to 1 but only after the TIE bit in
SCR is also set to 1 or when these two bits are set to 1 simultaneously by a single instruction.
2. After transferring data from FTDRL to TSR, the SCI starts transmission. When the amount of transmit data written
in FTDRL is equal to or less than the specified transmit triggering number, the SSR_FIFO.TDFE is set to 1. When
the SCR.TIE bit is set to 1, an SCIn_TXI interrupt request is generated. Continuous transmission is enabled by
writing the next transmit data to FTDRL in this SCIn_TXI interrupt handling routine before transmission of the
current transmit data has finished. When SCIn_TEI interrupt requests are in use, set the SCR.TIE bit to 0 and the
SCR.TEIE bit to 1 after the last of the data to be transmitted is written to the FTDRL from the handling routine for
SCIn_TXI requests.
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is
specified and in synchronization with the input clock when the use of an external clock is specified. Output of the
clock signal is suspended until the input CTS signal is low and while the CTSE bit in SPMR is 1.
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25. Serial Communications Interface (SCI)
4. The SCI checks whether non-transmitted data remains in FTDRL at the time of the output of the stop bit.
5. When FTDRL is updated, the next transmit data is transferred from FTDRL to TSR and serial transmission of the
next frame starts.
6. If FTDRL is not updated, set the SSR_FIFO.TEND flag to 1. The TXDn pin retains the output state of the last bit. If
the TEIE bit in SCR is 1, an SCIn_TEI interrupt request is generated and the SCKn pin is held high.
Note 1. In clock synchronous mode, FTDRH is not used.
Initialization
[1]
[1]
SCI initialization:
Set data transmission.
After the TE bit in SCR is set to 1, 1 is output for a frame,
and transmission is enabled.
[2]
Transmit data write to FTDRL by an SCIn_TXI interrupt
request:
When transmit data is transferred from FTDRL to TSR,
and when the amount of transmit data written in FTDRL is
equal to or less than the specified transmit triggering
number, a transmit data FIFO empty interrupt (SCIn_TXI)
request is generated. Write transmit data to FTDRL once
in the SCIn_TXI interrupt handling routine.
[3]
Serial transmission continuation procedure:
To continue serial transmission, write the next transmit
data to FTDRL in this SCIn_TXI interrupt handling routine
and clear the SSR_FIFO.TDFE flag to 0 before
transmission of the current transmit data finished.
Transmit data can also be written to FTDRL by activating
the DTC. The TDFE flag is cleared automatically in this
case. Do not write to the TDFE flag.
When SCIn_TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last of
the data to be transmitted is written to the FTDRL.
Start data transmission
SCIn_TXI interrupt
No
[2]
Yes
Write transmit data to FTDRL
All transmit data
written to FTDRL register?
[3]
No
Yes
Set the SCR.TIE bit to 0 and set the
SCR.TEIE bit to 1
No
SCIn_TEI interrupt
Yes
Set bits SCR.TE, TIE, and TEIE to 0
End
Note:
When the external clock is in use (the value of the SCR.CKE[1:0] bits is 10b or 11b), the rising edge on the SCK pin for
the last bit sets the SSR_FIFO.TEND flag to 1. Setting the SCR.TE bit to 0 immediately after this may lead to
insufficient received-data hold time on the receiver side.
Figure 25.38
25.5.5
(1)
Example flow of serial transmission in clock synchronous mode with FIFO selected
Serial Data Reception in Clock Synchronous Mode
Non-FIFO selected
Figure 25.39 and Figure 25.40 show examples of SCI operation for serial reception in clock synchronous mode.
In serial data reception, the SCI operates as follows:
1. When the value of the RE bit in SCR becomes 1, the CTSn_RTSn pin goes low.
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
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25. Serial Communications Interface (SCI)
input or output, and stores the receive data in RSR.
3. If an overrun error occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is 1, an SCIn_ERI interrupt request
is generated. Receive data is not transferred to RDR.
4. When reception completes successfully, receive data is transferred to RDR. If the RIE bit in SCR is 1, an SCIn_RXI
interrupt request is generated. Continuous reception is enabled by reading the receive data transferred to RDR in the
SCIn_RXI interrupt handling routine before reception of the next receive data completes. Reading the received data
that is transferred to RDR causes the CTSn_RTSn pin to output low.
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.ORER flag
SCIn_RXI
interrupt request
generated
RDR data read in SCIn_RXI
interrupt handling routine
SCIn_RXI
interrupt request
generated
SCIn_ERI interrupt request
generated by overrun error
1 frame
Note 1.
Figure 25.39
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example operation for serial reception in clock synchronous mode (1) when RTS function is not
used
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SSR.ORER flag
SCIn_RXI
interrupt request
generated
SCIn_RXI interrupt
request generated
RDR data read in
SCIn_RXI interrupt
handling routine
SCIn_ERI interrupt request
generated by overrun error
CTSn_RTSn pin
1 frame
Note 1.
Figure 25.40
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example of operation for serial reception in clock synchronous mode (2) when RTS function is
used
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25. Serial Communications Interface (SCI)
Data transfer cannot resume while the receive error flag is 1. Therefore, clear the ORER, FER, and PER bits in SSR to 0
before resuming data reception. Additionally, be sure to read the RDR during overrun error processing. When a data
reception is forcibly terminated by setting the SCR.RE bit to 0 during operation, read the RDR because received data that
is not yet read might be left in the RDR.
Figure 25.41 shows an example flow of serial data reception.
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25. Serial Communications Interface (SCI)
Initialization
Start data reception
No
SCI initialization:
Set the input port-pin to be used as RXDn pins.
[2]
[3] Receive error processing:
If a receive error occurs, read the ORER flag in
SSR, perform the relevant error processing, and
then set the ORER flag to 0. Data reception
cannot resume while the ORER flag is 1.
[4]
Read the receive data in RDR once in the receive
data full interrupt (SCIn_RXI) request handling
routine.
[5]
Serial reception continuation procedure:
To continue serial reception, before the MSB (bit
7) of the current frame is received, finish reading
the receive data in RDR. The RDR data can also
be read by activating the DTC by an SCIn_RXI
interrupt request.
[6]
Processing in response to an overrun error:
Read the RDR. In combination with step [7], this
makes correct reception of the next frame
possible.
[2]
Read ORER flag in SSR
SSR.ORER = 1
[1]
[1]
Yes
[3]
Error processing
(Continued below)
No
SCIn_RXI interrupt
Yes
No
Read receive data in RDR
[4]
All data received?
[5]
Yes
Set bits RIE and RE in SCR to 0
End
[3]
Error processing
Overrun error processing
[6]
[7]
Clearing the error flag:
Write 0 to the error flag.
Clear the SSR.ORER flag to 0
[7]
[8]
Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
Read the SSR.ORER flag
[8]
End
Figure 25.41
Example flow of serial reception in clock synchronous mode with non-FIFO selected
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(2)
25. Serial Communications Interface (SCI)
FIFO selected
Figure 25.42 shows an example of serial reception in clock synchronous mode with FIFO selected.
In serial data reception, the SCI operates as follows:
1. When the value of the RE bit in SCR becomes 1, the CTSn_RTSn pin goes low.
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
input or output, and stores the receive data in RSR.
3. If an overrun error occurs, the ORER bit in SSR_FIFO is set to 1. If the RIE bit in SCR is 1, an SCIn_ERI interrupt
request is generated. Received data is not transferred to FRDRL*1.
4. When data reception completes successfully, the receive data is transferred to FRDRL*1. RDF is set to 1 when the
amount of the receive data is equal to or greater than the specified receive triggering number stored in FRDRHL. If
the RIE bit in SCR is 1, an SCIn_RXI interrupt request is generated. Continuous data reception is enabled by
reading the receive data transferred to FRDRL*2 in the SCIn_RXI interrupt handling routine before an overrun error
occurs. If the amount of received data that is transferred to FRDRL is less than the RTS trigger number, the
CTSn_RTSn pin goes low.
Note 1. In clock synchronous mode, FTDRH is not used.
Note 2. Read the data in order from FRDRH to FRDRL when RDF and ORER are read with receive data.
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25. Serial Communications Interface (SCI)
Initialization
Start data reception
SCI initialization:
Set the input port-pin to be used as RXDn pins.
[2]
[3] Receive error processing:
If a receive error occurs, read the ORER flag in
SSR_FIFO, perform the relevant error processing,
then set the SSR_FIFO.ORER flag to 0. Data
reception cannot resume while the ORER flag is 1.
[4]
The reception data stored in FRDRL register is
read until the number of stored data is less than
the FCR.RTRG value. SW can check readable
data in FDR.R[4:0].
[5]
Serial reception continuation procedure:
To continue serial reception, before overrun error
occurs, finish reading the receive data in FRDRL
and clear the SSR_FIFO.RDF flag to 0.The
FRDRL data can also be read by activating the
DTC by an SCIn_RXI interrupt request. The RDF
flag is cleared automatically in this case. Do not
write to the RDF flag.
[6]
Processing in response to an overrun error:
Read the FRDRL. In combination with step [7], this
enables correct reception of the next frame
possible.
[7]
Clearing the error flag:
Write 0 to the error flag.
[8]
Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.
[2]
Read ORER*1 flag in SSR_FIFO
Yes
SSR_FIFO.ORER = 1
No
[1]
[1]
[3]
Error processing
(Continued below)
No
SCIn_RXI interrupt*2
Yes
No
Read receive data in FRDRL
[4]
All data received?
[5]
Yes
Set bits RIE and RE in SCR to 0
End
[3]
Error processing
Overrun error processing
[6]
Clear the SSR_FIFO.ORER flag to 0
[7]
Note 1.
Read the SSR_FIFO.ORER flag
[8]
Note 2.
It can also read from FRDRH.ORER. However,
to clear the ORER flag, write 0 to the
associated bit in the SSR_FIFO register.
It should be all receive data and is an integer
times the FIFO triggering number.
End
Figure 25.42
Example flow of serial reception in clock synchronous mode with FIFO selected
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25.5.6
(1)
25. Serial Communications Interface (SCI)
Simultaneous Serial Data Transmission and Reception in Clock Synchronous
Mode
Non-FIFO selected
Figure 25.43 shows an example flow of simultaneous serial transmit and receive operations in clock synchronous mode.
After initializing the SCI, use the following procedure for simultaneous serial data transmit and receive operations.
To switch from transmit mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the data transmission by verifying that the TEND flag in the SSR_FIFO register is set
to 1.
2. Initialize the SCR register, then set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously with a
single instruction.
To switch from receive mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the data reception.
2. Set SCR.RIE and SCR.RE to 0, then check that the receive error flag ORER in SSR register is 0.
3. Set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously with a single instruction.
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25. Serial Communications Interface (SCI)
[1]
Initialization
[1]
SCI initialization:
The TXDn pin can act as the output pin for
transmitted data and the RXDn pin can act as the
input pin for received data at the same time.
[2]
Transmit data write:
Write transmit data to TDR once in the SCIn_TXI
interrupt request handling routine.
[3]
Receive error processing:
If a receive error occurs, read the ORER flag in
SSR, perform the relevant error processing, then set
the ORER flag to 0. Data reception cannot resume
while the ORER flag is 1.
[4]
Reading receive data:
Read the receive data in RDR once in the SCIn_RXI
interrupt request handling routine.
[5]
Serial transmission/reception continuation
procedure:
To continue serial transmission and reception,
before the MSB bit [7] of the current frame is
received, finish reading the receive data in RDR by
the SCIn_RXI interrupt. Also, before the MSB bit [7]
of the current frame is transmitted, write data to
TDR by the SCIn_TXI interrupt.
Transmit data can also be written to TDR by
activating the DTC by a transmit data empty
interrupt (SCIn_TXI) request. Similarly, the RDR
data can also be read by activating the DTC by a
receive data full interrupt (SCIn_RXI) request.
Start data transmission/reception
No
SCIn_TXI interrupt
Yes
[2]
Write transmit data to TDR
Read ORER flag in SSR
Yes
SSR.ORER = 1
No
No
Error processing
SCIn_RXI interrupt
Yes
No
[3]
Read receive data in RDR
[4]
All data received?
[5]
Yes
Clear TIE, RIE, TE, RE, and TEIE
bits in SCR to 0
End
Note:
Figure 25.43
(2)
When switching from transmit or receive operation to simultaneous transmit and receive operations, first set the TIE,
RIE, TE, RE, and TEIE bits in SCR to 0, then set the TIE, RIE, TE, and RE bits to 1, simultaneously.
Example flow of simultaneous serial transmission and reception in clock synchronous mode with
non-FIFO selected
FIFO selected
Figure 25.44 shows an example flow of simultaneous serial transmit and receive operations in clock synchronous mode
with FIFO selected.
After initializing the SCI, use the following procedure for simultaneous serial data transmit and receive operations.
To switch from transmit mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the transmission by verifying that the TEND flag in the SSR_FIFO register is set to 1.
2. Initialize the SCR register, then set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously with a
single instruction.
To switch from receive mode to simultaneous transmit and receive mode:
1. Check that the SCI completes the reception.
2. Set SCR.RIE and SCR.RE bits to 0, then check that the receive error flags ORER, FER, and PER in the SSR_FIFO
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25. Serial Communications Interface (SCI)
register are 0.
3. Set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously with a single instruction.
[1]
Initialization
[1]
SCI initialization:
The TXDn pin can act as the output pin for transmitted
data and the RXDn pin can act as the input pin for
received data at the same time.
[2]
Transmit data write:
Write transmit data to FTDRL in the SCIn_TXI
Interrupt request handling routine. The number of
transmission data that is possible to write in is 16 –
(the number of stored transmit FIFO data).
[3]
Receive error processing:
If a receive error occurs, read the ORER flag in
SSR_FIFO, perform the relevant error processing, and
then set the ORER flag to 0. Data reception cannot
resume while the ORER flag is 1.
[4]
Reading receive data:
The reception data stored in FRDRL register is read
until the number of stored data is less than the
FCR.RTRG value. SW can check readable data in
FDR.R[4:0].
[5]
Serial transmission/reception continuation procedure:
To continue serial reception, before overrun error
occurs, finish reading the receive data in FRDRL and
clear the SSR_FIFO.RDF flag to 0. To continue serial
transmission, before transmission of the current
transmit data has finished, write the next transmit data
to FTDRL In this SCIn_TXI interrupt handling routine
and clear the SSR_FIFO.TDFE flag to 0.
Transmit data can also be written to FTDRL by
activating the DTC by a transmit FIFO data empty
interrupt (SCIn_TXI) request. Similarly, the FRDRL
data can also be read by activating the DTC by a
receive FIFO Data full interrupt (SCIn_RXI) request.
The RDF and TDFE flags are cleared automatically in
this case.
Do not write to the RDF And TDFE flags.
Start data transmission/reception
No
SCIn_TXI interrupt
Yes
[2]
Write transmit data to FTDRL
Read ORER*1 flag in SSR_FIFO
Yes
SSR_FIFO.ORER = 1
No
No
[3]
Error processing
SCIn_RXI interrupt*2
Yes
No
Read receive data in FRDRL
[4]
All data received?
[5]
Yes
Clear TIE, RIE, TE, RE, and TEIE
bits in SCR to 0
End
Note 1.
Note 2.
Figure 25.44
25.6
It can also read from FRDRH.ORER. To clear
the ORER flag, write 0 to the associated bit in
the SSR_FIFO register.
It should be all receive data with an integer
times the FIFO triggering number.
Example flow of simultaneous serial transmission and reception in clock synchronous mode with
FIFO selected
Operation in Smart Card Interface mode
The SCI supports smart card (IC card) interfaces conforming to ISO/IEC 7816-3 (standard for Identification Cards), as
an extended function of the SCI.
Smart card interface mode can be selected using the appropriate register.
25.6.1
Example Connection
Figure 25.45 shows an example connection between a smart card (IC card) and the MCU.
As shown in Figure 25.45, because the MCU communicates with an IC card using a single transmission line,
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25. Serial Communications Interface (SCI)
interconnect the TXDn and RXDn pins and pull up the data transmission line to VCC using a resistor.
Setting the TE and RE bits in SCR_SMCI to 1 with an IC card disconnected enables closed-loop transmission or
reception, allowing self-diagnosis. To supply an IC card with the clock pulses generated by the SCI, input the SCKn pin
output to the CLK pin of an IC card.
The output port of the MCU can be used to output a reset signal.
VCC
VCC
TXDn
RXDn
SCKn
Port
This MCU
Data line
Clock line
Reset line
I/O
CLK
RST
IC card
Main unit of the device to
be connected
Figure 25.45
25.6.2
Example connection with a Smart Card (IC Card)
Data Format (Except in Block Transfer Mode)
Figure 25.46 shows the data transfer formats in smart card interface mode.
One frame consists of 8-bit data and a parity bit in asynchronous mode
During transmission, at least 2 ETUs (elementary time unit – the time required for transferring 1 bit) is set as a
guard time from the end of the parity bit until the start of the next frame
If a parity error is detected during reception, a low error signal is output for 1 ETU after 10.5 ETUs elapse from the
start bit
If an error signal is sampled during transmission, the same data is automatically retransmitted after at least 2 ETUs.
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25. Serial Communications Interface (SCI)
In normal transmission/reception
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Output from the transmitting station
When a parity error occurs
Ds
D0
D1
D2
D3
D4
D5
DE
Output from the transmitting station
Output from the
receiving station
Ds:
D0 to D7:
Dp:
DE:
Figure 25.46
Start bit
Data bits
Parity bit
Error signal
Data formats in smart card interface mode
For communications with IC cards of the direct convention type and inverse convention type, follow the procedures in
this section.
(1)
Direct Convention Type
For the direct convention type, logic levels 1 and 0 indicate the Z and A states, respectively, and data is transferred with
LSB-first as the start character, as Figure 25.47 shows. Therefore, data in the start character in the figure is 3Bh.
When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the PM bit in
SMR_SMCI to use even parity, which is described by the smart card standard.
(Z)
Figure 25.47
(2)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp
(Z) state
Direct convention with SDIR in SCMR = 0, SINV in SCMR = 0, and PM in SMR_SMCI = 0
Inverse Convention Type
For the inverse convention type, logic levels 1 and 0 indicate the A and Z states, respectively and data is transferred with
MSB-first as the start character, as Figure 25.48 shows. Therefore, data in the start character in the figure is 3Fh.
When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0
to produce even parity, which is described by the smart card standard, and corresponds to state Z. Because the SINV bit
of the MCU only inverts data bits D7 to D0, write 1 to the PM bit in SMR_SMCI to invert the parity bit for both
transmission and reception.
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25. Serial Communications Interface (SCI)
(Z)
A
Z
Z
A
A
A
A
A
A
Z
(Z) state
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
Figure 25.48
25.6.3
Inverse convention with SDIR in SCMR = 1, SINV in SCMR = 1, and PM in SMR_SMCI = 1
Block Transfer Mode
Block transfer mode differs from non-block transfer mode of smart card interface mode as follows:
Even if a parity error is detected during reception, no error signal is output. Because the PER bit in SSR_SMCI is set
by error detection, clear the PER bit before receiving the parity bit of the next frame
During transmission, at least 1 ETU is set as a guard time from the end of the parity bit until the start of the next
frame
Because the same data is not retransmitted, the TEND flag in SSR_SMCI is set to 11.5 ETUs after transmission
starts
In block transfer mode, the ERS flag in SSR_SMCI indicates the error signal status as in non-block transfer mode of
smart card interface mode, but the flag is read as 0 because no error signal is transferred.
25.6.4
Receive Data Sampling Timing and Reception Margin
Only the clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode.
In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit
rate set up in the SCMR.BCP2 bit and the SMR_SMCI.BCP[1:0] bits.
For data reception, the falling edge of the start bit is sampled with the base clock to perform synchronization.
Receive data is sampled on the 16th, 32nd, 186th, 128th, 46th, 64th, 93rd, and 256th rising edges of the base clock so that
it can be latched at the middle of each bit as Figure 25.49 shows. The reception margin is determined by the following
formula:
M = (0.5 -
1
) - (L - 0.5) F 2N
D - 0.5
N
(1 + F)
× 100 [%]
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Duty cycle of clock (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N = 372 in the specified formula, the reception margin is determined by the
following formula:
M = {0.5 - 1/(2 × 372)} × 100 [%] = 49.866%
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25. Serial Communications Interface (SCI)
372 clocks
372 clocks
186 clocks
0
186 clocks
185
371 0
185
371 0
Base clock
Receive data (RXDn)
Start bit
D0
D1
Synchronization sampling
timing
Data sampling timing
Figure 25.49
25.6.5
Receive data sampling timing in smart card interface mode when clock frequency is 372 times the
bit rate
Initialization of the SCI
Before transmitting and receiving data, write the initial value 00h in the SCR_SMCI register and initialize the SCI
following the example flow shown in Figure 25.50.
Be sure to set the initial value in the TIE, RIE, TE, RE, TEIE bits in the SCR_SMCI register before switching from
transmission to reception mode or from reception to transmission mode. When SCR_SMCI.RE is set to 0, the RDR
register is not initialized.
To change from reception mode to transmission mode, first check that reception has completed, then initialize the SCI.
At the end of initialization, set SCR_SMCI.TE = 1 and SCR_SMCI.RE = 0. Reception completion can be verified by
reading the SCIn_RXI request, ORER, or PER flag in SSR_SMCI.
To change from transmission mode to reception mode, first check that transmission has completed, then initialize the
SCI. At the end of initialization, set SCR_SMCI.TE = 0 and SCR_SMCI.RE = 1. Transmission completion can be
verified by reading the TEND flag in SSR_SMCI.
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25. Serial Communications Interface (SCI)
Start initialization
Set SCR_SMCI.TIE, RIE, TE, RE,
TEIE, and CKE[1:0] to 0
[1]
[ 1 ] Stop the communication and initialize SKE[1:0]
Set SIMR1.IICM bit to 0
Set SCMR.SMIF to 1
[2]
[ 2 ] Set to smart card interface mode
Set SSR_SMCI.ORER, ERS, PER to 0
[3]
Set SPMR.CKPH, CKPOL
[3]
Write to SSR_SMCI after reading SSR_SMCI
[4]
[4]
Set the transmission or reception format in SPMR
Set SMR_SMCI.GM, BLK, PM,
BCP[1:0], CKS[1:0], and set
SMR_SMCI.PE to 1
[5]
[ 5 ] Set the operation mode and the transmission or
reception format in SMR_SMCI
Set SCMR.BCP2, SDIR, SINV
[6]
Set SEMR.BRME and
SEMR.RXDESEL to 0
[7]
Set a value in BRR
[8]
[ 8 ] Write the value for the bit rate in BRR.
Set the I/O port functions
[9]
[ 9 ] Set the I/O port functions for TXDn, RXDn, and SCKn
Set a value in SCR_SMCI.CKE[1:0]
[ 10 ]
[ 10 ] Set the SCR_SMCI.CKE[1:0]. Even though the function
depends on SMR_SMCI.GM, when the CKE[0] bit is set to 1,
the clock is output from the SCKn pin.
Set SCR_SCMI.TE or RE to 1, and
Set SCR_SMCI.TIE, RIE
[ 11 ]
[ 6 ] Set the transmission or reception format in SCMR
[ 7 ] Set SEMR.BRME and SEMR.RXDESEL to 0
[ 11 ] Set the TE or RE bit in SCR_SMCI to 1, then set the
TIE, and RIE bits in SCR_SMCI. Do not simultaneously set
the TE and RE bits to 1 if self-diagnosis is not used.
Initialization completed
Figure 25.50
Example flow of SCI initialization in smart card interface mode
Figure 25.51 shows a timing diagram when data transmission is performed by transitioning to smart card interface mode
according to the flow in Figure 25.50. Figure 25.51 shows when the GM bit in SMR_SMCI is set to 0. The timing in
Figure 25.51 shows when the port is connected as SCKn pin and TXDn pin, the pins are Hi-Z because CKE[0] bit in
SCR_SMCI is 0.
Start the clock output to the SCK pin by setting CKE[0] bit in SCR_SMCI to 1, then start data transmission by writing
transmit data after setting TE bit in SCR_SMCI to 1. When the TE bit in SCR_SMCI changes from 0 to 1, there is a
preamble period for one frame before data transmission starts. In smart card interface mode, the TXDn pin is Hi-Z during
the preamble period. Pull-up or pull-down for the SCKn and TXDn pins is required outside the MCU.
In the smart card interface mode, even when the TE and RE bits in SCR_SMCI are 0, the clock is continuously output if
the clock output setting is used.
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25. Serial Communications Interface (SCI)
Connect port
SCKn
SCKn starts when CKE[0] = 1
Hi-Z
Smart card interface mode
Mode
SCR.TE
Preamble period
TXDn
Ds
Hi-Z
TE = 1
Figure 25.51
25.6.6
Data transfer
D0
D1
Write transfer data
Example timing of data transmission in smart card interface mode
Serial Data Transmission (Except in Block Transfer mode)
Serial data transmission in smart card interface mode (except in block transfer mode) is different from that in non-smart
card interface mode, in that an error signal is sampled and data can be retransmitted in smart card interface mode. Figure
25.52 shows the data retransfer operation during transmission.
[1] indicates when an error signal from the receiver end is sampled after 1-frame data is transmitted, the ERS flag in
SSR_SMCI is set to 1. If the RIE bit in SCR_SMCI is 1, an SCIn_ERI interrupt request is generated. Clear the ERS flag
to 0 before the next parity bit is sampled.
[2] indicates for a frame in which an error signal is received, the TEND flag in SSR_SMCI is not set. Data is
retransferred from TDR to TSR allowing automatic data retransmission.
[3] indicates if no error signal is returned from the receiver, the ERS flag is not set to 1.
[4] indicates the SCI determines that transmission of 1-frame data, including the retransfer, is complete, and the TEND
flag is set. If the TIE bit in SCR_SMCI is 1, an SCIn_TXI interrupt request is generated. Write transmit data to the TDR
to start transmission of the next data.
Figure 25.54 shows an example flow of serial transmission. All the processing steps are automatically performed using
an SCIn_TXI interrupt request to activate the DTC.
When the TEND flag in SSR_SMCI is set to 1 in transmission and when the TIE bit in SCR_SMCI is 1, an SCIn_TXI
interrupt request is generated.
The DTC is activated by an SCIn_TXI interrupt request if the SCIn_TXI interrupt request is specified as a source of DTC
activation beforehand, allowing the transfer of transmit data. The TEND flag is automatically set to 0 when the DTC
transfers the data.
If an error occurs, the SCI automatically retransmits the same data. During this retransmission, the TEND flag is kept to
0 and the DTC is not activated. Therefore, the SCI and DTC automatically transmit the specified number of bytes,
including retransmission when an error occurs. Because the ERS flag is not automatically cleared, set the RIE bit to 1
before enabling an SCIn_ERI interrupt request to be generated if an error occurs, and clear the ERS flag to 0.
When transmitting or receiving data using the DTC, be sure to enable the DTC before setting the SCI.
For DTC settings, see section 14, Data Transfer Controller (DTC).
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25. Serial Communications Interface (SCI)
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(n + 1)-th transfer
frame
Retransfer frame
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
SCIn_TXI interrupt signal
[2]
[4]
SSR_SMCI.ERS flag
[1]
Figure 25.52
Note:
[3]
Data retransfer operation in SCI transmission mode
The SSR_SMCI.TEND flag is set at different timings depending on the GM bit setting in SMR_SMCI.
Figure 25.53 shows the TEND flag generation timing.
I/O data
Ds
D0
D1
D2
D3
D4
D5
D6
D7
SSR_SMCI.TEND flag
(SCIn_TXI interrupt)
When GM bit in SMR_SMCI = 1
Figure 25.53
DE
Guard
time
When GM bit in SMR_SMCI = 0
Ds:
D0 to D7:
Dp:
DE:
Dp
12.5 ETU (11.5 ETU in block transfer mode)
11.0 ETU
Start bit
Data bits
Parity bit
Error signal
SSR.TEND flag generation timing during transmission
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Start
Initialization
Start data transmission
SSR_SMCI.ERS flag = 0?
No
Yes
Error processing
No
SCIn_TXI interrupt
Yes
Write transmit data to TDR
No
Write all transmit data
Yes
SSR_SMCI.ERS flag = 0?
No
Yes
Error processing
No
SCIn_TXI interrupt
Yes
Set bits TIE, RIE, and TE
in SCR_SMCI to 0
End
Figure 25.54
25.6.7
Example flow of smart card interface transmission
Serial Data Reception (Except in Block Transfer Mode)
Serial data reception in smart card interface mode is similar to that in non-smart card interface mode. Figure 25.55 shows
the data retransfer operation in reception mode.
[1] indicates if a parity error is detected in the receive data, the PER flag in SSR_SMCI is set to 1. When the RIE bit
in SCR_SMCI is 1, an SCIn_ERI interrupt request is generated. Clear the PER flag to 0 before the next parity bit is
sampled.
[2] indicates for a frame in which a parity error is detected, no SCIn_RXI interrupt is generated.
[3] indicates when no parity error is detected, the PER flag in SSR_SMCI is not set to 1.
[4] indicates the data is determined to be received successfully. When the RIE bit in SCR_SMCI is 1, an SCIn_RXI
interrupt request is generated.
Figure 25.56 shows an example flow for serial data reception. All the processing steps are automatically performed using
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25. Serial Communications Interface (SCI)
an SCIn_RXI interrupt request to activate the DTC.
In reception, setting the RIE bit to 1 allows an SCIn_RXI interrupt request to be generated. The DTC is activated by an
SCIn_RXI interrupt request if the SCIn_RXI interrupt request is specified as a source of DTC activation beforehand,
allowing the transfer of receive data.
If an error occurs during reception and either the ORER or PER flag in SSR_SMCI is set to 1, a receive error interrupt
(SCIn_ERI) request is generated. Clear the error flag after the error occurrence. If an error occurs, the DTC is not
activated and receive data is skipped. Therefore, the number of bytes of receive data specified in the DTC is transferred.
If a parity error occurs and the PER flag is set to 1 during reception, the receive data is transferred to RDR, therefore
allowing the data to be read.
When a reception is forced to terminate by setting SCR_SMCI.RE to 0 during operation, read the RDR register because
the received data that is not yet read might be left in the RDR.
Note:
For operations in block transfer mode, see section 25.3.9, Serial Data Reception in Asynchronous Mode.
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(n + 1)-th transfer
frame
Retransfer frame
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Ds D0 D1 D2 D3 D4
SCIn_RXI interrupt signal
[2]
[4]
[1]
[3]
SSR_SMCI.PER flag
Figure 25.55
Data retransfer operation in SCI reception mode with data retransfer operation during reception
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25. Serial Communications Interface (SCI)
Start
Initialization
Start data reception
SSR_SMCI.ORER = 0 and
SSR_SMCI.PER = 0?
No
Yes
No
Error processing
SCIn_RXI interrupt
Yes
Read data from RDR
No
All data received?
Yes
Set bits RIE and RE
in SCR_SMCI to 0
Figure 25.56
25.6.8
Example flow of smart card interface reception
Clock Output Control
When the GM bit in SMR_SMCI is set to 1, the clock output can be controlled by the CKE[1: 0] bits in SCR_SMCI. For
details on the CKE[1:0] bits, see section 25.2.12, Serial Control Register for Smart Card Interface Mode (SCR_SMCI)
(SCMR.SMIF = 1). When setting the clock output, the base clock described in section 25.6.4, Receive Data Sampling
Timing and Reception Margin is output.
Figure 25.57 shows an example timing for the clock output control when the CKE[1] bit in SCR_SMCI is set to 0 and the
CKE[0] bit in SCR_SMCI is controlled.
When the GM bit in SMR_SMCI is 0, output control by the CKE[0] bit in SCR_SMCI is immediately reflected on the
SCK pin, so there is a possibility that pulses with an unintended width might be output from the SCK pin.
When the GM bit in SMR_SMCI is 1, the clock with the same pulse width as the base clock is output even if the CKE[0]
bit in SCR_SMCI is changed.
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25. Serial Communications Interface (SCI)
Base clock
CKE[0]
When GM = 0
SCK
When GM = 1
Figure 25.57
25.7
Clock output control
Operation in Simple IIC mode
Simple I2C bus format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame after
a start condition or restart condition, a master device can specify a slave device as the partner for communications. The
currently specified slave device remains valid until a new slave device is specified or a stop condition is satisfied. The 8
data bits in all frames are transmitted in order from the MSB.
The I2C bus format and timing of the I2C bus are shown in Figure 25.58 and Figure 25.59.
7-bit address format transmission
S
SLA (7 bits)
W#
A
DATA (8 bits)
A
A/A#
P
1
7
1
1
8
1
1
1
n: Number of transfer frames
n (n = 1 or larger)
: Master device Slave device
7-bit address format reception
S
SLA (7 bits)
R
A
DATA (8 bits)
A
A#
P
1
7
1
1
8
1
1
1
: Slave device Master device
n (n = 1 or larger)
10-bit address format transmission
S
11110b + SLA
(2 bits)
W#
A
SLA (8 bits)
A
DATA (8 bits)
A
A/A#
P
1
7
1
1
8
1
8
1
1
1
n (n = 1 or larger)
10-bit address format reception
S
11110b + SLA
(2 bits)
W#
A
SLA (8 bits)
A
Sr
11110b + SLA
(2 bits)
R
A
DATA (8 bits)
A
A#
P
1
7
1
1
8
1
1
7
1
1
8
1
1
1
n (n = 1 or larger)
Figure 25.58
I2C bus format
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25. Serial Communications Interface (SCI)
MSB
LSB
SDAn
D7-D1
D0
SCLn
1-7
8
9
SLA
R/W#
A
S
Figure 25.59
D7-D1
D0
1-7
8
DATA
D7-D1
D0
1-7
8
9
A
DATA
9
A
P
I2C bus timing when SLA is 7 bits
S:
Indicates a start condition, when the master device changes the level on the SDAn line from high to low while
the SCLn line is high.
SLA:
Indicates a slave address, by which the master device selects a slave device.
R/W#: Indicates the direction of transfer (reception or transmission). The value 1 indicates to transfer from the slave
device to the master device and 0 indicates to transfer from the master device to the slave device.
A/A#: Indicates an acknowledge bit. This is returned by the slave device for master transmission and by the master
device for master reception. Return low indicates ACK and return high indicates NACK.
Sr:
Indicates a restart condition, when the master device changes the level on the SDAn line from high to low
while the SCLn line is high and after the setup time elapses.
DATA:
Indicates the data being received or transmitted.
P:
Indicates a stop condition, when the master device changes the level on the SDAn line from low to high while
the SCLn line is high.
25.7.1
Generation of Start, Restart, and Stop Conditions
Writing 1 to the IICSTAREQ bit in SIMR3 causes the generation of a start condition. The generation of a start condition
proceeds through the following operations:
The level on the SDAn line falls (from the high level to the low level) and the SCLn line is kept in the released state
The hold time for the start condition is set as half of a bit period at the bit rate determined by the BRR setting
The level on the SCLn line falls (from the high level to the low level), the IICSTAREQ bit in SIMR3 is set to 0, and
a start-condition generated interrupt is output.
Writing 1 to the IICRSTAREQ bit in SIMR3 causes the generation of a restart condition. The generation of a restart
condition proceeds through the following operations.
The SDAn line is released and the SCLn line is kept at a low level
The period at the low level for the SCLn line is set as half of a bit period at the bit rate determined by the BRR
setting
The SCLn line is released (transition from a low to a high level)
Once the high level on the SCLn line is detected, the setup time for the restart condition is set as half of a bit period
at the bit rate determined by the BRR setting
The level on the SDAn line falls (from a high level to a low level)
The hold time for the restart condition is set as half of a bit period at the bit rate determined by the BRR setting
The level on the SCLn line falls (from a high level to a low level), the IICRSTAREQ bit in SIMR3 is set to 0, and a
restart-condition generated interrupt is output.
Writing 1 to the IICSTPREQ bit in SIMR3 causes the generation of a stop condition. The generation of a stop condition
proceeds through the following operations:
The level on the SDAn line falls (from a high level to a low level) and the SCLn line is kept at the low level
The period at low level for the SCLn line is set as half of a bit period at the bit rate determined by the BRR setting
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25. Serial Communications Interface (SCI)
The SCLn line is released (transition from the low to the high level)
When a high level on the SCLn line is detected, the setup time for the stop condition is set as half of a bit period at
the bit rate determined by the BRR setting
The SDAn is released (transition from a low to a high level), the IICSTPREQ bit in SIMR3 is set to 0, and a stopcondition generated interrupt is output.
Figure 25.60 shows the timing of operations in the generation of start, restart, and stop conditions.
SCLn
SDAn
SIMR3.IICSTAREQ
SIMR3.IICRSTAREQ
SIMR3.IICSTPREQ
SIMR3.IICSDAS[1:0]
11b 01b
SIMR3.IICSCLS[1:0]
00b
Start-condition generated
interrupt request
Figure 25.60
25.7.2
01b
00b
Restart-condition generated
interrupt request
01b
11b
Stop-condition generated
interrupt request
Timing of operations in generation of start, restart, and stop conditions
Clock Synchronization
The SCLn line can be driven low if a wait is inserted by a slave device at the other side of the transfer. Setting the
IICCSC bit in SIMR2 to 1 applies control to obtain synchronization when a difference arises between the levels of the
internal SCLn clock signal and the level being input on the SCLn pin.
When the IICCSC bit in SIMR2 is set to 1, the level of the internal SCLn clock signal changes from low to high.
Counting to determine the period at a high level stops while the low level is input on the SCLn pin. Counting to
determine the period at a high level starts after the transition of the input on the SCLn pin to the high level.
The interval from the time until counting to determine the period at high level starts on the transition of the SCLn pin to
the high level is the total of the delay of SCLn output, delay for noise filtering of the input on the SCLn pin (2 or 3 cycles
of sampling clock for the noise filter), and delay for internal processing (1 or 2 cycles of PCLKB). The period at high
level of the internal SCLn clock is extended even when other devices do not place the low level on the SCLn line.
If the IICCSC bit in SIMR2 is 1, synchronization is obtained for the transmission and reception of data by taking the
logical AND of the input on the SCLn pin and the internal SCLn clock. If the IICCSC bit in SIMR2 is 0, synchronization
with the internal SCLn clock is obtained for the transmission and reception of data.
If a slave device inserts a wait period into the interval until the transition of the internal SCLn clock signal from the low
to the high level after a request for the generation of a start, restart, or stop condition is issued, the time until generation is
prolonged by that period.
If a slave device inserts a wait period after the transition of the internal SCLn clock signal from the low to the high level,
although the generation-completed interrupt is issued without stopping the waiting period, generation of the condition
itself is not guaranteed. Figure 25.61 shows an example of operations to synchronize the clocks.
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25. Serial Communications Interface (SCI)
SCLn output from the
other device
SCLn line
Internal SCLn clock
Clock driving transfer
internally
Counting of the period
at low level starts
Counting of the period
at high level starts
Counting is stopped until the SCLn
line being at the high level is
conveyed within the SCI
Figure 25.61
25.7.3
Counting of the period
at high level starts
Counting is stopped while the SCLn
line is at the low level
Example operations for clock synchronization
SDA Output Delay
The IICDL[4:0] bits in SIMR1 can be used to set a delay for output on the SDAn pin relative to the falling edges of
output on the SCLn pin. Delay settings from 0 to 31 are selectable, representing periods of the corresponding numbers of
cycles of the clock signal from the on-chip baud rate generator (derived by frequency-dividing the base clock, PCLKB,
by the divisor selected in the CKS[1:0] bits in SMR). A delay for output on the SDAn pin applies to the start condition/
restart condition/stop condition signal, 8-bit transmit data, and an acknowledge bit.
If the SDAn output delay is shorter than the time for the level on the SCLn pin to fall, the change of the output on the
SDAn pin starts while the output level on the SCLn pin is falling, creating a possibility of erroneous operation for slave
devices. Ensure that settings for the delay of output on the SDAn pin specify times greater than the time output on the
SCLn pin takes to fall (300 ns for IIC in standard mode and fast mode).
Figure 25.62 shows the timing of delays in SDAn output.
Clock signal from the on-chip
baud rate generator (internal signal)
Output on the SCLn pin
Output on the SDAn pin
(IICDL[4:0] = 00000b)
Output on the SDAn pin
(IICDL[4:0] = 00001b)
Output on the SDAn pin
(IICDL[4:0] = 00010b)
Output on the SDAn pin
(IICDL[4:0] = 00111b)
Output on the SDAn pin
(IICDL[4:0] = 01000b)
Figure 25.62
Timing of delays in SDAn output
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25.7.4
25. Serial Communications Interface (SCI)
SCI Initialization in Simple IIC Mode
Before transferring data, write the initial value 00h to SCR and initialize the interface following the example shown in
Figure 25.63.
Before making any changes to the operating mode or transfer format, be sure to set SCR to its initial value.
In simple IIC mode, the open-drain setting for the communication ports should be made on the port side.
Start of initialization
[1]
Set the I/O port to allow use (on N-channel open-drain
output pins) of the SCLn and SDAn pin functions.
Set the TIE, RIE, TE, RE, TEIE and
CKE[1:0] bits in SCR to 0
[2]
Place the SCLn and SDAn pins in the high-impedance
state until a start condition is to be generated.
[3]
Set the format for transmission and reception in SMR
and SCMR.
In SMR, set the CKS[1:0] bits to the targeted value and
set the other bits to 0.
In SCMR, set the SDIR bit to 1 and the SINV and SMIF
bits to 0.
[4]
Write the value for the targeted bit rate to BRR.
[5]
Write the value obtained by correcting a bit rate error in
MDDR. This step is not required if the BRME bit in
SEMR is cleared to 0.
[6]
Set the values in SEMR, SNFR, SIMR1, SIMR2, and
SPMR.
Set the NFEN and BRME bits in SEMR.
In SNFR, set the NFCS[2:0] bits.
In SIMR1, set the IICM bit to 1 and the IICDL[4:0] bits
as required.
In SIMR2, set the IICACKT and IICCSC bits to 1 and
the IICINTM bits as required.
In SPMR, set all the bits to 0.
[7]
Set the RE and TE bits in the SCR to 1. Then, set the
SCR.TIE, RIE, and TEIE bits (for transmission and
when the SIMR2.IICINTM bit is 1, set the RIE bit to 0).
Setting the TE and RE bits to 1 make the SCLn and
SDAn pin functions available.
Set the I/O port functions
[1]
Set the IICSDAS[1:0] and IICSCLS[1:0] bits
in SIMR3 to 11b
[2]
Set up the transfer or reception format in
SMR and SCMR
[3]
Set the value in BRR
[4]
Set a value in MDDR
[5]
Set the values in SEMR, SNFR, SIMR1,
SIMR2, and SPMR
[6]
Set the SCR.RE and TE bit to 1 and set the
SCR.TIE, RIE and TEIE bits
[7]
Start of transmission or reception
Figure 25.63
25.7.5
Example flow of SCI initialization in simple IIC mode
Operation in Master Transmission in Simple IIC mode
Figure 25.64 and Figure 25.65 show examples of master transmission and Figure 25.66 shows an example flow of data
transmission. The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts) and
the value of the SCR.RIE bit is assumed to be 0 (SCIn_RXI and SCIn_ERI interrupt requests are disabled). See Table
25.29 for more information on the STI interrupt.
When 10-bit slave addresses are in use, steps [3] and [4] in Figure 25.66 are repeated twice.
In simple IIC mode, the transmit data empty interrupt (SCIn_TXI) is generated when communication of one frame is
complete, unlike the SCIn_TXI interrupt request generation timing during clock synchronous transmission.
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Start condition
25. Serial Communications Interface (SCI)
Slave address (7 bits)
Transmitted data
W#
Stop condition
SCLn
D7
SDAn
D6
D1
D0
ACK
D7
D6
D1
D0
ACK/NACK
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Acceptance of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
STI interrupt flag
(IELSRn.IR*1)
Generation of STI interrupt
Acceptance of request
Reception of ACK
SISR.IICACKR flag
Generation of request
Reception of NACK
Reception of ACK
Note 1.
Figure 25.64
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example 1 operation for master transmission in simple IIC bus mode with 7-bit slave addresses,
transmission interrupts, and reception interrupts
When the SIMR2.IICINTM bit is set to 0 (use ACK/NACK interrupts) during master transmission, the DTC is activated
by the ACK interrupt as the trigger and required number of data bytes are transmitted. When a NACK is received, error
processing such as transmission stop and retransmission, is performed using the NACK interrupt as the trigger.
Start condition
Slave address (7 bits)
Transmitted data
W#
Stop condition
SCLn
SDAn
D7
D6
D1
D0
ACK
D7
D6
D1
D0
NACK
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Generation of SCIn_TXI
interrupt request
SCIn_RXI interrupt flag
(IELSRn.IR*1)
Generation of SCIn_RXI
interrupt request
STI interrupt flag
(IELSRn.IR*1)
Generation of STI interrupt request
Note 1.
Figure 25.65
Acceptance of STI interrupt request
Acceptance of SCIn_TXI
interrupt request
Acceptance of SCIn_RXI
interrupt request
Generation of STI interrupt request
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example 2 operation for master transmission in simple IIC bus mode with 7-bit slave addresses,
ACK interrupts, and NACK interrupts
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25. Serial Communications Interface (SCI)
[1]
Initialization
For transmission, set the SCR.RIE to 0 to disable the
RXI and ERI interrupts.
Start of transmission
Simultaneously set the SIMR3.IICSTAREQ bit to
1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt
[ 1 ] Initialization in simple IIC mode:
[2]
[ 2 ] Generate a start condition.
No
Yes
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 00b
[ 3 ] Writing to TDR:
Write the slave address and value for the R/W bit to TDR.
[3]
Write the slave address and value for the
R/W bit in TDR
No
SCIn_TXI interrupt
[ 4 ] Confirming ACK response from the slave device:
Check the SISR.IICACKR bit. If SISR.IICACKR is 0, it
indicates that the slave device responded with ACK and
operations proceed. If SISR.IICACKR is 1, it indicates that
there was no response from the slave device so the next
transition is to generate a stop condition.
Yes
No
SISR.IICACKR = 0
[4]
If 10-bit slave addresses are in use, processing of [3] and [4]
is repeated twice.
Yes
Write transmit data in TDR
No
SCIn_TXI interrupt
Yes
No
All data transmitted
[5]
[ 5 ] Continuing with serial transmission:
When transmission is to continue, write additional
transmit data to TDR. Except for the first data to be
transmitted, a TXI interrupt request can activate
the DTC to handle writing of data to TDR.
[6]
[ 6 ] Generate a stop condition.
Yes
Simultaneously set the SIMR3.IICSTPREQ bit to
1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt
No
Yes
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 11b
End
Note:
Figure 25.66
In simple IIC mode, the SCIn_TXI interrupt is generated when communication completes
Example procedure for master transmission in simple IIC mode with transmission interrupts and
reception interrupts
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25.7.6
25. Serial Communications Interface (SCI)
Master Reception in Simple IIC Mode
Figure 25.67 shows an example operation in simple IIC mode master reception and Figure 25.68 shows an example flow
of master reception.
The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts).
In simple IIC mode, the transmit data empty interrupt (SCIn_TXI) is generated when communication of one frame is
complete, unlike the SCIn_TXI interrupt request generation timing during clock synchronous transmission.
Start
condition
Slave address (7 bits)
Stop condition
Received data
R
SCLn
D7
SDAn
D6
D1
D0
ACK
D7
D6
D1
D0
NACK
SCIn_RXI interrupt flag
(IELSRn.IR*1)
SCIn_TXI interrupt flag
(IELSRn.IR*1)
SCIn_RXI is assumed to have been disabled
by setting SCR.RIE = 0.
Generation of SCIn_RXI interrupt request
Acceptance of SCIn_TXI interrupt request
Generation of SCIn_TXI interrupt request
STI interrupt flag
(IELSRn.IR*1)
Generation of SCIn_TXI interrupt request
Acceptance of STI interrupt request
Generation of STI interrupt request
Generation of STI interrupt request
Note 1.
Figure 25.67
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Example operation for master reception in simple IIC bus mode with 7-bit slave addresses,
transmission interrupts, and reception interrupts
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25. Serial Communications Interface (SCI)
[1]
Initialization
Start of reception
[ 2 ] Generate a start condition.
Simultaneously set the SIMR3.IICSTAREQ bit
to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt
[2]
No
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 00b
Write the slave address and value for
the R/W bit to TDR
[3]
No
Yes
SISR.IICACKR = 0
[ 3 ] Writing to TDR:
Write the slave address and value for the R/W bit to TDR.
[ 4 ] Confirming ACK response from the slave device:
Check the SISR.IICACKR bit. If SISR.IICACKR is 0, it
indicates that the slave device responded with ACK
and operations proceed. If SISR.IICACKR is 1, it
indicates that there was no response from the slave
device so the next transition is to generate the stop
condition.
Yes
SCIn_TXI interrupt
[ 1 ] Initialization in simple IIC mode:
Set the RIE bit in SCR to 0.
[ 5 ] Continuing with reception:
To continue with reception, write FFh as dummy transit
data to TDR. Other than in the first and last rounds of
transmission, a TXI request can activate DMAC or DTC
to handle writing of data to TDR. Also, for data other
than the last data to be received, an RXI request can
activate DMAC or DTC to handle reading of data from
RDR.
[ 6 ] NACK is transmitted in response to the last data.
No
[4]
[ 7 ] Generate a stop condition.
Yes
Set SIMR2.IICACKT to 0
Set SCR.RIE to 1
Next data is the last
Yes
[5]
No
Set SIMR2.IICACKT to 1
[6]
Write FFh as dummy data to TDR
Write FFh as dummy data to TDR
SCIn_RXI interrupt
No
SCIn_RXI interrupt
No
Yes
Yes
Read received data from RDR
SCIn_TXI interrupt
Yes
Read received data from RDR
No
SCIn_TXI interrupt
No
Yes
Simultaneously set the SIMR3.IICSTPREQ bit to
1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt
[7]
No
Yes
Set the SIMR3.IICSTIF flag to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 11b
End
Note:
Figure 25.68
In simple IIC mode, the TXI interrupt request is generated when communication is complete.
Example flow of master reception in simple IIC mode with transmission interrupts and reception
interrupts
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25.8
25. Serial Communications Interface (SCI)
Operation in Simple SPI mode
As an extended function, the SCI supports a simple SPI mode that handles transfer among one or multiple master devices
and multiple slave devices.
Using the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) plus setting the SSE
bit in the SPMR to 1 places the SCI in simple SPI mode. However, the SSn pin function on the master side is not required
for connection of the device used as the master in simple SPI mode when the configuration only has a single master,
therefore set the SSE bit in the SPMR to 0 in such cases.
Figure 25.69 shows an example of connections for simple SPI mode. Control a general port pin to produce the SSn
output signal from the master.
In simple SPI mode, data is transferred in synchronization with clock pulses in the same way as in clock synchronous
mode. One character of data for transfer consists of 8 bits of data, and parity bits cannot be appended to this. The data can
be inverted by setting the SCMR.SINV bit to 1.
Because the receiver and transmitter are independent of each other within the SCI module, full-duplex communications
are possible, with a common clock signal. Additionally, because both the transmitter and receiver have a buffered
structure, writing the next transmit data while transmission is in progress and reading previously received data while
reception is in progress are both possible. This enables continuous transfer.
Device 2 (slave)
Device 1 (master)
Port pin (output)
SSn (input)
Port pin (output)
SSn (input)
*1
SCKn (input)
SCKn (output)
MISOn (output)
MISOn (input)
MOSIn (input)
MOSIn (output)
Device 3 (slave)
SSn (input)
SCKn (input)
MISOn (output)
MOSIn (input)
Note 1. The SSn input is not required in a single-master system
(the interface is used with the setting SPMR.SSE = 0).
Figure 25.69
25.8.1
Example connections using simple SPI mode in single master mode with SPMR.SSE bit = 0
States of Pins in Master and Slave Modes
The direction (input or output) of pins for the simple SPI mode interface differs according to whether the device is a
master (SCR.CKE[1:0] = 00b or 01b and SPMR.MSS = 0) or slave (SCR.CKE[1:0] = 10b or 11b and SPMR.MSS = 1).
Table 25.25 lists the relationship between the pin states, mode, and level on the SSn pin.
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Table 25.25
25. Serial Communications Interface (SCI)
States of pins by mode and input level on SSn pin
Mode
Input on SSn pin
State of TXDn pin
State of RXDn pin
State of SCKn pin
Master mode*1
High level
(transfer can proceed)
Output for data
transmission*2
Input for received data
Clock output*3
Low level
(transfer cannot proceed)
High-impedance
Input for received data
(but disabled)
High-impedance
High level
(transfer cannot proceed)
Input for received data
(but disabled)
High-impedance
Clock input
(but disabled)
Low level
(transfer can proceed)
Input for received data
Output for data
transmission
Clock input
Slave mode
Note 1. When there is only a single master (SPMR.SSE = 0), transfer is possible regardless of the input level on the SSn
pin. This is equivalent to input of a high level on the SSn pin. Because the SSn pin function is not required, the pin
is available for other purposes.
Note 2. The MOSIn pin output is in the high-impedance state when serial transmission is disabled (SCR.TE bit = 0).
Note 3. The SCKn pin output is in the high-impedance state when serial transmission is disabled (SCR.TE and RE bits =
00b) in a multimaster configuration (SPMR.SSE = 1).
25.8.2
SS Function in Master mode
Setting the CKE[1:0] bits in the SCR to 00b and the MSS bit in the SPMR to 0 selects master operation. The SSn pin is
not used in single-master configurations (SPMR.SSE = 0), so transmission or reception can proceed regardless of the
value of the SSn pin.
When the level on the SSn pin is high in a multi-master configuration (SPMR.SSE = 1), a master device outputs clock
signals from the SCKn pin before starting transmission or reception to indicate that there are no other masters or another
master is performing reception or transmission. When the level on the SSn pin is low in a multi-master configuration
(SPMR.SSE = 1), there are other masters, and this indicates that transmission or reception is in progress. At this time the
MOSIn output and SCKn pins are placed in the high-impedance state and starting transmission or reception is not
possible. Additionally, the value of the SPMR.MFF bit is 1, indicating a mode fault error. In a multi-master
configuration, start error processing by reading SPMR.MFF flag. Even if a mode fault error occurs while transmission or
reception is in progress, transmission or reception is not stopped, but the MOSIn and SCKn pin output are placed in the
high-impedance state after completion of the transfer. Control a general port pin to produce the SS output signal from the
master.
25.8.3
SS Function in Slave mode
Setting the CKE[1:0] bits in the SCR to 10b and the MSS bit in the SPMR to 1 selects slave operation. When the SSn pin
is high, the MISOn output pin is in the high-impedance state and clock input through the SCKn pin is ignored. When the
SSn pin is low, clock input through the SCKn pin is effective and transmission or reception can proceed.
If the input on the SSn pin changes from low to high during transmission or reception, the MISOn output pin is placed in
the high-impedance state. Meanwhile, the internal processing for transmission or reception continues at the rate of the
clock input through the SCKn pin until processing for the character currently being transmitted or received is complete,
after which it stops, and the appropriate interrupt (SCIn_TXI, SCIn_RXI, or SCIn_TEI) is generated.
25.8.4
Relationship between Clock and Transmit/Receive Data
The CKPOL and CKPH bits in the SPMR can be used to set up the clock for use in transmission and reception in four
different ways. The relation between the clock signal and the transmission and reception of data is shown in Figure
25.70. The relation is the same for both master and slave operation. This is the same as when the level on the SSn pin is
high.
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25. Serial Communications Interface (SCI)
One unit of transfer data (character or frame)
(1) When CKPH = 0
SSn pin
(slave)
SCKn pin
(CKPOL = 0)
SCKn pin
(CKPOL = 1)
MOSIn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MISOn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CKPH = 1
SSn pin
(slave)
SCKn pin
(CKPOL = 0)
SCKn pin
(CKPOL = 1)
MOSIn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MISOn pin
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 25.70
25.8.5
Relation between clock signal and transmit or receive data in simple SPI mode
SCI Initialization in Simple SPI Mode
Initialization in simple SPI mode is the same as in clock synchronous mode. See Figure 25.32 for an example
initialization flow. The CKPOL and CKPH bits in the SPMR must be set to ensure that the clock signal is suitable for
both master and slave devices.
Always initialize the SCR register before making any changes to the operating mode or transfer format.
Note 1. Only the RE bit is set to 0. The SSR.ORER, FER, PER, and RDR flags are not initialized.
Note 2. Changing the value of the TE bit from 1 to 0 or from 0 to 1 leads to the generation of a transmit data empty
interrupt (SCIn_TXI) if the value of the TIE bit in the SCR is 1 at the time.
25.8.6
Transmission and Reception of Serial Data in Simple SPI Mode
In master operation, ensure that the SSn pin of the slave device on the other side of the transfer is at a low level before
starting the transfer and at a high level on completion of the transfer. Otherwise, the procedures are the same as in clock
synchronous mode.
25.9
Bit Rate Modulation Function
Using the bit rate modulation function, the bit rate can be evenly corrected using the number specified in the MDDR
register when the PCLKB is selected in the CKS[1:0] bits in SMR/SMR_SMCI.
Figure 25.71 shows an example where the PCLKB is selected by the CKS[1:0] bits in SMR/SMR_SMCI and the BRR
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25. Serial Communications Interface (SCI)
and MDDR are set to 0 and 160 respectively, in asynchronous mode. In this example, the cycle of the base clock is
evenly corrected (256/160) and the bit rate is also corrected (160/256).
Note:
Enabling an internal clock causes bias and expansion. Contraction is generated in the pulse width of the internal
base clock.
Do not use this function in clock synchronous mode and in the highest speed settings in simple SPI mode
(SMR.CKS[1:0] = 00b, SCR.CKE[1] = 0, and BRR = 0).
Internal clock
(bit rate counter input)
Internal base clock
Transmit/receive data
1-bit interval is 16 cycles of the internal base clock.
(a) When the bit modulation function is not used
160 clocks among 256 clocks are evenly enabled (96 clocks are disabled) by setting MDDR.
Internal clock
(bit rate counter input)
Internal base clock
Transmit/receive data
1-bit interval is 16 cycles of the internal base clock.
This figure shows an example when 1-bit interval is corrected to 52/32. (1-bit interval is evenly corrected to 256/160.)
(b) The bit rate is corrected (160/256) using the bit rate modulation function
Figure 25.71
Example internal base clock when bit rate modulation function is used
25.10 Interrupt Sources
25.10.1
Buffer Operations for SCIn_TXI and SCIn_RXI Interrupts (non-FIFO selected)
If the conditions for an SCIn_TXI and SCIn_RXI interrupt are satisfied while the interrupt status flag in the Interrupt
Controller Unit is 1, the ICU does not output the interrupt request but retains it internally with a capacity for retention of
one request per source.
When the interrupt status flag in the ICU is 0, the interrupt request retained within the ICU is output. The internally
retained interrupt request is automatically discarded when the actual interrupt is output. Clearing of the associated
interrupt enable bit (the TIE or RIE bit in the SCR/SCR_SMCI) can also be used to discard an internally retained
interrupt request.
25.10.2
Buffer Operations for SCIn_TXI and SCIn_RXI Interrupts (FIFO selected)
Even when an interrupt status flag in the ICU is set to 1, the SCIn_TXI and SCIn_RXI interrupts do not output interrupt
requests to the ICU. When an interrupt status flag of the interrupt controller is set to 0, and if the conditions for an
SCIn_TXI and SCIn_RXI interrupts are satisfied, an interrupt request is generated.
25.10.3
(1)
Interrupts in Asynchronous, Clock Synchronous, and Simple SPI Modes
Non-FIFO selected
Table 25.26 lists interrupt sources in asynchronous mode, clock synchronous mode, and simple SPI mode. A different
interrupt vector can be assigned to each interrupt source. Individual interrupt sources can be enabled or disabled with the
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25. Serial Communications Interface (SCI)
enable bits in SCR.
If the SCR.TIE bit is 1, an SCIn_TXI interrupt request is generated when transmit data is transferred from the TDR or
TDRHL register*1 to the TSR. An SCIn_TXI interrupt request can also be generated using a single instruction to set the
SCR.TE and SCR.TIE bits to 1 simultaneously. An SCIn_TXI interrupt request can activate the DTC to handle data
transfer.
An SCIn_TXI interrupt request is not generated by setting the SCR.TE bit to 1 when SCR.TIE is 0 or by setting SCR.TIE
to 1 when SCR.TE is 1.*2
When new data is not written by the time of transmission of the last bit of the current transmit data and SCR.TEIE is 1,
the SSR.TEND flag becomes 1 and an SCIn_TEI interrupt request is generated. Additionally, when SCR.TE is 1, the
SSR.TEND flag retains the value 1 until more transmit data are written to the TDR or TDRHL register*1, and setting
SCR.TEIE to 1 leads to the generation of an SCIn_TEI interrupt request.
Writing data to the TDR or TDRHL register*1 leads to clearing of the SSR.TEND flag and, after a certain time,
discarding of the SCIn_TEI interrupt request.
If the SCR.RIE bit is 1, an SCIn_RXI interrupt request is generated when received data is stored in the RDR. An
SCIn_RXI interrupt request can activate the DTC to handle data transfer.
Setting any of the ORER, FER, and PER flags in the SSR to 1 when the SCR.RIE bit is 1 leads to the generation of an
SCIn_ERI interrupt request. An SCIn_RXI interrupt request is not generated at this time. Clearing all three flags (ORER,
FER, and PER) leads to discarding of the SCIn_ERI interrupt request.
(2)
FIFO selected
Table 25.26 lists interrupt sources in FIFO selected mode.
If the SCR.TIE bit is 1, an SCIn_TXI interrupt request is generated when the stored number of data in the FTDRL
register becomes the threshold value indicated in FCR.TTRG or below. An SCIn_TXI interrupt request can also be
generated using a single instruction to set the SCR.TE and SCR.TIE bits to 1 at the same time.
An SCIn_TXI interrupt request is not generated by setting SCR.TE to 1 when SCR.TIE is 0 or by setting SCR.TIE to 1
when SCR.TE is 1.
If SCR.TEIE bit is 1 and if the next data is not written to the FTDRL register by the time the last bit of the transmit data
is sent, the SSR_FIFO.TEND flag is set to 1 and the SCIn_TEI interrupt request is generated.
If SCR.RIE is 1, the SCIn_RXI interrupt request is generated when the stored number of data in the FRDRL register is
equal to or greater than the threshold value indicated in FCR.RTRG. When RTRG is 0, an SCIn_RXI interrupt does not
occur even when the amount of data in the receive FIFO is equal to 0.
If the SCR.RIE bit is 1, when the SSR_FIFO.ORER flag is set to 1 or data with a framing error or a parity error is stored
in the FRDRL register, the SCIn_ERI interrupt request is generated. When the amount of data stored in the FRDRL
register at this time is at the threshold value or above, the SCIn_RXI interrupt request is also generated. The SCIn_ERI
interrupt request can be canceled in which case SSR_FIFO.ORER, FER, and PER flags are all cleared.
Note 1. When asynchronous mode and 9-bit data length are selected.
Note 2. To temporarily prohibit SCIn_TXI interrupts on transmission of the last of the data when a new round of
transmission is to be started, after handling the transmission-completed interrupt, control activation of the
interrupt by using the interrupt request enable bit in the Interrupt Controller Unit rather than using the SCR.TIE
bit. This approach can prevent the suppression of SCIn_TXI interrupt requests in the transfer of new data.
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Table 25.26
Name
25. Serial Communications Interface (SCI)
SCI interrupt sources with non-FIFO selected
Interrupt source
error*1
Interrupt flag
Interrupt enable
DTC activation
ORER, FER, PER, DFER, DPER
RIE
Not possible
SCIn_ERI
Receive
SCIn_RXI
Receive data full
RDRF
RIE
Possible
Address match
DCMF
RIE
Possible
SCIn_AM
Address match
DCMF
—
Possible
SCIn_TXI
Transmit data empty
TDRE
TIE
Possible
SCIn_TEI
Transmit end
TEND
TEIE
Not possible
Note 1. The interrupt flag is only ORER when in clock synchronous and simple SPI modes.
Table 25.27
Name
SCI interrupt sources with FIFO selected
Interrupt source
error*1
Interrupt flag
Interrupt enable
DTC activation
ORER, FER, PER, DFER, DPER
RIE
Not possible
SCIn_ERI
Receive
DR (when FCR.DRES = 1)
RIE
Not possible
SCIn_RXI
Receive data full
RDF
RIE
Possible
Receive data ready
DR (when FCR.DRES = 0)
RIE
Possible
Address match
DCMF
RIE
Possible
SCIn_AM
Address match
DCMF
—
Possible
SCIn_TXI
Transmit data empty
TDFE
TIE
Possible
SCIn_TEI
Transmit end
TEND
TEIE
Not possible
Note 1. The interrupt flag is only ORER when in clock synchronous and simple SPI modes.
25.10.4
Interrupts in Smart Card Interface Mode
Table 25.28 lists interrupt sources in smart card interface mode. A transmit end interrupt (SCIn_TEI) request and an
address match (SCIn_AM) request cannot be used in this mode.
Table 25.28
SCI interrupt sources in smart card interface mode
Name
Interrupt source
Interrupt flag
Interrupt enable
DTC activation
SCIn_ERI
Receive error or error signal detection
ORER, FER, ERS
RIE
Not possible
SCIn_RXI
Receive data full
RDRF
RIE
Possible
SCIn_TXI
Transmit end
TEND
TIE
Possible
Data transmission or reception using the DTC is also possible in smart card interface mode. In transmission, when the
TEND flag in SSR_SMCI is set to 1, an SCIn_TXI interrupt request is generated. This SCIn_TXI interrupt request
activates the DTC allowing transfer of transmit data if the SCIn_TXI request is specified beforehand as a source of DTC
activation. The TEND flag is automatically set to 0 when the DTC transfers the data.
If an error occurs, the SCI automatically retransmits the same data. During the retransmission, the TEND flag is kept to 0
and the DTC is not activated. Therefore, the SCI and DTC automatically transmit the specified number of bytes,
including retransmission when errors occur. However, the ERS flag in SSR_SMCI is not automatically cleared to 0 at
error occurrence. Therefore, the ERS flag must be cleared by setting the RIE bit in SCR_SMCI to 1 to enable an
SCIn_ERI interrupt request to be generated at error occurrence.
When transmitting or receiving data using the DTC, be sure to enable the DTC before setting the SCI. For DTC settings,
see section 14, Data Transfer Controller (DTC).
In reception, an SCIn_RXI interrupt request is generated when receive data is set to RDR. The SCIn_RXI interrupt
request activates the DTC allowing the transfer of receive data if the SCIn_RXI request is previously specified as a
source of DTC activation. If an error occurs, the error flag is set. Therefore, the DTC is not activated and an SCIn_ERI
interrupt request is issued to the CPU instead. The error flag must be cleared.
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25.10.5
25. Serial Communications Interface (SCI)
Interrupts in Simple IIC Mode
Table 25.29 lists the interrupt sources in simple IIC mode. The STI interrupt is allocated to the transmit end interrupt
(SCIn_TEI) request. The receive error interrupt (SCIn_ERI) and the address match (SCIn_AM) request cannot be used.
The DTC can also be used to handle transfer in simple IIC mode.
When the SIMR2.IICINTM bit is 1, an SCIn_RXI request is generated on the falling edge of the SCLn signal for the 8th
bit. If SCIn_RXI is previously set up as an activation source for the DTC, the SCIn_RXI request activates the DTC to
handle transfer of the received data. Additionally, an SCIn_TXI request is generated on the falling edge of the SCLn
signal for the 9th bit (acknowledge bit). If SCIn_TXI is previously set up as an activation source for the DTC, the
SCIn_TXI request activates the DTC to handle transfer of the transmit data.
When the SIMR2.IICINTM bit is 0:
An SCIn_RXI request (ACK detection) is generated if the input on the SDAn pin is at the low level on the rising
edge of the SCLn signal for the 9th bit (acknowledge bit). If the SCIn_RXI is previously set up as an activation
source for the DTC, the SCIn_RXI request activates the DTC to handle transfer of the received data.
An SCIn_TXI request (NACK detection) is generated if the input on the SDAn pin is at the high level on the rising
edge of the SCLn signal for the 9th bit (acknowledge bit).
If the DTC is used for data transfer in reception or transmission, be sure to set up and enable the DTC before setting up
the SCI.
When the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits in SIMR3 are used to generate a start condition, restart
condition, or stop condition, the STI request is issued when generation is complete.
Table 25.29
SCI interrupt sources in simple IIC mode
Name
Interrupt source
Interrupt flag
Interrupt enable
DTC activation
SCIn_RXI
Reception, ACK detection
—
RIE
Possible
SCIn_TXI
Transmission, NACK detection
—
TIE
Possible
STIn
Completion of generation of a start, restart,
or stop condition
IICSTIF
TEIE
Not possible
Note:
Activation of the DTC is only possible when the SIMR2.IICINTM bit is 1 (use reception and transmission
interrupts).
25.11 Event Linking
By using interrupt request signals as event signals, the SCI can provide linked operation through the Event Link
Controller (ELC) for modules selected in advance.
Event signals can be output regardless of the values of the associated interrupt request enable bits.
(1)
Error event output (receive error or error signal detected)
Indicates abnormal termination because of a parity error during reception in asynchronous mode
Indicates abnormal termination because of a framing error during reception in asynchronous mode
Indicates abnormal termination because of an overrun error during reception
Indicates detection of the error signal during transmission in smart card interface mode
The SSR_FIFO.FER and PER flags are 0, and receive data less than the receive FIFO data trigger number is set in a
reception FIFO buffer, and it indicates that time of 15 ETUs elapse when FIFO is selected and the FCR.DRES bit is
1.
(2)
Receive data full event output
Indicates that ACK is detected if the SIMR2.IICINTM bit is 0 in simple IIC mode
Indicates that the 8th bit SCLn falling edge is detected if the SIMR2.IICINTM bit is 1 in simple IIC mode
When the SIMR2.IICINTM bit is 1 during master transmission in simple IIC mode, set the ELC so that receive data
full events are not used.
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(a)
25. Serial Communications Interface (SCI)
Non-FIFO selected
Indicates that received data is set in the Receive Data Register (RDR or RDRHL).
(b)
FIFO selected
Using this event output is prohibited.
(3)
Transmit data empty event output
Indicates that the SCR/SCR_SMCI.TE bit has changed from 0 to 1
Indicates that transmission is complete in smart card interface mode
Indicates that NACK is detected if the SIMR2.IICINTM bit is 0 in simple IIC mode
Indicates that the 9th bit SCLn falling edge is detected if the SIMR2.IICINTM bit is 1 in simple IIC mode.
(a)
Non-FIFO selected
Indicates that transmit data is transferred from the Transmit Data Register (TDR or TDRHL) to the Transmit Shift
Register (TSR).
(b)
(4)
FIFO selected
Using this event output is prohibited.
Transmit end event output
Indicates the completion of transmission
Indicates that the starting condition, resumption condition, or termination condition is generated in simple IIC
mode.
Note:
(5)
When FIFO is selected, using this event output is prohibited.
Address match event output
Address match event output indicates a match of the comparison data (CDR.CMPD) with one frame of receive data
when DCCR.DCME is set to 1 in asynchronous mode, including multi-processor mode.
(6)
Address Mismatch Event Output (SCI0_DCUF)
SCI0_DCUF indicates a mismatch of the comparison data (CDR.CMPD) with receive data that is one frame of the data
that is received when DCCR.DCME is set to 1 in asynchronous mode, including multi-processor mode. This event can
be used for snooze end request only.
25.12 Noise Cancellation Function
Figure 25.72 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of a 2-stage
flip-flop circuit and a match detection circuit. When the input signals of the noise filter and the output signals of the 2stage flip-flop circuits completely match, the matched level is conveyed as an internal signal. Unless otherwise matched,
the previous value is retained. When the same level is retained for 3 cycles or longer on the sampling clock of the noise
filter, it is considered a valid receive signal. A change in pulse for 3 cycles or shorter is considered as noise, not as a
receive signal.
When SEMR.ABCS = 0 and SEMR.ABCSE = 0, the cycle is 1/16 of a period 1 transfer bit.
When SEMR.ABCS = 1 and SEMR.ABCSE = 0, the cycle is 1/8 of a period 1 transfer bit.
When SEMR.ABCSE = 1, the cycle is 1/6 of a period 1 transfer bit.
In asynchronous mode, the noise cancellation function can be applied to the receive signal input to the RXDn pin. The
receive level of the RXDn is taken from the flip-flop circuit of the noise filter on the base clock of asynchronous mode.
In simple IIC mode, the noise cancellation function can be used for the input terminals of SDAn and SCLn. The
sampling clock for the noise cancellation function is selected in the SNFR.NFCS bit by dividing the baud rate generator
source clock by 1, 2, 4, or 8.
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25. Serial Communications Interface (SCI)
If the base clock stops once with the noise filter enabled and then the base clock input restarts again, the noise filter
operation resumes from the state where the clock stopped. When SCR.TE and SCR.RE are set to 0 during base clock
input, all of the noise filter flip-flop values are initialized to 1. Accordingly, if the input data is 1 when reception
operation resumes, the function determines that a level match is detected and the result is considered an internal signal.
When the input level corresponds to 0, the initial output of the noise filter is retained until the level matches in three
consecutive sampling cycles.
TXDn/SDAn,
RXDn/SCLn
Internal signal
Un-match
match
cmp
TXDn/SDAn,
RXDn/SCLn
inputs
Baud rate generator
Clock source
Base clock of
Asynchronous mode
D
1 div
2 div
4 div
8 div
Q
CLK
D
D
CLK
Q
CLK
NFCS[2:0] bits
Figure 25.72
Q
NFEN bit
Digital noise filter circuit block diagram
25.13 Usage Notes
25.13.1
Settings for the Module-Stop State
The Module Stop Control Register B (MSTPCRB) can enable or disable SCI operation. The SCI is initially stopped after
reset. Releasing the module-stop state enables access to the registers. For details, see section 10, Low Power Modes.
25.13.2
(1)
SCI Operations during Low Power State
Transmission
When setting the module to the stopped state or in transitions to Software Standby mode, stop the operations (by setting
the TIE, TE, and TEIE bits in the SCR/SCR_SMCI to 0) after switching the TXDn pin to the general I/O port pin
function. When setting I/O port as an SCI function, the SPTR register can control the state of the TXDn pin. Setting the
TE bit to 0 initializes the TSR register and the TEND bit in the SSR/SSR_SMCI is initialized to 1 with non-FIFO
selected. The value is kept with FIFO selected. Depending on the port settings and SPTR register settings, output pins
might output the level before a transition to the low power state is made after release from the module-stop state or
Software Standby mode. When transitions to these states are made during transmission, the transmitted data becomes
indeterminate.
To transmit data in the same transmission mode after cancellation of the low power state:
1. Set the TE bit to 1.
2. Read SSR/SSR_FIFO/SSR_SMCI.
3. Write data to TDR sequentially to start data transmission.
To transmit data with a different transmission mode, initialize the SCI first.
Figure 25.73 shows an example flow of transition to Software Standby mode during transmission. Figure 25.74 and
Figure 25.75 show the port pin states during transition to Software Standby mode.
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25. Serial Communications Interface (SCI)
Before specifying the module-stop state or making a transition to Software Standby mode from the transmission mode
using DTC transfer, stop the transmit operations (TE = 0). To start transmission after cancellation using the DTC, set the
TE bit to 1. The SCIn_TXI interrupt flag is set to 1 and transmission starts using the DTC.
(2)
Reception
(a)
When address match function is not used as wake-up condition
Before specifying the module-stop state or making a transition to Software Standby mode, stop the receive operations
(RE = 0 in SCR/SCR_SMCI). If transition is made during data reception, the received data is invalid.
Figure 25.76 shows an example flow of transition to Software Standby mode during reception.
(b)
When address match function is used as wake-up condition
Before specifying the module-stop state or making a transition to Software Standby mode:
1. Set the operations after cancellation of the low power state.
2. Set CDR.CMPD and DCCR.DCME to 1.
3. Set the receive operations (RE = 1 in SCR/SCR_SMCI).
4. Set the module-stop state or Software Standby mode.
When SCI transfers to the low power mode, if the receive data pin (RXD) is at the low level, set SEMR.RXDESEL to 0.
When setting it as SEMR.RXDESEL to 1, there is a possibility that a start bit (fall edge of RXDn pin) cannot be detected
on release of the low power mode.
Figure 25.77 shows an example flow of transition to Software Standby mode during reception with address match.
(c)
When using SCI0 in Snooze mode
When using SCI0 in Snooze mode, some restrictions, including the maximum bit rates, exist. For details, see section 10,
Low Power Modes.
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25. Serial Communications Interface (SCI)
Data transmission
No
All data transmitted?
[1]
[1]
Transmitted data is lost halfway. Data can be
normally transmitted from the CPU by setting the TE
bit in SCR/SCR_SMCI to 1, reading SSR/SSR_FIFO/
SSR_SMCI, and writing in Software Standby mode.
However, if the DTC is activated, the data remaining
in the DTC is transmitted when both the TE and TIE
bits in SCR/SCR_SMCI are set to 1.
[2]
Set the I/O port function and SPTR register to switch
the TXDn pin to operate as a general I/O port.
[3]
Set SCR/SCR_SMCI.TE bit to 0. If SCR/
SCR_SMCI.TIE = 1 and SCR/SCR_SMCI.TEIE = 1,
these are set to 0 simultaneously with the SCR.TE
bit.
[4]
This includes the setting for the module-stop state.
Yes
Read TEND flag in SSR/SSR_FIFO/SSR_SMCI
No
SSR/SSR_FIFO/SSR_SMCI.TEND = 1
Yes
Set the I/O port function and
SPTR register
[2]
SCR/SCR_SMCI.TE bit = 0
[3]
Make transition to Software Standby mode
[4]
Cancel Software Standby mode
Change operating mode?
Yes
Initialization
No
Set the I/O port function
SCR/SCR_SMCI.TE bit = 1
Start data transmission
Figure 25.73
Example flow of transition to Software Standby mode during transmission
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25. Serial Communications Interface (SCI)
Transition to
Software Standby
mode
Software Standby mode
canceled
PmnPFS.PMR bit setting
(TXDn pin function setting)
SPTR.SPB2IO bit
SCR/SCR_SMCI.TE bit
The level at transition to
Software Standby mode is
retained
SCKn output pin
TXDn output pin
Port input/output
Port
SCI TXDn output
The TXDn output pin state
(low or high level) after
PmnPFS.PMR bit setting is
set as a SPTR register.
Figure 25.74
The level before transition to
Software Standby mode is
output
Stop
High output
The TXDn pin status when
TE = 0, can be controlled by
SPTR register
SPTR.SPB2DT bit set value
Port pin states during transition to Software Standby mode with internal clock and
asynchronous transmission
Transition to Software
Standby mode
Software Standby
mode canceled
PmnPFS.PMR bit
setting
SCR/SCR_SMCI.TE bit
SCKn output pin
TXDn output pin
Port input/output
Port
Figure 25.75
Last TXD bit retained
Marking output
SCI TXDn output
Port input/output
Port
The level before transition to
Software Standby mode is output
SCI TXDn output
Port pin states during transition to Software Standby mode with internal clock and clock
synchronous transmission
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25. Serial Communications Interface (SCI)
Data reception
SCIn_RXI interrupt
No
[1]
[ 1 ] Received data is invalid
Yes
Read receive data in RDR
SCR/SCR_SMCI.RE = 0
Transition to Software Standby mode
[2]
[ 2 ] Setting for the module stop state is included
Cancel Software Standby mode
Change operating mode?
No
Yes
Initialization
SCR/SCR_SMCI.RE = 1
Start data reception
Figure 25.76
Example flow of transition to Software Standby mode during reception
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25. Serial Communications Interface (SCI)
Data reception
SCIn_RXI interrupt
No
[1]
[ 1 ] Received data is invalid
Yes
Read receive data in RDR
SCR/SCR_SMCI.RE = 0
[ 2 ] Setting for the module stop state is included
Set the operation mode to cancel Software
Standby mode
Set a compared data to CDR
DCCR.DCME = 1
SCR/SCR_SMCI.RE = 1
[2]
Transition to Software Standby mode
Cancel Software Standby mode
Change operating mode?
No
Yes
Initialization
Start/Continue data reception
Figure 25.77
25.13.3
(1)
Example flow of transition to Software Standby mode during reception with address match
Break Detection and Processing
Non-FIFO selected
When a framing error is detected, a break can be detected by reading the RXDn pin value directly. In a break, the input
from the RXDn pin becomes all 0s, and so the FER flag in SSR is set to 1 to indicate a framing error, and the PER flag in
SSR might also be set to 1 to indicate a parity error. The SCI continues the receive operation even after a break is
received. Therefore, even when the FER flag is set to 0, indicating no framing error occurred, it is set to 1 again. When
the SEMR.RXDESEL bit is 1, the SCI sets the SSR.FER flag to 1 and stops receiving operations until a start bit of the
next data frame is detected. If the SSR.FER flag is set to 0 at this time, the SSR.FER flag retains 0 during the break.
When the RXDn pin is set to 1 and the break ends, detecting the beginning of the start bit on the first falling edge of the
RXDn pin allows the SCI to start the receiving operation.
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(2)
25. Serial Communications Interface (SCI)
FIFO selected
After a framing error is detected and when the SCI detects that continuous receive data is 0 for 1 frame, reception stops.
When a framing error is detected, a break can be detected by reading the SPTR.RXDMON bit value. After the RXD
signal is in the mark state and the break is finished, reception data to the FRDRHL register resumes.
25.13.4
Mark State and Production of Breaks
When the SCR/SCR_SMCI.TE bit is 0, disabling serial transmission, the state of the TXDn pin can be set using the
SPTR.SPB2IO and SPTR.SPB2DT bits. With this approach, a TXDn pin can be placed in the mark state to transmit a
break.
Before setting the SCR/SCR_SMCI.TE bit to 1, enabling serial transmission, set the SPB2IO and SPB2DT bits to put a
communication line in the mark state (the state of 1), and change the TxDn pin using I/O port function. To output a break
on data transmission, after setting the TXDn pin to output 0 by setting the SPB2IO and SPB2DT bits, change the TXDn
pin using the I/O port function and set the SCR/SCR_SMCI.TE bit to 0. When the SCR/SCR_SMCI.TE bit is set to 0, the
transmitter is initialized regardless of the current state of transmission.
25.13.5
Receive Error Flags and Transmit Operations in Clock Synchronous and Simple
SPI Modes
Transmission cannot start when a receive error flag (ORER) in SSR/SSR_FIFO is set to 1, even when data is written to
TDR or FTDRL*2. Be sure to set the receive error flags to 0 before starting transmission.
Note 1. The receive error flags cannot be set to 0 even when the RE bit in SCR/SCR_SMCI is set to 0 (serial reception is
disabled).
Note 2. Do not use the FTDRH register in simple SPI mode.
25.13.6
Restrictions on Clock Synchronous Transmission in Clock Synchronous and
Simple SPI Modes
When the external clock source is used as a synchronization clock, the following restrictions apply.
(1)
Start of transmission
Wait at least the following time from writing transmit data to TDR to the start of the external clock input:
1 PCLKB cycle + data output delay time for the slave (tDO) + setup time for the master (tSU).
See Figure 25.78.
(2)
Continuous transmission
Write the next transmit data to TDR or TDRHL before the falling edge of the transmit clock, bit [7], see Figure 25.78.
When updating TDR after bit [7] starts to transmit, update TDR while the synchronization clock is in the low-level
period, and set the high-level width of the transmit clock, bit [7] to 4 PCLKB cycles or longer, see Figure 25.78.
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25. Serial Communications Interface (SCI)
Set t 1 PCLKB cycle + data output delay time for the slave (tDO) + setup time for the master (tSU)
Update TDR before bit [7] starts to transmit when continuous
transmission is performed on the external clock
Synchronous clock
(external clock)
t
Next frame of data
First frame of data
TDR
SCIn_TXI interrupt flag
(IELSRn.IR*1)
D0
Serial transmit data
D2
D1
D3
D4
D5
D6
D7
D0
D1
(1) Start of transmission and (2) Continuous transmission (a)
Set t 4 PCLKB cycles if TDR is updated after bit [7] starts to transmit when continuous transmission is performed on
the external clock
t
Synchronous clock
(external clock)
Next frame of data
Previous frame of data
TDR
SCIn_TXI interrupt flag
(IELSRn.IR*1)
Serial transmit data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
(2) Continuous transmission (b)
Note 1.
Figure 25.78
25.13.7
See section 12, Interrupt Controller Unit (ICU) for information on the corresponding interrupt event number.
Restrictions on the use of external clock in clock synchronous transmission
Restrictions on Using DTC
During transmission or reception operations using the DTC, do not transfer data for the DTC.
(1)
Writing data to TDR (FTDRHL)
(a)
Non-FIFO selected
Data can be written to TDR and TDRHL. However, if new data is written to TDR or TDRHL when transmit data remains
in TDR or TDRHL, the previous data in TDR and TDRHL is lost because it was not transferred to TSR yet. When using
DTC, be sure to write transmit data to TDR or TDRHL in the SCIn_TXI interrupt request handling routine.
(b)
FIFO selected
It is possible to write data to the FTDRH and FTDRL registers when SCR.TE is 1. Confirm the amount of writable data
using the FDR.T[4:0] bits.
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25. Serial Communications Interface (SCI)
Reading data from RDR (FRDRHL)
When using the DTC to read RDR and RDRHL, be sure to set the receive data full interrupt (SCIn_RXI) as the activation
source of the relevant SCI.
25.13.8
Notes on Starting Transfer
At the point where transfer starts when the interrupt status flag, IELSRn.IR flag, in the ICU is 1, follow the procedure in
this section to clear interrupt requests before permitting operations (by setting the SCR/SCR_SMCI.TE or SCR/
SCR_SMCI.RE bit to 1). For details on the interrupt status flag, see section 12, Interrupt Controller Unit (ICU).
Confirm that transfer has stopped (the setting of the SCR/SCR_SMCI.TE or SCR/SCR_SMCI.RE bit is 0).
Set the associated interrupt enable bit (SCR/SCR_SMCI.TIE or SCR/SCR_SMCI.RIE) to 0.
Read the associated interrupt enable bit (SCR/SCR_SMCI.TIE or SCR/SCR_SMCI.RIE bit) to check that it actually
becomes 0.
Set the interrupt status flag, IELSRn.IR, in the ICU to 0.
25.13.9
External Clock Input in Clock Synchronous and Simple SPI Modes
In clock synchronous mode and simple SPI mode, the external clock (SCKn) must be input as follows:
High-pulse period, low-pulse period = 2 PCLKB cycles or more, period = 6 PCLKB cycles or more.
25.13.10
(1)
Limitations on Simple SPI mode
Master mode
Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set by the
SPMR.CKPH and CKPOL bits when the SPMR.SSE bit is 1.
This prevents the clock line from being placed in the high-impedance state when the SCR.TE bit is set to 0 or
unexpected edges from being generated on the clock line when the SCR.TE bit changes from 0 to 1. When the
SPMR.SSE bit is 0 in single master mode, pulling up or pulling down the clock line is not required because the
clock line is not placed in the high-impedance state even when the SCR.TE bit is set to 0.
For the clock delay setting (SPMR.CKPH bit is 1), the receive data full interrupt (SCIn_RXI) is generated before
the final clock edge on the SCKn pin as indicated in Figure 25.79. If the TE and RE bits in the SCR become 0 at this
time before the final edge of the clock signal on the SCKn pin, the SCKn pin is placed in the high-impedance state,
so the width of the last clock pulse of the transfer clock is shortened. Additionally, an SCIn_RXI interrupt might
lead to the input signal on the SSn pin of a connected slave going to the high level before the final edge of the clock
signal on the SCKn pin, leading to incorrect operation of the slave.
In a multi-master configuration, take care because the SCKn pin output goes to high-impedance while the input on
the SSn pin is at the low level if a mode fault error occurs as the current character is being transferred, stopping
supply of the clock signal to the connected slave. Reset the connected slave to avoid misaligned bits when transfer is
restarted.
SCKn
(CKPOL = 0)
SCKn
(CKPOL = 1)
RXDn
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
SCIn_RXI interrupt
source
Figure 25.79
Timing of SCIn_RXI interrupt in simple SPI mode with clock delay
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25. Serial Communications Interface (SCI)
Slave mode
Wait at least the following time from writing transmit data in the TDR register to the start of the external clock
input.
1 PCLKB cycle + data output delay time for the slave (tDO) + setup time for the master (tSU)
Also wait at least 5 PCLKB cycles from the input of the low level on the SSn pin to the start of the external clock
input.
Provide an external clock signal to the master the same as the data length for transfer
Control the input on the SSn pin before the start and after the end of data transfer
When the input level on the SSn pin changes from low to high while a character is being transferred, set the TE and
RE bits in the SCR to 0 and, after restoring the settings, restart transfer of the first byte.
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26. I2C Bus Interface (IIC)
S124 User’s Manual
26.
I2C Bus Interface (IIC)
The MCU has a two-channel I2C Bus Interface (IIC). The IIC module conforms with and provides a subset of the NXP
I2C (Inter-Integrated Circuit) bus interface functions.
26.1
Overview
Table 26.1 lists the IIC specifications, Figure 26.1 shows a block diagram of the IIC, and Figure 26.2 shows an example
I/O pin connections to external circuits. Table 26.2 lists the IIC I/O pins.
Table 26.1
IIC specifications (1 of 2)
Parameter
Description
Communications format
I2C bus or SMBus format
Master or slave mode selectable
Automatic securing of the setup times, hold times, and bus-free times for the transfer rate.
Transfer rate
Fast-mode supported up to 400 kbps
SCL clock
For master operation, the duty cycle of the SCL clock is selectable in the range from 4% to 96%.
Issuing and detecting
conditions
Start, restart, and stop conditions are automatically generated
Start conditions (including restart conditions) and stop conditions are detectable.
Slave address
Configurable for up to three different slave addresses
7-bit and 10-bit address formats supported, including simultaneous use
General call addresses, device ID addresses, and SMBus host addresses detectable.
Acknowledgment
For transmission, automatic loading of the acknowledge bit
Transfer of the next transmit data can be automatically suspended on detection of a not-acknowledge bit.
For reception, automatic transmission of the acknowledge bit
If a wait between the eighth and ninth clock cycles is selected, software can control the value in the
acknowledge field in response to the received value.
Wait function
During reception, the following wait periods are available by holding the SCL clock low:
Waiting between the eighth and ninth clock cycles
Waiting between the ninth clock cycle and the first clock cycle of the next transfer.
SDA output delay
function
Output timing of transmitted data, including the acknowledge bit, can be delayed
Arbitration
For multi-master operation:
- SCL clock synchronization is possible when conflict occurs with the SCL signal from another master
- When issuing the start condition creates conflict on the bus, loss of arbitration is detected by testing for
mismatching between the internal signal for the SDA line and the level on the SDA line
- In master operation, loss of arbitration is detected by testing for mismatching between the signal on the
SDA line and the internal signal for the SDA line.
Loss of arbitration because the start condition occurs while the bus is busy is detectable, to prevent the
issuing of double start conditions
Loss of arbitration is detectable on transfer of a not-acknowledge bit because the internal signal for the
SDA line and the level on the SDA line do not match
Loss of arbitration because mismatching of internal and line levels for data is detectable in slave
transmission.
Timeout function
Internal detection of long-interval stops of the SCL clock
Noise cancellation
Digital noise filters for both the SCL and SDA signals
Programmable window for noise cancellation by the filters.
Interrupt sources
Transfer error or event occurrence (arbitration detection, NACK, timeout, start or restart condition, or stop
condition)
Receive data full, including matching with a slave address
Transmit data empty, including matching with a slave address
Transmit end.
Module-stop function
Module-stop state can be set to reduce power consumption
IIC operating modes
Master transmit
Master receive
Slave transmit
Slave receive.
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Table 26.1
IIC specifications (2 of 2)
Parameter
Description
Event link function
(output)
Transfer error or event occurrences (arbitration detection, NACK, timeout, start or restart condition, or
stop condition)
Receive data full, including matching with a slave address
Transmit data empty, including matching with a slave address
Transmit end.
Wakeup function*1
CPU can return from Software Standby mode using a wakeup event
Note 1. Only supported for IIC0. IIC1 is not supported.
PCLKB
PS
CKS[2:0]
ICMR1
BC[2:0]
IIC (PCLKB/1 to PCLKB/128)
Output
control
SCLn
ICBRH
Transfer clock
generator
CLO
Noise
canceller
ICBRL
SCLE
SCLI
ICCR1
SCLn, SDAn
NF[1:0]
NFE
Transmission/
reception control
circuit
PS
IICRST
SDAI
ST, RS, SP
DLCS
ICCR2
BBSY, MST, TRS
WAIT, RDRFS
ICFER
SDA output delay control
SDDL[2:0]
ICMR2
ICMR3
ACKBT
ACKBR
ACK output circuit
ICDRT
NACKE
Output
control
SDAn
ICDRS
NACK decision/ACK
reception circuit
SARL1
SARU2
SARL2
ICDRR
Arbitration decision
circuit
NFE
SARL0
SARU1
Address comparator
Noise
canceller
NF[1:0]
SARU0
Internal data bus
IIC, IIC/2
ICSR1
MALE, NALE, SALE
ICSER
Bus state decision
circuit
NACKF
TMOE
ICSR2
TMOS, TMOH, TMOL
Timeout circuit
TMOF
ICIER
Event output
Interrupt generator
Figure 26.1
Interrupt request
(IICn_TXI, IICn_TEI, IICn_RXI,
IICn_EEI, IIC0_WUI)
IIC block diagram
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Power supply for pull-up
SCLin
SCL
SCL
SDA
SDA
SCLout#
SDAin
SCLin
SCLout#
SCLout#
SDAin
SDAin
SDAout#
SDAout#
(Slave 1)
SDA
SCL
SCLin
SDA
(Master)
SCL
SDAout#
(Slave 2)
I/O pin connection to the external circuit (I2C bus configuration example)
Figure 26.2
The input level of the signals for the IIC is CMOS when I2C bus is selected (ICMR3.SMBS = 0), or TTL when SMBus is
selected (ICMR3.SMBS = 1).
Table 26.2
IIC pin configuration
Channel
Pin name
IIC0
IIC1
26.2
I/O
Function
SCL0
I/O
IIC0 serial clock input/output pin
SDA0
I/O
IIC0 serial data input/output pin
SCL1
I/O
IIC1 serial clock input/output pin
SDA1
I/O
IIC1 serial data input/output pin
Register Descriptions
I2C Bus Control Register 1 (ICCR1)
26.2.1
Address(es): IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h
Value after reset:
b7
b6
b5
ICE
IICRST
CLO
0
0
0
b4
b3
SOWP SCLO
1
1
b2
b1
b0
SDAO
SCLI
SDAI
1
1
1
Bit
Symbol
Bit name
Description
R/W
b0
SDAI
SDA Line Monitor
0: SDAn line is low
1: SDAn line is high.
R
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Bit
Symbol
Bit name
Description
R/W
b1
SCLI
SCL Line Monitor
0: SCLn line is low
1: SCLn line is high.
R
b2
SDAO
SDA Output Control/Monitor
Read:
0: IIC drove SDAn pin low
1: IIC released SDAn pin.
Write:
0: Drive SDAn pin low
1: Release SDAn pin.
R/W
b3
SCLO
SCL Output Control/Monitor
Read:
0: IIC drove SCLn pin low
1: IIC released SCLn pin.
Write:
0: Drive SCLn pin low
1: Release SCLn pin.
Use an external pull-up resistor to drive the signal high.
R/W
b4
SOWP
SCLO/SDAO Write Protect
0: Write-enable SCLO and SDAO bits
1: Write-protect SCLO and SDAO bits.
This bit is read as 1.
R/W
b5
CLO
Extra SCL Clock Cycle Output
0: Do not output extra SCL clock cycle (default)
1: Output extra SCL clock cycle.
This bit clears automatically after 1 clock cycle is output.
R/W
b6
IICRST
IIC bus Interface Internal Reset
0: Release IIC reset or internal reset
1: Initiate IIC reset or internal reset.
This setting clears the bit counter and the SCLn/SDAn output
latch.
R/W
b7
ICE
IIC bus Interface Enable
0: Disable (SCLn and SDAn pins in inactive state)
1: Enable (SCLn and SDAn pins in active state).
Combined with the IICRST bit to select either IIC or internal reset.
R/W
SDAO bit (SDA Output Control/Monitor) and SCLO bit (SCL Output Control/Monitor)
The SDAO and SCLO bits directly control the SDAn and SCLn signals output from the IIC.
When writing to the SDAO and SCLO bits, also write 0 to the SOWP bit. Setting the SDAO and SCLO bits results in
input to the IIC through the input buffer. When slave mode is selected, a start condition might be detected and the bus
might be released, depending on the bit settings.
Do not rewrite the SDAO and SCLO bits during a start condition, stop condition, restart condition, or during
transmission or reception. Operation after rewriting under these conditions is not guaranteed. The read values of these
bits are the states of the SDAn and SCLn signals output from the IIC.
CLO bit (Extra SCL Clock Cycle Output)
The CLO bit allows output of an extra SCL clock cycle for debugging or error processing. Normally, set this bit to 0.
Setting the CLO bit to 1 in a normal communication state causes a communication error. For details on this function, see
section 26.12.2, Extra SCL Clock Cycle Output Function.
IICRST bit (IIC bus Interface Internal Reset)
The IICRST bit initiates an internal state reset of the IIC.
Setting the IICRST bit to 1 initiates an IIC reset or internal reset. Whether an IIC reset or internal reset is initiated is
determined by the setting of the IICRST bit in combination with the ICE bit. Table 26.3 lists the IIC resets.
The IIC reset initializes all registers except ICCR1.ICE and ICCR1.IICRST bits, and internal states of the IIC. The
internal reset initializes the bit counter (ICMR1.BC[2:0] bits), the I2C Bus Shift Register (ICDRS), the I2C Bus Status
Registers (ICSR1 and ICSR2), SDAO and SCLO Output Control/Monitor (ICCR1.SCLO and ICCR1.SDAO bits), and
the I2C Bus Control Register 2 (except ICCR2.BBSY bit), in addition to the internal states of the IIC. For the reset
conditions for each register, see section 26.15, State of Registers when Issuing Each Condition.
An internal reset initiated with the IICRST bit set to 1 during operation (with the ICE bit set to 1) resets the internal states
of the IIC without initializing the port settings and the control and setting registers of the IIC. If the IIC hangs in a lowlevel output state, resetting the internal states cancels the low level output state and releases the bus with the SCLn pin
and SDAn pin at high impedance.
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Note:
If an internal reset is initiated using the IICRST bit for a bus hang that occurs during communication with the
master device in slave mode, the slave and master devices might enter different states, because the bit counter
information differs. For this reason, do not initiate an internal reset in slave mode. Initiate recovery processing
from the master device. If an internal reset is necessary because the IIC hangs with the SCLn line in a low-level
output state in slave mode, initiate an internal reset, then issue a restart condition from the master device, or
issue a stop condition and resume communication from the start condition. If communication is restarted by
initiating a reset solely in the slave device without issuing a start or restart condition from the master device,
synchronization is lost because the master and slave devices operate asynchronously.
Table 26.3
IIC resets
IICRST
ICE
State
Specifications
1
0
IIC reset
Resets all registers except ICCR1.ICE and ICCR1.IICRST bits, and internal states of the
IIC
1
Internal reset
Resets the ICMR1.BC[2:0] bits, the ICSR1, ICSR2, ICDRS registers, SDAO and SCLO
Output Control/Monitor (ICCR1.SCLO and ICCR1.SDAO bits), I2C Bus Control Register 2
(except ICCR2.BBSY bit), and the internal states of the IIC
ICE bit (IIC bus Interface Enable)
The ICE bit selects the active or inactive state of the SCLn and SDAn pins. It can also be combined with the IICRST bit
to initiate either of two types of resets. See Table 26.3 for the reset types.
Set the ICE bit to 1 when using the IIC. The SCLn and SDAn pins are placed in the active state when the ICE bit is set to
1. Set the ICE bit to 0 when the IIC is not used. The SCLn and SDAn pins are placed in the inactive state when the ICE
bit is set to 0. Do not assign the SCLn or SDAn pin to the IIC when setting up the pin function control. Slave address
comparison is performed if the pins are assigned to the IIC.
I2C Bus Control Register 2 (ICCR2)
26.2.2
Address(es): IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h
b7
b6
b5
b4
b3
b2
b1
b0
BBSY
MST
TRS
—
SP
RS
ST
—
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b1
ST
Start Condition Issuance
Request
0: Do not issue a start condition request
1: Issue a start condition request.
R/W
b2
RS
Restart Condition Issuance
Request
0: Do not issue a restart condition request
1: Issue a restart condition request.
R/W
b3
SP
Stop Condition Issuance
Request
0: Do not issue a stop condition request
1: Issue a stop condition request.
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
TRS
Transmit/Receive Mode
0: Receive mode
1: Transmit mode.
R/W*1
b6
MST
Master/Slave Mode
0: Slave mode
1: Master mode.
R/W*1
b7
BBSY
Bus Busy Detection Flag
0: I2C bus released (bus free state)
1: I2C bus occupied (bus busy state).
R
Note 1.
The MST and TRS bits can be written to when the ICMR1.MTWP bit is set to 1.
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26. I2C Bus Interface (IIC)
ST bit (Start Condition Issuance Request)
The ST bit requests transition to master mode and issues a start condition.
When the ST bit is set to 1, a start condition is issued when the BBSY flag is set to 0 (bus free state). For details on
issuing start conditions, see section 26.11, Start, Restart, and Stop Condition Issuing Function.
[Setting condition]
When 1 is written to the ST bit.
[Clearing conditions]
When 0 is written to the ST bit
When a start condition is issued (a start condition is detected)
When the AL (arbitration-lost) flag in the ICSR2 register is set to 1
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
Note:
Only set the ST bit to 1 (start condition request) when the BBSY flag is 0 (bus free state).
Arbitration might be lost if the ST bit is set to 1 when the BBSY flag is 1.
RS bit (Restart Condition Issuance Request)
The RS bit requests that a restart condition be issued in master mode.
When the RS bit is set to 1 to request a restart condition, a restart condition is issued when the BBSY flag is set to 1 (bus
busy state) and the MST bit is set to 1 (master mode). For details on issuing restart conditions, see section 26.11, Start,
Restart, and Stop Condition Issuing Function.
[Setting condition]
When 1 is written to the RS bit with the BBSY flag in the ICCR2 register set to 1.
[Clearing conditions]
When 0 is written to the RS bit
When a restart condition is issued (a start condition is detected)
When the AL (arbitration-lost) flag in the ICSR2 register is set to 1
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
Note:
Note:
Do not set the RS bit to 1 while issuing a stop condition.
If 1 (restart condition request) is written to the RS bit in slave mode, the restart condition is not issued, but the RS
bit remains set to 1. If the operating mode changes to master mode without the RS bit being cleared, a restart
condition might be issued.
SP bit (Stop Condition Issuance Request)
The SP bit requests that a stop condition be issued in master mode.
When this bit is set to 1, a stop condition is issued when the BBSY flag is set to 1 (bus busy state) and the MST bit is set
to 1 (master mode). For details on issuing stop conditions, see section 26.11, Start, Restart, and Stop Condition Issuing
Function.
[Setting condition]
When 1 is written to the SP bit with both the BBSY flag and the MST bit in the ICCR2 register set to 1.
[Clearing conditions]
When 0 is written to the SP bit
When a stop condition is issued (a stop condition is detected)
When the AL (arbitration-lost) flag in the ICSR2 register is set to 1
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When a start condition and a restart condition are detected
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
Note:
Note:
Writing to the SP bit is not possible when the BBSY flag is 0 (bus free state).
Do not set the SP bit to 1 when a restart condition is issued.
TRS bit (Transmit/Receive Mode)
The TRS bit indicates transmit or receive mode.
The IIC is in receive mode when the TRS bit is 0 and in transmit mode when the bit is 1. The combination of the TRS bit
and the MST bit indicates the operating mode of the IIC.
The value of the TRS bit automatically changes to 1 for transmit mode or 0 for receive mode when a start condition is
issued or detected and the R/W# bit is set. Although writing to the TRS bit is possible when the MTWP bit in the ICMR1
register is 1, writing to the TRS bit is not necessary during normal usage.
[Setting conditions]
When a start condition is issued normally because of a start condition request (when a start condition is detected
with the ST bit set to 1)
When a restart condition is issued normally because of a restart condition request (when a restart condition is
detected with the RS bit set to 1)
When the R/W# bit appended to the slave address is set to 0 in master mode
When the address received in slave mode matches the address enabled in the ICSER register, with the R/W# bit set
to 1
When 1 is written to the TRS bit with the MTWP bit in the ICMR1 register set to 1.
[Clearing conditions]
When a stop condition is detected
When the AL (arbitration-lost) flag in the ICSR2 register is set to 1
When the R/W# bit appended to the slave address is set to 1 in master mode
In slave mode, on a match between the received address and the address enabled in the ICSER register when the
value of the received R/W# bit is 0, including when the received address is the general call address
In slave mode, when a restart condition is detected (a start condition is detected with ICCR2.BBSY = 1 and
ICCR2.MST = 0)
When 0 is written to the TRS bit with the MTWP bit in the ICMR1 register set to 1
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
MST bit (Master/Slave Mode)
The MST bit indicates master or slave mode.
The IIC is in slave mode when the MST bit is set to 0 and is in master mode when the bit is set to 1. The combination of
the MST bit and the TRS bit indicates the operating mode of the IIC.
The value of the MST bit automatically changes to 1 for master mode or 0 for slave mode when a start condition is issued
or a stop condition is issued or detected. Although writing to the MST bit is possible when the MTWP bit in the ICMR1
register is 1, writing to the MST bit is not necessary during normal usage.
[Setting conditions]
When a start condition is issued normally because of a start condition request (when a start condition is detected
with the ST bit set to 1)
When 1 is written to the MST bit with the MTWP bit in ICMR1 set to 1.
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[Clearing conditions]
When a stop condition is detected
When the AL (arbitration-lost) flag in the ICSR2 register is set to 1
When 0 is written to the MST bit with the MTWP bit in the ICMR1 register set to 1
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
BBSY flag (Bus Busy Detection Flag)
The BBSY flag indicates whether the I2C bus is occupied (bus busy state) or released (bus free state).
The BBSY flag is set to 1 when the SDAn line changes from high to low when the SCLn line is high, assuming that a
start condition was issued. The BBSY flag is then set to 0 if the bus free time (ICBRL register setting) start condition is
not detected, assuming that a stop condition was issued.
[Setting condition]
When a start condition is detected.
[Clearing conditions]
When the bus free time (ICBRL register setting) start condition is not detected after a stop condition detection
When 1 is written to the ICCR1.IICRST bit with the ICCR1.ICE bit set to 0 (IIC reset).
I2C Bus Mode Register 1 (ICMR1)
26.2.3
Address(es): IIC0.ICMR1 4005 3002h, IIC1.ICMR1 4005 3102h
b7
b6
MTWP
Value after reset:
0
b5
b4
CKS[2:0]
0
0
b3
b2
BCWP
0
1
b1
b0
BC[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
BC[2:0]
Bit Counter
b2
R/W*1
b3
BCWP
BC Write Protect
0: Write enable BC[2:0] bits
1: Write protect BC[2:0] bits.
This bit is read as 1.
R/W*1
b6 to b4
CKS[2:0]
Internal Reference Clock Select
Select the internal reference clock source (IIC) for the IIC.
R/W
0
0
0
0
1
1
1
1
b6
0
0
0
0
1
1
1
1
b7
MTWP
MST/TRS Write Protect
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0: 9 bits
1: 2 bits
0: 3 bits
1: 4 bits
0: 5 bits
1: 6 bits
0: 7 bits
1: 8 bits.
b4
0: PCLKB clock
1: PCLKB/2 clock
0: PCLKB/4 clock
1: PCLKB/8 clock
0: PCLKB/16 clock
1: PCLKB/32 clock
0: PCLKB/64 clock
1: PCLKB/128 clock.
0: Write protect the MST and TRS bits in the ICCR2 register
1: Write enable the MST and TRS bits in the ICCR2 register.
R/W
Note 1. Rewrite the BC[2:0] bits and set the BCWP bit to 0 at the same time.
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BC[2:0] bits (Bit Counter)
The BC[2:0] bits function as a counter indicating the number of bits remaining to be transferred on detection of a rising
edge on the SCLn line. Although the BC[2:0] bits are writable and readable, it is not normally necessary to access these
bits.
To write to the BC[2:0] bits, specify the number of bits to be transferred plus one, for an additional acknowledge bit,
between transferred frames when the SCLn line is at a low level.
The value in the BC[2:0] bits returns to 000b at the end of a data transfer, including the acknowledge bit, or when a start
or restart condition is detected.
I2C Bus Mode Register 2 (ICMR2)
26.2.4
Address(es): IIC0.ICMR2 4005 3003h, IIC1.ICMR2 4005 3103h
b7
b6
DLCS
Value after reset:
0
b5
b4
SDDL[2:0]
0
0
b3
—
0
0
b2
b1
b0
TMOH TMOL
1
TMOS
1
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOS
Timeout Detection Time Select
0: Select long mode
1: Select short mode.
R/W
b1
TMOL
Timeout L Count Control
0: Disable count when SCLn line is low
1: Enable count when SCLn line is low.
R/W
b2
TMOH
Timeout H Count Control
0: Disable count when SCLn line is high
1: Enable count when SCLn line is high.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6 to b4
SDDL[2:0]
SDA Output Delay Counter
When ICMR2.DLCS = 0 (IIC):
R/W
b6
b4
0 0 0: No output delay
0 0 1: 1 IIC cycle
0 1 0: 2 IIC cycles
0 1 1: 3 IIC cycles
1 0 0: 4 IIC cycles
1 0 1: 5 IIC cycles
1 1 0: 6 IIC cycles
1 1 1: 7 IIC cycles.
When ICMR2.DLCS = 1 (IIC/2):
b6
0
0
0
0
1
1
1
1
b7
DLCS
SDA Output Delay Clock Source
Select
0
0
1
1
0
0
1
1
b4
0: No output delay
1: 1 or 2 IIC cycles
0: 3 or 4 IIC cycles
1: 5 or 6 IIC cycles
0: 7 or 8 IIC cycles
1: 9 or 10 IIC cycles
0: 11 or 12 IIC cycles
1: 13 or 14 IIC cycles.
0: Select internal reference clock (IIC) as clock source for SDA
output delay counter
1: Select internal reference clock divided by 2 (IIC/2) as clock
source for SDA output delay counter.*1
R/W
Note 1. The setting DLCS = 1 (IIC/2) is only valid when SCL is low. When SCL is high, the DLCS = 1 setting is invalid
and the clock source becomes the internal reference clock (IIC).
TMOS bit (Timeout Detection Time Select)
The TMOS bit selects long mode or short mode for the timeout detection time when the timeout function is enabled
(ICFER.TMOE = 1).
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When the TMOS bit is set to 0, long mode is selected. When the TMOS bit is set to 1, short mode is selected. In long
mode, the timeout detection internal counter functions as a 16-bit counter. In short mode, the counter functions as a 14bit counter. While the SCLn line is in the state that enables this counter as specified in the TMOH and TMOL bits, the
counter counts up in sync with the internal reference clock (IIC) as a count source.
For details on the timeout function, see section 26.12.1, Timeout Function.
TMOL bit (Timeout L Count Control)
The TMOL bit enables or disables up-counting on the internal counter of the timeout function when the SCLn line is held
low and the timeout function is enabled (ICFER.TMOE = 1).
TMOH bit (Timeout H Count Control)
The TMOH bit enables or disables up-counting on the internal counter of the timeout function when the SCLn line is
held high and the timeout function is enabled (ICFER.TMOE = 1).
SDDL[2:0] bits (SDA Output Delay Counter)
The SDDL[2:0] bits can be used to delay the SDA output. The SDA Output Delay Counter works with the clock source
selected in the DLCS bit. The SDDL[2:0] setting can be used for all types of SDA output, including transmission of the
acknowledge bit.
Set the SDA output delay to meet the I2C bus standard for the data enable time/acknowledge enable time*1, or the
SMBus standard, within [data hold time (300 ns or more + the SCL clock low-level period) - the data setup time (250 ns).
If a value outside the standard is set, communication between devices might malfunction or falsely indicate a start or stop
condition, depending on the bus state.
For details on this function, see section 26.5, SDA Output Delay Function.
Note 1. Data enable time/acknowledge enable time
3,450 ns for up to 100 kbps: Standard-mode (Sm)
900 ns for up to 400 kbps: Fast-mode (Fm)
I2C Bus Mode Register 3 (ICMR3)
26.2.5
Address(es): IIC0.ICMR3 4005 3004h, IIC1.ICMR3 4005 3104h
b7
SMBS
Value after reset:
0
b6
b5
b4
b3
b2
b1
WAIT RDRFS ACKW ACKBT ACKBR
P
0
0
0
0
0
b0
NF[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
NF[1:0]
Noise Filter Stage Select
b1 b0
R/W
b2
ACKBR
Receive Acknowledge
0: 0 received as the acknowledge bit (ACK reception)
1: 1 received as the acknowledge bit (NACK reception).
R
b3
ACKBT
Transmit Acknowledge
0: Send 0 as the acknowledge bit (ACK transmission)
1: Send 1 as the acknowledge bit (NACK transmission).
R/W*1
b4
ACKWP
ACKBT Write Protect
0: Write protect ACKBT bit
1: Write enable ACKBT bit.
R/W*1
b5
RDRFS
RDRF Flag Set Timing
Select
0: Set the RDRF flag on the rising edge of the ninth SCL clock cycle
The SCLn line is not held low on the falling edge of the eighth clock
cycle.
1: Set the RDRF flag on the rising edge of the eighth SCL clock cycle.
The SCLn line is held low on the falling edge of the eighth clock cycle.
Low-hold is released by writing to ACKBT.
R/W*2
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0 0: Filter out noise of up to 1 IIC cycle (single-stage filter)
0 1: Filter out noise of up to 2 IIC cycles (2-stage filter)
1 0: Filter out noise of up to 3 IIC cycles (3-stage filter)
1 1: Filter out noise of up to 4 IIC cycles (4-stage filter).
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Bit
Symbol
Bit name
Description
R/W
b6
WAIT
WAIT
0: No wait
The period between ninth clock cycle and first clock cycle is not held
low.
1: Wait.
The period between ninth clock cycle and first clock cycle is held low.
Low-hold is released by reading the ICDRR register.
R/W*2
b7
SMBS
SMBus/IIC bus Select
0: Select I2C bus
1: Select SMBus.
R/W
Note 1. Write to the ACKBT bit only when the ACKWP bit is already 1. If the application writes 1 to the ACKWP and
ACKBT bits at the same time, the ACKBT bit is not set to 1.
Note 2. The WAIT and RDRFS bits are valid only in receive mode (invalid in transmit mode).
NF[1:0] bits (Noise Filter Stage Select)
The NF[1:0] bits select the number of stages in the digital noise filter.
For details on the digital noise filter function, see section 26.6, Digital Noise Filter Circuits.
Note:
Set the noise range to be filtered within a range less than the SCLn line high-level period or low-level period. If
the noise range is set to a value of [SCL clock width: high-level period or low-level period, whichever is shorter] [1.5 internal reference clock (IIC) cycles + analog noise filter: 120 ns (reference values)] or more, the SCL clock
is regarded as noise, which might prevent the IIC from operating normally.
ACKBR bit (Receive Acknowledge)
The ACKBR bit stores the acknowledge bit information received from the receive device in transmit mode.
[Setting condition]
When 1 is received as the acknowledge bit with the TRS bit in the ICCR2 register set to 1.
[Clearing conditions]
When 0 is received as the acknowledge bit with the TRS bit in the ICCR2 register set to 1
When 1 is written to the IICRST bit in the ICCR1 register when the ICE bit in the ICCR1 register is 0 (IIC reset).
ACKBT bit (Transmit Acknowledge)
The ACKBT bit sets the acknowledge bit to be sent in receive mode.
[Setting condition]
When 1 is written to the ACKBT bit with the ACKWP bit set to 1.
[Clearing conditions]
When 0 is written to the ACKBT bit with the ACKWP bit set to 1
When a stop condition issuance is detected (when a stop condition is detected with the SP bit in the ICCR2 register
set to 1)
When 1 is written to the IICRST bit in the ICCR1 register when the ICE bit in the ICCR1 register is 0 (IIC reset).
ACKWP bit (ACKBT Write Protect)
The ACKWP bit controls write enabling of the ACKBT bit.
RDRFS bit (RDRF Flag Set Timing Select)
The RDRFS bit selects the RDRF flag set timing in receive mode and also selects whether to hold the SCLn line low on
the falling edge of the eighth SCL clock cycle.
When the RDRFS bit is 0, the SCLn line is not held low on the falling edge of the eighth SCL clock cycle, and the RDRF
flag is set to 1 on the rising edge of the ninth SCL clock cycle.
When the RDRFS bit is 1, the RDRF flag is set to 1 on the rising edge of the eighth SCL clock cycle, and the SCLn line
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is held low on the falling edge of the eighth SCL clock cycle. The low-hold of the SCLn line is released by a write to the
ACKBT bit. After data is received with this setting, the SCLn line is automatically held low before the acknowledge bit
is sent. This enables processing to send ACK (ACKBT = 0) or NACK (ACKBT = 1), based on the receive data.
WAIT bit (WAIT)
The WAIT bit controls whether to hold the period between the ninth SCL clock cycle and the first SCL clock cycle low
until the receive data buffer (ICDRR) is completely read each time single-byte data is received in receive mode.
When the WAIT bit is 0, the receive operation is continued without holding the period between the ninth and the first
SCL clock cycle low. When both the RDRFS and WAIT bits are 0, continuous receive operation is enabled with the
double buffer.
When the WAIT bit is 1, the SCLn line is held low from the falling edge of the ninth clock cycle until the ICDRR register
value is read each time single-byte data is received. This enables receive operation in byte units.
Note:
When the value of the WAIT bit is to be read, be sure to read the ICDRR register first.
SMBS bit (SMBus/IIC bus Select)
Setting the SMBS bit to 1 selects the SMBus and enables the HOAE bit in the ICSER register.
26.2.6
I2C Bus Function Enable Register (ICFER)
Address(es): IIC0.ICFER 4005 3005h, IIC1.ICFER 4005 3105h
b7
b6
b5
—
SCLE
NFE
0
1
1
Value after reset:
b4
b3
NACKE SALE
1
b2
b1
b0
NALE
MALE
TMOE
0
1
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOE
Timeout Function Enable
0: Disable
1: Enable.
R/W
b1
MALE
Master Arbitration-Lost Detection
Enable
0: Disable
Disables the arbitration-lost detection function and disables
automatic clearing of the MST and TRS bits in the ICCR2 register
when arbitration is lost.
1: Enable
Enables the arbitration-lost detection function and enables
automatic clearing of the MST and TRS bits in the ICCR2 register
when arbitration is lost.
R/W
b2
NALE
NACK Transmission ArbitrationLost Detection Enable
0: Disable
1: Enable.
R/W
b3
SALE
Slave Arbitration-Lost Detection
Enable
0: Disable
1: Enable.
R/W
b4
NACKE
NACK Reception Transfer
Suspension Enable
0: Do not suspend transfer operation during NACK reception
(transfer suspension disabled)
1: Suspend transfer operation during NACK reception (transfer
suspension enabled).
R/W
b5
NFE
Digital Noise Filter Circuit Enable
0: Do not use digital noise filter circuit
1: Use digital noise filter circuit.
R/W
b6
SCLE
SCL Synchronous Circuit Enable
0: Do not use SCL synchronous circuit
1: Use SCL synchronous circuit.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
TMOE bit (Timeout Function Enable)
The TMOE bit enables or disables the timeout function.
For details on the timeout function, see section 26.12.1, Timeout Function.
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MALE bit (Master Arbitration-Lost Detection Enable)
The MALE bit specifies whether to use the arbitration-lost detection function in master mode. In normal operation, set
the MALE bit to 1.
NALE bit (NACK Transmission Arbitration-Lost Detection Enable)
The NALE bit specifies whether to cause arbitration to be lost when ACK is detected during transmission of NACK in
receive mode, for example, when slaves with the same address exist on the bus or when two or more masters select the
same slave device simultaneously with a different number of receive bytes.
SALE bit (Slave Arbitration-Lost Detection Enable)
The SALE bit specifies whether to cause arbitration to be lost when a value different from the value being transmitted is
detected on the bus in slave transmit mode, for example, when slaves with the same address exist on the bus or when a
mismatch with the transmit data occurs because of noise.
NACKE bit (NACK Reception Transfer Suspension Enable)
The NACKE bit specifies whether to continue or discontinue the transfer operation when NACK is received from the
slave device in transmit mode. In normal operation, set the NACKE bit to 1.
When NACK is received with the NACKE bit set to 1, the next transfer operation is suspended. When the NACKE bit is
0, the next transfer operation is continued regardless of the received acknowledge content.
For details on the NACK reception transfer suspension function, see section 26.9.2, NACK Reception Transfer
Suspension Function.
SCLE bit (SCL Synchronous Circuit Enable)
The SCLE bit specifies whether to synchronize the SCL clock with the SCL input clock. In normal operation, set the
SCLE bit to 1.
When the SCLE bit is set to 0 (no SCL synchronous circuit used), the IIC does not synchronize the SCL clock with the
SCL input clock. With this setting, the IIC outputs the SCL clock with the transfer rate set in ICBRH and ICBRL,
regardless of the SCLn line state. For this reason, if the bus load of the I2C bus line is much larger than the specification
value, or if the SCL clock output overlaps in multiple masters, a short-cycle SCL clock that does not meet the
specification might be output. When no SCL synchronous circuit is used, the issuance of the start, restart, and stop
conditions, and the continuous output of extra SCL clock cycles are also affected.
The SCLE bit must not be set to 0 except when checking the output of the set transfer rate.
I2C Bus Status Enable Register (ICSER)
26.2.7
Address(es): IIC0.ICSER 4005 3006h, IIC1.ICSER 4005 3106h
b7
b6
b5
b4
HOAE
—
DIDE
—
0
0
0
0
Value after reset:
b3
b2
b1
b0
GCAE SAR2E SAR1E SAR0E
1
0
0
1
Bit
Symbol
Bit name
Description
R/W
b0
SAR0E
Slave Address Register 0 Enable
0: Disable slave address in SARL0 and SARU0
1: Enable slave address in SARL0 and SARU0.
R/W
b1
SAR1E
Slave Address Register 1 Enable
0: Disable slave address in SARL1 and SARU1
1: Enable slave address in SARL1 and SARU1.
R/W
b2
SAR2E
Slave Address Register 2 Enable
0: Disable slave address in SARL2 and SARU2
1: Enable slave address in SARL2 and SARU2.
R/W
b3
GCAE
General Call Address Enable
0: Disable general call address detection
1: Enable general call address detection.
R/W
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
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Bit
Symbol
Bit name
Description
R/W
b5
DIDE
Device-ID Address Detection
Enable
0: Disable device-ID address detection
1: Enable device-ID address detection.
R/W
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
HOAE
Host Address Enable
0: Disable host address detection
1: Enable host address detection.
R/W
SARyE bit (Slave Address Register y Enable) (y = 0 to 2)
The SARyE bit enables or disables the slave address set in the SARLy and SARUy registers.
When the SARyE bit is set to 1, the slave address set in the SARLy and SARUy registers is enabled and is compared with
the received slave address. When the SARyE bit is set to 0, the slave address set in the SARLy and SARUy registers is
disabled and is ignored even if it matches the received slave address.
GCAE bit (General Call Address Enable)
The GCAE bit specifies whether to ignore the general call address (0000 000b + 0 [W]: All 0s) when it is received.
When the GCAE bit is set to 1, if the received slave address matches the general call address, the IIC recognizes the
received slave address as the general call address independently of the slave addresses set in the SARLy and SARUy
registers (y = 0 to 2), and performs the data receive operation. When the GCAE bit is set to 0, the received slave address
is ignored even if it matches the general call address.
DIDE bit (Device-ID Address Detection Enable)
The DIDE bit specifies whether to recognize and execute the device-ID address when a device ID (1111 100b) is
received in the first frame after a start or restart condition is detected.
When the DIDE bit is set to 1, if the received first frame matches the device ID, the IIC recognizes that the device-ID
address was received. When the subsequent R/W# bit is 0 [W], the IIC recognizes the second and subsequent frames as
slave addresses and continues the receive operation. When the DIDE bit is set to 0, the IIC ignores the received first
frame even if it matches the device ID address and recognizes the first frame as a normal slave address.
For details on the device-ID address detection, see section 26.7.3, Device-ID Address Detection.
HOAE bit (Host Address Enable)
The HOAE bit specifies whether to ignore the received host address (0001 000b) when the SMBS bit in the ICMR3
register is 1.
When the HOAE bit is set to 1 when the SMBS bit in the ICMR3 register is 1, if the received slave address matches the
host address, the IIC recognizes the received slave address as the host address independently of the slave addresses set in
the SARLy and SARUy registers (y = 0 to 2) and performs the receive operation.
When the SMBS bit in the ICMR3 register or the HOAE bit is set to 0, the received slave address is ignored even if it
matches the host address.
I2C Bus Interrupt Enable Register (ICIER)
26.2.8
Address(es): IIC0.ICIER 4005 3007h, IIC1.ICIER 4005 3107h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TIE
TEIE
RIE
NAKIE
SPIE
STIE
ALIE
TMOIE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOIE
Timeout Interrupt Request Enable
0: Disable timeout interrupt (TMOIn) request
1: Enable timeout interrupt (TMOIn) request.
R/W
b1
ALIE
Arbitration-Lost Interrupt Request
Enable
0: Disable arbitration-lost interrupt (ALIn) request
1: Enable arbitration-lost interrupt (ALIn) request.
R/W
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Bit
Symbol
Bit name
Description
R/W
b2
STIE
Start Condition Detection Interrupt
Request Enable
0: Disable start condition detection interrupt (STIn) request
1: Enable start condition detection interrupt (STIn) request.
R/W
b3
SPIE
Stop Condition Detection Interrupt
Request Enable
0: Disable stop condition detection interrupt (SPIn) request
1: Enable stop condition detection interrupt (SPIn) request.
R/W
b4
NAKIE
NACK Reception Interrupt Request
Enable
0: Disable NACK reception interrupt (NAKIn) request
1: Enable NACK reception interrupt (NAKIn) request.
R/W
b5
RIE
Receive Data Full Interrupt
Request Enable
0: Disable receive data full interrupt (IICn_RXI) request
1: Enable receive data full interrupt (IICn_RXI) request.
R/W
b6
TEIE
Transmit End Interrupt Request
Enable
0: Disable transmit end interrupt (IICn_TEI) request
1: Enable transmit end interrupt (IICn_TEI) request.
R/W
b7
TIE
Transmit Data Empty Interrupt
Request Enable
0: Disable transmit data empty interrupt (IICn_TXI) request
1: Enable transmit data empty interrupt (IICn_TXI) request.
R/W
TMOIE bit (Timeout Interrupt Request Enable)
The TMOIE bit enables or disables timeout interrupt (TMOIn) requests when the TMOF flag in the ICSR2 register is set
to 1. To cancel a TMOI interrupt request, set the TMOF flag or the TMOIE bit to 0.
ALIE bit (Arbitration-Lost Interrupt Request Enable)
The ALIE bit enables or disables arbitration-lost interrupt (ALIn) requests when the AL flag in the ICSR2 register is 1.
To cancel an ALI interrupt request, set the AL flag or the ALIE bit to 0.
STIE bit (Start Condition Detection Interrupt Request Enable)
The STIE bit enables or disables start condition detection interrupt (STIn) requests when the START flag in the ICSR2
register is 1. To cancel an STI interrupt request, set the START flag or the STIE bit to 0.
SPIE bit (Stop Condition Detection Interrupt Request Enable)
The SPIE bit enables or disables stop condition detection interrupt (SPIn) requests when the STOP flag in the ICSR2
register is 1. To cancel an SPI interrupt request, set the STOP flag or the SPIE bit to 0.
NAKIE bit (NACK Reception Interrupt Request Enable)
The NAKIE bit enables or disables NACK reception interrupt (NAKIn) requests when the NACKF flag in the ICSR2
register is 1. To cancel an NAKI interrupt request, set the NACKF flag or the NAKIE bit to 0.
RIE bit (Receive Data Full Interrupt Request Enable)
The RIE bit enables or disables receive data full interrupt (IICn_RXI) requests when the RDRF flag in the ICSR2 register
is 1.
TEIE bit (Transmit End Interrupt Request Enable)
The TEIE bit enables or disables transmit end interrupt (IICn_TEI) requests when the TEND flag in the ICSR2 register is
1. To cancel an IICn_TEI interrupt request, set the TEND flag or the TEIE bit to 0.
TIE bit (Transmit Data Empty Interrupt Request Enable)
The TIE bit enables or disables transmit data empty interrupt (IICn_TXI) requests when the TDRE flag in ICSR2 is 1.
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I2C Bus Status Register 1 (ICSR1)
26.2.9
Address(es): IIC0.ICSR1 4005 3008h, IIC1.ICSR1 4005 3108h
b7
b6
b5
b4
b3
b2
b1
b0
HOA
—
DID
—
GCA
AAS2
AAS1
AAS0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
AAS0
Slave Address 0 Detection Flag
0: Slave address 0 not detected
1: Slave address 0 detected.
R/(W)
*1
b1
AAS1
Slave Address 1 Detection Flag
0: Slave address 1 not detected
1: Slave address 1 detected.
R/(W)
*1
b2
AAS2
Slave Address 2 Detection Flag
0: Slave address 2 not detected
1: Slave address 2 detected.
R/(W)
*1
b3
GCA
General Call Address Detection
Flag
0: General call address not detected
1: General call address detected.
R/(W)
*1
b4
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b5
DID
Device-ID Address Detection Flag
0: Device-ID command not detected
1: Device-ID command detected.
This bit is set to 1 when the first frame received immediately after
a start condition is detected matches a value of (device ID (1111
100b) + 0[W]).
R/(W)
*1
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
HOA
Host Address Detection Flag
0: Host address not detected
1: Host address detected.
This bit is set to 1 when the received slave address matches the
host address (0001 000b).
R/(W)
*1
Note 1. Only 0 can be written to clear the flag.
AASy flag (Slave Address y Detection Flag) (y = 0 to 2)
[Setting conditions]
For 7-bit address format (SARUy.FS = 0):
When the received slave address matches the SVA[6:0] value in the SARLy register, with the SARyE bit in the
ICSER register set to 1 (slave address y detection enabled). The AASy flag is set to 1 on the rising edge of the ninth
SCL clock cycle in the frame.
For 10-bit address format (SARUy.FS = 1):
When the received slave address matches a value of (11110b + SVA[1:0] in SARUy), and the subsequent address
matches the SARLy value with the SARyE bit in the ICSER register set to 1 (slave address y detection enabled).
The AAsy flag is set to 1 on the rising edge of the ninth SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the AASy bit after reading AASy = 1
When a stop condition is detected
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
For 7-bit address format (SARUy.FS = 0):
When the received slave address does not match the SVA[6:0] value in the SARLy register, with the SARyE bit in
the ICSER register set to 1 (slave address y detection enabled). The AASy flag is set to 0 on the rising edge of the
ninth SCL clock cycle in the frame.
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For 10-bit address format (SARUy.FS = 1):
When the received slave address does not match a value of (11110b + SVA[1:0] in SARUy), with the SARyE bit in
the ICSER register set to 1 (slave address y detection enabled). The AASy flag is set to 0 on the rising edge of the
ninth SCL clock cycle in the frame.
When the received slave address matches a value of (11110b + SVA[1:0] in SARUy), and the subsequent address
does not match the SARLy value with the SARyE bit in the ICSER register set to 1 (slave address y detection
enabled). The AASy flag is set to 0 on the rising edge of the ninth SCL clock cycle in the frame.
GCA flag (General Call Address Detection Flag)
[Setting condition]
When the received slave address matches the general call address (0000 000b + 0 [W]), with the GCAE bit in the
ICSER register set to 1 (general call address detection enabled). The GCA flag is set to 1 on the rising edge of the
ninth SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the GCA bit after reading GCA = 1
When a stop condition is detected
When the received slave address does not match the general call address (0000 000b + 0 [W]), with the GCAE bit in
the ICSER register set to 1 (general call address detection enabled). The GCA flag is set to 0 on the rising edge of
the ninth SCL clock cycle in the frame.
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
DID flag (Device-ID Address Detection Flag)
[Setting condition]
When the first frame received immediately after a start or restart condition is detected matches a value of (device ID
(1111 100b) + 0 [W]), with the DIDE bit in the ICSER register set to 1 (device-ID address detection enabled). The
DID flag is set to 1 on the rising edge of the ninth SCL clock cycle in the frame.
[Clearing conditions]
When 0 is written to the DID bit after reading DID = 1
When a stop condition is detected
When the first frame received immediately after a start or restart condition is detected does not match a value of
(device ID (1111 100b)), with the DIDE bit in the ICSER register set to 1 (device-ID address detection enabled).
The DID flag is set to 0 on the rising edge of the ninth SCL clock cycle in the frame.
When the first frame received immediately after a start or restart condition is detected matches a value of (device ID
(1111 100b) + 0 [W]), and the second frame does not match any slave address from 0 to 2, with the DIDE bit in the
ICSER register set to 1 (device-ID address detection enabled). The DID flag is set to 0 on the rising edge of the
ninth SCL clock cycle in the frame.
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
HOA flag (Host Address Detection Flag)
[Setting condition]
When the received slave address matches the host address (0001 000b), with the HOAE bit in the ICSER register set
to 1 (host address detection enabled). The HOA flag is set to 1 on the rising edge of the ninth SCL clock cycle in the
frame.
[Clearing conditions]
When 0 is written to the HOA bit after reading HOA = 1
When a stop condition is detected
When the received slave address does not match the host address (0001 000b), with the HOAE bit in the ICSER
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register set to 1 (host address detection enabled). The HOA flag is set to 0 on the rising edge of the ninth SCL clock
cycle in the frame.
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
I2C Bus Status Register 2 (ICSR2)
26.2.10
Address(es): IIC0.ICSR2 4005 3009h, IIC1.ICSR2 4005 3109h
b7
b6
TDRE
TEND
0
0
Value after reset:
b5
b4
b3
b2
RDRF NACKF STOP START
0
0
0
0
b1
b0
AL
TMOF
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TMOF
Timeout Detection Flag
0: Timeout not detected
1: Timeout detected.
R/(W)
*1
b1
AL
Arbitration-Lost Flag
0: Arbitration not lost
1: Arbitration lost.
R/(W)
*1
b2
START
Start Condition Detection Flag
0: Start condition not detected
1: Start condition detected.
R/(W)
*1
b3
STOP
Stop Condition Detection Flag
0: Stop condition not detected
1: Stop condition detected.
R/(W)
*1
b4
NACKF
NACK Detection Flag
0: NACK not detected
1: NACK detected.
R/(W)
*1
b5
RDRF
Receive Data Full Flag
0: ICDRR contains no receive data
1: ICDRR contains receive data.
R/(W)
*1
b6
TEND
Transmit End Flag
0: Data being transmitted
1: Data transmit complete.
R/(W)
*1
b7
TDRE
Transmit Data Empty Flag
0: ICDRT contains transmit data
1: ICDRT contains no transmit data.
R
Note 1. Only 0 can be written, to clear the flag.
TMOF flag (Timeout Detection Flag)
The TMOF flag is set to 1 when the IIC detects a timeout because the SCLn line state remained unchanged for the set
period.
[Setting condition]
When the SCLn line state remains unchanged for the period specified in the ICMR2.TMOH, TMOL, and TMOS
bits when the ICFER.TMOE bit is 1 (timeout function enabled) in master or in slave mode, and the received slave
address matches.
[Clearing conditions]
When 0 is written to the TMOF bit after reading TMOF = 1
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
AL flag (Arbitration-Lost Flag)
The AL flag indicates that bus mastership was lost in arbitration because of a bus conflict or some other reason when a
start condition was issued or an address and data was transmitted. The IIC monitors the level on the SDAn line during
transmission and, if the level on the line does not match the value of the bit being output, sets the value of the AL flag to
1 to indicate that the bus is occupied by another device.
The IIC can also set the AL flag to indicate the detection of arbitration loss during NACK transmission in master mode
or during data transmission in slave mode.
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[Setting conditions]
When master arbitration-lost detection is enabled (ICFER.MALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of the SCL clock, except
for the ACK period during data transmission in master transmit mode
When a start condition is detected when the ST bit in the ICCR2 register is 1 (start condition requested) or the
internal SDA output state does not match the SDAn line level
When the ST bit in the ICCR2 register is 1 (start condition requested), with the BBSY flag in the ICCR2 register set
to 1.
When NACK arbitration-lost detection is enabled (ICFER.NALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of the SCL clock in the
ACK period during NACK transmission in receive mode.
When slave arbitration-lost detection is enabled (ICFER.SALE = 1):
When the internal SDA output state does not match the SDAn line level on the rising edge of the SCL clock, except
for the ACK period during data transmission in slave transmit mode.
[Clearing conditions]
When 0 is written to the AL flag after reading AL = 1
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
Table 26.4
Relationship between arbitration-lost generation sources and arbitration-lost enable functions
ICFER
ICSR2
MALE
NALE
SALE
AL
Error
Arbitration-lost generation source
1
×
×
1
Start condition
issuance error
When internal SDA output state does not match SDAn line level when a
start condition is detected, when the ST bit in the ICCR2 register is 1
1
Transmit data
mismatch
When transmit data (including slave address) does not match the bus
state in master transmit mode
When the ICCR2.ST in ICCR2 is set to 1 and ICCR2.BBSY bit is 1
×
1
×
1
NACK
transmission
mismatch
When ACK is detected during transmission of NACK in master or slave
receive mode
×
×
1
1
Transmit data
mismatch
When transmit data does not match the bus state in slave transmit mode
×: Don’t care
START flag (Start Condition Detection Flag)
[Setting condition]
When a start (or restart) condition is detected.
[Clearing conditions]
When 0 is written to the START bit after reading START = 1
When a stop condition is detected
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
STOP flag (Stop Condition Detection Flag)
[Setting condition]
When a stop condition is detected.
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[Clearing conditions]
When 0 is written to the STOP bit after reading STOP = 1
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
NACKF flag (NACK Detection Flag)
[Setting condition]
When acknowledge is not received (NACK received) from the receive device in transmit mode, with the NACKE
bit in the ICFER register set to 1 (transfer suspension enabled).
[Clearing conditions]
When 0 is written to the NACKF bit after reading NACKF = 1
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
Note:
When the NACKF flag is set to 1, the IIC suspends data transmission and reception. Writing to the ICDRT
register in transmit mode or reading from the ICDRR register in receive mode with the NACKF flag set to 1 does
not enable data transmit or receive operation. To restart data transmission or reception, set the NACKF flag to 0.
RDRF flag (Receive Data Full Flag)
[Setting conditions]
When receive data is transferred from the ICDRS register to the ICDRR register. The RDRF flag is set to 1 on the
rising edge of the eighth or ninth SCL clock cycle (selected in the RDRFS bit in the ICMR3 register).
When the received slave address matches, after a start (or restart) condition is detected, with the TRS bit in the
ICCR2 register set to 0.
[Clearing conditions]
When 0 is written to the RDRF bit after reading RDRF = 1
When data is read from the ICDRR register
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
TEND flag (Transmit End Flag)
[Setting condition]
On the rising edge of the ninth SCL clock cycle when the TDRE flag is 1.
[Clearing conditions]
When 0 is written to the TEND bit after reading TEND = 1
When data is written to the ICDRT register
When a stop condition is detected
When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
TDRE flag (Transmit Data Empty Flag)
[Setting conditions]
When data is transferred from the ICDRT register to the ICDRS register and the ICDRT register becomes empty
When the TRS bit in the ICCR2 register is set to 1
When the received slave address matches when the TRS bit is 1.
[Clearing conditions]
When data is written to the ICDRT register
When the TRS bit in the ICCR2 register is set to 0.
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When 1 is written to the IICRST bit in the ICCR1 register to apply an IIC reset or an internal reset.
Note:
When the NACKF flag is set to 1 when the NACKE bit in the ICFER register is 1, the IIC suspends data
transmission and reception. In this case, if the TDRE flag is 0 (next transmit data written), data is transferred to
the ICDRS register and the ICDRT register becomes empty on the rising edge of the ninth clock cycle, but the
TDRE flag is not set to 1.
I2C Bus Wakeup Unit Register (ICWUR)
26.2.11
Address(es): IIC0.ICWUR 4005 3016h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
WUE
WUIE
WUF
WUAC
K
—
—
—
WUAFA
0
0
0
1
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
WUAFA
Wakeup Analog Filter Additional Selection
0: Do not add the wakeup analog filter
1: Add the wakeup analog filter.
R/W
b3 to b1
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b4
WUACK
ACK bit for Wakeup Mode
Choice of four response modes in combination with
ICCR1.IICRST. See Table 26.5.
R/W
b5
WUF
Wakeup Event Occurrence Flag
0: Slave address not matching during wakeup
1: Slave address matching during wakeup.
R/W
b6
WUIE
Wakeup Interrupt Request Enable
0: Disable wakeup interrupt request (IIC0_WUI)
1: Enable wakeup interrupt request (IIC0_WUI).
R/W
b7
WUE
Wakeup Function Enable
0: Disable wakeup function
1: Enable wakeup function.
R/W
Table 26.5
Wakeup mode
IICRST
WUACK
Operation mode
Description
0
0
Normal wakeup mode 1
ACK response on ninth SCL and SCL low-hold, and after on ninth SCL
0
1
Normal wakeup mode 2
No ACK response immediately and SCL low-hold between eight and ninth
SCL. SCL low-hold release and ACK response on ninth SCL.
1
0
Command recovery mode
ACK response on ninth SCL and no SCL low-hold
1
1
EEP response mode
NACK response on ninth SCL and no SCL low-hold
WUF flag (Wakeup Event Occurrence Flag)
[Setting condition]
When PCLKB is supplied after a slave-address match in the first eighth SCL low during wakeup mode.
[Clearing conditions]
When 0 is written to the WUF bit after reading WUF = 1
ICE = 0 and IICRST = 1.
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26.2.12
Reserved (ICWUR2)
Address(es): IIC0.ICWUR2 4005 3017h
b7
b6
b5
b4
b3
—
—
—
—
—
1
1
1
1
1
Value after reset:
b2
b1
b0
WUSY WUAS WUSE
F
YF
N
1
1
1
Bit
Symbol
Bit name
b0
WUSEN
Reserved
This bit is read as 1. Writing to this bit has no effect.
R/W
b1
WUASYF
Reserved
This bit is read as 1.
R
b2
WUSYF
Reserved
This bit is read as 1.
R
b7 to b3
—
Reserved
These bits are read as 1.
R
26.2.13
Description
R/W
Slave Address Register Ly (SARLy) (y = 0 to 2)
Address(es): IIC0.SARL0 4005 300Ah, IIC1.SARL0 4005 310Ah,
IIC0.SARL1 4005 300Ch, IIC1.SARL1 4005 310Ch,
IIC0.SARL2 4005 300Eh, IIC1.SARL2 4005 310Eh
b7
b6
b5
b4
b3
b2
b1
SVA[6:0]
Value after reset:
0
0
0
0
b0
SVA0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SVA0
10-Bit Address LSB
Slave address setting
R/W
b7 to b1
SVA[6:0]
7-Bit Address/10-Bit Address Lower Bits
Slave address setting
R/W
SVA0 bit (10-Bit Address LSB)
When the 10-bit address format is selected (SARUy.FS = 1), the SVA0 bit functions as the LSB of a 10-bit address and is
combined with the SVA[6:0] bits to form the lower 8 bits of a 10-bit address.
When the SARyE bit in the ICSER register is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1, the
SVA0 bit is valid. When the SARUy.FS bit or SARyE bit is 0, the setting of the SVA0 bit is ignored.
SVA[6:0] bits (7-Bit Address/10-Bit Address Lower Bits)
When the 7-bit address format is selected (SARUy.FS = 0), the SVA[6:0] bits function as a 7-bit address. When the 10bit address format is selected (SARUy.FS = 1), the SVA[6:0] bits combine with the SVA0 bit to form the lower 8 bits of
a 10-bit address.
When the SARyE bit in the ICSER register is 0, the setting in the SVA[6:0] bits is ignored.
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26.2.14
Slave Address Register Uy (SARUy) (y = 0 to 2)
Address(es): IIC0.SARU0 4005 300Bh, IIC1.SARU0 4005 310Bh,
IIC0.SARU1 4005 300Dh, IIC1.SARU1 4005 310Dh,
IIC0.SARU2 4005 300Fh, IIC1.SARU2 4005 310Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
SVA[1:0]
0
0
0
0
0
0
b0
FS
0
0
Bit
Symbol
Bit name
Description
R/W
b0
FS
7-Bit/10-Bit Address Format Select
0: Select 7-bit address format
1: Select 10-bit address format.
R/W
b2, b1
SVA[1:0]
10-Bit Address Upper Bits
Slave address setting
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
FS bit (7-Bit/10-Bit Address Format Select)
The FS bit selects the 7-bit or 10-bit format for slave address y in the SARLy and SARUy registers.
When the SARyE bit in the ICSER register is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 0, the 7-bit
address format is selected for slave address y, the SVA[6:0] setting in SARLy is valid, and the SVA[1:0] bits and the
SVA0 bit in the SARLy register are ignored.
When the SARyE bit in the ICSER register is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1, the 10bit address format is selected for slave address y, and the SVA[1:0] bits and the SARLy register are valid.
When the SARyE bit in the ICSER register is 0 (SARLy and SARUy disabled), the SARUy.FS bit is invalid.
SVA[1:0] bits (10-Bit Address Upper Bits)
When the 10-bit address format is selected (FS = 1), the SVA[1:0] bits function as the upper 2 bits of a 10-bit address.
When the SARyE bit in the ICSER register is set to 1 (SARLy and SARUy enabled) and the SARUy.FS bit is 1, the
SVA[1:0] bits are valid. When the SARUy.FS or SARyE bit is 0, the setting in the SVA[1:0] bits is ignored.
I2C Bus Bit Rate Low-Level Register (ICBRL)
26.2.15
Address(es): IIC0.ICBRL 4005 3010h, IIC1.ICBRL 4005 3110h
b7
b6
—
Value after reset:
1
b5
b4
b3
—
1
1
b2
b1
b0
1
1
BRL[4:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
BRL[4:0]
Bit Rate Low-Level Period
Low-level period of SCL clock
R/W
b7 to b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
ICBRL is a 5-bit register that sets the low-level period of the SCL clock. The ICBRL register also works to generate the
data setup time for automatic SCL low-hold operation (see section 26.9, Automatic Low-Hold Function for SCL).
When the IIC is used only in slave mode, the ICBRL register must be set to a value longer than the data setup time*1. e
ICBRL register counts the low-level period with the internal reference clock source (IIC) specified in the CKS[2:0] bits
in the ICMR1 register. If the digital noise filter is enabled (NFE bit in the ICFER register is 1), set the ICBRL register to
a value at least 1 greater than the number of stages in the noise filter. For this number, see the description of the
ICMR3.NF[1:0] bits.
Note 1. Data setup time (tSU: DAT)
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250 ns for up to 100 kbps: Standard-mode (Sm)
100 ns for up to 400 kbps: Fast-mode (Fm)
I2C Bus Bit Rate High-Level Register (ICBRH)
26.2.16
Address(es): IIC0.ICBRH 4005 3011h, IIC1.ICBRH 4005 3111h
Value after reset:
b7
b6
b5
—
—
—
1
1
1
b4
b3
b2
b1
b0
1
1
BRH[4:0]
1
1
1
Bit
Symbol
Bit name
Description
R/W
b4 to b0
BRH[4:0]
Bit Rate High-Level Period
High-level period of SCL clock
R/W
b7 to b5
—
Reserved
These bits are read as 1. The write value should be 1.
R/W
ICBRH is a 5-bit register that sets the high-level period of the SCL clock. The ICBRH register is valid in master mode. If
the IIC is used only in slave mode, no setting is required in the ICBRH register.
The ICBRH register counts the high-level period with the internal reference clock source (IIC) specified in the
CKS[2:0] bits in the ICMR1 register. If the digital noise filter is enabled (the NFE bit in the ICFER register is 1), set the
ICBRH register to a value at least 1 greater than the number of stages in the noise filter. For this number, see the
description of the ICMR3.NF[1:0] bits.
The IIC transfer rate and the SCL clock duty are calculated using the following expression:
1) ICFER.SCLE = 0:
Transfer rate = 1/{[(BRH + 1) + (BRL + 1)]/IICφ*1 + tr*2 + tf*2}
Duty cycle = {tr + [(BRH + 1)/IICφ]}/{tr + tf + [(BRH + 1) + (BRL + 1)]/IICφ}
2) ICFER.SCLE = 1 and ICFER.NFE = 0 and CKS[2:0] = 000b (IICφ = PCLKB):
Transfer rate = 1/{[(BRH + 3) + (BRL+ 3)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 3)/IICφ]}/{tr + tf + [(BRH + 3) + (BRL + 3)]/IICφ}
3) ICFER.SCLE = 1 and ICFER.NFE = 1 and CKS[2:0] = 000b (IICφ = PCLKB):
Transfer rate = 1/{[(BRH + 3 + nf*3) + (BRL + 3 + nf)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 3 + nf)/IICφ]}/{tr + tf + [(BRH + 3 + nf) + (BRL + 3 + nf)]/IICφ}
4) ICFER.SCLE = 1 and ICFER.NFE = 0 and CKS[2:0] ≠ 000b:
Transfer rate = 1/{[(BRH + 2) + (BRL + 2)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 2)/IICφ]}/{tr + tf + [(BRH + 2) + (BRL + 2)]/IICφ}
5) ICFER.SCLE = 1 and ICFER.NFE = 1 and CKS[2:0] ≠ 000b:
Transfer rate = 1/{[(BRH + 2 + nf) + (BRL + 2 + nf)]/IICφ + tr + tf}
Duty cycle = {tr + [(BRH + 2 + nf)/IICφ]}/{tr + tf + [(BRH + 2 + nf) + (BRL + 2 + nf)]/IICφ}
Note 1. IICφ = PCLKB × Division ratio
Note 2. The SCLn line rise time [tr] and SCLn line fall time [tf] depend on the total bus line capacitance [Cb] and the pullup resistor [Rp]. For details, see the I2C bus standard from NXP Semiconductors.
Note 3. nf = Number of digital noise filters selected in the ICMR3.NF bit.
Table 26.6
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 0
Transfer rate (kbps)
CKS[2:0]
BRH[4:0]
BRL[4:0]
PCLKB[MHz]
NF[1:0]
Computation expression
100
011
16 (10h)
16 (10h)
32
—
1)
400
001
14 (0Eh)
14 (0Eh)
32
—
1)
Note:
SCLn line rising time (tr): 100 kbps or less, [Sm]: 1000 ns, 400 kbps or less, [Fm]: 300 ns
SCLn line falling time (tf): 400 kbps or less, [Sm/Fm]: 300 ns.
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Table 26.7
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 1 and NFE = 0
Transfer rate (kbps)
CKS[2:0]
BRH
BRL
PCLKB[MHz]
NF[1:0]
Computation expression
100
011
15 (0Fh)
15 (0Fh)
32
—
4)
400
001
13 (0Dh)
13 (0Dh)
32
—
4)
Note:
SCLn line rising time (tr): 100 kbps; Sm: 1000 ns, 400 kbps; Fm: 300 ns
SCLn line falling time (tf): 400 kbps; Sm/Fm: 300 ns.
Table 26.8
Example of ICBRH/ICBRL settings for transfer rate when SCLE = 1 and NFE = 1
Transfer rate (kbps)
CKS[2:0]
BRH
BRL
PCLKB[MHz]
NF[1:0]
Computation expression
100
011
13 (0Dh)
13 (0Dh)
32
01b
5)
400
001
11 (0Bh)
11 (0Bh)
32
01b
5)
Note:
SCLn line rising time (tr): 100 kbps; Sm: 1000 ns, 400 kbps; Fm: 300 ns
SCLn line falling time (tf): 400 kbps; Sm/Fm: 300 ns.
26.2.17
I2C Bus Transmit Data Register (ICDRT)
Address(es): IIC0.ICDRT 4005 3012h, IIC1.ICDRT 4005 3112h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
When the ICDRT register detects a space in the I2C Bus Shift Register (ICDRS), it transfers the transmit data that was
written to the ICDRT register to the ICDRS register and starts transmitting data in transmit mode. The double-buffer
structure of the ICDRT and ICDRS registers allows continuous transmit operation if the next transmit data is written to
the ICDRT register while the ICDRS register data is being transmitted.
The ICDRT register can always be read from and written to. Write transmit data to the ICDRT register once when a
transmit data empty interrupt (IICn_TXI) request is generated.
26.2.18
I2C Bus Receive Data Register (ICDRR)
Address(es): IIC0.ICDRR 4005 3013h, IIC1.ICDRR 4005 3113h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
When 1 byte of data is received, the received data is transferred from the I2C Bus Shift Register (ICDRS) to the ICDRR
register to enable the next data to be received. The double-buffer structure of the ICDRS and ICDRR registers allows
continuous receive operation if the received data is read from the ICDRR register while the ICDRS register is receiving
data. The ICDRR register cannot be written to. Read data from v once when a receive data full interrupt (IICn_RXI)
request is generated.
If the ICDRR register receives the next receive data before the current data is read from the ICDRR register (when the
RDRF flag in ICSR2 is 1), the IIC automatically holds the SCL low for 1 clock cycle before the RDRF flag is set to 1
next.
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I2C Bus Shift Register (ICDRS)
26.2.19
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
ICDRS is an 8-bit shift register for data transmit and receive. During transmission, transmit data is transferred from the
ICDRT register to the ICDRS register and is sent from the SDAn pin. During reception, data is transferred from the
ICDRS register to the ICDRR register after 1 byte of data is received. The ICDRS register cannot be accessed directly.
26.3
Operation
26.3.1
Communication Data Format
The I2C bus format consists of 8-bit data and 1-bit acknowledge. The frame following a start or restart condition is an
address frame that specifies a slave device with which the master device communicates. The specified slave is valid until
a new slave is specified or a stop condition is issued.
Figure 26.3 shows the I2C bus format, and Figure 26.4 shows the I2C bus timing.
[7-bit address format]
S
SLA (7 bits)
R/W#
A
1
7
1
1
DATA (8 bits)
8
A
A/A#
P
1
1
1
n (n = 1 or more)
[10-bit address format]
S
11110b+SLA(2 bits) W#
1
7
1
A
SLA (8 bits)
A
DATA (8 bits)
A
A/A#
P
1
8
1
8
1
1
1
n (n = 1 or more)
S 11110b+SLA(2 bits) W#
A
SLA (8 bits)
A
Sr 11110b+SLA(2 bits)
R
A
DATA (8 bits)
A
A/A#
P
1
1
8
1
1
1
1
8
1
1
1
7
1
7
n (n = 1 or more)
n: Number of transfer frames
Figure 26.3
SCLn
I2C bus format
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDAn
S
Figure 26.4
SLA
R/W#
A
Data
A
Data
A
P
I2C bus timing (SLA = 7 bits)
S:
Start condition. The master device drives the SDAn line low from high while the SCLn line is high.
SLA:
Slave address, by which the master device selects a slave device.
R/W#:
Indicates the direction of data transfer: from the slave device to the master device when R/W# is 1, or from the master device
to the slave device when R/W# is 0.
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A:
Acknowledge. The receive device drives the SDAn line low. (In master transmit mode, the slave device returns acknowledge.
In master receive mode, the master device returns acknowledge.)
A#:
Not Acknowledge. The receive device drives the SDAn line high.
Sr:
Restart condition. The master device drives the SDAn line low from the high level after the setup time has elapsed with the
SCLn line high.
DATA:
Transmitted or received data.
P:
Stop condition. The master device drives the SDAn line high from low when the SCLn line is high.
26.3.2
Initial Settings
Before starting data transmission or reception, initialize the IIC using the procedure shown in Figure 26.5.
1. Set the ICCR1.ICE bit to 0 to set the SCLn and SDAn pins to the inactive state.
2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset.
3. Set the ICCR1.ICE bit to 1 to initiate internal reset.
4. Set the SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL registers (y = 0 to 2), and set the other registers as
necessary. For initial settings of the IIC, see Figure 26.5.
5. When the necessary register settings are complete, set the ICCR1.IICRST bit to 0 to release the IIC reset.
Note:
This procedure is not necessary if initialization of the IIC is already complete.
Initial settings
Set ICE in ICCR1 to 0
Set IICRST in ICCR1 to 1
Set ICE in ICCR1 to 1
Set SARLy and SARUy.
Set ICSER
Set CKS[2:0] in ICMR1 and
ICBRL/ICBRH
SCLn, SDAn pins not driven
IIC reset
Internal reset, SCLn and SDAn pins in active state
Set slave address format and slave address
Set transfer bit rate*1
Set ICMR2 and ICMR3
*2
Set ICFER
Set ICIER
Set IICRST in ICCR1 to 0
Set interrupt enable
Release from the internal reset state
End
y = 0 to 2
Note 1. When the IIC is used only in slave mode, set the ICBRL register to a value longer than the data setup time.
Note 2. Set these registers as required.
Figure 26.5
Example IIC initialization flow
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26.3.3
26. I2C Bus Interface (IIC)
Master Transmit Operation
In master transmit operation, the IIC outputs the SCL clock and transmitted data signals as the master device, and the
slave device returns acknowledgments. Figure 26.6 shows an example of master transmission, and Figure 26.7 to Figure
26.9 show the timing of operations in master transmission.
To set up and perform master transmission:
1. Initial settings. For details, see section 26.3.2, Initial Settings.
2. Read the ICCR2.BBSY flag to check that the bus is open, then set the ICCR2.ST bit to 1 (start condition request).
On receiving the request, the IIC issues a start condition. At the same time, the ICSR2.BBSY and ICSR2.START
flags automatically set to 1, and the ICCR2.ST bit is automatically set to 0. If the start condition is detected and the
internal level for the SDA output state and the level on the SDAn line match while the ST bit is 1, the IIC recognizes
that the start condition requested by the ST bit has successfully complete, and the ICCR2.MST and ICCR2.TRS bits
automatically set to 1, placing the IIC in master transmit mode. The ICSR2.TDRE flag is also automatically set to 1
in response to the setting of the TRS bit to 1.
3. Check that the ICSR2.TDRE flag is 1, then write the value for transmission (the slave address and the R/W# bit) to
the ICDRT register. When the transmit data is written to the ICDRT register, the TDRE flag is automatically set to
0, the data is transferred from the ICDRT register to the ICDRS register, and the TDRE flag is again set to 1. After
the byte containing the slave address and R/W# bit is transmitted, the value of the TRS bit automatically updates to
select master transmit or master receive mode according to the value of the transmitted R/W# bit. If the value of the
R/W# bit was 0, the IIC continues in master transmit mode.
If the ICSR2.NACKF flag is 1, indicating that no slave device recognized the address or there was an error in
communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For data transmission with an address in the 10-bit format, start by writing 1111 0b, the 2 upper-order bits of the
slave address, and W to the ICDRT register as the first address transmission. For the second address transmission,
write the 8 lower-order bits of the slave address to the ICDRT register.
4. Check that the ICSR2.TDRE flag is 1, then write the transmit data to the ICDRT register. The IIC automatically
holds the SCLn line low until the transmit data is ready or a stop condition is issued.
5. After all bytes of transmit data are written to the ICDRT register, wait until the value in the ICSR2.TEND flag
returns to 1, then set the ICCR2.SP bit to 1 (stop condition requested). On receiving a stop condition request, the IIC
issues the stop condition. For information on issuing a stop condition, see section 26.11.3, Issuing a Stop Condition.
6. On detecting the stop condition, the IIC automatically sets the ICCR2.MST and ICCR2.TRS bits to 0 and enters
slave receive mode. Additionally, the IIC automatically sets the ICSR2.TDRE and ICSR2.TEND flags to 0, and sets
the ICSR2.STOP flag to 1.
7. Check that the ICSR2.STOP flag is 1, and then set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
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Master transmission
[1] Initial settings
Initial settings
No
ICCR2.BBSY = 0?
[2] Check IIC bus occupation and issue a
start condition
Yes
ICCR2.ST = 1
ICSR2.NACKF = 0?
No
Yes
No
ICSR2.TDRE = 1?
Yes
[3] Transmit slave address and W (first byte)
[4] Check ACK and set transmit data
Write data to ICDRT
No
All data transmitted?
Yes
No
ICSR2.TEND = 1?
Yes
ICSR2.STOP = 0
[5] Check end of last data transmission and
issue a stop condition
ICCR2.SP = 1
No
ICSR2.STOP = 1?
[6] Check stop condition issuance
Yes
ICSR2.NACKF = 0
[7] Processing for the next transfer operation
ICSR2.STOP = 0
End of master transmission
Figure 26.6
Example master transmission flow
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Automatic low-hold (to prevent wrong transmission)
S
1
2
b7
b6
3
4
5
6
7
8
b5
b4
b3
b2
b1
b0
9
1
2
3
4
5
6
7
8
9
b7
b6
b5
b4
b3
b2
b1
b0
ACK
1
2
3
4
b7
b6
b5
SCLn
SDAn
ACK
W
7-bit slave address
DATA 1
b4
DATA 2
BBSY
MST
TRS
Transmit data (7-bit address + W)
Transmit data (DATA 1)
Transmit data (DATA 2)
TDRE
TEND
RDRF
ICDRT
DATA 1
7-bit address + W
DATA 2
7-bit address + W
ICDRS
DATA 3
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
START
ST
Write data to
Write data to
Write 1
ICDRT
ICDRT
to ST (7-bit address + W)
(DATA 1)
[2]
[3]
Figure 26.7
Write data to
ICDRT
(DATA 2)
Write data to
ICDRT
(DATA 3)
[4]
[4]
[4]
Master transmit operation timing (1) (7-bit address format)
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
8
9
1
2
b0
ACK
b7
b6
3
4
5
6
7
8
9
1
2
3
4
b5
b4
b3
b2
b1
b0
ACK
b7
b6
b5
b4
SCLn
SDAn
Upper 10-bit addresses (11110b + 2 bits)
Lower 10-bit addresses
W
DATA 1
BBSY
MST
TRS
Transmit data (upper 10 bits + W)
Transmit data (DATA 1)
Transmit data (lower 10 bits)
TDRE
TEND
RDRF
ICDRT
DATA 1
Lower 10 bits
10-bit address + W
Upper 10 bits + W
ICDRS
DATA 1
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
ACKBR
DATA 2
Lower 10 bits
X (ACK/NACK)
0 (ACK)
0 (ACK)
START
ST
Write data to
Write data to
Write 1
ICDRT
ICDRT
to ST (11110b + 2
(lower 8 bits)
bits + W)
[2]
[3]
Figure 26.8
Write data to
ICDRT
(DATA 1)
Write data to
ICDRT
(DATA 2)
[4]
[4]
Master transmit operation timing (2) (10-bit address format)
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7
8
9
1
2
3
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
b4
b3
b2
b1
b0
ACK
b7
b6
b5
b4
b3
b2
b1
b0
A/NA
SCLn
SDAn
DATA n-2
DATA n-1
DATA n
BBSY
MST
TRS
Transmit data (DATA n)
Transmit data (DATA n-1)
TDRE
TEND
RDRF
ICDRT
DATA n-1
ICDRS
DATA n-2
DATA n
DATA n-1
DATA n
XXXX (Initial value/final receive data)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
ACKBR
0 (ACK)
X (ACK/NACK)
STOP
SP
Figure 26.9
26.3.4
Write data to ICDRT
(Final transmit data [DATA n])
Write 1
to SP
Clear
STOP to 0
[4]
[5]
[7]
Master transmit operation timing (3)
Master Receive Operation
In master receive operation, the IIC as a master device outputs the SCL clock, receives data from the slave device, and
returns acknowledgments. Because the IIC must start by sending a slave address to the associated slave device, the slave
address phase of the procedure is performed in master transmit mode, but the subsequent steps are performed in master
receive mode.
Figure 26.10 and Figure 26.11 show examples of master reception (7-bit address format), and Figure 26.12 to Figure
26.14 show the timing of operations in master reception.
To set up and perform master reception:
1. IIC initial settings. For details, see section 26.3.2, Initial Settings.
2. Read the ICCR2.BBSY flag to check that the bus is open, then set the ICCR2.ST bit to 1 (start condition request).
On receiving the request, the IIC issues a start condition. When the IIC detects the start condition, the ICSR2.BBSY
the ICSR2.START flags automatically set to 1, and the ICCR2.ST bit is automatically set to 0. If the start condition
is detected and the level for the SDA output and the level on the SDAn line match while the ST bit is 1, the IIC
recognizes that the start condition requested by the ST bit has successfully complete, and the ICCR2.MST and
ICCR2.TRS bits automatically set to 1, placing the IIC in master transmit mode. The ICSR2.TDRE flag is also
automatically set to 1 in response to the setting of the ICCR2.TRS bit to 1.
3. Check that the ICSR2.TDRE flag is 1, then write the value for transmission (the first byte indicates the slave address
and value of the R/W# bit) to the ICDRT register. When the transmit data is written to the ICDRT register, the
ICSR2.TDRE flag is automatically set to 0, the data is transferred from the ICDRT register to the ICDRS register,
and the ICSR2.TDRE flag is again set to 1. When the byte containing the slave address and R/W# bit is transmitted,
the value of the ICCR2.TRS bit automatically updates to select transmit or receive mode according to the value of
the transmitted R/W# bit. If the value of the R/W# bit was 1, the ICCR2.TRS bit is set to 0 on the rising edge of the
ninth cycle of the SCL clock, placing the IIC in master receive mode. At this time, the ICSR2.TDRE flag is set to 0
and the ICSR2.RDRF flag is automatically set to 1.
If the ICSR2.NACKF flag is 1, indicating that no slave device recognized the address or there was an error in
communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit
address, then issue a restart condition. After issuing a restart condition, transmit 1111 0b, the two upper-order bits of
the slave address, and the R bit to place the IIC in master receive mode.
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26. I2C Bus Interface (IIC)
4. Dummy read the ICDRR register after confirming that the ICSR2.RDRF flag is 1. Doing so causes the IIC to start
output of the SCL clock and start data reception.
5. After 1 byte of data is received, the ICSR2.RDRF flag is set to 1 on the rising edge of the eighth or ninth cycle of the
SCL clock, as selected in the ICMR3.RDRFS bit. Reading the ICDRR register produces the received data, and the
ICSR2.RDRF flag is automatically set to 0. The value of the acknowledgment field received during the ninth cycle
of the SCL clock is returned as the value set in the ICMR3.ACKBT bit. If the next byte to be received is the next-tolast byte, set the ICMR3.WAIT bit to 1 for wait insertion before reading the ICDRR register, containing the second
byte from the last. In addition to enabling NACK output, even when interrupts or other operations result in delays in
setting the ICMR3.ACKBT bit to 1 (NACK) in step (6), this fixes the SCLn line to the low level on the rising edge
of the ninth clock cycle in reception of the last byte, which enables the issuing of a stop condition.
6. When the ICMR3.RDRFS bit is 0, and the slave device must be notified that it is to end transfer for data reception
after transfer of the next and final byte, set the ICMR3.ACKBT bit to 1 (NACK).
7. After reading the next-to-last byte from the ICDRR register, if the value of the ICSR2.RDRF flag is 1, write 1 to the
ICCR2.SP bit (stop condition requested), then read the last byte from the ICDRR register. When the ICDRR register
is read, the IIC is released from the wait state and issues the stop condition after low-level output in the ninth clock
cycle is complete or the SCLn line is released from the low-hold state.
8. On detecting the stop condition, the IIC automatically sets the ICCR2.MST and ICCR2.TRS bits to 0 and enters
slave receive mode. Additionally, detection of the stop condition sets the ICSR2.STOP flag to 1.
9. Check that the ICSR2.STOP flag is 1, then set the ICSR2.NACKF and ICSR2.STOP flags to 0 for the next transfer
operation.
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Master reception starts
Initial settings
No
(1) Initial settings
ICCR2.BBSY = 0?
(2) Check IIC bus occupation and issue a start condition
Yes
ICCR2.ST = 1
No
ICSR2.TDRE = 1?
Yes
Write to the ICDRT register
No
(3) Transmit the slave address followed by
R and check ACK
ICSR2.RDRF = 1?
Yes
ICSR2.NACKF = 0?
No
Yes
ICMR3.WAIT = 1
Next data = last byte?
(4) Set to WAIT
Yes
No
Dummy read the ICDRR register
No
(5) Set to NACK
When receiving 2 bytes, perform dummy
read.
ICSR2.RDRF = 1?
Yes
Set ICMR3.ACKBT
(6) Read received data
When receiving 1 byte, perform
dummy read.
Read the ICDRR register
No
ICSR2.RDRF = 1?
Yes
ICSR2.STOP = 0
ICSR2.STOP = 0
ICCR2.SP = 1
ICCR2.SP = 1
Read the ICDRR register
Dummy read the ICDRR register
(7) Read the last data,
release SCL with the ACKBT setting,
and generate a stop condition
ICMR3.WAIT = 0
No
ICSR2.STOP = 1?
(8) Confirm that the stop condition
has been generated
Yes
ICSR2.NACKF = 0
ICSR2.STOP = 0
(9) Processing for the next transfer operation
Master reception ends
Figure 26.10
Example of master reception flow with 7-bit address format of 1 or 2 bytes
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Master reception
Initial settings
No
[1] Initial settings
ICCR2.BBSY = 0?
[2] Check IIC bus occupation and issue a start
condition
Yes
ICCR2.ST = 1
No
ICSR2.TDRE = 1?
Yes
Write data to ICDRT
No
[3] Transmit the slave address followed by R and
check ACK
ICSR2.RDRF = 1?
Yes
No
ICSR2.NACKF = 0?
Yes
[4] Perform dummy read
Perform dummy read of ICDRR
No
ICSR2.RDRF = 1?
Yes
Next data = Final byte - 1?
No
Next data = Final byte - 2?
No
Yes
[5] Read received data and prepare for receiving
final data
Yes
ICMR3.WAIT = 1
Read ICDRR
Set ICMR3.ACKBT
[6] Set the acknowledgment and read data of
(final byte – 1 byte)
Read ICDRR
No
ICSR2.RDRF = 1?
Yes
ICSR2.STOP = 0
ICSR2.STOP = 0
ICCR2.SP = 1
ICCR2.SP = 1
Read ICDRR
Perform dummy read of ICDRR
[7] Read final data and issue a stop
condition
ICMR3.WAIT = 0
No
ICSR2.STOP = 1?
[8] Check stop condition issuance
Yes
ICSR2.NACKF = 0
[9] Processing for the next transfer operation
ICSR2.STOP = 0
End of master reception
Figure 26.11
Example master reception flow with 7-bit address format of 3 or more bytes
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Automatic low hold
(to prevent wrong transmission)
S
Master transmit mode
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
Master receive mode
8
9
1
2
3
4
5
6
7
8
ACK
b7
b6
b5
b4
b3
b2
b1
b0
9
1
2
3
b7
b6
b5
4
SCLn
SDAn
7-bit slave address
b0
R
ACK
DATA 1
b4
DATA 2
BBSY
MST
TRS
Transmit data (7-bit address + R)
TDRE
Receive data (7-bit address + R)
TEND
Receive data (DATA 1)
RDRF
7-bit address + R
ICDRT
ICDRS
7-bit address + R
ICDRR
XXXX (Initial value/last data for reception)
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
DATA 1
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
START
ST
Write 1 Write data to ICDRT
to ST (7-bit address + R)
[2]
[3]
Figure 26.12
Read ICDRR
(Dummy read)
Read ICDRR
(DATA 1)
[4]
[5]
Master receive operation timing (1) with 7-bit address format when RDRFS = 0
Master transmit mode
Automatic low hold (to prevent wrong transmission)
1 to 7
S
8
1 to 8
9
9
Sr
1
2
3
4
b6
b5
b4
5
6
7
b2
b1
Master receive mode
8
9
1
2
3
ACK
b7
b6
b5
4
SCLn
SDAn
b7
b1
Upper 10 bits
b0
W
ACK
b7
b0
ACK
Lower 10 bits
b7
b3
Upper 10-bit addresses (11110b + 2 bits)
b0
R
b4
DATA 1
BBSY
MST
TRS
Transmit data (upper 10 bits + W)Transmit data (lower 10 bits)
Transmit data (upper 10 bits + R)
TDRE
Transmit data (upper 10 bits + R)
TEND
RDRF
ICDRT
Upper 10 bits + W
ICDRS
Upper 10 bits + W
Upper 10 bits + R
Lower 10 bits
Lower 10 bits
Upper 10 bits + R
XXXX (Initial value/last data for reception)
ICDRR
DATA 1
XXXX (Initial value/last data for reception )
0 (ACK)
ACKBT
0 (ACK)
X (ACK/NACK)
ACKBR
0 (ACK)
0 (ACK)
START
ST
RS
Write 1 Write data to ICDRT
to ST (11110b + 2 bits + W)
Write data to
ICDRT
(lower 8 bits)
[2]
Figure 26.13
Clear
START to 0
Write 1 Write data to ICDRT
to RS (11110b + 2 bits + R)
Read ICDRR
(Dummy read)
[3]
[4]
Master receive operation timing (2) with 10-bit address format when RDRFS = 0
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26. I2C Bus Interface (IIC)
S124 User’s Manual
Automatic low hold (WAIT)
7
8
9
1
2
3
b1
b0
ACK
b7
b6
b5
Automatic low hold (WAIT)
4
5
6
7
8
9
1
2
3
b4
b3
b2
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
9
b4
b3
b2
b1
b0
NACK
P
SCLn
SDAn
DATA n-2
DATA n-1
DATA n
BBSY
MST
TRS
TDRE
TEND
Receive data (DATA n-1)
Receive data (DATA n-2)
Receive data (DATA n)
RDRF
XXXX (last data for transmission
[7-bit addresses + R/Upper 10 bits + R])
ICDRT
ICDRS
ICDRR
DATA n-2
DATA n-2
DATA n-1
0 (ACK)
ACKBT
ACKBR
DATA n
DATA n-1
DATA n-3
0 (ACK)
DATA n
1 (NACK)
0
0 (ACK)
0 (ACK)
1 (NACK)
STOP
SP
WAIT
Write 1
to WAIT
Read ICDRR
(DATA n-2)
[5]
Figure 26.14
26.3.5
Write 1
Read ICDRR
to ACKBT (DATA n-1)
[6]
Write 1
to SP
Read ICDRR
Clear
Clear
(last data for reception
WAIT to 0 STOP to 0
[DATA n])
[7]
[9]
Master receive operation timing (3) when RDRFS = 0
Slave Transmit Operation
In a slave transmit operation, the master device outputs the SCL clock, the IIC transmits data as a slave device, and the
master device returns acknowledgments.
Figure 26.15 shows an example of slave transmission, and Figure 26.16 and Figure 26.17 show the operation timing in
slave transmission.
To set up and perform slave transmission:
1. IIC initial settings. For details, see section 26.3.2, Initial Settings.
After the initial settings, the IIC stays in the standby state until it receives a slave address that it matches.
2. After receiving a matching slave address, the IIC sets one of the associated ICSR1.HOA, GCA, and AASy bits (y =
0 to 2) to 1 on the rising edge of the ninth cycle of the SCL clock and outputs the value set in the ICMR3.ACKBT
bit to the acknowledge bit on the ninth cycle of the SCL clock. If the value of the received R/W# bit is 1, the IIC
automatically places itself in slave transmit mode by setting both the ICCR2.TRS bit and the ICSR2.TDRE flag to
1.
3. Check that the ICSR2.TEND flag is 1, then write the transmit data to the ICDRT register. If the IIC receives no
acknowledge from the master device (receives an NACK signal) when the ICFER.NACKE bit is 1, the IIC suspends
transfer of the next data.
4. Wait unit the ICSR2.TEND flag is set to 1 while the ICSR2.TDRE flag is 1, after the ICSR2.NACKF flag is set to 1
or the last byte for transmission is written to the ICDRT register. When the ICSR2.NACKF flag or the TEND flag is
1, the IIC drives the SCLn line low on the ninth falling edge of the SCL clock.
5. When the ICSR2.NACKF flag or the ICSR2.TEND flag is 1, dummy read the ICDRR register to complete the
processing and release the SCLn line.
6. On detecting the stop condition, the IIC automatically sets the ICSR1.HOA, GCA, and AASy bits (y = 0 to 2), the
ICSR2.TDRE and TEND flags, and the ICCR2.TRS bit to 0, and enters slave receive mode.
7. Check that the ICSR2.STOP flag is 1, and then set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
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S124 User’s Manual
Slave transmission
[1] Initial settings
Initial settings
ICSR2.NACKF = 0?
No
Yes
No
ICSR2.TDRE = 1?
Yes
Write data to ICDRT
[2], [3] Check ACK and set transmit data
Checking of ACK not necessary immediately after
address is received
No
All data transmitted?
Yes
No
ICSR2.TEND = 1?
Yes
Read ICDRR
No
ICSR2.STOP = 1?
[4] Dummy read to release the SCL
[5] Check for stop condition detection
Yes
ICSR2.NACKF = 0
[6] Processing for the next transfer operation
ICSR2.STOP = 0
End of slave transmission
Figure 26.15
Example slave transmission flow
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S124 User’s Manual
Slave receive mode
S
1
2
b7
b6
Slave transmit mode
3
4
5
6
7
8
b5
b4
b3
b2
b1
b0
9
1
2
3
b7
b6
b5
Automatic low hold (to prevent wrong transmission)
4
5
6
7
8
b4
b3
b2
b1
b0
9
1
2
b7
b6
3
4
b5
b4
SCLn
SDAn
7-bit slave address
ACK
R
ACK
DATA 1
DATA 2
BBSY
MST
TRS
Transmit data (DATA 2)
Transmit data (DATA 1)
TDRE
TEND
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
DATA 1
DATA 2
7-bit address + R
ICDRS
DATA 3
DATA 1
DATA 2
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
X (ACK/NACK)
ACKBR
0 (ACK)
0 (ACK)
START
NACKF
Write data to Write data to
ICDRT
ICDRT
(DATA 2)
(DATA 1)
[3]
Figure 26.16
Write data to
ICDRT
(DATA 3)
[3]
[3]
Slave transmit operation timing (1) with 7-bit address format
7
8
9
1
2
3
b1
b0
ACK
b7
b6
b5
4
5
6
7
8
b4
b3
b2
b1
b0
9
1
2
3
b7
b6
b5
4
5
6
7
8
b4
b3
b2
b1
b0
9
P
SCLn
SDAn
DATA n-2
ACK
DATA n-1
NACK
DATA n
BBSY
MST
TRS
Transmit data (DATA n-1)
Transmit data (DATA n)
TDRE
TEND
RDRF
AASy
ICDRT
ICDRS
DATA n-1
DATA n
DATA n-2
DATA n-1
DATA n
XXXX (Initial value/last data for reception)
ICDRR
0 (ACK)
ACKBT
0 (ACK)
ACKBR
0 (ACK)
1 (NACK)
STOP
NACKF
Write data to ICDRT
(last data for transmission
[DATA n])
[4]
Figure 26.17
Dummy read ICDRR Clear
(SCLn line is released) NACKF
to 0
[5]
Clear
STOP
to 0
[7]
Slave transmit operation timing (2)
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26. I2C Bus Interface (IIC)
S124 User’s Manual
26.3.6
Slave Receive Operation
In slave receive operation, the master device outputs the SCL clock and transmit data, and the IIC returns
acknowledgments as a slave device.
Figure 26.18 shows an example of slave reception, and Figure 26.19 and Figure 26.20 show the operation timing in slave
reception.
To set up and perform slave reception:
1. IIC initial settings. For details, see section 26.3.2, Initial Settings.
After initialization, the IIC stays in the standby state until it receives a slave address that it matches.
2. After receiving a matching slave address, the IIC sets one of the associated ICSR1.HOA, GCA, and AASy bits (y =
0 to 2) to 1 on the rising edge of the ninth cycle of the SCL clock and outputs the value set in the ICMR3.ACKBT
bit to the acknowledge bit on the ninth cycle of the SCL clock. If the value of the received R/W# bit is 0, the IIC
continues to place itself in slave receive mode and sets the ICSR2.RDRF flag to 1.
3. Check that the ICSR2.STOP flag is 0 and the ICSR2.RDRF flag is 1, then dummy read the ICDRR register. The
dummy value consists of the slave address and R/W# bit when the 7-bit address format is selected, or the lower 8
bits when the 10-bit address format is selected.
4. When the ICDRR register is read, the IIC automatically sets the ICSR2.RDRF flag to 0. If reading of the ICDRR
register is delayed and a next byte is received while the RDRF flag is still set to 1, the IIC holds the SCLn line low
until 1 SCL cycle before the point where RDRF must be set. In this case, reading the ICDRR register releases the
SCLn line from being held at the low level.
When the ICSR2.STOP flag is 1 and the ICSR2.RDRF flag is also 1, read the ICDRR register until all the data is
completely received.
5. On detecting the stop condition, the IIC automatically sets the ICSR1.HOA, GCA, and AASy bits (y = 0 to 2) to 0.
6. Check that the ICSR2.STOP flag is 1, then set the ICSR2.STOP flag to 0 for the next transfer operation.
Slave reception
[1] Initial settings
Initial settings
ICSR2.STOP = 0?
No
Yes
No
ICSR2.RDRF = 1?
Yes
Yes
Read ICDRR
No
ICSR2.RDRF = 1?
Yes
No
[2], [3], [4] Read receive data
(Dummy read first)
Read ICDRR (last data)
All data received?
Yes
No
ICSR2.STOP = 1?
[5] Check stop condition detection
Yes
ICSR2.STOP = 0
[6] Processing for the next transfer
End of slave reception
Figure 26.18
Example slave reception flow
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S124 User’s Manual
Automatic low hold
(to prevent failure to receive data)
S
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
8
9
1
2
3
4
5
6
7
8
b7
b6
b5
b4
b3
b2
b1
b0
9
1
2
b7
b6
3
4
b5
b4
SCLn
SDAn
ACK
b0
7-bit slave address
W
ACK
DATA 1
DATA 2
BBSY
MST
TRS
TDRE
Receive data (7-bit address + W)
TEND
Receive data (DATA 1)
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
7-bit address + W
ICDRS
DATA 1
XXXX (Initial value/last data for reception)
ICDRR
DATA 2
DATA 1
7-bit address + W
0 (ACK)
ACKBT
X (ACK/NACK)
ACKBR
0 (ACK)
0 (ACK)
START
NACKF
Figure 26.19
Read ICDRR
(Dummy read
[7-bit address + W])
Read ICDRR
(DATA 1)
[3]
[3][4]
Slave receive operation timing (1) with 7-bit address format when RDRFS = 0
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
b1
b0
ACK
b7
b6
b5
b4
b3
b2
b1
b0
ACK
b7
b6
b5
b4
b3
b2
b1
b0
ACK
P
SCLn
SDAn
DATA n-2
DATA n-1
DATA n
BBSY
MST
TRS
TDRE
TEND
Receive data (DATA n-2)
Receive data (DATA n-1)
Receive data (DATA n)
RDRF
AASy
XXXX (Initial value/last data for transmission)
ICDRT
ICDRS
ICDRR
DATA n-2
DATA n
DATA n-1
DATA n-3
DATA n-2
DATA n-1
DATA n
0 (ACK)
ACKBT
0 (ACK)
0 (ACK)
ACKBR
0 (ACK)
STOP
NACKF
Figure 26.20
Read ICDRR
(DATA n-2)
Read ICDRR
(DATA n-1)
[3] [4]
[3] [4]
Read ICDRR
(DATA n)
[3] [4]
Clear
STOP to 0
[6]
Slave receive operation timing (2) when RDRFS = 0
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S124 User’s Manual
26.4
SCL Synchronization Circuit
To generate the SCL clock, the IIC starts counting the value for the high-level period specified in the ICBRH register
when it detects a rising edge on the SCLn line, then drives the SCLn line low when it completes counting. When the IIC
detects the falling edge of the SCLn line, it starts counting the value for the low-level period specified in the ICBRL
register, then stops driving the SCLn line (releases the line) when it completes counting. The IIC repeats this process to
generate the SCL clock.
If multiple master devices are connected to the I2C bus, a collision of SCL signals might arise because of contention with
another master device. In such cases, the master devices must synchronize their SCL signals. Because the
synchronization of SCL signals must be bit-by-bit, the IIC includes an SCL synchronization circuit to obtain bit-by-bit
synchronization of the SCL clock signals by monitoring the SCLn line while in master mode.
When the IIC detects a rising edge on the SCLn line and so starts counting out the high-level period specified in the
ICBRH register, and the level on the SCLn line falls because an SCL signal is being generated by another master device,
the IIC stops counting when it detects the falling edge, drives the level on the SCLn line low, and starts counting the lowlevel period specified in the ICBRL register. When the IIC finishes counting the low-level period, it stops driving the
SCLn line low to release the line. If the low-level period of the SCL clock signal from the other master device is longer
than the low-level period set in the IIC, the low-level period of the SCL signal is extended. When the low-level period for
the other master device has ended, the SCL signal rises because the SCLn line is released. When the IIC finishes
outputting the low-level period of the SCL clock, the SCLn line is released and the SCL clock rises. That is, when SCL
signals from more than one master are contending, the high-level period of the SCL signal is synchronized with that of
the clock with the narrower period, and the low-level period of the SCL signal is synchronized with that of the clock with
the broader period. However, such synchronization of the SCL signal is only enabled when the SCLE bit in the ICFER
register is set to 1.
[SCL clock generation]
Compare match
(Counter clear, low-drive start)
Rising of SCL detected
(High-level period count start)
ICBRH
ICBRH
ICBRH
SCLn
ICBRL
Falling of SCLn detected
(Low-level period count start)
[SCL synchronization]
ICBRL
Compare match
(Counter clear, SCLn line released)
Counter clear
ICBRH
Counter clear
Low-level output of
other master device
Low-level output of
other master device
ICBRH
ICBRH
SCLn
ICBRL
ICBRL
ICBRL
ICBRH: IIC bus bit rate high-level register (SCL clock high-level period counter)
ICBRL: IIC bus bit rate low-level register (SCL clock low-level period counter)
Figure 26.21
26.5
Generation and synchronization of SCL signal from IIC
SDA Output Delay Function
The IIC module incorporates a function for delaying output on the SDA line. The delay can be applied to all output on
the SDA line, including issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals.
With this function, SDA output is delayed from the detection of a falling edge of the SCL signal to ensure that the SDA
signal is output within the interval during which the SCL clock is low. This approach helps prevent erroneous operation
of communications devices, with the aim of satisfying the 300-ns minimum data-hold time requirement of the SMBus
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26. I2C Bus Interface (IIC)
S124 User’s Manual
specification. The output delay function is enabled by setting the SDDL[2:0] bits in the ICMR2 register to any value
other than 000b, and disabled by setting the same bits to 000b.
While the SDA output delay function is enabled, the DLCS bit in the ICMR2 register selects the clock source for
counting by the SDA output delay counter either as the internal base clock (IIC) for the IIC module or as the internal
base clock divided by two (IIC/2). The counter counts the number of cycles set in the SDDL[2:0] bits in the ICMR2
register. After delay cycles count is complete, the IIC module places the required output (start, restart, or stop condition,
data, or an ACK or NACK signal) on the SDA line.
Analog noise filter delay time + PCLKB sampling error (1 PCLKB (max))
Digital noise filter delay time (NFE, NF[1:0] settings = 0.5 PCLKB (min), 1 IIC to 4 IIC (max))
Transmit mode
SDA output delay time (DLCS, SDDL[2:0] settings = 0 (min) to 14 IIC (max))
S
SDA output release timing
8
9
SCLn
b0
b7 to b1
ACK/NACK
SDAn
SDA output delay
Receive mode
SDA output release timing
1 to 7
8
9
P
SCLn
b7 to b1
b0
ACK/NACK
SDAn
SDA output delay
Master mode
ICBRH
ST
ICBRL
ICBRH
1
ICBRL
ICBRL
2 to 8
9
ICBRH
RS
ICBRH
ICBRL
1 to 9
ICBRL
SP
SCLn
b7
b6 to b0
ACK/NACK
SDAn
*1
*1
*1
BBSY
ST
SDA output delay
Figure 26.22
26.6
Note 1. The output delay function is set by the DLCS and SDDL[2:0] bits when a start (ST),
restart (RS), or stop (SP) condition is issued.
SDA output delay function
Digital Noise Filter Circuits
The states of the SCLn and SDAn pins are conveyed to the internal circuitry through analog noise-filter and digital noisefilter circuits. Figure 26.23 is a block diagram of the digital noise-filter circuit.
The on-chip digital noise-filter circuit of the IIC consists of four flip-flop circuit stages connected in series and a matchdetection circuit.
The number of effective stages in the digital noise filter is selected in the NF[1:0] bits in the ICMR3 register. The
selected number of effective stages determines the noise-filtering capability as a period from 1 to 4 IIC cycles.
The input signal to the SCLn pin (or SDAn pin) is sampled on falling edges of the IIC signal. When the input signal
level matches the output level of the number of effective flip-flop circuit stages as selected in the NF[1:0] bits in the
ICMR3 register, the signal level is conveyed to the subsequent stage. If the signal levels do not match, the previous value
is saved.
If the ratio between the frequency of the internal operating clock (PCLKB) and the transfer rate is small, such as data
transfer at 400 kbps with PCLKB at 4 MHz, the characteristics of the digital noise filter might lead to the elimination of
valid signals as noise. In such cases, it is possible to disable the digital noise-filter circuit, by setting the ICFER.NFE bit
to 0, and use only the analog noise-filter circuit.
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26. I2C Bus Interface (IIC)
S124 User’s Manual
Mismatch
Match
D
Q
CLK
Comparator
PCLKB
Four-stage digital noise filter
D
Q
D
CLK
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
IIC
NF[1:0]
NFE
NFE:
Digital noise filter circuit enable bit
NF[1:0]: Noise filter stage select bits
Figure 26.23
26.7
Digital noise-filter circuit block diagram
Address Match Detection
The IIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7-bit
or 10-bit slave addresses.
26.7.1
Slave-Address Match Detection
The IIC can set three unique slave addresses and has a slave address detection function for each unique slave address.
When the SARyE bit (y = 0 to 2) in the ICSER register is set to 1, the slave addresses set in the SARUy and SARLy
registers (y = 0 to 2) can be detected.
When the IIC detects a match of a set slave address, the associated AASy flag (y = 0 to 2) in the ICSR1 register is set to
1 on the rising edge of the ninth SCL clock cycle, and the RDRF flag or TDRE flag in the ICSR2 register is set to 1 by
the subsequent R/W# bit. This causes a receive data full interrupt (IICn_RXI) or transmit data empty interrupt
(IICn_TXI) to be generated. The AASy flag identifies the slave address for which the match was detected.
Figure 26.24 to Figure 26.26 show the AASy flag set timing in three cases.
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26. I2C Bus Interface (IIC)
S124 User’s Manual
[7-bit address format: slave reception]
S
1
2
3
4
5
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
7-bit slave address
SDAn
BBSY
Data (DATA 1)
Data (DATA 2)
ACK
Address match
AASy
Receive data (7-bit address)
TRS
Receive data (DATA 1)
TDRE
RDRF
Read ICDRR
(Dummy read [7-bit address])
Read ICDRR
(DATA 1)
[7-bit address format: slave transmission]
S
1
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
7-bit slave address
SDAn
BBSY
Data (DATA 1)
Data (DATA 2)
ACK
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(DATA 1)
Figure 26.24
Write data to ICDRT
(DATA 2)
Write data to ICDRT
(DATA 3)
AASy flag set timing with 7-bit address format
[10-bit address format: slave reception]
S
1
2
3
4
5
1
1
1
1
0
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Upper 2 bits
10-bit slave address (lower 8 bits)
Data
ACK
BBSY
Address match
AASy
Receive data (lower addresses)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [lower addresses])
[10-bit address format: slave transmission]
S
1
2
3
4
5
1
1
1
1
0
6
7
8
9
1 to 8
9
Sr
1
2
3
4
5
1
1
1
1
0
6
7
8
9
R
ACK
SCLn
SDAn
BBSY
Upper 2 bits
W
ACK Lower 8 bits ACK
R
Upper 2 bits
Address match
AASy
Receive data (lower addresses)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [lower addresses])
Figure 26.25
AASy flag set timing with 10-bit address format
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26. I2C Bus Interface (IIC)
S124 User’s Manual
[When SAR0L = 7-bit address, SAR1L = 7-bit address, and SAR2 = 10-bit address (1)]
S
1
2
3
4
5
6
7
8
9
R/W# ACK
7-bit slave address (SAR0L)
1 to 8
9
DATA
ACK
Sr
1
2
3
4
5
6
7
8
9
R/W# ACK
7-bit slave address (SAR1L)
BBSY
Address mismatch
AAS0
Address match
Address match
AAS1
AAS2
[When SAR0L = 7-bit address, SAR1L = 7-bit address, and SAR2 = 10-bit address (2)]
S
1
2
3
4
5
6
7
8
9
R/W# ACK
7-bit slave address (SAR1L)
1 to 8
9
DATA
ACK
Sr
1
2
3
4
5
1
1
1
1
0
6
7
Upper 2 bits
8
9
W
ACK
BBSY
AAS0
AAS1
Address match
Address mismatch
AAS2
[When SAR0L = 7-bit address, SAR1L = 7-bit address, and SAR2 = 10-bit address (3)]
S
1
2
3
4
5
1
1
1
1
0
6
7
Upper 2 bits
8
W
9
1 to 8
9
Sr
ACK Lower 8 bits ACK
1
2
3
4
5
6
7
7-bit slave address (SAR0L)
8
9
R/W# ACK
BBSY
Address match
AAS0
AAS1
AAS2
Figure 26.26
26.7.2
Address match
Address mismatch
AASy flag set and clear timing with 7-bit and 10-bit address formats mixed
Detection of General Call Address
The IIC provides detection of the general call address (0000 000b + 0 [W]). This is enabled by setting the GCAE bit in
the ICSER register to 1.
If the address received after a start or restart condition is issued is 0000 000b + 1[R] (start byte), the IIC recognizes this
as the address of a slave device with an all-zero address, but not as the general call address.
When the IIC detects the general call address, both the GCA flag in the ICSR1 register and the RDRF flag in the ICSR2
register are set to 1 on the rising edge of the ninth cycle of the SCL clock. This leads to the generation of a receive data
full interrupt (IICn_RXI). The value of the GCA flag can be checked to confirm that the general call address was
transmitted.
Operation after detection of the general call address is the same as normal slave receive operation.
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26. I2C Bus Interface (IIC)
S124 User’s Manual
[General call address reception]
S
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Data (DATA 1)
Data (DATA 2)
ACK
BBSY
AAS0
AAS1
Receive data (7-bit address)
Receive data (DATA 1)
AAS2
GCA
General call address match (0000 000b + W)
RDRF
Read ICDRR
(Dummy read [7-bit address])
Figure 26.27
26.7.3
Read ICDRR
(DATA 1)
Timing of GCA flag setting during reception of general call address
Device-ID Address Detection
The IIC module provides detection of device-ID address in compliance with the I2C bus specification (Rev. 03). When
the IIC receives 1111 100b as the first byte after a start or restart condition was issued with the DIDE bit in the ICSER
register set to 1, it recognizes the address as a device ID, sets the DID flag in the ICSR1 register to 1 on the rising edge of
the eighth SCL clock cycle when the subsequent R/W# bit is 0, then compares the second and subsequent bytes with its
own slave address. If the address matches the value in the slave address register, the IIC sets the associated AASy flag (y
= 0 to 2) in the ICSR1 register to 1.
After that, when the first byte received after issuance of a start or restart condition matches the device ID address (1111
100b) again and the subsequent R/W# bit is 1, the IIC does not compare the second and subsequent bytes and sets the
ICSR2.TDRE flag to 1.
In the device-ID address detection function, the IIC sets the DID flag to 0 if a match with the IIC slave address is not
obtained or a match with the device ID address is not obtained after a match with the IIC slave address and the detection
of a restart condition. If the first byte after detection of a start or restart condition matches the device ID address (1111
100b) and the R/W# bit is 0, the IIC sets the DID flag to 1 and compares the second and subsequent bytes with the slave
address of the IIC. If the R/W# bit is 1, the DID flag holds the previous value and the IIC does not compare the second
and subsequent bytes. Therefore, the reception of a device ID address can be checked by reading the DID flag after
confirming that TDRE = 1.
Additionally, prepare the device ID fields (3 bytes: 12 bits indicating the manufacturer + 9 bits identifying the part + 3
bits indicating the revision) that must be sent to the host after reception of a continuous device ID field as normal
transmit data. For details of the information that must be included in device ID fields, contact NXP Semiconductors.
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26. I2C Bus Interface (IIC)
S124 User’s Manual
[Device-ID reception]
S
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
W
ACK
1
to
8
Address
9
Sr
ACK
BBSY
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
R
ACK
Slave address match
AASy
Device-ID match (1111 100b + R)
Device-ID match (1111 100b + W)
DID
Receive data (7-bit address/lower 10 bits)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [7-bit address/lower 10 bits])
[When address received after a restart condition is detected does not match the device-ID ]
S
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
W
ACK
1
to
8
Address
9
Sr
1
2
4
Slave address match
Receive data (7-bit address/lower 10 bits)
6
7
8
9
R/W# ACK
Slave address mismatch
AASy
Device-ID mismatch
Device-ID match (1111 100b + W)
DID
5
7-bit slave address (other station)
ACK
BBSY
3
RDRF
Read ICDRR
(Dummy read [7-bit address/lower 10 bits])
[When address before the device-ID + R does not match the slave address]
S
1
2
3
4
5
6
7
8
1
1
1
1
1
0
0
R
9
1
to
8
9
Sr
NACK
NACK
Comparing the second and the following
bytes is stopped.
1
2
3
4
5
6
7
8
9
1
1
1
1
1
0
0
R
NACK
BBSY
AASy
DID
Device-ID match (1111 100b + R)
Device-ID match (1111 100b + R)
Previous value is retained.
TDRE
RDRF
Figure 26.28
26.7.4
AASy/DID flag set and clear timing during reception of device ID
Host Address Detection
The IIC provides host address detection when operating in SMBus mode. When the HOAE bit in the ICSER register is
set to 1 and the SMBS bit in the ICMR3 register is 1, the IIC can detect the host address (0001 000b) in slave receive
mode (ICCR2.MST and ICCR2.TRS bits = 00b).
When the IIC detects the host address, the HOA flag in the ICSR1 register is set to 1 on the rising edge of the ninth SCL
clock cycle. At the same time, the RDRF flag in the ICSR2 register is set to 1 if the R/W# bit is 0. This causes a receive
data full interrupt (IICn_RXI) to be generated. The HOA flag indicates that the host address was detected.
If the bit following the host address (0001 000b) is a read bit (R/W# bit = 1), the IIC can also detect the host address.
After the host address is detected, the IIC operates in the same manner as in normal slave operation.
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26. I2C Bus Interface (IIC)
S124 User’s Manual
[Host address reception]
S
1
2
3
4
5
6
7
8
9
0
0
0
1
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
Data (DATA 1)
Data (DATA 2)
ACK
SDAn
BBSY
AAS0
Receive data (7-bit address)
AAS1
Receive data (DATA 1)
AAS2
HOA
Host address match (0001 000b)
RDRF
Read ICDRR
(Dummy read [7-bit address])
Figure 26.29
26.8
Read ICDRR
(DATA 1)
HOA flag set timing during reception of host address
Wakeup Function
The IIC provides a wakeup function that causes the MCU to transition from Software Standby mode to normal operation.
The wakeup function enables the reception of data when the system clock is stopped, and it generates a wakeup interrupt
signal on the match of the slave address of the received data. This interrupt signal triggers the return to normal operation.
The wakeup function has four operation modes:
Normal wakeup mode 1
Normal wakeup mode 2
Command recovery mode
EEP response mode.
Table 26.9 describes the behavior in these modes.
Table 26.9
Wakeup operation modes
Operation mode
ACK response timing
ACK response before wakeup
SCL state during wakeup
Normal wakeup mode 1
Before wakeup
ACK
Fixed low
Normal wakeup mode 2
After wakeup
Before wakeup: no response
After wakeup: ACK response
Fixed low
Command recovery mode
Before wakeup
ACK
Open
EEP response mode
Before wakeup
NACK
Open
Precautions on the use of the wakeup function
Disable the wakeup function (WUE = 0) after a wakeup interrupt triggers the transition from Software Standby
mode to normal operation
Do not change the content of the IIC registers while WUF is 0, even if the wakeup interrupt recovers the system
clock. Specify the register settings after confirming that WUF is 1.
Set ICWUR.WUE and ICWUR.WUIE to 1 and ICCR2.MST and ICCR2.TRS to 0 (slave reception mode) before
entering Software Standby mode
Do not invoke Software Standby mode while BBSY = 1
The wakeup function supports the 7-bit slave address of slave address registers SARL0, SARL1, SARL2, the
general call address, and the host address. 10-bit slave addresses are not supported.
When the wakeup function is enabled, disable the interrupts selectable in the ICIER register bits TIE, TEIE, RIE,
NAKIE, SPIE, STIE, ALIE, and TMOIE
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S124 User’s Manual
When the wakeup function is enabled, do not use the timeout function
If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for example
IRQn, the WUF flag is not set to 1.
26.8.1
Normal Wakeup Mode 1
This section describes the behavior, the timing, and a use case of normal wakeup mode 1.
1. A wakeup interrupt triggered by the match of the slave address initiates the transition to normal operation as
follows:
Before wakeup:
ACK is sent in response to the data received with its own slave address of the IIC.
During wakeup:
After wakeup:
ACK response is made on the ninth clock cycle of SCL, and SCL is held low afterwards.*1
Normal operation continues.
If the slave address does not match, the SCL line is not held low after the fall of the ninth clock cycle of SCL, and
the slave operation continues. Figure 26.32 provides detailed timing. For a use case, see Figure 26.30.
Note 1. Between the ninth clock cycle and first clock cycle during wakeup, WAIT = 1 does not work.
2. If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for example
IRQn, the WUF flag is not set to 1. Follow the processing shown in Figure 26.31.
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S124 User’s Manual
IIC normal operation
No
BBSY = 0
*1
[1] Wait until I2C bus is free and stay in standby state.
Yes
No
MST = 0 & TRS = 0
(slave receive)
Yes
IICRST = 0 (& ICE = 1)
[2] Negate internal reset (if asserted).
WUACK setting, WUIE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt.
WUE = 1
[4] Enable wakeup function.
*2
WUSEN = 0
[5] Set WUSEN to 0.
No
WUASYF = 1
*2
Yes
ICIER = 00h
[6] Disable all interrupt requests except WUI.
WFI instruction
[7] Stop PCLKB to IIC. IIC continues to receive.
Wakeup interrupt
No
WUF = 1
WUSEN = 1
*2
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match).
[9] Wait for WUF = 1.
[10] Set WUSEN to 1.
No
WUSYF = 1
*2
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling.
WUF = 0
WUF = 0
No
Yes
WUIE = 0
[12] Disable wakeup interrupt.
WUE = 0
[13] Disable wakeup function.
TRS = 1
No
Slave receive processing
Yes
Slave transmit processing
Note 1.
Note 2.
Do not issue start condition between BBSY = 0 and executing WFI instruction.
This step can be skipped.
Figure 26.30
Note:
Example operation of normal wakeup mode 1 when wakeup is triggered by a wakeup interrupt on
match of the slave address
See Precautions on the use of the wakeup function.
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S124 User’s Manual
WUE = 1
*1
WUSEN = 0
[1] Start PCLKB to IIC due to other return factor (IRQ).
WUASYF = 1
No
[2] Set WUSEN to 1.
*1
Yes
[3] Disable wakeup interrupts.
ICIER = 00h
[4] Disable wakeup function.
WFI instruction
*2
[5] Reset IIC (ICE = 0 & IICRST = 1).
Start system clock due to
other return factor (IRQ)
[1]
Yes
WUSEN = 0
*1
No
Continue
slave mode?
Yes
No
WUSEN = 1
WUSYF = 1
*1
[2]
Wakeup interrupt
WUSEN = 1
No
No
WUSYF = 1
*1
Yes
Yes
WUIE = 0
[3]
WUIE = 0
WUE = 0
[4]
WUE = 0
ICE = 0 & IICRST = 1
[5]
ICE = IICRST = 1, initialize
[6]
ICE = 1 & IICRST = 0
[7]
From here, the sequence is the same
as step [9] onward, as in Figure 26.30
for normal wakeup mode 1, and
Figure 26.33 for normal wakeup
mode 2.
[6] Reset IIC (internal reset: ICE = 1 & IICRST = 1).
Initial settings.
[7] Negate internal reset.
IIC normal operation
Note 1.
Note 2.
Figure 26.31
Note:
This step can be skipped.
Before this step, the flow is the same as Figure 26.30.
Example operation of normal wakeup modes 1 and 2 when wakeup by an interrupt other than IIC
wakeup interrupt, for example, IRQn
For details of the IIC initial settings, see section 26.3.2, Initial Settings.
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26. I2C Bus Interface (IIC)
S124 User’s Manual
[Normal Wakeup Mode 1]
As with the normal operation, ACK response on match with own slave address, and SCL held low until the return.
Before wake-up: own slave ACK response. During wake-up: SCL held low on 9th SCL. After wake-up: continue normal operation.
Active
Software Standby Active
(during wakeup)
Software Standby (before wakeu)p
Active (after wakeup)
Continue to receive after returning (WAIT = 0)
WFI command
ST
1
SCL
WUACK = 0 (ACK Return)
2
3
4
5
6
7
SLAVE ADDRESS
SDA
8
W
ICDRR read
9
Low hold period
1
2
3
4
5
ACK
6
7
8
ICDRR read
SP
WUF 0 clear
(0 write after 1 read)
9
DATA
ACK
WUF
AAS0
RDRF
TRS
Continue to transmit after returning (WAIT = 0)
WUF 0 clear
ICDRT write
WUACK = 0 (ACK Return)
SCL
1
2
SDA
3
4
5
6
SLAVE ADDRESS
7
8
9
Low hold period
1
2
ICDRT write
3
R ACK
4
5
DATA
6
7
8
9
1
SP
2
ACK
3
4
5
DATA
6
7
8
9
NACK
WUF
AAS0
TDRE
TRS
Asynchronous synchronous switching period
Figure 26.32
26.8.2
Timing of normal wakeup mode 1
Normal Wakeup Mode 2
This section describes the behavior, the timing, and a use case of normal wakeup mode 2.
1. A wakeup interrupt triggered by the match of the slave address initiates the transition to normal operation as
follows:
Before wakeup:
During wakeup:
After wakeup:
No response to the data received with its own slave address of the IIC until the end of the eighth
SCL cycle.
SCL line held low during the eighth and ninth clock cycles.
ACK returns on the ninth clock cycle of SCL, and normal operation continues.
If the slave address does not match, the SCL line is not held low after the fall of the eighth SCL clock cycle, and the
slave operation continues. Figure 26.34 provides detailed timing. For a use case, see Figure 26.33.
2. If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for example
IRQn, the WUF flag is not set to 1. Follow the processing shown in Figure 26.31.
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S124 User’s Manual
IIC normal operation
No
BBSY = 0
*1
[1] Wait until I2C bus is free and stay in standby state
Yes
No
MST = 0 & TRS = 0
(slave receive)
Yes
IICRST = 0 (& ICE = 1)
[2] Negate internal reset (if asserted)
WUACK setting, WUIE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt
WUE = 1
[4] Enable wakeup function
*2
WUSEN = 0
[5] Set WUSEN to 0
No
WUASYF = 1
*2
Yes
ICIER = 00h
[6] Disable all interrupt requests except WUI
WFI instruction
[7] Stop PCLKB to IIC. IIC continues to receive
Wakeup interrupt
No
WUF = 1
WUSEN = 1
*2
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match)
[9] Wait for WUF = 1
[10] Set WUSEN to 1
No
WUSYF = 1
*2
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling
WUF = 0
WUF = 0
No
Yes
WUIE = 0
[12] Disable wakeup interrupt
WUE = 0
[13] Disable wakeup function
TRS = 1
No
Slave receive processing
Yes
Slave transmit processing
Note 1.
Note 2.
Do not issue start condition between BBSY = 0 and executing WFI instruction.
This step can be skipped.
Figure 26.33
Note:
Example operation of normal wakeup mode 2 when wakeup is triggered by a wakeup interrupt on
match of the slave address
See Precautions on the use of the wakeup function.
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26. I2C Bus Interface (IIC)
S124 User’s Manual
[Normal Wakeup Mode 2]
SCL held low until wakeup on own slave match. ACK response after wake-up.
Before wake-up: own slave – Response. During wake-up: SCL held low between 8th and 9th SCL. After wake-up: normal operation continues after own slave ACK response.
Active
Software Standby Active
(during wakeup)
Software Standby (before wakeup)
Active (after wakeup)
Continue to receive after returning (WAIT = 0)
WFI command
ST
1
SCL
ICDRR read
WUF = 0 clear
2
3
4
5
6
7
SLAVE ADDRESS
SDA
8
W
Low hold period
NACK
9
1
2
3
4
5
ACK
6
7
8
ICDRR read
SP
9
DATA
ACK
WUF
AAS0
RDRF
TRS
WUF = 0 clear
Continue to transmit after returning (WAIT = 0)
1
SCL
2
SDA
3
4
5
6
SLAVE ADDRESS
ICDRT write
7
8
R
Low hold period
NACK
9
1
2
ICDRT write
3
ACK
4
5
DATA
6
7
8
9
ACK
1
SP
2
3
4
5
DATA
6
7
8
9
N ACK
WUF
AAS0
TDRE
TRS
Asynchronous synchronous switching period
Figure 26.34
26.8.3
Timing of normal wakeup mode 2
Command Recovery Mode and EEP Response Mode (Special Wakeup Modes)
In the command recovery and EEP response modes, the SCL line is not held low during the wakeup period (after the rise
of the ninth clock cycle of SCL), so other IIC devices can use the I2C bus during this period.
This section describes the behavior, the timing, and use cases of the command recovery and EEP response modes.
1. A wakeup interrupt triggered by the match of the slave address initiates the transition to normal operation as
follows:
Before wakeup:
During wakeup:
After wakeup:
In response to the data received with its own slave address of the IIC, ACK (command recovery
mode) or NACK (EEP response mode) is returned.
The SCL line is not held low.
Normal operation continues after the IIC initial settings.
If the slave address does not match, the slave operation continues. Figure 26.37 provides detailed timing. For a use
case, see Figure 26.35.
Note 1. Because the SCL line is not held low during wakeup, transmission or reception of the data that follows the slave
address is not possible.
Note 2. The command recovery and EEP response modes are internal reset states (ICE = IICRST = 1). Therefore, the
match of the slave address does not set the ICSR1 register flags HOA, GCA, AAS0, AAS1, and AAS2.
2. If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for example
IRQn, the WUF flag is not set to 1. Follow the processing shown in Figure 26.36.
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S124 User’s Manual
IIC normal operation
No
BBSY = 0
*1
[1] Wait until I2C bus is free and stay in standby state
Yes
No
MST = 0 & TRS = 0
(slave receive)
Yes
IICRST = 1 & ICE = 1
[2] Internal reset is asserted
WUACK setting, WUIE = 1
[3] Set up WUACK for desired wakeup mode. Enable wakeup interrupt.
WUE = 1
[4] Enable wakeup function
*2
WUSEN = 0
[5] Set WUSEN to 0
No
WUASYF = 1
*2
Yes
[6] Disable all interrupt requests except WUI
ICIER = 00h
[7] Stop PCLKB to IIC. IIC continues to receive
WFI instruction
Wakeup interrupt
No
WUF = 1
WUSEN = 1
*2
[8] Start system clock and PCLKB to IIC on wakeup interrupt
(address match)
[9] Wait for WUF = 1
[10] Set WUSEN = 1
No
WUSYF = 1
*2
Yes
[11] Write 0 to WUF. Read and check that WUF = 0 before
returning from interrupt handling.
WUF = 0
WUF = 0
No
Yes
WUIE = 0
[12] Disable wakeup interrupt
WUE = 0
[13] Disable wakeup function
ICE = 0 & IICRST = 1
ICE = IICRST = 1, initialize
ICE = 1 & IICRST = 0
[14] Reset IIC (ICE = 0 & IICRST = 1)
[15] Reset IIC (internal reset: ICE = 1 & IICRST = 1). Initial settings.
[16] Negate internal reset
IIC normal operation
Note 1.
Note 2.
Figure 26.35
Note:
Do not issue start condition between BBSY = 0 and executing WFI instruction.
This step can be skipped.
Example operation of command recovery and EEP response modes when wakeup is triggered by
a wakeup interrupt on match of the slave address
See Precautions on the use of the wakeup function.
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S124 User’s Manual
WUE = 1
[1] Start PCLKB to IIC due to other return factor (IRQ).
*1
WUSEN = 0
[2] Set WUSEN to 1.
[3] Disable wakeup interrupts.
No
WUASYF = 1
[4] Disable wakeup function.
*1
Yes
[5] Reset IIC (ICE = 0 & IICRST = 1).
ICIER = 00h
WFI instruction
Start system clock supply by
other return factor (IRQ)
[1]
Yes
WUSEN = 0
*1
No
No
WUSEN = 1
*1
Continue slave mode
in Command return mode/
EEP response mode?
[2]
Yes
WUSYF = 1
Wakeup interrupt
No
From here, the sequence is the same
as step [9] onward, as in Figure
26.35.
*1
Yes
WUIE = 0
[3]
WUE = 0
[4]
ICE = 0 & IICRST = 1
[5]
ICE = IICRST = 1, initialize
[6]
ICE = 1 & IICRST = 0
[7]
[6] Reset IIC (internal reset: ICE = 1 & IICRST = 1).
Initial settings.
[7] Negate internal reset.
IIC Normal Operation
Note 1.
Figure 26.36
Note:
This step can be skipped.
Example operation of command recovery and EEP response modes when wakeup is triggered by
an interrupt other than IIC wakeup interrupt, for example, IRQn
For details of the IIC initial settings, see section 26.3.2, Initial Settings.
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S124 User’s Manual
[Command return mode and EEP response mode]
Reply ACK / NACK in the period from wakeup start to wakeup processing.
Reply ACK if own slave is specified again after IICRST release after wakeup
Before wake-up: own slave ACK/NACK response. During wake-up: no SCL-low hold. After wake-up: continue normal operation.
Active
Software Standby active
(during wakeup)
Software Standby (before wakeup)
Active (after wake-up)
WFI command
SCL
1
2
SDA
3
4
5
6
7
SLAVE ADDRESS
8
R/W#
9
1
2
A/NA
3
5
6
DATA
0
BC
4
0
BBSY
START
WUF
AAS0
TDRE/
RDRF
Asynchronous synchronous switching period
Figure 26.37
26.8.4
Timing of command recovery and EEP response modes
Precautions for WFI Instruction Execution
In the use cases for the wakeup mode shown in Figure 26.30, Figure 26.33, and Figure 26.35, make sure that the start
condition is not issued during the period from the setting of BBSY = 0 to the execution of the WFI instruction. When a
start condition is issued during this period, NACK is returned after the reception the first byte of the first data block.
Detection of the start or restart condition then enables the wakeup function.
26.9
26.9.1
Automatic Low-Hold Function for SCL
Function to Prevent Wrong Transmission of Transmit Data
If the I2C Bus Shift Register (ICDRS) is empty when data has not been written to the I2C bus transmit data register
(ICDRT) with the IIC in transmission mode (TRS bit = 1 in ICCR2), the SCLn line is automatically held at the low level
over the subsequent intervals. This low-hold period is extended until the transmit data is written, which prevents the
unintended transmission of erroneous data.
Master transmit mode:
Low-level interval after a start or restart condition is issued
Low-level interval between the ninth clock cycle of one transfer and the first clock cycle of the next.
Slave transmit mode:
Low-level interval between the ninth clock cycle of one transfer and the first clock cycle of the next.
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Automatic low-hold
(to prevent wrong
transmission)
1
2
[Master transmit mode]
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
Automatic low-hold (to prevent wrong transmission)
8
9
W
ACK
1
2
3
4
5
6
7
8
9
SCLn
7-bit slave address
SDAn
Data (DATA 1)
ACK
BBSY
Transmit data (7-bit address + W)
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(7-bit address + W)
Write data to ICDRT
(DATA 1)
[Slave transmit mode]
S
1
Write data to ICDRT
(DATA 2)
Automatic low-hold (to prevent wrong transmission)
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
Automatic low-hold
(to prevent wrong
transmission)
1
2
3
SCLn
7-bit slave address
Data (DATA 1)
ACK
SDAn
BBSY
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
RDRF
Write data to ICDRT
(DATA 1)
Figure 26.38
26.9.2
Write data to ICDRT
(DATA 2)
Automatic low-hold operation in Transmit mode
NACK Reception Transfer Suspension Function
This function suspends transfer operation when NACK is received in transmit mode (TRS bit = 1 in ICCR2). This
function is enabled when the NACKE bit in ICFER is set to 1. If the next transmit data is already written (TDRE flag = 0
in ICSR2) when NACK is received, the next data transmission on the falling edge of the ninth SCL clock cycle is
automatically suspended. This prevents the SDAn line output level from being held low when the MSB of the next
transmit data is 0.
If the transfer operation is suspended by this function (NACKF flag = 1 in ICSR2), transmit and receive operations are
discontinued. To restore transmit and receive operation, you must set the NACKF flag to 0. In master transmit mode,
after issuing a restart or stop condition, set the NACKF flag to 0, then issue a start condition again.
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[Master transmit mode]
Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
Bus free time (ICBRL)
8
9
P
S
1
2
3
4
5
6
7
8
9
W
ACK
SCLn
W
7-bit slave address
SDAn
BBSY
Transmit data
(7-bit address + W)
AASy
NACK
Transfer suspended
7-bit slave address
Transmit data
(7-bit address + W)
Transmit data (DATA 1)
Transmit data (DATA 1)
TRS
TDRE
NACKF
Write data to ICDRT register Write data to ICDRT
(7-bit address + W)
register (DATA 1)
Write 1
to SP bit
[Slave transmit mode]
S
1
Clear
NACKF flag
Write data to ICDRT
register
(7-bit address + W)
Write data to ICDRT
register (DATA 1)
Automatic low-hold (to prevent wrong transmission)
2
3
4
5
6
7
8
9
W
ACK
1
2
3
4
5
6
7
8
9
P
Bus free time
(ICBRL)
SCLn
SDAn
7-bit slave address
Data (DATA 1)
Transfer suspended
BBSY
Address match
AASy
Transmit data (DATA 1)
Transmit data (DATA 2)
TRS
TDRE
NACKF
Write data to ICDRT
register (DATA 1)
Figure 26.39
26.9.3
Write data to ICDRT
register (DATA 2)
Write 1 to SP bit
Clear NACKF flag
Suspension of data transfer when NACK is received (NACKE = 1)
Function to Prevent Failure to Receive Data
If response processing when receive data (ICDRR) read is delayed for a period of one transfer frame or more with
receive data full (RDRF flag = 1 in ICSR2) in receive mode (TRS = 0 in ICCR2), the IIC holds the SCLn line low
automatically immediately before the next data is received to prevent failure to receive data.
This function is enabled even if the read processing of the final receive data is delayed and, in the meantime, the IIC
slave address is designated after a stop condition is issued. This function does not interfere with other communication
because the IIC does not hold the SCLn line low when a mismatch with its own slave address occurs after a stop
condition is issued.
Periods in which the SCLn line is held low can be selected with a combination of the WAIT and RDRFS bits in the
ICMR3 register.
(1)
1-byte receive operation and automatic low-hold function using the WAIT bit
When the WAIT bit in the ICMR3 register is set to 1, the IIC performs a 1-byte receive operation using the WAIT bit
function. Additionally, when the ICMR3.RDRFS bit is 0, the IIC automatically sends the ACKBT bit value in the
ICMR3 register for the acknowledge bit in the period from the falling edge of the eighth SCL clock cycle to the falling
edge of the ninth SCL clock cycle, and automatically holds the SCLn line low on the falling edge of the ninth SCL clock
cycle using the WAIT bit function. This low-hold is released by reading data from ICDRR, which enables byte-wise
receive operation.
The WAIT bit function is enabled for receive frames after a match with the IIC slave address, including the general call
address and host address, is obtained in master receive mode or slave receive mode.
(2)
1-byte receive operation (ACK/NACK transmission control) and automatic low-hold function
using the RDRFS bit
When the RDRFS bit in the ICMR3 register is set to 1, the IIC performs a 1-byte receive operation using the RDRFS bit
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S124 User’s Manual
function. When the RDRFS bit is set to 1, the RDRF flag in ICSR2 is set to 1 (receive data full) on the rising edge of the
eighth SCL clock cycle, and the SCLn line is automatically held low on the falling edge of the eighth SCL clock cycle.
This low-hold is released by writing a value to the ACKBT bit in ICMR3, but cannot be released by reading data from
ICDRR, which enables receive operation through the ACK or NACK transmission control based on the data received in
byte units.
The RDRFS bit function is enabled for receive frames after a match with the IIC slave address, including the general call
address and host address, is obtained in master receive mode or slave receive mode.
Automatic low-hold
(to prevent failure to receive data)
[RDRFS = 0, WAIT = 0]
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
SCLn
SDAn
ACK
ACK
Data
ACK
Data
Data
RDRF
Read ICDRR
Read ICDRR
[RDRFS = 0, WAIT = 1]
9
1
2
3
4
5
Read ICDRR
Automatic low-hold (WAIT)
Automatic low-hold (WAIT)
6
7
8
9
1
2
3
4
5
6
7
8
9
Automatic lowhold (WAIT)
1
SCLn
SDAn
ACK
ACK
Data
ACK
Data
RDRF
Read ICDRR
Read ICDRR
[RDRFS = 1, WAIT = 0]
2
3
Read ICDRR
Automatic low-hold
(to prevent failure to
receive data)
8
Automatic low-hold (RDRFS)
4
5
6
7
8
9
1
2
3
4
5
6
7
Automatic lowhold (RDRFS)
9
1
SCLn
Data
SDAn
ACK
Data
ACK
RDRF
ACKBT
Write 0 to ACKBT
[RDRFS = 1, WAIT = 1]
2
3
4
5
Automatic low-hold
(RDRFS)
6
7
8
Read ICDRR Read ICDRR
Automatic low-hold (WAIT)
9
1
2
3
4
5
6
7
Write 0 to ACKBT
Automatic low-hold
(RDRFS)
9
1
8
SCLn
SDAn
Data
ACK
Data
ACK
RDRF
ACKBT
Write 0 to ACKBT
Figure 26.40
Read ICDRR
Read ICDRR Write 0 to ACKBT
Automatic low-hold operation in receive mode using RDRFS and WAIT bits
26.10 Arbitration-Lost Detection Functions
In addition to the normal arbitration-lost detection function defined by the I2C bus standard, the IIC has functions to
prevent double-issue of a start condition, detect arbitration-lost during transmission of NACK, and detect arbitration-lost
in slave transmit mode.
26.10.1
Master Arbitration-Lost Detection (MALE Bit)
The IIC drives the SDAn line low to issue a start condition. However, if the SDAn line was already driven low by
another master device issuing a start condition, the IIC regards its own start condition as an error and considers this a loss
in arbitration. Priority is given to transfer by the other master device. Similarly, if a request to issue a start condition is
made by setting the ST bit in ICCR2 to 1 while the bus is busy (BBSY flag = 1 in ICCR2), the IIC regards this as a
double-issuing-of-start-condition error and considers itself to have lost the arbitration. This prevents a failure of transfer
resulting from a start condition being issued while transfer is in progress.
When a start condition is issued successfully, if the transmit data including the address bits (internal SDA output level)
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and the level on the SDAn line do not match (high output as the internal SDA output, meaning the SDAn pin is in the
high-impedance state) and a low level is detected on the SDAn line, the IIC loses in arbitration.
After a loss in arbitration of mastership, the IIC immediately enters slave receive mode. If a slave address, including the
general call address, matches its own address at this time, the IIC continues in slave operation.
A loss in arbitration of mastership is detected when the following conditions are met while the MALE bit in ICFER is 1
(master arbitration-lost detection enabled).
[Master arbitration-lost conditions]
Mismatching of the internal level for output on SDA and the level on the SDAn line after a start condition was
issued by setting the ICCR2.ST bit to 1 while the BBSY flag in ICCR2 was set to 0 (erroneous issuing of a start
condition)
Setting the ICCR2.ST bit to 1 (start condition double-issue error) while the BBSY flag is 1
When the transmit data excluding acknowledge (internal SDA output level) does not match the level on the SDAn
line in master transmit mode (MST and TRS bits = 11b in ICCR2).
[When slave addresses conflict]
S
1
2
3
4
5
6
Transmit data mismatch
(arbitration lost)
Release SCL/SDA
SCLn
1
SDAn
S
1
2
3
4
5
6
7
8
9
R
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
0
SDAn
ACK
Data
BBSY
Data
Address match
Address mismatch
MST
TRS
AL
AASy
TDRE
Clear AL to 0
[When data transmission conflicts after general call address is sent]
S
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
W
ACK
1
2
3
4
5
Transmit data mismatch
(arbitration lost)
Release SCL/SDA
SCLn
SDAn
S
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCLn
SDAn
ACK
0
Data
BBSY
MST
Receive data
TRS
AL
GCA
General call address match (0000 000b + W)
Clear AL to 0
RDRF
Read ICDRR
Figure 26.41
Examples of master arbitration-lost detection (MALE = 1)
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Bus free (BBSY = 0) start condition issuance (ST = 1) error
Bus busy (BBSY =1) start condition issuance (ST = 1) error
SDA mismatch
PCLKB
PCLKB
SCLn
PCLKB
SCLn
SCLn
SDAn
SCLn
SDAn
S
SDAn
1
S
SCLn
1
2
S
SCLn
SCLn
SDAn
ST = 1, BBSY = 1
SDAn
BBSY
BBSY
BBSY
MST
MST
MST
TRS
TRS
TRS
AASy
AASy
AASy
ST
ST
ST
AL
AL
AL
SDAn
ST = 1, BBSY = 1
Write 1 to ST
Figure 26.42
26.10.2
1
2
6
7
8
9
1
7-bit/10-bit slave address
R
ACK
ST = 1,
BBSY = 1
Write 1 to ST
Write 1 to ST
Arbitration-lost when start condition is issued (MALE = 1)
Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit)
This function causes arbitration to be lost if the internal SDA output level does not match the level on the SDAn line
(high output as the internal SDA output, meaning the SDAn pin is in the high-impedance state and a low level is detected
on the SDAn line) during transmission of NACK in receive mode. Arbitration is lost because of a conflict of NACK
transmission and ACK transmission when two or more master devices receive data from the same slave device
simultaneously in a multi-master system. Such conflict occurs when multiple master devices send or receive the same
information through a single slave device. Figure 26.43 shows an example of arbitration-lost detection during
transmission of NACK.
NACK transmission mismatch
(arbitration lost)
[Conflict during transmission of NACK (ACK received)]
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
Release SCL/SDA
8
9
SCLn
SDAn
ACK
Data
2
3
4
5
6
7
8
9
Data
1
2
3
4
5
NACK
6
7
8
9
1
2
3
4
5
SCLn
SDAn
Data
ACK
ACK
Data
Data
BBSY
MST
Receive data
TRS
Receive data
AL
RDRFS
RDRF
ACKBT
Write 1 to RDRFS
Figure 26.43
Read ICDRR
Read ICDRR
Write 1 to ACKBT
Clear AL to 0
Example of arbitration-lost detection during transmission of NACK (NALE = 1)
The following example explains arbitration-lost detection where two master devices (masters A and B) and a single slave
device are connected through the bus. In this example, master A receives 2 bytes of data from the slave device, and
master B receives 4 bytes of data from the slave device.
If masters A and B access the slave device simultaneously, because the slave address is identical, arbitration is not lost in
either master A or B during access to the slave device. Both masters A and B recognize that they obtained the bus
mastership and operate as such. Master A sends NACK when it has received 2 final bytes of data from the slave device.
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Meanwhile, master B sends ACK because it has not received the necessary 4 bytes of data. The NACK transmission
from master A and the ACK transmission from master B conflict. In general, if a conflict like this occurs, master A
cannot detect the ACK transmitted by master B and issues a stop condition. The issuance of the stop condition conflicts
with the SCL clock output of master B, which disrupts communication.
When the IIC receives ACK during transmission of NACK, it detects a defeat in conflict with other master devices and
causes arbitration to be lost. If arbitration is lost during transmission of NACK, the IIC immediately cancels the slave
match condition and enters slave receive mode. This prevents a stop condition from being issued, preventing a
communication failure on the bus.
Similarly, in the ARP command processing of SMBus, the function to detect loss of arbitration during transmission of
NACK is also available to eliminate the extra clock cycle processing, such as FFh transmission processing, necessary if
the UDID (Unique Device Identifier) of the assigned address does not match in the Get UDID general processing after
the Assign Address command.
The IIC detects arbitration-lost during transmission of NACK when the following condition is met with the NALE bit in
ICFER set to 1 (arbitration-lost detection during NACK transmission enabled).
[Condition for arbitration-lost during NACK transmission]
When the internal SDA output level does not match the SDAn line (ACK is received) during transmission of NACK
(ICMR3.ACKBT = 1).
26.10.3
Slave Arbitration-Lost Detection (SALE Bit)
This function causes arbitration to be lost if the transmit data (internal SDA output level) and the level on the SDAn line
do not match (high output as the internal SDA output, meaning the SDAn pin is in the high-impedance state, and a low
level is detected on the SDAn line) in slave transmit mode. This arbitration-lost detection function is mainly used when
transmitting a UDID (Unique Device Identifier) over an SMBus.
When the IIC loses slave arbitration, the IIC is immediately released from the slave-matched state and enters slave
receive mode. This function can detect conflicts of data during transmission of UDIDs over an SMBus and eliminates
subsequent redundant processing for the transmission of FFh.
The IIC detects slave arbitration-lost when the following condition is met with the SALE bit in ICFER set to 1 (slave
arbitration-lost detection enabled).
[Condition for slave arbitration-lost]
When transmit data excluding acknowledge (internal SDA output level) does not match the SDAn line in slave
transmit mode (MST and TRS bits = 01b in ICCR2).
Transmit data mismatch
(arbitration lost)
[Conflict during data transmission]
2
3
4
5
6
7
8
9
1
2
3
4
Release SCL/SDA
5
SCLn
ACK
Data
SDAn
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
SCLn
SDAn
Data
ACK
0
ACK
Data
BBSY
MST
TRS
AL
TDRE
Write data to ICDRT
Figure 26.44
Clear AL to 0
Example of slave arbitration-lost detection (SALE = 1)
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26. I2C Bus Interface (IIC)
26.11 Start, Restart, and Stop Condition Issuing Function
26.11.1
Issuing a Start Condition
The IIC issues a start condition when the ST bit in the ICCR2 register is set to 1.
When the ST bit is set to 1, a start condition request is made, and the IIC issues a start condition when the BBSY flag in
the ICCR2 register is 0 (bus free state). When a start condition is issued normally, the IIC automatically shifts to the
master transmit mode.
To issue a start condition:
1. Drive the SDAn line low (high level to low level).
2. Ensure that the time set in the ICBRH register and the start condition hold time elapse.
3. Drive the SCLn line low (high level to low level).
4. Detect low level of the SCLn line and ensure the low-level period of the SCLn line set in the ICBRL register
elapses.
26.11.2
Issuing a Restart Condition
The IIC issues a restart condition when the RS bit in the ICCR2 register is set to 1. When the RS bit is set to 1, a restart
condition request is made, and the IIC issues a restart condition when the ICCR2.BBSY flag is 1 (bus busy state) and the
ICCR2.MST bit is 1 (master mode).
To issue restart condition:
1. Release the SDAn line.
2. Ensure the low-level period of SCLn line set in the ICBRL register elapses.
3. Release the SCLn line (low level to high level).
4. Detect a high level on the SCLn line and ensure the time set in the ICBRL register and the restart condition setup
time elapse.
5. Drive the SDAn line low (high level to low level).
6. Ensure the time set in the ICBRH register and the restart condition hold time elapse.
7. Drive the SCLn line low (high level to low level).
8. Detect a low level on the SCLn line and ensure the low-level period of SCLn line set in the ICBRL register elapses.
Note:
When issuing restart condition requests, write the slave address to the ICDRT register after confirming that
ICCR2.RS = 0. Data written while ICCR2.RS = 1 is not forwarded because of the retransmission condition before
the occurrence.
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[Restart condition issuing operation]
[Start condition issuing operation]
ICBRH
SCLn
SDAn
Hold time
ICBRL
ICBRH
SCLn
S Issue start
condition
SDAn
IIC
IIC
BBSY
BBSY
MST
MST
TRS
TRS
TDRE
TDRE
7 bits address +R/W#
ICDRT
9
ACK/NACK
ICBRL
Setup time
ICBRL
ICBRH
Hold time
ICBRL
Sr
Issue restart
condition
7 bits address +R/W#
ICDRT
START
START
RS
ST
Write 1 to ST bit
Write to ICDRT (7 bits address +R/W#)
Write 1 to RS bit
Accept start condition issuance
Figure 26.45
Write to ICDRT (7 bits address +R/W#)
Accept restart condition issuance
Start condition and restart condition issue timing using the ST and RS bits
Figure 26.46 shows the operation timing when a restart condition is issued after the master transmission.
[Restart condition issuance after the master transmission]
1. Initial setting. For details, see section 26.3.2, Initial Settings.
2. Read the IICR2.BBSY flag to check that the bus is free, then set the ICCR2.ST bit to 1 (start condition issuance
request). On receiving the request, the IIC issues a start condition. At the same time, the ICSR2.BBSY flag and
ICSR2.START flag are automatically set to 1 and the ST bit is automatically set to 0. If the start condition is
detected and the internal levels for the SDA output state and the levels on the SDAn line have matched while the ST
bit is 1, the IIC recognizes that issuing of the start condition as requested by the ST bit has successfully completed.
The MST and TRS bits in ICCR2 are automatically set to 1, placing the IIC in master transmit mode. The TDRE
flag in ICSR2 is also automatically set to 1 in response to setting of the ICCR2.TRS bit to 1.
3. Check that the ICSR2.TDRE flag is 1, then write the value for transmission (the slave address and the R/W# bit) to
the ICDRT register. After the transmit data are written to the ICDRT register, the TDRE flag is automatically set to
0, the data is transferred from the ICDRT register to the ICDRS register, and the TDRE flag is again set to 1. After
the byte containing the slave address and R/W# bit has been transmitted, the value of the TRS bit is automatically
updated to select master transmit or master receive mode according to the value of the transmitted R/W# bit. If the
value of the R/W# bit was 0, the IIC continues in master transmit mode. If the NACKF.ICSR2 flag is 1 at this time,
indicating that no slave device recognized the address or there was an error in communications, write 1 to
ICCR2.SP bit to issue a stop condition.
To transmit data with an address in the 10-bit format, start by writing 1111 0b, the 2 upper-order bits of the slave
address, and W to the ICDRT register as the first address transmission. Then, as the second address transmission,
write the 8 lower-order bits of the slave address to the ICDRT register.
4. After confirming that the ICSR2.TDRE flag is 1, write the data for transmission to the ICDRT register. The IIC
automatically holds the SCLn line low until the transmit data is ready, a restart condition or a stop condition is
issued.
5. After all bytes of data for transmission are written to the ICDRT register, wait until the value of the ICSR2.TEND
flag returns to 1. Then, after checking that the ICSR2.START flag is 1, set the ICSR2.START flag to 0.
6. Set the ICCR2.RS bit to 1 (restart condition issuance request). On receiving the request, the IIC issues a restart
condition.
7. After checking that the ICSR2.START flag is 1, write the value for transmission (the slave address and the R/W#
bit) to the ICDRT register.
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Automatic low-hold (to prevent wrong transmission)
S
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
8
9
1
2
3
b0
ACK
b7
b6
b5
4
5
6
7
8
9
b4
b3
b2
b1
b0
ACK
Sr
1
SCL0
SDA0
7-bit slave address
W
b7
Data (DATA 1)
7-bit slave address
BBSY
MST
TRS
Transmit data (7-bit address + W)
Transmit data (DATA 1)
Transmit data (7-bit address + R)
TDRE
TEND
RDRF
7-bit address+W
ICDRT
Data (DATA 1)
7-bit address+R
7-bit address+W
ICDRS
Data (DATA 1)
7-bit address+R
XXXX (Initial value / Last data for reception)
ICDRR
“0”(ACK)
ACKBT
“X”(ACK/NACK)
ACKBR
“0”(ACK)
“0”(ACK)
START
ST
RS
Write data to
Write data to
ICDRT
Write 1
ICDRT
(7-bit
address + W)
to ST
(DATA 1)
(2)
Figure 26.46
26.11.3
(3)
(4)
Clear
Write data to
Write 1
START
ICDRT
to RS
to 0
(7-bit address + R)
(5)
(6)
(7)
Restart condition issue timing after master transmission
Issuing a Stop Condition
The IIC issues a stop condition when the SP bit in the ICCR2 register is set to 1.
When the SP bit is set to 1, a stop condition request is made, and the IIC issues a stop condition when the ICCR2.BBSY
flag is 1 (bus busy state) and the ICCR2.MST bit is 1 (master mode).
To issue a stop condition:
1. Drive the SDAn line low (high level to low level).
2. Ensure the low-level period of SCLn line set in the ICBRL register elapses.
3. Release the SCLn line (low level to high level).
4. Detect a high level of the SCLn line and ensure the time set in the ICBRH register and the stop condition setup time
elapse.
5. Release the SDAn line (low level to high level).
6. Ensure the time set in the ICBRL register and the bus free time elapse.
7. Clear the BBSY flag to 0 to release the bus mastership.
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ICBRL
ICBRH
SCLn
SDAn
ICBRL
ICBRH
8
b0
ICBRL
9
Issue stop
condition
ACK/NACK
Setup time
ICBRL
ICBRH
Bus free time
P
IIC
BBSY
MST
TRS
TDRE
STOP
SP
Write 1 to SP
Figure 26.47
Accept stop condition issuance
Clear STOP to 0
Stop condition issue timing using the SP bit
26.12 Bus Hanging
If the clock signals from the master and slave devices are out of synchronization because of noise or other factors, the I2C
bus might hang with a fixed level on the SCLn line or SDAn line. To manage bus hanging, the IIC has:
A timeout function to detect hanging by monitoring the SCLn line
A function for outputting an extra SCL clock cycle to release the bus from a hung state because of clock signals
being out of sync
The IIC reset function
An internal reset function.
By checking the SCLO, SDAO, SCLI, and SDAI bits in the ICCR1 register, it is possible to determine whether the IIC or
its communicating partner is placing the low level on the SCLn or SDAn lines.
26.12.1
Timeout Function
The timeout function can detect when the SCLn line is stuck longer than the predetermined time. The IIC can detect an
abnormal bus state by monitoring that the SCLn line is stuck low or high for a predetermined time.
The timeout function monitors the SCLn line state and counts the low-level period or high-level period using the internal
counter. The timeout function resets the internal counter each time the SCLn line changes (rising or falling), but
continues to count unless the SCLn line changes. If the internal counter overflows because no SCLn line changes, the IIC
can detect the timeout and report the bus hung state.
This timeout function is enabled when the ICFER.TMOE bit is 1. It detects a hung state when the SCLn line is stuck low
or high during the following conditions:
The bus is busy (ICCR2.BBSY flag is 1) in master mode (ICCR2.MST bit is 1)
The IIC slave address is detected (ICSR1 register is not 00h) and the bus is busy (ICCR2.BBSY flag is 1) in slave
mode (ICCR2.MST bit is 0)
The bus is free (ICCR2.BBSY flag is 0) while a start condition is requested (ICCR2.ST bit is 1).
The internal counter of the timeout function uses the internal reference clock (IIC) set in the CKS[2:0] bits in the
ICMR1 register as a count source. It functions as a 16-bit counter when long mode is selected (ICMR2.TMOS = 0) or a
14-bit counter when short mode is selected (ICMR2.TMOS = 1).
The SCLn line level (low, high, or both levels) during which this counter is activated can be selected in the TMOH and
TMOL bits in the ICMR2 register. If both TMOL and TMOH bits are set to 0, the internal counter is disabled.
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[Timeout function]
Start internal
counter
Start internal
counter
Clear internal
counter
Start internal
counter
Clear internal
counter
Clear internal
counter
Start internal
counter
Start internal
counter
Start internal
counter
Clear internal
counter
Clear internal
counter
Clear internal
counter
Clear internal
counter
IIC
BBSY
TMOE
TMOH
TMOL
Write 1 to TMOH
[Example operation when TMOH = 1 and TMOL = 1]
Clear internal counter
7
8
9
When a stat condition is issued
S
1
Bus free time
TMOS = 1
TMOS = 0
2
7
7-bit slave address
Write 0 to TMOE
In the slave-address matched state
Start internal counter
P
A/NA
Write 1 to TMOL
Write 0 to TMOL
8
9
R/W# ACK
1
14-bit counter
overflows
16-bit counter
overflows
2
Data
BBSY
ST
TMOE
TMOF
Figure 26.48
26.12.2
Timeout function using the TMOE, TMOS, TMOH, and TMOL bits
Extra SCL Clock Cycle Output Function
In master mode, the extra SCL clock cycle function outputs extra SCL clock cycles to release the SDAn line of the slave
device from being held at the low level because the master is out of sync with the slave device. This function is mainly
used in master mode to release the SDAn line of the slave device from being fixed low by including extra cycles of SCL
output from the IIC. It uses single cycles of the SCL clock for a bus error where the IIC cannot issue a stop condition
because the slave device is holding the SDAn line at the low level. Do not use this function in normal situations. Using it
when communications are proceeding correctly leads to malfunctions.
When the CLO bit in ICCR1 is set to 1 in master mode, a single cycle of the SCL clock at the transfer rate specified in the
CKS[2:0] bits in ICMR1, and in the ICBRH and ICBRL registers, is output as an extra clock cycle. After output of this
single cycle of the SCL clock, the CLO bit automatically sets to 0. Therefore, more extra clock cycles can be output
consecutively by the software program writing 1 to the CLO bit after having read CLO = 0.
When the IIC module is in master mode and the slave device is holding the SDAn line at the low level because
synchronization with the slave device was lost because of noise or other effects, the output of a stop condition is not
possible. This function can be used to output extra cycles of SCL one by one to make the slave device release the SDAn
line from being held at the low level, and recover the bus from an unusable state. Release of the SDAn line by the slave
device can be monitored by reading the ICCR1.SDAI bit. After confirming release of the SDAn line by the slave device,
complete communications by reissuing the stop condition.
Use this function with the MALE bit in the ICFER register set to 0 (master arbitration-lost detection disabled). If the
MALE bit is set to 1 (enabled), arbitration is lost when the value of the ICCR1.SDAO bit does not match the state of the
SDAn line.
[Output conditions for using the CLO bit in ICCR1]:
When the bus is free (ICCR2.BBSY = 0) or in master mode (MST = 1 and BBSY = 1 in ICCR2)
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When the communication device does not hold the SCLn line low.
Figure 26.49 shows the operation timing of the extra SCL clock cycle output function (CLO bit).
ICBRH
SCLn
ICBRL
9
SDAn line is held low because of irregular bits
ICBRH
ICBRL
Extra clock cycle
output
ACK or Data 0
SDAn
Release SDAn line
ICBRH
ICBRL
Extra clock cycle
output
MSB or Next Data
Data 1
IIC
BBSY
MST
TRS
CLO
Accept CLO output
Figure 26.49
26.12.3
Write 1 to CLO
Write 1 to CLO
Extra SCL clock cycle output function using the CLO bit
IIC Reset and Internal Reset
The IIC module incorporates a function for resetting itself. There are two types of reset:
IIC reset, which initializes all registers, including the BBSY flag in the ICCR2 register
Internal reset, which releases the IIC from the slave-address matched state and initializes the internal counter while
saving other settings.
After issuing a reset, be sure to set the IICRST bit in ICCR1 to 0.
Both types of reset are effective for release from bus-hung states, because both restore the output state of the SCLn and
SDAn pins to the high-impedance state.
Issuing a reset during slave operation might lead to a loss of synchronization between the master device clock and the
slave device clock, so avoid this when possible. In addition, monitoring of the bus state, such as for the presence of a start
condition, is not possible during an IIC reset (ICE and IICRST bits = 01b in ICCR1).
For a detailed description of the IIC and internal resets, see section 26.15, State of Registers when Issuing Each
Condition.
26.13 SMBus Operation
The IIC supports data communication conforming to the SMBus Specification (version 2.0). To perform SMBus
communication, set the SMBS bit in ICMR3 to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the
SMBus standard, set the ICMR1.CKS[2:0] bits, and the ICBRH and ICBRL registers. In addition, determine the values
of the ICMR2.DLCS bit and the ICMR2.SDDL[2:0] bits to meet the data hold time specification of 300 ns or more.
When the IIC is used only as a slave device, the transfer rate setting is not required, but the ICBRL register must be set to
a value longer than the data setup time (250 ns).
For the SMBus device default address (1100 001b), use one of the slave address registers L0 to L2 (SARL0, SARL1, and
SARL2), and set the associated FS bit (7- or 10-bit address format select) in SARUy (y = 0 to 2) to 0 (7-bit address
format).
When transmitting the UDID (Unique Device Identifier), set the ICFER.SALE bit to 1 to enable the slave arbitration-lost
detection function.
26.13.1
(1)
SMBus Timeout Measurement
Measuring slave device timeout
The following period (timeout interval: TLOW: SEXT) must be measured for slave devices in SMBus communication:
From start condition to stop condition.
To measure timeout for slave devices, measure the period from start condition detection to stop condition detection with
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the GPT using the IIC start condition detection interrupt (STIn) and stop condition detection interrupt (SPIn). The
measured timeout period must be within the total clock low-level period [slave device] TLOW: SEXT: 25 ms (maximum)
of the SMBus standard.
If the time measured with the GPT exceeds the clock low-level detection timeout TTIMEOUT: 25 ms (minimum) of the
SMBus standard, the slave device must release the bus by writing 1 to the ICCR1.IICRST bit to issue an internal reset of
the IIC. When an internal reset is issued, the IIC stops driving the bus for the SCLn pin and SDAn pin and makes the
SCLn and SDAn pin output high-impedance, which releases the bus.
(2)
Measuring master device timeout
The following periods (timeout interval: TLOW: MEXT) must be measured for master devices in SMBus communication:
From start condition to acknowledge bit
Between acknowledge bits
From acknowledge bit to stop condition.
To measure timeout for master devices, measure these periods with the GPT using the IIC start condition detection
interrupt (STIn), stop condition detection interrupt (SPIn), transmit end interrupt (IICn_TEI), or receive data full
interrupt (IICn_RXI). The measured timeout period must be within the total clock low-level extended period (master
device) TLOW: MEXT: 10 ms (maximum) of the SMBus standard, and the total of all TLOW: MEXT from start condition to
stop condition must be within TLOW: SEXT: 25 ms (maximum).
For the ACK receive timing (rising edge of the ninth SCL clock cycle), monitor the ICSR2.TEND flag in master transmit
mode (master transmitter) and the ICSR2.RDRF flag in master receive mode (master receiver). Perform byte-wise
transmit operations in master transmit mode, and hold the ICMR3.RDRFS bit 0 until the byte immediately before
reception of the final byte in master receive mode. While the RDRFS bit is 0, the RDRF flag is set to 1 on the rising edge
of the ninth SCL clock cycle.
If the period measured with the GPT exceeds the total clock low-level extended period (master device) TLOW: MEXT: 10
ms (maximum) of the SMBus standard or the total of measured periods exceeds the clock low-level detection timeout
TTIMEOUT: 25 ms (minimum) of the SMBus standard, the master device must stop the transaction by issuing a stop
condition. In master transmit mode, immediately stop the transmit operation (stop writing data to the ICDRT register).
SMBus standard
Start
Stop
TLOW:SEXT
Clk ACK
TLOW:MEXT
S
TLOW:SEXT: Total clock low-level extended period (slave device)
TLOW:MEXT: Total clock low-level extended period (master device)
1
2
7
8
9
Clk ACK
TLOW:MEXT
1
2
7
8
9
Clk ACK
TLOW:MEXT
1
2
7
8
9
TLOW:MEXT
P
SCLn
SDAn
7-bit slave address
R/W# ACK
Data
ACK
Data
A/NA
BBSY
TDRE
TEND
RDRF
RDRFS
START
STOP
Measured with the GPT
Figure 26.50
26.13.2
SMBus timeout measurement
Packet Error Code (PEC)
The MCU incorporates a CRC calculator, which enables transmission of a packet error code (PEC) or allows checking
the received data in SMBus data communication of the IIC. For the CRC generating polynomials of the CRC calculator,
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see section 29, Cyclic Redundancy Check (CRC) Calculator.
The PEC data in master transmit mode can be generated by writing all transmit data to the CRC data input register
(CRCDIR) in the CRC calculator.
The PEC data in master receive mode can be checked by writing all receive data to the CRCDIR register in the CRC
calculator and comparing the obtained value in the CRC data output register (CRCDOR) with the received PEC data.
To send ACK or NACK according to the match or mismatch result when the final byte is received as a result of the PEC
code check, set the ICMR3.RDRFS bit to 1 before the rising edge of the eighth SCL clock cycle during reception of the
final byte, and hold the SCLn line low on the falling edge of the eighth clock cycle.
26.13.3
SMBus Host Notification Protocol (Notify ARP Master Command)
In communications over an SMBus, a slave device can temporarily act as a master device to notify the SMBus host (or
ARP master) of its own slave address or to request its own slave address from the SMBus host.
For a product using the MCU to operate as an SMBus host or ARP master, the host address (0001 000b) sent from the
slave device must be detected as a slave address, so the IIC has a function for detecting the host address. To detect the
host address as a slave address, set the ICMR3.SMBS bit and the ICSER.HOAE bit to 1. Operation after the host address
is detected is the same as normal slave operation.
26.14 Interrupt Sources
The IIC issues four types of interrupt request:
Transfer error or event generation (arbitration-lost, NACK detection, timeout detection, start condition detection,
and stop condition detection)
Receive data full
Transmit data empty
Transmit end.
Table 26.10 lists details about the interrupt requests. The receive data full and transmit data empty conditions can activate
data transfer by the DTC.
Table 26.10
Interrupt sources
Symbol
Interrupt source
Interrupt flag
DTC activation
Interrupt condition
IICn_EEI*5
Transfer error/event generation
AL
Not possible
AL = 1, ALIE = 1
NACKF
NACKF = 1, NAKIE = 1
TMOF
TMOF = 1, TMOIE = 1
START
START = 1, STIE = 1
STOP
STOP = 1, SPIE = 1
IICn_RXI*2, *5
Receive data full
RDRF
Possible
RDRF = 1, RIE = 1
IICn_TXI*1, *5
Transmit data empty
TDRE
Possible
TDRE = 1, TIE = 1
IICn_TEI*3, *5
Transmit end
TEND
Not possible
TEND = 1, TEIE = 1
IIC0_WUI*4
Slave address match during wakeup
function
WUF
Not possible
Slave address match
Slave receive complete
RWAK operation ASY0 = 1
WUIE = 1
Note:
There is a delay between the execution of a write instruction for a peripheral module by the CPU and the actual
writing to the module. When an interrupt flag is cleared or masked, read the relevant flag again to check whether
clearing or masking is complete, and then return from interrupt handling. Not doing so creates the possibility of
repeated processing of the same interrupt.
Note 1. Because IICn_TXI is an edge-detected interrupt, it does not require clearing. Additionally, the ICSR2.TDRE flag
(a condition for IICn_TXI) is automatically set to 0 when transmit data is written to ICDRT or a stop condition is
detected (ICSR2.STOP = 1).
Note 2. Because IICn_RXI is an edge-detected interrupt, it does not require clearing. Additionally, the ICSR2.RDRF flag
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(a condition for IICn_RXI) is automatically set to 0 when data is read from ICDRR.
Note 3. When using the IICn_TEI interrupt, clear the ICSR2.TEND flag in the IICn_TEI interrupt handling.
The ICSR2.TEND flag is automatically set to 0 when transmit data is written to ICDRT or a stop condition is
detected (ICSR2.STOP = 1).
Note 4. Only channel 0 has a wakeup function, so IIC0_WUI is for channel 0 only.
Note 5. Channel number (n = 0, 1).
Clear or mask each flag during interrupt handling.
26.14.1
Buffer Operation for IICn_TXI and IICn_RXI Interrupts
If the conditions for generating an IICn_TXI and IICn_RXI interrupt are satisfied while the associated IR flag is 1, the
interrupt request is not output for the ICU but saved internally. One request per source can be saved internally.
An interrupt request that is saved within the ICU is output when the value of the ICU.IELSRn.IR flag becomes 0.
Internally saved interrupt requests are automatically cleared under normal conditions of usage. Internally saved interrupt
requests can also be cleared by writing 0 to the interrupt enable bit within the given peripheral module.
26.15 State of Registers when Issuing Each Condition
The IIC has two dedicated resets, IIC reset and internal reset. Table 26.11 lists the register states when issuing each
condition.
Table 26.11
Register states when issuing each condition (1 of 2)
Registers
ICCR1
ICE, IICRST
Reset
IIC reset
(ICE = 0, IICRST = 1)
Reset
SCLO, SDAO
Internal reset
(ICE = 1, IICRST = 1)
Start or restart
condition detection
Stop condition
detection
Saved
Saved
Saved
Saved
Reset
Reset
Saved
Set
Saved
Reset
Saved
Saved
Set or saved
Reset
Others
ICCR2
BBSY
Saved
Reset
Reset
ST
TRS, MST
Others
ICMR1
BC[2:0]
Reset
Reset
Others
Reset
Reset or saved
Reset
Reset
Saved
Saved
Saved
ICMR2
Reset
Reset
Saved
Saved
Saved
ICMR3
Reset
Reset
Saved
Saved
Saved
ICFER
Reset
Reset
Saved
Saved
Saved
ICSER
Reset
Reset
Saved
Saved
Saved
ICIER
Reset
Reset
Saved
Saved
Saved
ICSR1
Reset
Reset
Reset
Saved
Reset
Reset
Reset
Reset
Saved
Reset
ICSR2
TDRE, TEND
START
Set
STOP
Saved
Others
ICWUR
Set
Saved
Reset
Reset
Saved
Saved
Saved
SARL0, SARL1, SARL2 Reset
SARU0, SARU1, SARU2
Reset
Saved
Saved
Saved
ICBRH, ICBRL
Reset
Reset
Saved
Saved
Saved
ICDRT
Reset
Reset
Saved
Saved
Saved
ICDRR
Reset
Reset
Saved
Saved
Saved
ICDRS
Reset
Reset
Reset
Saved
Saved
Timeout function
Reset
Reset
Operation
Operation
Operation
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Table 26.11
Register states when issuing each condition (2 of 2)
Registers
Reset
IIC reset
(ICE = 0, IICRST = 1)
Internal reset
(ICE = 1, IICRST = 1)
Start or restart
condition detection
Stop condition
detection
Bus free time
measurement
Reset
Reset
Operation
Operation
Operation
26.16 Event Link Output
The IIC0 and IIC1 modules handle event output for the Event Link Controller (ELC) for the following sources:
(1)
Transfer Error Event
When a transfer error event occurs, the associated event signal can be output to another module by the ELC.
(2)
Receive Data Full
When a receive data register becomes full, the associated event signal can be output to another module by the ELC.
(3)
Transmit Data Empty
When a transmit data register becomes empty, the associated event signal can be output to another module by the ELC.
(4)
Transmit End
On completion of transfer, the associated event signal can be output to another module by the ELC.
26.16.1
Interrupt Handling and Event Linking
Each of the IIC interrupt types (see Table 26.10) has an enable bit to control enabling and disabling of the associated
interrupt signal. An interrupt request signal is output for the CPU when an interrupt source condition is satisfied while
the associated enable bit is set.
The associated event link output signals are sent to other modules as event signals by the ELC when the interrupt source
conditions are satisfied, regardless of the settings of the interrupt enable bits. For details on interrupt sources, see Table
26.10.
26.17 Usage Notes
26.17.1
Settings for the Module-Stop State
The Module Stop Control Register B (MSTPCRB) can enable or disable IIC operation. The module is initially stopped
after a reset. The registers become accessible on release from the module-stop state. For details on Module-Stop Control
Register B, see section 10, Low Power Modes.
26.17.2
Notes on Starting Transfer
If the IR flag associated with the IIC interrupt is 1 when transfer is started (ICCR1.ICE bit = 1), use the following
procedure to clear interrupts before enabling operations. Starting transfer with the IR flag set to 1 while the ICCR1.ICE
bit is 1 leads to an interrupt request being internally saved after transfer starts, and this can lead to unanticipated behavior
of the IR flag.
1. Confirm that the ICCR1.ICE bit is 0.
2. Set the relevant interrupt enable bits, such as ICIER.TIE, to 0.
3. Read the relevant interrupt enable bits, such as ICIER.TIE, and confirm that the value is 0.
4. Set the IR flag to 0.
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27.
27. Controller Area Network (CAN) Module
Controller Area Network (CAN) Module
The MCU has one Controller Area Network module.
27.1
Overview
The CAN module uses a message-based protocol to receive and transmit data between multiple slaves and masters in
electromagnetically noisy applications. The module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard
and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO
modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN module requires an
additional external CAN transceiver.
Table 27.1 lists the features of the CAN module and Figure 27.1 shows a block diagram.
Table 27.1
CAN module features (1 of 2)
Parameter
Description
Data transfer
ISO11898-1-compliant for standard and extended frames
Bit rate
Programmable up to 1 Mbps (fCAN 8 MHz)
fCAN: CAN clock source
Message box
32 mailboxes, with two selectable mailbox modes:
Normal mode: 32 mailboxes independently configurable for either transmission or reception
FIFO mode: 24 mailboxes independently configurable for either transmission or reception, with
remaining mailboxes used for receive and transmit 4-stage FIFOs.
Reception
Acceptance filter
Eight acceptance masks (one for every four mailboxes)
Masks independently enabled or disabled for each mailbox.
Transmission
Mode transition for bus-off
recovery
Mode transition for the recovery from the bus-off state selectable to:
ISO11898-1 specification-compliant
Automatic entry into CAN halt mode on bus-off entry
Automatic entry into CAN halt mode on bus-off end
Transition to CAN halt mode through software
Transition to error-active state through software.
Error status monitoring
Monitoring of CAN bus errors, including stuff error, form error, ACK error, 15-bit CRC error, bit error,
and ACK delimiter error
Detection of transition to error states, including error-warning, error-passive, bus-off entry, and bus-off
recovery
Supports reading of error counters.
Time stamping
Time stamp function using a 16-bit counter
Reference clock selectable to 1-, 2-, 4-, and 8-bit time periods.
Interrupt function
Supports five interrupt sources: reception complete, transmission complete, receive FIFO, transmit
FIFO, and error interrupts
Support for data frame and remote frame reception
Reception ID format selectable to only standard ID, only extended ID, or mixed IDs
Programmable one-shot reception function
Selectable between overwrite mode (unread message overwritten) and overrun mode (unread
message saved)
Reception complete interrupt independently enabled or disabled for each mailbox.
Support for data frame and remote frame transmission
Transmission ID format selectable to only standard ID, only extended ID, or mixed IDs
Programmable one-shot transmission function
Broadcast messaging function
Priority mode selectable based on message ID or mailbox number
Support for transmission request abort, with abort completion confirmable in status flag
Transmission complete interrupt independently enabled or disabled for each mailbox.
CAN sleep mode
CAN clock stopped to reduce power consumption
Software support unit
Three software support units:
Acceptance filter support
Mailbox search support, including receive mailbox search, transmit mailbox search, and message lost
search
Channel search support.
CAN clock source
Peripheral module clock, CANMCLK
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Table 27.1
27. Controller Area Network (CAN) Module
CAN module features (2 of 2)
Parameter
Description
Test mode
Three test modes available for evaluation purposes:
Listen-only mode
Self-test mode 0 (external loopback)
Self-test mode 1 (internal loopback).
Module-stop function
Module-stop state can be set to reduce power consumption
Internal peripheral bus
CAN control registers
CRX0
Protocol
controller
CTX0
fCANCLK
Baud rate
prescaler
(BRP)
Acceptance
filter
ID priority
transmission
controller
Mailboxes
Timer
Peripheral module clock
(PCLKB)
System clock ICLK
EXTAL
CAN0 reception complete interrupt
CANMCLK (fCAN)
CAN0 transmission complete interrupt
Interrupt
generator
BRP:
Bit in the BCR register
fCANCLK: CAN communication clock
fCAN:
CAN system clock
Figure 27.1
CAN0 receive FIFO interrupt
CAN0 transmit FIFO interrupt
CAN0 error interrupt
CAN module block diagram
The CAN module includes the following blocks:
CAN input and output pins
CRX0 and CTX0
Protocol controller
Handles CAN protocol processing such as bus arbitration, bit timing during transmission and reception, stuffing,
and error handling.
Mailboxes
Consists of 32 mailboxes, which can be configured as either transmit or receive. Each mailbox has an individual ID,
data length code (DLC), data field (8 bytes), and time stamp.
Acceptance filter
Performs filtering of received messages using MKRk register settings.
Timer
Used for the time stamp function. The timer value when a message is stored in the mailbox is written as the time
stamp value.
Interrupt generator
Generates five types of interrupts:
CAN0 reception complete interrupt
CAN0 transmission complete interrupt
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27. Controller Area Network (CAN) Module
CAN0 receive FIFO interrupt
CAN0 transmit FIFO interrupt
CAN0 error interrupt.
The CAN module communicates on the pins listed in Table 27.2. These pins are multiplexed with other signals on the
MCU. For details, see section 16, I/O Ports.
Table 27.2
Pin configuration
Pin name
I/O
Function
CRX0
Input
Data receive pin
CTX0
Output
Data transmit pin
27.2
Register Descriptions
27.2.1
Control Register (CTLR)
Address(es): CAN0.CTLR 4005 0840h
Value after reset:
b15
b14
b13
—
—
RBOC
0
0
0
b12
b11
BOM[1:0]
0
b10
SLPM
0
1
b9
b8
b7
b6
CANM[1:0]
TSPS[1:0]
0
0
1
0
b5
b4
b3
TSRC
TPM
MLM
0
0
0
b2
b1
IDFM[1:0]
0
0
b0
MBM
0
Bit
Symbol
Bit name
Description
R/W
b0
MBM
CAN Mailbox Mode
Select*1
0: Normal mailbox mode
1: FIFO mailbox mode.
R/W
b2, b1
IDFM[1:0]
ID Format Mode Select
*1
b2 b1
R/W
b3
MLM
Message Lost Mode
Select*1
0: Overwrite mode
1: Overrun mode.
R/W
b4
TPM
Transmission Priority
Mode Select*1
0: ID priority transmit mode
1: Mailbox number priority transmit mode.
R/W
b5
TSRC
Time Stamp Counter
Reset Command*4
0: Do not reset time stamp counter
1: Reset time stamp counter.*3
R/W
b7, b6
TSPS[1:0]
Time Stamp Prescaler
Select*1
b7 b6
R/W
b9, b8
CANM[1:0]
CAN Mode Operation
Select*5
b9 b8
R/W
b10
SLPM
CAN Sleep Mode*5,*6
0: Exit sleep mode
1: Enter CAN sleep mode.
R/W
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0 0: Standard ID mode:
All mailboxes, including FIFO mailboxes, handle only standard IDs.
0 1: Extended ID mode:
All mailboxes, including FIFO mailboxes, handle only extended IDs.
1 0: Mixed ID mode:
All mailboxes, including FIFO mailboxes, handle both standard and
extended IDs. In normal mailbox mode, use the associated IDE bit
to differentiate standard and extended IDs. In FIFO mailbox mode,
the associated IDE bits are used for mailboxes 0 to 23, the IDE bits
in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE
bit associated with mailbox 24 is used for the transmit FIFO.
1 1: Setting prohibited.
0
0
1
1
0
0
1
1
0: Every 1-bit time
1: Every 2-bit time
0: Every 4-bit time
1: Every 8-bit time.
0: CAN operation mode
1: CAN reset mode
0: CAN halt mode
1: CAN reset mode (forced transition).
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27. Controller Area Network (CAN) Module
Bit
Symbol
Bit name
Description
R/W
b12, b11
BOM[1:0]
Bus-Off Recovery
Mode*1
b12 b11
R/W
b13
RBOC
Forced Return from
Bus-Off*2
0: No return occurred
1: Forced return from bus-off state.*3
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0 0: Normal mode (ISO11898-1-compliant)
0 1: Enter CAN halt mode automatically on entering bus-off state
1 0: Enter CAN halt mode automatically on end of bus-off state
1 1: Enter CAN halt mode during bus-off recovery period through a software request.
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Write to the BOM[1:0], TSPS[1:0], TPM, MLM, IDFM[1:0], and MBM bits in CAN reset mode.
Set the RBOC bit to 1 in the bus-off state.
This bit automatically clears to 0 after being set to 1. It should be read as 0.
Set the TSRC bit to 1 in CAN operation mode.
When the CANM[1:0] and SLPM bits are changed, check the STR register to ensure that the mode is switched.
Do not change the CANM[1:0] bits or SLPM bit until the mode is switched.
Note 6. Write to the SLPM bit in CAN reset mode or CAN halt mode. When changing the SLPM bit, write 0 or 1 to only the
SLPM bit.
MBM bit (CAN Mailbox Mode Select)
When the MBM bit is 0 (normal mailbox mode), mailboxes 0 to 31 are configured as transmit or receive mailboxes.
When the MBM bit is 1 (FIFO mailbox mode):
Mailboxes 0 to 23 are configured as transmit or receive mailboxes
Mailboxes 24 to 27 are configured as a transmit FIFO
Mailboxes 28 to 31 are configured as a receive FIFO
Transmit data is written into mailbox 24, the window mailbox for the transmit FIFO
Receive data is read from mailbox 28, the window mailbox for the receive FIFO.
Table 27.3 lists the mailbox configurations.
IDFM[1:0] bits (ID Format Mode Select)
The IDFM[1:0] bits specify the ID format.
MLM bit (Message Lost Mode Select)
The MLM bit specifies the operation when a new message is captured in an unread mailbox. Overwrite mode or overrun
mode can be selected. In both cases, the mode applies to all mailboxes, including the receive FIFO.
When MLM is 0, all mailboxes are set to overwrite mode. Any new message received overwrites the pre-existing
message.
When MLM is 1, all mailboxes are set to overrun mode. Any new message received does not overwrite the pre-existing
message, and the new message is discarded.
TPM bit (Transmission Priority Mode Select)
The TPM bit specifies the priority when transmitting messages. ID priority transmit mode or mailbox number transmit
mode can be selected. All mailboxes are set for either ID priority transmission or mailbox number priority transmission.
When the TPM bit is 0, ID priority transmit mode is selected and transmission priority is arbitrated as defined in the
ISO11898-1 CAN specification. In ID priority transmit mode, mailboxes 0 to 31 (in normal mailbox mode), mailboxes 0
to 23 (in FIFO mailbox mode), and the transmit FIFO are compared for the IDs of mailboxes configured for
transmission. If two or more mailbox IDs are the same, the mailbox with the smaller number has higher priority.
Only the next message to be transmitted from the transmit FIFO is included in the transmission arbitration. If a FIFO
message is currently being transmitted, the next pending message within the transmit FIFO is included in the arbitration.
When the TPM bit is 1, mailbox number transmit mode is selected and the transmit mailbox with the smallest number
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27. Controller Area Network (CAN) Module
has the highest priority. In FIFO mailbox mode, the transmit FIFO has lower priority than normal mailboxes (0 to 23).
TSRC bit (Time Stamp Counter Reset Command)
The TSRC bit resets the time stamp counter. When the TSRC bit is set to 1, the TSR register is set to 0000h. The TSRC
bit clears to 0 automatically.
TSPS[1:0] bits (Time Stamp Prescaler Select)
The TSPS[1:0] bits select the prescaler for the time stamp. The reference clock for the time stamp can be selected to 1-,
2-, 4-, or 8-bit time periods.
CANM[1:0] bits (CAN Mode Operation Select)
The CANM[1:0] bits select one of the following modes for the CAN module:
CAN operation mode
CAN reset mode
CAN halt mode.
CAN sleep mode is set in the SLPM bit.
When the CAN module enters CAN halt mode based on the BOM[1:0] setting, the CANM[1:0] bits are automatically set
to 10b.
For details, see section 27.3, Operation Modes.
SLPM bit (CAN Sleep Mode)
When the SLPM bit is set to 1, the CAN module enters CAN sleep mode. When the SLPM bit is set to 0, the CAN
module exits CAN sleep mode. For details, see section 27.3, Operation Modes.
BOM[1:0] bits (Bus-Off Recovery Mode)
The BOM[1:0] bits select bus-off recovery mode for the CAN module.
When the BOM[1:0] bits are 00b, the recovery from bus-off is compliant with the ISO11898-1 specification. The CAN
module recovers CAN communication (error-active state) after detecting 11 consecutive recessive bits 128 times. A busoff recovery interrupt request is generated when recovering from bus-off.
When the BOM[1:0] bits are 01b and the CAN module reaches the bus-off state, the CANM[1:0] bits are set to 10b to
enter CAN halt mode. No bus-off recovery interrupt request is generated when recovering from bus-off, and the TECR
and RECR registers are set to 00h.
When the BOM[1:0] bits are 10b, the CANM[1:0] bits are set to 10b as soon as the CAN module reaches the bus-off
state. The CAN module enters CAN halt mode after the recovery from the bus-off state, after detecting 11 consecutive
recessive bits 128 times. A bus-off recovery interrupt request is generated when recovering from bus-off, and the TECR
and RECR registers are set to 00h.
When the BOM[1:0] bits are 11b, the CAN module enters CAN halt mode by setting the CANM[1:0] bits to 10b while
the CAN module is still in the bus-off state. No bus-off recovery interrupt request is generated when recovering from
bus-off and the TECR and RECR registers are set to 00h. However, the interrupt does occur if the CAN module recovers
from bus-off after detecting 11 consecutive recessive bits 128 times before the CANM[1:0] bits are set to 10b.
If the CPU requests an entry to CAN reset mode at the same time as the CAN module attempts to enter CAN halt mode
(at bus-off entry when the BOM[1:0] bits are 01b, or at bus-off end when the BOM[1:0] bits are 10b), then the CPU
request has higher priority.
RBOC bit (Forced Return from Bus-Off)
When the RBOC bit is set to 1 in the bus-off state, the CAN module forcibly exits bus-off. The RBOC bit is
automatically set to 0, and the error state changes from bus-off to error-active. When the RBOC bit is set to 1, the RECR
and TECR registers are set to 00h and the STR.BOST bit is set to 0, indicating no bus-off state. The other registers
remain unchanged when the RBOC bit is set to 1. No bus-off recovery interrupt request is generated. Use the RBOC bit
only when the BOM[1:0] bits are 00b (normal mode).
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Table 27.3
27. Controller Area Network (CAN) Module
Mailbox configuration
Mailbox
MBM bit = 0 (normal mailbox mode)
MBM bit = 1 (FIFO mailbox mode)*1 to *5
Mailboxes 0 to 23
Normal mailbox
Normal mailbox
Mailboxes 24 to 27
Transmit FIFO
Mailboxes 28 to 31
Receive FIFO
Note 1. The transmit FIFO is controlled by the TFCR register. The MCTL_TXj registers associated with mailboxes 24 to
27 are disabled. MCTL_TX24 to MCTL_TX27 cannot be used by the transmit FIFO.
Note 2. The receive FIFO is controlled by the RFCR register. The MCTL_RXj registers associated with mailboxes 28 to
31 are disabled. MCTL_RX28 to MCTL_RX31 cannot be used by the receive FIFO.
Note 3. See the MIER_FIFO register description for information on FIFO interrupts.
Note 4. The MKIVLR register bits associated with mailboxes 24 to 31 are disabled. Set these bits to 0.
Note 5. The transmit and receive FIFOs can be used for both data and remote frames.
27.2.2
Bit Configuration Register (BCR)
Address(es): CAN0.BCR 4005 0844h
b31
b30
b29
b28
TSEG1[3:0]
b27
b26
—
—
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BRP[9:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
SJW[1:0]
—
—
—
—
—
—
—
—
CCLKS
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Value after reset:
0
TSEG2[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CCLKS
CAN Clock Source
Selection
0: Setting prohibited
1: CANMCLK (generated by the main clock oscillator).
This bit must be set to 1 when using the CAN module.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b10 to b8
TSEG2[2:0]
Time Segment 2 Control
b10
R/W
b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b13, b12
SJW[1:0]
Synchronization Jump
Width Control
b13 b12
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b25 to b16
BRP[9:0]
Baud Rate Prescaler
Select*1
These bits set the frequency of the CAN communication clock
(fCANCLK).
R/W
b26
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b27
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
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0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b8
0: Setting prohibited
1: 2 Tq
0: 3 Tq
1: 4 Tq
0: 5 Tq
1: 6 Tq
0: 7 Tq
1: 8 Tq.
0: 1 Tq
1: 2 Tq
0: 3 Tq
1: 4 Tq.
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27. Controller Area Network (CAN) Module
Bit
Symbol
Bit name
Description
R/W
b31 to b28
TSEG1[3:0]
Time Segment 1 Control
b31
R/W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b28
0: Setting prohibited
1: Setting prohibited
0: Setting prohibited
1: 4 Tq
0: 5 Tq
1: 6 Tq
0: 7 Tq
1: 8 Tq
0: 9 Tq
1: 10 Tq
0: 11 Tq
1: 12 Tq
0: 13 Tq
1: 14 Tq
0: 15 Tq
1: 16 Tq.
Tq: Time Quantum
Note 1. Do not select a value less than 1 when the SCKSCR.CKSEL[2:0] bits are 011b (selecting the main clock
oscillator).
For details about setting the bit timing, see section 27.4, Data Transfer Rate Configuration. Set the BCR register before
entering CAN halt mode or CAN operation mode from CAN reset mode. After the setting is made once, this register can
be written to in CAN reset mode or CAN halt mode. A 32-bit read/write access must be performed carefully so as not to
change bits 0 to 7.
TSEG2[2:0] bits (Time Segment 2 Control)
The TSEG2[2:0] bits specify the length of the phase buffer segment 2 (PHASE_SEG2). A value from 2 to 8 Tq can be
set. Set a value smaller than that of the TSEG1[3:0] bits.
SJW[1:0] bits (Synchronization Jump Width Control)
The SJW[1:0] bits specify the synchronization jump width. A value from 1 to 4 Tq can be set. Set a value smaller than or
equal to that of the TSEG2[2:0] bits.
BRP[9:0] bits (Baud Rate Prescaler Select)
The BRP[9:0] bits set the frequency of the CAN communication clock (fCANCLK). The fCANCLK cycle is 1 Tq. If the
setting is P (0 to 1023), the baud rate prescaler divides fCAN by P + 1.
TSEG1[3:0] bits (Time Segment 1 Control)
The TSEG1[3:0] bits specify the total length of the propagation time segment (PROP_SEG) and phase buffer segment 1
(PHASE_SEG1). A value from 4 to 16 Tq can be set.
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27.2.3
27. Controller Area Network (CAN) Module
Mask Register k (MKRk) (k = 0 to 7)
Address(es): CAN0.MKR[0] 4005 0400h to CAN0.MKR[7] 4005 041Ch
b31
b30
b29
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
SID[10:0]
b16
EID[17:0]
EID[17:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b17 to b0
EID[17:0]
Extended ID
0: Do not compare associated EID[17:0] bit
1: Compare associated EID[17:0] bit.
R/W
b28 to b18
SID[10:0]
Standard ID
0: Do not compare associated SID[10:0] bit
1: Compare associated SID[10:0] bit.
R/W
b31 to b29
—
Reserved
The read value is undefined. The write value should be 0.
R/W
For the mask function in FIFO mailbox mode, see section 27.6, Acceptance Filtering and Masking Functions.
Write to the MKRk registers in CAN reset mode or CAN halt mode.
EID[17:0] bits (Extended ID)
The EID[17:0] bits are the filter mask bits associated with the CAN extended ID bits. They are used to receive extended
ID messages. When an EID[17:0] bit is set to 0, the respective received ID bit is not compared with the associated
mailbox ID bit. When an EID[17:0] bit is set to 1, the respective received ID bit is compared with the associated mailbox
ID bit.
SID[10:0] bits (Standard ID)
The SID[10:0] bits are the filter mask bits associated with the CAN standard ID bits. They are used to receive both
standard ID and extended ID messages. When an SID[10:0] bit is set to 0, the respective received ID bit is not compared
with the associated mailbox ID bit. When an SID[10:0] bit is set to 1, the respective received ID bit is compared with the
associated mailbox ID bit.
27.2.4
FIFO Received ID Compare Registers 0 and 1 (FIDCR0 and FIDCR1)
Address(es): CAN0.FIDCR0 4005 0420h, CAN0.FIDCR1 4005 0424h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
IDE
RTR
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
SID[10:0]
b17
b16
EID[17:0]
EID[17:0]
Value after reset:
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b17 to b0
EID[17:0]
Extended ID
Extended ID of the data and remote frames
R/W
b28 to b18
SID[10:0]
Standard ID
Standard ID of the data and remote frames
R/W
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27. Controller Area Network (CAN) Module
Bit
Symbol
Bit name
Description
R/W
b29
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b30
RTR
Remote Transmission
Request
0: Data frame
1: Remote frame.
R/W
b31
IDE
ID Extension*1
0: Standard ID
1: Extended ID.
R/W
Note 1. The IDE bit is enabled when the CTLR.IDFM[1:0] bits are 10b (mixed ID mode). When the CTLR.IDFM[1:0] bits
are any value other than 10b, the IDE bit should be written with 0 and read as 0.
The FIDCR0 and FIDCR1 registers are enabled when the MBM bit in the CTLR register is set to 1 (FIFO mailbox
mode). In FIFO mailbox mode, the EID[17:0], SID[10:0], RTR, and IDE bits in the mailbox 28 to mailbox 31 are
disabled. Write to the FIDCR0 and FIDCR1 registers in CAN reset mode or CAN halt mode. For information on using
the FIDCR0 and FIDCR1 registers, see section 27.6, Acceptance Filtering and Masking Functions.
EID[17:0] bits (Extended ID)
The EID[17:0] bits set the extended ID of data and remote frames. They are used to receive extended ID messages.
SID[10:0] bits (Standard ID)
The SID[10:0] bits set the standard ID of data and remote frames. They are used to receive both standard ID and
extended ID messages.
RTR bit (Remote Transmission Request)
The RTR bit sets the frame format to data frames or remote frames.
When the RTR bits in both the FIDCR0 and FIDCR1 registers are set to 0, only data frames are received.
When the RTR bits in both the FIDCR0 and FIDCR1 registers are set to 1, only remote frames are received.
When the RTR bits in FIDCR0 and FIDCR1 are set to different values, both data frames and remote frames are
received.
IDE bit (ID Extension)
The IDE bit sets the ID format to standard ID or extended ID. The IDE bit is enabled when the IDFM[1:0] bits in the
CTLR register are 10b (mixed ID mode).
When the IDE bits in both the FIDCR0 and FIDCR1 registers are set to 0, only standard ID frames are received.
When the IDE bits in both the FIDCR0 and FIDCR1 registers are set to 1, only extended ID frames are received.
When the IDE bits in FIDCR0 and FIDCR1 are set to different values, both standard ID and extended ID frames are
received.
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27.2.5
27. Controller Area Network (CAN) Module
Mask Invalid Register (MKIVLR)
Address(es): CAN0.MKIVLR 4005 0428h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MB31
MB30
MB29
MB28
MB27
MB26
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MB31 to
MB0
Mask Invalid
0: Mask valid
1: Mask invalid.
R/W
Each bit in the MKIVLR register is associated with a mailbox of the same number. Bit [0] in MKIVLR corresponds to
mailbox 0 (MB0), and bit [31] corresponds to mailbox 31 (MB31).
Note:
Set bits [31:24] to 0 in FIFO mailbox mode.
When an MBn bit is set to 1, the associated acceptance mask register becomes invalid for the associated mailbox. When
an MBn bit is set to 1, a message is received by the associated mailbox only if the receive message ID matches the
mailbox ID exactly.
Write to the MKIVLR register in CAN reset mode or CAN halt mode.
27.2.6
Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31, m = 0 to 7)
Table 27.4 lists the CAN mailbox memory mapping, and Table 27.5 lists the CAN data frame configuration.
The value of the CAN mailbox is undefined after reset.
Write to MBj_ID, MBj_DL, MBj_Dm, and MBj_TS only when the associated MCTL_TXj or MCTL_RXj (j = 0 to 31)
register is 00h and the associated mailbox is not processing an abort request.
See Table 27.4 for specific register addresses.
Table 27.4
CAN mailbox memory mapping (1 of 2)
Address
Mapped message content
4005 0200h + 16 × j + 0
IDE, RTR, SID10 to SID6
4005 0200h + 16 × j + 1
SID5 to SID0, EID17, EID16
4005 0200h + 16 × j + 2
EID15 to EID8
4005 0200h + 16 × j + 3
EID7 to EID0
4005 0200h + 16 × j + 4
—
4005 0200h + 16 × j + 5
Data length code (DLC[3:0])
4005 0200h + 16 × j + 6
Data byte 0
4005 0200h + 16 × j + 7
Data byte 1
4005 0200h + 16 × j + 8
Data byte 2
4005 0200h + 16 × j + 9
Data byte 3
4005 0200h + 16 × j + 10
Data byte 4
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Table 27.4
27. Controller Area Network (CAN) Module
CAN mailbox memory mapping (2 of 2)
Address
Mapped message content
4005 0200h + 16 × j + 11
Data byte 5
4005 0200h + 16 × j + 12
Data byte 6
4005 0200h + 16 × j + 13
Data byte 7
4005 0200h + 16 × j + 14
Upper byte time stamp
4005 0200h + 16 × j + 15
Lower byte time stamp
Table 27.5
CAN data frame configuration
SID10 to SID6
SID5 to SID0
EID17 to EID16
EID15 to EID8
EID7 to EID0
DLC3 to DLC1
DATA0
DATA1
DATA7
The previous value of each mailbox is saved unless a new message is received.
Address(es): CAN0.MB0_ID 4005 0200h to CAN0.MB31_ID 4005 03F0h
b31
b30
b29
IDE
RTR
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
Value after reset:
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
SID[10:0]
b17
b16
EID[17:0]
EID[17:0]
x
Value after reset:
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
ID*1
Description
R/W
b17 to b0
EID[17:0]
Extended
Extended ID of the data and remote frames
R/W
b28 to b18
SID[10:0]
Standard ID
Standard ID of the data and remote frames
R/W
b29
—
Reserved
This read value is undefined. The write value should be 0.
R/W
b30
RTR
Remote Transmission Request
0: Data frame
1: Remote frame.
R/W
b31
IDE
ID Extension*2
0: Standard ID
1: Extended ID.
R/W
Note 1. If the mailbox receives a standard ID message, the EID bits in the mailbox are undefined.
Note 2. The IDE bit is enabled when the CTLR.IDFM[1:0] bits are 10b (mixed ID mode). When the IDFM[1:0] bits are not
10b, only write 0. It reads as 0.
Address(es): CAN0.MB0_DL 4005 0204h to CAN0.MB31_DL 4005 03F4h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
b3
b2
b1
b0
DLC[3:0]
x
x
x
x
x: Undefined
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Bit
27. Controller Area Network (CAN) Module
Symbol
Bit name
b3 to b0
DLC[3:0]
Data Length
b15 to b4
—
Reserved
Code*1
Description
R/W
b3
R/W
b0
0 0 0 0: Data length = 0 byte
0 0 0 1: Data length = 1 byte
0 0 1 0: Data length = 2 bytes
0 0 1 1: Data length = 3 bytes
0 1 0 0: Data length = 4 bytes
0 1 0 1: Data length = 5 bytes
0 1 1 0: Data length = 6 bytes
0 1 1 1: Data length = 7 bytes
1 x x x: Data length = 8 bytes.
The read value is undefined. The write value should be 0.
R/W
x: Don’t care
Note 1. If the mailbox receives a message with data length (set in DLC[3:0]) of n bytes, where n is less than 8, the data in
the DATAn to DATA7 registers in the mailbox is undefined. DATA0 to DATA7 are data registers for this mailbox.
For example, if data length is 6 bytes (DLC[3:0] = 6h), the data in DATA6 and DATA7 registers is undefined.
Address(es): CAN0.MB0_D0 4005 0206h to CAN0.MB31_D0 4005 03F6h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA0
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D1 4005 0207h to CAN0.MB31_D1 4005 03F7h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA1
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D2 4005 0208h to CAN0.MB31_D2 4005 03F8h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA2
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D3 4005 0209h to CAN0.MB31_D3 4005 03F9h
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA3
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D4 4005 020Ah to CAN0.MB31_D4 4005 03FAh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA4
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D5 4005 020Bh to CAN0.MB31_D5 4005 03FBh
b7
b6
b5
b4
b3
b2
b1
b0
DATA5
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Value after reset:
x
27. Controller Area Network (CAN) Module
x
x
x
x
x
x
x
Address(es): CAN0.MB0_D6 4005 020Ch to CAN0.MB31_D6 4005 03FCh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA6
Value after reset:
x
x
x
x
x
Address(es): CAN0.MB0_D7 4005 020Dh to CAN0.MB31_D7 4005 03FDh
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
DATA7
Value after reset:
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b7 to b0
DATA0 to
DATA7
Data Bytes 0 to 7*1,*2
DATA0 to DATA7 store the transmitted or received CAN message data.
Transmission or reception starts from DATA0. The bit order on the CAN
bus is MSB-first, and transmission or reception starts from bit 7.
R/W
Note 1. If the mailbox receives a message with n bytes (where n is less than 8), the values of DATAn to DATA7 in the
mailbox are undefined. For example, if the received data length is 6 bytes, the values of DATA6 and DATA7 are
undefined.
Note 2. If the mailbox receives a remote frame, the previous values of DATA0 to DATA7 in the mailbox are saved.
Address(es): CAN0.MB0_TS 4005 020Eh to CAN0.MB31_TS 4005 03FEh
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
TSH[7:0]
Value after reset:
x
x
x
x
x
b4
b3
b2
b1
b0
x
x
x
TSL[7:0]
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b7 to b0
TSL[7:0]
Time Stamp Lower Byte
TSH[7:0]
Time Stamp Higher Byte
The TSH[7:0] and TSL[7:0] bits store the counter value of the time
stamp when received messages are stored in the mailbox.
R/W
b15 to b8
R/W
EID[17:0] bits (Extended ID)
The EID[17:0] bits set the extended ID of data and remote frames. They are used to transmit or receive extended ID
messages.
SID[10:0] bits (Standard ID)
The SID[10:0] bits set the standard ID of data and remote frames. They are used to transmit or receive both standard ID
and extended ID messages.
RTR bit (Remote Transmission Request)
The RTR bit sets the frame format to data frames or remote frames.
The receive mailbox only receives frames with the format specified in the RTR bit.
The transmit mailbox transmits with the frame format specified in the RTR bit.
The receive FIFO mailbox receives the data frame, remote frame, or both frames, as specified in the RTR bits in the
FIDCR0 and FIDCR1 registers.
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27. Controller Area Network (CAN) Module
The transmit FIFO mailbox transmits the data frame or remote frame, as specified in the RTR bit in the transmit
message.
IDE bit (ID Extension)
The IDE bit sets the ID format to standard ID or extended ID. The IDE bit is enabled when the IDFM[1:0] bits in the
CTLR register are 10b (mixed ID mode).
The receive mailbox only receives the ID format specified in the IDE bit
The transmit mailbox transmits with the ID format specified in the IDE bit
The receive FIFO mailbox receives messages with the standard ID and extended ID settings specified in the IDE
bits in the FIDCR0 and FIDCR1 registers
The transmit FIFO mailbox transmits messages with the standard ID or extended ID setting specified in the IDE bit
in the transmit message.
DLC[3:0] bits (Data Length Code)
The DLC[3:0] bits specify the data length to be transmitted in data frames. When a remote frame is used to request data,
the DLC[3:0] bits specify the requested data length.
When a data frame is received, the received data length is stored in DLC[3:0]. When a remote frame is received, the
DLC[3:0] bits store the requested data length.
27.2.7
Mailbox Interrupt Enable Register (MIER)
Address(es): CAN0.MIER 4005 042Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MB31
MB30
MB29
MB28
MB27
MB26
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b31 to b0
MB31 to MB0
Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
Bit [31] is associated with mailbox 31 (MB31), and bit [0] with
mailbox 0 (MB0).
R/W
The MIER register can enable interrupts for each mailbox, independently. This register is available in normal mailbox
mode. Do not access this register in FIFO mailbox mode.
Each bit is associated with the mailbox having the same number. These bits enable or disable transmission and reception
complete interrupts for the associated mailboxes.
Bit [0] in MIER corresponds to mailbox 0 (MB0).
Bit [31] in MIER corresponds to mailbox 31 (MB31).
Write to MIER only when the associated MCTL_TXj or MCTL_RXj (j = 0 to 31) register is 00h and the associated
mailbox is not processing a transmission or reception abort request.
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27.2.8
27. Controller Area Network (CAN) Module
Mailbox Interrupt Enable Register for FIFO Mailbox Mode (MIER_FIFO)
Address(es): CAN0.MIER_FIFO 4005 042Ch
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
MB29
MB28
—
—
MB25
MB24
MB23
MB22
MB21
MB20
MB19
MB18
MB17
MB16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Symbol
Bit name
Description
R/W
b23 to b0
MB23 to MB0
Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
Bit [23] is associated with mailbox 23 (MB23), and bit [0] with
mailbox 0 (MB0).
R/W
b24
MB24
Transmit FIFO Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b25
MB25
Transmit FIFO Interrupt
Generation Timing Control
0: Generate every time transmission completes
1: Generate when the transmit FIFO empties on transmission
completion.
R/W
b27, b26
—
Reserved
The read value is undefined. The write value should be 0.
R/W
b28
MB28
Receive FIFO Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b29
MB29
Receive FIFO Interrupt
Generation Timing Control*1
0: Generated every time reception completes
1: Generated when the receive FIFO becomes buffer warning*2 by
reception completion.
R/W
b31, b30
—
Reserved
The read value is undefined. The write value should be 0.
R/W
Note 1. No interrupt request occurs when the receive FIFO becomes buffer warning because it is full.
Note 2. “Buffer warning” indicates a state in which the third message is stored in the receive FIFO.
The MIER_FIFO register can individually enable interrupts for each mailbox and FIFO. This register is available in
FIFO mailbox mode. Do not access it in normal mailbox mode.
The MB0 to MB23 bits are associated with the mailbox having the same number. These bits enable or disable
transmission and reception complete interrupts for the associated mailboxes.
Bit [0] corresponds to mailbox 0 (MB0)
Bit [23] corresponds to mailbox 23 (MB23).
The MB24, MB25, MB28 and MB29 bits specify whether transmit and receive FIFO interrupts are enabled, and the
timing of interrupt requests.
Write to the MIER_FIFO register only when the relevant MCTL_TXj or MCTL_RXj (j = 0 to 31) register is 00h and the
associated mailbox is not processing a transmission or reception abort request. In addition, change the MIER_FIFO bits
for the relevant FIFO only when the following conditions are met:
The TFCR.TFE bit is 0 and the TFCR.TFEST bit is 1
The RFCR.RFE bit is 0 and the RFCR.RFEST bit is 1.
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27.2.9
27. Controller Area Network (CAN) Module
Message Control Register for Transmit (MCTL_TXj) (j = 0 to 31)
Transmit mode (when the TRMREQ bit is 1 and the RECREQ bit is 0)
Address(es): CAN0.MCTL_TX[0] 4005 0820h to CAN0.MCTL_TX[31] 4005 083Fh
b7
b6
TRMRE RECRE
Q
Q
Value after reset:
0
0
b5
b4
b3
—
ONESH
OT
—
0
0
0
b2
b1
b0
TRMAB TRMAC SENTD
T
TIVE
ATA
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SENTDATA
Transmission Complete Flag
*1,*2
0: Transmission not complete
1: Transmission complete.
R/W
b1
TRMACTIVE
Transmission-in-Progress
Status Flag
0: Transmission pending or not requested
1: Transmission in progress.
R
b2
TRMABT
Transmission Abort Complete
Flag*1,*2
0: Transmission started, transmission abort failed because
transmission completed, or transmission abort not requested
1: Transmission abort complete.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
0: Disable one-shot transmission
1: Enable one-shot transmission.
R/W
Enable*2,*3
b4
ONESHOT
One-Shot
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
RECREQ
Receive Mailbox Request
*2,*3,*4,*5
0: Do not configure for reception
1: Configure for reception.
R/W
b7
TRMREQ
Transmit Mailbox Request
*2,*4
0: Do not configure for transmission
1: Configure for transmission.
R/W
Note 1. Write 0 only. Writing 1 has no effect.
Note 2. When writing to bits of this register, write 1 to the SENTDATA and TRMABT bits if they are not the write target.
Note 3. To enter one-shot transmit mode, write 1 to the ONESHOT bit at the same time as setting the TRMREQ bit to 1.
To exit one-shot transmit mode, write 0 to the ONESHOT bit after the message is transmitted or aborted.
Note 4. Do not set both the RECREQ and TRMREQ bits to 1.
Note 5. When setting the RECREQ bit to 0, set the SENDDATA, TRMACTIVE, and TRMABT bits to 0 simultaneously.
The MCTL_TXj register sets mailbox j to transmit or receive mode. In transmit mode, MCTL_TXj also controls and
indicates the status of transmission. Do not access the MCTL_TXj register if mailbox j is in receive mode. Only write to
MCTL_TXj in CAN operation mode or CAN halt mode. Do not use the MCTL_TX24 to MCTL_TX31 registers in FIFO
mailbox mode.
SENTDATA flag (Transmission Complete Flag)
The SENTDATA flag is set to 1 when data transmission from the associated mailbox is complete. The SENTDATA flag
is set to 0 through a software write. To set the SENTDATA flag to 0, first set the TRMREQ bit to 0. The SENTDATA and
TRMREQ bits cannot be set to 0 simultaneously. To transmit a new message from the associated mailbox, set the
SENTDATA flag to 0.
TRMACTIVE flag (Transmission-in-Progress Status Flag)
The TRMACTIVE flag is set to 1 when the associated mailbox of the CAN module begins transmitting a message. The
TRMACTIVE flag is set to 0 when the CAN module loses CAN bus arbitration, a CAN bus error occurs, or data
transmission is complete.
TRMABT flag (Transmission Abort Complete Flag)
The TRMABT flag is set to 1 in the following cases:
Following a transmission abort request, when the transmission abort is complete before starting transmission
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27. Controller Area Network (CAN) Module
Following a transmission abort request, when the CAN module detects CAN bus arbitration-lost or CAN bus error
In one-shot transmission mode (RECREQ = 0, TRMREQ = 1, and ONESHOT = 1), when the CAN module detects
CAN bus arbitration-lost or a CAN bus error.
The TRMABT flag is not set to 1 when data transmission is complete. The TRMABT flag is set to 0 through a software
write.
ONESHOT bit (One-Shot Enable)
When the ONESHOT bit is set to 1 in transmit mode (RECREQ = 0 and TRMREQ = 1), the CAN module transmits a
message only one time. (The CAN module does not transmit the message again if a CAN bus error or CAN bus
arbitration-lost error occurs.) When transmission is complete, the SENTDATA flag is set to 1. If transmission does not
complete because of a CAN bus error or CAN bus arbitration-lost error, the TRMABT flag is set to 1. Set the ONESHOT
bit to 0 after the SENTDATA or TRMABT flag is set to 1.
RECREQ bit (Receive Mailbox Request)
When the RECREQ bit is set to 1, the associated mailbox is configured for reception of a data frame or remote frame.
When the RECREQ bit is set to 0, the associated mailbox is not configured for reception of a data frame or remote frame.
Due to hardware protection, the RECREQ bit cannot be set to 0 through a software write during the following period:
Hardware protection is started from acceptance filter processing (the beginning of the CRC field)
Hardware protection is released:
For the mailbox that is specified to receive the incoming message, after the received data is stored in the mailbox
or a CAN bus error occurs. This means that the maximum period of hardware protection is from the beginning of
CRC field to the end of the 7th bit of EOF.
For the other mailboxes, after acceptance filter processing
If no mailbox is specified to receive the message, after acceptance filter processing.
When setting the RECREQ bit to 1, do not set the TRMREQ bit to 1. To change the configuration of a mailbox from
transmission to reception, first abort the transmission, then set the SENTDATA and TRMABT flags to 0 before changing
to reception.
Note:
MCTL_TXj.RECREQ is the mirror bit of MCTL_RXj.RECREQ.
TRMREQ bit (Transmit Mailbox Request)
When the TRMREQ bit is set to 1, the associated mailbox is configured for transmission of a data frame or remote frame.
When the TRMREQ bit is set to 0, the associated mailbox is not configured for transmission of a data frame or remote
frame.
If the TRMREQ bit is changed from 1 to 0 to cancel the associated transmission request, either the TRMABT or
SENTDATA flag is set to 1. When setting the TRMREQ bit to 1, do not set the RECREQ bit to 1. To change the
configuration of a mailbox from reception to transmission, first abort the reception, then set the NEWDATA and
MSGLOST bits to 0 before changing to transmission.
Note:
MCTL_TXj.TRMREQ is the mirror bit of MCTL_RXj.TRMREQ.
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27.2.10
27. Controller Area Network (CAN) Module
Message Control Register for Receive (MCTL_RXj) (j = 0 to 31)
Receive mode (when the TRMREQ bit is 0 and the RECREQ bit is 1)
Address(es): CAN0.MCTL_RX[0] 4005 0820h to CAN0.MCTL_RX[31] 4005 083Fh
b7
b6
TRMRE RECRE
Q
Q
Value after reset:
Bit
0
0
Symbol
b5
b4
b3
—
ONESH
OT
—
0
0
0
b2
b1
b0
MSGL INVALD NEWD
OST
ATA
ATA
0
Bit name
Flag*1,*2
0
0
Description
R/W
0: No data received, or 0 was written to the bit
1: New message being stored or was stored to the mailbox.
R/W
b0
NEWDATA
Reception Complete
b1
INVALDATA
Reception-in-Progress Status
Flag
0: Message valid
1: Message being updated.
R
b2
MSGLOST
Message Lost Flag*1,*2
0: Message not overwritten or overrun
1: Message overwritten or overrun.
R/W
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
ONESHOT
One-Shot Enable*2,*3
0: Disable one-shot reception
1: Enable one-shot reception.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
RECREQ
Receive Mailbox Request
*2,*3,*4,*5
0: Do not configure for reception
1: Configure for reception.
R/W
b7
TRMREQ
Transmit Mailbox Request
*2,*4
0: Do not configure for transmission
1: Configure for transmission.
R/W
Note 1. Write 0 only. Writing 1 has no effect.
Note 2. When writing to bits of this register, write 1 to the NEWDATA and MSGLOST bits if they are not the write target.
Note 3. To enter one-shot receive mode, write 1 to the ONESHOT bit at the same time as setting the RECREQ bit to 1.
To exit one-shot receive mode, write 0 to the ONESHOT bit after writing 0 to the RECREQ bit and confirming that
it is 0.
Note 4. Do not set both the RECREQ and TRMREQ bits to 1.
Note 5. When setting the RECREQ bit to 0, set the MSGLOST, NEWDATA, and RECREQ bits to 0 simultaneously.
The MCTL_RXj register sets mailbox j to transmit or receive mode. In receive mode, MCTL_RXj also controls and
indicates the status of reception. Do not access the MCTL_RXj register if mailbox j is in transmit mode. Only write to
MCTL_RXj in CAN operation mode or CAN halt mode. Do not use the MCTL_RX24 to MCTL_RX31 registers in
FIFO mailbox mode.
NEWDATA flag (Reception Complete Flag)
The NEWDATA flag is set to 1 when a new message is being stored or was stored in the mailbox. The timing for setting
NEWDATA to 1 is simultaneous with the INVALDATA flag. The NEWDATA flag is set to 0 through a software write.
The NEWDATA flag cannot be set to 0 through a software write when the associated INVALDATA flag is 1.
INVALDATA flag (Reception-in-Progress Status Flag)
After the completion of a message reception, the INVALDATA flag is set to 1 while the received message is being
updated in the associated mailbox. The INVALDATA flag is set to 0 immediately after the message is stored. If the
mailbox is read when the INVALDATA flag is 1, the data is undefined.
MSGLOST flag (Message Lost Flag)
The MSGLOST flag is set to 1 when the mailbox is overwritten or overrun by a new received message while the
NEWDATA flag is 1. The MSGLOST flag is set to 1 at the end of the 6th bit of EOF. The MSGLOST flag is set to 0
through a software write.
In both overwrite and overrun modes, the MSGLOST flag cannot be set to 0 through a software write during the 5
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27. Controller Area Network (CAN) Module
PCLKB cycles following the 6th bit of EOF.
ONESHOT bit (One-Shot Enable)
When the ONESHOT bit is set to 1 in receive mode (RECREQ = 1 and TRMREQ = 0), the mailbox receives a message
only one time. The mailbox does not behave as a receive mailbox after having received a message one time. The
behavior of the NEWDATA and INVALDATA flags is the same as in normal receive mode. In one-shot receive mode,
the MSGLOST flag is not set to 1. To set the ONESHOT bit to 0, first write 0 to the RECREQ bit and ensure that it is 0.
RECREQ bit (Receive Mailbox Request)
When the RECREQ bit is set to 1, the associated mailbox is configured for reception of a data frame or remote frame.
When the RECREQ bit is set to 0, the associated mailbox is not configured for reception of a data frame or remote frame.
Due to hardware protection, the RECREQ bit cannot be set to 0 through a software write during the following period:
Hardware protection is started from acceptance filter processing (the beginning of the CRC field)
Hardware protection is released:
For the mailbox that is specified to receive the incoming message, after the received data is stored in the mailbox
or a CAN bus error occurs. This means that the maximum period of hardware protection is from the beginning of
CRC field to the end of the 7th bit of EOF.
For the other mailboxes, after acceptance filter processing.
If no mailbox is specified to receive the message, after acceptance filter processing.
When setting the RECREQ bit to 1, do not set the TRMREQ bit to 1. To change the configuration of a mailbox from
transmission to reception, first abort the transmission, then set the SENTDATA and TRMABT flags to 0 before changing
to reception.
Note:
MCTL_RXj.RECREQ is the mirror bit of MCTL_TXj.RECREQ.
TRMREQ bit (Transmit Mailbox Request)
When the TRMREQ bit is set to 1, the associated mailbox is configured for transmission of a data frame or remote frame.
When the TRMREQ bit is set to 0, the associated mailbox is not configured for transmission of a data frame or remote
frame.
If the TRMREQ bit is changed from 1 to 0 to cancel the associated transmission request, either the TRMABT or
SENTDATA flag is set to 1. When setting the TRMREQ bit to 1, do not set the RECREQ bit to 1. To change the
configuration of a mailbox from reception to transmission, first abort the reception, then set the NEWDATA and
MSGLOST bits to 0 before changing to transmission.
Note:
MCTL_RXj.TRMREQ is the mirror bit of MCTL_TXj.TRMREQ.
27.2.11
Receive FIFO Control Register (RFCR)
Address(es): CAN0.RFCR 4005 0848h
b7
b6
b5
b4
b3
RFEST RFWST RFFST RFMLF
Value after reset:
1
0
0
0
b2
b1
RFUST[2:0]
0
0
b0
RFE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
RFE
Receive FIFO Enable
0: Disable receive FIFO
1: Enable receive FIFO.
R/W
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Bit
Symbol
Bit name
Description
R/W
b3 to b1
RFUST[2:0]
Receive FIFO Unread Message
Number Status
b3
R
b4
RFMLF
Receive FIFO Message Lost Flag
0: Receive FIFO message not lost
1: Receive FIFO message lost.
R/W
b5
RFFST
Receive FIFO Full Status Flag
0: Receive FIFO not full
1: Receive FIFO full (4 unread messages).
R
b6
RFWST
Receive FIFO Buffer Warning
Status Flag
0: Receive FIFO is not buffer warning
1: Receive FIFO is buffer warning (3 unread messages).
R
b7
RFEST
Receive FIFO Empty Status Flag
0: Unread message in receive FIFO
1: No unread message in receive FIFO.
R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b1
0: No unread message
1: 1 unread message
0: 2 unread messages
1: 3 unread messages
0: 4 unread messages
1: Reserved
0: Reserved
1: Reserved.
Write to the RFCR register in CAN operation mode or CAN halt mode.
RFE bit (Receive FIFO Enable)
When the RFE bit is set to 1, the receive FIFO is enabled.
When the RFE bit is set to 0, the receive FIFO is disabled for reception and becomes empty (RFEST bit = 1). Write 0 to
the RFE bit simultaneously with the RFMLF bit setting.
Do not set the RFE bit to 1 in normal mailbox mode (CTLR.MBM = 0).
Due to hardware protection, the RFE bit cannot be set to 0 through a software write during the following period:
Hardware protection is started from acceptance filter processing (the beginning of the CRC field)
Hardware protection is released:
If the receive FIFO is specified to receive the incoming message, after the received data is stored in the receive
FIFO or a CAN bus error occurs. This means that the maximum period of hardware protection is from the
beginning of CRC field to the end of the 7th bit of EOF.
If the receive FIFO is not specified to receive the message, after acceptance filter processing.
RFUST[2:0] bits (Receive FIFO Unread Message Number Status)
The RFUST[2:0] bits indicate the number of unread messages in the receive FIFO. The value of the RFUST[2:0] bits
initializes to 000b when the RFE bit is set to 0.
RFMLF flag (Receive FIFO Message Lost Flag)
The RFMLF flag is set to 1 (receive FIFO message was lost) when the receive FIFO receives a new message and is full.
It is set to 1 at the end of the 6th bit of EOF.
The RFMLF flag is set to 0 through a software write (writing 1 has no effect). In both overwrite and overrun modes, if
the receive FIFO is full and determined to have received a message, the RFMLF flag cannot be set to 0 (receive FIFO
message was not lost) through a software write during the 5 PCLKB cycles following the 6th bit of EOF due to hardware
protection.
RFFST flag (Receive FIFO Full Status Flag)
The RFFST flag is set to 1 (receive FIFO is full) when the number of unread messages in the receive FIFO is 4. The
RFFST flag is 0 (receive FIFO is not full) when the number of unread messages in the receive FIFO is less than 4. The
RFFST flag is set to 0 when the RFE bit is 0.
RFWST flag (Receive FIFO Buffer Warning Status Flag)
The RFWST flag is set to 1 (receive FIFO is buffer warning) when the number of unread messages in the receive FIFO is
3. The RFWST flag is 0 (receive FIFO is not buffer warning) when the number of unread messages in the receive FIFO
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27. Controller Area Network (CAN) Module
is less than 3 or equal to 4. The RFWST flag is set to 0 when the RFE bit is 0.
RFEST flag (Receive FIFO Empty Status Flag)
The RFEST flag is set to 1 (no unread message in receive FIFO) when the number of unread messages in the receive
FIFO is 0. The RFEST flag is set to 1 when the RFE bit is set to 0. The RFEST flag is set to 0 (unread message in receive
FIFO) when the number of unread messages in the receive FIFO is one or more. Figure 27.2 shows the receive FIFO
mailbox operation.
Receive FIFO mailbox
Frame 1
Frame 2
Frame 3
Frame 4
CAN bus
Frame 1
Frame 2 Frame 3
Frame 4
Frame 1
Internal bus
Frame 2
Frame 3
Frame 4
RFCR.RFEST flag
RFCR.RFWST flag
RFCR.RFFST bit
CAN0 receive FIFO interrupt
Bits 29 and 28 in MIER_FIFO = 01b
CAN0 receive FIFO interrupt
Bits 29 and 28 in MIER_FIFO = 11b
RFPCR
Figure 27.2
27.2.12
Receive FIFO mailbox operation, when bits [29] and [28] in MIER_FIFO = 01b or 11b
Receive FIFO Pointer Control Register (RFPCR)
Address(es): CAN0.RFPCR 4005 0849h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b7 to b0
The CPU pointer for the receive FIFO is incremented by writing FFh to RFPCR
W
When the receive FIFO is not empty, write FFh to the RFPCR register through software to increment the CPU pointer to
the next mailbox location. Do not write to RFPCR when the RFCR.RFE bit is 0 (receive FIFO disabled).
Both the CAN and CPU pointers increment when a new message is received and the RFFST bit is 1 (receive FIFO is full)
in overwrite mode. When the RFMLF bit is 1 in this state, the CPU pointer does not increment on a software write to the
RFPCR register.
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27.2.13
27. Controller Area Network (CAN) Module
Transmit FIFO Control Register (TFCR)
Address(es): CAN0.TFCR 4005 084Ah
b7
b6
TFEST TFFST
Value after reset:
1
0
b5
b4
—
—
0
0
b3
b2
b1
b0
TFUST[2:0]
0
0
TFE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TFE
Transmit FIFO Enable
0: Disable transmit FIFO
1: Enable transmit FIFO.
R/W
b3 to b1
TFUST[2:0]
Transmit FIFO Unsent Message
Number Status
b3
R
b5, b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
TFFST
Transmit FIFO Full Status
0: Transmit FIFO not full
1: Transmit FIFO full (4 unsent messages).
R
b7
TFEST
Transmit FIFO Empty Status
0: Unsent message in transmit FIFO
1: No unsent message in transmit FIFO.
R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b1
0: 0 unsent messages
1: 1 unsent message
0: 2 unsent messages
1: 3 unsent messages
0: 4 unsent messages
1: Reserved
0: Reserved
1: Reserved.
Write to the TFCR register in CAN operation mode or CAN halt mode.
TFE bit (Transmit FIFO Enable)
Setting the TFE bit to 1 enables the transmit FIFO. Setting the TFE bit to 0 empties the transmit FIFO (TFEST bit = 1),
and unsent messages in the transmit FIFO are lost in the following ways:
Immediately if a message from the transmit FIFO is not scheduled for the next transmission or already in
transmission
On completion of transmission, a CAN bus error, CAN bus arbitration-lost, or entry to CAN halt mode, if a message
from the transmit FIFO is scheduled for the next transmission or already in transmission.
Before setting the TFE bit to 1 again, ensure that the TFEST bit is set to 1. After setting the TFE bit to 1, write transmit
data to mailbox 24.
Do not set the TFE bit to 1 in normal mailbox mode (CTLR.MBM bit = 0).
TFUST[2:0] bits (Transmit FIFO Unsent Message Number Status)
The TFUST[2:0] bits indicate the number of unsent messages in the transmit FIFO. The TFUST[2:0] bits are set to 000b
after the TFE bit is set to 0 and transmission aborts or completes.
TFFST bit (Transmit FIFO Full Status)
The TFFST bit is set to 1 (transmit FIFO is full) when the number of unsent messages in the transmit FIFO is 4. The
TFFST bit is set to 0 (transmit FIFO is not full) when the number of unsent messages in the transmit FIFO is less than 4.
The TFFST bit is set to 0 when transmission from the transmit FIFO is aborted.
TFEST bit (Transmit FIFO Empty Status)
The TFEST bit is set to 1 (no message in transmit FIFO) when the number of unsent messages in the transmit FIFO is 0.
The TFEST bit is set to 1 when transmission from the transmit FIFO is aborted. The TFEST bit is set to 0 (message in
transmit FIFO) when the number of unsent messages in the transmit FIFO is not 0.
Figure 27.3 shows the transmit FIFO mailbox operation.
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27. Controller Area Network (CAN) Module
Transmit FIFO mailbox
Frame 1
Frame 2
Frame 3
Frame 4
CAN bus
Frame 1
Frame 1
Internal bus
Frame 2 Frame 3
Frame 4
Frame 2 Frame 3 Frame 4
TFCR.TFEST flag
TFCR.TFFST bit
CAN0 transmit FIFO interrupt
Bits 25 and 24 in MIER_FIFO = 01b
CAN0 transmit FIFO interrupt
Bits 25 and 24 in MIER_FIFO = 11b
TFPCR
Figure 27.3
27.2.14
Transmit FIFO mailbox operation when bits [25] and [24] in MIER_FIFO = 01b or 11b
Transmit FIFO Pointer Control Register (TFPCR)
Address(es): CAN0.TFPCR 4005 084Bh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b7 to b0
The CPU pointer for the transmit FIFO is incremented by writing FFh to TFPCR
W
When the transmit FIFO is not full, write FFh to the TFPCR register through software to increment the CPU pointer for
the transmit FIFO to the next mailbox location.
Do not write to the TFPCR register when the TFCR.TFE bit is 0 (transmit FIFO disabled).
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27.2.15
27. Controller Area Network (CAN) Module
Status Register (STR)
Address(es): CAN0.STR 4005 0842h
b15
—
Value after reset:
0
b14
b13
b12
RECST TRMST BOST
0
0
b11
b10
b9
b8
EPST SLPST HLTST RSTST
0
0
1
0
1
b7
EST
b6
b5
b4
b3
TABST FMLST NMLST TFST
0
0
0
0
0
b2
b1
b0
RFST
SDST
NDST
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
NDST
NEWDATA Status Flag
0: No mailbox with NEWDATA bit = 1
1: 1 or more mailboxes with NEWDATA bit = 1.
R
b1
SDST
SENTDATA Status Flag
0: No mailbox with SENTDATA bit = 1
1: 1 or more mailboxes with SENTDATA bit = 1.
R
b2
RFST
Receive FIFO Status Flag
0: Receive FIFO empty
1: Message in receive FIFO.
R
b3
TFST
Transmit FIFO Status Flag
0: Transmit FIFO full
1: Transmit FIFO not full.
R
b4
NMLST
Normal Mailbox Message Lost
Status Flag
0: No mailbox with MSGLOST bit = 1
1: 1 or more mailboxes with MSGLOST bit = 1.
R
b5
FMLST
FIFO Mailbox Message Lost Status
Flag
0: RFMLF bit = 0
1: RFMLF bit = 1.
R
b6
TABST
Transmission Abort Status Flag
0: No mailbox with TRMABT bit = 1
1: 1 or more mailboxes with TRMABT bit = 1.
R
b7
EST
Error Status Flag
0: No error occurred
1: Error occurred.
R
b8
RSTST
CAN Reset Status Flag
0: Not in CAN reset mode
1: In CAN reset mode.
R
b9
HLTST
CAN Halt Status Flag
0: Not in CAN halt mode
1: In CAN halt mode.
R
b10
SLPST
CAN Sleep Status Flag
0: Not in CAN sleep mode
1: In CAN sleep mode.
R
b11
EPST
Error-Passive Status Flag
0: Not in error-passive state
1: In error-passive state.
R
b12
BOST
Bus-Off Status Flag
0: Not in bus-off state
1: In bus-off state.
R
b13
TRMST
Transmit Status Flag
0: Bus idle or reception in progress
1: Transmission in progress or module in bus-off state.
R
b14
RECST
Receive Status Flag
0: Bus idle or transmission in progress
1: Reception in progress.
R
b15
—
Reserved
This bit is read as 0.
R
NDST flag (NEWDATA Status Flag)
The NDST flag is set to 1 when at least one NEWDATA bit in MCTL_RXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. The NDST flag is set to 0 when all NEWDATA bits are 0.
SDST flag (SENTDATA Status Flag)
The SDST flag is set to 1 when at least one SENTDATA bit in MCTL_TXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. The SDST flag is set to 0 when all SENTDATA bits are 0.
RFST flag (Receive FIFO Status Flag)
The RFST flag is set to 1 when the receive FIFO is not empty. The RFST flag is set to 0 when the receive FIFO is empty
or normal mailbox mode is selected.
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TFST flag (Transmit FIFO Status Flag)
The TFST flag is set to 1 when the transmit FIFO is not full. The TFST flag is set to 0 when the transmit FIFO is full or
normal mailbox mode is selected.
NMLST flag (Normal Mailbox Message Lost Status Flag)
The NMLST flag is set to 1 when at least one MSGLOST bit in MCTL_RXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. The NMLST flag is set to 0 when all MSGLOST bits are 0.
FMLST flag (FIFO Mailbox Message Lost Status Flag)
The FMLST flag is set to 1 when the RFMLF bit in the RFCR register is 1, regardless of the value of MIER_FIFO. The
FMLST flag is set to 0 when the RFMLF bit is 0.
TABST flag (Transmission Abort Status Flag)
The TABST flag is set to 1 when at least one TRMABT bit in MCTL_TXj (j = 0 to 31) is 1, regardless of the value of
MIER or MIER_FIFO. The TABST flag is set to 0 when all TRMABT bits are 0.
EST flag (Error Status Flag)
The EST flag is set to 1 when at least one error is detected by the EIFR register, regardless of the value of EIER. The EST
flag is set to 0 when no error is detected by the EIFR register.
RSTST flag (CAN Reset Status Flag)
The RSTST flag is set to 1 when the CAN module is in CAN reset mode. The RSTST flag is set to 0 when the CAN
module is not in CAN reset mode. When the CAN module transitions from CAN reset mode to CAN sleep mode, the
RSTST flag remains 1.
HLTST flag (CAN Halt Status Flag)
The HLTST flag is set to 1 when the CAN module is in CAN halt mode. The HLTST flag is set to 0 when the CAN
module is not in CAN halt mode. When the CAN module transitions from CAN halt mode to CAN sleep mode, the
HLTST flag remains 1.
SLPST flag (CAN Sleep Status Flag)
The SLPST flag is set to 1 when the CAN module is in CAN sleep mode. The SLPST flag is set to 0 when the CAN
module is not in CAN sleep mode.
EPST flag (Error-Passive Status Flag)
The EPST flag is set to 1 when the value of the TECR or RECR register exceeds 127 and the CAN module is in the errorpassive state (128 ≤ TEC < 256 or 128 ≤ REC < 256). The EPST flag is set to 0 when the CAN module is not in the errorpassive state.
BOST flag (Bus-Off Status Flag)
The BOST flag is set to 1 when the value of the TECR register exceeds 255 and the CAN module is in the bus-off state
(TEC ≥ 256). The BOST flag is set to 0 when the CAN module is not in the bus-off state.
TRMST flag (Transmit Status Flag)
The TRMST flag is set to 1 when the CAN module performs as a transmitter node or is in the bus-off state. The TRMST
flag is set to 0 when the CAN module performs as a receiver node or is in the bus-idle state.
RECST flag (Receive Status Flag)
The RECST flag is set to 1 when the CAN module performs as a receiver node. The RECST flag is set to 0 when the
CAN module performs as a transmitter node or is in the bus-idle state.
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27.2.16
27. Controller Area Network (CAN) Module
Mailbox Search Mode Register (MSMR)
Address(es): CAN0.MSMR 4005 0853h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
MBSM[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
MBSM[1:0]
Mailbox Search Mode Select
b1 b0
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: Receive mailbox search mode
1: Transmit mailbox search mode
0: Message lost search mode
1: Channel search mode.
Write to the MSMR register in CAN operation mode or CAN halt mode.
MBSM[1:0] bits (Mailbox Search Mode Select)
The MBSM[1:0] bits select the search mode for the mailbox search function.
When the MBSM[1:0] bits are 00b, receive mailbox search mode is selected. In receive mailbox search mode, the search
targets are the NEWDATA bit in MCTL_RXj (j = 0 to 31) for the normal mailbox and the RFCR.RFEST bit for the
receive FIFO.
When the MBSM[1:0] bits are 01b, transmit mailbox search mode is selected. In transmit mailbox search mode, the
search target is the SENTDATA bit in MCTL_TXj.
When the MBSM[1:0] bits are 10b, message lost search mode is selected. In message lost search mode, the search targets
are the MSGLOST bit in MCTL_RXj for the normal mailbox and the RFCR.RFMLF bit for the receive FIFO.
When the MBSM[1:0] bits are 11b, channel search mode is selected. In channel search mode, the search target is the
CSSR register. See section 27.2.18, Channel Search Support Register (CSSR).
27.2.17
Mailbox Search Status Register (MSSR)
Address(es): CAN0.MSSR 4005 0852h
Value after reset:
b7
b6
b5
SEST
—
—
1
0
0
b4
b3
b2
b1
b0
0
0
MBNST[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
MBNST[4:0]
Search Result Mailbox
Number Status
These bits output the smallest mailbox number that is found in each
search mode selected in the MSMR register.
R
b6, b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
SEST
Search Result Status
0: Search result found
1: No search result.
R
MBNST[4:0] bits (Search Result Mailbox Number Status)
In all MSMR modes, the MBNST[4:0] bits output the smallest found mailbox number. In receive mailbox search mode,
transmit mailbox search mode, and message lost search mode, the value of the mailbox (search result to be output) is
updated under the following conditions:
When the NEWDATA, SENTDATA, or MSGLOST bit is set to 0 for a mailbox output by MBNST
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27. Controller Area Network (CAN) Module
When the NEWDATA, SENTDATA, or MSGLOST bit is set to 1 for a mailbox with a smaller number than that in
MBNST.
If the MBSM[1:0] bits are set to 00b (receive mailbox search mode) or 10b (message lost search mode), the receive FIFO
(mailbox 28) is output when it is not empty and there are no unread received messages and no lost messages in any of the
normal mailboxes (0 to 23). If the MBSM[1:0] bits are set to 01b (transmit mailbox search mode), the transmit FIFO
(mailbox 24) is not output. Table 27.6 lists the behavior of the MBNST[4:0] bits in FIFO mailbox mode.
In channel search mode, the MBNST[4:0] bits output the associated channel number. After the MSSR register is read by
software, the next target channel number is output.
SEST bit (Search Result Status)
The SEST bit is set to 1 (no search result) when no associated mailbox is found after searching all mailboxes. For
example, in transmit mailbox search mode, the SEST bit is set to 1 when no SENTDATA bit for any mailbox is 1. The
SEST bit is set to 0 when at least one SENTDATA bit is 1. When the SEST bit is 1, the value of the MBNST[4:0] bits is
undefined.
Table 27.6
Behavior of MBNST[4:0] bits in FIFO mailbox mode
MBSM[1:0] bits
Mailbox 24 (transmit FIFO)
Mailbox 28 (receive FIFO)
00b
Mailbox 24 is not output.
Mailbox 28 is output when no MCTL_RXj.NEWDATA bit for the normal mailboxes
is set to 1 (new message is being stored or was stored to the mailbox) and the
receive FIFO is not empty
01b
Mailbox 28 is not output
10b
Mailbox 28 is output when no MCTL_RXj.MSGLOST bit for the normal mailboxes
is set to 1 (message is overwritten or overrun) and the RFCR.RFMLF bit is set to
1 (receive FIFO message was lost) in the receive FIFO
11b
Mailbox 28 is not output
27.2.18
Channel Search Support Register (CSSR)
Address(es): CAN0.CSSR 4005 0851h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b7 to b0
When the value for the channel search is input, the channel number is output to the MSSR register
R/W
The bits that are set to 1 in the CSSR register are encoded by an 8/3 encoder (the LSB position has the higher priority)
and output to the MBNST[4:0] bits in the MSSR register. The MSSR register outputs the updated value whenever the
MSSR register is read by the software.
Write to the CSSR register only when the MSMR.MBSM[1:0] bits are 11b (channel search mode). Write to the CSSR
register in CAN operation mode or CAN halt mode.
Figure 27.4 shows writes to and reads from the CSSR and MSSR registers.
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27. Controller Area Network (CAN) Module
Address
CSSR
b7
b6
0
1
b3
0
0
1
0
b0
CAN0
1
4005 0851h
0
8/3 encoder
CAN0
MSSR
b7
b2
4005 0852h
b0
(1st read)
0
0
0
0
0
0
0
0
(Search result: Channel no. 0 read)
(2nd read)
0
0
0
0
0
0
1
1
(Search result: Channel no. 3 read)
(3rd read)
0
0
0
0
0
1
1
0
(Search result: Channel no. 6 read)
(4th read)
1
0
0
Figure 27.4
(Search result: No corresponding channel no .)
Writes to and reads from the CSSR and MSSR registers
The value of the CSSR register is also updated whenever the MSSR register is read. On this read, the value prior to
conversion by the 8/3 encoder can be read.
27.2.19
Acceptance Filter Support Register (AFSR)
Address(es): CAN0.AFSR 4005 0856h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x: Undefined
Bit
Description
R/W
b15 to b0
After the standard ID of a received message is written, the value converted for data table search can be read
R/W
Note:
Write to the AFSR register in CAN operation mode or CAN halt mode.
The acceptance filter support unit (ASU) can be used for data table (8 bits × 256) searches. In the data table, all standard
IDs that you create are set to be valid or invalid in bit units. When AFSR is written to with data in 16-bit units including
the SID[10:0] bits in MBj_ID (j = 0 to 31), in which a received standard ID is stored, a decoded row (byte offset) position
and column (bit) position for data table search can be read. The ASU can be used for standard (11-bit) IDs only.
The ASU is enabled in the following cases:
When the ID to be received cannot be masked by the acceptance filter. For example, if the IDs to be received are
078h, 087h, and 111h.
When there are too many IDs to receive, and the software filtering time is expected to be shortened.
Note:
The AFSR register cannot be set in CAN reset mode.
Figure 27.5 shows writes to and reads from the AFSR register.
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27. Controller Area Network (CAN) Module
Address
b15
b8
b7
b0
SID SID SID SID SID SID SID SID SID SID SID
10
9
8
7
6
5
4
3
2
1
0
When writing*1
CAN0
4005 0856h
3/8 decoder
b15
b8
b7
b0
SID SID SID SID SID SID SID SID
10
9
8
7
6
5
4
3
When reading
Column (bit) position in data table
CAN0
4005 0856h
Row (byte offset) position in data table
Note 1. Write the same value as the 16-bit unit data, including the SID[10:0] bits in MBj_ID (j = 0 to 31).
Figure 27.5
27.2.20
Writes to and reads from the AFSR register
Error Interrupt Enable Register (EIER)
Address(es): CAN0.EIER 4005 084Ch
Value after reset:
b7
b6
b5
BLIE
OLIE
ORIE
0
0
0
b4
b3
BORIE BOEIE
0
b2
b1
b0
EPIE
EWIE
BEIE
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BEIE
Bus Error Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b1
EWIE
Error-Warning Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b2
EPIE
Error-Passive Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b3
BOEIE
Bus-Off Entry Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b4
BORIE
Bus-Off Recovery Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b5
ORIE
Overrun Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b6
OLIE
Overload Frame Transmit Interrupt
Enable
0: Disable interrupt
1: Enable interrupt.
R/W
b7
BLIE
Bus Lock Interrupt Enable
0: Disable interrupt
1: Enable interrupt.
R/W
The EIER register enables or disables each error interrupt source independently in the EIFR register. Write to the EIER
register in CAN reset mode.
BEIE bit (Bus Error Interrupt Enable)
When the BEIE bit is 0, no error interrupt request occurs even if the EIFR.BEIF bit is 1. When the BEIE bit is 1, an error
interrupt request occurs if the EIFR.BEIF bit is set to 1.
EWIE bit (Error-Warning Interrupt Enable)
When the EWIE bit is 0, no error interrupt request occurs even if the EIFR.EWIF bit is 1. When the EWIE bit is 1, an
error interrupt request occurs if the EIFR.EWIF bit is set to 1.
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27. Controller Area Network (CAN) Module
EPIE bit (Error-Passive Interrupt Enable)
When the EPIE bit is 0, no error interrupt request occurs even if the EIFR.EPIF bit is 1. When the EPIE bit is 1, an error
interrupt request occurs if the EIFR.EPIF bit is set to 1.
BOEIE bit (Bus-Off Entry Interrupt Enable)
When the BOEIE bit is 0, no error interrupt request occurs even if the EIFR.BOEIF bit is 1. When the BOEIE bit is 1, an
error interrupt request occurs if the EIFR.BOEIF bit is set to 1.
BORIE bit (Bus-Off Recovery Interrupt Enable)
When the BORIE bit is 0, an error interrupt request does not occur even if the EIFR.BORIF bit is 1. When the BORIE bit
is set to 1, an error interrupt request occurs if the EIFR.BORIF bit is set to 1.
ORIE bit (Overrun Interrupt Enable)
When the ORIE bit is 0, an error interrupt request does not occur even if the EIFR.ORIF bit is 1. When the ORIE bit is 1,
an error interrupt request occurs if the EIFR.ORIF bit is set to 1.
OLIE bit (Overload Frame Transmit Interrupt Enable)
When the OLIE bit is 0, no error interrupt request occurs even if the EIFR.OLIF bit is 1. When the OLIE bit is 1, an error
interrupt request occurs if the EIFR.OLIF bit is set to 1.
BLIE bit (Bus Lock Interrupt Enable)
When the BLIE bit is 0, no error interrupt request occurs even if the EIFR.BLIF bit is 1. When the BLIE bit is 1, an error
interrupt request occurs if the EIFR.BLIF bit is set to 1.
27.2.21
Error Interrupt Factor Judge Register (EIFR)
Address(es): CAN0.EIFR 4005 084Dh
Value after reset:
b7
b6
b5
BLIF
OLIF
ORIF
0
0
0
b4
b3
BORIF BOEIF
0
b2
b1
b0
EPIF
EWIF
BEIF
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
BEIF
Bus Error Detect Flag
0: No bus error detected
1: Bus error detected.
R/W
b1
EWIF
Error-Warning Detect Flag
0: No error-warning detected
1: Error-warning detected.
R/W
b2
EPIF
Error-Passive Detect Flag
0: No error-passive detected
1: Error-passive detected.
R/W
b3
BOEIF
Bus-Off Entry Detect Flag
0: No bus-off entry detected
1: Bus-off entry detected.
R/W
b4
BORIF
Bus-Off Recovery Detect Flag
0: No bus-off recovery detected
1: Bus-off recovery detected.
R/W
b5
ORIF
Receive Overrun Detect Flag
0: No receive overrun detected
1: Receive overrun detected.
R/W
b6
OLIF
Overload Frame Transmission
Detect Flag
0: No overload frame transmission detected
1: Overload frame transmission detected.
R/W
b7
BLIF
Bus Lock Detect Flag
0: No bus lock detected
1: Bus lock detected.
R/W
If an event associated with one of these bit occurs, the associated bit in the EIFR register is set to 1, regardless of the
EIER setting.
Clear the bits to 0 through a software write. If a bit is set to 1 at the same time that the software clears it, it becomes 1.
When setting a single bit to 0 in software, use the transfer instruction (MOV) to ensure that only the specified bit is set to
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27. Controller Area Network (CAN) Module
0 and the other bits are set to 1. Writing 1 has no effect on these bit values.
BEIF flag (Bus Error Detect Flag)
The BEIF flag is set to 1 when a bus error is detected.
EWIF flag (Error-Warning Detect Flag)
The EWIF flag is set to 1 when the value of the receive error counter (REC) or transmit error counter (TEC) exceeds 95.
It is set to 1 only when REC or TEC initially exceeds 95. If 0 is written to the EWIF bit by software while REC or TEC
remains greater than 95, the EWIF flag is set to 1 until REC or TEC goes below 95 then exceeds 95 again.
EPIF flag (Error-Passive Detect Flag)
The EPIF flag is set to 1 when the CAN error state becomes error-passive, when the receive error counter (REC) or
transmit error counter (TEC) exceeds 127. The EPIF flag is set to 1 only when REC or TEC initially exceeds 127. If 0 is
written to the EPIF flag by the software while REC or TEC remains greater than 127, the EPIF flag is not set to 1 until
REC or TEC goes below 127 then exceeds 127 again.
BOEIF flag (Bus-Off Entry Detect Flag)
The BOEIF flag is set to 1 when the CAN error state becomes bus-off, when the transmit error counter (TEC) value
exceeds 255. The BOEIF flag is also set to 1 when the CTLR.BOM[1:0] bits are 01b (automatic entry to CAN halt mode
on bus-off entry) and the CAN module enters the bus-off state.
BORIF flag (Bus-Off Recovery Detect Flag)
The BORIF flag is set to 1 when the CAN module recovers from the bus-off state normally by detecting 11 consecutive
recessive bits 128 times in the following conditions:
When the CTLR.BOM[1:0] bits are 00b
When the CTLR.BOM[1:0] bits are 10b
When the CTLR.BOM[1:0] bits are11b.
However, the BORIF flag is not set to 1 if the CAN module recovers from the bus-off state in the following conditions:
When the CTLR.CANM[1:0] bits are set to 01b or 11b (CAN reset mode)
When the CTLR.RBOC bit is set to 1 (forced return from bus-off)
When the CTLR.BOM[1:0] bits are set to 01b
When the CTLR.BOM[1:0] bits are set to 11b and the CTLR.CANM[1:0] bits are set to 10b (CAN halt mode)
before normal recovery occurs.
Table 27.7 lists the behavior of the BOEIF and BORIF bits for each CTLR.BOM[1:0] setting.
Table 27.7
Behavior of BOEIF and BORIF flags for each CTLR.BOM[1:0] setting
BOM[1:0] bits
BOEIF flag
BORIF flag
00b
Set to 1 on entry to bus-off state.
Sets to 1 on exit from bus-off state
01b
Is not set to 1
10b
Sets to 1 on exit from the bus-off state
11b
Sets to 1 if normal bus-off recovery occurs before the CANM[1:0] bits
are set to 10b (CAN halt mode)
ORIF flag (Receive Overrun Detect Flag)
The ORIF flag is set to 1 when a receive overrun occurs. It is not set to 1 in overwrite mode.
In overwrite mode, a reception complete interrupt request occurs if an overwrite condition occurs and the ORIF bit is not
set to 1.
In overrun mode with normal mailbox mode, if an overrun occurs in any of mailboxes 0 to 31, the ORIF flag is set to 1.
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27. Controller Area Network (CAN) Module
In overrun mode with FIFO mailbox mode, if an overrun occurs in any of mailboxes 0 to 23 or the receive FIFO, the
ORIF flag is set to 1.
OLIF flag (Overload Frame Transmission Detect Flag)
The OLIF flag is set to 1 if the transmitting condition of an overload frame is detected when the CAN module is
transmitting or receiving.
BLIF flag (Bus Lock Detect Flag)
The BLIF flag is set to 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN
operation mode. After the BLIF flag is set to 1, 32 consecutive dominant bits are detected again in either of the following
conditions:
Recessive bits are detected after this flag changes to 0 from 1.
The CAN module enters CAN reset mode or CAN halt mode and then enters CAN operation mode again after this
flag changes to 0 from 1.
27.2.22
Receive Error Count Register (RECR)
Address(es): CAN0.RECR 4005 084Eh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
Bit
Description
b7 to b0
Receive error count function
R
RECR increments or decrements the counter value based on the error status of the CAN module during reception.
R/W
The RECR register indicates the value of the receive error counter. See the CAN specification (ISO11898-1) for
information about the increment and decrement conditions of the receive error counter.
The value of the RECR register in the bus-off state is undefined.
27.2.23
Transmit Error Count Register (TECR)
Address(es): CAN0.TECR 4005 084Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
Bit
Description
R/W
b7 to b0
Transmit error count function
TECR increments or decrements the counter value based on the error status of the CAN module during
transmission.
R
The TECR register indicates the value of the transmit error counter. See the CAN specification (ISO11898-1) for
information about the increment and decrement conditions of the transmit error counter.
The value of the TECR register in the bus-off state is undefined.
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27.2.24
27. Controller Area Network (CAN) Module
Error Code Store Register (ECSR)
Address(es): CAN0.ECSR 4005 0850h
b7
b6
b5
b4
b3
b2
b1
b0
EDPM
ADEF
BE0F
BE1F
CEF
AEF
FEF
SEF
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Flag*1,*2
Description
R/W
0: No stuff error detected
1: Stuff error detected.
R/W
b0
SEF
Stuff Error
b1
FEF
Form Error Flag*1,*2
0: No form error detected
1: Form error detected.
R/W
b2
AEF
ACK Error Flag*1,*2
0: No ACK error detected
1: ACK error detected.
R/W
b3
CEF
CRC Error Flag*1,*2
0: No CRC error detected
1: CRC error detected.
R/W
b4
BE1F
Bit Error (recessive) Flag*1,*2
0: No bit error (recessive) detected
1: Bit error (recessive) detected.
R/W
b5
BE0F
Bit Error (dominant) Flag*1,*2
0: No bit error (dominant) detected
1: Bit error (dominant) detected.
R/W
b6
ADEF
ACK Delimiter Error Flag*1,*2
0: No ACK delimiter error detected
1: ACK delimiter error detected.
R/W
b7
EDPM
Error Display Mode Select*3,*4
0: Output first detected error code
1: Output accumulated error code.
R/W
Note 1. Writing 1 has no effect on these bit values.
Note 2. To write 0 to the SEF, FEF, AEF, CEF, BE1F, BE0F, and ADEF bits, use the transfer (MOV) instruction to ensure
that only the specified bit is set to 0 and the other bits are set to 1.
Note 3. Write to the EDPM bit in CAN reset mode or CAN halt mode.
Note 4. If more than one error condition is detected simultaneously, all related bits are set to 1.
The ECSR register indicates whether an error occurs on the CAN bus. See the CAN specification (ISO11898-1) for the
conditions when each error occurs.
Clear all of the bits, except for EDPM, to 0 through a software write. If a bit is set to 1 at the same time that software
clears it, the bit becomes 1.
SEF flag (Stuff Error Flag)
The SEF flag is set to 1 when a stuff error is detected.
FEF flag (Form Error Flag)
The FEF flag is set to 1 when a form error is detected.
AEF flag (ACK Error Flag)
The AEF flag is set to 1 when an ACK error is detected.
CEF flag (CRC Error Flag)
The CEF flag is set to 1 when a CRC error is detected.
BE1F flag (Bit Error (recessive) Flag)
The BE1F flag is set to 1 when a recessive bit error is detected.
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27. Controller Area Network (CAN) Module
BE0F flag (Bit Error (dominant) Flag)
The BE0F flag is set to 1 when a dominant bit error is detected.
ADEF flag (ACK Delimiter Error Flag)
The ADEF flag is set to 1 when a form error is detected with the ACK delimiter during transmission.
EDPM bit (Error Display Mode Select)
The EDPM bit selects the output mode of the ECSR register. When the EDPM bit is set to 0, the ECSR register outputs
the first error code. When the EDPM bit is set to 1, the ECSR register outputs the accumulated error code.
27.2.25
Time Stamp Register (TSR)
Address(es): CAN0.TSR 4005 0854h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Description
R/W
b15 to b0
Free-running counter value for the time stamp function
R
Note:
Read the TSR register in 16-bit units.
When the TSR register is read, the value of the time stamp counter (16-bit free-running counter) at that moment is read.
The time stamp counter reference clock is configured in the TSPS[1:0] bits in the CTLR register. The counter stops in
CAN sleep mode and CAN halt mode, and is initialized in CAN reset mode. The TSR register value is stored to bits
TSL[7:0] and TSH[7:0] in the MBj_TS register when a received message is stored in a receive mailbox.
27.2.26
Test Control Register (TCR)
Address(es): CAN0.TCR 4005 0858h
Value after reset:
b7
b6
b5
b4
b3
b2
b1
—
—
—
—
—
TSTM[1:0]
0
0
0
0
0
0
b0
TSTE
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TSTE
CAN Test Mode Enable
0: Disable CAN test mode
1: Enable CAN test mode.
R/W
b2, b1
TSTM[1:0]
CAN Test Mode Select
b2 b1
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: Not CAN test mode
1: Listen-only mode
0: Self-test mode 0 (external loopback)
1: Self-test mode 1 (internal loopback).
The TCR register controls the CAN test mode. Write to the TCR register in CAN halt mode only.
(1)
Listen-only mode
The CAN specification (ISO11898-1) recommends an optional bus monitoring mode. In listen-only mode, valid data
frames and valid remote frames can be received. However, only recessive bits can be sent on the CAN bus. The ACK bit,
overload flag, and active error flag cannot be sent.
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27. Controller Area Network (CAN) Module
Listen-only mode can be used for baud rate detection. Do not request transmission from any mailboxes in listen-only
mode.
Figure 27.6 shows the connection when listen-only mode is selected.
CTX0
CRX0
Recessive level
CTX0
(internal)
Figure 27.6
(2)
CRX0
(internal)
Connection when listen-only mode is selected
Self-test mode 0 (external loopback)
Self-test mode 0 is provided for CAN transceiver tests. In this mode, the protocol module treats its own transmitted
messages as those received by the CAN transceiver and stores them into the receive mailbox. To be independent from
external stimulation, the protocol controller generates the ACK bit.
Connect the CTX0 and CRX0 pins to the transceiver.
Figure 27.7 shows the connection when self-test mode 0 is selected.
CAN transceiver
CTX0
CRX0
ACK
CTX0
(internal)
Figure 27.7
(3)
CRX0
(internal)
Connection when self-test mode 0 is selected
Self-test mode 1 (internal loopback)
Self-test mode 1 is provided for self-test functions.
In self-test mode 1, the protocol controller treats its transmitted messages as received messages and stores them into the
receive mailbox. To be independent from external stimulation, the protocol controller generates the ACK bit.
In self-test mode 1, the protocol controller performs internal loopback from the internal CTX0 pin to the internal CRX0
pin. The input value of the external CRX0 pin is ignored. The external CTX0 pin outputs only recessive bits. The CTX0
and CRX0 pins are not required to be connected to the CAN bus or any external device.
Figure 27.8 shows the connection when self-test mode 1 is selected.
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27. Controller Area Network (CAN) Module
CTX0
CRX0
Recessive level
ACK
CTX0
(internal)
Figure 27.8
27.3
CRX0
(internal)
Connection when self-test mode 1 is selected
Operation Modes
The CAN module operation modes include:
CAN reset mode
CAN halt mode
CAN operation mode
CAN sleep mode.
Figure 27.9 shows the transitions between the operation modes.
CPU reset
CANM[1:0] = 01b or 11b
when SLPM = 0
CAN sleep mode*2
CANM[1:0] = 00b
CAN reset mode
CANM[1:0]
= 00b
CANM[1:0] = 10b
when SLPM = 0
SLPM = 1
CAN operation mode
CANM[1:0]
= 01b, 11b
SLPM = 1
CANM[1:0]
= 10b
CANM[1:0]
= 01b, 11b
CAN halt mode
TEC > 255
CANM[1:0] = 10b
CANM[1:0]
= 01b, 11b
When BOM[1:0] = 00b or 11b
(no halt request) and 11
consecutive recessive bits are
detected 128 times or RBOC = 1
CAN operation mode
(bus-off state)
CANM[1:0] = 10b*1
CANM, SLPM, BOM, RBOC: Bits in CTLR
Note 1. The transition timing from the bus-off state to CAN halt mode depends on the setting of the CTLR.BOM[1:0] bits.
When the CTLR.BOM[1:0] bits are 01b, the state transition occurs immediately after entering the bus-off state.
When the CTLR.BOM[1:0] bits are 10b, the state transition occurs at the end of the bus -off state.
When the CTLR.BOM[1:0] bits are 11b, the state transition occurs on setting of the CTLR.CANM[1:0] bits to 10b (CAN halt
mode).
Note 2. Change the CTLR.SLPM bit to set or cancel CAN sleep mode.
Figure 27.9
27.3.1
Transition between different modes of operation
CAN Reset Mode
CAN reset mode is provided for CAN communication configuration. When the CTLR.CANM[1:0] bits are set to 01b or
11b, the CAN module enters CAN reset mode. The STR.RSTST bit is then set to 1. Do not change the
CTLR.CANM[1:0] bits until the RSTST bit is 1. Set the BCR register before exiting CAN reset mode to any other mode.
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27. Controller Area Network (CAN) Module
The following registers are initialized to their reset values after entering CAN reset mode, and their initial values are
retained during CAN reset mode:
MCTL_TXj and MCTL_RXj
STR (except for the SLPST and TFST bits)
EIFR
RECR
TECR
TSR
MSSR
MSMR
RFCR
TFCR
TCR
ECSR (except for the EDPM bit).
The following registers retain their previous values even after entering CAN reset mode:
CTLR
STR (only the SLPST and TFST bits)
MIER and MIER_FIFO
EIER
BCR
CSSR
ECSR (only the EDPM bit)
MBj_ID, MBj_DL, MBj_Dm and MBj_TS
MKRk
FIDCR0 and FIDCR1
MKIVLR
AFSR
RFPCR
TFPCR.
27.3.2
CAN Halt Mode
CAN halt mode is used for mailbox configuration and test mode setting.
When the CTLR.CANM[1:0] bits are set to 10b, CAN halt mode is selected. The STR.HLTST bit is then set to 1. Do not
change the CTLR.CANM[1:0] bits until the HLTST bit is 1.
See Table 27.8 for the state transition conditions when transmitting or receiving.
All registers except for bits RSTST, HLTST, and SLPST in the STR register remain unchanged when the CAN enters
CAN halt mode.
Do not change the CTLR register (except for the CANM[1:0] and SLPM bits) and EIER register in CAN halt mode. The
BCR register can be changed in CAN halt mode only when listen-only mode is selected for automatic baud rate
detection.
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Table 27.8
27. Controller Area Network (CAN) Module
Operation in CAN reset mode and CAN halt mode
Operation mode
Receiver
Transmitter
Bus-off
CAN reset mode
(forced transition)
CANM[1:0] = 11b
CAN module enters CAN reset
mode without waiting for the end
of message reception
CAN module enters CAN reset
mode without waiting for the end
of message transmission
CAN module enters CAN reset mode
without waiting for the end of bus-off
recovery
CAN reset mode
CANM[1:0] = 01b
CAN module enters CAN reset
mode without waiting for the end
of message reception
CAN module enters CAN reset
mode after waiting for the end of
message transmission*1,*4
CAN module enters CAN reset mode
without waiting for the end of bus-off
recovery
CAN halt mode
CAN module enters CAN halt
mode after waiting for the end of
message reception*2,*3
CAN module enters CAN halt
mode after waiting for the end of
message transmission*1,*4
When the BOM[1:0] bits are 00b:
A halt request from the software is
accepted only after bus-off recovery.
When the BOM[1:0] bits are 01b:
CAN module automatically enters CAN
halt mode without waiting for the end of
bus-off recovery, regardless of a halt
request from software.
When the BOM[1:0] bits are 10b:
CAN module automatically enters CAN
halt mode after waiting for the end of
bus-off recovery, regardless of a halt
request from software.
When the BOM[1:0] bits are 11b:
CAN module enters CAN halt mode,
without waiting for the end of bus-off
recovery, if a halt is requested by
software during bus-off.
Note 1. If transmission of multiple messages is requested, a mode transition occurs after completion of the first
transmission. If the CAN reset mode is being requested during suspend transmission, the mode transition occurs
when the bus is idle, the next transmission ends, or the CAN module becomes a receiver.
Note 2. If the CAN bus is locked at the dominant level, the program can detect this state by monitoring the BLIF bit in the
EIFR register.
Note 3. If a CAN bus error occurs during reception after CAN halt mode is requested, the CAN module transitions to CAN
halt mode.
Note 4. If a CAN bus error or arbitration-lost occurs during transmission after CAN reset mode or CAN halt mode is
requested, the CAN module transitions to the requested CAN mode.
27.3.3
CAN Sleep Mode
CAN sleep mode reduces power consumption by stopping the clock supply to the CAN module. After a reset from an
MCU pin or a software reset, the CAN module starts from CAN sleep mode.
When the CTLR.SLPM bit is set to 1, the CAN module enters CAN sleep mode. The STR.SLPST bit is then set to 1. Do
not change the value of the SLPM bit until the SLPST bit is 1. The other registers remain unchanged when the CAN
module enters CAN sleep mode.
Write to the SLPM bit in CAN reset mode or CAN halt mode. Do not change any registers (except for the SLPM bit)
during CAN sleep mode. Read operation is still allowed.
When the SLPM bit is set to 0, the CAN module is released from CAN sleep mode. When the CAN module exits CAN
sleep mode, the other registers remain unchanged.
27.3.4
CAN Operation Mode (Excluding Bus-Off State)
CAN operation mode is used for CAN communication.
When the CTLR.CANM[1:0] bits are set to 00b, the CAN module enters CAN operation mode. The STR.RSTST and
STR.HLTST bits are then set to 0. Do not change the value of the CANM[1:0] bits until the RSTST and HLTST bits are
0.
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27. Controller Area Network (CAN) Module
If 11 consecutive recessive bits are detected after entering CAN operation mode:
The CAN module becomes an active node on the network, which enables transmission and reception of CAN
messages
Error monitoring of the CAN bus, such as receive and transmit error counters, is performed.
During CAN operation mode, the CAN module is in one of the following three sub-modes, depending on the status of the
CAN bus:
Idle mode: No transmission or reception occurs
Receive mode: A CAN message sent by another node is being received
Transmit mode: A CAN message is being transmitted. The CAN module receives a message transmitted by the
local node simultaneously when self-test mode 0 (TCR.TSTM[1:0] = 10b) or self-test mode 1 (TCR.TSTM[1:0] =
11b) is selected.
Figure 27.10 shows the sub-modes in CAN operation mode.
Idle mode
STR.TRMST = 0
STR.RECST = 0
Transmission
starts
SOF
detected
Transmission
completed
Transmit mode
STR.TRMST = 1
STR.RECST = 0
Figure 27.10
27.3.5
Reception
completed
Arbitration lost
Receive mode
STR.TRMST = 0
STR.RECST = 1
Sub-modes of CAN operation mode
CAN Operation Mode (Bus-Off State)
The CAN module enters the bus-off state based on the increment/decrement rules for the transmit/receive error counters,
as defined in the CAN specification. The following cases apply when the CAN module is recovering from the bus-off
state. When the CAN module is in the bus-off state, the values in the CAN module registers (except STR, EIFR, RECR,
TECR, and TSR) remain unchanged.
(1)
When the CTLR.BOM[1:0] = 00b (Normal Mode)
The CAN module enters the error-active state after it completes recovery from the bus-off state and CAN communication
is enabled. The EIFR.BORIF flag is set to 1 (bus-off recovery detected).
(2)
When the CTLR.RBOC = 1 (Forced Return from Bus-Off)
The CAN module enters the error-active state when it is in the bus-off state and the RBOC bit is 1. CAN communication
is enabled again after 11b consecutive recessive bits are detected. The EIFR.BORIF flag is not set to 1.
(3)
When the CTLR.BOM[1:0] = 01b (Automatic Transition to CAN Halt Mode on Bus-Off Entry)
The CAN module enters CAN halt mode when it reaches the bus-off state. The EIFR.BORIF flag is not set to 1.
(4)
When CTLR.BOM[1:0] = 10b (Automatic Transition to CAN Halt Mode on Bus-Off End)
The CAN module enters CAN halt mode when it completes the recovery from bus-off. The EIFR.BORIF flag is set to 1.
(5)
When CTLR.BOM[1:0] = 11b (Automatic Transition to CAN Halt Mode through Software) and
the CTLR.CANM[1:0] = 10b (CAN Halt Mode) during Bus-Off State
The CAN module enters CAN halt mode when it is in the bus-off state and the CANM[1:0] bits are set to 10b (CAN halt
mode). The EIFR.BORIF flag is not set to 1.
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27. Controller Area Network (CAN) Module
If the CANM[1:0] bits are not set to 10b during bus-off, the same behavior as (1) applies.
27.4
Data Transfer Rate Configuration
This section describes how to configure the data transfer rate.
27.4.1
Clock Setting
The CAN module provides a CAN clock generator, as shown in Figure 27.11. Set the baud rate prescaler value in the
BCR.BRP[9:0] bits.
Baud rate
prescaler
1/(P + 1)
fCAN
EXTAL
fCANCLK
P = 0 to 1,023
fCAN:
CAN system clock
P:
Value selected in BRP[9:0] bits in BCR (P = 0 to 1,023)
fCANCLK: CAN communication clock (fCANCLK = fCAN/(P + 1))
Figure 27.11
27.4.2
Block diagram of CAN clock generator
Bit Time Setting
The bit time consists of the three segments shown in Figure 27.12.
Bit time
SS
TSEG1
TSEG2
Sample point
Range of each segment:
TSEG1 and TSEG2 settings:
Figure 27.12
27.4.3
Bit time = 8 to 25 Tq
SS = 1 Tq
TSEG1 = 4 to 16 Tq
TSEG2 = 2 to 8 Tq
SJW = 1 to 4 Tq
TSEG1 > TSEG2 SJW
Bit timing
Data Transfer Rate
The data transfer rate depends on the division value of fCAN (CAN system clock), the division value of the baud rate
prescaler, and the Tq count for 1 bit time.
Data transfer rate
[bps]
=
fCAN
Baud rate prescaler division value*1 x number of Tq of 1 bit time
=
fCANCLK
Number of Tq of 1 bit time
Note 1. Division value of baud rate prescaler = P + 1 (P: 0 to 1,023), where P is the BRP[9:0] setting in the BCR register.
Table 27.9 lists data transfer rate examples.
Table 27.9
Data transfer rate examples when fCAN = 32 MHz (1 of 2)
Data transfer rate
Tq Count
1 Mbps
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P+1
8 Tq
16 Tq
4
2
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Table 27.9
27. Controller Area Network (CAN) Module
Data transfer rate examples when fCAN = 32 MHz (2 of 2)
Data transfer rate
Tq Count
P+1
500 kbps
8 Tq
16 Tq
8
4
250 kbps
8 Tq
16 Tq
16
8
125 kbps
8 Tq
16 Tq
32
16
83.3 kbps
8 Tq
16 Tq
48
24
33.3 kbps
8 Tq
10 Tq
16 Tq
20 Tq
120
96
60
48
27.5
Mailbox and Mask Register Structure
Figure 27.13 shows the structure of the 32 mailbox registers (MBj_ID, MBj_DL, MBj_Dm, and MBj_TS).
Address
b7
b0
IDE
RTR
SID5
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0200h + 16 j + 0
4005 0200h + 16 j + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0200h + 16 j + 2
EID7
EID0
4005 0200h + 16 j + 3
EID6
EID5
EID4
EID3
EID2
EID1
4005 0200h + 16 j + 4
DLC3 DLC2 DLC1 DLC0
Figure 27.13
4005 0200h + 16 j + 5
DATA0
4005 0200h + 16 j + 6
DATA1
4005 0200h + 16 j + 7
DATA7
4005 0200h + 16 j + 13
TSH
4005 0200h + 16 j + 14
TSL
4005 0200h + 16 j + 15
Structure of the mailbox registers (j = 0 to 31)
Figure 27.14 shows the structure of the eight mask registers: MKRk.
Address
b7
SID5
b0
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0400h + 4 k + 0
4005 0400h + 4 k + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0400h + 4 k + 2
EID7
EID0
4005 0400h + 4 k + 3
EID6
EID5
EID4
EID3
EID2
EID1
MKRk register
Figure 27.14
Structure of the MKRk registers (k = 0 to 7)
Figure 27.15 shows the structure of the two FIFO receive ID compare registers, FIDCR0 and FIDCR1.
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27. Controller Area Network (CAN) Module
Address
b7
b0
IDE
RTR
SID5
SID4
SID3
SID10 SID9
SID8
SID2
SID0 EID17 EID16
SID1
SID7
SID6
CAN0
4005 0420h + 4 n + 0
4005 0420h + 4 n + 1
EID15 EID14 EID13 EID12 EID11 EID10 EID9
EID8
4005 0420h + 4 n + 2
EID7
EID0
4005 0420h + 4 n + 3
EID6
EID5
EID4
EID3
EID2
EID1
FIDCRn register
Figure 27.15
27.6
Structure of the FIDCRn registers (n = 0, 1)
Acceptance Filtering and Masking Functions
The acceptance filtering and masking functions allow you to select and receive messages with multiple IDs for
mailboxes within a specified range.
The MKRk registers can mask the standard ID and the extended ID.
MKR0 is the mask register for mailboxes 0 to 3
MKR1 is the mask register for mailboxes 4 to 7
MKR2 is the mask register for mailboxes 8 to 11
MKR3 is the mask register for mailboxes 12 to 15
MKR4 is the mask register for mailboxes 16 to 19
MKR5 is the mask register for mailboxes 20 to 23
MKR6 is the mask register for mailboxes 24 to 27 in normal mailbox mode and receive FIFO mailboxes 28 to 31 in
FIFO mailbox mode
MKR7 is the mask register for mailboxes 28 to 31 in normal mailbox mode and receive FIFO mailboxes 28 to 31 in
FIFO mailbox mode.
The MKIVLR register disables acceptance filtering independently for each mailbox.
The IDE bit in the MBj_ID register is valid when the CTLR.IDFM[1:0] bits are 10b (mixed ID mode).
The RTR bit in the MBj_ID register selects a data frame or a remote frame.
In FIFO mailbox mode, the normal mailboxes (0 to 23) use the associated register from MKR0 to MKR5 for acceptance
filtering. The receive FIFO mailboxes (28 to 31) use two registers, MKR6 and MKR7, for acceptance filtering.
The receive FIFO also uses two registers, FIDCR0 and FIDCR1, for ID comparison. The EID[17:0], SID[10:0], RTR,
and IDE bits in mailbox 28 to mailbox 31 for the receive FIFO are disabled. As acceptance filtering depends on the result
of two logic OR operations, two ranges of IDs can be received into the receive FIFO.
The MKIVLR register is disabled for the receive FIFO.
If different values are set in the IDE bits in the FIDCR0 and FIDCR1 registers, both ID formats are received.
If different values are set in the RTR bits in the FIDCR0 and FIDCR1 registers, both data and remote frames are
received.
When a combination of two ranges of IDs is not necessary, set the same mask value and the same ID in both the FIFO ID
and mask registers.
Figure 27.16 shows the associations between mask registers and mailboxes. Figure 27.17 shows the acceptance filtering.
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27. Controller Area Network (CAN) Module
Normal mailbox mode
FIFO mailbox mode
Mailbox 0
Mailbox 0
MKR0 register
MKR0 register
Mailbox 3
Mailbox 3
Mailbox 4
Mailbox 4
MKR1 register
MKR1 register
Mailbox 7
Mailbox 7
Mailbox 8
Mailbox 8
MKR2 register
MKR2 register
Mailbox 11
Mailbox 11
Mailbox 12
Mailbox 12
MKR3 register
MKR3 register
Mailbox 15
Mailbox 15
Mailbox 16
Mailbox 16
MKR4 register
MKR4 register
Mailbox 19
Mailbox 19
Mailbox 20
Mailbox 20
MKR5 register
MKR5 register
Mailbox 23
Mailbox 23
Mailbox 24
Transmit FIFO
FIDCR0 register
Mailbox 27
Mailbox 28
Mailbox 27
Mailbox 28
MKR7 register
MKR7 register
Receive FIFO
FIDCR1 register
Mailbox 31
Figure 27.16
Mailbox 24
MKR6 register
MKR6 register
Mailbox 31
Associations between mask registers and mailboxes
ID setting in MBj_ID
(j = 0 to 31)*1
ID value of received
message
Setting in MKIVLR*2
Setting in MKRk
(k = 0 to 7)
Mask bit values
0: IDs not compared
1: IDs compared
Acceptance judge signal
(internal signal)
Acceptance judge signal
0: Receiving message is ignored (not stored in
any mailbox)
1: Receiving message is stored in a mailbox that
matches the ID
Note 1. The settings in FIDCR0 and FIDCR1 are used in FIFO mailbox mode.
Note 2. Invalid in FIFO mailboxes.
Figure 27.17
Acceptance filtering
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27.7
27. Controller Area Network (CAN) Module
Reception and Transmission
Table 27.10 lists the CAN communication mode settings.
Table 27.10
Settings for CAN receive and transmit modes
MCTL_TXj
and
MCTL_RXjT
RMREQ
MCTL_TXj
and
MCTL_RXjR
ECREQ
MCTL_TXj
and
MCTL_RXj
ONESHOT
Mailbox communication mode
0
0
0
Mailbox disabled or transmission being aborted
0
0
1
Can be configured only when transmission or reception from a mailbox programmed in
one-shot mode is aborted
0
1
0
Configured as a receive mailbox for a data frame or a remote frame
0
1
1
Configured as a one-shot receive mailbox for a data frame or a remote frame
1
0
0
Configured as a transmit mailbox for a data frame or a remote frame
1
0
1
Configured as a one-shot transmit mailbox for a data frame or a remote frame
1
1
0
Do not set
1
1
1
Do not set
j = 0 to 31
When a mailbox is configured as a receive mailbox or a one-shot receive mailbox:
Before configuring the mailbox, set the MCTL_RXj register to 00h
A received message is stored into the first mailbox that matches the conditions resulting from the receive mode
settings and acceptance filtering. The matching mailbox with the smallest number takes priority for storing the
received message.
In CAN operation mode, the CAN module does not receive its own transmitted data even if the ID is a match. In
self-test mode, however, the CAN module receives its own transmitted data and returns ACK.
When configuring a mailbox as a transmit mailbox or a one-shot transmit mailbox:
Before configuring the mailbox, ensure that the MCTL_TXj register is 00h and that there is no pending abort
process.
27.7.1
Reception
Figure 27.18 shows an operation example of data frame reception in overwrite mode. The example shows the
overwriting of the first message when the CAN module receives two consecutive CAN messages that match the
receiving conditions in MCTL_RXj (j = 0 to 31).
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27. Controller Area Network (CAN) Module
Receive message in mailbox j
SOF
CRC
ACK
Receive message in mailbox j
EOF
IFS SOF
CRC
ACK
EOF
IFS
CAN bus
Acceptance filtering
MCTL_RX[j]
RECREQ
Acceptance filtering
MCTL_RX[j]
INVALDATA
MCTL_RX[j]
NEWDATA
MCTL_RX[j]
MSGLOST
CAN0 reception
complete interrupt
STR.
RECST
CAN0 error
interrupt
j = 0 to 31
Figure 27.18
Operation example of data frame reception in overwrite mode
1. When an SOF is detected on the CAN bus, the RECST bit in the STR register is set to 1 (reception in progress) if the
CAN module has no message ready to start transmission.
2. Acceptance filtering starts at the beginning of the CRC field to select the receive mailbox.
3. After a message is received, the MCTL_RXj.NEWDATA bit for the receive mailbox is set to 1 (new message is
being stored or was stored to the mailbox). The MCTL_RXj.INVALDATA flag is set to 1 (message is being
updated) at the same time. The INVALDATA flag is set to 0 (message valid) again after the complete message is
transferred to the mailbox.
4. If the interrupt enable bit in the MIER register for the receive mailbox is 1 (interrupt enabled), a CAN0 reception
complete interrupt request is generated when the INVALDATA flag is set to 0.
5. After the message is read from the mailbox, the NEWDATA bit must be set to 0 by software.
6. In overwrite mode, if the next CAN message is received before the NEWDATA bit in MCTL_RXj is set to 0, the
MSGLOST bit in MCTL_RXj is set to 1 (message was overwritten). The new received message is transferred to the
mailbox. The CAN0 reception complete interrupt request occurs the same as in step 4.
Figure 27.19 shows an operation example of data frame reception in overrun mode. The example shows the overrunning
of the second message when the CAN module receives two consecutive CAN messages that match the receiving
conditions in MCTL_RXj (j = 0 to 31).
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27. Controller Area Network (CAN) Module
Receive message in mailbox j
SOF
CRC
ACK
Receive message in mailbox j
EOF
IFS SOF
CRC
ACK
EOF
IFS
CAN bus
Acceptance filtering
MCTL_RX[j]
RECREQ
Acceptance filtering
MCTL_RX[j]
INVALDATA
MCTL_RX[j]
NEWDATA
MCTL_RX[j]
MSGLOST
CAN0 reception
complete interrupt
STR.RECST
CAN0 error
interrupt
j = 0 to 31
Figure 27.19
Operation example of data frame reception in overrun mode
Steps 1 to 5 are the same as in overwrite mode.
6. In overrun mode, if the next CAN message is received before the NEWDATA bit in MCTL_RXj is set to 0, the
MSGLOST bit in MCTL_RXj is set to 1 (message overrun). The new received message is discarded and a CAN0
error interrupt request occurs if the associated interrupt enable bit in the EIER register is 1 (interrupt enabled).
27.7.2
Transmission
Figure 27.20 shows an operation example of data frame transmission.
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27. Controller Area Network (CAN) Module
Transmission message in mailbox j
SOF
CRC
CRC
delimiter
Transmission message in mailbox k
EOF
IFS SOF
CRC
CRC
delimiter
EOF
IFS
CAN bus
Mailbox j
MCTL_TX[j]
TRMREQ
Next transmission scan
Next transmission scan
Next transmission scan
MCTL_TX[j]
TRMACTIVE
MCTL_TX[j]
SENTDATA
Mailbox k
MCTL_TX[k]
TRMREQ
MCTL_TX[k]
TRMACTIVE
MCTL_TX[k]
SENTDATA
CAN0
transmission
complete
interrupt
STR.TRMST
j, k = 0 to 31, j k
Figure 27.20
Operation example of data frame transmission
1. When a TRMREQ bit in MCTL_TXj (j = 0 to 31) is set to 1 (transmit mailbox) in the bus-idle state, mailbox
scanning starts to determine the highest-priority mailbox for transmission. When the transmit mailbox is
determined, the TRMACTIVE flag in MCTL_TXj is set to 1 (from acceptance of transmission request to
completion of transmission, or until error or arbitration-lost), the STR.TRMST bit is set to 1 (transmission in
progress), and the CAN module starts transmission.*1
2. If other TRMREQ bits are set, the transmission scanning starts with the CRC delimiter for the next transmission.
3. If transmission is completed without losing arbitration, the SENTDATA bit in MCTL_TXj is set to 1 (transmission
complete) and the TRMACTIVE flag is set to 0 (transmission is pending or transmission is not requested). If the
interrupt enable bit in MIER is 1 (interrupt enabled), the CAN0 transmission complete interrupt request is
generated.
4. When requesting the next transmission from the same mailbox, set bits SENTDATA and TRMREQ to 0, then set
the TRMREQ bit to 1 after checking that the SENTDATA and TRMREQ bits are set to 0.
Note 1. If arbitration is lost after the CAN module starts transmission, the TRMACTIVE flag is set to 0. Transmission
scanning is performed again to search for the highest-priority transmit mailbox from the beginning of the CRC
delimiter. If an error occurs either during transmission or following arbitration-lost, transmission scanning is
performed again to search for the highest-priority transmit mailbox from the start of the CRC delimiter.
27.8
Interrupt
The CAN module provides the following interrupts. Table 27.11 lists CAN interrupts.
CAN0 reception complete interrupt for mailboxes 0 to 31 (CAN0_RXM)
CAN0 transmission complete interrupt for mailboxes 0 to 31 (CAN0_TXM)
CAN0 receive FIFO interrupt (CAN0_RXF)
CAN0 transmit FIFO interrupt (CAN0_TXF)
CAN0 error interrupt (CAN0_ERS).
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27. Controller Area Network (CAN) Module
Eight interrupt sources are available for CAN0 error interrupts. Check the EIFR register to determine the interrupt
source:
Bus error
Error-warning
Error-passive
Bus-off entry
Bus-off recovery
Receive overrun
Overload frame transmission
Bus lock.
Table 27.11
CAN interrupts
Module
Interrupt
name
Interrupt source
Source flag
CAN0
CAN0_ERS
Bus lock detected
EIFR.BLIF
Overload frame transmission detected
EIFR.OLIF
Overrun detected
EIFR.ORIF
Bus-off recovery detected
EIFR.BORIF
Bus-off entry detected
EIFR.BOEIF
Error-passive detected
EIFR.EPIF
Error-warning detected
EIFR.EWIF
CAN0_RXF
Bus error detected
EIFR.BEIF
Receive FIFO message received (MIER_FIFO.MB29 = 0)
RFCR.RFUST[2:0]
Receive FIFO warning (MIER_FIFO.MB29 = 1)
CAN0_TXF
Transmit FIFO message transmission complete (MIER_FIFO.MB25 = 0)
TFCR.TFUST[2:0]
FIFO last message transmission complete (MIER_FIFO.MB25 = 1)
27.9
27.9.1
CAN0_RXM
Mailbox 0 to 31 message received
MCTL_RX[0].NEWDATA to
MCTL_RX[31].NEWDATA
CAN0_TXM
Mailbox 0 to 31 message transmission complete
MCTL_TX[0].SENTDATA to
MCTL_TX[31].SENTDATA
Usage Notes
Settings for the Module-Stop State
CAN module operation can be enabled or disabled using Module Stop Control Register B (MSTPCRB). The CAN
module is initially stopped after reset. Releasing the module-stop state enables access to the registers. For details, see
section 10, Low Power Modes.
27.9.2
Settings for the Operating Clock
The following clock constraints must be satisfied for the CAN module:
fPCLKB fCANMCLK
The clock frequency ratio of ICLK and PCLKB must be 2:1 when using the CAN module. Operation is not
guaranteed for other settings.
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28.
28. Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
In this section, n indicates A or B, and i indicates 0 or 1. A lower-case letter i in pin and signal names indicates a value
from 0 to 3.
28.1
Overview
The MCU includes two independent channels of the Serial Peripheral Interface (SPI). The SPI channels are capable of
high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices.
Table 28.1 lists the specifications of the SPI, and Figure 28.1 shows a block diagram.
Table 28.1
SPI specifications (1 of 2)
Parameter
Description
Number of channels
Two channels
SPI transfer functions
MOSI (master out/slave in), MISO (master in/slave out), SSL (slave select), and RSPCK (SPI clock)
signals enable serial communications through SPI operation (4-wire method) or clock synchronous
operation (3-wire method)
Transmit-only operation available
Communication mode selectable to full-duplex or transmit-only
Switching of RSPCK polarity
Switching of RSPCK phase.
Data format
MSB-first or LSB-first selectable
Transfer bit length selectable as 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits
32-bit transmit and receive buffers.
Bit rate
In master mode, the on-chip baud rate generator generates RSPCK by frequency-dividing PCLKB,
programmable from divide-by-2 to divide-by-4,096
In slave mode, the minimum PCLKB clock divided by 4 can be input as RSPCK (maximum RSPCK
frequency is PCLKB divided by 4).
Width at high level: 2 PCLKB cycles; width at low level: 2 PCLKB cycles
Buffer configuration
Double buffer configuration for the transmit/receive buffers
32 bits for the transmit and receive buffers.
Error detection
SSL control function
Control in master transfer
Support for the following commands:
SSL signal value, bit rate, RSPCK polarity and phase, transfer data length, MSB- or LSB-first, RSPCK
delay, SSL negation delay, and next-access delay
Transfers initiated by writing to the transmit buffer
MOSI signal value specifiable in SSL negation
RSPCK auto-stop function.
Interrupt sources
Mode fault error detection
Underrun error detection
Overrun error detection*1
Parity error detection.
Four SSL pins (SSLn0 to SSLn3) for each channel
In single-master mode, SSLn0 to SSLn3 pins for output
In multi-master mode, SSLn0 pin for output, and SSLn1 to SSLn3 pins either for output or unused
In slave mode: SSLn0 pin for input, and SSLn1 to SSLn3 pins unused
Controllable delay from SSL output assertion to RSPCK operation (RSPCK delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable delay from RSPCK stop to SSL output negation (SSL negation delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable wait for next-access SSL output assertion (next-access delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Function for changing SSL polarity.
Receive buffer full interrupt
Transmit buffer empty interrupt
SPI error interrupt (mode fault, overrun, parity error)
SPI idle interrupt (SPI idle)
Transmission-complete interrupt.
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Table 28.1
28. Serial Peripheral Interface (SPI)
SPI specifications (2 of 2)
Parameter
Description
Event link function (output)
The following events can be output to the event link controller:
Receive buffer full signal
Transmit buffer empty signal
Mode fault, underrun, overrun, or parity error signal
SPI idle signal
Transmission-complete signal.
Other
Function for initializing the SPI
Loopback mode.
Module-stop function
Module-stop state can be set
Note 1. In master reception and when the RSPCK auto-stop function is enabled, an overrun error does not occur,
because the transfer clock is stopped on overrun error detection.
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28. Serial Peripheral Interface (SPI)
Bus interface
S124 User’s Manual
Module data bus
SPRX
SPTX
Internal
peripheral bus
SPBR
SPCR
SSLP
Baud rate
generator
SPPCR
SPSR
PCLKB
SPDR/SPDR_HA
SPDCR
Parity circuit
SPCKD
SSLND
SPND
SPCR2
SPCMD0
Shift register
Selector
Normal
Loopback
MOSIn
Normal
Loopback
Loopback 2
MISOn
Normal
Loopback
Loopback 2
Master
Transmission/
reception controller
Event output
Clock
Loopback 2
Slave
Master
SPIn_SPTI
SPIn_SPRI
SPIn_SPII
Slave
SPIn_SPEI
SPIn_SPTEND
SSLn0
SSLn1 to SSLn3
RSPCKn
SPCR:
SPI Control Register
SPCR2:
SPI Control Register 2
SSLP:
SPI Slave Select Polarity Register
SPPCR:
SPI pin Control Register
SPSR:
SPI Status Register
SPDR/SPDR_HA: SPI Data Register
SPDCR:
SPI Data Control Register
SPCKD:
SPI Clock Delay Register
SSLND:
SPI Slave Select Negation Delay Register
Figure 28.1
SPND:
SPI Next-access Delay Register
SPCMD0:
SPI Command Register 0
SPBR:
SPI Bit Rate Register
SPTX:
SPI Transmit Buffer
SPRX:
SPI Receive Buffer
SPIn_SPTI: SPI Transmit Buffer Empty Interrupt
SPIn_SPRI: SPI Receive Buffer Full Interrupt
SPIn_SPII: SPI Idle Interrupt
SPIn_SPEI: SPI Error Interrupt
SPIn_SPTEND:SPI Transmission Complete Event
SPI block diagram
Table 28.2 lists the I/O pins used in the SPI.
The SPI automatically switches the I/O direction of the SSLn0 pin. SSLn0 is an output when the SPI is a single master
and an input when the SPI is a multi-master or a slave. The RSPCKn, MOSIn, and MISOn pins are automatically set as
inputs or outputs based on the master or slave setting and the level input on the SSLn0 pin.
See section 28.3.2, Controlling the SPI Pins for details.
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Table 28.2
28. Serial Peripheral Interface (SPI)
SPI pin configuration
Channel
Pin name
I/O
Function
SPI0
RSPCKA
I/O
Clock I/O
MOSIA
I/O
Master transmit data I/O
MISOA
I/O
Slave transmit data I/O
SSLA0
I/O
Slave selection I/O
SSLA1
Output
Slave selection output
SSLA2
Output
Slave selection output
SSLA3
Output
Slave selection output
SPI1
28.2
RSPCKB
I/O
Clock I/O
MOSIB
I/O
Master transmit data I/O
MISOB
I/O
Slave transmit data I/O
SSLB0
I/O
Slave selection I/O
SSLB1
Output
Slave selection output
SSLB2
Output
Slave selection output
SSLB3
Output
Slave selection output
Register Descriptions
28.2.1
SPI Control Register (SPCR)
Address(es): SPI0.SPCR 4007 2000h, SPI1.SPCR 4007 2100h
Value after reset:
b7
b6
SPRIE
SPE
0
0
b5
b4
b3
b2
b1
SPTIE SPEIE MSTR MODF TXMD
EN
0
0
0
0
0
b0
SPMS
0
Bit
Symbol
Bit name
Description
R/W
b0
SPMS
SPI Mode Select
0: Select SPI operation (4-wire method)
1: Select clock synchronous operation (3-wire method).
R/W
b1
TXMD
Communications Operating Mode
Select
0: Select full-duplex synchronous serial communications
1: Select serial communications with transmit only.
R/W
b2
MODFEN Mode Fault Error Detection Enable
0: Disable detection of mode fault errors
1: Enable detection of mode fault errors.
R/W
b3
MSTR
SPI Master/Slave Mode Select
0: Select slave mode
1: Select master mode.
R/W
b4
SPEIE
SPI Error Interrupt Enable
0: Disable SPI error interrupt requests
1: Enable SPI error interrupt requests.
R/W
b5
SPTIE
Transmit Buffer Empty Interrupt
Enable
0: Disable transmit buffer empty interrupt requests
1: Enable transmit buffer empty interrupt requests.
R/W
b6
SPE
SPI Function Enable
0: Disable SPI function
1: Enable SPI function.
R/W
b7
SPRIE
SPI Receive Buffer Full Interrupt
Enable
0: Disable SPI receive buffer full interrupt requests
1: Enable SPI receive buffer full interrupt requests.
R/W
If the SPCR.MSTR, SPCR.MODFEN, or SPCR.TXMD bit is changed while the SPCR.SPE bit is 1, do not perform
subsequent operations.
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28. Serial Peripheral Interface (SPI)
SPMS bit (SPI Mode Select)
The SPMS bit selects SPI operation (4-wire method) or clock synchronous operation (3-wire method).
The SSLn0 to SSLn3 pins are not used in clock synchronous operation. The RSPCKn, MOSIn, and MISOn pins handle
communications. For clock synchronous operation in master mode (SPCR.MSTR = 1), the SPCMD0.CPHA bit can be
set to either 0 or 1. For clock synchronous operation in slave mode (SPCR.MSTR = 0), set the CPHA bit to 1. Do not
perform operations if the CPHA bit is set to 0 for clock synchronous operation in slave mode (SPCR.MSTR = 0).
TXMD bit (Communications Operating Mode Select)
The TXMD bit selects full-duplex synchronous serial communications or transmit-only operations.
When this bit set to 1, the SPI only performs transmit operations and not receive operations (see section 28.3.6, Data
Transfer Modes), and receive buffer full interrupt requests cannot be used.
MODFEN bit (Mode Fault Error Detection Enable)
The MODFEN bit enables or disables the detection of mode fault errors (see section 28.3.8, Error Detection). In addition,
the SPI determines the I/O direction of the SSLn0 to SSLn3 pins based on combinations of the MODFEN and MSTR bit
settings (see section 28.3.2, Controlling the SPI Pins).
MSTR bit (SPI Master/Slave Mode Select)
The MSTR bit selects master or slave mode for the SPI. Based on the MSTR bit settings, the SPI determines the direction
of the RSPCKn, MOSIn, MISOn, and SSLn0 to SSLn3 pins.
SPEIE bit (SPI Error Interrupt Enable)
The SPEIE bit enables or disables the generation of SPI error interrupt requests when:
The SPI detects a mode fault error or underrun error and sets the SPSR.MODF flag to 1
The SPI detects an overrun error and sets the SPSR.OVRF flag to 1
The SPI detects a parity error and sets the SPSR.PERF flag to 1.
See section 28.3.8, Error Detection.
SPTIE bit (Transmit Buffer Empty Interrupt Enable)
The SPTIE bit enables or disables the generation of transmit buffer empty interrupt requests when the SPI detects that the
transmit buffer is empty.
A transmit buffer empty interrupt request on transmission start is generated by setting the SPE and SPTIE bits to 1 at the
same time or by setting the SPE bit to 1 after setting the SPTIE bit to 1. The interrupt occurs when the SPTIE bit is 1,
even if the SPI function is disabled (the SPE bit is changed to 0).
SPE bit (SPI Function Enable)
The SPE bit enables or disables the SPI function.
The SPE bit cannot be set to 1 when the SPSR.MODF flag is 1. For details, see section 28.3.8, Error Detection.
Setting the SPE bit to 0 disables the SPI function and initializes a part of the module function. For details, see section
28.3.9, Initializing SPI. In addition, a state change on the SPE bit, from 0 to 1 or 1 to 0, triggers a transmit buffer empty
interrupt request.
SPRIE bit (SPI Receive Buffer Full Interrupt Enable)
The SPRIE bit enables or disables the generation of an interrupt request if the SPI detects a receive buffer full write after
completing a serial transfer.
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28.2.2
28. Serial Peripheral Interface (SPI)
SPI Slave Select Polarity Register (SSLP)
Address(es): SPI0.SSLP 4007 2001h, SPI1.SSLP 4007 2101h
Value after reset:
b7
b6
b5
b4
—
—
—
—
0
0
0
0
b3
b2
b1
b0
SSL3P SSL2P SSL1P SSL0P
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SSL0P
SSL0 Signal Polarity Setting
0: Set SSL0 signal to active-low
1: Set SSL0 signal to active-high.
R/W
b1
SSL1P
SSL1 Signal Polarity Setting
0: Set SSL1 signal to active-low
1: Set SSL1 signal to active-high.
R/W
b2
SSL2P
SSL2 Signal Polarity Setting
0: Set SSL2 signal to active-low
1: Set SSL2 signal to active-high.
R/W
b3
SSL3P
SSL3 Signal Polarity Setting
0: Set SSL3 signal to active-low
1: Set SSL3 signal to active-high.
R/W
b7 to b4
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the contents of SSLP are changed while the SPCR.SPE bit is 1, do not perform subsequent operations.
28.2.3
SPI Pin Control Register (SPPCR)
Address(es): SPI0.SPPCR 4007 2002h, SPI1.SPPCR 4007 2102h
Value after reset:
b7
b6
—
—
0
0
b5
b4
MOIFE MOIFV
0
b3
b2
b1
b0
—
—
SPLP2
SPLP
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SPLP
SPI Loopback
0: Normal mode
1: Loopback mode, with data inverted for transmission.
R/W
b1
SPLP2
SPI Loopback 2
0: Normal mode
1: Loopback mode, with data not inverted for transmission.
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
MOIFV
MOSI Idle Fixed Value
0: The level output on the MOSIn pin during MOSI idling is defined as
low
1: The level output on the MOSIn pin during MOSI idling is defined as
high
R/W
b5
MOIFE
MOSI Idle Value Fixing
Enable
0: MOSI output value equals final data from previous transfer
1: MOSI output value equals the value set in the MOIFV bit
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the contents of SPPCR are changed while the SPCR.SPE bit is 1, do not perform subsequent operations.
SPLP bit (SPI Loopback)
The SPLP bit selects the mode of the SPI pins. When the SPLP bit is set to 1, the SPI shuts off the path between the
MISOn pin and the shift register if the SPCR.MSTR bit is 1, and between the MOSIn pin and the shift register if the
SPCR.MSTR bit is 0. It connects, and inverts, the input path and output path for the shift register, establishing loopback
mode.
SPLP2 bit (SPI Loopback 2)
The SPLP2 bit selects the mode of the SPI pins. When the SPLP2 bit is set to 1, the SPI shuts off the path between the
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28. Serial Peripheral Interface (SPI)
MISOn pin and the shift register if the SPCR.MSTR bit is 1, and between the MOSIn pin and the shift register if the
SPCR.MSTR bit is 0. The SPI then connects the input path and output path for the shift register, establishing loopback
mode 2.
MOIFV bit (MOSI Idle Fixed Value)
If the MOIFE bit is 1 in master mode, the MOIFV bit determines the MOSIn pin output value during the SSL negation
period.
MOIFE bit (MOSI Idle Value Fixing Enable)
The MOIFE bit fixes the MOSIn output value when the SPI is in master mode and in an SSL negation period. When the
MOIFE bit is 0, the SPI outputs to the MOSIn pin the last data from the previous serial transfer during the SSL negation
period. When the MOIFE bit is 1, the SPI outputs the fixed value set in the MOIFV bit to the MOSIn pin.
28.2.4
SPI Status Register (SPSR)
Address(es): SPI0.SPSR 4007 2003h, SPI1.SPSR 4007 2103h
b7
b6
SPRF
—
0
0
Value after reset:
b5
b4
SPTEF UDRF
1
b3
PERF
0
b2
b1
MODF IDLNF
0
0
0
b0
OVRF
0
Bit
Symbol
Bit name
Description
R/W
b0
OVRF
Overrun Error Flag
0: No overrun error occurred
1: Overrun error occurred.
R/(W)*1
b1
IDLNF
SPI Idle Flag
0: SPI is in the idle state
1: SPI is in the transfer state
R
b2
MODF
Mode Fault Error Flag
0: No mode fault error or underrun error occurred
1: A mode fault error or underrun error occurred.
R/(W)*1
b3
PERF
Parity Error Flag
0: No parity error occurred
1: A parity error occurred.
R/(W)*1
b4
UDRF
Underrun Error Flag
0: A mode fault error occurred (MODF = 1)
1: An underrun error occurred (MODF = 1).
This bit is invalid when MODF is 0.
R/W*1,*2
b5
SPTEF
SPI Transmit Buffer Empty Flag
0: Data found in the transmit buffer
1: No data in the transmit buffer.
R/(W)*1,*3
b6
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b7
SPRF
SPI Receive Buffer Full Flag
0: No valid data in SPDR/SPDR_HA
1: Valid data found in SPDR/SPDR_HA.
R/(W)*1,*3
Note 1. Only 0 can be written to clear the flag after reading 1.
Note 2. Clear the UDRF flag at the same time that you clear the MODF flag.
Note 3. The write value should be 1.
OVRF flag (Overrun Error Flag)
The OVRF flag indicates the occurrence of an overrun error. In master mode (SPCR.MSTR = 1) and when the RSPCK
clock auto-stop function is enabled (SPCR2.SCKASE = 1), overrun errors do not occur, and this flag does not set to 1.
For details, see section 28.3.8.1, Overrun errors.
[Setting condition]
When the next serial transfer ends while the SPCR.TXMD bit is 0 and the receive buffer is full.
[Clearing condition]
When SPSR is read while this flag is 1, and then 0 is written to this flag.
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28. Serial Peripheral Interface (SPI)
IDLNF flag (SPI Idle Flag)
The IDLNF flag indicates the transfer status of the SPI.
[Setting condition]
Master mode:
When conditions 1. and 2. in the master mode [Clearing condition] are not satisfied.
Slave mode:
When the SPCR.SPE bit is 1, enabling the SPI function.
[Clearing condition]
Master mode:
When condition 1. or conditions 2. and 3. are satisfied.
1. The SPCR.SPE bit is 0 for SPI initialization.
2. The transmit buffer (SPTX) is empty, meaning data for the next transfer is not set.
3. The SPI internal sequencer is in the idle state, indicating that operations up to the next-access delay are complete.
Slave mode:
When condition 1. is satisfied.
MODF flag (Mode Fault Error Flag)
The MODF flag indicates the occurrence of a mode fault error or an underrun error. Use the UDRF to identify which
errors occurred.
[Setting condition]
Multi-master mode:
When the input level of the SSLni pin changes to the active level while the SPCR.MSTR bit is 1 (master mode) and
the SPCR.MODFEN bit is 1 (mode fault error detection enabled), the SPI detects a mode fault error.
Slave mode:
When condition 1. or 2. is satisfied.
1. The SSLni pin is negated before the RSPCK cycle necessary for data transfer ends while the SPCR.MSTR bit is 0
(slave mode) and the SPCR.MODFEN bit is 1 (mode fault error detection enabled), triggering a mode fault error.
2. The serial transfer begins with the SPCR.MSTR bit set to 0 (slave mode), the SPCR.SPE bit set to 1, and the
transmission data is not prepared, triggering an underrun error.
The active level of the SSLni signal is determined by the SSLP.SSLiP bit (SSLi signal polarity setting).
[Clearing condition]
When SPSR is read while this flag is 1, and then 0 is written to this flag.
PERF flag (Parity Error Flag)
The PERF flag indicates the occurrence of a parity error.
[Setting condition]
When a serial transfer ends while the SPCR.TXMD bit is 0 and the SPCR2.SPPE bit is 1, triggering a parity error.
[Clearing condition]
When SPSR is read while this flag is 1, and then 0 is written to this flag.
UDRF flag (Underrun Error Flag)
The UDRF flag indicates the occurrence of an underrun error.
[Setting condition]
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28. Serial Peripheral Interface (SPI)
When the serial transfer begins with the SPCR.MSTR bit set to 0 (slave mode), SPCR.SPE bit set to 1, and the
transmission data is not prepared, triggering an underrun error.
[Clearing condition]
When SPSR is read while this flag is 1, and then 0 is written to this flag.
SPTEF flag (SPI Transmit Buffer Empty Flag)
The SPTEF flag indicates the status of the transmit buffer for the SPI Data Register (SPDR/SPDR_HA).
[Setting condition]
When condition 1. or 2. is satisfied.
1. The SPCR.SPE bit is 0 for SPI initialization.
2. Transmit data is transferred from the transmit buffer to the shift register.
[Clearing condition]
When data is written to SPDR/SPDR_HA.
Data can only be written to SPDR/SPDR_HA when the SPTEF bit is 1. If data is written to the transmit buffer of SPDR/
SPDR_HA when the SPTEF bit is 0, the data in the transmit buffer is not updated.
SPRF flag (SPI Receive Buffer Full Flag)
The SPRF flag indicates the status of the receive buffer for the SPI Data Register (SPDR/SPDR_HA).
[Setting condition]
When a serial transfer ends while the communication operating mode select bit (TXMD) in the SPI Control Register
(SPCR) is 0 and the SPRF bit is 0, and the SPI transfers the receive data from the shift register to SPDR/SPDR_HA.
However, when the OVRF flag is 1, SPRF does not change from 0 into 1.
[Clearing condition]
When received data is read from SPDR/SPDR_HA.
28.2.5
SPI Data Register (SPDR/SPDR_HA)
Address(es): SPI0.SPDR 4007 2004h, SPI1.SPDR 4007 2104h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address(es): SPI0.SPDR_HA 4007 2004h, SPI1.SPDR_HA 4007 2104h
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPDR/SPDR_HA is the interface with the buffers that hold data for transmission and reception by the SPI.
The transmit buffer (SPTX) and receive buffer (SPRX) are independent but are both mapped to SPDR/SPDR_HA.
Figure 28.2 shows the configuration of SPDR/SPDR_HA.
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28. Serial Peripheral Interface (SPI)
SPI data registers
Figure 28.2
SPDR/SPDR_HA
Internal peripheral bus
Transmit buffer
SPTX
Shift
register
Transmit data
Receive data
Receive buffer
SPRX
Configuration of SPDR/SPDR_HA
The transmit and receive buffers each have one stage. The two stages of the buffer are all mapped to the single address of
SPDR/SPDR_HA. Data written to SPDR/SPDR_HA is written to a transmit-buffer stage (SPTX) and then transmitted
from the buffer. The receive buffer holds received data on completion of reception. The receive buffer is not updated if an
overrun occurs.
If the data length is not 32 bits, bits not referred to in SPTX are stored in the associated bits in SPRX. For example, if the
data length is 9 bits, received data is stored in the SPRX[8:0] bits, and the SPTX[31:9] bits are stored in the SPRX[31:9]
bits.
(1)
Bus Interface
SPDR/SPDR_HA is an interface with 32-bit wide transmit and receive buffers, each of which has one stage, for a total of
8 bytes. The 8 bytes are mapped to the 4-byte address space for SPDR/SPDR_HA. The unit of access for SPDR/
SPDR_HA is selected in the SPI word access/halfword access specification bit in the SPI Data Control Register
(SPDCR.SPLW).
Flush transmission data at the LSB end of the register and store received data at the LSB end.
This section describes operations involved in writing to and reading from SPDR/SPDR_HA.
(a)
Writing
Data written to SPDR/SPDR_HA is written to a transmit buffer (SPTX). This is not affected by the value of the
SPDCR.SPRDTD bit, unlike when reading from SPDR/SPDR_HA.
SPDR/SPDR_HA
Figure 28.3 shows the configuration of the bus interface with the transmit buffer when writing to SPDR/SPDR_HA.
Figure 28.3
SPTX
Configuration of SPDR/SPDR_HA for write access
Write the transfer data to SPTX after generating the transmit buffer empty interrupt (when SPSR.SPTEF is 1). Even
when the data is written to the transmit buffer (SPTX), the value of the buffer is not updated after completion of the
writing and before the next transmit buffer empty interrupt is generated (when SPTEF is 0).
(b)
Reading
SPDR/SPDR_HA can be accessed to read the value of a receive buffer (SPRX) or a transmit buffer (SPTX). The setting
in the SPI receive/transmit data select bit in the SPI Data Control Register (SPDCR.SPRDTD) identifies whether reading
is of the receive or transmit buffer.
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28. Serial Peripheral Interface (SPI)
SPDR/SPDR_HA
Figure 28.4 shows the configuration of the bus interface with the receive and transmit buffers, for reads from SPDR/
SPDR_HA.
0
SPRX
1
SPTX
SPRDTD
Figure 28.4
Configuration of SPDR/SPDR_HA for read access
After generation of the transmit buffer empty interrupt, the values read from the buffer are all 0s in the interval after
completion of writing the data frame and before generation of the next buffer empty interrupt (when SPSR.SPTEF is 0).
28.2.6
SPI Bit Rate Register (SPBR)
Address(es): SPI0.SPBR 4007 200Ah, SPI1.SPBR 4007 210Ah
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
SPBR sets the bit rate in master mode. If the contents of SPBR are changed while both the SPCR.MSTR and SPCR.SPE
bits are 1, do not perform subsequent operations.
When the SPI is used in slave mode, the bit rate depends on the bit rate of the input clock, regardless of the settings in the
SPBR and the SPCMD0.BRDV[1:0] bits (bit rate division setting). For the input clock, use bit rates that satisfy the
electrical characteristics of the device.
The bit rate is determined by the combination of the SPBR and SPCMD0.BRDV[1:0] settings. The equation to calculate
the bit rate is as follows:
f(PCLKB)
Bit rate =
2 × (n + 1) × 2N
In the equation, n denotes an SPBR setting (0, 1, 2, …, 255), and N denotes a BRDV[1:0] bit setting (0, 1, 2, or 3).
Table 28.3 lists examples of the relationship between the SPBR settings, BRDV[1:0] settings, and bit rates.
Table 28.3
Relationship between SPBR settings, BRDV[1:0] settings, and bit rates
SPBR (n)
BRDV[1:0] bits (N)
Division ratio
Bit rate when PCLKB = 32 MHz
0
0
2
16.0 Mbps
1
0
4
8.00 Mbps
2
0
6
5.33 Mbps
3
0
8
4.00 Mbps
4
0
10
3.20 Mbps
5
0
12
2.67 Mbps
5
1
24
1.33 Mbps
5
2
48
667 Kbps
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Table 28.3
28. Serial Peripheral Interface (SPI)
Relationship between SPBR settings, BRDV[1:0] settings, and bit rates
SPBR (n)
BRDV[1:0] bits (N)
Division ratio
Bit rate when PCLKB = 32 MHz
5
3
96
333 Kbps
255
3
4096
7.81 Kbps
28.2.7
SPI Data Control Register (SPDCR)
Address(es): SPI0.SPDCR 4007 200Bh, SPI1.SPDCR 4007 210Bh
b7
Value after reset:
b6
—
—
0
0
b5
b4
SPLW SPRDT
D
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b4
SPRDTD
SPI Receive/Transmit Data
Select
0: Read SPDR/SPDR_HA values from receive buffer
1: Read SPDR/SPDR_HA values from transmit buffer, but
only if the transmit buffer is empty.
R/W
b5
SPLW
SPI Word Access/Halfword
Access Specification
0: Set SPDR_HA to valid for halfword access
1: Set SPDR to valid for word access.
R/W
b7 to b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
SPRDTD bit (SPI Receive/Transmit Data Select)
The SPRDTD bit selects whether the SPDR/SPDR_HA reads values from the receive buffer or from the transmit buffer.
If reading is from the transmit buffer, the last value written to SPDR/SPDR_HA register is read. Read the transmit buffer
after generation of the transmit buffer empty interrupt (when SPSR.SPTEF is 1).
For details, see section 28.2.5, SPI Data Register (SPDR/SPDR_HA).
SPLW bit (SPI Word Access/Halfword Access Specification)
The SPLW bit specifies the access width for the SPDR register. Access to SPDR_HA in halfwords is valid when the
SPLW bit is 0 and access to the SPDR register in words is valid when the SPLW bit is 1. In addition, when the SPLW bit
is 0, set the SPCMD0.SPB[3:0] bits (SPI data length setting bits) from 8 to 16 bits. When 20, 24, or 32 bits is specified,
do not perform any operations.
28.2.8
SPI Clock Delay Register (SPCKD)
Address(es): SPI0.SPCKD 4007 200Ch, SPI1.SPCKD 4007 210Ch
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SCKDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SCKDL[2:0]
RSPCK Delay Setting
b2
R/W
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0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK
1: 2 RSPCK
0: 3 RSPCK
1: 4 RSPCK
0: 5 RSPCK
1: 6 RSPCK
0: 7 RSPCK
1: 8 RSPCK.
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28. Serial Peripheral Interface (SPI)
Bit
Symbol
Bit name
Description
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
SPCKD sets the RSPCK delay, the period from the beginning of SSLni signal assertion to RSPCK oscillation, when the
SPCMD0.SCKDEN bit is 1. If the contents of SPCKD are changed while both the SPCR.MSTR and SPCR.SPE bits are
1, do not perform subsequent operations.
SCKDL[2:0] bits (RSPCK Delay Setting)
The SCKDL[2:0] bits set an RSPCK delay value when the SPCMD0.SCKDEN bit is 1. When using the SPI in slave
mode, set the SCKDL[2:0] bits to 000b.
28.2.9
SPI Slave Select Negation Delay Register (SSLND)
Address(es): SPI0.SSLND 4007 200Dh, SPI1.SSLND 4007 210Dh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SLNDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SLNDL[2:0]
SSL Negation Delay Setting
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK
1: 2 RSPCK
0: 3 RSPCK
1: 4 RSPCK
0: 5 RSPCK
1: 6 RSPCK
0: 7 RSPCK
1: 8 RSPCK.
R/W
SSLND sets the SSL negation delay, the period from the transmission of a final RSPCK edge to the negation of the
SSLni signal during a serial transfer by the SPI in master mode. If the contents of SSLND are changed while both the
SPCR.MSTR and SPCR.SPE bits are 1, do not perform subsequent operations.
SLNDL[2:0] bits (SSL Negation Delay Setting)
The SLNDL[2:0] bits set an SSL negation delay value when the SPI is in master mode. When using the SPI in slave
mode, set the SLNDL[2:0] bits to 000b.
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28.2.10
28. Serial Peripheral Interface (SPI)
SPI Next-Access Delay Register (SPND)
Address(es): SPI0.SPND 4007 200Eh, SPI1.SPND 4007 210Eh
Value after reset:
b7
b6
b5
b4
b3
—
—
—
—
—
0
0
0
0
0
b2
b1
b0
SPNDL[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
SPNDL[2:0]
SPI Next-Access Delay Setting
b2
R/W
b7 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b0
0: 1 RSPCK + 2 PCLKB
1: 2 RSPCK + 2 PCLKB
0: 3 RSPCK + 2 PCLKB
1: 4 RSPCK + 2 PCLKB
0: 5 RSPCK + 2 PCLKB
1: 6 RSPCK + 2 PCLKB
0: 7 RSPCK + 2 PCLKB
1: 8 RSPCK + 2 PCLKB.
R/W
SPND sets the next-access delay, the non-active period of the SSLni signal after termination of a serial transfer when the
SPCMD0.SPNDEN bit is 1. If the contents of SPND are changed while both the SPCR.MSTR and SPCR.SPE bits are 1,
do not perform subsequent operations.
SPNDL[2:0] bits (SPI Next-Access Delay Setting)
The SPNDL[2:0] bits set a next-access delay when the SPCMD0.SPNDEN bit is 1. When using the SPI in slave mode,
set the SPNDL[2:0] bits to 000b.
28.2.11
SPI Control Register 2 (SPCR2)
Address(es): SPI0.SPCR2 4007 200Fh, SPI1.SPCR2 4007 210Fh
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
SCKAS
E
PTE
SPIIE
SPOE
SPPE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SPPE
Parity Enable
0: No parity bit added to transmit data and parity bit in receive
data not checked
1: When SPCR.TXMD = 0: Parity bit added to transmit data
and parity bit of receive data checked
When SPCR.TXMD = 1: Parity bit added to transmit data
but parity bit of receive data not checked.
R/W
b1
SPOE
Parity Mode
0: Even parity selected for transmission and reception
1: Odd parity selected for transmission and reception.
R/W
b2
SPIIE
SPI Idle Interrupt Enable
0: Idle interrupt requests disabled
1: Idle interrupt requests enabled.
R/W
b3
PTE
Parity Self-Testing
0: Self-diagnosis function of the parity circuit disabled
1: Self-diagnosis function of the parity circuit enabled.
R/W
b4
SCKASE
RSPCK Auto-Stop Function
Enable
0: RSPCK auto-stop function disabled
1: RSPCK auto-stop function enabled.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
If the SPPE, SPOE, or SCKASE bit in SPCR2 is changed while the SPCR.SPE bit is 1, do not perform subsequent
operations.
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28. Serial Peripheral Interface (SPI)
SPPE bit (Parity Enable)
The SPPE bit enables or disables the parity function.
When the SPCR.TXMD bit is 0 and this bit is 1, the parity bit is added to transmit data and parity checking is performed
for receive data. When the SPCR.TXMD bit is 1 and this bit is 1, the parity bit is added to transmit data but parity
checking is not performed for receive data.
SPOE bit (Parity Mode)
The SPOE bit specifies odd or even parity.
When even parity is set, parity bit addition is performed so that the total number of 1-bits in the transmit or receive
character plus the parity bit is even. Similarly, when odd parity is set, parity bit addition is performed so that the total
number of 1-bits in the transmit or receive character plus the parity bit is odd.
The SPOE bit is valid only when the SPPE bit is 1.
SPIIE bit (SPI Idle Interrupt Enable)
The SPIIE bit enables or disables the generation of SPI idle interrupt requests when an SPI idle state is detected and the
SPSR.IDLNF flag sets to 0.
PTE bit (Parity Self-Testing)
The PTE bit enables self-diagnosis of the parity circuit to check whether the parity function is operating correctly.
SCKASE bit (RSPCK Auto-Stop Function Enable)
The SCKASE bit enables or disables the RSPCK auto-stop function. When this function is enabled, the RSPCK clock is
stopped before an overrun error occurs when data is received in master mode. For details, see section 28.3.8.1, Overrun
errors.
28.2.12
SPI Command Registers 0 (SPCMD0)
Address(es): SPI0.SPCMD0 4007 2010h, SPI1.SPCMD0 4007 2110h
b15
b14
b13
b12
b11
b10
SCKDE SLNDE SPNDE LSBF
N
N
N
Value after reset:
0
0
0
0
b9
b8
SPB[3:0]
0
1
b7
b6
—
1
1
0
b5
b4
SSLA[2:0]
0
0
b3
b2
BRDV[1:0]
0
1
b1
b0
CPOL
CPHA
0
1
1
Bit
Symbol
Bit name
Description
R/W
b0
CPHA
RSPCK Phase Setting
0: Select data sampling on leading edge, data change on
trailing edge
1: Select data change on leading edge, data sampling on
trailing edge.
R/W
b1
CPOL
RSPCK Polarity Setting
0: Set RSPCK low when idle
1: Set RSPCK high when idle.
R/W
b3, b2
BRDV[1:0]
Bit Rate Division Setting
b3 b2
R/W
b6 to b4
SSLA[2:0]
SSL Signal Assertion Setting
b7
—
Reserved
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0
0
1
1
b6
0: Base bit rate
1: Base bit rate divided by 2
0: Base bit rate divided by 4
1: Base bit rate divided by 8.
b4
0 0 0: SSL0
0 0 1: SSL1
0 1 0: SSL2
0 1 1: SSL3
1 x x: Setting prohibited.
x: Don’t care.
This bit is read as 0. The write value should be 0.
R/W
R/W
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28. Serial Peripheral Interface (SPI)
Bit
Symbol
Bit name
Description
R/W
b11 to b8
SPB[3:0]
SPI Data Length Setting
b11
R/W
b12
LSBF
SPI LSB First
0: MSB-first
1: LSB-first.
R/W
b13
SPNDEN
SPI Next-Access Delay Enable
0: Next-access delay is 1 RSPCK + 2 PCLKB
1: Next-access delay equals to the setting in the SPI Nextaccess Delay register (SPND).
R/W
b14
SLNDEN
SSL Negation Delay Setting
Enable
0: An SSL negation delay is 1 RSPCK
1: An SSL negation delay equals to the setting in the SPI
Slave Select Negation Delay register (SSLND).
R/W
b15
SCKDEN
RSPCK Delay Setting Enable
0: An RSPCK delay of 1 RSPCK
1: An RSPCK delay equals to the setting in the SPI Clock
Delay register (SPCKD).
R/W
b8
0100 to 0111: 8 bits
1 0 0 0: 9 bits
1 0 0 1: 10 bits
1 0 1 0: 11 bits
1 0 1 1: 12 bits
1 1 0 0: 13 bits
1 1 0 1: 14 bits
1 1 1 0: 15 bits
1 1 1 1: 16 bits
0 0 0 0: 20 bits
0 0 0 1: 24 bits
0010, 0011: 32 bits.
SPCMD0 sets a transfer format for the SPI in master mode.
Set this register while the transmit buffer is empty (SPSR.SPTEF is 1 and data for the next transfer is not set), and before
the setting of data to be transmitted when this register is referenced.
If the contents of SPCMD0 are changed while the SPCR.SPE bit is 1, do not perform subsequent operations.
CPHA bit (RSPCK Phase Setting)
The CPHA bit sets the RSPCK phase for the SPI in master mode or slave mode. Data communications between SPI
modules require the same RSPCK phase setting between the modules.
CPOL bit (RSPCK Polarity Setting)
The CPOL bit sets the RSPCK polarity for the SPI in master mode or slave mode. Data communications between SPI
modules require the same RSPCK polarity setting between the modules.
BRDV[1:0] bits (Bit Rate Division Setting)
The BRDV[1:0] bits determine the bit rate combination of the settings in SPBR (see section 28.2.6, SPI Bit Rate Register
(SPBR)). The SPBR settings determine the base bit rate. The BRDV[1:0] settings select a bit rate obtained by dividing
the base bit rate by 1, 2, 4, or 8. Different BRDV[1:0] bit settings can be specified, enabling execution of serial transfers
at a different bit rate for each command.
SSLA[2:0] bits (SSL Signal Assertion Setting)
The SSLA[2:0] bits control the SSLni signal assertion when the SPI performs serial transfers in master mode.
When an SSLni signal is asserted, its polarity is determined by the value set in the associated SSLP. When the SSLA[2:0]
bits are set to 000b in multi-master mode, serial transfers are performed with all the SSL signals in the negated state, as
the SSLn0 pin acts as input.
When using the SPI in slave mode, set the SSLA[2:0] bits to 000b.
SPB[3:0] bits (SPI Data Length Setting)
The SPB[3:0] bits set a transfer data length for the SPI in master or slave mode.
When the SPLW bit is 0, set these bits from 8 to 16 bits.
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28. Serial Peripheral Interface (SPI)
LSBF bit (SPI LSB First)
The LSBF bit sets the data format of the SPI in master or slave mode to MSB-first or LSB-first.
SPNDEN bit (SPI Next-Access Delay Enable)
The SPNDEN bit sets the next-access delay, the period from when the SPI in master mode terminates a serial transfer and
sets the SSLni signal inactive until the SPI enables the SSLni signal assertion for the next access. If the SPNDEN bit is 0,
the SPI sets the next-access delay to 1 RSPCK + 2 PCLKB. If the SPNDEN bit is 1, the SPI inserts a next-access delay
according to the SPND setting.
When using the SPI in slave mode, set the SPNDEN bit to 0.
SLNDEN bit (SSL Negation Delay Setting Enable)
The SLNDEN bit sets the SSL negation delay, the period from when the SPI in master mode stops RSPCK oscillation
until the SPI sets the SSLni signal inactive. If the SLNDEN bit is 0, the SPI sets the SSL negation delay to 1 RSPCK. If
the SLNDEN bit is 1, the SPI negates the SSL signal to an SSL negation delay according to the SSLND setting.
When using the SPI in slave mode, set the SLNDEN bit to 0.
SCKDEN bit (RSPCK Delay Setting Enable)
The SCKDEN bit sets the SPI clock delay, the period from when the SPI in master mode activates the SSLni signal until
the RSPCK starts oscillation. If the SCKDEN bit is 0, the SPI sets the RSPCK delay to 1 RSPCK. If the SCKDEN bit is
1, the SPI starts the oscillation of RSPCK at an RSPCK delay according to the SPCKD setting.
When using the SPI in slave mode, set the SCKDEN bit to 0.
28.3
Operation
In this section, the serial transfer period means the period from the beginning of driving valid data to the fetching of the
final valid data.
28.3.1
Overview of SPI Operations
The SPI is capable of synchronous serial transfers in the following modes:
Slave mode (SPI operation)
Single-master mode (SPI operation)
Multi-master mode (SPI operation)
Slave mode (clock synchronous operation)
Master mode (clock synchronous operation).
The SPI mode can be selected with the MSTR, MODFEN, and SPMS bits in SPCR. Table 28.4 lists the relationship
between SPI modes and SPCR settings, and a description of each mode.
Table 28.4
Relationship between SPI modes and SPCR settings and description of each mode (1 of 2)
Mode
Slave (SPI
operation)
MSTR bit setting
MODFEN bit setting
0
Single-master (SPI
operation)
1
Multi-master (SPI
operation)
1
Slave (clock
synchronous
operation)
0
Master (clock
synchronous
operation)
1
0 or 1
0
1
0
0
SPMS bit setting
0
0
0
1
1
RSPCKn signal
Input
Output
Output/Hi-Z
Input
Output
MOSIn signal
Input
Output
Output/Hi-Z
Input
Output
MISOn signal
Output/Hi-Z
Input
Input
Output
Input
Hi-Z*1
Hi-Z*1
SSLn0 signal
Input
Output
Input
Hi-Z*1
SSLn1 to SSLn3 signals
Hi-Z*1
Output
Output/Hi-Z
Hi-Z*1
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Table 28.4
28. Serial Peripheral Interface (SPI)
Relationship between SPI modes and SPCR settings and description of each mode (2 of 2)
Slave (SPI
operation)
Mode
SSL polarity change
function
Single-master (SPI
operation)
Multi-master (SPI
operation)
Slave (clock
synchronous
operation)
Master (clock
synchronous
operation)
Supported
Supported
Supported
—
—
Transfer rate
Up to PCLKB/4
Up to PCLKB/2
Up to PCLKB/2
Up to PCLKB/4
Up to PCLKB/2
Clock source
RSPCKn input
On-chip baud rate
generator
On-chip baud rate
generator
RSPCKn input
On-chip baud rate
generator
One (CPHA = 1)
Two
Clock polarity
Two
Clock phase
Two
Two
Two
First transfer bit
MSB/LSB
Transfer data length
8 to 16, 20, 24, or 32 bits
RSPCK delay control
Not supported
Supported
Supported
Not supported
Supported
SSL negation delay
control
Not supported
Supported
Supported
Not supported
Supported
Next-access delay control
Not supported
Supported
Supported
Not supported
Supported
Transfer activation method
SSL input
active or
RSPCK oscillation
Transmit buffer is
written to on generation of transmit
buffer empty interrupt request
(SPTEF is 1)
Transmit buffer is
written to on generation of transmit
buffer empty interrupt request
(SPTEF is 1)
RSPCK oscillation
Transmit buffer is
written to on generation of a transmit
buffer empty interrupt request
(SPTEF is 1)
Supported*2
Supported*2
Transmit buffer empty
detection
Supported
Supported*2
Receive buffer full
detection
Overrun error detection
Supported*2
Supported*2, *4
Supported*2, *4
Supported*2,*3
Parity error detection
Mode fault error detection
Supported
(MODFEN = 1)
Not supported
Supported
Not supported
Not supported
Underrun error detection
Supported
Not supported
Not supported
Supported
Not supported
Note 1.
Note 2.
Note 3.
Note 4.
This function is not supported in this mode.
When the SPCR.TXMD bit is 1, detection of receiver buffer full, overrun error, and parity error are not performed.
When the SPCR2.SPPE bit is 0, parity error detection is not performed.
When the SPCR2.SCKASE bit is 1, overrun error detection does not proceed.
28.3.2
Controlling the SPI Pins
The SPI can switch pin states based on the MSTR, MODFEN, and SPMS bit settings in SPCR. Table 28.5 lists the
relationship between the pin states and bit settings. The I/O port settings must follow this relationship.
Table 28.5
Relationship between pin states and bit settings (1 of 2)
Mode
Pin
Pin state*2
Single-master mode (SPI operation)
(MSTR = 1, MODFEN = 0, SPMS = 0)
RSPCKn
CMOS output
SSLn0 to SSLn3
CMOS output
MOSIn
CMOS output
MISOn
Input
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Table 28.5
28. Serial Peripheral Interface (SPI)
Relationship between pin states and bit settings (2 of 2)
Mode
Pin
Pin state*2
Multi-master mode (SPI operation)
(MSTR = 1, MODFEN = 1, SPMS = 0)
RSPCKn*3
CMOS output/Hi-Z
SSLn0
Input
SSLn1 to SSLn3*3
CMOS output/Hi-Z
MOSIn*3
CMOS output/Hi-Z
Slave mode (SPI operation)
(MSTR = 0, SPMS = 0)
MISOn
Input
RSPCKn
Input
SSLn0
Input
SSLn1 to
Master mode (clock synchronous operation)
(MSTR = 1, MODFEN = 0, SPMS = 1)
Slave mode (clock synchronous operation)
(MSTR = 0, SPMS = 1)
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
SSLn3*5
Hi-Z*1
MOSIn
Input
MISOn*4
CMOS output/Hi-Z
RSPCKn
CMOS output
SSLn0 to SSLn3*5
Hi-Z*1
MOSIn
CMOS output
MISOn
Input
RSPCKn
SSLn0 to
Input
SSLn3*5
Hi-Z*1
MOSIn
Input
MISOn
CMOS output
This function is not supported in this mode.
SPI settings are not reflected in multiplexed pins for which the SPI function is not selected.
When SSLn0 is at the active level, the pin state is Hi-Z.
When SSLn0 is at the non-active level or the SPCR.SPE bit is 0, the pin state is Hi-Z.
These pins are available for use as I/O port pins.
The SPI in single-master mode (SPI operation) or multi-master mode (SPI operation) determines the MOSI signal values
during the SSL negation period based on the MOIFE and MOIFV bit settings in SPPCR, as listed in Table 28.6.
Table 28.6
MOSI signal value determination during SSL negation period
MOIFE bit
MOIFV bit
MOSIn signal value during SSL negation period
0
0, 1
Final data from previous transfer
1
0
Low
1
1
High
28.3.3
28.3.3.1
SPI System Configuration Examples
Single master and single slave with the MCU as a master
Figure 28.5 shows a single-master and single-slave SPI system configuration example where the MCU is the master. In
the single-master and single-slave configuration, the SSLn0 to SSLn3 outputs of the MCU (master) are not used. The
SSL input of the SPI slave is fixed to the low level, and the SPI slave stays in the selected state.*1
The MCU (master) drives the RSPCKn and MOSIn signals. The SPI slave drives the MISO signals.
Note 1. In the transfer format used when SPCMD0.CPHA is 0, the SSL signal for some slave devices cannot be fixed to
the active level. In this case, always connect the SSLni output of the MCU to the SSL input of the slave device.
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28. Serial Peripheral Interface (SPI)
This MCU (master)
SPI slave
RSPCKn
SPCK
MOSIn
MOSI
MISOn
MISO
SSLn0
SSL
SSLn1
SSLn2
SSLn3
Figure 28.5
Single-master and single-slave configuration example with the MCU as the master
28.3.3.2
Single master and single slave with the MCU as a slave
Figure 28.6 shows a single-master and single-slave SPI system configuration example where the MCU is the slave.
When the MCU is to operate as a slave, the SSLn0 pin is used as SSL input. The SPI master drives the RSPCK and
MOSI signals. The MCU (slave) drives the MISOn signals.*1
In the single-slave configuration in which the SPCMD0.CPHA bit is set to 1, the SSLn0 input of the MCU (slave) is
fixed to the low level, and the MCU (slave) stays in the selected state. This enables serial transfer (Figure 28.7).
Note 1. When SSLn0 is at the non-active level, the pin state is Hi-Z.
This MCU (slave)
SPI master
SPCK
RSPCKn
MOSI
MOSIn
MISO
MISOn
SSL
SSLn0
SSLn1
SSLn2
SSLn3
Figure 28.6
Single-master and single-slave configuration example with the MCU as a slave and CPHA = 0
SPI master
This MCU (slave, CPHA = 1)
MOSI
RSPCKn
RSPCK
MOSIn
MOSI
MISO
MISOn
MISO
SSL
SSLn0
SSL0
SPCK
SSLn1
SSL1
SSLn2
SSL2
SSL3
SSLn3
Figure 28.7
Single-master and single-slave configuration example with the MCU as a slave and CPHA = 1
28.3.3.3
Single master and multi-slave with the MCU as a master
Figure 28.8 shows a single-master/multi-slave SPI system configuration example where the MCU is the master. In the
example, the SPI system includes the MCU (master) and four slaves (SPI slaves 0 to 3).
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28. Serial Peripheral Interface (SPI)
The RSPCKn and MOSIn outputs of the MCU (master) are connected to the RSPCK and MOSI inputs of SPI slaves 0 to
3. The MISO outputs of SPI slaves 0 to 3 are all connected to the MISOn input of the MCU (master). SSLn0 to SSLn3
outputs of the MCU (master) are connected to the SSL inputs of SPI slave 0 to SPI slave 3, respectively.
The MCU (master) drives RSPCKn, MOSIn, and SSLn0 to SSLn3. Of the SPI slaves 0 to 3, the slave that receives lowlevel input into the SSL input drives the MISO signal.
This MCU (master)
SPI slave 0
RSPCKn
SPCK
MOSIn
MOSI
MISOn
MISO
SSLn0
SSL
SSLn1
SSLn2
SSLn3
SPI slave 1
SPCK
MOSI
MISO
SSL
SPI slave 2
SPCK
MOSI
MISO
SSL
SPI slave 3
SPCK
MOSI
MISO
SSL
Figure 28.8
Single-master and multi-slave configuration example with the MCU as a master
28.3.3.4
Single master and multi-slave with the MCU as a slave
Figure 28.9 shows a single-master and multi-slave SPI system configuration example where the MCU is a slave. In the
example, the SPI system includes an SPI master and two MCUs (slave X and slave Y).
The SPCK and MOSI outputs of the SPI master are connected to the RSPCKn and MOSIn inputs of the MCUs (slave X
and slave Y). The MISOn outputs of the MCUs (slave X and slave Y) are all connected to the MISO input of the SPI
master. SSLX and SSLY outputs of the SPI master are connected to the SSLn0 inputs of the MCUs (slave X and slave
Y), respectively.
The SPI master drives SPCK, MOSI, SSLX, and SSLY. The MCU slave (X or Y) that receives low-level input into the
SSLn0 input drives the MISOn signal.
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28. Serial Peripheral Interface (SPI)
SPI master
This MCU (slave X)
SPCK
RSPCKn
RSPCK
MOSI
MOSIn
MOSI
MISO
MISOn
MISO
SSLX
SSLn0
SSL0
SSLY
SSLn1
SSL1
SSLn2
SSL2
SSLn3
SSL3
This MCU (slave Y)
RSPCKn
RSPCK
MOSIn
MOSI
MISOn
MISO
SSLn0
SSL0
SSLn1
SSL1
SSLn2
SSL2
SSLn3
SSL3
Figure 28.9
Single-master and multi-slave configuration example with the MCU as a slave
28.3.3.5
Multi-master and multi-slave with the MCU as a master
Figure 28.10 shows a multi-master/multi-slave SPI system configuration example where the MCU is a master. In the
example, the SPI system includes two MCUs (master X and master Y) and two SPI slaves (SPI slave 1 and SPI slave 2).
The RSPCKn and MOSIn outputs of the MCUs (master X and master Y) are connected to the RSPCK and MOSI inputs
of SPI slaves 1 and 2. The MISO outputs of SPI slaves 1 and 2 are connected to the MISOn inputs of the MCUs (master
X and master Y). Any generic port Y output from the MCU (master X) is connected to the SSLn0 input of the MCU
(master Y). Any generic port X output of the MCU (master Y) is connected to the SSLn0 input of the MCU (master X).
The SSLn1 and SSLn2 outputs of the MCUs (master X and master Y) are connected to the SSL inputs of SPI slaves 1
and 2. In this configuration, because the system can be comprised solely of SSLn0 input, and SSLn1 and SSLn2 outputs
for slave connections, the SSLn3 output of the MCU is not required.
The MCU drives RSPCKn, MOSIn, SSLn1, and SSLn2 when the SSLn0 input level is high. When the SSLn0 input level
is low, the MCU detects a mode fault error, sets RSPCKn, MOSIn, SSLn1, and SSLn2 to Hi-Z, and releases the SPI bus
directly to the other master. The SPI slave 1 or 2 that receives low-level input into the SSL input drives MISO.
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28. Serial Peripheral Interface (SPI)
This MCU (master X)
This MCU (master Y)
RSPCK
RSPCKn
RSPCKn
MOSIn
MOSI
MOSIn
MISOn
MISO
MISOn
SSLn0
SSL0
SSLn0
SSLn1
SSL1
SSLn1
SSLn2
SSL2
SSLn2
SSLn3
SSL3
SSLn3
Port Y
Port X
SPI slave 1
SPCK
MOSI
MISO
SSL
SPI slave 2
SPCK
MOSI
MISO
SSL
Figure 28.10
Multi-master and multi-slave configuration example with the MCU as a master
28.3.3.6
Master and slave in clock synchronous mode with the MCU as a master
Figure 28.11 shows a master and slave in clock synchronous mode configuration where the MCU is a master. In the
master and slave clock synchronous mode, SSLn0 to SSLn3 of the MCU (master) are not used.
The MCU (master) drives RSPCKn and MOSIn. The SPI slave drives MISO.
This MCU (master)
SPI slave
RSPCKn
SPCK
MOSIn
MOSI
MISOn
MISO
SSLn0
SSL
SSLn1
SSLn2
SSLn3
Figure 28.11
Configuration example of master and slave in clock synchronous mode with the MCU as a master
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28.3.3.7
28. Serial Peripheral Interface (SPI)
Master and slave in clock synchronous mode with the MCU as slave
Figure 28.12 shows a master and slave in clock synchronous mode configuration where the MCU is a slave. When the
MCU is to operate as a slave in clock synchronous mode, the MCU (slave) drives MISOn and the SPI master drives
SPCK and MOSI. In addition, SSLn0 to SSLn3 of the MCU (slave) are not used.
The MCU (slave) can only execute serial transfer in the single-slave configuration when SPCMD0.CPHA is set to 1.
SPI master
This MCU (slave)
SPCK
RSPCKn
RSPCK
MOSI
MOSIn
MOSI
MISO
MISOn
MISO
SSL
SSLn0
SSL0
SSLn1
SSL1
SSLn2
SSL2
SSLn3
SSL3
Figure 28.12
28.3.4
Configuration example of master and slave in clock synchronous mode with the MCU as a slave
and CPHA = 1
Data Format
The data format of the SPI depends on the settings in SPI Command Register m (SPCMD0) and the parity enable bit in
SPI Control Register 2 (SPCR2.SPPE). Regardless of whether the ordering is MSB- or LSB-first, the SPI treats the range
from the LSB bit in the SPI Data Register (SPDR/SPDR_HA) to the bit corresponding to the selected data length as
transfer data.
This section shows the format of one frame of data before or after transfer.
(a)
Data format with parity disabled
When parity is disabled, transmission or reception of data proceeds with the length in bits selected in the SPI data length
setting bits in SPI Command Register 0 (SPCMD0.SPB[3:0]).
(b)
Data format with parity enabled
When parity is enabled, transmission or reception of data proceeds with the length in bits selected in the SPI data length
setting bits in SPI Command Register 0 (SPCMD0.SPB[3:0]). In this case, the last bit is a parity bit.
With parity disabled
D0
D1
D2
Dn-2
Dn-1
Dn
Dn-2
Dn-1
P
SPCMD0.SPB[3:0]
With parity enabled
D0
D1
D2
SPCMD0.SPB[3:0]
Figure 28.13
Data format with parity disabled and enabled
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28.3.4.1
28. Serial Peripheral Interface (SPI)
Operation when parity is disabled (SPCR2.SPPE = 0)
When parity is disabled, data for transmission is copied to the shift register with no prior processing. This section
describes the connection between the SPI Data Register (SPDR/SPDR_HA) and the shift register in terms of the
combination of MSB- or LSB-first order and data length.
(1)
MSB-first transfer with 32-bit data
Figure 28.14 shows operations by the SPI Data Register (SPDR) and the shift register in transfers with parity disabled, an
SPI data length of 32 bits, and MSB-first selected.
In transmission, bits T31 to T00 from the current stage of the transmit buffer are copied to the shift register. Data for
transmission is shifted out from the shift register in order from T31 to T30, and continuing to T00.
In reception, received data is shifted in bit by bit through bit 0 of the shift register. When bits R31 to R00 are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer.
Transfer start
Transmit buffer
Bit 31
T31 T30
T29 T28
T27
T26
T25
T24 T23
Bit 0
T08 T07 T06 T05 T04 T03 T02 T01 T00
Copy
Output
T08 T07 T06 T05 T04 T03 T02 T01 T00
T31 T30 T29 T28 T27 T26 T25 T24 T23
Bit 31
Shift register
Bit 0
Transfer end
Bit 31
Shift register
Bit 0
R08 R07 R06 R05 R04 R03 R02 R01 R00
R31 R30 R29 R28 R27 R26 R25 R24 R23
Input
Copy
R31 R30 R29 R28 R27 R26 R25 R24 R23
Bit 31
R08 R07 R06 R05 R04 R03 R02 R01 R00
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 28.14
(2)
MSB-first transfer with 32-bit data and parity disabled
MSB-first transfer with 24-bit data
Figure 28.15 shows operations by the SPI Data Register (SPDR) and the shift register in transfers with parity disabled, 24
bits as the SPI data length for an example that is not 32 bits, and MSB-first selected.
In transmission, the lower 24 bits (T23 to T00) from the current stage of the transmit buffer are copied to the shift
register. Data for transmission is shifted out from the shift register in order from T23 to T22, and continuing to T00.
In reception, received data is shifted in bit by bit through bit 0 of the shift register. When bits R23 to R00 are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. The
upper 8 bits of the transmit buffer are stored in the upper 8 bits of the receive buffer. Writing 0 to bits T31 to T24 during
transmission results in 0 being inserted in the upper 8 bits of the receive buffer.
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28. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 23
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T08
T07
T06
T05
T04
T03
T02
T01
T00
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 23
Shift register
Bit 31
Bit 0
Transfer end
Bit 24
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
Shift register
Bit 23
Bit 0
R08 R07 R06 R05 R04 R03 R02 R01 R00
R23
Input
Copy
T31
T30
T29
T28
T27
T26
Bit 31
T25
T24
Bit 24
R23
R08 R07 R06 R05 R04 R03 R02 R01 R00
Bit 23
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 28.15
(3)
MSB-first transfer with 24-bit data and parity disabled
LSB-first transfer with 32-bit data
Figure 28.16 shows operations by the SPI Data Register (SPDR) and the shift register in transfers with parity disabled, an
SPI data length of 32 bits, and LSB-first selected.
In transmission, bits T31 to T00 from the current stage of the transmit buffer are reordered bit by bit to obtain the order
T00 to T31 for copying to the shift register. Data for transmission is shifted out from the shift register in order from T00
to T01, and continuing to T31.
In reception, received data is shifted in bit by bit through bit 0 of the shift register. When bits R00 to R31 are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer.
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28. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T23
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
Bit 31
T06
T07
T08
Shift register
Bit 0
Transfer end
Bit 31
Shift register
R00 R01 R02 R03 R04 R05 R06 R07 R08
Bit 0
R23 R24 R25 R26 R27 R28 R29 R30 R31
Input
Copy
R31 R30 R29 R28 R27 R26 R25 R24 R23
Bit 31
R08 R07 R06 R05 R04 R03 R02 R01 R00
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 28.16
(4)
LSB-first transfer with 32-bit data and parity disabled
LSB-first transfer with 24-bit data
Figure 28.17 shows operations by the SPI Data Register (SPDR) and the shift register in transfers with parity disabled, 24
bits as the SPI data length, for an example that is not 32 bits, and LSB-first selected.
In transmission, the lower 24 bits (T23 to T00) from the current stage of the transmit buffer are reordered bit by bit to
obtain the order T00 to T23 for copying to the shift register. Data for transmission is shifted out from the shift register in
order from T00 to T01, and continuing to T23.
In reception, received data is shifted in bit by bit through bit [8] of the shift register. When the R00 to R23 bits are
collected after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive
buffer. At this time, the upper 8 bits of the transmit buffer are stored in the upper 8 bits of the receive buffer. Writing 0 to
bits T31 to T24 during transmission leads to 0 being inserted in the upper 8 bits of the receive buffer.
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28. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 0
T08
T07
T06
T05
T04
T03
T02
T01
T00
T23
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Input
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
R23
T24
T25
T26
T27
T28
T29
T30
T31
R08
R07
R06
R05
R04
R03
R02
R01
R00
Copy
T31
T30
T29
T28
T27
T26
Bit 31
T25
T24
R23
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 28.17
LSB-first transfer with 24-bit data and parity disabled
28.3.4.2
When parity is enabled (SPCR2.SPPE = 1)
When parity is enabled, the lowest-order bit of the data for transmission becomes a parity bit. Hardware calculates the
value of the parity bit.
(1)
MSB-first transfer with 32-bit data
Figure 28.18 shows operations by the SPI Data Register (SPDR) and the shift register in transfers with parity enabled, an
SPI data length of 32 bits, and MSB-first selected.
In transmission, the value of the parity bit (P) is calculated from bits T31 to T01. This replaces the final bit, T00, and the
whole is copied to the shift register. Data is transmitted in the order T31, T30, …, T01, and P.
In reception, received data is shifted in bit by bit through bit 0 of the shift register. When bits R31 to P are collected after
input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On copying
of data to the shift register, the data from R31 to P is checked for parity.
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28. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T08
T23
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
T31
T30
T29
T28
T27
T26
T25
T24
T23
Parity added
T08
T07
T06
T05
T04
T03
T02
T01
P
T08
T07
T06
T05
T04
T03
T02
T01
P
Copy
Output
T31
T30
T29
T28
T27
T26
T25
Bit 31
T24
T23
Shift register
Bit 0
Transfer end
Bit 31
Shift register
R31 R30 R29 R28 R27 R26 R25 R24 R23
Bit 0
R08 R07 R06 R05 R04 R03 R02 R01
P
R08 R07 R06 R05 R04 R03 R02 R01
P
Input
Copy
R31 R30 R29 R28 R27 R26 R25 R24 R23
Bit 31
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 28.18
(2)
MSB-first transfer with 32-bit data and parity enabled
MSB-first transfer with 24-bit data
Figure 28.19 shows operations by the SPI Data Register (SPDR) and the shift register in transfers with parity enabled, 24
bits as the SPI data length, for an example that is not 32 bits, and MSB-first selected.
In transmission, the value of the parity bit P is calculated from bits T23 to T01. This replaces the final bit, T00, and the
whole is copied to the shift register. Data is transmitted in the order T23, T22, …, T01, and P.
In reception, received data is shifted in bit by bit through bit [0] of the shift register. When bits R23 to P are collected
after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On
copying of data to the shift register, the data from R23 to P is checked for parity. The upper 8 bits of the transmit buffer
are stored in the upper 8 bits of the receive buffer. Writing 0 to bits T31 to T24 during transmission results in 0 being
inserted in the upper 8 bits of the receive buffer.
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28. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 23
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
T08
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity added
T31
T30
T29
T28
T27
T26
T25
T24
T23
T08
T07
T06
T05
T04
T03
T02
T01
P
T08
T07
T06
T05
T04
T03
T02
T01
P
Copy
Output
T31
T30
T29
T28
T27
T26
T25
T24
T23
Bit 23
Shift register
Bit 31
Bit 0
Transfer end
Bit 24
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
Shift register
Bit 23
R23
Bit 0
R08 R07 R06 R05 R04 R03 R02 R01
P
R08 R07 R06 R05 R04 R03 R02 R01
P
Input
Copy
T31
T30
T29
T28
Bit 31
T27
T26
T25
T24
Bit 24
R23
Bit 23
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 28.19
(3)
MSB-first transfer with 24-bit data and parity enabled
LSB-first transfer with 32-bit data
Figure 28.20 shows operations by the SPI Data Register (SPDR) and the shift register in transfers with parity enabled, an
SPI data length of 32 bits, and LSB-first selected.
In transmission, the value of the parity bit P is calculated from bits T30 to T00. This replaces the final bit, T31, and the
whole value is copied to the shift register. Data is transmitted in the order T00, T01, …, T30, and P.
In reception, received data is shifted in bit by bit through bit 0 of the shift register. When bits R00 to P are collected after
input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On copying
of data to the shift register, the data from R00 to P is checked for parity.
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28. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T23
T08
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
Parity added
Bit 31
P
T30
Bit 0
T29
T28
T27
T26
T25
T24
T23
T08
T07
T06
T05
T04
T03
T02
T01
T00
T23
T24
T25
T26
T27
T28
T29
T30
P
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Shift register
Bit 0
Transfer end
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R23 R24 R25 R26 R27 R28 R29 R30
R08
Bit 0
P
Input
Copy
P
R30 R29 R28 R27 R26 R25 R24 R23
Bit 31
R08 R07 R06 R05 R04 R03 R02 R01 R00
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 28.20
(4)
LSB-first transfer with 32-bit data and parity enabled
LSB-first transfer with 24-bit data
Figure 28.21 shows operations by the SPI Data Register (SPDR) and the shift register in transfers with parity enabled, 24
bits as the SPI data length, for an example that is not 32 bits, and LSB-first selected.
In transmission, the value of the parity bit P is calculated from bits T22 to T00. This replaces the final bit, T23, and the
whole value is copied to the shift register. Data is transmitted in the order T00, T01, …, T22, and P.
In reception, received data is shifted in bit by bit through bit 8 of the shift register. When bits R00 to P are collected after
input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer. On copying
of data to the shift register, the data from R00 to P is checked for parity. The upper 8 bits of the transmit buffer are stored
in the upper 8 bits of the receive buffer. Writing 0 to bits T31 to T24 during transmission results in 0 being inserted in the
upper 8 bits of the receive buffer.
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28. Serial Peripheral Interface (SPI)
Transfer start
Transmit buffer
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
T08
T23
Bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Parity calculated
Parity added
Bit 0
Bit 31
T31
T30
T29
T28
T27
T26
T25
T24
P
T08
T07
T06
T05
T04
T03
T02
T01
T00
P
T24
T25
T26
T27
T28
T29
T30
T31
Copy
Output
T00
T01
T02
T03
T04
T05
T06
T07
Bit 31
T08
Bit 0
Shift register
Transfer end
Input
Shift register
Bit 31
R00
R01
R02
R03
R04
R05
R06
R07
R08
Bit 0
P
T24
T25
T26
T27
T28
T29
T30
T31
R08
R07
R06
R05
R04
R03
R02
R01
R00
Copy
T31
T30
T29
T28
T27
Bit 31
T26
T25
T24
P
Receive buffer
Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
Figure 28.21
28.3.5
28.3.5.1
LSB-first transfer with 24-bit data and parity enabled
Transfer Formats
CPHA = 0
Figure 28.22 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMD0.CPHA bit is 0. Do
not perform clock synchronous operation (SPCR.SPMS bit is 1) when the SPI operates in slave mode (SPCR.MSTR = 0)
and the CPHA bit is 0. In Figure 28.22, RSPCKn (CPOL = 0) indicates the RSPCKn signal waveform when the
SPCMD0.CPOL bit is 0. RSPCKn (CPOL = 1) indicates the RSPCKn signal waveform when the CPOL bit is 1. The
sampling timing represents the timing at which the SPI fetches serial transfer data into the shift register. The I/O
directions of the signals depend on the SPI settings. For details, see section 28.3.2, Controlling the SPI Pins.
When the SPCMD0.CPHA bit is 0, the driving of valid data to the MOSIn and MISOn signals starts on an SSLni signal
assertion. The first RSPCKn signal change that occurs after the SSLni signal assertion becomes the first transfer data
fetch. After this, data is sampled on every 1 RSPCK cycle. The change timing for MOSIn and MISOn signals is 1/2
RSPCK cycle after the transfer data fetch timing. The CPOL bit setting does not affect the RSPCK signal operation
timing. It only affects the signal polarity.
t1 denotes the RSPCK delay, the period from an SSLni signal assertion to RSPCKn oscillation. t2 denotes the SSL
negation delay, the period from the termination of RSPCKn oscillation to an SSLni signal negation. t3 denotes the nextaccess delay, the period in which SSLni signal assertion is suppressed for the next transfer after the end of serial transfer.
t1, t2, and t3 are controlled by a master device running on the SPI system. For a description of t1, t2, and t3 when the SPI
of the MCU is in master mode, see section 28.3.10.1, Master mode operation.
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28. Serial Peripheral Interface (SPI)
Start
End
Serial transfer period
RSPCK
cycle
1
2
3
4
5
6
7
8
RSPCK
RSPCKn
(CPOL = 0)
(CPOL = 0)
RSPCKn
RSPCK
(CPOL==1)
1)
(CPOL
Sampling
timing
MOSIn
MOSI
MISOn
MISO
SSLni
SSLi
t1
Figure 28.22
SPI transfer format when CPHA = 0
28.3.5.2
CPHA = 1
t2
t3
Figure 28.23 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMD0.CPHA bit is 1.
However, when the SPCR.SPMS bit is 1, the SSLni signals are not used, and only the three RSPCKn, MOSIn, and
MISOn signals handle communications. In Figure 28.23, RSPCK (CPOL = 0) indicates the RSPCKn signal waveform
when the SPCMD0.CPOL bit is 0. RSPCK (CPOL = 1) indicates the RSPCKn signal waveform when the CPOL bit is 1.
The sampling timing represents the timing at which the SPI fetches serial transfer data into the shift register. The I/O
directions of the signals depend on the SPI mode (master or slave). For details, see section 28.3.2, Controlling the SPI
Pins.
When the SPCMD0.CPHA bit is 1, the driving of invalid data to the MISOn signal starts on an SSLni signal assertion.
The output of valid data to the MOSIn and MISOn signals commences on the first RSPCKn signal change that occurs
after the SSLni signal assertion. After this, data is updated every 1 RSPCK cycle. The transfer data fetch timing is 1/2
RSPCK cycle after the data update timing. The SPCMD0.CPOL bit setting does not affect the RSPCKn signal operation
timing. It only affects the signal polarity.
t1, t2, and t3 are the same as those when CPHA = 0. For a description of t1, t2, and t3 when the SPI of the MCU is in
master mode, see section 28.3.10.1, Master mode operation.
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28. Serial Peripheral Interface (SPI)
Start
RSPCK
cycle
End
Serial transfer period
1
2
3
4
5
6
7
8
RSPCK
RSPCKn
(CPOL
(CPOL==0)0)
RSPCKn
RSPCK
(CPOL==1)1)
(CPOL
Sampling
timing
MOSIn
MOSI
MISOn
MISO
SSLni
SSLi
t1
Figure 28.23
28.3.6
t2
t3
SPI transfer format when CPHA = 1
Data Transfer Modes
Full-duplex synchronous serial communications or transmit operations can only be selected in the communications
operating mode select bit (SPCR.TXMD). The SPDR/SPDR_HA access shown in Figure 28.24 and Figure 28.25
indicate the condition of access to the SPDR/SPDR_HA register, where W denotes a write cycle.
28.3.6.1
Full-duplex synchronous serial communications (SPCR.TXMD = 0)
Figure 28.24 shows an example operation where the communications operating mode select bit (SPCR.TXMD) is set to
0. In the example, the SPI performs an 8-bit serial transfer in which the SPCMD0.CPHA bit is 1 and the SPCMD0.CPOL
bit is 0. The numbers given for RSPCKn in the waveform represent the number of RSPCK cycles, meaning the number
of transferred bits.
SPDR_HA access
RSPCKn
(CPHA = 1, CPOL = 0)
Receive buffer
state
W
W
1
2
3
4
5
6
7
8
1
Empty
2
3
4
5
6
7
8
Full
SPIn_SPRI
(1)
SPRF
OVRF
(2)
Figure 28.24
Operation example when SPCR.TXMD = 0
The operation of the flags at timings shown in (1) and (2) in the figure is as follows:
(1) When a serial transfer ends with the SPDR/SPDR_HA receive buffer empty, the SPI generates a receive buffer full
interrupt request (SPIn_SPRI), the SPSR.SPRF flag sets to 1, and the received data is copied from the shift register
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28. Serial Peripheral Interface (SPI)
to the receive buffer.
(2) When a serial transfer ends with the SPDR/SPDR_HA receive buffer holding data that was received in the previous
serial transfer, the SPI sets the SPSR.OVRF flag to 1 and discards the received data in the shift register.
28.3.6.2
Transmit-only operations (SPCR.TXMD = 1)
Figure 28.25 shows an example operation where the communications operating mode select bit (SPCR.TXMD) is set to
1. In the example, the SPI performs an 8-bit serial transfer in which the SPCMD0.CPHA bit is 1 and the SPCMD0.CPOL
bit is 0. The numbers given for RSPCKn in the waveform represent the number of RSPCK cycles, meaning the number
of transferred bits.
W
SPDR_HA access
RSPCKn
(CPHA = 1, CPOL = 0)
TXMD
(TXMD = 1)
W
1
2
3
4
5
6
7
1
8
2
3
4
5
6
7
8
(1)
Receive buffer
state
Empty
SPIn_SPRI
(2)
SPRF
OVRF
(3)
Figure 28.25
Operation example when SPCR.TXMD = 1
The operation of the flags at timings shown in (1) to (3) in the figure is as follows:
(1) Make sure there is no data left in the receive buffer (SPSR.SPRF flag is 0) and the SPSR.OVRF flag is 0 before
entering the transmit-only operation mode (SPCR.TXMD = 1).
(2) When a serial transfer ends with the receive buffer of SPDR/SPDR_HA empty, if the transmit-only mode is selected
(SPCR.TXMD = 1), the SPSR.SPRF flag retains the value of 0, and the SPI does not copy the data in the shift
register to the receive buffer.
(3) Because the receive buffer of SPDR/SPDR_HA does not hold data that was received in the previous serial transfer,
even when a serial transfer ends, the SPSR.OVRF flag retains the value of 0, and the data in the shift register is not
copied to the receive buffer.
When performing transmit-only operations (SPCR.TXMD = 1), the SPI transmits but does not receive data. Therefore,
the SPSR.SPRF and SPSR.OVRF flags remain 0 at timings (1) to (3).
28.3.7
Transmit Buffer Empty and Receive Buffer Full Interrupts
Figure 28.26 and Figure 28.27 show examples of operations of the transmit buffer empty interrupt (SPIn_SPTI) and the
receive buffer full interrupt (SPIn_SPRI). The SPDR/SPDR_HA register accesses shown in these figures indicate the
condition of access to the SPDR/SPDR_HA register, where W denotes a write cycle and R a read cycle. In Figure 28.27,
the SPI performs an 8-bit serial transfer in which the SPCR.TXMD bit is 0, the SPCMD0.CPHA bit is 1, and the
SPCMD0.CPOL bit is 0. In Figure 28.26, the SPI performs an 8-bit serial transfer in which the SPCR.TXMD bit is 0, the
SPCMD0.CPHA bit is 0, and the SPCMD0.CPOL bit is 0. The numbers given for RSPCKn in the waveform represent
the number of RSPCK cycles, meaning the number of transferred bits.
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SPDR_HA access
28. Serial Peripheral Interface (SPI)
W
W
RSPCKn
(CPHA = 0, CPOL = 0)
Transmit buffer state
2
1
Empty
Full
(1)
3
4
R
5
6
Empty
7
8
1
2
3
4
Full
(2)
5
6
7
8
Empty
(3)
(4)
SPIn_SPTI
SPTEF
Receive buffer state
Empty
Full
Empty
(4)
Full
(5)
SPIn_SPRI
SPRF
Figure 28.26
Operation example of SPIn_SPTI and SPIn_SPRI interrupts when CPHA = 0 and CPOL = 0
SPDR_HA access
W
W
RSPCKn
(CPHA = 1, CPOL = 0)
Transmit buffer state
1
Empty
Full
(1)
2
3
R
4
5
Empty
(2)
6
7
8
1
2
3
4
Full
(3)
5
6
7
8
Empty
(4)
SPIn_SPTI
SPTEF
Receive buffer state
Empty
Full
(4)
Empty
Full
(5)
SPIn_SPRI
SPRF
Figure 28.27
Operation example of SPIn_SPTI and SPIn_SPRI interrupts when CPHA = 1 and CPOL = 0
The operation of the SPI at timings shown in (1) to (5) in the figure is as follows:
(1) When transmit data is written to SPDR/SPDR_HA and when the transmit buffer of SPDR/SPDR_HA is empty (data
for the next transfer is not set), the SPI writes data to the transmit buffer and clears the SPSR.SPTEF flag to 0.
(2) If the shift register is empty, the SPI copies the data in the transmit buffer to the shift register, generates a transmit
buffer empty interrupt request (SPIn_SPTI), and sets the SPSR.SPTEF flag to 1. How a serial transfer is started
depends on the mode of the SPI. For details, see section 28.3.10, SPI Operation, and section 28.3.11, Clock
Synchronous Operation.
(3) When transmit data is written to SPDR/SPDR_HA either by the transmit buffer empty interrupt routine, or by the
processing of transmit buffer empty using the SPTEF flag, the SPI writes data to the transmit buffer and clears the
SPTEF flag to 0. Because the serially transferred data is stored in the shift register, the SPI does not copy the data in
the transmit buffer to the shift register.
(4) When the serial transfer ends with the receive buffer of SPDR/SPDR_HA empty, the SPI copies the receive data in
the shift register to the receive buffer, generates a receive buffer full interrupt request (SPIn_SPRI), and sets the
SPRF flag to 1. Because the shift register is empty on completion of serial transfer, when the transmit buffer is full
before the serial transfer ends, the SPI sets the SPTEF flag to 1 and copies the data in the transmit buffer to the shift
register. Even when received data is not copied from the shift register to the receive buffer in an overrun error status,
on completion of the serial transfer, the SPI determines that the shift register is empty, so data transfer from the
transmit buffer to the shift register is enabled.
(5) When SPDR/SPDR_HA is read either by the receive buffer full interrupt routine or processing of the receive buffer
full using the SPRF flag, the receive data can be read.
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28. Serial Peripheral Interface (SPI)
If SPDR/SPDR_HA is written to when the transmit buffer holds untransmitted data (the SPTEF flag is 0), the SPI does
not update the data in the transmit buffer. When writing to SPDR/SPDR_HA, make sure to use a transmit buffer empty
interrupt request or to process a transmit buffer empty interrupt using the SPTEF flag. To use a transmit buffer empty
interrupt, set the SPTIE bit in SPCR to 1. If the SPI function is disabled (the SPCR.SPE bit is 0), set the SPTIE bit to 0.
When serial transfer ends with the receive buffer full (the SPRF flag is 1), the SPI does not copy data from the shift
register to the receive buffer, and it detects an overrun error (see section 28.3.8, Error Detection). To prevent a receive
data overrun error, read the received data using a receive buffer full interrupt request before the next serial transfer ends.
To use an SPI receive buffer full interrupt, set the SPCR.SPRIE bit to 1.
Transmission and reception interrupts or the associated IELSRm.IR flags in the ICU, where m is the interrupt vector
number, can be used to confirm the states of the transmit and receive buffers. Similarly, the SPTEF and SPRF flags can
be used to confirm the states of the transmit and receive buffers. See section 12, Interrupt Controller Unit (ICU), for the
interrupt vector numbers.
28.3.8
Error Detection
In normal SPI serial transfer, data written to the transmit buffer of SPDR/SPDR_HA is transmitted, and received data can
be read from the receive buffer of SPDR/SPDR_HA. If access is made to SPDR/SPDR_HA, an abnormal transfer might
occur, depending on the status of the transmit or receive buffer, or the status of the SPI at the beginning or end of serial
transfer.
If a non-normal transfer occurs, the SPI detects the event as an underrun error, overrun error, parity error, or mode fault
error. Table 28.7 lists the relationship between non-normal transfer operations and the SPI error detection function.
Table 28.7
Relationship between non-normal transfer operations and SPI error detection function
Occurrence condition
SPI operation
Error detection
1
SPDR/SPDR_HA is written when the transmit buffer is
full
The contents of the transmit buffer are kept
Write data is missing.
None
2
SPDR/SPDR_HA is read when the receive buffer is
empty
The contents of the receive buffer and
previously received data are output.
None
3
Serial transfer is started in slave mode when it is not
possible for the SPI to transmit data
Underrun error
4
Serial transfer terminates when the receive buffer is full
The contents of the receive buffer are kept
Missing receive data.
Overrun error
5
An incorrect parity bit is received during full-duplex
synchronous serial communications with the parity
function enabled
The parity error flag is asserted
Parity error
6
The SSLn0 input signal is asserted when the serial
transfer is idle in multi-master mode
Driving of the RSPCKn, MOSIn, and SSLn1 to
SSLn3 output signals is stopped
SPI function is disabled.
Mode fault error
7
The SSLn0 input signal is asserted during serial transfer
in multi-master mode
Serial transfer is suspended
Transmit or receive data is missing
Driving of the RSPCKn, MOSIn, and SSLn1 to
SSLn3 output signals is stopped
SPI function is disabled.
Mode fault error
8
The SSLn0 input signal is negated during serial transfer
in slave mode
Mode fault error
Serial transfer is suspended
Transmit or receive data is missing
Driving of the MISOA output signal is stopped
SPI function is disabled.
Serial transfer is suspended
Transmit or receive data is missing
Driving of the MISOn output signal is stopped
SPI function is disabled.
In operation 1 described in Table 28.7, the SPI does not detect an error. To prevent data omission during writes to SPDR/
SPDR_HA, write operations must be executed using a transmit buffer empty interrupt request (when SPSR.SPTEF is 1).
Similarly, the SPI does not detect an error in operation 2. To prevent extraneous data from being read, SPDR/SPDR_HA
read operations must be executed using an SPI receive buffer full interrupt request (when SPSR.SPRF is 1).
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28. Serial Peripheral Interface (SPI)
For information on:
Underrun errors, indicated in operation 3, see section 28.3.8.4, Underrun errors
Overrun errors, indicated in operation 4, see section 28.3.8.1, Overrun errors
Parity errors, indicated in operation 5, see section 28.3.8.2, Parity errors
Mode fault errors indicated in operations 6 to 8, see section 28.3.8.3, Mode fault errors
Transmit and receive interrupts, see section 28.3.7, Transmit Buffer Empty and Receive Buffer Full Interrupts.
28.3.8.1
Overrun errors
If a serial transfer ends when the receive buffer of SPDR/SPDR_HA is full, the SPI detects an overrun error and sets the
SPSR.OVRF flag to 1. When the OVRF flag is 1, the SPI does not copy data from the shift register to the receive buffer,
so the data before the occurrence of the error is saved in the receive buffer. To set the OVRF flag to 0, write 0 to it after
the CPU reads SPSR with the OVRF flag set to 1.
Figure 28.28 shows an example operation of the OVRF and SPRF flags. The SPSR and SPDR/SPDR_HA accesses
shown in the figure indicate the condition of access to SPSR and SPDR/SPDR_HA, respectively, where W denotes a
write cycle, and R a read cycle. In the example, the SPI performs an 8-bit serial transfer in which the SPCMD0.CPHA bit
is 1 and the SPCMD0.CPOL bit is 0. The numbers given for RSPCKn in the waveform represent the number of RSPCK
cycles, meaning the number of transferred bits.
R
SPSR access
SPDR/SPDR_HA access
W
R
RSPCKn
(CPHA = 1, CPOL = 0)
1
Receive buffer
state
2
3
4
5
6
7
8
1
Figure 28.28
3
4
5
6
7
8
Empty
SPRF
OVRF
2
Full
(2)
(3)
(4)
(1)
Operation example of OVRF and SPRF flags
The operation of the flags at timings shown in (1) to (4) in the figure is as follows:
(1) If a serial transfer terminates with the SPRF flag set to 1 (receive buffer full), the SPI detects an overrun error, and
sets the OVRF flag to 1. The SPI does not copy the data in the shift register to the receive buffer. Even when the
SPPE bit is 1, parity errors are not detected.
(2) When SPDR/SPDR_HA is read, the SPI outputs the data in the receive buffer. The SPRF flag is then set to 0. The
receive buffer becoming empty does not set the OVRF flag to 0.
(3) If the serial transfer ends with the OVRF flag set to 1 (overrun error occurred), the SPI does not copy data in the
shift register to the receive buffer (the SPRF flag is not set to 1). A receive buffer full interrupt is not generated.
Even when the SPPE bit is 1, parity errors are not detected. In an overrun error when the SPI does not copy the
received data from the shift register to the receive buffer, on termination of the serial transfer, the SPI determines
that the shift register is empty. This enables data transfer from the transmit buffer to the shift register.
(4) If 0 is written to the OVRF flag after SPSR is read when the OVRF flag is 1, the OVRF flag is set to 0.
The application can check for an overrun either by reading SPSR or by using an SPI error interrupt and reading SPSR.
When executing a serial transfer, make sure that overrun errors are detected early, for instance by reading SPSR
immediately after SPDR/SPDR_HA is read. If an overrun error occurs and the OVRF flag is set to 1, normal reception
cannot be performed until OVRF is set to 0.
When the RSPCK auto-stop function is enabled in master mode, an overrun error does not occur. Figure 28.29 and
Figure 28.30 show the clock stop waveform when a serial transfer continues while the receive buffer is full in master
mode.
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28. Serial Peripheral Interface (SPI)
Start
Start
End
Serial transfer period
End
Serial transfer period
R
SPDR/SPDR_HA access
RSPCK
cycle
1
2
3
4
5
6
7
RSPCK
cycle
8
1
2
3
4
5
6
7
8
Clock is stopped
RSPCKn
(CPOL = 0)
(2)
RSPCKn
(CPOL = 1)
Sampling
timing
MOSIn
MISOn
SSLni
t2
t1
Receive buffer
state
t3
t2
t1
Empty
Em
pty
Full
Full
SPRF
(Receive buffer full flag)
OVRF
(Overrun error flag)
Low
Receive buffer
read
(1)
SPI transfer format (CPHA = 1)
Output: Undefined (0 or 1)
Input: don’t care
t1: SPI clock delay register (SPCKD)
t2: SPI slave select negation delay register (SSLND)
t3: SPI next-access delay register (SPND)
Figure 28.29
Clock stop waveform when serial transfer continues while receive buffer is full in master mode
(CPHA = 1)
Start
Start
End
Serial transfer period
End
Serial transfer period
SPDR/SPDR_HA access
R
RSPCK
cycle
1
2
3
4
5
6
7
RSPCK
cycle
8
1
2
3
4
5
6
7
8
Clock is stopped
RSPCKn
(CPOL = 0)
(2)
RSPCKn
(CPOL = 1)
Sampling
timing
MOSIn
MISOn
SSLni
t2
t1
Receive buffer
state
Empty
t3
t2
t1
Em
pty
Full
Full
SPRF
(Receive buffer full flag)
OVRF
(Overrun error flag)
Low
SPI transfer format (CPHA = 0)
Receive buffer
read
(1)
t1: SPI clock delay register (SPCKD)
Output: Undefined (0 or 1)
Input: don’t care
t2: SPI slave select negation delay register (SSLND)
t3: SPI next-access delay register (SPND)
Figure 28.30
Clock stop waveform when serial transfer continues while receive buffer is full in master mode
(CPHA = 0)
The operation of the flags at timings shown in (1) and (2) in the figure is as follows:
(1) When the receive buffer is full, an overrun error does not occur because the RSPCK clock is stopped.
(2) If SPDR/SPDR_HA is read while the clock is stopped, data in the receive buffer can be read. The RSPCK clock
restarts after reading the receive buffer (after SPSR.SPRF sets to 0).
28.3.8.2
Parity errors
When full-duplex synchronous serial communications is performed with the SPCR.TXMD bit set to 0 and the
SPCR2.SPPE bit set to 1, the SPI checks for parity errors when serial transfer ends. On detecting a parity error in the
received data, the SPI sets the SPSR.PERF flag to 1. Because the SPI does not copy data in the shift register to the
receive buffer when the SPSR.OVRF flag is set to 1, parity error detection is not performed for the received data. To set
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28. Serial Peripheral Interface (SPI)
the PERF flag to 0, write 0 to the PERF flag after the SPSR register is read with the PERF flag set to 1.
Figure 28.31 shows an example operation of the OVRF and PERF flags. The SPSR access shown in Figure 28.31
indicates the condition of access to the SPSR register, where W denotes a write cycle, and R a read cycle. In the example
of Figure 28.31, full-duplex synchronous serial communications is performed while the SPCR.TXMD bit is 0 and the
SPCR2.SPPE bit is 1. The SPI performs an 8-bit serial transfer in which the SPCMD0.CPHA bit is 1 and the
SPCMD0.CPOL bit is 0. The numbers given for RSPCKn in the waveform represent the number of RSPCK cycles,
meaning the number of transferred bits.
SPSR access
R
W
RSPCKn
(CPHA = 1, CPOL = 0)
1
2
PERF
3
4
5
6
7
8
1
(1)
OVRF
Figure 28.31
2
3
4
5
6
7
8
(2)
(3)
Operation example of PERF flag
The operation of the flags shown in steps (1) to (3) in the figure is as follows:
(1) If a serial transfer terminates with the SPI not detecting an overrun error, the SPI copies the data in the shift register
to the receive buffer. The SPI checks the received data and sets the PERF flag to 1 if a parity error is detected.
(2) If 0 is written to the PERF flag after the SPSR register is read when the PERF flag is 1, the PERF flag sets to 0.
(3) When the SPI detects an overrun error and serial transfer is terminated, the data in the shift register is not copied to
the receive buffer. The SPI does not perform parity error detection at this time.
The application can check for a parity error by reading SPSR or by using an SPI error interrupt and reading SPSR. When
executing a serial transfer, make sure that parity errors are detected early, for instance by reading SPSR.
28.3.8.3
Mode fault errors
The SPI operates in multi-master mode when the SPCR.MSTR bit is 1, the SPCR.SPMS bit is 0, and the
SPCR.MODFEN bit is 1. If the active level is input for the SSLn0 input signal of the SPI in multi-master mode, the SPI
detects a mode fault error regardless of the status of the serial transfer, and it sets the SPSR.MODF flag to 1. The active
level of the SSLn0 signal is determined by the SSLP.SSL0P bit.
When the MSTR bit is 0, the SPI operates in slave mode. The SPI detects a mode fault error if the MODFEN bit of the
SPI in slave mode is 1, and the SPMS bit is 0, and if the SSLn0 input signal is negated during the serial transfer period
(from the time the driving of valid data is started to the time the final valid data is fetched).
On detecting a mode fault error, the SPI stops driving the output signals and clears the SPCR.SPE bit to 0 (see section
28.3.9, Initializing SPI). For multi-master configuration, detection of a mode fault error is used to stop the driving of the
output signals and the SPI function, which allows the master to be released.
Mode fault errors can be checked by reading SPSR or by using an SPI error interrupt and reading SPSR. Detecting modefault errors without using the SPI error interrupt requires polling of SPSR.
When the MODF flag is 1, writing 1 to the SPE bit is ignored by the SPI. To enable the SPI function after the detection of
a mode fault error, the MODF flag must be set to 0.
28.3.8.4
Underrun errors
When a serial transfer begins with the SPCR.MSTR bit set to 0 (slave mode), the SPCR.SPE bit is set to 1, and the
transmission data not prepared, the SPI detects an underrun error. The SPI then sets the SPSR.MODF flag and
SPSR.UDRF flag to 1. On detecting an underrun error, the SPI stops the driving of output signals and clears the
SPCR.SPE bit to 0 (see section 28.3.9, Initializing SPI).
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28. Serial Peripheral Interface (SPI)
Underrun errors can be checked by reading SPSR or by using an SPI error interrupt and reading SPSR. Detecting
underrun errors without using the SPI error interrupt requires polling of SPSR.
When the MODF flag is 1, writing 1 to the SPE bit is ignored by the SPI. To enable the SPI function after the detection of
an underrun error, the MODF flag must be set to 0.
28.3.9
Initializing SPI
If 0 is written to the SPCR.SPE bit or the SPI sets the SPE bit to 0 because it detected a mode fault error or an underrun
error, the SPI disables the SPI function and initializes some of the module functions. When a system reset occurs, the SPI
initializes all of the module functions. The following describes initialization by clearing of the SPCR.SPE bit and by a
system reset.
28.3.9.1
Initialization by clearing the SPE bit
When the SPCR.SPE bit is set to 0, the SPI performs the following initialization:
Suspends any serial transfer that is being executed
Stops the driving of output signals (Hi-Z) in slave mode
Initializes the internal state of the SPI
Initializes the transmit buffer of the SPI (SPSR.SPTEF flag is set to 1).
Initialization by clearing of the SPE bit does not initialize the control bits of the SPI. For this reason, the SPI can be
started in the same transfer mode in use before initialization when the SPE bit is set to 1 again.
The SPSR.SPRF, SPSR.OVRF, SPSR.MODF, SPSR.PERF, and SPSR.UDRF flags are not initialized. Therefore, even
after the SPI is initialized, data from the receive buffer can be read to check the error status during an SPI transfer.
The transmit buffer is initialized to an empty state (SPSR.SPTEF flag sets to 1). Therefore, if the SPCR.SPTIE bit is set
to 1 after SPI initialization, a transmit buffer empty interrupt is generated. To disable any transmit buffer empty interrupts
when the SPI is initialized, write 0 to the SPTIE bit at the same time as writing 0 to the SPE bit.
28.3.9.2
Initialization by system reset
A system reset completely initializes the SPI by initializing all bits that control the SPI, the status bits, and the data
registers, in addition to the actions described in section 28.3.9.1, Initialization by clearing the SPE bit.
28.3.10
28.3.10.1
SPI Operation
Master mode operation
The only difference between single-master and multi-master mode operation is the use of mode fault error detection (see
section 28.3.8, Error Detection). In single-master mode, the SPI does not detect mode fault errors, while in multi-master
mode, it does. This section explains operations that are common to both modes.
(1)
Starting serial transfer
The SPI updates the data in the transmit buffer (SPTX) when data is written to the SPI Data Register (SPDR/SPDR_HA)
with the SPI transmit buffer being empty (data for the next transfer is not set) (SPSR.SPTEF flag is 1). When the shift
register is empty, the SPI copies data from the transmit buffer to the shift register and starts serial transfer. On copying
transmit data to the shift register, the SPI changes the status of the shift register to full, and on termination of serial
transfer, it changes the status of the shift register to empty. The status of the shift register cannot be referenced.
For details on the SPI transfer format, see section 28.3.5, Transfer Formats. The polarity of the SSLni output pins
depends on the SSLP register settings.
(2)
Terminating serial transfer
Regardless of the SPCMD0.CPHA bit setting, the SPI terminates a serial transfer after transmitting an RSPCKn edge
associated with the final sampling timing. If free space is available in the receive buffer (SPRX) (SPSR.SPRF flag is 0),
on termination of serial transfer, the SPI copies data from the shift register to the receive buffer of the SPDR/SPDR_HA
register.
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28. Serial Peripheral Interface (SPI)
The final sampling timing varies depending on the bit length of the transfer data. In master mode, the SPI data length
depends on the SPCMD0.SPB[3:0] bit setting. The polarity of the SSLni output pin depends on the SSLP register
settings.
For details on the SPI transfer format, see section 28.3.5, Transfer Formats.
(3)
RSPCK delay (t1)
The RSPCK delay in master mode depends on the SPCMD0.SCKDEN bit setting and the SPCKD register setting. The
SPI determines an RSPCK delay during serial transfer using the SPCMD0.SCKDEN bit and SPCKD, as shown in Table
28.8. For a definition of RSPCK delay, see section 28.3.5, Transfer Formats.
Table 28.8
Relationship between the SCKDEN bit, SPCKD, and RSPCK delays
SPCMD0.SCKDEN bit
SPCKD.SCKDL[2:0] bits
RSPCK delay
0
000b to 111b
1 RSPCK
1
000b
1 RSPCK
001b
2 RSPCK
010b
3 RSPCK
011b
4 RSPCK
100b
5 RSPCK
101b
6 RSPCK
110b
7 RSPCK
111b
8 RSPCK
(4)
SSL negation delay (t2)
The SSL negation delay in master mode depends on the SPCMD0.SLNDEN bit setting and the SSLND register setting.
The SPI determines the SSL negation delay during serial transfer using the SPCMD0.SLNDEN bit and SSLND, as
shown in Table 28.9. For a definition of SSL negation delay, see section 28.3.5, Transfer Formats.
Table 28.9
Relationship between the SLNDEN bit, SSLND, and SSL degation delays
SPCMD0.SLNDEN bit
SSLND.SLNDL[2:0] bits
SSL negation delay
0
000b to 111b
1 RSPCK
1
000b
1 RSPCK
001b
2 RSPCK
(5)
010b
3 RSPCK
011b
4 RSPCK
100b
5 RSPCK
101b
6 RSPCK
110b
7 RSPCK
111b
8 RSPCK
Next-access delay (t3)
The next-access delay in master mode depends on the SPCMD0.SPNDEN bit setting and the SPND register setting. The
SPI determines the next-access delay during serial transfer using the SPCMD0.SPNDEN bit and SPND, as shown in
Table 28.10. For a definition of next-access delay, see section 28.3.5, Transfer Formats.
Table 28.10
Relationship between the SPNDEN bit, SPND, and next-access delays (1 of 2)
SPCMD0.SPNDEN bit
SPND.SPNDL[2:0] bits
Next-access delay
0
000b to 111b
1 RSPCK + 2 PCLKB
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Table 28.10
28. Serial Peripheral Interface (SPI)
Relationship between the SPNDEN bit, SPND, and next-access delays (2 of 2)
SPCMD0.SPNDEN bit
SPND.SPNDL[2:0] bits
Next-access delay
1
000b
1 RSPCK + 2 PCLKB
001b
2 RSPCK + 2 PCLKB
010b
3 RSPCK + 2 PCLKB
011b
4 RSPCK + 2 PCLKB
100b
5 RSPCK + 2 PCLKB
101b
6 RSPCK + 2 PCLKB
110b
7 RSPCK + 2 PCLKB
111b
8 RSPCK + 2 PCLKB
(6)
Initialization flow
The flow in Figure 28.32 provides an example of SPI initialization when the SPI is used in master mode. For information
on setting up the Interrupt Controller Unit, DTC, and I/O Ports, see the individual block descriptions.
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Start of initialization in master mode
Set SPI Slave Select Polarity register (SSLP)
Set SPI Pin Control Register (SPPCR)
Set SPI Bit Rate Register (SPBR)
• Sets polarity of SSL signal
• Sets output mode
• Sets MOSI signal value when transfer is in idle state
• Sets transfer bit rate
Set SPI Data Control Register (SPDCR)
Set SPI Clock Delay register (SPCKD)
Set SPI Slave Select Negation Delay register
(SSLND)
Set SPI Next-access Delay register (SPND)
Set SPI Control Register 2 (SPCR2)
Set SPI Command Register 0 (SPCMD0)
Set interrupt controller
Set DTC
• Sets RSPCK delay
• Sets SSL negation delay
• Sets next-access delay
• Sets parity function
• Sets interrupt mask
• Sets SSL signal level
• Sets RSPCK delay enable
• Sets SSL negation delay enable
• Sets next-access delay enable
• Sets MSB- or LSB-first
• Sets data length
• Sets transfer bit rate
• Sets clock phase
• Sets clock polarity
• Sets SSL assertion signal
(When using an interrupt)
(When using the DTC)
Set I/O ports
Set SPI Control Register (SPCR)
• Sets master mode
• Sets interrupt mask
• Sets SPI mode
Read SPI Control Register (SPCR)
End of initialization in master mode
Figure 28.32
(7)
Example of initialization flow in master mode for SPI operation
Software processing flow
Figure 28.33 to Figure 28.35 show example flows of software processing.
(a)
Transmit processing flow
When transmitting data and when the idle interrupt (SPIn_SPII) is enabled, the CPU is notified of the completion of data
transmission after the last data write for transmission.
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Transmission processing
Start
transmission
processing
Pre-transfer processing
End of initial settings
Clear the SPSR.MODF, OVRF,
PERF and UDRF flags
[1] Clear error sources
Transmit buffer
empty interrupt (SPIn_SPTI)?
or
*1
SPSR.SPTEF = 1?
No
Yes
Set SPCR2.SPIIE = 0
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
transmission
processing
[2] Disable idle interrupts
[3] Set the SPE bit to enabled
Enable the required interrupts at the
same time.
Using the interrupt is prohibited if
the flag for polling is used.
Proceed to
reception
processing
Proceed to
error
processing
Note 1. Proceed to transmission processing for writing data
to SPDR/SPDR_HA after checking that the
transmit buffer is empty by reading the
SPSR.SPTEF flag, if the flag for polling is used.
Note 2. Setting the idle interrupt is prohibited
(SPCR2.SPIIE = 0) if the flag for polling is
used.
Note 3. Wait more than 1 PCLKB after writing data
for
transmission to SPDE and before starting to
poll PSR.IDLNF, if the flag for polling is used.
Figure 28.33
(b)
Write transmission data to
SPDR/SPDR_HA
Have the last of the
data been written?
No
Yes
SPCR.SPTIE = 0,
SPCR2.SPIIE
=1
Yes
or
SPCR.SPTIE = 0,
*2
SPCR2.SPIIE = 0
Idle interrupt (SPIn_SPII)
or
*3
SPSR.IDLNF = 0?
No
Yes
SPCR.SPE = 0,
SPCR2.SPIIE = 0
End of
transmission
processing
Transmission flow in master mode
Receive processing flow
The SPI does not handle receive-only operations, therefore processing for transmission is required.
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Pre-transfer processing
Reception processing
Start reception
processing
End of initial settings
Clear the SPSR.MODF, OVRF,
PERF, and UDRF flags
Set SPCR2.SPIIE = 0
[2] Disable Idle interrupts
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
processing for
transmission
[1] Clear error sources
[3] Set the SPE bit to enabled
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the flag for polling is used.
Proceed to
processing for
reception
Proceed to
error
processing
Receive buffer
full interrupt (SPIn_SPRI)?
or
SPSR.SPRF = 1?
Yes
Read receive data from SPDR/SPDR_HA
No
Has the last of the
data been read?
Yes
SPCR.SPRIE = 0
End of reception
processing
Figure 28.34
(c)
No
[4] Prohibited operation is handled in
transmission processing
Reception flow in master mode
Error processing flow
The SPI detects mode fault errors, underrun errors, overrun errors, and parity errors. When a mode fault error is
generated, the SPCR.SPE bit is automatically cleared, stopping operations for transmission and reception. For errors
from other sources, the SPCR.SPE bit is not cleared and operations for transmission and reception continue. Renesas
recommends clearing the SPCR.SPE bit to stop operations for errors other than mode fault errors.
When an error is detected by using interrupt, clear the ICU.IELSRm.IR flag in the error processing routine. If this is not
done, the ICU.IELSRm.IR flag might continue to indicate the transmit buffer empty or the receive buffer full interrupt
request. If the SPRI interrupt request is indicated, read the receive buffer and initialize the sequencer in the SPI.
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Error processing
Pre-transfer processing
Start error
processing
End of initial settings
Clear the SPSR.MODF, OVRF,
PERF, and UDRF flags
[1] Clear error sources
No
Error interrupt (SPIn_SPEI)
or
SPSR.MODF/OVRF/PERF/UDRF
= 1?
Yes
Set SPCR2.SPIIE = 0
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
transmission
processing
[2] Disable idle interrupts
[3] Set the SPE bit to “enabled”
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the flag for polling is used.
Proceed to
reception
processing
Proceed to
error
processing
SPSR.MODF = 0
No
Yes
No
SSLn0 = inactive?
SPCR.SPE = 0
[4]
Set SPCR.SPTIE = 0,
SPRIE = 0, SPEIE = 0,
and SPCR2.SPIIE = 0
Error processing
[4] Read the port register and confirm that
the SSLn0 pin is at the inactive level
[5]
[5] Clear the ICU.IELSRm.IR flag
associated with SPIn_SPTI,
SPIn_SPRI, and other relevant
signals
Clear the SPSR.MODF, OVRF,
PERF and UDRF flags
Repeat the transfer processing
End of error
processing
Figure 28.35
Error processing flow in master mode
28.3.10.2
Slave mode operation
(1)
[6] Run the initialization processing again
The order of processing can be changed
Starting a serial transfer
When the SPCMD0.CPHA bit is 0, if the SPI detects an SSLn0 input signal assertion, the SPI must drive valid data to the
MISOn output signal. For this reason, when the CPHA bit is 0, the assertion of the SSLn0 input signal triggers the start of
a serial transfer.
When the CPHA bit is 1, if the SPI detects the first RSPCKn edge in an SSLn0 signal asserted condition, the SPI must
drive valid data to the MISOn output signal. For this reason, when the CPHA bit is 1, the first RSPCKn edge in an SSLn0
signal asserted condition triggers the start of a serial transfer.
Regardless of the CPHA bit setting, the SPI drives the MISOn output signal on SSLn0 signal assertion. The data that is
output by the SPI is either valid or invalid, depending on the CPHA bit setting.
For details on the SPI transfer format, see section 28.3.5, Transfer Formats. The polarity of the SSLn0 input signal
depends on the SSLP.SSL0P setting.
(2)
Terminating a serial transfer
Regardless of the SPCMD0.CPHA bit, the SPI terminates the serial transfer after detecting an RSPCKn edge
corresponding to the final sampling timing. When free space is available in the receive buffer (the SPSR.SPRF flag is 0),
on termination of serial transfer the SPI copies received data from the shift register to the receive buffer of the SPDR/
SPDR_HA register. On termination of a serial transfer, the SPI changes the status of the shift register to empty, regardless
of the receive buffer state. A mode fault error occurs if the SPI detects an SSLn0 input signal negation from the
beginning of serial transfer to the end of serial transfer (see section 28.3.8, Error Detection).
The final sampling timing changes depending on the bit length of transfer data. In slave mode, the SPI data length
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28. Serial Peripheral Interface (SPI)
depends on the SPCMD0.SPB[3:0] bit setting. The polarity of the SSLn0 input signal depends on the SSLP.SSL0P bit
setting. For details on the SPI transfer format, see section 28.3.5, Transfer Formats.
(3)
Notes on single-slave operations
If the SPCMD0.CPHA bit is 0, the SPI starts serial transfers when it detects the assertion edge for an SSLn0 input signal.
In the type of configuration shown in Figure 28.7 as an example, if the SPI is used in single-slave mode, the SSLn0
signal is fixed at the active state. Therefore, when the CPHA bit is set to 0, the SPI cannot correctly start a serial transfer.
To correctly execute transmit and receive operations by the SPI in slave mode when the SSLn0 input signal is fixed at the
active state, the CPHA bit must be set to 1. Do not fix the SSLn0 input signal if there is a requirement for setting the
CPHA bit to 0.
(4)
Initialization flow
Figure 28.36 shows an example of initialization flow for SPI operation when the SPI is in slave mode. For information
on how to set up the Interrupt Controller Unit, DTC, and I/O Ports, see the individual block descriptions.
Start of initialization in
slave mode
Set SPI slave select polarity
register (SSLP)
• Sets polarity of SSLn0 input signal
Set SPI data control
register (SPDCR)
Set SPI control register 2 (SPCR2)
• Sets parity function
• Sets interrupt mask
Set SPI command register 0
(SPCMD0)
• Sets MSB- or LSB-first
• Sets data length
• Sets clock phase
• Sets clock polarity
Set interrupt controller
(When using an interrupt)
Set DTC
Set I/O ports
(When using the DTC)
• Sets slave mode
• Sets mode fault error detection
• Sets interrupt mask
• Sets SPI mode
Set SPI control register
(SPCR)
Read SPI control register (SPCR)
End of initialization in
slave mode
Figure 28.36
(5)
Example of initialization flow in slave mode for SPI operation
Software processing flow
Figure 28.37 to Figure 28.39 show example flows of software processing.
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(a)
28. Serial Peripheral Interface (SPI)
Transmit processing flow
Pre-transfer processing
Transmission processing
Start
transmission
processing
End of initial settings
Clear the SPSR.MODF, OVRF,
UDRF, and PERF flags
[1] Clear error sources
[2] Disable idle interrupts
Set SPCR2.SPIIE = 0
[3] Set the SPE bit to enabled
Enable the required interrupts at the
same time.
Using the interrupt is prohibited if
the flag for polling is used.
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
transmission
processing
Proceed to
reception
processing
Proceed to
error
processing
Transmit buffer empty
interrupt (SPIn_SPTI)?
or
SPSR.SPTEF = 1? *1
No
Yes
Write data for transmission to
SPDR/SPDR_HA
Have the last of the
data been written?
No
Yes
End of
transmission
processing
Note 1. Proceed to transmission processing for data writes
to SPDR/SPDR_HA after checking transmit buffer
empty by reading SPSR.SPTEF flag, if the flag for
polling is used.
Figure 28.37
(b)
Transmission flow in slave mode
Receive processing flow
The SPI does not handle receive-only operation, therefore processing for transmission is required.
Pre-transfer processing
Reception processing
Start reception
processing
End of initial settings
Clear the SPSR.MODF, OVRF,
UDRF, and PERF flags
Set SPCR2.SPIIE = 0
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
transmission
processing
[1] Clear error sources
[2] Disable idle interrupts
[3] Set the SPE bit to enabled.
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the flag for polling is used.
Proceed to
reception
processing
Proceed to
error
processing
Receive buffer full
interrupt (SPIn_SPRI)?
or
SPSR.SPRF = 1?
No
Yes
Read receive data from SPDR/SPDR_HA
Has the last of the
data been read?
No
Yes
SPCR.SPRIE = 0
End of reception
processing
Figure 28.38
Reception flow in slave mode
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(c)
28. Serial Peripheral Interface (SPI)
Error processing flow
In slave operation, even when a mode-fault error is generated, the SPSR.MODF flag can be cleared regardless of the
state of the SSLn0 pin.
When an error is detected by using an interrupt, clear the ICU.IELSRm.IR flag in the error processing routine. If this is
not done, the ICU.IELSRm.IR flag might continue to indicate the transmit buffer empty or receive buffer full interrupt
request. If the receive buffer full request is indicated, read the receive buffer and initialize the sequencer in the SPI.
Error processing
Pre-transfer processing
Start error
processing
End of initial settings
Clear the SPSR.MODF, OVRF,
UDRF, and PERF flags
[1] Clear error sources
Error interrupt
(SPIn_SPEI) or
SPSR.MODF/OVRF/PERF
=1?
No
Yes
Set SPCR2.SPIIE = 0
Set SPCR.SPE = 1
Set SPTIE, SPRIE, and SPEIE
Proceed to
transmission
processing
[2] Disable idle interrupts
[3] Set the SPE bit to enabled
Enable the required interrupts at
the same time.
Using the interrupt is prohibited if
the flag for polling is used.
Proceed to
reception
processing
Proceed to
error
processing
SPSR.MODF = 0
No
Yes
SPCR.SPE = 0
Set SPCR.SPTIE = 0,
SPRIE = 0, SPEIE = 0,
and SPCR2.SPIIE = 0
Error processing
[4]
[4] Clear the ICU.IELSRm.IR flag
associated with SPTI, SPRI, and
other relevant signals
Clear the SPSR.MODF, UDRF,
OVRF, and PERF flags
Repeat the transfer processing
End of error
processing
Figure 28.39
28.3.11
[5] Run the initialization processing again
The order of processing can be changed
Error processing flow for slave mode
Clock Synchronous Operation
Setting the SPCR.SPMS bit to 1 selects clock synchronous operation of the SPI. In clock synchronous operation, the
SSLni pin is not used, and the RSPCKn, MOSIn, and MISOn pins handle communications. All SSLni pins are available
as I/O port pins.
Although clock synchronous operation does not require the use of the SSLni pin, operation of the module is the same as
in SPI operation. In both master and slave operations, communications can be performed with the same flow as in SPI
operation. However, mode fault errors are not detected because the SSLni pin is not used.
Additionally, do not perform operation if clock synchronous operation enabled when the SPCMD0.CPHA bit is set to 0
in slave mode (SPCR.MSTR = 0).
28.3.11.1
(1)
Master mode operation
Starting serial transfer
The SPI updates the data in the transmit buffer (SPTX) of SPDR/SPDR_HA when data is written to the SPDR/
SPDR_HA register with the transmit buffer being empty, that is, data for the next transfer is not set and the SPSR.SPTEF
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28. Serial Peripheral Interface (SPI)
flag is 1. When the shift register is empty after data is written to SPDR/SPDR_HA, the SPI copies data from the transmit
buffer to the shift register and starts serial transmission. On copying transmit data to the shift register, the SPI changes the
status of the shift register to full, and on termination of serial transfer, it changes the status of the shift register to empty.
The status of the shift register cannot be referenced.
Transfer in clock synchronous operation is conducted without the SSLn0 output signal. For details on the SPI transfer
format, see section 28.3.5, Transfer Formats.
(2)
Terminating serial transfer
The SPI terminates the serial transfer after transmitting an RSPCKn edge corresponding to the sampling timing. If free
space is available in the receive buffer (the SPSR.SPRF flag is 0), on termination of serial transfer, the SPI copies data
from the shift register to the receive buffer of the SPI Data Register (SPDR/SPDR_HA).
The final sampling timing varies depending on the bit length of transfer data. In master mode, the SPI data length
depends on the SPCMD0.SPB[3:0] bit setting.
Transfer in clock synchronous operation is conducted without the SSLn0 output signal. For details on the SPI transfer
format, see section 28.3.5, Transfer Formats.
(3)
Initialization flow
Figure 28.40 shows an example of initialization flow for clock synchronous operation when the SPI is in master mode.
For information on how to set up the Interrupt Controller Unit, DTC, and I/O Ports, see the individual block descriptions.
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28. Serial Peripheral Interface (SPI)
Start of initialization in
master mode
Set SPI Pin Control Register
(SPPCR)
Set SPI Bit Rate Register (SPBR)
• Sets MOSI signal value when transfer is in idle state
• Sets transfer bit rate
Set SPI Data Control Register
(SPDCR)
Set SPI clock delay register
(SPCKD)
Set SPI Slave Select Negation
Delay Register (SSLND)
• Sets RSPCK delay
• Sets SSL negation delay
Set SPI Next-access Delay Register
(SPND)
• Sets next-access delay
Set SPI Control Register 2 (SPCR2)
• Sets parity function
• Sets interrupt mask
Set SPI Command Registers 0
(SPCMD0)
Set interrupt controller
Set DTC
• Sets RSPCK delay enable
• Sets SSL negation delay enable
• Sets next-access delay enable
• Sets MSB- or LSB-first
• Sets data length
• Sets transfer bit rate
• Sets clock polarity
(When using an interrupt)
(When using the DTC)
Set I/O ports
Set SPI Control Register (SPCR)
• Sets master mode
• Sets interrupt mask
• Sets SPI mode
Read SPI Control Register (SPCR)
End of initialization in
master mode
Figure 28.40
(4)
Example of initialization flow in master mode for clock synchronous operation
Software processing flow
Software processing during clock synchronous master operation is the same as that for SPI master operation. For details,
see section 28.3.10.1, (7) Software processing flow. Mode fault errors do not occur in clock synchronous operation.
28.3.11.2
(1)
Slave mode operation
Starting serial transfer
When the SPCR.SPMS bit is 1, the first RSPCKn edge triggers the start of a serial transfer in the SPI and the SPI drives
the MISOn output signal. The SSLn0 input signal is not used in clock synchronous operation. For details on the SPI
transfer format, see section 28.3.5, Transfer Formats.
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(2)
28. Serial Peripheral Interface (SPI)
Terminating serial transfer
The SPI terminates the serial transfer after detecting an RSPCKn edge corresponding to the final sampling timing. When
free space is available in the receive buffer (the SPSR.SPRF flag is 0), on termination of a serial transfer, the SPI copies
received data from the shift register to the receive buffer of the SPDR/SPDR_HA register. On termination of a serial
transfer, the SPI changes the status of the shift register to empty regardless of the receive buffer. The final sampling
timing changes depending on the bit length of transfer data. In slave mode, the SPI data length depends on the
SPCMD0.SPB[3:0] bit setting.
For details on the SPI transfer format, see section 28.3.5, Transfer Formats.
(3)
Initialization flow
Figure 28.41 shows an example of initialization flow for clock synchronous operation when the SPI is in slave mode. For
information on how to set up the Interrupt Controller Unit, DTC, and I/O Ports, see the individual block descriptions.
Start of initialization in slave mode
Set SPI Data Control Register (SPDCR)
Set SPI Control Register 2 (SPCR2)
• Sets parity function
• Sets interrupt mask
Set SPI Command Register 0 (SPCMD0)
• Sets MSB- or LSB-first
• Sets data length
• Sets clock phase
• Sets clock polarity
Set interrupt controller
(When using an interrupt)
Set DTC
(When using the DTC)
Set I/O ports
Set SPI Control Register (SPCR)
• Sets slave mode
• Sets interrupt mask
• Sets SPI mode
Read SPI Control Register (SPCR)
End of initialization in slave mode
Figure 28.41
(4)
Example of initialization flow in slave mode for clock synchronous operation
Software processing flow
Software processing during clock synchronous slave operation is the same as that for SPI slave operation. For details, see
section 28.3.10.2, (5) Software processing flow. Mode fault errors do not occur in clock synchronous mode.
28.3.12
Loopback Mode
When 1 is written to the SPPCR.SPLP2 bit or SPPCR.SPLP bit, the SPI shuts off the path between the MISOn pin and
the shift register if the SPCR.MSTR bit is 1, or between the MOSIn pin and the shift register if the SPCR.MSTR bit is 0,
and connects the input path and output path of the shift register. The SPI does not shut off the path between the MOSIn
pin and the shift register if the SPCR.MSTR bit is 1, or between the MISOn pin and the shift register if the SPCR.MSTR
bit is 0. This is called loopback mode. When a serial transfer is executed in loopback mode, the transmit data for the SPI
or the reversed transmit data becomes the received data for the SPI.
Table 28.11 shows the relationship between the SPLP2 and SPLP bits and the received data. Figure 28.42 shows the
configuration of the shift register I/O paths when the SPI in master mode is set in loopback mode (SPPCR.SPLP2 = 1,
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28. Serial Peripheral Interface (SPI)
SPPCR.SPLP = 0 or 1).
Table 28.11
SPLP2 and SPLP bit settings and received data
SPPCR.SPLP2 bit
SPPCR.SPLP bit
Received data
0
0
Input data from the MOSIn or MISOn pin
0
1
Inverted transmit data
1
0
Transmit data
1
1
Transmit data
Transmission
Shift register
(MOSIn/MISOn)
Loopback
Loopback 2
Reception
Normal
(MISOn/MOSIn)
Figure 28.42
28.3.13
Configuration of shift register I/O paths in loopback mode for master mode
Self-Diagnosis of Parity Bit Function
The parity circuit consists of a parity bit adding unit for transmit data and an error detecting unit for received data. To
detect defects in these units, the parity circuit performs self-diagnosis as shown in Figure 28.43.
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28. Serial Peripheral Interface (SPI)
Start of self-diagnosis of
parity circuit
Select full-duplex synchronous serial communications (SPCR.TXMD = 0)
Enable the parity circuit self-diagnosis function (SPCR2.PTE = 1)
Enable the parity function (SPCR2.SPPE = 1)
Select loopback mode (SPPCR.SPLP2 = 1)
Parity error occurred
Add correct parity bit to
transmit data and transfer it
No parity error
No parity error
Add incorrect parity bit to
transmit data and transfer it
Parity error occurred
Disable the parity circuit self-diagnosis function (SPCR2.PTE = 0)
Loopback operation with
the parity bit added in
normal operation
Parity error occurred
No parity error
Incorrect parity bit
added
Check the data that is stored in
the transmit data register
Correct parity bit added
Normal end
No defect in parity circuit
Figure 28.43
28.3.14
Erroneous end
Erroneous end
Defect found in parity bit adding unit
No defect in error detecting unit
Defect found in error
detecting unit
Self-diagnosis flow for parity circuit
Interrupt Sources
The SPI has eight interrupt sources:
Receive buffer full
Transmit buffer empty
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28. Serial Peripheral Interface (SPI)
Transmission complete
Mode fault
Underrun
Overrun
Parity error
SPI idle.
The DTC can be activated by the receive buffer full or transmit buffer empty interrupt to perform data transfer.
Because the vector address for SPIn_SPEI is allocated to interrupt requests triggered by mode-fault, underrun, overrun,
and parity errors, the actual interrupt source must be determined from the flags. Table 28.12 lists the flags associated with
the interrupt sources for the SPI. An interrupt is generated on satisfaction of an interrupt condition in Table 28.12. Clear
the receive buffer full and transmit buffer empty sources through a data transfer.
When using the DTC to perform data transmission or reception, you must first set up the DTC to a transfer-enabled status
before making the SPI settings. For information on setting the DTC, see section 14, Data Transfer Controller (DTC).
If the conditions for generating a transmit buffer empty or receive buffer full interrupt occur while the ICU.IELSRm.IR
flag is 1, the interrupt is not output as a request for the ICU but is saved internally (the capacity for retention is one
request per source). A saved interrupt request is output when the ICU.IELSRm.IR flag becomes 0. A saved interrupt
request is automatically discarded when it is output as an actual interrupt request. The interrupt enable bit (SPCR.SPTIE
or SPCR.SPRIE) for an internally saved interrupt request can also be cleared to 0.
Table 28.12
SPI interrupt sources
Interrupt source
Symbol
Interrupt condition
DTC activation
Receive buffer full
SPIn_SPRI
The receive buffer becomes full (SPSR.SPRF flag is
1) while the SPCR.SPRIE bit is 1
Possible
Transmit buffer empty
SPIn_SPTI
The transmit buffer becomes empty (SPSR.SPTEF
flag is 1) while the SPCR.SPTIE bit is 1
Possible
SPI errors (mode fault,
underrun, overrun, and parity
error)
SPIn_SPEI
The SPSR.MODF, OVRF, PERF, or UDRF flag is set
to 1 while the SPCR.SPEIE bit is 1
Not possible
SPI idle
SPIn_SPII
The SPSR.IDLNF flag sets to 0 while the
SPCR2.SPIIE bit is 1
Not possible
Transmission complete
SPIn_SPTEND
In master mode, an interrupt is generated when the
IDLNF flag (SPI idle flag) changes from 1 to 0. In
slave mode, an interrupt occurs on conditions shown
in Table 28.14.
Not possible
28.4
Event Link Operation
The Event Link Controller (ELC) can produce the following event output signals:
Receive buffer full event output
Transmit buffer empty event output
Mode fault, underrun, overrun, or parity event output
SPI idle event output
Transmission-complete event output.
The event link output signal is output regardless of the interrupt enable bit setting.
28.4.1
Receive Buffer Full Event Output
This event signal is output when received data is transferred from the shift register to the SPDR/SPDR_HA on
completion of a serial transfer.
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28.4.2
28. Serial Peripheral Interface (SPI)
Transmit Buffer Empty Event Output
This event signal is output when data for transmission is transferred from the transmission buffer to the shift register and
when the value of the SPE bit changed from 0 to 1.
28.4.3
Mode Fault, Underrun, Overrun, or Parity Error Event Output
This event signal is output when mode fault, underrun, overrun, or parity error is detected. See section 28.5.4,
Restrictions on Mode Fault, Underrun, Overrun, or Parity Error Event Output if using this event signal.
(1)
Mode fault
Table 28.13 lists the conditions for occurrence of a mode fault event.
Table 28.13
Conditions for mode fault occurrence
Conditions
SPCR.MODFEN bit
SSLn0 pin
Remarks
SPI operation (SPMS = 0)
Slave (SPCR.MSTR bit = 0)
1
Not active
Event is output only when the pin is deactivated
during transmission
(2)
Underrun
This event signal is output in response to an underrun when a serial transfer starts while the transmission data is not
ready, and the value in the SPCR.MSTR bit is 0, and SPCR.SPE bit is 1. Under these conditions, the MODF and UDRF
flags are set to 1.
(3)
Overrun
This event signal is output in response to an overrun when a serial transfer completes while the reception buffer contains
unread data, and the value of the SPCR.TXMD bit is 0. Under these conditions, the OVRF flag is set to 1.
(4)
Parity error
This event signal is output in response to a parity error detected on completion of a serial transfer while the value in the
TXMD bit in SPCR is 0 and the value of the SPPE bit in SPCR2 is 1.
28.4.4
(1)
SPI Idle Event Output
In master mode
In master mode, an event is output when the condition for setting the IDLNF flag (SPI idle flag) to 0 is satisfied.
(2)
In slave mode
In slave mode, an event is output when the SPCR.SPE bit is set to 0 (SPI is initialized).
28.4.5
Transmission-Complete Event Output
During both SPI operation and clock synchronous operation in master mode, an event is output when the IDLNF flag
(SPI idle flag) changes from 1 to 0. Table 28.4 lists the conditions for occurrence of a mode fault event.
Table 28.14
Conditions for generation of transmission-complete event in slave mode
Conditions
Transmit buffer state
Shift register state
Others
SPI operation (SPMS = 0)
Empty
Empty
Negation of SSLn0 input
Clock synchronous operation
(SPMS = 1)
Empty
Empty
Edge detection of the last RSPCKn
Whether the operation is in master or slave mode, an event is not output if 0 is written to the SPCR.SPE bit in
transmission or the SPCR.SPE bit is cleared by the mode fault or underrun error.
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28.5
28.5.1
28. Serial Peripheral Interface (SPI)
Usage Notes
Settings for the Module-Stop State
The Module-Stop Control Register B (MSTPCRB) can enable or disable SPI operation. The SPI is initially stopped after
a reset. The registers become accessible on release from the module-stop state. For details on the Module-Stop Control
Register B, see section 10, Low Power Modes.
28.5.2
Restrictions on Low Power Function
When using the module-stop function and entering a low power mode other than Sleep mode, set the SPCR.SPE bit to 0
before completing communication.
28.5.3
Restrictions on Starting Transfer
If the ICU.IELSRm.IR flag is 1 when transfer starts, the interrupt request is internally saved, which can lead to
unanticipated behavior of the ICU.IELSRm.IR flag. To prevent this, use the following procedure to clear interrupt
requests before enabling operations (by setting the SPCR.SPE bit to 1).
1. Confirm that transfer stopped (SPCR.SPE is 0).
2. Set the relevant interrupt enable bit (SPCR.SPTIE or SPCR.SPRIE) to 0.
3. Read the relevant interrupt enable bit (SPCR.SPTIE or SPCR.SPRIE) and confirm that its value is 0.
4. Set the ICU.IELSRm.IR flag to 0.
28.5.4
Restrictions on Mode Fault, Underrun, Overrun, or Parity Error Event Output
Using the mode fault, underrun, overrun, or parity error event is prohibited if the SPI is in multi-master mode (when the
SPCR.SPMS bit is 0, the SPCR.MSTR bit is 1, and the SPCR.MODFEN bit is 1).
28.5.5
Constraints on the SPRF and SPTEF Flags
If the polling flags, SPRF and SPTEF, are used, using the interrupts are prohibited, and you must set the SPCR.SPRIE
and SPCR.SPTIE bits to 0. Either the interrupts or the flags can be used, but not both.
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29.
29. Cyclic Redundancy Check (CRC) Calculator
Cyclic Redundancy Check (CRC) Calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the data. The bit order of CRC
calculation results can be switched for LSB first or MSB first communication. Additionally, various CRC generation
polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This
function is useful in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer.
29.1
Overview
Table 29.1 lists the specifications of the CRC calculator, and Figure 29.1 shows a block diagram.
Table 29.1
CRC calculator specifications
Parameter
Description
Data size
Data for CRC
calculation*1
8-bit
32-bit
CRC code generated for any desired data in
8n-bit units (where n is a whole number)
CRC code generated for data in 32n-bit units
(where n is a whole number)
CRC processor unit
Operation executed on 8 bits in parallel
Operation executed on 32 bits in parallel
CRC generating polynomial
One of three generating polynomials that is
selectable:
[8-bit CRC]
X8 + X2 + X + 1 (CRC-8)
[16-bit CRC]
X16 + X15 + X2 + 1 (CRC-16)
X16 + X12 + X5 + 1 (CRC-CCITT)
One of two generating polynomials that is
selectable:
[32-bit CRC]
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10
+ X8 + X7 + X5 + X4 + X2 + X + 1 (CRC-32)
X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20
+ X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8
+ X6 + 1 (CRC-32C)
CRC calculation switching
The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication
Module-stop function
Module-stop state can be set
CRC snoop
Monitor reads from and writes to a certain
register address
—
Note 1. The circuit does not have functionality to divide data used in CRC calculations. Write data in 8-bit or 32-bit units.
Data bus
CRCDOR/
CRCDOR_HA/
CRCDOR_BY
CRC code
generation
circuit
CRCCR0
CRC snoop block
CRCSAR
Control signal
CRCDIR/
CRCDIR_BY
=?
CRCCR1
Address bus
Figure 29.1
CRC calculator block diagram
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29.2
29. Cyclic Redundancy Check (CRC) Calculator
Register Descriptions
29.2.1
CRC Control Register 0 (CRCCR0)
Address(es): CRC.CRCCR0 4007 4000h
b7
b6
b5
b4
b3
DORCL
R
LMS
—
—
—
0
0
0
0
0
Value after reset:
b2
b1
b0
GPS[2:0]
0
0
0
Bit
Symbol
Bit name
Description
b2 to b0
GPS[2:0]
CRC Generating Polynomial
Switching
b5 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b6
LMS
CRC Calculation Switching
0: Generates CRC for LSB-first communication
1: Generates CRC for MSB-first communication.
R/W
b7
DORCLR
CRCDOR/CRCDOR_HA/
CRCDOR_BY Register Clear
1: Clears the CRCDOR/CRCDOR_HA/CRCDOR_BY register.
This bit is read as 0.
W*1
b2
0
0
0
0
1
R/W
b0
0
0
1
1
0
0: No calculation is executed
1: 8-bit CRC-8 (X8 + X2 + X + 1)
0: 16-bit CRC-16 (X16 + X15 + X2 + 1)
1: 16-bit CRC-CCITT (X16 + X12 + X5 + 1)
0: 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +
X10 + X8 + X7 + X5 + X4 + X2 + X + 1)
1 0 1: 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 +
X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1)
Other: No calculation is executed.
R/W
Note 1. Always set this bit to 1 when writing to this register.
DORCLR bit (CRCDOR/CRCDOR_HA/CRCDOR_BY)
Write 1 to this bit so that the CRCDOR/CRCDOR_HA/CRCDOR_BY register is set to 0000 0000h.
This bit is read as 0. Only 1 can be written.
LMS bit (CRC Calculation Switching)
Set this bit to select the bit order of generated CRC code. Transmit the lower-order byte of the CRC code first for LSBfirst communication and the upper-order byte first for MSB-first communication. For details on transmitting and
receiving CRC code, see section 29.3, Operation.
GPS[2:0] bits (CRC Generating Polynomial Switching)
Set these bits to select the CRC Generating Polynomial.
29.2.2
CRC Control Register 1 (CRCCR1)
Address(es): CRC.CRCCR1 4007 4001h
b7
b6
CRCSE CRCS
N
WR
Value after reset:
0
0
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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29. Cyclic Redundancy Check (CRC) Calculator
Bit
Symbol
Bit name
Description
R/W
b6
CRCSWR
Snoop-On-Write/Read Switch
0: Snoop-on-read
1: Snoop-on-write.
R/W
b7
CRCSEN
Snoop Enable
0: Disabled
1: Enabled.
R/W
CRCSWR bit (Snoop-On-Write/Read Switch)
The CRCSWR bit selects the direction of the access in the address monitoring function.
When setting this bit to 0 (initial value), the CRC snoop operation to read a specific register address is valid. Similarly,
when setting this bit to 1, the CRC snoop operation to write a specific register address is valid.
CRCSEN bit (Snoop Enable)
When setting this bit to 1, the CRC snoop operation is valid. When setting this bit to 0, the CRC snoop operation is
invalid.
29.2.3
CRC Data Input Register (CRCDIR/CRCDIR_BY)
Address(es): CRC.CRCDIR/CRCDIR_BY 4007 4004h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The CRCDIR register is a read/write 32-bit register to write data for CRC-32 or CRC-32C calculation. The
CRCDIR_BY register is a read/write 8-bit register to write data for CRC-8, CRC-16, or CRC-CCITT calculation.
29.2.4
CRC Data Output Register (CRCDOR/CRCDOR_HA/CRCDOR_BY)
Address(es): CRC.CRCDOR/CRCDOR_HA/CRCDOR_BY 4007 4008h
Value after reset:
Value after reset:
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The CRCDOR register is a read/write 32-bit register for CRC-32 or CRC-32C.
The CRCDOR_HA register is a read/write 16-bit register for CRC-16 or CRC-CCITT.
The CRCDOR_BY register is a read/write 8-bit register for CRC-8.
Because its initial value is 0000 0000h, rewrite the CRCDOR/CRCDOR_HA/CRCDOR_BY register to perform the
calculation using a value other than the initial value.
Data written to the CRCDIR/CRCDIR_BY register is CRC calculated and the result is stored in the CRCDOR/
CRCDOR_HA/CRCDOR_BY register. If the CRC code is calculated following transferred data and the result is 0000
0000h, there is no CRC error.
When an 8-bit CRC (X8 + X2 + X + 1 polynomial) is in use, the valid CRC code is obtained in CRCDOR_BY.
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29. Cyclic Redundancy Check (CRC) Calculator
When a 16-bit CRC (X16 + X15 + X2 + 1 or X16 + X12 + X5 + 1 polynomial) is in use, the valid CRC code is obtained in
CRCDOR_HA.
29.2.5
Snoop Address Register (CRCSAR)
Address(es): CRC.CRCSAR 4007 400Ch
Value after reset:
b15
b14
—
—
0
0
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
CRCSA[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
CRCSA[13:0]
Register Snoop Address
Set the TDR or RDR address in the SCI module to snoop
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CRCSA[13:0] bits (Register Snoop Address)
Set these bits to the lower 14-bit of register address monitored by the CRC snoop operation.
Only the following address can be used for the CRCSA[13:0] bits.
4007 0003h: SCI0.TDR, 4007 0005h: SCI0.RDR
4007 0023h: SCI1.TDR, 4007 0025h: SCI1.RDR
4007 0123h: SCI9.TDR, 4007 0125h: SCI9.RDR
4007 000Fh: SCI0.FTDRL, 4007 0011h: SCI0.FRDRL.
29.3
29.3.1
Operation
Basic Operation
The CRC calculator generates CRC codes for use in LSB-first or MSB-first transfer.
The following examples show CRC code generation for input data (F0h) using the 16-bit CRC-CCITT generating
polynomial (X16 + X12 + X5 + 1). In these examples, the value of the CRC data output register (CRCDOR_HA) is
cleared before CRC calculation.
When an 8-bit CRC (with the polynomial X8 + X2 + X + 1) is in use, the valid bits of the CRC code are obtained in
CRCDOR_BY. When an 32-bit CRC is in use, the valid bits of the CRC code are obtained in CRCDOR.
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29. Cyclic Redundancy Check (CRC) Calculator
1. Write 83h to CRC control register 0 (CRCCR0)
CRCCR0
7
1
0
CRCDOR_HA
15
0
0
0
0
0
1
1
0
0
0
0
0
0
0
8
7
0
0
8
7
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
clear CRCDOR/CRCDOR_HA/CRCDOR_BY
2. Write F0h to the CRC data input register (CRCDIR_BY)
CRCDIR_BY
7
1
1
1
CRCDOR_HA
15
0
1
0
0
0
1
0
1
1
1
0
1
1
0
CRC code generation
3. Read the calculation result in the CRC data output register (CRCDOR_HA)
CRC code = F78Fh
4. 8-bit serial transmission (LSB first)
CRC code
7
1
1
1
1
0
1
1
F
0
7
1
1
Data
0
7
Figure 29.2
0
0
1
1
1
8
0
7
0
1
1
1
1
F
1
0
0
F
0
Output
0
0
LSB-first data transmission
1. Write C3h to CRC control register 0 (CRCCR0)
CRCCR0
7
1
1
CRCDOR_HA
15
0
0
0
0
0
1
1
0
0
0
0
0
0
0
8
7
0
0
8
7
1
0
0
0
0
0
0
0
0
0
clear CRCDOR/CRCDOR_HA/CRCDOR_BY
2. Write F0h to the CRC data input register (CRCDIR_BY)
CRCDIR_BY
7
1
1
1
CRCDOR_HA
15
0
1
0
0
0
1
0
1
1
0
1
1
1
0
0
0
1
1
1
1
1
CRC code generation
3. Read the calculation result in the CRC data output register (CRCDOR_HA)
CRC code = EF1Fh
4. 8-bit serial transmission (MSB first)
CRC code
Data
7
Output
1
1
1
F
Figure 29.3
1
0
0
0
0
0
7
0
1
1
1
E
0
1
1
1
F
0
7
1
0
0
0
0
1
1
1
1
1
1
F
MSB-first data transmission
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29. Cyclic Redundancy Check (CRC) Calculator
1. 8-bit serial reception (LSB-first)
CRC code
Data
0 7
7
1
1
1
1
0
1
F
1
1
1
7
0 7
0
0
0
1
1
8
1
1
1
0
1
F
1
1
0
0
F
0
Input
0
0
2. Write 83h to the CRC Control Register 0 (CRCCR0)
CRCCR0
CRCDOR_HA
7
0
1
0
0
0
0
0
1
1
15
0
0
0
0
0
0
0
8
7
0
0
8
7
1
1
0
0
0
0
0
0
0
0
Clear CRCDOR/CRCDOR_HA/CRCDOR_BY
3. Write F0h to the CRC Data Input Register (CRCDIR_BY)
CRCDIR_BY
CRCDOR_HA
7
1
0
1
1
1
0
0
0
0
15
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
CRC code generation
4. Write 8Fh to the CRC Data Input Register (CRCDIR_BY)
CRCDOR_HA
CRCDIR_BY
7
0
1
0
0
0
1
1
1
1
15
0
0
0
8
7
0
1
8
7
0
0
0
CRC code generation
5. Write F7h to the CRC Data Input Register (CRCDIR_BY)
CRCDIR_BY
CRCDOR_HA
7
1
0
1
1
1
0
1
1
1
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CRC code generation
6. Read the calculation result in the CRC Data Output Register (CRCDOR_HA)
CRC code = 0000h no error
Figure 29.4
LSB-first data reception
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S124 User’s Manual
29. Cyclic Redundancy Check (CRC) Calculator
1. 8-bit serial reception (MSB first)
CRC code
Data
0 7
7
Input
1
1
1
1
0
0
F
0
0
1
07
1
0
1
0
1
1
E
1
1
0
0
0
F
0
1
1
1
1
1
1
F
2. Write C3h to CRC control register 0 (CRCCR0)
CRCCR0
CRCDOR_HA
7
0
1
1
0
0
0
0
1
1
15
0
0
0
0
0
0
0
8
7
0
0
8
7
1
0
0
0
0
0
0
0
0
0
clear CRCDOR/CRCDOR_HA/CRCDOR_BY
3. Write F0h to the CRC data input register (CRCDIR_BY)
CRCDIR_BY
CRCDOR_HA
7
1
0
1
1
1
0
0
0
0
15
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
CRC code generation
4. Write EFh to the CRC data input register (CRCDIR_BY)
CRCDOR_HA
CRCDIR_BY
7
1
1
1
0
1
1
1
0
15
1
0
0
0
8
7
1
0
8
7
0
0
0
CRC code generation
5. Write 1Fh to the CRC data input register (CRCDIR_BY)
CRCDIR_BY
CRCDOR_HA
7
0
0
0
0
1
1
1
1
1
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CRC code generation
6. Read the calculation result in the CRC data output register (CRCDOR_HA)
CRC code = 0000h no error
Figure 29.5
29.3.2
MSB-first data reception
CRC Snoop
The CRC snoop function monitors reads from and writes to a specific register address and performs CRC calculation on
the data read from and written to the aforementioned I/O register address automatically. Because the CRC snoop
recognizes writes to and reads from a specific register address as a trigger to automatically perform CRC calculation,
there is no need to write data to the CRCDIR_BY register. All I/O register addresses specified in the Snoop Address
Register (CRCSAR) are subject to the CRC snoop. The CRC snoop is useful in monitoring writes to the serial transmit
buffer, and reads from the serial receive buffer.
To use this function, write a target I/O register address to bits CRCSA13 to CRCSA0 in the CRCSAR register, and set
CRCSEN bit in the CRCCR1 register to 1. Then, set the CRCSWR bit in the CRCCR1 register to 1 to enable snooping
on writes to the target address, or set the CRCSWR bit in the CRCCR1 register to 0 to enable snooping on reads from the
target address.
When setting the CRCSEN bit to 1, CRCSWR bit to 1 and writing data to a target I/O register address in a bus master
module such as CPU and DTC, the CRC calculator stores the data in the CRCDIR_BY register and performs CRC
calculation. Similarly, when setting the CRCSEN bit to 1, CRCSWR bit to 0 and reading data in a target I/O register
address in a bus master module such as CPU and DTC, the CRC calculator stores the data in the CRCDIR_BY register
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29. Cyclic Redundancy Check (CRC) Calculator
and performs CRC calculation.
CRC calculation is performed 1 byte at a time. When the target I/O register address is accessed in words (16 bits) or long
words (32 bits), CRC code is generated on the lower byte (1 byte) of data.
29.4
Usage Notes
29.4.1
Settings for the Module-Stop State
The Module Stop Control Register C (MSTPCRC) can enable or disable CRC calculator operation. The CRC is stopped
after a reset. The registers become accessible on release from the module-stop state. For details, see section 10, Low
Power Modes.
29.4.2
Note on Transmission
The sequence of transmission for the CRC code differs according to whether transmission is LSB-first or MSB-first.
When transmitting 32-bit data (In case operation executed on 8 bits in parallel)
1. CRC code
After specifying the method for generation calculation, write data to CRCDIR in order of (1), (2), (3), and (4).
7
0
(1)
CRCDIR
7
0
(2)
CRCDIR
7
0
(3)
CRCDIR
7
0
(4)
CRCDIR
CRC code generation
8 7
15
0
CRC code (L)
CRC code (H)
CRCDOR
2. Transmit data
(i) When transmission is LSB first
CRC code
7
07
(H)
0 7
(L)
07
(4)
07
(3)
(ii) When transmission is MSB first
7
Output
Figure 29.6
0
(1)
Output
CRC code
07
(1)
07
(2)
07
(2)
0 7
(3)
0 7
(4)
07
(H)
0
(L)
LSB-first and MSB-first data transmission
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30. 14-Bit A/D Converter (ADC14)
30.
14-Bit A/D Converter (ADC14)
30.1
Overview
The MCU includes one 14-bit successive approximation A/D converter (ADC14) unit. Up to 18 analog input channels,
plus the temperature sensor output and internal reference voltage, can be selected for conversion. The A/D conversion
accuracy is selectable between 14-bit and 12-bit conversion, making it possible to optimize the trade-off between speed
and resolution in generating a digital value.
The ADC14 supports the following operating modes:
Single scan mode to convert the analog inputs of selected channels in ascending order of channel number
Continuous scan mode to convert the analog inputs of selected channels continuously in ascending order of channel
number
Group scan mode to divide the analog inputs of channels into two groups (group A and group B) and convert the
analog inputs of the selected channels for each group in ascending order of channel number.
In group scan mode, you can start group A and group B A/D conversion at different times by individually selecting their
scan start conditions. In addition, when group A priority control operation is set, the ADC14 accepts group A scan start
during group B A/D conversion, suspending group B conversion. This allows you to assign higher priority to A/D
conversion start for group A.
In double trigger mode, the analog input of a selected channel is converted in single scan mode or group scan mode
(group A), and the data converted by the first and second A/D conversion start triggers are stored in different registers,
providing duplexing of A/D converted data.
Self-diagnosis is performed once at the beginning of each scan, and one of the three reference voltage values is A/D
converted.
The temperature sensor output and internal reference voltage cannot be selected for conversion simultaneously. Perform
A/D conversion independently for the temperature sensor output or the internal reference voltage.
The ADC14 also provides a compare function (window A and window B). The compare function specifies the upper-side
reference value for window A and lower-side reference value for window B, and outputs an interrupt when the A/D
converted value of the selected channel meets the comparison conditions.
The reference power supply pin (VREFH0), or the analog block power supply pin (AVCC0), or the internal reference
voltage is selectable as the reference voltage on the high-potential side. The reference power supply ground pin
(VREFL0) or the analog block power supply ground pin (AVSS0) is selectable as the reference voltage on the lowpotential side. If the internal reference voltage is selected as the reference voltage on the high-potential side, A/D
conversion of the temperature sensor or the internal reference voltage is prohibited.
Table 30.1 lists the ADC14 specifications. Table 30.2 lists the ADC14 functions. Figure 30.1 shows a block diagram of
the ADC14.
Table 30.1
ADC14 specifications (1 of 3)
Parameter
Specifications
Number of units
One unit
Input channels
Up to 18 channels (AN000 to AN010, AN016 to AN022)
Extended analog function
Temperature sensor output, internal reference voltage
A/D conversion method
Successive approximation method
Resolution
14 bits (14-bit or 12-bit conversion selectable)
Conversion time
0.79 µs/channel (when 14-bit A/D conversion clock PCLKD (ADCLK) operates at 64 MHz)
A/D conversion clock
Peripheral module clock PCLKB*1 and A/D conversion clock PCLKD (ADCLK)*1 can be set with the
following division ratios: PCLKB to PCLKD (ADCLK) frequency ratio = 1:1, 1:2, 1:4
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Table 30.1
30. 14-Bit A/D Converter (ADC14)
ADC14 specifications (2 of 3)
Parameter
Specifications
Data registers
18 registers for analog input, plus one register for A/D-converted data duplication in double trigger
mode and two registers for A/D-converted data duplication during extended operation in double
trigger mode
One register for temperature sensor output
One register for internal reference voltage
One register for self-diagnosis
A/D conversion results are stored in A/D data registers
12-bit and 14-bit accuracy for A/D conversion results
A/D-converted value addition mode, in which the sum of all A/D-converted results is stored in the
A/D data registers as a value with the conversion accuracy bit count + 2 bits*4
Double-trigger mode (selectable in single scan and group scan modes):
The first unit of A/D-converted analog input data on one selected channel is stored in the data
register for the channel, and the second unit is stored in the duplication register.
Extended operation in double trigger mode (available for specific triggers):
A/D-converted analog input data on one selected channel is stored in the duplication register
provided for the associated trigger.
Operating modes
Single scan mode:
A/D conversion is performed once on the analog inputs of the selected channels, the temperature
sensor output, or the internal reference voltage.
Continuous scan mode:
A/D conversion is performed repeatedly on the analog inputs of the selected channels.
Group scan mode:
- Analog inputs of selected channels are divided into group A and group B, and A/D conversion of the
analog inputs selected on a group basis is performed once.
- The scan start conditions can be independently selected for group A and group B, allowing A/D
conversion of group A and group B to be started independently.
Group scan mode (when group A is given priority):
- If a group A trigger is input during A/D conversion on group B, the A/D conversion on group B is
stopped and A/D conversion is performed on group A.
- Restart (rescan) of A/D conversion on group B after completion of A/D conversion on group A can
be set.
Conditions for A/D conversion
start
Software trigger
Synchronous trigger from the Event Link Controller (ELC)
Asynchronous trigger from the external trigger pin, ADTRG0.
Functions
Interrupt sources
In single scan mode (double trigger deselected), an A/D scan end interrupt request and ELC event
signal (ADC140_ADI) can be generated on completion of single scan.
- A compare interrupt request (ADC140_CMPAI/ADC140_CMPBI) can be generated in response to
a match with a digital comparison condition.
- A window compare ELC event signal (ADC140_WCMPM) can be generated in response to a match
with a digital comparison condition.
- A window compare ELC event signal (ADC140_WCMPUM) can be generated in response to a
mismatch with a digital comparison condition.
In single scan mode (double trigger selected), an A/D scan end interrupt request and ELC event
signal (ADC140_ADI) is generated on completion of two scans.
In continuous scan mode, an A/D scan end interrupt request and ELC event signal (ADC140_ADI) is
generated on completion of all the selected channel scans.
In group scan mode (double trigger deselected), an A/D scan end interrupt request and ELC event
signal (ADC140_ADI) is generated on completion of group A scan, and an A/D scan end interrupt
request for group B (ADC140_GBADI) can be generated on completion of group B scan.
In group scan mode (double trigger selected), an A/D scan end interrupt request and ELC event
signal (ADC140_ADI) is generated on completion of two group A scans, and an A/D scan end
interrupt request for group B (ADC140_GBADI) can be generated on completion of group B scan.
ADC140_ADI, ADC140_GBADI, ADC140_WCMPM, and ADC140_WCMPUM can activate the Data
Transfer Controller (DTC).
ELC interface
Scan can be started by a trigger from the ELC
Variable sampling state count
Self-diagnosis of A/D converter
Selectable A/D-converted value addition mode or average mode
Analog input disconnection detection function (discharge function/precharge function)
Double-trigger mode (duplication of A/D conversion data)
Selectable 12-bit or 14-bit conversion*2
Automatic clear function for A/D data registers
Digital comparison of values in the comparison register and the data register, and comparison
between values in the data registers.
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Table 30.1
30. 14-Bit A/D Converter (ADC14)
ADC14 specifications (3 of 3)
Parameter
Specifications
Reference voltage
VREFH0, AVCC0, or internal reference voltage can be selected as the high-potential reference
voltage
VREFL0 or AVSS0 can be selected as the low-potential reference voltage.
Module-stop function
Module-stop state can be specified*3
Note 1. Peripheral module clock PCLKB frequency is set in the SCKDIVCR.PCKB[2:0] bits and A/D conversion clock
ADCLK frequency is set in the SCKDIVCR.PCKD[2:0] bits. The maximum frequency of PCLKB is 32 MHz and
the maximum frequency of PCLKD (ADCLK) is 64 MHz.
Note 2. Changing the A/D conversion accuracy also changes the A/D conversion time. For details, see section 30.3.6,
Analog Input Sampling and Scan Conversion Time.
Note 3. For details, see section 10, Low Power Modes.
Note 4. The number of extended bits for addition varies with the A/D conversion accuracy and the number of addition
times. A 2-bit extension is used for up to 4 times conversion (3 times addition) when the A/D conversion accuracy
is 12 or 14 bits.
Note 5. When selecting the temperature sensor output or the internal reference voltage, do not use continuous scan
mode or group scan mode.
Table 30.2
ADC14 functions
Parameter
ADC140
Analog input channel
AN000 to AN010, AN016 to AN022
Internal reference voltage
Temperature sensor output
Conditions for A/D
conversion start
Software
Software trigger
Enabled
External trigger
Trigger input pin
ADTRG0
Synchronous trigger (trigger
from ELC)
ELC trigger
ELC_AD00
ELC_AD01
Interrupt
ADC140_ADI
ADC140_GBADI
ADC140_CMPAI
ADC140_CMPBI
Output to ELC
ADC140_ADI
ADC140_WCMPM
ADC140_WCMPUM
Setting of module-stop function*1, *2
MSTPCRD.MSTPD16 bit
Note 1. For details, see section 10, Low Power Modes.
Note 2. Wait 1 μs or longer to start A/D conversion after release from the module-stop state.
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30. 14-Bit A/D Converter (ADC14)
Successive approximation
register
Bus interface
AVCC0
AVSS0
MUX
MUX
D/A
A/D data register
A/D control register
Power generator
(for self-diagnosis)
Interrupt requests
(ADC140_ADI, ADC140_GBADI,
ADC140_CMPAI, ADC140_CMPBI)
MUX
Internal reference voltage
Temperature sensor output
Analog multiplexer
AN022
AN016
AN010
AN008
AN007
VREFL0/AN006
Comparator
Sample-andhold circuit
+
-
Control circuit
(including decoder)
VREFH0/AN005
AN004
AN003
AN002
AN001
AN000
Figure 30.1
Event output to the ELC
(ADC140_ADI, ADC140_WCMPM,
ADC140_WCMPUM)
Synchronous trigger
(ELC_AD00, ELC_AD01)
Asynchronous trigger
(ADTRG0)
ADC14 block diagram
Table 30.3 lists the ADC14 I/O pins.
Table 30.3
ADC14 I/O pins
Pin name
I/O
Function
AVCC0
Input
Analog block power supply pin
AVSS0
Input
Analog block power supply ground pin
VREFH0
Input
Reference power supply pin
VREFL0
Input
Reference power supply ground pin
AN000 to AN010, AN016 to AN022
Input
Analog input pins 0 to 10, 16 to 22
ADTRG0
Input
External trigger input pin for starting A/D conversion
30.2
30.2.1
Register Descriptions
A/D Data Registers y (ADDRy), A/D Data Duplexing Register (ADDBLDR),
A/D Data Duplexing Register A (ADDBLDRA), A/D Data Duplexing Register B
(ADDBLDRB), A/D Temperature Sensor Data Register (ADTSDR),
A/D Internal Reference Voltage Data Register (ADOCDR)
The A/D data registers include:
ADDRy registers (y = 0 to 10, 16 to 22): 16-bit read-only registers for storing the A/D conversion results
ADDBLDR register: 16-bit read-only register for storing the A/D conversion results in response to the second
trigger in double trigger mode
ADDBLDRA and ADDBLDRB registers: 16-bit read-only registers for storing the A/D conversion results in
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30. 14-Bit A/D Converter (ADC14)
response to the respective triggers during extended operation in double trigger mode
ADTSDR register: 16-bit read-only register for storing the A/D conversion result of temperature sensor output
ADOCDR register: 16-bit read-only register for storing the A/D conversion result of the internal reference voltage.
The following conditions determine the formats for data in the A/D data registers:
The setting of the A/D Data Register Format Select bit (ADCER.ADRFMT) (flush-left or flush-right)
The setting of the A/D Data Conversion Accuracy Specify bits (ADCER.ADPRC[1:0]) (12- or 14-bit)
The setting of the Addition/Average Count Select bits (ADADC.ADC[2:0]) (once, twice, three times, four times, or
16 times)
The setting of the Average Mode Enable bit (ADADC.AVEE) (addition or average).
(1)
When A/D-Converted Value Addition/Average Mode is Not Selected
Settings for flush-right data with 14-bit accuracy
Address(es): ADC140.ADDR0 4005 C020h to ADC140.ADDR10 4005 C034h,
ADC140.ADDR16 4005 C040h to ADC140.ADDR22 4005 C04Ch,
ADC140.ADDBLDR 4005 C018h, ADC140.ADDBLDRA 4005 C084h, ADC140.ADDBLDRB 4005 C086h,
ADC140.ADTSDR 4005 C01Ah, ADC140.ADOCDR 4005 C01Ch
Value after reset:
b15
b14
—
—
0
0
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
AD[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
AD[13:0]
Converted Value 13 to 0
14-bit A/D-converted value
R
b15, b14
—
Reserved
These bits are read as 0
R
Settings for flush-right data with 12-bit accuracy
Value after reset:
b15
b14
b13
b12
—
—
—
—
0
0
0
0
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
AD[11:0]
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b11 to b0
AD[11:0]
Converted Value 11 to 0
12-bit A/D-converted value
R
b15 to b12
—
Reserved
These bits are read as 0
R
Settings for flush-left data with 14-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
AD[13:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b1
b0
—
—
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0
R
b15 to b2
AD[13:0]
Converted Value 13 to 0
14-bit A/D-converted value
R
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30. 14-Bit A/D Converter (ADC14)
Settings for flush-left data with 12-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
AD[11:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
b1
b0
—
—
—
—
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
—
Reserved
These bits are read as 0
R
b15 to b4
AD[11:0]
Converted Value 11 to 0
12-bit A/D-converted value
R
(2)
When A/D-converted value average mode is selected
A/D-converted value average mode can be selected when 2 or 4 times is specified in the A/D-converted value addition
mode. This register indicates the mean of A/D-converted values on a specific channel. The value is stored in the A/D data
register based on the setting of the A/D Data Register Format Select bit in the same way as for normal A/D conversion.
(3)
When A/D-converted value addition mode is selected
For 12-bit or 14-bit accuracy, 1, 2, 3, or 4 times can be selected in the A/D-converted value addition mode. A/D
conversion results are stored in the A/D data register as a 2-bit-extended value of the specified conversion accuracy.
When selecting 12-bit accuracy, 16 times can also be selected in the A/D-converted value addition mode. In A/Dconverted value addition mode, this register indicates the value that is obtained by adding A/D converted values on a
specific channel. A/D conversion results are stored in the A/D data register as a 4-bit-extended value of the specified
conversion accuracy.
When A/D-converted value addition mode is selected, the value is stored in the A/D data register based on the settings of
the A/D Data Register Format Select bits.
The data formats for each condition are shown in the following sections.
Settings for flush-right data with 14-bit accuracy in A/D-converted value addition mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
AD[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
AD[15:0]
Added Value 15 to 0
16-bit sum of A/D conversion results
R
Settings for flush-right data with 12-bit accuracy in A/D-converted value addition mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
AD[15:0]*1
Value after reset:
—
—
0
0
AD[13:0]*2
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
AD[15:0]*1
Added Value 15 to 0
16-bit sum of A/D conversion results
R
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30. 14-Bit A/D Converter (ADC14)
Bit
Symbol
b13 to b0
AD[13:0]*2
Bit name
Description
R/W
Added Value 13 to 0
14-bit sum of A/D conversion results
R
b15, b14
—
Reserved
These bits are read as 0
R
Note 1. Used when 16 conversion times is selected in A/D-converted value addition mode.
Note 2. Used when 1, 2, 3, or 4 conversion times is selected in A/D-converted value addition mode.
Settings for flush-left data with 14-bit accuracy in A/D-converted value addition mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
AD[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
AD[15:0]
Added Value 15 to 0
16-bit sum of A/D conversion results
R
Settings for flush-left data with 12-bit accuracy in A/D-converted value addition mode
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
0
0
AD[15:0]*1
AD[13:0]*2
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
AD[15:0]*1
Added Value 15 to 0
16-bit sum of A/D conversion results
R
Bit
Symbol
Bit name
Description
R/W
b1, b0
—
Reserved
These bits are read as 0
R
b15 to b2
AD[13:0]*2
Added Value 13 to 0
14-bit sum of A/D conversion results
R
Note 1. Used when 16 conversion times is selected in A/D-converted value addition mode.
Note 2. Used when 1, 2, 3, or 4 conversion times is selected in A/D-converted value addition mode.
30.2.2
A/D Self-Diagnosis Data Register (ADRD)
The ADRD register is a 16-bit read-only register that holds the A/D conversion results based on the self-diagnosis of the
ADC14. In addition to the AD bits that indicate the A/D-converted value, the ADRD register includes the self-diagnosis
status bit (DIAGST).
The following conditions determine the format for data in this register:
The setting of the A/D Data Register Format Select bit (ADCER.ADRFMT) (flush-left or flush-right)
The setting of the A/D Data Conversion Accuracy Specify bits (ADCER.ADPRC[1:0]) (12-bit or 14-bit).
A/D-converted value addition mode and A/D-converted value average mode cannot be applied to the A/D self-diagnosis
function. For details of self-diagnosis, see section 30.2.11, A/D Control Extended Register (ADCER).
The data formats for each given condition are shown in the following sections.
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30. 14-Bit A/D Converter (ADC14)
Settings for flush-right data with 14-bit accuracy
Address(es): ADC140.ADRD 4005 C01Eh
b15
b14
b13
b12
b11
b10
b9
b8
DIAGST[1:0]
Value after reset:
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
AD[13:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b13 to b0
AD[13:0]
Converted Value 13 to 0
14-bit A/D-converted value
R
b15, b14
DIAGST[1:0]
Self-Diagnosis Status
b15 b14
R
0 0: Self-diagnosis has not been executed since power-on
0 1: Self-diagnosis was executed using 0 volts
1 0: Self-diagnosis was executed using the reference power
supply*1 voltage × 1/2
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 30.2.11, A/D Control
Extended Register (ADCER).
Note 1. Reference voltage refers to VREFH0.
Settings for flush-right data with 12-bit accuracy
b15
b14
DIAGST[1:0]
Value after reset:
Bit
0
0
Symbol
b13
b12
—
—
0
0
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
AD[11:0]
0
Bit name
0
0
0
0
0
0
Description
R/W
b11 to b0
AD[11:0]
Converted Value 11 to 0
12-bit A/D-converted value
R
b13, b12
—
Reserved
These bits are read as 0.
R
b15, b14
DIAGST[1:0]
Self-Diagnosis Status
b15 b14
R
0 0: Self-diagnosis has not been executed since power-on
0 1: Self-diagnosis was executed using 0 volts
1 0: Self-diagnosis was executed using the reference power
supply*1 voltage × 1/2
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 30.2.11, A/D Control
Extended Register (ADCER).
Note 1. Reference voltage refers to VREFH0.
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30. 14-Bit A/D Converter (ADC14)
Settings for flush-left data with 14-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
AD[13:0]
Value after reset:
0
0
0
0
0
0
0
0
b1
b0
DIAGST[1:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
DIAGST[1:0]
Self-Diagnosis Status
b1 b0
R
b15 to b2
AD[13:0]
Converted Value 13 to 0
14-bit A/D-converted value
R
0 0: Self-diagnosis has not been executed since power-on
0 1: Self-diagnosis was executed using 0 volts
1 0: Self-diagnosis was executed using the reference power
supply*1 voltage × 1/2
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 30.2.11, A/D Control
Extended Register (ADCER).
Note 1. Reference voltage refers to VREFH0.
Settings for flush-left data with 12-bit accuracy
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
AD[11:0]
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
b3
b2
—
—
0
0
b1
b0
DIAGST[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
DIAGST[1:0]
Self-Diagnosis Status
b1 b0
R
b3, b2
—
Reserved
These bits are read as 0
R
b15 to b4
AD[11:0]
Converted Value 11 to 0
12-bit A/D-converted value
R
0 0: Self-diagnosis has not been executed since power-on
0 1: Self-diagnosis was executed using 0 volts
1 0: Self-diagnosis was executed using the reference power
supply*1 voltage × 1/2
1 1: Self-diagnosis was executed using the reference power
supply*1 voltage.
For details on self-diagnosis, see section 30.2.11, A/D Control
Extended Register (ADCER).
Note 1. Reference voltage refers to VREFH0.
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30.2.3
30. 14-Bit A/D Converter (ADC14)
A/D Control Register (ADCSR)
Address(es): ADC140.ADCSR 4005 C000h
b15
ADST
Value after reset:
0
b14
b13
b12
b11
ADCS[1:0]
—
—
0
0
0
0
b10
b9
b8
b7
ADHSC TRGE EXTRG DBLE
0
0
0
0
b6
b5
GBADI
E
—
0
0
b4
b3
b2
b1
b0
0
0
DBLANS[4:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b4 to b0
DBLANS[4:0]
Double Trigger Channel
Select
These bits select one analog input channel for double trigger
operation. The setting is only valid in double trigger mode.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
GBADIE
Group B Scan End
Interrupt Enable
0: Disable ADC140_GBADI interrupt generation on group B scan
completion
1: Enable ADC140_GBADI interrupt generation on group B scan
completion.
Group B scan works only in group scan mode.
R/W
b7
DBLE
Double Trigger Mode
Select
0: Deselect double trigger mode
1: Select double trigger mode.
R/W
b8
EXTRG
Trigger Select *1
0: Start A/D conversion by a synchronous trigger (ELC)
1: Start A/D conversion by the asynchronous trigger (ADTRG0).
R/W
b9
TRGE
Trigger Start Enable
0: Disable A/D conversion to be started by a synchronous or
asynchronous trigger
1: Enable A/D conversion to be started by a synchronous or
asynchronous trigger.
R/W
b10
ADHSC
A/D Conversion Mode
Select
0: High-speed A/D conversion mode
1: Low-power A/D conversion mode.
R/W
b12, b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b14, b13
ADCS[1:0]
Scan Mode Select
b14 b13
R/W
b15
ADST
A/D Conversion Start
0: Stop A/D conversion process
1: Start A/D conversion process.
R/W
0
0
1
1
0: Single scan mode
1: Group scan mode
0: Continuous scan mode
1: Setting prohibited.
Note 1. To start A/D conversion using an external pin (asynchronous trigger):
After a high-level signal is input to the external pin (ADTRG0), write 1 to both the TRGE and EXTRG bits in the
ADCSR register and drive the ADTRG0 pin low. With these settings, the scan conversion process starts on
detection of the falling edge on ADTRG0. The pulse width of the low-level input must be at least 1.5 clock cycles
of PCLKB.
DBLANS[4:0] bits (Double Trigger Channel Select)
The DBLANS[4:0] bits select one channel for A/D conversion data duplication in double trigger mode. The A/D
conversion results of the analog input of the channel selected in the DBLANS[4:0] bits are stored in A/D Data Register y
when conversion is started by the first trigger, and in the A/D Data Duplexing Register when conversion is started by the
second trigger. Table 30.4 shows the channel selection settings for double triggered operation.
In double trigger mode, the channels selected in the ADANSA0 and ADANSA1 registers are invalid, and the channel
selected in the DBLANS[4:0] bits is subjected to A/D conversion instead.
When double trigger mode is used in group scan mode, double trigger control is only applied to group A and not to group
B. Therefore, multiple channel analog input can be selected for group B even in double trigger mode.
Only set the DBLANS[4:0] bits when the ADST bit is 0. Do not set the DBLANS[4:0] bits at the same time that you
write 1 to the ADST bit.
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30. 14-Bit A/D Converter (ADC14)
To enter A/D-converted value addition/average mode when in double trigger mode, select the channel using the
DBLANS[4:0] bits in the ADANSA0 and ADANSA1 registers.
Table 30.4
Relationship between DBLANS[4:0] bit settings and double trigger enabled channels
DBLANS[4:0]
Duplication channel
DBLANS[4:0]
Duplication channel
00000
AN000
10000
AN016
00001
AN001
10001
AN017
00010
AN002
10010
AN018
00011
AN003
10011
AN019
00100
AN004
10100
AN020
00101
AN005
10101
AN021
00110
AN006
10110
AN022
00111
AN007
10111
—
01000
AN008
11000
—
01001
AN009
11001
—
01010
AN010
11010
—
01011
—
11011
—
01100
—
01101
—
01110
—
01111
—
Note 1. A/D-converted data from the self-diagnosis function, temperature sensor output, and internal reference voltage
cannot be used in double trigger mode.
GBADIE bit (Group B Scan End Interrupt Enable)
The GBADIE bit enables or disables group B scan end interrupt (ADC140_GBADI) in group scan mode.
DBLE bit (Double Trigger Mode Select)
The DBLE bit selects or deselects double trigger mode. Double-trigger mode can only be operated by the synchronous
trigger (ELC) selected in the ADSTRGR.TRSA[5:0] bits. The operation of double trigger is as follows:
1. The ADC140_ADI interrupt is output not on completion of the first conversion but on completion of the second
conversion.
2. The A/D conversion results from the duplication channel (selected in DBLANS[4:0]) started by the first trigger are
stored in the A/D Data Register y and those started by the second trigger are stored in the A/D Data Duplication
Register.
When the DBLE bit is set (double trigger mode is selected), the channels specified in the ADANSA0 and ADANSA1
registers are invalid. Double trigger mode is deselected by setting DBLE to 0. When DBLE is set to 1 again, the double
trigger operation is the same as the first time scanning with the first trigger.
Do not select double trigger mode in continuous scan mode. Software triggering cannot be used in double trigger mode.
Always set the ADST bit to 0 before setting the DBLE bit. Do not set the DBLE bit at that same time as writing 1 to the
ADST bit.
EXTRG bit (Trigger Select)
The EXTRG bit selects the synchronous trigger or asynchronous trigger as the trigger for starting A/D conversion.
TRGE bit (Trigger Start Enable)
The TRGE bit enables or disables A/D conversion by the synchronous trigger or asynchronous trigger. In group scan
mode, set the TRGE bit to 1.
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30. 14-Bit A/D Converter (ADC14)
ADHSC bit (A/D Conversion Mode Select)
The ADHSC bit selects either high speed mode or low current mode for A/D conversion.
For details on how to rewrite the ADHSC bit, see section 30.8.8, ADHSC Bit Rewriting Procedure.
ADCS[1:0] bits (Scan Mode Select)
The ADCS[1:0] bits select the scan mode.
In single scan mode, A/D conversion is performed for the analog inputs of the channels selected in the ADANSA0 and
ADANSA1 registers, in ascending order of channel number. When 1 cycle of A/D conversion completes for all the
selected channels, the scan conversion stops.
In continuous scan mode, when the ADCSR.ADST bit is 1, A/D conversion is performed for the analog inputs of the
channels selected with the ADANSA0 and ADANSA1 registers, in ascending order of channel number. When 1 cycle of
A/D conversion completes for all the selected channels, A/D conversion repeats from the first channel. If the
ADCSR.ADST bit is set to 0 during continuous scan, A/D conversion stops even if scanning is in progress.
In group scan mode:
Group A scanning is started by the synchronous trigger (ELC) selected in the TRSA[5:0] bits in the ADSTRGR
register. A/D conversion is performed on group A analog inputs of the channels selected in the ADANSA0 and
ADANSA1 registers, in ascending order of channel number. When 1 cycle of A/D conversion completes for all the
selected channels, A/D conversion stops.
Group B scanning is started by the synchronous trigger (ELC) selected in the TRSB[5:0] bits in the ADSTRGR
register. A/D conversion is performed on group B analog inputs of the channels selected in the ADANSB0 and
ADANSB1 registers, in ascending order of channel number. When 1 cycle of A/D conversion completes for all the
selected channels, A/D conversion stops.
If the conversion processes in group A and B occur at the same time, those conversions cannot be controlled separately.
In this case, set the group A Priority Control Setting bit (ADGSPCR.PGS) in the A/D Group Scan Priority Control
Register (ADGSPCR) to 1 to assign a priority to group A conversion.
In group scan mode, select different channels and triggers for group A and group B.
When selecting temperature sensor output or internal reference voltage, select single scan mode, and perform A/D
conversion after deselecting all analog input channels in the ADANSA0 and ADANSA1 registers. When A/D
conversion of the temperature sensor output or internal reference voltage completes, A/D conversion stops.
Only set the ADCS[1:0] bits when the ADST bit is 0. Do not set the ADCS[1:0] bits at the same time that you write 1 to
the ADST bit.
Table 30.5
Selectable targets for A/D Conversion depending on settings of scan mode and double trigger
mode
Targets for A/D conversion
Scan mode setting
Double trigger
mode setting
Single scan
DBLE = 0
DBLE = 1
Continuous scan
Group scan
Self-diagnosis
Analog input
(including
group A)
Analog input
(group B)
Temperature
sensor output
Internal
reference
voltage
×
×
(1 ch only)
×
×
×
DBLE = 0
×
×
×
DBLE = 1
×
×
×
×
×
DBLE = 0
×
×
DBLE = 1
×
(1 ch only)
×
×
: Selectable. ×: Not selectable.
ADST bit (A/D Conversion Start)
The ADST bit starts or stops the A/D conversion process. Before the ADST bit is set to 1, set the A/D conversion clock,
the conversion mode, and the conversion target analog input.
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30. 14-Bit A/D Converter (ADC14)
[Setting conditions]
1 is written by software
The synchronous trigger (ELC) selected in the ADSTRGR.TRSA[5:0] bits is detected when the ADCSR.EXTRG
bit is 0 and the ADCSR.TRGE bit is 1
The synchronous trigger (ELC) selected in the ADSTRGR.TRSB[5:0] bits is detected when the ADCSR.TRGE bit
is 1 in group scan mode
The asynchronous trigger is detected when the ADCSR.TRGE and ADCSR.EXTRG bits are 1 and the
ADSTRGR.TRSA[5:0] bits are 000000b
When group A priority control operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit
= 1), the ADGSPCR.GBRP bit is set to 1, and each time A/D conversion of group B starts.
[Clearing conditions]
0 is written by software
A/D conversion of all the selected channels, the temperature sensor output, or the internal reference voltage
completes in single scan mode
Group A scan completes in group scan mode
Group B scan completes in group scan mode
When group A priority control operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit
= 1), the ADGSPCR.GBRP bit is set to 1, and each time a scanning of Group B completes.
Note:
Note:
Note:
When group A priority control operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit
= 1), do not set the ADST bit to 1.
When group A priority control operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit
= 1), do not set the ADST bit to 0. When forcing A/D conversion to terminate, follow the procedure for clearing the
ADST bit.
If the single scan continuous function is used (ADGSPCR.GBRP = 1) when the group priority operation mode is
enabled (ADCSR.ADCS[1:0] = 01b and ADGSPCR.PGS = 1), the ADST bit remains 1.
30.2.4
A/D Channel Select Register A0 (ADANSA0)
Address(es): ADC140.ADANSA0 4005 C004h
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
ANSA1 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
ANSA10 to ANSA00
A/D Conversion Channels Select
0: Associated input channel not selected
1: Associated input channel selected.
Bit [10] (ANSA10) is associated with AN010 and bit [0]
(ANSA00) is associated with AN000.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0. R/W
ANSAn bits (n = 00 to 10) (A/D Conversion Channels Select)
The ADANSA0 register selects any combination of analog input channels from AN000 to AN010 for A/D conversion.
The channels and the number of channels can be arbitrarily set. The ANSA00 bit is associated with AN000 and the
ANSA10 bit is associated with AN010.
When performing A/D conversion of temperature sensor output or internal reference voltage, set the ADANSA0 register
to 0000h to deselect all analog input channels.
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30. 14-Bit A/D Converter (ADC14)
In double trigger mode, the channels selected in the ADANSA0 register are invalid, and the channel selected in the
ADCSR.DBLANS[4:0] bits is selected in group A instead.
When group scan mode is selected, do not select the channels specified in A/D Channel Select Register B0 (ADANSB0)
and A/D Channel Select Register B1 (ADANSB1).
Only set the ADANSA0 register when the ADCSR.ADST bit is 0.
30.2.5
A/D Channel Select Register A1 (ADANSA1)
Address(es): ADC140.ADANSA1 4005 C006h
b15
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
Value after reset:
b6
b5
b4
b3
b2
b1
b0
ANSA2 ANSA2 ANSA2 ANSA1 ANSA1 ANSA1 ANSA1
2
1
0
9
8
7
6
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
ANSA22 to ANSA16
A/D Conversion Channels
Select
0: Do not select associated input channel
1: Select associated input channel.
Bit [6] (ANSA22) is associated with AN022 and bit [0]
(ANSA16) is associated with AN016.
R/W
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
ANSAn bits (n = 16 to 22) (A/D Conversion Channels Select)
The ADANSA1 register selects any combination of analog input channels from AN016 to AN022 for A/D conversion.
The channels and the number of channels can be arbitrarily set. The ANSA16 bit is associated with AN016 and the
ANSA22 bit is associated with AN022. In double trigger mode, the channels selected in the ADANSA1 register are
invalid, and the channel selected in the ADCSR.DBLANS[4:0] bits is selected in group A instead.
When performing A/D conversion of temperature sensor output or internal reference voltage, set the ADANSA1 register
to 0000h to deselect all analog input channels.
When group scan mode is selected, do not select the channels specified in A/D Channel Select Register B0 (ADANSB0)
and A/D Channel Select Register B1 (ADANSB1).
Only set the ADANSA1 register when the ADCSR.ADST bit is 0.
30.2.6
A/D Channel Select Register B0 (ADANSB0)
Address(es): ADC140.ADANSB0 4005 C014h
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
ANSB1 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
ANSB10 to ANSB00
A/D Conversion Channels
Select
0: Associated input channel not selected
1: Associated input channel selected.
Bit [10] (ANSB10) is associated with AN010 and bit [0]
(ANSB00) is associated with AN000.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
ANSBn bits (n = 00 to 10) (A/D Conversion Channels Select)
The ADANSB0 register selects any combination of analog input channels from AN000 to AN010 in group B for A/D
conversion when group scan mode is selected. The ADANSB0 register is used for group scan mode only and not for any
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30. 14-Bit A/D Converter (ADC14)
other modes.
Do not select channels specified in group A as selected in the ADANSA0 and ADANSA1 registers or the
ADCSR.DBLANS[4:0] bits in double trigger mode.
The ANSB00 bit is associated with AN000 and the ANSB10 bit is associated with AN010.
When performing A/D conversion of temperature sensor output or internal reference voltage, set the ADANSB0 register
to 0000h to deselect all analog input channels.
Only set the ADANSB0 register when the ADCSR.ADST bit is 0.
30.2.7
A/D Channel Select Register B1 (ADANSB1)
Address(es): ADC140.ADANSB1 4005 C016h
b15
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
Value after reset:
b6
b5
b4
b3
b2
b1
b0
ANSB2 ANSB2 ANSB2 ANSB1 ANSB1 ANSB1 ANSB1
2
1
0
9
8
7
6
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
ANSB22 to ANSB16
A/D Conversion Channels Select
0: Associated input channel not selected
1: Associated input channel selected.
Bit [6] (ANSB22) is associated with AN022 and bit [0]
(ANSB16) is associated with AN016.
R/W
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
ANSBn bits (n = 16 to 22) (A/D Conversion Channels Select)
The ADANSB1 register selects any combination of analog input channels from AN016 to AN022 in group B for A/D
conversion when group scan mode is selected. The ADANSB1 register is used for group scan mode only and not for any
other modes.
Do not select channels specified in group A as selected in the ADANSA0 and ADANSA1 registers or the
ADCSR.DBLANS[4:0] bits in double trigger mode.
The ANSB16 bit is associated with AN016 and the ANSB22 bit is associated with AN022.
When performing A/D conversion of temperature sensor output or internal reference voltage, set the ADANSB1 register
to 0000h to deselect all analog input channels.
Only set the ADANSB1 register when the ADCSR.ADST bit is 0.
30.2.8
A/D-Converted Value Addition/Average Channel Select Register 0 (ADADS0)
Address(es): ADC140.ADADS0 4005 C008h
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
ADS10 ADS09 ADS08 ADS07 ADS06 ADS05 ADS04 ADS03 ADS02 ADS01 ADS00
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
ADS10 to ADS00
A/D-Converted Value Addition/
Average Channel Select
0: Associated input channel not selected
1: Associated input channel selected.
Bit [10] (ADS10) is associated with AN010 and bit [0]
(ADS00) is associated with AN000.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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30. 14-Bit A/D Converter (ADC14)
ADSn bits (n = 00 to 10) (A/D-Converted Value Addition/Average Channel Select)
The ADSn bits determine which A/D-converted channels from AN000 to AN010 are subject to A/D-converted value
addition/averaging. When an ADSn bit associated with a channel selected for A/D conversion is set to 1, A/D conversion
of the analog input of the respective channel is performed successively 1, 2, 3, 4, or 16 times, as specified in the
ADC[2:0] bits in the ADADC register.
When the ADADC.AVEE bit is 0, the value obtained by addition is stored in the A/D data register. When the
ADADC.AVEE bit is 1, the mean value of the results obtained by addition is stored in the A/D data register.
The ADSn bits apply only to channels that are selected for A/D conversion in:
The ANSAn bits (n = 00 to 10) in the ADANSA0 register or the DBLANS[4:0] bits in the ADCSR register
The ANSBn bits (n = 00 to 10) in the ADANSB0 register.
For channels on which the A/D conversion is performed and for which addition/average mode is not selected, a normal
1-time conversion is executed and the conversion result is stored in the A/D data register.
Only set ADADS0 register bits when the ADCSR.ADST bit is 0.
Figure 30.2 shows a scanning operation sequence in which both the ADADS0.ADS02 and ADADS0.ADS06 bits are set
to 1. In this figure:
Addition mode is selected (ADADS.AVEE = 0)
The number of conversions is set to 4 (ADADC.ADC[1:0] = 11b)
Channels AN000 to AN007 are selected (ADANSA0.ANSA0[15:0] = 00FFh) in continuous scan mode
(ADCSR.ADCS[1:0] = 10b).
The conversion process begins with AN000. The AN002 conversion is performed successively 4 times and the added
value is returned to A/D Data Register 2 (ADDR2). Next, the AN003 conversion process is started. The AN006
conversion is performed successively 4 times and the added value is returned to A/D Data Register 6 (ADDR6). After
conversion of AN007, the conversion operation repeats in the same sequence starting with AN000.
Continuous
conversion count
4 times
3 times
2 times
1 time
AN002
AN006
AN002
AN002
AN006
AN002
AN002
AN006
AN002
AN000 AN001 AN002 AN003 AN004 AN005 AN006 AN007 AN000 AN001 AN002 • • •
Conversion in progress
Figure 30.2
Scan conversion sequence with ADADC.ADC[2:0] = 011b, ADADS0.ADS02 = 1, ADADS0.ADS06 =
1
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30.2.9
30. 14-Bit A/D Converter (ADC14)
A/D-Converted Value Addition/Average Channel Select Register 1 (ADADS1)
Address(es): ADC140.ADADS1 4005 C00Ah
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b6
b5
b4
b3
b2
b1
b0
ADS22 ADS21 ADS20 ADS19 ADS18 ADS17 ADS16
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
ADS22 to ADS16
A/D-Converted Value
Addition/Average Channel
Select
0: Associated input channel not selected
1: Associated input channel selected.
Bit [6] (ADS22) is associated with AN022 and bit [0] (ADS16)
is associated with AN016.
R/W
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
ADSn bits (n = 16 to 22) (A/D-Converted Value Addition/Average Channel Select)
The ADSn bits determine which A/D-converted channels from AN016 to AN022 are subject to A/D-converted value
addition/averaging. When an ADSn bit associated with a channel selected for A/D conversion is set to 1, A/D conversion
of the analog input of the respective channel is performed successively 1, 2, 3, 4, or 16 times, as specified in the
ADC[2:0] bits in the ADADC register.
When the ADADC.AVEE bit is 0, the value obtained by addition is stored in the A/D data register. When the
ADADC.AVEE bit is 1, the mean value of the results obtained by addition is stored in the A/D data register.
The ADSn bits apply only to channels that are selected for A/D conversion in:
The ANSAn bits (n = 16 to 22) in the ADANSA1 register or the DBLANS[4:0] bits in the ADCSR register
The ANSBn bits (n = 16 to 22) in the ADANSB1 register.
For channels on which the A/D conversion is performed and for which addition/average mode is not selected, a normal
1-time conversion is executed and the conversion result is stored in the A/D data register.
Only set ADADS1 register bits when the ADCSR.ADST bit is 0.
30.2.10
A/D-Converted Value Addition/Average Count Select Register (ADADC)
Address(es): ADC140.ADADC 4005 C00Ch
b7
b6
b5
b4
b3
AVEE
—
—
—
—
0
0
0
0
0
Value after reset:
b2
b1
b0
ADC[2:0]
0
0
0
Bit
Symbol
Bit name
Description
b2 to b0
ADC[2:0]
Count Select
b6 to b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b7
AVEE
Average Mode Enable
0: Average mode disabled*1
1: Average mode enabled.*2
R/W
b2
b0
R/W
0 0 0: 1-time conversion (no addition: same as normal conversion)
0 0 1: 2-time conversion (one addition)
0 1 0: 3-time conversion (two additions)
0 1 1: 4-time conversion (three additions)
1 0 1: 16-time conversion (15 additions).
Other settings are prohibited.
R/W
Note 1. When average mode is deselected by setting the ADADC.AVEE bit to 0, set addition count to 1, 2, 3, 4, or 16-
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30. 14-Bit A/D Converter (ADC14)
time conversion when using 12-bit accuracy, or 1, 2, 3, or 4-time conversion when using 14-bit accuracy.
Note 2. When average mode is selected by setting the ADADC.AVEE bit to 1, set addition count to 2-time or 4-time
conversion. Do not set the addition count to 3-time or 16-time conversion (ADC[2:0] = 010b and 101b).
ADC[2:0] bits (Count Select)
The ADC[2:0] bits set the addition count for all channels for which A/D conversion and addition/average mode are
selected, including the channel selected in double trigger mode with the ADCSR.DBLANS[4:0] bits. The count also
applies to A/D conversion of the temperature sensor output and internal reference voltage.
The following restrictions apply to the setting of the ADC[2:0] bits:
When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the count to 3-time conversion
(ADADC.ADC[2:0] = 010b) or 16-time conversion (ADADC.ADC[2:0] = 101b).
When self-diagnosis is executed (ADCER.DIAGM = 1), do not set the ADC[2:0] bits to any value other than 000b.
For 14-bit conversion accuracy (ADCER.ADPRC[1:0] = 11b), do not set the ADC[2:0] bits to 101b.
Only set the ADC[2:0] bits when the ADCSR.ADST bit is 0.
AVEE bit (Average Mode Enable)
The AVEE bit selects addition or average mode for all channels for which A/D conversion and A/D-converted value
addition/average mode are selected, including the channel selected for double trigger mode in the
ADCSR.DBLANS[4:0] bits, the temperature sensor output, and internal reference voltage.
When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to 3-time conversion
(ADADC.ADC[2:0] = 010b) or 16-time conversion (ADADC.ADC[2:0] = 101b).
Only set the AVEE bit when the ADCSR.ADST bit is 0.
30.2.11
A/D Control Extended Register (ADCER)
Address(es): ADC140.ADCER 4005 C00Eh
b15
b14
b13
b12
ADRFM
T
—
—
—
0
0
0
0
Value after reset:
b11
b10
DIAGM DIAGL
D
0
0
b9
b8
DIAGVAL[1:0]
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
ACE
—
—
ADPRC[1:0]
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b0
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b2, b1
ADPRC[1:0]
A/D Conversion Accuracy Specify
b2 b1
R/W
b4, b3
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5
ACE
A/D Data Register Automatic Clearing
Enable
0: Automatic clearing disabled
1: Automatic clearing enabled.
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b9, b8
DIAGVAL[1:0]
Self-Diagnosis Conversion Voltage
Select
b9 b8
R/W
b10
DIAGLD
Self-Diagnosis Mode Select
0: Rotation mode for self-diagnosis voltage
1: Fixed mode for self-diagnosis voltage.
R/W
b11
DIAGM
Self-Diagnosis Enable
0: Self-diagnosis of ADC14 disabled
1: Self-diagnosis of ADC14 enabled.
R/W
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0
0
1
1
0
0
1
1
R/W
0: 12-bit accuracy
1: Setting prohibited
0: Setting prohibited
1: 14-bit accuracy.
0: Setting prohibited when self-diagnosis is enabled
1: 0 volts
0: Reference power supply*1 voltage × 1/2
1: Reference power supply*1 voltage.
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Bit
Symbol
30. 14-Bit A/D Converter (ADC14)
Bit name
Description
R/W
b14 to b12 —
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
A/D Data Register Format Select
0: Flush-right selected for the A/D data register format
1: Flush-left selected for the A/D data register format.
R/W
ADRFMT
Note 1. Reference voltage refers to VREFH0.
ADPRC[1:0] bits (A/D Conversion Accuracy Specify)
The ADPRC[1:0] bits select either 12 bits or 14 bits for the A/D conversion accuracy. Changing the A/D conversion
accuracy also changes the bit width of the data stored in the result register and A/D conversion time. For details, see
section 30.3.6, Analog Input Sampling and Scan Conversion Time.
Only set the ADPRC[1:0] bits when the ADCSR.ADST bit is 0.
ACE bit (A/D Data Register Automatic Clearing Enable)
The ACE bit enables or disables automatic clearing (all 0) of the ADDRy, ADRD, ADDBLDR, ADDBLDRA,
ADDBLDRB, ADTSDR, or ADOCDR register after any of these registers is read by the CPU or DTC. Automatic
clearing of the A/D data registers enables detection of failures that are not updated in the A/D data registers. For details,
see section 30.3.7, Usage Example of A/D Data Register Automatic Clearing Function.
DIAGVAL[1:0] bits (Self-Diagnosis Conversion Voltage Select)
The DIAGVAL[1:0] bits select the voltage value used in self-diagnosis voltage fixed mode. For details, see the
ADCER.DIAGLD bit description.
Do not execute self-diagnosis by setting the ADCER.DIAGLD bit to 1 when the ADCER.DIAGVAL[1:0] bits are set to
00b.
DIAGLD bit (Self-Diagnosis Mode Select)
The DIAGLD bit selects whether the three voltage values are rotated or the fixed voltage is used in self-diagnosis.
Setting the DIAGLD bit to 0 selects conversion of the voltages in rotation mode, where 0 V, the reference power supply
voltage × 1/2, and the reference power supply voltage are converted, in that order. After reset and when self-diagnosis
voltage rotation mode is selected, self-diagnosis is executed from 0 V. The self-diagnosis voltage value does not return to
0 V when scan conversion completes. When scan conversion is restarted, rotation starts at the voltage value following the
previous value.
Setting the DIAGLD bit to 1 selects fixed voltage, in which the fixed voltage specified in the ADCER.DIAGVAL[1:0]
bits is converted. If fixed mode is switched to rotation mode, rotation starts at the fixed voltage value.
Only set the DIAGLD bit when the ADCSR.ADST bit is 0.
DIAGM bit (Self-Diagnosis Enable)
The DIAGM bit enables or disables self-diagnosis.
Self-diagnosis is used to detect a failure of the ADC14. In self-diagnosis mode, one of the three voltage values (0 V, the
reference power supply voltage × 1/2, or the reference power supply voltage) is converted. When conversion completes,
information on the converted voltage and the conversion result is stored into the A/D Self-Diagnosis Data Register
(ADRD). The ADRD register can be read out by software to determine whether the conversion result falls within the
normal or abnormal range.
Self-diagnosis is executed once at the beginning of each scan, and one of the three voltages is converted. In double
trigger mode (ADCSR.DBLE = 1), self-diagnosis (DIAGM = 0) is deselected. When self-diagnosis is selected in group
scan mode, self-diagnosis is executed separately for group A and group B.
Only set the DIAGM bit when the ADCSR.ADST bit is 0.
ADRFMT bit (A/D Data Register Format Select)
The ADRFMT bit specifies flush-right or flush-left for data to be stored in the ADDRy, ADDBLDR, ADDBLDRA,
ADDBLDRB, ADTSDR, ADOCDR, ADCMPDR0/1, ADWINLLB, ADWINULB, or ADRD register.
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30. 14-Bit A/D Converter (ADC14)
Only set the ADRFMT bit when the ADCSR.ADST bit is 0.
30.2.12
A/D Conversion Start Trigger Select Register (ADSTRGR)
Address(es): ADC140.ADSTRGR 4005 C010h
Value after reset:
b15
b14
—
—
0
0
b13
b12
b11
b10
b9
b8
TRSA[5:0]
0
0
0
0
0
0
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
0
0
TRSB[5:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
TRSB[5:0]
A/D Conversion Start Trigger Select
for Group B
Select the A/D conversion start trigger for group B in
group scan mode
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b13 to b8
TRSA[5:0]
A/D Conversion Start Trigger Select
Select the A/D conversion start trigger in single scan
mode and continuous scan mode. In group scan mode,
the A/D conversion start trigger for group A is selected.
R/W
b15, b14
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
TRSB[5:0] bits (A/D Conversion Start Trigger Select for Group B)
The TRSB[5:0] bits select the trigger to start scanning of the analog inputs selected in group B. The TRSB[5:0] bits must
only be set in group scan mode and are not used in any other scan mode. Software trigger or asynchronous trigger cannot
be used as the scan conversion start trigger for group B. In group scan, set the TRSB[5:0] bits to a value other than
000000b and set the ADCSR.TRGE bit to 1.
When group A is given priority in group scan mode, setting the ADGSPCR.GBRP bit to 1 allows group B to
continuously operate in single scan mode. When setting the ADGSPCR.GBRP bit to 1, set the TRSB[5:0] bits to 3Fh.
The issuance period for a conversion trigger must be more than or equal to the actual scan conversion time (tSCAN). If
the issuance period is less than tSCAN, A/D conversion by the trigger might have no effect.
When the GPT module is selected as an A/D conversion start trigger, a delay for synchronization processing occurs. For
details, see section 30.3.6, Analog Input Sampling and Scan Conversion Time.
Table 30.6 lists the A/D conversion start sources selected in the TRSB[5:0] bits.
Table 30.6
Selection of A/D activation sources by TRSB[5:0] bits
Source
TRSB[5]
TRSB[4]
TRSB[3]
TRSB[2]
TRSB[1]
TRSB[0]
Trigger source de-selection state
Remarks
1
1
1
1
1
1
ELC_AD00
ELC
0
0
1
0
0
1
ELC_AD01
ELC
0
0
1
0
1
0
ELC_AD00/ELC_AD01
ELC
0
0
1
0
1
1
TRSA[5:0] bits (A/D Conversion Start Trigger Select)
The TRSA[5:0] bits select the trigger to start A/D conversion in single scan mode and continuous scan mode, or the
trigger to start scanning of the group A analog inputs in group scan mode. When scanning is executed in group scan
mode or double trigger mode, software trigger or asynchronous trigger is prohibited.
When using a synchronous trigger (ELC), set the TRGE bit in the ADCSR register to 1 and set the EXTRG bit in
the ADCSR register to 0.
When using the asynchronous trigger (ADTRG0), set the TRGE bit in the ADCSR register to 1 and set the EXTRG
bit in the ADCSR register to 1.
Software trigger (ADCSR.ADST) is enabled regardless of the settings of the ADCSR.TRGE bit, the
ADCSR.EXTRG bit, or the TRSA[5:0] bits.
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30. 14-Bit A/D Converter (ADC14)
The issuance period for a conversion trigger must be more than or equal to the actual scan conversion time (tSCAN). If
the issuance period is less than tSCAN, A/D conversion by a trigger might have no effect.
Table 30.7 lists the A/D conversion start sources selected in the TRSA[5:0] bits.
Table 30.7
Selection of A/D activation sources by TRSA[5:0] bits
Source
TRSA[5]
TRSA[4]
TRSA[3]
TRSA[2]
TRSA[1]
TRSA[0]
Trigger source de-selection state
1
1
1
1
1
1
ADTRG0
Input pin for the
trigger
0
0
0
0
0
0
ELC_AD00
ELC
0
0
1
0
0
1
ELC_AD01
ELC
0
0
1
0
1
0
ELC_AD00/ELC_AD01
ELC
0
0
1
0
1
1
30.2.13
Remarks
A/D Conversion Extended Input Control Register (ADEXICR)
Address(es): ADC140.ADEXICR 4005 C012h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
—
—
—
—
—
—
OCSA
TSSA
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
b1
b0
OCSAD TSSAD
0
0
Bit
Symbol
Bit name
Description
R/W
b0
TSSAD
Temperature Sensor Output A/DConverted Value Addition/Average
Mode Select
0: Temperature sensor output A/D-converted value
addition/average mode not selected
1: Temperature sensor output A/D-converted value
addition/average mode selected.
R/W
b1
OCSAD
Internal Reference Voltage A/DConverted Value Addition/Average
Mode Select
0: Internal reference voltage A/D-converted value
addition/average mode not selected
1: Internal reference voltage A/D-converted value
addition/average mode selected.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b8
TSSA
Temperature Sensor Output A/D
Conversion Select
0: Disable A/D conversion of temperature sensor output
1: Enable A/D conversion of temperature sensor output.
R/W
b9
OCSA
Internal Reference Voltage A/D
Conversion Select
0: A/D conversion of internal reference voltage disabled
1: A/D conversion of internal reference voltage enabled.
R/W
b15 to b10
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
TSSAD bit (Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select)
When the TSSAD bit is 1, A/D conversion of the temperature sensor output is selected and performed successively the
number of times specified in the ADC[2:0] bits in the ADADC register. The maximum addition count differs depending
on the conversion accuracy, see section 30.2.1. When the ADADC.AVEE bit is 0, the value obtained by addition is
returned to the A/D Temperature Sensor Data Register (ADTSDR). When the ADADC.AVEE bit is 1, the mean value is
returned to the ADTSDR register.
Only set the TSSAD bit when the ADCSR.ADST bit is 0.
OCSAD bit (Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select)
When the OCSAD bit is 1, A/D conversion of the internal reference voltage is selected and performed successively the
number of times specified in the ADC[2:0] bits in the ADADC register. The maximum addition count differs depending
on the conversion accuracy, see section 30.2.1. When the ADADC.AVEE bit is 0, the value obtained by addition is
returned to the A/D Internal Reference Voltage Data Register (ADOCDR). When the ADADC.AVEE bit is 1, the mean
value is returned to the ADOCDR register.
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30. 14-Bit A/D Converter (ADC14)
Only set the OCSAD bit when the ADCSR.ADST bit is 0.
TSSA bit (Temperature Sensor Output A/D Conversion Select)
The TSSA bit selects A/D conversion of the temperature sensor output. When executing the A/D conversion of the
temperature sensor output:
1. Set all bits in the ADANSA0/1 and ADANSB0/1 registers, the ADCSR.DBLE bit, and the ADEXICR.OCSA bit to
0.
2. Execute the A/D conversion in single scan mode.
Only set the TSSA bit when the ADCSR.ADST bit is 0.
When executing the A/D conversion of the temperature sensor output, DNDIS[4:0] is set to 0Fh and the A/D converter
executes discharge (15 ADCLK) before executing sampling. The required sampling time is 5 μs or more.
The A/D converter executes discharge each time A/D conversion is executed on the temperature sensor output.
OCSA bit (Internal Reference Voltage A/D Conversion Select)
The OCSA bit selects A/D conversion of the internal reference voltage. When executing the A/D conversion of the
internal reference voltage:
1. Set all bits in the ADANSA0/1 and ADANSB0/1 registers, the ADCSR.DBLE bit, and the ADEXICR.TSSA bit to
0.
2. Execute the A/D conversion in single scan mode.
Only set the OCSA bit when the ADCSR.ADST bit is 0.
When executing the A/D conversion of the internal reference voltage, DNDIS[4:0] are set to 0Fh and the A/D converter
executes discharge (15 ADCLK) before executing sampling. The required sampling time is 5 μs or more.
The A/D converter executes discharge each time A/D conversion is executed on the internal reference voltage.
30.2.14
A/D Sampling State Register n (ADSSTRn) (n = 00 to 10, L, T, O)
Address(es): ADC140.ADSSTR00 4005 C0E0h to ADC140.ADSSTR10 4005 C0EAh,
ADC140.ADSSTRL 4005 C0DDh, ADC140.ADSSTRT 4005 C0DEh, ADC140.ADSSTRO 4005 C0DFh
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
SST[7:0]
Value after reset:
0
0
0
0
1
Bit
Symbol
Bit name
Description
R/W
b7 to b0
SST[7:0]
Sampling Time Setting
These bits set the sampling time in the range from 5 to 255 states
R/W
The ADSSTRn register sets the sampling time for analog input.
If one state is 1 A/D conversion clock cycle (ADCLK) and the ADCLK clock is 64 MHz, one state is 15.625 ns. The
initial value is 13 states. The sampling time can be adjusted if the impedance of the analog input signal source is too high
to secure sufficient sampling time, or if the ADCLK clock is slow.
The lower limit of the sampling time setting depends on the frequency ratio:
If the frequency ratio of PCLKB to PCLKD (ADCLK) = 1:1, the sampling time must be set to a value of more than
5 states
If the frequency ratio of PCLKB to PCLKD (ADCLK) = 1:2 or 1:4, the sampling time must be set to a value of
more than 6 states.
Table 30.8 shows the relationship between the A/D Sampling State Register and the associated channels.
For details, see section 30.3.6, Analog Input Sampling and Scan Conversion Time.
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30. 14-Bit A/D Converter (ADC14)
Only set the SST[7:0] bits when the ADCSR.ADST bit is 0.
Table 30.8
Relationship between A/D Sampling State Register and associated channels
Bit name
Associated channels
ADSSTR00.SST[7:0] bits*1
AN000
ADSSTR01.SST[7:0] bits
AN001
ADSSTR02.SST[7:0] bits
AN002
ADSSTR03.SST[7:0] bits
AN003
ADSSTR04.SST[7:0] bits
AN004
ADSSTR05.SST[7:0] bits
AN005
ADSSTR06.SST[7:0] bits
AN006
ADSSTR07.SST[7:0] bits
AN007
ADSSTR08.SST[7:0] bits
AN008
ADSSTR09.SST[7:0] bits
AN009
ADSSTR10.SST[7:0] bits
AN010
ADSSTRL.SST[7:0] bits
AN016-AN022
ADSSTRT.SST[7:0] bits
Temperature sensor output*2
ADSSTRO.SST[7:0] bits
Internal reference voltage*2
Note 1. When the self-diagnosis function is selected, the sampling time set in the ADSSTR00.SST[7:0] bits is applied.
Note 2. When the temperature sensor output or the internal reference voltage is converted, set the sampling time to more
than 5 μs. Because the maximum SST[7:0] value is 255 states, the ADCLK frequency must be 51 MHz or less to
achieve 5 μs sampling time.
30.2.15
A/D Disconnection Detection Control Register (ADDISCR)
Address(es): ADC140.ADDISCR 4005 C07Ah
Value after reset:
b7
b6
b5
b4
—
—
—
PCHG
0
0
0
0
b3
b2
b1
b0
ADNDIS[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
b3 to b0
ADNDIS[3:0]
Disconnection Detection Assist Setting
b4
PCHG
Precharge/discharge select
0: Select discharge
1: Select precharge.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b3
R/W
b0
0 0 0 0: The disconnection detection assist function is
disabled
0 0 0 1: Setting prohibited
Others: The number of states for the discharge or
precharge period.
R/W
The ADDISCR register selects either precharge or discharge, and the period of precharge or discharge for the A/D
disconnection detection assist function. Only set the ADDISCR register when the ADCSR.ADST bit is 0.
When the temperature sensor output or internal reference voltage is converted, the A/D converter executes discharge
automatically. This operation is achieved by setting the ADDISCR register to 0Fh (15 ADCLK) when ADEXICR.OCSA
or TSSA is set to 1. After executing discharge, the A/D converter executes sampling. The required sampling time is 5 s
or more.
Disable the disconnection detection assist function if any of the following functions are used:
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30. 14-Bit A/D Converter (ADC14)
The temperature sensor
The internal reference voltage
A/D self-diagnosis.
ADNDIS[3:0] bits (Disconnection Detection Assist Setting)
The ADNDIS[3:0] bits specify the period of precharge or discharge. When ADNDIS[3:0] = 0000b, the disconnection
detection assist function is disabled. Setting the ADNDIS[3:0] bits to 0001b is prohibited. Except when ADNDIS[3:0] =
0000b or 0001b, the specified value indicates the number of states for the period of precharge or discharge. When the
ADNDIS[3:0] bits are set to any values other than 0000b or 0001b, the disconnection detection assistance function is
enabled.
PCHG bit (Precharge/discharge select)
The PCHG bit selects either precharge or discharge.
30.2.16
A/D Group Scan Priority Control Register (ADGSPCR)
Address(es): ADC140.ADGSPCR 4005 C080h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
GBRP
—
—
—
—
—
—
—
—
—
—
—
—
—
GBRSC
N
PGS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
PGS
Group A Priority Control Setting*1
0: Operate without group A priority control
1: Operate with group A priority control.
R/W
b1
GBRSCN
Group B Restart Setting
Enabled only when PGS = 1, reserved when PGS = 0.
0: Do not restart group B after it is stopped by group A priority
control
1: Restart group B after it is stopped by group A priority
control.
R/W
b14 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15
GBRP
Group B Single Scan Continuous
Start*2
Enabled only when PGS = 1, reserved when PGS = 0
0: Single scan for group B not continuously activated
1: Single scan for group B continuously activated.
R/W
Note 1. The ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode) before setting the PGS bit to 1. Operation is
not guaranteed if these bits are set to any other value.
Note 2. When the GBRP bit is set to 1, single scan is performed continuously for group B regardless of the GBRSCN bit.
PGS bit (Group A Priority Control Setting)
Set the PGS bit to 1 to give priority to operation on group A.
The ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode) before setting the PGS bit to 1. Operation is not
guaranteed if the bits are set to any other value.
When the PGS bit is set to 0, software must perform a clear operation as described in section 30.8.2, Notes on Stopping
A/D Conversion. When the PGS bit is set to 1, use the settings described in section 30.3.4.3, Operation under group A
priority control.
GBRSCN bit (Group B Restart Setting)
The GBRSCN bit controls the restarting of scan operation on group B when operation on group A is given priority.
If a scan operation on group B is stopped by a group A trigger input when the GBRSCN bit is 1, the scan operation is
restarted on completion of group A conversion. Also, if a group B trigger is input during A/D conversion on group A, the
scan operation on group B is restarted on completion of the group A conversion.
R01UM0003EU0130 Rev.1.30
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30. 14-Bit A/D Converter (ADC14)
When the GBRSCN bit is 0, triggers input during A/D conversion are ignored. Additionally, the ADCSR.ADST bit must
be 0 when the GBRSCN bit is set.
GBRP bit (Group B Single Scan Continuous Start)
Set the GBRP bit to perform a single scan operation continuously on group B.
Setting the GBRP bit to 1 starts a single scan on group B. On completion of the scan, another single scan on group B
starts automatically. If a group B conversion stops because of an operation on group A, the group A takes priority, and
single scan on group B automatically restarts on completion of group A conversion.
Disable group B trigger input before setting the GBRP bit to 1. Setting the GBRP bit to 1 invalidates the setting of the
GBRSCN bit. The ADCSR.ADST bit must be 0 when the GBRP bit is set.
The setting in the GBRP bit is valid when the PGS bit is 1.
30.2.17
A/D Compare Function Control Register (ADCMPCR)
Address(es): ADC140.ADCMPCR 4005 C090h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
—
CMPAE
—
CMPBE
—
—
—
—
—
—
—
CMPAB[1:0]
0
0
0
0
0
0
0
0
0
0
0
CMPAI WCMP CMPBI
E
E
E
0
Value after reset:
0
0
0
0
Bit
Symbol
Bit name
b1, b0
CMPAB[1:0]
Window A/B Composite
Conditions Setting
b8 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b9
CMPBE
Compare Window B
Operation Enable
0: Compare window B operation disabled
Disable ADC140_WCMPM and ADC140_WCMPUM outputs.
1: Compare window B operation enabled.
R/W
b10
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b11
CMPAE
Compare Window A
Operation Enable
0: Compare window A operation disabled
Disable ADC140_WCMPM and ADC140_WCMPUM outputs.
1: Compare window A operation enabled.
R/W
b12
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b13
CMPBIE
Compare B Interrupt
Enable
0: ADC140_CMPBI interrupt disabled when comparison conditions
(window B) are met
1: ADC140_CMPBI interrupt enabled when comparison conditions
(window B) are met.
R/W
b14
WCMPE
Window Function Setting
0: Window function disabled
Window A and window B operate as a comparator to compare the
single value on the lower side with the A/D conversion result.
1: Window function enabled
Window A and window B operate as a comparator to compare the
two values on the upper and lower sides with the A/D conversion
result.
R/W
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Description
b0
R/W
b1 b0
0 0: Output ADC140_WCMPM when window A OR window B comparison conditions are met; otherwise, output
ADC140_WCMPUM
0 1: Output ADC140_WCMPM when window A EXOR window B
comparison conditions are met; otherwise, output
ADC140_WCMPUM
1 0: Output ADC140_WCMPM when window A AND window B
comparison conditions are met; otherwise, output
ADC140_WCMPUM
1 1: Setting prohibited.
These bits are valid when both window A and window B are enabled
(CMPAE = 1 and CMPBE = 1).
R/W
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30. 14-Bit A/D Converter (ADC14)
Bit
Symbol
Bit name
Description
R/W
b15
CMPAIE
Compare A Interrupt
Enable
0: ADC140_CMPAI interrupt disabled when comparison conditions
(window A) are met
1: ADC140_CMPAI interrupt enabled when comparison conditions
(window A) are met.
R/W
CMPAB[1:0] bits (Window A/B Composite Conditions Setting)
The CMPAB[1:0] bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1) in
single scan mode. These bits specify the compare function match/mismatch event output conditions and monitoring
conditions of ADWINMON.MONCONB. Only set the CMPAB[1:0] bits when the ADCSR.ADST bit is 0.
CMPBE bit (Compare Window B Operation Enable)
The CMPBE bit enables or disables the compare window B operation. Set the CMPBE bit when the ADCSR.ADST bit is
0.
Set the CMPBE bit to 0 before setting the following registers:
A/D channel select registers A0/A1/B0/B1 (ADANSA0, ADANSA1, ADANSB0, ADANSB1)
OCSA or TSSA bits in the A/D Conversion Extended Input Control Register (ADEXICR)
CMPCHB[5:0] bits in the window B Channel Select Register (ADCMPBNSR).
CMPAE bit (Compare Window A Operation Enable)
The CMPAE bit enables or disables the compare window A operation. Set the CMPAE bit when the ADCSR.ADST bit is
0.
Set the CMPAE bit to 0 before setting the following registers:
A/D channel select registers A0/A1/B0/B1 (ADANSA0, ADANSA1, ADANSB0, ADANSB1)
OCSA or TSSA bits in the A/D Conversion Extended Input Control Register (ADEXICR)
Window A channel select registers 0/1 (ADCMPANSR0, ADCMPANSR1)
Window A extended input select register (ADCMPANSER).
CMPBIE bit (Compare B Interrupt Enable)
The CMPBIE bit enables or disables the ADC140_CMPBI interrupt output when the comparison conditions (window B)
are met.
WCMPE bit (Window Function Setting)
The WCMPE bit enables or disables the window function. Set the WCMPE bit when the ADCSR.ADST bit is 0.
CMPAIE bit (Compare A Interrupt Enable)
The CMPAIE bit enables or disables the ADC140_CMPAI interrupt output when the comparison conditions (window A)
are met.
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30.2.18
30. 14-Bit A/D Converter (ADC14)
A/D Compare Function Window A Channel Select Register 0 (ADCMPANSR0)
Address(es): ADC140.ADCMPANSR0 4005 C094h
Value after reset:
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
CMPC CMPC CMPC CMPC CMPC CMPC CMPC CMPC CMPC CMPC CMPC
HA10 HA09 HA08 HA07 HA06 HA05 HA04 HA03 HA02 HA01 HA00
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
CMPCHA10 to
CMPCHA00
Compare Window A Channel
Select
0: Compare function disabled for associated input channel
1: Compare function enabled for associated input channel.
Bit [10] (CHPCHA10) is associated with AN010 and bit [0]
(CMPCHA00) is associated with AN000.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPCHAn bits (n = 00 to 10) (Compare Window A Channel Select)
The compare function is enabled by writing 1 to the CMPCHAn bit with the same number as the A/D conversion channel
selected in the ADANSA0.ANSAn bits (n = 00 to 10) and the ADANSB0.ANSBn bits (n = 00 to 10).
Set the CMPCHAn bits when the ADCSR.ADST bit is 0.
30.2.19
A/D Compare Function Window A Channel Select Register 1 (ADCMPANSR1)
Address(es): ADC140.ADCMPANSR1 4005 C096h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b6
b5
b4
b3
b2
b1
b0
CMPC CMPC CMPC CMPC CMPC CMPC CMPC
HA22 HA21 HA20 HA19 HA18 HA17 HA16
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
CMPCHA22 to
CMPCHA16
Compare Window A Channel
Select
0: Compare function disabled for associated input channel
1: Compare function enabled for associated input channel.
Bit [6] (CMPCHA22) is associated with AN022 and bit [0]
(CMPCHA16) is associated with AN016.
R/W
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPCHAn bits (n = 16 to 22) (Compare Window A Channel Select)
The compare function is enabled by writing 1 to the CMPCHAn bit with the same number as the A/D conversion channel
selected in the ADANSA1.ANSAn bits (n = 16 to 22) and the ADANSB1.ANSBn bits (n = 16 to 22).
Set the CMPCHAn bits when the ADCSR.ADST bit is 0.
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30.2.20
30. 14-Bit A/D Converter (ADC14)
A/D Compare Function Window A Extended Input Select Register
(ADCMPANSER)
Address(es): ADC140.ADCMPANSER 4005 C092h
b7
b6
b5
b4
b3
b2
—
—
—
—
—
—
0
0
0
0
0
0
Value after reset:
b1
b0
CMPO CMPTS
CA
A
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CMPTSA
Temperature Sensor
Output Compare Select
0: Exclude the temperature sensor output from the compare window
A target range
1: Include the temperature sensor output in the compare window A
target range.
R/W
b1
CMPOCA
Internal Reference
Voltage Compare Select
0: Exclude the internal reference voltage from the compare window A
target range
1: Include the internal reference voltage in the compare window A
target range.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPTSA bit (Temperature Sensor Output Compare Select)
The compare window A function is enabled by setting the CMPTSA bit to 1 when the ADEXICR.TSSA bit is 1. Set the
CMPTSA bit when the ADSCR.ADST bit is 0.
CMPOCA bit (Internal Reference Voltage Compare Select)
The compare window A function is enabled by setting the CMPOCA bit to 1 when the ADEXICR.OCSA bit is 1. Set the
CMPOCA bit when the ADSCR.ADST bit is 0.
30.2.21
A/D Compare Function Window A Comparison Condition Setting Register 0
(ADCMPLR0)
Address(es): ADC140.ADCMPLR0 4005 C098h
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC
HA10 HA09 HA08 HA07 HA06 HA05 HA04 HA03 HA02 HA01 HA00
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b10 to b0
CMPLCHA10
to
CMPLCHA00
Compare Window A
Comparison Condition
Select
These bits set comparison conditions for channels AN000 to AN010
to which window A comparison conditions are applied. Comparison
conditions are shown in Figure 30.3.
When window function is disabled (ADCMPCR.WCMPE = 0):
0: ADCMPDR0 value > A/D-converted value
1: ADCMPDR0 value < A/D-converted value.
When window function is enabled (ADCMPCR.WCMPE = 1):
0: A/D converted value < ADCMPDR0 value or ADCMPDR1 value <
A/D-converted value
1: ADCMPDR0 value < A/D-converted value < ADCMPDR1 value.
R/W
b15 to b11
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPLCHAn bits (n = 00 to 10) (Compare Window A Comparison Condition Select)
The CMPLCHAn bits specify the comparison conditions for channels AN000 to AN010 to which window A comparison
conditions are applied. These bits can be set for each analog input to be compared. CMPLCHA00 is associated with
R01UM0003EU0130 Rev.1.30
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30. 14-Bit A/D Converter (ADC14)
AN000 and CMPLCHA10 is associated with AN010. When the comparison result of each analog input meets the set
condition, the ADCMPSR0.CMPSTCHAn bit is set to 1 and a compare interrupt (ADC140_CMPAI) is generated.
Comparison conditions when the window function is disabled
CMPLCHAn = 0
CMPLCHAn = 1
ADCMPDR0 value A/D converted value
Not met
ADCMPDR0 value < A/D converted value
Met
ADCMPDR0 value > A/D converted value
Met
ADCMPDR0 value A/D converted value
Not met
Comparison conditions when the window function is enabled
CMPLCHAn = 0
ADCMPDR1 value < A/D converted value
ADCMPDR0 value A/D converted value ADCMPDR1 value
A/D converted value < ADCMPDR0 value
Met
Not met
Met
CMPLCHAn = 1
ADCMPDR1 value A/D converted value
ADCMPDR0 value < A/D converted value < ADCMPDR1 value
A/D converted value ADCMPDR0 value
Figure 30.3
Not met
Met
Not met
Comparison conditions for compare function window A
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30.2.22
30. 14-Bit A/D Converter (ADC14)
A/D Compare Function Window A Comparison Condition Setting Register 1
(ADCMPLR1)
Address(es): ADC140.ADCMPLR1 4005 C09Ah
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b6
b5
b4
b3
b2
b1
b0
CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC CMPLC
HA22 HA21 HA20 HA19 HA18 HA17 HA16
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
CMPLCHA22 to
CMPLCHA16
Compare Window A
Comparison Condition
Select
These bits set comparison conditions for channels AN016 to AN022
to which window A comparison conditions are applied. Comparison
conditions are shown in Figure 30.3.
When window function is disabled (ADCMPCR.WCMPE = 0):
0: ADCMPDR0 value > A/D-converted value
1: ADCMPDR0 value < A/D-converted value.
When window function is enabled (ADCMPCR.WCMPE = 1):
0: A/D-converted value < ADCMPDR0 value or ADCMPDR1 value <
A/D-converted value
1: ADCMPDR0 value < A/D-converted value < ADCMPDR1 value.
R/W
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPLCHAn bits (n = 16 to 22) (Compare Window A Comparison Condition Select)
The CMPLCHAn bits specify the comparison conditions for channels AN016 to AN022 to which window A comparison
conditions are applied. These bits can be set for each analog input to be compared. CMPLCHA16 is associated with
AN016 and CMPLCHA22 is associated with AN022. When the comparison result of each analog input meets the set
condition, the ADCMPSR1.CMPSTCHAn bit is set to 1 and a compare interrupt (ADC140_CMPAI) is generated.
30.2.23
A/D Compare Function Window A Extended Input Comparison Condition
Setting Register (ADCMPLER)
Address(es): ADC140.ADCMPLER 4005 C093h
Value after reset:
b7
b6
b5
b4
b3
b2
—
—
—
—
—
—
0
0
0
0
0
0
b1
b0
CMPLO CMPLT
CA
SA
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CMPLTSA
Compare Window A
Temperature Sensor
Output Comparison
Condition Select
Comparison conditions are shown in Figure 30.3.
When window A function is disabled (ADCMPCR.WCMPE = 0):
0: ADCMPDR0 value > A/D-converted value
1: ADCMPDR0 value < A/D-converted value.
When window A function is enabled (ADCMPCR.WCMPE = 1):
0: A/D-converted value < ADCMPDR0 value or A/D-converted value >
ADCMPDR1 value
1: ADCMPDR0 value < A/D-converted value < ADCMPDR1 value.
R/W
b1
CMPLOCA
Compare Window A
Internal Reference
Voltage Comparison
Condition Select
Comparison conditions are shown in Figure 30.3.
When window A function is disabled (ADCMPCR.WCMPE = 0):
0: ADCMPDR0 value > A/D-converted value
1: ADCMPDR0 value < A/D-converted value.
When window A function is enabled (ADCMPCR.WCMPE bit = 1):
0: A/D-converted value < ADCMPDR0 value or A/D-converted value >
ADCMPDR1 value
1: ADCMPDR0 value < A/D-converted value < ADCMPDR1 value.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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30. 14-Bit A/D Converter (ADC14)
CMPLTSA bit (Compare Window A Temperature Sensor Output Comparison Condition Select)
The CMPLTSA bit specifies comparison conditions when the temperature sensor output is the target for the window A
comparison condition. When the temperature sensor output comparison result meets the set condition, the
ADCMPSER.CMPSTTSA bit is set to 1 and a compare interrupt (ADC140_CMPAI) is generated.
CMPLOCA bit (Compare Window A Internal Reference Voltage Comparison Condition Select)
The CMPLOCA bit specifies comparison conditions when the internal reference voltage is the target for the window A
comparison condition. When the internal reference voltage comparison result meets the set condition, the
ADCMPSER.CMPSTOCA bit is set to 1 and a compare interrupt (ADC140_CMPAI) is generated.
30.2.24
A/D Compare Function Window A Lower-Side Level Setting Register
(ADCMPDR0), A/D Compare Function Window A Upper-Side Level Setting
Register (ADCMPDR1), A/D Compare Function Window B Lower-Side Level
Setting Register (ADWINLLB), A/D Compare Function Window B Upper-Side
Level Setting Register (ADWINULB)
Address(es): ADC140.ADCMPDR0 4005 C09Ch, ADC140.ADCMPDR1 4005 C09Eh,
ADC140.ADWINLLB 4005 C0A8h, ADC140.ADWINULB 4005 C0AAh
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
—
—
Reference value
R/W
The ADCMPDRy (y = 0,1) register specifies the reference data when the compare window A function is used.
ADCMPDR0 sets the lower reference for window A, and ADCMPDR1 sets the upper reference for window A.
The ADWINULB and ADWINLLB registers specify the reference data when the compare window B function is used.
ADWINLLB sets the lower reference for window B, and ADWINULB sets the upper reference for window B.
ADCMPDRy, ADWINULB, and ADWINLLB are read/write registers.
ADCMPDRy, ADWINULB, and ADWINLLB are writable even during A/D conversion. The reference data can be
dynamically changed by rewriting register values during A/D conversion*1.
Set these registers so that the upper reference is not less than the lower reference (ADCMPDR1 ADCMPDR0 and
ADWINULB ADWINLLB). ADCMPDR1 and ADWINULB are not used when the window function is disabled.
Note 1. The lower and the upper references are changed when each register is written. For example, when the upper
reference value is changed and the lower reference value is being changed, the MCU compares the upper
reference (after rewrite), and the lower reference (before rewrite) with the A/D conversion result. See Figure 30.4.
If the comparison during the rewriting of these two references is erroneous, then rewrite these reference values
when both ADCSR.ADST and the target Compare Window Operation Enable bit (ADCMPCR.CMPAE or
ADCMPCR.CMPBE) are 0.
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30. 14-Bit A/D Converter (ADC14)
Write Timing
ADCMPDR1/
ADWINULB
Write Timing
ADCMPDR0/
ADWINLLB
Upper reference
(before rewrite)
Upper reference
(after rewrite)
Lower reference
(before rewrite)
A/D conversion 1
Compare the reference
before rewrite
Figure 30.4
Lower reference
(after rewrite)
A/D conversion 2
A/D conversion 3
Compare the upper reference
(after rewrite)
and the lower reference
(before rewrite)
Compare the reference after
rewrite
Comparison between upper reference and lower reference before and after a rewrite
The ADCMPDRy, ADWINLLB, and ADWINULB registers use different formats depending on the following
conditions:
The value of A/D Data Register Format Select bit (flush-right or flush-left)
The value of A/D-Conversion Accuracy Specify bit (14-bit or 12-bit)
The value of A/D-Converted Value Addition/Average Channel Select bits (A/D-converted value addition mode
selected or not selected).
The data formats for each condition are shown as follows:
(1)
When A/D-converted value addition mode is not selected
Flush-right data with 14-bit accuracy — Lower 14 bits ([13:0]) are valid
Flush-right data with 12-bit accuracy — Lower 12 bits ([11:0]) are valid
Flush-left data with 14-bit accuracy — Upper 14 bits ([15:2]) are valid
Flush-left data with 12-bit accuracy — Upper 12 bits ([15:4]) are valid.
(2)
When A/D-converted value addition mode is selected
Flush-right data with 14-bit accuracy — All bits ([15:0]) are valid
Flush-right data with 12-bit accuracy — Lower 14 bits ([13:0]) are valid
Flush-left data with 14-bit accuracy — All bits ([15:0]) are valid
Flush-left data with 12-bit accuracy — Upper 14 bits ([15:2]) are valid.
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30.2.25
30. 14-Bit A/D Converter (ADC14)
A/D Compare Function Window A Channel Status Register 0 (ADCMPSR0)
Address(es): ADC140.ADCMPSR0 4005 C0A0h
b15
b14
b13
b12
b11
—
—
—
—
—
0
0
0
0
0
Value after reset:
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
CMPST CMPST CMPST CMPST CMPST CMPST CMPST CMPST CMPST CMPST CMPST
CHA10 CHA09 CHA08 CHA07 CHA06 CHA05 CHA04 CHA03 CHA02 CHA01 CHA00
0
0
0
0
0
0
0
0
0
0
Description
0
Bit
Symbol
Bit name
R/W
b10 to b0
CMPSTCHA10 to
CMPSTCHA00
Compare Window A Flag When window A operation is enabled (ADCMPCR.CMPAE = 1),
these bits indicate the comparison result of channels AN000 to
AN010 to which window A comparison conditions are applied.
0: Comparison conditions are not met
1: Comparison conditions are met.
R/W
b15 to b11
—
Reserved
R/W
These bits are read as 0. The write value should be 0.
CMPSTCHAn bits (n = 00 to 10) (Compare Window A Flag)
The CMPSTCHAn bits are comparison result status flags of channels AN000 to AN010 to which window A comparison
conditions are applied. When a comparison condition set in ADCMPLR0.CMPLCHAn is met at the end of A/D
conversion, the associated CMPSTCHAn bit is set to 1. When the ADCMPCR.CMPAIE bit is 1, a compare interrupt
(ADC140_CMPAI) request is generated when a CMPSTCHAn bit is set to 1. CMPSTCHA00 is associated with AN000
and CMPSTCHA10 is associated with AN010.
Writing 1 to the CMPSTCHAn bits is disabled.
[Setting condition]
The condition set in ADCMPLR0.CMPLCHAn is met when ADCMPCR.CMPAE = 1.
[Clearing condition]
Writing 0 after reading 1.
30.2.26
A/D Compare Function Window A Channel Status Register1 (ADCMPSR1)
Address(es): ADC140.ADCMPSR1 4005 C0A2h
b15
Value after reset:
b14
b13
b12
b11
b10
b9
b8
b7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
b6
b5
b4
b3
b2
b1
b0
CMPST CMPST CMPST CMPST CMPST CMPST CMPST
CHA22 CHA21 CHA20 CHA19 CHA18 CHA17 CHA16
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b6 to b0
CMPSTCHA22 to
CMPSTCHA16
Compare Window A Flag
When window A operation is enabled (ADCMPCR.CMPAE = 1),
these bits indicate the comparison result of channels AN016 to
AN022 to which window A comparison conditions are applied.
0: Comparison conditions not met
1: Comparison conditions met.
R/W
b15 to b7
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPSTCHAn bits (n = 16 to 22) (Compare Window A Flag)
The CMPSTCHAn bits are comparison result status flags of channels AN016 to AN022 to which window A comparison
conditions are applied. When a comparison condition set in ADCMPLR1.CMPLCHAn is met at the end of A/D
conversion, the associated CMPSTCHAn bit is set to 1. When the ADCMPCR.CMPAIE bit is 1, a compare interrupt
(ADC140_CMPAI) request is generated when a CMPSTCHAn bit is set to 1. CMPSTCHA16 is associated with AN016
and CMPSTCHA22 is associated with AN022.
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30. 14-Bit A/D Converter (ADC14)
Writing 1 to the CMPSTCHAn bits is disabled.
[Setting condition]
The condition set in ADCMPLR1.CMPLCHAn is met when ADCMPCR.CMPAE = 1.
[Clearing condition]
Writing 0 after reading 1.
30.2.27
A/D Compare Function Window A Extended Input Channel Status Register
(ADCMPSER)
Address(es): ADC140.ADCMPSER 4005 C0A4h
Value after reset:
b7
b6
b5
b4
b3
b2
—
—
—
—
—
—
0
0
0
0
0
0
b1
b0
CMPST CMPST
OCA
TSA
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CMPSTTSA
Compare Window A
Temperature Sensor Output
Compare Flag
When window A operation is enabled (ADCMPCR.CMPAE = 1),
this bit indicates the temperature sensor output comparison
result.
0: Comparison conditions not met
1: Comparison conditions met.
R/W
b1
CMPSTOCA
Compare Window A Internal
Reference Voltage Compare
Flag
When window A operation is enabled (ADCMPCR.CMPAE = 1),
this bit indicates the internal reference voltage comparison
result.
0: Comparison conditions not met
1: Comparison conditions met.
R/W
b7 to b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
CMPSTTSA bit (Compare Window A Temperature Sensor Output Compare Flag)
The CMPSTTSA bit is a status flag that indicates the temperature sensor output comparison result. When the comparison
condition set in the ADCMPLER.CMPLTSA bit is met at the end of A/D conversion, the CMPSTTSA bit is set to 1.
When the ADCMPCR.CMPAIE bit is 1, a compare interrupt (ADC140_CMPAI) request is generated when the
CMPSTTSA bit is set to 1.
Writing 1 to the CMPSTTSA bit is disabled.
[Setting condition]
The condition set in ADCMPLER.CMPLTSA is met when ADCMPCR.CMPAE = 1.
[Clearing condition]
Writing 0 after reading 1.
CMPSTOCA bit (Compare Window A Internal Reference Voltage Compare Flag)
The CMPSTOCA bit is a status flag that indicates the internal reference voltage comparison result. When the comparison
condition set in the ADCMPLER.CMPLOCA bit is met at the end of A/D conversion, the CMPSTOCA bit is set to 1.
When the ADCMPCR.CMPAIE bit is 1, a compare interrupt (ADC140_CMPAI) request is generated when the
CMPSTOCA bit is set to 1.
Writing 1 to the CMPSTOCA bit is disabled.
[Setting condition]
The condition set in ADCMPLER.CMPLOCA is met when ADCMPCR.CMPAE = 1.
[Clearing condition]
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30. 14-Bit A/D Converter (ADC14)
Writing 0 after reading 1.
30.2.28
A/D Compare Function Window B Channel Select Register (ADCMPBNSR)
Address(es): ADC140.ADCMPBNSR 4005 C0A6h
b7
b6
CMPLB
—
0
0
Value after reset:
b5
b4
b3
b2
b1
b0
0
0
CMPCHB[5:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b5 to b0
CMPCHB[5:0]
Compare Window B Channel
Select
These bits select the channel to be compared with the compare
window B conditions.
R/W
b5
0 0 0 0
0 0 0 0
0 0 0 0
:
0 0 1 0
0 1 0 0
:
:
0 1 0 1
0 1 0 1
0 1 0 1
1 0 0 0
1 0 0 0
1 1 1 1
b0
0 0: AN000
0 1: AN001
1 0: AN002
:
1 0: AN010
0 0: AN016
:
:
0 0: AN020
0 1: AN021
1 0: AN022
0 0: Temperature sensor
0 1: Internal reference voltage
1 1: Do not select.
Other settings are prohibited.
b6
—
Reserved
This bit is read as 0. The write value should be 0.
b7
CMPLB
Compare Window B
Comparison Condition Setting
This bit sets comparison conditions of channels for window B.
R/W
The comparison conditions are shown in Figure 30.5.
When window function is disabled (ADCMPCR.WCMPE = 0):
0: CMPLLB value > A/D-converted value
1: CMPLLB value < A/D-converted value.
When window function is enabled (ADCMPCR.WCMPE = 1):
0: A/D converted value < CMPLLB value or CMPULB value < A/
D-converted value
1: CMPLLB value < A/D-converted value < CMPULB value.
R/W
CMPCHB[5:0] bits (Compare Window B Channel Select)
The CMPCHB[5:0] bits select the channel to be compared with the compare window B conditions from AN000 to
AN010, AN016 to AN022, the temperature sensor, and the internal reference voltage. The compare window B function
is enabled by specifying the hexadecimal number of an A/D conversion channel selected in the ADANSA0.ANSAn bits
(n = 0 to 10), ADANSA1.ANSAn bits (n = 16 to 22), ADANSB0.ANSBn bits (n = 0 to 10), and ADANSB1.ANSBn bits
(n = 16 to 22).
Set the CMPCHB[5:0] bits when the ADCSR.ADST bit is 0.
CMPLB bit (Compare Window B Comparison Condition Setting)
The CMPLB bit sets comparison conditions of channels for window B. When the comparison result of each analog input
meets the set condition, the ADCMPBSR.CMPSTB bit is set to 1 and a compare interrupt request (ADC140_CMPBI) is
generated.
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30. 14-Bit A/D Converter (ADC14)
Compare conditions when the window function is disabled
CMPLB = 0
CMPLB = 1
ADWINLLB value A/D converted value
Not met
ADWINLLB value < A/D converted value
Met
ADWINLLB value > A/D converted value
Met
ADWINLLB value A/D converted value
Not met
Compare conditions when the window function is enabled
CMPLB = 0
Met
A/D converted value > ADWINULB value
ADWINLLB value A/D converted value ADWINULB value
Not met
A/D converted value < ADWINLLB value
Met
CMPLB = 1
A/D converted value ADWINULB value
Not met
ADWINLLB value internal reference
voltage.
When the window function is enabled:
0: CMPIN0 < VRFL, CMPIN0 > VRFH, or ACMPLP0
operation disabled
1: VRFL < CMPIN0 < VRFH.
R
b4
C1ENB
ACMPLP1 Operation Enable
0: Disable comparator channel ACMPLP1
1: Enable comparator channel ACMPLP1.
R/W
b5
C1WDE
ACMPLP1 Window Function Mode
Enable*1,*2
0: Disable window function for ACMPLP1
1: Enable window function for ACMPLP1.
R/W
b6
C1VRF
ACMPLP1 Reference Voltage
Selection
0: Select CMPREF1 input as ACMPLP1 reference voltage
1: Select internal reference voltage (Vref) as ACMPLP1
reference voltage.
R/W
b7
C1MON
ACMPLP1 Monitor Flag*3
When the window function is disabled:
0: CMPIN1 < CMPREF1, CMPIN1 < internal reference
voltage, or ACMPLP1 operation disabled
1: CMPIN1 > CMPREF1, or CMPIN1 > internal reference
voltage.
When the window function is enabled:
0: CMPIN1 < VRFL, CMPIN1 > VRFH, or ACMPLP1
operation disabled
1: VRFL < CMPIN1 < VRFH.
R
Note 1. Window function mode cannot be set when low-speed mode is selected (the SPDMD bit in the COMPOCR
register is 0).
Note 2. In window function mode, the reference voltage in the comparator is selected regardless of the setting of this bit.
Note 3. The initial value is 0 immediately after a reset is released. However, the value is undefined when C0ENB is set to
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33. Low-Power Analog Comparator (ACMPLP)
0 and C1ENB is set to 0 after operation of the comparator is enabled once.
33.2.2
ACMPLP Filter Control Register (COMPFIR)
Address(es): ACMPLP.COMPFIR 4008 5E01h
b7
b6
b5
C1EDG C1EPO
0
Value after reset:
Bit
0
C1FCK[1:0]
0
Symbol
b4
b3
b2
b1
C0EDG C0EPO
0
0
b0
C0FCK[1:0]
0
0
0
Bit name
Select*1
Description
R/W
b1 b0
R/W
b1, b0
C0FCK[1:0]
ACMPLP0 Filter
b2
C0EPO
ACMPLP0 Edge Polarity
Switching*1
0: Interrupt and ELC event request at rising edge
1: Interrupt and ELC event request at falling edge.
R/W
b3
C0EDG
ACMPLP0 Edge Detection
Selection*1
0: Interrupt and ELC event request by one-edge detection
1: Interrupt and ELC event request by both-edge detection.
R/W
b5, b4
C1FCK[1:0]
ACMPLP1 Filter Select*1
b5 b4
R/W
b6
C1EPO
ACMPLP1 Edge Polarity
Switching*1
0: Interrupt and ELC event request at rising edge
1: Interrupt and ELC event request at falling edge.
R/W
b7
C1EDG
ACMPLP1 Edge Detection
Selection*1
0: Interrupt and ELC event request by one-edge detection
1: Interrupt and ELC event request by both-edge detection.
R/W
0
0
1
1
0
0
1
1
0: No Sampling (bypass)
1: Sampling at PCLKB
0: Sampling at PCLKB/8
1: Sampling at PCLKB/32.
0: No Sampling (bypass)
1: Sampling at PCLKB
0: Sampling at PCLKB/8
1: Sampling at PCLKB/32.
Note 1. If bits CiFCK[1:0], CiEPO, and CiEDG (i = 0, 1) are changed, an ACMPLP interrupt request and an ELC event
request can be generated. Change these bits only after setting event link to deselected. Also, be sure to clear
corresponding interrupt request flag.
33.2.3
ACMPLP Output Control Register (COMPOCR)
Address(es): ACMPLP.COMPOCR 4008 5E02h
b7
b6
b5
b4
b3
b2
b1
b0
SPDM
D
C1OP
C1OE
—
—
C0OP
C0OE
—
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
—
Reserved
This bit is read as 0. The write value should be 0.
R
b1
C0OE
ACMPLP0 VCOUT Pin Output
Enable*1
0: Disabled
1: Enabled.
R/W
b2
C0OP
ACMPLP0 VCOUT Output Polarity
Selection*1
0: Non-inverted
1: Inverted.
R/W
b4, b3
—
Reserved
These bits are read as 0. The write value should be 0.
R
b5
C1OE
ACMPLP1 VCOUT Pin Output
Enable*1
0: Disabled
1: Enabled.
R/W
b6
C1OP
ACMPLP1 VCOUT Output Polarity
Selection*1
0: Non-inverted
1: Inverted.
R/W
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33. Low-Power Analog Comparator (ACMPLP)
Bit
Symbol
Bit name
Description
R/W
b7
SPDMD
ACMPLP0/ACMPLP1 Speed
Selection*2
0: Select comparator low-speed mode
1: Select comparator high-speed mode.
R/W
Note 1. ACMPLP0 and ACMPLP1 result outputs are bundled on the VCOUT pin.
Note 2. Set the CiENB bits (i = 0, 1) in the COMPMDR register to 0 before rewriting the SPDMD bit.
33.3
Operation
ACMPLP0 and ACMPLP1 operate independently, and their operations are the same. Operation is not guaranteed when
the values of their associated registers are changed during comparator operation. Table 33.3 shows the procedure for
setting the ACMPLP associated registers.
Table 33.3
Procedure for setting the ACMPLP associated registers (i = 0, 1)
Step
No.
Register
1
MSTPCRD
MSTPD29
0: Input clock supply
2
Corresponding Port mn
Pin Function Select
Register (PmnPFS)
ASEL
1: Select the function of pins CMPREFi and CMPINi.
3
COMPOCR
SPDMD
Select the comparator response speed
(0: Low-speed mode / 1: High-speed mode)*1
4
COMPMDR
CiWDE
0: Disable window function mode
1: Enable window
function mode*2
CiVRF
0: Reference =
CMPREFi input
Window comparator
operation (reference =
VRFL and VRFH*3)
CiENB
1: Operation enabled
Bit
Setting
5
Wait for the comparator stabilization time Tcmp (minimum 100 μs).
6
COMPFIR
1: Reference = Internal
reference voltage
CiFCK[1:0]
Select whether the digital filter is used or not and the sampling clock.
CiEPO, CiEDG
Select the edge detection condition for an interrupt request (rising edge/
falling edge/both edges).
COMPOCR
CiOP, CiOE
Set the VCOUT output (select the polarity and set output enabled or
disabled).
Corresponding Port mn
Pin Function Select
Register (PmnPFS)
PSEL, PMR
Select the VCOUT port function.
8
IELSRn
IR, IELS[7:0]
When using an interrupt: select the interrupt status flag, ICU event link
select.*3
9
ELSRn
ELS[7:0]
When using an ELC: Select the Event Link Select.*4
10
Operation started
7
Note 1. ACMPLP0 and ACMPLP1 cannot be set independently.
Note 2. Can be set in high-speed mode (SPDMD = 1).
Note 3. After the setting of the comparator, a spurious interrupt may occur until operation becomes stable, so initialize the
interrupt flag.
Note 4. After the setting of the comparator, a spurious interrupt may occur until operation becomes stable, so initialize the
event link select.
Figure 33.3 shows an operating example of the ACMPLPi (i = 0, 1) when the window function is disabled. The reference
input voltage (CMPREFi) or internal reference voltage (Vref) and the analog input voltage (CMPINi) are compared. If
the analog input voltage is higher than the reference input voltage, the COMPMDR.CiMON bit is set to 1. If the analog
input voltage is lower than the reference input voltage, the CiMON bit is set to 0.
ACMPLPi outputs an interrupt to ICU. For details on the interrupt, see section 33.5, ACMPLP Interrupts.
ACMPLPi outputs an event signal to the ELC to activate other modules. For details on the ELC, see section 33.6, ELC
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33. Low-Power Analog Comparator (ACMPLP)
Event Output.
Analog input voltage (V)
Do not change the values of the registers during comparison.
Reference input voltage
0
COMPMDR.CiMON bit (I = 0, 1)
IELSRn.IR flag
in ICU
1
0
1
0
(A)
(B)
(A)
Set to 0 by program
Figure 33.3
Operating example of ACMPLPi (i = 0, 1) when window function is disabled
Figure 33.3 applies when the following conditions are met:
CiFCK[1:0] = 00b (no sampling) and CiEDG = 1 (both edges).
When CiEDG = 0 and CiEPO = 0 (rising edge), IELSRn.IR changes as shown by (A) only.
When CiEDG = 0 and CiEPO = 1 (falling edge), IELSRn.IR changes as shown by (B) only.
Figure 33.4 shows an operation example of ACMPLPi (i = 0, 1) when the window function is enabled. The internal Vref
(VRFL/VRFH) and the analog input voltage are compared. The CiMON bit is set to 1 when VRFL < the analog input
voltage < VRFH, and the CiMON bit is set to 0 when the analog input voltage < VRFL, or VRFH < the analog input
voltage.
ACMPLPi outputs an interrupt to ICU. For details on the interrupt, see section 33.5, ACMPLP Interrupts.
ACMPLPi outputs an event signal to the ELC to activate other modules. For details on the ELC, see section 33.6, ELC
Event Output.
Do not change the values of the registers during comparison.
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Analog input voltage (V)
S124 User’s Manual
33. Low-Power Analog Comparator (ACMPLP)
Reference input voltage
(VRFH)
Reference input voltage
(VRFL)
0
COMPMDR.CiMON bit (i = 0, 1)
1
0
IELSRn.IR flag
in the ICU
1
0
(A)
(B)
(A)
(B)
(A)
(B)
Set to 0 by program
Figure 33.4
Operating example of ACMPLPi (i = 0, 1) when window function is enabled
Figure 33.4 applies when the following conditions are met:
CiFCK[1:0] = 00b (no sampling) and
CiEDG = 1 (both edges).
When CiEDG = 0 and CiEPO = 0 (rising edge), IELSRn.IR changes as shown by (A) only.
When CiEDG = 0 and CiEPO = 1 (falling edge), IELSRn.IR changes as shown by (B) only.
33.4
Noise Filter
Figure 33.5 shows the configuration of the ACMPLPi noise filter and Figure 33.6 shows an operating example of the
ACMPLPi noise filter.
The sampling clock can be selected in the COMPFIR.CiFCK[1:0] bits. The ACMP_LPi signal (internal signal) output
from ACMPLPi is sampled at every sampling clock cycle. When the level matches three times, the corresponding
IELSRn.IR bit is set to 1 (interrupt requested) and an ELC event is output.
When using an interrupt and ELC in Software Standby mode, set the COMPFIR.CiFCK[1:0] bits to 00b (bypass).
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33. Low-Power Analog Comparator (ACMPLP)
C1MON
C1EDG
C0MON
C0EDG
ACMPLP1
signal
Noise reduction
filter (same value
sampled 3 times)
else
0
00
1
ACMP_LP1
interrupt request
ELC event request
Edge
selector
1
CPLOUT1
0
ACMPLP0
signal
Noise reduction
filter (same value
sampled 3 times)
else
0
00
1
ACMP_LP0
interrupt request
ELC event request
Edge
selector
1
CPLOUT0
0
Figure 33.5
C1FCK[1:0]
C1EPO
C1OP
C1OE
C0FCK[1:0]
C0EPO
C0OP
C0OE
Noise filter and edge detection configuration
Noise filter input
Sampling timing
Unless the same value is sampled 3
consecutive times, it is assumed to be noise
and the IR flag does not change .
IELSRn.IR flag
in ICU
Since the same value is
sampled 3 times, it is
recognized as a signal
change and the IR flag
changes to 1.
Set to 0 by program .
Figure 33.6
33.5
Noise filter and interrupt operation example
ACMPLP Interrupts
The ACMPLP generates two interrupt requests from sources ACMPLP0 and ACMPLP1. The ACMPLPi (i = 0 and 1)
interrupt can be used by selecting it in the IELSRn register in the Interrupt Controller Unit.
To use the ACMPLPi interrupt, select either single-edge detection or both-edge detection using the COMPFIR.CiEDG
bit. When single-edge detection is selected, select the polarity using the CiEPO bit.
The interrupt output can also be passed through the noise filter, which uses one of three different sampling clocks, as
selected in the COMPFIR.CiFCK[1:0] bits. Set the COMPFIR.CiFCK[1:0] bits to 01b, 10b, or 11b to select the
respective sampling clock. To use the ACMPLP0 interrupt request to release Software Standby mode or Snooze mode,
set COMPFIR.C0FCK[1:0] to 00b to bypass the ACMPLP0 noise filter. The ACMPLP1 interrupt request cannot be used
to release Software Standby mode or Snooze mode.
33.6
ELC Event Output
The Event Link Controller (ELC) uses the ACMPLPi interrupt request signal as an ELC event signal, enabling link
operation for the preset module. The ELC event of ACMPLPi can be used by selecting it in the ELSRn register in the
ELC. When using the ACMPLPi ELC event request, set the COMPFIR.CiFCK[1:0] bits to 01b, 10b, or 11b.
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33.7
33. Low-Power Analog Comparator (ACMPLP)
Interrupt Handling and ELC Linking
ACMPLPi outputs event signals to the ELC to initiate operations of other modules selected in advance. In the same way
as for the interrupt sources, the conditions for generation of the event signals output from ACMPLPi to the ELC can be
selected as a single-edge detection or both-edge detection by setting the COMPFIR.CiEDG bit. When the single-edge
detection is selected, the polarity can be selected in the CiEPO bit.
33.8
Comparator Pin Output
The comparison result from ACMPLPi can be output to external pins. The COMPOCR.CiOP and CiOE bits can be used
to set the output polarity (non-inverted output or inverted output) and to enable or disable the output.
To output the ACMPLP comparison result to the VCOUT output pin, set the corresponding Port mn Pin Function Select
Register (PmnPFS) in the I/O register.
33.9
Usage Notes
33.9.1
Settings for the Module-Stop State
The Module Stop Control Register can enable or disable ACMPLP operation. The ACMPLP is initially stopped after
reset. Release the module-stop state enables access to the registers. For details, see section 10, Low Power Modes.
33.9.2
Relationship between ADC14 and ACMPLP
The A/D conversion targets in Table 33.4 cannot be selected as an ACMPLP input during A/D conversion.
Table 33.4
Relationship between ADC14 and ACMPLP
Target of A/D conversion
ACMPLP
AN019
CMPREF1
AN020
CMPIN1
AN021
CMPREF0
AN022
CMPIN0
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34.
34. Capacitive Touch Sensing Unit (CTSU)
Capacitive Touch Sensing Unit (CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the
electrostatic capacitance are determined by software that enables the CTSU to detect whether a finger is in contact with
the touch sensor. The electrode surface of the touch sensor is usually enclosed with an electrical insulator so that fingers
do not come into direct contact with the electrode.
As Figure 34.1 shows, electrostatic capacitance (parasitic capacitance) exists between the electrode and the surrounding
insulators. Because the human body is an electrical conductor, when a finger is placed close to the electrode, the
electrostatic capacitance increases.
Circuit board pattern
Circuit board pattern
Touch
electrode
Touch
electrode
MCU
MCU
Metal enclosure
Figure 34.1
Finger
Ground
Ground
Metal enclosure
Increased electrostatic capacitance because of the presence of a finger
Electrostatic capacitance is detected by the self-capacitance and mutual capacitance methods. In the self-capacitance
method, the CTSU detects electrostatic capacitance generated between a finger and a single electrode. In the mutual
capacitance method, two electrodes are used as a transmit electrode and a receive electrode, and the CTSU detects the
change in the electrostatic capacitance generated between the two when a finger is placed close to them.
Self-capacitance method
Mutual capacitance method
Electrical insulator
(panel)
Electrode
board
Touch electrode
Figure 34.2
MCU
MCU
(transmission)
(reception)
Self-capacitance and mutual capacitance methods
Electrostatic capacitance is measured by counting a clock signal whose frequency changes according to the amount of
charged or discharged current, for a specified period. For details on the measurement principles of the CTSU, see section
34.3.1, Principles of Measurement Operation.
34.1
Overview
Table 34.1 lists the specifications of the CTSU and Figure 34.3 shows a block diagram of the CTSU.
Table 34.1
CTSU specifications (1 of 2)
Parameter
Description
Operating clock
PCLKB, PCLKB/2, or PCLKB/4
Pins
Electrostatic capacitance
measurement
31 channels (TS00 to TS28, TS30, TS31)
TSCAP
Low Pass Filter (LPF) connection pin
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Table 34.1
34. Capacitive Touch Sensing Unit (CTSU)
CTSU specifications (2 of 2)
Parameter
Description
Measurement
modes
Self-capacitance single scan mode
Electrostatic capacitance is measured on one channel using the selfcapacitance method
Self-capacitance multi-scan mode
Electrostatic capacitance is measured on multiple channels successively
using the self-capacitance method
Mutual capacitance full scan mode
Electrostatic capacitance is measured successively on multiple channels
using the mutual capacitance method
Noise prevention
Synchronous noise prevention, high-pass noise prevention
Measurement start conditions
Software trigger
External trigger (ELC_CTSU from the ELC).
As Figure 34.3 shows, the CTSU consists of the following components:
Status control block
Trigger control block
Clock control block
Channel control block
Port control block
Sensor drive pulse generator
Measurement block
Interrupt block
I/O registers.
I/O block
Capacitive Touch Sensing Unit (CTSU)
Touch I/O
PCLKB
PCLKB/2
PCLKB/4
Clock
control
block
System control block
Memory
Data bus
Count
source
Sensor drive
pulse generator
ICU
CTSU_CTSURD
interrupt request
Measurement
block
(counter
measurement)
• CTSUSC register
• CTSURC register
Interrupt
block
Port control
CTSU_CTSUFN
interrupt request
TSn*1
Port
control
Sensor drive pulse
Diffusion clock
Operation enabled
Offset control
Status
control
CTSU_CTSUWR
interrupt request
DTC
CPU
Channel
control block
Port
control
block
Diffusion clock
Power supply
control
Power
supply
Event input from the ELC
Trigger
control block
Sensor ICO
Reference ICO
TSCAP I/O
TSCAP
Sensor ICO clock
Reference ICO clock
LPF
I/O register (control register)
ICO: Intensity of Current Controlled Oscillator
Note 1. n = 00 to 28, 30, 31
Figure 34.3
CTSU block diagram
Table 34.2
CTSU pin configuration
Pin name
I/O
Function
TS00 to TS28, TS30, TS31
Input
Electrostatic capacitive measurement pins (touch pins)
TSCAP
-
LPF connection pin
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34.2
34. Capacitive Touch Sensing Unit (CTSU)
Register Descriptions
34.2.1
CTSU Control Register 0 (CTSUCR0)
Address(es): CTSU.CTSUCR0 4008 1000h
Value after reset:
Bit
b7
b6
b5
b4
b3
—
—
—
CTSUI
NIT
—
0
0
0
0
0
Symbol
b2
b1
b0
CTSUS CTSUC CTSUS
NZ
AP
TRT
0
Bit name
0
0
Description
R/W
operation*1
b0
CTSUSTRT
CTSU Measurement Operation
Start
0: Stop measurement
1: Start measurement operation.
R/W
b1
CTSUCAP
CTSU Measurement Operation
Start Trigger Select
0: Software trigger
1: External trigger.
R/W
b2
CTSUSNZ
CTSU Wait State Power-Saving
Enable
0: Disable power-saving function during wait state
1: Enable power-saving function during wait state.
R/W
b3
-
Reserved
This bit read as 0. The write value should be 0.
R/W
b4
CTSUINIT
CTSU Control Block
Initialization
Writing 1 to this bit initializes the CTSU control block and
CTSUSC, CTSURC, CTSUMCH0, CTSUMCH1, and CTSUST
registers. This bit is read as 0.
R/W
b7 to b5
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Note 1. When the CTSU is not used, fix the value of this bit to 0.
Only set the CTSUCAP and CTSUSNZ bits when the CTSUSTRT bit is 0. These bits can be set at the same time that
measurement operation starts.
CTSUSTRT bit (CTSU Measurement Operation Start)
The CTSUSTRT bit specifies whether CTSU operation starts or stops.
When the CTSUCAP bit is 0, measurement starts when software writes 1 to the CTSUSTRT bit (software trigger) and
stops when hardware clears the CTSUSTRT bit to 0. When the CTSUCAP bit is 1, the CTSU waits for an external
trigger by writing 1 to the CTSUSTRT bit, and measurement starts on the rising edge of the external trigger. When
measurement is stopped, the CTSU waits for the next external trigger and operation continues.
Table 34.3 lists the CTSU states.
Table 34.3
CTSU states
CTSUSTRT bit
CTSUCAP bit
CTSU state
0
0
Stopped
0
1
Stopped
1
0
Measurement in progress
1
1
Measurement in progress and waiting for an external trigger*1
Note 1. The state can be read from the CTSUST.CTSUSTC[2:0] flags as follows:
- During measurement: CTSUST.CTSUSTC[2:0] flags ≠ 000b
- While waiting for an external trigger: CTSUST.CTSUSTC[2:0] flags = 000b.
If software sets the CTSUSTRT bit to 1 when the bit is already 1, the write is ignored and operation continues. To force
operation to stop through the software when the CTSUSTRT bit is 1, set the CTSUSTRT bit to 0 and the CTSUINIT bit
to 1 at the same time.
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34. Capacitive Touch Sensing Unit (CTSU)
CTSUCAP bit (CTSU Measurement Operation Start Trigger Select)
The CTSUCAP bit specifies the measurement start condition. For details, see CTSUSTRT bit (CTSU Measurement
Operation Start).
CTSUSNZ bit (CTSU Wait State Power-Saving Enable)
The CTSUSNZ bit enables or disables power-saving operation during a wait state. It can also suspend the CTSU power
supply, which decreases power consumption during the wait state. In the suspended state, the CTSU power supply is
turned off while the external TSCAP is still charged.
Table 34.4 shows the CTSU power supply state control.
Table 34.4
CTSU power supply state control
CTSUCR1.CTSUPON bit
CTSUSNZ bit
CTSUCAP bit
CTSUSTRT bit
CTSU power supply state
0
0
0
0
Stopped
1
0
—
—
Operating
1
1
0
0
Suspended
Note:
Settings other than those listed in the table are prohibited.
To start measurement from the suspended state, set the CTSUSNZ bit to 0, and then set the CTSUSTRT bit to 1. To
suspend the module after measurement stops, set the CTSUSNZ bit to 1.
CTSUINIT bit (CTSU Control Block Initialization)
Write 1 to the CTSUINIT bit to initialize the internal control registers. To force the current operation to stop, set the
CTSUSTRT bit to 0 and the CTSUINIT bit to 1 at the same time. This stops the operation and initializes the internal
control registers.
Do not write 1 to the CTSUINIT bit when the CTSUSTRT bit is 1.
34.2.2
CTSU Control Register 1 (CTSUCR1)
Address(es): CTSU.CTSUCR1 4008 1001h
b7
b6
CTSUMD[1:0]
Value after reset:
0
0
b5
b4
b3
b2
b1
b0
CTSUCLK[1:0] CTSUA CTSUA CTSUC CTSUP
TUNE1 TUNE0 SW
ON
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
CTSUPON
CTSU Power Supply Enable
0: Power off the CTSU
1: Power on the CTSU.
R/W
b1
CTSUCSW
CTSU LPF Capacitance Charging
Control
This bit controls charging of the LPF capacitance
connected to the TSCAP pin:
0: Turn off capacitance switch
1: Turn on capacitance switch.
R/W
b2
CTSUATUNE0
CTSU Power Supply Operating
Mode Setting
VCC ≥ 2.4 V:
0: Normal operating mode
1: Low-voltage operating mode.
VCC < 2.4 V:
0: Setting prohibited
1: Low-voltage operating mode.
R/W
b3
CTSUATUNE1
CTSU Power Supply Capacity
Adjustment
0: Normal output
1: High-current output.
R/W
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34. Capacitive Touch Sensing Unit (CTSU)
Bit
Symbol
Bit name
Description
b5, b4
CTSUCLK[1:0]
CTSU Operating Clock Select
b5 b4
b7, b6
CTSUMD[1:0]
CTSU Measurement Mode Select
b7 b6
0
0
1
1
0
0
1
1
0:
1:
0:
1:
0:
1:
0:
1:
R/W
R/W
PCLKB
PCLKB/2
PCLKB/4
Setting prohibited.
R/W
Self-capacitance single scan mode
Self-capacitance multi-scan mode
Setting prohibited
Mutual capacitance full scan mode.
Only set the CTSUCR1 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUPON bit (CTSU Power Supply Enable)
The CTSUPON bit controls the power supply to the CTSU. Set the CTSUPON and CTSUCSW bits to the same value.
CTSUCSW bit (CTSU LPF Capacitance Charging Control)
The CTSUCSW bit controls charging of the LPF capacitor connected to the TSCAP pin by turning the capacitance
switch on or off. After the capacitance switch is turned on, wait until the capacitance connected to the TSCAP pin is
charged for the specified time before starting measurement by setting CTSUCR0.CTSUSTRT to 1. Before starting
measurement, use an I/O port to output low to the TSCAP pin, and discharge the existing LPF capacitance. Set the
CTSUPON and CTSUCSW bits to the same value.
CTSUATUNE0 bit (CTSU Power Supply Operating Mode Setting)
The CTSUATUNE0 bit sets the power supply operating mode. Set this bit according to the lower limit of VCC for
operating the CTSU. For example, when using touch measurement in a system where VCC varies depending on the
battery operation, set this bit to 1 regardless of the initial VCC voltage. The VCC voltage range is 2 to 3 V.
CTSUATUNE1 bit (CTSU Power Supply Capacity Adjustment)
The CTSUATUNE1 bit sets the capacity of the CTSU power supply. In general, a setting of 0 is recommended.
CTSUCLK[1:0] bits (CTSU Operating Clock Select)
The CTSUCLK[1:0] bits select the operating clock.
CTSUMD[1:0] bits (CTSU Measurement Mode Select)
The CTSUMD[1:0] bits set the measurement mode. For details, see section 34.3.2, Measurement Modes.
34.2.3
CTSU Synchronous Noise Reduction Setting Register (CTSUSDPRS)
Address(es): CTSU.CTSUSDPRS 4008 1002h
b7
—
Value after reset:
0
b6
b5
b4
b3
CTSUS CTSUPRMODE[
OFF
1:0]
0
0
0
b2
b1
b0
CTSUPRRATIO[3:0]
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b3 to b0
CTSUPRRATIO
[3:0]
CTSU Measurement Time and Pulse
Count Adjustment
These bits set the measurement time and
measurement pulse count. The recommended setting
is 3 (0011b).
R/W
b5, b4
CTSUPRMODE
[1:0]
CTSU Base Period and Pulse Count
Setting
These bits set the base pulse count:
R/W
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
b5 b4
0
0
1
1
0:
1:
0:
1:
510 pulses
126 pulses
62 pulses (recommended setting)
Setting prohibited.
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34. Capacitive Touch Sensing Unit (CTSU)
Bit
Symbol
Bit name
Description
R/W
b6
CTSUSOFF
CTSU High-Pass Noise Reduction
Function Off Setting
This bit controls spectrum diffusion, which can be used
to reduce high-pass noise:
0: Turn spectrum diffusion on
1: Turn spectrum diffusion off.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Only set the CTSUSDPRS register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUPRRATIO[3:0] bits (CTSU Measurement Time and Pulse Count Adjustment)
The CTSUPRRATIO[3:0] bits set the measurement time and the number of measurement pulses using the following
formulas, where the number of base pulses is determined by the CTSUPRMODE[1:0] setting:
Measurement pulse count = base pulse count × (CTSUPRRATIO[3:0] bits + 1)
Measurement time = (base pulse count × (CTSUPRRATIO[3:0] bits + 1) + base pulse count - 2) × 0.25 × base clock
cycle
Note:
For details on the base clock cycle, see section 34.2.19, CTSU Sensor Offset Register 1 (CTSUSO1).
CTSUPRMODE[1:0] bits (CTSU Base Period and Pulse Count Setting)
The CTSUPRMODE[1:0] bits select the number of base pulses that occur during measurement.
CTSUSOFF bit (CTSU High-Pass Noise Reduction Function Off Setting)
The CTSUSOFF bit turns on or off the function for reducing high-pass noise. Set this bit to 1 to turn the function off.
34.2.4
CTSU Sensor Stabilization Wait Control Register (CTSUSST)
Address(es): CTSU.CTSUSST 4008 1003h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUSST[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUSST[7:0]
CTSU Sensor Stabilization Wait Control
Fix the value of these bits to 00010000b
R/W
Only set the CTSUSST register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUSST[7:0] bits (CTSU Sensor Stabilization Wait Control)
The CTSUSST[7:0] bits set the stabilization wait time for the TSCAP pin voltage. Always fix these bits to 00010000b. If
these bits are not set, the TSCAP voltage is unstable at the start of measurement, and the CTSU is unable to produce the
correct touch measurements.
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34.2.5
34. Capacitive Touch Sensing Unit (CTSU)
CTSU Measurement Channel Register 0 (CTSUMCH0)
Address(es): CTSU.CTSUMCH0 4008 1004h
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
1
1
CTSUMCH0[5:0]
1
1
1
1
Bit
Symbol
Bit name
Description
R/W
b5 to b0
CTSUMCH0
[5:0]
CTSU Measurement Channel 0
In self-capacitance single scan mode, these bits set the
channel to be measured.
R/W*1
b5
b0
0 0 0 0 0 0: TS0
0 0 0 0 0 1: TS1
0 0 0 0 1 0: TS2
0 0 0 0 1 1: TS3
0 0 0 1 0 0: TS4
0 0 0 1 0 1: TS5
0 0 0 1 1 0: TS6
0 0 0 1 1 1: TS7
0 0 1 0 0 0: TS8
0 0 1 0 0 1: TS9
0 0 1 0 1 0: TS10
0 0 1 0 1 1: TS11
0 0 1 1 0 0: TS12
0 0 1 1 0 1: TS13
0 0 1 1 1 0: TS14
0 0 1 1 1 1: TS15
0 1 0 0 0 0: TS16
0 1 0 0 0 1: TS17
0 1 0 0 1 0: TS18
0 1 0 0 1 1: TS19
0 1 0 1 0 0: TS20
0 1 0 1 0 1: TS21
0 1 0 1 1 0: TS22
0 1 0 1 1 1: TS23
0 1 1 0 0 0: TS24
0 1 1 0 0 1: TS25
0 1 1 0 1 0: TS26
0 1 1 0 1 1: TS27
0 1 1 1 0 0: TS28
0 1 1 1 1 0: TS30
0 1 1 1 1 1: TS31.
Other than when specified, starting measurement by
setting CTSUCR0.CTSUSTRT to 1 is prohibited after
these bits are set.
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Bit
Symbol
34. Capacitive Touch Sensing Unit (CTSU)
Bit name
Description
R/W
In other measurement modes, these bits indicate the
channel that is currently being measured.
b5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
b7, b6
—
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
b0
0: TS0
1: TS1
0: TS2
1: TS3
0: TS4
1: TS5
0: TS6
1: TS7
0: TS8
1: TS9
0: TS10
1: TS11
0: TS12
1: TS13
0: TS14
1: TS15
0: TS16
1: TS17
0: TS18
1: TS19
0: TS20
1: TS21
0: TS22
1: TS23
0: TS24
1: TS25
0: TS26
1: TS27
0: TS28
0: TS30
1: TS31
1: Measurement is being stopped.
These bits are read as 0. The write value should be 0.
R/W
Note 1. Writing to these bits is enabled only in self-capacitance single scan mode, when CTSUCR1.CTSUMD[1:0] bits =
00b.
Only set the CTSUMCH0 register when CTSUCR0.CTSUSTRT bit is 0.
CTSUMCH0[5:0] bits (CTSU Measurement Channel 0)
In self-capacitance single scan mode, the CTSUMCH0[5:0] bits set the channel to be measured. In this mode, only
specify enabled channels (000000b to 011100b, 011110b to 011111b). In all other modes, these bits indicate the receive
channel that is being measured, and writing to these bits has no effect.
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34.2.6
34. Capacitive Touch Sensing Unit (CTSU)
CTSU Measurement Channel Register 1 (CTSUMCH1)
Address(es): CTSU.CTSUMCH1 4008 1005h
Value after reset:
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
1
1
CTSUMCH1[5:0]
1
1
1
1
Bit
Symbol
Bit name
Description
b5 to b0
CTSUMCH1[5:0]
CTSU Measurement Channel 1
b5
b7, b6
—
Reserved
These bits are read as 0. The write value should
be 0.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
R/W
b0
0: TS0
1: TS1
0: TS2
1: TS3
0: TS4
1: TS5
0: TS6
1: TS7
0: TS8
1: TS9
0: TS10
1: TS11
0: TS12
1: TS13
0: TS14
1: TS15
0: TS16
1: TS17
0: TS18
1: TS19
0: TS20
1: TS21
0: TS22
1: TS23
0: TS24
1: TS25
0: TS26
1: TS27
0: TS28
0: TS30
1: TS31
1: Measurement is being stopped.
R
R/W
CTSUMCH1[5:0] bits (CTSU Measurement Channel 1)
In full scan mode, the CTSUMCH1[5:0] bits indicate the transmit channel that is being measured. They are always
111111b when measurement is stopped, or in self-capacitance single scan and multi-scan modes.
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34.2.7
34. Capacitive Touch Sensing Unit (CTSU)
CTSU Channel Enable Control Register 0 (CTSUCHAC0)
Address(es): CTSU.CTSUCHAC0 4008 1006h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUCHAC0[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUCHAC0[7:0]
CTSU Channel Enable Control 0
These bits select whether the associated TS pin is
measured:
0: Do not measure
1: Measure.
These bits specify the TS0 to TS7 pins.
R/W
Only set the CTSUCHAC0 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUCHAC0[7:0] bits (CTSU Channel Enable Control 0)
The CTSUCHAC0[7:0] bits select the receive and transmit pins whose electrostatic capacitance is to be measured.
CTSUCHAC0[0] is associated with TS0 and CTSUCHAC0[7] with TS7.
34.2.8
CTSU Channel Enable Control Register 1 (CTSUCHAC1)
Address(es): CTSU.CTSUCHAC1 4008 1007h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUCHAC1[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUCHAC1[7:0]
CTSU Channel Enable Control 1
These bits select whether the associated TS pin is
measured:
0: Do not measure
1: Measure.
These bits specify the TS8 to TS15 pins.
R/W
Only set the CTSUCHAC1 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUCHAC1[7:0] bits (CTSU Channel Enable Control 1)
The CTSUCHAC1[7:0] bits select the receive and transmit pins whose electrostatic capacitance is to be measured.
CTSUCHAC1[0] is associated with TS8 and CTSUCHAC1[7] with TS15.
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34.2.9
34. Capacitive Touch Sensing Unit (CTSU)
CTSU Channel Enable Control Register 2 (CTSUCHAC2)
Address(es): CTSU.CTSUCHAC2 4008 1008h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUCHAC2[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUCHAC2[7:0]
CTSU Channel Enable Control 2
These bits select whether the associated TS pin is to be
measured:
0: Do not measure
1: Measure.
These bits specify the TS16 to TS23 pins.
R/W
Only set the CTSUCHAC2 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUCHAC2[7:0] bits (CTSU Channel Enable Control 2)
The CTSUCHAC2[7:0] bits select the receive and transmit pins whose electrostatic capacitance is to be measured.
CTSUCHAC2[0] is associated with TS16 and CTSUCHAC2[7] with TS23.
34.2.10
CTSU Channel Enable Control Register 3 (CTSUCHAC3)
Address(es): CTSU.CTSUCHAC3 4008 1009h
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUCHAC3[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUCHAC3[7:0]
CTSU Channel Enable Control 3
These bits select whether the associated TS pin is
measured.
0: Do not measure
1: Measure.
These bits specify the TS24 to TS28, TS30, TS31 pins.
R/W
Note 1. The MCU does not support the TS29 pin. Therefore, b5 (CTSUCHAC3[5]) is read as 0. The write value should be
0.
Only set the CTSUCHAC3 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUCHAC3[7:0] bits (CTSU Channel Enable Control 3)
The CTSUCHAC3[7:0] bits select the receive and transmit pins whose electrostatic capacitance is to be measured.
CTSUCHAC3[0] is associated with TS24 and CTSUCHAC3[7] with TS31.
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34.2.11
34. Capacitive Touch Sensing Unit (CTSU)
CTSU Channel Transmit/Receive Control Register 0 (CTSUCHTRC0)
Address(es): CTSU.CTSUCHTRC0 4008 100Bh
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUCHTRC0[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUCHTR
C0[7:0]
CTSU Channel Transmit/Receive
Control 0
0: Reception
1: Transmission.
These bits specify the TS0 to TS7 pins.
R/W
Only set the CTSUCHTRC0 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUCHTRC0[7:0] bits (CTSU Channel Transmit/Receive Control 0)
In full scan mode, the CTSUCHTRC0[7:0] bits assign the associated TS pins to reception or transmission. The setting is
ignored in self-capacitance single scan and multi-scan modes. CTSUCHTRC0[0] is associated with TS0 and
CTSUCHTRC0[7] with TS7.
34.2.12
CTSU Channel Transmit/Receive Control Register 1 (CTSUCHTRC1)
Address(es): CTSU.CTSUCHTRC1 4008 100Ch
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUCHTRC1[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUCHTR
C1[7:0]
CTSU Channel Transmit/Receive
Control 1
0: Reception
1: Transmission.
These bits specify the TS8 to TS15 pins.
R/W
Only set the CTSUCHTRC1 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUCHTRC1[7:0] bits (CTSU Channel Transmit/Receive Control 1)
In full scan mode, the CTSUCHTRC1[7:0] bits assign the associated TS pins to reception or transmission. The setting is
ignored in self-capacitance single scan and multi-scan modes. CTSUCHTRC1[0] is associated with TS7 and
CTSUCHTRC1[7] with TS15.
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34.2.13
34. Capacitive Touch Sensing Unit (CTSU)
CTSU Channel Transmit/Receive Control Register 2 (CTSUCHTRC2)
Address(es): CTSU.CTSUCHTRC2 4008 100Dh
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUCHTRC2[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUCHTR
C2[7:0]
CTSU Channel Transmit/Receive
Control 2
0: Reception
1: Transmission.
These bits specify the TS16 to TS23 pins.
R/W
Only set the CTSUCHTRC2 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUCHTRC2[7:0] bits (CTSU Channel Transmit/Receive Control 2)
In full scan mode, the CTSUCHTRC2[7:0] bits assign the associated TS pins to reception or transmission. The setting is
ignored in self-capacitance single scan and multi-scan modes. CTSUCHTRC2[0] is associated with TS16 and
CTSUCHTRC2[7] with TS23.
34.2.14
CTSU Channel Transmit/Receive Control Register 3 (CTSUCHTRC3)
Address(es): CTSU.CTSUCHTRC3 4008 100Eh
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
CTSUCHTRC3[7:0]
Value after reset:
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
CTSUCHTRC3[7:0]
CTSU Channel Transmit/Receive
Control 3
0: Reception
R/W
1: Transmission.
These bits specify the TS24 to TS28, TS30, TS31 pins.
Note 1. The MCU does not support the TS29 pin. Therefore, b5 (CTSUCHTRC3[5]) is read as 0. The write value should
be 0.
Only set the CTSUCHTRC3 register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUCHTRC3[7:0] bits (CTSU Channel Transmit/Receive Control 3)
In full scan mode, the CTSUCHTRC3[7:0] bits assign the associated TS pins to reception or transmission. The setting is
ignored in self-capacitance single scan and multi-scan modes. CTSUCHTRC3[0] is associated with TS24 and
CTSUCHTRC3[7] with TS31.
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34.2.15
34. Capacitive Touch Sensing Unit (CTSU)
CTSU High-Pass Noise Reduction Control Register (CTSUDCLKC)
Address(es): CTSU.CTSUDCLKC 4008 1010h
Value after reset:
Bit
b7
b6
—
—
0
0
Symbol
b5
b4
CTSUSSCNT[1:
0]
0
0
b3
b2
—
—
0
0
b1
b0
CTSUSSMOD[1
:0]
0
0
Bit name
Description
R/W
b1, b0
CTSUSSMOD[1:0]
CTSU Diffusion Clock Mode Select
Set these bits to 00b
R/W
b3, b2
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
b5, b4
CTSUSSCNT[1:0]
CTSU Diffusion Clock Mode Control
Set these bits to 11b
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
Only set the CTSUDCLKC register when the CTSUCR0.CTSUSTRT bit is 0.
CTSUSSMOD[1:0] bits (CTSU Diffusion Clock Mode Select)
The CTSUSSMOD[1:0] bits set the mode of the spectrum diffusion clock for high-pass noise reduction. When using the
high-pass noise reduction function, always fix these bits to 00b. If these bits are not set, the CTSU is unable to effectively
reduce high-pass noise.
CTSUSSCNT[1:0] bits (CTSU Diffusion Clock Mode Control)
The CTSUSSCNT[1:0] bits adjust the amount of spectrum diffusion applied to reduce high-pass noise. When using the
high-pass noise reduction function, always fix these bits to 11b. If these bits are not set, touch measurement might be
performed incorrectly.
34.2.16
CTSU Status Register (CTSUST)
Address(es): CTSU.CTSUST 4008 1011h
b7
b6
b5
b4
CTSUP CTSUR CTSUS CTSUD
S
OVF
OVF
TSR
0
Value after reset:
0
0
0
b3
b2
—
0
b1
b0
CTSUSTC[2:0]
0
0
0
Bit
Symbol
Bit name
Description
R/W
b2 to b0
CTSUSTC[2:0]
CTSU Measurement Status Counter
These counters indicate the current measurement
status:
R
b2
0
0
0
0
1
1
0
0
1
1
0
0
b0
0:
1:
0:
1:
0:
1:
Status 0
Status 1
Status 2
Status 3
Status 4
Status 5.
b3
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b4
CTSUDTSR
CTSU Data Transfer Status Flag
This flag indicates whether the measurement result
stored in the sensor counter and the reference counter
was read.
0: Read
1: Not read.
R
b5
CTSUSOVF
CTSU Sensor Counter Overflow Flag This flag indicates an overflow on the sensor counter:
0: No overflow occurred
1: Overflow occurred.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
R/W
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34. Capacitive Touch Sensing Unit (CTSU)
Bit
Symbol
Bit name
Description
R/W
b6
CTSUROVF
CTSU Reference Counter Overflow
Flag
This flag indicates an overflow on the reference
counter:
0: No overflow occurred
1: Overflow occurred.
R/W
b7
CTSUPS
CTSU Mutual Capacitance Status
Flag
This flag indicates the measurement status in mutual
capacitance full scan mode.
0: First measurement
1: Second measurement.
R
When using the CTSUCR0.CTSUINIT bit to clear an overflow flag, make sure that the CTSUCR0.CTSUSTRT bit is 0.
CTSUSTC[2:0] flags (CTSU Measurement Status Counter)
The CTSUSTC[2:0] flags are a counter indicating the current measurement status. For details on each status, see section
34.3.2.2, Status counter.
CTSUDTSR flag (CTSU Data Transfer Status Flag)
The CTSUDTSR flag indicates whether the measurement result stored in the sensor counter and the reference counter
was read. The flag is set to 1 when measurement completes and 0 when the reference counter is read by software or the
DTC. The flag can also be cleared using the CTSUCR0.CTSUINIT bit.
CTSUSOVF flag (CTSU Sensor Counter Overflow Flag)
The CTSUSOVF flag is set to 1 when the sensor counter, CTSUSC, overflows. On overflow, the counter value reads as
FFFFh. Measurement processing continues for the specified period.
No interrupt occurs on an overflow. To determine the channel on which the overflow occurred, read the measurement
result of each channel after measurement completes, as signaled by a measurement end interrupt.
This flag is cleared when 0 is written after 1 is read by software. It can also be cleared using the CTSUCR0.CTSUINIT
bit.
CTSUROVF flag (CTSU Reference Counter Overflow Flag)
The CTSUROVF flag is set to 1 when the reference counter, CTSURC, overflows. On overflow, the counter value reads
as FFFFh. Measurement processing continues for the specified period.
No interrupt occurs on an overflow. To determine the channel on which the overflow occurred, read the measurement
result of each channel after measurement completes, as signaled by a measurement end interrupt.
This flag is cleared when 0 is written after 1 is read by software. It can also be cleared using the CTSUCR0.CTSUINIT
bit.
CTSUPS flag (CTSU Mutual Capacitance Status Flag)
In mutual capacitance full scan mode, when CTSUCR1.CTSUMD[1:0] = 11b, the CTSUPS flag indicates whether the
measurement is the first or second of two measurements for each channel.
When measurement is stopped or in other measurement modes, the flag is always 0.
34.2.17
CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register
(CTSUSSC)
Address(es): CTSU.CTSUSSC 4008 1012h
Value after reset:
b15
b14
b13
b12
—
—
—
—
0
0
0
0
b11
b10
b9
b8
CTSUSSDIV[3:0]
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b7 to b0
—
Reserved
These bits are read as 0. The write value should be 0.
R/W
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34. Capacitive Touch Sensing Unit (CTSU)
Bit
Symbol
Bit name
Description
R/W
b11 to b8
CTSUSSDIV[3:0]
CTSU Spectrum Diffusion
Frequency Division Setting
These bits specify the spectrum diffusion frequency
division setting based on the base clock frequency
division setting
R/W
Reserved
These bits are read as 0. The write value should be 0.
R/W
b15 to b12 —
CTSUSSDIV[3:0] bits (CTSU Spectrum Diffusion Frequency Division Setting)
The CTSUSSDIV[3:0] bits specify the spectrum diffusion frequency division setting, derived from the base clock
frequency division setting. To calculate the correct setting for CTSUSSDIV[3:0], see the relationship between base clock
frequencies and the settings in Table 34.5.
Table 34.5
Relationship between base clock frequencies and CTSUSSDIV[3:0] bit settings
Base clock frequency fb (MHz)
CTSUSSDIV[3:0] bit setting
4.00 ≤ fb
0000b
2.00 ≤ fb < 4.00
0001b
1.33 ≤ fb < 2.00
0010b
1.00 ≤ fb < 1.33
0011b
0.80 ≤ fb < 1.00
0100b
0.67 ≤ fb < 0.80
0101b
0.57 ≤ fb < 0.67
0110b
0.50 ≤ fb < 0.57
0111b
0.44 ≤ fb < 0.50
1000b
0.40 ≤ fb < 0.44
1001b
0.36 ≤ fb < 0.40
1010b
0.33 ≤ fb < 0.36
1011b
0.31 ≤ fb < 0.33
1100b
0.29 ≤ fb < 0.31
1101b
0.27 ≤ fb < 0.29
1110b
fb < 0.27
1111b
34.2.18
CTSU Sensor Offset Register 0 (CTSUSO0)
Address(es): CTSU.CTSUSO0 4008 1014h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
CTSUSNUM[5:0]
Value after reset:
0
0
0
0
b4
b3
b2
b1
b0
0
0
0
0
CTSUSO[9:0]
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b9 to b0
CTSUSO[9:0]
CTSU Sensor Offset Adjustment
These bits adjust the electronic capacitance when the
electrode is not being touched:
R/W
b9
b0
0 0 0 0 0 0 0 0 0 0: Current offset is 0
0 0 0 0 0 0 0 0 0 1: Current offset is 1
0 0 0 0 0 0 0 0 1 0: Current offset is 2
:
:
1 1 1 1 1 1 1 1 1 0: Current offset is 1022
1 1 1 1 1 1 1 1 1 1: Current offset is maximum.
b15 to b10 CTSUSNUM[5:0]
CTSU Measurement Count Setting
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
These bits set the number of measurements
R/W
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34. Capacitive Touch Sensing Unit (CTSU)
CTSUSO[9:0] bits (CTSU Sensor Offset Adjustment)
The CTSUSO[9:0] bits offset the sensor ICO input current generated from electrostatic capacitance during touch
measurement when the electrode is not being touched. This prevents the CTSU sensor counter from overflowing.
Set the TS pin that is to be measured next after a CTSU_CTSUWR interrupt occurs.
CTSUSNUM[5:0] bits (CTSU Measurement Count Setting)
The CTSUSNUM[5:0] bits specify how many times the measurement pulse count specified in the
CTSUSDPRS.CTSUPRRATIO[3:0] and CTSUSDPRS.CTSUPRMODE[1:0] bits is repeated during the measurement
time. The measurement pulse count is repeated (CTSUSNUM[5:0] bits + 1) times.
Set the TS pin that is to be measured next after a CTSU_CTSUWR interrupt occurs.
34.2.19
CTSU Sensor Offset Register 1 (CTSUSO1)
Address(es): CTSU.CTSUSO1 4008 1016h
b15
—
Value after reset:
0
b14
b13
b12
CTSUICOG[1:0]
0
0
b11
b10
b9
b8
b7
b6
b5
CTSUSDPA[4:0]
0
0
0
0
b4
b3
b2
b1
b0
0
0
0
CTSURICOA[7:0]
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
b7 to b0
CTSURICOA[7:0]
CTSU Reference ICO Current
Adjustment
These bits adjust the input current of the reference ICO: R/W
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
b7
R/W
b0
0 0 0 0 0 0 0 0: Current offset is 0
0 0 0 0 0 0 0 1: Current offset is 1
0 0 0 0 0 0 1 0: Current offset is 2
:
:
1 1 1 1 1 1 1 0: Current offset is 254
1 1 1 1 1 1 1 1: Current offset is maximum.
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34. Capacitive Touch Sensing Unit (CTSU)
Bit
Symbol
Bit name
Description
R/W
b12 to b8
CTSUSDPA[4:0]
CTSU Base Clock Setting
These bits are used to generate the base clock:
R/W
b12
b8
0 0 0 0 0: Operating clock divided by 2*1
0 0 0 0 1: Operating clock divided by 4
0 0 0 1 0: Operating clock divided by 6
0 0 0 1 1: Operating clock divided by 8
0 0 1 0 0: Operating clock divided by 10
0 0 1 0 1: Operating clock divided by 12
0 0 1 1 0: Operating clock divided by 14
0 0 1 1 1: Operating clock divided by 16
0 1 0 0 0: Operating clock divided by 18
0 1 0 0 1: Operating clock divided by 20
0 1 0 1 0: Operating clock divided by 22
0 1 0 1 1: Operating clock divided by 24
0 1 1 0 0: Operating clock divided by 26
0 1 1 0 1: Operating clock divided by 28
0 1 1 1 0: Operating clock divided by 30
0 1 1 1 1: Operating clock divided by 32
1 0 0 0 0: Operating clock divided by 34
1 0 0 0 1: Operating clock divided by 36
1 0 0 1 0: Operating clock divided by 38
1 0 0 1 1: Operating clock divided by 40
1 0 1 0 0: Operating clock divided by 42
1 0 1 0 1: Operating clock divided by 44
1 0 1 1 0: Operating clock divided by 46
1 0 1 1 1: Operating clock divided by 48
1 1 0 0 0: Operating clock divided by 50
1 1 0 0 1: Operating clock divided by 52
1 1 0 1 0: Operating clock divided by 54
1 1 0 1 1: Operating clock divided by 56
1 1 1 0 0: Operating clock divided by 58
1 1 1 0 1: Operating clock divided by 60
1 1 1 1 0: Operating clock divided by 62
1 1 1 1 1: Operating clock divided by 64.
b14, b13
CTSUICOG[1:0]
CTSU ICO Gain Adjustment
These bits adjust the output frequency gain of the
sensor ICO and the reference ICO:
b14 b13
0
0
1
1
b15
—
Reserved
0:
1:
0:
1:
R/W
100% gain
66% gain
50% gain
40% gain.
This bit is read as 0. The write value should be 0.
R/W
Note 1. Do not set the CTSUSDPA[4:0] bits to 00000b while the high-pass noise reduction function is turned off
(CTSUSDPRS.CTSUSOFF = 1) in mutual capacitance full scan mode (CTSUCR1.CTSUMD[1:0] = 11b).
After a CTSU_CTSUWR interrupt occurs, write first to the CTSUSSC register, next to the CTSUSO0 register, and then
to the CTSUSO1 register. The write to the CTSUSO1 register causes a transition to Status 3. (See Table 34.6 and Table
34.7). Set all of the bits in a single operation when writing to the CTSUSO1 register.
CTSURICOA[7:0] bits (CTSU Reference ICO Current Adjustment)
The CTSURICOA[7:0] bits adjust the oscillation frequency using the input current of the reference ICO.
CTSUSDPA[4:0] bits (CTSU Base Clock Setting)
The CTSUSDPA[4:0] bits select the base clock used as the source for the sensor drive pulse by dividing the operating
clock. For details on the setting procedure, see section 34.3.2.1, Initial settings flow.
CTSUICOG[1:0] bits (CTSU ICO Gain Adjustment)
The CTSUICOG[1:0] bits adjust the output frequency gain of the sensor ICO and the reference ICO. In general, set these
bits to 00b for the maximum gain. If changes in the capacitance between when the electrode is touched and when it is not
touched greatly exceed the dynamic range of the sensor ICO, adjust the gain appropriately with this setting.
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34.2.20
34. Capacitive Touch Sensing Unit (CTSU)
CTSU Sensor Counter (CTSUSC)
Address(es): CTSU.CTSUSC 4008 1018h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
CTSUSC[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
CTSUSC[15:0]
CTSU Sensor Counter
These bits indicate the measurement result of the sensor ICO.
They read FFFFh when an overflow occurs.
R
After a CTSU_CTSURD interrupt occurs, read first from the CTSUSC counter and then from the CTSURC counter.
CTSUSC[15:0] bits (CTSU Sensor Counter)
The CTSUSC[15:0] bits are configured as an increment counter for the sensor ICO.
Read these bits after a CTSU_CTSURD interrupt occurs. After the CTSURC counter is read, these bits are cleared
immediately before the CTSU measurement status counter value changes to Status 4 (the CTSUST.CTSUSTC[2:0] flags
change to 100b) in the next measurement. They can also be cleared using the CTSUCR0.CTSUINIT bit.
34.2.21
CTSU Reference Counter (CTSURC)
Address(es): CTSU.CTSURC 4008 101Ah
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
CTSURC[15:0]
Value after reset:
0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b15 to b0
CTSURC[15:0]
CTSU Reference Counter
These bits indicate the measurement result of the reference
ICO. They read FFFFh when an overflow occurs.
R
After a CTSU_CTSURD interrupt occurs, read first from the CTSUSC counter and then from the CTSURC counter.
Status 3 continues until the CTSURC counter is read, even if the stabilization time specified for Status 3 elapses.
CTSURC[15:0] bits (CTSU Reference Counter)
The CTSURC[15:0] bits are configured as an increment counter for the reference ICO clock. The reference ICO
optimizes the touch measurement performed by the sensor ICO. There is some deviation depending on the internal
sensor ICO and the reference ICO in the CTSU, but both ICOs have almost the same characteristics, including the
dynamic range and the current-to-frequency characteristics. The range of current that can be set in the reference ICO
current adjustment bits is about the same as the dynamic range of both ICOs, and the current input to the sensor ICO
must be within this dynamic range. To ensure this, use the reference ICO to check the differences between the ICOs and
measure the current-to-oscillation frequency characteristics. The reference ICO oscillation frequency can be obtained
from the reference ICO counter, and the ICO oscillation frequency for the input current (counter value/measurement
time) can be measured by setting the value in the reference ICO current adjustment bits and measuring the reference ICO
counter. The reference ICO counter value measured using the maximum value in the reference ICO current adjustment
bits is the maximum value of the ICO dynamic range. The current to the sensor ICO needs to be offset in the offset
adjustment bits so that the sensor ICO counter value does not exceed this value.
Read the CTSURC[15:0] bits after a CTSU_CTSURD interrupt occurs. After these bits are read, they are cleared
immediately before the CTSU measurement status counter value changes to Status 4 (the CTSUST.CTSUSTC[2:0] flags
change to 100b) in the next measurement. They can also be cleared using the CTSUCR0.CTSUINIT bit.
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34.2.22
34. Capacitive Touch Sensing Unit (CTSU)
CTSU Error Status Register (CTSUERRS)
Address(es): CTSU.CTSUERRS 4008 101Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
CTSUI
COMP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b14 to b0
—
Reserved
These bits are read as 0.
R
b15
CTSUICOMP
TSCAP Voltage Error Monitor
This bit monitors the error status of the TSCAP voltage:
0: Normal TSCAP voltage
1: Abnormal TSCAP voltage.
R
CTSUICOMP bit (TSCAP Voltage Error Monitor)
If the offset current amount set in the CTSUSO1 register exceeds the sensor ICO input current during touch
measurement, the TSCAP voltage becomes abnormal and touch measurement cannot be correctly performed. The
CTSUICOMP bit monitors the TSCAP voltage and is set to 1 if the voltage becomes abnormal.
If the TSCAP voltage becomes abnormal, the sensor ICO counter value becomes undefined, but touch measurement
completes normally, so it is difficult to detect an abnormality by reading the sensor ICO counter value. If the CTSU
reference ICO current adjustment bits (CTSURICOA[7:0]) in the CTSUSO1 register are set to any value other than 0,
always check this bit when touch measurement completes.
This bit is cleared by writing 0 to the CTSUCR1.CTSUPON bit and turning off the power supply.
34.3
Operation
34.3.1
Principles of Measurement Operation
Figure 34.4 shows the measurement circuit.
Power
supply
LPF
Reference
electric
potential
VCC
+
Control
current
TSCAP
Sensor
(electrode)
ICO
Counter
SW1
Sensor drive pulse
TSn*1
SW2
Note 1.
Figure 34.4
Switched
capacitor filter
R = 1/(fC)
n = 00 to 28, 30, 31
Measurement circuit
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34. Capacitive Touch Sensing Unit (CTSU)
Figure 34.5 to Figure 34.7 explain the electrostatic capacitance measurement operation principles of the CTSU current
frequency conversion. The operation is as follows:
1.
The electrostatic capacitance of the electrode is charged by turning SW1 on and SW2 off. See Figure 34.5.
2.
The charged capacitance is discharged by turning SW1 off and SW2 on. See Figure 34.6.
3. Current flows to the switched capacitor filter by repeatedly charging and discharging the electrodes as in steps 1.
and 2. At this point, if a finger is in close proximity, the capacitance and the flowing current change. A clock is
generated by supplying a control current that is proportional to the amount of the current flowing through the
switched capacitor filter, from the circuit that generates the TSCAP power supply to the ICO. The counter measures
the clock frequency that changes depending on whether a finger is in close proximity. Software uses the value read
from the counter to determine contact with a finger. See Figure 34.7.
Reference
electric
potential
Power
supply
LPF
VCC
+
Control
current
TSCAP
Sensor
(electrode)
Sensor drive pulse
Switched
capacitor filter
i = fCV
SW2
Figure 34.5
n = 00 to 28, 30, 31
Charging operation
Power
supply
LPF
Reference
electric
potential
VCC
+
Control
current
TSCAP
Sensor
(electrode)
Turn SW2 on
Note 1.
ICO
Counter
Turn SW1 off
TSn*1
Figure 34.6
Counter
SW1
TSn*1
Note 1.
ICO
Sensor drive pulse
Switched
capacitor filter
i = fCV
n = 00 to 28, 30, 31
Discharging operation
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34. Capacitive Touch Sensing Unit (CTSU)
Number of counts
Touching
Touch is determined
based on the difference
Not touching
0
Sensor drive pulse generated
Time
Figure 34.7
34.3.2
Change in measured value when finger is touching and not touching
Measurement Modes
The CTSU supports self-capacitance and mutual capacitance methods. Figure 34.8 shows these methods.
Receive pin
Touch key
TS0
Key 1
TS1
TS2
Key 2
Key 3
Key 4
Key 5
TS4
TS1 TS2 TS3 TS4 TS5 TS6
Transmit pin
TS3
TS5
Touch key arrangement for
self-capacitance method
Touch sensor arrangement for
mutual capacitance method
Figure 34.8
Overview of self-capacitance method and mutual capacitance method
In the self-capacitance method, a single touch pin is allocated to a single touch key to measure individual electrostatic
capacitance when a finger is in close proximity. In this method, capacitance can be measured in both single scan and
multi-scan modes.
In the mutual capacitance method, the capacitance between two opposing electrodes (transmit and receive pins) is
measured.
34.3.2.1
Initial settings flow
Figure 34.9 shows the flow for the initial CTSU settings.
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34. Capacitive Touch Sensing Unit (CTSU)
Discharge external LPF capacitor
connected to TSCAP pin
Discharge the external LPF capacitor connected to the MCU by using
the TSCAP pin as the I/O port function and driving it low for the specified time.
Set I/O port
Set the associated pin to TSn (n = 00 to 28, 30, 31) by setting the pin function
select register of the I/O port function (PmnPFS.PSEL[4:0] = 01100b), and set
the pin to the peripheral function by setting the Port Mode Control bit for the I/
O port (PMR) (PmnPFS.PMR = 1).
Enable CTSU input clock
Set CTSU power supply
Set CTSU base clock
Enable the module clock by setting the MSTPC3 bit in Module Stop Control
Register C (MSTPCRC) to 0.
Set the CTSU power supply operating mode and capacity adjustment.
When operating the CTSU while VCC is 2.4 V or lower, set the
CTSUCR1.CTSUATUNE0 bit.
Set the CTSUCR1.CTSUATUNE1 bit according to electrostatic capacitance
generated in the electrode connected to the TS pin.
Use the CTSUCR1.CTSUCLK[1:0] and CTSUSO1.CTSUSDPA[4:0] bits to set
the base clock.
Supply power to the CTSU and connect the LPF capacitor to the TSCAP pin.
Write 1 to the CTSUCR1.CTSUPON bit and 1 to the CTSUCR1.CTSUCSW bit
at the same time.
Power on CTSU
Wait for stabilization
After data is written, wait until charging of the external LPF capacitor
connected to the TSCAP pin stabilizes.
Measurement operation starts
Figure 34.9
Initial CTSU settings flow
Figure 34.10 shows the flow for stopping CTSU operation and invoking the standby state.
CTSU operation completed
Power off CTSU
Enable module standby
Figure 34.10
Power off the CTSU and disconnect the TSCAP pin
from the LPF capacitor.
Write 0 to the CTSUCR1.CTSUPON bit and
0 to the CTSUCR1.CTSUCSW bit.
Disable the module clock by setting the MSTPC3 bit in
Module Stop Control Register C (MSTPCRC) to 1.
CTSU stopping flow
To restart operation, follow the initial setting flow shown in Figure 34.9.
34.3.2.2
Status counter
The measurement status counter of the CTSU Status Register (CTSUST) indicates the current measurement status. The
measurement status applies to all three modes. Figure 34.11 shows status operation transitions.
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34. Capacitive Touch Sensing Unit (CTSU)
Conditions for transition to Status 1:
If CTSUCR0.CTSUCAP bit = 0, CTSUCR0.CTSUSTRT bit = 1
If CTSUCR0.CTSUCAP bit = 1, CTSUCR0.CTSUSTRT bit = 1 and the
rising edge of the external trigger is detected.
Status 0
Stopped/wait for external trigger
Condition for transition to Status 0:
There is no channel to be measured next.
(A CTSU_CTSUFN interrupt occurs and measurement is stopped.)
Condition for transition to Status 2:
Update of the measurement channel completes.
Condition for transition to Status 3:
CTSUST.CTSUPS = 1 (second measurement) in mutual capacitance full
scan mode.
Status1
Measurement channel update/
determination of measurement stop
Condition for transition to Status 3:
Write access to the CTSUSO1 register*1.
Status 2
Wait for sensor drive pulse setting
Condition for transition to Status 4:
CTSUST.CTSUDTSR flag = 0 when the sensor stabilization wait elapses
after supply of the sensor drive pulse starts.
Status 3
Sensor drive pulse output start/
sensor stabilization wait period*2
Status 4
Measurement start/
measurement period
Condition for transition to Status 5:
The measurement time elapses after measurement started.
For details on the measurement time, see section 34.3.3.1, Sensor
stabilization wait time and measurement time.
Condition for transition to Status 1:
Two clocks of the operating clock elapse.
Status 5
Measurement completed
Note 1.
Note 2.
Figure 34.11
When using the DTC or ICU to set the registers during CTSU_CTSUWR
interrupt handling, write to the CTSUSO1 register last.
If the CTSUST.CTSUDTSR flag = 1, wait until the previous measurement
result is transferred.
Status operation transitions
The status counter transitions to Status 0 when all of the specified measurement channels are measured.
The CTSUCR0.CTSUSTRT bit is set to 0 by hardware when a software trigger is used. When an external trigger is used,
the value of 1 is retained, and the CTSU waits for the next trigger.
When operation is forced to stop during measurement or the trigger wait state, by a simultaneous 0 write to the
CTSUCR0.CTSUSTRT bit and a 1 write to the CTSUCR0.CTSUINIT bit, the status transitions to Status 0 and
measurement stops.
In the following situations, there is no channel to be measured:
No measurement target channel is specified in the CTSUCHAC0 to CTSUCHAC3 registers
In self-capacitance single scan mode, the channel specified in the CTSUMCH0 register is not a measurement target
in the CTSUCHAC0 to CTSUCHAC3 registers
In full scan modes, there is no transmit or receive channel to be measured based on the combined settings of the
CTSUCHAC0 to CTSUCHAC3 and CTSUCHTRC0 to CTSUCHTRC3 registers.
If there is no channel to be measured based on these settings, a CTSU_CTSUFN interrupt occurs immediately after a
transition to Status 1, and the counter transitions to Status 0.
34.3.2.3
Self-capacitance single scan mode operation
In self-capacitance single scan mode, electrostatic capacitance is measured on one channel. Figure 34.12 shows the
software flow and an operation example, and Figure 34.13 shows the timing.
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34. Capacitive Touch Sensing Unit (CTSU)
Self-capacitance single scan mode
Initial settings
Set interrupt operation
(DTC or ICU)
Set CTSU registers
Power supply stabilization
time has elapsed after
CTSUPON = 1
Set CTSU control
(measurement start)
using CTSUCR0 register
• CTSU_CTSUWR interrupt operation setting:
Transfer from the RAM to the CTSUSSC, CTSUSO0, and CTSUSO1 registers
• CTSU_CTSURD interrupt operation setting:
Transfer the CTSUSC and CTSURC counters to the SRAM
CTSUCR1 register:
• CTSUCR1.CTSUCLK[1:0] bits: Operating clock can be selected
• CTSUCR1.CTSUMD[1:0] bits: Set these bits to 00b
CTSUSDPRS register:
• CTSUSDPRS.CTSUSOFF bit: High-pass noise prevention can be turned off
• CTSUSDPRS.CTSUPRMODE[1:0] bits: Set the number of base pulses for synchronous noise prevention
• CTSUSDPRS.CTSUPRRATIO[3:0] bits: Set the measurement time for synchronous noise prevention
CTSUSST register: Set the sensor stabilization time
CTSUCHAC0 to CTSUCHAC3 registers: Set the enabled channel
CTSUMCH0 register: Set the measurement channel
• CTSUCR0.CTSUSTRT bit: Set this bit to 1
• CTSUCR0.CTSUCAP bit: Starting of CTSU operation by external trigger can be selected
• CTSUCR0.CTSUSNZ bit: Power-saving function during wait state can be enabled or disabled
CTSU operation starts
CTSU_CTSUWR
interrupt generated?
Set the measurement channel
CTSU_CTSURD
generated?
Read the measurement result
CTSU_CTSUFN
generated?
Touch determination
processing
Figure 34.12
No
CTSUSSC register
CTSUSO0 register
CTSUSO1 register
Transferred by the DTC
when the DTC is selected
No
CTSUSC counter
CTSURC counter
No
Transferred by the DTC
when the DTC is selected
Wait for the measurement end interrupt
When a software trigger is used, the CTSUCR0.CTSUSTRT bit sets to 0 when CTSU operation stops.
Software flow and operation example of self-capacitance single scan mode
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34. Capacitive Touch Sensing Unit (CTSU)
Sensor stabilization wait time
(CTSUSST register)
Measurement time
Operating clock
CTSUCR0.CTSUSTRT bit
CTSUMCH0 register
63
CTSUST.CTSUSTC[2:0]
flags (Status)
5
0
1
2
3
63
4 (During current/count value conversion)
5
1
0
Sensor ICO clock
CTSUSC counter
0
Measurement result
CTSU_CTSUWR interrupt
CTSU_CTSURD interrupt
CTSU_CTSUFN interrupt
Sensor drive pulse
(1)
Figure 34.13
(2)
(3)
(4) (5)
Timing of self-capacitance single scan mode when the measurement start condition is a software
trigger
The following sequence describes the operation shown in Figure 34.13:
1. After initial settings are made, operation is started by writing 1 to the CTSUCR0.CTSUSTRT bit.
2. After the channel to be measured is determined according to the preset conditions, a request to set the channel
(CTSU_CTSUWR) is output.
3. On completion of writing the measurement channel settings (CTSUSSC, CTSUSO0, and CTSUSO1 registers), the
sensor drive pulse is output and the sensor ICO clock and the reference ICO clock operate.
4. After the sensor stabilization wait time and the measurement time have elapsed, and measurement stops, a
measurement result read request (CTSU_CTSURD) is output.
5. A measurement end interrupt (CTSU_CTSUFN) is output and measurement stops (transition to Status 0).
Table 34.6 lists the touch pin states in self-capacitance single scan mode.
Table 34.6
Touch pin states in self-capacitance single scan mode
Touch pin
Status
Measured channel
Non-measured channel
0
Low
Low
1
Low
Low
2
Low
Low
3
Pulse
Low
4
Pulse
Low
5
Low
Low
34.3.2.4
Self-capacitance multiscan mode operation
In self-capacitance multiscan mode, electrostatic capacitance on all channels that are specified as measurement targets in
the CTSUCHAC0 to CTSUCHAC3 registers is measured sequentially in ascending order. Figure 34.14 shows the
software flow and an operation example, and Figure 34.15 shows the timing.
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34. Capacitive Touch Sensing Unit (CTSU)
Initial settings
Set interrupt operation
(DTC or ICU)
Set CTSU registers
Power supply stabilization
time has elapsed after
CTSUPON = 1
Set CTSU control
(measurement start)
using CTSUCR0 register
• CTSU_CTSUWR interrupt operation setting:
Transfer from the RAM to the CTSUSSC, CTSUSO0, and CTSUSO1 registers
• CTSU_CTSURD interrupt operation setting:
Transfer the CTSUSC and CTSURC counters to the RAM
CTSUCR1 register:
• CTSUCR1.CTSUCLK[1:0] bits: Operating clock can be selected
• CTSUCR1.CTSUMD[1:0] bits: Set these bits to 01b
CTSUSDPRS register:
• CTSUSDPRS.CTSUSOFF bit: High-pass noise prevention can be turned off
• CTSUSDPRS.CTSUPRMODE[1:0] bits: Set the number of base pulses for synchronous noise prevention
• CTSUSDPRS.CTSUPRRATIO[3:0] bits: Set the measurement time for synchronous noise prevention
CTSUSST register: Set the sensor stabilization time
CTSUCHAC0 to CTSUCHAC3 registers: Set the enabled channel
CTSUMCH0 register: Set the measurement channel
CTSUCR0.CTSUSTRT bit: Set this bit to 1
CTSUCR0.CTSUCAP bit: Starting of CTSU operation by external trigger can be selected
CTSUCR0.CTSUSNZ bit: Power-saving function during wait state can be enabled or disabled
CTSU operation starts
No
CTSU_CTSUWR
interrupt generated?
Set the measurement channel
CTSUSSC register
CTSUSO0 register
CTSUSO1 register
Transferred by the DTC
when the DTC is selected
Repeat for the number of
the measurement channels
No
CTSU_CTSURD
generated?
Read the measurement result
CTSU_CTSUFN
generated?
Touch determination
processing
Transferred by the DTC
when the DTC is selected
CTSUSC counter
CTSURC counter
No
Wait for the measurement end interrupt
When a software trigger is used, the CTSUCR0.CTSUSTRT bit sets to 0 when CTSU operation stops.
Channel measurement sequence in self -capacitance multiscan mode
Settings:
• Select self-capacitance multi-scan mode (CTSUCR1.CTSUMD[1:0] bits = 01b)
• Set channels 0, 3, 5, and 6 to enabled channels (CTSUCHAC0.CTSUCHAC0[7:0] bits = 01101001b)
Receive Channels
Channel 7
Figure 34.14
Channel 6
Channel 5
(4)
(3)
Channel 4
Channel 3
(2)
Channel 2
Channel 1
Channel 0
(1)
Software flow and operation example of self-capacitance multi-scan mode
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34. Capacitive Touch Sensing Unit (CTSU)
Measurement of channel 2
Sensor stabilization wait time
(CTSUSST register)
Measurement of channel N
Measurement time
Operating clock
CTSUCR0.CTSUSTRT bit
CTSUMCH0 register 63
CTSUST.CTSUSTC[2:0]
flags (Status)
0 1
0
2
1
2
3
4 (During current/count value conversion)
N
5
1
2
4 (During current/count value
conversion)
3
63
5
1
0
Sensor ICO clock
0
CTSUSC counter
Measurement result
0
Measurement result
CTSU_CTSUWR interrupt
CTSU_CTSURD interrupt
CTSU_CTSUFN interrupt
Sensor drive pulse
(1)
Figure 34.15
(2)
(3)
(4)
(5)
(6)
(7)
Timing of self-capacitance multi-scan mode when the measurement start condition is a software
trigger
The following sequence describes the operation shown in Figure 34.15:
1. After initial settings are made, operation is started by writing 1 to the CTSUCR0.CTSUSTRT bit.
2. After the channel to be measured is determined according to the preset conditions, a request to set the channel
(CTSU_CTSUWR) is output.
3. On completion of writing the measurement channel settings (CTSUSSC, CTSUSO0, and CTSUSO1 registers), the
sensor drive pulse is output and the sensor ICO clock and the reference ICO clock operate.
4. After the sensor stabilization wait time and the measurement time have elapsed and measurement stops, a
measurement result read request (CTSU_CTSURD) is output.
5. After the channel to be measured next is determined, a request to set the channel (CTSU_CTSUWR) is output.
6. After the stabilization wait time elapses and when the previous measurement is read, the result is cleared and
measurement starts.
7. On completion of all channel measurements, a measurement end interrupt (CTSU_CTSUFN) is output and
measurement stops (transition to Status 0).
Table 34.7 lists the touch pin states in self-capacitance multi-scan mode.
Table 34.7
Touch pin states in self-capacitance multi-scan mode
Touch pin
Status
Measured channel
Non-measured channel
0
Low
Low
1
Low
Low
2
Low
Low
3
Pulse
Low
4
Pulse
Low
5
Low
Low
34.3.2.5
Mutual capacitance full scan mode operation
In mutual capacitance full scan mode, measurement is performed during the high-level period of the sensor drive pulse
on the receive channel by applying the edge to the target transmit channel to be measured. A single measurement target is
measured twice, on the rising and falling edges. The difference between the data of these two measurements determines
whether or not the electrode was touched. This creates higher touch sensitivity.
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34. Capacitive Touch Sensing Unit (CTSU)
Electrostatic capacitance is measured sequentially on channels set to transmission or reception in the CTSUCHTRC0 to
CTSUCHTRC3 registers and specified as measurement targets in the CTSUCHAC0 to CTSUCHAC3 registers. The
capacitance is measured by combining these signals. Figure 34.16 shows the software flow and an operation example,
and Figure 34.17 shows the timing.
Initial settings
• CTSU_CTSUWR interrupt operation setting:
Transfer from the RAM to the CTSUSSC, CTSUSO0, and CTSUSO1 registers
• CTSU_CTSURD interrupt operation setting:
Transfer the CTSUSC and CTSURC counters to the RAM
Set interrupt operation
(DTC or ICU)
Power supply stabilization
time has elapsed after
CTSUPON = 1
CTSUCR1 register:
• CTSUCR1.CTSUCLK[1:0] bits: Operating clock can be selected
• CTSUCR1.CTSUMD[1:0] bits: Set these bits to 11b
CTSUSDPRS register:
• CTSUSDPRS.CTSUSOFF bit: High-pass noise prevention can be turned off
• CTSUSDPRS.CTSUPRMODE[1:0] bits: Set the number of base pulses for synchronous noise
prevention
• CTSUSDPRS.CTSUPRRATIO[3:0] bits: Set the measurement time for synchronous noise prevention
CTSUSST register: Set the sensor stabilization time
CTSUCHAC0 to CTSUCHAC3 registers: Set the enabled channels
CTSUCHTRC0 to CTSUCHTRC3 registers: Allocate transmission or reception to the TS pins
CTSUMCH0 register: Set the measurement channel
Set CTSU control
(measurement starts)
using CTSUCR0 register
CTSUCR0.CTSUSTRT bit: Set this bit to 1
CTSUCR0.CTSUCAP bit: Starting of CTSU operation by external trigger can be selected
CTSUCR0.CTSUSNZ bit: Power-saving function during wait state can be enabled or disabled
Set CTSU registers
CTSU operation starts
CTSU_CTSUWR
interrupt generated?
No
CTSUSSC register
CTSUSO0 register
CTSUSO1 register
Set the measurement
channel
Transferred by the DTC
when the DTC is set
No
CTSU_CTSURD
generated?
Repeat for the number of
the measurement channels
Read the first
measurement result
CTSUSC counter
CTSURC counter
Transferred by the DTC
when the DTC is selected
No
CTSU_CTSURD
generated?
Read the second
measurement result
CTSUSC counter
CTSURC counter
Transferred by the DTC
when the DTC is selected
No Wait for the measurement end interrupt
CTSU_CTSUFN
generated?
Touch determination
processing
When a software trigger is used, the CTSUCR0.CTSUSTRT bit sets to 0 when CTSU operation stops.
Channel measurement sequence in mutual capacitance full scan mode
Settings:
• Select mutual capacitance full scan mode (CTSUCR1.CTSUMD[1:0] = 11b)
• Set channels 0, 3, 5, and 6 to enabled channels (CTSUCHAC0.CTSUCHAC0[7:0] bits = 01101001b)
• Set channels 0 to 3 to receive channels and channels 4 to 7 to transmit channels (CTSUCHTRC0.CTSUCHTRC0[7:0] bits = 11110000b)
Receive Channels
Channel 3
Channel 2
Channel 1
Channel 0
Channel 4
Transmit
channels
Channel 5
(3)
(1)
Channel 6
(4)
(2)
Channel 7
Figure 34.16
Software flow and operation example of mutual capacitance full scan mode
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34. Capacitive Touch Sensing Unit (CTSU)
Measurement of rising edge
Sensor stabilization wait time
(CTSUSST register)
Measurement of falling edge
Measurement time
Operating clock
CTSUCR0.CTSUSTRT bit
CTSUMCH0 register
63
(Receive channel)
0
CTSUMCH1 register
63
(Transmit channel)
CTSUST.CTSUSTC[2:0]
flags (Status)
0 1
0
2
1
2
3
4 (During current/count value conversion)
5
1
3
4 (During current/count value
conversion)
5
3 4
5
1
2
CTSUST.CTSUPS flag
Sensor ICO clock
0
CTSUSC counter
Measurement result
Measurement result
CTSU_CTSUWR interrupt
CTSU_CTSURD interrupt
CTSU_CTSUFN interrupt
Transmit pin state of
measurement channel
Sensor drive pulse
(1)
Figure 34.17
(2)
(3)
(4)
(5)
(6)
Timing of mutual capacitance full scan mode when the measurement start condition is a software
trigger
The following sequence describes the operation shown in Figure 34.17:
1. After initial settings are made, operation is started by writing 1 to the CTSUCR0.CTSUSTRT bit.
2. After the channel to be measured is determined according to the preset conditions, a request to set the channel
(CTSU_CTSUWR) is output.
3. On completion of writing the measurement channel settings (CTSUSSC, CTSUSO0, and CTSUSO1 registers), the
sensor drive pulse is output and the sensor ICO clock and the reference ICO clock operate. At the same time, a pulse
detected on the rising edge is output to the transmit pin on the measurement channel during the high-level period of
the sensor drive pulse.
4. After the sensor stabilization wait time and the measurement time have elapsed and measurement stops, a
measurement result read request (CTSU_CTSURD) is output.
5. The same channel is measured by outputting a pulse detected on the falling edge during the high-level period of the
sensor drive pulse.
6. After the same channel is measured twice, the channel to be measured next is determined and measured in the same
way.
7. On completion of all channel measurements, a measurement end interrupt (CTSU_CTSUFN) is output and
measurement stops (transition to Status 0).
The CTSU mutual capacitance status flag (CTSUST.CTSUPS bit) changes when Status 5 transitions to Status 1.
Table 34.8 lists the touch pin states in mutual capacitance full scan mode.
Table 34.8
Touch pin states in mutual capacitance full scan mode (1 of 2)
Touch pins for receive channels
Touch pins for transmit channels
Status
Measured
channels
Non-measured
channels
Measured
channels
Non-measured
channel
Remarks
0
Low
Low
Low
Low
-
1
Low
Low
Low/high
Low
-
2
Low
Low
Low
Low
-
3
Pulse
Low
Pulse
Low
The transmit pulse phase is the same as that of
the receive channel on the first measurement
and opposite on the second measurement.
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Table 34.8
34. Capacitive Touch Sensing Unit (CTSU)
Touch pin states in mutual capacitance full scan mode (2 of 2)
Touch pins for receive channels
Touch pins for transmit channels
Status
Measured
channels
Non-measured
channels
Measured
channels
Non-measured
channel
Remarks
4
Pulse
Low
Pulse
Low
-
5
Low
Low
Low
Low
-
34.3.3
Functions Common to Multiple Modes
34.3.3.1
Sensor stabilization wait time and measurement time
Figure 34.18 shows the timing of the sensor stabilization wait and measurement.
(1)
Sensor stabilization wait time
(CTSUSST register)
(2)
Measurement time
Sensor drive pulse
stop period
(3)
Operating clock
CTSUCR0.CTSUSTRT
bit
(4)
Sensor ICO clock
CTSUST.CTSUSTC[2:0]
flags (Status)
0
1
2
3
4
5
1
0
CTSU_CTSUWR interrupt
CTSU_CTSURD interrupt
CTSU_CTSUFN interrupt
Sensor drive pulse
Figure 34.18
Sensor stabilization wait and measurement timing
The following sequence describes the operation shown in Figure 34.18:
1. In response to the CTSU_CTSUWR interrupt request, output of the sensor drive pulse is started by a write access to
the CTSUSO1 register. The CTSU waits for the stabilization time set in the CTSUSST register.
2. When the sensor stabilization time elapses and the CTSUST.CTSUDTSR flag is set to 0, measurement starts on
transition to Status 4. The measurement time is determined by the base clock cycle setting and the
CTSUSDPRS.CTSUPRMODE[1:0], CTSUPRRATIO[3:0], and CTSUSO0.CTSUSNUM[5:0] bits. When the
measurement time elapses, measurement of the channel stops.
3. After the measurement time elapses, the status transitions to Status 1 after two operating clock cycles, and a
CTSU_CTSURD interrupt occurs. Read the data from the CTSUSC and CTSURC counters. The sensor drive pulse
is the output at the low level. When measurement of all specified channels completes, the CTSUCR0.CTSUSTRT
bit is set to 0.
4. The sensor ICO clock oscillates while the CTSUST.CTSUSTC[2:0] flags = 011b (Status 3) or 100b (Status 4).
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34.3.3.2
34. Capacitive Touch Sensing Unit (CTSU)
Interrupts
The CTSU supports the following interrupts:
Write request interrupt for setting registers for each channel (CTSU_CTSUWR)
Measurement data transfer request interrupt (CTSU_CTSURD)
Measurement end interrupt (CTSU_CTSUFN).
(1)
Write request interrupt for setting registers for each channel (CTSU_CTSUWR)
Store the settings for each measurement channel in the SRAM, and set up the DTC or ICU transfer associated with the
CTSU_CTSUWR interrupt in advance. The CTSU_CTSUWR interrupt is output when Status 1 transitions to Status 2.
Write the channel settings from the SRAM to the associated CTSUSSC, CTSUSO0, and CTSUSO1 registers (Figure
34.19). Because write access to the CTSUSO1 register controls a transition to the next status, you must set this register
last.
CTSU register
Write the settings for each channel
SRAM
Transfer
4008 1012h
CTSUSSC
4008 1014h
CTSUSO0
4008 1016h
CTSUSO1
Channel 0
Channel 1
First CTSU_CTSUWR interrupt
Second CTSU_CTSUWR interrupt
Figure 34.19
Channel 2
Example DTC transfer operation using the CTSU_CTSUWR interrupt
The registers to be set (CTSUSSC, CTSUSO0, and CTSUSO1) are allocated at sequential addresses. On
CTSU_CTSUWR interrupt generation, set up the operation as follows:
Transfer destination address: CTSUSSC register address
Handling at the transfer destination address: Transfer 2-byte data three times for a single interrupt. The address of
the start byte is fixed
Transfer source address: CTSUSSC register data storage address for the lowest number channel in the settings
stored in the SRAM
Handling at the transfer source address: Transfer 2-byte data three times for a single interrupt. The address of the
first byte is continued from the previous interrupt handling.
Number of transfers per interrupt: Specify the number of measurements.
(2)
Measurement data transfer request interrupt (CTSU_CTSURD)
Set up the DTC or ICU transfer associated with the CTSU_CTSURD interrupt in advance. The CTSU_CTSURD
interrupt is output when Status 5 transitions to Status 1. Read the measurement results from the CTSUSC and CTSURC
counters (Figure 34.20).
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34. Capacitive Touch Sensing Unit (CTSU)
CTSU register
Write the measurement results
for each channel
RAM
Transfer
4008 1018h
CTSUSC
4008 101Ah
CTSURC
Channel 0
Channel 1
First CTSU_CTSURD interrupt
Second CTSU_CTSURD interrupt
Figure 34.20
Channel 2
Example DTC transfer operation using the CTSU_CTSURD interrupt
The measurement result registers (CTSUSC and CTSURC counters) used as transfer sources are allocated at sequential
addresses. On CTSU_CTSURD interrupt generation, set up the operation as follows:
Transfer source address: CTSUSC counter address
Handling at the transfer source address: Transfer 2-byte data twice for a single interrupt. The start address is fixed.
Transfer destination address: CTSUSC counter data storage address for the lowest number channel in the settings
stored in the SRAM
Handling at the transfer destination address: Transfer 2-byte data twice for a single interrupt. The start address is
continued from the previous interrupt handling
Number of transfers per interrupt: Specify the number of measurements.
(3)
Measurement End Interrupt (CTSU_CTSUFN)
After all channels are measured, an interrupt occurs when Status 1 transitions to Status 0. In the software, check the
overflow flags (CTSUST.CTSUSOVF and CTSUROVF) and read the measurement results to determine whether the
electrode was touched. Interrupt requests are accepted or disabled in the interrupt control block.
34.4
34.4.1
Usage Notes
Measurement Result Data (CTSUSC and CTSURC Counters)
Read access during measurement is prohibited. If the measurement result data is accessed, an incorrect value might be
read because of an asynchronous operation.
34.4.2
Software Trigger
When 10b (PCLKB/4) is selected in the CTSUCR1.CTSUCLK[1:0] bits, to restart measurement by writing 1 to the
CTSUR0.CTSUSTRT bit after measurement is complete, wait for at least 3 cycles to elapse after an interrupt occurs, and
then write to the CTSUCR0.CTSUSTRT bit.
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34. Capacitive Touch Sensing Unit (CTSU)
Writing 1 to CTSUSTRT (restart) is disabled
PCLKB
CTSU_CTSUFN interrupt
CTSUSTRT
Automatically cleared by CTSU
Figure 34.21
34.4.3
Restart setting is possible (fastest)
Notes on restarting measurement
External Trigger
If an external trigger is input during the measurement time, measurement does not start. The next external event is
enabled after 1 cycle of the operating clock when a CTSU_CTSUFN interrupt occurs.
To stop external trigger mode, write 0 to the CTSUCR0.CTSUSTRT bit and 0 to the CTSUCR0.CTSUINIT bit at
the same time (forced stop).
34.4.4
Notes on Forcing Operation Stop
To force the current operation to stop, write 0 to the CTSUCR0.CTSUSTRT bit and 1 to the CTSUCR0.CTSUINIT bit at
the same time. After this setting, the operation is stopped and the internal control registers are initialized.
When the CTSUCR0.CTSUINIT bit is used for initialization, the following registers are initialized in addition to the
internal measurement state:
CTSUMCH0 register
CTSUMCH1 register
CTSUST register
CTSUSC counter
CTSURC counter.
If operation is forced to stop, an interrupt request might be generated depending on the internal state. After a forced stop,
perform the processing for stopping or disabling the DTC or ICU. If a DTC transfer is stopped in an installed system for
some reason, also perform the processing to force the stop and to initialize the CTSU.
34.4.5
TSCAP Pin
The TSCAP pin requires an external decoupling capacitor to stabilize CTSU internal voltage. The traces between the
TSCAP pin and the capacitor, and the capacitor and ground should be as short and wide as physically possible.
The capacitor connected to the TSCAP pin should be fully discharged using I/O port control to output low before turning
on the switch (CTSUCR1.CTSUCSW bit = 1) to establish a connection.
34.4.6
Notes on Measurement Operation (CTSUCR0.CTSUSTRT Bit = 1)
During measurement (CTSUCR0.CTSUSTRT bit = 1), do not use the settings for stopping the peripheral clock or
changing the port settings related to the touch pins (TS and TSCAP) in the higher layers of the system.
If control settings non-compliant with this constraint are made, after operation is forced to stop (CTSUCR0.CTSUSTRT
bit = 0 and CTSUCR0.CTSUINIT bit = 1), write 0 to the CTSUCR1.CTSUPON bit and 0 to the CTSUCR1.CTSUCSW
bit at the same time, and set the CTSUCR0.CTSUSNZ bit to 0. Next, restart from the initial settings flow shown in
Figure 34.9.
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35. Data Operation Circuit (DOC)
35.
Data Operation Circuit (DOC)
35.1
Overview
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. An interrupt can be generated when a
selected condition applies. Table 35.1 lists the DOC specifications and Figure 35.1 shows a block diagram.
Table 35.1
DOC specifications
Parameter
Description
Data operation function
16-bit data comparison, addition, and subtraction
Module-stop function
Module-stop state can be set to reduce power consumption
Interrupts and event link function (DOC_DOPCI)
An interrupt occurs on the following conditions:
The compared values either match or mismatch
The result of data addition is greater than FFFFh
The result of data subtraction is less than 0000h.
Internal peripheral bus
DODIR
Operation
circuit
DOC_DOPCI
DODSR
OMS[1:0]
DOCR
DOCR:
DODIR:
DODSR:
Figure 35.1
DOC control register
DOC data input register
DOC data setting register
DOC block diagram
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35.2
35. Data Operation Circuit (DOC)
Register Descriptions
35.2.1
DOC Control Register (DOCR)
Address(es): DOC.DOCR 4005 4100h
b7
—
Value after reset:
b6
b5
DOPCF DOPCF
CL
0
0
0
b4
b3
b2
—
—
DCSEL
0
0
0
b1
b0
OMS[1:0]
0
0
Bit
Symbol
Bit name
Description
R/W
b1, b0
OMS[1:0]
Operating Mode Select
b1 b0
R/W
b2
DCSEL*1
Detection Condition Select
0: Set DOPCF when data mismatch is detected
1: Set DOPCF when data match is detected.
R/W
b4, b3
—
Reserved
There bits are read as 0. The write value should be 0.
R/W
0
0
1
1
0: Data comparison mode
1: Data addition mode
0: Data subtraction mode
1: Setting prohibited.
b5
DOPCF
Data Operation Circuit Flag
Indicates the result of an operation
R
b6
DOPCFCL
DOPCF Clear
0: Save DOPCF flag state
1: Clear DOPCF flag.
R/W
b7
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
Note 1. Only valid when data comparison mode is selected.
OMS[1:0] bits (Operating Mode Select)
The OMS[1:0] bits select the operating mode of the DOC.
DCSEL bit (Detection Condition Select)
The DCSEL bit selects the detection condition in data comparison mode. This bit is only valid when data comparison
mode is selected.
DOPCF flag (Data Operation Circuit Flag)
[Setting conditions]
The condition selected in the DCSEL bit is met
A data addition result is greater than FFFFh.
A data subtraction result is less than 0000h.
[Clearing condition]
Writing 1 to the DOPCFCL bit.
DOPCFCL bit (DOPCF Clear)
Setting the DOPCFCL bit to 1 clears the DOPCF flag. This bit is read as 0.
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35.2.2
35. Data Operation Circuit (DOC)
DOC Data Input Register (DODIR)
Address(es): DOC.DODIR 4005 4102h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The DODIR register is a 16-bit read/write register that stores 16-bit data for use in all operations.
35.2.3
DOC Data Setting Register (DODSR)
Address(es): DOC.DODSR 4005 4104h
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The DODSR register is a 16-bit read/write register that stores 16-bit data used as a reference in data comparison mode.
This register also stores the results of operations in data addition and subtraction modes.
35.3
Operation
35.3.1
Data Comparison Mode
Figure 35.2 shows an example DOC operation in data comparison mode. In this example, the DCSEL bit is set to 0 (data
mismatch is detected as a result of data comparison). The steps are as follows:
1. Write 00b to the DOCR.OMS[1:0] bits to select data comparison mode.
2. Set the 16-bit reference data in the DODSR register.
3. Write the 16-bit data to be compared to the DODIR register.
4. Continue writing 16-bit data until all data to be compared is written to the DODIR register.
5. When DOCR.DCSEL = 0, if a value written to DODIR does not match that in DODSR, the DOCR.DOPCF flag is
set to 1.
DOCR.OMS[1:0] bits
xxb
00b
xxxxh
DODSR register
AAAAh
xxxxh
DODIR register
DOCR.DOPCF bit
5555h
AAAAh
Write 1 to
DOCR.DOPCFCL bit
1
0
(1)
Figure 35.2
AAAAh
(2)
(3)
(4)
(5)
Example operation in data comparison mode
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35.3.2
35. Data Operation Circuit (DOC)
Data Addition Mode
Figure 35.3 shows an example DOC operation in data addition mode. The steps are as follows:
1. Write 01b to the DOCR.OMS[1:0] bits to select data addition mode.
2. Set 16-bit data as the initial value in the DODSR register.
3. Write the 16-bit data to be added to the DODIR register. The result of the operation is stored in the DODSR register.
4. Continue writing 16-bit data to the DODIR register until all data to be added is written.
5. If the result of an operation is greater than FFFFh, the DOCR.DOPCF flag is set to 1.
DOCR.OMS[1:0] bits
xxb
01b
xxxxh
DODSR register
FFF0h
xxxxh
DODIR register
DOCR.DOPCF bit
FFF4h
FFFAh
0002h
0004h
0006h
0008h
Write 1 to
DOCR.DOPCFCL bit
1
0
(1)
Figure 35.3
35.3.3
(2)
(3)
(5)
(4)
Example operation in data addition mode
Data Subtraction Mode
Figure 35.4 shows an example DOC operation in data subtraction mode. The steps are as follows:
1. Write 10b to the DOCR.OMS[1:0] bits to select data subtraction mode.
2. Set 16-bit data as the initial value in the DODSR register.
3. Write the 16-bit data to be subtracted to the DODIR register. The result of the operation is stored in the DODSR
register.
4. Continue writing 16-bit data to the DODIR register until all data to be subtracted is written.
5. If the result of an operation is less than 0000h, the DOCR.DOPCF flag is set to 1.
DOCR.OMS[1:0] bits
xxb
10b
DODSR register
xxxxh
000Fh
DODIR register
DOCR.DOPCF bit
xxxxh
0005h
FFFDh
0004h
0006h
0008h
Write 1 to
DOCR.DOPCFCL bit
1
0
(1)
Figure 35.4
000Bh
(2)
(3)
(4)
(5)
Example operation in data subtraction mode
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35.4
35. Data Operation Circuit (DOC)
Interrupt Request and Event Link Output
The DOC outputs an event signal to the ELC under the following conditions:
The compared values either match or mismatch
The data addition result is greater than FFFFh
The data subtraction result is less than 0000h.
This signal can initiate operations by other modules selected in advance and can also serve as an interrupt request. When
an event signal occurs, the data operation circuit flag (DOCR.DOPCF) is set to 1.
35.5
35.5.1
Usage Note
Settings for the Module-Stop State
The Module Stop Control Register C (MSTPCRC) can enable or disable DOC operation. The DOC is initially stopped
after reset. Releasing the module-stop state enables access to the registers. For details, see section 10, Low Power Modes.
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36.
36. SRAM
SRAM
The MCU provides on-chip, high-speed SRAMs with parity-bit protection.
36.1
Overview
Table 36.1 lists the SRAM specifications.
Table 36.1
SRAM specifications
Parameter
Description
SRAM capacity
SRAM0: 16 KB
SRAM address
2000 0000h to 2000 3FFFh
Access*1
0 wait
Module-stop function
Not available
Parity
Even parity with 8-bit data and 1 parity bit
Error checking
Even parity error check
SRAM0 and Trace_RAM are shared. For the Trace_RAM specifications, see the ARM® CoreSight™ MTB-M0+
Technical Reference Manual.
Note 1. For details, see section 36.3.3, Access Cycle.
Note:
36.2
Register Descriptions
36.2.1
SRAM Parity Error Operation After Detection Register (PARIOAD)
Address(es): SRAM.PARIOAD 4000 2000h
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
OAD
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit name
Description
R/W
b0
OAD
Operation After Detection
1: Reset
0: Non-maskable interrupt.
R/W
b7 to b1
—
Reserved
These bits are read as 0. The write value should be 0.
R
The SRAM protection register (SRAMPRCR) protects this register against writes. Always set the SRAMPRCR bit in
SRAMPRCR to enabled before writing to this bit. Do not write to the PARIOAD register while accessing the SRAM.
OAD bit (Operation After Detection)
The OAD bit specifies either a reset or non-maskable interrupt when a parity error is detected. It applies to SRAM0.
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36.2.2
36. SRAM
SRAM Protection Register (SRAMPRCR)
Address(es): SRAM.SRAMPRCR 4000 2004h
b7
b6
b5
b4
b3
b2
b1
SRAMP
RCR
KW[6:0]
Value after reset:
0
0
0
0
b0
0
0
0
0
Bit
Symbol
Bit name
Description
R/W
b0
SRAMPRCR
Register Write Control
0: Disable writes to the protected register
1: Enable writes to the protected register.
R/W
b7 to b1
KW[6:0]
Write Key Code
These bits enable or disable writes to the SRAMPRCR bit. R/W
SRAMPRCR bit (Register Write Control)
The SRAMPRCR bit controls the write mode of the PARIOAD register. Setting the bit to 1 enables writes to the
PARIOAD register. When you write to this bit, always write 78h to KW[6:0] at the same time.
KW[6:0] bit (Write Key Code)
The KW[6:0] bits enable or disable writes to the SRAMPRCR bit. When you write to SRAMPRCR bit, always write 78h
to these bits at the same time. When any other value is written to KW[6:0], the SRAMPRCR bit does not update. The
KW[6:0] bits always read as 00h.
36.2.3
Trace Control (for the MTB)
The Micro Trace Buffer (MTB) has programmable registers to control the behavior of the trace features and the
POSITION, MASTER, FLOW, and BASE registers. The following shows the registers in offset order from the base
address:
MTB_BASE: 4001 9000h
MTB_BASE + 000h: POSITION value on reset:
MTB_BASE + 004h: MASTER value on reset:
MTB_BASE + 008h: FLOW (Value after reset:
MTB_BASE + 00Ch: BASE
Bits [31:0] = UNKNOWN)
Bits [31] = 0, Bits [30:10] = UNKNOWN,
Bits [9:8] = 0, Bits [7]=1, Bits [6:5] = 0,
Bits [4:0] = UNKNOWN)
Bits [31:2] = UNKNOWN, Bits[1:0] = 0
For more information on these registers, see the ARM® CoreSight™ MTB-M0+ Technical Reference Manual (revision:
r0p1).
Note:
36.2.4
Do not attempt to access reserved or unused address locations. This can result in UNPREDICTABLE behavior.
CoreSight™ (for MTB)
See the ARM® CoreSight™ Architecture Specification for more information about the registers and access types. The
following shows the registers in offset order from the base address:
MTB_BASE: 4001 9000h
MTB_BASE + FF0h to FFCh: Component ID
MTB_BASE + FE0h to FDCh: Peripheral ID
MTB_BASE + FCCh: Device Type Identifier
MTB_BASE + FC8h: Device Configuration
MTB_BASE + FBCh: Device Architecture
MTB_BASE + FB8h: Authentication Status
MTB_BASE + FB4h: Lock Status
MTB_BASE + FB0h: Lock Access
For more information on these registers, see the ARM® CoreSight™ MTB-M0+ Technical Reference Manual (Revision:
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36. SRAM
r0p1).
Note:
Do not attempt to access reserved or unused address locations. This can result in UNPREDICTABLE behavior.
36.3
Operation
36.3.1
Parity Calculation Function
To meet the IEC60730 standard requirement of checking the SRAM data, a parity detection function is included. The
function adds a parity bit to all 8-bit data in the SRAM which has 32-bit data width when data is written, and it checks the
parity when the data is read. When a parity error occurs, a parity-error notification is generated. This function can also
trigger a reset. The specification of SRAM0 is even parity.
The parity-error notification can be specified as either a non-maskable interrupt or a reset, in the OAD bit of the
PARIOAD register. When OAD is 1, a parity error is output to the Reset function. When OAD is 0, a parity error is
output to the ICU as non-maskable interrupt.
Parity errors often occur because of noise. To check whether the parity error cause is noise or damage, follow the parity
check flows shown in Figure 36.1 and Figure 36.2.
Start of Check
Yes
*RPERF = 1?
No
Initial setting
(Parity Reset)
Initial setting
(Parity NMI)
Check SRAM
Check SRAM
Parity error
generated?
Parity error
generated?
No
Yes
No
Yes
Reset generated
Normal
operation
SRAM failure
processing
*RPERF: SRAM parity error reset detect flag (RSTSR1.RPERF bit)
Figure 36.1
Flowchart of SRAM parity check when the SRAM parity reset is enabled
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36. SRAM
Start of check
Initial setting
(Parity NMI)
Check SRAM
Parity error
generated?
Yes
No
*RPEST = 0
Check SRAM
RETURN
No
*RPEST = 1?
Yes
Normal
operation
SRAM failure
processing
*RPEST: SRAM parity error interrupt status flag (NMISR.RPEST bit)
Figure 36.2
36.3.2
Flowchart of SRAM parity check when the SRAM parity interrupt is enabled
SRAM Error Source
The SRAM error source is a parity error. Parity errors can be specified as either non-maskable interrupts or a reset, in the
OAD bit of PARIOAD. TDC activation is not supported for SRAM parity errors.
36.3.3
Table 36.2
Access Cycle
SRAM0 access cycle (parity area 2000 0000h to 2000 3FFFh)
Read (cycles)
Word access
Write (cycles)
Halfword or byte access
2
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Halfword or byte access
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36.4
36.4.1
36. SRAM
Usage Note
Instruction Fetch from the SRAM Area
When using SRAM0 to operate a program, initialize the SRAM area so that the CPU can correctly prefetch the data. If
the CPU prefetches from an uninitialized SRAM area, a parity error might occur. Initialize the additional 2-byte area
from the end address of programs with a 4-byte boundary. Renesas recommends using a NOP instruction to initialize
these areas.
36.4.2
Store Buffer of SRAM
For fast access between SRAM and CPU, a store buffer is used. When a load instruction is executed from the same
address after a store instruction to SRAM, the load instruction might read out data from the buffer instead of data on the
SRAM. To read data on the SRAM correctly, use either of the following procedures:
After writing to the SRAM (address = A), use the NOP instruction, then read the SRAM (address = A)
After writing to the SRAM (address = A), read data from area other than SRAM (address = A), then read the SRAM
(address = A).
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37.
Flash Memory
37.1
Overview
37. Flash Memory
The MCU provides 128-KB code flash memory and 4-KB data flash memory. The Flash Control Block (FCB) controls
the programming commands.
This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
Table 37.1 lists the specifications of the code flash memory and data flash memory. Figure 37.1 shows the block diagram
of the related modules. Figure 37.2 shows the configuration of the code flash memory and Figure 37.3 shows the
configuration of the data flash memory.
Table 37.1
Specifications of code flash memory and data flash memory
Parameter
Code flash memory
Data flash memory
Memory capacity
128 KB of user area
4 KB of data area
Read cycle
ICLK frequency ≤ 32 MHz
ICLK frequency ≤ 32 MHz
A read operation takes 6 ICLK cycles in bytes.
Value after erasure
FFh
FFh
Programming and erasing method
Programming and erasing of code and data flash memory through the FCB commands
specified in the registers
Programming by dedicated flash-memory programmer through a serial interface (serial
programming)
Programming of flash memory by a user program (self-programming).
Security function
Protection against illicit tampering with or reading of data in flash memory
Protection
Protection against erroneous overwriting of the flash memory
Background operations (BGOs)
Code flash memory can be read during data flash memory programming.
Programming and erasing units
32-bit units for programming in user area
1-KB erasing units for the user area.
Other functions
Interrupts accepted during self-programming
8-bit units for programming in data area
1-KB units for erasure in data area.
An expansion area of flash memory (option bytes) can be set in the initial MCU settings
On-board programming
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Programming in serial programming mode (SCI boot mode):
Asynchronous serial interface (SCI9) used
Transfer rate adjusted automatically
Programming in On-Chip Debug (OCD) mode:
SWD interface used
Dedicated hardware not required.
Programming by a routine code and data flash programming within the user program:
Allows code and data flash memory programming without resetting the system.
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37. Flash Memory
Internal peripheral bus 0
CPU
Flash ready interrupt
(FCU_FRDYI)
FCB
MD pin
Figure 37.1
37.2
Memory bus 1
Data flash memory
Code flash memory
Mode control
Block diagram of flash memory-related modules
Memory Structure
Figure 37.2 shows the mapping of the code flash memory, and Table 37.2 shows the read and programming/erasure
addresses of the code flash memory. The user area of the code flash memory is divided into 1-KB blocks, which serve as
the erasure units. The user area is available for storing user program.
Read address
0001 FFFFh
Block 127 (1 KB)
128 KB
:
0000 0000h
Figure 37.2
Table 37.2
Block 0 (1 KB)
Mapping of code flash memory
Read and P/E addresses of the code flash memory
Size of code flash memory
Read address
P/E address
Number of blocks
128 KB
0000 0000h to 0001 FFFFh
0000 0000h to 0001 FFFFh
0 to 127
The data area of the data flash memory is divided into 1-KB blocks, with each being an erasure unit. Figure 37.3 shows
the mapping of the data flash memory, and Table 37.3 shows the read and programming/erasure addresses of the data
flash memory.
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37. Flash Memory
Read address
P/E Address
4010 0FFFh
FE00 0FFFh
Block 3 (1 KB)
4 KB
Block 2 (1 KB)
Block 1 (1 KB)
Block 0 (1 KB)
4010 0000h
Figure 37.3
Table 37.3
FE00 0000h
Mapping of data flash memory
Read and P/E addresses of the data flash memory
Size of data flash memory
Read address
P/E address
Number of blocks
4 KB
4010 0000h to 4010 0FFFh
FE00 0000h to FE00 0FFFh
0 to 3
37.3
Operating Modes Associated with the Flash Memory
Figure 37.4 shows a diagram of the mode transitions associated with the flash memory. For information on setting up the
modes, see section 3, Operating Modes.
Reset
Set Serial programming
mode
m
od
pe
ra
tin
g
t
Re
se
No
rm
al
o
e
od
m
Serial programming mode
(SCI boot mode)
g
bu
de
t
Se
t
ip
ch
n-
Figure 37.4
se
Re
Normal operating mode
tO
Se
e
Reset state
On-chip debug mode
(SWD boot mode)
Mode transitions associated with the flash memory
The flash memory areas where programming and erasure are permitted, and where the boot program executes after a
reset differs with the mode. Table 37.4 shows the differences between the modes.
Table 37.4
Difference between modes
Parameter
Normal operating mode
Serial programming mode
(SCI boot mode)
On-chip debug mode
(SWD boot mode)
Programmable and erasable
areas
Code flash memory
Data flash memory
Code flash memory
Data flash memory
Code flash memory
Data flash memory
Erasure in block units
Possible
Possible
Possible
Boot program on reset
User area program
Embedded program for serial
programming
Depends on debug command
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37.3.1
37. Flash Memory
ID Code Protection
The ID code protection function prohibits programming and on-chip debugging. When ID code protection is enabled, the
device validates or invalidates the ID code sent from the host by comparing it with the ID code stored in the flash
memory. Programming and on-chip debugging are enabled only when the two match.
The ID code in the flash memory consists of four 32-bit words. ID code bits [127] and [126] determine whether ID code
protection is enabled and the authentication method to use with the host. Table 37.5 shows how ID code determines the
authentication method.
Table 37.5
Specifications for ID code protection
Operating mode on boot
up
ID code
State of protection
Serial programming mode
(SCI boot mode)
FFh, …, FFh
(all bytes FFh)
Protection disabled
ID code validation is not performed, the ID code
always matches, and connection to the programmer
or the on-chip debugger is permitted
Bit [127] = 1 and bit [126]
= 1, and at least one of the
16 bytes is not FFh
Protection enabled
Matching ID code: Authentication ends and
connection to the programmer or the on-chip
debugger is permitted.
Mismatching ID code: Additional transition to the ID
code protection waiting state.
On-chip debug mode
(SWD boot mode)
Operations on connection with the programmer
or on-chip debugger
When the ID code sent from the programmer or the
on-chip debugger is “ALeRASE” in ASCII code
(414C_6552_4153_45FF_FFFF_FFFF_FFFF_FFF
Fh), the content of the user flash (code and data)
area and configuration area are erased immediately.
However, forced erasure is not executed when the
FSPR bit is 0.
37.4
bit [127] = 1 and bit [126] =
0
Protection enabled
Matching ID code: Authentication ends and
connection to the programmer or the on-chip
debugger is permitted.
Mismatching ID code: Additional transition to the ID
code protection waiting state.
Bit [127] = 0
Protection enabled
ID code validation is not performed, the ID code is
always mismatching, and connection to the
programmer or the on-chip debugger is prohibited
Overview of Functions
By using a dedicated flash-memory programmer to program the on-chip flash memory through a serial interface for
serial programming or through an SWD interface for on-chip debug mode, the device can be programmed before or after
it is mounted on the target system. Additionally, security functions to prohibit overwriting of the user program prevent
tampering by third parties.
Programming by the user program (self-programming) is available for applications that might require updating after
system manufacturing or shipment. Protection features for safely overwriting the flash memory area are also provided.
Additionally, interrupt processing during self-programming is supported so that programming can proceed while
processing external communications and other functions. Table 37.6 lists the programming methods and the
corresponding operating modes.
Table 37.6
Programming methods (1 of 2)
Programming method
Functional overview
Operating mode
Serial programming
A dedicated flash-memory programmer connected through the SCI
interface enables on-board programming of the flash memory after the
device is mounted on the target system
Serial programming mode
A dedicated flash-memory programmer connected through the SCI and
a dedicated programming adapter board allow off-board programming of
the flash memory, for example, programming of the device before it is
mounted on the target system
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Table 37.6
37. Flash Memory
Programming methods (2 of 2)
Programming method
Functional overview
Operating mode
Self-programming
A user program written to memory in advance of serial programming
execution can also program the flash memory. The background
operation capability makes it possible to fetch instructions or otherwise
read data from the code flash memory while the data flash memory is
programmed. As a result, a program resident in code flash memory is
able to program the data flash memory.
Background operation can also be used to read the code flash memory
while programming the data flash memory (see Table 37.11).
While the code flash memory is being self-programmed, background
fetching of instructions in the code flash memory and data access are
not possible. In such cases, a program for programming from the
internal SRAM or external memory must be transferred in advance and
executed.
Normal operating mode
SWD programming
A dedicated flash-memory programmer or an on-chip debugger
connected through SWD enables on-board programming of the flash
memory after the device is mounted on the target system
On-chip debug mode
A dedicated flash-memory programmer or an on-chip debugger
connected through SWD and a dedicated programming adapter board
allow off-board programming of the flash memory, for example,
programming of the device before it is mounted on the target system
Table 37.7 lists the functions of the on-chip flash memory. Use serial programmer commands for serial programming.
For self-programming, use the programming commands to read the on-chip flash memory or run the user program.
Table 37.7
Basic functions
Supported/not supported
Function
Functional overview
Serial programming
Self-programming
Blank check
Checks a specified block to ensure that writing to it
has not already proceeded. Results of reading from
data flash memory to which nothing was written after
erasure are not guaranteed, so use blank checking
to confirm that writing to memory has not occurred
after erasure.
Not supported
Supported
Block erasure
Erases the memory contents in the specified block
Supported
Supported
Programming
Writes to the specified address
Supported
Supported
Read
Reads data programmed to the flash memory
Supported
Not supported
(read by user program is
possible)
ID code check
Compares the ID code sent by the host with the
code stored in the ROM, and if the two match, the
FCB enters the wait state for programming and
erasure commands from the host.
Supported
Not supported
(ID authentication is not
performed)
Security configuration
Configures the security function for serial
programming
Supported with conditions
(only switching the
configuration from enabled
to disabled is possible)
Supported with conditions
(only switching the
configuration from enabled
to disabled is possible)
Protection
configuration
Configures access window for flash area protection
in the code flash memory
Supported
Supported
The on-chip flash memory supports the ID code security function. Authentication of ID codes is a security function for
use with serial programming and SWD programming. Table 37.8 lists the security functions supported by the on-chip
flash memory, and Table 37.9 lists available operations and security settings.
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Table 37.8
37. Flash Memory
Security functions
Function
Description
ID authentication
The result of ID authentication can be used to control the connection of a serial programmer for serial
programming
Table 37.9
Available operations and security settings
All security settings and erasure, programming, and read operations
Constraints on the
security setting
configuration
Function
Serial programming and on-chip debug mode
Self-programming mode
Self-programming mode
ID authentication
When ID codes do not match:
Block erasure commands not supported
Programming commands not supported
Read commands not supported
Security configuration commands not supported
Protection configuration commands not
supported.
ID authentication is not
performed:
Blank check supported
Block erasure supported
Programming supported
Security configuration
supported
Protection configuration
supported.
ID authentication is not
performed
When ID codes match:
Block erasure commands supported
Programming commands supported
Read commands supported
Security configuration commands supported
Protection configuration commands supported.
37.4.1
Configuration Area Bit Map
The bits used for the ID authentication, startup area select, access window protection, and security configuration
functions are mapped in Figure 37.5. The boot program must use these bits as hexadecimal data.
Base R-address 0101_0000h
P/E-address 0000_0000h
Bit
offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ID[127:96]
0030h
002Ch
ID[95:64]
0028h
0024h
ID[63:32]
0020h
001Ch
ID[31:0]
0018h
0014h
FAWE[11:0]
0010h
000Ch
FSPR
0008h
Figure 37.5
37.4.2
8
7
6
5
4
3
2
1
0
FAWS[11:0]
BTFLG
Configuration area bit map
Startup Area Select
The startup area select function allows the boot program to be safely updated. The size of the startup area is 8 KB and the
startup area is located in the user area. The FCB controls the address based on the startup area select flag (BTFLG) that is
located in the configuration area or the AWSC register. The startup area can be locked by the FSPR bit.
Figure 37.6 shows an overview of the startup program protection.
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Address
37. Flash Memory
Before rewriting
(1)
(2)
User program
User program
User program
No program
(alternate area)
New startup
program
(alternate area)
Original startup
program
(default area)
Original startup
program
(default area)
Original startup
program
(default area)
New startup
program
(alternate area)
0000 3FFFh
0000 1FFFh
0000 0000h
(1) Program a new startup program in the alternate area. If the alternate area fails to be rewritten, the new startup
program can be rewritten again after starting up using the default area , because the original startup program is in
the default area.
(2) After the alternate area is successfully rewritten, the default area and the alternate area are switched using the
self-programming library. After that, the program in the alternate area starts after a reset .
Figure 37.6
37.4.3
Overview of startup program protection
Protection with the Access Window
Issuing the program or block erase command to a flash memory area outside of the access window results in the
command-locked state. The access window is only valid in the user area of the code flash memory. The access window
provides protection in self-programming, serial programming, and on-chip debug modes.
Specify the access window in the FAWS[11:0] bits and the FAWE[11:0] bits. The following describes how to set the
FAWS and the FAWE bits in different conditions:
FAWE[11:0] = FAWS[11:0]: The P/E command can execute anywhere in the user area of the code flash memory.
FAWE[11:0] > FAWS[11:0]: The P/E command can only execute in the window from the block pointed to by the
FAWS bits to one block lower than the block pointed to by the FAWE bits.
FAWE[11:0] < FAWS[11:0]: The P/E command cannot execute anywhere in the user area of the code flash
memory.
Figure 37.7 shows an overview of flash area protection.
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37. Flash Memory
Address
…
0001 FFFFh
Disabled
0000 2000h
0000 1FFFh
Block 8
Block 7
(end block)
Block 6
Access
window
Enabled
Block 5
0000 1000h
Block 4
(start block)
0000 0FFFh
Block 3
Block 2
Disabled
Block 1
0000 0000h
Figure 37.7
37.5
Block 0
Flash area protection overview
Programming Commands
The FCB controls the programming commands.
37.6
Suspend Operation
The forced stop command forces the blank check or block erase command to stop. When a forced stop is executed, the
stopped address values are stored in the registers. The command can restart from the stopped address after a reset to the
registers for command execution by copying the saved addresses.
37.7
Protection
The types of protection include:
Software protection
Error protection
Boot program protection.
37.8
Serial Programming Mode
The serial programming mode includes boot mode with SCI9. Table 37.10 lists the I/O pins of the flash memory-related
modules.
Table 37.10
II/O pins of flash memory-related modules
Pin name
I/O
Applicable modes
Function
MD
Input
SCI boot mode
(serial programming mode)
Selection of operating mode
P110/RXD9
Input
SCI boot mode
For host communication, to receive data through the SCI
P109/TXD9
Output
37.8.1
For host communication, to transmit data through the SCI
SCI Boot Mode
In boot mode, the host sends control commands and data for programming, and the code and data flash memory areas are
programmed or erased accordingly. An on-chip SCI handles transfers between the host and the MCU in asynchronous
mode. Tools for transmission of control commands and the programming data must be prepared in the host.
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37. Flash Memory
When the MCU is activated in boot mode, the embedded program for serial programming is executed. This program
automatically adjusts the bit rate of the SCI and controls programming and erasure by receiving control commands from
the host.
Figure 37.8 shows the system configuration for operations in boot mode.
Code flash memory
Data flash memory
Host
Boot programming
tools and
programming data
Boot program
Control commands and
programming data
SCI
Status
Figure 37.8
37.9
System configuration in SCI boot mode
Using a Serial Programmer
Use a dedicated flash memory programmer to program the flash memory in serial programming mode. The MCU is
mounted on the system board for serial programming. A connector to the board enables programming by the flash
memory programmer.
Figure 37.9 shows the recommended environment for programming the flash memory of the MCU with data.
Reception
RS-232-C
USB
Level
converter
Transmission
This MCU
Host machine
Figure 37.9
Environment for writing programs to the flash memory
37.10 Self-Programming
37.10.1
Overview
The MCU supports programming of the flash memory by the user program itself. The programming commands can be
used with user programs for writing to the code and data flash memory. This enables updates to the user programs and
overwriting of constant data fields.
The background operation facility makes it possible to execute a program from the code flash memory to program the
data flash memory under the conditions shown in Table 37.11. This program can also be copied in advance to and
executed from the internal SRAM. When executing from the internal SRAM, this program can also program the code
flash memory area.
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37. Flash Memory
Internal SRAM
Internal SRAM or code flash memory
User’s programming program
User’s programming program
Programming command
Programming command
Execution of programming command
functions
Erasure and programming
Information on
flash memory
Execution of programming command
functions
Erasure and programming
Code flash memory
Figure 37.10
37.10.2
Information on
flash memory
Data flash memory
Schematic view of self-programming
Background Operation
Background operation can be used when a combination of the flash memory for writing and reading is any of those listed
in Table 37.11.
Table 37.11
Conditions under which background operation is available
Product
Writable range
Readable range
Common to all products
Data flash memory
Code flash memory
37.11 Reading the Flash Memory
37.11.1
Reading the Code Flash Memory
No special settings are required to read the code flash memory in normal mode. Data can be read through access to
addresses in the code flash memory. Values read from code flash memory that was erased but not yet reprogrammed,
such as code flash memory in the non-programmed state, are all read as 1s.
37.11.2
Reading the Data Flash Memory
No special settings are required to read the data flash memory in normal mode, except when issuing a reset that causes
the data flash access disable mode to disable reading. In this case, the application must transfer back to the data flash read
mode. Values read from data flash memory that was erased but not yet reprogrammed, such as data flash memory in the
non-programmed state, are all read as 1s.
37.12 Usage Notes
37.12.1
Erase Suspended Area
Data in areas where an erase operation is suspended is undefined. To avoid malfunctions caused by reading undefined
data, do not execute commands or read data in an area where erase operation is suspended.
37.12.2
Suspension with Erase Suspend Commands
When suspending an erase operation with the erase suspend command, complete the operation with a resume command.
37.12.3
Constraint on Additional Writes
Other than the configuration area, no other area can be written to twice. After a write to a flash memory area is complete,
erase the area before attempting to overwrite data in that area. The configuration area can be overwritten.
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37.12.4
37. Flash Memory
Reset during Programming and Erasing
If inputting a reset from the RES pin, release the reset after a reset input time of at least tRESW (see section 41, Electrical
Characteristics) within the range of the operating voltage defined in the electrical characteristics.
The IWDT reset and software reset do not require a tRESW input time.
37.12.5
Non-maskable Interrupt Disabled during Programming and Erasing
Do not enable non-maskable interrupts*1 during program and erase operations in the code flash memory. When a nonmaskable interrupt occurs during a program or erase operation, the vectors are fetched from the code flash memory, and
undefined data is read. This constraint only applies to the code flash memory.
Note 1. A non-maskable interrupts is an NMI pin interrupt, oscillation stop detection interrupt, WDT underflow or refresh
error, IWDT underflow or refresh error, voltage monitor 1 interrupt, voltage monitor 2 interrupt, or SRAM parity
error.
37.12.6
Location of Interrupt Vectors during Programming and Erasing
When an interrupt occurs during program and erase operations, the vector can be fetched from the code flash memory. To
avoid fetching the vector from the code flash memory, set the fetching destination to an area other than the code flash
memory with the interrupt table.
37.12.7
Programming and Erasing in Low-Speed Operating Mode
Do not program or erase the flash memory when low-speed operating mode is selected in the SOPCCR register for lowpower consumption functions.
37.12.8
Abnormal Termination during Programming and Erasing
When the voltage exceeds the range of the operating voltage during program or erase operation, or when a program or
erase operation did not complete successfully because of a reset or prohibited actions as described in section 37.12.9,
Actions Prohibited during Programming and Erasing, erase the area again.
37.12.9
Actions Prohibited during Programming and Erasing
To prevent damage to the flash memory, comply with the following constraints during programming and erasing:
Do not use an MCU power supply that is outside the operating voltage range
Do not update the OPCCR.OPCM[1:0] bit value
Do not update the SOPCCR.SOPCM bit value
Do not change the division ratio of the flash interface clock (ICLK)
Do not place the MCU in Software Standby mode
Do not access the data flash memory during a program or erase operation to the code flash memory
Do not update the DFLCTL.DFLEN bit value during a program or erase operation to the data flash memory.
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38.
38. AES Engine
AES Engine
Regarding the public release of this information, a non-disclosure agreement is required. For details, contact your
Renesas sales office.
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39.
39. True Random Number Generator (TRNG)
True Random Number Generator (TRNG)
Regarding the public release of this information, a non-disclosure agreement is required. For details, contact your
Renesas sales office.
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40. Internal Voltage Regulator
40.
Internal Voltage Regulator
40.1
Overview
The MCU includes a linear regulator (LDO) that supplies voltage to the internal circuits and memory, except for I/O and
the analog domain.
40.2
Operation
Table 40.1 lists the LDO mode pin settings. Figure 40.1 shows the LDO mode settings. The internal voltage is generated
from VCC.
Table 40.1
LDO mode pin settings
Pin
Settings
All VCC pins
Connect each pin to the system power supply
Connect each pin to VSS with a 0.1-μF multilayer ceramic capacitor. Place the capacitor
close to the pin.
VCL pin
Connect each pin to VSS with a 4.7-μF multilayer ceramic capacitor. Place the capacitor
close to the pin.
External power supply
VCL
VCC
0.1 µF
(each VCC
pin)
LDO
4.7 µF
VSS
VSS
Internal
logic and memory
Figure 40.1
LDO mode settings
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41.
41. Electrical Characteristics
Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC*1 = AVCC0 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5V, VREFH0 = 1.6 to AVCC0,
VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, Ta = Topr
Note 1. The typical condition is set to VCC = 3.3V.
Note 2. When USBFS is not used.
Figure 41.1 shows the timing conditions.
For example P100
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30pF
Figure 41.1
Input or output timing measurement conditions
The measurement conditions of timing specification in each peripherals are recommended for the best peripheral
operation. However, make sure to adjust driving abilities of each pins to meet your conditions.
Each function pin used for the same function must select the same drive ability. If I/O drive ability of each function is
mixed, the AC specification of the function is not guaranteed.
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41.1
41. Electrical Characteristics
Absolute Maximum Ratings
Table 41.1
Absolute maximum ratings
Parameter
Power supply voltage
Input voltage
5V-tolerant
ports*1
Symbol
Value
Unit
VCC
–0.5 to +6.5
V
Vin
–0.3 to +6.5
V
P000 to P004
P010 to P015
Vin
–0.3 to AVCC0 + 0.3
V
Others
Vin
–0.3 to VCC + 0.3
V
Reference power supply voltage
VREFH0
–0.3 to +6.5
V
Analog power supply voltage
AVCC0
–0.5 to +6.5
V
USB power supply voltage
VCC_USB
–0.5 to +6.5
V
VCC_USB_LDO
–0.5 to +6.5
V
VAN
–0.3 to AVCC0 + 0.3
V
–0.3 to VCC + 0.3
V
Analog input voltage
When AN000 to AN010 are
used
When AN016 to AN022 are
used
Operating temperature*2 *3
Topr
–40 to +85
–40 to +105
°C
Storage temperature
Tstg
–55 to +125
°C
Note:
See the Total Operating Time (TOT) Utility located at http://www.renesas.com. This utility is provided for
educational and evaluation purposes only and is subject to the accompanying disclaimer.
Note 1. Ports P205, P206, P400, P401, and P407 are 5V-tolerant.
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that
results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in
the device at this time might cause degradation of internal elements.
Note 2. See section 41.2.1, Tj/Ta Definition.
Note 3. The upper limit of the operating temperature is 85°C or 105°C, depending on the product. For details, see section
1, Part Numbering
Caution:
Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors of high frequency
characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the
VCC_USB and VSS_USB pins, and between the VREFH0 and VREFL0 pins. Place capacitors of about
0.1 μF as close as possible to every power supply pin and use the shortest and heaviest possible
traces. Also, connect capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin by a 4.7-µF capacitor. The capacitor must be placed close to the
pin.
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Table 41.2
41. Electrical Characteristics
Recommended operating conditions
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltages
VCC*1, *2
When USBFS is not
used
1.6
-
5.5
V
When USBFS is used VCC_USB
USB Regulator
Disable
-
3.6
V
When USBFS is used VCC_USB
_LDO
USB Regulator
Enable
-
5.5
V
-
0
-
V
-
VCC
-
V
When USBFS is used 3.0
USB Regulator
Disable
(Input)
3.3
3.6
V
When USBFS is not
used
VCC
-
V
When USBFS is used 3.8
USB Regulator
Enable
-
5.5
V
When USBFS is used USB Regulator
Disable
VCC
-
V
-
V
VSS
USB power supply voltages
VCC_USB
VCC_USB_LDO
When USBFS is not
used
VSS_USB
Analog power supply voltages
-
-
0
AVCC0*1, *2
1.6
-
5.5
V
AVSS0
-
0
-
V
1.6
-
AVCC0
V
-
0
-
V
VREFH0
VREFL0
When used as
ADC14 Reference
Note 1. Use AVCC0 and VCC under the following conditions:
AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 ≥ 2.2 V
AVCC0 = VCC when VCC < 2.2 V or AVCC0 < 2.2 V.
Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the
AVCC0 pin.
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41.2
41. Electrical Characteristics
DC Characteristics
41.2.1
Tj/Ta Definition
Table 41.3
DC characteristics
Conditions: Products with operating temperature (Ta) –40 to +105°C
Parameter
Symbol
Typ
Max
Unit
Test conditions
Permissible junction temperature
Tj
-
125
°C
High-speed mode
Middle-speed mode
Low-voltage mode
Low-speed mode
Subosc-speed mode
105*1
Note:
Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC – VOH) ×
ΣIOH + VOL × ΣIOL + ICCmax × VCC.
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section
1.3, Part Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of Tj
is 105°C, otherwise, it is 125°C.
41.2.2
Table 41.4
I/O VIH, VIL
I/O VIH, VIL (1)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
Schmitt trigger
input voltage
IIC (except for SMBus)*1
RES, NMI
Other peripheral input pins
excluding IIC
Input voltage
(except for
Schmitt trigger
input pin)
IIC
(SMBus)*2
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH
VCC × 0.7
-
5.8
V
-
VIL
-
-
VCC × 0.3
∆VT
VCC × 0.05
-
-
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
∆VT
VCC × 0.1
-
-
VIH
2.2
-
-
VCC = 3.6 to
5.5 V
VIH
2.0
-
-
VCC =2.7 to
3.6 V
-
VIL
-
-
0.8
5V-tolerant ports*3
VIH
VCC × 0.8
-
5.8
VIL
-
-
VCC × 0.2
P000 to P004
P010 to P015
VIH
AVCC0 × 0.8
-
-
VIL
-
-
AVCC0 × 0.2
EXTAL
Input ports pins except for
P000 to P004, P010 to P015
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
Note 1. SCL0_A, SDA0_A, SDA0_B, SCL1_A, SDA1_A (total 5 pins)
Note 2. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins)
Note 3. P205, P206, P400, P401, P407 (total 5pins)
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Table 41.5
41. Electrical Characteristics
I/O VIH, VIL (2)
Conditions: VCC = AVCC0 = 1.6 to 2.7 V
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH
VCC × 0.8
-
-
V
-
VIL
-
-
VCC × 0.2
∆VT
VCC × 0.01
-
-
VIH
VCC × 0.8
-
5.8
VIL
-
-
VCC × 0.2
P000 to P004
P010 to P015
VIH
AVCC0 × 0.8
-
-
VIL
-
-
AVCC0 × 0.2
EXTAL
Input ports pins except for
P000 to P004, P010 to P015
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
Parameter
Schmitt trigger
input voltage
Input voltage
(except for
Schmitt trigger
input pin)
RES, NMI
Peripheral input pins
5V-tolerant ports*1
Note 1. P205, P206, P400, P401, P407 (total 5pins)
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41.2.3
Table 41.6
41. Electrical Characteristics
I/O IOH, IOL
I/O IOH, IOL
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Permissible output current
(average value per pin)
Ports P000 to P004,
P010 to P015, P212, P213
Ports P408, P409
-
Low
drive*1
drive*2
Middle
VCC = 2.7 to 3.0 V
drive*2
Middle
VCC = 3.0 to 5.5 V
Other output
Permissible output current
(max value per pin)
pins*3
Min
Typ
Max
Unit
IOH
-
-
–4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
–4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
–8.0
mA
IOL
-
-
8.0
mA
IOH
-
-
–20.0
mA
IOL
-
-
20.0
mA
IOH
-
-
–4.0
mA
IOL
-
-
4.0
mA
Middle drive*2
IOH
-
-
–8.0
mA
IOL
-
-
8.0
mA
Ports P000 to P004,
P010 to P015, P212, P213
-
IOH
-
-
–4.0
mA
IOL
-
-
4.0
mA
Ports P408, P409
Low drive*1
IOH
-
-
–4.0
mA
IOL
-
-
4.0
mA
Middle drive*2
VCC = 2.7 to 3.0 V
IOH
-
-
–8.0
mA
IOL
-
-
8.0
mA
Middle drive*2
VCC = 3.0 to 5.5 V
IOH
-
-
–20.0
mA
IOL
-
-
20.0
mA
Low drive*1
IOH
-
-
–4.0
mA
IOL
-
-
4.0
mA
Middle drive*2
IOH
-
-
–8.0
mA
Other output pins*3
Permissible output current
(max value total pins)
Low
drive*1
Symbol
Total of ports P000 to P004, P010 to P015
Total of all output pin
IOL
-
-
8.0
mA
ΣIOH (max)
-
-
–30
mA
ΣIOL (max)
-
-
30
mA
ΣIOH (max)
-
-
–60
mA
ΣIOL (max)
-
-
60
mA
Caution:
To protect the reliability of the MCU, the output current values should not exceed the values in this
table. The average output current indicates the average value of current measured during 100 μs.
Note 1. This is the value when low driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the register.
Note 3. Except for Ports P200, P214, P215, which are input ports.
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41.2.4
41. Electrical Characteristics
I/O VOH, VOL, and Other Characteristics
Table 41.7
I/O VOH, VOL (1)
Conditions: VCC = AVCC0 = 4.0 to 5.5 V
Parameter
Output voltage
Symbol
Min
Typ
Max
Unit
Test conditions
VOL
-
-
0.4
V
IOL = 3.0 mA
VOL
-
-
0.6
IOL = 6.0 mA
VOH
VCC – 1.0
-
-
IOH = –20 mA
VOL
-
-
1.0
IOL = 20 mA
VOH
AVCC0 –
0.8
-
VOL
-
-
VOH
AVCC0 –
0.8
-
VOL
-
-
0.8
IOL = 4.0 mA
Low drive
VOH
VCC – 0.8
-
-
IOH = –2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
Middle
drive*5
VOH
VCC – 0.8
-
-
IOH = –4.0 mA
VOL
-
-
0.8
IOL = 4.0 mA
IIC*1, *2
Ports P408,
P409*2, *3
Ports P000 to P004
P010 to P015
Low drive
Middle drive
Other output
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
pins*4
IOH = –2.0 mA
0.8
IOL = 2.0 mA
IOH = –4.0 mA
SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins).
This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Based on characterization data, not tested in production.
Except for Ports P200, P214, and P215, which are input ports.
Except for P212, P213.
Table 41.8
I/O VOH, VOL (2)
Conditions: VCC = AVCC0 = 2.7 to 4.0 V
Parameter
Output voltage
Symbol
Min
Typ
Max
Unit
Test conditions
IIC*1, *2
VOL
-
-
0.4
V
IOL = 3.0 mA
VOL
-
-
0.6
IOL = 6.0 mA
Ports P408, P409*2, *3
VOH
VCC – 1.0
-
-
IOH = –20 mA
VCC = 3.3 V
VOL
-
-
1.0
IOL = 20 mA
VCC = 3.3 V
VOH
AVCC0 –
0.5
-
-
IOH = –1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
AVCC0 –
0.5
-
-
IOH = –2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
Ports P000 to P004
P010 to P015
Low drive
Middle drive
Other output
pins*4
Low drive
Middle
drive*5
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
VOH
VCC – 0.5
-
-
IOH = –1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
VCC – 0.5
-
-
IOH = –2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins).
This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Based on characterization data, not tested in production.
Except for Ports P200, P214, P215, which are input ports.
Except for P212, P213.
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Table 41.9
41. Electrical Characteristics
I/O VOH, VOL (3)
Conditions: VCC = AVCC0 = 1.6 to 2.7 V
Parameter
Output voltage
Ports P000 to P004
P010 to P015
Low drive
Middle drive
Other output pins*1
Symbol
Min
Typ
Max
VOH
AVCC0 –
0.3
-
-
Unit
Test conditions
IOH = –0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
VOH
AVCC0 –
0.3
-
-
IOH = –1.0 mA
VOL
-
-
0.3
Low drive
VOH
VCC – 0.3
-
-
IOL = 1.0 mA
VOL
-
-
0.3
IOL = 0.5 mA
Middle drive*2
VOH
VCC – 0.3
-
-
IOH = –1.0 mA
VOL
-
-
0.3
IOL = 1.0 mA
V
IOH = –0.5 mA
Note 1. Except for Ports P200, P214, P215, which are input ports.
Note 2. Except for P212, P213.
Table 41.10
I/O other characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current
RES, Ports P200, P214, P215
| Iin |
-
-
1.0
μA
Vin = 0 V
Vin = VCC
Three-state leakage
current (off state)
5V-tolerant ports
| ITSI |
-
-
1.0
μA
Vin = 0 V
Vin = 5.8 V
-
-
1.0
Other ports
Input pull-up resistor
Input capacitance
Vin = 0 V
Vin = VCC
All ports
(except for P200, P214, P215)
RU
10
20
50
kΩ
Vin = 0 V
USB_DP, USB_DM, P200
Cin
-
-
30
pF
-
-
15
Vin = 0 V
f = 1 MHz
Ta = 25°C
Other input pins
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41.2.5
41. Electrical Characteristics
I/O Pin Output Characteristics of Low Drive Capacity
IOH/IOL vs VOH/VOL
60
50
VCC = 5.5 V
40
30
VCC = 3.3 V
IOH/IOL [mA]
20
VCC = 2.7 V
10
VCC = 1.6 V
0
VCC = 1.6 V
-10
VCC = 2.7 V
-20
VCC = 3.3 V
-30
-40
-50
VCC = 5.5 V
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 41.2
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when low drive output is selected
(reference data)
IOH/IOL vs VOH/VOL
3
Ta = -40°C
Ta = 25°C
Ta = 105°C
2
IOH/IOL [mA]
1
0
-1
Ta = 105°C
Ta = 25°C
-2
Ta = -40°C
-3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 41.3
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected
(reference data)
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41. Electrical Characteristics
IOH/IOL vs VOH/VOL
20
15
Ta = -40°C
Ta = 25°C
Ta = 105°C
IOH/IOL [mA]
10
5
0
-5
Ta = 105°C
Ta = 25°C
-10
Ta = -40°C
-15
-20
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 41.4
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when low drive output is selected
(reference data)
IOH/IOL vs VOH/VOL
30
Ta = -40°C
Ta = 25°C
Ta = 105°C
20
IOH/IOL [mA]
10
0
-10
Ta = 105°C
Ta = 25°C
-20
Ta = -40°C
-30
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 41.5
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when low drive output is selected
(reference data)
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41. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
Ta = -40°C
Ta = 25°C
Ta = 105°C
40
IOH/IOL [mA]
20
0
-20
Ta = 105°C
-40
Ta = 25°C
Ta = -40°C
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 41.6
41.2.6
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected
(reference data)
I/O Pin Output Characteristics of Middle Drive Capacity
IOH/IOL [mA]
IOH/IOL vs VOH/VOL
140
120
100
80
60
40
20
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 1.6 V
0
-20
-40
-60
-80
-100
-120
-140
VCC = 1.6 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 41.7
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
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Page 994 of 1104
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41. Electrical Characteristics
IOH/IOL vs VOH/VOL
6
Ta = -40°C
Ta = 25°C
Ta = 105°C
4
IOH/IOL [mA]
2
0
-2
Ta = 105°C
-4
Ta = 25°C
Ta = -40°C
-6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 41.8
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when middle drive output is
selected (reference data)
IOH/IOL vs VOH/VOL
40
Ta = -40°C
Ta = 25°C
Ta = 105°C
30
IOH/IOL [mA]
20
10
0
-10
-20
Ta = 105°C
Ta = 25°C
-30
Ta = -40°C
-40
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 41.9
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
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S124 User’s Manual
41. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
Ta = -40°C
Ta = 25°C
40
Ta = 105°C
IOH/IOL [mA]
20
0
-20
Ta = 105°C
-40
Ta = 25°C
Ta = -40°C
-60
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 41.10
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
IOH/IOL [mA]
IOH/IOL vs VOH/VOL
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
Ta = -40°C
Ta = 25°C
Ta = 105°C
Ta = 105°C
Ta = 25°C
Ta = -40°C
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 41.11
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
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Feb 5, 2018
Page 996 of 1104
S124 User’s Manual
41.2.7
41. Electrical Characteristics
P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity
IOH/IOL [mA]
IOH/IOL vs VOH/VOL
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 41.12
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
IOH/IOL vs VOH/VOL
60
Ta = -40°C
Ta = 25°C
Ta = 105°C
40
IOH/IOL [mA]
20
0
-20
Ta = 105°C
-40
Ta = 25°C
Ta = -40°C
-60
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 41.13
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
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41. Electrical Characteristics
IOH/IOL vs VOH/VOL
100
Ta = -40°C
Ta = 25°C
Ta = 105°C
80
60
40
IOH/IOL [mA]
20
0
-20
-40
Ta = 105°C
-60
Ta = 25°C
-80
Ta = -40°C
-100
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 41.14
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
IOH/IOL vs VOH/VOL
220
Ta = -40°C
Ta = 25°C
Ta = 105°C
180
140
IOH/IOL [mA]
100
60
20
-20
-60
-100
-140
Ta = 105°C
Ta = 25°C
-180
Ta = -40°C
-220
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 41.15
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
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Feb 5, 2018
Page 998 of 1104
S124 User’s Manual
41.2.8
41. Electrical Characteristics
IIC I/O Pin Output Characteristics
IOL vs VOL
120
110
VCC = 5.5 V (Middle drive)
100
90
IOL [mA]
80
70
60
50
VCC = 3.3V (Middle drive)
VCC = 5.5V (Low drive)
40
VCC = 2.7V (Middle drive)
30
VCC = 3.3V (Low drive)
20
10
VCC = 2.7V (Low drive)
0
0
1
2
3
4
5
6
VOL [V]
Figure 41.16
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C
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Feb 5, 2018
Page 999 of 1104
S124 User’s Manual
41.2.9
41. Electrical Characteristics
Operating and Standby Current
Table 41.11
Operating and standby current (1) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
High-speed
mode*2
Normal mode
All peripheral clock
disabled, while (1) code
executing from flash*5
All peripheral clock
disabled, CoreMark code
executing from flash*5
All peripheral clock
enabled, while (1) code
executing from flash*5
Sleep mode
ICLK = 32 MHz
Symbol
Typ*9
Max
Unit
Test
Conditions
ICC
3.6
-
mA
*7
ICLK = 16 MHz
2.4
-
ICLK = 8 MHz
1.7
-
ICLK = 32 MHz
5.6
-
ICLK = 16 MHz
3.5
-
ICLK = 8 MHz
2.4
-
ICLK = 32 MHz
9.5
-
ICLK = 16 MHz
5.4
-
ICLK = 8 MHz
3.3
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 32 MHz
-
21.0
All peripheral clock
disabled*5
ICLK = 32 MHz
1.5
-
ICLK = 16 MHz
1.1
-
ICLK = 8 MHz
0.9
-
ICLK = 32 MHz
7.2
-
All peripheral clock
enabled*5
ICLK = 16 MHz
4.0
-
ICLK = 8 MHz
2.4
-
Increase during BGO operation*6
Middle-speed
mode*2
Normal mode
Sleep mode
2.5
-
1.7
-
ICLK = 8 MHz
1.5
-
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 12 MHz
2.7
-
ICLK = 8 MHz
1.9
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 12 MHz
3.9
-
ICLK = 8 MHz
3.0
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 12 MHz
-
8.0
All peripheral clock
disabled*5
ICLK = 12 MHz
0.8
-
ICLK = 8 MHz
0.8
-
All peripheral clock
enabled*5
ICLK = 12 MHz
2.9
-
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 12 MHz
ICC
ICLK = 8 MHz
Increase during BGO operation*6
Low-speed
mode*3
Normal mode
Sleep mode
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
ICC
2.2
-
2.5
-
0.2
-
*8
*7
*8
mA
*7
*8
*7
*8
mA
*7
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 1 MHz
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 1 MHz
0.3
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 1 MHz
0.4
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 1 MHz
-
2.0
All peripheral clock
disabled*5
ICLK = 1 MHz
0.2
-
*7
All peripheral clock
enabled*5
ICLK = 1 MHz
0.3
-
*8
*8
Page 1000 of 1104
S124 User’s Manual
Table 41.11
41. Electrical Characteristics
Operating and standby current (1) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
Low-voltage
mode*3
Normal mode
Sleep mode
Suboscspeed
mode*4
Normal mode
Sleep mode
Symbol
Typ*9
Max
Unit
Test
Conditions
ICC
1.4
-
mA
*7
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 4 MHz
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 4 MHz
1.4
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 4 MHz
2.1
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 4 MHz
-
4.0
All peripheral clock
disabled*5
ICLK = 4 MHz
0.9
-
*7
All peripheral clock
enabled*5
ICLK = 4 MHz
1.6
-
*8
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
5.9
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
13.0
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 32.768 kHz
-
55.0
All peripheral clock
disabled*5
ICLK = 32.768 kHz
3.2
-
*7
All peripheral clock
enabled*5
ICLK = 32.768 kHz
10.0
-
*8
ICC
*8
μA
*7
*8
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when
internal pull-up MOSs are in the off state.
Note 2. The clock source is HOCO.
Note 3. The clock source is MOCO.
Note 4. The clock source is the sub-clock oscillator.
Note 5. This does not include BGO operation.
Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 7. PCLKB and PCLKD are set to divided by 64.
Note 8. PCLKB and PCLKD are the same frequency as that of ICLK.
Note 9. VCC = 3.3 V.
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Feb 5, 2018
Page 1001 of 1104
S124 User’s Manual
41. Electrical Characteristics
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
Figure 41.17
Voltage dependency in high-speed operating mode (reference data)
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
Figure 41.18
Voltage dependency in middle-speed operating mode (reference data)
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1002 of 1104
S124 User’s Manual
41. Electrical Characteristics
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
Figure 41.19
Voltage dependency in low-speed operating mode (reference data)
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
Figure 41.20
Voltage dependency in low-voltage operating mode (reference data)
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1003 of 1104
S124 User’s Manual
41. Electrical Characteristics
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
Note 3. MOCO and DAC are stopped.
Figure 41.21
Table 41.12
Voltage dependency in subosc-speed operating mode (reference data)
Operating and standby current (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
Software Standby
mode*2
Ta = 25°C
Symbol
Typ*3
Max
Unit
Test conditions
ICC
μA
-
0.4
1.5
Ta = 55°C
0.6
5.5
Ta = 85°C
1.2
10.0
Ta = 105°C
2.6
40.0
Increment for RTC operation with
low-speed on-chip oscillator*4
0.4
-
-
Increment for RTC operation with
sub-clock oscillator*4
0.5
-
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
1.3
-
SOMCR.SODRV[1:0] are 00b
(normal mode)
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when
internal pull-up MOS transistors are in the off state.
Note 2. The IWDT and LVD are not operating.
Note 3. VCC = 3.3 V.
Note 4. Includes the current of low-speed on-chip oscillator or sub-oscillation circuit.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1004 of 1104
S124 User’s Manual
41. Electrical Characteristics
Figure 41.22
Temperature dependency in Software Standby mode (reference data)
Figure 41.23
Temperature dependency of RTC operation (reference data)
Table 41.13
Operating and standby current (3) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Symbol Min
Typ
Max
Unit
Test
conditions
IAVCC
-
-
3.0
mA
-
During A/D conversion (at low-power conversion)
-
-
1.0
mA
-
During D/A conversion*1
-
0.4
0.8
mA
-
-
-
1.0
μA
-
-
-
150
μA
-
-
-
60
nA
-
-
75
-
μA
-
Parameter
Analog power
supply current
During A/D conversion (at high-speed conversion)
Waiting for A/D and D/A conversion (all
Reference
power supply
current
During A/D conversion
units)*5
IREFH0
Waiting for A/D conversion (all units)
Temperature sensor
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
ITNS
Page 1005 of 1104
S124 User’s Manual
Table 41.13
41. Electrical Characteristics
Operating and standby current (3) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Low-power
analog
comparator
(ACMPLP)
operating
current
USB operating
current
Symbol Min
Typ
Max
Unit
Test
conditions
-
15
-
μA
-
Comparator high-speed mode
-
10
-
μA
-
Comparator low-speed mode
-
2
-
μA
-
Window mode
ICMPLP
During USB communication under the following
settings and conditions:
Function controller is in Full-Speed mode and
- Bulk OUT transfer is (64 bytes) × 1
- Bulk IN transfer is (64 bytes) × 1
Host device is connected by a 1-meter USB cable
from the USB port.
IUSBF*2
-
3.6 (VCC)
1.1 (VCC_USB)*4
-
mA
-
During suspended state under the following setting
and conditions:
Function controller is in Full-Speed mode (the
USB_DP pin is pulled up)
Software Standby mode
Host device is connected by a 1-meter USB cable
from the USB port.
ISUSP*3
-
0.35 (VCC)
170 (VCC_USB)*4
-
μA
-
Note 1. The reference power supply current is included in the power supply current value for D/A conversion.
Note 2. Current is consumed only by the USBFS.
Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host
device, in addition to the current consumed by the MCU in the suspended state.
Note 4. When VCC = VCC_USB = 3.3 V.
Note 5. When the MSTPCRD.MSTPD16 (ADC140 module-stop bit) is in the module-stop state.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1006 of 1104
S124 User’s Manual
41.2.10
41. Electrical Characteristics
VCC Rise and Fall Gradient and Ripple Frequency
Table 41.14
Rise and fall gradient characteristics
Conditions: VCC = AVCC0 = 0 to 5.5 V
Parameter
Power-on VCC
rising gradient
Voltage monitor 0 reset disabled at startup
Symbol Min
Typ
Max
Unit
Test conditions
SrVCC
0.02
-
2
ms/V
-
0.02
-
-
0.02
-
2
Voltage monitor 0 reset enabled at startup*1, *2
SCI Boot
mode*2
Note 1. When OFS1.LVDAS = 0.
Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Table 41.15
Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit
(1.6 V).
When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Allowable ripple frequency
fr (VCC)
-
-
10
-
-
1
-
-
10
1.0
-
-
Allowable voltage change rising and
falling gradient
dt/dVCC
Unit
Test conditions
kHz
Figure 41.24
Vr (VCC) ≤ VCC × 0.2
MHz
Figure 41.24
Vr (VCC) ≤ VCC × 0.08
MHz
Figure 41.24
Vr (VCC) ≤ VCC × 0.06
ms/V
When VCC change exceeds VCC ±10%
1/fr(VCC)
VCC
Figure 41.24
Vr(VCC)
Ripple waveform
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Feb 5, 2018
Page 1007 of 1104
S124 User’s Manual
41.3
41. Electrical Characteristics
AC Characteristics
41.3.1
Table 41.16
Frequency
Operation frequency in high-speed operating mode
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Symbol
Min
Typ
Max*5
Unit
f
0.032768
-
32
MHz
2.4 to 2.7 V
0.032768
-
16
2.7 to 5.5 V
-
-
32
2.4 to 2.7 V
-
-
16
2.7 to 5.5 V
-
-
64
2.4 to 2.7 V
-
-
16
Parameter
Operation
frequency
System clock (ICLK)*1, *2, *4
Peripheral module clock
Peripheral module clock
(PCLKB)*4
(PCLKD)*3, *4
2.7 to 5.5 V
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 41.21, Clock timing.
Table 41.17
Operation frequency in middle-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
Symbol
System clock
(ICLK)*1, *2, *4
Peripheral module clock
(PCLKB)*4
Peripheral module clock (PCLKD)*3, *4
2.7 to 5.5 V
f
Min
Typ
Max*5
Unit
MHz
0.032768
-
12
2.4 to 2.7 V
0.032768
-
12
1.8 to 2.4 V
0.032768
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 41.21, Clock timing.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1008 of 1104
S124 User’s Manual
Table 41.18
41. Electrical Characteristics
Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
Symbol
Min
Typ
Max*5
Unit
f
0.032768
-
1
MHz
System clock (ICLK)*1, *2, *4
1.8 to 5.5 V
Peripheral module clock (PCLKB)*4
1.8 to 5.5 V
-
-
1
Peripheral module clock (PCLKD)*3, *4
1.8 to 5.5 V
-
-
1
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Note 4. See section 8, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 41.21, Clock timing.
Table 41.19
Operation frequency in low-voltage mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Operation
frequency
Symbol
Min
Typ
Max*5
Unit
f
0.032768
-
4
MHz
System clock (ICLK)*1, *2, *4
1.6 to 5.5 V
Peripheral module clock (PCLKB)*4
1.6 to 5.5 V
-
-
4
Peripheral module clock (PCLKD)*3, *4
1.6 to 5.5 V
-
-
4
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 41.21, Clock timing.
Table 41.20
Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
Symbol
System clock
(ICLK)*1, *3
1.8 to 5.5 V
f
Min
Typ
Max
Unit
kHz
27.8528
32.768
37.6832
Peripheral module clock (PCLKB)*3
1.8 to 5.5 V
-
-
37.6832
Peripheral module clock (PCLKD)*2, *3
1.8 to 5.5 V
-
-
37.6832
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The 14-bit A/D converter cannot be used.
Note 3. See section 8, Clock Generation Circuit for the relationship between ICLK, PCLKB, and PCLKD frequencies.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1009 of 1104
S124 User’s Manual
41.3.2
Table 41.21
41. Electrical Characteristics
Clock Timing
Clock timing (1 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
EXTAL external clock input cycle time
tXcyc
50
-
-
ns
Figure 41.25
EXTAL external clock input high pulse width
tXH
20
-
-
ns
EXTAL external clock input low pulse width
tXL
20
-
-
ns
EXTAL external clock rising time
tXr
-
-
5
ns
EXTAL external clock falling time
tXf
-
-
5
ns
tEXWT
0.3
-
-
μs
-
fEXTAL
-
-
20
MHz
2.4 ≤ VCC ≤ 5.5
EXTAL external clock input wait
time*1
EXTAL external clock input frequency
Main clock oscillator oscillation frequency
fMAIN
-
-
8
1.8 ≤ VCC < 2.4
-
-
1
1.6 ≤ VCC < 1.8
1
-
20
1
-
8
1
-
4
LOCO clock oscillation frequency
fLOCO
27.8528
32.768
37.6832
LOCO clock oscillation stabilization time
tLOCO
-
-
IWDT-dedicated clock oscillation frequency
fILOCO
12.75
15
MOCO clock oscillation frequency
fMOCO
6.8
8
MOCO clock oscillation stabilization time
tMOCO
-
-
HOCO clock oscillation frequency
fHOCO24
23.64
Sub-clock oscillator oscillation frequency
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
1.6 ≤ VCC < 1.8
100
μs
Figure 41.26
17.25
kHz
-
9.2
MHz
-
1
μs
-
24
24.36
MHz
Ta = –40 to –20°C
1.8 ≤ VCC ≤ 5.5
22.68
24
25.32
Ta = –40 to 85°C
1.6 ≤ VCC < 1.8
23.76
24
24.24
Ta = –20 to 85°C
1.8 ≤ VCC ≤ 5.5
23.52
24
24.48
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
31.52
32
32.48
Ta = –40 to –20°C
1.8 ≤ VCC ≤ 5.5
30.24
32
33.76
Ta = –40 to 85°C
1.6 ≤ VCC < 1.8
31.68
32
32.32
Ta = –20 to 85°C
1.8 ≤ VCC ≤ 5.5
31.36
32
32.64
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
47.28
48
48.72
Ta = –40 to –20°C
1.8 ≤ VCC ≤ 5.5
47.52
48
48.48
Ta = –20 to 85°C
1.8 ≤ VCC ≤ 5.5
47.04
48
48.96
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
63.04
64
64.96
Ta = –40 to –20°C
2.4 ≤ VCC ≤ 5.5
63.36
64
64.64
Ta = –20 to 85°C
2.4 ≤ VCC ≤ 5.5
62.72
64
65.28
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
tHOCO24
tHOCO32
-
-
37.1
tHOCO48
-
-
43.3
tHOCO64
-
-
80.6
tHOCO24
tHOCO32
tHOCO48
tHOCO64
-
-
100.9
fSUB
-
32.768
-
fHOCO64*4
Low-voltage
mode
1.8 ≤ VCC < 2.4
-
fHOCO48*3
Except lowvoltage mode
2.4 ≤ VCC ≤ 5.5
kHz
fHOCO32
HOCO clock oscillation
stabilization time*5, *6
MHz
μs
Figure 41.27
kHz
-
Page 1010 of 1104
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Table 41.21
41. Electrical Characteristics
Clock timing (2 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Sub-clock oscillation stabilization time*2
tSUBOSC
-
0.5
-
s
Figure 41.28
Note 1. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating)
when the external clock is stable.
Note 2. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the
sub-clock oscillator after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time
value recommended by the oscillator manufacturer.
Note 3. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V.
Note 4. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V.
Note 5. This is a characteristic when the HOCOCR.HCSTP bit is cleared to 0 (oscillation) in the MOCO stop state.
When the HOCOCR.HCSTP bit is cleared to 0 (oscillation) during MOCO oscillation, this specification is
shortened by 1 μs.
Note 6. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
tXcyc
tXH
tXL
EXTAL external clock input
VCC × 0.5
tXr
Figure 41.25
tXf
EXTAL external clock input timing
LOCOCR.LCSTP
tLOCO
LOCO clock oscillator output
Figure 41.26
LOCO clock oscillation start timing
HOCOCR.HCSTP
tHOCOx*1
HOCO clock
Note 1.
Figure 41.27
x = 24, 32, 48, 64
HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
Figure 41.28
Sub-clock oscillation start timing
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41.3.3
Table 41.22
41. Electrical Characteristics
Reset Timing
Reset timing
Symbol
Min
Typ
Max
Unit
Test
conditions
At power-on
tRESWP
3
-
-
ms
Figure 41.29
Not at power-on
tRESW
30
-
-
μs
Figure 41.30
tRESWT
-
0.7
-
ms
Figure 41.29
-
0.3
-
-
0.5
-
ms
Figure 41.30
-
0.05
-
-
0.6
-
-
0.15
-
Parameter
RES pulse width
Wait time after RES cancellation
(at power-on)
LVD0
enabled*1
LVD0 disabled*2
LVD0 enabled*1
Wait time after RES cancellation
(during powered-on state)
LVD0
Internal reset cancellation time (Watchdog
timer reset, SRAM parity error reset,
Software reset)
tRESWT2
disabled*2
LVD0 enabled*1
tRESWT3
LVD0 disabled*2
ms
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
VCC
RES
tRESWP
Internal reset
tRESWT
Figure 41.29
Reset input timing at power-on
tRESW
RES
Internal reset
tRESWT2
Figure 41.30
Reset input timing (1)
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41.3.4
41. Electrical Characteristics
Wakeup Time
Table 41.23
Timing of recovery from low power modes (1)
Parameter
Recovery time
from Software
Standby mode*1
High-speed
mode
Symbol Min
Typ
Max
Unit
Test
conditions
Figure 41.31
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(20 MHz)*2
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(20 MHz)*3
tSBYEX
-
14
25
μs
System clock source is HOCO*4
(HOCO clock is 32 MHz)
tSBYHO
-
43
52
μs
System clock source is HOCO*4
(HOCO clock is 48 MHz)
tSBYHO
-
44
52
μs
System clock source is HOCO*5
(HOCO clock is 64 MHz)
tSBYHO
-
82
110
μs
System clock source is MOCO
tSBYMO
-
16
25
μs
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 4. The HOCO clock wait control register (HOCOWTCR) is set to 05h.
Note 5. The HOCO clock wait control register (HOCOWTCR) is set to 06h.
Table 41.24
Timing of recovery from low power modes (2)
Parameter
Recovery time
from Software
Standby mode*1
Middle-speed
mode
Symbol
Min
Typ
Max
Unit
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(12 MHz)*2
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(12 MHz)*3
tSBYEX
-
2.9
10
μs
System clock source is HOCO*4
tSBYHO
-
38
50
μs
System clock source is MOCO
tSBYMO
-
3.5
5.5
μs
Test
conditions
Figure 41.31
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 4. The system clock is 12 MHz.
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Table 41.25
41. Electrical Characteristics
Timing of recovery from low power modes (3)
Parameter
Recovery time
from Software
Standby mode*1
Low-speed
mode
Symbol
Min
Typ
Max
Unit
Test
conditions
Figure 41.31
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(1 MHz)*2
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(1 MHz)*3
tSBYEX
-
28
50
μs
tSBYMO
-
25
35
μs
System clock source is MOCO
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 41.26
Timing of recovery from low power modes (4)
Parameter
Recovery time
from Software
Standby mode*1
Low-voltage
mode
Crystal
resonator
connected to
main clock
oscillator
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
Symbol
Min
Typ
Max
Unit
Test
conditions
tSBYMC
-
2
3
ms
Figure 41.31
tSBYEX
-
108
130
μs
tSBYHO
-
108
130
μs
(4 MHz)*2
System clock source is
main clock oscillator
(4 MHz)*3
System clock source is HOCO
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 41.27
Timing of recovery from low power modes (5)
Symbol
Min
Typ
Max
Unit
Test
conditions
System clock source is sub-clock
oscillator (32.768 kHz)
tSBYSC
-
0.85
1
ms
Figure 41.31
System clock source is LOCO
(32.768 kHz)
tSBYLO
-
0.85
1.2
ms
Parameter
Recovery time
from Software
Standby mode*1
SubOSC-speed mode
Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed
mode.
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41. Electrical Characteristics
Oscillator
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX,
tSBYMO, tSBYHO
Oscillator
ICLK
IRQ
Software Standby mode
tSBYSC, tSBYLO
Figure 41.31
Software Standby mode cancellation timing
Table 41.28
Timing of recovery from low power modes (6)
Parameter
Recovery time from
Software Standby
mode to Snooze
mode
Symbol
Min
Typ
Max
Unit
Test conditions
High-speed mode
System clock source is HOCO
tSNZ
-
36
45
μs
Figure 41.32
Middle-speed mode
System clock source is MOCO
tSNZ
-
1.3
3.6
μs
Low-speed mode
System clock source is MOCO
tSNZ
-
10
13
μs
Low-voltage mode
System clock source is HOCO
tSNZ
-
87
110
μs
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1 PCLK
IRQ
Software Standby mode
Snooze mode
tSNZ
Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.
Figure 41.32
Recovery timing from Software Standby mode to Snooze mode
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41.3.5
41. Electrical Characteristics
NMI and IRQ Noise Filter
Table 41.29
NMI and IRQ noise filter
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
NMI pulse width
tNMIW
200
-
-
ns
NMI digital filter disabled
tPcyc × 2 ≤ 200 ns
-
-
200
-
-
NMI digital filter enabled
tNMICK × 3 ≤ 200 ns
tNMICK × 3.5*2
-
-
200
-
-
tPcyc × 2*1
-
-
200
-
-
-
-
tPcyc ×
IRQ pulse width
tIRQW
2*1
tIRQCK ×
3.5*3
tPcyc × 2 > 200 ns
tNMICK × 3 > 200 ns
ns
IRQ digital filter disabled
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
IRQ digital filter enabled
tIRQCK × 3 ≤ 200 ns
tIRQCK × 3 > 200 ns
Note:
200 ns minimum in Software Standby mode.
Note 1. tPcyc indicates the PCLKB cycle.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
NMI
tNMIW
Figure 41.33
NMI interrupt input timing
IRQ
tIRQW
Figure 41.34
IRQ interrupt input timing
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41.3.6
41. Electrical Characteristics
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing
Table 41.30
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing
Parameter
Symbol Min
Max
Unit
Test
conditions
I/O Ports
Input data pulse width
tPRW
1.5
-
tPcyc
Figure 41.35
POEG
POEG input trigger pulse width
tPOEW
3
-
tPcyc
Figure 41.36
GPT
Input capture pulse width
tGTICW
1.5
-
tPDcyc
Figure 41.37
2.5
-
250
-
ns
Figure 41.38
2.4 V ≤ VCC < 2.7 V
500
-
ns
1.8 V ≤ VCC < 2.4 V
1000
-
ns
1.6 V ≤ VCC < 1.8 V
2000
-
ns
Single edge
Dual edge
AGT
AGTIO, AGTEE input cycle
AGTIO, AGTEE input high level
width, low-level width
2.7 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
tACYC*1
tACKWH,
tACKWL
100
-
ns
200
-
ns
400
-
ns
800
-
ns
62.5
-
ns
2.4 V ≤ VCC < 2.7 V
125
-
ns
1.8 V ≤ VCC < 2.4 V
250
-
ns
1.6 V ≤ VCC < 1.8 V
500
-
ns
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTO, AGTOA, AGTOB
output cycle
2.7 V ≤ VCC ≤ 5.5 V
tACYC2
Figure 41.38
ADC14
14-bit A/D converter trigger input pulse width
tTRGW
1.5
-
tPcyc
Figure 41.39
KINT
KRn (n = 00 to 07) pulse width
tKR
250
-
ns
Figure 41.40
Note:
tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.
Note 1. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.
Port
tPRW
Figure 41.35
I/O ports input timing
POEG input trigger
tPOEW
Figure 41.36
POEG input trigger timing
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41. Electrical Characteristics
Input capture
tGTICW
Figure 41.37
GPT input capture timing
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 41.38
AGT I/O timing
ADTRG0
tTRGW
Figure 41.39
ADC14 trigger input timing
KR00 to KR07
tKR
Figure 41.40
41.3.7
Key interrupt input timing
CAC Timing
Table 41.31
CAC timing
Parameter
CAC
CACREF input pulse width
tPBcyc ≤ tcac*2
tPBcyc >
tcac*2
Symbol
Min
Typ
Max
Unit
Test
conditions
tCACREF
4.5 × tcac + 3 × tPBcyc
-
-
ns
-
5 × tcac + 6.5 × tPBcyc
-
-
ns
Note 1. tPBcyc: PCLKB cycle.
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41. Electrical Characteristics
Note 2. tcac: CAC count clock source cycle.
41.3.8
SCI Timing
Table 41.32
SCI timing (1)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
SCI
Input clock cycle
Asynchronous
Symbol
Min
Max
Unit*1
Test conditions
tScyc
4
-
tPcyc
Figure 41.41
6
-
Input clock pulse width
Clock synchronous
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
-
20
ns
Input clock fall time
tSCKf
-
20
ns
6
-
tPcyc
4
-
Output clock cycle
Asynchronous
tScyc
Clock synchronous
Output clock pulse width
tSCKW
0.4
0.6
tScyc
tSCKr
-
20
ns
-
30
tSCKf
-
20
-
30
tTXD
-
40
1.6V or above
-
45
2.7V or above
-
55
2.4V or above
-
60
1.8V or above
-
100
Output clock rise time
1.8V or above
Output clock fall time
1.8V or above
1.6V or above
1.6V or above
Transmit data delay
(master)
Clock
synchro
nous
Transmit data delay
(slave)
Clock
synchro
nous
1.8V or above
1.6V or above
Receive data setup
time (master)
Clock
synchro
nous
2.7V or above
tRXS
-
125
45
-
2.4V or above
55
-
1.8V or above
90
-
1.6V or above
110
-
2.7V or above
40
-
1.6V or above
45
-
ns
ns
Figure 41.42
ns
ns
Receive data setup
time (slave)
Clock
synchro
nous
ns
Receive data hold
time (master)
Clock synchronous
tRXH
5
-
ns
Receive data hold
time (slave)
Clock synchronous
tRXH
40
-
ns
Note 1. tPcyc: PCLKB cycle.
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41. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 0, 1, 9)
tScyc
Figure 41.41
SCK clock input timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
n = 0, 1, 9
Figure 41.42
SCI input/output timing in clock synchronous mode
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Page 1020 of 1104
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Table 41.33
41. Electrical Characteristics
SCI timing (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
Max
Unit*1
Test conditions
Simple
SPI
tSPcyc
4
65536
tPcyc
Figure 41.43
6
65536
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
tSPCKr,
tSPCKf
-
20
ns
-
30
tSU
45
-
2.4V or above
55
-
1.8V or above
80
-
1.6V or above
110
-
2.7V or above
40
-
1.6V or above
45
-
33.3
-
40
-
SCK clock rise and fall time
1.8V or above
1.6V or above
Data input setup
time
Master
Slave
Data input hold time
2.7V or above
Master
tH
Slave
tLEAD
1
-
tSPcyc
SS input hold time
tLAG
1
-
tSPcyc
tOD
-
40
ns
Data output hold
time
Master
1.8V or above
1.6V or above
-
50
Slave
2.4V or above
-
65
1.8V or above
-
100
1.6V or above
-
125
–10
-
2.4V or above
–20
-
1.8V or above
–30
-
1.6V or above
–40
-
–10
-
-
20
1.6V or above
-
30
1.8V or above
-
20
1.6V or above
-
30
Master
2.7V or above
tOH
Slave
Data rise and fall
time
Master
Slave
1.8V or above
tDr, tDf
Figure 41.44 to
Figure 41.47
ns
SS input setup time
Data output delay
Simple
SPI
ns
ns
ns
Slave access time
tSA
-
6
tPcyc
Slave output release time
tREL
-
6
tPcyc
Figure 41.47
Note 1. tPcyc: PCLKB cycle
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41. Electrical Characteristics
tSPCKr
tSPCKWH
VOH
SCKn
master select
output
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
SCKn
slave select input
VIL
(n = 0, 1, 9)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 41.43
SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tDr, tDf
MOSIn
output
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 0, 1, 9)
Figure 41.44
SCI simple SPI mode timing (master, CKPH = 1)
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41. Electrical Characteristics
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
MISOn
input
tH
MSB IN
tOH
DATA
LSB IN
tOD
MOSIn
output
MSB IN
tDr, tDf
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
(n = 0, 1, 9)
Figure 41.45
SCI simple SPI mode timing (master, CKPH = 0)
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
MISOn
output
MSB OUT
tSU
MOSIn
input
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB IN
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 0, 1, 9)
Figure 41.46
SCI simple SPI mode timing (slave, CKPH = 1)
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41. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOn
output
MSB OUT
tSU
MOSIn
input
tREL
LSB OUT
DATA
tH
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 0, 1, 9)
Figure 41.47
Table 41.34
SCI simple SPI mode timing (slave, CKPH = 0)
SCI timing (3)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
Simple IIC
(Standard mode)
IIC*2
Simple
(Fast mode)
Symbol
Min
Max
Unit
Test conditions
SDA input rise time
tSr
-
1000
ns
Figure 41.48
SDA input fall time
tSf
-
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
250
-
ns
Data input hold time
tSDAH
0
-
ns
-
400
pF
SCL, SDA capacitive load
Cb
SDA input rise time
tSr
-
300
ns
SDA input fall time
tSf
-
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
100
-
ns
Data input hold time
tSDAH
0
-
ns
-
400
pF
SCL, SDA capacitive load
Note:
*1
Cb
*1
Figure 41.48
tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.
Note 1. Cb indicates the total capacity of the bus line.
Note 2. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
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Page 1024 of 1104
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41. Electrical Characteristics
VIH
SDAn
VIL
tSr
tSf
tSP
SCLn
P*1
(n = 0,1,9)
tSDAH
Note 1. S, P, and Sr indicate the following:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 41.48
P*1
Sr*1
S*1
tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
SCI simple IIC mode timing
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Page 1025 of 1104
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41.3.9
41. Electrical Characteristics
SPI Timing
Table 41.35
SPI timing (1 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Symbol
Min
Max
Unit*1
Test conditions
tSPcyc
2
4096
tPcyc
6
4096
Figure 41.49
C = 30PF
(tSPcyc –
tSPCKr
– tSPCKf) / 2
–3
-
3 × tPcyc
-
(tSPcyc –
tSPCKr
– tSPCKf) / 2
–3
-
3 × tPcyc
-
-
10
-
15
1.8V or above
-
20
1.6V or above
-
30
-
1
µs
10
-
ns
2.4V or above
10
-
1.8V or above
15
-
Parameter
SPI
RSPCK clock cycle
Master
Slave
RSPCK clock high
pulse width
Master
tSPCKWH
Slave
RSPCK clock low
pulse width
Master
tSPCKWL
Slave
RSPCK clock rise
and fall time
Output
2.7V or above
2.4V or above
tSPCKr,
tSPCKf
Input
Data input setup
time
Master
Slave
tSU
1.6V or above
ns
ns
ns
20
-
Master
(RSPCK is PCLKB/2)
tHF
0
-
Master
(RSPCK is not PCLKB/2)
tH
tPcyc
-
Slave
tH
20
-
SSL setup time
Master
tLEAD
– 30 + N x
tSpcyc*2
-
ns
6 x tPcyc
-
ns
SSL hold time
Master
– 30 + N x
tSpcyc*3
-
ns
6 x tPcyc
-
ns
Data input hold time
Slave
Slave
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
tLAG
Figure 41.50 to
Figure 41.55
C = 30PF
ns
Page 1026 of 1104
S124 User’s Manual
Table 41.35
41. Electrical Characteristics
SPI timing (2 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
SPI
Data output delay
Master
Slave
2.7V or above
Symbol
Min
Max
Unit*1
Test conditions
tOD
-
14
ns
Figure 41.50 to
Figure 41.55
C = 30PF
2.4V or above
-
20
1.8V or above
-
25
1.6V or above
-
30
2.7V or above
-
50
2.4V or above
-
60
1.8V or above
-
85
-
110
0
-
0
-
tSPcyc + 2 ×
tPcyc
8 × tSPcyc
+ 2 × tPcyc
6 × tPcyc
-
-
10
2.4V or above
-
15
1.8V or above
-
20
1.6V or above
-
30
-
1
µs
ns
1.6V or above
Data output hold
time
Master
Successive
transmission delay
Master
MOSI and MISO
rise and fall time
Output
tOH
Slave
tTD
Slave
2.7V or above
tDr, tDf
Input
SSL rise and fall
time
Output
Slave output release time
ns
-
10
-
15
1.8V or above
-
20
1.6V or above
-
30
-
1
µs
-
2 × tPcyc
+100
ns
1.8V or above
-
2 × tPcyc
+140
1.6V or above
-
2 × tPcyc
+180
-
2 × tPcyc
+100
1.8V or above
-
2 × tPcyc
+140
1.6V or above
-
2 × tPcyc
+180
Input
Slave access time
ns
2.4V or above
2.7V or above
tSSLr, tSSLf
ns
2.4V or above
2.4V or above
tSA
tREL
Figure 41.54 and
Figure 41.55
C = 30PF
ns
Note 1. tPcyc: PCLKB cycle.
Note 2. N is set as an integer from 1 to 8 by the SPCKD register.
Note 3. N is set as an integer from 1 to 8 by the SSLND register.
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41. Electrical Characteristics
tSPCKr
tSPCKWH
VOH
RSPCKn
master select
output
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
RSPCKn
slave select input
VIL
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
n = A or B
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 41.49
SPI clock timing
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tDr, tDf
MOSIn
output
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 41.50
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to any value other than 1/2)
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Feb 5, 2018
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41. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tHF
tHF
MSB IN
t Dr, tDf
MOSIn
output
LSB IN
DATA
tOH
MSB OUT
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 41.51
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to 1/2)
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tOH
MOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 41.52
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to any value other than 1/2)
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Feb 5, 2018
Page 1029 of 1104
S124 User’s Manual
41. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
t SU
MISOn
input
tHF
MSB IN
tOH
tH
DATA
LSB IN
tOD
MOSIn
output
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 41.53
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to 1/2)
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
MISOn
output
MSB OUT
tSU
MOSIn
input
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB IN
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
n = A or B
Figure 41.54
SPI timing (slave, CPHA = 0)
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Feb 5, 2018
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41. Electrical Characteristics
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
MISOn
output
tOH
tOD
LSB OUT
(Last data)
MSB OUT
tSU
MOSIn
input
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
n = A or B
Figure 41.55
SPI timing (slave, CPHA = 1)
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Feb 5, 2018
Page 1031 of 1104
S124 User’s Manual
41.3.10
Table 41.36
41. Electrical Characteristics
IIC Timing
IIC timing
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Symbol Min*1
Parameter
IIC
(standard mode,
SMBus)
IIC*2
(Fast mode)
Note:
Max
Unit
Test
conditions
Figure 41.56
SCL input cycle time
tSCL
6 (12) × tIICcyc + 1300
-
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
-
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
-
ns
SCL, SDA input rise time
tSr
-
1000
ns
SCL, SDA input fall time
tSf
-
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
(When wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
-
ns
SDA input bus free time
(When wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 × tPcyc
+ 300
-
ns
START condition input hold time
(When wakeup function is disabled)
tSTAH
tIICcyc + 300
-
ns
START condition input hold time
(When wakeup function is enabled)
tSTAH
1 (5) × tIICcyc + tPcyc +
300
-
ns
Repeated START condition input
setup time
tSTAS
1000
-
ns
STOP condition input setup time
tSTOS
1000
-
ns
Data input setup time
tSDAS
tIICcyc + 50
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb
-
400
pF
SCL input cycle time
tSCL
6 (12) × tIICcyc + 600
-
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
-
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
-
ns
SCL, SDA input rise time
tSr
-
300
ns
SCL, SDA input fall time
tSf
-
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
(When wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
-
ns
SDA input bus free time
(When wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 × tPcyc
+ 300
-
ns
START condition input hold time
(When wakeup function is disabled)
tSTAH
tIICcyc + 300
-
ns
START condition input hold time
(When wakeup function is enabled)
tSTAH
1(5) × tIICcyc + tPcyc +
300
-
ns
Repeated START condition input
setup time
tSTAS
300
-
ns
STOP condition input setup time
tSTOS
300
-
ns
Data input setup time
tSDAS
tIICcyc + 50
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb
-
400
pF
Figure 41.56
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE
set to 1.
Note 2. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
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Page 1032 of 1104
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41. Electrical Characteristics
VIH
SDA0 and SDA1
VIL
tBUF
tSCLH
tSTAH
tSTAS
tSTOS
tSP
SCL0 and SCL1
P*1
tSf
P*1
Sr*1
S*1
tSCLL
tSr
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 41.56
I2C bus interface input/output timing
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Feb 5, 2018
Page 1033 of 1104
S124 User’s Manual
41.3.11
41. Electrical Characteristics
CLKOUT Timing
Table 41.37
CLKOUT timing
Symbol
Min
Max
Unit*1
Test conditions
tCcyc
62.5
-
ns
Figure 41.57
VCC = 1.8 V or above
125
-
VCC = 1.6 V or above
250
-
Parameter
CLKOUT
CLKOUT pin output cycle*1
CLKOUT pin high pulse
width*2
VCC = 2.7 V or above
VCC = 2.7 V or above
tCH
15
-
30
-
150
-
15
-
VCC = 1.8 V or above
30
-
VCC = 1.6 V or above
150
-
VCC = 1.8 V or above
VCC = 1.6 V or above
CLKOUT pin low pulse width*2
CLKOUT pin output rise time
CLKOUT pin output fall time
Note 1.
Note 2.
VCC = 2.7 V or above
tCL
-
12
VCC = 1.8 V or above
-
25
VCC = 1.6 V or above
-
50
VCC = 2.7 V or above
tCr
-
12
VCC = 1.8 V or above
-
25
VCC = 1.6 V or above
-
50
VCC = 2.7 V or above
tCf
ns
ns
ns
ns
When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and
the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to
55%.
When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division
ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).
tCcyc
tCH
tCf
CLKOUT pin output
tCL
tCr
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 41.57
CLKOUT output timing
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Feb 5, 2018
Page 1034 of 1104
S124 User’s Manual
41.4
41. Electrical Characteristics
USB Characteristics
41.4.1
Table 41.38
USBFS Timing
USB characteristics
Conditions: VCC = AVCC0 = VCC_USB = 3.0 to 3.6V, Ta = –20 to +85°C
Parameter
Input
characteristics
Output
characteristics
Symbol
Min
Max
Unit
Test conditions
Input high level voltage
VIH
2.0
-
V
-
Input low level voltage
VIL
-
0.8
V
-
Differential input sensitivity VDI
0.2
-
V
| USB_DP – USB_DM |
Differential common mode
range
VCM
0.8
2.5
V
-
Output high level voltage
VOH
2.8
VCC_USB
V
IOH = –200 μA
Output low level voltage
VOL
0.0
0.3
V
IOL= 2 mA
Cross-over voltage
VCRS
1.3
2.0
V
ns
Figure 41.58,
Figure 41.59,
Figure 41.60
Rise time
FS
tr
LS
Fall time
FS
tf
LS
Rise/fall time ratio
FS
tr/tf
LS
4
20
75
300
4
20
75
300
90
111.11
80
125
ns
%
Output resistance
ZDRV
28
44
Ω
(Adjusting the resistance
of external elements is not
necessary.)
VBUS
characteristics
VBUS input voltage
VIH
VCC × 0.8
-
V
-
VIL
-
VCC × 0.2
V
-
Pull-up,
pull-down
Pull-down resistor
RPD
14.25
24.80
kΩ
-
Pull-up resistor
RPUI
0.9
1.575
kΩ
During idle state
RPUA
1.425
3.09
kΩ
During reception
Battery Charging
Specification
Ver 1.2
D + sink current
IDP_SINK
25
175
μA
-
D – sink current
IDM_SINK
25
175
μA
-
DCD source current
IDP_SRC
7
13
μA
-
Data detection voltage
VDAT_REF
0.25
0.4
V
-
D + source voltage
VDP_SRC
0.5
0.7
V
Output current = 250 μA
D – source voltage
VDM_SRC
0.5
0.7
V
Output current = 250 μA
USB_DP,
USB_DM
VCRS
90%
10%
tr
Figure 41.58
90%
10%
tf
USB_DP and USB_DM output timing
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Feb 5, 2018
Page 1035 of 1104
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41. Electrical Characteristics
Observation
point
USB_DP
50 pF
USB_DM
50 pF
Figure 41.59
Test circuit for Full-Speed (FS) connection
Observation
point
USB_DP
200 pF to
600 pF
3.6 V
1.5 K
USB_DM
200 pF to
600 pF Observation
point
Figure 41.60
41.4.2
Table 41.39
Test circuit for Low-Speed (LS) connection
USB External Supply
USB regulator
Parameter
VCC_USB supply current
Min
Typ
Max
Unit
Test conditions
VCC_USB_LDO ≥ 3.8V
-
-
50
mA
-
VCC_USB_LDO ≥ 4.5V
-
-
100
mA
-
-
3.6
V
-
VCC_USB supply voltage
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Feb 5, 2018
3.0
Page 1036 of 1104
S124 User’s Manual
41.5
41. Electrical Characteristics
ADC14 Characteristics
VREFH0
VREFH0
5.5
5.5
A/D Conversion
Characteristics (1)
5.0
A/D Conversion
Characteristics (2)
4.0
3.0
2.7
2.4
A/D Conversion
Characteristics (3)
5.0
3.0
2.7
2.4
2.0
2.0
1.8
1.6
1.0
1.0
2.4 2.7
1.0
2.0
3.0
5.5
4.0
A/D Conversion
Characteristics (4)
4.0
A/D Conversion
Characteristics (5)
A/D Conversion
Characteristics (6)
A/D Conversion
Characteristics (7)
AVCC0
1.8
5.0
1.0
ADCSR.ADHSC = 0
Figure 41.61
Table 41.40
2.4 2.7
1.6 2.0
3.0
5.5
4.0
AVCC0
5.0
ADCSR.ADHSC = 1
AVCC0 to VREFH0 voltage range
A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Frequency
1
-
64
MHz
-
-
-
8*3
pF
High-precision channel
-
-
9*3
pF
Normal-precision channel
-
2.5*3
kΩ
High-precision channel
Analog input
capacitance*2
Cs
Analog input resistance
Rs
Analog input voltage range
Ain
-
-
6.7*3
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
0.70
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.13
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
-
±0.5
12-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 64 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
Offset error
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
14-bit mode
Resolution
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Feb 5, 2018
Page 1037 of 1104
S124 User’s Manual
Table 41.40
41. Electrical Characteristics
A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
0.80
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.22
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±2.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
Conversion time*1
(Operation at
PCLKD = 64 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 41.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Table 41.41
A/D conversion characteristics (2) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Frequency
Analog input capacitance*2
Cs
Min
Typ
Max
Unit
Test Conditions
1
-
48
MHz
-
-
-
8*3
pF
High-precision channel
pF
Normal-precision channel
kΩ
High-precision channel
-
-
9*3
-
-
2.5*3
-
-
6.7*3
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
0.94
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.50
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
Analog input resistance
Rs
Analog input voltage range
Ain
12-bit mode
Resolution
Conversion time*1
(Operation at
PCLKD = 48 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1038 of 1104
S124 User’s Manual
Table 41.41
41. Electrical Characteristics
A/D conversion characteristics (2) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
14-bit mode
Resolution
-
-
14
Bit
-
1.06
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.63
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±2.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Conversion time*1
(Operation at
PCLKD = 48 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 41.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Table 41.42
A/D conversion characteristics (3) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Frequency
Analog input capacitance*2
Cs
Analog input resistance
Rs
Analog input voltage range
Ain
Min
Typ
Max
Unit
Test Conditions
1
-
32
MHz
-
-
-
8*3
pF
High-precision channel
pF
Normal-precision channel
kΩ
High-precision channel
-
-
9*3
-
-
2.5*3
-
-
6.7*3
kΩ
Normal-precision channel
0
-
VREFH0
V
-
12-bit mode
Resolution
-
-
12
Bit
-
1.41
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
2.25
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
Conversion time*1
(Operation at
PCLKD = 32 MHz)
Permissible signal
source impedance
Max. = 1.3 kΩ
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1039 of 1104
S124 User’s Manual
Table 41.42
41. Electrical Characteristics
A/D conversion characteristics (3) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
14-bit mode
Resolution
-
-
14
Bit
-
1.59
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
2.44
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±2.0
±18
LSB
High-precision channel
Full-scale error
-
±3.0
Conversion time*1
(Operation at
PCLKD = 32 MHz)
Permissible signal
source impedance
Max. = 1.3 kΩ
±24.0
LSB
Other than above
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 41.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Table 41.43
A/D conversion characteristics (4) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Frequency
1
-
24
MHz
-
-
-
8*3
pF
High-precision channel
-
-
9*3
pF
Normal-precision channel
-
2.5*3
kΩ
High-precision channel
Analog input
capacitance*2
Cs
Analog input resistance
Rs
Analog input voltage range
Ain
-
-
6.7*3
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
2.25
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
3.38
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±0.5
12-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 24 MHz)
Permissible signal
source impedance
Max. = 1.1 kΩ
Offset error
Full-scale error
Quantization error
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
-
±0.75
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
-
LSB
-
Page 1040 of 1104
S124 User’s Manual
Table 41.43
41. Electrical Characteristics
A/D conversion characteristics (4) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
2.50
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
3.63
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±2.0
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 24 MHz)
Permissible signal
source impedance
Max. = 1.1 kΩ
Offset error
±18
LSB
High-precision channel
±24.0
LSB
Other than above
LSB
High-precision channel
Full-scale error
-
±3.0
±18
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 41.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Table 41.44
A/D conversion characteristics (5) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Frequency
Analog input capacitance*2
Cs
Analog input resistance
Rs
Analog input voltage range
Ain
Min
Typ
Max
Unit
Test Conditions
1
-
16
MHz
-
-
-
8*3
pF
High-precision channel
-
-
9*3
pF
Normal-precision channel
-
-
2.5*3
kΩ
High-precision channel
-
-
6.7*3
kΩ
Normal-precision channel
0
-
VREFH0
V
-
12-bit mode
Resolution
Conversion time*1
(Operation at
PCLKD = 16 MHz)
Permissible signal
source impedance
Max. = 2.2 kΩ
Offset error
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
-
-
12
Bit
-
3.38
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
5.06
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Page 1041 of 1104
S124 User’s Manual
Table 41.44
41. Electrical Characteristics
A/D conversion characteristics (5) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Full-scale error
-
±0.75
Max
Unit
Test Conditions
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
14-bit mode
Resolution
Conversion time*1
(Operation at
PCLKD = 16 MHz)
Permissible signal
source impedance
Max. = 2.2 kΩ
Offset error
Full-scale error
-
-
14
Bit
-
3.75
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
5.44
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±2.0
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 41.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Table 41.45
A/D conversion characteristics (6) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Frequency
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
Typ
Max
Unit
Test Conditions
1
-
8
MHz
-
-
-
8*3
pF
High-precision channel
pF
Normal-precision channel
kΩ
High-precision channel
-
-
9*3
-
-
3.8*3
-
-
8.2*3
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
12-bit mode
Resolution
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1042 of 1104
S124 User’s Manual
Table 41.45
41. Electrical Characteristics
A/D conversion characteristics (6) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
time*1
Conversion
(Operation at
PCLKD = 8 MHz)
Permissible signal
source impedance
Max. = 5 kΩ
Offset error
Full-scale error
Min
Typ
Max
Unit
Test Conditions
6.75
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
10.13
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±1.0
-
±1.5
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±3.0
±8.0
LSB
High-precision channel
±12.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
7.50
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
10.88
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±4.0
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 8 MHz)
Permissible signal
source impedance
Max. = 5 kΩ
Offset error
Full-scale error
-
±6.0
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±12.0
±32.0
LSB
High-precision channel
±48.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 41.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Table 41.46
A/D conversion characteristics (7) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Frequency
1
-
4
MHz
-
-
-
8*3
pF
High-precision channel
-
-
9*3
pF
Normal-precision channel
-
-
13.1*3
kΩ
High-precision channel
-
-
14.3*3
kΩ
Normal-precision channel
Analog input
capacitance*2
Analog input resistance
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Cs
Rs
Page 1043 of 1104
S124 User’s Manual
Table 41.46
41. Electrical Characteristics
A/D conversion characteristics (7) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Analog input voltage range
Ain
Min
Typ
Max
Unit
Test Conditions
0
-
VREFH0
V
-
-
-
12
Bit
-
13.5
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
20.25
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±1.0
12-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 4 MHz)
Permissible signal
source impedance
Max. = 9.9 kΩ
Offset error
Full-scale error
-
±1.5
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±3.0
±8.0
LSB
High-precision channel
±12.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
15.0
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
21.75
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±4.0
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 4 MHz)
Permissible signal
source impedance
Max. = 9.9 kΩ
Offset error
Full-scale error
-
±6.0
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±12.0
±32.0
LSB
High-precision channel
±48.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 41.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1044 of 1104
S124 User’s Manual
Figure 41.62
Table 41.47
41. Electrical Characteristics
Equivalent circuit for analog input
14-bit A/D converter channel classification
Classification
Channel
Conditions
Remarks
High-precision channel
AN000 to AN010
AVCC0 = 1.6 to 5.5 V
Normal-precision channel
AN016 to AN022
Pins AN000 to AN010 cannot be used
as general I/O, TS transmission,
when the A/D converter is in use.
Internal reference voltage
input channel
Internal reference voltage
AVCC0 = 2.0 to 5.5 V
-
Temperature sensor input
channel
Temperature sensor output
AVCC0 = 2.0 to 5.5 V
-
Table 41.48
A/D internal reference voltage characteristics
Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1
Parameter
Min
Typ
Max
Unit
Test conditions
Internal reference voltage input
channel*2
1.36
1.43
1.50
V
-
Frequency
1
-
2
MHz
-
Sampling time
5.0
-
-
μs
-
Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
Note 2. The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the
14-bit A/D converter.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1045 of 1104
S124 User’s Manual
41. Electrical Characteristics
3FFFh
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code
Ideal line of actual A/D
conversion characteristic
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Differential non-linearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential non-linearity error
(DNL)
1-LSB width for ideal A/D
conversion characteristic
Absolute accuracy
0000h
Offset error
0
Figure 41.63
Analog input voltage
VREFH0
(full scale)
Illustration of 14-bit A/D converter characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion
result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D
conversion characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actual output code.
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
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Feb 5, 2018
Page 1046 of 1104
S124 User’s Manual
41.6
41. Electrical Characteristics
DAC12 Characteristics
Table 41.49
D/A conversion characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Reference voltage = AVCC0 or AVSS0 selected
Parameter
Min
Typ
Max
Unit
Test conditions
Resolution
-
-
12
bit
-
Resistive load
30
-
-
kΩ
-
Capacitive load
-
-
50
pF
-
Output voltage range
0.35
-
AVCC0 – 0.47
V
-
DNL differential nonlinearity error
-
±0.5
±2.0
LSB
-
INL integral nonlinearity error
-
±2.0
±8.0
LSB
-
Offset error
-
-
±30
mV
-
Full-scale error
-
-
±30
mV
-
Output impedance
-
5
-
Ω
-
Conversion time
-
-
30
μs
-
Gain error
Full-scale error
Upper output limit
Integral nonlinearity error (INL)
Offset error
Output analog voltage
1-LSB width for ideal D/A conversion
characteristic
Ideal output voltage
Differential nonlinearity error
(DNL)
*1
Lower output limit
Actual D/A conversion characteristic
Offset error
Ideal output voltage
000h
D/A converter input code
FFFh
Note 1. Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed.
Figure 41.64
Illustration of D/A converter characteristic terms
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion
characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion
characteristics and the width of the actual output voltage.
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41. Electrical Characteristics
Offset error
Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the
ideal output voltage based on the input code.
Full-scale error
Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the
ideal output voltage based on the input code.
41.7
TSN Characteristics
Table 41.50
TSN characteristics
Conditions: VCC = AVCC0 = 2.0 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Relative accuracy
-
-
±1.5
-
°C
2.4 V or above
-
±2.0
-
°C
Below 2.4 V
-
–3.65
-
mV/°C
-
Temperature slope
-
Output voltage (at 25°C)
-
-
1.05
-
V
VCC = 3.3 V
Temperature sensor start time
tSTART
-
-
5
μs
-
Sampling time
-
5
-
-
μs
41.8
OSC Stop Detect Characteristics
Table 41.51
Oscillation stop detection circuit characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Detection time
tdr
-
-
1
ms
Figure 41.65
Main clock
tdr
OSTDSR.OSTDF
MOCO clock
ICLK
Figure 41.65
Oscillation stop detection timing
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41.9
41. Electrical Characteristics
POR and LVD Characteristics
Table 41.52
Power-on reset circuit and voltage detection circuit characteristics (1)
Parameter
Voltage detection
level*1
Symbol
Min
Typ
Max
Unit
Test Conditions
Power-on reset (POR)
VPOR
1.27
1.42
1.57
V
Figure 41.66,
Figure 41.67
Voltage detection circuit (LVD0)*2
Vdet0_0
3.68
3.85
4.00
V
Vdet0_1
2.68
2.85
2.96
Figure 41.68
At falling edge
VCC
Vdet0_2
2.38
2.53
2.64
Vdet0_3
1.78
1.90
2.02
V
Figure 41.69
At falling edge
VCC
V
Figure 41.70
At falling edge
VCC
Voltage detection circuit (LVD1)*3
Voltage detection circuit
(LVD2)*4
Vdet0_4
1.60
1.69
1.82
Vdet1_0
4.13
4.29
4.45
Vdet1_1
3.98
4.16
4.30
Vdet1_2
3.86
4.03
4.18
Vdet1_3
3.68
3.86
4.00
Vdet1_4
2.98
3.10
3.22
Vdet1_5
2.89
3.00
3.11
Vdet1_6
2.79
2.90
3.01
Vdet1_7
2.68
2.79
2.90
Vdet1_8
2.58
2.68
2.78
Vdet1_9
2.48
2.58
2.68
Vdet1_A
2.38
2.48
2.58
Vdet1_B
2.10
2.20
2.30
Vdet1_C
1.84
1.96
2.05
Vdet1_D
1.74
1.86
1.95
Vdet1_E
1.63
1.75
1.84
Vdet1_F
1.60
1.65
1.73
Vdet2_0
4.11
4.31
4.48
Vdet2_1
3.97
4.17
4.34
Vdet2_2
3.83
4.03
4.20
Vdet2_3
3.64
3.84
4.01
Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this
voltage detection level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or
LVD2 is used for voltage detection.
Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.
Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
Table 41.53
Power-on reset circuit and voltage detection circuit characteristics (2) (1 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Wait time after power-on
Reset cancellation
LVD0:enable
tPOR
-
1.7
-
ms
-
LVD0:disable
tPOR
-
1.3
-
ms
-
Wait time after voltage
monitor 0,1,2 reset
cancellation
LVD0:enable*1
tLVD0,1,2
-
0.6
-
ms
-
LVD0:disable*2
tLVD1,2
-
0.2
-
ms
-
Response delay*3
tdet
-
-
350
μs
Figure 41.66, Figure 41.67
Minimum VCC down time
tVOFF
450
-
-
μs
Figure 41.66,
VCC = 1.0 V or above
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Feb 5, 2018
Page 1049 of 1104
S124 User’s Manual
Table 41.53
41. Electrical Characteristics
Power-on reset circuit and voltage detection circuit characteristics (2) (2 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Power-on reset enable time
tW (POR)
1
-
-
ms
Figure 41.67,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is
enabled)
Td (E-A)
-
-
300
μs
Figure 41.69,
Figure 41.70
Hysteresis width (POR)
VPORH
-
110
-
mV
-
Hysteresis width (LVD0, LVD1, and LVD2)
VLVH
-
60
-
mV
-
100
-
Vdet1_0 to Vdet1_2 selected.
-
60
-
Vdet1_3 to Vdet1_9 selected.
-
50
-
Vdet1_A to Vdet1_B
selected.
-
40
-
Vdet1_C to Vdet1_F
selected.
-
60
-
LVD2 selected
LVD0 selected
Note 1. When OFS1.LVDAS = 0
Note 2. When OFS1.LVDAS = 1
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection
levels VPOR, Vdet0, Vdet1, and Vdet2 for the POR/LVD.
tVOFF
VCC
VPOR
1.0 V
Internal reset signal
(active-low)
tdet
Figure 41.66
tdet
tPOR
Voltage detection reset timing
VPOR
VCC
1.0 V
tw(POR)
Internal reset signal
(active-low)
*1
tdet
Note:
tPOR
tW(POR) is the time required for a power-on reset to be enabled while the external power VCC is
being held below the valid voltage (1.0 V).
When VCC turns on, maintain tW(POR) for 1.0 ms or more.
Figure 41.67
Power-on reset timing
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41. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet0
Internal reset signal
(active-low)
tdet
Figure 41.68
tdet
tLVD0
Voltage detection circuit timing (Vdet0)
tVOFF
VCC
VLVH
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tdet
tLVD1
When LVD1CR0.RN = 1
tLVD1
Figure 41.69
Voltage detection circuit timing (Vdet1)
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41. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet2
LVCMPCR.LVD2E
LVD2
Comparator output
Td(E-A)
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 41.70
Voltage detection circuit timing (Vdet2)
41.10 CTSU Characteristics
Table 41.54
CTSU characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
External capacitance connected to TSCAP pin
Ctscap
9
10
11
nF
-
TS pin capacitive load
Cbase
-
-
50
pF
-
Permissible output high current
ΣIoH
-
-
-24
mA
When the mutual
capacitance method
is applied
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41. Electrical Characteristics
41.11 Comparator Characteristics
Table 41.55
ACMPLP characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Reference voltage range
VREF
0
-
VCC
–1.4
V
-
Input voltage range
VI
0
-
VCC
V
-
Internal reference voltage
-
1.36
1.44
1.50
V
-
Output delay
Td
-
-
1.2
μs
-
-
5
μs
VCC = 3.0
Slew rate of input
signal > 50 mV/μs
High-speed mode
Low-speed mode
-
-
2
μs
High-speed mode
-
-
-
50
mV
-
Low-speed mode
-
-
-
40
mV
-
Window mode
Offset voltage
Window mode
Internal reference voltage for window mode
Operation stabilization wait time
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
-
-
-
60
mV
-
VRFH
-
0.76 ×
VCC
-
V
-
VRFL
-
0.24 ×
VCC
-
V
-
Tcmp
100
-
-
μs
-
Page 1053 of 1104
S124 User’s Manual
41. Electrical Characteristics
41.12 Flash Memory Characteristics
41.12.1
Table 41.56
Code Flash Memory Characteristics
Code flash characteristics (1)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Reprogramming/erasure cycle*1
NPEC
1000
-
-
Times
-
tDRP
20*2, *3
-
-
Year
Ta = +85°C
Data hold time
After 1000 times NPEC
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times
(n = 1,000), erasing can be performed n times for each block. For instance, when 4-byte programming is
performed 256 times for different addresses in 1-KB blocks, and then the entire block is erased, the reprogram/
erase cycle is counted as 1. However, programming the same address for several times as one erasure is not
enabled. (overwriting is prohibited.)
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas
Electronics.
Note 3. This result is obtained from reliability testing.
Table 41.57
Code flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
ICLK = 1 MHz
Parameter
Programming time
4-byte
ICLK = 32 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
tP4
-
116
998
-
54
506
μs
Erasure time
1-KB
tE1K
-
9.03
287
-
5.67
222
ms
Blank check time
4-byte
tBC4
-
-
56.8
-
-
16.6
μs
1-KB
tBC1K
-
-
1899
-
-
140
μs
Erase suspended time
tSED
-
-
22.5
-
-
10.7
μs
Startup area switching setting time
tSAS
-
21.9
585
-
12.1
447
ms
Access window time
tAWS
-
21.9
585
-
12.1
447
ms
OCD/serial programmer ID setting time
tOSIS
-
21.9
585
-
12.1
447
ms
Flash memory mode transition wait
time 1
tDIS
2
-
-
2
-
-
μs
Flash memory mode transition wait
time 2
tMS
5
-
-
5
-
-
μs
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
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Page 1054 of 1104
S124 User’s Manual
Table 41.58
41. Electrical Characteristics
Code flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85°C
ICLK = 1 MHz
Parameter
ICLK = 8 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Programming time
4-byte
tP4
-
157
1411
-
101
966
μs
Erasure time
1-KB
tE1K
-
9.10
289
-
6.10
228
ms
Blank check time
2-byte
tBC4
-
-
87.7
-
-
52.5
μs
1-KB
-
-
tBC1K
-
1930
-
414
μs
Erase suspended time
tSED
-
-
32.7
-
-
21.6
μs
Startup area switching setting time
tSAS
-
22.8
592
-
14.2
465
ms
Access window time
tAWS
-
22.8
592
-
14.2
465
ms
OCD/serial programmer ID setting time
tOSIS
-
22.8
592
-
14.2
465
ms
Flash memory mode transition wait
time 1
tDIS
2
-
-
2
-
-
μs
Flash memory mode transition wait
time 2
tMS
720
-
-
720
-
-
ns
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
41.12.2
Table 41.59
Data Flash Memory Characteristics
Data flash characteristics (1)
Parameter
Reprogramming/erasure
Data hold time
cycle*1
After 10000 times of NDPEC
After 100000 times of NDPEC
After 1000000 times of NDPEC
Symbol
Min
Typ
Max
Unit
NDPEC
100000
1000000
-
Conditions
Times
-
tDDRP
20*2, *3
-
-
Year
Ta = +85°C
5*2, *3
-
-
Year
-
1*2, *3
-
Year
Ta = +25°C
Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times
(n = 100,000), erasing can be performed n times for each block. For instance, when 1-byte programming is
performed 1,000 times for different addresses in 1-byte blocks, and then the entire block is erased, the
reprogram/erase cycle is counted as 1. However, programming the same address for several times as one
erasure is not enabled. (overwriting is prohibited.)
Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas
Electronics.
Note 3. These results are obtained from reliability testing.
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Page 1055 of 1104
S124 User’s Manual
Table 41.60
41. Electrical Characteristics
Data flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
ICLK = 4 MHz
Parameter
ICLK = 32 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Programming time
1-byte
tDP1
-
52.4
463
-
42.1
387
μs
Erasure time
1-KB
tDE1K
-
8.98
286
-
6.42
237
ms
Blank check time
1-byte
tDBC1
-
-
24.3
-
-
16.6
μs
1-KB
-
-
tDBC1K
-
1872
-
512
μs
Suspended time during erasing
tDSED
-
-
13.0
-
-
10.7
μs
Data flash STOP recovery time
tDSTOP
5
-
-
5
-
-
μs
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Table 41.61
Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85°C
ICLK = 4 MHz
Parameter
Programming time
1-byte
ICLK = 8 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
tDP1
-
94.7
886
-
89.3
849
μs
Erasure time
1-KB
tDE1K
-
9.59
299
-
8.29
273
ms
Blank check time
1-byte
tDBC1
-
-
56.2
-
-
52.5
μs
1-KB
tDBC1K
-
-
2.17
-
-
1.51
ms
Suspended time during erasing
tDSED
-
-
23.0
-
-
21.7
μs
Data flash STOP recovery time
tDSTOP
720
-
-
720
-
-
ns
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1056 of 1104
S124 User’s Manual
41.12.3
Table 41.62
41. Electrical Characteristics
Serial Wire Debug (SWD)
SWD characteristics (1)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
80
-
-
ns
Figure 41.71
SWCLK clock high pulse width
tSWCKH
35
-
-
ns
SWCLK clock low pulse width
tSWCKL
35
-
-
ns
SWCLK clock rise time
tSWCKr
-
-
5
ns
SWCLK clock fall time
tSWCKf
-
-
5
ns
SWDIO setup time
tSWDS
16
-
-
ns
SWDIO hold time
tSWDH
16
-
-
ns
SWDIO data delay time
tSWDD
2
-
70
ns
Table 41.63
Figure 41.72
SWD characteristics (2)
Conditions: VCC = AVCC0 = 1.6 to 2.4 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
250
-
-
ns
Figure 41.71
SWCLK clock high pulse width
tSWCKH
120
-
-
ns
SWCLK clock low pulse width
tSWCKL
120
-
-
ns
SWCLK clock rise time
tSWCKr
-
-
5
ns
SWCLK clock fall time
tSWCKf
-
-
5
ns
SWDIO setup time
tSWDS
50
-
-
ns
SWDIO hold time
tSWDH
50
-
-
ns
SWDIO data delay time
tSWDD
2
-
150
ns
Figure 41.72
tSWCKcyc
tSWCKH
SWCLK
tSWCKf
tSWCKL
Figure 41.71
tSWCKr
SWD SWCLK timing
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Page 1057 of 1104
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41. Electrical Characteristics
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
Figure 41.72
SWD input output timing
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1058 of 1104
S124 User’s Manual
Appendix 1. Port States in Each Processing Mode
Appendix 1. Port States in Each Processing Mode
Table 1.1
Port states in each processing state (1 of 2)
Port Name
P000/IRQ6,
P001/IRQ7,
P002/IRQ2
Reset
Software Standby Mode
Hi-Z
Keep-O*1
P003
Hi-Z
Keep-O
P004/IRQ3
Hi-Z
Keep-O*1
P010 to P013
Hi-Z
Keep-O
P014/DA0
Hi-Z
[DA0 output (DAOE0=1)]
DA output retained
[Other than the above (DAOE0=0)]
Keep-O
P015/IRQ7
Hi-Z
Keep-O*1
P100/KR00/IRQ2/CMPIN0/
AGTIO0_A/RXD0_A
Hi-Z
[AGTIO0_A selected]
AGTIO0_A output
[Other than the above]
Keep-O*1
P101/KR01/IRQ1/CMPREF0
Hi-Z
Keep-O*1
P102/KR02/AGTO0
Hi-Z
[AGTO0 selected]
AGTO0 output
[Other than the above]
Keep-O*1
P103/KR03,
P104/KR04/IRQ1/RXD0_C,
P105/KR05/IRQ0,
P106/KR06,
P107/KR07
Hi-Z
Keep-O*1
P108/SWDIO
Pull-up
Keep-O
P109/CLKOUT_B
Hi-Z
[CLKOUT selected]
CLKOUT output
[Other than the above]
Keep-O
P110/IRQ3/VCOUT
Hi-Z
[ACMPLP selected]
VCOUT output
[Other than the above]
Keep-O*1
P111/IRQ4
Hi-Z
Keep-O*1
P112, P113
Hi-Z
Keep-O
P200/NMI
Hi-Z
Hi-Z
Pull-up
Keep-O
P204/AGTIO1_A/SCL0_B
Hi-Z
[AGTIO1_A output selected]
AGTIO1_A output
[Other than the above]
Keep-O*1
P205/IRQ1/CLKOUT_A/AGTO1
Hi-Z
[AGTO1 selected]
AGTO1 output
[CLKOUT selected]
CLKOUT output
[Other than the above]
Keep-O*1
P206/IRQ0/RXD0_D
P212/IRQ3/EXTAL,
P213/IRQ2/XTAL
Hi-Z
Keep-O*1
P214/XCOUT,
P215/XCIN
Hi-Z
[Sub-clock Oscillator selected]
Sub-clock Oscillator is operating
[Other than the above]
Hi-Z
P300/SWCLK
P201
Pull-up
Keep-O
P301/IRQ6,
P302/IRQ5
Hi-Z
Keep-O*1
P303, P304
Hi-Z
Keep-O
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1059 of 1104
S124 User’s Manual
Table 1.1
Appendix 1. Port States in Each Processing Mode
Port states in each processing state (2 of 2)
Port Name
Reset
Software Standby Mode
P400/AGTIO1_D/SCL0_A/IRQ0
Hi-Z
[AGTIO1_D output selected]
AGTIO1_D output
[Other than the above]
Keep-O*1
P401/SDA0_A/IRQ5,
P402/IRQ4
Hi-Z
Keep-O*1
P403
Hi-Z
Keep-O
P407/SDA0_B/RTCOUT/USB_VBUS
Hi-Z
[RTCOUT selected]
RTCOUT output
[Other than the above]
Keep-O*1
P408/IRQ7,
P409/IRQ6
Hi-Z
Keep-O*1
P410/IRQ5/AGTOB1/RXD0_B
Hi-Z
[AGTOB1 selected]
AGTIOB1 output
[Other than the above]
Keep-O*1
P411/IRQ4/AGTOA1
Hi-Z
[AGTOA1 selected]
AGTIOA1 output
[Other than the above]
Keep-O*1
P500 to P502
Hi-Z
Keep-O
USB_DP
Hi-Z
Keep-O
USB_DM
Hi-Z
Keep-O
Hi-Z: High-impedance
Keep-O: Output pins retain their previous values. Input pins become high-impedance.
Note 1.
Input is enabled if the pin is specified as the software standby canceling source while it is used as an external interrupt pin.
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1060 of 1104
S124 User’s Manual
Appendix 2. Package Dimensions
Appendix 2. Package Dimensions
Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP64-10x10-0.50
PLQP0064KB-C
—
0.3
Unit: mm
HD
*1 D
48
33
64
HE
32
*2 E
49
17
1
16
NOTE 4
Index area
NOTE 3
F
S
y S
*3
bp
0.25
c
A1
T
A2
A
e
Lp
L1
Detail F
M
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
Min
Nom
Max
D
9.9
10.0
10.1
10.1
E
9.9
10.0
A2
1.4
HD
11.8
12.0
12.2
HE
11.8
12.0
12.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.1
LQFP 64-pin
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1061 of 1104
S124 User’s Manual
Appendix 2. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP48-7x7-0.50
PLQP0048KB-B
—
0.2
HD
Unit: mm
*1 D
36
25
*2
48
HE
24
E
37
13
1
12
NOTE 4
Index area
NOTE 3
F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
S
Reference Dimensions in millimeters
Symbol
y S
*3
bp
0.25
M
A1
T
c
A2
A
e
Lp
L1
Detail F
Min
Nom
Max
D
6.9
7.0
7.1
E
6.9
7.0
7.1
A2
1.4
HD
8.8
9.0
9.2
HE
8.8
9.0
9.2
A
1.7
A1
0.05
0.15
bp
0.17
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.2
LQFP 48-pin
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1062 of 1104
S124 User’s Manual
Appendix 2. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-WFLGA36-4x4-0.50
PWLG0036KA-A
P36FC-50-AA4-2
0.023
32x b
S AB
e
ZE
w S A
M
A
ZD
D
x
6
5
B
4
E
3
2.90
2
C
INDEX MARK
y1
D
w S B
S
1
F
E D C B A
E
2.90
A
S
y
S
DETAIL C
DETAIL E
DETAIL D
R0.17± 0.05
0.70 ±0.05
0.55 ±0.05 R0.12 ±0.05
0.75
0.55
(UNIT:mm)
R0.17 ±0.05
0.70 ±0.05
R0.12 ±0.05 0.55 ±0.05
0.75
0.55
φb
(LAND PAD)
φ 0.34±0.05
(APERTURE OF
SOLDER RESIST)
0.55
0.75
0.55±0.05
0.70± 0.05
0.55
0.75
0.55±0.05
R0.275±0.05
R0.35±0.05
ITEM
D
DIMENSIONS
E
4.00±0.10
w
0.20
4.00±0.10
e
0.50
A
0.69±0.07
b
0.24±0.05
x
0.05
y
0.08
y1
0.20
ZD
0.75
ZE
0.75
0.70±0.05
2012 Renesas Electronics Corporation. All rights reserved.
Figure 2.3
LGA 36-pin
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1063 of 1104
S124 User’s Manual
Appendix 2. Package Dimensions
JEITA Package code
P-HWQFN64-8x8-0.40
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0064LA-A
P64K8-40-9B5-3
0.16
D
33
48
DETAIL OF A PART
32
49
E
A
A1
17
64
c2
16
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
16
1
64
17
Dimension in Millimeters
Min
Nom
Max
D
7.95
8.00
8.05
E
7.95
8.00
8.05
A
0.80
A1
0.00
b
0.17
e
Lp
B
E2
ZE
32
49
33
ZD
e
b
x
M
0.23
0.40
0.30
0.40
0.50
x
0.05
y
0.05
ZD
1.00
ZE
1.00
c2
48
0.20
0.15
0.20
D2
6.50
E2
6.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
Figure 2.4
QFN 64-pin
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1064 of 1104
S124 User’s Manual
Appendix 2. Package Dimensions
JEITA Package code
P-HWQFN48-7x7-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0048KB-A
48PJN-A
P48K8-50-5B4-6
0.13
D
25
36
DETAIL OF A PART
24
37
E
A
A1
13
48
c2
12
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
12
1
13
48
Dimension in Millimeters
Min
Nom
Max
D
6.95
7.00
7.05
E
6.95
7.00
7.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
0.30
24
36
25
ZD
e
b
x
M
0.40
0.50
x
0.05
y
0.05
0.75
ZE
37
0.30
0.50
ZD
ZE
0.25
c2
0.75
0.15
0.20
D2
5.50
E2
5.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
Figure 2.5
QFN 48-pin
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1065 of 1104
S124 User’s Manual
Appendix 2. Package Dimensions
JEITA Package code
P-HWQFN40-6x6-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0040KC-A
P40K8-50-4B4-5
0.09
D
21
30
DETAIL OF A PART
20
31
E
40
A
A1
11
c2
10
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
1
10
11
40
Dimension in Millimeters
Min
Nom
Max
D
5.95
6.00
6.05
E
5.95
6.00
6.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
ZE
20
31
30
21
ZD
e
b
Figure 2.6
x
M
0.25
0.30
0.50
0.30
0.40
0.50
x
0.05
y
0.05
ZD
0.75
ZE
0.75
c2
0.15
0.20
D2
4.50
E2
4.50
0.25
S AB
QFN 40-pin
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1066 of 1104
S124 User’s Manual
Appendix 3. I/O Registers
Appendix 3. I/O Registers
This appendix describes I/O register addresses, access cycles, and reset values by function.
3.1
Peripheral Base Addresses
This section provides the base addresses for peripherals described in this manual.
Table 3.1 shows the name of each peripheral, description, and its base address.
Table 3.1
Name
Peripheral base address (1 of 2)
Description
Base address
SRAM
SRAM Control
0x40002000
BUS
BUS Control
0x40003000
DTC
Data Transfer Controller
0x40005400
ICU
Interrupt Controller
0x40006000
DBG
Debug Function
0x4001B000
SYSTEM
System Control
0x4001E000
PORT0
Port 0 Control Registers
0x40040000
PORT1
Port 1 Control Registers
0x40040020
PORT2
Port 2 Control Registers
0x40040040
PORT3
Port 3 Control Registers
0x40040060
PORT4
Port 4 Control Registers
0x40040080
PORT5
Port 5 Control Registers
0x400400A0
PFS
Pmn Pin Function Control Register
0x40040800
PMISC
Miscellaneous Port Control Register
0x40040D00
ELC
Event Link Controller
0x40041000
POEG
Port Output Enable Module for GPT
0x40042000
RTC
Realtime Clock
0x40044000
WDT
Watchdog Timer
0x40044200
IWDT
Independent Watchdog Timer
0x40044400
CAC
Clock Frequency Accuracy Measurement Circuit
0x40044600
MSTP
Module Stop Control B, C, D
0x40047000
CAN0
CAN0 Module
0x40050000
IIC0
Inter-Integrated Circuit 0
0x40053000
IIC1
Inter-Integrated Circuit 1
0x40053100
DOC
Data Operation Circuit
0x40054100
ADC140
14-bit A/D Converter
0x4005C000
DAC12
12-bit D/A converter
0x4005E000
SCI0
Serial Communication Interface 0
0x40070000
SCI1
Serial Communication Interface 1
0x40070020
SCI9
Serial Communication Interface 9
0x40070120
SPI0
Serial Peripheral Interface 0
0x40072000
SPI1
Serial Peripheral Interface 1
0x40072100
CRC
CRC Calculator
0x40074000
GPT320
General PWM Timer 0 (32-bit)
0x40078000
GPT161
General PWM Timer 1 (16-bit)
0x40078100
GPT162
General PWM Timer 2 (16-bit)
0x40078200
GPT163
General PWM Timer 3 (16-bit)
0x40078300
GPT164
General PWM Timer 4 (16-bit)
0x40078400
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1067 of 1104
S124 User’s Manual
Table 3.1
Appendix 3. I/O Registers
Peripheral base address (2 of 2)
Name
Description
Base address
GPT165
General PWM Timer 5 (16-bit)
0x40078500
GPT166
General PWM Timer 6 (16-bit)
0x40078600
GPT_OPS
Output Phase Switching Controller
0x40078FF0
KINT
Key Interrupt Function
0x40080000
CTSU
Capacitive Touch Sensing Unit
0x40081000
AGT0
Asynchronous General purpose Timer 0
0x40084000
AGT1
Asynchronous General purpose Timer 1
0x40084100
ACMPLP
Low-Power Analog Comparator
0x40085E00
USBFS
USB 2.0 Full-Speed Module
0x40090000
TSN
Temperature Sensor
0x407EC000
Name = Peripheral name
Description = Peripheral functionality
Base address = Lowest reserved address or address used by the peripheral
3.2
Access Cycles
This section provides access cycle information for the I/O registers described in this manual.
The following information applies to Table 3.2 and Table 3.3:
Registers are grouped by associated module
The number of access cycles indicates the number of cycles based on the specified reference clock
In the internal I/O register area, reserved addresses that are not allocated to registers must not be accessed, otherwise
operations cannot be guaranteed
The number of I/O register access cycles depends on bus cycles of the internal peripheral bus and divided clock
synchronization cycles. Divided clock synchronization cycles differ depending on the frequency ratio between
ICLK and PCLK.
When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is
always constant.
When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided
clock synchronization cycles.
Note:
This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to
the external memory or bus access from other bus master such as DTC.
Table 3.2 shows register access cycles for non-GPT modules.
Table 3.2
Access cycles for non-GPT modules (1 of 2)
Number of access cycles
Address
ICLK = PCLK
ICLK > PCLK*1
Read
Read
From
To
SRAM, BUS,
DTC, ICU,
DBG
4000 2000h
4001 BFFFh
2
ICLK
SRAM, Buses, Data Transfer
Controller, Interrupt Controller, CPU
SYSTEM
4001 E000h
4001 E3FFh
3
ICLK
Low Power Modes, Resets, Low
Voltage Detection, Clock Generation
Circuit, Register Write Protection
SYSTEM
4001 E400h
4001 E6FFh
PCLKB
Low Power Modes, Resets, Low
Voltage Detection, Battery Backup
Function
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Write
7
Write
Cycle
unit
Peripheral
5 to 7
Related function
Page 1068 of 1104
S124 User’s Manual
Table 3.2
Appendix 3. I/O Registers
Access cycles for non-GPT modules (2 of 2)
Number of access cycles
Address
ICLK = PCLK
ICLK > PCLK*1
Read
Read
Write
From
To
PORTn, PFS,
PMISC, ELC,
POEG, RTC,
WDT, IWDT,
CAC, MSTP
4004 0000h
4004 7FFFh
3
2 to 3
PCLKB
I/O Ports, Event Link Controller, Port
Output Enable for GPT, Realtime
Clock, Watchdog Timer, Independent
Watchdog Timer, Clock Frequency
Accuracy Measurement Circuit,
Module Stop Control
CAN0, IICn,
DOC,
ADC140,
DAC12
4005 0000h
4005 EFFFh
3
2 to 3
PCLKB
Controller Area Network, I2C Bus
Interface, Data Operation Circuit, 14Bit A/D Converter, 12-Bit D/A
Converter
SCIn
4007 0000h
4007 0EFFh
5*2
2 to 3*2
PCLKB
Serial Communications Interface
SPIn
4007 2000h
4007 2FFFh
5*3
2 to 3*3
PCLKB
Serial Peripheral Interface
CRC
4007 4000h
4007 4FFFh
3
2 to 3
PCLKB
CRC Calculator
PCLKB
General PWM Timer
ICLK
Temperature Sensor
See Table
Write
Cycle
unit
Peripheral
3.3*4
Related function
GPT32n,
GPT16n,
GPT_OPS
4007 8000h
4007 8FFFh
TSN
407E C000h
407E CFFFh
7
7
KINT, CTSU,
SLCDC
4008 0000h
4008 1FFFh
2
1 to 2
PCLKB
Key Interrupt Function, Capacitive
Touch Sensing Unit, Segment LCD
Controller
AGTn
4008 4000h
4008 4FFFh
3
2 to 3
PCLKB
Asynchronous General Purpose
Timer
ACMPLP
4008 5E00h
4008 5FFFh
2
1 to 2
PCLKB
Low-Power Analog Comparator
USBFS
4009 0000h
4009 03FFh
4
3 to 4
PCLKB
USB 2.0 Full-Speed Module
USBFS
4009 0400h
4009 04FFh
3
2 to 3
PCLKB
USB 2.0 Full-Speed Module
Note 1. If the number of PCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point,
and the maximum value is rounded up to the decimal point. For example, 1.5 to 2.5 is 1 to 3.
Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than
the value shown in Table 3.2. When accessing an 8-bit register (FTDRH, FTDRL, FRDRH, and FRDRL), the
access cycles are as shown in Table 3.2.
Note 3. When accessing a 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing
an 8-bit or a 16-bit register (SPDR_HA), the access cycles are as shown in Table 3.2.
Note 4. The access cycles differs depending on the frequency ratio between ICLK, PCLKB, and PCLKD, as shown in
Table 3.3.
Table 3.3 shows register access cycles for GPT modules.
Table 3.3
Access cycles for GPT modules
Number of access cycles
Frequency ratio between ICLK and PCLK
Read
Write
Cycle unit
ICLK > PCLKD = PCLKB
5 to 6
3 to 4
PCLKB
ICLK > PCLKD > PCLKB
3 to 4
2 to 3
PCLKB
PCLKD = ICLK = PCLKB
6
4
PCLKB
PCLKD = ICLK > PCLKB
2 to 3
1 to 2
PCLKB
PCLKD > ICLK = PCLKB
4
3
PCLKB
PCLKD > ICLK > PCLKB
2 to 3
1 to 2
PCLKB
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1069 of 1104
S124 User’s Manual
3.3
Appendix 3. I/O Registers
Register Descriptions
This section provides information associated with registers described in this manual.
Table 3.4 shows a list of the registers, including address offset and sizes, access rights, and reset values.
Table 3.4
Register description (1 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
SRAM
-
-
-
PARIOAD
BUS
DTC
ICU
DBG
-
-
-
Address
offset
Size
Access
Reset
value
Reset
mask
SRAM Parity Error
Operation After
Detection Register
0x00
8
readwrite
0x00
0xFF
SRAMPRCR
SRAM Protection
Register
0x04
8
readwrite
0x00
0xFF
BUSMCNTSYS
Master Bus
Control Register
SYS
0x1008
16
readwrite
0x0000
0xFFFF
BUSMCNTDMA
Master Bus
Control Register
DMA
0x100C
16
readwrite
0x0000
0xFFFF
BUSSCNTFLI
Slave Bus Control
Register FLI
0x1100
16
readwrite
0x0000
0xFFFF
BUSSCNTRAM0
Slave Bus Control
Register RAM0
0x110C
16
readwrite
0x0000
0xFFFF
2
0x4
P0B, P2B
BUSSCNT%s
Slave Bus Control
Register %s
0x1114
16
readwrite
0x0000
0xFFFF
-
-
-
BUSSCNTP4B
Slave Bus Control
Register P4B
0x1120
16
readwrite
0x0000
0xFFFF
-
-
-
DTCCR
DTC Control
Register
0x00
8
readwrite
0x08
0xFF
DTCVBR
DTC Vector Base
Register
0x04
32
readwrite
0x0000
0000
0xFFFF
FFFF
DTCST
DTC Module Start
Register
0x0C
8
readwrite
0x00
0xFF
DTCSTS
DTC Status
Register
0x0E
16
readonly
0x0000
0xFFFF
8
0x1
0-7
IRQCR%s
IRQ Control
Register %s
0x000
8
readwrite
0x00
0xFF
-
-
-
NMICR
NMI Pin Interrupt
Control Register
0x100
8
readwrite
0x00
0xFF
NMIER
Non-Maskable
Interrupt Enable
Register
0x120
16
readwrite
0x0000
0xFFFF
NMICLR
Non-Maskable
Interrupt Status
Clear Register
0x130
16
readwrite
0x0000
0xFFFF
NMISR
Non-Maskable
Interrupt Status
Register
0x140
16
readonly
0x0000
0xFFFF
WUPEN
Wakeup Interrupt
Enable Register
0x1A0
32
readwrite
0x0000
0000
0xFFFF
FFFF
SELSR0
Snooze Event Link
Setting Register
0x200
16
readwrite
0x0000
0xFFFF
32
0x4
0-31
IELSR%s
ICU Event Link
Setting Register
%s
0x300
32
readwrite
0x0000
0000
0xFFFF
FFFF
-
-
-
DBGSTR
Debug Status
Register
0x00
32
readonly
0x0000
0000
0xFFFF
FFFF
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1070 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (2 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
DBG
-
-
-
DBGSTOPCR
SYSTEM
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
Debug Stop
Control Register
0x10
32
readwrite
0x0000
0003
0xFFFF
FFFF
SBYCR
Standby Control
Register
0x00C
16
readwrite
0x0000
0xFFFF
MSTPCRA
Module Stop
Control Register A
0x01C
32
readwrite
0xFFBF
FFFF
0xFFFF
FFFF
SCKDIVCR
System Clock
Division Control
Register
0x020
32
readwrite
0x0400
0404
0xFFFF
FFFF
SCKSCR
System Clock
Source Control
Register
0x026
8
readwrite
0x01
0xFF
MOSCCR
Main Clock
Oscillator Control
Register
0x032
8
readwrite
0x01
0xFF
HOCOCR
High-Speed OnChip Oscillator
Control Register
0x036
8
readwrite
0x00
0xFE
MOCOCR
Middle-Speed OnChip Oscillator
Control Register
0x038
8
readwrite
0x00
0xFF
OSCSF
Oscillation
Stabilization Flag
Register
0x03C
8
readonly
0x00
0xFE
CKOCR
Clock Out Control
Register
0x03E
8
readwrite
0x00
0xFF
OSTDCR
Oscillation Stop
Detection Control
Register
0x040
8
readwrite
0x00
0xFF
OSTDSR
Oscillation Stop
Detection Status
Register
0x041
8
readwrite
0x00
0xFF
MOCOUTCR
MOCO User
Trimming Control
Register
0x061
8
readwrite
0x00
0xFF
HOCOUTCR
HOCO User
Trimming Control
Register
0x062
8
readwrite
0x00
0xFF
SNZCR
Snooze Control
Register
0x092
8
readwrite
0x00
0xFF
SNZEDCR
Snooze End
Control Register
0x094
8
readwrite
0x00
0xFF
SNZREQCR
Snooze Request
Control Register
0x098
32
readwrite
0x0000
0000
0xFFFF
FFFF
FLSTOP
Flash Operation
Control Register
0x09E
8
readwrite
0x00
0xFF
OPCCR
Operating Power
Control Register
0x0A0
8
readwrite
0x02
0xFF
MOSCWTCR
Main Clock
Oscillator Wait
Control Register
0x0A2
8
readwrite
0x05
0xFF
HOCOWTCR
High-Speed OnChip Oscillator
Wait Control
Register
0x0A5
8
readwrite
0x05
0xFF
Page 1071 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (3 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
SYSTEM
-
-
-
SOPCCR
PORT0,3-5
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
Sub Operating
Power Control
Register
0x0AA
8
readwrite
0x00
0xFF
RSTSR1
Reset Status
Register 1
0x0C0
16
readwrite
0x0000
0xFEF8
LVD1CR1
Voltage Monitor 1
Circuit Control
Register 1
0x0E0
8
readwrite
0x01
0xFF
LVD1SR
Voltage Monitor 1
Circuit Status
Register
0x0E1
8
readwrite
0x02
0xFF
LVD2CR1
Voltage Monitor 2
Circuit Control
Register 1
0x0E2
8
readwrite
0x01
0xFF
LVD2SR
Voltage Monitor 2
Circuit Status
Register
0x0E3
8
readwrite
0x02
0xFF
PRCR
Protect Register
0x3FE
16
readwrite
0x0000
0xFFFF
SYOCDCR
System Control
OCD Control
Register
0x40E
8
readwrite
0x00
0xFF
RSTSR0
Reset Status
Register 0
0x410
8
readwrite
0x00
0xF0
RSTSR2
Reset Status
Register 2
0x411
8
readwrite
0x00
0xFE
MOMCR
Main Clock
Oscillator Mode
Oscillation Control
Register
0x413
8
readwrite
0x00
0xFF
LVCMPCR
Voltage Monitor
Circuit Control
Register
0x417
8
readwrite
0x00
0xFF
LVDLVLR
Voltage Detection
Level Select
Register
0x418
8
readwrite
0x07
0xFF
LVD1CR0
Voltage Monitor 1
Circuit Control
Register 0
0x41A
8
readwrite
0x80
0xF7
LVD2CR0
Voltage Monitor 2
Circuit Control
Register 0
0x41B
8
readwrite
0x80
0xF7
SOSCCR
Sub-clock
Oscillator Control
Register
0x480
8
readwrite
0x01
0xFF
SOMCR
Sub-clock
Oscillator Mode
Control Register
0x481
8
readwrite
0x00
0xFF
LOCOCR
Low-Speed OnChip Oscillator
Control Register
0x490
8
readwrite
0x00
0xFF
LOCOUTCR
LOCO User
Trimming Control
Register
0x492
8
readwrite
0x00
0xFF
PCNTR1
Port Control
Register 1
0x00
32
readwrite
0x0000
0000
0xFFFF
FFFF
Page 1072 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (4 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
PORT0,3-5
-
-
-
PODR
PORT1,2
PFS
-
-
-
-
-
-
Address
offset
Size
Access
Reset
value
Reset
mask
Output Data
Register
0x00
16
readwrite
0x0000
0xFFFF
PDR
Data Direction
Register
0x02
16
readwrite
0x0000
0xFFFF
PCNTR2
Port Control
Register 2
0x04
32
readonly
0x0000
0000
0xFFFF
0000
PIDR
Input Data
Register
0x06
16
readonly
0x0000
0xFFFF
PCNTR3
Port Control
Register 3
0x08
32
writeonly
0x0000
0000
0xFFFF
FFFF
PORR
Output Reset
Register
0x08
16
writeonly
0x0000
0xFFFF
POSR
Output Set
Register
0x0A
16
writeonly
0x0000
0xFFFF
PCNTR1
Port Control
Register 1
0x00
32
readwrite
0x0000
0000
0xFFFF
FFFF
PODR
Output Data
Register
0x00
16
readwrite
0x0000
0xFFFF
PDR
Data Direction
Register
0x02
16
readwrite
0x0000
0xFFFF
PCNTR2
Port Control
Register 2
0x04
32
readonly
0x0000
0000
0xFFFF
0000
EIDR
Event Input Data
Register
0x04
16
readonly
0x0000
0x0000
PIDR
Input Data
Register
0x06
16
readonly
0x0000
0xFFFF
PCNTR3
Port Control
Register 3
0x08
32
writeonly
0x0000
0000
0xFFFF
FFFF
PORR
Output Reset
Register
0x08
16
writeonly
0x0000
0xFFFF
POSR
Output Set
Register
0x0A
16
writeonly
0x0000
0xFFFF
PCNTR4
Port Control
Register 4
0x0C
32
readwrite
0x0000
0000
0xFFFF
FFFF
EORR
Event Output
Reset Register
0x0C
16
writeonly
0x0000
0xFFFF
EOSR
Event Output Set
Register
0x0E
16
writeonly
0x0000
0xFFFF
P000PFS
P000 Pin Function
Control Register
0x000
32
readwrite
0x0000
0000
0xFFFF
FFFD
P000PFS_HA
P000 Pin Function
Control Register
0x002
16
readwrite
0x0000
0xFFF
D
P000PFS_BY
P000 Pin Function
Control Register
0x003
8
readwrite
0x00
0xFD
4
0x4
1-4
P00%sPFS
P00%s Pin
Function Control
Register
0x004
32
readwrite
0x0000
0000
0xFFFF
FFFD
4
0x4
1-4
P00%sPFS_HA
P00%s Pin
Function Control
Register
0x006
16
readwrite
0x0000
0xFFF
D
4
0x4
1-4
P00%sPFS_BY
P00%s Pin
Function Control
Register
0x007
8
readwrite
0x00
0xFD
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1073 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (5 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
Address
offset
Size
Access
Reset
value
Reset
mask
PFS
6
0x4
10-15
P0%sPFS
P0%s Pin
Function Control
Register
0x028
32
readwrite
0x0000
0000
0xFFFF
FFFD
6
0x4
10-15
P0%sPFS_HA
P0%s Pin
Function Control
Register
0x02A
16
readwrite
0x0000
0xFFF
D
6
0x4
10-15
P0%sPFS_BY
P0%s Pin
Function Control
Register
0x02B
8
readwrite
0x00
0xFD
-
-
-
P100PFS
P100 Pin Function
Control Register
0x040
32
readwrite
0x0000
0000
0xFFFF
FFFD
P100PFS_HA
P100 Pin Function
Control Register
0x042
16
readwrite
0x0000
0xFFF
D
P100PFS_BY
P100 Pin Function
Control Register
0x043
8
readwrite
0x00
0xFD
7
0x4
1-7
P10%sPFS
P10%s Pin
Function Control
Register
0x044
32
readwrite
0x0000
0000
0xFFFF
FFFD
7
0x4
1-7
P10%sPFS_HA
P10%s Pin
Function Control
Register
0x046
16
readwrite
0x0000
0xFFF
D
7
0x4
1-7
P10%sPFS_BY
P10%s Pin
Function Control
Register
0x047
8
readwrite
0x00
0xFD
-
-
-
P108PFS
P108 Pin Function
Control Register
0x060
32
readwrite
0x0001
0010
0xFFFF
FFFD
P108PFS_HA
P108 Pin Function
Control Register
0x062
16
readwrite
0x0010
0xFFF
D
P108PFS_BY
P108 Pin Function
Control Register
0x063
8
readwrite
0x10
0xFD
P109PFS
P109 Pin Function
Control Register
0x064
32
readwrite
0x0000
0000
0xFFFF
FFFD
P109PFS_HA
P109 Pin Function
Control Register
0x066
16
readwrite
0x0000
0xFFF
D
P109PFS_BY
P109 Pin Function
Control Register
0x067
8
readwrite
0x00
0xFD
4
0x4
10-13
P1%sPFS
P1%s Pin
Function Control
Register
0x068
32
readwrite
0x0000
0000
0xFFFF
FFFD
4
0x4
10-13
P1%sPFS_HA
P1%s Pin
Function Control
Register
0x06A
16
readwrite
0x0000
0xFFF
D
4
0x4
10-13
P1%sPFS_BY
P1%s Pin
Function Control
Register
0x06B
8
readwrite
0x00
0xFD
-
-
-
P200PFS
P200 Pin Function
Control Register
0x080
32
readwrite
0x0000
0000
0xFFFF
FFFD
P200PFS_HA
P200 Pin Function
Control Register
0x082
16
readwrite
0x0000
0xFFF
D
P200PFS_BY
P200 Pin Function
Control Register
0x083
8
readwrite
0x00
0xFD
P201PFS
P201 Pin Function
Control Register
0x084
32
readwrite
0x0000
0010
0xFFFF
FFFD
P201PFS_HA
P201 Pin Function
Control Register
0x086
16
readwrite
0x0010
0xFFF
D
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1074 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (6 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
Address
offset
Size
Access
Reset
value
Reset
mask
PFS
-
-
-
P201PFS_BY
P201 Pin Function
Control Register
0x087
8
readwrite
0x10
0xFD
3
0x4
4-6
P20%sPFS
P20%s Pin
Function Control
Register
0x090
32
readwrite
0x0000
0000
0xFFFF
FFFD
3
0x4
4-6
P20%sPFS_HA
P20%s Pin
Function Control
Register
0x092
16
readwrite
0x0000
0xFFF
D
3
0x4
4-6
P20%sPFS_BY
P20%s Pin
Function Control
Register
0x093
8
readwrite
0x00
0xFD
4
0x4
12-15
P2%sPFS
P2%s Pin
Function Control
Register
0x0B0
32
readwrite
0x0000
0000
0xFFFF
FFFD
4
0x4
12-15
P2%sPFS_HA
P2%s Pin
Function Control
Register
0x0B2
16
readwrite
0x0000
0xFFF
D
4
0x4
12-15
P2%sPFS_BY
P2%s Pin
Function Control
Register
0x0B3
8
readwrite
0x00
0xFD
-
-
-
P300PFS
P300 Pin Function
Control Register
0x0C0
32
readwrite
0x0001
0010
0xFFFF
FFFD
P300PFS_HA
P300 Pin Function
Control Register
0x0C2
16
readwrite
0x0010
0xFFF
D
P300PFS_BY
P300 Pin Function
Control Register
0x0C3
8
readwrite
0x10
0xFD
4
0x4
1-4
P30%sPFS
P30%s Pin
Function Control
Register
0x0C4
32
readwrite
0x0000
0000
0xFFFF
FFFD
4
0x4
1-4
P30%sPFS_HA
P30%s Pin
Function Control
Register
0x0C6
16
readwrite
0x0000
0xFFF
D
4
0x4
1-4
P30%sPFS_BY
P30%s Pin
Function Control
Register
0x0C7
8
readwrite
0x00
0xFD
4
0x4
0-3
P40%sPFS
P40%s Pin
Function Control
Register
0x100
32
readwrite
0x0000
0000
0xFFFF
FFFD
4
0x4
0-3
P40%sPFS_HA
P40%s Pin
Function Control
Register
0x102
16
readwrite
0x0000
0xFFF
D
4
0x4
0-3
P40%sPFS_BY
P40%s Pin
Function Control
Register
0x103
8
readwrite
0x00
0xFD
3
0x4
7-9
P40%sPFS
P40%s Pin
Function Control
Register
0x11C
32
readwrite
0x0000
0000
0xFFFF
FFFD
3
0x4
7-9
P40%sPFS_HA
P40%s Pin
Function Control
Register
0x11E
16
readwrite
0x0000
0xFFF
D
3
0x4
7-9
P40%sPFS_BY
P40%s Pin
Function Control
Register
0x11F
8
readwrite
0x00
0xFD
2
0x4
10,11
P4%sPFS
P4%s Pin
Function Control
Register
0x128
32
readwrite
0x0000
0000
0xFFFF
FFFD
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1075 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (7 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
Address
offset
Size
Access
Reset
value
Reset
mask
PFS
2
0x4
10,11
P4%sPFS_HA
P4%s Pin
Function Control
Register
0x12A
16
readwrite
0x0000
0xFFF
D
2
0x4
10,11
P4%sPFS_BY
P4%s Pin
Function Control
Register
0x12B
8
readwrite
0x00
0xFD
3
0x4
0-2
P50%sPFS
P50%s Pin
Function Control
Register
0x140
32
readwrite
0x0000
0000
0xFFFF
FFFD
3
0x4
0-2
P50%sPFS_HA
P50%s Pin
Function Control
Register
0x142
16
readwrite
0x0000
0xFFF
D
3
0x4
0-2
P50%sPFS_BY
P50%s Pin
Function Control
Register
0x143
8
readwrite
0x00
0xFD
PMISC
-
-
-
PWPR
Write-Protect
Register
0x03
8
readwrite
0x80
0xFF
ELC
-
-
-
ELCR
Event Link
0x00
Controller Register
8
readwrite
0x00
0xFF
2
0x2
0,1
ELSEGR%s
Event Link
Software Event
Generation
Register %s
0x02
8
readwrite
0x80
0xFF
4
0x4
0-3
ELSR%s
Event Link Setting
Register %s
0x10
16
readwrite
0x0000
0xFFFF
2
0x4
8,9
ELSR%s
Event Link Setting
Register %s
0x30
16
readwrite
0x0000
0xFFFF
-
-
-
ELSR12
Event Link Setting
Register 12
0x40
16
readwrite
0x0000
0xFFFF
2
0x4
14,15
ELSR%s
Event Link Setting
Register %s
0x48
16
readwrite
0x0000
0xFFFF
-
-
-
ELSR18
Event Link Setting
Register 18
0x58
16
readwrite
0x0000
0xFFFF
POEG
2
0x100
A,B
POEGG%s
POEG Group %s
Setting Register
0x00
32
readwrite
0x0000
0000
0xFFFF
FFFF
RTC
-
-
-
R64CNT
64-Hz Counter
0x00
8
readonly
0x00
0x80
RSECCNT
Second Counter
0x02
8
readwrite
0x00
0x00
BCNT0
Binary Counter 0
0x02
8
readwrite
0x00
0x00
RMINCNT
Minute Counter
0x04
8
readwrite
0x00
0x00
BCNT1
Binary Counter 1
0x04
8
readwrite
0x00
0x00
RHRCNT
Hour Counter
0x06
8
readwrite
0x00
0x00
BCNT2
Binary Counter 2
0x06
8
readwrite
0x00
0x00
RWKCNT
Day-of-Week
Counter
0x08
8
readwrite
0x00
0x00
BCNT3
Binary Counter 3
0x08
8
readwrite
0x00
0x00
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1076 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (8 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
Address
offset
Size
Access
RTC
-
-
-
RDAYCNT
Day Counter
0x0A
8
RMONCNT
Month Counter
0x0C
RYRCNT
Year Counter
RSECAR
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Reset
value
Reset
mask
readwrite
0x00
0xC0
8
readwrite
0x00
0xE0
0x0E
16
readwrite
0x0000
0xFF00
Second Alarm
Register
0x10
8
readwrite
0x00
0x00
BCNT0AR
Binary Counter 0
Alarm Register
0x10
8
readwrite
0x00
0x00
RMINAR
Minute Alarm
Register
0x12
8
readwrite
0x00
0x00
BCNT1AR
Binary Counter 1
Alarm Register
0x12
8
readwrite
0x00
0x00
RHRAR
Hour Alarm
Register
0x14
8
readwrite
0x00
0x00
BCNT2AR
Binary Counter 2
Alarm Register
0x14
8
readwrite
0x00
0x00
RWKAR
Day-of-Week
Alarm Register
0x16
8
readwrite
0x00
0x00
BCNT3AR
Binary Counter 3
Alarm Register
0x16
8
readwrite
0x00
0x00
RDAYAR
Date Alarm
Register
0x18
8
readwrite
0x00
0x00
BCNT0AER
Binary Counter 0
Alarm Enable
Register
0x18
8
readwrite
0x00
0x00
RMONAR
Month Alarm
Register
0x1A
8
readwrite
0x00
0x00
BCNT1AER
Binary Counter 1
Alarm Enable
Register
0x1A
8
readwrite
0x00
0x00
RYRAR
Year Alarm
Register
0x1C
16
readwrite
0x0000
0xFF00
BCNT2AER
Binary Counter 2
Alarm Enable
Register
0x1C
16
readwrite
0x0000
0xFF00
RYRAREN
Year Alarm Enable
Register
0x1E
8
readwrite
0x00
0x00
BCNT3AER
Binary Counter 3
Alarm Enable
Register
0x1E
8
readwrite
0x00
0x00
RCR1
RTC Control
Register 1
0x22
8
readwrite
0x00
0x0A
RCR2
RTC Control
Register 2
0x24
8
readwrite
0x00
0x0E
RCR4
RTC Control
Register 4
0x28
8
readwrite
0x00
0xFE
RFRH
Frequency
Register H
0x2A
16
readwrite
0x0000
0xFFFE
RFRL
Frequency
Register L
0x2C
16
readwrite
0x0000
0x0000
Page 1077 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (9 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
RTC
-
-
-
RADJ
WDT
-
-
-
IWDT
CAC
MSTP
CAN0
-
-
-
-
-
-
-
-
-
Address
offset
Size
Access
Reset
value
Reset
mask
Time Error
Adjustment
Register
0x2E
8
readwrite
0x00
0x00
WDTRR
WDT Refresh
Register
0x00
8
readwrite
0xFF
0xFF
WDTCR
WDT Control
Register
0x02
16
readwrite
0x33F3
0xFFFF
WDTSR
WDT Status
Register
0x04
16
readwrite
0x0000
0xFFFF
WDTRCR
WDT Reset
Control Register
0x06
8
readwrite
0x80
0xFF
WDTCSTPR
WDT Count Stop
Control Register
0x08
8
readwrite
0x80
0xFF
IWDTRR
IWDT Refresh
Register
0x00
8
readwrite
0xFF
0xFF
IWDTSR
IWDT Status
Register
0x04
16
readwrite
0x0000
0xFFFF
CACR0
CAC Control
Register 0
0x00
8
readwrite
0x00
0xFF
CACR1
CAC Control
Register 1
0x01
8
readwrite
0x00
0xFF
CACR2
CAC Control
Register 2
0x02
8
readwrite
0x00
0xFF
CAICR
CAC Interrupt
Control Register
0x03
8
readwrite
0x00
0xFF
CASTR
CAC Status
Register
0x04
8
readonly
0x00
0xFF
CAULVR
CAC Upper-Limit
Value Setting
Register
0x06
16
readwrite
0x0000
0xFFFF
CALLVR
CAC Lower-Limit
Value Setting
Register
0x08
16
readwrite
0x0000
0xFFFF
CACNTBR
CAC Counter
Buffer Register
0x0A
16
readonly
0x0000
0xFFFF
MSTPCRB
Module Stop
Control Register B
0x00
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
MSTPCRC
Module Stop
Control Register C
0x04
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
MSTPCRD
Module Stop
Control Register D
0x08
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
32
0x10
0-31
MB%s_ID
Mailbox Register
0x200
32
readwrite
0x0000
0000
0x0000
0000
32
0x10
0-31
MB%s_DL
Mailbox Register
0x204
16
readwrite
0x0000
0x0000
32
0x10
0-31
MB%s_D0
Mailbox Register
0x206
8
readwrite
0x00
0x00
32
0x10
0-31
MB%s_D1
Mailbox Register
0x207
8
readwrite
0x00
0x00
32
0x10
0-31
MB%s_D2
Mailbox Register
0x208
8
readwrite
0x00
0x00
32
0x10
0-31
MB%s_D3
Mailbox Register
0x209
8
readwrite
0x00
0x00
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1078 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (10 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
Address
offset
Size
Access
Reset
value
Reset
mask
CAN0
32
0x10
0-31
MB%s_D4
Mailbox Register
0x20A
8
readwrite
0x00
0x00
32
0x10
0-31
MB%s_D5
Mailbox Register
0x20B
8
readwrite
0x00
0x00
32
0x10
0-31
MB%s_D6
Mailbox Register
0x20C
8
readwrite
0x00
0x00
32
0x10
0-31
MB%s_D7
Mailbox Register
0x20D
8
readwrite
0x00
0x00
32
0x10
0-31
MB%s_TS
Mailbox Register
0x20E
16
readwrite
0x0000
0x0000
8
0x4
0-7
MKR[%s]
Mask Register
0x400
32
readwrite
0x0000
0000
0x0000
0000
2
0x4
0,1
FIDCR%s
FIFO Received ID
Compare
Registers
0x420
32
readwrite
0x0000
0000
0x0000
0000
-
-
-
MKIVLR
Mask Invalid
Register
0x428
32
readwrite
0x0000
0000
0x0000
0000
MIER
Mailbox Interrupt
Enable Register
(Normal mailbox
mode)
0x42C
32
readwrite
0x0000
0000
0x0000
0000
MIER_FIFO
Mailbox Interrupt
Enable Register
(FIFO mailbox
mode)
0x42C
32
readwrite
0x0000
0000
0x0000
0000
32
0x1
0-31
MCTL_TX[%s]
Message Control
Register -Transmit
mode (when the
TRMREQ bit is 1
and the RECREQ
bit is 0)
0x820
8
readwrite
0x00
0xFF
32
0x1
0-31
MCTL_RX[%s]
Message Control
Register - Receive
mode (when the
TRMREQ bit is 0
and the RECREQ
bit is 1)
0x820
8
readwrite
0x00
0xFF
-
-
-
CTLR
Control Register
0x840
16
readwrite
0x0500
0xFFFF
STR
Status Register
0x842
16
readonly
0x0500
0xFFFF
BCR
Bit Configuration
Register
0x844
32
readwrite
0x0000
0000
0xFFFF
FFFF
RFCR
Receive FIFO
Control Register
0x848
8
readwrite
0x80
0xFF
RFPCR
Receive FIFO
Pointer Control
Register
0x849
8
writeonly
0x00
0x00
TFCR
Transmit FIFO
Control Register
0x84A
8
readwrite
0x80
0xFF
TFPCR
Transmit FIFO
Pointer Control
Register
0x84B
8
writeonly
0x00
0x00
EIER
Error Interrupt
Enable Register
0x84C
8
readwrite
0x00
0xFF
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1079 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (11 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
CAN0
-
-
-
EIFR
IIC0
-
-
-
Address
offset
Size
Access
Reset
value
Reset
mask
Error Interrupt
Factor Judge
Register
0x84D
8
readwrite
0x00
0xFF
RECR
Receive Error
Count Register
0x84E
8
readonly
0x00
0xFF
TECR
Transmit Error
Count Register
0x84F
8
readonly
0x00
0xFF
ECSR
Error Code Store
Register
0x850
8
readwrite
0x00
0xFF
CSSR
Channel Search
Support Register
0x851
8
readwrite
0x00
0x00
MSSR
Mailbox Search
Status Register
0x852
8
readonly
0x80
0xFF
MSMR
Mailbox Search
Mode Register
0x853
8
readwrite
0x00
0xFF
TSR
Time Stamp
Register
0x854
16
readonly
0x0000
0xFFFF
AFSR
Acceptance Filter
Support Register
0x856
16
readwrite
0x0000
0x0000
TCR
Test Control
Register
0x858
8
readwrite
0x00
0xFF
ICCR1
I2C Bus Control
Register 1
0x00
8
readwrite
0x1F
0xFF
ICCR2
I2C Bus Control
Register 2
0x01
8
readwrite
0x00
0xFF
ICMR1
I2C Bus Mode
Register 1
0x02
8
readwrite
0x08
0xFF
ICMR2
I2C Bus Mode
Register 2
0x03
8
readwrite
0x06
0xFF
ICMR3
I2C Bus Mode
Register 3
0x04
8
readwrite
0x00
0xFF
ICFER
I2C Bus Function
Enable Register
0x05
8
readwrite
0x72
0xFF
ICSER
I2C Bus Status
Enable Register
0x06
8
readwrite
0x09
0xFF
ICIER
I2C Bus Interrupt
Enable Register
0x07
8
readwrite
0x00
0xFF
ICSR1
I2C Bus Status
Register 1
0x08
8
readwrite
0x00
0xFF
ICSR2
I2C Bus Status
Register 2
0x09
8
readwrite
0x00
0xFF
3
0x2
0-2
SARL%s
Slave Address
Register L%s
0x0A
8
readwrite
0x00
0xFF
3
0x2
0-2
SARU%s
Slave Address
Register U%s
0x0B
8
readwrite
0x00
0xFF
-
-
-
ICBRL
I2C Bus Bit Rate
Low-Level
Register
0x10
8
readwrite
0xFF
0xFF
ICBRH
I2C Bus Bit Rate
High-Level
Register
0x11
8
readwrite
0xFF
0xFF
ICDRT
I2C Bus Transmit
Data Register
0x12
8
readwrite
0xFF
0xFF
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1080 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (12 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
IIC0
-
-
-
ICDRR
IIC1
DOC
ADC140
-
-
-
Address
offset
Size
Access
Reset
value
Reset
mask
I2C Bus Receive
Data Register
0x13
8
readonly
0x00
0xFF
ICWUR
I2C Bus Wake Up
Unit Register
0x16
8
readwrite
0x10
0xFF
ICWUR2
Reserved
0x17
8
readonly
0xFF
0xFF
ICCR1
I2C Bus Control
Register 1
0x00
8
readwrite
0x1F
0xFF
ICCR2
I2C Bus Control
Register 2
0x01
8
readwrite
0x00
0xFF
ICMR1
I2C Bus Mode
Register 1
0x02
8
readwrite
0x08
0xFF
ICMR2
I2C Bus Mode
Register 2
0x03
8
readwrite
0x06
0xFF
ICMR3
I2C Bus Mode
Register 3
0x04
8
readwrite
0x00
0xFF
ICFER
I2C Bus Function
Enable Register
0x05
8
readwrite
0x72
0xFF
ICSER
I2C Bus Status
Enable Register
0x06
8
readwrite
0x09
0xFF
ICIER
I2C Bus Interrupt
Enable Register
0x07
8
readwrite
0x00
0xFF
ICSR1
I2C Bus Status
Register 1
0x08
8
readwrite
0x00
0xFF
ICSR2
I2C Bus Status
Register 2
0x09
8
readwrite
0x00
0xFF
3
0x2
0-2
SARL%s
Slave Address
Register L%s
0x0A
8
readwrite
0x00
0xFF
3
0x2
0-2
SARU%s
Slave Address
Register U%s
0x0B
8
readwrite
0x00
0xFF
-
-
-
ICBRL
I2C Bus Bit Rate
Low-Level
Register
0x10
8
readwrite
0xFF
0xFF
ICBRH
I2C Bus Bit Rate
High-Level
Register
0x11
8
readwrite
0xFF
0xFF
ICDRT
I2C Bus Transmit
Data Register
0x12
8
readwrite
0xFF
0xFF
ICDRR
I2C Bus Receive
Data Register
0x13
8
readonly
0x00
0xFF
DOCR
DOC Control
Register
0x00
8
readwrite
0x00
0xFF
DODIR
DOC Data Input
Register
0x02
16
readwrite
0x0000
0xFFFF
DODSR
DOC Data Setting
Register
0x04
16
readwrite
0x0000
0xFFFF
ADCSR
A/D Control
Register
0x000
16
readwrite
0x0000
0xFFFF
ADANSA0
A/D Channel
Select Register A0
0x004
16
readwrite
0x0000
0xFFFF
ADANSA1
A/D Channel
Select Register A1
0x006
16
readwrite
0x0000
0xFFFF
-
-
-
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1081 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (13 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
Address
offset
Size
Access
Reset
value
Reset
mask
ADC140
-
-
-
ADADS0
A/D-Converted
Value Addition/
Average Channel
Select Register 0
0x008
16
readwrite
0x0000
0xFFFF
ADADS1
A/D-Converted
Value Addition/
Average Channel
Select Register 1
0x00A
16
readwrite
0x0000
0xFFFF
ADADC
A/D-Converted
Value Addition/
Average Count
Select Register
0x00C
8
readwrite
0x00
0xFF
ADCER
A/D Control
Extended Register
0x00E
16
readwrite
0x0000
0xFFFF
ADSTRGR
A/D Conversion
Start Trigger
Select Register
0x010
16
readwrite
0x0000
0xFFFF
ADEXICR
A/D Conversion
Extended Input
Control Register
0x012
16
readwrite
0x0000
0xFFFF
ADANSB0
A/D Channel
Select Register B0
0x014
16
readwrite
0x0000
0xFFFF
ADANSB1
A/D Channel
Select Register B1
0x016
16
readwrite
0x0000
0xFFFF
ADDBLDR
A/D Data
Duplication
Register
0x018
16
readonly
0x0000
0xFFFF
ADTSDR
A/D Temperature
Sensor Data
Register
0x01A
16
readonly
0x0000
0xFFFF
ADOCDR
A/D Internal
Reference Voltage
Data Register
0x01C
16
readonly
0x0000
0xFFFF
ADRD
A/D SelfDiagnosis Data
Register
0x01E
16
readonly
0x0000
0xFFFF
11
0x2
0-10
ADDR%s
A/D Data Register
%s
0x020
16
readonly
0x0000
0xFFFF
7
0x2
16-22
ADDR%s
A/D Data Register
%s
0x040
16
readonly
0x0000
0xFFFF
-
-
-
ADDISCR
A/D Disconnection
Detection Control
Register
0x07A
8
readwrite
0x00
0xFF
ADGSPCR
A/D Group Scan
Priority Control
Register
0x080
16
readwrite
0x0000
0xFFFF
ADDBLDRA
A/D Data
Duplication
Register A
0x084
16
readonly
0x0000
0xFFFF
ADDBLDRB
A/D Data
Duplication
Register B
0x086
16
readonly
0x0000
0xFFFF
ADHVREFCNT
A/D HighPotential/LowPotential
Reference Voltage
Control Register
0x08A
8
readwrite
0x00
0xFF
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1082 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (14 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
ADC140
-
-
-
ADWINMON
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
A/D Compare
Function Window
A/B Status Monitor
Register
0x08C
8
readonly
0x00
0xFF
ADCMPCR
A/D Compare
Function Control
Register
0x090
16
readwrite
0x0000
0xFFFF
ADCMPANSER
A/D Compare
Function Window
A Extended Input
Select Register
0x092
8
readwrite
0x00
0xFF
ADCMPLER
A/D Compare
Function Window
A Extended Input
Comparison
Condition Setting
Register
0x093
8
readwrite
0x00
0xFF
ADCMPANSR0
A/D Compare
Function Window
A Channel Select
Register 0
0x094
16
readwrite
0x0000
0xFFFF
ADCMPANSR1
A/D Compare
Function Window
A Channel Select
Register 1
0x096
16
readwrite
0x0000
0xFFFF
ADCMPLR0
A/D Compare
Function Window
A Comparison
Condition Setting
Register 0
0x098
16
readwrite
0x0000
0xFFFF
ADCMPLR1
A/D Compare
Function Window
A Comparison
Condition Setting
Register 1
0x09A
16
readwrite
0x0000
0xFFFF
ADCMPDR0
A/D Compare
Function Window
A Lower-Side
Level Setting
Register
0x09C
16
readwrite
0x0000
0xFFFF
ADCMPDR1
A/D Compare
Function Window
A Upper-Side
Level Setting
Register
0x09E
16
readwrite
0x0000
0xFFFF
ADCMPSR0
A/D Compare
Function Window
A Channel Status
Register 0
0x0A0
16
readwrite
0x0000
0xFFFF
ADCMPSR1
A/D Compare
Function Window
A Channel Status
Register 1
0x0A2
16
readwrite
0x0000
0xFFFF
ADCMPSER
A/D Compare
Function Window
A Extended Input
Channel Status
Register
0x0A4
8
readwrite
0x00
0xFF
Page 1083 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (15 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
ADC140
-
-
-
ADCMPBNSR
DAC12
SCI0
Address
offset
Size
Access
Reset
value
Reset
mask
A/D Compare
Function Window
B Channel
Selection Register
0x0A6
8
readwrite
0x00
0xFF
ADWINLLB
A/D Compare
Function Window
B Lower-Side
Level Setting
Register
0x0A8
16
readwrite
0x0000
0xFFFF
ADWINULB
A/D Compare
Function Window
B Upper-Side
Level Setting
Register
0x0AA
16
readwrite
0x0000
0xFFFF
ADCMPBSR
A/D Compare
Function Window
B Status Register
0x0AC
8
readwrite
0x00
0xFF
ADSSTRL
A/D Sampling
State Register L
0x0DD
8
readwrite
0x0D
0xFF
ADSSTRT
A/D Sampling
State Register T
0x0DE
8
readwrite
0x0D
0xFF
ADSSTRO
A/D Sampling
State Register O
0x0DF
8
readwrite
0x0D
0xFF
11
0x1
00-10
ADSSTR%s
A/D Sampling
State Register %s
0x0E0
8
readwrite
0x0D
0xFF
-
-
-
DADR0
D/A Data Register
0
0x00
16
readwrite
0x0000
0xFFFF
DACR
D/A Control
Register
0x04
8
readwrite
0x1F
0xFF
DADPR
DADR0 Format
Select Register
0x05
8
readwrite
0x00
0xFF
DAADSCR
D/A-A/D
Synchronous Start
Control Register
0x06
8
readwrite
0x00
0xFF
DAVREFCR
D/A VREF Control
Register
0x07
8
readwrite
0x00
0xFF
SMR
Serial Mode
Register
(SCMR.SMIF = 0)
0x00
8
readwrite
0x00
0xFF
SMR_SMCI
Serial mode
register
(SCMR.SMIF = 1)
0x00
8
readwrite
0x00
0xFF
BRR
Bit Rate Register
0x01
8
readwrite
0xFF
0xFF
SCR
Serial Control
Register
(SCMR.SMIF = 0)
0x02
8
readwrite
0x00
0xFF
SCR_SMCI
Serial Control
Register
(SCMR.SMIF =1)
0x02
8
readwrite
0x00
0xFF
TDR
Transmit Data
Register
0x03
8
readwrite
0xFF
0xFF
SSR
Serial Status
Register
(SCMR.SMIF = 0
and FCR.FM=0)
0x04
8
readwrite
0x84
0xFF
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1084 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (16 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
SCI0
-
-
-
SSR_FIFO
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
Serial Status
Register
(SCMR.SMIF = 0
and FCR.FM=1)
0x04
8
readwrite
0x80
0xFD
SSR_SMCI
Serial Status
Register
(SCMR.SMIF = 1)
0x04
8
readwrite
0x84
0xFF
RDR
Receive Data
Register
0x05
8
readonly
0x00
0xFF
SCMR
Smart Card Mode
Register
0x06
8
readwrite
0xF2
0xFF
SEMR
Serial Extended
Mode Register
0x07
8
readwrite
0x00
0xFF
SNFR
Noise Filter
Setting Register
0x08
8
readwrite
0x00
0xFF
SIMR1
I2C Mode Register
1
0x09
8
readwrite
0x00
0xFF
SIMR2
I2C Mode Register
2
0x0A
8
readwrite
0x00
0xFF
SIMR3
IIC Mode Register
3
0x0B
8
readwrite
0x00
0xFF
SISR
IIC Status Register 0x0C
8
readonly
0x00
0xCB
SPMR
SPI Mode
Register
0x0D
8
readwrite
0x00
0xFF
TDRHL
Transmit 9-bit
Data Register
0x0E
16
readwrite
0xFFFF
0xFFFF
FTDRHL
Transmit FIFO
Data Register HL
0x0E
16
writeonly
0xFFFF
0xFFFF
FTDRH
Transmit FIFO
Data Register H
0x0E
8
writeonly
0xFF
0xFF
FTDRL
Transmit FIFO
Data Register L
0x0F
8
writeonly
0xFF
0xFF
RDRHL
Receive 9-bit Data
Register
0x10
16
readonly
0x0000
0xFFFF
FRDRHL
Receive FIFO
Data Register HL
0x10
16
readonly
0x0000
0xFFFF
FRDRH
Receive FIFO
Data Register H
0x10
8
readonly
0x00
0xFF
FRDRL
Receive FIFO
Data Register L
0x11
8
readonly
0x00
0xFF
MDDR
Modulation Duty
Register
0x12
8
readwrite
0xFF
0xFF
DCCR
Data Compare
Match Control
Register
0x13
8
readwrite
0x40
0xFF
FCR
FIFO Control
Register
0x14
16
readwrite
0xF800
0xFFFF
FDR
FIFO Data Count
Register
0x16
16
readonly
0x0000
0xFFFF
LSR
Line Status
Register
0x18
16
readonly
0x0000
0xFFFF
CDR
Compare Match
Data Register
0x1A
16
readwrite
0x0000
0xFFFF
Page 1085 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (17 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
SCI0
-
-
-
SPTR
SCI1,9
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
Serial Port
Register
0x1C
8
readwrite
0x03
0xFF
SMR
Serial Mode
Register
(SCMR.SMIF = 0)
0x00
8
readwrite
0x00
0xFF
SMR_SMCI
Serial mode
register
(SCMR.SMIF = 1)
0x00
8
readwrite
0x00
0xFF
BRR
Bit Rate Register
0x01
8
readwrite
0xFF
0xFF
SCR
Serial Control
Register
(SCMR.SMIF = 0)
0x02
8
readwrite
0x00
0xFF
SCR_SMCI
Serial Control
Register
(SCMR.SMIF =1)
0x02
8
readwrite
0x00
0xFF
TDR
Transmit Data
Register
0x03
8
readwrite
0xFF
0xFF
SSR
Serial Status
Register
(SCMR.SMIF = 0
and FCR.FM=0)
0x04
8
readwrite
0x84
0xFF
SSR_SMCI
Serial Status
Register
(SCMR.SMIF = 1)
0x04
8
readwrite
0x84
0xFF
RDR
Receive Data
Register
0x05
8
readonly
0x00
0xFF
SCMR
Smart Card Mode
Register
0x06
8
readwrite
0xF2
0xFF
SEMR
Serial Extended
Mode Register
0x07
8
readwrite
0x00
0xFF
SNFR
Noise Filter
Setting Register
0x08
8
readwrite
0x00
0xFF
SIMR1
I2C Mode Register
1
0x09
8
readwrite
0x00
0xFF
SIMR2
I2C Mode Register
2
0x0A
8
readwrite
0x00
0xFF
SIMR3
IIC Mode Register
3
0x0B
8
readwrite
0x00
0xFF
SISR
IIC Status Register 0x0C
8
readonly
0x00
0xCB
SPMR
SPI Mode
Register
0x0D
8
readwrite
0x00
0xFF
TDRHL
Transmit 9-bit
Data Register
0x0E
16
readwrite
0xFFFF
0xFFFF
RDRHL
Receive 9-bit Data
Register
0x10
16
readonly
0x0000
0xFFFF
MDDR
Modulation Duty
Register
0x12
8
readwrite
0xFF
0xFF
DCCR
Data Compare
Match Control
Register
0x13
8
readwrite
0x40
0xFF
CDR
Compare Match
Data Register
0x1A
16
readwrite
0x0000
0xFFFF
Page 1086 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (18 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
SCI1,9
-
-
-
SPTR
SPI0,1
-
-
-
CRC
GPT320
-
-
-
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
Serial Port
Register
0x1C
8
readwrite
0x03
0xFF
SPCR
SPI Control
Register
0x00
8
readwrite
0x00
0xFF
SSLP
SPI Slave Select
Polarity Register
0x01
8
readwrite
0x00
0xFF
SPPCR
SPI Pin Control
Register
0x02
8
readwrite
0x00
0xFF
SPSR
SPI Status
Register
0x03
8
readwrite
0x20
0xFF
SPDR
SPI Data Register
0x04
32
readwrite
0x0000
0000
0xFFFF
FFFF
SPDR_HA
SPI Data Register
(halfword access )
0x04
16
readwrite
0x0000
0xFFFF
SPBR
SPI Bit Rate
Register
0x0A
8
readwrite
0xFF
0xFF
SPDCR
SPI Data Control
Register
0x0B
8
readwrite
0x00
0xFF
SPCKD
SPI Clock Delay
Register
0x0C
8
readwrite
0x00
0xFF
SSLND
SPI Slave Select
Negation Delay
Register
0x0D
8
readwrite
0x00
0xFF
SPND
SPI Next-Access
Delay Register
0x0E
8
readwrite
0x00
0xFF
SPCR2
SPI Control
Register 2
0x0F
8
readwrite
0x00
0xFF
SPCMD0
SPI Command
Register 0
0x10
16
readwrite
0x070D
0xFFFF
CRCCR0
CRC Control
Register0
0x00
8
readwrite
0x00
0xFF
CRCCR1
CRC Control
Register1
0x01
8
readwrite
0x00
0xFF
CRCDIR
CRC Data Input
Register
0x04
32
readwrite
0x0000
0000
0xFFFF
FFFF
CRCDIR_BY
CRC Data Input
Register (byte
access)
0x04
8
readwrite
0x00
0xFF
CRCDOR
CRC Data Output
Register
0x08
32
readwrite
0x0000
0000
0xFFFF
FFFF
CRCDOR_HA
CRC Data Output
Register (halfword
access)
0x08
16
readwrite
0x0000
0xFFFF
CRCDOR_BY
CRC Data Output
Register (byte
access)
0x08
8
readwrite
0x00
0xFF
CRCSAR
Snoop Address
Register
0x0C
16
readwrite
0x0000
0xFFFF
GTWP
General PWM
Timer WriteProtection
Register
0x00
32
readwrite
0x0000
0000
0xFFFF
FFFF
Page 1087 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (19 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
GPT320
-
-
-
GTSTR
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
General PWM
Timer Software
Start Register
0x04
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTSTP
General PWM
Timer Software
Stop Register
0x08
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTCLR
General PWM
Timer Software
Clear Register
0x0C
32
writeonly
0x0000
0000
0xFFFF
FFFF
GTSSR
General PWM
Timer Start Source
Select Register
0x10
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTPSR
General PWM
Timer Stop Source
Select Register
0x14
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTCSR
General PWM
Timer Clear
Source Select
Register
0x18
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTUPSR
General PWM
Timer Up Count
Source Select
Register
0x1C
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTDNSR
General PWM
Timer Down Count
Source Select
Register
0x20
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTICASR
General PWM
Timer Input
Capture Source
Select Register A
0x24
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTICBSR
General PWM
Timer Input
Capture Source
Select Register B
0x28
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTCR
General PWM
Timer Control
Register
0x2C
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTUDDTYC
General PWM
Timer Count
Direction and Duty
Setting Register
0x30
32
readwrite
0x0000
0001
0xFFFF
FFFF
GTIOR
General PWM
Timer I/O Control
Register
0x34
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTINTAD
General PWM
Timer Interrupt
Output Setting
Register
0x38
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTST
General PWM
Timer Status
Register
0x3C
32
readwrite
0x0000
8000
0xFFFF
FFFF
GTBER
General PWM
Timer Buffer
Enable Register
0x40
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTCNT
General PWM
Timer Counter
0x48
32
readwrite
0x0000
0000
0xFFFF
FFFF
Page 1088 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (20 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
GPT320
-
-
-
GTCCRA
GPT161-6
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
General PWM
Timer Compare
Capture Register
A
0x4C
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTCCRB
General PWM
Timer Compare
Capture Register
B
0x50
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTCCRC
General PWM
Timer Compare
Capture Register
C
0x54
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTCCRE
General PWM
Timer Compare
Capture Register
E
0x58
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTCCRD
General PWM
Timer Compare
Capture Register
D
0x5C
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTCCRF
General PWM
Timer Compare
Capture Register
F
0x60
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTPR
General PWM
Timer Cycle
Setting Register
0x64
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTPBR
General PWM
Timer Cycle
Setting Buffer
Register
0x68
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTDTCR
General PWM
Timer Dead Time
Control Register
0x88
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTDVU
General PWM
Timer Dead Time
Value Register U
0x8C
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTWP
General PWM
Timer WriteProtection
Register
0x00
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTSTR
General PWM
Timer Software
Start Register
0x04
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTSTP
General PWM
Timer Software
Stop Register
0x08
32
readwrite
0xFFFF
FFFF
0xFFFF
FFFF
GTCLR
General PWM
Timer Software
Clear Register
0x0C
32
writeonly
0x0000
0000
0xFFFF
FFFF
GTSSR
General PWM
Timer Start Source
Select Register
0x10
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTPSR
General PWM
Timer Stop Source
Select Register
0x14
32
readwrite
0x0000
0000
0xFFFF
FFFF
Page 1089 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (21 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
GPT161-6
-
-
-
GTCSR
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
General PWM
Timer Clear
Source Select
Register
0x18
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTUPSR
General PWM
Timer Up Count
Source Select
Register
0x1C
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTDNSR
General PWM
Timer Down Count
Source Select
Register
0x20
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTICASR
General PWM
Timer Input
Capture Source
Select Register A
0x24
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTICBSR
General PWM
Timer Input
Capture Source
Select Register B
0x28
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTCR
General PWM
Timer Control
Register
0x2C
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTUDDTYC
General PWM
Timer Count
Direction and Duty
Setting Register
0x30
32
readwrite
0x0000
0001
0xFFFF
FFFF
GTIOR
General PWM
Timer I/O Control
Register
0x34
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTINTAD
General PWM
Timer Interrupt
Output Setting
Register
0x38
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTST
General PWM
Timer Status
Register
0x3C
32
readwrite
0x0000
8000
0xFFFF
FFFF
GTBER
General PWM
Timer Buffer
Enable Register
0x40
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTCNT
General PWM
Timer Counter
0x48
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTCCRA
General PWM
Timer Compare
Capture Register
A
0x4C
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
GTCCRB
General PWM
Timer Compare
Capture Register
B
0x50
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
GTCCRC
General PWM
Timer Compare
Capture Register
C
0x54
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
GTCCRE
General PWM
Timer Compare
Capture Register
E
0x58
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
Page 1090 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (22 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
Address
offset
Size
Access
Reset
value
Reset
mask
GPT161-6
-
-
-
GTCCRD
General PWM
Timer Compare
Capture Register
D
0x5C
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
GTCCRF
General PWM
Timer Compare
Capture Register
F
0x60
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
GTPR
General PWM
Timer Cycle
Setting Register
0x64
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
GTPBR
General PWM
Timer Cycle
Setting Buffer
Register
0x68
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
GTDTCR
General PWM
Timer Dead Time
Control Register
0x88
32
readwrite
0x0000
0000
0xFFFF
FFFF
GTDVU
General PWM
Timer Dead Time
Value Register U
0x8C
32
readwrite
0x0000
FFFF
0xFFFF
FFFF
GPT_OPS
-
-
-
OPSCR
Output Phase
Switching Control
Register
0x00
32
readwrite
0x0000
0000
0xFFFF
FFFF
KINT
-
-
-
KRCTL
KEY Return
Control Register
0x00
8
readwrite
0x00
0xFF
KRF
KEY Return Flag
Register
0x04
8
readwrite
0x00
0xFF
KRM
KEY Return Mode
Register
0x08
8
readwrite
0x00
0xFF
CTSUCR0
CTSU Control
Register 0
0x00
8
readwrite
0x00
0xFF
CTSUCR1
CTSU Control
Register 1
0x01
8
readwrite
0x00
0xFF
CTSUSDPRS
CTSU
Synchronous
Noise Reduction
Setting Register
0x02
8
readwrite
0x00
0xFF
CTSUSST
CTSU Sensor
Stabilization Wait
Control Register
0x03
8
readwrite
0x00
0xFF
CTSUMCH0
CTSU
Measurement
Channel Register
0
0x04
8
readwrite
0x3F
0xFF
CTSUMCH1
CTSU
Measurement
Channel Register
1
0x05
8
readwrite
0x3F
0xFF
CTSUCHAC0
CTSU Channel
Enable Control
Register 0
0x06
8
readwrite
0x00
0xFF
CTSUCHAC1
CTSU Channel
Enable Control
Register 1
0x07
8
readwrite
0x00
0xFF
CTSU
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1091 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (23 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
CTSU
-
-
-
CTSUCHAC2
AGT0,1
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
CTSU Channel
Enable Control
Register 2
0x08
8
readwrite
0x00
0xFF
CTSUCHAC3
CTSU Channel
Enable Control
Register 3
0x09
8
readwrite
0x00
0xFF
CTSUCHTRC0
CTSU Channel
Transmit/Receive
Control Register 0
0x0B
8
readwrite
0x00
0xFF
CTSUCHTRC1
CTSU Channel
Transmit/Receive
Control Register 1
0x0C
8
readwrite
0x00
0xFF
CTSUCHTRC2
CTSU Channel
Transmit/Receive
Control Register 2
0x0D
8
readwrite
0x00
0xFF
CTSUCHTRC3
CTSU Channel
Transmit/Receive
Control Register 3
0x0E
8
readwrite
0x00
0xFF
CTSUDCLKC
CTSU High-Pass
Noise Reduction
Control Register
0x10
8
readwrite
0x00
0xFF
CTSUST
CTSU Status
Register
0x11
8
readwrite
0x00
0xFF
CTSUSSC
CTSU High-Pass
Noise Reduction
Spectrum
Diffusion Control
Register
0x12
16
readwrite
0x0000
0xFFFF
CTSUSO0
CTSU Sensor
Offset Register 0
0x14
16
readwrite
0x0000
0xFFFF
CTSUSO1
CTSU Sensor
Offset Register 1
0x16
16
readwrite
0x0000
0xFFFF
CTSUSC
CTSU Sensor
Counter
0x18
16
readonly
0x0000
0xFFFF
CTSURC
CTSU Reference
Counter
0x1A
16
readonly
0x0000
0xFFFF
CTSUERRS
CTSU Error Status
Register
0x1C
16
readonly
0x0000
0xFFFF
AGT
AGT Counter
Register
0x00
16
readwrite
0xFFFF
0xFFFF
AGTCMA
AGT Compare
Match A Register
0x02
16
readwrite
0xFFFF
0xFFFF
AGTCMB
AGT Compare
Match B Register
0x04
16
readwrite
0xFFFF
0xFFFF
AGTCR
AGT Control
Register
0x08
8
readwrite
0x00
0xFF
AGTMR1
AGT Mode
Register 1
0x09
8
readwrite
0x00
0xFF
AGTMR2
AGT Mode
Register 2
0x0A
8
readwrite
0x00
0xFF
AGTIOC
AGT I/O Control
Register
0x0C
8
readwrite
0x00
0xFF
AGTISR
AGT Event Pin
Select Register
0x0D
8
readwrite
0x00
0xFF
Page 1092 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (24 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
AGT0,1
-
-
-
AGTCMSR
ACMPLP
USBFS
-
-
-
-
-
-
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Address
offset
Size
Access
Reset
value
Reset
mask
AGT Compare
Match Function
Select Register
0x0E
8
readwrite
0x00
0xFF
AGTIOSEL
AGT Pin Select
Register
0x0F
8
readwrite
0x00
0xFF
COMPMDR
ACMPLP Mode
Setting Register
0x00
8
readwrite
0x00
0xFF
COMPFIR
ACMPLP Filter
Control Register
0x01
8
readwrite
0x00
0xFF
COMPOCR
ACMPLP Output
Control Register
0x02
8
readwrite
0x00
0xFF
SYSCFG
System
Configuration
Control Register
0x000
16
readwrite
0x0000
0xFFFF
SYSSTS0
System
Configuration
Status Register 0
0x004
16
readonly
0x0000
0xFFFF
DVSTCTR0
Device State
Control Register 0
0x008
16
readwrite
0x0000
0xFFFF
CFIFO
CFIFO Port
Register
0x014
16
readwrite
0x0000
0xFFFF
CFIFOL
CFIFO Port
Register L
0x014
8
readwrite
0x00
0xFF
CFIFOSEL
CFIFO Port Select
Register
0x020
16
readwrite
0x0000
0xFFFF
CFIFOCTR
CFIFO Port
Control Register
0x022
16
readwrite
0x0000
0xFFFF
INTENB0
Interrupt Enable
Register 0
0x030
16
readwrite
0x0000
0xFFFF
BRDYENB
BRDY Interrupt
Enable Register
0x036
16
readwrite
0x0000
0xFFFF
NRDYENB
NRDY Interrupt
Enable Register
0x038
16
readwrite
0x0000
0xFFFF
BEMPENB
BEMP Interrupt
Enable Register
0x03A
16
readwrite
0x0000
0xFFFF
SOFCFG
SOF Output
Configuration
Register
0x03C
16
readwrite
0x0000
0xFFFF
INTSTS0
Interrupt Status
Register 0
0x040
16
readwrite
0x0000
0xFF7F
BRDYSTS
BRDY Interrupt
Status Register
0x046
16
readwrite
0x0000
0xFFFF
NRDYSTS
NRDY Interrupt
Status Register
0x048
16
readwrite
0x0000
0xFFFF
BEMPSTS
BEMP Interrupt
Status Register
0x04A
16
readwrite
0x0000
0xFFFF
FRMNUM
Frame Number
Register
0x04C
16
readwrite
0x0000
0xFFFF
USBREQ
USB Request
Type Register
0x054
16
readonly
0x0000
0xFFFF
USBVAL
USB Request
Value Register
0x056
16
readonly
0x0000
0xFFFF
USBINDX
USB Request
Index Register
0x058
16
readonly
0x0000
0xFFFF
Page 1093 of 1104
S124 User’s Manual
Table 3.4
Appendix 3. I/O Registers
Register description (25 of 25)
Peripheral
name
Dim
Dim
incr.
Dim
index
Register name
Description
USBFS
-
-
-
USBLENG
TSN
Address
offset
Size
Access
Reset
value
Reset
mask
USB Request
Length Register
0x05A
16
readonly
0x0000
0xFFFF
DCPCFG
DCP Configuration
Register
0x05C
16
readwrite
0x0000
0xFFFF
DCPMAXP
DCP Maximum
Packet Size
Register
0x05E
16
readwrite
0x0040
0xFFFF
DCPCTR
DCP Control
Register
0x060
16
readwrite
0x0040
0xFFFF
PIPESEL
Pipe Window
Select Register
0x064
16
readwrite
0x0000
0xFFFF
PIPECFG
Pipe Configuration
Register
0x068
16
readwrite
0x0000
0xFFFF
PIPEMAXP
Pipe Maximum
Packet Size
Register
0x06C
16
readwrite
0x0000
0xFFBF
2
0x002
4,5
PIPE%sCTR
Pipe %s Control
Register
0x076
16
readwrite
0x0000
0xFFFF
2
0x002
6,7
PIPE%sCTR
Pipe %s Control
Register
0x07A
16
readwrite
0x0000
0xFFFF
2
0x004
4,5
PIPE%sTRE
Pipe %s
Transaction
Counter Enable
Register
0x09C
16
readwrite
0x0000
0xFFFF
2
0x004
4,5
PIPE%sTRN
Pipe %s
Transaction
Counter Register
0x09E
16
readwrite
0x0000
0xFFFF
-
-
-
USBBCCTRL0
BC Control
Register 0
0x0B0
16
readwrite
0x0000
0xFFFF
UCKSEL
USB Clock
Selection Register
0x0C4
16
readwrite
0x0000
0xFFFF
USBMC
USB Module
Control Register
0x0CC
16
readwrite
0x0002
0xFFFF
TSCDRH
Temperature
Sensor Calibration
Data Register H
0x229
8
readonly
0x00
0x00
TSCDRL
Temperature
Sensor Calibration
Data Register L
0x228
8
readonly
0x00
0x00
-
-
-
Peripheral name = Name of peripheral
Dim = Number of elements in an array of registers
Dim inc = Address increment between two neighboring registers of a register array in the address map
Dim index = Substring that replaces the %s placeholder in the register name
Register name = Name of register
Description = Register description
Address offset = Address of the register relative to the base address defined by the peripheral of the register
Size = Bit width of the register
Access = Register access rights:
Read-only: Read access is permitted. Write operations have undefined results.
Write-only: Write access is permitted. Read operations have undefined results.
Read-write: Both read and write accesses are permitted. Writes affect the state of the register and reads return a value related
to the register.
Reset value = Default reset value of the register
Reset mask = Identifies which register bits have a defined reset value
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1094 of 1104
REVISION HISTORY
S124 User’s Manual
Revision History
Revision History
Rev.
1.00
1.10
Date
Feb 23, 2016
Jul 22, 2016
S124 Microcontroller Group User’s Manual
Chapter
Summary
Synergy S124 User’s Manual
section 1, Overview Updated Figure 1.1, Block diagram
Updated Figure 1.2, Part numbering scheme
Added Table 1.12, Product list in section 1, Overview
Updated Table 1.13, Function comparison
Updated section 1.7, Pin Lists
section 2, CPU
Corrected R/W permission for b15 to b2, b24, and b31 to b25 of section 2.6.5.2,
Debug Stop Control Register (DBGSTOPCR)
Updated section 2.8.3.4, Connecting sequence and SWD authentication
section 4, Address Updated Figure 4.1, Memory map
Space
section 5, Resets Corrected the software reset bit in Table 5.1, Reset names and sources
Updated Figure 5.3, Example of cold/warm start determination operation
section 6, Option- Updated Table 6.1, Specifications for ID code protection
Setting Memory
Corrected the bit names for voltage monitor 1 and voltage monitor 2 in Table 7.1,
section 7, Low
Voltage Detection LVD specifications
(LVD)
Updated information about voltage monitor 0 in section 7.4, Reset from Voltage Monitor 0
section 8, Clock
Removed TSN as the peripheral module in Table 8.2, Clock generation circuit speciGeneration Circuit fications for the internal clocks
section 8, Clock
Updated description for CKSEL[2:0] bits (Clock Source Select)
Generation Circuit Updated description for HOCOSF flag (HOCO Clock Oscillation Stabilization Flag)
Corrected bit name for MOCOCR.MOSTP to MOCOCR.MCSTP in MSTS[3:0] bits
(Main Clock Oscillator Wait Time Setting) and HSTS[2:0] bits (HOCO wait time setting)
Updated description for CKOEN bit (Clock Out Enable)
Updated section 8.7.1, Notes on Clock Generation Circuit
section 10, Low
Updated section 10.2.9, Snooze End Control Register (SNZEDCR)
Power Modes
Modified bit names for bits [28] and [29] in section 10.2.10, Snooze Request Control
Register (SNZREQCR)
Modified bit SNZCR.DTCE to SNZCR.SNZDTCEN in section 10.8.1, Transition to
Snooze Mode
Updated Table 10.9, HOCO: ± 1.0% (Ta = -20 to 85°C) (Unit: bps)
Updated Table 10.10, HOCO: ± 1.5% (Ta = -40 to -20°C), HOCO: ± 2.0% (Ta = 85 to
105°C) (Unit: bps)
section 12, Interrupt Updated section 12.2.7, SYS Event Link Setting Register (SELSR0)
Controller Unit (ICU) Updated section 12.4.4, External Pin Interrupts
section 15, Event Updated description for ELS[7:0] in section 15.2.3, Event Link Setting Register n
Link Controller
(ELSRn)
(ELC)
section 16, I/O Ports Updated addresses and description in section 16.2.1, Port Control Register 1 (PCNTR1/PODR/PDR)
Updated addresses and description in section 16.2.2, Port Control Register 2 (PCNTR2/EIDR/PIDR)
Updated addresses and description in section 16.2.3, Port Control Register 3 (PCNTR3/PORR/POSR)
Updated addresses and description in section 16.2.4, Port Control Register 4 (PCNTR4/EORR/EOSR)
Updated addresses and description in section 16.2.5, Port mn Pin Function Select
Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 5; n = 00 to 15)
Updated description in section 16.3.1, General I/O Ports
section 17, Key
Updated the module symbol in section 17.2.1, Key Return Control Register (KRCTL),
Interrupt Function section 17.2.2, Key Return Flag Register (KRF), and section 17.2.3, Key Return
(KINT)
Mode Register (KRM)
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1095 of 1104
S124 User’s Manual
Rev.
1.10
Date
Jul 22, 2016
Revision History
Chapter
section 18, Port
Output Enable for
GPT (POEG)
section 19, General
PWM Timer (GPT)
section 20,
Asynchronous
General Purpose
Timer (AGT)
section 21, Realtime
Clock (RTC)
section 22,
Watchdog Timer
(WDT)
Summary
Updated Figure 18.1, POEG block diagram
Updated Table 18.3, Interrupt source and condition
Updated Figure 19.1, GPT block diagram
Updated Figure 19.2, Association between GPT channels and module names
Updated section 19.3.3.5, Triangle-wave PWM mode 3 (64-bit transfer at trough)
Updated Figure 19.52, Example for setting count start/stop operation by hardware
source
Updated Figure 19.55, Example for setting count clearing operation by hardware
source
Updated Figure 19.60, Example for setting simultaneous start by hardware source
Updated section 19.9.2, Settings of GTCCRn during Compare Match Operation (n =
A to F)
Removed section 20.4.2 Access to Flags (TEDGF, TUNDF, TCMAF, TCMBF Bits in
AGTCR Register
Updated description of bit [7] in section 21.2.1, 64-Hz Counter (R64CNT)
Changed PCLK to PCLKB throughout chapter
Changed access permission for b3, b2, b11, b10, and b15, b14 in section 22.2.2,
WDT Control Register (WDTCR)
Changed access permission for b6 to b0 in section 22.2.4, WDT Reset Control Register (WDTRCR)
Changed access permission for b6 to b0 in section 22.2.5, WDT Count Stop Control
Register (WDTCSTPR)
section 24, USB 2.0 Updated section 24.1, Overview
Full-Speed Module
(USBFS)
section 25, Serial Updated FM bit in section 25.2.26, FIFO Control Register (FCR)
Communications
Added section (6), Address Mismatch Event Output (SCI0_DCUF)
Interface (SCI)
Updated section 25.13.6, Restrictions on Clock Synchronous Transmission in Clock
Synchronous and Simple SPI Modes
Updated Figure 25.78, Restrictions on the use of external clock in clock synchronous
transmission
section 26, I2C Bus Updated Figure 26.22, Figure 26.23, Figure 26.42
Interface (IIC)
Updated Table 26.11
section 28, Serial Changed PCLK to PCLKB throughout chapter
Peripheral Interface Changed SPDR_HA to SPDR/SPDR_HA throughout chapter
(SPI)
Updated Figure 28.1, Figure 28.2, Figure 28.3, and Figure 28.4
Added bit [5] and updated description in SPI Data Control Register (SPDCR)
Updated description in SPB[3:0] bits (SPI Data Length Setting)
Updated information in section 28.3.4, Data Format
section 30, 14-Bit A/ Added section 30.8.10, Notes on Board Design
D Converter
Updated Figure 30.32, Example protection circuit for analog inputs
(ADC14)
Updated section 30.8.12, Port Setting when Using the ADC14 Input
section 31, 12-Bit D/ Updated Figure 31.3 and Figure 31.4
A Converter
(DAC12)
Updated Figure 34.3, Figure 34.10, and Figure 34.21
section 34,
Capacitive Touch
Sensing Unit
(CTSU)
section 36, SRAM Removed the note in section 36.3.2, SRAM Error Source
section 37, Flash
Updated Table 37.5, Specifications for ID code protection
Memory
section 41, Electrical Updated Table 41.1, Table 41.11, Table 41.14, Table 41.36, and Table 41.53
Characteristics
Updated Table 1.1
section 1, Port
States in Each
Processing Mode
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1096 of 1104
S124 User’s Manual
Rev.
1.20
Date
Aug 26, 2016
Revision History
Chapter
section 2, CPU
section 4, Address
Space
section 5, Resets
section 7, Low
Voltage Detection
(LVD)
section 8, Clock
Generation Circuit
Summary
Updated the start address for SCS in Table 2.5, Cortex-M0+ peripheral address map
Updated Figure 4.1, Memory map
Updated Note 1. of Figure 5.2, Examples of operation during voltage monitor 1 and
voltage monitor 2 resets
Modified the text of the notes in section 7.2.1
Updated signal name from LOCOCR.LCSTP to MOCOCR.MCSTP in section 7.2.7
and section 7.2.8
Updated Table 7.4
Updated description for HCSTP bit (HOCO Stop) in section 8.2.6
Updated description for HSTS[2:0] in section 8.2.12
Updated table title for Table 10.10
section 10, Low
Power Modes
section 12, Interrupt Updated Figure 12.2
Controller Unit (ICU) Updated the procedure to return to Normal mode from Snooze mode in section
12.6.3
section 13, Buses Removed the restriction for accessing address space that spans areas in section
13.2.4
Updated description for the SAR register in section 14.2.3
section 14, Data
Transfer Controller
(DTC)
section 16, I/O Ports Updated the note in section 16.2.5
section 19, General Added a footnote for the description of the external trigger input pin in Table 19.2
PWM Timer (GPT) Updated signal ELCA to ELC_GPTA, ELCB to ELC_GPTB, ELCC to ELC_GPTC,
and ELCD to ELC_GPTD throughout document
Updated description for MD[2:0] in section 19.2.12, General PWM Timer Control
Register (GTCR)
Updated Figure 19.5
Updated pin names in Table 19.6
Updated register name GTCLR to GTCSR in Figure 19.55
Modified title in Figure 19.59
Updated Table 19.9 and Table 19.10
Updated section 19.2.2
Modified Note 1. in section 20.2.6
section 20,
Asynchronous
Updated description for the LPM bit in section 20.2.6
General Purpose
Timer (AGT)
Updated description for the UNDFF and REFEF flags in section 22.2.4, WDT Reset
section 22,
Control Register (WDTRCR)
Watchdog Timer
(WDT)
Updated description for the UNDFF and REFEF flags in section 23.2.2, IWDT Status
section 23,
Register (IWDTSR)
Independent
Watchdog Timer
(IWDT)
section 24, USB 2.0 Updated description for the BSTS bit in section 24.2.3, Device State Control Register
Full-Speed Module 0 (DVSTCTR0)
(USBFS)
Updated bit names in section 24.3.12.1, Processing
Updated Figure 24.15
section 25, Serial Removed reference to the BRK bit in section 25.2.11, Serial Control Register (SCR)
for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
Communications
Interface (SCI)
Updated sections 25.2.14, 25.2.15, 25.2.23, 25.2.24, and 25.2.30
Updated title of Figure 25.27, Figure 25.28, Figure 25.37, Figure 25.41, Figure 25.43
section 26, I2C Bus Updated the note in Table 26.6, Table 26.7, and Table 26.8
Interface (IIC)
section 29, Cyclic Updated the Note after Table 29.1, CRC calculator specifications
Redundancy Check
(CRC) Calculator
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1097 of 1104
S124 User’s Manual
Rev.
1.20
Date
Aug 26, 2016
1.30
Feb 5, 2018
Revision History
Chapter
Summary
section 30, 14-Bit A/ Updated description for CMPCHAn bits in section 30.2.19
D Converter
Updated description for CMPCHB[5:0] bits in section 30.2.28
(ADC14)
Updated Figure 30.22 and Figure 30.31
section 33, LowModified MSTPDRD register name to MSTPCRD in Table 33.3
Power Analog
Comparator
(ACMPLP)
section 36, SRAM Updated description in section 36.3.1, Parity Calculation Function
section 37, Flash
Added section 37.12.3, Constraint on Additional Writes
Memory
section 41, Electrical Updated Table 41.13, Table 41.22, Table 41.23, Table 41.24, Table 41.25, Table
Characteristics
41.26, and Table 41.28
Removed Figure 41.24 Reset input timing (2)
Added a Note after Table 41.30
Updated Table 41.33, Table 41.34, Table 41.35, Table 41.36, Table 41.38, Table
41.48, Table 41.52, Table 41.53, and Table 41.55
Updated Figure 41.25
section 3, I/O
Added a new appendix for I/O Registers
Registers
Third release
section 1, Overview Updated Figure 1.1 and Figure 1.2
Updated Table 1.1
Updated orderable part number in Table 1.12
Updated part number in Table 1.13
Updated Table 1.14
section 2, CPU
Updated section 2.1.1
Updated implementation and configurable options Table 2.1
Updated description in section 2.5.1, Debug Mode Definition
Added a note about DBIRQ and EDBGRQ in section 2.6.6.3, MCU Control Register
(MCUCTRL)
Updated section 2.7
Added section 2.8.1, DBGEN
Updated section 2.8.3.4, Connecting sequence and SWD authentication
section 3, Operating Updated Figure 3.1
Modes
section 5, Resets Updated Table 5.3 and Table 5.4
Updated description for the HOCOEN bit in section 6.2.2, Option Function Select
Register 1 (OFS1)
Updated the value after reset of bit [3] in section 7.2.7, Voltage Monitor 1 Circuit Consection 7, Low
Voltage Detection trol Register 0 (LVD1CR0)
(LVD)
Updated the value after reset of bit [3] in section 7.2.8, Voltage Monitor 2 Circuit Control Register 0 (LVD2CR0)
Updated Figure 7.4
Removed Note 3 from Table 7.6
section 8, Clock
Updated Table 8.2
Generation Circuit Updated Figure 8.1
Updated the setting condition for the MOSCSF flag in section 8.2.8, Oscillation Stabilization Flag Register (OSCSF)
Updated section 8.5.2, Oscillation Stop Detection Interrupts
Updated description of the RCDS[1:0] bits in section 9.2.3, CAC Control Register 2
section 9, Clock
Frequency Accuracy (CACR2)
Measurement
Circuit (CAC)
section 10, Low
Updated Note 4. in Table 10.2, Operating conditions of each low power mode
Power Modes
Added Note 2. to section 10.2.4, Module Stop Control Register C (MSTPCRC)
Updated description in section 10.7.1, Transition to Software Standby Mode
section 12, Interrupt Added a Note to section 12.2.6, ICU Event Link Setting Register n (IELSRn)
Controller Unit (ICU) Updated the value set in IELSRn.IELS to trigger a return from Snooze mode to Normal mode in section 12.6.3, Return from Snooze Mode
section 13, Buses Updated the reserved address in Table 13.6, Conditions leading to illegal address
access errors
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1098 of 1104
S124 User’s Manual
Rev.
1.30
Date
Feb 5, 2018
Revision History
Chapter
section 14, Data
Transfer Controller
(DTC)
section 14, Data
Transfer Controller
(DTC)
Summary
Changed ROM to Code flash in Figure 14.1, DTC block diagram
Updated information about the CRAH and CRAL registers in section (2), Repeat
Transfer mode (MRA.MD[1:0] bits = 01b) and section (3), Block Transfer mode
(MRA.MD[1:0] bits = 10b)
Updated Figure 14.2
Updated steps 4. and 5. in section 14.6.3, Chain Transfer when Counter = 0
Updated Figure 15.1
Added section 15.4.4, ELC Delay Time
section 15, Event
Link Controller
(ELC)
section 16, I/O Ports Updated section 16.2.1, section 16.2.2, section 16.2.3, section 16.2.4, section
16.2.5, section 16.3.2, section 16.5.4
Updated Table 16.3
Updated P410 and P411 signal names in Table 16.9
section 17, Key
Updated Table 17.1 and Figure 17.1
Interrupt Function Added information about key return factors after Figure 17.1
(KINT)
Updated section 17.2.1, section 17.2.2, and section 17.2.3
Updated the Note in section 17.2.2, Key Return Flag Register (KRF)
Updated Table 18.1
section 18, Port
Output Enable for Deleted the GTINTAD.GRPDTE signal from Figure 18.1
GPT (POEG)
Updated Figure 18.2 and Figure 18.4
section 19, General Updated Table 19.2
PWM Timer (GPT) Changed GPT0_COMPA and GPT0_COMPB to GPT0_CCMPA and GPT0_CCMPB
in Figure 19.1
Updated description for the GRP[1:0] bits in section 19.2.15, General PWM Timer
Interrupt Output Setting Register (GTINTAD)
Updated section 19.2.16, General PWM Timer Status Register (GTST)
Updated section 19.2.24
Removed the note in Figure 19.25, Figure 19.30, Figure 19.32, Figure 19.34, Figure
19.36, and Figure 19.38
Removed GTIOCA/GTIOCB pin input as a hardware source for starting GTCNT
counters in section 19.3.8.2, Synchronized operation by hardware
Updated section 19.3.11.6, ELC output
Updated Figure 19.77 through Figure 19.81
Deleted section 19.3.11.4 Rotation Direction Control
Updated Table 19.19 and Table 19.20
Updated Figure 20.1 and Figure 20.7
section 20,
Asynchronous
Updated procedure for stopping AGT operation in section 20.4.7
General Purpose
Timer (AGT)
section 21, Realtime Updated Figure 21.7
Clock (RTC)
Updated Figure 23.1
section 23,
Independent
Watchdog Timer
(IWDT)
section 24, USB 2.0 Updated the DPRPU bit description in section 24.2.1, System Configuration Control
Full-Speed Module Register (SYSCFG)
(USBFS)
Updated the RHST[2:0] bits in section 24.2.3, Device State Control Register 0
(DVSTCTR0)
Updated the constraints of the CFIFO Port Register in section 24.2.4, CFIFO Port
Register (CFIFO/CFIFOL)
Updated register access permission in 24.2.17, 24.2.18, 24.2.19, and 24.2.20
Updated Note 1. in 24.2.26
Removed the DCLRM bit column and updated Table 24.9
Updated text and graphics throughout the chapter
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1099 of 1104
S124 User’s Manual
Rev.
1.30
Date
Feb 5, 2018
Revision History
Chapter
section 25, Serial
Communications
Interface (SCI)
section 25, Serial
Communications
Interface (SCI)
section 26, I2C Bus
Interface (IIC)
Summary
Updated description of bits [6] and [7] in section 25.2.10, bit [3] in section 25.2.11,
and bit [7] in section 25.2.12
Added a note to the description of the RDRF flag and the TDRE flag in section
25.2.13
Added a note to the description of the RDF flag in section 25.2.14
Updated Table 25.18 through Table 25.18
Updated section 25.3.5
Updated Figure 25.5, Figure 25.6, and Figure 25.30
Updated section 25.5.2, section 25.5.3
Updated description in Figure 25.38, Figure 25.45, Figure 25.50, Figure 25.52, and
Figure 25.53
Updated section 25.6.3
Added Figure 25.51, Example timing of data transmission in smart card interface
mode
Updated Figure 25.66, Figure 25.68
Updated Note 1. in section 25.8.5, SCI Initialization in Simple SPI Mode
Updated Table 25.26 through Table 25.29
Updated section (6) and section 25.12
Updated Figure 25.72, Figure 25.74, and Figure 25.75
Updated section 25.13.8
Updated section 26.2.1
Updated Table 26.3
Updated Figure 26.26, Figure 26.28, Figure 26.31, Figure 26.36, Figure 26.37, Figure 26.45, Figure 26.48, and Figure 26.50
Updated Table 26.10
Updated Figure 27.3
section 27,
Controller Area
Network (CAN)
Module
section 28, Serial Updated description in section (4), LSB-first transfer with 24-bit data
Peripheral Interface Updated Figure 28.29, Figure 28.30, Figure 28.33, Figure 28.34, Figure 28.35, and
(SPI)
Figure 28.40
Updated Table 28.12 and Table 28.14
section 30, 14-Bit A/ Updated the notes in section 30.2.3, A/D Control Register (ADCSR)
D Converter
Updated section 30.2.15, 30.3.2.4, 30.3.2.5
(ADC14)
Updated Figure 30.10, Figure 30.18, Figure 30.22
Updated 30.4.1
Updated Table 30.11
Updated 30.8.9
section 31, 12-Bit D/ Updated Figure 31.4
A Converter
(DAC12)
Updated address in section 32.2.1, section 32.2.2
section 32,
Temperature Sensor
(TSN)
Updated Table 33.3 and section 33.8
section 33, LowPower Analog
Comparator
(ACMPLP)
Updated Figure 34.14
section 34,
Capacitive Touch
Sensing Unit
(CTSU)
section 36, SRAM Added a new section 36.4.2, Store Buffer of SRAM
section 37, Flash
Updated Figure 37.3
Memory
Updated Table 37.3
Updated 37.10.1
Updated Figure 37.10
Updated Note 1. in section 37.12.5, Non-maskable Interrupt Disabled during Programming and Erasing
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1100 of 1104
S124 User’s Manual
Rev.
1.30
Date
Feb 5, 2018
Revision History
Chapter
Summary
section 41, Electrical Updated Table 41.2 through Table 41.5, and Table 41.7 through Table 41.9
Characteristics
Added Figure 41.17 to Figure 41.23
Added Note 5. in Table 41.16 through Table 41.19
Updated Table 41.21 and Table 41.22
Added Figure 41.32
Updated Table 41.34
Updated Figure 41.48 through Figure 41.52
Updated Figure 41.61
Updated Table 41.40 through Table 41.46
Inserted Figure 41.62, Equivalent circuit for analog input
Updated Figure 41.63
Updated Table 41.61
Updated Table 1.1
section 1, Port
States in Each
Processing Mode
section 3, I/O
Updated Table 3.4
Registers
section 30, 14-Bit A/ Updated Figure 30.16 through Figure 30.20
D Converter
Updated Table 30.10
(ADC14)
section 41, Electrical Updated Table 41.35
Characteristics
R01UM0003EU0130 Rev.1.30
Feb 5, 2018
Page 1101 of 1104
Colophon
S124 Microcontroller Group User’s Manual
Publication Date:
Rev.1.30
Feb 5, 2018
Published by:
Renesas Electronics Corporation
Address List
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Renesas Synergy™ Platform
S124 Microcontroller Group
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