R8A66150SP

R8A66150SP 12-BIT I/O EXPANDER REJ03F0257-0100 Rev. 1.00 Jan.08.2008 DESCRIPTION R8A66150 is a semiconductor integrated circuit which has 12-bit shift register function to execute serial in parallel out conversion and parallel in - serial out conversion. Built in two shift registers for serial in - parallel out and parallel in - serial out are constructed independently, This IC is able to read serial input data into a shift register while output the serial data converting from the parallel data input. Also, parallel data I/O pins can be set to input mode or output mode by a bit. R8A66150 is useful in a wide range of applications, such as MCU (micro controller unit) I/O port extension and serial bus system data communication. R8A66150 is the succession product of M66006. FEATURES Bi-directional serial communication with MCU Serial data can be input during parallel to serial data conversion Parallel data I/O pins can be set input mode or output mode by a bit Schmitt input (DI, CLK, /S, /CS) N-ch open drain output (DO, D1~D12) Parallel data I/O pins (D1~D12) Wide supply voltage range (Vcc=2.0 to 6.0V) Wide operating temperature range (Ta=-40 to 85 oC) APPLICATION Serial - parallel or parallel - serial data conversion for MCU peripheral. Serial bus control by MCU. PIN CONFIGURATION (TOP VIEW) SERIAL DATA OUTPUT SERIAL DATA INPUT DO DI 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 PARALLEL DATA I/O CLOCK INPUT CLK CHIP SELECT INPUT CS Vcc SET INPUT S GND PARALLEL DATA I/O D12 D11 GND REJ03F0257-0100 Rev.1.00 Jan.08.2008 Page 1 of 7 R8A66150SP BLOCK DIAGRAM Vcc 5 Vcc Shift register 1 D12 D11 D10 CLK 3 S CS 6 4 DO D3 D2 D1 1 DO CLK, S, CS, DI S Control circuit D1 19 D2 18 D3 20 Input type 11 D10 9 D11 8 D12 Vcc Vcc Q12 Q11 Q10 Q3 Q2 Q1 Parallel output latch D12 D11 D10 D3 D2 D1 Q12 Q11 Q10 DI DI 2 7 10 DO D1~D12 Q3 Q2 Q1 Shift register 2 Output type GND GND FUNCTION The R8A66150 is produced by using the silicon gate CMOS technology and has low power dissipation and high noise margin. Built in two shift registers for serial in-parallel out (Shift register 2) and parallel in-serial out (Shift register 1) are constructed independently, R8A66150 is able to read serial input data into a shift register while output the serial data converting from the parallel data input. Serial output operation of 12-bit parallel latched data and serial input operation from MCU are started when /CS is changed from "H" to "L". 12-bits parallel data are latched by the negative edge of /CS and are output from the DO terminal synchronously to the negative edge of CLK, and also the DI terminal read serial input data from MCU and are written into the internal shift register 2. The 13th and following shift clock pulse are ignored and serial input data is masked, and DO terminal becomes high-impedance ("High-Z"). When /CS is changed from "L" to "H", 12-bits serial data which is read from the DI terminal are output to the D1~D12 terminals as parallel data. As the output circuit type of D1~D12 terminals is N-ch open drain output, write data "H" for pins which should be set to input mode. REJ03F0257-0100 Rev.1.00 Jan.08.2008 Page 2 of 7 R8A66150SP DESCRIPTION OF OPERATION (1) When power ON, the status of DO and D1~D12 terminals are not determined. These terminals are turn to high-impedance when "L" is input to the /S terminal. (2) By the negative edge of /CS, the status of D1~D12 terminals is loaded on shift register 1. (3) Synchronous to the negative edge of CLK, 12-bit loaded data is serial output from the DO terminal. (4) Synchronous to the positive edge of CLK, 12-bit serial input data from DI is write into the shift register 2. (5) The 13th and following shift clock pulse are ignored and the serial data input operation is stopped. And the DO terminal becomes high-impedance ("High-Z"). (6) By the positive edge of /CS, input data described in (4) is output to D1~D12 terminals. (7) Shift register 1 loads the AND tie data of external parallel input data and latched data on parallel output latch. (8) If the /CS is changed from "L" to "H" before reaches the 12th bit of CLK, parallel output latch latches data which has been written on shift register 2 and output it to D1~D12 terminals. Serial data after this since is ignored and the DO terminal becomes high-impedance. (9) Input/output mode set to D1~D12 terminals is done by the serial input data to the DI terminal. Terminals which "H" is written are set to input, and "L" is written are set to output. OPERATION TIMING CHART S (1) CS (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 (5) CLK (4) DI High-Z DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 High-Z (3) DO DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 (6) D1 High-Z DI1 DO1 D2 High-Z DI2 DO2 High-Z D12 DI12 DO12 1 Sequence REJ03F0257-0100 Rev.1.00 Jan.08.2008 Page 3 of 7 R8A66150SP ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI Vo Tstg Parameter Supply voltage Input voltage Output voltage Storage temperature range (Ta=-40~85 oC, unless otherwise noted) Conditions Ratings -0.5 ~ +7.0 -0.5 ~ Vcc+0.5 -0.5 ~ Vcc+0.5 -65 ~ 150 Unit V V V o C RECOMMENDED OPERATING CONDITIONS Symbol Vcc VI Vo Topr Parameter Supply voltage Input voltage Output voltage Operating temperature range Min. 2.0 0 0 -40 Limits Typ. Max. 6.0 Vcc Vcc 85 Unit V V V o C ELECTRICAL CHARACTERISTICS Symbol VT+ VTVIH VIL VOL IO IIH IIL Icc Parameter Positive going threshold voltage (*1) Negative going threshold voltage (*1) "H" input voltage (*2) "L" input voltage (*2) "L" output voltage Output leakage current "H" input current "L" input current Quiescent supply current (Vcc=2.0~6.0V, Ta=-40~85 oC, unless otherwise noted) Test conditions Vo=0.1V, Vcc-0.1V l Io l=20uA Vcc=4.5V, IOL=3mA Vo=Vcc Vcc=6V Vo=GND VI=Vcc, Vcc=6V VI=GND, Vcc=6V VI=Vcc, GND Vcc=6V Min. 0.35 x Vcc 0.20 x Vcc 0.75 x Vcc Limits Typ. Max. 0.80 x Vcc 0.65 x Vcc 0.25 x Vcc 0.5 10 -10 1 -1 100 Unit V V V V V uA uA uA *1 : DI, CLK, /CS, /S *2 : D1~D12 REJ03F0257-0100 Rev.1.00 Jan.08.2008 Page 4 of 7 R8A66150SP SWITCHING CHARACTERISTICS Symbol fmax tPLZ tPZL tPLZ tPZL tPLZ Parameter Maximum repeat frequency Output "L-Z" and "Z-L" propagation time CLK - DO Output "L-Z" and "Z-L" propagation time /CS - D1~D12 Output "L-Z" propagation time /S - DO, /S - D1~D12 (Vcc=2.0~6.0V, Ta=-40~85 oC, unless otherwise noted) Test conditions Min. Limits Typ. Max. 1.9 400 400 400 400 400 Unit MHz ns ns ns ns ns CL=50pF RL=1kΩ (note1) TIMING REQUIREMENTS Symbol tw tsu (Vcc=2.0~6.0V, Ta=-40~85 oC, unless otherwise noted) Test conditions Min. 260 130 130 130 130 130 130 130 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns Parameter CLK, /CS, /S pulse width Setup time of DI to CLK Setup time of /CS to CLK Setup time of D1~D12 to /CS Hold time of DI to CLK Hold time of /CS to CLK Hold time of D1~D12 to /CS Recovery time of /CS to /S th trec NOTE1: TEST CIRCUIT Input Vcc Vcc RL P.G. 50 Ω DUT CL DO, D1~D12 GND (1) The pulse generator (P.G.) has the following characteristics (10%~90%) tr=6ns, tf=6ns, Zo=50 Ω (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance. REJ03F0257-0100 Rev.1.00 Jan.08.2008 Page 5 of 7 R8A66150SP TIMING DIAGRAM tw tw CLK 50% tPLZ 50% 50% tPZL CS 50% tsu th 50% DO 10% 50% CLK 50% 50% tw tw CS 50% tPLZ 50% 50% tPZL S 50% trec D1~D12 10% 50% CS 50% tw S 50% tPLZ 50% DO, D1~D12 10% DI 50% tsu th 50% CLK 50% D1~D12 50% tsu th 50% CS 50% REJ03F0257-0100 Rev.1.00 Jan.08.2008 Page 6 of 7 R8A66150SP PACKAGE OUTLINE Package 20pin SOP RENESAS Code PRSP0020DG-A Previous Code 20P2X-C All trademarks and registered trademarks are the property of their respective owners. REJ03F0257-0100 Rev.1.00 Jan.08.2008 Page 7 of 7