R8A77800BDBGV

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Rev.1.00 Dec. 13, 2005 Page iii of l General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. 5. Reading from/Writing Reserved Bit of Each Register Note: Treat the reserved bit of register used in each module as follows except in cases where the specifications for values which are read from or written to the bit are provided in the description. The bit is always read as 0. The write value should be 0 or one, which has been read immediately before writing. Writing the value, which has been read immediately before writing has the advantage of preventing the bit from being affected on its extended function when the function is assigned. Rev.1.00 Dec. 13, 2005 Page iv of l Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. Electrical Characteristics 8. Appendix 9. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 10. Index Rev.1.00 Dec. 13, 2005 Page v of l Preface This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. Rules: Bit order: Number notation: Signal notation: Rev.1.00 Dec. 13, 2005 Page vi of l The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx Abbreviations ALU Arithmetic Logic Unit ASID Address Space Identifier BGA Ball Grid Array CMT Compare Match Timer (Timer/Counter) CPG Clock Pulse Generator CPU Central Processing Unit DDR Double Data Rate DDRIF DDR-SDRAM Interface DMA Direct Memory Access DMAC Direct Memory Access Controller FIFO First-In First-Out FLCTL NAND Flash Memory Controller FPU Floating-point Unit HAC Audio Codec HSPI Serial Protocol Interface H-UDI User Debugging Interface INTC Interrupt Controller JTAG Joint Test Action Group LBSC Local Bus State Controller LRAM L Memory LRU Least Recently Used LSB Least Significant Bit Rev.1.00 Dec. 13, 2005 Page vii of l MMCIF Multimedia Card Interface MMU Memory Management Unit MSB Most Significant Bit PC Program Counter PCI Peripheral Component Interconnect PCIC PCI (local bus) Controller RISC Reduced Instruction Set Computer RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO SSI Serial Sound Interface TAP Test Access Port TLB Translation Lookaside Buffer TMU Timer Unit UART Universal Asynchronous Receiver/Transmitter UBC User Break Controller WDT Watchdog Timer Rev.1.00 Dec. 13, 2005 Page viii of l Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 SH7780 Features.................................................................................................................... 1 Block Diagram ....................................................................................................................... 9 Pin Arrangement .................................................................................................................. 10 Pin Functions ....................................................................................................................... 11 Memory Address Map ......................................................................................................... 27 SuperHyway Bus ................................................................................................................. 30 SuperHyway Memory (SuperHyway RAM)........................................................................ 31 Section 2 Programming Model ............................................................................33 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Data Formats........................................................................................................................ 33 Register Descriptions ........................................................................................................... 34 2.2.1 Privileged Mode and Banks .................................................................................... 34 2.2.2 General Registers.................................................................................................... 37 2.2.3 Floating-Point Registers.......................................................................................... 38 2.2.4 Control Registers .................................................................................................... 40 2.2.5 System Registers..................................................................................................... 42 Memory-Mapped Registers.................................................................................................. 46 Data Formats in Registers .................................................................................................... 47 Data Formats in Memory ..................................................................................................... 48 Processing States.................................................................................................................. 49 Usage Note........................................................................................................................... 50 2.7.1 Notes on self-modified codes.................................................................................. 50 Section 3 Instruction Set ......................................................................................51 3.1 3.2 3.3 Execution Environment ....................................................................................................... 51 Addressing Modes ............................................................................................................... 53 Instruction Set ...................................................................................................................... 57 Section 4 Pipelining .............................................................................................73 4.1 4.2 4.3 Pipelines............................................................................................................................... 73 Parallel-Executability........................................................................................................... 84 Issue Rates and Execution Cycles........................................................................................ 87 Section 5 Exception Handling .............................................................................97 5.1 Summary of Exception Handling......................................................................................... 97 Rev.1.00 Dec. 13, 2005 Page ix of l 5.2 5.3 5.4 5.5 5.6 5.7 Register Descriptions........................................................................................................... 97 5.2.1 TRAPA Exception Register (TRA) ........................................................................ 98 5.2.2 Exception Event Register (EXPEVT)..................................................................... 99 5.2.3 Interrupt Event Register (INTEVT)...................................................................... 100 Exception Handling Functions........................................................................................... 101 5.3.1 Exception Handling Flow ..................................................................................... 101 5.3.2 Exception Handling Vector Addresses ................................................................. 101 Exception Types and Priorities .......................................................................................... 102 Exception Flow .................................................................................................................. 104 5.5.1 Exception Flow..................................................................................................... 104 5.5.2 Exception Source Acceptance............................................................................... 106 5.5.3 Exception Requests and BL Bit ............................................................................ 107 5.5.4 Return from Exception Handling.......................................................................... 107 Description of Exceptions.................................................................................................. 108 5.6.1 Resets.................................................................................................................... 108 5.6.2 General Exceptions............................................................................................... 110 5.6.3 Interrupts............................................................................................................... 124 5.6.4 Priority Order with Multiple Exceptions .............................................................. 125 Usage Notes ....................................................................................................................... 127 Section 6 Floating-Point Unit (FPU)................................................................. 129 6.1 6.2 6.3 6.4 6.5 6.6 Features.............................................................................................................................. 129 Data Formats...................................................................................................................... 130 6.2.1 Floating-Point Format........................................................................................... 130 6.2.2 Non-Numbers (NaN) ............................................................................................ 133 6.2.3 Denormalized Numbers ........................................................................................ 134 Register Descriptions......................................................................................................... 135 6.3.1 Floating-Point Registers ....................................................................................... 135 6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................. 137 6.3.3 Floating-Point Communication Register (FPUL) ................................................. 140 Rounding............................................................................................................................ 141 Floating-Point Exceptions.................................................................................................. 142 6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions ................... 142 6.5.2 FPU Exception Sources ........................................................................................ 142 6.5.3 FPU Exception Handling ...................................................................................... 142 Graphics Support Functions............................................................................................... 144 6.6.1 Geometric Operation Instructions......................................................................... 144 6.6.2 Pair Single-Precision Data Transfer...................................................................... 145 Rev.1.00 Dec. 13, 2005 Page x of l Section 7 Memory Management Unit (MMU) ..................................................147 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Overview of MMU ............................................................................................................ 147 7.1.1 Address Spaces ..................................................................................................... 149 Register Descriptions ......................................................................................................... 156 7.2.1 Page Table Entry High Register (PTEH) .............................................................. 157 7.2.2 Page Table Entry Low Register (PTEL) ............................................................... 158 7.2.3 Translation Table Base Register (TTB) ................................................................ 159 7.2.4 TLB Exception Address Register (TEA) .............................................................. 159 7.2.5 MMU Control Register (MMUCR) ...................................................................... 160 7.2.6 Physical Address Space Control Register (PASCR)............................................. 164 7.2.7 Instruction Re-Fetch Inhibit Control Register (IRMCR) ...................................... 165 TLB Functions ................................................................................................................... 167 7.3.1 Unified TLB (UTLB) Configuration .................................................................... 167 7.3.2 Instruction TLB (ITLB) Configuration................................................................. 170 7.3.3 Address Translation Method................................................................................. 171 MMU Functions................................................................................................................. 173 7.4.1 MMU Hardware Management .............................................................................. 173 7.4.2 MMU Software Management ............................................................................... 173 7.4.3 MMU Instruction (LDTLB).................................................................................. 174 7.4.4 Hardware ITLB Miss Handling ............................................................................ 175 7.4.5 Avoiding Synonym Problems ............................................................................... 176 MMU Exceptions............................................................................................................... 177 7.5.1 Instruction TLB Multiple Hit Exception............................................................... 177 7.5.2 Instruction TLB Miss Exception........................................................................... 178 7.5.3 Instruction TLB Protection Violation Exception .................................................. 179 7.5.4 Data TLB Multiple Hit Exception ........................................................................ 180 7.5.5 Data TLB Miss Exception .................................................................................... 180 7.5.6 Data TLB Protection Violation Exception............................................................ 181 7.5.7 Initial Page Write Exception................................................................................. 182 Memory-Mapped TLB Configuration................................................................................ 183 7.6.1 ITLB Address Array ............................................................................................. 184 7.6.2 ITLB Data Array................................................................................................... 185 7.6.3 UTLB Address Array............................................................................................ 186 7.6.4 UTLB Data Array ................................................................................................. 187 32-Bit Address Extended Mode ......................................................................................... 188 7.7.1 Overview of 32-Bit Address Extended Mode....................................................... 189 7.7.2 Transition to 32-Bit Address Extended Mode ...................................................... 189 7.7.3 Privileged Space Mapping Buffer (PMB) Configuration ..................................... 189 7.7.4 PMB Function....................................................................................................... 191 Rev.1.00 Dec. 13, 2005 Page xi of l 7.7.5 7.7.6 Memory-Mapped PMB Configuration.................................................................. 192 Notes on Using 32-Bit Address Extended Mode .................................................. 194 Section 8 Caches................................................................................................ 197 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Features.............................................................................................................................. 197 Register Descriptions......................................................................................................... 200 8.2.1 Cache Control Register (CCR) ............................................................................. 201 8.2.2 Queue Address Control Register 0 (QACR0)....................................................... 203 8.2.3 Queue Address Control Register 1 (QACR1)....................................................... 204 8.2.4 On-Chip Memory Control Register (RAMCR) .................................................... 205 Operand Cache Operation.................................................................................................. 207 8.3.1 Read Operation ..................................................................................................... 207 8.3.2 Prefetch Operation ................................................................................................ 208 8.3.3 Write Operation .................................................................................................... 209 8.3.4 Write-Back Buffer ................................................................................................ 211 8.3.5 Write-Through Buffer........................................................................................... 211 8.3.6 OC Two-Way Mode ............................................................................................. 211 Instruction Cache Operation .............................................................................................. 212 8.4.1 Read Operation ..................................................................................................... 212 8.4.2 Prefetch Operation ................................................................................................ 213 8.4.3 IC Two-Way Mode............................................................................................... 213 Cache Operation Instruction .............................................................................................. 214 8.5.1 Coherency between Cache and External Memory ................................................ 214 8.5.2 Prefetch Operation ................................................................................................ 215 Memory-Mapped Cache Configuration ............................................................................. 216 8.6.1 IC Address Array.................................................................................................. 217 8.6.2 IC Data Array ....................................................................................................... 219 8.6.3 OC Address Array ................................................................................................ 220 8.6.4 OC Data Array...................................................................................................... 222 Store Queues ...................................................................................................................... 223 8.7.1 SQ Configuration.................................................................................................. 223 8.7.2 Writing to SQ........................................................................................................ 223 8.7.3 Transfer to External Memory ............................................................................... 224 8.7.4 Determination of SQ Access Exception................................................................ 225 8.7.5 Reading from SQ .................................................................................................. 225 Notes on Using 32-Bit Address Extended Mode ............................................................... 226 Section 9 L Memory.......................................................................................... 227 9.1 9.2 Features.............................................................................................................................. 227 Register Descriptions......................................................................................................... 228 Rev.1.00 Dec. 13, 2005 Page xii of l 9.3 9.4 9.5 9.6 9.2.1 On-Chip Memory Control Register (RAMCR) .................................................... 229 9.2.2 L Memory Transfer Source Address Register 0 (LSA0) ...................................... 230 9.2.3 L Memory Transfer Source Address Register 1 (LSA1) ...................................... 232 9.2.4 L Memory Transfer Destination Address Register 0 (LDA0) .............................. 234 9.2.5 L Memory Transfer Destination Address Register 1 (LDA1) .............................. 236 Operation ........................................................................................................................... 238 9.3.1 Access from the CPU and FPU............................................................................. 238 9.3.2 Access from the SuperHyway Bus Master Module .............................................. 238 9.3.3 Block Transfer ...................................................................................................... 238 L Memory Protective Functions ........................................................................................ 240 Usage Notes ....................................................................................................................... 241 9.5.1 Page Conflict ........................................................................................................ 241 9.5.2 L Memory Coherency ........................................................................................... 241 9.5.3 Sleep Mode ........................................................................................................... 241 Note on Using 32-Bit Address Extended Mode................................................................. 241 Section 10 Interrupt Controller (INTC) .............................................................243 10.1 Features.............................................................................................................................. 243 10.1.1 Interrupt Method ................................................................................................... 245 10.1.2 Interrupt Types in INTC ....................................................................................... 246 10.2 Input/Output Pins ............................................................................................................... 250 10.3 Register Descriptions ......................................................................................................... 251 10.3.1 Interrupt Control Register 0 (ICR0)...................................................................... 255 10.3.2 Interrupt Control Register 1 (ICR1)...................................................................... 258 10.3.3 Interrupt Priority Register (INTPRI)..................................................................... 259 10.3.4 Interrupt Source Register (INTREQ).................................................................... 260 10.3.5 Interrupt Mask Registers (INTMSK0 to INTMSK2)............................................ 261 10.3.6 Interrupt Mask Clear Registers (INTMSKCLR0 to INTMSKCLR2)................... 266 10.3.7 NMI Flag Control Register (NMIFCR) ................................................................ 271 10.3.8 User Interrupt Mask Level Register (USERIMASK) ........................................... 273 10.3.9 On-chip Module Interrupt Priority Registers (INT2PRI0 to INT2PRI7).............. 276 10.3.10 Interrupt Source Register (INT2A0: Not affected by Mask States) ...................... 277 10.3.11 Interrupt Source Register (INT2A1: Affected by Mask States)............................ 280 10.3.12 Interrupt Mask Register (INT2MSKR)................................................................. 282 10.3.13 Interrupt Mask Clear Register (INT2MSKCR)..................................................... 285 10.3.14 On-chip Module Interrupt Source Registers (INT2B0 to INT2B7) ...................... 287 10.3.15 GPIO Interrupt Set Register (INT2GPIC)............................................................. 294 10.4 Interrupt Sources................................................................................................................ 296 10.4.1 NMI Interrupt........................................................................................................ 296 10.4.2 IRQ Interrupts ....................................................................................................... 296 Rev.1.00 Dec. 13, 2005 Page xiii of l 10.4.3 IRL Interrupts ....................................................................................................... 297 10.4.4 On-chip Module Interrupts ................................................................................... 299 10.4.5 Interrupt Priority Levels of On-chip Module Interrupts ....................................... 300 10.4.6 Interrupt Exception Handling and Priority............................................................ 301 10.5 Operation ........................................................................................................................... 308 10.5.1 Interrupt Sequence ................................................................................................ 308 10.5.2 Multiple Interrupts ................................................................................................ 310 10.5.3 Interrupt Masking by MAI Bit.............................................................................. 310 10.6 Interrupt Response Time.................................................................................................... 311 10.7 Usage Notes ....................................................................................................................... 312 10.7.1 To Clear Interrupt Request When Holding Function Selected ............................. 312 10.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function ....................................................... 313 10.7.3 To clear IRQ and IRL interrupt requests .............................................................. 313 Section 11 Local Bus State Controller (LBSC)................................................. 315 11.1 Features.............................................................................................................................. 315 11.2 Input/Output Pins............................................................................................................... 318 11.3 Area Overview................................................................................................................... 320 11.3.1 Space Divisions .................................................................................................... 320 11.3.2 Memory Bus Width .............................................................................................. 324 11.3.3 Data Alignment..................................................................................................... 325 11.3.4 PCMCIA Support ................................................................................................. 325 11.4 Register Descriptions......................................................................................................... 329 11.4.1 Memory Address Map Select Register (MMSELR)............................................. 331 11.4.2 Bus Control Register (BCR) ................................................................................. 333 11.4.3 CSn Bus Control Register (CSnBCR) .................................................................. 336 11.4.4 CSn Wait Control Register (CSnWCR)................................................................ 342 11.4.5 CSn PCMCIA Control Register (CSnPCR).......................................................... 347 11.5 Operation ........................................................................................................................... 352 11.5.1 Endian/Access Size and Data Alignment.............................................................. 352 11.5.2 Areas..................................................................................................................... 357 11.5.3 SRAM interface .................................................................................................... 361 11.5.4 Burst ROM (Clock Asynchronous) Interface ....................................................... 370 11.5.5 PCMCIA Interface................................................................................................ 372 11.5.6 MPX Interface ...................................................................................................... 383 11.5.7 Byte Control SRAM Interface .............................................................................. 389 11.5.8 Wait Cycles between Accesses............................................................................. 393 11.5.9 Bus Arbitration ..................................................................................................... 395 11.5.10 Bus Release and Acquire Sequence...................................................................... 397 11.5.11 Cooperation between Master and Slave................................................................ 399 Rev.1.00 Dec. 13, 2005 Page xiv of l Section 12 DDR-SDRAM Interface (DDRIF)...................................................401 12.1 Features.............................................................................................................................. 401 12.2 Input/Output Pins ............................................................................................................... 403 12.3 Address Space, Bus Width, and Data Alignment............................................................... 404 12.3.1 Address Space of the DDRIF................................................................................ 404 12.3.2 Memory Data Bus Width ...................................................................................... 405 12.3.3 Data Alignment..................................................................................................... 406 12.4 Register Descriptions ......................................................................................................... 410 12.4.1 Memory Interface Mode Register (MIM) ............................................................. 412 12.4.2 SDRAM Control Register (SCR).......................................................................... 416 12.4.3 SDRAM Timing Register (STR) .......................................................................... 418 12.4.4 SDRAM Row Attribute Register (SDR)............................................................... 421 12.4.5 SDRAM Mode Register (SDMR)......................................................................... 422 12.4.6 DDR-SDRAM Back-up Register (DBK).............................................................. 424 12.5 Operation ........................................................................................................................... 425 12.5.1 DDR-SDRAM Access .......................................................................................... 425 12.5.2 DDR-SDRAM Initialization Sequence................................................................. 425 12.5.3 Supported SDRAM Commands............................................................................ 426 12.5.4 SDRAM Access Mode.......................................................................................... 427 12.5.5 Power-Down Modes ............................................................................................. 427 12.5.6 Address Multiplexing ........................................................................................... 429 12.6 DDR-SDRAM Basic Timing ............................................................................................. 430 12.7 Usage Notes ....................................................................................................................... 440 12.7.1 Operating Frequency............................................................................................. 440 12.7.2 Stopping Clock ..................................................................................................... 440 12.7.3 Using SCR to Issue REFA Command (Outside the Initialization Sequence) ....... 440 12.7.4 Timing of Connected SDRAM ............................................................................. 440 12.7.5 Setting Auto-Refresh Interval ............................................................................... 441 Section 13 PCI Controller (PCIC) .....................................................................443 13.1 Features.............................................................................................................................. 443 13.2 Input/Output Pins ............................................................................................................... 446 13.3 Register Descriptions ......................................................................................................... 449 13.3.1 PCIC Enable Control Register (PCIECR) ............................................................ 455 13.3.2 Configuration Registers ........................................................................................ 456 13.3.3 Local Register ....................................................................................................... 481 13.4 Operation ........................................................................................................................... 522 13.4.1 Supported PCI Commands.................................................................................... 522 13.4.2 PCIC Initialization ................................................................................................ 523 13.4.3 Master Access ....................................................................................................... 524 Rev.1.00 Dec. 13, 2005 Page xv of l 13.4.4 13.4.5 13.4.6 13.4.7 13.4.8 Target Access........................................................................................................ 532 Host Bus Bridge Mode ......................................................................................... 541 Normal mode ........................................................................................................ 544 Power Management .............................................................................................. 544 PCI Local Bus Basic Interface.............................................................................. 545 Section 14 Direct Memory Access Controller (DMAC)................................... 557 14.1 Features.............................................................................................................................. 557 14.2 Input/Output Pins............................................................................................................... 559 14.3 Register Descriptions......................................................................................................... 561 14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11) ................................. 567 14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9) .............................................................. 568 14.3.3 DMA Destination Address Registers 0 to 11 (DAR0 to DAR11) ........................ 568 14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9 (DARB0 to DARB3, DARB6 to DARB9) ........................................................... 569 14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11).................................. 570 14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9 (TCRB0 to TCRB3, TCRB6 to TCRB9) .............................................................. 571 14.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) ......................... 572 14.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1) .................................. 581 14.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2)............................. 584 14.4 Operation ........................................................................................................................... 588 14.4.1 DMA Transfer Requests ....................................................................................... 588 14.4.2 Channel Priority.................................................................................................... 592 14.4.3 DMA Transfer Types............................................................................................ 595 14.4.4 DMA Transfer Flow ............................................................................................. 602 14.4.5 Repeat Mode Transfer .......................................................................................... 604 14.4.6 Reload Mode Transfer .......................................................................................... 605 14.4.7 DREQ Pin Sampling Timing ................................................................................ 606 14.5 Usage Notes ....................................................................................................................... 608 14.5.1 Module Stop ......................................................................................................... 608 14.5.2 Address Error........................................................................................................ 608 14.5.3 Notes on Burst Mode Transfer.............................................................................. 608 14.5.4 DACK output division .......................................................................................... 609 14.5.5 Clear DMINT Interrupt......................................................................................... 609 14.5.6 CS Output Settings and Transfer Size Larger than External Bus Width............... 609 14.5.7 DACK Assertion and DREQ Sampling ................................................................ 609 Rev.1.00 Dec. 13, 2005 Page xvi of l Section 15 Clock Pulse Generator (CPG)..........................................................613 15.1 15.2 15.3 15.4 Features.............................................................................................................................. 613 Input/Output Pins ............................................................................................................... 616 Clock Operating Modes ..................................................................................................... 617 Register Descriptions ......................................................................................................... 618 15.4.1 Frequency Control Register (FRQCR) ................................................................. 619 15.4.2 PLL Control Register (PLLCR)............................................................................ 621 15.5 Notes on Board Design ...................................................................................................... 622 Section 16 Watchdog Timer and Reset..............................................................625 16.1 Features.............................................................................................................................. 625 16.2 Input/Output Pins ............................................................................................................... 627 16.3 Register Descriptions ......................................................................................................... 628 16.3.1 Watchdog Timer Stop Time Register (WDTST) .................................................. 629 16.3.2 Watchdog Timer Control/Status Register (WDTCSR)......................................... 630 16.3.3 Watchdog timer Base Stop Time Register (WDTBST) ........................................ 631 16.3.4 Watchdog Timer Counter (WDTCNT)................................................................. 632 16.3.5 Watchdog Timer Base Counter (WDTBCNT) ..................................................... 632 16.4 Operation ........................................................................................................................... 633 16.4.1 Reset request......................................................................................................... 633 16.4.2 Using watchdog timer mode ................................................................................. 634 16.4.3 Using Interval timer mode .................................................................................... 634 16.4.4 Time for WDT Overflow ...................................................................................... 635 16.4.5 Clearing WDT Counter......................................................................................... 636 16.5 Status Pin Change Timing during Reset ............................................................................ 636 16.5.1 Power-On Reset by PRESET................................................................................ 636 16.5.2 Power-On Reset by Watchdog Timer Overflow................................................... 638 16.5.3 Manual Reset by Watchdog Timer Overflow ....................................................... 640 Section 17 Power-Down Mode..........................................................................643 17.1 Features.............................................................................................................................. 643 17.1.1 Types of Power-Down Modes .............................................................................. 643 17.2 Input/Output Pins ............................................................................................................... 645 17.3 Register Descriptions ......................................................................................................... 645 17.3.1 Standby Control Register (MSTPCR)................................................................... 646 17.4 Sleep Mode ........................................................................................................................ 648 17.4.1 Transition to Sleep mode ...................................................................................... 648 17.4.2 Cancellation of Sleep Mode.................................................................................. 648 Rev.1.00 Dec. 13, 2005 Page xvii of l 17.5 Module Standby State ........................................................................................................ 649 17.5.1 Transition to Module Standby Mode .................................................................... 649 17.5.2 Cancellation of Module Standby Mode and Resume............................................ 649 17.6 DDR-SDRAM Power Supply Backup............................................................................... 650 17.6.1 Self-Refresh and Initialization .............................................................................. 650 17.6.2 DDR-SDRAM Backup Sequence when Turning Off System Power Supply ....... 651 17.7 RTC Power Supply Backup ............................................................................................... 653 17.7.1 Transition to RTC Power Supply Backup............................................................. 653 17.7.2 Cancellation of RTC Power Supply Backup......................................................... 653 17.8 Mode Transitions ............................................................................................................... 655 17.9 STATUS Pin Change Timing ............................................................................................ 656 17.9.1 In Reset ................................................................................................................. 656 17.9.2 In Sleep ................................................................................................................. 656 Section 18 Timer Unit (TMU)........................................................................... 657 18.1 Features.............................................................................................................................. 657 18.2 Input/Output Pins............................................................................................................... 659 18.3 Register Descriptions......................................................................................................... 660 18.3.1 Timer Output Control Register (TOCR)............................................................... 662 18.3.2 Timer Start Register (TSTR0, TSTR1)................................................................. 663 18.3.3 Timer Constant Register (TCORn) (n = 0 to 5) .................................................... 665 18.3.4 Timer Counter (TCNTn) (n = 0 to 5).................................................................... 665 18.3.5 Timer Control Registers (TCRn) (n = 0 to 5) ....................................................... 666 18.3.6 Input Capture Register 2 (TCPR2) ....................................................................... 668 18.4 Operation ........................................................................................................................... 669 18.4.1 Counter Operation ................................................................................................ 669 18.4.2 Input Capture Function ......................................................................................... 673 18.5 Interrupts............................................................................................................................ 674 18.6 Usage Notes ....................................................................................................................... 675 18.6.1 Register Writes ..................................................................................................... 675 18.6.2 Reading from TCNT............................................................................................. 675 18.6.3 Reset RTC Frequency Divider Circuit.................................................................. 675 18.6.4 External Clock Frequency .................................................................................... 675 Section 19 Compare Match Timer (CMT) ........................................................ 677 19.1 Features.............................................................................................................................. 677 19.2 Input/Output Pins............................................................................................................... 679 19.3 Register Descriptions......................................................................................................... 679 19.3.1 Configuration Register (CMTCFG)...................................................................... 681 19.3.2 Free-Running Timer (CMTFRT).......................................................................... 684 Rev.1.00 Dec. 13, 2005 Page xviii of l 19.3.3 Control Register (CMTCTL) ................................................................................ 684 19.3.4 Interrupt Status Register (CMTIRQS) .................................................................. 688 19.3.5 Channels 0 to 3 Time Registers (CMTCH0T to CMTCH3T)............................... 689 19.3.6 Channels 0 to 1 Stop Time Registers (CMTCH0ST to CMTCH1ST).................. 689 19.3.7 Channels 0 to 3 Counters (CMTCH0C to CMTCH3C)........................................ 690 19.4 Operation ........................................................................................................................... 691 19.4.1 Edge Detection...................................................................................................... 691 19.4.2 32-Bit Timer: Input Capture ................................................................................. 692 19.4.3 32-Bit Timer: Output Compare............................................................................. 693 19.4.4 16-Bit Timer: Input Capture ................................................................................. 697 19.4.5 16-Bit Timer: Output Compare............................................................................. 699 19.4.6 Counter: Up-counter ............................................................................................. 701 19.4.7 Counter: Updown-counter .................................................................................... 703 19.4.8 Counter: Rotary Switch Operation of Updown-counter ....................................... 705 19.4.9 Interrupts............................................................................................................... 706 Section 20 Realtime Clock (RTC) .....................................................................707 20.1 Features.............................................................................................................................. 707 20.1.1 Block Diagram...................................................................................................... 708 20.2 Input/Output Pins ............................................................................................................... 709 20.3 Register Descriptions ......................................................................................................... 710 20.3.1 64 Hz Counter (R64CNT)..................................................................................... 712 20.3.2 Second Counter (RSECCNT) ............................................................................... 712 20.3.3 Minute Counter (RMINCNT) ............................................................................... 713 20.3.4 Hour Counter (RHRCNT)..................................................................................... 713 20.3.5 Day-of-Week Counter (RWKCNT)...................................................................... 714 20.3.6 Day Counter (RDAYCNT) ................................................................................... 715 20.3.7 Month Counter (RMONCNT) .............................................................................. 716 20.3.8 Year Counter (RYRCNT) ..................................................................................... 716 20.3.9 Second Alarm Register (RSECAR) ...................................................................... 717 20.3.10 Minute Alarm Register (RMINAR)...................................................................... 717 20.3.11 Hour Alarm Register (RHRAR) ........................................................................... 718 20.3.12 Day-of-Week Alarm Register (RWKAR)............................................................. 718 20.3.13 Day Alarm Register (RDAYAR).......................................................................... 719 20.3.14 Month Alarm Register (RMONAR) ..................................................................... 720 20.3.15 Year-Alarm Register (RYRAR)............................................................................ 720 20.3.16 RTC Control Register 1 (RCR1)........................................................................... 721 20.3.17 RTC Control Register 2 (RCR2)........................................................................... 723 20.3.18 RTC Control Register (RCR3).............................................................................. 726 Rev.1.00 Dec. 13, 2005 Page xix of l 20.4 Operation ........................................................................................................................... 727 20.4.1 Time Setting Procedures....................................................................................... 727 20.4.2 Time Reading Procedures..................................................................................... 728 20.4.3 Alarm Function..................................................................................................... 729 20.5 Interrupts............................................................................................................................ 730 20.6 Usage Notes ....................................................................................................................... 730 20.6.1 Register Initialization............................................................................................ 730 20.6.2 Crystal Oscillator Circuit ...................................................................................... 730 20.6.3 Interrupt source and request generating order....................................................... 732 Section 21 Serial Communication Interface with FIFO (SCIF)........................ 733 21.1 Features.............................................................................................................................. 733 21.2 Input/Output Pins............................................................................................................... 739 21.3 Register Descriptions......................................................................................................... 740 21.3.1 Receive Shift Register (SCRSR) .......................................................................... 742 21.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 742 21.3.3 Transmit Shift Register (SCTSR) ......................................................................... 743 21.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 743 21.3.5 Serial Mode Register (SCSMR)............................................................................ 744 21.3.6 Serial Control Register (SCSCR).......................................................................... 747 21.3.7 Serial Status Register n (SCFSR) ......................................................................... 751 21.3.8 Bit Rate Register n (SCBRR) ............................................................................... 758 21.3.9 FIFO Control Register n (SCFCR) ....................................................................... 759 21.3.10 Transmit FIFO Data Count Register n (SCTFDR) ............................................... 762 21.3.11 Receive FIFO Data Count Register n (SCRFDR)................................................. 763 21.3.12 Serial Port Register n (SCSPTR) .......................................................................... 764 21.3.13 Line Status Register n (SCLSR) ........................................................................... 767 21.3.14 Serial Error Register n (SCRER) .......................................................................... 768 21.4 Operation ........................................................................................................................... 769 21.4.1 Overview .............................................................................................................. 769 21.4.2 Operation in Asynchronous Mode ........................................................................ 772 21.4.3 Operation in Clocked Synchronous Mode ............................................................ 783 21.5 SCIF Interrupt Sources and the DMAC ............................................................................. 792 21.6 Usage Notes ....................................................................................................................... 794 Section 22 Serial I/O with FIFO (SIOF) ........................................................... 797 22.1 Features.............................................................................................................................. 797 22.2 Input/Output Pins............................................................................................................... 799 22.3 Register Descriptions......................................................................................................... 800 22.3.1 Mode Register (SIMDR) ...................................................................................... 802 Rev.1.00 Dec. 13, 2005 Page xx of l 22.3.2 Clock Select Register (SISCR) ............................................................................. 804 22.3.3 Control Register (SICTR) ..................................................................................... 806 22.3.4 Transmit Data Register (SITDR) .......................................................................... 809 22.3.5 Receive Data Register (SIRDR) ........................................................................... 810 22.3.6 Transmit Control Data Register (SITCR) ............................................................. 811 22.3.7 Receive Control Data Register (SIRCR) .............................................................. 812 22.3.8 Status Register (SISTR)........................................................................................ 813 22.3.9 Interrupt Enable Register (SIIER)......................................................................... 819 22.3.10 FIFO Control Register (SIFCTR) ......................................................................... 821 22.3.11 Transmit Data Assign Register (SITDAR) ........................................................... 823 22.3.12 Receive Data Assign Register (SIRDAR)............................................................. 824 22.3.13 Control Data Assign Register (SICDAR) ............................................................. 825 22.4 Operation ........................................................................................................................... 827 22.4.1 Serial Clocks ......................................................................................................... 827 22.4.2 Serial Timing ........................................................................................................ 829 22.4.3 Transfer Data Format............................................................................................ 830 22.4.4 Register Allocation of Transfer Data .................................................................... 832 22.4.5 Control Data Interface .......................................................................................... 834 22.4.6 FIFO...................................................................................................................... 836 22.4.7 Transmit and Receive Procedures......................................................................... 838 22.4.8 Interrupts............................................................................................................... 843 22.4.9 Transmit and Receive Timing............................................................................... 845 Section 23 Serial Protocol Interface (HSPI) ......................................................849 23.1 Features.............................................................................................................................. 849 23.2 Input/Output Pins ............................................................................................................... 851 23.3 Register Descriptions ......................................................................................................... 851 23.3.1 Control Register (SPCR)....................................................................................... 852 23.3.2 Status Register (SPSR) ......................................................................................... 854 23.3.3 System Control Register (SPSCR)........................................................................ 857 23.3.4 Transmit Buffer Register (SPTBR)....................................................................... 859 23.3.5 Receive Buffer Register (SPRBR)........................................................................ 860 23.4 Operation ........................................................................................................................... 861 23.4.1 Operation Overview without DMA (FIFO Mode Disabled)................................. 861 23.4.2 Operation Overview with DMA ........................................................................... 862 23.4.3 Operation with FIFO Mode Enabled .................................................................... 862 23.4.4 Timing Diagrams .................................................................................................. 863 23.4.5 HSPI Software Reset ............................................................................................ 864 23.4.6 Clock Polarity and Transmit Control .................................................................... 864 23.4.7 Transmit and Receive Routines ............................................................................ 864 Rev.1.00 Dec. 13, 2005 Page xxi of l Section 24 Multimedia Card Interface (MMCIF) ............................................. 865 24.1 Features.............................................................................................................................. 865 24.2 Input/Output Pins............................................................................................................... 866 24.3 Register Descriptions......................................................................................................... 867 24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)................................................ 871 24.3.2 Command Start Register (CMDSTRT) ................................................................ 872 24.3.3 Operation Control Register (OPCR)..................................................................... 873 24.3.4 Card Status Register (CSTR)................................................................................ 875 24.3.5 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)..................................... 877 24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) ................................... 880 24.3.7 Transfer Clock Control Register (CLKON).......................................................... 885 24.3.8 Command Timeout Control Register (CTOCR) ................................................... 886 24.3.9 Transfer Byte Number Count Register (TBCR) ................................................... 887 24.3.10 Mode Register (MODER)..................................................................................... 888 24.3.11 Command Type Register (CMDTYR).................................................................. 889 24.3.12 Response Type Register (RSPTYR)..................................................................... 890 24.3.13 Transfer Block Number Counter (TBNCR).......................................................... 894 24.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD).............................. 895 24.3.15 Data Timeout Register (DTOUTR) ...................................................................... 897 24.3.16 Data Register (DR) ............................................................................................... 898 24.3.17 FIFO Pointer Clear Register (FIFOCLR) ............................................................. 899 24.3.18 DMA Control Register (DMACR) ....................................................................... 900 24.4 Operation ........................................................................................................................... 901 24.4.1 Operations in MMC Mode.................................................................................... 901 24.5 MMCIF Interrupt Sources.................................................................................................. 931 24.6 Operations when Using DMA ........................................................................................... 932 24.6.1 Operation in Read Sequence................................................................................. 932 24.6.2 Operation in Write Sequence ................................................................................ 942 24.7 Register Accesses with Little Endian Specification........................................................... 953 Section 25 Audio Codec Interface (HAC)......................................................... 955 25.1 Features.............................................................................................................................. 955 25.2 Input/Output Pins............................................................................................................... 956 25.3 Register Descriptions......................................................................................................... 957 25.3.1 Control and Status Register (HACCR) ................................................................. 958 25.3.2 Command/Status Address Register (HACCSAR) ................................................ 960 25.3.3 Command/Status Data Register (HACCSDR)...................................................... 962 25.3.4 PCM Left Channel Register (HACPCML)........................................................... 963 25.3.5 PCM Right Channel Register (HACPCMR) ........................................................ 965 25.3.6 TX Interrupt Enable Register (HACTIER)........................................................... 966 Rev.1.00 Dec. 13, 2005 Page xxii of l 25.3.7 TX Status Register (HACTSR)............................................................................. 967 25.3.8 RX Interrupt Enable Register (HACRIER)........................................................... 969 25.3.9 RX Status Register (HACRSR) ............................................................................ 970 25.3.10 HAC Control Register (HACACR) ...................................................................... 971 25.4 AC 97 Frame Slot Structure............................................................................................... 973 25.5 Operation ........................................................................................................................... 974 25.5.1 Receiver ................................................................................................................ 974 25.5.2 Transmitter............................................................................................................ 975 25.5.3 DMA ..................................................................................................................... 975 25.5.4 Interrupts............................................................................................................... 975 25.5.5 Initialization Sequence.......................................................................................... 976 25.5.6 Notes ..................................................................................................................... 981 25.5.7 Reference .............................................................................................................. 981 Section 26 Serial Sound Interface (SSI) Module...............................................983 26.1 Features.............................................................................................................................. 983 26.2 Input/Output Pins ............................................................................................................... 984 26.3 Register Descriptions ......................................................................................................... 985 26.3.1 Control Register (SSICR) ..................................................................................... 986 26.3.2 Status Register (SSISR) ........................................................................................ 992 26.3.3 Transmit Data Register (SSITDR)........................................................................ 997 26.3.4 Receive Data Register (SSIRDR) ......................................................................... 997 26.4 Operation ........................................................................................................................... 998 26.4.1 Bus Format............................................................................................................ 998 26.4.2 Non-Compressed Modes....................................................................................... 999 26.4.3 Compressed Modes............................................................................................. 1008 26.4.4 Operation Modes................................................................................................. 1011 26.4.5 Transmit Operation ............................................................................................. 1012 26.4.6 Receive Operation............................................................................................... 1015 26.4.7 Serial Clock Control ........................................................................................... 1018 26.5 Usage Note....................................................................................................................... 1019 26.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation .......... 1019 Section 27 NAND Flash Memory Controller (FLCTL) ..................................1021 27.1 Features............................................................................................................................ 1021 27.2 Input/Output Pins ............................................................................................................. 1024 27.3 Register Descriptions ....................................................................................................... 1025 27.3.1 Common Control Register (FLCMNCR)............................................................ 1026 27.3.2 Command Control Register (FLCMDCR).......................................................... 1028 27.3.3 Command Code Register (FLCMCDR) ............................................................. 1030 Rev.1.00 Dec. 13, 2005 Page xxiii of l 27.4 27.5 27.6 27.7 27.3.4 Address Register (FLADR) ................................................................................ 1030 27.3.5 Data Counter Register (FLDTCNTR) ................................................................ 1032 27.3.6 Data Register (FLDATAR) ................................................................................ 1033 27.3.7 Interrupt DMA Control Register (FLINTDMACR) ........................................... 1034 27.3.8 Ready Busy Timeout Setting Register (FLBSYTMR) ....................................... 1039 27.3.9 Ready Busy Timeout Counter (FLBSYCNT)..................................................... 1040 27.3.10 Data FIFO Register (FLDTFIFO)....................................................................... 1041 27.3.11 Control Code FIFO Register (FLECFIFO)......................................................... 1042 27.3.12 Transfer Control Register (FLTRCR)................................................................. 1043 Operation ......................................................................................................................... 1044 27.4.1 Operating Modes ................................................................................................ 1044 27.4.2 Command Access Mode ..................................................................................... 1044 27.4.3 Sector Access Mode ........................................................................................... 1046 27.4.4 ECC Error Correction ......................................................................................... 1048 27.4.5 Status Read ......................................................................................................... 1049 Example of Register Setting ............................................................................................ 1050 Interrupt Sources.............................................................................................................. 1053 DMA Transfer Specifications .......................................................................................... 1053 Section 28 General Purpose I/O (GPIO) ......................................................... 1055 28.1 Features............................................................................................................................ 1055 28.2 Register Descriptions....................................................................................................... 1060 28.2.1 Port A Control Register (PACR) ........................................................................ 1063 28.2.2 Port B Control Register (PBCR)......................................................................... 1064 28.2.3 Port C Control Register (PCCR)......................................................................... 1066 28.2.4 Port D Control Register (PDCR) ........................................................................ 1067 28.2.5 Port E Control Register (PECR) ......................................................................... 1069 28.2.6 Port F Control Register (PFCR).......................................................................... 1070 28.2.7 Port G Control Register (PGCR) ........................................................................ 1072 28.2.8 Port H Control Register (PHCR) ........................................................................ 1074 28.2.9 Port J Control Register (PJCR) ........................................................................... 1075 28.2.10 Port K Control Register (PKCR) ........................................................................ 1077 28.2.11 Port L Control Register (PLCR) ......................................................................... 1079 28.2.12 Port M Control Register (PMCR) ....................................................................... 1080 28.2.13 Port A Data Register (PADR)............................................................................. 1081 28.2.14 Port B Data Register (PBDR) ............................................................................. 1081 28.2.15 Port C Data Register (PCDR) ............................................................................. 1082 28.2.16 Port D Data Register (PDDR)............................................................................. 1082 28.2.17 Port E Data Register (PEDR).............................................................................. 1083 28.2.18 Port F Data Register (PFDR) .............................................................................. 1084 Rev.1.00 Dec. 13, 2005 Page xxiv of l 28.2.19 Port G Data Register (PGDR)............................................................................. 1084 28.2.20 Port H Data Register (PHDR)............................................................................. 1085 28.2.21 Port J Data Register (PJDR) ............................................................................... 1085 28.2.22 Port K Data Register (PKDR)............................................................................. 1086 28.2.23 Port L Data Register (PLDR).............................................................................. 1086 28.2.24 Port M Data Register (PMDR) ........................................................................... 1087 28.2.25 Port E Pull-Up Control Register (PEPUPR) ....................................................... 1087 28.2.26 Port H Pull-Up Control Register (PHPUPR) ...................................................... 1088 28.2.27 Port J Pull-Up Control Register (PJPUPR)......................................................... 1089 28.2.28 Port K Pull-Up Control Register (PKPUPR) ...................................................... 1090 28.2.29 Port M Pull-Up Control Register (PMPUPR)..................................................... 1091 28.2.30 Input-Pin Pull-Up Control Register 1 (PPUPR1)................................................ 1092 28.2.31 Input-Pin Pull-Up Control Register 2 (PPUPR2)................................................ 1093 28.2.32 On-chip Module Select Register (OMSELR) ..................................................... 1094 28.3 Usage Example ................................................................................................................ 1097 28.3.1 Port Output Function .......................................................................................... 1097 28.3.2 Port Input function .............................................................................................. 1098 28.3.3 On-chip Module Function................................................................................... 1099 Section 29 User Break Controller (UBC) ........................................................1101 29.1 Features............................................................................................................................ 1101 29.2 Register Descriptions ....................................................................................................... 1103 29.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ......................... 1105 29.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ......................... 1111 29.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)............................ 1113 29.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)........... 1114 29.2.5 Match Data Setting Register 1 (CDR1) .............................................................. 1115 29.2.6 Match Data Mask Setting Register 1 (CDMR1) ................................................. 1116 29.2.7 Execution Count Break Register 1 (CETR1) ...................................................... 1117 29.2.8 Channel Match Flag Register (CCMFR) ............................................................ 1118 29.2.9 Break Control Register (CBCR) ......................................................................... 1119 29.3 Operation Description ...................................................................................................... 1120 29.3.1 Definition of Words Related to Accesses ........................................................... 1120 29.3.2 User Break Operation Sequence ......................................................................... 1121 29.3.3 Instruction Fetch Cycle Break ............................................................................ 1122 29.3.4 Operand Access Cycle Break.............................................................................. 1123 29.3.5 Sequential Break ................................................................................................. 1124 29.3.6 Program Counter Value to be Saved................................................................... 1126 29.4 User Break Debugging Support Function ........................................................................ 1127 29.5 User Break Examples....................................................................................................... 1128 Rev.1.00 Dec. 13, 2005 Page xxv of l 29.6 Usage Notes ..................................................................................................................... 1132 Section 30 User Debugging Interface (H-UDI)............................................... 1135 30.1 Features............................................................................................................................ 1135 30.2 Input/Output Pins............................................................................................................. 1137 30.3 Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS) .......................................... 1138 30.4 Register Descriptions....................................................................................................... 1140 30.4.1 Instruction Register (SDIR) ................................................................................ 1141 30.4.2 Interrupt Source Register (SDINT)..................................................................... 1142 30.4.3 Bypass Register (SDBPR) .................................................................................. 1142 30.4.4 Boundary Scan Register (SDBSR) ..................................................................... 1143 30.5 Operation ......................................................................................................................... 1152 30.5.1 TAP Control ....................................................................................................... 1152 30.5.2 H-UDI Reset ....................................................................................................... 1153 30.5.3 H-UDI Interrupt .................................................................................................. 1153 30.6 Usage Notes ..................................................................................................................... 1154 Section 31 Electrical Characteristics ............................................................... 1155 31.1 Absolute Maximum Ratings ............................................................................................ 1155 31.2 DC Characteristics ........................................................................................................... 1156 31.3 AC Characteristics ........................................................................................................... 1159 31.3.1 Clock and Control Signal Timing ....................................................................... 1160 31.3.2 Control Signal Timing ........................................................................................ 1163 31.3.3 Bus Timing ......................................................................................................... 1164 31.3.4 DDRIF Signal Timing ........................................................................................ 1182 31.3.5 INTC Module Signal Timing.............................................................................. 1186 31.3.6 PCIC Module Signal Timing .............................................................................. 1188 31.3.7 DMAC Module Signal Timing ........................................................................... 1190 31.3.8 TMU Module Signal Timing .............................................................................. 1191 31.3.9 CMT Module Signal Timing .............................................................................. 1192 31.3.10 SCIF Module Signal Timing............................................................................... 1193 31.3.11 SIOF Module Signal Timing .............................................................................. 1195 31.3.12 HSPI Module Signal Timing .............................................................................. 1199 31.3.13 MMCIF Module Signal Timing.......................................................................... 1201 31.3.14 HAC Interface Module Signal Timing ............................................................... 1203 31.3.15 SSI Interface Module Signal Timing .................................................................. 1205 31.3.16 FLCTL Module Signal Timing........................................................................... 1207 31.3.17 GPIO Signal Timing ........................................................................................... 1211 31.3.18 H-UDI Module Signal Timing............................................................................ 1212 Rev.1.00 Dec. 13, 2005 Page xxvi of l 31.4 AC Characteristic Test Conditions................................................................................... 1214 31.5 Change in Delay Time Based on Load Capacitance ........................................................ 1215 Appendix ..........................................................................................................1217 A. B. C. D. E. F. G. H. I. J. CPU Operation Mode Register (CPUOPM) .................................................................... 1217 Instruction Prefetching and Its Side Effects..................................................................... 1219 Speculative Execution for Subroutine Return.................................................................. 1220 Register Address Map...................................................................................................... 1221 Package Dimensions ........................................................................................................ 1255 Mode Pin Settings ............................................................................................................ 1256 Pin Functions ................................................................................................................... 1258 G.1 Pin States ............................................................................................................ 1258 G.2 Handling of Unused Pins .................................................................................... 1267 Turning On and Off Power Supply .................................................................................. 1275 Version Registers (PVR, PRR) ........................................................................................ 1276 Part Number List.............................................................................................................. 1277 Index ................................................................................................................1279 Rev.1.00 Dec. 13, 2005 Page xxvii of l Rev.1.00 Dec. 13, 2005 Page xxviii of l Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Overview SH7780 Block Diagram ................................................................................................ 9 SH7780 Pin Arrangement............................................................................................ 10 Physical Address Space of SH7780............................................................................. 28 Relationship between AREASEL Bits and Memory Address Map............................. 29 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Programming Model Data Formats ............................................................................................................... 33 CPU Register Configuration in Each Processing Mode .............................................. 36 General Registers ........................................................................................................ 37 Floating-Point Registers .............................................................................................. 39 Relationship between SZ bit and Endian..................................................................... 45 Formats of Byte Data and Word Data in Register ....................................................... 47 Data Formats in Memory............................................................................................. 48 Processing State Transitions........................................................................................ 49 Section 4 Figure 4.1 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Pipelining Basic Pipelines ............................................................................................................ 73 Instruction Execution Patterns (1) ............................................................................... 75 Instruction Execution Patterns (2) ............................................................................... 76 Instruction Execution Patterns (3) ............................................................................... 77 Instruction Execution Patterns (4) ............................................................................... 78 Instruction Execution Patterns (5) ............................................................................... 79 Instruction Execution Patterns (6) ............................................................................... 80 Instruction Execution Patterns (7) ............................................................................... 81 Instruction Execution Patterns (8) ............................................................................... 82 Instruction Execution Patterns (9) ............................................................................... 83 Section 5 Exception Handling Figure 5.1 Instruction Execution and Exception Handling......................................................... 105 Figure 5.2 Example of General Exception Acceptance Order .................................................... 106 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Floating-Point Unit (FPU) Format of Single-Precision Floating-Point Number.................................................. 130 Format of Double-Precision Floating-Point Number ................................................ 130 Single-Precision NaN Bit Pattern .............................................................................. 133 Floating-Point Registers ............................................................................................ 136 Relation between SZ Bit and Endian......................................................................... 139 Rev.1.00 Dec. 13, 2005 Page xxix of l Section 7 Memory Management Unit (MMU) Figure 7.1 Role of MMU............................................................................................................ 149 Figure 7.2 Virtual Address Space (AT in MMUCR = 0)............................................................ 150 Figure 7.3 Virtual Address Space (AT in MMUCR = 1)............................................................ 151 Figure 7.4 P4 Area...................................................................................................................... 153 Figure 7.5 Physical Address Space............................................................................................. 154 Figure 7.6 UTLB Configuration ................................................................................................. 167 Figure 7.7 Relationship between Page Size and Address Format............................................... 169 Figure 7.8 ITLB Configuration................................................................................................... 170 Figure 7.9 Flowchart of Memory Access Using UTLB.............................................................. 171 Figure 7.10 Flowchart of Memory Access Using ITLB ............................................................. 172 Figure 7.11 Operation of LDTLB Instruction............................................................................. 175 Figure 7.12 Memory-Mapped ITLB Address Array................................................................... 184 Figure 7.13 Memory-Mapped ITLB Data Array ........................................................................ 185 Figure 7.14 Memory-Mapped UTLB Address Array ................................................................. 187 Figure 7.15 Memory-Mapped UTLB Data Array....................................................................... 188 Figure 7.16 Physical Address Space (32-Bit Address Extended Mode)..................................... 188 Figure 7.17 PMB Configuration ................................................................................................. 190 Figure 7.18 Memory-Mapped PMB Address Array ................................................................... 193 Figure 7.19 Memory-Mapped PMB Data Array......................................................................... 193 Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Caches Configuration of Operand Cache (OC) ..................................................................... 198 Configuration of Instruction Cache (IC) ................................................................... 199 Configuration of Write-Back Buffer ......................................................................... 211 Configuration of Write-Through Buffer.................................................................... 211 Memory-Mapped IC Address Array ......................................................................... 218 Memory-Mapped IC Data Array ............................................................................... 219 Memory-Mapped OC Address Array........................................................................ 221 Memory-Mapped OC Data Array ............................................................................. 222 Store Queue Configuration........................................................................................ 223 Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Interrupt Controller (INTC) Block Diagram of INTC.......................................................................................... 244 Example of IRL Interrupt Connection..................................................................... 297 On-chip Module Interrupt Priority .......................................................................... 301 Interrupt Operation Flowchart................................................................................. 309 Example of Interrupt Handling Routine .................................................................. 312 Section 11 Local Bus State Controller (LBSC) Figure 11.1 LBSC Block Diagram ............................................................................................. 317 Rev.1.00 Dec. 13, 2005 Page xxx of l Figure 11.2 Correspondence between Virtual Address Space and External Memory Space of LBSC........................................................................................................ 321 Figure 11.3 External Memory Space Allocation (29-bit address mode)..................................... 323 Figure 11.4 Basic Timing of SRAM Interface............................................................................ 362 Figure 11.5 Example of 32-Bit Data-Width SRAM Connection ................................................ 363 Figure 11.6 Example of 16-Bit Data-Width SRAM Connection ................................................ 364 Figure 11.7 Example of 8-Bit Data-Width SRAM Connection .................................................. 365 Figure 11.8 SRAM Interface Wait Timing (Software Wait Only) ............................................. 366 Figure 11.9 SRAM Interface Wait Timing (Wait Cycle Insertion by RDY Signal, RDY Signal is synchronous input) ............ 367 Figure 11.10 SRAM Interface Wait Timing (Read-Strobe Negate Timing Setting) .................. 369 Figure 11.11 Burst ROM Basic Timing...................................................................................... 371 Figure 11.12 Burst ROM Wait Timing....................................................................................... 371 Figure 11.13 Burst ROM Wait Timing....................................................................................... 372 Figure 11.14 CExx and DACK Output of ATA Complement Mode in DMA Transfer............. 374 Figure 11.15 Example of PCMCIA Interface ............................................................................. 377 Figure 11.16 Basic Timing for PCMCIA Memory Card Interface ............................................. 378 Figure 11.17 Wait Timing for PCMCIA Memory Card Interface .............................................. 379 Figure 11.18 Basic Timing for PCMCIA I/O Card Interface ..................................................... 380 Figure 11.19 Wait Timing for PCMCIA I/O Card Interface ...................................................... 381 Figure 11.20 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................. 382 Figure 11.21 Example of 32-Bit Data Width MPX Connection ................................................. 384 Figure 11.22 MPX Interface Timing 1 (Single Read Cycle, IW = 0, No External Wait) ........... 384 Figure 11.23 MPX Interface Timing 2 (Single Read, IW = 0, One External Wait Inserted)...... 385 Figure 11.24 MPX Interface Timing 3 (Single Write Cycle, IW = 0, No External Wait) .......... 385 Figure 11.25 MPX Interface Timing 4 (Single Write Cycle, IW = 1, One External Wait Inserted).................................. 386 Figure 11.26 MPX Interface Timing 5 (Burst Read Cycle, IW = 0, No External Wait, 32-Byte Data Transfer) ............... 386 Figure 11.27 MPX Interface Timing 6 (Burst Read Cycle, IW = 0, External Wait Control, 32-Byte Data Transfer)........ 387 Figure 11.28 MPX Interface Timing 7 (Burst Write Cycle, IW = 0, No External Wait, 32-Byte Data Transfer) .............. 387 Figure 11.29 MPX Interface Timing 8 (Burst Write Cycle, IW = 1, External Wait Control, 32-Byte Data Transfer) ....... 388 Figure 11.30 Example of 32-Bit Data-Width Byte-Control SRAM ........................................... 389 Figure 11.31 Byte-Control SRAM Basic Read Cycle (No Wait) ............................................... 390 Figure 11.32 Byte-Control SRAM Basic Read Cycle (One Internal Wait Cycle)...................... 391 Figure 11.33 Byte-Control SRAM Basic Read Cycle (One Internal Wait + One External Wait).............................................................. 392 Rev.1.00 Dec. 13, 2005 Page xxxi of l Figure 11.34 Wait Cycles between Access Cycles ..................................................................... 394 Figure 11.35 Arbitration Sequence............................................................................................. 396 Figure 11.36 Example of the Bus Release Restraint by the DMAC CHCR LCKN bit .............. 398 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 DDR-SDRAM Interface (DDRIF) DDRIF Block Diagram ........................................................................................... 402 Physical Address Space of This LSI ....................................................................... 405 Data Alignment in DDR-SDRAM and DDRIF....................................................... 409 Relationship between Write Values in SDMR and Output Signals to Memory Pins .............................................................................. 423 Figure 12.5 DDRIF Basic Timing (1-/2-/4-/8-Byte Single Burst Read without Auto Precharge) ................................. 430 Figure 12.6 DDRIF Basic Timing (1-/2-/4-/8-Byte Single Burst Write without Auto Precharge) ................................ 431 Figure 12.7 DDRIF Basic Timing (1-/2-/4-/8-Byte Single Burst Read with Auto Precharge)... 432 Figure 12.8 DDRIF Basic Timing (1-/2-/4-/8-Byte Single Burst Write with Auto Precharge) ..................................... 433 Figure 12.9 DDRIF Basic Timing (4 Burst Read: 32-byte without Auto Precharge)................. 434 Figure 12.10 DDRIF Basic Timing (4 Burst Write: 32-byte without Auto Precharge).............. 435 Figure 12.11 DDRIF Basic Timing (from Precharging All Banks to Bank Activation)............. 436 Figure 12.12 DDRIF Basic Timing (Mode Register Setting)..................................................... 437 Figure 12.13 DDRIF Basic Timing (Enter Auto-Refresh/Exit to Bank Activation)................... 438 Figure 12.14 DDRIF Basic Timing (Enter Self-Refresh/Exit to Command Issuing) ................. 439 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 PCI Controller (PCIC) PCIC Block Diagram .............................................................................................. 445 SuperHyway Bus to PCI Local Bus Access ............................................................ 525 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 0) ........................................................................................... 526 Figure 13.4 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 1) ........................................................................................... 527 Figure 13.5 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 2)............................................................................................ 527 Figure 13.6 SuperHyway Bus to PCI Local Bus Address Translation (PCI I/O) ....................... 528 Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Local bus (Non-Byte Swapping: TBS = 0) .............................................................................. 530 Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local bus (Byte Swapping: TBS = 1)...................................................................................... 531 Figure 13.9 PCI local bus to SuperHyway bus Memory Map .................................................... 532 Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation (Local Address Space 0/1)..................................................................................... 534 Rev.1.00 Dec. 13, 2005 Page xxxii of l Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) ........ 535 Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 0) ............................................................................ 537 Figure 13.13 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 1) ............................................................................ 538 Figure 13.14 Cache Flush/Purge Execution Flow for PCI local Bus to SuperHyway Bus......... 540 Figure 13.15 Address Generation for Type 0 Configuration Access.......................................... 542 Figure 13.16 PCI Local Bus Power Down State Transition ....................................................... 545 Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)........................................ 546 Figure 13.18 Master Read Cycle in Host Bus Bridge Mode (Single)......................................... 547 Figure 13.19 Master Write Cycle in Normal Mode (Burst)........................................................ 548 Figure 13.20 Master Read Cycle in Normal Mode (Burst)......................................................... 549 Figure 13.21 Target Read Cycle in Normal Mode (Single)........................................................ 551 Figure 13.22 Target Write Cycle in Normal Mode (Single)....................................................... 552 Figure 13.23 Target Memory Read Cycle in Host Bus Bridge Mode (Burst) ............................ 553 Figure 13.24 Target Memory Write Cycle in Host Bus Bridge Mode (Burst) ........................... 554 Figure 13.25 Master Write Cycle in Host Bus Bridge Mode (Burst, with stepping) .................. 555 Figure 13.26 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with stepping)..... 556 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Direct Memory Access Controller (DMAC) Block Diagram of DMAC ....................................................................................... 558 Round-Robin Mode (example of channel 0 to 5) .................................................... 593 Changes in Channel Priority in Round-Robin Mode (example of channel 0 to 5)..................................................................................... 594 Figure 14.4 Data Flow of Dual Address Mode........................................................................... 595 Figure 14.5 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary Memory, Destination: Ordinary Memory) ................................ 596 Figure 14.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1 (DREQ Low Level Detection) ................................................................................ 597 Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2 (DREQ Low Level Detection) ................................................................................ 598 Figure 14.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode (DREQ Low Level Detection) ................................................................................ 598 Figure 14.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) .... 599 Figure 14.10 Bus State when Multiple Channels are Operating ................................................. 602 Figure 14.11 DMA Transfer Flowchart ...................................................................................... 603 Figure 14.12 Reload Mode Transfer........................................................................................... 605 Figure 14.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 606 Figure 14.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 606 Figure 14.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 607 Figure 14.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 607 Rev.1.00 Dec. 13, 2005 Page xxxiii of l Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Clock Pulse Generator (CPG) Block Diagram of CPG ........................................................................................... 614 Points for Attention when Using Crystal Resonator................................................ 622 Points for Attention when Using PLL and DLL Circuit.......................................... 623 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Watchdog Timer and Reset Block Diagram of WDT .......................................................................................... 626 WDT Counting Up Operation ................................................................................. 635 STATUS Output during Power-on.......................................................................... 637 STATUS Output by Reset input during Normal Operation .................................... 637 STATUS Output by Reset input during Sleep Mode .............................................. 638 STATUS Output by Watchdog timer overflow Power-On Reset during Normal Operation ........................................................................................ 639 Figure 16.7 STATUS Output by Watchdog timer overflow Power-On Reset during Sleep Mode .................................................................................................. 639 Figure 16.8 STATUS Output by Watchdog timer overflow Manual Reset during Normal Operation........................................................................................ 640 Figure 16.9 STATUS Output by Watchdog timer overflow Manual Reset during Sleep Mode.................................................................................................. 641 Section 17 Power-Down Mode Figure 17.1 DDR-SDRAM Interface Operation when Turning System Power Supply On/Off ................................................................... 650 Figure 17.2 Sequence for Turning Off System Power Supply in Self-Refresh Mode ................ 652 Figure 17.3 Sequence for Turning System Power Supply On/Off.............................................. 654 Figure 17.4 Mode Transition Diagram ....................................................................................... 655 Figure 17.5 Status Pins Output from Sleep to Interrupt.............................................................. 656 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Timer Unit (TMU) Block Diagram of TMU .......................................................................................... 658 Example of Count Operation Setting Procedure ..................................................... 670 TCNT Auto-Reload Operation ................................................................................ 671 Count Timing when Operating on Internal Clock ................................................... 671 Count Timing when Operating on External Clock .................................................. 672 Count Timing when Operating on on-chip RTC output Clock ............................... 672 Operation Timing when Using Input Capture Function .......................................... 673 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Timer/Counter (CMT) Block Diagram of CMT .......................................................................................... 678 Edge Detection (example of rising edge) ................................................................ 691 32-Bit Timer Mode: Input Capture (channel 1 and channel 0)................................ 692 32-bit Timer mode: Input Capture Operation Timing ............................................. 692 Rev.1.00 Dec. 13, 2005 Page xxxiv of l Figure 19.5 CMT_CTRn Assert Timing (channel 0 and 1) ........................................................ 694 Figure 19.6 32-Bit Timer Mode: Output Compare (channel 1 and channel 0) ........................... 694 Figure 19.7 32-bit Timer Mode: Output Compare Operation Timing (Example of High output in Active and Not Active by CMTCHnST).................... 695 Figure 19.8 32-bit Timer Mode: Output Compare Operation Timing (Example of High output in Active and Not Active by CMTFRT)......................... 695 Figure 19.9 16-Bit Timer Mode: Input Capture (channel 1 and channel 0)................................ 697 Figure 19.10 16-Bit Timer Mode: Input Capture Operation Timing .......................................... 698 Figure 19.11 16-Bit Timer Mode: Output Compare (CMT_CTR pins are available for channel 1 and channel 0) ................................ 699 Figure 19.12 16-Bit Timer Mode: Output Compare Operation Timing ..................................... 700 Figure 19.13 Up-Counter Mode (channel 1 and channel 0)........................................................ 701 Figure 19.14 Up-counter Mode Operation Timing..................................................................... 701 Figure 19.15 Updown-Counter Mode (only channel 0).............................................................. 703 Figure 19.16 Updown-Counter Mode: Countdown Operation Timing (only channel 0)............ 703 Figure 19.17 Rotary Switch Operation Count-Up Timing.......................................................... 705 Figure 19.18 Rotary Switch Operation Count-Down Timing..................................................... 705 Section 20 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 Figure 20.6 Realtime Clock (RTC) Block Diagram of RTC ........................................................................................... 708 Examples of Time Setting Procedures..................................................................... 727 Examples of Time Reading Procedures................................................................... 728 Example of Use of Alarm Function......................................................................... 729 Example of Crystal Oscillator Circuit Connection .................................................. 731 Interrupt Request Signal Generation Timing of Complex Sources ......................... 732 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Figure 21.7 Serial Communication Interface with FIFO (SCIF) Block Diagram of SCIF........................................................................................... 735 SCIF0_RTS Pin (Only in Channel 0) ...................................................................... 736 SCIF0_CTS Pin (Only in Channel 0) ...................................................................... 736 SCIFn_SCK Pin (n = 0, 1)....................................................................................... 737 SCIFn_TXD Pin (n = 0, 1) ...................................................................................... 737 SCIFn_RXD Pin (n = 0, 1)...................................................................................... 738 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, and Two Stop Bits) ........................................... 772 Figure 21.8 Sample SCIF Initialization Flowchart ..................................................................... 775 Figure 21.9 Sample Serial Transmission Flowchart ................................................................... 776 Figure 21.10 Sample SCIF Transmission Operation (Example with 8-Bit Data, Parity, One Stop Bit).................................................. 778 Figure 21.11 Sample Operation Using Modem Control (SCIF0_CTS) (Only in Channel 0) ..... 778 Figure 21.12 Sample Serial Reception Flowchart (1)................................................................. 779 Rev.1.00 Dec. 13, 2005 Page xxxv of l Figure 21.12 Sample Serial Reception Flowchart (2)................................................................. 780 Figure 21.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 782 Figure 21.14 Sample Operation Using Modem Control (SCIF0_RTS) (Only in Channel 0)..... 782 Figure 21.15 Data Format in Clocked Synchronous Communication ........................................ 783 Figure 21.16 Sample SCIF Initialization Flowchart ................................................................... 785 Figure 21.17 Sample Serial Transmission Flowchart ................................................................. 786 Figure 21.18 Sample SCIF Transmission Operation in Clocked Synchronous Mode................ 787 Figure 21.19 Sample Serial Reception Flowchart (1)................................................................. 788 Figure 21.19 Sample Serial Reception Flowchart (2)................................................................. 789 Figure 21.20 Sample SCIF Reception Operation in Clocked Synchronous Mode ..................... 790 Figure 21.21 Sample Simultaneous Serial Transmission and Reception Flowchart................... 791 Figure 21.22 Receive Data Sampling Timing in Asynchronous Mode ...................................... 795 Figure 21.23 Example of Synchronization Clock Transfer by DMAC ...................................... 796 Section 22 Serial I/O with FIFO (SIOF) Figure 22.1 Block Diagram of SIOF .......................................................................................... 798 Figure 22.2 Serial Clock Supply................................................................................................. 827 Figure 22.3 Serial Data Synchronization Timing ....................................................................... 829 Figure 22.4 SIOF Transmit/Receive Timing .............................................................................. 830 Figure 22.5 Transmit/Receive Data Bit Alignment .................................................................... 832 Figure 22.6 Control Data Bit Alignment .................................................................................... 833 Figure 22.7 Control Data Interface (Slot Position)..................................................................... 834 Figure 22.8 Control Data Interface (Secondary FS) ................................................................... 835 Figure 22.9 Example of Transmit Operation in Master Mode.................................................... 838 Figure 22.10 Example of Receive Operation in Master Mode ................................................... 839 Figure 22.11 Example of Transmit Operation in Slave Mode .................................................... 840 Figure 22.12 Example of Receive Operation in Slave Mode ..................................................... 841 Figure 22.13 Transmit and Receive Timing (8-Bit Monaural Data (1))..................................... 845 Figure 22.14 Transmit and Receive Timing (8-Bit Monaural Data (2))..................................... 845 Figure 22.15 Transmit and Receive Timing (16-Bit Monaural Data) ........................................ 846 Figure 22.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) ........................................ 846 Figure 22.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) ........................................ 847 Figure 22.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) ........................................ 847 Figure 22.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) ........................................ 848 Figure 22.20 Transmit and Receive Timing (16-Bit Stereo Data).............................................. 848 Section 23 Figure 23.1 Figure 23.2 Figure 23.3 Serial Protocol Interface (HSPI) Block Diagram of HSPI .......................................................................................... 850 Operational Flowchart............................................................................................. 861 Timing Conditions when FBS = 0........................................................................... 863 Rev.1.00 Dec. 13, 2005 Page xxxvi of l Figure 23.4 Timing Conditions when FBS = 1........................................................................... 864 Section 24 Figure 24.1 Figure 24.2 Figure 24.3 Multimedia Card Interface (MMCIF) Block Diagram of MMCIF...................................................................................... 866 DR Access Example ................................................................................................ 899 Example of Command Sequence for Commands Not Requiring Command Response ........................................................................ 903 Figure 24.4 Example of Operational Flow for Commands Not Requiring Command Response ........................................................................ 904 Figure 24.5 Example of Command Sequence for Commands without Data Transfer (No Data Busy State)............................................................................................... 905 Figure 24.6 Example of Command Sequence for Commands without Data Transfer (with Data Busy State)............................................................................................. 906 Figure 24.7 Example of Operational Flow for Commands without Data Transfer..................... 907 Figure 24.8 Example of Command Sequence for Commands with Read Data (Block Size ≤ FIFO Size) ........................................................................................ 909 Figure 24.9 Example of Command Sequence for Commands with Read Data (Block Size > FIFO Size) ........................................................................................ 910 Figure 24.10 Example of Command Sequence for Commands with Read Data (Multiple Block Transfer)...................................................................................... 911 Figure 24.11 Example of Command Sequence for Commands with Read Data (Stream Transfer)................................................................................................... 912 Figure 24.12 Example of Operational Flow for Commands with Read Data (Single Block Transfer) ......................................................................................... 913 Figure 24.13 Example of Operational Flow for Commands with Read Data (1) (Open-ended Multiple Block Transfer) ................................................................. 914 Figure 24.13 Example of Operational Flow for Commands with Read Data (2) (Open-ended Multiple Block Transfer).................................................................. 915 Figure 24.13 Example of Operational Flow for Commands with Read Data (3) (Pre-defined Multiple Block Transfer) .................................................................. 916 Figure 24.13 Example of Operational Flow for Commands with Read Data (4) (Pre-defined Multiple Block Transfer) .................................................................. 917 Figure 24.14 Example of Operational Flow for Commands with Read Data (Stream Transfer) .................................................................................................. 918 Figure 24.15 Example of Command Sequence for Commands with Write Data (Block Size ≤ FIFO Size) ...................................................................................... 921 Figure 24.16 Example of Command Sequence for Commands with Write Data (Block Size > FIFO Size) ...................................................................................... 922 Figure 24.17 Example of Command Sequence for Commands with Write Data (Multiple Block Transfer) ..................................................................................... 923 Rev.1.00 Dec. 13, 2005 Page xxxvii of l Figure 24.18 Example of Command Sequence for Commands with Write Data (Stream Transfer)................................................................................................... 924 Figure 24.19 Example of Operational Flow for Commands with Write Data (Single Block Transfer) ......................................................................................... 925 Figure 24.20 Example of Operational Flow for Commands with Write Data (1) (Open-ended Multiple Block Transfer) ................................................................. 926 Figure 24.20 Example of Operational Flow for Commands with Write Data (2) (Open-ended Multiple Block Transfer) ................................................................. 927 Figure 24.20 Example of Operational Flow for Commands with Write Data (3) (Pre-defined Multiple Block Transfer).................................................................. 928 Figure 24.20 Example of Operational Flow for Commands with Write Data (4) (Pre-defined Multiple Block Transfer).................................................................. 929 Figure 24.21 Example of Operational Flow for Commands with Write Data (Stream Transfer) .................................................................................................. 930 Figure 24.22 Example of Read Sequence Flow (Single Block Transfer) ................................... 934 Figure 24.23 Example of Read Sequence Flow (1) (Open-ended Multiple Block Transfer)...... 935 Figure 24.23 Example of Read Sequence Flow (2) (Open-ended Multiple Block Transfer)...... 936 Figure 24.23 Example of Read Sequence Flow (3) (Pre-defined Multiple Block Transfer) ...... 937 Figure 24.23 Example of Read Sequence Flow (4) (Pre-defined Multiple Block Transfer) ...... 938 Figure 24.24 Example of Operational Flow for Stream Read Transfer ...................................... 939 Figure 24.25 Example of Operational Flow for Auto-mode Pre-defined Multiple Block Read Transfer (1)...................................................... 940 Figure 24.25 Example of Operational Flow for Auto-mode Pre-defined Multiple Block Read Transfer (2) ...................................................... 941 Figure 24.26 Example of Write Sequence Flow (1) (Single Block Transfer)............................. 944 Figure 24.26 Example of Write Sequence Flow (2) (Single Block Transfer)............................. 945 Figure 24.27 Example of Write Sequence Flow (1) (Open-ended Multiple Block Transfer)..... 946 Figure 24.27 Example of Write Sequence Flow (2) (Open-ended Multiple Block Transfer)..... 947 Figure 24.27 Example of Write Sequence Flow (3) (Pre-defined Multiple Block Transfer)...... 948 Figure 24.27 Example of Write Sequence Flow (4) (Pre-defined Multiple Block Transfer)...... 949 Figure 24.28 Example of Operational Flow for Stream Write Transfer ..................................... 950 Figure 24.29 Example of Operational Flow for Auto-mode Pre-defined Multiple Block Write Transfer (1)..................................................... 951 Figure 24.29 Example of Operational Flow for Auto-mode Pre-defined Multiple Block Write Transfer (2)..................................................... 952 Section 25 Figure 25.1 Figure 25.2 Figure 25.3 Figure 25.4 Audio Codec Interface (HAC) Block Diagram ........................................................................................................ 956 AC97 Frame Slot Structure ..................................................................................... 973 Initialization Sequence ............................................................................................ 976 Sample Flowchart for Off-Chip Codec Register Write ........................................... 977 Rev.1.00 Dec. 13, 2005 Page xxxviii of l Figure 25.5 Sample Flowchart for Off-Chip Codec Register Read (1) ...................................... 978 Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (2) ...................................... 979 Figure 25.7 Sample Flowchart for Off-Chip Codec Register Read (3) ...................................... 980 Section 26 Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 Figure 26.5 Figure 26.6 Figure 26.7 Figure 26.8 Serial Sound Interface (SSI) Module Block Diagram of SSI Module ................................................................................ 984 Philips Format (with no Padding).......................................................................... 1000 Philips Format (with Padding)............................................................................... 1000 Sony Format (with Serial Data First, Followed by Padding Bits) ......................... 1001 Matsushita Format (with Padding Bits First, Followed by Serial Data)................ 1001 Multi-channel Format (4 Channels, No Padding).................................................. 1003 Multi-channel Format (6 Channels with High Padding) ....................................... 1003 Multi-channel Format (8 Channels, with Padding Bits First, Followed by Serial Data, with Padding)................................................................ 1004 Figure 26.9 Basic Sample Format (Transmit Mode with Example System/Data Word Length)................................. 1005 Figure 26.10 Inverted Clock ..................................................................................................... 1005 Figure 26.11 Inverted Word Select........................................................................................... 1006 Figure 26.12 Inverted Padding Polarity .................................................................................... 1006 Figure 26.13 Padding Bits First, Followed by Serial Data, with Delay.................................... 1006 Figure 26.14 Padding Bits First, Followed by Serial Data, without Delay............................... 1007 Figure 26.15 Serial Data First, Followed by Padding Bits, without Delay............................... 1007 Figure 26.16 Parallel Right Aligned with Delay....................................................................... 1007 Figure 26.17 Mute Enabled ...................................................................................................... 1008 Figure 26.18 Compressed Data Format, Slave Transmitter, Burst Mode Disabled .................. 1009 Figure 26.19 Compressed Data Format, Slave Transmitter, and Burst Mode Enabled ............ 1009 Figure 26.20 Transition Diagram between Operation Modes................................................... 1011 Figure 26.21 Transmission Using DMA Controller ................................................................. 1013 Figure 26.22 Transmission using Interrupt Data Flow Control ................................................ 1014 Figure 26.23 Reception using DMA Controller........................................................................ 1016 Figure 26.24 Reception using Interrupt Data Flow Control ..................................................... 1017 Section 27 Figure 27.1 Figure 27.2 Figure 27.3 Figure 27.4 Figure 27.5 NAND Flash Memory Controller (FLCTL) FLCTL Block Diagram ......................................................................................... 1023 Read Operation Timing for NAND-Type Flash Memory (1)................................ 1044 Programming Operation Timing for NAND-Type Flash Memory (1) .................. 1045 Programming Operation Timing for NAND-Type Flash Memory (2) .................. 1045 Relationship between DMA Transfer and Sector (Data and Control Code), and Memory and DMA Transfer........................................................................... 1046 Figure 27.6 Relationship between Sector Number and Address Expansion of NAND-Type Flash Memory.................................................................................. 1047 Rev.1.00 Dec. 13, 2005 Page xxxix of l Figure 27.7 Sector Access when Unusable Sector Exists in Continuous Sectors..................... 1048 Figure 27.8 NAND Flash Command Access (Block Erase)..................................................... 1050 Figure 27.9 NAND Flash Sector Access (Flash Write) Using DMA ....................................... 1051 Figure 27.10 NAND Flash Command Access (Flash Read) .................................................... 1052 Section 28 General Purpose I/O (GPIO) Figure 28.1 Port Data Output Timing (Example of Port A) ..................................................... 1097 Figure 28.2 Port Data input Timing (Example of Port A) ........................................................ 1098 Section 29 User Break Controller (UBC) Figure 29.1 Block Diagram of UBC......................................................................................... 1102 Figure 29.2 Flowchart of User Break Debugging Support Function ........................................ 1127 Section 30 Figure 30.1 Figure 30.2 Figure 30.3 Figure 30.4 User Debugging Interface (H-UDI) H-UDI Block Diagram .......................................................................................... 1136 Sequence for Switching from Boundary-Scan TAP Controller to H-UDI ............ 1139 TAP Controller State Transitions .......................................................................... 1152 H-UDI Reset.......................................................................................................... 1153 Section 31 Electrical Characteristics Figure 31.1 EXTAL Clock Input Timing ................................................................................. 1161 Figure 31.2 CLKOUT Clock Output Timing (1)...................................................................... 1161 Figure 31.3 CLKOUT Clock Output Timing (2)...................................................................... 1161 Figure 31.4 Power-On Oscillation Settling Time ..................................................................... 1162 Figure 31.5 MODE pins Setup/Hold Timing............................................................................ 1162 Figure 31.6 PLL Synchronization Settling Time ...................................................................... 1163 Figure 31.7 Control Signal Timing........................................................................................... 1163 Figure 31.8 SRAM Bus Cycle: Basic Bus Cycle (No Wait) .................................................... 1165 Figure 31.9 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ..................................... 1166 Figure 31.10 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) ........................................................... 1167 Figure 31.11 SRAM Bus Cycle: Basic Bus Cycle (No Wait, No Address Setup/ Hold Time Insertion, RDS = 1, RDH = 0, WTS = 1, WTH = 1)......................... 1168 Figure 31.12 Burst ROM Bus Cycle (No Wait) ....................................................................... 1169 Figure 31.13 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait ; 2nd/3rd/4th Data: One Internal Wait)................................. 1170 Figure 31.14 Burst ROM Bus Cycle (No Wait, No Address Setup/ Hold Time Insertion, RDS = 1, RDH = 0) .......................................................... 1171 Figure 31.15 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ...................... 1172 Figure 31.16 PCMCIA Memory Bus Cycle ............................................................................. 1173 Figure 31.17 PCMCIA I/O Bus Cycle...................................................................................... 1174 Rev.1.00 Dec. 13, 2005 Page xl of l Figure 31.18 PCMCIA I/O Bus Cycle (TEDx = 1, THEx = 1, IW/PCIW = 1, One Internal Wait, Dynamic Bus Sizing).................................... 1175 Figure 31.19 MPX Basic Bus Cycle: Read............................................................................... 1176 Figure 31.20 MPX Basic Bus Cycle: Write.............................................................................. 1177 Figure 31.21 MPX Bus Cycle: Burst Read............................................................................... 1178 Figure 31.22 MPX Bus Cycle: Burst Write .............................................................................. 1179 Figure 31.23 Byte Control SRAM Bus Cycle .......................................................................... 1180 Figure 31.24 Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, No Address Setup/Hold Time Insertion, RDS = 1, RDH = 0)............ 1181 Figure 31.25 MCLK Output Timing......................................................................................... 1183 Figure 31.26 Read Timing of DDR-SDRAM (2 Burst Read) ................................................. 1184 Figure 31.27 Write Timing of DDR-SDRAM (2 Burst Write)................................................. 1185 Figure 31.28 NMI Input Timing ............................................................................................... 1186 Figure 31.29 IRQ/IRL, GPIO Interrupt Input and IRQOUT Output Timing............................ 1187 Figure 31.30 PCI Clock Input Timing ...................................................................................... 1189 Figure 31.31 Output Signal Timing .......................................................................................... 1189 Figure 31.32 Input Signal Timing............................................................................................. 1189 Figure 31.33 DREQ and DRAK Timing .................................................................................. 1190 Figure 31.34 TCLK Input Timing ............................................................................................ 1191 Figure 31.35 CMT Timing (1).................................................................................................. 1192 Figure 31.36 CMT Timing (2).................................................................................................. 1192 Figure 31.37 SCIFn_SCK Input Clock Timing (n = 0, 1) ........................................................ 1193 Figure 31.38 SCIF Channel n I/O Synchronous Mode Clock Timing (n = 0, 1) ...................... 1194 Figure 31.39 SIOF_MCLK Input Timing................................................................................. 1195 Figure 31.40 SIOF Transmission/Reception Timing (Master Mode 1, Fall Sampling)............ 1196 Figure 31.41 SIOF Transmission/Reception Timing (Master Mode 1, Rise Sampling)........... 1196 Figure 31.42 SIOF Transmission/Reception Timing (Master Mode 2, Fall Sampling)............ 1197 Figure 31.43 SIOF Transmission/Reception Timing (Master Mode 2, Rise Sampling)........... 1197 Figure 31.44 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) .............. 1198 Figure 31.45 HSPI Data Output/Input Timing ......................................................................... 1200 Figure 31.46 MMCIF Transmit Timing.................................................................................... 1201 Figure 31.47 MMCIF Receive Timing ..................................................................................... 1202 Figure 31.48 HAC Cold Reset Timing ..................................................................................... 1203 Figure 31.49 HAC SYNC Output Timing ................................................................................ 1203 Figure 31.50 HAC Clock Input Timing.................................................................................... 1203 Figure 31.51 HAC Interface Module Signal Timing ................................................................ 1204 Figure 31.52 SSI Clock Input/Output Timing .......................................................................... 1205 Figure 31.53 SSI Transmit Timing (1) ..................................................................................... 1205 Figure 31.54 SSI Transmit Timing (2) ..................................................................................... 1206 Figure 31.55 SSI Receive Timing (1) ....................................................................................... 1206 Rev.1.00 Dec. 13, 2005 Page xli of l Figure 31.56 Figure 31.57 Figure 31.58 Figure 31.59 Figure 31.60 Figure 31.61 Figure 31.62 Figure 31.63 Figure 31.64 Figure 31.65 Figure 31.66 Figure 31.67 Figure 31.68 SSI Receive Timing (2)....................................................................................... 1206 Command Issue Timing of NAND-type Flash Memory ..................................... 1208 Address Issue Timing of NAND-type Flash Memory......................................... 1209 Data Read Timing of NAND-type Flash Memory .............................................. 1209 Data Write Timing of NAND-type Flash Memory ............................................. 1210 Status Read Timing of NAND-type Flash Memory ............................................ 1210 GPIO Timing....................................................................................................... 1211 TCK Input Timing............................................................................................... 1212 PRESET Hold Timing......................................................................................... 1213 H-UDI Data Transfer Timing.............................................................................. 1213 ASEBRK Pin Break Timing................................................................................ 1213 Output Load Circuit ............................................................................................ 1214 Load Capacitance-Delay Time ............................................................................ 1215 Appendix Figure B.1 Instruction Prefetch................................................................................................. 1219 Figure E.1 Package Dimensions (449-Pin BGA) ..................................................................... 1255 Figure H.1 Sequence of Turning On and Off Power Supply .................................................... 1275 Rev.1.00 Dec. 13, 2005 Page xlii of l Tables Section 1 Overview Table 1.1 SH7780 Features....................................................................................................... 2 Table 1.2 Pin Functions .......................................................................................................... 11 Section 2 Programming Model Table 2.1 Initial Register Values............................................................................................. 35 Table 2.2 Bit Allocation for FPU Exception Handling........................................................... 45 Section 3 Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions ................................................... 51 Table 3.2 Addressing Modes and Effective Addresses........................................................... 53 Table 3.3 Notation Used in Instruction List............................................................................ 57 Table 3.4 Fixed-Point Transfer Instructions ........................................................................... 59 Table 3.5 Arithmetic Operation Instructions .......................................................................... 61 Table 3.6 Logic Operation Instructions .................................................................................. 63 Table 3.7 Shift Instructions..................................................................................................... 64 Table 3.8 Branch Instructions ................................................................................................. 65 Table 3.9 System Control Instructions.................................................................................... 66 Table 3.10 Floating-Point Single-Precision Instructions ...................................................... 69 Table 3.11 Floating-Point Double-Precision Instructions..................................................... 70 Table 3.12 Floating-Point Control Instructions .................................................................... 70 Table 3.13 Floating-Point Graphics Acceleration Instructions ............................................. 71 Section 4 Pipelining Table 4.1 Representations of Instruction Execution Patterns.................................................. 74 Table 4.2 Instruction Groups .................................................................................................. 84 Table 4.3 Combination of Preceding and Following Instructions........................................... 86 Table 4.4 Issue Rates and Execution Cycles........................................................................... 88 Section 5 Exception Handling Table 5.1 Register Configuration............................................................................................ 97 Table 5.2 States of Register in Each Operating Mode ............................................................ 97 Table 5.3 Exceptions............................................................................................................. 102 Section 6 Floating-Point Unit (FPU) Table 6.1 Floating-Point Number Formats and Parameters .................................................. 131 Table 6.2 Floating-Point Ranges........................................................................................... 132 Table 6.3 Bit Allocation for FPU Exception Handling......................................................... 140 Rev.1.00 Dec. 13, 2005 Page xliii of l Section 7 Memory Management Unit (MMU) Table 7.1 Register Configuration.......................................................................................... 156 Table 7.2 Register States in Each Processing State .............................................................. 156 Section 8 Caches Table 8.1 Cache Features...................................................................................................... 197 Table 8.2 Store Queue Features ............................................................................................ 197 Table 8.3 Register Configuration.......................................................................................... 200 Table 8.4 Register States in Each Processing State .............................................................. 200 Section 9 L Memory Table 9.1 L Memory Addresses............................................................................................ 227 Table 9.2 Register Configuration.......................................................................................... 228 Table 9.3 Register Status in Each Processing State .............................................................. 228 Table 9.4 Protective Function Exceptions to Access L Memory.......................................... 240 Section 10 Interrupt Controller (INTC) Table 10.1 Interrupt Types...................................................................................................... 246 Table 10.2 INTC Pin Configuration ....................................................................................... 250 Table 10.3 INTC Register Configuration ............................................................................... 251 Table 10.4 Register States in Each Operating Mode .............................................................. 253 Table 10.5 Interrupt Request Sources and INT2PRI0 to INT2PRI7....................................... 276 Table 10.6 Correspondence between Bits in INT2A0 and Sources ........................................ 277 Table 10.7 Correspondence between Bits in INT2A1 and Sources ........................................ 280 Table 10.8 Correspondence between Bits in INT2MSKR and Interrupt Masking ................. 283 Table 10.9 Correspondence between Bits in INT2MSKCR and Interrupt Mask Clearing ..... 285 Table 10.10 Correspondence between Interrupt Input Pins and Bits in INT2GPIC ............. 295 Table 10.11 IRL[3:0], IRL[7:4] Pins and Interrupt Levels ................................................... 298 Table 10.12 Interrupt Exception Handling and Priority........................................................ 302 Table 10.13 Interrupt Response Time................................................................................... 311 Table 10.14 Switching Sequence of IRQ/IRL[7:0] Pin Function ......................................... 313 Section 11 Local Bus State Controller (LBSC) Table 11.1 Pin Configuration.................................................................................................. 318 Table 11.2 LBSC External Memory Space Map .................................................................... 322 Table 11.3 Correspondence Between External Pins (MODE4 and MODE3)......................... 324 Table 11.4 Correspondence Between External Pin (MODE5) and Endian ............................ 325 Table 11.5 PCMCIA Interface Features ................................................................................. 325 Table 11.6 PCMCIA Support Interface .................................................................................. 326 Table 11.7 Register Configuration.......................................................................................... 329 Table 11.8 Register State in Each Processing Mode............................................................... 330 Table 11.9 32-Bit External Device/Big-Endian Access and Data Alignment......................... 353 Rev.1.00 Dec. 13, 2005 Page xliv of l Table 11.10 Table 11.11 Table 11.12 Table 11.13 Table 11.14 Table 11.15 Table 11.16 16-Bit External Device/Big-Endian Access and Data Alignment..................... 353 8-Bit External Device/Big-Endian Access and Data Alignment....................... 354 32-Bit External Device/Little-Endian Access and Data Alignment.................. 355 16-Bit External Device/Little-Endian Access and Data Alignment.................. 355 8-Bit External Device/Little-Endian Access and Data Alignment.................... 356 Relationship between Address and CE When Using PCMCIA Interface ......... 375 Relationship between D31 to D29 and Access Size in Address Phase ............. 383 Section 12 DDR-SDRAM Interface (DDRIF) Table 12.1 Pin Configuration.................................................................................................. 403 Table 12.2 Access and Data Alignment in Little Endian Mode.............................................. 406 Table 12.3 Access and Data Alignment in Big Endian Mode................................................. 408 Table 12.4 Register Configuration.......................................................................................... 410 Table 12.5 Register States in Each Operating Mode .............................................................. 411 Table 12.6 SDRAM Commands Issuable by DDRIF ............................................................. 426 Table 12.7 Relationship between SPLIT Bits and Address Multiplexing............................... 429 Section 13 PCI Controller (PCIC) Table 13.1 Input/Output Pins.................................................................................................. 446 Table 13.2 List of PCIC Registers .......................................................................................... 449 Table 13.3 Register States in Each Operating Mode .............................................................. 452 Table 13.4 Supported Bus Commands.................................................................................... 522 Table 13.5 PCIC Address Map ............................................................................................... 524 Table 13.6 Interrupt Priority ................................................................................................... 543 Section 14 Direct Memory Access Controller (DMAC) Table 14.1 Pin Configuration.................................................................................................. 559 Table 14.2 Register Configuration of DMAC......................................................................... 561 Table 14.3 Register States in Each Processing Mode ............................................................. 564 Table 14.4 Transfer Request Sources ..................................................................................... 587 Table 14.5 Selecting External Request Detection with DL, DS Bits ...................................... 589 Table 14.6 Selecting External Request Detection with DO Bit .............................................. 589 Table 14.7 Peripheral Module Request Modes ....................................................................... 591 Table 14.8 DMA Transfer Matrix in Auto-Request Mode (all channels)............................... 599 Table 14.9 DMA Transfer Matrix in External Request Mode (only channels 0 to 3)............. 600 Table 14.10 DMA Transfer Matrix in Peripheral module Request Mode ............................ 601 Table 14.11 Register Settings for SRAM, Burst ROM, Byte Control SRAM Interface....... 611 Table 14.12 Register Settings for PCMCIA Interface .......................................................... 612 Table 14.13 Register Settings for MPX Interface (Read Access)......................................... 612 Table 14.14 Register Settings for MPX Interface (Write Access) ........................................ 612 Rev.1.00 Dec. 13, 2005 Page xlv of l Section 15 Clock Pulse Generator (CPG) Table 15.1 CPG Pin Configuration......................................................................................... 616 Table 15.2 Clock Operating Modes ........................................................................................ 617 Table 15.3 Register configuration........................................................................................... 618 Table 15.4 Register States of CPG in Each Processing Mode ................................................ 618 Section 16 Watchdog Timer and Reset Table 16.1 Pin Configuration.................................................................................................. 627 Table 16.2 Register Configuration.......................................................................................... 628 Table 16.3 Register States in Each Processing Mode ............................................................. 628 Section 17 Power-Down Mode Table 17.1 Power-Down Modes ............................................................................................. 644 Table 17.2 Pin Configuration.................................................................................................. 645 Table 17.3 Register configuration........................................................................................... 645 Table 17.4 Register States in Each Processing Mode ............................................................. 645 Table 17.5 Pin Configuration.................................................................................................. 653 Section 18 Timer Unit (TMU) Table 18.1 Pin Configuration.................................................................................................. 659 Table 18.2 Register Configuration.......................................................................................... 660 Table 18.3 Register States in Each Processing Mode ............................................................. 661 Table 18.4 TMU Interrupt Sources......................................................................................... 674 Section 19 Timer/Counter (CMT) Table 19.1 Pin Configuration.................................................................................................. 679 Table 19.2 Register Configuration.......................................................................................... 679 Table 19.3 Register States of CMT in Each Processing Mode ............................................... 680 Table 19.4 32-bit Timer Mode: Example of Input Capture Setting ........................................ 693 Table 19.5 32-bit Timer Mode: Example of Output Compare Setting ................................... 696 Table 19.6 16-bit Timer Mode: Example of Input Capture Setting ........................................ 698 Table 19.7 16-bit Timer Mode: Example of Output Compare Setting ................................... 700 Table 19.8 Setting Example of Up-counter Mode .................................................................. 702 Table 19.9 Setting Example of Updown-counter Mode ......................................................... 704 Table 19.10 Setting Example of Updown-counter Mode ..................................................... 706 Table 19.11 CMT Interrupt Setting ...................................................................................... 706 Section 20 Realtime Clock (RTC) Table 20.1 RTC Pins............................................................................................................... 709 Table 20.2 RTC Registers....................................................................................................... 710 Table 20.3 Register States of RTC in Each Processing Mode ................................................ 711 Table 20.4 Crystal Oscillator Circuit Constants (Recommended Values).............................. 730 Rev.1.00 Dec. 13, 2005 Page xlvi of l Section 21 Serial Communication Interface with FIFO (SCIF) Table 21.1 Pin Configuration.................................................................................................. 739 Table 21.2 Register Configuration.......................................................................................... 740 Table 21.3 Register States of SCIF in Each Processing Mode ............................................... 741 Table 21.4 SCSMR Settings ................................................................................................... 758 Table 21.5 SCSMR Settings for Serial Transfer Format Selection......................................... 770 Table 21.6 SCSMR and SCSCR Settings for SCIF Clock Source Selection.......................... 771 Table 21.7 Serial Transfer Formats (Asynchronous Mode).................................................... 773 Table 21.8 SCIF Interrupt Sources ......................................................................................... 793 Section 22 Serial I/O with FIFO (SIOF) Table 22.1 Pin Configuration.................................................................................................. 799 Table 22.2 Register Configuration of SIOF............................................................................ 800 Table 22.3 Register States of SIOF in Each Processing Mode ............................................... 801 Table 22.4 Operation in Each Transfer Mode......................................................................... 804 Table 22.5 SIOF Serial Clock Frequency ............................................................................... 828 Table 22.6 Serial Transfer Modes........................................................................................... 830 Table 22.7 Frame Length........................................................................................................ 831 Table 22.8 Audio Mode Specification for Transmit Data....................................................... 833 Table 22.9 Audio Mode Specification for Receive Data ........................................................ 833 Table 22.10 Setting Number of Channels in Control Data ................................................... 834 Table 22.11 Conditions to Issue Transmit Request .............................................................. 836 Table 22.12 Conditions to Issue Receive Request ................................................................ 836 Table 22.13 Transmit and Receive Reset.............................................................................. 842 Table 22.14 SIOF Interrupt Sources ..................................................................................... 843 Section 23 Serial Protocol Interface (HSPI) Table 23.1 Pin Configuration.................................................................................................. 851 Table 23.2 Register Configuration.......................................................................................... 851 Table 23.3 Register States of HSPI in Each Processing Mode ............................................... 851 Section 24 Multimedia Card Interface (MMCIF) Table 24.1 Pin Configuration.................................................................................................. 866 Table 24.2 Register Configuration.......................................................................................... 867 Table 24.3 Register States of HSPI in Each Processing Mode ............................................... 869 Table 24.4 CMDR Configuration ........................................................................................... 871 Table 24.5 Correspondence between Commands and Settings of CMDTYR and RSPTYR ........................................................................................................ 892 Table 24.6 Correspondence between Command Response Byte Number and RSPR............. 895 Table 24.7 MMCIF Interrupt Sources..................................................................................... 931 Rev.1.00 Dec. 13, 2005 Page xlvii of l Section 25 Audio Codec Interface (HAC) Table 25.1 Pin Configuration.................................................................................................. 956 Table 25.2 Register Configuration.......................................................................................... 957 Table 25.3 Register States of HAC in Each Processing Mode ............................................... 957 Table 25.4 AC97 Transmit Frame Structure........................................................................... 973 Table 25.5 AC97 Receive Frame Structure ............................................................................ 974 Section 26 Serial Sound Interface (SSI) Module Table 26.1 Pin Configuration.................................................................................................. 984 Table 26.2 Register Configuration.......................................................................................... 985 Table 26.3 Register States of SSI in Each Processing Mode .................................................. 985 Table 26.4 Bus Formats of SSI Module.................................................................................. 998 Table 26.5 Number of Padding Bits for Each Valid Configuration...................................... 1002 Section 27 NAND Flash Memory Controller (FLCTL) Table 27.1 Pin Configuration................................................................................................ 1024 Table 27.2 Register Configuration of FLCTL ...................................................................... 1025 Table 27.3 Register States of FLCTL in Each Processing Mode.......................................... 1025 Table 27.4 Status Read of NAND-Type Flash Memory....................................................... 1049 Table 27.5 FLCTL Interrupt Requests.................................................................................. 1053 Table 27.6 DMA Transfer Specifications ............................................................................. 1053 Section 28 General Purpose I/O (GPIO) Table 28.1 Multiplexed Pins Controlled by Port Control Registers ..................................... 1056 Table 28.2 Register Configuration........................................................................................ 1060 Table 28.3 Register States of GPIO in Each Processing Mode ............................................ 1062 Section 29 User Break Controller (UBC) Table 29.1 Register Configuration........................................................................................ 1103 Table 29.2 Register Status in Each Processing State ............................................................ 1104 Table 29.3 Settings for Match Data Setting Register............................................................ 1116 Table 29.4 Relation between Operand Sizes and Address Bits to be Compared .................. 1123 Section 30 User Debugging Interface (H-UDI) Table 30.1 Pin Configuration................................................................................................ 1137 Table 30.2 Commands Supported by Boundary-Scan TAP Controller ................................ 1139 Table 30.3 Register Configuration (1) .................................................................................. 1140 Table 30.4 Register Configuration (2) .................................................................................. 1140 Table 30.5 Register Status in Each Processing State ............................................................ 1140 Table 30.6 SDBSR Configuration ........................................................................................ 1143 Section 31 Electrical Characteristics Table 31.1 Absolute Maximum Ratings ............................................................................... 1155 Rev.1.00 Dec. 13, 2005 Page xlviii of l Table 31.2 Table 31.3 Table 31.4 Table 31.5 Table 31.6 Table 31.7 Table 31.8 Table 31.9 Table 31.10 Table 31.11 Table 31.12 Table 31.13 Table 31.14 Table 31.15 Table 31.16 Table 31.17 Table 31.18 Table 31.19 Table 31.20 Table 31.21 Table 31.22 DC Characteristics (Ta = −20 to 75°C / −40 to 85°C)......................................... 1156 Permissible Output Currents ............................................................................... 1159 Clock Timing ...................................................................................................... 1159 Clock and Control Signal Timing ....................................................................... 1160 Control Signal Timing ........................................................................................ 1163 Bus Timing ......................................................................................................... 1164 DDRIF Signal Timing ........................................................................................ 1182 INTC Module Signal Timing.............................................................................. 1186 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1)................... 1188 DMAC Module Signal Timing ....................................................................... 1190 TMU Module Signal Timing .......................................................................... 1191 CMT Module Signal Timing .......................................................................... 1192 SCIF Module Signal Timing........................................................................... 1193 SIOF Module Signal Timing .......................................................................... 1195 HSPI Module Signal Timing .......................................................................... 1199 MMCIF Module Signal Timing...................................................................... 1201 HAC Interface Module Signal Timing............................................................ 1203 SSI Interface Module Signal Timing .............................................................. 1205 FLCTL Module Signal Timing ....................................................................... 1207 GPIO Signal Timing ....................................................................................... 1211 H-UDI Module Signal Timing........................................................................ 1212 Appendix Table F.1 Table F.2 Table F.3 Table F.4 Table F.5 Table F.6 Table G.1 Table G.2 Table I.1 Table J.1 Clock Operating Modes with External Pin Combination.................................... 1256 Area 0 Memory Map and Bus Width.................................................................. 1256 Endian ................................................................................................................. 1256 PCI Mode............................................................................................................ 1257 Clock Input ......................................................................................................... 1257 Mode Control...................................................................................................... 1257 Pin states in Reset, Power-Down State, and Bus-Released State........................ 1258 Treatment of Unused Pins................................................................................... 1267 Register Configuration........................................................................................ 1276 SH7780 Product Lineup...................................................................................... 1277 Rev.1.00 Dec. 13, 2005 Page xlix of l Rev.1.00 Dec. 13, 2005 Page l of l Section 1 Overview Section 1 Overview 1.1 SH7780 Features The SH7780 is an integrated system-on-a-chip microprocessor that is designed as a high performance, embedded, stand-alone Host Processor aimed at the multimedia, infotainment and consumer networking market. The SH7780 features a DDR-SDRAM interface that can be coupled to the DDR320* or 266 SDRAM. Also, because of its built-in functions, such as a PCI bus controller, a DMA controller, timers, and serial communications functions with an audio interface, as required for multimedia, network, and OA equipment, use of the SH7780 enables a high performance and high integrated system. The SH7780 contains the new generation SH-4A 32-bit RISC (reduced instruction set computer) microprocessor core which runs at 400 MHz (720 MIPS, 2.8 GFLOPS). The SH-4A is upwardly compatible with the SH-1, SH-2, SH-3, and SH-4 microcomputers at the instruction set level. This microprocessor core integrates a cache memory and the MMU. Note: "DDR320" indicates the DDR-SDRAM bus interface which operates at a frequency of 160 MHz in this manual. The features of the SH7780 are summarized in table 1.1. Rev.1.00 Dec. 13, 2005 Page 1 of 1286 REJ09B0158-0100 Section 1 Overview Table 1.1 SH7780 Features Item Features LSI • Operating frequency: 400 MHz • Performance: 720MIPS, 2.8 GFLOPS • Voltage: 1.25 V (internal), 2.5 V (DDR-SDRAM interface), 3.3 V (I/O) • Superscalar architecture: Parallel execution of two instructions • Packages: 449-pin BGA (Size: 21 × 21 mm, pin pitch: 0.8 mm) • Local bus interface (External bus):  Separate 26-bit address and 32-bit data buses  External bus frequency: 100 MHz • DDR-SDRAM bus interface (External bus):  Separate 14-bit address and 32-bit data buses  External bus frequency: 133 M or 160 MHz (DDR266/320) • PCI bus interface (External bus):  32-bit address/data multiplexing  External bus frequency: 33M or 66 MHz CPU • Renesas Technology original architecture • 32-bit internal data bus • General-register files:  Sixteen 32-bit general registers (eight 32-bit shadow registers)  Seven 32-bit control registers  Four 32-bit system registers • RISC-type instruction set (upward compatible with the SH-1, SH-2, SH-3 and SH-4 microcomputers)  Instruction length: 16-bit fixed length for improved code efficiency  Load/store architecture  Delayed branch instructions  Instructions executed with conditions  Instruction set based on the C language • Super scalar which executes two instructions simultaneously including the FPU • Instruction execution time: Two instructions per cycle (max) • Virtual address space: 4 Gbytes • Space identifier ASID: 8 bits, 256 virtual address spaces • On-chip multiplier • Seven-stage pipeline Rev.1.00 Dec. 13, 2005 Page 2 of 1286 REJ09B0158-0100 Section 1 Overview Item Features FPU • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to zero or interrupt generation for IEEE754 compliance • Floating-point registers: 32 bits × 16 words × 2 banks (single-precision × 16 words or double-precision × 8 words) × 2 banks • 32-bit CPU-FPU floating-point communication register (FPUL) • Supports FMAC (multiply-and-accumulate) instruction • Supports FDIV (divide) and FSQRT (square root) instructions • Supports FLDI0/FLDI1 (load constant 0/1) instructions • Instruction execution times  Latency (FADD/FSUB): 3 cycles (single-precision), 5 cycles (doubleprecision)  Latency (FMAC/ FMUL): 5 cycles (single-precision), 7 cycles (doubleprecision)  Pitch (FADD/FSUB): 1 cycle (single-precision/double-precision)  Pitch (FMAC/FMUL): 1 cycle (single-precision), 3 cycles (doubleprecision) Note: • FMAC is supported for single-precision only. 3-D graphics instructions (single-precision only):  4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 8 cycles (latency)  4-dimensional vector (FIPR) inner product: 1 cycle (pitch), 5 cycles (latency) • Ten-stage pipeline Rev.1.00 Dec. 13, 2005 Page 3 of 1286 REJ09B0158-0100 Section 1 Overview Item Features Memory management unit (MMU) • 4 Gbytes of physical address space, 256 address space identifiers (address space identifier ASID: 8 bits) • Supports single virtual memory mode and multiple virtual memory mode • Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, or 1 Mbyte • 4-entry full associative TLB for instructions • 64-entry full associative TLB for instructions and operands • Supports software selection of replacement method and random-counter replacement algorithms • Contents of TLB are directly accessible through address mapping • Instruction cache (IC) Cache memory  32-Kbyte 4-way set associative  32-byte block length • Operand cache (OC)  32-Kbyte 4-way set associative  32-byte block length  Selectable write method (copy-back or write-through) L memory • Storage queue (32 bytes × 2 entries) • Three independent read/write ports  Instruction fetch access by the CPU  8-/16-/32-/64-bit operand access by the CPU  8-/16-/32-/64-bit and 16-/32-byte access by the SuperHyway bus master SuperHyway memory • 16-Kbyte capacity • Supports memory protective functions during CPU accesses • 8-/16-/32-/64-bit and 16-/32-byte access from the SuperHyway bus master • 32-Kbyte capacity Rev.1.00 Dec. 13, 2005 Page 4 of 1286 REJ09B0158-0100 Section 1 Overview Item Features Interrupt controller (INTC) • Nine independent external interrupts: NMI and IRQ7 to IRQ0  NMI: Fall/rise selectable  IRQ: Fall/rise/high level/low level selectable • • User break controller (UBC) Local bus state controller (LBSC) 15-level signed external interrupts: IRL3 to IRL0, or IRL7 to IRL4 On-chip module interrupts: Priority level can be set for each module The following modules can issue on-chip module interrupts: TMU, RTC, SCIF, WDT, H-UDI, DMAC, CMT, HAC, PCIC, SIOF, HSPI, MMCIF, SSI, FLCTL, and GPIO • Supports debugging by means of user break interrupts • Two break channels • Address, data value, access type, and data size are available as break condition settings • Supports sequential break functions • Supports external memory access • External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area:  Bus size (8, 16, or 32 bits)  Number of wait cycles (hardware wait function also supported)  SRAM or burst ROM  Supports PCMCIA interface (only in little endian mode) DDR-SDRAM interface (DDRIF) • Big endian or little endian mode can be set • The data bus width of the DDRIF is 32 bits • Supports DDR-SDRAM self-refreshing • Supports the DDR320 or DDR266 SDRAM • Efficient data transfer is possible using the SuperHyway bus(Internal bus) • Supports a 4-bank DDR-SDRAM • Supports a burst length of 2 • Connectable memory size: 256-Mbit, 512-Mbit, 1-Gbit, and 2-Gbit Rev.1.00 Dec. 13, 2005 Page 5 of 1286 REJ09B0158-0100 Section 1 Overview Item Features PCI bus controller (PCIC) • PCI bus controller (subset of revision 2.2)  32-bit bus  33 MHz/66 MHz support • PCI master/target support • PCI host function support  Built-in bus arbiter Direct memory access controller (DMAC) • Interrupt requests can be sent to CPU • Up to 512-Mbyte memory can be connected for PCI memory space • 12-channel physical address DMA controller • 4-channel supports external requests (channel 0 to 3) • Address space: 4 Gbytes on architecture • Transfer data size: 8, 16, or 32 bits; 16, or 32 bytes • Address modes:  2-bus-cycle dual address mode Clock pulse generator (CPG) • Transfer requests: External (channel 0 to 3), peripheral module (channel 0 to 5), or auto-requests • Choice of DACK or DRAK (four external pins) • Bus modes: Cycle-steal or burst mode • Main clock: 12 times XTAL clock • Clock modes:  CPU frequency: 1/1 time main clock  Local bus frequency: 1/4, 1/6, 1/8, or 1/12 times main clock  DDR-SDRAM frequency: 2/5 or 1/3 times main clock (Supports DDR320 or DDR266 SDRAM devices)  Peripheral frequency: 1/8 or 1/12 times main clock • Power-down modes:  Sleep mode  Module standby mode Watchdog timer (WDT) • Single-channel watchdog timer (watchdog timer mode or interval timer mode can be selectable) • Selectable reset function: Power-on reset or manual reset Rev.1.00 Dec. 13, 2005 Page 6 of 1286 REJ09B0158-0100 Section 1 Overview Item Features Timer unit (TMU) • 6-channel auto-reload 32-bit timer • Input-capture function (only channel 2) • Choice of seven types counter input clocks (external and peripheral clocks) • 4-channel auto-reload 32-bit timers • Choice of 16 or 32 bits • Choice of 1-shot or free-running operation • Choice of an interrupt source or DMA transfer request from compare match or overflow • On-chip clock and calendar functions • Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution (cycle interrupts) • RTC power supply back-up function • Two full-duplex communications channels • On-chip 64-byte FIFOs for all channels • Choice of asynchronous mode or synchronous mode • Can select any bit rate generated by on-chip baud-rate generator • On-chip modem control function (SCIF0_RTS and SCIF0_CTS) for channel 0 Compare Match Timer (CMT) Realtime clock (RTC) Serial communication interface (SCIF) Serial I/O with FIFO • (SIOF) • Serial protocol interface (HSPI) Multimedia card interface (MMCIF) Internal 64-byte transmit/receive FIFOs Supports 8-/16-bit data and 16-bit stereo audio input/output • Sampling rate clock input selectable from Pck and external pin • Maximum sampling rate: 48-kHz • Internal prescaler for Pck • 1 channel • Master/slave mode • Selectable bit rate generated by on-chip baud-rate generator • Complies with the multimedia card system specification version 3.1 • Supports MMC mode • Interface with MCCLK output for transfer clock output, MCCMD I/O for command output/response input, MCDAT I/O (data I/O) • Four interrupt sources Rev.1.00 Dec. 13, 2005 Page 7 of 1286 REJ09B0158-0100 Section 1 Overview Item Features Audio codec interface (HAC) • Digital interface for audio codec • Supports transfer for slot 1 to slot 4 • Choice of 16- or 20-bit DMA transfer • Supports various sampling rates by adjusting slot data • Generates interrupt: data ready, data request, overflow, and underrun • 1-channel bi-directional transfer • Support compressed-data and non-compressed-data transfer Serial sound interface (SSI)  The compressed mode is used for continuous bit stream transfer  The non-compressed mode supports all serial audio streams divided into channels. • The SSI module is configured as any of a transmitter or receiver. The serial bus format can be used in the compressed and non-compressed mode. • Interface connectable to a NAND-type flash memory • Read or write in sector units (512 + 16 bytes) • Read or write in byte units • Supports up to 512-Mbit of flash memory General purpose I/O (GPIO) • 83 general purpose I/O ports (75 for I/Os and 8 for outputs) • GPIO interrupts are supported Debug interface • H-UDI (User Debugging Interface) • AUD (Advanced User Debugger) NAND flash memory controller (FLCTL) Rev.1.00 Dec. 13, 2005 Page 8 of 1286 REJ09B0158-0100 Section 1 Overview Block Diagram CPU O-cache SuperHyway bus UBC Operand bus MMU FPU LBSC (External bus) DDRIF (External bus) PCIC (External bus) I-cache Instruction bus DMAC TMU SuperHyway RAM SCIF channel 0 HPB AUD HSPI LRAM INTC SuperHyway router [Legend] AUD: CMT: CPG: CPU: DDRIF: DMAC: FLCTL: FPU: GPIO: HAC: HPB: HSPI: H-UDI: I-Cache: INTC: LBSC: LRAM: MMCIF: MMU: O-Cache: PCIC: RTC: Advanced user debugger Timer/counter Clock pulse generator Central processing unit DDR-SDRAM interface Direct memory access controller NAND flash memory controller Floating-point unit General purpose I/O Audio codec Peripheral bus bridge Serial protocol interface User debugging interface Instruction cache Interrupt controller Local bus state controller L memory Multimedia card interface Memory management unit Operand (data) cache PCI controller Realtime clock CPG SCIF channel 1 I/O multiplexed MMCIF WDT SIOF RTC HAC CMT SSI H-UDI GPIO SCIF: SIOF: SSI: SuperHyway RAM: TMU: UBC: WDT: I/O multiplexed FLCTL SH-4A core Peripheral bus 1.2 I/O multiplexed Serial communication interface with FIFO Serial I/O with FIFO Serial sound interface SuperHyway memory Timer unit User break controller Watchdog timer Figure 1.1 SH7780 Block Diagram Rev.1.00 Dec. 13, 2005 Page 9 of 1286 REJ09B0158-0100 BKPRST REJ09B0158-0100 Rev.1.00 Dec. 13, 2005 Page 10 of 1286 MDA9 MDA10 MDA11 MDA13 MDA15 N P R T U Figure 1.2 SH7780 Pin Arrangement A22 A19 A16 A14 A13 VSSQ Y AB AC AD AE A25 AA W MDA14 MDA12 MDA30 MDA28 MDA26 MDA24 MDQM1 A12 VDDQ A15 A17 A20 A23 MA9 MCS MRAS 7 VSS-DLL2 VSS VSS VSS-DLL1 VDD VSS VCCQ-DDR VCCQ-DDR VCCQ-DDR VCCQ-DDR VSSQ-DDR VSSQ-DDR VDD-DLL2 VDD VDD VDD-DLL1 VDD VSS VCCQ-DDR VSSQ-DDR VSSQ-DDR VSSQ-DDR VSSQ-DDR STATUS1/ A10 A11 VDDQ A18 A21 A24 A7 A8 A9 VSSQ VDDQ VSS VDD A3 A4 A5 A6 VSSQ VSS VDD D31 A0 A1 A2 VSS D27 D28 D29 D30 VDD VCCQ-DDR VSSQ-DDR VSSQ-DDR VCCQ-DDR VSSQ-DDR VSSQ-DDR VCCQ-DDR MDA31 MDA29 MDA27 MDA25 MDQM3 MDQS3 MDQM2 MDQS2 MDA22 MDA20 MDA18 CMT_CTR0 CMT_CTR1 STATUS0/ MA11 MCAS MWE 6 MA8 BA1 BA0 8 MA7 MA0 MA10 9 MA6 MA2 MA1 10 MA5 MA4 MA3 11 IOWR WE3/ D24 D25 D26 VDDQ VDD D20 D21 D22 D23 VSSQ VSS D17 D18 D19 VSSQ VSS VSS VSS VSS VSS VSS VSS VSS IORD WE2/ D16 D15 VDDQ VDD VSS VSS VSS VSS VSS VSS VSS VSSQ-DDR VCCQ-DDR VSSQ-DDR VCCQ-DDR VSSQ-DDR VSSQ-DDR VCCQ-DDR VCCQ-DDR VSSQ-DDR VSSQ-DDR VCCQ-DDR MA12 MA13 MCLK 5 VCCQ-DDR VCCQ-DDR VCCQ-DDR VCCQ-DDR VCCQ-DDR MDA8 M V MDQS1 L MDQS0 MDA6 MDA7 MDQM0 J K MDA23 MDA21 MDA19 MDA5 MDA3 F MDA17 H MDA2 E MDA16 MDA4 MDA1 D CKE MCLK 4 VCCQ-DDR VSSQ-DDR VCCQ-DDR G MDA0 C VSSQ-DDR VCCQ-DDR VSSQ-DDR VCCQ-DDR DDR-VREF 3 B 2 13 VDDQ VDD VDDQ DREQ2/ INTB/ AUDATA0 DRAK3/ CE2B/ AUDSYNC VDDQ DREQ1 DREQ0 14 DRAK2/ CE2A/ AUDCK MODE7 DRAK1/ D12 D13 D14 VDDQ VDDQ VSS VSS VSS-DDR VSS-DDR VSS-DDR VSS VSS D9 D10 D11 VSSQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS WE1 D7 D8 VDDQ VSSQ VSS VSS VSS VSS VSS VSS VSS (Top view) VSSQ VSSQ MODE2 DRAK0/ VSS PRESET 12 15 16 D4 D5 D6 VDDQ VDD VSS VSS VSS VSS VSS VSS VSS VSS VSSQ MODE1 DACK1/ MODE0 DACK0/ D1 D2 D3 VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSSQ TMS TCK DACK3/ IRQOUT/ AUDATA3 DACK2/ DREQ3/ INTC/ MRESETOUT/ AUDATA1 AUDATA2 REG WE0/ D0 BREQ BACK VDDQ VSSQ TRST /BRKACK ASEBRK TDO TDI 17 /FALE R/W RD/FRMAE BS CS4 VDDQ VDDQ 21 EXTAL2 23 VDD-RTC 24 RDY CS2 CS5 CS6 VSSQ CLKOUT CS0 CS1 VSS-PLL3 VSSQ VDDQ VDD-PLL2 VDD-PLL3 VSS-PLL2 VDD VSSQ VDDQ VSS VSS VDD VDD VDDQ VDD VSS VSS VDDQ * VDD-PLL1 VSS-PLL1 VDD VDDQ NC REQOUT REQ0/ REQ2 AD31 AD27 CBE3 AD21 AD17 IRDY LOCK SERR AD14 AD10 VDD VDD AD7 AD1 VDDQ VSS VSSQ VDDQ VDD AD6 XTAL VSSQ VDDQ VDDQ * NC PCICLK REQ1 REQ3 AD29 AD25 AD23 AD19 CBE2 DEVSEL PERR EXTAL VDDQ VDDQ VSS VSS GNTIN GNT0/ GNT2 AD30 AD26 IDSEL AD20 AD16 TRDY PAR AD13 AD9 AD12 CBE1 AD2 AD5 IRQ/IRL0 AD8 AD3 IRQ/IRL1 IRQ/IRL3 VDDQ VSSQ IRQ/IRL6/ FD6/ MODE6 VDD IRQ/IRL4/ FD4/ MODE3 SCIF0_CTS /INTD /FCLE VDD VDDQ SIOF_RXD/ SCIF0_RXD SCIF1_SCK HAC_SDIN/ HSPI_RX/ TCLK/IOIS16 XRTCSTBI /MCCMD SSI_SCK FRB XTAL2 22 SIOF_SCK/ SIOF_TXD/ SCIF0_RTS SCIF0_TXD SCIF0_SCK/ HAC_BITCLK/ HAC_SDOUT/ /HSPI_CS HSPI_TX HSPI_CLK/ /FSE SSI_CLK SSI_SDATA FWE/MODE8 FRE FD0 20 SIOF_SYNC/ SCIF1_TXD /MCCLK HAC_SYNC/ /MODE5 SSI_WS AUDATA2 SIOF_MCLK SCIF1_RXD MCDAT /FD2 /HAC_RES /FD3 AUDATA3 AUDATA0/ FD1 AUDCK /FCE 19 AUDATA1/ 18 AUDSYNC VSSQ VSSQ MPMD VSS INTA PCIRESET GNT1 GNT3 AD28 AD24 AD22 AD18 PCIFRAME STOP AD15 AD11 CBE0 AD4 AD0 NMI IRQ/IRL2 IRQ/IRL5/ FD5/ MODE4 IRQ/IRL7/ FD7 VSSQ VSS-RTC 25 1.3 A 1 Section 1 Overview Pin Arrangement Section 1 Overview 1.4 Pin Functions Table 1.2 lists the pin functions of the SH7780. In the I/O column, I, O, and IO indicate input, output, and input/output, respectively. In the GPIO column, for example, A0 indicates the port A0, which also functions as a general I/O port (input/output). Table 1.2 Pin Functions No. Pin No. Pin Name I/O Function 1 A1 VSSQ-DDR — DDR I/O GND 2 A2 VCCQ-DDR — DDR I/O VCC 3 A3 DDR-VREF I DDR VREF 4 A4 MCLK O DDR clock 5 A5 MCLK O DDR clock 6 A6 MWE O DDR write enable 7 A7 MRAS O DDR RAS 8 A8 BA0 O DDR bank address 0 9 A9 MA10 O DDR address 10 A10 MA1 O DDR address 11 A11 MA3 O DDR address 12 A12 PRESET I Power-on reset 13 A13 DRAK1/MODE7 O/I DMA channel 1 transfer request acknowledge/mode control 7 L0(O) 14 A14 DREQ0 I DMA channel 0 request K7 15 A15 DREQ3/INTC/AUDATA1 I/I/O DMA channel 3 request/ PCI interrupt C/H-UDI emulator K4* 16 A16 DACK2/MRESETOUT/AUDATA2 O/O/O DMA channel 2 bus acknowledgment/manual reset output/ H-UDI emulator K3 17 A17 TDI I H-UDI data 18 A18 AUDSYNC/FCE O/O H-UDI emulator/NAND flash CE 19 A19 AUDATA1/FD1 O/IO H-UDI emulator/NAND flash data 20 A20 SIOF_SYNC/HAC_SYNC/SSI_WS IO/O/IO SIOF flame synchronous/ J3 HAC flame synchronous/SSI word select GPIO* Rev.1.00 Dec. 13, 2005 Page 11 of 1286 REJ09B0158-0100 Section 1 Overview No. Pin No. Pin Name I/O Function GPIO* 21 A21 SCIF1_TXD/MCCLK/MODE5 O/O/I SCIF 1 transmit data/ card clock output/mode control 5 H6(O) 22 A22 XTAL2 O RTC clock 23 A23 EXTAL2 I RTC crystal resonator 24 A24 VDD-RTC — RTC VDD 25 A25 VSS-RTC — RTC GND 26 B1 VSSQ-DDR — DDR I/O GND 27 B2 VCCQ-DDR — DDR I/O VCC 28 B3 BKPRST I Back-up reset 29 B4 CKE O DDR clock enable 30 B5 MA13 O DDR address 31 B6 MCAS O DDR CAS 32 B7 MCS O DDR chip select 33 B8 BA1 O DDR bank address 1 34 B9 MA0 O DDR address 35 B10 MA2 O DDR address 36 B11 MA4 O DDR address 37 B12 VSS — Internal GND 38 B13 DRAK2/CE2A/AUDCK O/O/O DMA channel 2 transfer request acknowledge/PCMCIA CE2/ H-UDI emulator K1(O) 39 B14 DREQ1 I DMA channel 1 request K6 40 B15 DACK0/MODE0 O/I DMA channel 0 bus acknowledgement/mode control 0 L3(O) 41 B16 DACK3/IRQOUT/AUDATA3 O/O/O DMA channel 3 bus acknowledgement/ interrupt request output/H-UDI emulator K2 42 B17 TDO O H-UDI data 43 B18 AUDCK/FALE O/O H-UDI emulator/NAND flash ALE 44 B19 AUDATA0/FD0 O/IO H-UDI emulator/NAND flash data 45 B20 SIOF_RXD/HAC_SDIN/SSI_SCK I/I/IO SIOF receive data/HAC serial data J4 incoming to Rx frame/SSI serial bit clock 46 B21 SCIF1_SCK/MCCMD IO/IO SCIF1 serial clock/ MMCIF command response Rev.1.00 Dec. 13, 2005 Page 12 of 1286 REJ09B0158-0100 H7 Section 1 Overview No. Pin No. Pin Name I/O Function GPIO* 47 B22 SCIF0_RXD/HSPI_RX/FRB I/I/I SCIF receive data/HSPI receive data input/NAND flash ready or busy H2 48 B23 TCLK/IOIS16 IO/I TMU clock/PCMCIA IOIS16 J0* 49 B24 XRTCSTBI I RTC standby 50 B25 VSSQ — I/O GND 51 C1 MDA0 IO DDR data 52 C2 VCCQ-DDR — DDR I/O VCC 53 C3 VSSQ-DDR — DDR I/O GND 54 C4 VCCQ-DDR — DDR I/O VCC 55 C5 MA12 O DDR address 56 C6 MA11 O DDR address 57 C7 MA9 O DDR address 58 C8 MA8 O DDR address 59 C9 MA7 O DDR address 60 C10 MA6 O DDR address 61 C11 MA5 O DDR address 62 C12 DRAK0/MODE2 O/I DMA channel 0 transfer request acknowledge/mode control 2 L1(O) 63 C13 DRAK3/CE2B/AUDSYNC O/O/O DMA channel 3 request acknowledgment/PCMCIA CE2/ H-UDI emulator K0(O) 64 C14 DREQ2/INTB/AUDATA0 I/I/O DMA channel 2 request/PCI interrupt B/H-UDI emulator K5* 65 C15 DACK1/MODE1 O/I DMA channel 1 bus acknowledgement/mode control 1 L2(O) 66 C16 TCK I H-UDI clock 67 C17 ASEBRK/BRKACK I/O H-UDI emulator 68 C18 AUDATA3/FD3 O/IO H-UDI emulator/NAND flash data 69 C19 SIOF_SCK/HAC_BITCLK/SSI_CLK IO/I/IO SIOF serial clock/HAC/SSI serial bit clock J1 70 C20 SIOF_TXD/HAC_SDOUT/ SSI_SDATA O/O/IO SIOF transmit data/HAC serial data/ SSI serial data 71 C21 SCIF0_RTS/HSPI_CS/FSE IO/IO/O SCIF modem control/HSPI chip H0* selection/NAND flash spare area enable J5 Rev.1.00 Dec. 13, 2005 Page 13 of 1286 REJ09B0158-0100 Section 1 Overview No. Pin No. 72 C22 SCIF0_TXD/HSPI_TX/FWE/MODE8 O/O/O/I SCIF0 transmit data/HSPI transmit data/NAND flash write enable/ mode control 8 H3(O) 73 C23 SCIF0_SCK/HSPI_CLK/FRE IO/IO/O SCIF0 serial clock/HSPI serial clock/NAND flash read enable H4 74 C24 VDDQ — I/O VDD 75 C25 IRQ/IRL7/FD7 I/IO IRL IRQ interrupt request 7/ NAND flash data 76 D1 MDA1 IO DDR data 77 D2 MDA16 IO DDR data 78 D3 VSSQ-DDR — DDR I/O GND 79 D4 VCCQ-DDR — DDR I/O VCC 80 D5 VSSQ-DDR — DDR I/O GND 81 D6 VSSQ-DDR — DDR I/O GND 82 D7 VCCQ-DDR — DDR I/O VCC 83 D8 VCCQ-DDR — DDR I/O VCC 84 D9 VSSQ-DDR — DDR I/O GND 85 D10 VSSQ-DDR — DDR I/O GND 86 D11 VCCQ-DDR — DDR I/O VCC 87 D12 VSSQ — I/O GND 88 D13 VDDQ — I/O VDD 89 D14 VDDQ — I/O VDD 90 D15 VSSQ — I/O GND 91 D16 TMS I H-UDI emulator 92 D17 TRST I H-UDI emulator 93 D18 AUDATA2/FD2 O/IO H-UDI emulator/NAND flash data 94 D19 SIOF_MCLK/HAC_RES I/O SIOF master clock/HAC reset J2 95 D20 SCIF1_RXD/MCDAT I/IO SCIF1 receive data/MMCIF data H5 96 D21 SCIF0_CTS/INTD/FCLE IO/I/O SCIF modem control/PCI interrupt D /NAND flash command latch enable H1* 97 D22 VDD — Internal VDD Pin Name Rev.1.00 Dec. 13, 2005 Page 14 of 1286 REJ09B0158-0100 I/O Function GPIO* E6* Section 1 Overview No. Pin No. Pin Name I/O Function 98 D23 VDD — Internal VDD 99 D24 IRQ/IRL6/FD6/MODE6 I/IO/I IRL IRQ interrupt request 6/NAND flash data/mode control 6 100 D25 IRQ/IRL5/FD5/MODE4 I/IO/I IRL IRQ interrupt request 5/NAND flash data/mode control 4 101 E1 MDA2 IO DDR data 102 E2 MDA17 IO DDR data 103 E3 MDA18 IO DDR data 104 E4 VCCQ-DDR — DDR I/O VCC 105 E5 VSSQ-DDR — DDR I/O GND 106 E6 VSSQ-DDR — DDR I/O GND 107 E7 VCCQ-DDR — DDR I/O VCC 108 E8 VDD — Internal VDD 109 E9 VSS — Internal GND 110 E10 VSSQ-DDR — DDR I/O GND 111 E11 VCCQ-DDR — DDR I/O VCC 112 E12 VSSQ — I/O GND 113 E13 VDDQ — I/O VDD 114 E14 VDD — Internal VDD 115 E15 VSS — Internal GND 116 E16 VSSQ — I/O GND 117 E17 VSSQ — I/O GND 118 E18 VDDQ — I/O VDD 119 E19 VDDQ — I/O VDD 120 E20 VDDQ — I/O VDD 121 E21 VSSQ — I/O GND 122 E22 VDD — Internal VDD 123 E23 IRQ/IRL4/FD4/MODE3 I/IO/I IRL IRQ interrupt request 4/ NAND flash data/mode control 3 124 E24 IRQ/IRL3 I IRL IRQ interrupt request 3 125 E25 IRQ/IRL2 I IRL IRQ interrupt request 2 GPIO* Rev.1.00 Dec. 13, 2005 Page 15 of 1286 REJ09B0158-0100 Section 1 Overview No. Pin No. Pin Name I/O Function 126 F1 MDA3 IO DDR data 127 F2 MDA19 IO DDR data 128 F3 MDA20 IO DDR data 129 F4 VCCQ-DDR — DDR I/O VCC 130 F5 VSSQ-DDR — DDR I/O GND 131 F21 VDDQ — I/O VDD 132 F22 VDDQ — I/O VDD 133 F23 IRQ/IRL1 I IRL IRQ interrupt request 1 134 F24 IRQ/IRL0 I IRL IRQ interrupt request 0 135 F25 NMI I Nonmaskable interrupt 136 G1 MDA4 IO DDR data 137 G2 MDA21 IO DDR data 138 G3 MDA22 IO DDR data 139 G4 VSS — Internal GND 140 G5 VSS — Internal GND 141 G21 VSSQ — I/O GND 142 G22 AD1 IO PCI address/data D1 143 G23 AD3 IO PCI address/data D3 144 G24 AD5 IO PCI address/data D5 145 G25 AD0 IO PCI address/data D0 146 H1 MDA5 IO DDR data 147 H2 MDA23 IO DDR data 148 H3 MDQS2 IO DDR data strobe 149 H4 VDD — Internal VDD 150 H5 VDD — Internal VDD 151 H21 VSS — Internal GND 152 H22 AD7 IO PCI address/data D7 153 H23 AD8 IO PCI address/data C0 154 H24 AD2 IO PCI address/data D2 155 H25 AD4 IO PCI address/data D4 Rev.1.00 Dec. 13, 2005 Page 16 of 1286 REJ09B0158-0100 GPIO* Section 1 Overview No. Pin No. Pin Name I/O Function 156 J1 MDA7 IO DDR data 157 J2 MDA6 IO DDR data 158 J3 MDQM2 O DDR data mask 159 J4 VDD-DLL1 — DLL1 VDD 160 J5 VSS-DLL1 — DLL1 GND 161 J21 VDD — Internal VDD 162 J22 AD10 IO PCI address/data C2 163 J23 AD12 IO PCI address/data C4 164 J24 AD6 IO PCI address/data D6 165 J25 CBE0 IO PCI command/byte enable 166 K1 MDQM0 O DDR data mask 167 K2 MDQS0 IO DDR data strobe 168 K3 MDQS3 IO DDR data strobe 169 K4 VDD — Internal VDD 170 K5 VSS — Internal GND 171 K10 VSS — Internal GND 172 K11 VSS — Internal GND 173 K12 VSS — Internal GND 174 K13 VSS — Internal GND 175 K14 VSS — Internal GND 176 K15 VSS — Internal GND 177 K16 VSS — Internal GND 178 K21 VDD — Internal VDD 179 K22 AD14 IO PCI address/data 180 K23 CBE1 IO PCI command/byte enable 181 K24 AD9 IO PCI address/data C1 182 K25 AD11 IO PCI address/data C3 183 L1 MDQS1 IO DDR data strobe 184 L2 MDQM1 O DDR data mask GPIO* C6 Rev.1.00 Dec. 13, 2005 Page 17 of 1286 REJ09B0158-0100 Section 1 Overview No. Pin No. Pin Name I/O Function 185 L3 MDQM3 O DDR data mask 186 L4 VDD — Internal VDD 187 L5 VSS — Internal GND 188 L10 VSS — Internal GND 189 L11 VSS — Internal GND 190 L12 VSS — Internal GND 191 L13 VSSQ — I/O GND 192 L14 VSS — Internal GND 193 L15 VSS — Internal GND 194 L16 VSS — Internal GND 195 L21 VDDQ — I/O VDD 196 L22 SERR IO PCI system error 197 L23 PERR IO PCI parity error 198 L24 AD13 IO PCI address/data C5 199 L25 AD15 IO PCI address/data C7 200 M1 MDA8 IO DDR data 201 M2 MDA24 IO DDR data 202 M3 MDA25 IO DDR data 203 M4 VDD-DLL2 — DLL2 VDD 204 M5 VSS-DLL2 — DLL2 GND 205 M10 VSS — Internal GND 206 M11 VSS — Internal GND 207 M12 VSSQ-DDR — DDR I/O GND 208 M13 VSSQ — I/O GND 209 M14 VSS — Internal GND 210 M15 VSS — Internal GND 211 M16 VSS — Internal GND 212 M21 VSS — Internal GND 213 M22 LOCK IO PCI lock 214 M23 DEVSEL IO PCI device select Rev.1.00 Dec. 13, 2005 Page 18 of 1286 REJ09B0158-0100 GPIO* Section 1 Overview No. Pin No. Pin Name I/O Function 215 M24 PAR IO PCI parity 216 M25 STOP IO PCI transaction stop 217 N1 MDA9 IO DDR data 218 N2 MDA26 IO DDR data 219 N3 MDA27 IO DDR data 220 N4 VSSQ-DDR — DDR I/O GND 221 N5 VSSQ-DDR — DDR I/O GND 222 N10 VSS — Internal GND 223 N11 VSS — Internal GND 224 N12 VSSQ-DDR — DDR I/O GND 225 N13 VSSQ — I/O GND 226 N14 VSS — Internal GND 227 N15 VSS — Internal GND 228 N16 VSS — Internal GND 229 N21 VSS — Internal GND 230 N22 IRDY IO PCI initiator ready 231 N23 CBE2 IO PCI command/byte enable 232 N24 TRDY IO PCI target ready 233 N25 PCIFRAME IO PCI cycle frame 234 P1 MDA10 IO DDR data 235 P2 MDA28 IO DDR data 236 P3 MDA29 IO DDR data 237 P4 VCCQ-DDR — DDR I/O VCC 238 P5 VCCQ-DDR — DDR I/O VCC 239 P10 VSS — Internal GND 240 P11 VSS — Internal GND 241 P12 VSSQ-DDR — DDR I/O GND 242 P13 VSSQ — I/O GND 243 P14 VSS — Internal GND 244 P15 VSS — Internal GND GPIO* Rev.1.00 Dec. 13, 2005 Page 19 of 1286 REJ09B0158-0100 Section 1 Overview No. Pin No. Pin Name I/O Function 245 P16 VSS — Internal GND 246 P21 VDD — Internal VDD 247 P22 AD17 IO PCI address/data B1 248 P23 AD19 IO PCI address/data B3 249 P24 AD16 IO PCI address/data B0 250 P25 AD18 IO PCI address/data B2 251 R1 MDA11 IO DDR data 252 R2 MDA30 IO DDR data 253 R3 MDA31 IO DDR data 254 R4 VCCQ-DDR — DDR I/O VCC 255 R5 VCCQ-DDR — DDR I/O VCC 256 R10 VSS — Internal GND 257 R11 VSS — Internal GND 258 R12 VSS — Internal GND 259 R13 VSSQ — I/O GND 260 R14 VSS — Internal GND 261 R15 VSS — Internal GND 262 R16 VSS — Internal GND 263 R21 VDDQ — I/O VDD 264 R22 AD21 IO PCI address/data B5 265 R23 AD23 IO PCI address/data B7 266 R24 AD20 IO PCI address/data B4 267 R25 AD22 IO PCI address/data B6 268 T1 MDA13 IO DDR data 269 T2 MDA12 IO DDR data 270 T3 VSSQ-DDR — DDR I/O GND 271 T4 VSSQ-DDR — DDR I/O GND 272 T5 VCCQ-DDR — DDR I/O VCC 273 T10 VSS — Internal GND 274 T11 VSS — Internal GND Rev.1.00 Dec. 13, 2005 Page 20 of 1286 REJ09B0158-0100 GPIO* Section 1 Overview No. Pin No. Pin Name I/O Function 275 T12 VSS — Internal GND 276 T13 VSS — Internal GND 277 T14 VSS — Internal GND 278 T15 VSS — Internal GND 279 T16 VSS — Internal GND 280 T21 VDD — Internal VDD 281 T22 CBE3 IO PCI command/byte enable 282 T23 AD25 IO PCI address/data 283 T24 IDSEL I PCI configuration device select 284 T25 AD24 IO PCI address/data 285 U1 MDA15 IO DDR data 286 U2 MDA14 IO DDR data 287 U3 VSSQ-DDR — DDR I/O GND 288 U4 VSSQ-DDR — DDR I/O GND 289 U5 VSSQ-DDR — DDR I/O GND 290 U21 VDD — Internal VDD 291 U22 AD27 IO PCI address/data A3 292 U23 AD29 IO PCI address/data A5 293 U24 AD26 IO PCI address/data A2 294 U25 AD28 IO PCI address/data A4 295 V1 VCCQ-DDR — DDR I/O VCC 296 V2 VCCQ-DDR — DDR I/O VCC 297 V3 VCCQ-DDR — DDR I/O VCC 298 V4 VCCQ-DDR — DDR I/O VCC 299 V5 VCCQ-DDR — DDR I/O VCC 300 V21 VSS — Internal GND 301 V22 AD31 IO PCI address/data A7 302 V23 REQ3 I Bus request (PCI host) E3* 303 V24 AD30 IO PCI address/data A6 304 V25 GNT3 O PCI bus grant E0* GPIO* A1 A0 Rev.1.00 Dec. 13, 2005 Page 21 of 1286 REJ09B0158-0100 Section 1 Overview No. Pin No. Pin Name I/O Function 305 W1 A25 O Address bus 306 W2 STATUS0/CMT_CTR0 O/IO Status0/CMT0 timer counter 307 W3 STATUS1/CMT_CTR1 O/IO Status1/CMT1 timer counter 308 W4 VDD — Internal VDD 309 W5 VDD — Internal VDD 310 W21 VSS — Internal GND 311 W22 REQ2 I Bus request (PCI host) E4* 312 W23 REQ1 I Bus request (PCI host) E5* 313 W24 GNT2 O PCI bus grant E1* 314 W25 GNT1 O PCI bus grant E2* 315 Y1 A22 O Address bus 316 Y2 A23 O Address bus 317 Y3 A24 O Address bus 318 Y4 VSS — Internal GND 319 Y5 VSS — Internal GND 320 Y21 VDDQ — I/O VDD 321 Y22 REQ0/REQOUT I/O Bus request (PCI host)/ bus request output 322 Y23 PCICLK I PCI input clock 323 Y24 GNT0/GNTIN O/I PCI bus grant 324 Y25 PCIRESET O PCI reset 325 AA1 A19 O Address bus 326 AA2 A20 O Address bus 327 AA3 A21 O Address bus 328 AA4 VDDQ — I/O VDD 329 AA5 VSSQ — I/O GND 330 AA6 VSS — Internal GND 331 AA7 VDD — Internal VDD 332 AA8 VDDQ — I/O VDD 333 AA9 VSSQ — I/O GND Rev.1.00 Dec. 13, 2005 Page 22 of 1286 REJ09B0158-0100 GPIO* Section 1 Overview No. Pin No. 334 Pin Name I/O Function GPIO* AA10 VSS — Internal GND 335 AA11 VDD — Internal VDD 336 AA12 VDDQ — I/O VDD 337 AA13 VSSQ — I/O GND 338 AA14 VSSQ — I/O GND 339 AA15 VDD — Internal VDD 340 AA16 VSS — Internal GND 341 AA17 VDDQ — I/O VDD 342 AA18 VDDQ — I/O VDD 343 AA19 VSSQ — I/O GND 344 AA20 VSSQ — I/O GND 345 AA21 VSSQ — I/O GND 346 AA22 NC — Open 347 AA23 NC — Open 348 AA24 VSS — Internal GND 349 AA25 INTA IO PCI interrupt A 350 AB1 A16 O Address bus 351 AB2 A17 O Address bus 352 AB3 A18 O Address bus 353 AB4 VSSQ — I/O GND 354 AB5 A6 O Address bus 355 AB6 A2 O Address bus 356 AB7 D30 IO Data bus F6 357 AB8 D26 IO Data bus F2 358 AB9 D23 IO Data bus G7 359 AB10 VSSQ — I/O GND 360 AB11 VDDQ — I/O VDD 361 AB12 VDDQ — I/O VDD 362 AB13 VSSQ — I/O GND 363 AB14 VDDQ — I/O VDD Rev.1.00 Dec. 13, 2005 Page 23 of 1286 REJ09B0158-0100 Section 1 Overview No. Pin No. 364 Pin Name I/O Function AB15 VDDQ — I/O VDD 365 AB16 VSSQ — I/O GND 366 AB17 BACK O Bus acknowledgement 367 AB18 CS4 O Chip select 4 368 AB19 CS6 O Chip select 6 369 AB20 VSS-PLL3 — PLL3 GND 370 AB21 VDD — Internal VDD 371 AB22 VDDQ — I/O VDD 372 AB23 VDDQ — I/O VDD 373 AB24 VSS — Internal GND 374 AB25 VSS — Internal GND 375 AC1 A14 O Address bus 376 AC2 A15 O Address bus 377 AC3 VDDQ — I/O VDD 378 AC4 A9 O Address bus 379 AC5 A5 O Address bus 380 AC6 A1 O Address bus 381 AC7 D29 IO Data bus F5 382 AC8 D25 IO Data bus F1 383 AC9 D22 IO Data bus G6 384 AC10 D19 IO Data bus G3 385 AC11 D15 IO Data bus 386 AC12 D14 IO Data bus 387 AC13 D11 IO Data bus 388 AC14 D8 IO Data bus 389 AC15 D6 IO Data bus 390 AC16 D3 IO Data bus 391 AC17 BREQ I Bus request 392 AC18 BS O Bus start 393 AC19 CS5 O Chip select 5 Rev.1.00 Dec. 13, 2005 Page 24 of 1286 REJ09B0158-0100 GPIO* M0 M1 Section 1 Overview No. Pin No. 394 Pin Name I/O Function GPIO* AC20 CS1 O Chip select 1 395 AC21 VSS-PLL2 — PLL2 GND 396 AC22 VDD — Internal VDD 397 AC23 VDDQ — I/O VDD 398 AC24 VDDQ — I/O VDD 399 AC25 MPMD I Mode control 400 AD1 A13 O Address bus 401 AD2 VDDQ — I/O VDD 402 AD3 A11 O Address bus 403 AD4 A8 O Address bus 404 AD5 A4 O Address bus 405 AD6 A0 O Address bus 406 AD7 D28 IO Data bus F4 407 AD8 D24 IO Data bus F0 408 AD9 D21 IO Data bus G5 409 AD10 D18 IO Data bus G2 410 AD11 D16 IO Data bus G0 411 AD12 D13 IO Data bus 412 AD13 D10 IO Data bus 413 AD14 D7 IO Data bus 414 AD15 D5 IO Data bus 415 AD16 D2 IO Data bus 416 AD17 D0 IO Data bus 417 AD18 RD/FRAME O Read strobe/MPX interface cycle frame 418 AD19 CS2 O Chip select 2 419 AD20 CS0 O Chip select 0 420 AD21 VDD-PLL3 — PLL3 VDD 421 AD22 VSS-PLL1 — PLL1 GND 422 AD23 VSSQ — I/O GND 423 AD24 VDDQ — I/O VDD Rev.1.00 Dec. 13, 2005 Page 25 of 1286 REJ09B0158-0100 Section 1 Overview No. Pin No. 424 I/O Function AD25 VSSQ — I/O GND 425 AE1 VSSQ — I/O GND 426 AE2 A12 O Address bus 427 AE3 A10 O Address bus 428 AE4 A7 O Address bus 429 AE5 A3 O Address bus 430 AE6 D31 IO Data bus F7 431 AE7 D27 IO Data bus F3 432 AE8 WE3/IOWR O/O Selection signal for D31 to D24 433 AE9 D20 IO Data bus G4 434 AE10 D17 IO Data bus G1 435 AE11 WE2/IORD O/O Selection signal for D23 to D16/PCMCIA IORD 436 AE12 D12 IO Data bus 437 AE13 D9 IO Data bus 438 AE14 WE1 O Selection signal for D15 to D8 439 AE15 D4 IO Data bus 440 AE16 D1 IO Data bus 441 AE17 WE0/REG O/O Selection signal for D7 to D0/PCMCIA REG 442 AE18 R/W O Read/write 443 AE19 RDY I Bus ready 444 AE20 CLKOUT O Clock output 445 AE21 VDD-PLL2 — PLL2 VDD 446 AE22 VDD-PLL1 — PLL1 VDD 447 AE23 XTAL O Crystal resonator 448 AE24 EXTAL I External input clock/crystal resonator 449 AE25 VSSQ — I/O GND Note: * Pin Name Can be used as a GPIO interrupt pin. (O) Only outputs. Rev.1.00 Dec. 13, 2005 Page 26 of 1286 REJ09B0158-0100 GPIO* Section 1 Overview 1.5 Memory Address Map The SH7780 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical address spaces (normal mode and extended mode). For details of mappings from the virtual address space to the physical address spaces, see section 7, Memory Management Unit (MMU). The external memory space of the SH7780 consists of the LBSC space, DDRIF space and PCIC space. The LBSC has up to 384 Mbytes, the DDRIF has up to 256 Mbytes and the PCIC has up to 512 Mbytes external memory space individually and the SH7780 can control the external memory space up to 1152 Mbytes totally. Areas 0, 1, and 6 are controlled by the LBSC. Areas 2, 4, and 5 are controlled by the LBSC, DDRIF or PCIC that depends on the setting of the memory address map select register (MMSELR) of the LBSC. Note that area 3 is for the DDRIF. For details, see section 11, Local Bus Sate Controller (LBSC), section 12, DDR-SDRAM Interface (DDRIF) or section 13, PCI Controller (PCIC). Figure 1.3 shows the physical address space of the SH7780. Figure 1.4 shows the relationship between the AREASEL bits and the memory address map. The 32-bit physical address space corresponds with the address space of the SuperHyway bus. Rev.1.00 Dec. 13, 2005 Page 27 of 1286 REJ09B0158-0100 Section 1 Overview H'0000 0000 Area 0 (LBSC) H'0400 0000 Area 1 (LBSC) H'0800 0000 Area 2 (LBSC/DDRIF) H'0C00 0000 Area 3 (DDRIF) H'1000 0000 Area 4 (LBSC/DDRIF/PCIC) H'1400 0000 Area 5 (LBSC/DDRIF) H'1800 0000 Area 6 (LBSC) H'1C00 0000 Area 7 (Reserved) H'2000 0000 29-bit physical address space (Normal mode) (Undefined) 32-bit physical address space (Extended mode) H'4000 0000 DDR-SDRAM (DDRIF) H'E000 0000 Store queue area (64MB)* H'E500 0000 On-chip memory area (16MB)* H'F000 0000 Cache, TLB and PMB address /data array area (128MB)* Control register area (H'FC00 0000 to H'FFFF FFFF) H'FC00 0000 H-UDI (8MB) H'FC80 0000 DMAC (8MB) H'FD00 0000 PCI memory (16MB) H'FE00 0000 PCIC (4MB) H'8000 0000 H'FE40 0000 SuperHyway RAM (4MB) H'FE80 0000 DDRIF (8MB) (Undefined) H'C000 0000 PCI (PCIC) H'E000 0000 (Internal resources) H'FFFF FFFF H'FF00 0000 CPU (4MB) H'FF40 0000 SuperHyway router (4MB) H'FF80 0000 LBSC (4MB) H'FFC0 0000 Peripheral modules (4MB) Note: For details of these areas, refer to section 7.1.1, Address Spaces. Figure 1.3 Physical Address Space of SH7780 Rev.1.00 Dec. 13, 2005 Page 28 of 1286 REJ09B0158-0100 Section 1 Overview MMSELR.AREASEL[2:0]* B'000 B'001 B'010 B'011 B'100 Area 0 (LBSC) LBSC LBSC LBSC LBSC LBSC Area 1 (LBSC) LBSC LBSC LBSC LBSC LBSC Area 2 (LBSC/DDRIF) LBSC LBSC DDRIF-0 DDRIF-0 DDRIF-0 Area 3 (DDRIF) DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-1 Area 4 (LBSC/DDRIF/PCIC) LBSC PCIC LBSC PCIC DDRIF-2 Area 5 (LBSC/DDRIF) LBSC LBSC LBSC LBSC DDRIF-3 Area 6 (LBSC) LBSC LBSC LBSC LBSC LBSC H'4000 0000 DDRIF-2 DDRIF-2 DDRIF-2 DDRIF-2 DDRIF-2 H'4400 0000 DDRIF-3 DDRIF-3 DDRIF-3 DDRIF-3 DDRIF-3 H'4800 0000 DDRIF-0 DDRIF-0 DDRIF-0 DDRIF-0 DDRIF-0 H'4C00 0000 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-1 H'5000 0000 DDRIF-2 DDRIF-2 DDRIF-2 DDRIF-2 DDRIF-2 H'5400 0000 DDRIF-3 DDRIF-3 DDRIF-3 DDRIF-3 DDRIF-3 H'5800 0000 DDRIF-0 DDRIF-0 DDRIF-0 DDRIF-0 DDRIF-0 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-2 DDRIF-2 DDRIF-2 DDRIF-2 DDRIF-2 H'6800 0000 DDRIF-3 DDRIF-0 DDRIF-3 DDRIF-0 DDRIF-3 DDRIF-0 DDRIF-3 DDRIF-0 DDRIF-3 DDRIF-0 H'6C00 0000 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-2 DDRIF-2 DDRIF-1 DDRIF-2 DDRIF-1 H'7000 0000 DDRIF-2 DDRIF-2 H'7400 0000 DDRIF-3 DDRIF-3 DDRIF-3 DDRIF-3 DDRIF-3 DDRIF-0 DDRIF-0 DDRIF-0 DDRIF-0 DDRIF-0 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-1 DDRIF-1 PCIC PCIC PCIC PCIC PCIC H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 29-bit physical address space (Normal mode) Area 7 (Reserved area) H'2000 0000 (Undefined) H'5C00 0000 DDR-SDRAM (DDRIF) H'6000 0000 H'6400 0000 : Shadow H'7800 0000 H'7C00 0000 32-bit physical address space (Extended mode) H'8000 0000 (Undefined) H'C000 0000 PCI (PCIC) H'E000 0000 H'FFFF FFFF (Internal resources) Note: Memory Address Map Select Register (MMSELR) Area Select Bit (AREASEL) For details, refer to section 11.4.1, Memory Address Map Select Register (MMSELR). Figure 1.4 Relationship between AREASEL Bits and Memory Address Map Rev.1.00 Dec. 13, 2005 Page 29 of 1286 REJ09B0158-0100 Section 1 Overview 1.6 SuperHyway Bus The SH7780 is implemented with the SuperHyway bus as the system bus. The SuperHyway bus is a 32-bit-address, 64-bit-data internal bus capable of up to 200 MHz operation that is connected to on-chip modules to allow high speed communication. Each module that is connected to the SuperHyway bus operates as an initiator (i.e. , bus master) that issues a transfer request or a target that replies with a response to the request. The transaction is controlled by the dedicated SuperHyway router. The CPU, PCIC, and DMAC modules can all operate as an initiator. The LRU method is used to decide the request priority of the SuperHyway bus mastership. The initial request priority order is: CPU > DMAC > PCIC. The response priority level is fixed: peripheral modules* > DMAC > CPU > SuperHyway RAM > LBSC > PCIC > DDRIF. Note that when using debugging function (HUDI emulator), the debugging functional module has the highest priority. The transfer data size varies with each module. For details, refer to the corresponding section for each module. An actual transaction on the SuperHyway bus is started from a request issued by the initiator module according to a read/write command sent to the SuperHyway bus address (physical address), and then the target module replies with a response to the request (LOAD/STORE transaction). In addition, a transaction that controls the cache coherency occurs if necessary (FLUSH/PURGE transaction). Note that these transactions are done automatically by the SuperHyway modules, so they cannot be explicitly issued by software. Note: "Peripheral modules" means modules that are connected to the peripheral bus (except for the INTC and DMAC modules). Rev.1.00 Dec. 13, 2005 Page 30 of 1286 REJ09B0158-0100 Section 1 Overview 1.7 SuperHyway Memory (SuperHyway RAM) The SH7780 includes an on-chip SuperHyway memory which stores instructions or data. The SuperHyway memory has the following features. • Capacity Total SuperHyway memory capacity is 32 Kbytes (512 words × 256 bits × 2 pages). • Memory address map The SuperHyway memory is allocated within the physical address H'FE41 0000 to H'FE41 3FFF and H'FE42 0000 to H'FE42 3FFF. • Ports Each page has one common read and write port, and is connected to the SuperHyway bus via a 4-stage buffer respectively. High-speed access to the SuperHyway memory is enabled by the SuperHyway bus master. • Access The SuperHyway memory is always accessed by the SuperHyway bus master module, including the CPU, via the SuperHyway bus which is a physical address bus. 1-/2-/4-/8-/16-/32-byte access is possible for both reading and writing (with wraparound on 32-byte boundary data). A 32-byte cache fill can be read out with one access (an 8-byte × 4 transfer on the SuperHyway bus). Note that the read/write operation on the SuperHyway bus is done with one clock. After that the bus is released. • Minimum access time 1-/2-/4-/8-byte read access: 14 clock cycles; 1-/2-/4-/8-byte write access: 12 clock cycles 16-/32-byte read access: 17 clock cycles; 16-/32-byte write access: 15 clock cycles (The SuperHyway clock ≤ 200 MHz) • Usage note A SuperHyway bus master module, such as DMAC, can access the SuperHyway memory in sleep mode. Rev.1.00 Dec. 13, 2005 Page 31 of 1286 REJ09B0158-0100 Section 1 Overview Rev.1.00 Dec. 13, 2005 Page 32 of 1286 REJ09B0158-0100 Section 2 Programming Model Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. 2.1 Data Formats The data formats supported in this LSI are shown in figure 2.1. 7 0 Byte (8 bits) 15 0 Word (16 bits) 31 0 Longword (32 bits) 31 30 s e Single-precision floating-point (32 bits) Double-precision floating-point (64 bits) 63 62 s e 51 22 0 f 0 f [Legend] s: Sign field e: Exponent field f: Fraction field Figure 2.1 Data Formats Rev.1.00 Dec. 13, 2005 Page 33 of 1286 REJ09B0158-0100 Section 2 Programming Model 2.2 Register Descriptions 2.2.1 Privileged Mode and Banks Processing Modes: This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processing modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processing mode change. • Privileged mode In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. • User mode In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processing modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processing mode. Rev.1.00 Dec. 13, 2005 Page 34 of 1286 REJ09B0158-0100 Section 2 Programming Model Floating-Point Registers and System Registers Related to FPU: There are thirty-two floatingpoint registers, FR0–FR15 and XF0–XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. System registers related to the FPU comprise the floating-point communication register (FPUL) and the floating-point status/control register (FPSCR). These registers are used for communication between the FPU and the CPU, and the exception handling setting. Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value* General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 Undefined Control registers SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = B'1111, reserved bits = 0, others = undefined GBR, SSR, SPC, SGR, DBR Undefined VBR System registers MACH, MACL, PR Floating-point registers Note: * H'00000000 Undefined PC H'A0000000 FR0 to FR15, XF0 to XF15, FPUL Undefined FPSCR H'00040001 Initialized by a power-on reset and manual reset. The CPU register configuration in each processing mode is shown in figure 2.2. User mode and privileged mode are switched by the processing mode bit (MD) in the status register. Rev.1.00 Dec. 13, 2005 Page 35 of 1286 REJ09B0158-0100 Section 2 Programming Model 31 0 31 0 31 0 R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SR SSR SR SSR GBR MACH MACL PR GBR MACH MACL PR VBR GBR MACH MACL PR VBR PC PC SPC PC SPC SGR SGR DBR (a) Register configuration in user mode R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1) DBR R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0) Notes: 1. R0 is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. 2. Banked registers 3. Banked registers Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Banked registers Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.2 CPU Register Configuration in Each Processing Mode Rev.1.00 Dec. 13, 2005 Page 36 of 1286 REJ09B0158-0100 Section 2 Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode. This LSI has two processing modes, user mode and privileged mode. • R0_BANK0 to R7_BANK0 Allocated to R0 to R7 in user mode (SR.MD = 0) Allocated to R0 to R7 when SR.RB = 0 in privileged mode (SR.MD = 1). • R0_BANK1 to R7_BANK1 Cannot be accessed in user mode. Allocated to R0 to R7 when SR.RB = 1 in privileged mode. SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 Figure 2.3 General Registers Rev.1.00 Dec. 13, 2005 Page 37 of 1286 REJ09B0158-0100 Section 2 Programming Model Note on Programming: 2.2.3 As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0 to R7 (R0_BANK0 to R7_BANK0). Floating-Point Registers Figure 2.4 shows the floating-point register configuration. There are thirty-two 32-bit floatingpoint registers, FPR0_BANK0 to FPR15_BANK0, AND FPR0_BANK1 to FPR15_BANK1, comprising two banks. These registers are referenced as FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, or XMTRX. Reference names of each register are defined depending on the state of the FR bit in FPSCR (see figure 2.4). 1. Floating-point registers, FPRn_BANKi (32 registers) FPR0_BANK0 to FPR15_BANK0 FPR0_BANK1 to FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0 to FR15 are assigned to FPR0_BANK0 to FPR15_BANK0; when FPSCR.FR = 1, FR0 to FR15 are assigned to FPR0_BANK1 to FPR15_BANK1. 3. Double-precision floating-point registers or single-precision floating-point registers, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} 4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers. FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} 5. Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0 to XF15 are assigned to FPR0_BANK1 to FPR15_BANK1; when FPSCR.FR = 1, XF0 to XF15 are assigned to FPR0_BANK0 to FPR15_BANK0. 6. Double-precision floating-point extended registers, XDi (8 registers): An XD register comprises two XF registers. XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} Rev.1.00 Dec. 13, 2005 Page 38 of 1286 REJ09B0158-0100 Section 2 Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPSCR.FR=0 FV0 DR0 DR2 FV4 DR4 DR6 FV8 DR8 DR10 FV12 DR12 DR14 XMTRX XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPSCR.FR=1 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 XD0 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FV0 DR2 DR4 FV4 DR6 DR8 FV8 DR10 DR12 FV12 DR14 Figure 2.4 Floating-Point Registers Rev.1.00 Dec. 13, 2005 Page 39 of 1286 REJ09B0158-0100 Section 2 Programming Model 2.2.4 Control Registers Status Register (SR): BIt: 31 30 29 28 MD RB BL 27 26 25 24 23 22 21 20 19 18 17 16 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 0 R S 0 R/W T 0 R/W Initial value: R/W: 0 R 1 R/W 1 R/W 1 R/W 0 R 0 R BIt: 15 14 13 12 11 10 9 8 0 R M 0 R/W Q 0 R/W FD Initial value: 0 R/W: R/W 0 R 0 R 0 R 0 R 1 R/W Bit Bit Name Initial Value R/W Description 31 — 0 R Reserved IMASK 1 1 R/W R/W 1 R/W 0 R For details on reading/writing this bit, see General Precautions on Handling of Product. 30 MD 1 R/W Processing Mode Selects the processing mode. 0: User mode (Some instructions cannot be executed and some resources cannot be accessed.) 1: Privileged mode This bit is set to 1 by an exception or interrupt. 29 RB 1 R/W Privileged Mode General Register Bank Specification Bit 0: R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC/STC instructions 1: R0_BANK1 to R7_BANK1 are accessed as general registers R0 to R7 and R0_BANK0–R7_BANK0 can be accessed using LDC/STC instructions This bit is set to 1 by an exception or interrupt. 28 BL 1 R/W Exception/Interrupt Block Bit This bit is set to 1 by a reset, an exception, or an interrupt. While this bit is set to 1, an interrupt request is masked. In this case, this processor enters the reset state when a general exception other than a user break occurs. Rev.1.00 Dec. 13, 2005 Page 40 of 1286 REJ09B0158-0100 Section 2 Programming Model Bit Bit Name 27 to 16 — Initial Value R/W Description All 0 R Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 15 FD 0 R/W FPU Disable Bit When this bit is set to 1 and an FPU instruction is not in a delay slot, a general FPU disable exception occurs. When this bit is set to 1 and an FPU instruction is in a delay slot, a slot FPU disable exception occurs. (FPU instructions: H'F*** instructions and LDS (.L)/STS(.L) instructions using FPUL/FPSCR) 14 to 10 — All 0 R Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 9 M 0 R/W M Bit Used by the DIV0S, DIV0U, and DIV1 instructions. 8 Q 0 R/W Q Bit 7 to 4 IMASK All 1 R/W Interrupt Mask Level Bits Used by the DIV0S, DIV0U, and DIV1 instructions. An interrupt whose priority is equal to or less than the value of the IMASK bits is masked. It can be chosen by CPU operation mode register (CPUOPM) whether the level of IMASK is changed to accept an interrupt or not when an interrupt is occurred. For details, see Appendix A, CPU Operation Mode Register (CPUOPM). 3, 2 — All 0 R Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 1 S 0 R/W S Bit Used by the MAC instruction. 0 T 0 R/W T Bit Indicates true/false condition, carry/borrow, or overflow/underflow. For details, see section 3, Instruction Set. Rev.1.00 Dec. 13, 2005 Page 41 of 1286 REJ09B0158-0100 Section 2 Programming Model Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined): The contents of SR are saved to SSR in the event of an exception or interrupt. Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC. Global Base Register (GBR) (32 bits, Initial Value = Undefined): GBR is referenced as the base address of addressing @(disp,GBR) and @(R0,GBR). Vector Base Register (VBR) (32 bits, Privileged Mode, Initial Value = H'00000000): VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exception Handling. Saved General Register 15 (SGR) (32 bits, Privileged Mode, Initial Value = Undefined): The contents of R15 are saved to SGR in the event of an exception or interrupt. Debug Base Register (DBR) (32 bits, Privileged Mode, Initial Value = Undefined): When the user break debugging function is enabled (CBCR.UBDE = 1), DBR is referenced as the branch destination address of the user break handler instead of VBR. 2.2.5 System Registers Multiply-and-Accumulate Registers (MACH and MACL) (32 bits, Initial Value = Undefined): MACH and MACL are used for the added value in a MAC instruction, and to store the operation result of a MAC or MUL instruction. Procedure Register (PR) (32 bits, Initial Value = Undefined): The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction. PR is referenced by the subroutine return instruction (RTS). Program Counter (PC) (32 bits, Initial Value = H'A0000000): PC indicates the address of the instruction currently being executed. Rev.1.00 Dec. 13, 2005 Page 42 of 1286 REJ09B0158-0100 Section 2 Programming Model Floating-Point Status/Control Register (FPSCR) BIt: 31 30 29 28 27 26 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R BIt: 15 14 13 12 11 10 Cause Initial value: R/W: Bit 0 R/W 0 R/W Bit Name 31 to 22 — 0 R/W 25 24 23 22 21 20 19 18 FR SZ PR DN 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R/W 9 8 7 6 5 Enable (EN) 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R Reserved 17 Flag 0 R/W 0 R/W 0 R/W 0 R/W 16 Cause RM 0 R/W 0 R/W 0 R/W 1 R/W For details on reading/writing this bit, see General Precautions on Handling of Product. 21 FR 0 R/W Floating-Point Register Bank 0: FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1: FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 20 SZ 0 R/W Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits) For relationship between the SZ bit, PR bit, and endian, see figure 2.5. 19 PR 0 R/W Precision Mode 0: Floating-point instructions are executed as single-precision operations 1: Floating-point instructions are executed as double-precision operations (graphics support instructions are undefined) For relationship between the SZ bit, PR bit, and endian, see figure 2.5 18 DN 1 R/W Denormalization Mode 0: Denormalized number is treated as such 1: Denormalized number is treated as zero Rev.1.00 Dec. 13, 2005 Page 43 of 1286 REJ09B0158-0100 Section 2 Programming Model Initial Value R/W Description All 0 R/W FPU Exception Cause Field 11 to 7 Enable (EN) All 0 R/W FPU Exception Enable Field 6 to 2 Flag R/W FPU Exception Flag Field Bit Bit Name 17 to 12 Cause All 0 Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. When an FPU exception occurs, the bits corresponding to FPU exception cause field and flag field are set to 1. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. For bit allocations of each field, see table 2.2. 1, 0 RM 01 R/W Rounding Mode These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved Rev.1.00 Dec. 13, 2005 Page 44 of 1286 REJ09B0158-0100 Section 2 Programming Model 63 0 Floating-point register DR (2i) 63 0 FR (2i) 63 FR (2i+1) 32 31 0 Memory area 8n 8n+3 8n+4 8n+7 63 0 Floating-point register 63 0 DR (2i) 0 *2 63 FR (2i+1) 63 0 DR (2i) *1, *2 63 FR (2i) 63 DR (2i) 32 31 0 FR (2i) 0 63 4m 8n+3 63 FR (2i+1) 32 31 0 FR (2i) 0 63 8n+4 8n+7 FR (2i+1) 32 31 0 8n+4 8n+3 8n Memory area 4n+3 4n 4m+3 (1) SZ = 0 8n 8n+7 (2) SZ = 1, PR = 0 (3) SZ = 1, PR = 1 Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used. 2. The bit-location of DR register is used for double precision format when PR = 1. (In the case of (2), it is used when PR is changed from 0 to 1.) Figure 2.5 Relationship between SZ bit and Endian Table 2.2 Bit Allocation for FPU Exception Handling Field Name FPU Error (E) Invalid Division Operation (V) by Zero (Z) Overflow Underflow Inexact (O) (U) (I) Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag None field Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Floating-Point Communication Register (FPUL) (32 bits, Initial Value = Undefined): Information is transferred between the FPU and CPU via FPUL. Rev.1.00 Dec. 13, 2005 Page 45 of 1286 REJ09B0158-0100 Section 2 Programming Model 2.3 Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. • H'1C00 0000 to H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding field of the TLB enables access to a memory-mapped register. The operation of an access to this area without using the address translation function of the MMU is not guaranteed. • H'FC00 0000 to H'FFFF FFFF Access to area H'FC00 0000 to H'FFFF FFFF in user mode will cause an address error. Memory-mapped registers can be referenced in user mode by means of access that involves address translation. Note: Do not access addresses to which registers are not mapped in either area. The operation of an access to an address with no register mapped is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Rev.1.00 Dec. 13, 2005 Page 46 of 1286 REJ09B0158-0100 Section 2 Programming Model 2.4 Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 7 6 0 S 31 S 7 6 S 15 14 0 0 S 31 S 15 14 S 0 Figure 2.6 Formats of Byte Data and Word Data in Register Rev.1.00 Dec. 13, 2005 Page 47 of 1286 REJ09B0158-0100 Section 2 Programming Model 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in an 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the external pin after a power-on reset. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.7. A 31 7 A+1 23 A+2 07 07 A + 11 A + 10 A + 9 A+3 15 7 0 31 07 0 7 0 15 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Word 0 31 Big endian 07 07 7 0 07 0 0 15 Word 1 0 A+8 15 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 Word 1 Longword 23 31 0 Word 0 Longword Little endian Figure 2.7 Data Formats in Memory For the 64-bit data format, see figure 2.5. Rev.1.00 Dec. 13, 2005 Page 48 of 1286 REJ09B0158-0100 0 Address A + 4 Address A Section 2 Programming Model 2.6 Processing States This LSI has major three processing states: the reset state, instruction execution state, and powerdown state. Reset State: In this state the CPU is reset. The reset state is divided into the power-on reset state and the manual reset. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and some registers of on-chip peripheral modules are initialized. For details, see register descriptions for each section. Instruction Execution State: In this state, the CPU executes program instructions in sequence. The Instruction execution state has the normal program execution state and the exception handling state. Power-Down State: In a power-down state, the CPU halts operation and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. This LSI supports sleep mode for the power-down state. From any state when reset/manual reset input Reset state Reset/manual reset clearance Instruction execution state Reset/manual Reset/manual reset input reset input Sleep instruction execution Interrupt occurence Power-down state Figure 2.8 Processing State Transitions Rev.1.00 Dec. 13, 2005 Page 49 of 1286 REJ09B0158-0100 Section 2 Programming Model 2.7 Usage Note 2.7.1 Notes on self-modified codes* This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the processing speed. Therefore if the instruction in the memory is modified and it is executed immediately, then the pre-modified code that is prefetched are likely to be executed. In order to execute the modified code definitely, one of the following sequences should be executed between the execution of modifying codes and modified codes. (1) In case the modified codes are in non-cacheable area SYNCO ICBI @Rn The target for the ICBI instruction can be any address within the range where no address error exception occurs. (2) In case the modified codes are in cacheable area (write-through) SYNCO ICBI @Rn The all instruction cache area corresponding to the modified codes should be invalidated by the ICBI instruction. The ICBI instruction should be issued to each cache line. One cache line is 32 bytes. (3) In case the modified codes are in cacheable area (copy-back) OCBP @Rm or OCBWB @Rm SYNCO ICBI @Rn The all operand cache area corresponding to the modified codes should be written back to the main memory by the OCBP or OCBWB instruction. Then the all instruction cache area corresponding to the modified codes should be invalidated by the ICBI instruction. The OCBP, OCBWB and ICBI instruction should be issued to each cache line. One cache line is 32 bytes. Note: * Processes executed while changing the instructions on the memory dynamically. Rev.1.00 Dec. 13, 2005 Page 50 of 1286 REJ09B0158-0100 Section 3 Instruction Set Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and from memory using longword size. When this LSI moves byte-size or word-size data from memory to a register, the data is sign-extended. 3.1 Execution Environment PC: At the start of instruction execution, the PC indicates the address of the instruction itself. Load-Store Architecture: This LSI has a load-store architecture in which operations are basically executed using registers. Except for bit-manipulation operations such as logical AND that are executed directly in memory, operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers. Delayed Branches: Except for the two branch instructions BF and BT, this LSI's branch instructions and RTE are delayed branches. In a delayed branch, the instruction following the branch is executed before the branch destination instruction. Delay Slot: This execution slot following a delayed branch is called a delay slot. For example, the BRA execution sequence is as follows: Table 3.1 Execution Order of Delayed Branch Instructions Instructions BRA ADD TARGET Execution Order (Delayed branch instruction) BRA (Delay slot) ↓ : ADD : TARGET target-inst ↓ (Branch destination instruction) target-inst A slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for which the branch is not taken is also a delay slot instruction. Rev.1.00 Dec. 13, 2005 Page 51 of 1286 REJ09B0158-0100 Section 3 Instruction Set T Bit: The T bit in SR is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below. ADD #1, R0 CMP/EQ R1, R0 BT TARGET ; T bit is not changed by ADD operation ; If R0 = R1, T bit is set to 1 ; Branches to TARGET if T bit = 1 (R0 = R1) In an RTE delay slot, the SR bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution. The STC and STC.L SR instructions access all SR bits after modification. Constant Values: An 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a PC-relative load instruction. MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn There are no PC-relative load instructions for floating-point operations. However, it is possible to set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point register. Rev.1.00 Dec. 13, 2005 Page 52 of 1286 REJ09B0158-0100 Section 3 Instruction Set 3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID. For details, see section 7, Memory Management Unit (MMU). Table 3.2 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Address Calculation Method Register direct Rn Effective address is register Rn. (Operand is register Rn contents.) — Register indirect @Rn Effective address is register Rn contents. Rn → EA (EA: effective address) Register indirect with postincrement @Rn+ Rn Rn Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn + 1/2/4/8 Rn + @–Rn Rn 1/2/4/8 Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Quadword: Rn + 8 → Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn – 1/2/4/8 Rn → EA After instruction execution Longword: Rn + 4 → Rn 1/2/4/8 Register indirect with predecrement Calculation Formula – Rn – 1/2/4/8 Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn Quadword: Rn – 8 → Rn Rn → EA (Instruction executed with Rn after calculation) Rev.1.00 Dec. 13, 2005 Page 53 of 1286 REJ09B0158-0100 Section 3 Instruction Set Addressing Mode Instruction Format Register @(disp:4, Rn) indirect with displacement Effective Address Calculation Method Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) Rn + disp × 1/2/4 + Calculation Formula Byte: Rn + disp → EA Word: Rn + disp × 2 → EA Longword: Rn + disp × 4 → EA × 1/2/4 Indexed register indirect @(R0, Rn) Effective address is sum of register Rn and R0 contents. Rn + R0 → EA Rn + Rn + R0 R0 GBR indirect @(disp:8, GBR) Effective address is register GBR contents with with displace8-bit displacement disp added. After disp is ment zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) + GBR + disp × 1/2/4 Byte: GBR + disp → EA Word: GBR + disp × 2 → EA Longword: GBR + disp × 4 → EA × 1/2/4 Indexed GBR @(R0, GBR) indirect Effective address is sum of register GBR and R0 GBR + R0 → EA contents. GBR + R0 Rev.1.00 Dec. 13, 2005 Page 54 of 1286 REJ09B0158-0100 GBR + R0 Section 3 Instruction Set Addressing Mode Instruction Format Calculation Formula Effective Address Calculation Method PC-relative @(disp:8, PC) Effective address is PC + 4 with 8-bit displacement with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. Word: PC + 4 + disp × 2 → EA Longword: PC & H'FFFF FFFC + 4 + disp × 4 → EA PC & * + H'FFFF FFFC 4 + disp (zero-extended) PC + 4 + disp ×2 or PC & H'FFFF FFFC + 4 + disp × 4 × 2/4 PC-relative disp:8 * With longword operand Effective address is PC + 4 with 8-bit displacement PC + 4 + disp × 2 → Branchdisp added after being sign-extended and Target multiplied by 2. PC + 4 + PC + 4 + disp × 2 disp (sign-extended) × 2 Rev.1.00 Dec. 13, 2005 Page 55 of 1286 REJ09B0158-0100 Section 3 Instruction Set Addressing Instruction Mode Format PC-relative disp:12 Effective Address Calculation Method Calculation Formula Effective address is PC + 4 with 12-bit PC + 4 + disp displacement disp added after being sign-extended × 2 → Branchand Target multiplied by 2. PC + 4 + PC + 4 + disp × 2 disp (sign-extended) × 2 Rn Effective address is sum of PC + 4 and Rn. PC PC + 4 + Rn → Branch-Target + 4 + PC + 4 + Rn Rn Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. — #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. — #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. — Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the operand size. This is done to clarify the operation of the LSI. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative Rev.1.00 Dec. 13, 2005 Page 56 of 1286 REJ09B0158-0100 Section 3 Instruction Set 3.3 Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Description Instruction mnemonic OP.Sz SRC, DEST OP: Sz: SRC: DEST: Rm: Rn: imm: disp: →, ← (xx) M/Q/T & | Operation notation Instruction code Operation code Size Source operand Source and/or destination operand Source register Destination register Immediate data Displacement Transfer direction Memory operand SR flag bits Logical AND of individual bits Logical OR of individual bits ∧ Logical exclusive-OR of individual bits ~ Logical NOT of individual bits n n-bit shift MSB ↔ LSB mmmm: nnnn: 0000: 0001: : 1111: mmm: nnn: 000: 001: : 111: mm: nn: 00: 01: 10: 11: iiii: dddd: Register number (Rm, FRm) Register number (Rn, FRn) R0, FR0 R1, FR1 R15, FR15 Register number (DRm, XDm, Rm_BANK) Register number (DRn, XDn, Rn_BANK) DR0, XD0, R0_BANK DR2, XD2, R1_BANK DR14, XD14, R7_BANK Register number (FVm) Register number (FVn) FV0 FV4 FV8 FV12 Immediate data Displacement Rev.1.00 Dec. 13, 2005 Page 57 of 1286 REJ09B0158-0100 Section 3 Instruction Set Item Format Privileged mode Description "Privileged" means the instruction can only be executed in privileged mode. T bit Value of T bit after —: No change instruction execution New  "New" means the instruction which is newly added in this LSI. Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand. Rev.1.00 Dec. 13, 2005 Page 58 of 1286 REJ09B0158-0100 Section 3 Instruction Set Table 3.4 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit New MOV #imm,Rn imm → sign extension → Rn 1110nnnniiiiiiii — — — MOV.W @(disp*,PC),Rn (disp × 2 + PC + 4) → sign extension → Rn 1001nnnndddddddd — — — MOV.L @(disp*,PC),Rn (disp × 4 + PC & H'FFFF FFFC 1101nnnndddddddd + 4) → Rn — — — MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 — — — MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 — — — MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 — — — MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 — — — MOV.B @Rm,Rn (Rm) → sign extension → Rn 0110nnnnmmmm0000 — — — MOV.W @Rm,Rn (Rm) → sign extension → Rn 0110nnnnmmmm0001 — — — MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 — — — MOV.B Rm,@-Rn Rn-1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 — — — MOV.W Rm,@-Rn Rn-2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 — — — MOV.L Rm,@-Rn Rn-4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 — — — MOV.B @Rm+,Rn (Rm)→ sign extension → Rn, Rm + 1 → Rm 0110nnnnmmmm0100 — — — MOV.W @Rm+,Rn (Rm) → sign extension → Rn, Rm + 2 → Rm 0110nnnnmmmm0101 — — — MOV.L @Rm+,Rn (Rm) → Rn, Rm + 4 → Rm 0110nnnnmmmm0110 — — — MOV.B R0,@(disp*,Rn) R0 → (disp + Rn) 10000000nnnndddd — — — MOV.W R0,@(disp*,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd — — — MOV.L Rm,@(disp*,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd — — — MOV.B @(disp*,Rm),R0 (disp + Rm) → sign extension → R0 10000100mmmmdddd — — — MOV.W @(disp*,Rm),R0 (disp × 2 + Rm) → sign extension → R0 10000101mmmmdddd — — — MOV.L @(disp*,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd — — — MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 — — — MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 — — — MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 — — — MOV.B @(R0,Rm),Rn (R0 + Rm) → sign extension → Rn 0000nnnnmmmm1100 — — — Rev.1.00 Dec. 13, 2005 Page 59 of 1286 REJ09B0158-0100 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit New MOV.W @(R0,Rm),Rn (R0 + Rm) → sign extension → Rn 0000nnnnmmmm1101 — — — MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 — — — MOV.B R0,@(disp*,GBR) R0 → (disp + GBR) 11000000dddddddd — — — MOV.W R0,@(disp*,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd — — — MOV.L R0,@(disp*,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd — — — MOV.B @(disp*,GBR),R0 (disp + GBR) → sign extension → R0 11000100dddddddd — — — MOV.W @(disp*,GBR),R0 (disp × 2 + GBR) → sign extension → R0 11000101dddddddd — — — MOV.L @(disp*,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd — — — MOVA @(disp*,PC),R0 disp × 4 + PC & H'FFFF FFFC + 4 → R0 11000111dddddddd — — — MOVCO.L R0,@Rn LDST → T If (T == 1) R0 → (Rn) 0 → LDST 0000nnnn01110011  LDST New MOVLI.L 1 → LDST (Rm) → R0 When interrupt/exception occurred 0 → LDST 0000mmmm01100011   New MOVUA.L @Rm,R0 0100mmmm10101001 (Rm) → R0 Load non-boundary alignment data   New MOVUA.L @Rm+,R0 (Rm) → R0, Rm + 4 → Rm 0100mmmm11101001 Load non-boundary alignment data   New MOVT Rn T → Rn 0000nnnn00101001 — — — SWAP.B Rm,Rn Rm → swap lower 2 bytes → Rn 0110nnnnmmmm1000 — — — SWAP.W Rm,Rn Rm → swap upper/lower words → Rn 0110nnnnmmmm1001 — — — XTRCT Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101 — — — Note: @Rm,R0 Rm,Rn * The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the displacement (disp). Rev.1.00 Dec. 13, 2005 Page 60 of 1286 REJ09B0158-0100 Section 3 Instruction Set Table 3.5 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit New ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 — — — ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii — — — ADDC Rm,Rn Rn + Rm + T → Rn, carry → T 0011nnnnmmmm1110 — Carry — ADDV Rm,Rn Rn + Rm → Rn, overflow → T 0011nnnnmmmm1111 — Overflow — CMP/EQ #imm,R0 When R0 = imm, 1 → T Otherwise, 0 → T 10001000iiiiiiii — Comparison — result CMP/EQ Rm,Rn When Rn = Rm, 1 → T Otherwise, 0 → T 0011nnnnmmmm0000 — Comparison — result CMP/HS Rm,Rn When Rn ≥ Rm (unsigned), 1→T Otherwise, 0 → T 0011nnnnmmmm0010 — Comparison — result CMP/GE Rm,Rn When Rn ≥ Rm (signed), 1→T Otherwise, 0 → T 0011nnnnmmmm0011 — Comparison — result CMP/HI Rm,Rn When Rn > Rm (unsigned), 1→T Otherwise, 0 → T 0011nnnnmmmm0110 — Comparison — result CMP/GT Rm,Rn When Rn > Rm (signed), 1→T Otherwise, 0 → T 0011nnnnmmmm0111 — Comparison — result CMP/PZ Rn When Rn ≥ 0, 1 → T Otherwise, 0 → T 0100nnnn00010001 — Comparison — result CMP/PL Rn When Rn > 0, 1 → T Otherwise, 0 → T 0100nnnn00010101 — Comparison — result CMP/STR Rm,Rn When any bytes are equal, 1→T Otherwise, 0 → T 0010nnnnmmmm1100 — Comparison — result DIV1 Rm,Rn 1-step division (Rn ÷ Rm) 0011nnnnmmmm0100 — Calculation result — DIV0S Rm,Rn MSB of Rn → Q, MSB of Rm → M, M^Q → T 0010nnnnmmmm0111 — Calculation result — DIV0U 0 → M/Q/T 0000000000011001 — 0 — DMULS.L Rm,Rn Signed, Rn × Rm → MAC, 32 × 32 → 64 bits 0011nnnnmmmm1101 — — — Rev.1.00 Dec. 13, 2005 Page 61 of 1286 REJ09B0158-0100 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit New DMULU.L Rm,Rn Unsigned, Rn × Rm → MAC, 32 × 32 → 64 bits 0011nnnnmmmm0101 — — — DT Rn Rn – 1 → Rn; when Rn = 0, 1→T When Rn ≠ 0, 0 → T 0100nnnn00010000 — Comparison — result EXTS.B Rm,Rn Rm sign-extended from byte → Rn 0110nnnnmmmm1110 — — — EXTS.W Rm,Rn Rm sign-extended from word → Rn 0110nnnnmmmm1111 — — — EXTU.B Rm,Rn Rm zero-extended from byte → Rn 0110nnnnmmmm1100 — — — EXTU.W Rm,Rn Rm zero-extended from word → Rn 0110nnnnmmmm1101 — — — 0000nnnnmmmm1111 — — — 0100nnnnmmmm1111 — — — MAC.L @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 4 → Rn, Rm + 4 → Rm 32 × 32 + 64 → 64 bits MAC.W @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 2 → Rn, Rm + 2 → Rm 16 × 16 + 64 → 64 bits Rm,Rn Rn × Rm → MACL 32 × 32 → 32 bits 0000nnnnmmmm0111 — — — MULS.W Rm,Rn Signed, Rn × Rm → MACL 16 × 16 → 32 bits 0010nnnnmmmm1111 — — — MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0010nnnnmmmm1110 — — — NEG Rm,Rn 0 – Rm → Rn 0110nnnnmmmm1011 — — — NEGC Rm,Rn 0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010 — Borrow — SUB Rm,Rn Rn – Rm → Rn 0011nnnnmmmm1000 — — — SUBC Rm,Rn Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010 — Borrow — SUBV Rm,Rn Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 — Underflow — MUL.L Rev.1.00 Dec. 13, 2005 Page 62 of 1286 REJ09B0158-0100 Section 3 Instruction Set Table 3.6 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit New AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 — — — AND #imm,R0 R0 & imm → R0 11001001iiiiiiii — — — 11001101iiiiiiii — — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + GBR) NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 — — — OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 — — — OR #imm,R0 R0 | imm → R0 11001011iiiiiiii — — — OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → (R0 + GBR) 11001111iiiiiiii — — — TAS.B @Rn When (Rn) = 0, 1 → T Otherwise, 0 → T In both cases, 1 → MSB of (Rn) 0100nnnn00011011 — Test result — TST Rm,Rn Rn & Rm; when result = 0, 1 → T Otherwise, 0 → T 0010nnnnmmmm1000 — Test result — TST #imm,R0 R0 & imm; when result = 0, 1 → T Otherwise, 0 → T 11001000iiiiiiii — Test result — TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; when result = 0, 1 → T Otherwise, 0 → T 11001100iiiiiiii — Test result — XOR Rm,Rn Rn ∧ Rm → Rn 0010nnnnmmmm1010 — — — XOR #imm,R0 R0 ∧ imm → R0 11001010iiiiiiii — — — 11001110iiiiiiii — — — XOR.B #imm,@(R0,GBR) (R0 + GBR) ∧ imm → (R0 + GBR) Rev.1.00 Dec. 13, 2005 Page 63 of 1286 REJ09B0158-0100 Section 3 Instruction Set Table 3.7 Shift Instructions Instruction Operation Instruction Code ROTL Rn T ← Rn ← MSB 0100nnnn00000100 — MSB — ROTR Rn LSB → Rn → T 0100nnnn00000101 — LSB — ROTCL Rn T ← Rn ← T 0100nnnn00100100 — MSB — ROTCR Rn T → Rn → T 0100nnnn00100101 — LSB — SHAD Rm,Rn When Rm ≥ 0, Rn > Rm → [MSB → Rn] — — SHAL Rn T ← Rn ← 0 0100nnnn00100000 — MSB — SHAR Rn MSB → Rn → T 0100nnnn00100001 — LSB — SHLD Rm,Rn When Rm ≥ 0, Rn > Rm → [0 → Rn] — — SHLL Rn T ← Rn ← 0 0100nnnn00000000 — MSB — SHLR Rn 0 → Rn → T 0100nnnn00000001 — LSB — SHLL2 Rn Rn > 2 → Rn 0100nnnn00001001 — — — SHLL8 Rn Rn > 8 → Rn 0100nnnn00011001 — — — SHLL16 Rn Rn > 16 → Rn 0100nnnn00101001 — — — Rev.1.00 Dec. 13, 2005 Page 64 of 1286 REJ09B0158-0100 Privileged T Bit New Section 3 Instruction Set Table 3.8 Branch Instructions Instruction Operation Instruction Code Privileged T Bit New BF label When T = 0, disp × 2 + PC + 4 → PC When T = 1, nop 10001011dddddddd — — — BF/S label Delayed branch; when T = 0, disp × 2 + PC + 4 → PC When T = 1, nop 10001111dddddddd — — — BT label When T = 1, disp × 2 + PC + 4 → PC When T = 0, nop 10001001dddddddd — — — BT/S label Delayed branch; when T = 1, disp × 2 + PC + 4 → PC When T = 0, nop 10001101dddddddd — — — BRA label Delayed branch, disp × 2 + PC + 4 → PC 1010dddddddddddd — — — BRAF Rn Delayed branch, Rn + PC + 4 → 0000nnnn00100011 — PC — — BSR label Delayed branch, PC + 4 → PR, 1011dddddddddddd — disp × 2 + PC + 4 → PC — — BSRF Rn Delayed branch, PC + 4 → PR, 0000nnnn00000011 — Rn + PC + 4 → PC — — JMP @Rn Delayed branch, Rn → PC 0100nnnn00101011 — — — JSR @Rn Delayed branch, PC + 4 → PR, 0100nnnn00001011 — Rn → PC — — Delayed branch, PR → PC — — RTS 0000000000001011 — Rev.1.00 Dec. 13, 2005 Page 65 of 1286 REJ09B0158-0100 Section 3 Instruction Set Table 3.9 System Control Instructions Instruction Operation Instruction Code Privileged T Bit New CLRMAC 0 → MACH, MACL 0000000000101000 — — CLRS 0→S 0000000001001000 — — — CLRT 0→T 0000000000001000 — 0 —  New — ICBI @Rn Invalidates instruction cache block indicated by virtual address 0000nnnn11100011  LDC Rm,SR Rm → SR 0100mmmm00001110 Privileged LSB — LDC Rm,GBR Rm → GBR 0100mmmm00011110 — — LDC Rm,VBR Rm → VBR 0100mmmm00101110 Privileged — — LDC Rm,SGR Rm → SGR 0100mmmm00111010 Privileged — New LDC Rm,SSR Rm → SSR 0100mmmm00111110 Privileged — — LDC Rm,SPC Rm → SPC 0100mmmm01001110 Privileged — — LDC Rm,DBR Rm → DBR 0100mmmm11111010 Privileged — — — LDC Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged — — LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 Privileged LSB — LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 — — — LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 Privileged — — LDC.L @Rm+,SGR (Rm) → SGR, Rm + 4 → Rm 0100mmmm00110110 Privileged — New LDC.L @Rm+,SSR (Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111 Privileged — — LDC.L @Rm+,SPC (Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111 Privileged — — LDC.L @Rm+,DBR (Rm) → DBR, Rm + 4 → Rm 0100mmmm11110110 Privileged — — LDC.L @Rm+,Rn_BANK (Rm) → Rn_BANK, Rm + 4 → Rm 0100mmmm1nnn0111 Privileged — — LDS Rm,MACH Rm → MACH 0100mmmm00001010 — — — LDS Rm,MACL Rm → MACL 0100mmmm00011010 — — — LDS Rm,PR Rm → PR 0100mmmm00101010 — — — LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 — — — LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 — — — LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 — — — LDTLB PTEH/PTEL → TLB 0000000000111000 Privileged — — MOVCA.L R0,@Rn R0 → (Rn) (without fetching cache block) 0000nnnn11000011 — — Rev.1.00 Dec. 13, 2005 Page 66 of 1286 REJ09B0158-0100 — Section 3 Instruction Set Instruction NOP Operation Instruction Code Privileged T Bit New No operation 0000000000001001 — — — OCBI @Rn Invalidates operand cache block 0000nnnn10010011 — — — OCBP @Rn Writes back and invalidates operand cache block 0000nnnn10100011 — — — OCBWB @Rn Writes back operand cache block 0000nnnn10110011 — — — PREF @Rn (Rn) → operand cache 0000nnnn10000011 — — — PREFI @Rn Reads 32-byte instruction block into instruction cache 0000nnnn11010011   New Delayed branch, SSR/SPC → 0000000000101011 Privileged SR/PC — — SETS 1→S 0000000001011000 — — — SETT 1→T 0000000000011000 — 1 — RTE SLEEP Sleep 0000000000011011 Privileged — — STC SR,Rn SR → Rn 0000nnnn00000010 Privileged — — STC GBR,Rn GBR → Rn 0000nnnn00010010 — — — STC VBR,Rn VBR → Rn 0000nnnn00100010 Privileged — — STC SSR,Rn SSR → Rn 0000nnnn00110010 Privileged — — STC SPC,Rn SPC → Rn 0000nnnn01000010 Privileged — — STC SGR,Rn SGR → Rn 0000nnnn00111010 Privileged — — STC DBR,Rn DBR → Rn 0000nnnn11111010 Privileged — — STC Rm_BANK,Rn Rm_BANK → Rn (m = 0 to 7) 0000nnnn1mmm0010 Privileged — — STC.L SR,@-Rn Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011 Privileged — — STC.L GBR,@-Rn Rn – 4 → Rn, GBR → (Rn) 0100nnnn00010011 — — — STC.L VBR,@-Rn Rn – 4 → Rn, VBR → (Rn) 0100nnnn00100011 Privileged — — STC.L SSR,@-Rn Rn – 4 → Rn, SSR → (Rn) 0100nnnn00110011 Privileged — — STC.L SPC,@-Rn Rn – 4 → Rn, SPC → (Rn) 0100nnnn01000011 Privileged — — STC.L SGR,@-Rn Rn – 4 → Rn, SGR → (Rn) 0100nnnn00110010 Privileged — — STC.L DBR,@-Rn Rn – 4 → Rn, DBR → (Rn) 0100nnnn11110010 Privileged — — STC.L Rm_BANK,@-Rn Rn – 4 → Rn, Rm_BANK → (Rn) (m = 0 to 7) 0100nnnn1mmm0011 Privileged — — STS MACH,Rn MACH → Rn 0000nnnn00001010 — — — STS MACL,Rn MACL → Rn 0000nnnn00011010 — — — Rev.1.00 Dec. 13, 2005 Page 67 of 1286 REJ09B0158-0100 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit New STS PR,Rn PR → Rn 0000nnnn00101010 — — — STS.L MACH,@-Rn Rn – 4 → Rn, MACH → (Rn) 0100nnnn00000010 — — — STS.L MACL,@-Rn Rn – 4 → Rn, MACL → (Rn) 0100nnnn00010010 — — — STS.L PR,@-Rn Rn – 4 → Rn, PR → (Rn) 0100nnnn00100010 — — — SYNCO Prevents the next instruction 0000000010101011 from being issued until instructions issued before this instruction have been completed.   New TRAPA #imm PC + 2 → SPC, SR → SSR, #imm