R8C-2G

R8C/2G Group RENESAS MCU REJ03B0223-0100 Rev.1.00 Apr 04, 2008 1. 1.1 Overview Features The R8C/2G Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs also use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. 1.1.1 Applications Electric power meters, electronic household appliances, office equipment, audio equipment, consumer equipment, etc. 1.1.2 Specifications Table 1.1 outlines the Specifications for R8C/2G Group. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 1 of 41 R8C/2G Group 1. Overview Table 1.1 Item CPU Specifications for R8C/2G Group Function Central processing unit Specification R8C/Tiny series core • Number of fundamental instructions: 89 • Minimum instruction execution time: 125 ns (System clock = 8 MHz, VCC = 2.7 to 5.5 V) 250 ns (System clock = 4 MHz, VCC = 2.2 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.2 Product List for R8C/2G Group. • Power-on reset • Voltage detection 3 • • • • • 2 circuits (shared with voltage monitor 1 and voltage monitor 2) External reference voltage input is available Output-only: 1 CMOS I/O ports: 27, selectable pull-up resistor 2 circuits: On-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function), XCIN clock oscillation circuit (32 kHz) • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Real-time clock (timer RE) • External: 5 sources, Internal: 17 sources, Software: 4 sources • Priority levels: 7 levels 15 bits × 1 (with prescaler), reset start selectable 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 8 bits × 1 Real-time clock mode (count seconds, minutes, hours, days of week), output compare mode 16 bits × 1 (with capture/compare register pin and compare register pin) Input capture mode, output compare mode Clock synchronous serial I/O/UART × 2 Hardware LIN: 1 (timer RA, UART0) • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 100 times • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function System clock = 8 MHz (VCC = 2.7 to 5.5 V) System clock = 4 MHz (VCC = 2.2 to 5.5 V) 5 mA (VCC = 5 V, system clock = 8 MHz) 23 µA (VCC = 3 V, wait mode (low-speed on-chip oscillator on)) 0.7 µA (VCC = 3 V, stop mode, BGR trimming circuit disabled) -20 to 85°C (N version) -40 to 85°C (D version)(1) 32-pin LQFP Package code: PLQP0032GB-A (previous code: 32P6U-A) Memory ROM, RAM Power Supply Voltage detection Voltage circuit Detection Comparator I/O Ports Clock Clock generation circuits Interrupts Watchdog Timer Timer Timer RA Timer RB Timer RE Timer RF Serial UART0, UART2 Interface LIN Module Flash Memory Operating Frequency/Supply Voltage Current consumption Operating Ambient Temperature Package NOTE: 1. Specify the D version if D version functions are to be used. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 2 of 41 R8C/2G Group 1. Overview 1.2 Product List Table 1.2 lists Product List for R8C/2G Group, Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/2G Group. Table 1.2 Product List for R8C/2G Group ROM Capacity 16 Kbytes 24 Kbytes 32 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes RAM Capacity 512 bytes 1 Kbytes 1 Kbytes 512 bytes 1 Kbytes 1 Kbytes Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A Current of Apr. 2008 Remarks N version Part No. R5F212G4SNFP R5F212G5SNFP R5F212G6SNFP R5F212G4SDFP R5F212G5SDFP R5F212G6SDFP D version Part No. R 5 F 21 2G 4 S N FP Package type: FP: PLQP0032GB-A Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C S: Low-voltage version (other no symbols) ROM capacity 4: 16 KB 5: 24 KB 6: 32 KB R8C/2G Group R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductor Figure 1.1 Part Number, Memory Size, and Package of R8C/2G Group Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 3 of 41 R8C/2G Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a Block Diagram. 4 8 8 2 1 5 I/O ports Port P0 Port P1 Port P3 Port P4 Port P6 Peripheral functions UART or clock synchronous serial I/O (8 bits × 2 channels) System clock generation circuit High-speed on-chip oscillator Low-Speed on-chip oscillator XCIN-XCOUT Timers Timer RA (8 bits) Timer RB (8 bits) Timer RE (8 bits) Timer RF (16 bits) LIN module (1 channel) Voltage detection circuit (3 circuits) Comparator (2 circuits) Watchdog timer (15 bits) R8C/Tiny Series CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) RAM(2) Multiplier NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. Figure 1.2 Block Diagram Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 4 of 41 R8C/2G Group 1. Overview 1.4 Pin Assignment Figure 1.3 shows Pin Assignment (Top View). Table 1.3 outlines the Pin Name Information by Pin Number. P1_3/KI3/VCOUT1/(TRBO)(1) P1_0/KI0/TRFO00/VCMP1 P1_1/KI1/TRFO01/VCMP2 P6_5/CLK2/(TREO) (1) P1_2/KI2/TRFO02/CVREF P3_4/TRFO11 P3_3/TRFO10/TRFI 24 23 22 21 20 19 18 17 P1_4/TXD0 P0_7/(Kl0)(1) P0_6/INT4 P0_5 P0_4/(TREO)(1) P6_3/TXD2 P6_0/TREO P6_6/(Kl1)(1) P6_4/RXD2 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 R8C/2G Group PLQP0032GB-A (32P6U-A) (top view) 14 13 12 11 10 9 P1_5/RXD0/(TRAIO)/(INT1)(1) P1_6/CLK0/VCOUT2 P3_2/INT2 P3_0/TRAO P3_1/TRBO P3_6/(INT1)(1) P1_7/TRAIO/INT1 P4_5/INT0 P3_5/TRFO12 P3_7/(TRAO)/(TRFO11)(1) RESET XCOUT/(P4_4)(1) VSS XCIN/(P4_3)(1) NOTES: 1. Can be assigned to the pin in parentheses by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.3 Pin Assignment (Top View) Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 5 of 41 MODE VCC R8C/2G Group 1. Overview Table 1.3 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name Information by Pin Number Control Pin Port P3_5 P3_7 RESET XCOUT VSS XCIN VCC MODE P4_5 P1_7 P3_6 P3_1 P3_0 P3_2 P1_6 P1_5 P1_4 P1_3 P1_2 P6_5 P1_1 P1_0 P3_3 P3_4 P0_7 P0_6 P0_5 P0_4 P6_3 P6_0 P6_6 P6_4 (Kl1)(1) RXD2 TREO (TREO)(1) TXD2 (Kl0)(1) INT4 KI1 KI0 KI3 KI2 (TRBO)(1) TRFO02 (TREO)(1) TRFO01 TRFO00 TRFO10/TRFI TRFO11 CLK2 VCMP2 VCMP1 (INT1)(1) (TRAIO)(1) INT2 CLK0 RXD0 TXD0 VCOUT1 CVREF VCOUT2 INT0 INT1 (INT1)(1) TRBO TRAO TRAIO (P4_3) (P4_4) I/O Pin Functions for of Peripheral Modules Interrupt Timer TRFO12 (TRAO)/(TRFO11)(1) Serial Interface Comparator NOTE: 1. Can be assigned to the pin in parentheses by a program. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 6 of 41 R8C/2G Group 1. Overview 1.5 Pin Functions Table 1.4 lists Pin Functions. Table 1.4 Type Power supply input Reset input MODE XCIN clock input XCIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RE Timer RF Pin Functions Symbol VCC, VSS RESET MODE XCIN XCOUT INT0 to INT2, INT4 KI0 to KI3 TRAIO TRAO TRBO TREO TRFI TRFO00 to TRFO02, TRFO10 to TRFO12 I/O Type Description Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Input “L” on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins.(1) To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin Divided clock output pin Timer RF input pin Timer RF output pins Clock I/O pin Serial data input pin Serial data output pin Analog input pins to comparator Reference voltage input pin to comparator Comparator output pins CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. Output-only port – I I I O I I I/O O O O I O I/O I O I I O I/O Serial interface CLK0, CLK2 RXD0, RXD2 TXD0, TXD2 Comparator VCMP1, VCMP2 CVREF VCOUT1, VCOUT2 I/O port P0_4 to P0_7, P1_0 to P1_7, P3_0 to P3_7, P4_3, P4_5, P6_0, P6_3 to P6_6 P4_4 Output port O I: Input O: Output I/O: Input and output NOTE: 1. Refer to the oscillator manufacturer for oscillation characteristics. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 7 of 41 R8C/2G Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 b8b7 b0 R2 R3 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1) R2 R3 A0 A1 FB b19 b15 b0 Address registers(1) Frame base register(1) INTBH INTBL Interrupt table register The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OBSZDC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 8 of 41 R8C/2G Group 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 9 of 41 R8C/2G Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 10 of 41 R8C/2G Group 3. Memory 3. Memory Figure 3.1 is a Memory Map of R8C/2G Group. The R8C/2G group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h SFR (Refer to 4. Special Function Registers (SFRs)) 002FFh 00400h Internal RAM 0XXXh 0FFDCh 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer/voltage monitor/comparator (Reserved) (Reserved) Reset FFFFFh NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F212G4SNFP, R5F212G4SDFP R5F212G5SNFP, R5F212G5SDFP R5F212G6SNFP, R5F212G6SDFP Size 16 Kbytes 24 Kbytes 32 Kbytes Address 0YYYYh 0C000h 0A000h 08000h Size 512 bytes 1 Kbyte 1 Kbyte Internal RAM Address 0XXXXh 005FFh 007FFh 007FFh Figure 3.1 Memory Map of R8C/2G Group Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 11 of 41 R8C/2G Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh SFR Information (1)(1) Register Symbol After reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 00h 00h 01011000b 00h Protect Register System Clock Select Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 PRCR OCD WDTR WDTS WDC RMAD0 00h 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 Count Source Protection Mode Register CSPR 00h 10000000b(2) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 HRA0 HRA1 HRA2 00h When Shipping 00h Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 6 CPSRF FRA4 FRA6 00h When Shipping When Shipping BGR Trimming Auxiliary Register A BGR Trimming Auxiliary Register B BGRTRMA BGRTRMB When Shipping When Shipping X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The CSPROINI bit in the OFS register is set to 0. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 12 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.2 Address 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh SFR Information (2)(1) Register Voltage Detection Register 1(2) Voltage Detection Register 2(2) VCA1 VCA2 Symbol After reset 00001000b 00h(3) 00100000b(4) Voltage Monitor 1 Circuit Control Register(5) Voltage Monitor 2 Circuit Control Register(5) Voltage Monitor 0 Circuit Control Register(2) VW1C VW2C VW0C 00001010b 00000010b 1000X010b(3) 1100X011b(4) Voltage Detection Circuit External Input Control Register Comparator Mode Register Voltage Monitor Circuit Edge Select Register BGR Control Register BGR Trimming Register Comparator 1 Interrupt Control Register Comparator 2 Interrupt Control Register VCAB ALCMR VCAC BGRCR BGRTRM VCMP1IC VCMP2IC 00h 00h 00h 00h When Shipping XXXXX000b XXXXX000b Timer RE Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register Key Input Interrupt Control Register TREIC S2TIC S2RIC KUPIC XXXXX000b XXXXX000b XXXXX000b XXXXX000b Compare 1 Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register CMP1IC S0TIC S0RIC XXXXX000b XXXXX000b XXXXX000b INT2 Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register Timer RF Interrupt Control Register Compare 0 Interrupt Control Register INT0 Interrupt Control Register INT4 Interrupt Control Register Capture Interrupt Control Register INT2IC TRAIC TRBIC INT1IC TRFIC CMP0IC INT0IC INT4IC CAPIC XX00X000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1 and hardware reset. 4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset. 5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 13 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.3 Address 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh SFR Information (3)(1) Register Symbol After reset UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0MR U0BRG U0TB U0C0 U0C1 U0RB 00h XXh XXh XXh 00001000b 00000010b XXh XXh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 14 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.4 Address 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh SFR Information (4)(1) Register Symbol After reset Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P4 Direction Register Port P6 Register Port P6 Direction Register P0 P1 PD0 PD1 P3 PD3 P4 PD4 P6 PD6 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 15 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.5 Address 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh SFR Information (5)(1) Register Symbol After reset Pin Select Register 2 Pin Select Register 3 Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 00h 00h 00h 00h 00h 00h 00h 00h Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h FFh FFh FFh Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register Timer RE Real-Time Clock Precision Adjust Register TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TREOPR XXh XXh X0XXXXXXb X0000XXXb XXX0X0X0b 00XXXXXXb 00001000b 00h X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 16 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.6 Address 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh SFR Information (6)(1) Register Symbol After reset UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register U2MR U2BRG U2TB U2C0 U2C1 U2RB 00h XXh XXh XXh 00001000b 00000010b XXh XXh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 17 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.7 Address 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh SFR Information (7)(1) Register Symbol After reset X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 18 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.8 Address 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh SFR Information (8)(1) Register Symbol After reset Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0 FMR4 FMR1 FMR0 01000000b 1000000Xb 00000001b X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 19 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.9 Address 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh SFR Information (9)(1) Register Symbol After reset X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 20 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.10 Address 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh SFR Information (10)(1) Register Symbol After reset X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 21 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.11 Address 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh SFR Information (11)(1) Register Symbol After reset Timer RF Register TRF 00h 00h Timer RF Control Register 2 Timer RF Control Register 0 Timer RF Control Register 1 Capture and Compare 0 Register Compare 1 Register TRFCR2 TRFCR0 TRFCR1 TRFM0 TRFM1 00h 00h 00h 0000h(2) FFFFh(3) FFh FFh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. After input capture mode. 3. After output compare mode. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 22 of 41 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.12 Address 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh FFFFh SFR Information (12)(1) Register Symbol After reset Pin Select Register 4 External Input Enable Register 2 INT Input Filter Select Register 2 Timer RF Output Control Register Option Function Select Register PINSR4 INTEN2 INTF2 TRFOUT OFS 00h 00h 00h 00h (Note 2) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 23 of 41 R8C/2G Group 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Symbol VCC VI VO Pd Topr Tstg Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr = 25°C Absolute Maximum Ratings Parameter Condition Rated Value −0.3 to 6.5 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 500 −20 to 85 (N version) / −40 to 85 (D version) −65 to 150 Unit V V V mW °C °C Table 5.2 Symbol VCC VSS VIH VIL IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XCIN) − Recommended Operating Conditions Parameter Supply voltage Supply voltage Input “H” voltage Input “L” voltage Peak sum output “H” Sum of all pins IOH(peak) current Average sum output “H” Sum of all pins IOH(avg) current Peak output “H” current All pins Average output “H” All pins current Peak sum output “L” Sum of all pins IOL(peak) currents Average sum output “L” Sum of all pins IOL(avg) currents Peak output “L” currents All pins Average output “L” current All pins XCIN clock input oscillation frequency System clock OCD2 = 0 XClN clock selected OCD2 = 1 On-chip oscillator clock selected Conditions Min. 2.2 − 0.8 VCC 0 − − − − − − − − 0 0 − − Standard Typ. − 0 − − − − − − − − − − − − 125 − Max. 5.5 − VCC 0.2 VCC −160 −80 −10 −5 160 80 10 5 70 70 − Unit V V V V mA mA mA mA mA mA mA mA kHz kHz kHz 2.2 V ≤ VCC ≤ 5.5 V 2.2 V ≤ VCC ≤ 5.5 V HRA01 = 0 Low-speed on-chip oscillator selected HRA01 = 1 High-speed on-chip oscillator selected 2.7 V ≤ VCC ≤ 5.5 V HRA01 = 1 High-speed on-chip oscillator selected 2.2 V ≤ VCC ≤ 5.5 V 8 MHz − − 4 MHz NOTES: 1. VCC = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. P0 P1 P3 P4 P6 30pF Figure 5.1 Ports P0, P1, P3, P4, and P6 Timing Measurement Circuit Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 24 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.3 Symbol − − − − − − − Flash Memory (Program ROM) Electrical Characteristics Parameter Program/erase endurance(2) Byte program time Block erase time Program, erase voltage Read voltage Program, erase temperature Data hold time(7) Ambient temperature = 55°C Conditions Standard Min. 100(3) − − 2.7 2.2 0 20 Typ. − 50 0.4 − − − − Max. − 400 9 5.5 5.5 60 − Unit times µs s V V °C year NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 25 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.4 Symbol Vdet0 − td(E-A) Vccmin Voltage Detection 0 Circuit Electrical Characteristics Parameter Voltage detection level Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(2) MCU operating voltage minimum value VCA25 = 1, VCC = 5.0 V Condition Standard Min. 2.2 − − 2.2 Typ. 2.3 0.9 − − Max. 2.4 − 300 − Unit V µA µs V NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. Table 5.5 Symbol Vdet1 − − td(E-A) Voltage Detection 1 Circuit Electrical Characteristics Parameter Voltage detection level(4) Voltage monitor 1 interrupt request generation time(2) VCA26 = 1, VCC = 5.0 V Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) Condition Standard Min. 2.70 − − − Typ. 2.85 40 0.6 − Max. 3.00 − − 100 Unit V µs µA µs NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V. Table 5.6 Symbol Vdet2 − − td(E-A) Voltage Detection 2 Circuit Electrical Characteristics Parameter Voltage detection level Voltage monitor 2 interrupt request generation time(2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) VCA27 = 1, VCC = 5.0 V Condition Standard Min. 3.3 − − − Typ. 3.6 40 0.6 − Max. 3.9 − − 100 Unit V µs µA µs NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 26 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.7 Symbol Vpor1 Vpor2 trth Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3) Parameter Power-on reset valid voltage(4) Power-on reset or voltage monitor 0 reset valid voltage External power VCC rise gradient(2) Condition Standard Min. − 0 20 Typ. − − − Max. 0.1 Vdet0 − Unit V V mV/msec NOTES: 1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for 3,000 s or more if −40°C ≤ Topr < −20°C. Vdet0(3) 2.2 V External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth Vpor2 trth Vdet0(3) Internal reset signal (“L” valid) 1 × 32 fOCO-S 1 × 32 fOCO-S NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. Figure 5.2 Reset Circuit Electrical Characteristics Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 27 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.8 Symbol Vref Comparator Electrical Characteristics Parameter Internal reference voltage Condition VCC = 2.2 V to 5.5 V, Topr = 25°C VCC = 2.2 V to 5.5 V, Topr = −40 to 85°C Standard Min. 1.15 − 0.5 0.5 −0.3 − − Typ. 1.25 1.25 − − − 20 4 Max. 1.35 − VCC − 1.1 VCC − 1.5 VCC + 0.3 120 − V mV µs Unit V V V Vcref Vcin Vofs Tcrsp External input reference voltage External comparison voltage input range Input offset voltage Response time VCC = 2.2 V to 4.0 V VCC = 4.0 V to 5.5 V NOTE: 1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Table 5.9 Symbol fOCO-F High-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter High-speed on-chip oscillator frequency temperature • supply voltage dependence Condition VCC = 4.75 V to 5.25 V Topr = 0 to 60°C(2) VCC = 2.7 V to 5.5 V Topr = −20 to 85°C(2) VCC = 2.7 V to 5.5 V Topr = −40 to 85°C(2) VCC = 2.2 V to 5.5 V Topr = −20 to 85°C(3) VCC = 2.2 V to 5.5 V Topr = −40 to 85°C(3) Standard Min. 7.76 7.68 7.44 7.04 6.8 Typ. 8 8 8 8 8 Max. 8.24 8.32 8.32 8.96 9.2 Unit MHz MHz MHz MHz MHz NOTES: 1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. These standard values show when the HRA1 register is set to the value before shipment and the HRA2 register is set to 00h. 3. These standard values show when the correction value in the FRA6 register is written into the HRA1 register. Table 5.10 Symbol fOCO-S − − Low-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C Condition Standard Min. 30 − − Typ. 125 10 15 Max. 250 100 − Unit kHz µs µA NOTE: 1. VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Table 5.11 Symbol td(P-R) td(R-S) Power Supply Circuit Timing Characteristics Parameter Time for internal power supply stabilization during power-on(2) STOP exit time(3) Condition Standard Min. 1 − Typ. − − Max. 2000 150 Unit µs µs NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 28 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.12 Symbol VOH VOL VT+-VT- Electrical Characteristics (1) [VCC = 5 V] Parameter Condition IOH = −5 mA IOH = −200 µA IOL = 5 mA IOL = 200 µA INT0, INT1, INT2, INT4, KI0, KI1, KI2, KI3, RXD0, RXD2, CLK0, CLK2 RESET VI = 5 V, VCC = 5 V VI = 0 V, VCC = 5 V VI = 0 V, VCC = 5 V XCIN During stop mode Standard Min. VCC − 2.0 VCC − 0.5 − − 0.1 Typ. − − − − 0.5 Max. VCC VCC 2.0 0.45 − Unit V V V V V Output “H” voltage Output “L” voltage Hysteresis 0.1 − − 30 − 2.0 1.0 − − 50 18 − − 5.0 −5.0 167 − − V µA µA kΩ MΩ V IIH IIL RfXCIN VRAM Input “H” current Input “L” current Feedback resistance RAM hold voltage RPULLUP Pull-up resistance NOTE: 1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 29 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.13 Electrical Characteristics (2) [Vcc = 5 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Parameter Condition High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz No division High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) FMR47 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) Program operation on RAM Flash memory off, FMSTP = 1 Symbol ICC Standard Min. − − − − Typ. 5 2 130 130 Max. 8 − 300 300 Unit mA mA µA µA Power supply current High-speed (VCC = 3.3 to 5.5 V) on-chip oscillator mode Single-chip mode, output pins are open, other pins are VSS Low-speed on-chip oscillator mode Low-speed clock mode High-speed on-chip oscillator off − 30 − µA Wait mode High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) − 25 75 µA − 23 60 µA − 4 − µA − 2.2 − µA − 8 − µA − 6 − µA Stop mode XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) − 0.8 3 µA − 1.2 − µA − 5 8 µA − 5.5 − µA Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 30 of 41 R8C/2G Group Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V] Table 5.14 Symbol tc(XCIN) tWH(XCIN) tWL(XCIN) XCIN input cycle time XCIN input “H” width XCIN input “L” width 5. Electrical Characteristics XCIN Input Parameter Standard Min. 14 7 7 Max. − − − Unit µs µs µs tC(XCIN) tWH(XCIN) VCC = 5 V XCIN input tWL(XCIN) Figure 5.3 XCIN Input Timing Diagram when VCC = 5 V Table 5.15 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 100 40 40 Max. − − − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 5 V TRAIO input tWL(TRAIO) Figure 5.4 TRAIO Input Timing Diagram when VCC = 5 V Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 31 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.16 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 200 100 100 − 0 50 90 Max. − − − 50 − − − Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 5 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 2 Figure 5.5 Serial Interface Timing Diagram when VCC = 5 V Table 5.17 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 2, 4) Input Parameter INTi input “H” width INTi input “L” width Standard Min. 250(1) 250(2) Max. − − Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 5 V tW(INL) INTi input tW(INH) i = 0, 1, 2, 4 Figure 5.6 External Interrupt INTi Input Timing Diagram when VCC = 5 V Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 32 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.18 Symbol VOH VOL VT+-VT- Electrical Characteristics (3) [VCC = 3 V] Parameter Condition IOH = −1 mA IOL = 1 mA INT0, INT1, INT2, INT4, KI0, KI1, KI2, KI3, RXD0, RXD2, CLK0, CLK2 RESET VI = 3 V, VCC = 3 V VI = 0 V, VCC = 3 V VI = 0 V, VCC = 3 V XCIN During stop mode Standard Min. VCC − 0.5 − 0.1 Typ. − − 0.3 Max. VCC 0.5 − Unit V V V Output “H” voltage Output “L” voltage Hysteresis 0.1 − − 66 − 1.8 0.4 − − 160 18 − − 4.0 −4.0 500 − − V µA µA kΩ MΩ V IIH IIL RfXCIN VRAM Input “H” current Input “L” current Feedback resistance RAM hold voltage RPULLUP Pull-up resistance NOTE: 1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 33 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.19 Electrical Characteristics (4) [Vcc = 3 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Parameter Condition High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz No division High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) FMR47 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) Program operation on RAM Flash memory off, FMSTP = 1 Symbol ICC Standard Min. − − − − Typ. 5 2 130 130 Max. − − 300 300 Unit mA mA µA µA Power supply current High-speed (VCC = 2.7 to 3.3 V) on-chip oscillator mode Single-chip mode, output pins are open, other pins are VSS Low-speed on-chip oscillator mode Low-speed clock mode High-speed on-chip oscillator off − 30 − µA Wait mode High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) − 25 70 µA − 23 55 µA − 3.8 − µA − 2 − µA − 8 − µA − 6 − µA Stop mode XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) − 0.7 3 µA − 1.1 − µA − 5 7 µA − 5.5 − µA Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 34 of 41 R8C/2G Group Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V] Table 5.20 Symbol tc(XCIN) tWH(XCIN) tWL(XCIN) XCIN input cycle time XCIN input “H” width XCIN input “L” width 5. Electrical Characteristics XCIN Input Parameter Standard Min. 14 7 7 Max. − − − Unit µs µs µs tC(XCIN) tWH(XCIN) VCC = 3 V XCIN input tWL(XCIN) Figure 5.7 XCIN Input Timing Diagram when VCC = 3 V Table 5.21 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 300 120 120 Max. − − − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 3 V TRAIO input tWL(TRAIO) Figure 5.8 TRAIO Input Timing Diagram when VCC = 3 V Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 35 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.22 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi Input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 300 150 150 − 0 70 90 Max. − − − 80 − − − Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 3 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 2 Figure 5.9 Serial Interface Timing Diagram when VCC = 3 V Table 5.23 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 2, 4) Input Parameter INTi input “H” width INTi input “L” width Standard Min. 380(1) 380(2) Max. − − Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 3 V tW(INL) INTi input tW(INH) i = 0, 1, 2, 4 Figure 5.10 External Interrupt INTi Input Timing Diagram when VCC = 3 V Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 36 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.24 Symbol VOH VOL VT+-VT- Electrical Characteristics (5) [VCC = 2.2 V] Parameter Condition IOH = −1 mA IOL = 1 mA INT0, INT1, INT2, INT4, KI0, KI1, KI2, KI3, RXD0, RXD2, CLK0, CLK2 RESET VI = 2.2 V VI = 0 V VI = 0 V XCIN During stop mode Standard Min. VCC − 0.5 − 0.05 Typ. − − 0.3 Max. VCC 0.5 − Unit V V V Output “H” voltage Output “L” voltage Hysteresis 0.05 − − 100 − 1.8 0.15 − − 200 35 − − 4.0 −4.0 600 − − V µA µA kΩ MΩ V IIH IIL RfXCIN VRAM Input “H” current Input “L” current Feedback resistance RAM hold voltage RPULLUP Pull-up resistance NOTE: 1. VCC = 2.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 37 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.25 Electrical Characteristics (6) [Vcc = 2.2 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Parameter Condition High-speed on-chip oscillator on = 4 MHz Low-speed on-chip oscillator on = 125 kHz No division High-speed on-chip oscillator on = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) FMR47 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) Program operation on RAM Flash memory off, FMSTP = 1 Symbol ICC Standard Min. − − − − Typ. 3.5 1.5 100 100 Max. − − 230 230 Unit mA mA µA µA Power supply current High-speed (VCC = 2.2 to 2.7 V) on-chip oscillator mode Single-chip mode, output pins are open, other pins are VSS Low-speed on-chip oscillator mode Low-speed clock mode High-speed on-chip oscillator off − 25 − µA Wait mode High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) − 22 60 µA − 20 55 µA − 3 − µA − 1.8 − µA − 7 − µA − 6 − µA Stop mode XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) − 0.7 3 µA − 1.1 − µA − 5 7 µA − 5.5 − µA Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 38 of 41 R8C/2G Group 5. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V] Table 5.26 Symbol tc(XCIN) tWH(XCIN) tWL(XCIN) XCIN input cycle time XCIN input “H” width XCIN input “L” width XCIN Input Parameter Standard Min. 14 7 7 Max. − − − Unit µs µs µs tC(XCIN) tWH(XCIN) VCC = 2.2 V XCIN input tWL(XCIN) Figure 5.11 XCIN Input Timing Diagram when VCC = 2.2 V Table 5.27 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 500 200 200 Max. − − − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 2.2 V TRAIO input tWL(TRAIO) Figure 5.12 TRAIO Input Timing Diagram when VCC = 2.2 V Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 39 of 41 R8C/2G Group 5. Electrical Characteristics Table 5.28 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 800 400 400 − 0 150 90 Max. − − − 200 − − − Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 2.2 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 2 Figure 5.13 Serial Interface Timing Diagram when VCC = 2.2 V Table 5.29 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 2, 4) Input Parameter INTi input “H” width INTi input “L” width Standard Min. 1000(1) 1000(2) Max. − − Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 2.2 V tW(INL) INTi input tW(INH) i = 0, 1, 2, 4 Figure 5.14 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 40 of 41 R8C/2G Group Package Dimensions Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g HD *1 D 24 17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 25 16 HE E c1 *2 c Reference Dimension in Millimeters Symbol Terminal cross section 32 1 ZD Index mark 8 ZE 9 A2 A F A1 L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e *3 Detail F bp x Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0° 8° 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0 Rev.1.00 Apr 04, 2008 REJ03B0223-0100 Page 41 of 41 c REVISION HISTORY REVISION HISTORY R8C/2G Group Datasheet R8C/2G Group Datasheet Description Rev. 0.10 0.20 Date Jul 20, 2007 Nov 12, 2007 Page − Summary First Edition issued Table 1.1 I/O Ports: “• Output-only: 1” added “• CMOS I/O ports: 28” → “• CMOS I/O ports: 27” Figure 1.2 revised Figure 1.3 revised Table 1.3 Pin Number: 4, 6, 20 revised Table 1.4 I/O port: “P4_3 to P4_5” → “P4_3, P4_5” Output port added Table 4.1 0006h “01001000b” → “01011000b” Table 4.5 0118h to 011Dh: After reset revised 011Fh “Timer RE Real-Time Clock Precision Adjust Register” added Table 5.2 NOTE2 revised Table 1.1 revised Table 1.2 “(D): Under development” deleted Figure 3.1 “Expanded area” deleted Table 4.1 “002Eh” “002Fh” revised Table 4.2 “003Eh” “003Fh” revised Table 5.3 revised Figure 5.2 deleted Table 5.8, Table 5.11 revised Table 5.9 revised, NOTE3 added Table 5.13 revised Table 5.19 revised Table 5.25 revised 2 4 5 6 7 12 16 24 1.00 Apr 04, 2008 2 3 11 12 13 25 28 30 34 38 All pages “Under development” deleted All trademarks and registered trademarks are the property of their respective owners. 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