Data Sheet
R9A02G011
ASSP (USB Power Delivery Controller)
R19DS0088EJ0210
Rev.2.10
Apr. 22, 2022
1. OVERVIEW
The R9A02G011 is a USB Power Delivery Controller that is based on the Universal Serial Bus (USB) Power
Delivery Specification Revision 3.1 and USB Type-CTM Cable and Connecter Specification Release 2.1. The
R9A02G011 performs negotiation for more current and/or higher voltages over the USB cable (VBUS) than are
defined in the USB2.0, USB3.0 or BC1.2 specifications, and controls circuitry to select local power source or
power sink. The R9A02G011 uses a 300kbps BMC modulated signal through the CC wire in the USB Type-CTM
cable. It comes in two types of packages, 32-pin QFN for easy implementation, and 42-pin BGA for reducing
space, so that it can choose according to the application and PCB space. In addition, the R9A02G011
incorporates Renesas’ low-power technologies.
1.1
Features
1.2
Compliant with USB Power Delivery Specification Revision 3.1 and USB Type-CTM Cable and
Connector Specification Release 2.1
Certified by USB Implementers Forum: TID= 64651080009 (Silicon), 1020074 (E-marker)
Supports Standard Power Range including Programmable Power Supply
* Not cover Extended Power Range including Adjustable Voltage Supply
Supports IEC63002
Supports up to 260 bytes data transfer
Supports all USB Type-CTM Connection State Diagrams for USB Type-CTM port control
Supports alternate mode and electronically marked cables
Supports Dual Role operation and Role Swap protocol
Supports Dead Battery operation
Integrated CC-PHY and CC-logic and many peripheral components
Single Power Supply with wide voltage range
From 3.0 to 5.5V: R9A02G011GNP
From 2.7 to 5.5V: R9A02G011GBG
On-chip Flash ROM, Oscillator, and Power-On-Reset (POR) circuit
Selectable two types of packages according to the application and PCB space
Supports SMBus Master and Slave interfaces
Suitable for Energy Star and EuP specifications for low-power PC peripheral systems.
Applications
AC Adapter, Power outlet, USB PD Hub, PC, Tablet, Smartphone, Docking Station, PC Peripheral Device
(Monitor, Printer, Router, External HDD), Consumer Electronics (DTV, STB, Home Gateway), USB Type-CTM
Cable (E-Marker) etc.
Remark E-Marker: Electric marker that can return information about the cable’s specifications, its manufacturer, and more.
1.3
Ordering Information
Part Number
R9A02G011GNP#AC0
R9A02G011GBG#AC0
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Package
32-pin QFN (5 × 5 mm)
42-pin BGA (3.6 x 3.1 mm)
Remark
Lead-free product
Lead-free product
Page 1 of 23
R9A02G011
1.4
1. OVERVIEW
Block Diagram
Figure 1-1.
R9A02G011 Block Diagram
VDD
CC1/CC2
RD1/RD2
REGCTX
Power Delivery
CC-PHY
&
CC-Logic
Flash
ROM
Power
Delivery
Logic
LDO
REGC
System
Controller
RAM
POR
Reset
Controller
RESETB
(Optional)
Port
Terminology
Block Name
Power Delivery
CC-PHY & Logic
OCO
SLVADDR0/1
SLVSCL
MSTSALTB
MSTSDA
MSTSCL
Px
Table 1-1.
SLVSALTB
SMBus
Slave
SMBus
Master
ADC
SLVSDA
VBUSM
Description
CC-PHY (Tx/Rx), CC-logic, and LDO used for CC-PHY
Power Delivery Logic
Power Delivery logic controller
System Controller
System CPU core (RL78)
Flash ROM
Internal Flash ROM
RAM
Internal SRAM
SMBus Slave
Interface signals to external SMBus Master.
SMBus Master
Interface signals to external SMBus Slave.
Port
Controls Port I/O signals
OCO
On-Chip Oscillator
POR
Internal Power-On-Reset circuit
Reset Controller
External reset signal (Optional)
ADC
AD Converter
LDO
Low Drop Out regulator integrated in this IC
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 2 of 23
R9A02G011
1.5
1. OVERVIEW
Pin Configuration
• 32-pin QFN (5 × 5 mm)
Pin Configuration of R9A02G011 32-pin QFN (Top View)
P137/MSTSALTB/INTP0
P122/SLVADDR1
P121/SLVADDR0
REGC
VDD
REGCTX
RD2
CC2
Figure 1-2.
24 23 22 21 20 19 18 17
RESETB
P70/INTP4
P71
P72
P73
P81/INTP6
P82/INTP7
P17
25
16
26
15
27
14
GND
Pad
28
29
13
12
30
11
31
10
32
9
2
3 4
5
6
7
8
P16
P20/ANI8/VBUSM
P21/ANI9
P22/ANI10
P31/MSTSDA
P30/MSTSCL
P40/TOOL0
P61/SLVSDA
1
CC1
RD1
P51/INTP2
P50/INTP1
P80/INTP5
P32/INTP3
P62/SLVSALTB
P60/SLVSCL
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 3 of 23
µPD
1. OVERVIEW
• 42-pin BGA (3.6 x 3.1 mm)
Figure 1-3.
Pin Configuration of R9A02G011 42-pin BGA (Top View)
Bottom View
Top View
INDEX MARK
A
B
C
D
E
F
G
1
2
4
5
6
6
5
4
3
1
2
3
4
5
A
VSS
P17
P81/
(NC)
RESETB
B
VSS
P16
P73
P72
P70/
C
P21/
ANI9
D
P30/
E
P31/
F
G
MSTSCL
MSTSDA
(NC)
P40/
TOOL0
1
R19DS0088EJ0210
Apr. 22, 2022
3
Rev.2.10
P20/
ANI8/
VBUSM
P22/
ANI10
(NC)
P60/
SLVSCL
P61/
SLVSDA
2
INTP6
P82/
INTP7
P71
(NC)
P32/
INTP3
P62/
SLVSALTB
INTP4
P121/
2
1
6
P137/
MSTSALTB/
INTP0
P122/
SLVADDR1
B
SLVADDR0
REGC
C
VDD
VDD
VDD
D
(NC)
RD2
REGCTX
E
RD1
CC2
F
G
P80/
INTP5
P50/
P51/
INTP2
CC1
VSS
3
4
5
6
INTP1
A
Page 4 of 23
R9A02G011
2. PIN FUNCTION
2. PIN FUNCTION
This section describes each pin’s function.
2.1
Power supply
QFN
Pin No.
BGA
Ball No.
I/O
Type
VDD
20
D4/D5/D6
Power
REGCTX
19
E6
Power
Regulator capacitance for CC-PHY. Connecting regulator
output stabilization capacitance for internal operation.
REGC
21
C6
Power
Regulator capacitance. Connecting regulator output
stabilization capacitance for internal operation.
Die Pad
A1/B1/G6
-
Pin Name
VSS
2.2
Function
Power supply
(from 3.0V to 5.5V: R9A02G011GNP)
(from 2.7V to 5.5V: R9A02G011GBG)
Ground
System Interface Pins
Pin Name
RESETB
2.3
QFN
Pin No.
BGA
Ball No.
I/O
Type
25
A5
IN
Function
Chip Reset Input (L active)
USB PD and Type-CTM Port Pins
QFN
Pin No.
BGA
Ball No.
I/O
Type
RD1
15
F5
I/O
Rd resistor 1, Analog pin from CC-PHY.
CC1
16
G5
I/O
Configuration Channel 1, Analog pin from CC-PHY
CC2
17
F6
I/O
Configuration Channel 2, Analog pin from CC-PHY
RD2
18
E5
I/O
Rd resistor 2, Analog pin from CC-PHY
Pin Name
2.4
Function
I/O Port Pins
QFN
Pin No.
BGA
Ball No.
I/O
Type
During
reset
After reset
P16
1
B2
I/O
Input
Input
Port 1, 2 bit I/O port.
P17
32
A2
I/O
Input
Input
Port 1, 2 bit I/O port.
Pin Name
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Function
Page 5 of 23
R9A02G011
2. PIN FUNCTION
QFN
Pin No.
BGA
Ball No.
I/O
Type
During
reset
After reset
Function
P20
2
C2
I/O
Input
Input
Port 2, 3 bit I/O port.
It is also configurable as VBUSM or ANI8
P21
3
C1
I/O
Input
Input
Port 2, 3 bit I/O port.
It is also configurable as ANI9
P22
4
D2
I/O
Input
Input
Port 2, 3 bit I/O port.
It is also configurable as ANI10
P30
6
D1
I/O
Input
Input
Port 3, 3 bit I/O port.
It is also configurable as MSTSCL.
P31
5
E1
I/O
Input
Input
Port 3, 3 bit I/O port.
It is also configurable as MSTSDA
P32
11
E3
I/O
Input
Input
Port 3, 3 bit I/O port.
It is also configurable as INTP3
P40
7
G1
I/O
Input
Input
Pull-up
Port 4, 1 bit I/O port.
It is also configurable as TOOL0
P50
13
G3
I/O
Input
Input
Port 5, 2 bit I/O port.
It is also configurable as INTP1
P51
14
G4
I/O
Input
Input
Port 5, 2 bit I/O port.
It is also configurable as INTP2
P60
9
F2
I/O
Input
Input
Port 6, 3 bit I/O port.
It is also configurable as SLVSCL
P61
8
G2
I/O
Input
Input
Port 6, 3 bit I/O port.
It is also configurable as SLVSDA
P62
10
F3
I/O
Input
Input
Port 6, 3 bit I/O port.
It is also configurable as SLVSALTB
P70
26
B5
I/O
Input
Input
Port 7, 4 bit I/O port.
It is also configurable as INTP4
P71
27
C4
I/O
Input
Input
P72
28
B4
I/O
Input
Input
P73
29
B3
I/O
Input
Input
P80
12
F4
I/O
Input
Input
Port 8, 3 bit I/O port.
It is also configurable as INTP5
P81
30
A3
I/O
Input
Input
Port 8, 3 bit I/O port.
It is also configurable as INTP6
P82
31
C3
I/O
Input
Input
Port 8, 3 bit I/O port.
It is also configurable as INTP7
P121
22
C5
IN
Input
Input
Port 12, 2 bit Input port.
It is also configurable as SLVADDR0
P122
23
B6
IN
Input
Input
Port 12, 2 bit Input port.
It is also configurable as SLVADDR1
P137
24
A6
IN
Input
Input
Port 13, 1 bit Input port.
It is also configurable as MSTSALTB or
INTP0.
Pin Name
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Port 7, 4 bit I/O port.
Port 7, 4 bit I/O port.
Port 7, 4 bit I/O port.
Page 6 of 23
R9A02G011
2.5
2. PIN FUNCTION
Alternate Functions on I/O Port Pins
I/O ports support the following alternate functions.
Function Name
I/O
ANI8 to ANI10
Input
MSTSCL
I/O
SMBus master clock input/output (open-drain) Note 1
MSTSDA
I/O
SMBus master data input/output (open-drain) Note 1
MSTSALTB
Input
SLVSCL
I/O
SMBus slave clock input/output (open-drain) Note 2
SLVSDA
I/O
SMBus slave data input/output (open-drain) Note 2
SLVSALTB
Output
SLVADDR0
input
SMBus slave address bit [1] Note 2
SLVADDR1
input
SMBus slave address bit [2] Note 2
VBUSM
Input
INTP0 to INTP7
Input
TOOL0
I/O
Note 1.
Note 2.
Function
Analog Input
SMBus master alert input Note 1
SMBus slave alert output (open-drain)
VBUS voltage monitor input.
The pin assignment is fixed to this function.
Interrupt detection input. The valid edge (rising edge, falling
edge, or rising and falling edges) can be specified.
Data input/output for flash programming tool.
The pin assignment is fixed to this function.
The pin assignment is fixed to this function when SMBus Master is enabled.
The pin assignment is fixed to this function when SMBus Slave is enabled.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 7 of 23
R9A02G011
3. ELECTRICAL SPECIFICATIONS
3. ELECTRICAL SPECIFICATIONS
This chapter describes the following electrical specifications.
3.1
Absolute Maximum Ratings
Absolute Maximum Ratings (1/2)
Parameter
Supply voltage
REGC pin input
Symbols
Ratings
Unit
VDD
−0.5 to +6.5
V
VSS
−0.5 to +0.3
V
−0.3 to +2.8
V
VIREGC
Conditions
REGC
and −0.3 to VDD +0.3 Note 1
voltage
Input voltage
−0.3 to +2.8
VIREGCTX
REGCTX
VI
P16, P17, P20 to P22, P30 to P32, P40, P50,
−0.3 to VDD +0.3
V
Note 2
V
P51, P60 to P62, P70 to P73, P80 to P82, P121,
P122, P137, RESETB
Output voltage
VO
P16, P17, P20 to P22, P30 to P32, P40, P50,
P51, P60 to P62, P70 to P73, P80 to P82
−0.3 to VDD +0.3 Note 2
V
Analog input voltage
VAI1
ANI8 to ANI10
−0.3 to VDD +0.3 Note 2
V
VAI2
CC1, CC2, RD1, RD2
−0.5 to +6.5
V
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
maximum rating of the REGC pin.
This value regulates the absolute
Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2.
VSS : Reference voltage
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 8 of 23
R9A02G011
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (2/2)
Parameter
Output current, high
Output current, low
Symbols
IOH1
IOL1
Conditions
TA
temperature
Unit
Per pin
P16, P17, P20 to P22, P30 to
−40
mA
Total of all pins
P32, P40, P50, P51, P60 to P62,
P70 to 73, P80 to P82
-170
mA
40
mA
170
mA
−40 to +105:
°C
Per pin
Total of all pins
Operating ambient
Ratings
P16, P17, P20 to P22, P30 to
P32, P40, P50, P51, P60 to P62,
P70 to 73, P80 to P82
In normal operation mode
In flash memory programming mode
R9A02G011GNP
−40 to +90:
R9A02G011GBG
Storage temperature
Tstg
−65 to +150:
°C
R9A02G011GNP
−55 to +90:
R9A02G011GBG
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 9 of 23
R9A02G011
3.2
3. ELECTRICAL SPECIFICATIONS
Oscillator Characteristics
On-chip oscillator characteristics of R9A02G011GNP
(TA = −40 to +105°C, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators
Parameters
High-speed on-chip
oscillator clock frequency
Conditions
MIN.
TYP.
MAX.
24
fIH
Unit
MHz
Notes 1
High-speed on-chip
−20 to +85 °C
3.0 V ≤ VDD ≤ 5.5 V
-1
+1
%
oscillator clock frequency
accuracy
−40 to −20 °C
3.0 V ≤ VDD ≤ 5.5 V
-1.5
+1.5
%
+85 to +105 °C
3.0 V ≤ VDD ≤ 5.5 V
-2
+2
%
Notes 1. This indicates the oscillator characteristics only.
Refer to AC Characteristics for instruction execution time.
On-chip oscillator characteristics of R9A02G011GBG
(TA = −40 to +90°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators
Parameters
High-speed on-chip
Conditions
MIN.
TYP.
MAX.
24
fIH
Unit
MHz
oscillator clock frequency
Notes 2
High-speed on-chip
oscillator clock frequency
accuracy
−20 to +85 °C
2.7 V ≤ VDD ≤ 5.5 V
-1
+1
%
−40 to −20 °C
2.7 V ≤ VDD ≤ 5.5 V
-1.5
+1.5
%
+85 to +90 °C
2.7 V ≤ VDD ≤ 5.5 V
-2
+2
%
Notes 2. This indicates the oscillator characteristics only.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Refer to AC Characteristics for instruction execution time.
Page 10 of 23
R9A02G011
3.3
3. ELECTRICAL SPECIFICATIONS
DC Characteristics
Pin characteristics of R9A02G011GNP
(TA = −40 to +105°C, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/3)
Items
Input voltage,
Symbol
VIH1
P16, P17, P20 to P22, P30 to P32,
P50, P51, P60 to P62, P70 to P73,
P80 to P82
high
Input voltage,
Conditions
VIH2
P40, P121, P122, P137, RESETB
VIL1
P16, P17, P20 to P22, P30 to P32,
P50, P51, P60 to P62, P70 to P73,
P80 to P82
low
VIL2
P40, P121, P122, P137, RESETB
MIN.
TYP.
MAX.
Unit
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
2.2
VDD
V
TTL input buffer
3.3 V ≤ VDD < 4.0 V
2.0
VDD
V
TTL input buffer
3.0 V ≤ VDD < 3.3 V
1.5
VDD
V
0.8 VDD
VDD
V
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
0
0.8
V
TTL input buffer
3.3 V ≤ VDD < 4.0 V
0
0.5
V
TTL input buffer
3.0 V ≤ VDD < 3.3 V
0
0.32
V
0
0.2 VDD
V
Caution The maximum value of all pins is VDD, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 11 of 23
R9A02G011
3. ELECTRICAL SPECIFICATIONS
(TA = −40 to +105°C, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/3)
Items
Symbol
Output voltage,
VOH1
high
Output voltage,
VOL1
low
Conditions
MIN.
P16, P17, P20 to P22, P30 to P32,
3.0 V ≤ VDD ≤ 5.5 V,
VDD −
P40, P50, P51, P60 to P62, P70 to
P73, P80 to P82
IOH1 = −1.5 mA
0.5
P16, P17, P20 to P22, P30 to P32,
3.0 V ≤ VDD ≤ 5.5 V,
P40, P50, P51, P60 to P62, P70 to
P73, P80 to P82
IOL1 = 1.5 mA
TYP.
MAX.
Unit
V
0.4
V
Caution
All pins do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
(TA = −40 to +105°C, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (3/3)
Items
Symbol
Input leakage
ILIH1
P16, P17, P20 to P22, P30 to
MIN.
TYP.
MAX.
Unit
VI = VDD
1
μA
P32, P40, P50, P51, P60 to
P62, P70 to P73, P80 to P82,
P137, RESETB
current, high
Input leakage
current, low
On-chip pull-up
resistance
Remark
Conditions
ILIH2
P121, P122
VI = VDD, In input port
1
μA
ILIL1
P16, P17, P20 to P22, P30 to
P32, P40, P50, P51, P60 to
P62, P70 to P73, P80 to P82,
P137, RESETB
VI = VSS
−1
μA
ILIL2
P121, P122
VI = VSS, In input port
−1
μA
RU
P16, P17, P20 to P22, P30 to
P32, P40, P50, P51, P60 to
P62, P70 to P73, P80 to P82
VI = VSS, In input port
100
kΩ
10
20
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 12 of 23
R9A02G011
3. ELECTRICAL SPECIFICATIONS
Pin characteristics of R9A02G011GBG
(TA = −40 to +90°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/3)
Items
Input voltage,
Symbol
VIH1
P16, P17, P20 to P22, P30 to
P32, P50, P51, P60 to P62, P70
to P73, P80 to P82
high
Input voltage,
Conditions
VIH2
P40, P121, P122, P137, RESETB
VIL1
P16, P17, P20 to P22, P30 to
P32, P50, P51, P60 to P62, P70
to P73, P80 to P82
low
VIL2
MIN.
TYP.
MAX.
Unit
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
2.2
VDD
V
TTL input buffer
3.3 V ≤ VDD < 4.0 V
2.0
VDD
V
TTL input buffer
2.7 V ≤ VDD < 3.3 V
1.5
VDD
V
0.8 VDD
VDD
V
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
0
0.8
V
TTL input buffer
3.3 V ≤ VDD < 4.0 V
0
0.5
V
TTL input buffer
2.7 V ≤ VDD < 3.3 V
0
0.32
V
0
0.2 VDD
V
P40, P121, P122, P137, RESETB
Caution The maximum value of all pins is VDD, even in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 13 of 23
R9A02G011
3. ELECTRICAL SPECIFICATIONS
(TA = −40 to +90°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/3)
Items
Symbol
Output voltage,
VOH1
Conditions
P16, P17, P20 to P22, P30 to
P32, P40, P50, P51, P60 to P62,
P70 to P73, P80 to P82
high
Output voltage,
VOL1
2.7 V ≤ VDD ≤ 5.5 V,
VDD −
IOH1 = −1.5 mA
0.5
TYP.
MAX.
Unit
V
2.7 V ≤ VDD ≤ 5.5 V,
P16, P17, P20 to P22, P30 to
P32, P40, P50, P51, P60 to P62,
P70 to P73, P80 to P82
low
MIN.
0.4
V
IOL1 = 1.5 mA
Caution
All pins do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
(TA = −40 to +90°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (3/3)
Items
Symbol
Input leakage
ILIH1
P16, P17, P20 to P22, P30 to
MIN.
TYP.
MAX.
Unit
VI1 = VDD
1
μA
P32, P40, P50, P51, P60 to
P62, P70 to 73, P80 to P82,
P137, RESETB
current, high
Input leakage
current, low
On-chip pull-up
resistance
Remark
Conditions
ILIH2
P121, P122
VI1 = VDD, In input port
1
μA
ILIL1
P16, P17, P20 to P22, P30 to
P32, P40, P50, P51, P60 to
P62, P70 to 73, P80 to P82,
P137, RESETB
VI1 = VSS
−1
μA
ILIL2
P121, P122
VI1 = VSS, In input port
−1
μA
RU
P16, P17, P20 to P22, P30 to
P32, P40, P50, P51, P60 to
P62, P70 to 73, P80 to P82
VI1 = VSS, In input port
100
kΩ
10
20
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 14 of 23
R9A02G011
3.4
3. ELECTRICAL SPECIFICATIONS
AC Characteristics
R9A02G011GNP: (TA = −40 to +105°C, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
R9A02G011GBG: (TA = −40 to +90°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items
Symbol
RESETB low-level width
tRSL
Conditions
MIN.
10
TYP.
MAX.
Unit
μs
AC Timing Test Points
RESETB Input Timing
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 15 of 23
R9A02G011
3.5
3. ELECTRICAL SPECIFICATIONS
Peripheral Functions Characteristics
SMBus Interface
R9A02G011GNP: (TA = −40 to +105°C, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
R9A02G011GBG: (TA = −40 to +90°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Condition
100 kHz
400 kHz
1 MHz
Class
Class
Class
MIN
MAX
MIN
MAX
MIN
MAX
100
10
400
10
1000
Units
SMBus operating frequency
FSMB
10
Bus free time between stop and
start condition
TBUF
4.7
1.3
0.5
μs
Hold time after (Repeated) start
condition. After this period, the first
clock is generated.
THD:STA
4.0
0.6
0.26
μs
Repeated start condition setup time
TSU:STA
4.7
0.6
0.26
μs
Stop condition setup time
TSU:STO
4.0
0.6
0.26
μs
Data hold time
THD:DAT
0
0
0
ns
Data setup time
TSU:DAT
250
100
50
ns
Clock low period
TLOW
4.7
1.3
0.5
μs
Clock high period
THIGH
4.0
Cumulative clock low extend time
(slave device)
TLOW:SEXT
25
Cumulative clock low extend time
(master device)
TLOW:MEXT
Clock/Data fall time
50
μs
25
25
ms
10
10
10
ms
TF
300
300
120
ns
Clock/Data rise time
TR
1000
300
120
ns
Noise spike suppression time
Tspike
50
ns
Operational time after power-on
reset
TPOR
500
ms
Rev.2.10
0.6
0
500
Figure 3-1.
R19DS0088EJ0210
Apr. 22, 2022
50
50
50
500
0.26
kHz
0
SMBus Signal Timing
Page 16 of 23
R9A02G011
3.6
3. ELECTRICAL SPECIFICATIONS
Analog Characteristics
A/D converter characteristics of R9A02G011GNP
(TA = −40 to +105°C, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS)
Parameter
Symbol
Conditions
Resolution
RES
Overall errorNotes 1, 2
AINL
10-bit resolution
Analog input voltage
VAIN
ANI8 to ANI10
MIN.
TYP.
MAX.
10
bit
1.2
±7.0
LSB
VDD
V
8
3.0 V ≤ VDD ≤ 5.5 V
0
Unit
A/D converter characteristics of R9A02G011GBG
(TA = −40 to +90°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS)
Parameter
Resolution
Symbol
Conditions
RES
Notes 1, 2
MIN.
TYP.
8
Overall error
AINL
10-bit resolution
Analog input voltage
VAIN
ANI8 to ANI10
2.7 V ≤ VDD ≤ 5.5 V
1.2
0
MAX.
Unit
10
bit
±7.0
LSB
VDD
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 17 of 23
R9A02G011
3. ELECTRICAL SPECIFICATIONS
POR circuit characteristics
R9A02G011GNP: (TA = −40 to +105°C, VSS = 0 V)
R9A02G011GBG: (TA = −40 to +90°C, VSS = 0 V)
Parameter
Symbol
Detection voltage
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
V
VPOR
Power supply rise time
1.43
1.51
1.59
VPDR
Power supply fall time
1.42
1.50
1.58
TPW
300
V
µs
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for
a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the
main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status
control register (CSC).
Power supply voltage rising slope characteristics
R9A02G011GNP: (TA = −40 to +105°C, VSS = 0 V)
R9A02G011GBG: (TA = −40 to +90°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Symbol
SVDD
Conditions
MIN.
TYP.
MAX.
Unit
54
V/ms
Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD
reaches the operating voltage range.
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 18 of 23
R9A02G011
3. ELECTRICAL SPECIFICATIONS
CC-PHY characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
80
96
µA
CC Current Source (Default)
I80u
64
CC Current Source (1.5A)
I180u
166
180
194
µA
CC Current Source (3A)
I330u
304
330
356
µA
Transmitter Output Impedance
zDriver
33
75
Ω
Transmitter Rise Time
tRISE_TX
300
ns
Transmitter Fall Time
tFALL_TX
300
ns
Receiver Input Impedance
zBMCRX
1
MΩ
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 19 of 23
R9A02G011
3.7
3. ELECTRICAL SPECIFICATIONS
Flash Memory Programming Characteristics
Flash Memory Programming Characteristics of R9A02G011GNP
(TA = −40 to +105°C, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
System clock frequency
Number of code flash rewrites
fCLK
Cerwr
Conditions
MIN.
3.0 V ≤ VDD ≤ 5.5 V
Retained for 20 years
TYP.
1
TA = 85°C
Notes 4
MAX.
Unit
24
MHz
1,000
Times
Notes 1,2,3
Flash Memory Programming Characteristics of R9A02G011GBG
(TA = −40 to +90°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
System clock frequency
Number of code flash rewrites
fCLK
Cerwr
Conditions
MIN.
2.7 V ≤ VDD ≤ 5.5 V
Retained for 20 years
TYP.
1
TA = 85°C
Notes 4
MAX.
Unit
24
MHz
1,000
Times
Notes 1,2,3
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2. When using flash memory programmer and Renesas Electronics self-programming library.
3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas
Electronics Corporation.
4. This temperature is the average value at which data are retained.
3.8
Pin Capacitance
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
System Interface Pin capacitance
CSYS
5
pF
I/O Port Pin capacitance
CIO
5
pF
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 20 of 23
R9A02G011
3.9
3. ELECTRICAL SPECIFICATIONS
Power Consumption
Power Consumption for applications other than E-Marker
(TA = 25°C, VDD = 3.3 V, VSS = 0 V)
Parameter
Conditions
Operating current as Source role
Operating current as Sink role
Supply current in sleep mode
Sink attached.
Source attached.
TYP.
Unit
No PD Communication.
3.2
mA
PD Communication.
4.1
mA
No PD Communication.
2.7
mA
PD Communication.
3.6
mA
205
μA
2.8
μA
TYP.
Unit
No PD Communication.
3.9
mA
PD Communication.
4.8
mA
No PD Communication.
3.4
mA
PD Communication.
4.3
mA
Unplugged. SMBus, WAKEUP/INTP and CC enabled for wakeup. Source
role.
Supply current in deep sleep mode
Unplugged. SMBus and WAKEUP/INTP enabled for wakeup.
(TA = 25°C, VDD = 5.0 V, VSS = 0 V)
Parameter
Conditions
Operating current as Source role
Operating current as Sink role
Sink attached.
Source attached.
Supply current in sleep mode
Unplugged. SMBus, WAKEUP/INTP and CC enabled for wakeup. Source
role.
230
μA
Supply current in deep sleep mode
Unplugged. SMBus and WAKEUP/INTP enabled for wakeup.
3.2
μA
TYP.
Unit
No PD Communication
2.2
mA
PD Communication
3.5
mA
TYP.
Unit
No PD Communication
2.5
mA
PD Communication
4.0
mA
Power Consumption for E-Marker in a USB Type-CTM Cable
(TA = 25°C, VDD = 3.3 V, VSS = 0 V)
Parameter
Conditions
Operating current as Cable Plug
Attached between a Port Pair
(TA = 25°C, VDD = 5.0 V, VSS = 0 V)
Parameter
Conditions
Operating current as Cable Plug
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Attached between a Port Pair
Page 21 of 23
R9A02G011
4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
32-PIN QFN (5 x 5 mm)
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 22 of 23
R9A02G011
4. PACKAGE DRAWINGS
42-pin BGA (3.6 x 3.1 mm)
R19DS0088EJ0210
Apr. 22, 2022
Rev.2.10
Page 23 of 23
Revision History
Rev.
R9A02G011 Data Sheet
Date
Description
Page
Summary
1.0
Nov. 25, 2016
-
First Edition issued
1.01
Feb. 17, 2017
3
Updated Figure 1-2
5
Updated section 2.4
6
Updated section 2.5
1
Updated section 1, section 1.1
-
Corrected writing errors
1
Updated section 1, section 1.1, section 1.3
3
Updated section 1.5
15
Updated section 3.6.2
18
Updated section 3.9
19
Updated section 4
Updated section 1.1
1.02
1.10
Oct. 24, 2017
Jan. 29, 2018
1.20
Mar. 27, 2018
1
1.30
Jan. 29, 2019
4-6
2.00
Dec. 23, 2021
-
Completely revised with the addition of R9A02G011GBG.
1
Updated section 1, section 1.1
1
Updated section 1, section 1.1
2.10
Apr. 22, 2022
Updated section 2.4, section 2.6
SuperFlash(R) is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
NOTE) This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, inc.
All trademarks and registered trademarks are the property of their respective owners.
C- 1
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
2.
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
3.
level at which resetting is specified.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
4.
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
5.
become possible.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
6.
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
7.
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
8.
addresses as the correct operation of the LSI is not guaranteed.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use
of these circuits, software, or information.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights,
or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this
document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics
or others.
You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export,
manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, if required.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any
and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for
each Renesas Electronics product depends on the product’s quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home
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Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
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RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE,
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When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for
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Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific
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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas
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(Note1)
(Note2)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled
subsidiaries.
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.5.0-1 October 2020)
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