User’s Manual
32
Cover
RZ/N1D Group,
RZ/N1S Group,
RZ/N1L Group
User’s Manual: System Introduction, Multiplexing,
Electrical and Mechanical Information
RZ Family
RZ/N Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.40
Feb, 2021
Notice
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of
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Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or
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(Note1)
(Note2)
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General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be
touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in
a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level
at which resetting is specified.
3.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements.
Follow the guideline for input signal during power-off state as described in your product documentation.
4.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced
with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.)
and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7.
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of
internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users,
i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logic circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control
functions, and peripheral functions, electrical characteristics of the device, and usage notes.
When designing an application system that includes this LSI, take all points to note into account.
Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all
revised items. For details on the revised points, see the actual locations in the manual.
The following documents have been prepared for reference.
Documents related to RZ/N1
Document Name
Document Number
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group DATASHEET
R01DS0323EJ****
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group User’s Manual: System Introduction,
Multiplexing, Electrical and Mechanical Information
R01UH0750EJ****
(this manual)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group User’s Manual: System Control and Peripheral
R01UH0751EJ****
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group User’s Manual: Peripherals
R01UH0752EJ****
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group User’s Manual: R-IN Engine and Ethernet
Peripherals
R01UH0753EJ****
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group User’s Manual: PWMTimer
R01UH0913EJ****
2. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the
meanings of the bit settings. The standard format and notation for bit charts and tables are described below.
X.X.X
[Register Name]
Address:
Bit
Value after reset
Table X.X
(2)
XXXX XXXXh
b15
b14
b13
—
—
—
0
0
0
b12
b11
b10
b9
b8
[Bit Field]
0
1
0
0
0
b7
b6
—
—
0
0
b5
b4
b3
b2
b1
b0
[Bit Field]
—
[Bit]
[Bit]
[Bit]
0
0
1
1
0
0
[Register Name] Register Contents
Bit Position
Bit Name
Function
R/W
b12 to b8
[Bit Field]
[Description]
R/W
b5 to b4
[Bit Field]
[Description]
2’b00: Hi-Z
R/W
(3)
2’b01: L Output
Others: Prohibited
b2
[Bit]
[Description]
R/W
1’b0: H-Z
1’b1: Output (defult)
b1
[Bit]
[Description]
1’b0: H-Z
(1)
R/W
1’b1: Output (defult)
b0
[Bit]
[Description]
R/W
1’b0: H-Z
1’b1: Output
(1) R/W:
The bit or field is readable and writable.
R/(W):
The bit or field is readable and writable. However, writing to this bit or field has some
limitations. For details on the limitations, see the description or notes of respective registers.
R:
The bit or field is readable. Writing to this bit or field has no effect.
W:
The bit or field is writable. Reading to this bit or field is not guaranteed.
(2) Reserved. Make sure to use the specified value when writing to this bit or field; otherwise, the correct
operation is not guaranteed.
(3) Setting prohibited. The correct operation is not guaranteed if such a setting is performed.
3. List of Abbreviations and Acronyms
Abbreviation
Full Form
AHB
Arm Advanced High-performance Bus
APB
Arm Advanced Peripheral Bus
AXI
Arm Advanced eXtensible Interface
bps
bits per second
CA7
Arm Cortex-A7 module
CM3
Arm Cortex-M3 module
CRC
Cyclic Redundancy Check
DMA
Direct Memory Access
DMAC
Direct Memory Access Controller
Hi-Z
High Impedance
HSR
High-availability Seamless Redundancy
HW-RTOS
Hard Ware Real Time OS
I/O
Input/Output
INTC
Interrupt Controller
LSB
Least Significant Bit
MSB
Most Significant Bit
NC
Non-Connect
NoC
Network-on-Chip
PLL
Phase Locked Loop
PWM
Pulse Width Modulation
UART
Universal Asynchronous Receiver/Transmitter
OTP
One Time Programmable
PTP
Precision Time Protocol
PRP
Parallel Redundancy Protocol
SoC
System On Chip
4. Description of the Access Size
Access size:
8 bits = Byte
16 bits = Halfword
32 bits = Word
CAN(Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.
Arm is a registered trademark of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
Section 1 General Architecture ......................................................................................... 13
1.1
Device Overview ............................................................................................................................. 13
1.2
Outline of Specifications ................................................................................................................. 14
1.3
Function Comparison per Device Family and Package ................................................................. 22
1.4
List of Products ............................................................................................................................... 23
1.5
Block Diagram ................................................................................................................................ 24
Section 2 Address Space.................................................................................................. 27
2.1
2.2
Memory Map ................................................................................................................................... 27
2.1.1
RZ/N1D ................................................................................................................................ 27
2.1.2
RZ/N1S ................................................................................................................................ 29
2.1.3
RZ/N1L ................................................................................................................................. 31
Register Map Summary .................................................................................................................. 32
Section 3 Clock Generation .............................................................................................. 34
3.1
Overview ......................................................................................................................................... 34
3.2
Clock Gating ................................................................................................................................... 36
3.3
Clock Multiplexing ........................................................................................................................... 36
3.4
Clock Division ................................................................................................................................. 37
3.5
Clock Frequency Scaling ................................................................................................................ 38
3.6
Clock Oscillator Connection ........................................................................................................... 41
3.6.1
Main Clock Oscillator ........................................................................................................... 41
3.6.1.1
Connected a Crystal Resonator................................................................................ 41
3.6.1.2
External Clock Input .................................................................................................. 41
3.6.2
RTC Clock Oscillator ............................................................................................................ 42
3.6.2.1
Connected a Crystal Resonator................................................................................ 42
3.6.2.2
Unused RTC on the System ..................................................................................... 42
Section 4 Reset ................................................................................................................ 43
4.1
Overview ......................................................................................................................................... 43
4.2
Chip-level Reset ............................................................................................................................. 44
4.3
4.2.1
Master Reset ........................................................................................................................ 44
4.2.2
System Reset ....................................................................................................................... 44
4.2.3
JTAG Reset.......................................................................................................................... 44
Module Reset.................................................................................................................................. 45
Section 5 IO Multiplexing .................................................................................................. 46
5.1
Overview ......................................................................................................................................... 46
5.2
Register Map .................................................................................................................................. 49
5.3
Register Description ....................................................................................................................... 50
5.3.1
rGPIOs_Level1_ConfigA_[n] — GPIO[n] RGMII Multiplexing Level1 Configuration
Register (n = 0..59) .............................................................................................................. 50
5.3.2
rGPIOs_Level1_ConfigB_[n] — GPIO[n] Standard Multiplexing Level1 Configuration
Register (n = 60..169 (max)) ................................................................................................ 51
5.3.3
rGPIOs_Level1_StatusProtect — GPIO Multiplexing Level1 Status and Protect
Register ................................................................................................................................ 52
5.3.4
rGPIOs_Level2_Config_[n] — GPIO[n] Multiplexing Level2 Configuration Register
(n = 0..169 (max)) ................................................................................................................ 53
5.3.5
rGPIOs_Level2_StatusProtect — GPIO Multiplexing Level2 Status and Protect
Register ................................................................................................................................ 54
5.4
5.3.6
rGPIOs_Level2_Config_MDIO1 — MDIO1 Interface Configuration Register ..................... 55
5.3.7
rGPIOs_Level2_Config_MDIO2 — MDIO2 Interface Configuration Register ..................... 56
5.3.8
rGPIOs_Level2_Gpio_Int_[n] — GPIO_Int[n] Interrupt Configuration Register (n = 0..7) ... 57
Operation ........................................................................................................................................ 58
5.4.1
Protected Access of GPIOs Level1 Configuration Register ................................................ 58
5.4.2
Protected Access of GPIOs Level2 Configuration Register ................................................ 59
5.4.3
Configuration of GPIO Interrupt Line ................................................................................... 60
Section 6 System Control ................................................................................................. 61
6.1
Overview ......................................................................................................................................... 61
6.2
Register Map .................................................................................................................................. 61
6.3
Register Description ....................................................................................................................... 65
6.3.1
PWRCTRL_SWITCHDIV — Clock Divider Control for A5PSW .......................................... 65
6.3.2
PWRCTRL_OPPDIV — Clock Divider Control for OPP Modes .......................................... 66
6.3.3
PWRCTRL_CA7DIV — Clock Divider Control for CA7 ....................................................... 67
6.3.4
PWRCTRL_PG1_PR2DIV — Clock Divider Control for PG1 Program2 ............................. 68
6.3.5
PWRCTRL_PG1_PR3DIV — Clock Divider Control for PG1 Program3 ............................. 69
6.3.6
PWRCTRL_PG1_PR4DIV — Clock Divider Control for PG1 Program4 ............................. 70
6.3.7
PWRCTRL_PG4_PR1DIV — Clock Divider Control for PG4 Program1 ............................. 71
6.3.8
PWRCTRL_QSPI1DIV — Clock Divider Control for QSPI1 ................................................ 72
6.3.9
PWRCTRL_SDIO1DIV — Clock Divider Control for SDIO1 ................................................ 73
6.3.10
PWRCTRL_SDIO2DIV — Clock Divider Control for SDIO2 ................................................ 74
6.3.11
PWRCTRL_PG0_ADCDIV — Clock Divider Control for PG0 ADC..................................... 75
6.3.12
PWRCTRL_PG0_I2CDIV — Clock Divider Control for PG0 I2C......................................... 76
6.3.13
PWRCTRL_PG0_UARTDIV — Clock Divider Control for PG0 UART ................................ 77
6.3.14
PWRCTRL_NFLASHDIV — Clock Divider Control for NAND FLASH Controller ............... 78
6.3.15
PWRCTRL_HWRTOS_MDCDIV — Clock Divider Control for HW-RTOS GMAC MDC
Clock .................................................................................................................................... 79
6.3.16
PWRCTRL_QSPI2DIV — Clock Divider Control for QSPI2 ................................................ 80
6.3.17
PWRCTRL_SDIO1 — Power Management Control for SDIO1 ........................................... 81
6.3.18
PWRSTAT_SDIO1 — Power Management Status for SDIO1 ............................................ 82
6.3.19
SYSSTAT — System Status Flags Register ....................................................................... 83
6.3.20
PWRCTRL_USB — Power Management Control for USB2.0 ............................................ 84
6.3.21
PWRSTAT_USB — Power Management Status for USB2.0 .............................................. 85
6.3.22
PWRCTRL_MSEBI — Power Management Control for MSEBI .......................................... 86
6.3.23
PWRSTAT_MSEBI — Power Management Status for MSEBI ........................................... 87
6.3.24
PWRCTRL_PG0_0 — Power Management Control #0 for PG0 ......................................... 88
6.3.25
PWRSTAT_PG0 — Power Management Status for PG0.................................................... 90
6.3.26
PWRCTRL_PG0_1 — Power Management Control #1 for PG0 ......................................... 91
6.3.27
PWRCTRL_PG1_1 — Power Management Control #1 for PG1 ......................................... 92
6.3.28
PWRCTRL_PG1_2 — Power Management Control #2 for PG1 ......................................... 94
6.3.29
PWRCTRL_DMA — Power Management Control for DMAC1 & DMAC2........................... 95
6.3.30
PWRCTRL_NFLASH — Power Management Control for NAND FLASH Controller .......... 96
6.3.31
PWRCTRL_QSPI1 — Power Management Control for QSPI1 ........................................... 97
6.3.32
PWRSTAT_DMA — Power Management Status for DMAC1 & DMAC2 ............................ 98
6.3.33
PWRSTAT_NFLASH — Power Management Status for NAND FLASH Controller ............ 99
6.3.34
PWRSTAT_QSPI1 — Power Management Status for QSPI1 ...........................................100
6.3.35
PWRCTRL_DDRC — Power Management Control for DDR Memory Controller .............101
6.3.36
PWRCTRL_EETH — Power Management Control for External Ethernet Clock ...............102
6.3.37
PWRCTRL_MAC1 — Power Management Control for GMAC1 .......................................103
6.3.38
PWRCTRL_MAC2 — Power Management Control for GMAC2 .......................................104
6.3.39
PWRSTAT_DDRC — Power Management Status for DDR Memory Controller ...............105
6.3.40
PWRSTAT_MAC1 — Power Management Status for GMAC1 .........................................106
6.3.41
PWRSTAT_MAC2 — Power Management Status for GMAC2 .........................................107
6.3.42
PWRCTRL_ECAT — Power Management Control for ETHERCAT .................................108
6.3.43
PWRCTRL_SERCOS — Power Management Control for SERCOSIII .............................109
6.3.44
PWRSTAT_ECAT — Power Management Status for ETHERCAT ...................................110
6.3.45
PWRSTAT_SERCOS — Power Management Status for SERCOSIII ..............................111
6.3.46
PWRCTRL_HSR — Power Management Control for HSR ...............................................112
6.3.47
PWRCTRL_QSPI2 — Power Management Control for QSPI2 .........................................113
6.3.48
PWRSTAT_HSR — Power Management Status for HSR .................................................114
6.3.49
PWRSTAT_QSPI2 — Power Management Status for QSPI2 ...........................................115
6.3.50
PWRSTAT_SWITCH — Power Management Status for A5PSW .....................................116
6.3.51
RSTSTAT — Reset Status Register ..................................................................................117
6.3.52
USBSTAT — Status information for USBPLL ....................................................................118
6.3.53
PWRCTRL_SDIO2 — Power Management Control for SDIO2 .........................................119
6.3.54
PWRSTAT_SDIO2 — Power Management Status for SDIO2 ..........................................120
6.3.55
PWRCTRL_PG2_25MHZ — Power Management Control for PG2 25MHz......................121
6.3.56
PWRCTRL_PG1_PR2 — Power Management Control for PG1 Program2 ......................122
6.3.57
PWRCTRL_PG3_48MHZ — Power Management Control for PG3 48MHz......................124
6.3.58
PWRCTRL_PG4 — Power Management Control for PG4 ................................................125
6.3.59
PWRCTRL_PG1_PR3 — Power Management Control for PG1 Program3 ......................126
6.3.60
PWRCTRL_PG1_PR4 — Power Management Control for PG1 Program4 ......................127
6.3.61
PWRCTRL_PG4_PR1 — Power Management Control for PG4 Program1 ......................128
6.3.62
RSTEN — Reset Enable Register .....................................................................................129
6.3.63
PWRCTRL_SWITCH — Power Management Control for A5PSW ...................................130
6.3.64
PWRCTRL_RTC — Power Management Control for RTC ...............................................131
6.3.65
PWRSTAT_RTC — Power Management Status for RTC .................................................132
6.3.66
PWRCTRL_ROM — Power Management Control for ROM .............................................133
6.3.67
PWRSTAT_PG1 — Power Management Status for PG1..................................................134
6.3.68
PWRSTAT_PG2_25MHZ — Power Management Status for PG2 25MHz .......................136
6.3.69
PWRSTAT_PG3_48MHZ — Power Management Status for PG3 48MHz .......................137
6.3.70
PWRSTAT_PG4 — Power Management Status for PG4..................................................138
6.3.71
PWRSTAT_ROM — Power Management Status for ROM ...............................................139
6.3.72
PWRCTRL_CM3 — Power Management Control for CM3 ...............................................140
6.3.73
PWRSTAT_CM3 — Power Management Status for CM3 .................................................141
6.3.74
PWRSTAT_RINCTRL — Power Management Status for R-IN Engine Accessory
Register ..............................................................................................................................142
6.3.75
PWRSTAT_SWITCHCTRL — Power Management Status for Ethernet Accessory
Register ..............................................................................................................................143
6.3.76
PWRCTRL_RINCTRL — Power Management Control for R-IN Engine Accessory
Register ..............................................................................................................................144
6.3.77
PWRCTRL_SWITCHCTRL — Power Management Control for Ethernet Accessory
Register ..............................................................................................................................145
6.3.78
PWRCTRL_HWRTOS — Power Management Control for HW-RTOS .............................146
6.3.79
RSTCTRL — Reset Control Register ................................................................................147
6.3.80
CFG_USB — USB Mode Configuration Register ..............................................................148
6.3.81
OPMODE — System and Boot Configuration Register .....................................................149
6.3.82
CFG_SDIO[m] — SDIO[m] Configuration Register (m = 1 or 2) .......................................150
6.3.83
DBGCON — Debug Control Register ................................................................................151
6.3.84
CFG_GPIOT_PTEN_xx — GPIO Trigger Enable Register ...............................................152
6.3.85
CFG_GPIOT_TSRC — GPIO Trigger Source Select Register .........................................153
6.3.86
CFG_DMAMUX — DMAC1 & DMAC2 Multiplexer Register .............................................154
6.3.87
VERSION — Product Version Register .............................................................................157
6.3.88
BOOTADDR — Cortex-A7 processor1 Boot Address Configuration Register ..................157
Section 7 Operating Modes ............................................................................................ 158
7.1
Overview .......................................................................................................................................158
7.2
Boot Mode Specification (for RZ/N1D and RZ/N1S) ....................................................................159
7.3
7.2.1
Common Feature ...............................................................................................................159
7.2.2
QSPI Boot Feature .............................................................................................................159
7.2.3
NAND Boot Feature ...........................................................................................................160
7.2.4
USB Boot Feature ..............................................................................................................161
Standard Boot Sequence .............................................................................................................162
7.3.1
Overview ............................................................................................................................162
7.3.2
External Pin Configuration .................................................................................................162
7.3.3
CPU Booting ......................................................................................................................163
7.3.4
RZ/N1D and RZ/N1S Boot .................................................................................................164
7.3.5
RZ/N1L Boot ......................................................................................................................164
7.4
7.5
SPKG Format (for RZ/N1D and RZ/N1S) .....................................................................................165
7.4.1
Overview ............................................................................................................................165
7.4.2
Implementation Specifics ...................................................................................................165
RZ/N1 Initialize Sequence ............................................................................................................168
7.5.1
Standard Initialize Sequence .............................................................................................168
7.5.2
USBPLL Setting .................................................................................................................168
7.5.3
Activating Cortex-M3 ..........................................................................................................168
7.5.4
Generic Programming Sequence for NoC .........................................................................169
Section 8 Ethernet Interface Modes ................................................................................ 174
8.1
Overview .......................................................................................................................................174
8.2
Support Modes .............................................................................................................................176
8.3
8.4
8.2.1
Internal Connection of Ethernet Ports ................................................................................180
8.2.2
Selection of clocks for PTP ................................................................................................181
Operation ......................................................................................................................................183
8.3.1
Initializing ...........................................................................................................................183
8.3.2
ETHMODE_SET ................................................................................................................184
Usage Notes .................................................................................................................................185
8.4.1
Restriction ..........................................................................................................................185
8.4.1.1
Supported Ethernet Signals ....................................................................................185
Section 9 Interrupts ......................................................................................................... 186
9.1
9.2
Overview .......................................................................................................................................186
9.1.1
Cortex-A7 GICv2 ................................................................................................................186
9.1.2
Cortex-M3 NVIC .................................................................................................................186
Operation ......................................................................................................................................187
9.2.1
IRQ Synchronization ..........................................................................................................187
9.2.2
Non Maskable Interrupt ......................................................................................................187
9.2.3
Interrupt Management on Cortex-A7 and Cortex-M3 ........................................................188
9.2.4
Interrupts Allocation and Vector Number ...........................................................................189
Section 10
IOs ............................................................................................................. 193
10.1
Pinout Description.........................................................................................................................193
10.2
Handling of Unused Pins ..............................................................................................................199
10.3
Pinout ............................................................................................................................................200
10.3.1
RZ/N1D BGA-400 Package ...............................................................................................200
10.3.2
RZ/N1D BGA-324 Package ...............................................................................................201
10.3.3
RZ/N1S BGA-324 Package ...............................................................................................202
10.3.4
RZ/N1S BGA-196 Package ...............................................................................................203
10.3.5
RZ/N1L BGA-196 Package ................................................................................................204
Section 11
11.1
Electrical Characteristics ............................................................................ 205
Absolute Maximum Ratings ..........................................................................................................205
11.2
Recommended Operating Conditions ..........................................................................................206
11.3
DC Characteristics ........................................................................................................................207
11.4
11.5
11.3.1
Current ...............................................................................................................................207
11.3.2
Digital IO ............................................................................................................................208
11.3.3
DDR3/DDR2 SDRAM Interface .........................................................................................208
Power-up/down Sequence ...........................................................................................................209
11.4.1
Power-up ............................................................................................................................209
11.4.2
Power-down .......................................................................................................................209
AC Timing Characteristics ............................................................................................................210
11.5.1 Ether MAC Interface Timing...............................................................................................210
11.5.1.1 RGMII ......................................................................................................................210
11.5.1.2 RMII ........................................................................................................................211
11.5.1.3 MII ...........................................................................................................................212
11.5.1.4 MDIO .......................................................................................................................213
11.5.2 Memory Interface Timing ...................................................................................................214
11.5.2.1 QSPI Flash Interface...............................................................................................214
11.5.2.2 DDR3/DDR2 Interface ............................................................................................215
11.5.2.3 NAND Flash Interface .............................................................................................218
11.5.2.4 SD/MMC/SDIO Interface ........................................................................................219
11.5.3 Serial Interface Timing .......................................................................................................221
11.5.3.1 UART ......................................................................................................................221
11.5.3.2 SPI Master ..............................................................................................................222
11.5.3.3 SPI Slave ................................................................................................................223
11.5.3.4 I2C...........................................................................................................................224
11.5.3.5 CAN ........................................................................................................................225
11.5.3.6 JTAG/SWD .............................................................................................................226
11.5.4
LCD Interface Timing .........................................................................................................227
11.5.5
MSEBI Interface Timing .....................................................................................................228
11.6
ADC Characteristics .....................................................................................................................230
11.7
RTC Oscillator Characteristics .....................................................................................................230
Section 12
12.1
Mechanical Characteristics ........................................................................ 231
Package Information .....................................................................................................................231
12.1.1
BGA-400 Package .............................................................................................................231
12.1.2
BGA-324 Package .............................................................................................................232
12.1.3
BGA-196 Package .............................................................................................................233
Appendix A
Pin Assignment .......................................................................................... 234
Appendix B
IO Multiplexing Assignment ....................................................................... 243
Appendix C Clock Tree Structure .................................................................................. 247
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 1
1.1
Section 1 General Architecture
General Architecture
Device Overview
On-Chip 32-bit Arm® Cortex®-A7 MPCore
Peripherals
● Up to 500 MHz
● CPU resources
● Single or Dual core
− Mailbox
● FPU, VFPv4-D16
− 2 × Timer block (16bit × 6ch, 32bit × 2ch)
− 1 × PWMTimer (16bit × 16ch)
● MMU
● L1 cache: 16 KB (instruction)/16 KB (data) per core
● L2 cache: up to 256 KB
On-Chip 32-bit Arm® Cortex®-M3 Processor
● Up to 125 MHz
− 1 × Watchdog per CPU
− Semaphore
● General Connectivity
− 1 × USB2.0 Host
− 1 × USB2.0 Host & Function
● Memory Protection Unit (MPU) supported
Low Power Features
● Clock gating management
● Clock frequency scaling
On-Chip Extended SRAM
● Up to 6 MB with ECC
− 8 × UART
− 6 × SPI (4 masters/2 slaves)
− 2 × I2C
− 2 × CAN
− Up to 2 × 12-bit ADC (up to 1 MSPS)
− MSEBI (Parallel Bus Interface)
● Other features
− LCD controller
Data Transfer
● 2 × DMAC with 8 channels each
Memory Interfaces
● Up to 2 × Quad SPI/XIP
● NAND Flash with advanced ECC management
● 16-bit DDR interface (DDR2-500/DDR3-1000)
● Up to 2 × SD/SDIO/eMMC
IO Multiplexing Controller
● Locations of I/Os for peripherals are selectable from
multiple pins
− GPIO pins (up to 170)
R-IN Engine
● Arm® Cortex®-M3 CPU
● Hardware RTOS accelerator (HW-RTOS)
● Hardware Ethernet accelerator
Advanced real-time Ethernet features
● Sercos®*1III Slave Controller
● EtherCAT®*2 3 ports slave controller
● Advanced 5 (4 + 1) Port Switch (A5PSW)
− Switch 5 ports with QoS and IEEE1588
Clock Oscillator
Up to 5 Gbit ports
● External clock/oscillator input frequency: 40 MHz
● RTC with 32 kHz oscillator
Security functions (option)
● Secure Boot/JTAG Lock/64bit Chip-ID
− PRP compliant to IEC62439-3 Ed2.0- 2012
(option)
● HSR compliant to IEC62439-3 Ed2.0-2012 (option)
● Up to 2 independent GMAC, IEEE1588
● Up to 5 external ports with MII/RMII/RGMII
Note 1.
Sercos is a registered trademark of Sercos International e.V.
Note 2.
EtherCAT is registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.
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1.2
Section 1 General Architecture
Outline of Specifications
Table 1.1
Outline of Specifications (1/8)
Classification
Module/Function
Description
CPU
Arm Cortex-A7
●
●
●
●
●
●
●
●
●
●
Arm 32-bit CPU Cortex-A7 (Revision r0p5)
●
●
●
●
Arm 32-bit CPU Cortex-M3 (Revision r2p1)
Arm Cortex-M3
Memory
Dual core or single core
Maximum operating frequency: 500 MHz
Clock frequency scaling
L1 cache: 16 KB (instruction)/16 KB (data) per core
L2 cache: up to 256 KB
FPU, VFPv4-D16
MMU
Hardware coherent caches
Little endian
Maximum operating frequency: 125 MHz
Memory Protection Unit (MPU)
Little endian
On-chip 2MB SRAM
● Capacity: 2 MB (1MB + 1MB)
● Separated access ports per 512 KB unit
● SEC-DED (Single Error Correction, Double Error Detection)
On-chip 4MB SRAM
● Capacity: 4 MB
● Separated access ports per 1 MB unit
● SEC-DED (Single Error Correction, Double Error Detection)
● Free running 12-bit decrementing counters with reload register
● Output can be used to activate a system reset or as an interrupt
● Stop of watchdog effect while CPU is being stopped by debugger (e.g. by
Watchdog
breakpoint execution)
● Three boot modes (CA7)
Operating Modes
– NAND Flash
– QSPI Flash
– USB DFU
Clock
Clock Generation Circuit
RTC
Input 40 MHz clock selectable from an oscillator or crystal
●
●
●
●
●
Time-of-day clock in 24-hour mode
System clock up to 125 MHz
Cortex-A7 clock x1/x2/x4 with system clock
DDR memory clock 250 MHz/500 MHz
Calendar
Alarm capability
XTAL 32 kHz
Separate and isolated power supply for RTC backup mode
● Master Reset input
● Internal System Reset (Software, watchdog)
Reset
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●
●
●
Rev.1.40
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Table 1.1
Section 1 General Architecture
Outline of Specifications (2/8)
Classification
Module/Function
Description
Data Transfer
Direct Memory Access
Controller (DMAC)
● 2 units:
– 8 channels, 16 request sources for DMAC1
– 8 channels, 16 request sources for DMAC2
● Memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers
● Transfer width:
– 8, 16, 32, 64 bits
● Programmable DMA burst size
● 3x programmable mailboxes
Mailbox
– 7× 32-bit data registers per mailbox
● Hardware lock mechanism of internal shared resources
Semaphore
Parallel Bus
Interface
Medium Speed External
Bus Interface (MSEBI)
● Master and slave modes
– Data bus width selectable from 8, 16 and 32 bits
● Address/data/control-data are multiplexed on data bus
● Burst mode
● DMA Support
– Master mode: Coupling with 4 DMA channels (external request reception
capability)
– Slave Mode: External request transmission capability
●
●
●
●
Up to 4 chip selects
Programmable address capability from 2B to 4GB
Programmable setup and hold time
External wait request
I/O Ports
IO Multiplexing
● Locations of IOs for peripherals are selectable
● Output drive strength selectable
● On-chip Pull-up/Pull-down select
Memory Interfaces
DDR2/3 Controller
●
●
●
●
●
●
●
●
●
DDR2-500/DDR3-1000
Programmable memory data path size: 16 bits, 8 bits, 8+ECC bits
Up to 2 chip selects and 2 ODT
Up to 2 GB address capability
ECC SEC/DED software configurable (enable/disable)
Programmable on die termination
Configurable impedance drive and slew rate
DDR2/DDR3 low power control management (by software)
Port Address Protection Check
– Up to 16 address protection regions per port
NAND Flash Controller
●
●
●
●
●
●
●
●
NAND interface with 8-bit bus width
Support for asynchronous mode
4 chip selects
Write protection
Programmable address cycle (0/1/2/3/4/5)
Integrated DMA
Support for 256 B, 512 B, 2 KB, 1 KB, 4 KB, 8 KB, 16 KB pages
BCH ECC (Error detection and data correction)
– ECC data block size: 256 B, 512 B, 1024 B
– ECC correction capability: 2, 4, 8, 16, 24, 32 bits errors
● Bad Block Management (BBM)
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Table 1.1
Section 1 General Architecture
Outline of Specifications (3/8)
Classification
Module/Function
Description
Memory Interfaces
Quad SPI (QSPI)
●
●
●
●
●
●
●
●
●
●
●
●
Up to 2 units
Single, dual or quad I/O instructions supported
Supported read performance enhanced mode (NoCMD mode)
Remap address direct access
Programmable device sizes
Up to 4 chip selects
Support for 1/2/3/4 byte addressing
Support for programmable page size (default 256 bytes)
Support for programmable number of bytes per device block
Programmable write protected regions
Transmit and receive FIFOs are 16 bytes
Legacy mode allowing software direct access to low level transmit and receive
FIFOs
● Set of control registers to perform any FLASH command
● Support for write burst in direct access
SD/SDIO/eMMC
● Up to 2 units
● SD/SDIO Card interface
– Transfers data in 1 bit or 4 bits mode
– Transfers data in Default or High Speed mode
● eMMC interface
– Transfers data in 1 bit, 4 bits, or 8 bits mode
● Speeds
– Default mode up to 25 MHz
– High Speed mode up to 50 MHz
● Support for PIO/SDMA/ADMA2 transfer
Networking
Elements
R-IN Engine
● ITRON-like system calls
– 30 system calls for elements such as events, semaphores, and mailboxes
● Task Scheduler
– Hardware ISR: Maximum 32 selectable from 128 interrupts
– Number of context elements: 64
– Number of semaphore identifiers: 128
– Number of event identifiers: 64
– Number of mailbox identifiers: 64
– Number of mailbox elements: 192
– Number of context priority levels: 16
●
●
●
●
●
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Hardware function manager
Internal DMA controller
Buffer allocator
Header EnDec
Dedicated Gigabit Ethernet MAC (with built-in MACDMAC)
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Table 1.1
Section 1 General Architecture
Outline of Specifications (4/8)
Classification
Module/Function
Description
Networking
Elements
Advanced 5 Port Switch
● Operation modes:
– 10 Mbps half- and full-duplex
– 100 Mbps half- and full-duplex
– 1000 Mbps full-duplex only
●
●
●
●
●
MAC based RMON statistics counters/per port
Port statistics on per port basis (no aggregation)
Look-up table up to 8192 MAC addresses (static and learned)
Packet buffer size: 1 Mbit
4 queues with individual QoS levels, supporting frame priority classification for the
flexible handling of output queues
– Optional arbitration management through weighted fair queuing
● Support for Ethernet multicast and broadcast frames with flooding control to avoid
unnecessary duplication of frames
● Programmable multicast destination port mask to restrict frame duplication for
individual multicast addresses
● IEEE 1588-2008 compatible
– Support for 1 step Peer-to-Peer (P2P) (Layer 2 only)
– Support for 1 step End-to-End (E2E) (Layer 2 only)
● Multicast and broadcast resolution with VLAN domain filtering providing a strict
separation of up to 32 VLANs
● Support for reception and transmission of VLAN frames
● Programmable addition, removal and manipulation of ingress and egress VLAN
tags, supporting single and double-tagged VLAN frames on each port
● Support for standard frame size (1536 bytes), extended frame sizes up to 1700
bytes and jumbo frames up to 10 Kbytes
● Port mirroring programmable per port
● RSTP port states (3 for RSTP/ 5 for STP)
– RSTP Port states learning, discarding, forwarding configurable per port
– BPDU frame supported
– MSTP BPDU frame supported (software)
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
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Frame snooping engine
Standalone Energy-Efficient-Ethernet (EEE) management
Programmable egress rate limit per port
Ingress Configurable Broadcast storm protection per port
Ingress Configurable Multicast storm protection per port
802.1X source address authentication supported
802.1X guest VLAN supported
PRP functionality (IEC 62439-3 edition 2.0- 2012)
DLR module
Cut-through
TDMA (Time Division Multiple Access) 4 time slots
Pattern Matchers 8 channels
Remote monitoring via SNMP and the (RMON/MIB)
Hub function
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Table 1.1
Section 1 General Architecture
Outline of Specifications (5/8)
Classification
Module/Function
Description
Networking
Elements
HSR Switch
● HSR functionality (IEC 62439-3 edition 2.0- 2012)
– DANH
– Redundancy Box (Red Box)
– Generation of redundant transmit frames
– Filtering of duplicated received frames
– Redundancy header generation and detection
– Table to keep track of received frames
EtherCAT Slave
Controller
SercosIII Slave Controller
●
●
●
●
●
●
●
●
●
●
●
●
●
●
100 Mbps full-duplex Ethernet
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Up to 3 ports
Dynamic frame buffer allocation (page manager)
128 proxy nodes (VDANs) supported
Support for link-local protocols
Duplicate detection memory
MAC address filtering
1× VLAN tag supported
Port statistics on per port basis (no aggregation)
144 KB frame buffer
IEEE 1588-2008
Support for Ethernet multicast frames with flooding control
Extended frame size: up to 2000 bytes (Jumbo frames not supported)
Support for a minimum of 16 nodes in an HSR loop
Configurable duplicate detection residence time
Automatic TX Shift
Enhanced Link Detection
8 FMMU (Fieldbus Memory Management Unit)
8 SyncManagers
64-bit Distributed Clocks
Mapping to global IRQ
Read/Write Offset
Write Protection
AL Status Code Register
Extended Watchdog
AL Event Mask Register
Watchdog Counter
SyncManager Event Times
EPU Error Counter
Lost Link Counter
I2C interface for external EEPROM
● 2 ports
● The serial interface operates with 100 Mbaud
● Telegram processing for automatic transmission, and monitoring of
synchronization telegrams and data telegrams
● Switch over function between Sercos protocol and standard Ethernet protocol via
multiplexer
● Monitors the received data stream to detect the frame type and starts operation
when SercosIII frame type is detected
● Handling of the data transfers to and from SRAM based on telegram type
(MST/MDT or AT)
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Table 1.1
Section 1 General Architecture
Outline of Specifications (6/8)
Classification
Module/Function
Description
Networking
Elements
Independent GMAC
● 2× MAC instances (GMAC1, GMAC2)
● Compliance with the following standards:
– IEEE 1588-2008 v2 standard for precision networked clock synchronization
– IEEE 1588-2008 v2 is compliant with Power IEEE C37.238 profile
– IEEE 802.3-az-2010 for Energy Efficient Ethernet (EEE)
● Support for 10/100/1000 Mbps data transfer rates
● Support for both half-duplex and full-duplex operation
● Programmable frame length to support both standard and “jumbo” Ethernet frames
●
●
●
●
●
with size up to 16 Kbytes (16KB-1)
17 MAC address registers for the address filter block
Variety of flexible addresses filtering modes are supported
Native DMA with simple-independent channels for transmit and receive engines
Advanced IEEE 1588-2002 & 2008 Ethernet frame time-stamping supported
Provides the flexibility to control the Pulse-Per-Second (PPS) output signal
(GMAC1 only)
● Programmable CRC generation and checking
● Support for RMON statistics (L2 layer only)
● Station Management Block, MDIO interface
Subsystem
Elements
USB2.0 HOST
● 1 dedicated port + 1 configurable port (Host or Function)
● Supports:
– High speed (HS): 480 Mbps (USB 2.0)
– Full speed (FS): 12 Mbps (USB 1.1)
– Low speed (LS): 1.5 Mbps (USB 1.1)
●
●
●
●
●
USB2.0 Function
USB Plug Detect (UPD)
Output port power switch management
Overcurrent indication from application
Integrated DMA
Transmit and receive FIFOs
● 1 configurable port (Host or Function)
● Supports:
– High speed (HS): 480 Mbps (USB 2.0)
– Full speed (FS): 12 Mbps (USB 1.1)
UART 1, 2, 3
UART 4, 5, 6, 7, 8
●
●
●
●
USB Plug Detect (UPD) which detects the connection of a host via VBUS
●
●
●
●
●
●
●
●
Compliant with 16550 UART
16 physical endpoints
Integrated DMA
Endpoint buffer
Separate 16×8 (16 location depth × 8-bit width) transmit and 16×8 receive FIFOs
RS485 & MODBUS® enhanced features
Baud rate generation up to 5.2 Mbaud
Generation and detection of line breaks
Programmable hardware flow control
Auto Flow Control mode as specified in the 16750 standard
Supports TXD, RXD, CTS_N, RTS_N, DTR_N, DSR_N, DCD_N, RI_N
● In addition to UART 1, 2, 3, the following function is available:
– DMA coupling with burst-mode management
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Table 1.1
Section 1 General Architecture
Outline of Specifications (7/8)
Classification
Module/Function
Description
Subsystem
Elements
SPI 1, 2, 3, 4
●
●
●
●
●
(Master)
Transmit and receive FIFOs (16×16)
Programmable RXD sampling logic
Programmable data-size for frames (from 4 to 16 bits)
4 chip selects
DMA controller interface
(Slave)
● Transmit and receive FIFOs (16×16)
● Programmable data-size for frames (from 4 to 16 bits)
● DMA controller interface
I2C 1, 2
● Two speeds:
SPI 5, 6
– Standard mode (0 to 100 Kbps)
– Fast mode (≤ 400 Kbps)
CAN 1, 2
General Purpose
Timers(Timer)
●
●
●
●
●
●
Separated 8×8 transmit and 8×8 receive FIFOs
●
●
●
●
●
●
●
●
●
●
●
Supports both 11-bit and 29-bit identifiers
Master or slave I2C operation
7- or 10-bit addressing
7- or 10-bit combined format transfers
Bulk transmit mode
Programmable SDA hold time (tHD; DAT)
Supports bit rates from 125 Kbps to 1 Mbps
Acceptance filtering
Software-driven bit-rate detection (offering hot plug-in support)
Single-shot transmission option, listen-only mode, reception of ‘own’ messages
Arbitration lost interrupt with data of bit position
Read/write error counters
Last error register
Programmable error limit warning
Transmit periodic “Sync frame”
Programmable time base
● 2 units, each supporting:
– 6 programmable 16-bit timers
– 2 programmable 32-bit timers
● Prescaler selectable between 2 time bases
● Auto-reload mode or single-shot mode
● DMA coupling (only for the 32-bit timers)
PWMTimer
● 6 inputs for capture and clock:
– Bounce filter
– 40 external inputs
● 16 outputs for compare match:
– 20 external outputs
● 16 basic 16-bit counters:
– Capture and compare functions
– 32-bit cascaded counter
– Two clock prescalers 10 bit
– Synchronized with other counters
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Table 1.1
Section 1 General Architecture
Outline of Specifications (8/8)
Classification
Module/Function
Description
ADC
ADC
●
●
●
●
Up to 2units
●
●
●
●
●
●
Individual trigger per channel
Resolution 12 bits
Sampling rate from 0.0625 MSPS to 1 MSPS
Analog inputs
– 8 channels: (5ch + 3ch S/H)
DNL, ± 1.0 LSB (Max.) [at VAIN = 0.0 V to AVDD, fCLK = 20 MHz]
INL, ± 4.0 LSB (Max.) [at VAIN = 0.0 V to AVDD, fCLK = 20 MHz]
Power-down mode
Two level of priority
Round-robin management of simultaneous conversion requests with the same
level of priority
● DMA coupling
● Virtual channel capability
Multimedia
LCD Controller
● Programmable LCD Panel resolutions
● Interface for 1 Port TFT LCD Panel:
– 18-bit digital (6 bits/color)
– 24-bit digital (8 bits/color)
● Programmable frame buffer bits per pixel (bpp)
– 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel
– 16, 18, bpp directly drive 18-bit LCD pixel
– 24 bpp directly drive 24-bit LCD pixel
●
●
●
●
Hardware blink supported
Pulse Width Modulation module for LCD panel LED backlight brightness control
Power up and down sequencing supported
Integrated DMA
Security
● Checks the signature of the Secure Boot program
● Disable the JTAG I/F debugging function
● 64bit Chip-ID which can be read by Cortex-A7
Debugging
Interface
●
●
●
●
ETM coupled with JTAG debugger
Single Embedded Trace Buffer (32 KB) shared by Cortex-A7 and Cortex-M3 cores
Arm JTAG
Arm SWD
Power Supply
Voltage
● Core Voltage: 1.15 V ± 0.05 V
● IO voltage: 3.3 V ± 0.3 V
● DDR IO voltage: 1.8 V ± 0.1 V; 1.5 V ± 0.075 V
Operating
Temperature
Junction temperature: −40°C to +110°C
Packages
● RZ/N1D:
– 400LFBGA, 17×17 mm, 0.8 mm pitch
– 324LFBGA, 15×15 mm, 0.8 mm pitch
● RZ/N1S
– 324LFBGA, 15×15 mm, 0.8 mm pitch
– 196LFBGA, 12×12 mm, 0.8 mm pitch
● RZ/N1L
– 196LFBGA, 12×12 mm, 0.8 mm pitch
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 21 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
1.3
Section 1 General Architecture
Function Comparison per Device Family and Package
Table 1.2
Renesas CPU Subsystem Part Description
Hardware Features
RZ/N1D
Package Type:
Processor Unit
Memory Unit
400BGA
Arm Cortex-A7
RZ/N1S
324BGA
324BGA
Dual
Available
2 MB with ECC
Available
DDR Memory Controller
—
Available
—
1ch
2ch
SDIO/SD/eMMC
Available
R-IN Engine & HWRTOS
Available*5
Ethernet Port
5 ports
3 ports*3
5 ports
3 ports*3
Independent GMAC
Up to 2
N/A*
Up to 2
Up to 1*4
4
EtherCAT Slave Controller
Available*6 *7
SercosIII Slave Controller
Available*6 *7
Advanced 5port Switch
PRP
HSR Switch*5 *6
Peripheral Group
ADC
5 ports (4 + 1)
4 ports (3 + 1)
5 ports (4 + 1)
Optional
—
Available
3 ports (2 + 1)*7
—
Optional
—
2unit
1unit
RTC
Available
N/A
DMAC
2ch
UART
8ch
I2C
2ch
Parallel bus Master & Slave*
Available
8
USB Host & Function
Slave only
Available
Mailbox
Available
Watchdog for CA7
N/A
Available, 2
Available, 1
Watchdog for CM3
4ch
SPI Slave
2ch
CAN
2ch
Available
N/A
Semaphore
Available
Timer block
2unit
PWMTimer
Available
170
9
N/A
Available
SPI Master
LCDC
GPIO pin*
1ch*2
2ch
NAND Flash
Networking
elements
—
Available*1
Quad SPI
196BGA
Single
Arm Cortex-M3
4 MB with ECC
RZ/N1L
196BGA
132
160
95
95
Optional
Security
functions*10
Note 1.
RZ/N1D-324 has 1 Chip Select and 1 ODT.
Note 2.
RZ/N1S-196 and RZ/N1L have up to 2 chip selects.
Note 3.
Please refer to Restriction of Ethernet Interface Modes chapter for more details about N/A port numbers.
Note 4.
GMAC2 is available via A5PSW in RZ/N1D-324, RZ/N1S-196 and RZ/N1L.
—
Note 5.
HW-RTOS and HSR are not available simultaneously.
Note 6.
SERCOSIII, ETHERCAT and HSR function are not available simultaneously.
Note 7.
A5PSW, SERCOSIII and ETHERCAT function are not available simultaneously in RZ/N1S-196 and RZ/N1L.
R01UH0750EJ0140
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Rev.1.40
Page 22 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 1 General Architecture
Note 8.
RZ/N1D-324 is not able to use 32-bit mode. RZ/N1S-196 and RZ/N1L are only able to use 8-bit mode and 2 external wait
requests. RZ/N1S-196 is only able to use ALE serial mode in Master.
Note 9.
Shared with peripheral signals.
Note 10. Please contact our sales office for information regarding the optional security functions.
1.4
Table 1.3
Name
RZ/N1D
List of Products
List of Products
P/N
Package(s)
Main CPU
PRP/HSR
Security
R9A06G032VGBG
400BGA
Dual Cortex-A7
―
―
R9A06G032EGBG
R9A06G032VGBA
Available
324BGA
―
R9A06G032EGBA
R9A06G032NGBG
Available
400BGA
PRP/HSR
R9A06G032PGBG
RZ/N1S
R9A06G033VGBA
Available
196BGA
Single Cortex-A7
―
R9A06G033EGBA
R9A06G033NGBG
R9A06G034VGBA
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
―
Available
324BGA
PRP
R9A06G033PGBG
RZ/N1L
―
―
Available
196BGA
Cortex-M3
―
―
Page 23 of 263
Figure 1.1
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
SPI5 (S)
UART8 f
BGPIO2
APB S
32b
APB S
32b
AHB S
32b
LCDC
SEMAP x64
AHB S
32b
AHB M
64b
PG4 (Peripheral Group4)
CAN2
CAN1
bridge
Network
On
Chip
AHB M
64b
AHB S
32b
AHB S
32b
L1 I$
16KB
AHB M
32b
MSEBI S
AHB S
32b
GIC
Parallel interface
MSEBI M
AHB S
32b
AXI M
128b
L1 I$
16KB
Processor1
L1 D$
16KB
FPU/MMU
Cortex-A7
L2$ 256KB
SCU
Processor0
L1 D$
16KB
FPU/MMU
AHB M
32b
AHB M
32b
AHB M
32b
AHB S
32b
AHB S
32b
Con figurable
Arb iter
AHB S
32b
AHB M
32b
AHB S
32b
NAND Flash
AHB S
32b
Con figurable
Arb iter
AHB S
32b
AHB S
32b
Con figurable
Arb iter
RAM_data0
512kB
AHB S
32b
AHB M
64b
DMACs
AHB M
64b
DMAC1
AHB S
32b
AHB S
32b
Mail
box
ROM
64kB
AHB S
32b
AHB M
32b
AHB M
32b
APB S
32b
QSPI
AHB S
32b
GMAC1
AXI M
32b
QSPI 1
AHB S
32b
AHB S
32b
GMAC2
A5PSW
I2C2
(P eriph eral Group0)
PG0
PWMTimer
ConfigSys1
ADC Ctrl
ADC2
ADC1
I2C1
UART3 r
UART2 r
UART1 r
AHB S
32b
ETHERCAT
APB S
32b
AHB S
32b
System Control
System
Controller
WDOGA7_2
WDOGM3
WDOGA7_1
RTC
APB S
32b
AHB S
32b
SERCOSIII
AHB S
32b
HSR
Ethernet Peripherals
Mux
MAC2RTOS
AXI M
32b
USB
Host
AHB S
32b
USB 2.0
USB
Function
AHB S
32b
AHB S
32b
HW-RTOS
GMAC
HW-RTOS
R-IN Engine
Network-On-Chip (NoC)
DMAC2
AHB S
32b
AHB S
32b
Con figurable
Arb iter
RAM_data1
512kB
2MB SRAM
RAM_inst0
512kB
NAND
Controller
AHB S
32b
RAM_inst1
512kB
SD/SDIO/
eMMC2
AHB S
32b
AHB M
32b
SD/SD/eMMC
Host Controller
SD/SDIO/
eMMC1
AHB S
32b
AHB M
32b
VIC
Debug & ETM
Cortex-M3
Arm Cortex-M3
DDR2/3 Controller
AHB M
32b
AXI M
64b
APB S
32b
APB S
32b
AHB S
32b
AXI S
64b
AXI S
64b
AXI S
64b
AXI S
64b
16b DDR2/3 interface
PG3 (Peripheral Group3)
ConfigSys2
TIMER2 x8
TIMER1 x8
PG2 (Peripheral Group2)
BGPIO3
BGPIO1
SPI4 (M)
UART7 f
SPI6 (S)
SPI2 (M)
SPI1 (M)
SPI3 (M)
UART5 f
UART6 f
UART4 f
PG1 (Peripheral Group1)
Arm Cortex-A7
Debug & ETM
1.5
Cortex-A7
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 1 General Architecture
Block Diagram
CoreSight
RZ/N1D Dual Cortex-A7 & Cortex-M3
Page 24 of 263
Figure 1.2
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
SPI3 (M)
SPI4 (M)
SPI5 (S)
UART6 f
UART7 f
UART8 f
BGPIO3
APB S
32b
APB S
32b
AHB S
32b
LCDC
SEMAP x64
AHB S
32b
AHB M
64b
PG4 (Peripheral Group4)
CAN2
CAN1
PG3 (Peripheral Group3)
ConfigSys2
TIMER2 x8
TIMER1 x8
PG2 (Peripheral Group2)
BGPIO2
SPI6 (S)
SPI2 (M)
UART5 f
BGPIO1
SPI1 (M)
UART4 f
PG1 (Peripheral Group1)
bridge
Network
On
Chip
AHB M
64b
AHB S
32b
AHB S
32b
Arm Cortex-A7
AHB M
32b
MSEBI S
AHB S
32b
Parallel interface
MSEBI M
AHB S
32b
AXI M
128b
L2$ 128KB
SCU
GIC
L1 D$
16KB
Processor0
L1 I$
16KB
FPU/MMU
Cortex-A7
Debug & ETM
AHB M
32b
AHB M
32b
AHB M
32b
SD/SDIO/
eMMC2
AHB S
32b
AHB M
32b
SD/SD/eMMC
Host Controller
SD/SDIO/
eMMC1
AHB S
32b
AHB M
32b
VIC
Debug & ETM
Cortex-M3
Arm Cortex-M3
AHB M
32b
AHB S
32b
NAND Flash
NAND
Controller
AHB S
32b
AHB S
32b
Con figurable
Arb iter
RAM_inst1
512kB
AHB S
32b
Con figurable
Arb iter
AHB S
32b
AHB S
32b
Con figurable
Arb iter
AHB M
64b
DMAC1
AHB S
32b
AHB S
32b
Mail
box
ROM
64kB
AHB S
32b
AHBM
32b
AHB M
32b
AHB S
32b
USB
Host
AHB S
32b
USB 2.0
USB
Function
AHB S
32b
AHB S
32b
HW-RTOS
GMAC
HW-RTOS
R-IN Engine
RAM_data0
512kB
Network-On-Chip (NoC)
AHB S
32b
DMACs
DMAC2
AHB M
64b
AHB S
32b
AHB S
32b
AHB S
32b
Con figurable
Arb iter
RAM_data1
512kB
2MB SRAM
RAM_inst0
512kB
QSPI
QSPI 2
APB S
32b
AHB S
32b
GMAC1
A5PSW
AXI M
32b
AHB S
32b
AHB S
32b
APB S
32b
QSPI 1
AHB S
32b
AXI M
32b
GMAC2
Mux
MAC2RTOS
APB S
32b
AHB S
32b
ETHERCAT
I2C2
(P eriph eral Group0)
PG0
PWMTimer
ConfigSys1
ADC Ctrl
ADC1
I2C1
UART3 r
UART2 r
UART1 r
AHB S
32b
System Control
System
Controller
WDOGM3
WDOGA7_1
RTC
APB S
32b
AHB S
32b
SERCOSIII
Ethernet Peripherals
SRAM 1MB
SRAM 1MB
AHB S
128b
AHB M
32b
AXI M
64b
APB S
32b
APB S
32b
SRAM 1MB
SRAM 1MB
AHB S
128b
4MB SRAM
AHB S
128b
AHB S
128b
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 1 General Architecture
CoreSight
RZ/N1S Single Cortex-A7 & Cortex-M3
Page 25 of 263
Figure 1.3
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
SPI3 (M)
SPI4 (M)
SPI5 (S)
UART6 f
UART7 f
UART8 f
APB S
32b
APB S
32b
AHB S
32b
SEMAP x64
AHB S
32b
PG4 (Peripheral Group4)
CAN2
CAN1
PG3 (Peripheral Group3)
ConfigSys2
TIMER2 x8
TIMER1 x8
PG2 (Peripheral Group2)
BGPIO3
BGPIO2
SPI6 (S)
SPI2 (M)
UART5 f
BGPIO1
SPI1 (M)
UART4 f
PG1 (Peripheral Group1)
bridge
Network
On
Chip
AHB M
64b
AHB S
32b
AHB S
32b
VIC
AHB M
32b
AHB M
32b
Parallel
interface
MSEBI S
AHB S
32b
AHB M
32b
AHB M
32b
AHB M
32b
AHB S
32b
SD/SD/eMMC
Host Controller
SD/SDIO/
eMMC2
AHB S
32b
AHB S
32b
Con figurable
Arb iter
RAM_inst1
512kB
AHB S
32b
SD/SDIO/
eMMC1
AHB S
32b
AHB M
32b
Debug & ETM
Cortex-M3
Arm Cortex-M3
NAND Flash
NAND
Controller
AHB S
32b
AHB S
32b
DMACs
AHB M
64b
DMAC1
AHB S
32b
AHBM
32b
USB 2.0
USB
Function
AHB S
32b
APB S
32b
QSPI
ADC1
(P eriph eral Group0)
PG0
PWMTimer
ConfigSys1
ADC Ctrl
System Control
System
Controller
I2C2
UART3 r
UART2 r
APB S
32b
AHB S
32b
SERCOSIII
WDOGM3
AHB S
32b
ETHERCAT
UART1 r
APB S
32b
AHB S
32b
I2C1
AHB S
32b
GMAC1
A5PSW
AXI M
32b
QSPI 1
AHB S
32b
AHB S
32b
GMAC2
Mux
MAC2RTOS
Ethernet Peripherals
AXI M
32b
AHB M
32b
USB
Host
AHB S
32b
AHB S
32b
HW-RTOS
GMAC
Network-On-Chip (NoC)
AHB M
64b
AHB S
32b
Con figurable
Arb iter
HW-RTOS
R-IN Engine
RAM_data0
512kB
DMAC2
AHB S
32b
Con figurable
Arb iter
AHB S
32b
AHB M
32b
AHB S
32b
AHB S
32b
AHB S
32b
Con figurable
Arb iter
RAM_data1
512kB
2MB SRAM
RAM_inst0
512kB
SRAM 1MB
SRAM 1MB
AHB S
128b
AHB S
128b
AHB M
32b
AXI M
64b
APB S
32b
APB S
32b
SRAM 1MB
SRAM 1MB
AHB S
128b
4MB SRAM
AHB S
128b
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 1 General Architecture
CoreSight
RZ/N1L Cortex-M3
Page 26 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 2
2.1
Section 2 Address Space
Address Space
Memory Map
2.1.1
RZ/N1D
The figure below provides an overview of the memory map as seen by Arm Cortex-A7.
5000 0000H
Reserved
4520 0000H
CoreSi ght
(2MByte)
4500 0000H
GIC access area
(32K Byte)
4410 0000H
Reserved
4406 0000H
4404 0000H
4403 0000H
4402 0000H
4401 0000H
DDR2/DDR3 SDRAM ar ea
(2G Byte)
Reserved
4410 8000H
4405 0000H
FFFF FFFFH
Advanced 5po rt Switch
(64K Byte)
HSR(PTP) 16KByte
HSR(CORE) 1 6KByte
HSR(CPU) 32 KByte
Etherne t Acce ssory Reg ister
(64K Byte)
Ser cosIII S lave Controll er
(64KByte )
EtherCAT Slave Con tro ller
(64KByte )
8000 0000H
7FFF FFFFH
MSEBI (Exter nal Bus I/F) area
(512 MB yte)
6000 0000H
5FFF FFFFH
5000 0000H
4FFF FFFFH
4400 0000H
43FF FFFFH
Reserved
4400 2000H
4400 0000H
Gig abit Ethern et MAC 1
(8K Byte)
Inte rnal resources
(CoreS ight, A5P SW…)
(192 MB yte)
4010 5000H
DMAC2 (4 KByte)
4010 4000H
DMAC1 (4 KByte)
4010 2000H NAND Flash Controller (8KByte)
4010 1000H
SD/SDIO/eMMC2 (4 KByte)
4010 0000H
SD/SDIO/eMMC1 (4 KByte)
400F 2000H
R-IN Engine Accessory Register
(56KByte)
Reserved
4400 4000H
Gig abit Ethern et MAC 2
(8K Byte)
4010 6000H
Per ipheral Gr oup 1,2 ,3,4
(256 MB yte)
4010 6000H
4010 5FFFH
4000
3FFF
3001
3000
3000
2FFF
0000H
FFFFH
0000H
FFFFH
0000H
FFFFH
Reserved
Per ipheral reg isters
(1MByte)
Reserved
Boo t ROM are a ( 64KByte)
400C 3000H
400C 2000H
400C 0000H
4008 0000H
Reserved
4006 0000H
MSEBI Slave (4KByte)
MSEBI Ma ster (8KB yte)
MSEBI Ma ster (DMA )
(256 KByte )
Per ipheral Gr oup 0
(128 KByte )
Reserved
4004 0000H
2010 0000H
200F FFFFH
2000 0000H
1FFF FFFFH
Data RAM area
(1MByte)
QSP I1 ROM a rea
(256 MB yte)
1000 0000H
0FFF FFFFH
Reserved
0410 0000H
040F FFFFH
0400 0000H
03FF FFFFH
0001 0000H
0000 FFFFH
0000 0000H
Figure 2.1
4002 0000H
USB 2.0 Host
(128 KByte )
4001 E000H
USB 2.0 Function (8KByte)
Reserved
4000 F000H
4000 E000H
DDR PHY (4KByte)
4000 D000H
DDR Controller (4KB yte)
4000 C000H
System Co ntr oller (4K Byte)
4000 B000H
Mailbox (4KB yte)
4000 A000H
WDOGM3 (4KByte)
4000 9000H
WDOGA7_ 2 ( 4KByte )
4000 8000H
WDOGA7_ 1 ( 4KByte )
4000 7000H
Reserved
Instruction RAM area
(1MByte)
4000 6000H
Real-Time Clock (4 KByte)
4000 5000H
QSP I1 (4K Byte)
Reserved
4000 0000H
Reserved
Boo t ROM are a ( 64KByte)
Memory Map of RZ/N1D (Cortex-A7)
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 27 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 2 Address Space
The figure below provides an overview of the memory map as seen by Arm Cortex-M3.
5000 0000H
Reserved
4520 0000H
CoreSi ght
(2MByte)
4500 0000H
Reserved
4406 0000H
4405 0000H
4404 0000H
4403 0000H
4402 0000H
4401 0000H
Advanced 5po rt Switch
(64K Byte)
HSR(PTP) 16KByte
HSR(CORE) 1 6KByte
HSR(CPU) 32 KByte
Etherne t Acce ssory Reg ister
(64K Byte)
Ser cosIII S lave Controll er
(64KByte )
EtherCAT Slave Con tro ller
(64KByte )
FFFF FFFFH
E000 0000H
DFFF FFFFH
8000 0000H
7FFF FFFFH
4400 2000H
Gig abit Ethern et MAC 2
(8K Byte)
4400 0000H
Gig abit Ethern et MAC 1
(8K Byte)
(1MByte) *2
DDR2/DDR3 SDRAM ar ea
(1.5GB yte)
MSEBI (Exter nal Bus I/F) area
(512 MB yte)
System area
6000 0000H
5FFF FFFFH
4010 6000H
Per ipheral Gr oup 1,2 ,3,4
(256 MB yte)
5000 0000H
4FFF FFFFH
Reserved
4400 4000H
DDR2/DDR3 SDRAM ar ea
(511 MB yte)
E010 0000H
E00F FFFFH Cortex-M3 System le vel are a
4400 0000H
43FF FFFFH
4200 0000H
41FF FFFFH
4010 6000H
4010 5FFFH
4000 0000H
3FFF FFFFH
2400 0000H
23FF FFFFH
2200 0000H
21FF FFFFH
4010 5000H
DMAC2 (4 KByte)
4010 4000H
DMAC1 (4 KByte)
4010 2000H NAND Flash Controller (8KByte)
Inte rnal resources
(CoreS ight, A5P SW…)
(192 MB yte)
4010 1000H
4010 0000H
Bitband alias area
400F 2000H
(32MByte ) *2
Reserved
400F 0000H
Per ipheral reg isters
(1MByte)
400E 0000H
Reserved
400C 3000H
SD/SDIO/eMMC2 (4 KByte)
SD/SDIO/eMMC1 (4 KByte)
R-IN Engine Accessory Register
(56KByte)
Gigabit Ethernet MAC
for HW-RTOS
(8KByte) *2
HW-RTOS Hardware
Function Call
(64KByte) *2
Reserved
400C 2000H
Bitband alias area
(32MByte ) *2
400C 0000H
4008 0000H
4006 0000H
Reserved
MSEBI Slave (4KByte)
MSEBI Ma ster (8KB yte)
MSEBI Ma ster (DMA )
(256 KByte )
Per ipheral Gr oup 0
(128 KByte )
Reserved
4004 0000H
2010 0000H
200F FFFFH
2000 0000H
1FFF FFFFH
Data RAM area
(1MByte)
[Note2]
R-IN ENGINE area
(400E_0000H – 400F_1FFFH,
0800_0000H – 0FFF_FFFFH)
and
Cortex-M3 System level area
(2200_0000H – 23FF_FFFFH,
4200_0000H – 43FF_FFFFH,
E000_0000H – E00F_FFFFH)
can be accessed only from Cortex-M3
Figure 2.2
1000 0000H
0FFF FFFFH
0800 0000H
07FF FFFFH
0410 0000H
040F FFFFH
HW-RTO S (128MByte ) *2
0400 0000H
03FF FFFFH
Instruction RAM area
(1MByte)
Reserved
0010 0000H
000F FFFFH
BOO T Code area
0000 0000H
(1MByte) *1
4001 E000H
USB 2.0 Function (8KByte)
4000 F000H
Buffer memor y area
Reserved
USB 2.0 Host
(128 KByte )
Reserved
QSP I1 ROM a rea
(256 MB yte)
[Note1]
BOOT Code area
(0000_0000H – 000F_FFFFH)
is alias area of Instruction RAM area
(0400_0000H – 040F_FFFFH)
4002 0000H
ICo de, DCode
area
4000 E000H
DDR PHY (4KByte)
4000 D000H
DDR Controller (4KB yte)
4000 C000H
System Co ntr oller (4K Byte)
4000 B000H
Mailbox (4KB yte)
4000 A000H
WDOGM3 (4KByte)
4000 9000H
WDOGA7_ 2 ( 4KByte )
4000 8000H
WDOGA7_ 1 ( 4KByte )
4000 7000H
Reserved
4000 6000H
Real-Time Clock (4 KByte)
4000 5000H
QSP I1 (4K Byte)
Reserved
4000 0000H
Memory Map of RZ/N1D (Cortex-M3)
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2.1.2
Section 2 Address Space
RZ/N1S
The figure below provides an overview of the memory map as seen by Arm Cortex-A7.
FFFF FFFFH
Reserved
B000 0000H
AFFF FFFFH
5000 0000H
4520 0000H
4500 0000H
4410 8000H
4410 0000H
4406 0000H
4405 0000H
Reserved
CoreSi ght
(2MByte)
Reserved
GIC access area
(32K Byte)
Reserved
Advanced 5po rt Switch
(64K Byte)
MSEBI (Exter nal Bus I/F) area
(512 MB yte)
6000 0000H
5FFF FFFFH
Per ipheral Gr oup 1,2 ,3,4
(256 MB yte)
5000 0000H
4FFF FFFFH
Reserved
4404 0000H
4403 0000H
4402 0000H
4401 0000H
Etherne t Acce ssory Reg ister
(64K Byte)
Ser cosIII S lave Controll er
(64KByte )
EtherCAT Slave Con tro ller
(64KByte )
Reserved
4400 4000H
4400 2000H
Gig abit Ethern et MAC 2
(8K Byte)
4400 0000H
Gig abit Ethern et MAC 1
(8K Byte)
QSP I2 ROM a rea
(256 MB yte)
0000H
FFFFH
Reserved
1000H
0FFFH SRAM 4MB ECC register (4KByte)
0000H
FFFFH
SRAM 4MB a rea
(4MByte)
8000 0000H
7FFF FFFFH
A000
9FFF
8040
8040
8040
803F
4400 0000H
43FF FFFFH
Inte rnal resources
(CoreSi ght, A5P SW…)
(192 MB yte)
4010 6000H
4010 5000H
DMAC2 (4 KByte)
4010 4000H
DMAC1 (4 KByte)
4010 2000H NAND Flash Controller (8KByte)
4010 1000H
SD/SDIO/eMMC2 (4 KByte)
4010 0000H
SD/SDIO/eMMC1 (4 KByte)
400F 2000H
R-IN Engine Accessory Register
(56KByte)
Reserved
4010 6000H
4010 5FFFH
4000
3FFF
3001
3000
3000
2FFF
0000H
FFFFH
0000H
FFFFH
0000H
FFFFH
Reserved
Per ipheral reg isters
(1Mbyte)
Reserved
Boo t ROM are a ( 64KByte)
Reserved
400C 3000H
400C 2000H
MSEBI Slave (4KByte)
400C 0000H
MSEBI Ma ster (8KB yte)
4008 0000H
MSEBI Ma ster (DMA )
(256 KByte )
4006 0000H
Per ipheral Gr oup 0
(128 KByte )
Reserved
4004 0000H
2010 0000H
200F FFFFH
2000 0000H
1FFF FFFFH
Data RAM area
(1MByte)
QSP I1 ROM a rea
(256 MB yte)
4002 0000H
USB 2.0 Host
(128 KByte )
4001 E000H
USB 2.0 Function (8KByte)
Reserved
4000 F000H
4000 E000H
1000 0000H
0FFF FFFFH
Reserved
0410 0000H
040F FFFFH
0400 0000H
03FF FFFFH
0001 0000H
0000 FFFFH
0000 0000H
Figure 2.3
QSP I2 (4K Byte)
4000 D000H
Reserved
4000 C000H
System Co ntr oller (4K Byte)
4000 B000H
Mailbox (4KB yte)
4000 A000H
WDOGM3 (4KByte)
4000 9000H
Reserved
4000 8000H
WDOGA7_ 1 ( 4KByte )
4000 7000H
Reserved
Instruction RAM area
(1MByte)
4000 6000H
Real-Time Clock (4 KByte)
4000 5000H
QSP I1 (4K Byte)
Reserved
4000 0000H
Reserved
Boo t ROM are a ( 64KByte)
Memory Map of RZ/N1S (Cortex-A7)
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Section 2 Address Space
The figure below provides an overview of the memory map as seen by Arm Cortex-M3.
FFFF FFFFH
Reserved
E010 0000H
E00F FFFFH Cortex-M3 System le vel are a
E000 0000H
DFFF FFFFH
(1MByte) *2
Reserved
B000 0000H
AFFF FFFFH
5000 0000H
Reserved
4520 0000H
CoreSi ght
(2MB)
4500 0000H
Reserved
4406 0000H
4405 0000H
Advanced 5po rt Switch
(64K Byte)
A000
9FFF
8040
8040
8040
803F
0000H
FFFFH
1000H
0FFFH
0000H
FFFFH
8000 0000H
7FFF FFFFH
Etherne t Acce ssory Reg ister
(64K Byte)
4403 0000H
Ser cosIII S lave Controll er
(64KByte )
4402 0000H
4401 0000H
EtherCAT Slave Con tro ller
(64KByte )
Reserved
4400 4000H
4400 2000H
Gig abit Ethern et MAC 2
(8K Byte)
4400 0000H
Gig abit Ethern et MAC 1
(8K Byte)
Reserved
SRAM 4MB ECC register (4KByte)
System area
SRAM 4MB a rea
(4MByte)
MSEBI (Exter nal Bus I/F) area
(512 MB yte)
4010 6000H
4010 5000H
6000 0000H
5FFF FFFFH
Per ipheral Gr oup 1,2 ,3,4
(256 MB yte)
Reserved
4404 0000H
QSP I2 ROM a rea
(256 MB yte)
5000 0000H
4FFF FFFFH
4400 0000H
43FF FFFFH
4200
41FF
4010
4010
0000H
FFFFH
6000H
5FFFH
4000 0000H
3FFF FFFFH
DMAC1 (4 KByte)
4010 2000H
NAND Flash Controller (8KByte)
4010 1000H
SD/SDIO/eMMC2 (4 KByte)
4010 0000H
Inte rnal resources
(CoreSi ght, A5P SW…)
(192 MB yte)
400F 2000H
Bitband alias area
400F 0000H
(32MByte ) *2
Reserved
400E 0000H
Per ipheral reg isters
(1Mbyte)
400C 0000H
4008 0000H
2010 0000H
200F FFFFH
2000 0000H
1FFF FFFFH
HW-RTOS Hardware
Function Call
(64KByte) *2
Reserved
Reserved
2200 0000H
21FF FFFFH
SD/SDIO/eMMC1 (4 KByte)
R-IN Engine Accessory Register
(56KByte)
Gigabit Ethernet MAC
for HW-RTOS
(8KByte) *2
400C 3000H
400C 2000H
2400 0000H
23FF FFFFH
DMAC2 (4 KByte)
4010 4000H
4006 0000H
Bitband alias area
(32MByte ) *2
MSEBI Slave (4KByte)
MSEBI Ma ster (8KB yte)
MSEBI Ma ster (DMA )
(256 KByte )
Per ipheral Gr oup 0
(128 KByte )
Reserved
Reserved
4004 0000H
Data RAM area
(1MByte)
4002 0000H
USB 2.0 Host
(128 KByte )
4001 E000H
USB 2.0 Function (8KByte)
QSP I1 ROM a rea
(256 MB yte)
4000 F000H
Reserved
4000 E000H
[Note1]
BOOT Code area
(0000_0000H – 000F_FFFFH)
is alias area of Instruction RAM area
(0400_0000H – 040F_FFFFH)
[Note2]
R-IN ENGINE area
(400E_0000H – 400F_1FFFH,
0800_0000H – 0FFF_FFFFH)
and
Cortex-M3 System level area
(2200_0000H – 23FF_FFFFH,
4200_0000H – 43FF_FFFFH,
E000_0000H – E00F_FFFFH)
can be accessed only from Cortex-M3
Figure 2.4
1000 0000H
0FFF FFFFH
0800 0000H
07FF FFFFH
Buffer memor y area
HW-RTO S (128MByte ) *2
Reserved
0410 0000H
040F FFFFH
0400 0000H
03FF FFFFH
Instruction RAM area
(1MByte)
Reserved
0010 0000H
000F FFFFH
Boo t Code area
0000 0000H
(1MByte) *1
ICo de, DCode
area
QSP I2 (4K Byte)
4000 D000H
Reserved
4000 C000H
System Co ntr oller (4K Byte)
4000 B000H
Mailbox (4KB yte)
4000 A000H
WDOGM3 (4KByte)
4000 9000H
Reserved
4000 8000H
WDOGA7_ 1 ( 4KByte )
4000 7000H
Reserved
4000 6000H
Real-Time Clock (4 KByte)
4000 5000H
QSP I1 (4K Byte)
Reserved
4000 0000H
Memory Map of RZ/N1S (Cortex-M3)
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2.1.3
Section 2 Address Space
RZ/N1L
The figure below provides an overview of the memory map as seen by Arm Cortex-M3.
FFFF FFFFH
Reserved
E000 0000H
DFFF FFFFH Cortex-M3 System le vel are a
B000 0000H
AFFF FFFFH
(1MByte)
Reserved
5000 0000H
Reserved
4520 0000H
CoreSi ght
(2MB)
4500 0000H
Reserved
4406 0000H
Advanced 5po rt Switch
(64K Byte)
4405 0000H
8040
8040
8040
803F
1000H
0FFFH
0000H
FFFFH
8000 0000H
7FFF FFFFH
4403 0000H
Etherne t Acce ssory Reg ister
(64K Byte)
4402 0000H
Ser cosIII S lave Controll er
(64KByte )
4401 0000H
EtherCAT Slave Con tro ller
(64KByte )
System area
Reserved
Per ipheral Gr oup 1,2 ,3,4
(256 MB yte)
5000 0000H
4FFF FFFFH
4400
43FF
4200
41FF
0000H
FFFFH
0000H
FFFFH
Reserved
4010 6000H
4010 5FFFH
4400 2000H
Gig abit Ethern et MAC 2
(8K Byte)
4000 0000H
3FFF FFFFH
4400 0000H
Gig abit Ethern et MAC 1
(8K Byte)
4400 4000H
SRAM 4MB a rea
(4MByte)
6000 0000H
5FFF FFFFH
Reserved
4404 0000H
SRAM 4MB ECC register (4KByte)
Inte rnal resources
(CoreSi ght, A5P SW…)
(192 MB yte)
4010 6000H
4010 4000H
DMAC1 (4 KByte)
Bitband alias area
(32MByte )
4010 2000H
NAND Flash Controler (8KByte)
4010 1000H
SD/SDIO/eMMC2 (4 KByte)
Reserved
4010 0000H
SD/SDIO/eMMC1 (4 KByte)
400F 2000H
R-IN Engine Accessory Register
(56KByte)
4010 5000H
Per ipheral reg isters
(1Mbyte)
400F 0000H
Reserved
2400 0000H
23FF FFFFH
2200 0000H
21FF FFFFH
2010 0000H
200F FFFFH
2000 0000H
1FFF FFFFH
400E 0000H
Bitband alias area
(32MByte )
400C 3000H
Reserved
4008 0000H
400C 2000H
4006 0000H
Data RAM area
(1MByte)
(256 MB yte) *1
0800 0000H
07FF FFFFH
Buffer memor y area
HW-RTO S (128MByte )
Reserved
0410 0000H
040F FFFFH
Instruction RAM area
(1MByte)
[Note1]
0400 0000H
03FF FFFFH
(0000_0000H – 000F_FFFFH)
is alias area of QSPI1 ROM area
(1000_0000H – 100F_FFFFH)
0010 0000H
000F FFFFH
Boo t Code area
0000 0000H
(1MByte) *1
Boo t Code area
Figure 2.5
Gigabit Ethernet MAC
for HW-RTOS
(8KByte)
HW-RTOS Hardware
Function Call
(64KByte)
Reserved
QSP I1 ROM a rea
1000 0000H
0FFF FFFFH
DMAC2 (4 KByte)
MSEBI Slave (4KByte)
Reserved
Per ipheral Gr oup 0
(128 KByte )
4004 0000H
Reserved
4002 0000H
USB 2.0 Host
(128 KByte )
4001 E000H
USB 2.0 Function (8KByte)
4000 D000H
Reserved
4000 C000H
System Co ntr oller (4K Byte)
4000 B000H
Reserved
4000 A000H
WDOGM3 (4KByte)
4000 6000H
Reserved
4000 5000H
QSP I1 (4K Byte)
4000 0000H
Reserved
ICo de, DCode
area
Reserved
Memory Map of RZ/N1L
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
2.2
Section 2 Address Space
Register Map Summary
Following Register map covers base address of peripheral module in all RZ/N1 groups. The unchecked modules should
not be accessed.
Start Address
Peripheral Module
RZ/N1D-324
RZ/N1S-324
RZ/N1S-196
RZ/N1L
Register Map (1/2)
RZ/N1D-400
Table 2.1
4000_5000
Quad SPI Controller1 (QSPI1)
4000_6000
Real-Time Clock (RTC)
N/A
4000_8000
Watchdog for CA7 processor0 (WDOGA7_1)
N/A
4000_9000
Watchdog for CA7 processor1 (WDOGA7_2)
4000_A000
Watchdog for CM3 (WDOGCM3)
4000_B000
Mailbox (IPCM)
N/A
4000_C000
System Controller
4000_D000
DDR2/3 Controller
—
—
—
4000_E000
DDR2/3 PHY
—
—
—
Quad SPI Controller2 (QSPI2)
—
—
N/A
N/A
4001_E000
USB 2.0 HS Function Controller (USBf) / EPC
4001_F000
USB 2.0 HS Function Controller (USBf) / AHB-EPC Bridge
4002_0000
USB 2.0 HS Host Controller (USBh) / OHCI Operation
4002_1000
USB 2.0 HS Host Controller (USBh) / EHCI Operation
4003_0000
USB 2.0 HS Host Controller (USBh) / AHB PCI Bridge (PCI Config. Space)
4003_0000
USB 2.0 HS Host Controller (USBh) / OHCI (PCI Config. Space)
4003_0100
USB 2.0 HS Host Controller (USBh) / EHCI (PCI Config. Space)
4003_0800
USB 2.0 HS Host Controller (USBh) / AHB PCI Bridge (PCI Com. Space)
4006_0000
UART1
4006_1000
UART2
4006_2000
UART3
4006_3000
I2C1
4006_4000
I2C2
4006_5000
ADC Controller / 12bit A/D Converters
4006_7000
ConfigSys1
4006_8000
PWMTimer
4008_0000
Medium Speed External Bus Interface / Master (MSEBIM) From DMA
N/A
400C_0000
Medium Speed External Bus Interface / Master (MSEBIM) From CPU
N/A
400C_1000
Medium Speed External Bus Interface / Slave (MSEBIS) From MSEBI
400C_2000
Medium Speed External Bus Interface / Slave (MSEBIS) From CPU
400E_0000
HW-RTOS Hardware Function Call
400F_0000
Gigabit Ethernet MAC for HW-RTOS (HW-RTOS GMAC)
400F_2000
R-IN Engine Accessory Register
4010_0000
SD/SDIO/eMMC Controller1 (SDIO1)
4010_1000
SD/SDIO/eMMC Controller2 (SDIO2)
4010_2000
NAND Flash Controller
4010_4000
DMAC1
4010_5000
DMAC2
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N/A
Page 32 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Start Address
Peripheral Module
RZ/N1D-324
RZ/N1S-324
RZ/N1S-196
RZ/N1L
Register Map (2/2)
RZ/N1D-400
Table 2.1
Section 2 Address Space
4400_0000
Gigabit Ethernet MAC1 (GMAC1)
N/A
4400_2000
Gigabit Ethernet MAC2 (GMAC2)
4401_0000
EtherCAT Slave Controller (ETHERCAT)
4402_0000
SercosIII Slave Controller (SERCOSIII)
4403_0000
Ethernet Accessory Register
4404_0000
HSR Switch / CPU
*1
—
—
—
—
4404_8000
HSR Switch / CORE
*1
—
—
—
—
4404_C000
HSR Switch / PTP
*1
—
—
—
—
4405_0000
Advanced 5port Switch (A5PSW)
5000_0000
UART4
5000_1000
UART5
5000_2000
UART6
5000_3000
UART7
5000_4000
UART8
5000_5000
SPI1 (Master)
5000_6000
SPI2 (Master)
5000_7000
SPI3 (Master)
5000_8000
SPI4 (Master)
5000_9000
SPI5 (Slave)
5000_A000
SPI6 (Slave)
5000_B000
BGPIO1
5000_C000
BGPIO2
5000_D000
BGPIO3
N/A
N/A
5100_0000
ConfigSys2
5100_1000
Timer Block1 (TIMER1)
5100_2000
Timer Block2 (TIMER2)
5210_4000
CAN1
5210_5000
CAN2
5300_0000
Semaphore (SEMAP)
5300_4000
LCD Controller (LCDC)
N/A
N/A
Note 1.
HSR is optional.
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Section 3
3.1
Section 3 Clock Generation
Clock Generation
Overview
RZ/N1 has 3 clock sources, 1 reference clock inputs for RGMII, and 2 reference clock outputs for RMII/MII.
System controller includes registers for RZ/N1 Clock Controller. This allows the power management software to have
fully flexible control over the implemented clock gating, clock multiplexing and clock division features.
Table 3.1
Specification of Clock Generation
Item
Specifications
Main clock oscillator
Resonator frequency: 40 MHz
External clock input frequency: 40 MHz
Main clock source for this system. External clock input mode is also available.
RTC clock oscillator
Resonator frequency: 32.768 kHz
External clock input for
JTAG (JTAG_TCK)
Input frequency: 10 MHz (max) for JTAG
PLL
Input clock source: Main clock oscillator
RTC clock source. It belongs to RTC dedicated power domain.
Clock for CoreSight® and JTAG controller.
Output clock frequency: 1000 MHz
Main PLL for this system
USBPLL
Input clock source: Main clock oscillator
Output clock frequency: 480 MHz
PLL for USBPHY. 48 MHz, 1/10 of 480 MHz, is provided to system. Default in power down mode.
External clock input for
RGMII (RGMII_REFCLK)
External clock output for
RMII (RMII_REFCLK)
External clock output for
MII (MII_REFCLK)
Input frequency: 125 MHz
Clock for RGMII output signals. Internally generated 125 MHz is also available for RGMII
Output frequency: 50 MHz
Clock supply for external RMII interface
Output frequency: 25 MHz
Clock supply for external MII interface
A Figure in next page shows abstract clock system of RZ/N1.
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Section 3 Clock Generation
# italic&under-bar shows multi instances
# “xxxDIV” and “CLKEN” are configured by
clock controller registers.
# “Clock gating” is controlled by each block
OPPDIV
CLKEN
1/2
1/4
CLKEN
internal bus AHB/AXI/APB
1/8
CLKEN
internal bus APBdiv2
Clock
Gating
CA7DIV
DDR2
DDR3
xxxDIV
0
CLKEN
DDR memory controller
1/2
Clock
Gating
DDR memory
1/160
ADC/NAND/QSPI[m](m=1,2)/SDIO[m](m=1,2)/
MDC/A5PSW
Cortex-M3 SysTick
1/10
CLKEN
100MHz for HSR/SERCOSIII/ETHERCAT
1/8
CLKEN
125MHz for ETHERCAT
1/40
CLKEN
25MHz for ETHERCAT/MII_REFCLK
1/20
CLKEN
50MHz for
HSR/SERCOSIII/EtherCAT/RMII_REFCLK
1/400
2.5MHz for Ethernet
xxxDIV
CLKEN
I2C[m](m=1,2)/LCDC/SPI[m](m=1..6)
1/40
CLKEN
TIMER[m](m=1,2)/ConfigSys2
1/10
CLKEN
PWMTimer
xxxDIV
CLKEN
xxxDIV
CLKEN
USBCLK
48MHz
RGMII_REFCLK
(External Input)
Figure 3.1
internal bus USB
1/4
CLKEN
Clock for
Internal bus &
synchronous region
(sCore)
Cortex-A7
CLKEN
1
CM3_HCLK
CM3_FCLK
HW-RTOS
RINBUS_HCLK
CLKEN
1/8
PLL
1GHz
Clock
Gating
0
Clock for
External interface
(asCore)
UART[m](m=1..3)
1
CLKEN
0
CLKEN
1
UART[m](m=4..8)
CLKEN
PG3/CAN[m](m=1,2)
CLKEN
RGMII_REFCLK(internal)
Block Diagram of Clock Generation
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3.2
Section 3 Clock Generation
Clock Gating
“PWRCTRL_*” registers contain clock gate control bits, “CLKEN_*”. There is no special logic in place for the clock
gate control signals, all signals are directly feed through the Core block and driven by register bits.
Clock gating of a functioning module may result in system hang up or unpredictable behavior. It is the power
management software’s responsibility to ensure that no clocks are gated before the corresponding peripheral is
disconnected from interconnect.
CAUTION
● RZ/N1 uses the clock provided by USBPLL. The software shall ensure that prior to any access towards USB clocked
domain the USBPLL shall be locked. Otherwise the system may hang.
● The software shall not apply clock gating or software reset to any module unless all corresponding ports of the module
are disconnected (SCON = 1’b0) and in idle (MISTAT = 1’b1).
3.3
Clock Multiplexing
RZ/N1 Clock Controller has programmable clock multiplexers for each UART. Those multiplexers can be configured
by PWRCTRL_PG0_0 and PWRCTRL_PG1_PR2 registers in System Controller Registers.
CAUTION
RZ/N1 uses the clock provided by USBPLL. The software shall ensure that prior to any access towards USB clocked
domain the USBPLL shall be locked. Otherwise the system may hang.
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3.4
Section 3 Clock Generation
Clock Division
RZ/N1 clock controller has programmable clock dividers. Software may or may not gate the corresponding clocks prior
to reprogramming of the dividers. The clock dividers implement a full hardware handshake between System Controller
and the clock divider.
CAUTION
The software shall not initiate writes to the control registers of programmable dividers unless the busy flag in the
corresponding register is de-asserted.
Software decides to
change a divider
PWRCTRL*DIV register read
BUSY = 1
Yes
No
PWRCTRL*DIV register write
• BUSY = 1
• DiV= new divider value
PWRCTRL*DIV register read
BUSY = 0
No
Yes
New clock divider
value effective
Figure 3.1
Programming Sequence for Programmable Dividers
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3.5
Section 3 Clock Generation
Clock Frequency Scaling
RZ/N1 Clock Controller provides two dedicated clock dividers to enable low power operation. One divider is to scale
the Cortex-A7 CPU clock by PWRCTRL_CA7DIV register, the other divider is to scale the main NoC interconnect
frequency by PWRCTRL_OPPDIV register. The power management software has full control over these dividers and it
is in charge of making any decision based on the actual circumstances to scale the clock frequency.
CAUTION
Scaling the frequency of the interconnect scales the frequency of the Watchdog timers.
Following the table shows available clock frequency scaling and use cases. The circuit of each module is classified
depending on whether the clock is synchronized with NoC. For each clock, please refer to “Figure 3.1, Block
Diagram of Clock Generation” and “Appendix C, Clock Tree Structure”.
● sCore: Circuit which is synchronous to NoC (Clock for AXI/AHB/APB)
● asCore: Circuit which is asynchronous to NoC
Table 3.2
Frequency Mode (1/3)
125 MHz Mode
(Default)
62.5 MHz Mode
31.25 MHz Mode
15.625 MHz Mode
Network-on-Chip
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
DMAC
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
System Control block
(RTC, Watchdog, …)
62.5 MHz
31.25 MHz
15.625 MHz
7.8125 MHz
500 MHz (4×)
250 MHz (4×)
125 MHz (4×)
62.5 MHz (4×)
250 MHz (2×) (Default)
125 MHz (2×)
62.5 MHz (2×)
31.25 MHz (2×)
125 MHz (1×)
62.5 MHz (1×)
31.25 MHz (1×)
15.625 MHz (1×)
Function List
General System – synchronous to NoC
CPU & R-IN Engine – synchronous to NoC
Cortex-A7
sCore
Cortex-M3
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
HW-RTOS
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
asCore
250 MHz
250 MHz
250 MHz
250 MHz
Memory Clk
500 MHz
500 MHz
500 MHz
500 MHz
asCore
125 MHz
125 MHz
125 MHz
125 MHz
Memory Unit
DDR3-1000
DDR2-500
Memory Clk
250 MHz
250 MHz
250 MHz
250 MHz
SRAM 2MB & 4MB
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
NAND Flash Controller
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
asCore
Up to 83.33 MHz
←
←
←
QSPI
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
SD/SDIO/eMMC
asCore
Up to 250 MHz*
←
←
←
sCore
125 MHz
62.5 MHz
31.25 MHz
Not available
asCore
Up to 50 MHz
←
←
asCore
125 MHz
125 MHz
125 MHz
USBCLK out
48 MHz
←
←
1
Networking element & USB
USB Host & Function
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Table 3.2
Section 3 Clock Generation
Frequency Mode (2/3)
Function List
GMAC
125 MHz Mode
(Default)
62.5 MHz Mode
31.25 MHz Mode
15.625 MHz Mode
Not available
sCore
125 MHz
62.5 MHz
31.25 MHz
PTP
125 MHz or 25 MHz
←
←
Ether mode*3
GMII/RMII/MII
RMII/MII
RMII/MII
sCore
125 MHz
62.5 MHz
31.25 MHz
asCore
200 MHz
←
←
Ether mode*3
GMII/RMII/MII 5ports RMII/MII 5ports
asCore
100 MHz
100 MHz
100 MHz
Ether mode*3
MII/RMII
MII/RMII
MII/RMII
asCore
125 MHz
125 MHz
125 MHz
Ether mode*3
MII/RMII
MII/RMII
MII/RMII
HSR
asCore
100 MHz
100 MHz
Not available
Not available
RGMII/RMII Converter
Ether mode*
RGMII/RMII/MII
RMII/MII
RMII/MII
RMII/MII
Advanced 5 Port
Switch/PRP
SERCOSIII
ETHERCAT
3
Not available
RMII/MII 3ports
Not available
Not available
Peripheral
2 clock sources are available for UARTs 1) PLL via divider, up to 83.33 MHz 2) USBPLL, fixed to 48 MHz
UART 1..3
UART 4..8
SPI config1
SPI config2
SPI config3
SPI config4
IC
2
sCore
62.5 MHz
31.25 MHz
15.625 MHz
7.8125 MHz
asCore
Up to 83.33 MHz or
48 MHz
←
←
←
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
asCore
Up to 83.33 MHz or
48 MHz
←
←
←
sCore
125 MHz
Not available
Not available
Not available
asCore
Up to 125 MHz
sCore
125 MHz
62.5 MHz
Not available
Not available
asCore
Up to 62.5 MHz
←
sCore
125 MHz
62.5 MHz
31.25 MHz
Not available
asCore
Up to 31.25 MHz
←
←
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
asCore
Up to 15.625 MHz
←
←
←
sCore
62.5 MHz
31.25 MHz
15.625 MHz
7.8125 MHz
asCore
Up to 83.33 MHz*
←
←
←
MSEBI
sCore
125 MHz
62.5 MHz
31.25 MHz
Not available
CAN
asCore
48 MHz
←
←
←
BGPIO
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
ADC
sCore
62.5 MHz
31.25 MHz
15.625 MHz
7.8125 MHz
asCore
Up to 20 MHz
←
←
←
TIMER
asCore
25 MHz
←
←
←
PWMTimer
asCore
100 MHz
←
←
Not available
Semaphore
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
Mailbox
sCore
125 MHz
62.5 MHz
31.25 MHz
15.625 MHz
LCDC (Config1)
sCore
125 MHz
Not available
Not available
Not available
asCore
Up to 83.33 MHz
LCDC (Config2)
sCore
125 MHz
62.5 MHz
Not available
Not available
asCore
Up to 62.5 MHz
Less than 62.5 MHz
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Table 3.2
Section 3 Clock Generation
Frequency Mode (3/3)
125 MHz Mode
(Default)
62.5 MHz Mode
31.25 MHz Mode
15.625 MHz Mode
sCore
125 MHz
62.5 MHz
31.25 MHz
Not available
asCore
Up to 31.25 MHz
←
Less than
31.25 MHz
Function List
LCDC (Config3)
Note 1.
QSPI asCore must be faster than sCore.
Note 2.
I2C asCore must be faster than or equal to sCore.
Note 3.
Available RGMII/RMII converter mode
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3.6
Section 3 Clock Generation
Clock Oscillator Connection
3.6.1
Main Clock Oscillator
There are two ways of supplying the clock signal to the main clock oscillator: connecting an oscillator or the input of an
external clock signal. The clock input mode is set based on the status of the THMODE pin.
Table 3.3
Clock Input Mode Selected for THMODE
THMODE
Clock Input Mode
Low
Oscillator Mode
High
External clock Mode
3.6.1.1
Connected a Crystal Resonator
The following figure shows an example of connecting a crystal resonator.
CL1
MCLK_XI
R
MCLK_XO
Rd
Note:
CL2
The values for CL1, CL2, R and Rd should be determined after consultation with the crystal resonator
manufacturer.
Figure 3.2
3.6.1.2
Example of Crystal Resonator Connection (Main Clock)
External Clock Input
The following figure shows an example of connection of external clock input. The MCLK_XI pin is tied-down to
ground.
MCLK_XI
MCLK_XO
Figure 3.3
External clock input
Example of External Clock Connection
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3.6.2
Section 3 Clock Generation
RTC Clock Oscillator
RTC clock supports oscillator mode only.
3.6.2.1
Connected a Crystal Resonator
The following figure shows an example of connecting a crystal resonator.
CL1
RTC_XI
R
RTC_XO
Rd
Note:
CL2
The values for CL1, CL2, R and Rd should be determined after consultation with the crystal resonator
manufacturer.
Figure 3.4
3.6.2.2
Example of Crystal Resonator Connection (RTC)
Unused RTC on the System
The following figure shows the clock pin connection if RTC is not used on your system. RZ/N1 requires that RTC_XI
pin is tied-down to ground and RTC_XO is left opened on the board.
As additional requirements related with RTC, 3.3V power supply is required to RTC_VDD33 and 3.3V input is
required to RTC_PWRGOOD input pin.
RTC_XI
RTC_XO
Figure 3.5
Open
Connection of RTC Clock Pins when RTC is Unused
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Section 4
4.1
Section 4 Reset
Reset
Overview
RZ/N1 has 2 types of reset, chip-level reset and function module level reset.
Those are shown in below table.
Table 4.1
Category of Reset
Related External
Pin
Master Reset
System Reset
Description
MRESET_N
MRESET_OUT
Reset for entire RZ/N1 LSI. All hardware resource in LSI is in reset during MRESET_N = 0,
but only RTC backup domain is exception. MRESET_OUT is 1 during MRESET_N = 0.
MRESET_OUT
Reset by internal generated event like watchdog, software trigger.
Most part of RZ/N1 is reset by this reset.
Software can distinguish source of the last reset, Master reset or System Reset, by RSTSTAT
register.
When the System reset becomes active, MRESET_OUT outputs 1 with a pulse width of
0.5 μs.
RTC Reset
—
Reset by low voltage detection circuit in RTC domain.
The reset is active when supplied voltage for RTC domain becomes below defined level.
JTAG Reset
JTAG_TRST_N
Reset for CoreSight and JTAG TAP controller.
Those circuits are reset during JTAG_TRST_N = 0
Module Reset
—
Reset for each function module in RZ/N1.
It is controlled by “RSTN_* bit in PWRCTRL_*” registers.
Table 4.2
Reset Domain Definition
Reset Type
Reset Target
Master Reset
System Reset
RTC Reset
JTAG Reset
Module Reset
Main Oscillator
—
—
—
—
—
RTC domain
—
—
—
—
PLL
—
—
—
—
USBPLL
—
—
—
RSTSTAT register
—
—
—
—
Main CPU*
—
—
—
1
NoC
—
—
—
Function module
—
—
(each module)
CoreSight
—
—
—
JTAG TAP controller
Note 1.
Cortex-A7 in RZ/N1D, RZ/N1S.
Cortex-M3 in RZ/N1L.
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4.2
Section 4 Reset
Chip-level Reset
4.2.1
Master Reset
MRESET_N external pin reset entire RZ/N1 LSI except RTC backup domain. Main oscillator and RTC oscillator are
still working during MRESET_N = 0.
CAUTION
RTC backup domain is reset by voltage detection circuit in the domain. The RTC can still count by keep supplying a
power for the domain. Therefore, the domain is reset only during entire system power up or low voltage of the power
supply.
4.2.2
System Reset
RZ/N1 system controller includes the following registers for system reset control. The reset sources are either the
software triggered, watchdog timer, or etc. Each reset source can be enabled or disabled individually and this feature
can be enabled or disabled.
Table 4.3
RZ/N1 System Reset Control Register
Address
Register Symbol
Note
4000 C0A8h
RSTSTAT
Reset Status Register
4000 C120h
RSTEN
It shows the source of the last reset.
Reset Enable Register.
This Register can enable or disable each system reset source. Enabling an active system
reset request (in RSTCTRL) will result in immediate reset of the system.
4000 C198h
RSTCTRL
Reset Control Register.
Software can use this register to initiate system reset or identify if any of the current hardware
system reset sources are requesting a system reset.
CAUTION
● USBPLL is power down mode by system reset and it is the software’s responsibility to start it again if needed.
● All programmable dividers return to their power on reset value.
● Before enabling the reset sources in RSTEN register, the software shall make sure that the corresponding reset
triggers are cleared in RSTCTRL register otherwise an immediate system reset will occur.
4.2.3
JTAG Reset
JTAG_TRST_N external pin reset CoreSight subsystem and JTAG TAP controller. JTAG TAP controller includes
boundary scan circuit. JTAG_TRST_N shall be 0 if CPU debug or JTAG TAP is not used.
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4.3
Section 4 Reset
Module Reset
The system controller is capable of providing software reset request to certain modules in the system. The registers that
contain the software module reset control bits are named “PWRCTRL_*”, the bit fields are named as “RSTN_*”.
CAUTION
Module reset must be performed with the clock supplied.
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Section 5
Section 5 IO Multiplexing
IO Multiplexing
Signals for System/Peripheral function are multiplexed with External GPIO pins. Timing sensitive signals are routed in
Level1 multiplex block, and others are routed in Level2 multiplex blocks. Those are managed by IO multiplex
configuration register.
5.1
Overview
Each GPIO[n] pins can be configured individually on following features:
● RGMII interface:
− Power supply 3.3V for GPIO[n] with n = 0..59
● Standard interface:
− Power supply 3.3V for GPIO[n] with n = 60..169
● Drive strength capability
● Pull up, pull down or none
ConfigSys1
System/Peripheral Function
Level1 functions
IO buffer config
Input
Multiplexer
Level1
Output
Enable
3.3V CMOS
Level1 Config Reg.
GPIO[n]
Level2 functions
MDIO signals
MDIO1
Multiplexer
Level2
MDIO2
for MDIO
Multiplexer
Level2
ConfigSys2
Level2 Config MDIO[m]
Level2 Config
Reg. MDIO Reg.
Figure 5.1
Level2 Config Reg.
IO Multiplex Configuration Level1, Level2
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Section 5 IO Multiplexing
Available Level1 configurations are defined as below.
Table 5.1
IO Multiplex Configuration Level1 List
Function Number
Level1 Function
0
No function (default value)
1
Drive level logic 0
2
RGMII/RMII/MII & Ethernet reference clock
3
NAND Flash & Ethernet reference clock
4
QSPI1,2
5
SDIO1,2
6
LCDC
8
External Bus Interface Master (MSEBIM)
9
External Bus Interface Slave (MSEBIS)
15
IO Multiplex are controlled by Level2
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Section 5 IO Multiplexing
Available Level2 configurations are defined as below.
Table 5.2
IO Multiplex Configuration Level2 List
Function Number
Level2 Function
0
No function (default value)
1
ETHERCAT & Cortex-M3 NMI
2
SERCOSIII
3
Extended SDIO
4
MDIO
6
Extended USB
7
Extended MSEBIM (master)
8
Extended MSEBIS (slave)
12
UART1 Inverted
13
Extended UART1 Inverted
14
UART2 Inverted
15
Extended UART2 Inverted
16
UART3 Inverted
17
Extended UART3 Inverted
18
UART1
19
Extended UART1
20
UART2
21
Extended UART2
22
UART3
23
Extended UART3
24
UART4
25
Extended UART4
26
UART5
27
Extended UART5
28
UART6
29
Extended UART6
30
UART7
31
Extended UART7
32
UART8
33
Extended UART8
34
SPI1 (Master)
36
SPI2 (Master)
38
SPI3 (Master)
40
SPI4 (Master)
42
SPI5 (Slave)
44
SPI6 (Slave)
48
BGPIO
49
CAN
50
I2C
52 to 56
PWMTimer
61
Extended A5PSW & GMAC
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5.2
Section 5 IO Multiplexing
Register Map
Table 5.3
IO Multiplexing Register Map
Address
Register Symbol
Register Name
4006 7000h + 4h × n
rGPIOs_Level1_ConfigA_[n]
(n = 0..59)
GPIO[n] RGMII Multiplexing Level1 Configuration Register
4006 7000h + 4h × n
rGPIOs_Level1_ConfigB_[n]
(n = 60..169)
GPIO[n] Standard Multiplexing Level1 Configuration Register
4006 7400h
rGPIOs_Level1_StatusProtect
GPIO Multiplexing Level1 Status and Protect Register
5100 0000h + 4h × n
rGPIOs_Level2_Config_[n]
(n = 0..169)
GPIO[n] Multiplexing Level2 Configuration Register
5100 0400h
rGPIOs_Level2_StatusProtect
GPIO Multiplexing Level2 Status and Protect Register
5100 0404h
rGPIOs_Level2_Config_MDIO1
MDIO1 Interface Configuration Register
5100 0408h
rGPIOs_Level2_Config_MDIO2
MDIO2 Interface Configuration Register
5100 0480h+ 4h × n
rGPIOs_Level2_GPIO_Int_[n]
(n = 0..7)
GPIO_Int[n] Interrupt Configuration Register
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5.3
Section 5 IO Multiplexing
Register Description
5.3.1
rGPIOs_Level1_ConfigA_[n] — GPIO[n] RGMII Multiplexing Level1
Configuration Register (n = 0..59)
Address:
Bit
Value after reset
Bit
Value after reset
Table 5.4
4006 7000h + 4h × n
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
bGPIOs_Level1_IOFunction
0
0
0
0
0
—
—
—
—
0
0
0
0
bGPIOs_Level1
bGPIOs_Level1
_PulUp
_DriveStrength
_PullDown
1
0
0
1
0
0
0
rGPIOs_Level1_ConfigA_[n] Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b12
Reserved
Read as 0.
R
b11, b10
bGPIOs_Level1_Driv
eStrength
Select drive strength capability used on GPIO.
R/W
2’b00: 4 mA
2’b01: 6 mA
2’b10: 8 mA (default value)
2’b11: 12 mA
b9, b8
bGPIOs_Level1_PulU Select a pull-up, pull-down resistor used on GPIO.
p_PullDown
2’b00: None
R/W
2’b01: Pull up (default value)
2’b10: None
2’b11: Pull down
b7 to b4
Reserved
Read as 0.
b3 to b0
bGPIOs_Level1_IOFu Select the Level1 function used on GPIO:
nction
See Table 5.1, IO Multiplex Configuration Level1 List.
R
R/W
CAUTION
● A write access is protected by bGPIOs_Level1_Config_StatusProtect bit.
● For total output current, see Note 1 of “Table 11.3, Current” in “Section 11.3.1, Current”.
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5.3.2
Section 5 IO Multiplexing
rGPIOs_Level1_ConfigB_[n] — GPIO[n] Standard Multiplexing Level1
Configuration Register (n = 60..169 (max))
Address:
Bit
Value after reset
Bit
Value after reset
Table 5.5
4006 7000h + 4h × n
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
bGPIOs_Level1_Standard
_IOFunction
0
0
0
0
0
—
—
—
—
0
0
0
0
bGPIOs_Level1
_Standard
_DriveStrength
1
0
bGPIOs_Level1
_Standard_PulUp
_PullDown
0
1
0
0
0
rGPIOs_Level1_ConfigB_[n] Register Contents
Bit Position
Bit Name
Function
b31 to b12
Reserved
Read as 0.
b11, b10
bGPIOs_Level1_Stan Select drive strength capability used on GPIO.
dard_DriveStrength
2’b00: 4 mA
R/W
R
R/W
2’b01: 6 mA
2’b10: 8 mA (default value)
2’b11: 12 mA
b9, b8
bGPIOs_Level1_Stan Select a pull-up, pull-down resistor used on GPIO.*1
dard_PulUp_PullDow
2’b00: None
n
2’b01: Pull up (default value)
R/W
2’b10: None
2’b11: Pull down
b7 to b4
Reserved
b3 to b0
bGPIOs_Level1_Stan Select the Level1 function used on GPIO.*2
dard_IOFunction
See Table 5.1, IO Multiplex Configuration Level1 List.
Read as 0.
Note 1.
GPIO[73:62] and GPIO[145:127] are configured according to GPIO[79] level at rising of MRESET_N
1: Pull up on GPIO[73:62] and GPIO[145:127]
0: Pull down on GPIO[73:62] and GPIO[145:127]
Note 2.
GPIO[79:74] are directly configured on QSPI interface in RZ/N1L.
GPIO[103] is configured on UART1_TXD by boot ROM.
R
R/W
CAUTION
● A write access is protected by bGPIOs_Level1_Config_StatusProtect bit.
● For total output current, see Note 1 of “Table 11.3, Current” in “Section 11.3.1, Current”.
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5.3.3
rGPIOs_Level1_StatusProtect — GPIO Multiplexing Level1 Status and
Protect Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 5.6
Section 5 IO Multiplexing
4006 7400h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
bGPIOs_
Level1_C
onfig_Stat
usProtect
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
bGPIOs_
Level1_B
adSequen
ce
0
0
0
0
0
0
0
0
0
0
0
0
rGPIOs_Level1_StatusProtect Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b5
Reserved
Read as 0.
R
b4
bGPIOs_Level1_Bad
Sequence
Bad sequence detection
R/W
Set “1” when it happens a bad write sequence in the rGPIOs_Level1_StatusProtect
register
Clear “0” when it happens
– Reset
– By a specific write sequence (write 4006_7402h to this register)
b3 to b1
Reserved
b0
bGPIOs_Level1_Conf Write protection of following registers
ig_StatusProtect
● rGPIOs_Level1_ConfigA_[n]
● rGPIOs_Level1_ConfigB_[n]
Read as 0.
R
R/W
0: All the registers are protected in write, read only
1: All the registers are not protected, write and read are enable
Clear “0” when it happens
– Reset
– A bad write sequence in register
Set or cleared bGPIOs_Level1_Config_StatusProtect bit by a specific write sequence
[Set]
Write 4006_7400h to this register
[Clear]
Write 4006_7401h to this register
See Protected access of GPIOs Level1 Configuration Register.
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5.3.4
Section 5 IO Multiplexing
rGPIOs_Level2_Config_[n] — GPIO[n] Multiplexing Level2 Configuration
Register (n = 0..169 (max))
Address:
Bit
Value after reset
Bit
Value after reset
Table 5.7
5100 0000h + 4h × n
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
bGPIOs_Level2_IOFunction
0
0
0
0
0
0
rGPIOs_Level2_Config_[n] Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b6
Reserved
Read as 0.
R
b5 to b0
bGPIOs_Level2_IOFu Select the Level2 function used on GPIO.
nction
See Table 5.2, IO Multiplex Configuration Level2 List.
R/W
CAUTION
A write access is protected by bGPIOs_Level2_Config_StatusProtect bit.
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
5.3.5
rGPIOs_Level2_StatusProtect — GPIO Multiplexing Level2 Status and
Protect Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 5.8
Section 5 IO Multiplexing
5100 0400h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
bGPIOs_
Level2_C
onfig_Stat
usProtect
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
bGPIOs_
Level2_B
adSequen
ce
0
0
0
0
0
0
0
0
0
0
0
0
rGPIOs_Level2_StatusProtect Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b5
Reserved
Read as 0.
R
b4
bGPIOs_Level2_Bad
Sequence
Bad sequence detection
R/W
Set “1” when it happens a bad write sequence in the rGPIOs_Level2_StatusProtect
register
Clear “0” when it happens
– Reset
– By a specific write sequence (write 5100_0420h to this register)
Write {Upper 29 bits of rGPIOs_Level2_StatusProtect address, 3’b010} to
rGPIOs_Level2_StatusProtect register
b3 to b1
Reserved
b0
bGPIOs_Level2_Conf Write protection of following registers
ig_StatusProtect
● rGPIOs_Level2_Config_[n]
Read as 0.
R
R/W
● rGPIOs_Level2_Config_MDIO1
● rGPIOs_Level2_Config_MDIO2
0: All the registers are protected in write, read only
1: All the registers are not protected, write and read are enable
Clear “0” when it happens
– Reset
– A bad write sequence in register
Set or cleared bGPIOs_Level2_Config_StatusProtect bit by a specific write sequence
[Set]
Write 5100_0400h to this register
[Clear]
Write 5100_0401h to this register
See Protected access of GPIO Level2 Configuration Register
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5.3.6
Section 5 IO Multiplexing
rGPIOs_Level2_Config_MDIO1 — MDIO1 Interface Configuration Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 5.9
5100 0404h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
bGPIOs_Level2_Config_
MDIO1
0
0
0
rGPIOs_Level2_Config_MDIO1 Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b3
Reserved
Read as 0.
R
b2 to b0
bGPIOs_Level2_Conf MDIO1 interface configuration.
ig_MDIO1
3’b000: Floating
R/W
3’b001: GMAC1
3’b010: GMAC2
3’b011: ETHERCAT
3’b100: SERCOSIII MDIO1
3’b101: SERCOSIII MDIO2
3’b110: HW-RTOS GMAC
3’b111: Advanced 5port Switch
CAUTION
A write access is protected by bGPIOs_Level2_Config_StatusProtect bit.
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5.3.7
Section 5 IO Multiplexing
rGPIOs_Level2_Config_MDIO2 — MDIO2 Interface Configuration Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 5.10
5100 0408h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
bGPIOs_Level2_Config_
MDIO2
0
0
0
rGPIOs_Level2_Config_MDIO2 Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b3
Reserved
Read as 0.
R
b2 to b0
bGPIOs_Level2_Conf MDIO2 interface configuration.
ig_MDIO2
Same as rGPIOs_Level2_Config_MDIO1
R/W
CAUTION
A write access is protected by bGPIOs_Level2_Config_StatusProtect bit.
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5.3.8
Section 5 IO Multiplexing
rGPIOs_Level2_GPIO_Int_[n] — GPIO_Int[n] Interrupt Configuration
Register (n = 0..7)
GPIO_Int[n] (IRQ103 to IRQ110) interrupt line configuration with n = 0..7.
Address:
Bit
Value after reset
Bit
Value after reset
Table 5.11
5100 0480h + 4h × n
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
bGPIOs_Level2_GPIO_Int
0
0
0
0
0
rGPIOs_Level2_GPIO_Int_[n] Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b7
Reserved
Read as 0.
R
b6 to b0
bGPIOs_Level2_GPIO_Int For each interrupt GPIO_Int[n]
R/W
Selects an interrupt source from 3x32 possible interrupt sources
BGPIO1_Int[31:0] or BGPIO2_Int[31:0] or BGPIO3_Int[31:0]
Select function used on multiplexing level2:
● Interrupt sources routed from BGPIO1:
7’b00_00000: BGPIO1_Int[0]
....... ........ ......
7’b00_11111: BGPIO1_Int[31]
● Interrupt sources routed from BGPIO2:
7’b01_00000: BGPIO2_Int[0]
........ ........ ......
7’b01_11111: BGPIO2_Int[31]
● Interrupt sources routed from BGPIO3:
7’b10_00000: BGPIO3_Int[0]
........ ........ ......
7’b10_11111: BGPIO3_Int[31]
● Others
7’b11_xxxxx: Reserved
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5.4
5.4.1
Section 5 IO Multiplexing
Operation
Protected Access of GPIOs Level1 Configuration Register
Lock register to protect registers from unexpected behavior, a specific sequence must be written to change protect
status. Set or cleared a protect bit dedicated bGPIOs_Level1_Config_StatusProtect, allowing write of following
registers:
− rGPIOs_Level1_ConfigA_[n]
− rGPIOs_Level1_ConfigB_[n]
● Unprotect (writable) — Set bGPIOs_Level1_Config_StatusProtect
Write {Upper 29 bits of rGPIOs_Level1_StatusProtect address, 3’b000} to rGPIOs_Level1_StatusProtect register
i.e. *(4006 7400h) = 4006 7400h
● Protect — Clear bGPIOs_Level1_Config_StatusProtect
Write {Upper 29 bits of rGPIOs_Level1_StatusProtect address, 3’b001} to rGPIOs_Level1_StatusProtect register
i.e. *(4006 7400h) = 4006 7401h
● Clear BadSequence Bit
If incorrect data is written to rGPIOs_Level1_StatusProtect Register,
bGPIOs_Level1_BadSequence is set
bGPIOs_Level1_Config_StatusProtect is cleared.
The bit is cleared by
Write {Upper 29 bits of rGPIOs_Level1_StatusProtect address, 3’b010} to rGPIOs_Level1_StatusProtect register
i.e. *(4006 7400h) = 4006 7402h
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5.4.2
Section 5 IO Multiplexing
Protected Access of GPIOs Level2 Configuration Register
Lock register to protect registers from unexpected behavior, a specific sequence must be written to change protect
status. Set or cleared a protect bit dedicated bGPIOs_Level2_Config_StatusProtect, allowing write of following
registers:
− rGPIOs_Level2_Config_[n]
− rGPIOs_Level2_Config_MDIO1
− rGPIOs_Level2_Config_MDIO2
● Unprotect (writable) — Set bGPIOs_Level2_Config_StatusProtect
Write {Upper 29 bits of rGPIOs_Level2_StatusProtect address, 3’b000} to rGPIOs_Level2_StatusProtect register
i.e. *(5100 0400h) = 5100 0400h
● Protect — Clear bGPIOs_Level2_Config_StatusProtect
Write {Upper 29 bits of rGPIOs_Level2_StatusProtect address, 3’b001} to rGPIOs_Level2_StatusProtect register
i.e. *(5100 0400h) = 5100 0401h
● Clear BadSequence Bit
If incorrect data is written to rGPIOs_Level2_StatusProtect Register,
bGPIOs_Level2_BadSequence is set
bGPIOs_Level2_Config_StatusProtect is cleared.
The bit is cleared by
Write {Upper 29 bits of rGPIOs_Level2_StatusProtect address, 3’b010} to rGPIOs_Level2_StatusProtect register
i.e. *(5100 0400h) = 5100 0402h
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5.4.3
Section 5 IO Multiplexing
Configuration of GPIO Interrupt Line
Input
GPIO signals
Multiplexer
Level2
BGPIO1
GPIO
module
module
GPIO
module
BGPIO1_int[31:0]
BGPIO2_int[31:0]
BGPIO3_int[31:0]
Multiplexer
Level1
GPIO
Interrupt
Multiplexer
Output
Enable
3.3V CMOS
Interrupt line to CPUs, GPIO_Int[n], are configured by rGPIOs_Level2_GPIO_Int_[n]. GPIO_Int[n] are selected from
32bits × 3 interrupts output of BGPIO modules.
GPIO[n]
GPIO_int[n] n=0..7
ConfigSys2
GPIO_Int[n] Interrupt
Configuration Reg.
Figure 5.2
GPIO_Int[n] Configuration
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Section 6
6.1
Section 6 System Control
System Control
Overview
The RZ/N1 system controller includes registers for setting clock, reset, NoC (Network-on-Chip) management and chiplevel LSI configuration. Please refer to Clock Generation, Reset, Operating Mode chapter for more detail.
6.2
Register Map
Table 6.1
Clock Control Registers (1/2)
Address
Register Symbol
Register Name
4000 C00Ch
PWRCTRL_SDIO1
Power Management Control for SDIO1
4000 C010h
PWRSTAT_SDIO1
Power Management Status for SDIO1
4000 C01Ch
PWRCTRL_USB
Power Management Control for USB2.0
4000 C020h
PWRSTAT_USB
Power Management Status for USB2.0
4000 C02Ch
PWRCTRL_MSEBI
Power Management Control for MSEBI
4000 C030h
PWRSTAT_MSEBI
Power Management Status for MSEBI
4000 C034h
PWRCTRL_PG0_0
Power Management Control #0 for PG0
4000 C038h
PWRSTAT_PG0
Power Management Status for PG0
4000 C03Ch
PWRCTRL_PG0_1
Power Management Control #1 for PG0
4000 C040h
PWRCTRL_PG1_1
Power Management Control #1 for PG1
4000 C044h
PWRCTRL_PG1_2
Power Management Control #2 for PG1
4000 C04Ch
PWRCTRL_DMA
Power Management Control for DMAC1 & DMAC2
4000 C050h
PWRCTRL_NFLASH
Power Management Control for NAND FLASH Controller
4000 C054h
PWRCTRL_QSPI1
Power Management Control for QSPI1
4000 C058h
PWRSTAT_DMA
Power Management Status for DMAC1 & DMAC2
4000 C05Ch
PWRSTAT_NFLASH
Power Management Status for NAND FLASH Controller
4000 C060h
PWRSTAT_QSPI1
Power Management Status for QSPI1
4000 C064h
(RZ/N1D) PWRCTRL_DDRC
Power Management Control for DDR Memory Controller
(RZ/N1S) PWRCTRL_QSPI2DIV
Clock Divider Control for QSPI2
(RZ/N1L) Reserved
4000 C068h
PWRCTRL_EETH
Power Management Control for External Ethernet Clock
4000 C06Ch
PWRCTRL_MAC1
Power Management Control for GMAC1
4000 C070h
PWRCTRL_MAC2
Power Management Control for GMAC2
4000 C074h
(RZ/N1D) PWRSTAT_DDRC
Power Management Status for DDR Memory Controller
(RZ/N1S, RZ/N1L) Reserved
4000 C078h
PWRSTAT_MAC1
Power Management Status for GMAC1
4000 C07Ch
PWRSTAT_MAC2
Power Management Status for GMAC2
4000 C080h
PWRCTRL_ECAT
Power Management Control for ETHERCAT
4000 C084h
PWRCTRL_SERCOS
Power Management Control for SERCOSIII
4000 C088h
PWRSTAT_ECAT
Power Management Status for ETHERCAT
4000 C08Ch
PWRSTAT_SERCOS
Power Management Status for SERCOSIII
4000 C090h
(RZ/N1D) PWRCTRL_HSR
Power Management Control for HSR
(RZ/N1S) PWRCTRL_QSPI2
Power Management Control for QSPI2
(RZ/N1L) Reserved
4000 C094h
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Rev.1.40
Clock Divider Control for A5PSW
Page 61 of 263
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Table 6.1
Section 6 System Control
Clock Control Registers (2/2)
Address
Register Symbol
Register Name
4000 C098h
(RZ/N1D) PWRSTAT_HSR
Power Management Status for HSR
(RZ/N1S) PWRSTAT_QSPI2
Power Management Status for QSPI2
(RZ/N1L) Reserved
4000 C09Ch
PWRSTAT_SWITCH
Power Management Status for A5PSW
4000 C0C8h
PWRCTRL_SDIO2
Power Management Control for SDIO2
4000 C0CCh
PWRSTAT_SDIO2
Power Management Status for SDIO2
4000 C0E0h
PWRCTRL_OPPDIV
Clock Divider Control for OPP Modes
4000 C0E4h
PWRCTRL_CA7DIV
Clock Divider Control for CA7
4000 C0E8h
PWRCTRL_PG2_25MHZ
Power Management Control for PG2 25MHz
4000 C0ECh
PWRCTRL_PG1_PR2
Power Management Control for PG1 Program2
4000 C0F0h
PWRCTRL_PG3_48MHZ
Power Management Control for PG3 48MHz
4000 C0F4h
PWRCTRL_PG4
Power Management Control for PG4
4000 C0F8h
PWRCTRL_PG1_PR2DIV
Clock Divider Control for PG1 Program2
4000 C0FCh
PWRCTRL_PG1_PR3
Power Management Control for PG1 Program3
4000 C100h
PWRCTRL_PG1_PR3DIV
Clock Divider Control for PG1 Program3
4000 C104h
PWRCTRL_PG1_PR4
Power Management Control for PG1 Program4
4000 C108h
PWRCTRL_PG1_PR4DIV
Clock Divider Control for PG1 Program4
4000 C10Ch
PWRCTRL_PG4_PR1
Power Management Control for PG4 Program1
4000 C110h
PWRCTRL_PG4_PR1DIV
Clock Divider Control for PG4 Program1
4000 C124h
PWRCTRL_QSPI1DIV
Clock Divider Control for QSPI1
4000 C128h
PWRCTRL_SDIO1DIV
Clock Divider Control for SDIO1
4000 C12Ch
PWRCTRL_SDIO2DIV
Clock Divider Control for SDIO2
4000 C130h
PWRCTRL_SWITCH
Power Management Control for A5PSW
4000 C134h
PWRCTRL_PG0_ADCDIV
Clock Divider Control for PG0 ADC
4000 C138h
PWRCTRL_PG0_I2CDIV
Clock Divider Control for PG0 I2C
4000 C13Ch
PWRCTRL_PG0_UARTDIV
Clock Divider Control for PG0 UART
4000 C140h
PWRCTRL_RTC
Power Management Control for RTC
4000 C144h
PWRSTAT_RTC
Power Management Status for RTC
4000 C148h
PWRCTRL_NFLASHDIV
Clock Divider Control for NAND FLASH Controller
4000 C154h
(RZ/N1D, RZ/N1S) PWRCTRL_ROM
Power Management Control for ROM
(RZ/N1L) Reserved
4000 C158h
PWRSTAT_PG1
Power Management Status for PG1
4000 C15Ch
PWRSTAT_PG2_25MHZ
Power Management Status for PG2 25MHz
4000 C160h
PWRSTAT_PG3_48MHZ
Power Management Status for PG3 48MHz
4000 C164h
PWRSTAT_PG4
Power Management Status for PG4
4000 C170h
(RZ/N1D, RZ/N1S) PWRSTAT_ROM
Power Management Status for ROM
4000 C174h
PWRCTRL_CM3
Power Management Control for CM3
4000 C178h
PWRSTAT_CM3
Power Management Status for CM3
(RZ/N1L) Reserved
4000 C17Ch
PWRSTAT_RINCTRL
Power Management Status for R-IN Engine Accessory Register
4000 C180h
PWRSTAT_SWITCHCTRL
Power Management Status for Ethernet Accessory Register
4000 C184h
PWRCTRL_RINCTRL
Power Management Control for R-IN Engine Accessory Register
4000 C188h
PWRCTRL_SWITCHCTRL
Power Management Control for Ethernet Accessory Register
4000 C18Ch
PWRCTRL_HWRTOS
Power Management Control for HW-RTOS
4000 C190h
PWRCTRL_HWRTOS_MDCDIV
Clock Divider Control for HW-RTOS GMAC MDC Clock
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Table 6.2
Section 6 System Control
Register Map of Reset Control (1/2)
Address
Register Symbol
Register Name
4000 C00Ch
PWRCTRL_SDIO1
Power Management Control for SDIO1
4000 C010h
PWRSTAT_SDIO1
Power Management Status for SDIO1
4000 C018h
SYSSTAT
System Status Flags Register
4000 C01Ch
PWRCTRL_USB
Power Management Control for USB2.0
4000 C020h
PWRSTAT_USB
Power Management Status for USB2.0
4000 C02Ch
PWRCTRL_MSEBI
Power Management Control for MSEBI
4000 C030h
PWRSTAT_MSEBI
Power Management Status for MSEBI
4000 C034h
PWRCTRL_PG0_0
Power Management Control #0 for PG0
4000 C038h
PWRSTAT_PG0
Power Management Status for PG0
4000 C03Ch
PWRCTRL_PG0_1
Power Management Control #1 for PG0
4000 C040h
PWRCTRL_PG1_1
Power Management Control #1 for PG1
4000 C044h
PWRCTRL_PG1_2
Power Management Control #2 for PG1
4000 C04Ch
PWRCTRL_DMA
Power Management Control for DMAC1 & DMAC2
4000 C050h
PWRCTRL_NFLASH
Power Management Control for NAND FLASH Controller
4000 C054h
PWRCTRL_QSPI1
Power Management Control for QSPI1
4000 C058h
PWRSTAT_DMA
Power Management Status for DMAC1 & DMAC2
4000 C05Ch
PWRSTAT_NFLASH
Power Management Status for NAND FLASH Controller
4000 C060h
PWRSTAT_QSPI1
Power Management Status for QSPI1
4000 C064h
(RZ/N1D) PWRCTRL_DDRC
Power Management Control for DDR memory controller
(RZ/N1S) PWRCTRL_QSPI2DIV
Clock divider Control for QSPI2
(RZ/N1L) Reserved
4000 C068h
PWRCTRL_EETH
Power Management Control for External Ethernet Clock
4000 C06Ch
PWRCTRL_MAC1
Power Management Control for GMAC1
4000 C070h
PWRCTRL_MAC2
Power Management Control for GMAC2
4000 C074h
(RZ/N1D) PWRSTAT_DDRC
Power Management Status for DDR memory controller
(RZ/N1S, RZ/N1L) Reserved
4000 C078h
PWRSTAT_MAC1
Power Management Status for GMAC1
4000 C07Ch
PWRSTAT_MAC2
Power Management Status for GMAC2
4000 C080h
PWRCTRL_ECAT
Power Management Control for ETHERCAT
4000 C084h
PWRCTRL_SERCOS
Power Management Control for SERCOSIII
4000 C088h
PWRSTAT_ECAT
Power Management Status for ETHERCAT
4000 C08Ch
PWRSTAT_SERCOS
Power Management Status for SERCOSIII
4000 C090h
(RZ/N1D) PWRCTRL_HSR
Power Management Control for HSR
(RZ/N1S) PWRCTRL_QSPI2
Power Management Control for QSPI2
(RZ/N1L) Reserved
4000 C098h
(RZ/N1D) PWRSTAT_HSR
Power Management Status for HSR
(RZ/N1S) PWRSTAT_QSPI2
Power Management Status for QSPI2
(RZ/N1L) Reserved
4000 C09Ch
PWRSTAT_SWITCH
Power Management Status for A5PSW
4000 C0A8h
RSTSTAT
Reset Status Register
4000 C0C0h
USBSTAT
Status information for USBPLL
4000 C0C8h
PWRCTRL_SDIO2
Power Management Control for SDIO2
4000 C0CCh
PWRSTAT_SDIO2
Power Management Status for SDIO2
4000 C0E8h
PWRCTRL_PG2_25MHZ
Power Management Control for PG2 25MHz
4000 C0ECh
PWRCTRL_PG1_PR2
Power Management Control for PG1 Program2
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Table 6.2
Section 6 System Control
Register Map of Reset Control (2/2)
Address
Register Symbol
Register Name
4000 C0F0h
PWRCTRL_PG3_48MHZ
Power Management Control for PG3 48MHz
4000 C0F4h
PWRCTRL_PG4
Power Management Control for PG4
4000 C0FCh
PWRCTRL_PG1_PR3
Power Management Control for PG1 Program3
4000 C104h
PWRCTRL_PG1_PR4
Power Management Control for PG1 Program4
4000 C10Ch
PWRCTRL_PG4_PR1
Power Management Control for PG4 Program1
4000 C120h
RSTEN
Reset Enable Register
4000 C130h
PWRCTRL_SWITCH
Power Management Control for A5PSW
4000 C140h
PWRCTRL_RTC
Power Management Control for RTC
4000 C144h
PWRSTAT_RTC
Power Management Status for RTC
4000 C154h
(RZ/N1D, RZ/N1S) PWRCTRL_ROM
Power Management Control for ROM
4000 C158h
PWRSTAT_PG1
(RZ/N1L) Reserved
Power Management Status for PG1
4000 C15Ch
PWRSTAT_PG2_25MHZ
Power Management Status for PG2 25MHz
4000 C160h
PWRSTAT_PG3_48MHZ
Power Management Status for PG3 48MHz
4000 C164h
PWRSTAT_PG4
Power Management Status for PG4
4000 C170h
(RZ/N1D, RZ/N1S) PWRSTAT_ROM
Power Management Status for ROM
(RZ/N1L) Reserved
4000 C174h
PWRCTRL_CM3
Power Management Control for CM3
4000 C178h
PWRSTAT_CM3
Power Management Status for CM3
4000 C17Ch
PWRSTAT_RINCTRL
Power Management Status for R-IN Engine Accessory Register
4000 C180h
PWRSTAT_SWITCHCTRL
Power Management Status for Ethernet Accessory Register
4000 C184h
PWRCTRL_RINCTRL
Power Management Control for R-IN Engine Accessory Register
4000 C188h
PWRCTRL_SWITCHCTRL
Power Management Control for Ethernet Accessory Register
4000 C18Ch
PWRCTRL_HWRTOS
Power Management Control for HW-RTOS
4000 C198h
RSTCTRL
Reset Control Register
Table 6.3
Register Map of System Configuration
Address
Register Symbol
Register Name
4000 C000h
CFG_USB
USB Mode Configuration Register
4000 C004h
OPMODE
System and Boot Configuration Register
4000 C008h
CFG_SDIO1
SDIO1 Configuration Register
4000 C014h
DBGCON
Debug Control Register
4000 C0A0h
CFG_DMAMUX
DMAC1 & DMAC2 Multiplexer Register
4000 C0A4h
CFG_GPIOT_PTEN_1A
GPIO Trigger Enable Register 1A
4000 C0B0h
CFG_GPIOT_PTEN_1B
GPIO Trigger Enable Register 1B
4000 C0B4h
CFG_GPIOT_PTEN_2A
GPIO Trigger Enable Register 2A
4000 C0B8h
CFG_GPIOT_PTEN_2B
GPIO Trigger Enable Register 2B
4000 C0BCh
CFG_GPIOT_TSRC
GPIO Trigger Source Select Register
4000 C0C4h
CFG_SDIO2
SDIO2 Configuration Register
4000 C0D8h
CFG_GPIOT_PTEN_3A
GPIO Trigger Enable Register 3A
4000 C0DCh
CFG_GPIOT_PTEN_3B
GPIO Trigger Enable Register 3B
4000 C19Ch
VERSION
Product Version Register
4000 C204h
BOOTADDR
Cortex-A7 processor1 Boot Address Configuration Register
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3
Section 6 System Control
Register Description
6.3.1
PWRCTRL_SWITCHDIV — Clock Divider Control for A5PSW
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.4
4000 C094h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
1
0
1
DIV
0
0
0
0
PWRCTRL_SWITCHDIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b7
Reserved
b6 to b0
DIV
R
Clock Divider for A5PSW clock (A5PSW_SXCLK)
R/W
Valid range: 5
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.2
Section 6 System Control
PWRCTRL_OPPDIV — Clock Divider Control for OPP Modes
This register scales the reference frequency of the system. This value has direct effect on interconnect clocks and
Cortex-A7 clock.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.5
4000 C0E0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
1
0
DIV
0
0
0
PWRCTRL_OPPDIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b5
Reserved
b4 to b0
DIV
R
Clock Divider for the NoC clock
R/W
Valid values are: [2,4,8,16]
NOTE
● This register values should be changed to initial value in case of entering RTC backup mode.
● Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
● Changing the frequency of the main interconnect effects the reference clock frequency of the Watchdog timers.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.3
PWRCTRL_CA7DIV — Clock Divider Control for CA7
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.6
Section 6 System Control
4000 C0E4h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
DIV
0
1
0
PWRCTRL_CA7DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b3
Reserved
b2 to b0
DIV
R
Clock Divider for the Cortex-A7 processor clock
R/W
Valid values are: [1,2,4]
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.4
PWRCTRL_PG1_PR2DIV — Clock Divider Control for PG1 Program2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.7
Section 6 System Control
4000 C0F8h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
1
1
0
0
DIV
0
0
0
0
PWRCTRL_PG1_PR2DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b8
Reserved
b7 to b0
DIV
R
PG1 Program2 Clock Divider for UART[m]_SCLK (m = 4..8)
R/W
Valid range: 12 to 128
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.5
PWRCTRL_PG1_PR3DIV — Clock Divider Control for PG1 Program3
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.8
Section 6 System Control
4000 C100h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
1
0
0
0
DIV
0
0
0
0
PWRCTRL_PG1_PR3DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b8
Reserved
b7 to b0
DIV
R
PG1 Program3 Clock Divider for SPI[m]_SCLK (m = 1..4)
R/W
Valid range (also depend on frequency mode): 8–128
Note) SPI[m]_SCLK must be less than or equal to the frequency of NoC clock.
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.6
PWRCTRL_PG1_PR4DIV — Clock Divider Control for PG1 Program4
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.9
Section 6 System Control
4000 C108h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
1
0
0
0
DIV
0
0
0
0
PWRCTRL_PG1_PR4DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b8
Reserved
b7 to b0
DIV
R
PG1 Program4 Clock Divider for SPI[m]_SCLK (m = 5, 6)
R/W
Valid range (also depend on frequency mode): 8–128
Note) SPI[m]_SCLK must be less than or equal to the frequency of NoC clock.
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.7
PWRCTRL_PG4_PR1DIV — Clock Divider Control for PG4 Program1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.10
Section 6 System Control
4000 C110h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
1
1
0
0
DIV
0
0
0
0
PWRCTRL_PG4_PR1DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b8
Reserved
b7 to b0
DIV
R
PG4 Program1 Clock Divider for LCD_ECLK
R/W
Valid range (also depend on frequency mode): 12–200
Note) LCD_ECLK must be slower than LCD_HCLK.
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.8
PWRCTRL_QSPI1DIV — Clock Divider Control for QSPI1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.11
Section 6 System Control
4000 C124h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
1
1
0
DIV
0
0
0
0
PWRCTRL_QSPI1DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b7
Reserved
b6 to b0
DIV
R
Clock Divider for QSPI1_REFCLK
R/W
Valid range: 4–64
Note) QSPI1_REFCLK must be faster than NoC clock.
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.9
PWRCTRL_SDIO1DIV — Clock Divider Control for SDIO1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.12
Section 6 System Control
4000 C128h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
0
1
0
0
DIV
0
0
0
1
PWRCTRL_SDIO1DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b8
Reserved
b7 to b0
DIV
R
Clock Divider for SDIO1_ECLK
R/W
Valid range: 20–100
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
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Rev.1.40
Page 73 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.10
PWRCTRL_SDIO2DIV — Clock Divider Control for SDIO2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.13
Section 6 System Control
4000 C12Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
0
1
0
0
DIV
0
0
0
1
PWRCTRL_SDIO2DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b8
Reserved
b7 to b0
DIV
R
Clock Divider for SDIO2_ECLK
R/W
Valid range: 20–100
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
R01UH0750EJ0140
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.11
PWRCTRL_PG0_ADCDIV — Clock Divider Control for PG0 ADC
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.14
Section 6 System Control
4000 C134h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
X
X
X
X
X
X
1
0
0
1
0
DIV
0
0
0
0
1
PWRCTRL_PG0_ADCDIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b10
Reserved
b9 to b0
DIV
R
Clock Divider for ADC_CLK
R/W
Valid range: 50–250
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
R01UH0750EJ0140
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Rev.1.40
Page 75 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.12
PWRCTRL_PG0_I2CDIV — Clock Divider Control for PG0 I2C
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.15
Section 6 System Control
4000 C138h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
1
0
0
DIV
0
0
0
1
PWRCTRL_PG0_I2CDIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b7
Reserved
b6 to b0
DIV
R
Clock Divider for I2C[m]_SCLK (m = 1, 2)
R/W
Valid range (also depend on frequency mode): 12–64
Note) I2C[m]_SCLK must be faster than or equal to the frequency of I2C[m]_PCLK.
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 76 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.13
PWRCTRL_PG0_UARTDIV — Clock Divider Control for PG0 UART
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.16
Section 6 System Control
4000 C13Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
1
1
0
0
DIV
0
0
0
0
PWRCTRL_PG0_UARTDIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b8
Reserved
b7 to b0
DIV
R
Clock Divider for UART[m]_SCLK (m = 1..3)
R/W
Valid range: 12–128
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 77 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.14
PWRCTRL_NFLASHDIV — Clock Divider Control for NAND FLASH
Controller
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.17
Section 6 System Control
4000 C148h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
1
0
0
DIV
0
0
0
1
PWRCTRL_NFLASHDIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
R/W
b30 to b7
Reserved
b6 to b0
DIV
0: Clock setting has been applied, new setting may be written to DIV.
R
Clock Divider for NAND_ECLK
R/W
Valid range: 12–64
Note) If PWRCTRL_OPPDIV.DIV = 2 then the maximum value is 32.
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 78 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.15
PWRCTRL_HWRTOS_MDCDIV — Clock Divider Control for HW-RTOS
GMAC MDC Clock
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.18
Section 6 System Control
4000 C190h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
X
X
X
X
X
X
1
0
0
0
0
DIV
0
0
0
1
0
PWRCTRL_HWRTOS_MDCDIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
R/W
b30 to b10
Reserved
b9 to b0
DIV
0: Clock setting has been applied, new setting may be written to DIV.
R
Clock Divider for HWRTOS_MDCCLK
R/W
Valid values are: [80,160,320,640]
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 79 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.16
PWRCTRL_QSPI2DIV — Clock Divider Control for QSPI2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.19
Section 6 System Control
4000 C064h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
1
1
0
DIV
0
0
0
0
PWRCTRL_QSPI2DIV Register Contents
Bit Position
Bit Name
Function
R/W
b31
BUSY
Register Write (BUSY = 1) triggers the divider value change. Register Read Shows
the status of the Programmable divider.
R/W
1: Divider setting is being changed, changing DIV value is forbidden and results in
non-deterministic behavior.
0: Clock setting has been applied, new setting may be written to DIV.
b30 to b7
Reserved
b6 to b0
DIV
R
Clock Divider for QSPI2_REFCLK
R/W
Valid range: 4–64
Note) QSPI2_REFCLK must be faster than NoC clock.
NOTE
Writing to this register is forbidden and results in a bus error response when BUSY field is asserted.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 80 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.17
PWRCTRL_SDIO1 — Power Management Control for SDIO1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.20
Section 6 System Control
4000 C00Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
CLKEN MIREQ SLVRD RSTN_ CLKEN
_B
_A
Y_A
A
_A
1
1
0
1
1
PWRCTRL_SDIO1 Register Contents
Bit Position
Bit Name
b31 to b5
Reserved
Function
b4
CLKEN_B
R/W
R
Clock Enable for SDIO1_ECLK (external interface)
R/W
0: Disable
1: Enable
b3
MIREQ_A
AHBM Idle Request to the NoC interconnect for SDIO1
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the AHBS is ready for SDIO1 access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for SDIO1_HCLK domain. If set to 0, reset the NoC interconnect for
SDIO1.
R/W
b0
CLKEN_A
Clock Enable for SDIO1_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 81 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.18
PWRSTAT_SDIO1 — Power Management Status for SDIO1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.21
Section 6 System Control
4000 C010h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC SCON_
_A
K_A
A
0
0
0
PWRSTAT_SDIO1 Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
MISTAT_A
R/W
R
AHBM Idle Status of the NoC interconnect for SDIO1
R
0: Active
1: Idle
b1
MIRACK_A
AHBM Idle Request Acknowledge for SDIO1
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
AHBS NoC Interconnection Status for SDIO1
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 82 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.19
SYSSTAT — System Status Flags Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.22
Section 6 System Control
4000 C018h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
PKGMO
DE
—
X
X
X
X
X
X
X
X
X
0
1
CA7_S
CA7_STANDBY CA7_STANDBY
TANDB
WFI
WFE
YWFIL2
0
0
0
0
0
SYSSTAT Register Contents
Bit Position
Bit Name
b31 to b7
Reserved
Function
b6
PKGMODE
R/W
R
Package type
R
(RZ/N1D)
0: 400 pin package
1: 324 pin package
(RZ/N1S)
0: 324 pin package
1: 196 pin package
(RZ/N1L)
1: 196 pin package
b5
Reserved
b4
CA7_STANDBYWFIL
2
R
Indicates if the L2 memory system is in WFI state:
R
When in the WFI state, all Cortex-A7 processors are in the WFI state.
0: L2 memory system not in WFI state
1: L2 memory system in WFI state
b3, b2
CA7_STANDBYWFI
Indicates if a Cortex-A7 processor is in WFI state:
R
0: Processor not in WFI state
1: Processor in WFI state
Bit3 (RZ/N1D) represents processor 1. (RZ/N1S) Reserved.
Bit2 represents processor 0.
b1, b0
CA7_STANDBYWFE
Indicates if a Cortex-A7 processor is in WFE state:
R
0: Processor not in WFE state
1: Processor in WFE state
Bit1 (RZ/N1D) represents processor 1. (RZ/N1S) Reserved.
Bit0 represents processor 0.
NOTE
Bit 5 to 0 are reserved bits for RZ/N1L.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 83 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.20
PWRCTRL_USB — Power Management Control for USB2.0
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.23
Section 6 System Control
4000 C01Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
RSTN_ CLKEN CLKEN MIREQ CLKEN MIREQ RSTN_ CLKEN
F
_E
_C
_B
_B
_A
A
_A
1
1
1
1
1
1
1
1
PWRCTRL_USB Register Contents
Bit Position
Bit Name
b31 to b8
Reserved
Function
R/W
b7
RSTN_F
Active low Reset for 48 MHz clock domain. If set to 0, reset the complete 48 MHz
clock domain.
R/W
b6
CLKEN_E
Clock Enable for USB_PCICLK
R/W
R
0: Disable
1: Enable
b5
CLKEN_C
Clock Enable for USB_HCLKPM (internal bus—Power Management)
R/W
0: Disable
1: Enable
b4
MIREQ_B
Idle Request to the NoC interconnect for USB Function
R/W
0: Active
1: Idle
b3
CLKEN_B
Clock Enable for USB_HCLKF (Internal bus—USB Function)
R/W
0: Disable
1: Enable
b2
MIREQ_A
Idle Request to the NoC interconnect for USB Host
R/W
0: Active
1: Idle
b1
RSTN_A
Active low Reset for USB_HCLKH domain. If set to 0, reset the NoC interconnect for
USB.
R/W
b0
CLKEN_A
Clock Enable for USB_HCLKH (internal bus—USB Host)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 84 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.21
PWRSTAT_USB — Power Management Status for USB2.0
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.24
Section 6 System Control
4000 C020h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC MISTAT MIRAC
_B
K_B
_A
K_A
0
0
0
0
PWRSTAT_USB Register Contents
Bit Position
Bit Name
b31 to b4
Reserved
Function
b3
MISTAT_B
R/W
R
Idle Status of the NoC interconnect for USB Function
R
0: Active
1: Idle
b2
MIRACK_B
Idle Request Acknowledge for USB Function
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b1
MISTAT_A
Idle Status of the NoC interconnect for USB Host
R
0: Active
1: Idle
b0
MIRACK_A
Idle Request Acknowledge for USB Host
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 85 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.22
PWRCTRL_MSEBI — Power Management Control for MSEBI
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.25
Section 6 System Control
4000 C02Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
SLVRD RSTN_ CLKEN MIREQ SLVRD RSTN_ CLKEN
Y_B
B
_B
_A
Y_A
A
_A
0
1
1
1
0
1
1
PWRCTRL_MSEBI Register Contents
Bit Position
Bit Name
b31 to b7
Reserved
Function
b6
SLVRDY_B
R/W
R
Indicates to the NoC interconnect that the AHBS is ready for MSEBI master access
R/W
0: Not Ready
1: Ready
b5
RSTN_B
Active low Reset for MSEBIM_HCLK domain
R/W
b4
CLKEN_B
Clock Enable for MSEBIM_HCLK
R/W
0: Disable
1: Enable
b3
MIREQ_A
AHBM Idle Request to the NoC interconnect for MSEBI slave
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the AHBS is ready for MSEBI slave access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for MSEBIS_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for MSEBIS_HCLK
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 86 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.23
PWRSTAT_MSEBI — Power Management Status for MSEBI
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.26
Section 6 System Control
4000 C030h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
SCON_ MISTAT MIRAC SCON_
B
_A
K_A
A
0
0
0
0
PWRSTAT_MSEBI Register Contents
Bit Position
Bit Name
b31 to b4
Reserved
b3
SCON_B
Function
R/W
R
NoC Interconnection Status for MSEBI master
R
0: Disconnected
1: Connected
b2
MISTAT_A
AHBM Idle Status of the NoC interconnect for MSEBI slave
R
0: Active
1: Idle
b1
MIRACK_A
AHBM Idle Request Acknowledge for MSEBI slave
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
AHBS NoC Interconnection Status for MSEBI slave
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 87 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.24
Section 6 System Control
PWRCTRL_PG0_0 — Power Management Control #0 for PG0
Address:
Bit
b31
—
Value after reset
Bit
4000 C034h
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
UARTC RSTN_ CLKEN RSTN_ CLKEN RSTN_I CLKEN RSTN_I CLKEN RSTN_ CLKEN RSTN_ CLKEN SLVRD RSTN_
LKSEL
J2
_J2
J1
_J1
2
_I2
1
_I1
H2
_H2
H1
_H1
Y_F
F
X
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN
_F
Y_E
E
_E
Y_D
D
_D
Y_C
C
_C
Y_B
B
_B
Y_A
A
_A
Value after reset
Table 6.27
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
PWRCTRL_PG0_0 Register Contents (1/2)
Bit Position
Bit Name
b31
Reserved
Function
b30
UARTCLKSEL
R/W
R
Select source of all PG0 UART[m]_SCLK (m = 1..3)*1
R/W
0: MAIN PLL (output of the divider controlled by PWRCTRL_PG0_UARTDIV)
1: USB_DCLK48 (48 MHz clock from USBPLL) clock
b29
RSTN_J2
Active low Reset for UART3_SCLK domain (when USB_DCLK48 is selected).*2
R/W
b28
CLKEN_J2
Clock Enable for UART3_SCLK (when USB_DCLK48 is selected).*2
R/W
0: Disable
1: Enable
b27
RSTN_J1
Active low Reset for UART3_SCLK domain (when MAIN PLL is selected).
R/W
b26
CLKEN_J1
Clock Enable for UART3_SCLK (when MAIN PLL is selected).
R/W
0: Disable
1: Enable
b25
b24
Active low Reset for UART2_SCLK domain (when USB_DCLK48 is selected).*2
RSTN_I2
CLKEN_I2
Clock Enable for UART2_SCLK (when USB_DCLK48 is selected).*
2
R/W
R/W
0: Disable
1: Enable
b23
RSTN_I1
Active low Reset for UART2_SCLK domain (when MAIN PLL is selected).
R/W
b22
CLKEN_I1
Clock Enable for UART2_SCLK (when MAIN PLL is selected).
R/W
0: Disable
1: Enable
b21
RSTN_H2
Active low Reset for UART1_SCLK domain (when USB_DCLK48 is selected).*2
R/W
b20
CLKEN_H2
Clock Enable for UART1_SCLK (when USB_DCLK48 is selected).*2
R/W
0: Disable
1: Enable
b19
RSTN_H1
Active low Reset for UART1_SCLK domain (when MAIN PLL is selected).
R/W
b18
CLKEN_H1
Clock Enable for UART1_SCLK (when MAIN PLL is selected).
R/W
0: Disable
1: Enable
b17
SLVRDY_F
Indicates to the NoC interconnect that the ADC is ready for access
R/W
0: Not Ready
1: Ready
b16
RSTN_F
Active low Reset for ADC_PCLK domain
R/W
b15
CLKEN_F
Clock Enable for ADC_PCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 88 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Table 6.27
Section 6 System Control
PWRCTRL_PG0_0 Register Contents (2/2)
Bit Position
Bit Name
Function
R/W
b14
SLVRDY_E
Indicates to the NoC interconnect that the I2C2 is ready for access
R/W
0: Not Ready
1: Ready
b13
RSTN_E
Active low Reset for I2C2_PCLK domain
R/W
b12
CLKEN_E
Clock Enable for I2C2_PCLK (internal bus)
R/W
0: Disable
1: Enable
b11
SLVRDY_D
Indicates to the NoC interconnect that the I2C1 is ready for access
R/W
0: Not Ready
1: Ready
b10
RSTN_D
Active low Reset for I2C1_PCLK domain
R/W
b9
CLKEN_D
Clock Enable for I2C1_PCLK (internal bus)
R/W
0: Disable
1: Enable
b8
SLVRDY_C
Indicates to the NoC interconnect that the UART3 is ready for access
R/W
0: Not Ready
1: Ready
b7
RSTN_C
Active low Reset for UART3_PCLK domain
R/W
b6
CLKEN_C
Clock Enable for UART3_PCLK (internal bus)
R/W
0: Disable
1: Enable
b5
SLVRDY_B
Indicates to the NoC interconnect that the UART2 is ready for access
R/W
0: Not Ready
1: Ready
b4
RSTN_B
Active low Reset for UART2_PCLK domain
R/W
b3
CLKEN_B
Clock Enable for UART2_PCLK (internal bus)
R/W
0: Disable
1: Enable
b2
SLVRDY_A
Indicates to the NoC interconnect that the UART1 is ready for access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for UART1_PCLK domain
R/W
b0
CLKEN_A
Clock Enable for UART1_PCLK (internal bus)
R/W
0: Disable
1: Enable
Note 1.
Prior to changing the Clock Multiplexer, the Software shall return both clocks to SW reset values and make sure that the
USBPLL is LOCKED.
Note 2.
For the proper operation this functionality, the USBPLL shall be locked.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 89 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.25
PWRSTAT_PG0 — Power Management Status for PG0
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.28
Section 6 System Control
4000 C038h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
SCON_
P
—
—
X
X
X
X
X
X
X
0
X
X
SCON_ SCON_ SCON_ SCON_ SCON_ SCON_
F
E
D
C
B
A
0
0
0
0
0
0
PWRSTAT_PG0 Register Contents
Bit Position
Bit Name
b31 to b9
Reserved
b8
SCON_P
Function
R/W
R
NoC Interconnection Status for PWMTimer
R
0: Disconnected
1: Connected
b7 to b6
Reserved
b5
SCON_F
R
NoC Interconnection Status for ADC
R
0: Disconnected
1: Connected
b4
SCON_E
NoC Interconnection Status for I2C2
R
0: Disconnected
1: Connected
b3
SCON_D
NoC Interconnection Status for I2C1
R
0: Disconnected
1: Connected
b2
SCON_C
NoC Interconnection Status for UART3
R
0: Disconnected
1: Connected
b1
SCON_B
NoC Interconnection Status for UART2
R
0: Disconnected
1: Connected
b0
SCON_A
NoC Interconnection Status for UART1
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 90 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.26
PWRCTRL_PG0_1 — Power Management Control #1 for PG0
Address:
Bit
Value after reset
Bit
Value after reset
4000 C03Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
X
X
X
X
X
X
—
Table 6.29
Section 6 System Control
SLVRD RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN
Y_P
P
_P
M
_M
L
_L
K
_K
X
0
1
1
1
1
1
1
1
1
PWRCTRL_PG0_1 Register Contents
Bit Position
Bit Name
b31 to b15
Reserved
Function
b14
SLVRDY_P
R/W
R
Indicates to the NoC interconnect that the PWMTimer is ready for access
R/W
0: Not Ready
1: Ready
b13
RSTN_P
Active low Reset for PWM_PCLK domain
R/W
b12
CLKEN_P
Clock Enable for PWM_PCLK (internal bus)
R/W
0: Disable
1: Enable
b11
RSTN_M
Active low Reset for ADC_CLK domain
R/W
b10
CLKEN_M
Clock Enable for ADC_CLK
R/W
0: Disable
1: Enable
b9
RSTN_L
Active low Reset for I2C2_SCLK domain
R/W
b8
CLKEN_L
Clock Enable for I2C2_SCLK
R/W
0: Disable
1: Enable
b7
RSTN_K
Active low Reset for I2C1_SCLK domain
R/W
b6
CLKEN_K
Clock Enable for I2C1_SCLK
R/W
0: Disable
1: Enable
b5 to b0
Reserved
R01UH0750EJ0140
Feb 28, 2021
R
Rev.1.40
Page 91 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.27
Section 6 System Control
PWRCTRL_PG1_1 — Power Management Control #1 for PG1
Address:
Bit
Value after reset
Bit
4000 C040h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
X
X
0
1
1
0
1
1
0
1
1
0
1
1
0
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
SLVRD RSTN_ CLKEN SLVRD
CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_
RSTN_I
Y_J
J
_J
Y_I
_I
Y_H
H
_H
Y_G
G
_G
Y_F
F
CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN
_F
Y_E
E
_E
Y_D
D
_D
Y_C
C
_C
Y_B
B
_B
Y_A
A
_A
Value after reset
Table 6.30
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
PWRCTRL_PG1_1 Register Contents (1/2)
Bit Position
Bit Name
b31, b30
Reserved
Function
b29
SLVRDY_J
R/W
R
Indicates to the NoC interconnect that the UART5 is ready for access
R/W
0: Not Ready
1: Ready
b28
RSTN_J
Active low Reset for UART5_PCLK domain
R/W
b27
CLKEN_J
Clock Enable for UART5_PCLK (internal bus)
R/W
0: Disable
1: Enable
b26
SLVRDY_I
Indicates to the NoC interconnect that the UART4 is ready for access
R/W
0: Not Ready
1: Ready
b25
RSTN_I
Active low Reset for UART4_PCLK domain
R/W
b24
CLKEN_I
Clock Enable for UART4_PCLK (internal bus)
R/W
0: Disable
1: Enable
b23
SLVRDY_H
Indicates to the NoC interconnect that the BGPIO2 is ready for access
R/W
0: Not Ready
1: Ready
b22
RSTN_H
Active low Reset for BGPIO2_PCLK domain
R/W
b21
CLKEN_H
Clock Enable for BGPIO2_PCLK (internal bus)
R/W
0: Disable
1: Enable
b20
SLVRDY_G
Indicates to the NoC interconnect that the BGPIO1 is ready for access
R/W
0: Not Ready
1: Ready
b19
RSTN_G
Active low Reset for BGPIO1_PCLK domain
R/W
b18
CLKEN_G
Clock Enable for BGPIO1_PCLK (internal bus)
R/W
0: Disable
1: Enable
b17
SLVRDY_F
Indicates to the NoC interconnect that the SPI6 is ready for access
R/W
0: Not Ready
1: Ready
b16
RSTN_F
Active low Reset for SPI6_PCLK domain
R/W
b15
CLKEN_F
Clock Enable for SPI6_PCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 92 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Table 6.30
Section 6 System Control
PWRCTRL_PG1_1 Register Contents (2/2)
Bit Position
Bit Name
Function
R/W
b14
SLVRDY_E
Indicates to the NoC interconnect that the SPI5 is ready for access
R/W
0: Not Ready
1: Ready
b13
RSTN_E
Active low Reset for SPI5_PCLK domain
R/W
b12
CLKEN_E
Clock Enable for SPI5_PCLK (internal bus)
R/W
0: Disable
1: Enable
b11
SLVRDY_D
Indicates to the interconnect that the SPI4 is ready for access
R/W
0: Not Ready
1: Ready
b10
RSTN_D
Active low Reset for SPI4_PCLK domain
R/W
b9
CLKEN_D
Clock Enable for SPI4_PCLK (internal bus)
R/W
0: Disable
1: Enable
b8
SLVRDY_C
Indicates to the NoC interconnect that the SPI3 is ready for access
R/W
0: Not Ready
1: Ready
b7
RSTN_C
Active low Reset for SPI3_PCLK domain
R/W
b6
CLKEN_C
Clock Enable for SPI3_PCLK (internal bus)
R/W
0: Disable
1: Enable
b5
SLVRDY_B
Indicates to the NoC interconnect that the SPI2 is ready for access
R/W
0: Not Ready
1: Ready
b4
RSTN_B
Active low Reset for SPI2_PCLK domain
R/W
b3
CLKEN_B
Clock Enable for SPI2_PCLK (internal bus)
R/W
0: Disable
1: Enable
b2
SLVRDY_A
Indicates to the NoC interconnect that the SPI1 is ready for access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for SPI1_PCLK domain
R/W
b0
CLKEN_A
Clock Enable for SPI1_PCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 93 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.28
PWRCTRL_PG1_2 — Power Management Control #2 for PG1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.31
Section 6 System Control
4000 C044h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
1
0
1
1
SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN
Y_N
N
_N
Y_M
M
_M
Y_L
L
_L
Y_K
K
_K
0
1
1
0
1
1
0
1
1
0
1
1
PWRCTRL_PG1_2 Register Contents
Bit Position
Bit Name
b31 to b18
Reserved
Function
R/W
b17 to b12
Reserved
Keep initial value
R/W
b11
SLVRDY_N
Indicates to the NoC interconnect that the BGPIO3 is ready for access
R/W
R
0: Not Ready
1: Ready
b10
RSTN_N
Active low Reset for BGPIO3_PCLK domain
R/W
b9
CLKEN_N
Clock Enable for BGPIO3_PCLK (internal bus)
R/W
0: Disable
1: Enable
b8
SLVRDY_M
Indicates to the NoC interconnect that the UART8 is ready for access
R/W
0: Not Ready
1: Ready
b7
RSTN_M
Active low Reset for UART8_PCLK domain
R/W
b6
CLKEN_M
Clock Enable for UART8_PCLK (internal bus)
R/W
0: Disable
1: Enable
b5
SLVRDY_L
Indicates to the NoC interconnect that the UART7 is ready for access
R/W
0: Not Ready
1: Ready
b4
RSTN_L
Active low Reset for UART7_PCLK domain
R/W
b3
CLKEN_L
Clock Enable for UART7_PCLK (internal bus)
R/W
0: Disable
1: Enable
b2
SLVRDY_K
Indicates to the NoC interconnect that the UART6 is ready for access
R/W
0: Not Ready
1: Ready
b1
RSTN_K
Active low Reset for UART6_PCLK domain
R/W
b0
CLKEN_K
Clock Enable for UART6_PCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 94 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.29
PWRCTRL_DMA — Power Management Control for DMAC1 & DMAC2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.32
Section 6 System Control
4000 C04Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
MIREQ SLVRD RSTN_ CLKEN MIREQ SLVRD RSTN_ CLKEN
_B
Y_B
B
_B
_A
Y_A
A
_A
1
0
1
1
1
0
1
1
PWRCTRL_DMA Register Contents
Bit Position
Bit Name
b31 to b8
Reserved
Function
b7
MIREQ_B
R/W
R
AHBM Idle Request to the NoC interconnect for DMAC2
R/W
0: Active
1: Idle
b6
SLVRDY_B
Indicates to the NoC interconnect that the AHBS is ready for DMAC2 access
R/W
0: Not Ready
1: Ready
b5
RSTN_B
Active low Reset for DMA2_HCLK domain
R/W
b4
CLKEN_B
Clock Enable for DMA2_HCLK (internal bus)
R/W
0: Disable
1: Enable
b3
MIREQ_A
AHBM Idle Request to the NoC interconnect for DMAC1
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the AHBS is ready for DMAC1 access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for DMA1_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for DMA1_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 95 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.30
PWRCTRL_NFLASH — Power Management Control for NAND FLASH
Controller
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.33
Section 6 System Control
4000 C050h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
RSTN_ CLKEN MIREQ SLVRD RSTN_ CLKEN
B
_B
_A
Y_A
A
_A
1
1
1
0
1
1
PWRCTRL_NFLASH Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b6
Reserved
b5
RSTN_B
Active low Reset for NAND_ECLK domain
R/W
b4
CLKEN_B
Clock Enable for NAND_ECLK (external interface)
R/W
R
0: Disable
1: Enable
b3
MIREQ_A
AHBM Idle Request to the NoC interconnect for NAND Flash Controller
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the AHBS is ready for NAND Flash Controller
access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for NAND_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for NAND_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 96 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.31
PWRCTRL_QSPI1 — Power Management Control for QSPI1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.34
Section 6 System Control
4000 C054h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
RSTN_ CLKEN MIREQ SLVRD RSTN_ CLKEN
B
_B
_A
Y_A
A
_A
1
1
1
0
1
1
PWRCTRL_QSPI1 Register Contents
Bit Position
Bit Name
b31 to b6
Reserved
Function
R/W
b5
RSTN_B
Active low Reset for QSPI1_REFCLK domain
R/W
b4
CLKEN_B
Clock Enable for QSPI1_REFCLK (external interface)
R/W
R
0: Disable
1: Enable
b3
MIREQ_A
AHBS Idle Request to the NoC interconnect for QuadSPI1
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the APBS is ready for QuadSPI1 access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for QSPI1_HCLK/QSPI1_PCLK domain
R/W
b0
CLKEN_A
Clock Enable for QSPI1_HCLK, QSPI1_PCLK (internal bus)
R/W
0: Disable
1: Enable
NOTE
Reset shall be initiated during QSPI1 module is in process. In case of RZ/N1L, this register initial value is 0x37.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 97 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.32
PWRSTAT_DMA — Power Management Status for DMAC1 & DMAC2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.35
Section 6 System Control
4000 C058h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC SCON_ MISTAT MIRAC SCON_
_B
K_B
B
_A
K_A
A
0
0
0
0
0
0
PWRSTAT_DMA Register Contents
Bit Position
Bit Name
b31 to b6
Reserved
Function
b5
MISTAT_B
R/W
R
AHBM Idle Status of the NoC interconnect for DMAC2
R
0: Active
1: Idle
b4
MIRACK_B
AHBM Idle Request Acknowledge for DMAC2
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b3
SCON_B
AHBS NoC Interconnection Status for DMAC2
R
0: Disconnected
1: Connected
b2
MISTAT_A
AHBM Idle Status of the NoC interconnect for DMAC1
R
0: Active
1: Idle
b1
MIRACK_A
AHBM Idle Request Acknowledge for DMAC1
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
AHBS NoC Interconnection Status for DMAC1
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 98 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.33
PWRSTAT_NFLASH — Power Management Status for NAND FLASH
Controller
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.36
Section 6 System Control
4000 C05Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC SCON_
_A
K_A
A
0
0
0
PWRSTAT_NFLASH Register Contents
Bit Position
Bit Name
Function
b31 to b3
Reserved
b2
MISTAT_A
R/W
R
AHBM Idle Status of the NoC interconnect for NAND Flash Controller
R
0: Active
1: Idle
b1
MIRACK_A
AHBM Idle Request Acknowledge for NAND Flash Controller
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
AHBS NoC Interconnection Status for NAND Flash Controller
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 99 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.34
PWRSTAT_QSPI1 — Power Management Status for QSPI1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.37
Section 6 System Control
4000 C060h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC SCON_
_A
K_A
A
0
0
0
PWRSTAT_QSPI1 Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
MISTAT_A
R/W
R
AHBS Idle Status of the NoC interconnect for QSPI1
R
0: Active
1: Idle
b1
MIRACK_A
AHBS Idle Request Acknowledge for QSPI1
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
APBS NoC Interconnection Status for QSPI1
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 100 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.35
PWRCTRL_DDRC — Power Management Control for DDR Memory
Controller
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.38
Section 6 System Control
4000 C064h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
RSTN_ CLKEN RSTN_ MIREQ CLKEN
B
_B
A
_A
_A
1
1
1
1
1
PWRCTRL_DDRC Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b5
Reserved
b4
RSTN_B
Active low Reset for DDR_DFICLK domain.
R/W
b3
CLKEN_B
Clock Enable for DDR_DFICLK
R/W
R
0: Disable
1: Enable
b2
RSTN_A
Active low Reset for DDR_XCLK domain
R/W
b1
MIREQ_A
Idle Request to the NoC interconnect for DDR memory controller
R/W
0: Active
1: Idle
b0
CLKEN_A
Clock Enable for DDR_XCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 101 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.36
PWRCTRL_EETH — Power Management Control for External Ethernet
Clock
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.39
Section 6 System Control
4000 C068h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
CLKEN CLKEN CLKEN
_C
_B
_A
1
1
1
PWRCTRL_EETH Register Contents
Bit Position
Bit Name
Function
b31 to b3
Reserved
b2
CLKEN_C
R/W
R
Clock Enable for MII_REFCLK (External output)
R/W
0: Disable
1: Enable
b1
CLKEN_B
Clock Enable for RMII_REFCLK (External output)
R/W
0: Disable
1: Enable
b0
CLKEN_A
Clock Enable for RGMII_REFCLK (External input)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 102 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.37
PWRCTRL_MAC1 — Power Management Control for GMAC1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.40
Section 6 System Control
4000 C06Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
MIREQ SLVRD RSTN_ CLKEN
_A
Y_A
A
_A
1
0
0
1
PWRCTRL_MAC1 Register Contents
Bit Position
Bit Name
b31 to b4
Reserved
Function
b3
MIREQ_A
R/W
R
AXIM Idle Request to the NoC interconnect for GMAC1
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the AHBS is ready for GMAC1 access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for GMAC1_XCLK/GMAC1_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for GMAC1_XCLK, GMAC1_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 103 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.38
PWRCTRL_MAC2 — Power Management Control for GMAC2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.41
Section 6 System Control
4000 C070h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
MIREQ SLVRD RSTN_ CLKEN
_A
Y_A
A
_A
1
0
0
1
PWRCTRL_MAC2 Register Contents
Bit Position
Bit Name
b31 to b4
Reserved
Function
b3
MIREQ_A
R/W
R
AXIM Idle Request to the NoC interconnect for GMAC2
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the AHBS is ready for GMAC2 access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for GMAC2_XCLK/GMAC2_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for GMAC2_XCLK, GMAC2_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 104 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.39
PWRSTAT_DDRC — Power Management Status for DDR Memory Controller
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.42
Section 6 System Control
4000 C074h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC
_A
K_A
0
0
PWRSTAT_DDRC Register Contents
Bit Position
Bit Name
b31 to b2
Reserved
Function
b1
MISTAT_A
R/W
R
Idle Status of the NoC interconnect for DDR memory controller
R
0: Active
1: Idle
b0
MIRACK_A
Idle Request Acknowledge for DDR memory controller
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 105 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.40
PWRSTAT_MAC1 — Power Management Status for GMAC1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.43
Section 6 System Control
4000 C078h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC SCON_
_A
K_A
A
0
0
0
PWRSTAT_MAC1 Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
MISTAT_A
R/W
R
AXIM Idle Status of the NoC interconnect for GMAC1
R
0: Active
1: Idle
b1
MIRACK_A
AXIM Idle Request Acknowledge for GMAC1
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
AHBS NoC Interconnection Status for GMAC1
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 106 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.41
PWRSTAT_MAC2 — Power Management Status for GMAC2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.44
Section 6 System Control
4000 C07Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC SCON_
_A
K_A
A
0
0
0
PWRSTAT_MAC2 Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
MISTAT_A
R/W
R
AXIM Idle Status of the NoC interconnect for GMAC2
R
0: Active
1: Idle
b1
MIRACK_A
AXIM Idle Request Acknowledge for GMAC2
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
AHBS NoC Interconnection Status for GMAC2
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 107 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.42
PWRCTRL_ECAT — Power Management Control for ETHERCAT
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.45
Section 6 System Control
4000 C080h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
CLKEN RSTN_ CLKEN MIREQ RSTN_ CLKEN
_C
B
_B
_A
A
_A
1
0
1
1
0
1
PWRCTRL_ECAT Register Contents
Bit Position
Bit Name
b31 to b6
Reserved
Function
b5
CLKEN_C
R/W
R
Clock Enable for ECAT_CLK100
R/W
0: Disable
1: Enable
b4
RSTN_B
Active low Reset for ECAT_CLK25 domain
R/W
b3
CLKEN_B
Clock Enable for ECAT_CLK25
R/W
0: Disable
1: Enable
b2
MIREQ_A
Idle Request to the NoC interconnect for ETHERCAT
R/W
0: Active
1: Idle
b1
RSTN_A
Active low Reset for ECAT_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for ECAT_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 108 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.43
PWRCTRL_SERCOS — Power Management Control for SERCOSIII
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.46
Section 6 System Control
4000 C084h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
CLKEN CLKEN RSTN_ RSTN_ MIREQ CLKEN
_C
_B
B
A
_A
_A
1
1
0
0
1
1
PWRCTRL_SERCOS Register Contents
Bit Position
Bit Name
b31 to b6
Reserved
Function
b5
CLKEN_C
R/W
R
Clock Enable for SERCOS_CLK100
R/W
0: Disable
1: Enable
b4
CLKEN_B
Clock Enable for SERCOS_CLK50
R/W
0: Disable
1: Enable
b3
RSTN_B
Active low Reset for SERCOS_CLK50 domain
R/W
b2
RSTN_A
Active low Reset for SERCOS_HCLK domain
R/W
b1
MIREQ_A
Idle Request to the NoC interconnect for SERCOSIII
R/W
0: Active
1: Idle
b0
CLKEN_A
Clock Enable for SERCOS_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 109 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.44
PWRSTAT_ECAT — Power Management Status for ETHERCAT
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.47
Section 6 System Control
4000 C088h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC
_A
K_A
0
0
PWRSTAT_ECAT Register Contents
Bit Position
Bit Name
b31 to b2
Reserved
Function
b1
MISTAT_A
R/W
R
Idle Status of the NoC interconnect for ETHERCAT
R
0: Active
1: Idle
b0
MIRACK_A
Idle Request Acknowledge for ETHERCAT
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 110 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.45
PWRSTAT_SERCOS — Power Management Status for SERCOSIII
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.48
Section 6 System Control
4000 C08Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC
_A
K_A
0
0
PWRSTAT_SERCOS Register Contents
Bit Position
Bit Name
b31 to b2
Reserved
Function
b1
MISTAT_A
R/W
R
Idle Status of the NoC interconnect for SERCOSIII
R
0: Active
1: Idle
b0
MIRACK_A
Idle Request Acknowledge for SERCOSIII
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 111 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.46
PWRCTRL_HSR — Power Management Control for HSR
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.49
Section 6 System Control
4000 C090h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
RSTN_ CLKEN CLKEN RSTN_ MIREQ CLKEN
C
_C
_B
A
_A
_A
0
1
1
0
1
1
PWRCTRL_HSR Register Contents
Bit Position
Bit Name
b31 to b6
Reserved
Function
R/W
b5
RSTN_C
Active low Reset for HSR_CLK50 domain
R/W
b4
CLKEN_C
Clock Enable for HSR_CLK50
R/W
R
0: Disable
1: Enable
b3
CLKEN_B
Clock Enable for HSR_CLK100
R/W
0: Disable
1: Enable
b2
RSTN_A
Active low Reset for HSR_HCLK domain
R/W
b1
MIREQ_A
Idle Request to the NoC interconnect for HSR
R/W
0: Active
1: Idle
b0
CLKEN_A
Clock Enable for HSR_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 112 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.47
PWRCTRL_QSPI2 — Power Management Control for QSPI2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.50
Section 6 System Control
4000 C090h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
RSTN_ CLKEN MIREQ SLVRD RSTN_ CLKEN
B
_B
_A
Y_A
A
_A
1
1
1
0
1
1
PWRCTRL_QSPI2 Register Contents
Bit Position
Bit Name
b31 to b6
Reserved
Function
R/W
b5
RSTN_B
Active low Reset for QSPI2_REFCLK
R/W
b4
CLKEN_B
Clock Enable for QSPI2_REFCLK (external interface)
R/W
R
0: Disable
1: Enable
b3
MIREQ_A
AHBS Idle Request to the NoC interconnect for QuadSPI2
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the APBS is ready for QuadSPI2 access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for QSPI2_HCLK/QSPI2_PCLK domain
R/W
b0
CLKEN_A
Clock Enable for QSPI2_HCLK, QSPI2_PCLK (internal bus)
R/W
0: Disable
1: Enable
NOTE
Reset shall be initiated during QSPI2 module is in process.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 113 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.48
PWRSTAT_HSR — Power Management Status for HSR
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.51
Section 6 System Control
4000 C098h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC
_A
K_A
0
0
PWRSTAT_HSR Register Contents
Bit Position
Bit Name
b31 to b2
Reserved
Function
b1
MISTAT_A
R/W
R
Idle Status of the NoC interconnect for HSR
R
0: Active
1: Idle
b0
MIRACK_A
Idle Request Acknowledge for HSR
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 114 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.49
PWRSTAT_QSPI2 — Power Management Status for QSPI2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.52
Section 6 System Control
4000 C098h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC SCON_
_A
K_A
A
0
0
0
PWRSTAT_QSPI2 Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
MISTAT_A
R/W
R
AHBS Idle Status of the NoC interconnect for QSPI2
R
0: Active
1: Idle
b1
MIRACK_A
AHBS Idle Request Acknowledge for QSPI2
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
APBS NoC Interconnection Status for QSPI2
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 115 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.50
PWRSTAT_SWITCH — Power Management Status for A5PSW
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.53
Section 6 System Control
4000 C09Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCON_
A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
PWRSTAT_SWITCH Register Contents
Bit Position
Bit Name
b31 to b1
Reserved
b0
SCON_A
Function
R/W
R
NoC Interconnection Status for A5PSW
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 116 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.51
RSTSTAT — Reset Status Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.54
Section 6 System Control
4000 C0A8h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PORRS
T_ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
CM3SY CM3LO WDM3
SWRST
SRESE CKUPR RST_S WDA7RST_ST
_ST
T_ST ST_ST
T
0
0
0
0
0
—
0
X
RSTSTAT Register Contents
Bit Position
Bit Name
Function
R/W
b31
PORRST_ST
Status bit whether or not external (power-on) reset has been performed
R/W
0: External (power-on) reset has not been performed.
1: External (power-on) reset is performed.
b30 to b7
Reserved
R
b6
SWRST_ST
Status bit of Software reset
R/W
0: Software triggered reset has not been performed.
1: Software triggered reset is performed.
b5
CM3SYSRESET_ST
Status bit of Cortex-M3 initiated system reset
R/W
0: Cortex-M3 triggered system reset has not been performed.
1: Cortex-M3 triggered system reset is performed.
b4
CM3LOCKUPRST_S
T
Status bit of Cortex-M3 Core Lockup initiated system reset
R/W
WDM3RST_ST
Status bit of Cortex-M3 watchdog initiated system reset; If a software failure prevents R/W
the Watchdog Counter Register from being refreshed, the Watchdog Counter Register
reaches zero, the Watchdog reset status flag is set and the associated reset request is
asserted.
0: Cortex-M3 Lockup triggered system reset has not been performed.
1: Cortex-M3 Lockup triggered system reset is performed.
b3
0: Device has not performed any watchdog triggered system reset.
1: Device has performed a watchdog triggered system reset.
b2, b1
WDA7RST_ST
Status bit of Cortex-A7 watchdog initiated system reset
R/W
0: Watchdog triggered system reset has not been performed.
1: Watchdog triggered system reset is performed.
Bit2 (RZ/N1D) Cortex-A7 processor1 watchdog reset (RZ/N1S, RZ/N1L) Reserved
Bit1 (RZ/N1D, RZ/N1S) Cortex-A7 processor0 watchdog reset (RZ/N1L) Reserved
b0
Reserved
R
NOTE
These status bits are cleared by write 1.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 117 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.52
Section 6 System Control
USBSTAT — Status information for USBPLL
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.55
4000 C0C0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PLL_LO
CK
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
USBSTAT Register Contents
Bit Position
Bit Name
b31 to b1
Reserved
Function
b0
PLL_LOCK
R/W
R
Status of USBPLL
R
0: UNLOCKED
1: LOCKED
NOTE
Software shall make sure that the USBPLL is locked prior to initiating any access to peripherals running on USBPLL
clock. Otherwise the system may hang-up.
CAUTION
USBPLL is unlocked by specific register access (e.g. PLL_RST) to USB module or resetting the USB module.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 118 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.53
PWRCTRL_SDIO2 — Power Management Control for SDIO2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.56
Section 6 System Control
4000 C0C8h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
CLKEN MIREQ SLVRD RSTN_ CLKEN
_B
_A
Y_A
A
_A
1
1
0
1
1
PWRCTRL_SDIO2 Register Contents
Bit Position
Bit Name
b31 to b5
Reserved
Function
b4
CLKEN_B
R/W
R
Clock Enable for SDIO2_ECLK (external interface)
R/W
0: Disable
1: Enable
b3
MIREQ_A
AHBM Idle Request to the NoC interconnect for SDIO2
R/W
0: Active
1: Idle
b2
SLVRDY_A
Indicates to the NoC interconnect that the AHBS is ready for SDIO2 access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for SDIO2_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for SDIO2_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 119 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.54
PWRSTAT_SDIO2 — Power Management Status for SDIO2
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.57
Section 6 System Control
4000 C0CCh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC SCON_
_A
K_A
A
0
0
0
PWRSTAT_SDIO2 Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
MISTAT_A
R/W
R
AHBM Idle Status of the NoC interconnect for SDIO2
R
0: Active
1: Idle
b1
MIRACK_A
AHBM Idle Request Acknowledge for SDIO2
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b0
SCON_A
AHBS NoC Interconnection Status for SDIO2
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 120 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.55
PWRCTRL_PG2_25MHZ — Power Management Control for PG2 25MHz
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.58
Section 6 System Control
4000 C0E8h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
0
1
1
0
1
1
0
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
1
0
1
1
0
1
1
SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN
Y_S
S
_S
Y_R
R
_R
Y_Q
Q
_Q
0
1
1
0
1
1
0
1
1
PWRCTRL_PG2_25MHZ Register Contents
Bit Position
Bit Name
b31 to b24
Reserved
Function
R/W
b23 to b9
Reserved
Keep initial value
R/W
b8
SLVRDY_S
Indicates to the NoC interconnect that the TIMER2 is ready for access
R/W
R
0: Not Ready
1: Ready
b7
RSTN_S
Active low Reset for TIMER2_PCLK domain
R/W
b6
CLKEN_S
Clock Enable for TIMER2_PCLK (internal bus)
R/W
0: Disable
1: Enable
b5
SLVRDY_R
Indicates to the NoC interconnect that the TIMER1 is ready for access
R/W
0: Not Ready
1: Ready
b4
RSTN_R
Active low Reset for TIMER1_PCLK domain
R/W
b3
CLKEN_R
Clock Enable for TIMER1_PCLK (internal bus)
R/W
0: Disable
1: Enable
b2
SLVRDY_Q
Indicates to the NoC interconnect that the ConfigSys2 is ready for access
R/W
0: Not Ready
1: Ready
b1
RSTN_Q
Active low Reset for PG2_PCLK domain
R/W
b0
CLKEN_Q
Clock Enable for PG2_PCLK (internal bus of ConfigSys2)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 121 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.56
Section 6 System Control
PWRCTRL_PG1_PR2 — Power Management Control for PG1 Program2
Address:
Bit
Value after reset
Bit
4000 C0ECh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
UARTC
LKSEL
—
—
—
—
X
X
X
X
X
X
X
0
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
RSTN_ CLKEN RSTN_ CLKEN
AK2
_AK2
AK1
_AK1
RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN
AJ2
_AJ2
AJ1
_AJ1
AI2
_AI2
AI1
_AI1
AH2
_AH2
AH1
_AH1
AG2
_AG2
AG1
_AG1
Value after reset
Table 6.59
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PWRCTRL_PG1_PR2 Register Contents (1/2)
Bit Position
Bit Name
b31 to b25
Reserved
Function
b24
UARTCLKSEL
R/W
R
Select source of all PG1 UART[m]_SCLK (m = 4..8)*1
R/W
0: MAIN PLL (output of the divider controlled by PWRCTRL_PG1_PR2DIV)
1: USB_DCLK48 (48 MHz clock from USBPLL) clock.
b23 to b20
Reserved
Keep initial value.
R/W
b19
RSTN_AK2
Active low Reset for UART8_SCLK domain (when USB_DCLK48 is selected).*2
R/W
b18
CLKEN_AK2
Clock Enable for UART8_SCLK (when USB_DCLK48 is selected).*2
R/W
0: Disable
1: Enable
b17
RSTN_AK1
Active low Reset for UART8_SCLK domain (when MAIN PLL is selected).
R/W
b16
CLKEN_AK1
Clock Enable for UART8_SCLK (when MAIN PLL is selected).
R/W
0: Disable
1: Enable
b15
RSTN_AJ2
Active low Reset for UART7_SCLK domain (when USB_DCLK48 is selected).*2
R/W
b14
CLKEN_AJ2
Clock Enable for UART7_SCLK (when USB_DCLK48 is selected).*2
R/W
0: Disable
1: Enable
b13
RSTN_AJ1
Active low Reset for UART7_SCLK domain (when MAIN PLL is selected).
R/W
b12
CLKEN_AJ1
Clock Enable for UART7_SCLK (when MAIN PLL is selected).
R/W
0: Disable
1: Enable
b11
b10
RSTN_AI2
CLKEN_AI2
Active low Reset for UART6_SCLK domain (when USB_DCLK48 is selected).*2
Clock Enable for UART6_SCLK (when USB_DCLK48 is selected).*
2
R/W
R/W
0: Disable
1: Enable
b9
RSTN_AI1
Active low Reset for UART6_SCLK domain (when MAIN PLL is selected).
R/W
b8
CLKEN_AI1
Clock Enable for UART6_SCLK (when MAIN PLL is selected).
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 122 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Table 6.59
Section 6 System Control
PWRCTRL_PG1_PR2 Register Contents (2/2)
Bit Position
Bit Name
Function
R/W
b7
RSTN_AH2
Active low Reset for UART5_SCLK domain (when USB_DCLK48 is selected).*2
R/W
b6
CLKEN_AH2
Clock Enable for UART5_SCLK (when USB_DCLK48 is selected).*2
R/W
0: Disable
1: Enable
b5
RSTN_AH1
Active low Reset for UART5_SCLK domain (when MAIN PLL is selected).
R/W
b4
CLKEN_AH1
Clock Enable for UART5_SCLK (when MAIN PLL is selected).
R/W
0: Disable
1: Enable
b3
RSTN_AG2
Active low Reset for UART4_SCLK domain (when USB_DCLK48 is selected).*2
R/W
b2
CLKEN_AG2
Clock Enable for UART4_SCLK (when USB_DCLK48 is selected).*2
R/W
0: Disable
1: Enable
b1
RSTN_AG1
Active low Reset for UART4_SCLK domain (when MAIN PLL is selected).
R/W
b0
CLKEN_AG1
Clock Enable for UART4_SCLK (when MAIN PLL is selected).
R/W
0: Disable
1: Enable
Note 1.
Prior to changing the Clock Multiplexer, the Software shall return both clocks to SW reset values and make sure that the
USBPLL is LOCKED.
Note 2.
For the proper operation of this function, the USBPLL shall be locked.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.57
Section 6 System Control
PWRCTRL_PG3_48MHZ — Power Management Control for PG3 48MHz
CAUTION
The USBPLL shall be locked prior to making any access to Peripheral Group 3. Otherwise the system may hang-up.
Address:
Bit
Value after reset
Bit
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
1
1
0
1
1
—
Value after reset
Table 6.60
Bit Position
4000 C0F0h
MIREQ RSTN_ CLKEN
_UF
UF
_UF
X
1
1
1
SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN
Y_AA
AA
_AA
Y_Z
Z
_Z
0
1
1
0
1
1
PWRCTRL_PG3_48MHZ Register Contents
Bit Name
Function
b31 to b15
Reserved
b14
MIREQ_UF
R/W
R
Idle Request to the NoC interconnect for Peripheral Group 3
R/W
0: Active
1: Idle
b13
RSTN_UF
Active low Reset for Peripheral Group 3
R/W
b12
CLKEN_UF
Clock Enable for Peripheral Group 3
R/W
0: Disable
1: Enable
b11 to b9
Reserved
Keep initial value.
R/W
b8
SLVRDY_AA
Indicates to the NoC interconnect that the CAN2 is ready for access
R/W
0: Not Ready
1: Ready
b7
RSTN_AA
Active low Reset for CAN2_HCLK domain
R/W
b6
CLKEN_AA
Clock Enable for CAN2_HCLK (internal bus)
R/W
0: Disable
1: Enable
b5
SLVRDY_Z
Indicates to the NoC interconnect that the CAN1 is ready for access
R/W
0: Not Ready
1: Ready
b4
RSTN_Z
Active low Reset for CAN1_HCLK domain
R/W
b3
CLKEN_Z
Clock Enable for CAN1_HCLK (internal bus)
R/W
0: Disable
1: Enable
b2 to b0
Reserved
R01UH0750EJ0140
Feb 28, 2021
Keep initial value
Rev.1.40
R/W
Page 124 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.58
PWRCTRL_PG4 — Power Management Control for PG4
Address:
Bit
Value after reset
Bit
Value after reset
4000 C0F4h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
0
1
1
0
1
1
—
Table 6.61
Section 6 System Control
MIREQ RSTN_ CLKEN
_UI
UI
_UI
X
1
1
1
SLVRD RSTN_ CLKEN SLVRD RSTN_ CLKEN
Y_AD
AD
_AD
Y_AC
AC
_AC
0
1
1
0
1
1
PWRCTRL_PG4 Register Contents
Bit Position
Bit Name
b31 to b15
Reserved
Function
b14
MIREQ_UI
R/W
R
Idle Request to the NoC interconnect for Peripheral Group 4
R/W
0: Active
1: Idle
b13
RSTN_UI
Active low Reset for Peripheral Group 4
R/W
b12
CLKEN_UI
Clock Enable for Peripheral Group 4
R/W
0: Disable
1: Enable
b11 to b6
Reserved
Keep initial value
R/W
b5
SLVRDY_AD
Indicates to the NoC interconnect that the Semaphore is ready for access
R/W
0: Not Ready
1: Ready
b4
RSTN_AD
Active low Reset for SEMAP_HCLK domain
R/W
b3
CLKEN_AD
Clock Enable for SEMAP_HCLK (internal bus)
R/W
0: Disable
1: Enable
b2
SLVRDY_AC
Indicates to the NoC interconnect that the LCDC is ready for access
R/W
0: Not Ready
1: Ready
b1
RSTN_AC
Active low Reset for LCD_HCLK domain
R/W
b0
CLKEN_AC
Clock Enable for LCD_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 125 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.59
PWRCTRL_PG1_PR3 — Power Management Control for PG1 Program3
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.62
Section 6 System Control
4000 C0FCh
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN RSTN_ CLKEN
AP
_AP
AO
_AO
AN
_AN
AM
_AM
1
1
1
1
1
1
1
1
PWRCTRL_PG1_PR3 Register Contents
Bit Position
Bit Name
b31 to b8
Reserved
Function
R/W
b7
RSTN_AP
Active low Reset for SPI4_SCLK domain
R/W
b6
CLKEN_AP
Clock Enable for SPI4_SCLK (external interface)
R/W
R
0: Disable
1: Enable
b5
RSTN_AO
Active low Reset for SPI3_SCLK domain
R/W
b4
CLKEN_AO
Clock Enable for SPI3_SCLK (external interface)
R/W
0: Disable
1: Enable
b3
RSTN_AN
Active low Reset for SPI2_SCLK domain
R/W
b2
CLKEN_AN
Clock Enable for SPI2_SCLK (external interface)
R/W
0: Disable
1: Enable
b1
RSTN_AM
Active low Reset for SPI1_SCLK domain
R/W
b0
CLKEN_AM
Clock Enable for SPI1_SCLK (external interface)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 126 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.60
PWRCTRL_PG1_PR4 — Power Management Control for PG1 Program4
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.63
Section 6 System Control
4000 C104h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
1
1
1
1
RSTN_ CLKEN RSTN_ CLKEN
AR
_AR
AQ
_AQ
1
1
1
1
PWRCTRL_PG1_PR4 Register Contents
Bit Position
Bit Name
b31 to b8
Reserved
Function
R/W
b7 to b4
Reserved
Keep initial value
R/W
b3
RSTN_AR
Active low Reset for SPI6_SCLK domain
R/W
b2
CLKEN_AR
Clock Enable for SPI6_SCLK (external interface)
R/W
R
0: Disable
1: Enable
b1
RSTN_AQ
Active low Reset for SPI5_SCLK domain
R/W
b0
CLKEN_AQ
Clock Enable for SPI5_SCLK (external interface)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 127 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.61
PWRCTRL_PG4_PR1 — Power Management Control for PG4 Program1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.64
Section 6 System Control
4000 C10Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
1
1
1
1
1
1
RSTN_ CLKEN
AU
_AU
1
1
PWRCTRL_PG4_PR1 Register Contents
Bit Position
Bit Name
b31 to b8
Reserved
Function
R/W
b7 to b2
Reserved
Keep initial value
R/W
b1
RSTN_AU
Active low Reset for LCD_ECLK domain
R/W
b0
CLKEN_AU
Clock Enable for LCD_ECLK (external interface)
R/W
R
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 128 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.62
Section 6 System Control
RSTEN — Reset Enable Register
This Register can enable or disable each system reset source. Enabling an active system reset request (in RSTCTRL)
will result in immediate reset of the system.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.65
4000 C120h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
CM3SY CM3LO WDM3
SWRST
MRESE
SRESE CKUPR RST_E WDA7RST_EN
_EN
T_EN
T_EN ST_EN
N
0
0
0
0
0
0
0
RSTEN Register Contents
Bit Position
Bit Name
Function
b31 to b7
Reserved
b6
SWRST_EN
R/W
R
Enable bit of Software triggered system reset request (SWRST_REQ bit of RSTCTRL
register)
R/W
0: Disable
1: Enable
b5
CM3SYSRESET_EN
Enable Cortex-M3 SYSRESETREQ initiated reset
R/W
0: Disable
1: Enable
b4
CM3LOCKUPRST_E
N
Enable bit of Cortex-M3 Core Lockup reset
R/W
0: Disable
1: Enable
b3
WDM3RST_EN
Enable bit of Cortex-M3 Core watchdog reset
R/W
0: Disable
1: Enable
b2, b1
WDA7RST_EN
Enable bit of Cortex-A7 watchdog reset
R/W
0: Disable
1: Enable
Bit2 (RZ/N1D) Cortex-A7 processor1 watchdog reset request (RZ/N1S, RZ/N1L)
Reserved.
Bit1 (RZ/N1D, RZ/N1S) Cortex-A7 processor0 watchdog reset request (RZ/N1L)
Reserved.
b0
MRESET_EN
Enable bit of system reset
R/W
Bit6..1 are activated if this bit is set to 1.
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.63
PWRCTRL_SWITCH — Power Management Control for A5PSW
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.66
Section 6 System Control
4000 C130h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
RSTN_ CLKEN SLVRD CLKEN
B
_B
Y_A
_A
0
1
0
1
PWRCTRL_SWITCH Register Contents
Bit Position
Bit Name
b31 to b4
Reserved
Function
R/W
b3
RSTN_B
Active low Reset for A5PSW_SXCLK domain
R/W
b2
CLKEN_B
Clock Enable for A5PSW_SXCLK (core clock)
R/W
R
0: Disable
1: Enable
b1
SLVRDY_A
Indicates to the NoC interconnect that the A5PSW is ready for access
R/W
0: Not Ready
1: Ready
b0
CLKEN_A
Clock Enable for A5PSW_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 130 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.64
Section 6 System Control
PWRCTRL_RTC — Power Management Control for RTC
Use below order to enable RTC for software access:
1. Release RST_RTC
2. Enable RTC_PCLK
3. Release RSTN_FW_RTC
4. Release IDLE_REQ
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.67
4000 C140h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
RSTN_
IDLE_R RST_R CLKEN
FW_RT
EQ
TC
_RTC
C
0
1
0
0
PWRCTRL_RTC Register Contents
Bit Position
Bit Name
b31 to b4
Reserved
Function
b3
RSTN_FW_RTC
R/W
R
Software reset to the NoC interconnect for RTC
R/W
0: Reset
1: Reset release
b2
IDLE_REQ
Idle Request to the NoC interconnect for RTC
R/W
1: IDLE-status request
0: Active status
b1
RST_RTC
Active high Reset for RTC_PCLK domain
R/W
1: Reset
0: Reset release
b0
CLKEN_RTC
Clock Enable for RTC_PCLK (internal bus)
R/W
1: CLK for RTC APB and NoC interconnect on
0: CLK off
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6.3.65
PWRSTAT_RTC — Power Management Status for RTC
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.68
Section 6 System Control
4000 C144h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
PWR_G RTC_ID RTC_IA
OOD
LE
CK
0
0
0
PWRSTAT_RTC Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
R/W
b2
PWR_GOOD
Indicate status of RTC_PWRGOOD signal
R
b1
RTC_IDLE
Idle Status of the NoC interconnect for RTC
R
R
0: Active
1: Idle
b0
RTC_IACK
Idle Request Acknowledge for RTC
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
NOTE
The software shall not apply clock gating or software reset unless idle (RTC_IDLE = 1).
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.66
PWRCTRL_ROM — Power Management Control for ROM
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.69
Section 6 System Control
4000 C154h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
SLVRD RSTN_ CLKEN
Y_A
A
_A
1
1
1
PWRCTRL_ROM Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
SLVRDY_A
R/W
R
Indicates to the NoC interconnect that the ROM is ready for access
R/W
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for ROM_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for ROM_HCLK (internal bus)
R/W
0: Disable
1: Enable
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Rev.1.40
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6.3.67
PWRSTAT_PG1 — Power Management Status for PG1
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.70
Section 6 System Control
4000 C158h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
X
X
SCON_ SCON_ SCON_ SCON_ SCON_ SCON_ SCON_ SCON_ SCON_ SCON_ SCON_ SCON_ SCON_ SCON_
N
M
L
K
J
I
H
G
F
E
D
C
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWRSTAT_PG1 Register Contents (1/2)
Bit Position
Bit Name
b31 to b14
Reserved
b13
SCON_N
Function
R/W
R
NoC Interconnection Status for BGPIO3
R
0: Disconnected
1: Connected
b12
SCON_M
NoC Interconnection Status for UART8
R
0: Disconnected
1: Connected
b11
SCON_L
NoC Interconnection Status for UART7
R
0: Disconnected
1: Connected
b10
SCON_K
NoC Interconnection Status for UART6
R
0: Disconnected
1: Connected
b9
SCON_J
NoC Interconnection Status for UART5
R
0: Disconnected
1: Connected
b8
SCON_I
NoC Interconnection Status for UART4
R
0: Disconnected
1: Connected
b7
SCON_H
NoC Interconnection Status for BGPIO2
R
0: Disconnected
1: Connected
b6
SCON_G
NoC Interconnection Status for BGPIO1
R
0: Disconnected
1: Connected
b5
SCON_F
NoC Interconnection Status for SPI6
R
0: Disconnected
1: Connected
b4
SCON_E
NoC Interconnection Status for SPI5
R
0: Disconnected
1: Connected
b3
SCON_D
NoC Interconnection Status for SPI4
R
0: Disconnected
1: Connected
b2
SCON_C
NoC Interconnection Status for SPI3
R
0: Disconnected
1: Connected
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Table 6.70
Section 6 System Control
PWRSTAT_PG1 Register Contents (2/2)
Bit Position
Bit Name
Function
R/W
b1
SCON_B
NoC Interconnection Status for SPI2
R
0: Disconnected
1: Connected
b0
SCON_A
NoC Interconnection Status for SPI1
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
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Rev.1.40
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6.3.68
PWRSTAT_PG2_25MHZ — Power Management Status for PG2 25MHz
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.71
Section 6 System Control
4000 C15Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
SCON_ SCON_ SCON_
S
R
Q
0
0
0
PWRSTAT_PG2_25MHZ Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
b2
SCON_S
Function
R/W
R
NoC Interconnection Status for TIMER2
R
0: Disconnected
1: Connected
b1
SCON_R
NoC Interconnection Status for TIMER1
R
0: Disconnected
1: Connected
b0
SCON_Q
NoC Interconnection Status for ConfigSys2
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.69
PWRSTAT_PG3_48MHZ — Power Management Status for PG3 48MHz
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.72
Section 6 System Control
4000 C160h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC
_UF
K_UF
0
0
—
X
SCON_ SCON_
AA
Z
0
—
0
X
PWRSTAT_PG3_48MHZ Register Contents
Bit Position
Bit Name
b31 to b6
Reserved
Function
b5
MISTAT_UF
R/W
R
Idle Status of the NoC interconnect for Peripheral Group 3
R
0: Active
1: Idle
b4
MIRACK_UF
Idle Request Acknowledge for Peripheral Group 3
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b3
Reserved
R
b2
SCON_AA
NoC Interconnection Status for CAN2
R
0: Disconnected
1: Connected
b1
SCON_Z
NoC Interconnection Status for CAN1
R
0: Disconnected
1: Connected
b0
Reserved
R
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.70
PWRSTAT_PG4 — Power Management Status for PG4
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.73
Section 6 System Control
4000 C164h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC
_UI
K_UI
0
0
SCON_ SCON_
AD
AC
0
0
PWRSTAT_PG4 Register Contents
Bit Position
Bit Name
b31 to b6
Reserved
Function
b5
MISTAT_UI
R/W
R
Idle Status of the NoC interconnect for Peripheral Group 4
R
0: Active
1: Idle
b4
MIRACK_UI
Idle Request Acknowledge for Peripheral Group 4
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
b3, b2
Reserved
R
b1
SCON_AD
NoC Interconnection Status for Semaphore
R
0: Disconnected
1: Connected
b0
SCON_AC
NoC Interconnection Status for LCDC
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.71
PWRSTAT_ROM — Power Management Status for ROM
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.74
Section 6 System Control
4000 C170h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCON_
A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
PWRSTAT_ROM Register Contents
Bit Position
Bit Name
b31 to b1
Reserved
b0
SCON_A
Function
R/W
R
NoC Interconnection Status for ROM
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.72
PWRCTRL_CM3 — Power Management Control for CM3
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.75
Section 6 System Control
4000 C174h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
MIREQ RSTN_ CLKEN
_A
A
_A
1
0
1
PWRCTRL_CM3 Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
MIREQ_A
R/W
R
Idle Request to the NoC interconnect for Cortex-M3
R/W
0: Active
1: Idle
Note that the clock and reset domain of CM3 belongs to RIN BUS sub system.
Therefore, clock and reset in PWRCTRL_RINCTRL should be controlled accordingly.
b1
RSTN_A
Active low Reset for CM3_HCLK/CM3_FCLK domain
R/W
b0
CLKEN_A
Clock Enable for CM3_HCLK, CM3_FCLK
R/W
0: Disable
1: Enable
NOTE
Software shall request reset of Cortex-M3 only if there are no pending transactions on the NoC interconnect. e.g. The
Cortex-M3 is in WFE state. Interruption of Cortex-M3 bus operation results in hang-up of the NoC interconnect. In case
of RZ/N1L, this register initial value is 0x3.
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Rev.1.40
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6.3.73
PWRSTAT_CM3 — Power Management Status for CM3
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.76
Section 6 System Control
4000 C178h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MISTAT MIRAC
_A
K_A
0
0
PWRSTAT_CM3 Register Contents
Bit Position
Bit Name
b31 to b2
Reserved
Function
b1
MISTAT_A
R/W
R
Idle Status of the NoC interconnect for Cortex-M3
R
0: Active
1: Idle
b0
MIRACK_A
Idle Request Acknowledge for Cortex-M3
R
0: Not acknowledged Idle Request
1: Acknowledged Idle Request
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
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Rev.1.40
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6.3.74
Section 6 System Control
PWRSTAT_RINCTRL — Power Management Status for R-IN Engine
Accessory Register
Gating of the RINBUS_HCLK may result in non-deterministic behavior of the 2MB SRAM clocked by
RINBUS_HCLK in R-IN Engine Accessory Register block.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.77
4000 C17Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCON_
A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
PWRSTAT_RINCTRL Register Contents
Bit Position
Bit Name
b31 to b1
Reserved
b0
SCON_A
Function
R/W
R
NoC Interconnection Status for R-IN Engine Accessory Register
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.75
PWRSTAT_SWITCHCTRL — Power Management Status for Ethernet
Accessory Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.78
Section 6 System Control
4000 C180h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCON_
A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
PWRSTAT_SWITCHCTRL Register Contents
Bit Position
Bit Name
b31 to b1
Reserved
b0
SCON_A
Function
R/W
NoC Interconnection Status for Ethernet Accessory Register
R
R
0: Disconnected
1: Connected
NOTE
The software shall not apply clock gating or software reset to any module unless all corresponding NoC interconnect of
the module are disconnected (SCON = 0) and in idle (MISTAT = 1).
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Rev.1.40
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.76
Section 6 System Control
PWRCTRL_RINCTRL — Power Management Control for R-IN Engine
Accessory Register
Gating of the RINBUS_HCLK may result in non-deterministic behavior of the 2MB SRAM clocked by
RINBUS_HCLK in R-IN Engine Accessory Register block.
During Cortex-M3 operation, gating the RINBUS_HCLK results in hang-up of the Cortex-M3 accesses since RIN BUS
sub system used in Cortex-M3 accesses is stopped.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.79
4000 C184h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
SLVRD RSTN_ CLKEN
Y_A
A
_A
0
1
1
PWRCTRL_RINCTRL Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
SLVRDY_A
R/W
R
Indicates to the NoC interconnect that the R-IN Engine Accessory Register is ready for R/W
access
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for RINBUS_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for RINBUS_HCLK (internal bus)
R/W
0: Disable
1: Enable
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 144 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.77
PWRCTRL_SWITCHCTRL — Power Management Control for Ethernet
Accessory Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.80
Section 6 System Control
4000 C188h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
RSTN_ RSTN_ SLVRD RSTN_ CLKEN
ETH CLK25 Y_A
A
_A
0
0
0
1
1
PWRCTRL_SWITCHCTRL Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b5
Reserved
b4
RSTN_ETH
Active low Reset for RGMII/RMII Converter (50 MHz).
R/W
b3
RSTN_CLK25
Active low Reset for Timestamp signal selection logic
R/W
b2
SLVRDY_A
Indicates to the NoC interconnect that the Ethernet Accessory Register is ready for
access
R/W
R
0: Not Ready
1: Ready
b1
RSTN_A
Active low Reset for RINEG_HCLK domain
R/W
b0
CLKEN_A
Clock Enable for RINEG_HCLK (internal bus—Ethernet Accessory Register)
R/W
0: Disable
1: Enable
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Feb 28, 2021
Rev.1.40
Page 145 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.78
PWRCTRL_HWRTOS — Power Management Control for HW-RTOS
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.81
Section 6 System Control
4000 C18Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
CLKEN RSTN_ CLKEN
_B
A
_A
1
1
1
PWRCTRL_HWRTOS Register Contents
Bit Position
Bit Name
b31 to b3
Reserved
Function
b2
CLKEN_B
R/W
R
Clock Enable for HWRTOS_MDCCLK
R/W
0: Disable
1: Enable
b1
RSTN_A
Active low Reset for HWRTOS_CLK domain
R/W
b0
CLKEN_A
Clock Enable for HWRTOS_CLK
R/W
0: Disable
1: Enable
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Feb 28, 2021
Rev.1.40
Page 146 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.79
Section 6 System Control
RSTCTRL — Reset Control Register
Software can use this register to initiate system reset or identify if any of the current hardware system reset sources are
requesting a system reset.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.82
4000 C198h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
CM3SY CM3LOC WDM3
WDA7RST_RE
SWRST
SRESE KUPRST RST_R
Q
_REQ
T_REQ _REQ
EQ
0
0
0
0
0
—
0
X
RSTCTRL Register Contents
Bit Position
Bit Name
Function
b31 to b7
Reserved
b6
SWRST_REQ
R/W
R
Software triggered system reset request
R/W
0: No system reset request
1: Software requests a system reset to be performed.
b5
CM3SYSRESET_RE
Q
R/W
Cortex-M3 SYSRESETREQ initiated system reset
0: No system reset request
1: Pending system reset request*1
b4
CM3LOCKUPRST_R
EQ
Cortex-M3 Core Lockup reset request
R/W
0: No system reset request
1: Pending system reset request*1
b3
WDM3RST_REQ
R/W
Cortex-M3 Core watchdog reset request
0: No system reset request
1: Pending system reset request*1
b2, b1
WDA7RST_REQ
Cortex-A7 watchdog reset request
R/W
0: No system reset request
1: Pending system reset request*1
Bit2 (RZ/N1D) Cortex-A7 processor1 watchdog reset request (RZ/N1S, RZ/N1L)
Reserved.
Bit1 (RZ/N1D, RZ/N1S) Cortex-A7 processor0 watchdog reset request (RZ/N1L)
Reserved.
b0
Note 1.
Reserved
R
Cleared by write 1
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Feb 28, 2021
Rev.1.40
Page 147 of 263
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6.3.80
Section 6 System Control
CFG_USB — USB Mode Configuration Register
Changing the USB Host/Function controller configuration may affect the USBPLL operation. The interruption of
USBPLL operation may lead to a system hang-up. The software shall make sure that prior to applying any change to
USB configuration, disconnect all module operated by USBPLL clock from the NoC interconnect in order to avoid bus
hang-up.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.83
4000 C000h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
FRCLK H2MOD
DIRPD
48MOD
E
1
0
1
CFG_USB Register Contents
Bit Position
Bit Name
Function
b31 to b3
Reserved
b2
FRCLK48MOD
R/W
R
0: USBPLL stops during USB suspend
R/W
1: USBPLL operates regardless of USB state i.e. It can be used to clock other
modules
b1
H2MODE
USB interface Port setting signal
R/W
0: Port1 Function, Port2 Host
1: Port1 Host, Port2 Host
In the USB reset sequence, set this bit before canceling the host reset.
b0
DIRPD
Direct power down control
R/W
0: USBPLL Powered
1: USBPLL Powered down
This bit is direct power down signal to USB module. Please refer to USB 2.0 HS
Host/Function Controller section in UM of System Control and Peripheral for more
details about Direct power down feature.
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Feb 28, 2021
Rev.1.40
Page 148 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.81
Section 6 System Control
OPMODE — System and Boot Configuration Register
Boot mode configurations are read from external configuration pins after Power on Reset. System reset has no effect on
these values.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.84
4000 C004h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
LCD1P
U
—
—
DDRM
OD
X
X
X
X
X
X
X
X
X
X*1
X
X
X*1
CM3BO
CA7BOOTSRC
OTSEL
X*1
X*1
X*1
OPMODE Register Contents
Bit Position
Bit Name
b31 to b7
Reserved
b6
LCD1PU
Function
R/W
LCD interface (assignment to GPIO pins) default pull configuration (RZ/N1D and
RZ/N1S)
R
R
0: Pull-down on GPIO[73:62] and GPIO[145:127]
1: Pull-up on GPIO[73:62] and GPIO[145:127]
b5
Reserved
R
b4
CM3BOOTSEL
Cortex-M3 Boot mode configuration
R
0: CA7 boot from CA7BOOTSRC
1: CM3 boot from QSPI (RZ/N1L)
b3, b2
CA7BOOTSRC
Boot mode configuration
R
2’b00: Boot on QuadSPI1
2’b01: Boot on NAND Flash
2’b10: Boot on USB function
2’b11: Reserved
b1
Reserved
R
b0
DDRMOD
DDR Controller Configuration (RZ/N1D)
R
0: DDR3
1: DDR2
Note 1.
The value is reflected after power-on reset.
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Rev.1.40
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6.3.82
Section 6 System Control
CFG_SDIO[m] — SDIO[m] Configuration Register (m = 1 or 2)
Address:
CFG_SDIO1: 4000 C008h
CFG_SDIO2: 4000 C0C4h
Bit
Value after reset
Bit
Value after reset
Table 6.85
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
X
X
X
X
X
X
0
0
1
SLOTTYPE
0
0
BASECLKFREQ
0
0
0
0
0
CFG_SDIO[m] Register Contents
Bit Position
Bit Name
b31 to b10
Reserved
Function
b9, b8
SLOTTYPE
R/W
R
Slot Type—Should be set based on the product usage
R/W
2’b00: Removable Card Slot
2’b01: Embedded Slot
Other: Reserved
This slot type is reflected to the SDIO Capabilities register. This field should be set to
an appropriate value since it is also used to determine the Card Detection time.
b7 to b0
BASECLKFREQ
Base Clock Frequency (MHz) setting for SDIO[m]_ECLK Clock
R/W
This field must be set to the below value:
SDIO[m]_ECLK frequency = roundup (1000 / PWRCTRL_SDIO[m]DIV.DIV)
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Feb 28, 2021
Rev.1.40
Page 150 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.83
DBGCON — Debug Control Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.86
Section 6 System Control
4000 C014h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
CA7WD CA7WD CM3W PR_DB
1_DBG 0_DBG D_DBG G_EN
_EN
_EN
_EN
0
0
0
1
DBGCON Register Contents
Bit Position
Bit Name
b31 to b4
Reserved
Function
b3
CA7WD1_DBG_EN
R/W
R
(RZ/N1D)
R/W
Control the watchdog function while Cortex-A7 processor1 is HALTED
0: Enable Cortex-A7 processor1 watchdog on HALT
1: Stop Cortex-A7 processor1 watchdog on HALT
(RZ/N1S, RZ/N1L)
Reserved
b2
CA7WD0_DBG_EN
(RZ/N1D, RZ/N1S)
R/W
Control the watchdog function while Cortex-A7 processor0 is HALTED
0: Enable Cortex-A7 processor0 watchdog on HALT
1: Stop Cortex-A7 processor0 watchdog on HALT
(RZ/N1L)
Reserved
b1
CM3WD_DBG_EN
Control the watchdog function while Cortex-M3 Core is HALTED
R/W
0: Enable Cortex-M3 Core watchdog on HALT
1: Stop Cortex-M3 Core watchdog on HALT
b0
PR_DBG_EN
Control Emulation function
R/W
0: Disable emulation function
1: Enable emulation function—Stop HW-RTOS timers on Halt PR_DBG_EN bit is
control enable, disable of emulation function. Initial setting is enable of emulation
function. During PR_DBG_EN is enable and CPU is halted by debug (e.g. Stop
CPU by ICE), HW-RTOS timer is stopped. This function prevents HW-RTOS OS
timer inconsistence
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Feb 28, 2021
Rev.1.40
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6.3.84
Section 6 System Control
CFG_GPIOT_PTEN_xx — GPIO Trigger Enable Register
Address:
CFG_GPIOT_PTEN_1A: 4000 C0A4h
CFG_GPIOT_PTEN_1B: 4000 C0B0h
CFG_GPIOT_PTEN_2A: 4000 C0B4h
CFG_GPIOT_PTEN_2B: 4000 C0B8h
CFG_GPIOT_PTEN_3A: 4000 C0D8h
CFG_GPIOT_PTEN_3B: 4000 C0DCh
Bit
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
PORTEN
Value after reset
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
PORTEN
Value after reset
Table 6.87
0
0
0
0
0
0
0
0
0
CFG_GPIOT_PTEN_xx Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b0
PORTEN
GPIO port trigger enable (per bit)
R/W
0: Port trigger disable (Enable original BGPIO function)
1: Port trigger enable
NOTE
Bit 31 to 10 are reserved bits for CFG_GPIOT_PTEN_3B.
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Rev.1.40
Page 152 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.85
Section 6 System Control
CFG_GPIOT_TSRC — GPIO Trigger Source Select Register
Trigger Source Select Control for BGPIO1/2/3 Port A/B.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.88
4000 C0BCh
b31
b30
b29
b28
b27
b26
b25
—
—
—
X
X
X
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
—
—
—
X
X
X
b24
b23
b22
b21
—
—
—
0
X
X
X
0
0
b8
b7
b6
b5
b4
b3
—
—
—
X
X
X
TRIG3
TRIG1
0
0
0
0
0
b20
b19
b18
b17
b16
0
0
0
b2
b1
b0
0
0
TRIG2
TRIG0
0
0
0
CFG_GPIOT_TSRC Register Contents
Bit Position
Bit Name
b31 to b29
Reserved
b28 to b24
TRIG3
b23 to b21
Reserved
b20 to b16
TRIG2
Function
R/W
R
GPIO Trigger Source Select for GPIO_TRIGGER[3] (to BGPIO) from interrupt
sources.
TRIG3[4:0]
interrupt source
5’h00:
GPIO_TRIGGER[0] selected by Ethernet Accessary Register
5’h01:
GPIO_TRIGGER[1] selected by Ethernet Accessary Register
5’h02:
GPIO_TRIGGER[2] selected by Ethernet Accessary Register
5’h03:
GPIO_TRIGGER[3] selected by Ethernet Accessary Register
Others:
Not used
R/W
R
GPIO Trigger Source Select for GPIO_TRIGGER[2] (to BGPIO) from interrupt
sources.
R/W
The interrupt sources are same as TRIG3.
b15 to b13
Reserved
b12 to b8
TRIG1
R
GPIO Trigger Source Select for GPIO_TRIGGER[1] (to BGPIO) from interrupt
sources.
R/W
The interrupt sources are same as TRIG3.
b7 to b5
Reserved
b4 to b0
TRIG0
R
GPIO Trigger Source Select for GPIO_TRIGGER[0] (to BGPIO) from interrupt
sources.
R/W
The interrupt sources are same as TRIG3.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 153 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
6.3.86
Section 6 System Control
CFG_DMAMUX — DMAC1 & DMAC2 Multiplexer Register
Ethernet DMA sources can be assigned to 4 DMA channels. However, the same DMA source must not be assigned to
multiple channels.
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.89
4000 C0A0h
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
D2M
X15
D2M
X14
D2M
X13
D2M
X12
D2M
X11
D2M
X10
D2M
X9
D2M
X8
D2M
X7
D2M
X6
D2M
X5
D2M
X4
D2M
X3
D2M
X2
D2M
X1
D2M
X0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
D1M
X15
D1M
X14
D1M
X13
D1M
X12
D1M
X11
D1M
X10
D1M
X9
D1M
X8
D1M
X7
D1M
X6
D1M
X5
D1M
X4
D1M
X3
D1M
X2
D1M
X1
D1M
X0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFG_DMAMUX Register Contents (1/3)
Bit Position
Bit Name
Function
R/W
b31
D2MX15
DMAC2 Request interface15 Multiplexer
R/W
0: TIMER2_SubTimer7
1: ADC ch1
b30
D2MX14
DMAC2 Request interface14 Multiplexer
R/W
0: S3_DIVCLK*1
1: ADC ch0
b29
D2MX13
DMAC2 Request interface13 Multiplexer
R/W
0: S3_CONCLK*1
1: MSEBIM3 (TX on CS1_N)
b28
D2MX12
DMAC2 Request interface12 Multiplexer
R/W
0: MAC_TRIG[1]*1
1: MSEBIM2 (RX on CS1_N)
b27
D2MX11
DMAC2 Request interface11 Multiplexer
R/W
0: MAC_PPS[1]*1
1: MSEBIM1 (TX on CS0_N)
b26
D2MX10
DMAC2 Request interface10 Multiplexer
R/W
0: MAC_PPS[0]*1
1: MSEBIM0 (RX on CS0_N)
b25
D2MX9
DMAC2 Request interface9 Multiplexer
R/W
0: CAT_SYNC1 or SERCOS3_Int[1]*1
1: Reserved
b24
D2MX8
DMAC2 Request interface8 Multiplexer
R/W
0: CAT_SYNC0 or SERCOS3_Int[0]*1
1: Reserved
b23
D2MX7
DMAC2 Request interface7 Multiplexer
R/W
0: TIMER2_SubTimer6
1: Reserved
b22
D2MX6
DMAC2 Request interface6 Multiplexer
R/W
0: S3_DIVCLK*1
1: Reserved
b21
D2MX5
DMAC2 Request interface5 Multiplexer
R/W
0: S3_CONCLK*1
1: UART8 TX
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Table 6.89
Section 6 System Control
CFG_DMAMUX Register Contents (2/3)
Bit Position
Bit Name
Function
R/W
b20
D2MX4
DMAC2 Request interface4 Multiplexer
R/W
0: MAC_TRIG[1]*1
1: UART8 RX
b19
D2MX3
DMAC2 Request interface3 Multiplexer
R/W
0: MAC_PPS[1]*1
1: SPI6 TX
b18
D2MX2
DMAC2 Request interface2 Multiplexer
R/W
0: MAC_PPS[0]*1
1: SPI6 RX
b17
D2MX1
DMAC2 Request interface1 Multiplexer
R/W
0: CAT_SYNC1 or SERCOS3_Int[1]*1
1: SPI5 TX
b16
D2MX0
DMAC2 Request interface0 Multiplexer
R/W
0: CAT_SYNC0 or SERCOS3_Int[0]*1
1: SPI5 RX
b15
D1MX15
DMAC1 Request interface15 Multiplexer
R/W
0: TIMER1_SubTimer7
1: SPI4 TX
b14
D1MX14
DMAC1 Request interface14 Multiplexer
R/W
0: S3_DIVCLK*1
1: SPI4 RX
b13
D1MX13
DMAC1 Request interface13 Multiplexer
R/W
0: S3_CONCLK*1
1: SPI3 TX
b12
D1MX12
DMAC1 Request interface12 Multiplexer
R/W
0: MAC_TRIG[1]*1
1: SPI3 RX
b11
D1MX11
DMAC1 Request interface11 Multiplexer
R/W
0: MAC_PPS[1]*1
1: SPI2 TX
b10
D1MX10
DMAC1 Request interface10 Multiplexer
R/W
0: MAC_PPS[0]*1
1: SPI2 RX
b9
D1MX9
DMAC1 Request interface9 Multiplexer
R/W
0: CAT_SYNC1 or SERCOS3_Int[1]*1
1: SPI1 TX
b8
D1MX8
DMAC1 Request interface8 Multiplexer
R/W
0: CAT_SYNC0 or SERCOS3_Int[0]*1
1: SPI1 RX
b7
D1MX7
DMAC1 Request interface7 Multiplexer
R/W
0: TIMER1_SubTimer6
1: UART7 TX
b6
D1MX6
DMAC1 Request interface6 Multiplexer
R/W
0: S3_DIVCLK*1
1: UART7 RX
b5
D1MX5
DMAC1 Request interface5 Multiplexer
R/W
0: S3_CONCLK*1
1: UART6 TX
b4
D1MX4
DMAC1 Request interface4 Multiplexer
R/W
0: MAC_TRIG[1]*1
1: UART6 RX
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Table 6.89
Section 6 System Control
CFG_DMAMUX Register Contents (3/3)
Bit Position
Bit Name
Function
R/W
b3
D1MX3
DMAC1 Request interface3 Multiplexer
R/W
0: MAC_PPS[1]*1
1: UART5 TX
b2
D1MX2
DMAC1 Request interface2 Multiplexer
R/W
0: MAC_PPS[0]*1
1: UART5 RX
b1
D1MX1
DMAC1 Request interface1 Multiplexer
R/W
0: CAT_SYNC1 or SERCOS3_Int[1]*1
1: UART4 TX
b0
D1MX0
DMAC1 Request interface0 Multiplexer
R/W
0: CAT_SYNC0 or SERCOS3_Int[0]*1
1: UART4 RX
Note 1.
CAT_SYNC0 or SERCOS3_Int[0] is selected by DMACTRL in Ethernet Accessory registers.
CAT_SYNC1 or SERCOS3_Int[1] is selected by DMACTRL in Ethernet Accessory registers.
7 DMA requests from Ethernet Peripherals are assigned to the request interface 4 times, only one request should be used at
the same time.
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6.3.87
Section 6 System Control
VERSION — Product Version Register
Address:
Bit
Value after reset
Bit
Value after reset
Table 6.90
4000 C19Ch
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
—
—
—
—
—
—
—
PROD
X
X
X
X
X
X
X
X
X
X
X
VERSION
X
X
X
X
X
VERSION Register Contents
Bit Position
Bit Name
b31 to b9
Reserved
Function
b8
PROD
R/W
R
0: RZ/N1D
R
1: RZ/N1S, RZ/N1L
b7 to b0
HW version*1
VERSION
R
RZ/N1D: 0x13
RZ/N1S, RZ/N1L: 0x11
Note 1.
If the version shows RZ/N1D: 0x11 or RZ/N1S, RZ/N1L: 0x10, A5PSW register write access issue might happen. Please refer
to Technical Update with regard to the workaround.
6.3.88
BOOTADDR — Cortex-A7 processor1 Boot Address Configuration Register
Cortex-A7 processor1 is in standby mode during processor0 ROM boot process. 2nd boot loader should set this register
in order to define the processor1 boot address. Once the processor1 reset is released, it executes a code in ROM at first,
and gets jump address from this register.
This register is only used in RZ/N1D and is available from Cortex-A7.
Address:
Bit
b31
b30
4000 C204h
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
BOOTADDR
Value after reset
Bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
BOOTADDR
Value after reset
Table 6.91
0
0
0
0
0
0
0
0
0
BOOTADDR Register Contents
Bit Position
Bit Name
Function
R/W
b31 to b0
BOOTADDR
2nd boot address of the Cortex-A7 processor1
R/W
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Section 7
7.1
Section 7 Operating Modes
Operating Modes
Overview
In RZ/N1D and RZ/N1S, Cortex-A7 boots at first, then executes the bootloader in embedded ROM. 3 boot sources,
QSPI or NAND Flash or USB are available. The bootloader initializes the RZ/N1 for 1st boot, after that loads and
executes a second bootloader from the boot sources.
In RZ/N1L, Cortex-M3 boots (Cortex-A7 is not available). Cortex-M3 executes a code in QSPI directly.
System Controller manages reset, clock and configuration based on external pins or registers. Boot mode and sequence
are also handled in the System Controller.
System Controller
n=75..79, 83
as External Pin Configuration
OPMODE
GPIO[n]
CONFIG[2:0]
MRESET_N
PWRCTRL_*
Clock
Controller
Figure 7.1
MRESET_OUT
System Controller
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7.2
Section 7 Operating Modes
Boot Mode Specification (for RZ/N1D and RZ/N1S)
7.2.1
Common Feature
● Cortex-A7 Clock Speed
− Cortex-A7: 250 MHz
− The BootROM uses the default divider setting (/2).
● RAM requirements
− 64 kB, 0x200F_0000 – 0x200F_FFFF, is used by for BootROM
● UART1 outputs boot messages.
− 115200Baud
− UART TXD pin (GPIO[103]) is used for UART interface
− Boot progress and error messages
● 2nd Stage Boot Image
− Maximum Size 1 MByte
− Minimum Size 4 Bytes
− 2nd Stage Image must execute from internal SRAM (2MB SRAM) in continuous region.
In other words, address region from either 0x0400_0000 – 0x040F_FFFF or 0x2000_0000 – 0x200E_FFFF.
7.2.2
QSPI Boot Feature
● The bootloader in embedded ROM initializes QSPI module and configures following GPIO pins as
Level1/Func4 (QSPI1) in QSPI boot mode. QUAD1_CS_N[3:1] (GPIO73, GPIO149 and 150) are configured as CS
output pins. Please take into account the I/O mode if those pins are used for other function on a board design.
GPIO pins
Pull mode
QSPI1 pin name
GPIO74
without
Pullup/Pulldown
QUAD1_CS_N[0]
Output
Always used in QSPI boot
QUAD1_IO[3]
Input/Output
GPIO76
QUAD1_IO[2]
Input/Output
Refer to “Section 7.3.2, External Pin
Configuration”.
GPIO77
QUAD1_IO[1]
Input/Output
GPIO78
QUAD1_IO[0]
Input/Output
GPIO79
QUAD1_CLK
Output
GPIO73
QUAD1_CS_N[1]
Output
GPIO149
QUAD1_CS_N[2]
Output
GPIO150
QUAD1_CS_N[3]
Output
GPIO75
Pin I/O mode
Note
These pins could be used for other
function by user configuration. but please
be aware of pin state set by the ROM.
● Supported Serial Flash
(1) Quad IO SPI Flash
(2) Single IO SPI Flash
The bootloader accesses the device connected to QUAD1_CS_N[0] in standard SPI mode.
● CLK frequency for Flash: 5.2 MHz
● Address: 3 bytes
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7.2.3
Section 7 Operating Modes
NAND Boot Feature
● The bootloader in embedded ROM initializes NAND module and configures following GPIO pins as
Level1/Func3 (NAND) in NAND boot mode.
GPIO pins
Pull mode
QSPI1 pin name
Pin I/O mode
GPIO80
without
Pullup/Pulldown
FNAND_ALE
Output
GPIO81
FNAND_CLE
Output
GPIO82
FNAND_WE_N
Output
GPIO83
FNAND_RE_N
Output
GPIO91..84
FNAND_IO[7:0]
Input/Output
GPIO92
FNAND_CE_N[0]
Output
GPIO93
FNAND_WP_N[0]
Output
FNAND_RY/BY_N[0]
Input
GPIO94
with pullup
Note
Refer to “Section 7.3.2, External Pin
Configuration”.
● Supported NAND Flash
(1) ONFI 1.0 / asynchronous NAND Flash
− IO bus size: 8-bit
− Density: 1 to 8-Gbit
− Mode 0 is used through boot. Devices must support Mode0.
The bootloader identifies the device before triggering the boot sequence (either “Read ID” command or Read
ONFI parameters) and set timings & ECC accordingly.
If “READ ID” is not supported on the device, it cannot be booted.
(2) ONFI 2.0 synchronous NAND Flash
Only in ONFI 1.0 backwards compatibility mode, compliant to the NAND Flash Controller limitations
● NAND_ECLK frequency: 83.3MHz
− FNAND_RE_N/FNAND_WE_N is asserted for 5 NAND_ECLK cycles and held high for 3 NAND_ECLK
cycles.
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7.2.4
Section 7 Operating Modes
USB Boot Feature
● The bootloader in embedded ROM configures the RZ/N1 USB Port1 as a USB Function mode and DFU Device
● USB Speed
− Full speed and High speed
● USB DFU Function interface
− Standard DFU interface for uploading 2nd stage image
● PC / Host DFU Software
− Generic DFU host software may be used
e.g. “dfu_util” from Sourceforge, and a generic DFU driver “libUSBk”
http://dfu-util.sourceforge.net/releases/dfu-util-0.8-binaries/win32-mingw32/
https://sourceforge.net/projects/libusbk/
The Boot from USB downloads an SPKG format image at first. An SPKG image will be downloaded to the internal
SRAM from a USB DFU Host e.g. a PC running USB Function Firmware Upgrade application.
The PC utility only provides a mechanism for downloading an SPKG. The host PC is not able to directly reprogram the
FLASH.
After USB boot, this application (possibly uBoot or similar) is able to update the FLASH with a new image from the
PC.
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7.3
Section 7 Operating Modes
Standard Boot Sequence
7.3.1
Overview
RZ/N1 System Controller captures initial system setting from certain external pins at rising of MRESET_N pin. Then,
primary CPU execute 1st bootloader. In RZ/N1D and RZ/N1S, primary CPU is Cortex-A7 and 1st bootloader is placed
in embedded ROM. In RZ/N1L, primary CPU is Cortex-M3 and 1st boot loader should be placed in QSPI Flash.
7.3.2
External Pin Configuration
The following external pins are used to system configuration and boot sequence.
− GPIO[75] (QUAD1_IO[3])
− GPIO[76] (QUAD1_IO[2])
− GPIO[77] (QUAD1_IO[1])
− GPIO[78] (QUAD1_IO[0])
− GPIO[79] (QUAD1_CLK)
− GPIO[83] (FNAND_RE_N)
These pins come up as input without integrated pull-up/-down.
Please select suitable mode by external pull-up/-down resister on a PCB board.
Table 7.1
External Pin Configuration
Control Signal
Function Configured
Comment
GPIO[75]
0: DDR3
DDR Memory controller configuration for RZ/N1D.
1: DDR2
In other models, should be pulled up or down.
GPIO[76]
Should be 1
GPIO[78:77]
2’b00: CA7 Boot on QuadSPI
Boot mode configuration for RZ/N1D and RZ/N1S.
2’b01: CA7 Boot on NAND Flash
In RZ/N1L, pulled up or down.
2’b10: CA7 Boot on USB Function
2’b11: Reserved
GPIO[79]
1: Pull-up on GPIO[73:62] and
GPIO[145:127]
LCD interface default pull configuration for RZ/N1D and
RZ/N1S.
0: Pull-down on GPIO[73:62] and
GPIO[145:127]
In RZ/N1L, should be 1.
GPIO[83]
Should be 1
Boot Debug signal
Function configured
Comment
GPIO[103]
UART1 TXD
UART debugging for boot (for RZ/N1D and RZ/N1S)
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7.3.3
Section 7 Operating Modes
CPU Booting
The system controller carries out the initial setup of the interconnect and releases the reset of the primary CPU based on
the system configuration. A series of actions precedes the reset de-assertion of the primary CPU. These initial setup
actions are carried out in system controller. During this phase, all CPUs are held in reset. Once all steps accomplished,
the primary CPU is released from reset.
During the system initialization after external reset triggered by “MRESET_N”, the system controller samples and
stores the external pin configuration defined by external pull resistors.
The sampling sequence is as follows:
● On the first oscillator clock edge after “MRESET_N” de-assertion: The external pin configurations are sampled, the
LCD pull up/down control bit is directly taken from the GPIO[79].
● On the second “clock” edge after “MRESET_N” de-assertion: The boot configuration is sampled to FF, the LCD pull
up/down control bit switches to be driven from FF value.
● On the third “clock” edge after “MRESET_N” de-assertion: The “BOOTMODE_LATCHED” signal is asserted for
the de-assertion of “MRESET_OUT” in clock controller
MCLK_XI, MCLK_XO
MRESET_N
iMRESETn
BOOTMODE_reg
0x0
PU/PD value
BOOTMODE_LATCHED
Default LCD Pull value
Figure 7.2
PU/PD value
PU/PD value
Boot Configuration Sampling Sequence
CAUTION
External pull values must be kept that the appropriate value is captured in the External Pin Configuration while the
“MRESET_OUT” signal is being asserted.
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7.3.4
Section 7 Operating Modes
RZ/N1D and RZ/N1S Boot
In a system with Cortex-A7 processor(s) and Cortex-M3 processor, Cortex-A7 processor0 will be the Primary or Boot
processor.
After the system is powered up, both Cortex-A7 processors, Cortex-A7 processor0 and processor1, will come out of
reset and execute the code in embedded ROM at address 0x00000000. An initial core ID check puts Cortex-A7
processor1 to WFE.
Only Cortex-A7 processor0 will be permitted to execute the remainder of the boot code. Then the 2nd stage bootloader
is executed. The Reset vector address for the Cortex-A7 processor1 and the Cortex-M3 processor may be configured to
any locations. BOOTADDR register defines the boot address for Cortex-A7 processor1.
● For debug purpose, the bootloader configures the GPIO[103] in Level 1 function 15 and Level 2 function 12
(UART1_TXD), this IO Multiplexing configuration is kept after the end of bootloader.
7.3.5
RZ/N1L Boot
In RZ/N1L, Cortex-M3 will be the Primary processor.
The Cortex-M3 will not run the Bootloader in embedded ROM. It boots directly at 5.2 MHz from QSPI Flash mapped
to 0x00000000.
GPIO[74:79] is configured to QSPI1 by System Controller with the following settings:
GPIO pins
Pull mode
QSPI1 pin name
GPIO74
with Pullup
QUAD1_CS_N[0]
Output
GPIO75
without
Pullup/Pulldown
QUAD1_IO[3]
Input/Output
GPIO76
QUAD1_IO[2]
Input/Output
GPIO77
QUAD1_IO[1]
Input/Output
GPIO78
QUAD1_IO[0]
Input/Output
GPIO79
QUAD1_CLK
Output
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Note
Refer to “Section 7.3.2, External Pin
Configuration”.
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7.4
7.4.1
Section 7 Operating Modes
SPKG Format (for RZ/N1D and RZ/N1S)
Overview
Data loaded from boot source (QSPI, NAND FLASH, USB) is subject to the possibility of the corrupt image by bit
errors. SPKG format is used to check the contents.
7.4.2
Implementation Specifics
The Bootloader loads a valid SPKG from the chosen boot source (QSPI, NAND FLASH or USB).
The SPKG contains:
● A block consisting of 8 headers (with a header CRC)
● A Payload (Immediately following the block of headers):
− The 2nd stage bootloader image
− A payload CRC value
The SPKG data fields are defined in the following table.
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Table 7.2
SPKG Field
Section 7 Operating Modes
SPKG Fields
Bits
Length
Field
Header*1
Description
Total 24 bytes
31:0
32 bits
Marker
“R”, “Z”, “N”, “1” to mark the Header start
35:32
4 bits
version
SPKG header type version
39:36
4 bits
spare bits
Set to “0”
40
1 bit
padding
Set to “0”
42:41
2 bits
NAND ECC block size
(codeword size)
Value is configured to ECC_BLOCK_SIZE in CONTROL
register of NAND Flash Controller
2’b00 – 256 bytes
2’b01 – 512 bytes
2’b10 – 1024 bytes
2’b11 – INVALID
44:43
2 bits
padding
Set to “0”
45
1 bit
Hardware ECC Support
enable
Value is configured to ECC_EN in CONTROL register of
NAND Flash Controller
0 – ECC disabled
1 – ECC enabled
47:46
2 bits
padding
Set to “0”
50:48
3 bits
NAND ECC scheme
Value is configured to ECC_CAP in ECC_CTRL register of
NAND Flash Controller
3’b000 – BCH2
3’b001 – BCH4
3’b010 – BCH8
3’b011 – BCH16
3’b100 – BCH24
3’b101, 3’b110, 3’b111 – BCH32
55:51
5 bits
padding
Set to “0”
63:56
8 bits
NAND ECC bytes per
block
Number (8-bit value) of NAND Flash ECC Bytes per NAND
ECC block
e.g. for BCH8 and NAND ECC block size = 512, this value
will be typically 14 (0x0E)
71:64
8 bits
spare byte
Set to “0”
95:72
24 bits
payload length
Payload length consisting of BLp_header, image and
Payload CRC
127:96
32 bits
load addr
Address of internal memory to where the 2nd stage
bootloader image should be written.
159:128
32 bits
execution offset*2
Offset from the start of the 2nd stage bootloader image in
internal memory to where the code should execute from.
191:160
32 bits
Header CRC
Payload
variable length
264 Bytes
BLp_header
variable
2nd stage bootloader
image
32 bits
Payload CRC
Header for Security option. Set to “0” if not to use the security
function.
Note 1.
When downloading from NAND Flash, the Header will not have ECC but will check by CRC. The Payload will be ECCprotected using the scheme as specified in bits 41-63. The Header will be repeated 8 times since no ECC. i.e. the SPKG will
consist of 8 Headers followed by 1 Payload.
Note 2.
Bit 0 of execution offset is used to select Thumb® or Arm instruction for the 2nd Stage Bootloader (0 = Arm instruction, 1 =
Thumb instruction).
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Section 7 Operating Modes
The integrity of the boot image data from three sources (QSPI, NAND FLASH, USB) is taken account as following.
● NAND – Data stored in NAND FLASH will be verified integrity by CRC feature and is also able to use option to be
safeguarded by the BCH ECC feature in the hardware. The ECC data is stored in the spare area of the NAND
FLASH.
− The bootloader accesses the data of header block in the NAND without ECC. The header block is read and
verified using the header CRC value. Since the header is not subject to ECC, eight copies of the header are used to
mitigate for errors.
− Once a header is validated, the ECC parameter of the payload is configured.
− The ECC parameter is user defined. The parameter used when writing the image to NAND FLASH should be
reflected to SPKG header. The user should be free to decide on the level of ECC within what supported by the
NAND Flash controller.
− An SPKG should be located at the start of a page. The bootloader searches an SPKG from the first page in order.
● QuadSPI – This is less likely to contain errors, but will also be CRC checked to verify its integrity as part of the
standard SPKG processing.
− An SPKG should be located at the start of a page. The bootloader searches an SPKG from the first page in order.
● USB –The bootloader will also CRC check for the SPKG received via USB DFU. SPKG downloaded over USB is
only one.
The SPKG verification is as follows:
● The header is located in the first of SPKG, and verified using header CRC value. When fail, the next header is used,
if all 8 headers fail, the next SPKG is used. Then the process repeats until no errors. Failures in the CRC check will
be reported as UART message. The bootloader process is halted if all SPKGs are invalid.
● The payload is verified by CRC check
● If an error is detected in SPKG, this will be reported as UART message.
In a multi Logical Unit (multi-LUN) Flash device, the Bootloader will use the images stored in the first LUN detected –
LUN0.
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7.5
7.5.1
Section 7 Operating Modes
RZ/N1 Initialize Sequence
Standard Initialize Sequence
1)
Set programmable clock divider value by DIV of PWRCTRL_*DIV register.
2)
Enable target clock by CLKEN_* bit of PWRCTRL_* register
3)
De-assert reset for target function module by RSTN_* bit of PWRCTRL_* register.
4)
Connect NoC interconnect by PWRCTRL_* and PWRSTAT_* registers.
Refer to “Generic Programming Sequence for NoC” part
5)
IO multiplexing configuration by rGPIOs_Level1_Config* and rGPIOs_Level2_Config* registers.
Refer to “IO Multiplexing” chapter
6)
Module initialize
7.5.2
USBPLL Setting
USBPLL can provide 48MHz clock for some modules besides USB. If the clock is necessary, following sequence is
required.
1)
Enable USB_HCLKH, USB_HCLKF, USB_HCLKPM and USB_PCICLK by CLKEN_* bit of
PWRCTRL_USB register.
2)
De-assert reset of USB by RSTN_* bit of PWRCTRL_USB register.
3)
Connect NoC interconnect by PWRCTRL_USB and PWRSTAT_USB registers.
4)
Enable FRCLK48MOD bit of CFG_USB register.
5)
Disable DIRPD bit of CFG_USB register.
6)
Wait 1ms.
7)
De-assert PLL_RST bit of EPCTR register in USB Function.
8)
Wait until PLL_LOCK bit of EPCTR register in USB Function is asserted.
7.5.3
Activating Cortex-M3
In case of RZ/N1D and RZ/N1S, Cortex-M3 reset is enabled after Cortex-A7 bootup.
Cortex-A7 needs to execute following sequence in order to activate Cortex-M3.
1)
Enable RINBUS_HCLK by CLKEN_A of PWRCTRL_RINCTRL register.
2)
Enable CM3_HCLK by CLKEN_A of PWRCTRL_CM3 register.
3)
Release reset of Cortex-M3 by RSTN_A of PWRCTRL_CM3 register.
4)
Connect NoC interconnect by PWRCTRL_CM3 and PWRSTAT_CM3 registers.
Then, Cortex-M3 boots up by the code placed at 0x0400_0000.
(In RZ/N1D and RZ/N1S, 0x0400_0000 – is mirrored to 0x0 by R-IN Engine internal structure)
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7.5.4
Section 7 Operating Modes
Generic Programming Sequence for NoC
The following figure shows the programming sequence of the clock, reset and NoC connect/disconnect flow.
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module is in Ope ration
module is in O peration
Stop module activity
Section 7 Operating Modes
Stop a new da ta access requ est to the
NoC in terconn ect to be disconnected.
Gra cefully Sto p the module Activity
using th e Reg isters o f th e mod ule.
(1) Stop a new da ta transfe r
requ est to the Target NoC
interconne ct.
Var ious module accessin g the
target NoC in terconn ect stop s a
new data tran sfer reque st
False
(2) Ver ify that activity is stoppe d
with a status regi ster of the tar get
module.
All module activity disabled?
No
All module activity disabled?
True
Yes
False
Type of REQ
(3) Set Idle Requ est to NoC
interconne ct for disconnection.
No
Has all traffic been fl ush ed?
Yes
True
(5) NoC in terconn ect wi ll be Idle
when all th e traffi c has b een
flushed.
Registe r write
PWRCTRL_XXX.SLV RDY=0
Discon nect th e modu le from NoC
interconne ct, preven t to initiate new
requ ests to th e targe t and let the target
interface serve all th e pe nding
transaction s, wait for which all
respon ses returned to the requ est
initiator.
(4) Set ackno wle dge by NoC
interconne ct.
Registe r re ad
PWRSTAT_XXX.MIS TA T=1
(6) Indicate to the NoC
interconne ct that target mo dule
has become "Not Ready".
No
False
Registe r re ad
PWRSTAT_XXX.SCON=0
Type of RDY
Disconnect the module from NoC
Registe r write
PWRCTRL_*.MIREQ=1
Has all respon se s returned?
Yes
(7) Status is re se t to 0 by NoC
interconne ct to a cknowledg e
disconnection.
Put the module in reset (optional),
and Gate module clocks
True
Figure 7.3
Acti vate all resets of the mo dule
Registe r write
PWRCTRL_XXX.RSTN=0
Afte r di sconne cting a module. Softwa re
may or may n ot appl y reset to the
module . In case Re set is app lied
Softwa re shal l wait u ntil the reset
prop agates to all domains o f th e
affe cted module. This time i s
dep enden t on the pa rticula r
requ irements of the module and the
actu ally configure d clock frequ ency of
the affecte d d omain.
Wait for reset pro pagation
5us d elay is recomme nded
Gate module clocks
Registe r write
PWRCTRL_XXX.CLKEN=0
(8) The clo ck for the mo dule co uld
be gated
Generic Programming Sequence for NoC – Disconnect
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Release module reset and start
module clocks
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Start modu le clocks and
de-assert module re set
Registe r write
PWRCTRL_XXX.CLKEN=1
PWRCTRL_XXX.RSTN=1
(1) The clo ck is activated
Afte r re set is rele ase d, wait time
dep ending on ea ch module is require d
before reconn ection to NoC
interconne ct.
Wait for reset propagation and
access prohibit time
5us delay is recommended
(2) Indicate to the NoC
interconne ct that target mo dule
has become "Ready".
False
Registe r re ad
PWRSTAT_XXX.SCON=1
Type of RDY
Registe r write
PWRCTRL_*.SLV RDY=1
Once th e mod ule is read y, Conne ct it to
the NoC interconnect.
(3) Status is set to 1 by NoC
interconne ct to a cknowledg e
connection.
True
Registe r write
PWRCTRL_XXX.MIREQ=0
(4) Reset Idle Re quest to NoC
interconne ct for connection.
False
Registe r re ad
PWRSTAT_XXX.MIS TA T=0
Type of REQ
Connect the module to NoC
Section 7 Operating Modes
(5) Idle Sta tus is reset to 0 by NoC
interconne ct to a cknowledg e
connection.
Start module
activity
True
Figure 7.4
module is accessible
Generic Programming Sequence for NoC – Connect
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Section 7 Operating Modes
The following table shows related PWRCTRL and PWRSTAT registers to make each module available.
There is no need to control PWRCTRL & PWRSTAT registers to access Watchdog for CA7/CM3, System Controller,
ConfigSys1, 4MB SRAM with ECC Controller, CoreSight, Mailbox.
PWRCTRL_RINCTRL should be enabled before accessing registers since ECC registers of 2MB SRAM is running on
a clock controlled by PWRCTRL_RINCTRL.
Table 7.3
Related Registers for Connect/Disconnect of Each module (1/2)
PWRCTRL_XXX Register for
NoC Connect
(Type of REQ)
MIREQ/MISTAT
CLKEN/RSTN
PWRCTRL_XXX Register for
NoC Connect
(Type of RDY)
SLVRDY/SCON
CLKEN/RSTN
PWRCTRL_XXX
Register for
module Interface
CLKEN/RSTN
MSEBIM
MSEBI
MSEBI
ROM
ROM
ROM
R-IN Engine
Accessory Register
RINCTRL
RINCTRL
Ethernet Accessory
Register
SWITCHCTRL
SWITCHCTRL
SWITCHCTRL*1
A5PSW
SWITCH
SWITCH
SWITCH
QSPI1
QSPI1*
2
QSPI1
QSPI2
QSPI2*
2
QSPI2
PG0_0
PG0_0
PG0_1
PG0_0
PG0_0
PG0_0
ADC 1/2
PG0_0
PG0_0
PG0_1
PWMTimer
PG0_1
UART 4/5*
QSPI1
QSPI1
QSPI1*
2
QSPI2
QSPI2
QSPI2*
2
I2C 1/2
UART 1/2/3*
3
PG0_1
PG1_1
PG1_1
PG1_PR2
UART 6/7/8*3
PG1_2
PG1_2
PG1_PR2
SPI 1/2/3/4
PG1_1
PG1_1
PG1_PR3
SPI 5/6
PG1_1
PG1_1
PG1_PR4
CAN 1/2
PG3_48MHZ
PG3_48MHZ
ConfigSys2
PG2_25MHZ
PG2_25MHZ
TIMER 1/2
PG2_25MHZ
Semaphore
PG4
PG4
BGPIO 1/2
PG1_1
PG1_1
BGPIO 3
PG1_2
PG1_2
PG4
PG4
3
PG2_25MHZ
LCDC
PG4
PG4
ETHERCAT
ECAT
ECAT
ECAT*4
SERCOSIII
SERCOS
SERCOS
SERCOS*4
HSR
HSR
HSR
HSR*4
DDR 2/3 Controller
DDRC
DDRC
DDRC
USB
USB*5
USB*5
USB
Cortex-M3*
CM3
CM3
MSEBIS
MSEBI
MSEBI*2
MSEBI
MSEBI*2
DMAC 1/2
DMA
DMA*
DMA
DMA*2
GMAC1
MAC1
MAC1*2
MAC1
MAC1*2
GMAC2
MAC2
MAC2*2
MAC2
MAC2*2
6
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Table 7.3
Section 7 Operating Modes
Related Registers for Connect/Disconnect of Each module (2/2)
PWRCTRL_XXX Register
for NoC Connect
(Type of REQ)
MIREQ/MISTAT
CLKEN/RSTN
SDIO1
SDIO1
SDIO1*
2
SDIO2
SDIO2
SDIO2*
2
NAND Flash
Controller
NFLASH
NFLASH*2
RTC*7
RTC
RTC
PWRCTRL_XXX Register
for NoC Connect
(Type of RDY)
SLVRDY/SCON
SDIO1
CLKEN/RSTN
PWRCTRL_XXX
Register for
module Interface
CLKEN/RSTN
SDIO1*
2
SDIO1
SDIO2
SDIO2*
2
SDIO2
NFLASH
NFLASH*2
NFLASH
RTC
External Ethernet
Clock
EETH*8
HW-RTOS
HWRTOS*9
Note 1.
2xRSTNs (RSTN_ETH, RSTN_CLK25)
Note 2.
CLKEN/RSTN are common for both type
Note 3.
Main PLL or USBPLL are selectable for clock source
Note 4.
2xCLKENs, 1xRSTN
Note 5.
2xMIREQs, 3xCLKENs, 1xRSTN
Note 6.
PWRCTRL_RINCTRL should be enabled before PWRCTRL_CM3
Note 7.
Special sequence is required for RTC
Release RST_RTC → Enable RTC_PCLK → Release RSTN_FW_RTC → Release IDLE_REQ
CLKEN_RTC should be enabled during RTC access only
Note 8.
CLKEN for MII REFCLK (External output), RMII REFCLK (External output) and RGMII REFCLK (External input)
Note 9.
CLKEN/RST for HW-RTOS and CLKEN for HW-RTOS GMAC MDC
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Section 8
8.1
Section 8 Ethernet Interface Modes
Ethernet Interface Modes
Overview
Several modules for Ethernet protocols, GMII/MII Multiplexing logic and RGMII/RMII Converters are in Ethernet
Peripherals part. This chapter provides the information about available Ethernet Peripherals part configuration.
HWRTOS GMAC
GMAC2
GMAC1
MAC2
PORT
MAC1
PORT
RTOS
PORT
RTOS PORT
SERCOS III
SERCOS
PORTA(Port1)
ETHERCAT
SERCOS
PORTB(Port2)
ETHERCAT
PORTA(Port0)
ETHERCAT
PORTB(Port1)
SWITCH
PORTA(Port0)
SWITCH
PORTC(Port2)
Mux HSR
HSR PORTI
SW_MODE[4:0]
SWITCH
PORTD(Port3)
MAC2 PORT
HSR
HSR
PORTA
SWITCH
PORTIN(Port4)
SWITCH
PORTB(Port1)
SWITCH PORTA
SW_MODE[4:0]
MAC2_RTOS PORT
Advanced
5ports SWITCH
Cut-through
ETHERCAT
PORTC(Port2)
MAC2 PORT
Mux MAC2/RTOS
SW_MODE[4:0]
HSR
PORTI
INTERLINK
HSR
PORTB
SW_MODE[4:0]
SERCOS PORTA
ETHERCAT PORTA
HSR PORTA
SWITCH PORTA
HSR PORTI
SERCOS PORTB
ETHERCAT PORTB
SWITCH PORTD
SWITCH PORTC
Mux GMII/MII3
Mux GMII/MII5
GMII/MII5 PORT
ETHERCAT PORTC
GMII/MII3 PORT
HSR_PORTB
SWITCH PORTB
MAC2 PORTC
Mux GMII/MII2
GMII/MII2 PORT
SW_MODE[4:0]
SW_MODE[4:0]
Mux GMII/MII4
GMII/MII4 PORT
RGMII/RMII
Converter
(MII_CONV5)
RGMII/RMII
Converter
(MII_CONV3)
SW_MODE[4:0]
RGMII/RMII
Converter
(MII_CONV4)
RGMII/RMII
Converter
(MII_CONV2)
RGMII/RMII
Converter
(MII_CONV1)
IO Multiplexer Level1
Buffer
Buffer
GPIO48 to GPIO59
IO Multiplexer Level2
GPIO36 to GPIO47
Figure 8.1
Ethernet Peripherals Part Structure
Table 8.1
Supported Ethernet Port
RZ/N1D
Ethernet Port
Buffer
Buffer
Buffer
GPIO24 to GPIO35
GPIO12 to GPIO23
GPIO0 to GPIO11
RZ/N1S
RZ/N1L
BGA-400
BGA-324
BGA-324
BGA-196
BGA-196
Port 1
N/A
Port 2
N/A
N/A
N/A
Port 3
N/A
N/A
Port 4
Port 5
Note: Please refer to Section 8.2.1, Internal Connection of Ethernet Ports about SW_MODE[4:0] in the above figure.
However, the available setting is different for each product.
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Section 8 Ethernet Interface Modes
The following registers are used for configuring RGMII/RMII Converter and multiplex of Ethernet Peripherals part.
Please refer to UM for R-IN Engine and Ethernet Peripherals.
Table 8.2
Operation Mode Control Registers
Address
Register Symbol
Register Name
4403 0008h
MODCTRL
Mode Control register
4403 000Ch
PTPMCTRL
PTP Mode Control register
4403 0100h
CONVCTRL1
RGMII/RMII Converter1 Control register
4403 0104h
CONVCTRL2
RGMII/RMII Converter2 Control register
4403 0108h
CONVCTRL3
RGMII/RMII Converter3 Control register
4403 010Ch
CONVCTRL4
RGMII/RMII Converter4 Control register
4403 0110h
CONVCTRL5
RGMII/RMII Converter5 Control register
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8.2
Section 8 Ethernet Interface Modes
Support Modes
Table 8.3
Support Modes of Ethernet I/F
Ethernet I/F Mode
After
Before
Conversion Conversion Communication Mode
Register Value
RGMII/RMII Converter
RGMII Clock
Selector
Speed
[bps]
Full
Duplex
/Half
Duplex
CONVCTRL[m].
CONV_MODE
(m = 1 to 5)
CONVCTRL[m].
FULLD
(m = 1 to 5)
CONVCTRL[m].
RMII_CRS_MODE PTPMCTRL.
(m = 1 to 5)
RGMII_CLKSEL
MII
10 M
Half
5’b00000
1’b0
1’b1
1’b0
MII
10 M
Full
5’b00000
1’b1
1’b1
1’b0
MII
MII
100 M
Half
5’b00000
1’b0
1’b1
1’b0
MII_100M_FULL
MII
MII
100 M
Full
5’b00000
1’b1
1’b1
1’b0
5
RMII_10M_HALF_RI
RMII
MII
10 M
Half
5’b00100
1’b0
1’b1
1’b0
6
RMII_10M_FULL_RI
RMII
MII
10 M
Full
5’b00100
1’b1
1’b1
1’b0
7
RMII_100M_HALF_RI
RMII
MII
100 M
Half
5’b00101
1’b0
1’b1
1’b0
8
RMII_100M_FULL_RI
RMII
MII
100 M
Full
5’b00101
1’b1
1’b1
1’b0
9
RMII_10M_HALF_RO
RMII
MII
10 M
Half
5’b10100
1’b0
1’b1
1’b0
10
RMII_10M_FULL_RO
RMII
MII
10 M
Full
5’b10100
1’b1
1’b1
1’b0
11
RMII_100M_HALF_RO
RMII
MII
100 M
Half
5’b10101
1’b0
1’b1
1’b0
12
RMII_100M_FULL_RO
RMII
MII
100 M
Full
5’b10101
1’b1
1’b1
1’b0
13
RGMII_10M_HALF_RI
RGMII
MII
10 M
Half
5’b01000
1’b0
1’b1
1’b1
14
RGMII_10M_FULL_RI
RGMII
MII
10 M
Full
5’b01000
1’b1
1’b1
1’b1
15
RGMII_100M_HALF_RI
RGMII
MII
100 M
Half
5’b01001
1’b0
1’b1
1’b1
16
RGMII_100M_FULL_RI
RGMII
MII
100 M
Full
5’b01001
1’b1
1’b1
1’b1
17
RGMII_1G_HALF_RI
RGMII
GMII
1G
Half
5’b01010
1’b0
1’b1
1’b1
18
RGMII_1G_FULL_RI
RGMII
GMII
1G
Full
5’b01010
1’b1
1’b1
1’b1
19
RGMII_10M_HALF
RGMII
MII
10 M
Half
5’b01000
1’b0
1’b1
1’b0
20
RGMII_10M_FULL
RGMII
MII
10 M
Full
5’b01000
1’b1
1’b1
1’b0
21
RGMII_100M_HALF
RGMII
MII
100 M
Half
5’b01001
1’b0
1’b1
1’b0
22
RGMII_100M_FULL
RGMII
MII
100 M
Full
5’b01001
1’b1
1’b1
1’b0
23
RGMII_1G_HALF
RGMII
GMII
1G
Half
5’b01010
1’b0
1’b1
1’b0
24
RGMII_1G_FULL
RGMII
GMII
1G
Full
5’b01010
1’b1
1’b1
1’b0
No. Mode Name
MII
/RMII
/RGMII
MII
/GMII
1
MII_10M_HALF
MII
2
MII_10M_FULL
MII
3
MII_100M_HALF
4
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Table 8.4
Clock I/F for Ethernet PHY (Part 1)
No. & Mode Name
Clocks
Reference
Clock
Section 8 Ethernet Interface Modes
1
2
3
4
MII_10M_HALF
MII_10M_FULL
MII_100M_HALF
MII_100M_FULL
Direction
output to PHY
Clock Signal Name
MII_REFCLK
Frequency [MHz]
Transmit
Clock
25
Direction
Input from PHY
Clock Signal Name
GMII[m]_TXCLK (m = 1..5)
Frequency [MHz]
Receive
Clock
2.5
Input from PHY
Clock Signal Name
GMII[m]_RXCLK (m = 1..5)
Frequency [MHz]
Table 8.5
2.5
25
Clock I/F for Ethernet PHY (Part 2)
5
6
7
8
RMII_10M_HALF_RI
RMII_10M_FULL_RI
RMII_100M_HALF_RI
RMII_100M_FULL_RI
No. & Mode Name
Clocks
Reference
Clock
25
Direction
Direction
Input from PHY
Clock Signal Name
GMII[m]_RXCLK (m = 1..5)
Frequency [MHz]
Transmit
Clock
50
Direction
Reference Clock is used
Clock Signal Name
Frequency [MHz]
Receive
Clock
Direction
Reference Clock is used
Clock Signal Name
Frequency [MHz]
Table 8.6
Clock I/F for Ethernet PHY (Part 3)
9
10
11
12
RMII_10M_HALF_RO
RMII_10M_FULL_RO
RMII_100M_HALF_RO
RMII_100M_FULL_RO
No. & Mode Name
Clocks
Reference
Clock
Direction
Output to PHY
Clock Signal Name
RMII_REFCLK
Frequency [MHz]
Transmit
Clock
50
Direction
Reference Clock is used
Clock Signal Name
Frequency [MHz]
Receive
Clock
Direction
Reference Clock is used
Clock Signal Name
Frequency [MHz]
Table 8.7
Clock I/F for Ethernet PHY (Part 4)
13
14
RGMII_10M_HALF_RI
RGMII_10M_FULL_RI
No. & Mode Name
Clocks
Reference
Clock
Direction
Clock Signal Name
RGMII_100M_FULL_RI
125
Output to PHY
Clock Signal Name
GMII[m]_TXCLK (m = 1..5)
2.5
Direction
25
Input from PHY
Clock Signal Name
Frequency [MHz]
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RGMII_REFCLK
Direction
Frequency [MHz]
Receive
Clock
16
Input from external oscillator
Frequency [MHz]
Transmit
Clock
15
Rev.1.40
GMII[m]_RXCLK (m = 1..5)
2.5
25
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Table 8.8
Clock I/F for Ethernet PHY (Part 5)
17
18
RGMII_1G_HALF_RI
RGMII_1G_FULL_RI
No. & Mode Name
Clocks
Reference
Clock
Section 8 Ethernet Interface Modes
Direction
Input from external oscillator
Clock Signal Name
RGMII_REFCLK
Frequency [MHz]
Transmit
Clock
125
Direction
Output to PHY
Clock Signal Name
GMII[m]_TXCLK (m = 1..5)
Frequency [MHz]
Receive
Clock
125
Direction
Input from PHY
Clock Signal Name
GMII[m]_RXCLK (m = 1..5)
Frequency [MHz]
Table 8.9
125
Clock I/F for Ethernet PHY (Part 6)
19
20
21
22
RGMII_10M_HALF
RGMII_10M_FULL
RGMII_100M_HALF
RGMII_100M_FULL
No. & Mode Name
Clocks
Reference
Clock
Transmit
Clock
Direction
—
Clock Signal Name
—
Frequency [MHz]
—
Direction
Output to PHY
Clock Signal Name
GMII[m]_TXCLK (m = 1..5)
Frequency [MHz]
Receive
Clock
2.5
Direction
Clock Signal Name
GMII[m]_RXCLK (m = 1..5)
Frequency [MHz]
Table 8.10
No. & Mode Name
23
24
RGMII_1G_HALF
RGMII_1G_FULL
—
Clock Signal Name
—
Direction
Clock Signal Name
Direction
GMII[m]_TXCLK (m = 1..5)
125
Input from PHY
Clock Signal Name
Frequency [MHz]
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Output to PHY
Frequency [MHz]
Receive
Clock
25
Direction
Frequency [MHz]
Transmit
Clock
2.5
Clock I/F for Ethernet PHY (Part 7)
Clocks
Reference
Clock
25
Input from PHY
Rev.1.40
GMII[m]_RXCLK (m = 1..5)
125
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Table 8.11
Section 8 Ethernet Interface Modes
Support Modes for Each Module
Ethernet I/F Mode
Support Modes for Each Module
A5PSW Port A/B/C/D
No.
Mode Name
GMAC1/2
Store and
Forward/
Cut Through
1
MII_10M_HALF
Yes
Yes
No
No
No
No
2
MII_10M_FULL
Yes
Yes
No
No
No
No
3
MII_100M_HALF
Yes
Yes
No
No
No
No
4
MII_100M_FULL
Yes
Yes
No
Yes*2
Yes
Yes
5
RMII_10M_HALF_RI
Yes
Yes
No
No
No
No
6
RMII_10M_FULL_RI
Yes
Yes
No
No
No
No
7
RMII_100M_HALF_RI
Yes
Yes
No
No
No
No
8
RMII_100M_FULL_RI
Yes
Yes
No
Yes*
Yes
Yes
9
RMII_10M_HALF_RO
Yes
Yes
No
No
No
No
10
RMII_10M_FULL_RO
Yes
Yes
No
No
No
No
11
RMII_100M_HALF_RO
Yes
Yes
Yes
No
No
No
12
RMII_100M_FULL_RO
Yes
Yes
No
Yes
Yes
Yes
13
RGMII_10M_HALF_RI
Yes
Yes
No
No
No
No
14
RGMII_10M_FULL_RI
Yes
Yes
No
No
No
No
15
RGMII_100M_HALF_RI
Yes
Yes
No
No
No
No
16
RGMII_100M_FULL_RI
Yes
Yes
No
No
No
No
17
RGMII_1G_HALF_RI
Yes
No
No
No
No
No
18
RGMII_1G_FULL_RI
Yes
Yes
No
No
No
No
19
RGMII_10M_HALF
Yes
Yes
No
No
No
No
20
RGMII_10M_FULL
Yes
Yes
No
No
No
No
21
RGMII_100M_HALF
Yes
Yes
No
No
No
No
22
RGMII_100M_FULL
Yes
Yes
No
No
No
No
23
RGMII_1G_HALF
Yes
No
No
No
No
No
24
RGMII_1G_FULL
Yes
Yes
No
No
No
No
HUB Mode
ETHERCAT
Port A/B/C
SERCOSIII
Port A/B
HSR Port A/B
InterLink*1
3
Note 1.
Port InterLink is only supported when connected to external port (MODCTRL.SW_MODE[4:0] = 5’b11110).
Note 2.
Reference Clock of input GMII[m]_TXCLK (m = 3..5) must be synchronized to output clock of MII_REFCLK when ETHERCAT
is used.
Note 3.
Reference Clock of input GMII[m]_RXCLK (m = 3..5) must be synchronized to output clock of RMII_REFCLK when
ETHERCAT is used.
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8.2.1
Section 8 Ethernet Interface Modes
Internal Connection of Ethernet Ports
Internal connection of Ethernet ports are controlled by Mode Control register (MODCTRL) of Ethernet Accessory
Register as follows.
Table 8.12
Internal Connection of Ethernet Ports
Mode Control
Register
MODCTRL.
SW_MODE[4:0]
Internal Connection of Ethernet Ports
decimal
binary
HSR PORTI
INTERLINK
SWITCH
PORTIN
(A5PSW
Management
Port)
MII_CONV1
MII_CONV2
MII_CONV3
MII_CONV4
MII_CONV5
0
5’b00000
—
RTOS PORT
MAC1 PORT
SWITCH
PORTD
SWITCH
PORTC
SERCOS
PORTB
SERCOS
PORTA
1
5’b00001
—
RTOS PORT
MAC1 PORT
SWITCH
PORTD
SWITCH
PORTC
ETHERCAT
PORTB
ETHERCAT
PORTA
2
5’b00010
—
RTOS PORT
MAC1 PORT
SWITCH
PORTD
ETHERCAT
PORTC
ETHERCAT
PORTB
ETHERCAT
PORTA
3
5’b00011
—
RTOS PORT
MAC1 PORT
SWITCH
PORTD
SWITCH
PORTC
SWITCH
PORTB
SWITCH
PORTA
4 to 7
5’b00100 to
5’b00111
8
5’b01000
—
RTOS PORT
MAC1 PORT
MAC2 PORT
SWITCH
PORTC
SERCOS
PORTB
SERCOS
PORTA
9
5’b01001
—
RTOS PORT
MAC1 PORT
MAC2 PORT
SWITCH
PORTC
ETHERCAT
PORTB
ETHERCAT
PORTA
10
5’b01010
—
RTOS PORT
MAC1 PORT
MAC2 PORT
ETHERCAT
PORTC
ETHERCAT
PORTB
ETHERCAT
PORTA
11
5’b01011
—
RTOS PORT
MAC1 PORT
MAC2 PORT
SWITCH
PORTC
SWITCH
PORTB
SWITCH
PORTA
12 to 15
5’b01100 to
5’b01111
16
5’b10000
—
MAC2 PORT
MAC1 PORT
SWITCH
PORTD
SWITCH
PORTC
SERCOS
PORTB
SERCOS
PORTA
17
5’b10001
—
MAC2 PORT
MAC1 PORT
SWITCH
PORTD
SWITCH
PORTC
ETHERCAT
PORTB
ETHERCAT
PORTA
18
5’b10010
—
MAC2 PORT
MAC1 PORT
SWITCH
PORTD
ETHERCAT
PORTC
ETHERCAT
PORTB
ETHERCAT
PORTA
19
5’b10011
—
MAC2 PORT
MAC1 PORT
SWITCH
PORTD
SWITCH
PORTC
SWITCH
PORTB
SWITCH
PORTA
20 to 27
5’b10100 to
5’b11011
28
5’b11100
—
MAC2 PORT
MAC1 PORT
SWITCH
PORTD
SWITCH
PORTC
HSR PORTB
HSR PORTA
29
5’b11101
SWITCH
PORTA
MAC2 PORT
MAC1 PORT
SWITCH
PORTD
SWITCH
PORTC
HSR PORTB
HSR PORTA
30
5’b11110
MII_CONV3
MAC2 PORT
MAC1 PORT
SWITCH
PORTD
HSR PORTI
INTERLINK
HSR PORTB
HSR PORTA
31
5’b11111
MAC2 PORT
—
MAC1 PORT
—
—
HSR PORTB
HSR PORTA
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Reserved (Do not use)
Reserved (Do not use)
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8.2.2
Section 8 Ethernet Interface Modes
Selection of clocks for PTP
Clocks for PTP are selected by PTP Mode Control register (PTPMCTRL) of Ethernet Accessory Register.
“Table 8.13, Selection of Clocks for PTP” shows clock setting for each PTP and “Table 8.14, Recommended
Setting of PTP_MODE” shows the recommended value for MODCTRL.SW_MODE bits.
For the PTP function of each module, please refer to “Programming Guidelines for IEEE 1588 Timestamping” and
“Timestamping Functions (TSM)” in UM for R-IN Engine and Ethernet Peripherals.
GMAC1_PTP_TIMESTAMP_O[63:0]
GMAC1
GMAC2
GMAC2_
PTP_TIM
ESTAMP
_I[63:0]
Divi der
(1/8)
A5PS
W_TS
CLK
HSR
A5PSW_T
S_NS_IN
[31:0]*1*5
Timing slicer*3
(for 125 MHz)
From external pin
RGMII_REFCLK
(125 MHz)
Divi der
(1/40)
A5PSW
HSR_OVER
WRITE_TIM
E_I[79:0]*2*5
Timing slicer*3
(for 50 MHz)
Synchroni zer*4
(for 50 MHz)
25 MHz
125 MHz
GMAC_PTP_REFCLK_I
50 MHz
Divi der
(1/20)
1 GHz
PLL
Note 1.
Bit map for Advanced 5 port Switch is below.
A5PSW_TS_NS_IN[31:30] = 00b
A5PSW_TS_NS_IN[29:0] = GMAC1_PTP_TIMESTAMP_O[29:0]
Note 2.
Bit map for HSR is below.
HSR_OVERWRITE_TIME_I[79:64] = 0000h
HSR_OVERWRITE_TIME_I[63:32] = GMAC1_PTP_TIMESTAMP_O[63:32]
HSR_OVERWRITE_TIME_I[31:30] = 00b
HSR_OVERWRITE_TIME_I[29:0] = GMAC1_PTP_TIMESTAMP_O[29:0]
Note 3.
Timing slicer is a synchronous bridge to convert clock frequency.
Note 4.
Synchronizer is an asynchronous bridge to convert clock frequency.
Note 5.
In order to validate, release the reset by RSTN_CLK25 in PWRCTRL_SWITCHCTRL register.
Figure 8.2
Selection of Clocks for PTP by PTPMCTRL Register
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Table 8.13
Section 8 Ethernet Interface Modes
Selection of Clocks for PTP
GMAC1
PTPMCTRL.PTP_
GMAC_PTP_REFCLK_I
MODE[3:0]
GMAC2
A5PSW
GMAC_PTP_REFCLK_I
Clock for PTP
(A5PSW_TSCLK)
HSR
Timing
Slicer
Clock for PTP
Synchronizer
Timing
Slicer
O
4’b0000
Stop
Stop
Stop
Disable
Disable
Disable
Disable
A
4’b0001
RGMII_REFCLK
(125 MHz from external
pin)
RGMII_REFCLK
(125 MHz from external
pin)
RGMII_REFCLK
(125 MHz from external
pin)
Disable
50 MHz
(from PLL source)
Enable
Disable
B
4’b0010
125 MHz
(from PLL source)
125 MHz
(from PLL source)
125 MHz
(from PLL source)
Disable
50 MHz
(from PLL source)
Disable
Enable
C
4’b0011
50 MHz
(from PLL source)
50 MHz
(from PLL source)
125 MHz
(from PLL source)
Enable
50 MHz
(from PLL source)
Disable
Disable
D
4’b0100
25 MHz
(from PLL source)
25 MHz
(from PLL source)
125 MHz
(from PLL source)
Enable
50 MHz
(from PLL source)
Disable
Enable
Table 8.14
Recommended Setting of PTP_MODE
Mode Control Register
PTP Mode Control Register
Recommended Value of PTPMCTRL.PTP_MODE[3:0]
When High-Accuracy is required for PTP-Timer
MODCTRL.SW
_MODE[4:0]
When
when
When
RGMII_REFCLK is used
No RGMII_REFCLK is used
Low-Power is required for
(PTPMCTRL.RGMII_CLKSEL = 1) (PTPMCTRL.RGMII_CLKSEL = 0) PTP-Timer
decimal binary
When
No PTP-Timer is used
Symbol
Symbol
Symbol
Symbol
0
5’b00000
A
B
D
O
1
5’b00001
A
B
D
O
2
5’b00010
A
B
D
O
3
5’b00011
A
B
D
O
4 to 7
5’b00100 to
5’b00111
8
5’b01000
A
B
D
O
9
5’b01001
A
B
D
O
10
5’b01010
A
B
D
O
11
5’b01011
A
B
D
O
Reserved (Do not set)
12 to 15 5’b01100 to
5’b01111
Reserved (Do not set)
16
5’b10000
A
B
D
O
17
5’b10001
A
B
D
O
18
5’b10010
A
B
D
O
19
5’b10011
A
B
D
O
20 to 27 5’b10100 to
5’b11011
Reserved (Do not set)
28
5’b11100
B
B
C
O
29
5’b11101
B
B
C
O
30
5’b11110
B
B
C
O
31
5’b11111
B
B
C
O
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8.3
8.3.1
Section 8 Ethernet Interface Modes
Operation
Initializing
Example sequence for using Ethernet is shown as below.
Ethernet initialization start
NoC connect on R-IN Engine
Accessory Register
NoC Connect on Ethernet
Accessory Register
PWRCTRL_RINCTRL and
PWRSTAT_RINCTRL registers
PWRCTRL_SWITCHCTRL and
PWRSTAT_SWITCHCTRL registers
IO Multiplexing Configuration
Ether Mode setting
(See ETHMODE_SET section)
Ethernet Accessory register
Each Ethernet module setting
De-assert Ethernet/CLK25 Reset
De-assert reset of “RSTN_ETH” and “RSTN_CLK25"
in PWRCTRL_SWITCHCTRL register
Ethernet initialization end
Figure 8.3
Initializing of Ethernet Flowchart
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8.3.2
Section 8 Ethernet Interface Modes
ETHMODE_SET
For ETHMODE_SET operation, complete the following flowchart:
ETHMODE SET START
Ethernet Protect Permit Write
Access (PRCMD)
Mode Control Setting
(MODCTRL)
PTP Mode Control Setting
(PTPMCTRL)
EthernetPHY Link Mode Setting
(PHYLNK)
Set RGMII/RMII Converter[m] *1
(CONVCTRL[m])
(m=1..5)
Release CONVRST.PHYIF_RSTn
Ethernet Protect Prohibit Write
Access (PRCMD)
ETHMODE SET END
Note:
Note 1.
See Register Description in Ethernet Accessory Register.
If ethernet port1 is not used, set RGMII/RMII Converter1 = 0000_0115h. Without this setting, PTP circuit doesn’t work.
For example, RZ/N1D-324 doesn’t have the port1, therefore this setting is essential.
Figure 8.4
ETHMODE_SET Flowchart
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8.4
Section 8 Ethernet Interface Modes
Usage Notes
8.4.1
Restriction
● SERCOSIII, ETHERCAT and HSR function are not available simultaneously.
● HW-RTOS GMAC and HSR are not available simultaneously.
● HSR is available only in RZ/N1D.
● RZ/N1D-324 can only use port3, port4, and port5.
● RZ/N1S-196 and RZ/N1L can only use port1, port4, and port5.
8.4.1.1
Supported Ethernet Signals
Table 8.15
Ethernet Signals for Each PHY Mode
Signal Name
MII Mode
RMII Mode
RGMII Mode
Remark
GMII[m]_TXCLK
TX_CLK
Not use
TXC
GMII[m]_TXD0
TXD0
TXD0
TXD0
GMII[m]_TXD1
TXD1
TXD1
TXD1
GMII[m]_TXD2
TXD2
Not use
TXD2
GMII[m]_TXD3
TXD3
Not use
TXD3
GMII[m]_TXEN
TX_EN
TX_EN
TX_CTL
GMII[m]_TXER
TX_ER
Not use
Not use
GMII[m]_RXCLK
RX_CLK
REF_CLK
RXC
GMII[m]_RXD0
RXD0
RXD0
RXD0
GMII[m]_RXD1
RXD1
RXD1
RXD1
GMII[m]_RXD2
RXD2
Not use
RXD2
GMII[m]_RXD3
RXD3
Not use
RXD3
GMII[m]_RXDV
RX_DV
CRS_DV
RX_CTL
GMII[m]_RXER
RX_ER
RX_ER (option)
Not use
Port1 of RZ/N1S-196 and RZ/N1L doesn’t have it.
GMII[m]_CRS
CRS
Not use
Not use
Port1 of RZ/N1S-196 and RZ/N1L doesn’t have it.
GMII[m]_COL
COL
Not use
Not use
Port1 of RZ/N1S-196 and RZ/N1L doesn’t have it.
Port1 of RZ/N1S-196 and RZ/N1L doesn’t have it.
Note: m = 1..5.
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Section 9
9.1
Section 9 Interrupts
Interrupts
Overview
RZ/N1 has Cortex-A7 GICv2 and Cortex-M3 NVIC as an interrupt controller.
9.1.1
Cortex-A7 GICv2
The GIC collates and arbitrates from a large number of interrupt sources. It provides:
● Masking of interrupts
● Prioritization of interrupts
● Distribution of the interrupts to the target processors nIRQ and nFIQ
● Tracking the status of interrupts
● Generation of interrupts by software
● Support for Security Extensions
● Support for Virtualization Extensions
● Support for 160 standard interrupt sources
● The GIC is compliant with the version 2.0 of the Arm Generic Interrupt Controller (GIC) Architecture Specification
Please refer to “CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual” on Arm website.
9.1.2
Cortex-M3 NVIC
The NVIC main features are listed below:
● Masking of interrupts
● Prioritization of interrupts
● Generation of interrupts by software
● Facilitates low latency interrupt (The NVIC and the processor core interface are closely coupled). The NVIC
maintains knowledge of the stacked (nested) interrupts to enable multiple interrupts
● Controls power management
● Support for 240 standard interrupt sources with up to 256 levels of priority
● NMI Interrupt controlled from external IO
Please refer to “Cortex-M3 Technical Reference Manual” on Arm website.
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9.2
Section 9 Interrupts
Operation
9.2.1
IRQ Synchronization
RZ/N1 System Controller receives all the IRQ signals from all sources and it delivers to Cortex-A7 GIC, Cortex-M3
NVIC and to HW-RTOS. The following IRQ handling categories are differentiated.
− Cortex-A7 GIC has synchronization logic.
− RZ/N1 System Controller has a synchronization logic for Cortex-M3 and HW-RTOS on all interrupt. Therefore,
Cortex-M3 and HW-RTOS receives synchronized interrupt signals.
− Ethernet peripherals share certain interrupt (IRQ 49..52) the combination of these IRQs
9.2.2
Non Maskable Interrupt
The Cortex-M3 CPU has a non-maskable interrupt input. This interrupt is able to be assigned to external pin by the IO
multiplexing.
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9.2.3
Section 9 Interrupts
Interrupt Management on Cortex-A7 and Cortex-M3
Cortex-A7
processor0
nIRQ
Cortex-A7
processor1
nFIQ
nIRQ
nFIQ
Generic
Interrupt
Controller
(GICv2)
Peripheral_Int[x]
nIRQ[1:0] set to 1
nFIQ[1:0] set to 1
Peripheral_Int[y]
UARTs
Peripheral_Int[x]
Peripheral_Int[z]
SPIs
Peripheral_Int[y]
LCD
Peripheral_Int[z]
Peripheral_Int[..]
XXX
Peripheral_Int[..]
Nested
Vectored
Interrupt
Controller
(NVIC)
nIRQ
Cortex-M3
NMI_CORTEXM3
(External port)
Figure 9.1
Interrupt Management on Cortex-A7 and Cortex-M3
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9.2.4
Section 9 Interrupts
Interrupts Allocation and Vector Number
Table 9.1
Interrupts Allocation and Vector Number (1/4)
N1D
N1S
N1L
IRQ
[Index]
IRQ
0
ADC_Int
ADC interrupt
1
I2C1_Int
I2C1 interrupt
2
I2C2_Int
I2C2 interrupt
3
Reserved
—
—
—
—
—
Reserved
4
Reserved
—
—
—
—
—
Reserved
5
Reserved
—
—
—
—
—
Reserved
6
UART1_Int
UART1 interrupt
7
UART2_Int
UART2 interrupt
8
UART3_Int
UART3 interrupt
9
Reserved
—
—
—
—
—
Reserved
10
PWM_Int
PWMTimer interrupt
11
ECC_4MB_Int
—
—
ECC error detected and not corrected on 4MB SRAM
12
ECC_2MB_Int
ECC error detected and not corrected on 2MB SRAM
13
CM3_LOCKUP_Int
—
—
—
Cortex-M3 lockup
14
CM3_TRING_Int[0]
—
Trigger Interrupt0 (Cross Trigger Interface for Cortex-M3)
15
CM3_TRING_Int[1]
—
Trigger Interrupt1 (Cross Trigger Interface for Cortex-M3)
16
HWRTOS_BRAMERR_Int
—
—
HW-RTOS GMAC Buffer RAM area access error
17
HWRTOS_BUFDMA_Int
—
—
HW-RTOS GMAC InterBuffer DMA transfer completion
18
HWRTOS_BUFDMAERR_Int
—
—
HW-RTOS GMAC InterBuffer DMA error
19
HWRTOS_ETHMMAI_Int
—
—
HW-RTOS GMAC MII management access completion
interrupt
20
HWRTOS_ETHPPIT_Int
—
—
HW-RTOS GMAC pause packet transmission completion
21
HWRTOS_ETHDRIE_Int
—
—
HW-RTOS GMAC MACDMA reception error
22
HWRTOS_ETHDMAIR_Int
—
—
HW-RTOS GMAC MACDMA reception completion
23
HWRTOS_ETHRFE_Int
—
—
HW-RTOS GMAC MACDMA error frame reception
completion
24
HWRTOS_ETHRFIV_Int
—
—
HW-RTOS GMAC RX FIFO overflow
25
HWRTOS_ETHIT_Int
—
—
HW-RTOS GMAC transmission completion interrupt
26
HWRTOS_ETHDTIE_Int
—
—
HW-RTOS GMAC MACDMA transmission error
27
HWRTOS_ETHDMAIT_Int
—
—
HW-RTOS GMAC MACDMA transmission completion
28
HWRTOS_ETHTFIU_Int
—
—
HW-RTOS GMAC TX FIFO underflow
29
HWRTOS_ETHTFIE_Int
—
—
HW-RTOS GMAC TX FIFO error interrupt
30
HWRTOS_Int
—
—
HW-RTOS interrupt
31
HWRTOS_ETHRFI_Int
—
—
HW-RTOS GMAC MACDMA valid frame reception
completion
32
Reserved
—
—
—
—
—
Reserved
33
Reserved
—
—
—
—
—
Reserved
34
GMAC1_SBD_Int
GMAC1 general
35
GMAC1_LPI_Int
GMAC1 energy efficient
36
GMAC1_PMT_Int
GMAC1 power management
37
GMAC2_SBD_Int
GMAC2 general
38
GMAC2_LPI_Int
GMAC2 energy efficient
39
GMAC2_PMT_Int
GMAC2 power management
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Table 9.1
Section 9 Interrupts
Interrupts Allocation and Vector Number (2/4)
N1D
N1S
N1L
IRQ
[Index]
IRQ
40
A5PSW_DLR_Int
41
Reserved
—
—
—
—
—
Reserved
42
A5PSW_Int
A5PSW
43
A5PSW_PRP_Int
—
A5PSW – PRP interrupt
44
A5PSW_HUB_Int
A5PSW – integrated Hub module
45
A5PSW_PTRN_Int
A5PSW – RX Pattern Matcher
46
ETHCAT_RST_Int
ETHERCAT Reset interrupt
47
ETHCAT_SYNC_Int[0]
ETHERCAT Sync0 interrupt
48
ETHCAT_SYNC_Int[1]
ETHERCAT Sync1 interrupt
49
ETHCAT_WDT_Int
OR’ed between ETHERCAT, SERCOSIII IRQs (Only 1
module is used exclusively)
CA7 CM3 CA7 CM3 CM3 Description
SERCOS3_DIVCLK_Int
A5PSW – DLR interrupt
ETHERCAT: WDT interrupt
SERCOSIII: Divided communication clock out
50
ETHCAT_EOF_Int
SERCOS3_CONCLK_Int
OR’ed between ETHERCAT, SERCOSIII and HSR IRQs
(Only 1 module is used exclusively)
ETHERCAT: EOF interrupt
HSR_PTP_I_IRQ
SERCOSIII: Communication synchronized control clock
output
HSR: PTP interface interrupt
51
ETHCAT_SOF_Int
SERCOS3_Int[0]
OR’ed between ETHERCAT, SERCOSIII and HSR IRQs
(Only 1 module is used exclusively)
ETHERCAT: SOF interrupt
HSR_CPU_I_IRQ
SERCOSIII: Port1 interrupt
HSR: CPU interface interrupt
52
ETHCAT_Int
SERCOS3_Int[1]
Multiplexing between ETHERCAT, SERCOSIII IRQs
(depending on active module)
ETHERCAT interrupt
SERCOSIII: Port2 interrupt
53
Reserved
—
—
—
—
—
Reserved
54
Reserved
—
—
—
—
—
Reserved
55
Reserved
—
—
—
—
—
Reserved
56
DMA1_Int
DMAC1 interrupt
57
DMA2_Int
DMAC2 interrupt
58
NAND_Int
NAND Flash Controller interrupt
59
IPCM_Int[0]
—
Mailbox interrupt0
60
IPCM_Int[1]
—
Mailbox interrupt1
61
IPCM_Int[2]
—
Mailbox interrupt2
62
Reserved
—
—
—
—
—
Reserved
63
MSEBIS_Int
MSEBI Slave bus interrupt
64
QSPI1_Int
QuadSPI1 interrupt
65
QSPI2_Int
—
—
—
QuadSPI2 interrupt
66
RTCATINTAL_Int
—
—
—
RTC (Alarm interrupt)
67
RTCATINTR_Int
—
—
—
RTC (Fixed period interrupt)
68
RTCATINT1S_Int
—
—
—
RTC (1 second interrupt)
69
SDIF1_Int
SDIO/SD/eMMC 1 interrupt
70
SDIF1_wkup_Int
SDIO/SD/eMMC 1 wakeup
71
SDIF2_Int
SDIO/SD/eMMC 2 interrupt
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Table 9.1
Section 9 Interrupts
Interrupts Allocation and Vector Number (3/4)
N1D
N1S
IRQ
[Index]
IRQ
72
SDIF2_wkup_Int
73
WDT_CA7_p0_reset_Int
74
WDT_CA7_p1_reset_Int
75
WDT_CM3_reset_Int
76
DDRC_Int
—
77
USB2F_EPC_Int
78
USB2F_Int
79
USB2H_BIND_Int
80
SPI1_Int
81
SPI2_Int
82
SPI3_Int
83
84
N1L
CA7 CM3 CA7 CM3 CM3 Description
SDIO/SD/eMMC 2 wakeup
—
Watchdog timer for CA7 processor0
—
—
—
Watchdog timer for CA7 processor1
Watchdog timer for CM3
—
—
DDR Controller
USB Function
USB Function
USB Host
SPI1 Master interrupt
SPI2 Master interrupt
SPI3 Master interrupt
SPI4_Int
SPI4 Master interrupt
SPI5_Int
SPI5 Slave interrupt
85
SPI6_Int
SPI6 Slave interrupt
86
UART4_Int
UART4 interrupt
87
UART5_Int
UART5 interrupt
88
UART6_Int
UART6 interrupt
89
UART7_Int
UART7 interrupt
90
UART8_Int
UART8 interrupt
91
Reserved
—
—
—
—
—
Reserved
92
Reserved
—
—
—
—
—
Reserved
93
Reserved
—
—
—
—
—
Reserved
94
Reserved
—
—
—
—
—
Reserved
95
CAN1_Int
CAN1
96
CAN2_Int
CAN2
97
LCDC_Int
—
LCD Controller interrupt
98
Reserved
—
—
—
—
—
Reserved
99
Reserved
—
—
—
—
—
Reserved
100
Reserved
—
—
—
—
—
Reserved
101
Reserved
—
—
—
—
—
Reserved
102
Reserved
—
—
—
—
—
Reserved
103
GPIO_Int[0]
Multiplexed from 32*3 interrupt sources (BGPIO1,2,3)*1
104
GPIO_Int[1]
Multiplexed from 32*3 interrupt sources (BGPIO1,2,3)*1
105
GPIO_Int[2]
Multiplexed from 32*3 interrupt sources (BGPIO1,2,3)*1
106
GPIO_Int[3]
Multiplexed from 32*3 interrupt sources (BGPIO1,2,3)*1
107
GPIO_Int[4]
Multiplexed from 32*3 interrupt sources (BGPIO1,2,3)*1
108
GPIO_Int[5]
Multiplexed from 32*3 interrupt sources (BGPIO1,2,3)*1
109
GPIO_Int[6]
Multiplexed from 32*3 interrupt sources (BGPIO1,2,3)*1
110
GPIO_Int[7]
Multiplexed from 32*3 interrupt sources (BGPIO1,2,3)*1
111
Reserved
—
—
—
—
—
Reserved
112
TIMER1_Int[0]
TIMER1, Sub Timer0 interrupt
113
TIMER1_Int[1]
TIMER1, Sub Timer1 interrupt
114
TIMER1_Int[2]
TIMER1, Sub Timer2 interrupt
115
TIMER1_Int[3]
TIMER1, Sub Timer3 interrupt
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Table 9.1
Section 9 Interrupts
Interrupts Allocation and Vector Number (4/4)
N1D
N1S
N1L
IRQ
[Index]
IRQ
116
TIMER1_Int[4]
TIMER1, Sub Timer4 interrupt
117
TIMER1_Int[5]
TIMER1, Sub Timer5 interrupt
118
TIMER1_Int[6]
TIMER1, Sub Timer6 interrupt
119
TIMER1_Int[7]
TIMER1, Sub Timer7 interrupt
120
TIMER2_Int[0]
TIMER2, Sub Timer0 interrupt
121
TIMER2_Int[1]
TIMER2, Sub Timer1 interrupt
122
TIMER2_Int[2]
TIMER2, Sub Timer2 interrupt
123
TIMER2_Int[3]
TIMER2, Sub Timer3 interrupt
124
TIMER2_Int[4]
TIMER2, Sub Timer4 interrupt
125
TIMER2_Int[5]
TIMER2, Sub Timer5 interrupt
126
TIMER2_Int[6]
TIMER2, Sub Timer6 interrupt
127
TIMER2_Int[7]
TIMER2, Sub Timer7 interrupt
128 …
154
Reserved
—
—
—
—
—
Reserved
155
AXIERR_IRQ
—
—
—
External memory errors on cacheable writes Interrupt
156-239
Reserved
n/a
—
n/a
—
—
Reserved
Note 1.
CA7 CM3 CA7 CM3 CM3 Description
Select from the interrupt source of BGPIO [m] _Int [31: 0] (m = 1, 2, 3) by rGPIOs_Level 2 _Gpio_Int_ [n] (n = 0..7)
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RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 10
10.1
Section 10 IOs
IOs
Pinout Description
Table 10.1
PKG Power Supply Pin Name
Classification
PKG Pin Name
Power
Description
Power supply
VDD11
(VDD11)
Power supply pin for Internal logic
GND
—
Ground pin
VDD33
(VDD33)
Power supply pin for I/O pin other than GPIO59 to GPIO0
RGMII1_VDDQ
(VRGMII)
Power supply pin for GPIO11 to GPIO0
VDD11_CA7
PLL Power supply
USB Power supply
RGMII2_VDDQ
Power supply pin for GPIO23 to GPIO12
RGMII3_VDDQ
Power supply pin for GPIO35 to GPIO24
RGMII4_VDDQ
Power supply pin for GPIO47 to GPIO36
RGMII5_VDDQ
Power supply pin for GPIO59 to GPIO48
PLL_AVDD
(VPLL)
Power supply pin for PLL
PLL_AGND
—
Ground pin for PLL
USB_VD33
(VUSB)
Power supply pin for USB PHY
USB_GND
—
Ground pin for USB PHY
USB_AVDD
(VUSB)
Analog power supply pin for USB PHY
USB_AVSS
—
Analog ground pin for USB PHY
RTC Power supply
RTC_VDD33
(VRTC)
Power supply pin for RTC
ADC Power supply
ADC1_AVDD
(VADC)
Power supply pin for ADC1
ADC1_AGND
—
Ground pin for ADC1
ADC2_AVDD
(VADC)
Power supply pin for ADC2
ADC2_AGND
—
Ground pin for ADC2
OTP Power supply
ANF_VDD_PRG
(VANFPRG)
OTP memory programming voltage input pin
DDR PHY Power
supply
DVDD
(VDVDD)
Power supply pin for DDR PHY Core and PLL
DVDDQ
(VDVDDQ)
Power supply pin for DDR PHY I/O
DVSS
—
Ground pin for DDR PHY
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Table 10.2
Section 10 IOs
PKG Pin Name (1/2)
Classification
PKG Pin Name
IO
Active Power
Description
Clock
MCLK_XO
I/O
—
MCLK_XI
Input
—
Connected to a crystal resonator. And external clock signal
may also be input to the MCLK_XO pin.
RTC_XO
Output
—
RTC_XI
Input
—
Input
—
Operating mode CONFIG[1:0]
control
VDD33
Connected to a crystal resonator
Debugging interface mode control pins
2’b00: Arm-JTAG/SWD (CoreSight)
2’b10: Boundary Scan (JTAG-TAP Controller)
Others: Reserved
These pins have internal pull-down resistor (RPUUD).
CONFIG2
Input
—
Reserved configuration pin. Should be 1.
TMC[2:1]
Input
—
Production test pins. Should be 2’b00.
CTRSTBYB
Input
High
IO Buffer enable pin, Schmitt input
0: IO Buffer Disable (Output: Hi-Z)
1: IO Buffer Enable
Please refer to “Power-up/down Sequence”
This pin has internal pull-up resistor (RPUUD).
System control
MRESET_N
Input
Low
Master reset signal input pin, Schmitt input
MRESET_OUT
Output
High
Master reset signal output pin. Output 1 during
MRESET_N=0 or System Reset.
THMODE
Input
—
Main clock input mode select pin.
This pin has internal pull-down resistor (RPUUD).
Debugging
interface
DDR2/3
interface
JTAG_TRST_N
Input
Low
CoreSight or boundary scan pins.
JTAG_TMS
I/O
—
These pins have internal pull-up/down resistor (RPUUD):
JTAG_TDI
Input
—
JTAG_TRST_N, JTAG_TMS, JTAG_TDI, and JTAG_TDO:
pull-up
JTAG_TDO
Output
—
JTAG_TCK
Input
—
DDR_CLKP
Output
—
DDR_CLKN
Output
—
CLKP – CK for DDR, CLKN -- /CK for DDR
DDR_CLKEN
Output
High
Clock enable signal
DDR_RESET_N
Output
JTAG_TCK: pull-down
DVDDQ
Differential clock output pins
Low
Reset signal for DDR3-SDRAM
DDR_ADDR[15:0] Output
—
Address bus
DDR_BA[2:0]
Output
—
Bank address
DDR_DQ[15:0]
I/O
—
Data bus
DDR_DM1
DDR_DM0
Output
High
Data mask signal
DDR_DQS1
DDR_DQS0
I/O
—
Differential bidirectional data strobe
DDR_DQS_N1
DDR_DQS_N0
I/O
—
DQS_N[n] -- /DQS for DDR
DDR_WE
Output
Low
/WE for DDR
DDR_RAS
Output
Low
/RAS for DDR
DDR_CAS
Output
Low
/CAS for DDR
DDR_CS1
Output
Low
Chip Select
Output
High
ODT Control
DQS[n] -- DQS for DDR
DDR_CS0
DDR_ODT1
DDR_ODT0
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Table 10.2
Section 10 IOs
PKG Pin Name (2/2)
Classification
PKG Pin Name
IO
Active Power
Description
DDR2/3
interface
DDR_MZQ
I/O
—
External Reference resistance connection pin for the output
impedance control
—
DDR2: should be connected to GND via 150Ω ±1%
DDR3: should be connected to GND via 120Ω ±1%
USB interface
DDR_VREF
Input
—
(VDDR REF)
Reference voltage input pin
USB_RREF
Input
—
—
Reference current generation pin
RZ/N1D: should be connected to GND via 1.6kΩ ±1%
RZ/N1S, N1L: should be connected to GND via 2.2kΩ ±1%
USB_VBUS
Input
—
USB_DP1
I/O
—
USB_DM1
I/O
—
USB_DP2
I/O
—
USB_DM2
I/O
—
ADC1_VREFP
Input
—
(VADC REFP)
ADC1_VREFN
Input
—
(VADC REFM)
ADC1_IN[n]
Input
—
ADC1_AVDD
Analog input pins for ADC1 n = 0..4, 6..8
ADC2_VREFP
Input
—
(VADC REFP)
Reference voltage input pins
ADC2_VREFN
Input
—
(VADC REFM)
ADC2_IN[n]
Input
—
ADC2_AVDD
Analog input pins for ADC2 n = 0..4, 6..8
Real Time
Clock (RTC)
RTC_PWRGOOD Input
—
RTC_VDD33
RTC backup mode control pin
GPIO
GPIO[n]
AD Converter
USB_VD33
Port power detection pin for USB Function, Schmitt input
USB High Speed D ±signal (Port1)
USB High Speed D ±signal (Port2)
Reference voltage input pins
0: Backup
1: Normal
I/O
—
RGMII1_VDDQ
n = 0..11
RGMII2_VDDQ
n = 12..23
RGMII3_VDDQ
n = 24..35
RGMII4_VDDQ
n = 36..47
RGMII5_VDDQ
n = 48..59
VDD33
n = 60..169 (max)
GPIO75..79, 83 are also used in External Pin Configuration.
Detail of this function is described in Section 7.3.2,
External Pin Configuration.
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Table 10.3
Section 10 IOs
GPIO Multiplexed Pin Name (1/3)
Classification
IOMuxed Signal Name
IO
Active Level Description
Ethernet
RGMII/RMII/MII
GMII[m]_TXCLK
I/O
—
TX clock m = 1..5
GMII[m]_TXD[3:0]
Output
—
TX data m = 1..5
GMII[m]_TXEN
Output
High
TX data enable m = 1..5
GMII[m]_TXER
Output
High
TX data error m = 1..5
GMII[m]_RXCLK
Input
—
RX clock m = 1..5
GMII[m]_RXD[3:0]
Output
—
RX data m = 1..5
GMII[m]_RXDV
Input
High
RX data enable m = 1..5
GMII[m]_RXER
Input
High
RX data error m = 1..5
GMII[m]_CRS
Input
High
Carrier detection m = 1..5
GMII[m]_COL
Input
High
Collision detection m = 1..5
RGMII_REFCLK
Input
—
125 MHz input for RGMII
RMII_REFCLK
Output
—
50 MHz output for RMII
MII_REFCLK_[5:0]
Output
—
25 MHz output for MII
FNAND_CE_N[3:0]
Output
Low
Chip Enable
FNAND_IO[7:0]
I/O
—
Data
FNAND_CLE
Output
High
Command Latch Enable
FNAND_ALE
Output
High
Address Latch Enable
FNAND_RE_N
Output
Low
Read Enable
FNAND_WE_N
Output
Low
Write Enable
FNAND_WP_N[3:0]
Output
Low
Write Protect/Reset
FNAND_RY/BY_N[3:0]
Input
—
Ready/Busy
QUAD[m]_CLK
Output
—
Clock m = 1..2
QUAD[m]_IO[3:0]
I/O
—
Data m = 1..2
NAND Flash
QSPI
SD/MMC/SDIO
LCD
QUAD[m]_CS_N[3:0]
Output
Low
Slave selection m = 1..2
SDIO[m]_CLK
Output
—
Clock m = 1..2
SDIO[m]_CMD
I/O
—
Command/response m = 1..2
SDIO[m]_IO[7:0]
I/O
—
Data m = 1..2
SDIO[m]_CD_N
Input
Low
Card Detection m = 1..2
SDIO[m]_WP
Input
High
SD Card Write Protect m = 1..2
SDIO[m]_LEDCTRL
Output
High
LED control m = 1..2
LCD_PCLK
Output
—
Pixel Clock
LCD_HSYNC
Output
Selectable
Horizontal Sync Pulse
LCD_VSYNC
Output
Selectable
Vertical Sync Pulse
LCD_DE
Output
Selectable
Data Enable
LCD_PE
Output
High
Power Enable
LCD_PWM[n]
Output
—
LCD LED Pulse Width Modulation n = 0..1
LCD_R[7:0]
Output
—
Red Data
LCD_G[7:0]
Output
—
Green Data
LCD_B[7:0]
Output
—
Blue Data
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Table 10.3
Section 10 IOs
GPIO Multiplexed Pin Name (2/3)
Classification
IOMuxed Signal Name
IO
Active Level Description
MSEBI Master
MSEBIM_ACD[31:0]
I/O
—
Address, Control and Data multiplexed
MSEBIM_ALE
Output
High
Address Latch Enable
MSEBIM_ALE1
Output
High
Address Latch Enable for parallel mode
MSEBIM_ALE2
Output
High
Address Latch Enable for parallel mode
MSEBIM_ALE3
Output
High
Address Latch Enable for parallel mode
MSEBIM_CLE
Output
High
Address and Control Latch Enable
MSEBIM_DLE
Output
High
Data Latch Enable
MSEBIM_WR_N
Output
Low
Write enable
MSEBIM_RD_N
Output
Low
Read enable
MSEBIM_CLK
Output
—
Clock
MSEBI Slave
MSEBIM_WAIT_N[3:0]
Input
Low
Wait Request input
MSEBIM_DMA_RD_N[1:0]
Input
Low
DMA Read Request
MSEBIM_DMA_WR_N[1:0]
Input
Low
DMA Write Request
MSEBIS_ACD[31:0]
I/O
—
Address, Control and Data multiplexed
MSEBIS_ALE
Input
High
Address Latch Enable
MSEBIS_CLE
Input
High
Address and Control Latch Enable
MSEBIS_DLE
Input
High
Data Latch Enable
MSEBIS_CLK
Input
—
Clock
MSEBIS_WAIT_N[3:0]
Output
Low
Wait Request output
MSEBIS_DMA_RD_N[1:0]
Output
Low
DMA Read Request
MSEBIS_DMA_WR_N[1:0]
Output
Low
DMA Write Request
Cortex-M3
NMI_CORTEXM3
Input
High
Non-maskable Interrupt for Cortex-M3
ETHERCAT
CAT_LEDRUN
Output
High
RUN LED
CAT_LEDSTER
Output
High
Dual-color State LED
CAT_LEDERR
Output
High
Error LED
CAT_LINKACT[n]
Output
High
link / Activity LED n = 0..2
SERCOSIII
GMAC/A5PSW
CAT_SYNC[n]
Output
High
SYNC n = 0..1
CAT_LATCH[n]
Input
Both edge
LATCH n = 0..1
CAT_MII_LINK[n]
Input
Selectable
Link status from PHY n = 0..2
CAT_RESETOUT_N
Output
Low
RESET OUT
CAT_I2CCLK
Output
—
EEPROM I2C clock
CAT_I2CDATA
I/O
—
EEPROM I2C data
S3_LED_GN
Output
High
LED (green)
S3_LED_RD
Output
High
LED (red)
S3_ACTLEDP[m]
Output
High
activity LED m = 1..2
S3_LINKLEDP[m]
Output
High
link LED m = 1..2
S3_CONCLK
Output
—
Communication synchronized control clock output
S3_DIVCLK
Output
—
Divided communication clock out
S3_MII_LINKP[m]
Input
Selectable
Link status from PHY m = 1..2
S3_PHY_RESET_N
Output
Low
PHY RESET
S3_TESTPIN[m]
Output
—
test signal output by DBGOCR m = 1..2
MAC_PPS[n]
Output
High
GMAC1 Pulse Per Second output n = 0..1
MAC_TRIG[m]
Input
Rise Edge
GMAC[m] Auxiliary Timestamp Trigger Input m = 1..2
SWITCH_MII_LINK[m]
Input
Selectable
A5PSW Link status from PHY m = 2..5
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Table 10.3
Section 10 IOs
GPIO Multiplexed Pin Name (3/3)
Classification
IOMuxed Signal Name
IO
Active Level Description
MDIO
MDC[m]
Output
—
Management data clock m = 1..2
MDIO[m]
I/O
—
Management data I/O m = 1..2
USB_OC[m]
Input
Low
Overcurrent status for USB Host m = 1..2
USB_PPON[m]
Output
High
Port Power control for USB Host m = 1..2
UART[m]_RXD
Input
—
Receive data m = 1..8
UART[m]_TXD
Output
—
Transmit data m = 1..8
UART[m]_CTS_N
Input
Low
Clear To Send Modem Status m = 1..8
UART[m]_DSR_N
Input
Low
Data Set Ready Modem Status m = 1..8
UART[m]_DCD_N
Input
Low
Data Carrier Detect Modem Status m = 1..8
UART[m]_RI_N
Input
Low
Ring Indicator Modem Status m = 1..8
UART[m]_DTR_N
Output
Low
Modem Control Data Terminal Ready m = 1..8
UART[m]_RTS_N
Output
Low
Modem Control Request To Send m = 1..8
SPI[m]_CLK
Output
—
Clock m = 1..4
SPI[m]_MOSI
Output
—
Master transmit data m = 1..4
SPI[m]_MISO
Input
—
Slave transmit data m = 1..4
SPI[m]_SS_N[n]
Output
Low
Slave selection m = 1..4, n = 0..3
SPI[m]_CLK
Input
—
Clock m = 5..6
SPI[m]_MOSI
Input
—
Master transmit data m = 5..6
SPI[m]_MISO
Output
—
Slave transmit data m = 5..6
SPI[m]_SS_N
Input
Low
Slave selection m = 5..6
BGPIO[m]A[n]
I/O
—
Basic GPIO[m] port A m = 1..3, n = 0..31
BGPIO[m]B[n]
I/O
—
Basic GPIO[m] port B m = 1..3, n = 0..31
CAN[m]_RXD
Input
—
Receive data m = 1..2
CAN[m]_TXD
Output
—
Transmit data m = 1..2
I2C[m]_SCL
I/O
—
Serial clock m = 1..2
I2C[m]_SDA
I/O
—
Serial data m = 1..2
USB
UART
SPI Master
SPI Slave
BGPIO
CAN
I2C
PWMTimer
PWM_IN[n]
Input
—
Input pins n = 0..39
PWM_OUT[n]
Output
—
Output pins n = 0..19
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10.2
Section 10 IOs
Handling of Unused Pins
Table 10.4
Handling of Unused Pins
Pin Name
Handling
USB_VD33
Connect this pin to VDD33
USB_GND
GND
USB_AVDD
Connect this pin to VDD33
USB_AVSS
GND
RTC_VDD33
Connect this pin to VDD33
ADC1_AVDD
Connect this pin to VDD33
ADC1_AGND
GND
ADC2_AVDD
Connect this pin to VDD33
ADC2_AGND
GND
MCLK_XI
GND
RTC_XO
Open
RTC_XI
GND
MRESET_OUT
Open
JTAG_TRST_N
Open or 4.7kΩ pull-down
JTAG_TMS
Open or 4.7kΩ pull-up
JTAG_TDI
Open or 4.7kΩ pull-up
JTAG_TDO
Open
JTAG_TCK
Open or 4.7kΩ pull-up or pull-down
USB_RREF
Same as used case. Refer to NOTES 2.
USB_VBUS
10kΩ pull-down
USB_DP1
10kΩ pull-down
USB_DM1
USB_DP2
10kΩ pull-down
USB_DM2
ADC1_VREFP
Open
ADC1_VREFN
ADC1_IN[n]
Open
ADC2_VREFP
Open
ADC2_VREFN
ADC2_IN[n]
Open
RTC_PWRGOOD
Connect this pin to VDD33
ANF_VDD_PRG
GND
GPIO[n]
n = 0..169 (max)
[Mode Config] Level1 function: floating (default) and pull-up (default) / down
NOTES
1.
ADC should be set to power down mode when ADC is not used.
2.
USB_RREF needs reference resister as normal use case, it is necessary for USBPLL operation.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 199 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
10.3
Section 10 IOs
Pinout
10.3.1
RZ/N1D BGA-400 Package
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20
GND
GPIO75
GPIO77
GPIO36
GPIO37
GPIO42
GPIO48
GPIO53
GPIO54
GPIO59
GPIO12
GPIO18
GPIO20
GPIO62
GPIO63
GPIO90
GPIO88
GPIO86
GPIO84
GND
20
19
GPIO78
GPIO76
GPIO74
GPIO68
GPIO38
GPIO41
GPIO45
GPIO51
GPIO56
GPIO58
GPIO13
GPIO17
GPIO64
GPIO106
GPIO91
GPIO89
GPIO87
GPIO85
GPIO93
GPIO82
19
18
GPIO30
GPIO79
GPIO73
GPIO71
GPIO66
GPIO39
GPIO44
GPIO47
GPIO52
GPIO55
GPIO19
GPIO15
GPIO22
GPIO102 GPIO107
GPIO96
GPIO95
GPIO100
GPIO80
GPIO81
18
17
GPIO27
GPIO32
GPIO34
GPIO69
GPIO70
GPIO67
GPIO40
GPIO46
GPIO49
GPIO57
GPIO16
GPIO21
GPIO104
GPIO99
GPIO97
GPIO105 GPIO103
GPIO92
GPIO83
17
16
GPIO24
GPIO28
GPIO29
GPIO129 GPIO128
GPIO72
GPIO65
GPIO43
GPIO50
GND
GPIO14
GPIO23
GPIO108 GPIO101
VDD11_C
GPIO120 GPIO109 GPIO118
A7
GPIO94
GPIO117
16
15
GPIO6
GPIO8
GPIO31
GPIO33
GPIO35
GND
GND
GND
RGMII5
_VDDQ
RGMII5
_VDDQ
GND
GND
VDD33
GND
VDD11_C
GPIO125 GPIO126 GPIO121 GPIO116 GPIO119
A7
15
14
GPIO5
GPIO9
GPIO10
GPIO26
RGMII3
_VDDQ
RGMII3
_VDDQ
VDD33
RGMII4
_VDDQ
RGMII4
_VDDQ
GND
RGMII2
_VDDQ
RGMII2
_VDDQ
VDD33
GND
GPIO124 GPIO123 GPIO122 GPIO111 GPIO115 GPIO113
14
13
GPIO2
GPIO4
GPIO3
GPIO11
GPIO25
GND
VDD11
GND
VDD11
VDD11
GND
VDD11
GND
VDD33
GPIO127
JTAG
_TDO
JTAG
_TCK
12
GPIO0
GPIO131
GPIO1
GPIO7
RGMII1
_VDDQ
GND
VDD11
GND
GND
GND
GND
GND
VDD11
VDD33
GND
JTAG
_TRST_N
JTAG
_TDI
GPIO98
GPIO114 GPIO112 GPIO110
JTAG
_TMS
GPIO61
MRESET MRESET
_N
_OUT
13
GPIO60
12
USB
_GND
11
11
GPIO137 GPIO135 GPIO133 GPIO132 GPIO130
RGMII1
_VDDQ
GND
GND
GND
GND
GND
GND
GND
USB
_AVSS
USB
_RREF
USB
_AVDD
USB
_VBUS
10
GPIO139 GPIO136 GPIO138 GPIO140 GPIO134
GND
VDD33
GND
GND
GND
GND
GND
VDD11
USB
_AVSS
USB
_GND
USB
_GND
USB
_GND
USB
_GND
USB
_DM1
USB
_DP1
10
9
GPIO141 GPIO143 GPIO147 GPIO144
CTRSTBY
B
VDD33
VDD33
VDD11
GND
GND
GND
GND
VDD11
GND
USB
_VD33
USB
_VD33
USB
_GND
USB
_GND
USB
_DM2
USB
_DP2
9
8
GPIO145 GPIO149 GPIO142 GPIO148
ANF_VDD RTC_VDD
_PRG
33
GND
VDD11
VDD11
DVSS
DVDD
VDD11
GND
VDD33
ADC2
_AGND
ADC2
_AVDD
ADC2
_IN6
ADC2
_IN7
ADC2
_IN8
USB
_GND
8
TMC2
THMODE
ADC2
_VREFN
ADC2
_VREFP
ADC2
_IN3
ADC2
_IN2
ADC2
_IN4
7
7
RTC_XI
RTC
GPIO146 _PWRGO GPIO152 GPIO150
OD
GND
VDD33
DVDDQ
GND
DVSS
DVDD
DVDDQ
VDD33
6
RTC_XO GPIO151 GPIO153 GPIO154 GPIO158
GND
VDD33
GND
DVDDQ
DVDDQ
DVDDQ
DVDDQ
GND
CONFIG1 CONFIG0
ADC1
_AVDD
ADC1
_VREFP
ADC1
_IN8
ADC2
_IN1
ADC2
_IN0
6
5
GPIO155 GPIO157 GPIO159 GPIO163 GPIO162
DDR
_DQ6
GND
GND
GND
DDR
_VREF
GND
DDR
_ADDR0
GND
DDR
CONFIG2
_ADDR5
ADC1
_AGND
ADC1
_VREFN
ADC1
_IN4
ADC1
_IN6
ADC1
_IN7
5
4
GPIO160 GPIO156 GPIO167 GPIO165
GND
DDR
_DQ0
DDR
_DQS_N0
DDR
_DQ7
DDR
_DQ5
DDR
_MZQ
DDR
_CS1
DDR
DDR
_ADDR12 _ADDR15
TMC1
ADC1
_IN3
ADC1
_IN0
ADC1
_IN2
4
3
GPIO161 GPIO169 GPIO166
GND
DDR
_DQ4
DDR
_DQS0
DDR
_DM0
DDR
_DQ1
DDR
_DQ3
GND
DDR
_ADDR10
DDR
_RAS
GND
ADC1
_IN1
3
2
GPIO164 GPIO168
DDR
_DQ14
DDR
_DQ8
DDR
_DQ2
DDR
_DM1
DDR
_DQS_N1
DDR
_DQ9
DDR
_DQ15
DDR
_CLKP
DDR
_CLKEN
1
DDR
_BA0
DDR
_ADDR7
DDR
_ADDR1
DDR
_CAS
DDR
_ADDR3
DDR
_ADDR4
DDR
DDR
DDR
_RESET_
_ADDR9 _ADDR14
N
DDR
_WE
DDR
_ODT0
DDR
_BA2
DDR
DDR
DDR
_ADDR2 _ADDR11 _ADDR13
GND
MCLK_XO
GND
2
1
GND
GND
DDR
_DQ12
DDR
_DQ10
GND
DDR
_DQS1
GND
DDR
_DQ11
DDR
_DQ13
DDR
_CLKN
GND
DDR
_CS0
DDR
_ODT1
DDR
_BA1
GND
DDR
_ADDR6
DDR
_ADDR8
GND
MCLK_XI
GND
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
Figure 10.1
RZ/N1D Pinout BGA-400 (Top View)
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 200 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
10.3.2
Section 10 IOs
RZ/N1D BGA-324 Package
A
B
C
D
E
F
G
H
J
K
L
18
GND
GPIO75
GPIO77
GPIO36
GPIO41
GPIO42
GPIO46
GPIO48
GPIO51
GPIO54
GPIO64
17
GPIO78
GPIO76
GPIO74
GPIO66
GPIO39
GPIO44
GPIO47
GPIO52
GPIO53
GPIO56
16
GPIO79
GPIO69
GPIO72
GPIO68
GPIO37
GPIO40
GPIO45
GPIO50
GPIO57
GPIO58
15
GPIO30
GPIO33
GPIO73
GPIO70
GPIO67
GPIO38
GPIO43
GPIO49
14
GPIO35
GPIO28
GPIO31
GPIO128
GPIO71
GPIO65
RGMII4
_VDDQ
13
GPIO29
GPIO32
GPIO34
GPIO129
VDD33
GND
12
GPIO24
GPIO27
GPIO25
GPIO26
RGMII3
_VDDQ
11
GPIO133 GPIO131 GPIO132 GPIO130
10
P
R
T
U
V
GPIO101 GPIO107
GPIO90
GPIO88
GPIO86
GPIO84
GND
18
GPIO108
GPIO99
GPIO91
GPIO89
GPIO87
GPIO85
GPIO93
GPIO82
17
GPIO106
GPIO96
GPIO97
GPIO95
GPIO120 GPIO100
GPIO80
GPIO81
16
GPIO55
GPIO102 GPIO104
GPIO98
GPIO105
VDD11_C
GPIO125 GPIO103
A7
GPIO92
GPIO83
15
GND
GPIO59
GPIO62
GPIO63
GPIO109
GND
VDD11_C
GPIO124 GPIO126
A7
GPIO94
GPIO115
14
RGMII4
_VDDQ
RGMII5
_VDDQ
RGMII5
_VDDQ
VDD33
VDD33
GND
GND
GPIO123 GPIO122 GPIO118 GPIO116 GPIO113
13
GND
VDD11
GND
GND
VDD11
GND
VDD11
VDD33
GPIO127 GPIO121 GPIO117 GPIO119 GPIO114
12
RGMII3
_VDDQ
VDD33
GND
GND
GND
GND
GND
VDD11
VDD33
JTAG
_TDO
JTAG
_TDI
GPIO135 GPIO137 GPIO136 GPIO134
GND
VDD11
GND
GND
GND
GND
GND
USB
_AVSS
GND
JTAG
_TRST_N
JTAG
_TMS
9
GPIO139 GPIO138 GPIO147 GPIO142
VDD33
VDD33
GND
GND
GND
GND
GND
USB
_AVSS
USB
_RREF
USB
_AVDD
USB
_VBUS
8
GPIO141 GPIO143 GPIO140 GPIO146
ANF_VDD
_PRG
VDD33
GND
GND
DVSS
DVDD
VDD11
USB
_VD33
USB
_VD33
USB
_GND
USB
_GND
USB
_GND
7
GPIO145 GPIO149 GPIO144
CTRSTBY RTC_VDD
B
33
VDD11
GND
DVDDQ
DVSS
DVDD
VDD11
GND
VDD33
CONFIG0
USB
_GND
GND
VDD33
VDD11
DVDDQ
DVDDQ
DVDDQ
DVDDQ
VDD33
TMC2
ADC1
_AVDD
CONFIG2
RTC
GPIO148 GPIO150 _PWRGO
OD
M
N
GPIO111 GPIO112 GPIO110
JTAG
_TCK
GPIO60
10
USB
_GND
9
USB
_DM1
USB
_DP1
8
USB
_GND
USB
_DM2
USB
_DP2
7
ADC1
_VREFP
ADC1
_IN6
ADC1
_IN8
USB
_GND
6
ADC1
_AGND
ADC1
_VREFN
ADC1
_IN4
ADC1
_IN7
5
ADC1
_IN1
ADC1
_IN2
ADC1
_IN0
4
GND
ADC1
_IN3
3
MRESET MRESET
_N
_OUT
6
RTC_XI
5
RTC_XO GPIO151 GPIO154
GND
DDR
_DQ6
GND
GND
GND
DDR
_VREF
DDR
_ADDR0
GND
THMODE
TMC1
4
GPIO152 GPIO153
GND
DDR
_DQ0
DDR
_DQS0
DDR
_DQ1
DDR
_DQ7
DDR
_MZQ
GND
DDR
_ADDR12
DDR
_BA0
DDR
_ADDR5
DDR
_ADDR7
DDR
CONFIG1
_ADDR1
3
GPIO155
DDR
_DQ14
DDR
_DQ4
DDR
_DQS_N0
DDR
_DM0
DDR
_DQ3
DDR
_DQ5
GND
DDR
_ADDR10
DDR
_RAS
DDR
DDR
_ADDR15 _ADDR3
DDR
_ADDR4
DDR
DDR
DDR_
_ADDR9 _ADDR14 RESET_N
2
DDR
_DQ12
DDR
_DQ10
DDR
_DQ2
DDR
_DM1
DDR
_DQS_N1
DDR
_DQ9
DDR
_DQ15
DDR
_CLKP
DDR
_CLKEN
DDR
_WE
DDR
_CAS
DDR
_BA2
1
GND
DDR
_DQ8
GND
DDR
_DQS1
GND
DDR
_DQ11
DDR
_DQ13
DDR
_CLKN
GND
DDR
_CS0
DDR
_ODT0
DDR
_BA1
A
B
C
D
E
F
G
H
J
K
L
M
Figure 10.2
GPIO61
11
DDR
DDR
DDR
_ADDR2 _ADDR11 _ADDR13
GND
MCLK_XO
GND
2
GND
DDR
_ADDR6
DDR
_ADDR8
GND
MCLK_XI
GND
1
N
P
R
T
U
V
RZ/N1D Pinout BGA-324 (Top View)
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 201 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
10.3.3
Section 10 IOs
RZ/N1S BGA-324 Package
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
18
GND
GPIO69
GND
GPIO48
GPIO55
GPIO59
GPIO12
GPIO17
GPIO20
GND
GPIO0
GPIO2
GPIO6
GND
GPIO88
GPIO86
GPIO84
GND
18
17
GPIO67
GPIO68
GPIO70
GPIO50
GPIO51
GPIO57
GND
GPIO14
GPIO19
GPIO21
GPIO1
GPIO3
GPIO8
GPIO90
GPIO89
GPIO87
GPIO85
GPIO93
17
16
GPIO66
GPIO65
GPIO64
GPIO71
GPIO53
GPIO49
GPIO56
GPIO13
GPIO18
GPIO23
GPIO5
GPIO7
GPIO9
GPIO153
GPIO91
GPIO81
GPIO82
GPIO80
16
15
GND
GPIO62
GPIO63
GPIO72
GPIO52
GPIO54
GPIO58
GPIO15
GPIO16
GPIO22
GPIO4
GPIO11
GPIO10
GPIO154 GPIO152 GPIO151
GPIO92
GND
15
14
GPIO43
GPIO45
GPIO46
GPIO73
VDD33
VDD33
RGMII5
_VDDQ
RGMII5
_VDDQ
RGMII2
_VDDQ
RGMII2
_VDDQ
RGMII1
_VDDQ
RGMII1
_VDDQ
VDD33
GPIO155 GPIO157 GPIO150
GPIO83
GPIO94
14
13
GPIO38
GPIO39
GPIO44
GPIO47
GND
GND
GND
GND
GND
GND
GND
GND
VDD33
GPIO156 GPIO158 GPIO159
MRESET
_OUT
GND
13
12
GPIO36
GPIO37
GPIO41
GPIO42
RGMII4
_VDDQ
GND
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
GND
GND
GND
MRESET
_N
MCLK
_XO
MCLK
_XI
12
11
GND
GPIO34
GPIO33
GPIO40
RGMII4
_VDDQ
GND
VDD11
GND
GND
GND
GND
VDD11
PLL
_AVDD
GND
GND
USB
_VBUS
USB
_GND
USB
_GND
11
10
GPIO32
GPIO35
GPIO31
GPIO30
RGMII3
_VDDQ
GND
VDD11
GND
GND
GND
GND
VDD11
PLL
_AGND
USB
_AVDD
USB
_RREF
USB
_GND
USB
_DM1
USB
_DP1
10
9
GPIO28
GPIO27
GPIO29
GPIO25
RGMII3
_VDDQ
GND
VDD11
GND
GND
GND
GND
VDD11
VDD33
USB
_VD33
USB
_VD33
USB
_GND
USB
_DM2
USB
_DP2
9
8
GPIO24
GPIO26
GPIO77
GND
GND
VDD33
VDD11
GND
GND
GND
GND
VDD11
GND
ADC1
_AVDD
ADC1
_VREFN
ADC1
_IN7
USB
_GND
USB
_GND
8
7
GND
GPIO79
GPIO76
GPIO74
GND
VDD33
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
GND
ADC1
_AGND
ADC1
_VREFP
ADC1
_IN2
ADC1
_IN8
ADC1
_IN6
7
6
GPIO61
GPIO78
GPIO75
GPIO133
GND
VDD33
GND
GND
GND
GND
GND
GND
GND
VDD33
TMC2
ADC1
_IN0
ADC1
_IN1
ADC1
_IN3
6
5
GPIO60
VDD33
GPIO149
RTC
_VDD33
GND
GND
VDD33
VDD33
VDD33
GND
GND
GND
VDD33
VDD33
JTAG
_TRST_N
JTAG
_TDI
JTAG
_TMS
ADC1
_IN4
5
4
GND
TMC1
JTAG
_TCK
GPIO148
GND
4
ANF_VDD RTC_PWR
CTRSTBY
GPIO123 GPIO125 GPIO127 GPIO129 GPIO130 GPIO131 GPIO132 GPIO134 GPIO136
CONFIG1
_PRG
GOOD
B
JTAG_TD
GPIO145 GPIO146 GPIO147
O
3
GPIO100 GPIO102 GPIO104 GPIO105 GPIO108 GPIO111 GPIO113 GPIO116 GPIO137 GPIO138 GPIO139 GPIO142 GPIO143 GPIO144
2
GND
GPIO99
1
D
E
3
RTC_XO GPIO120 GPIO121 GPIO122 GPIO124 GPIO126 GPIO128 GPIO106 GPIO109 GPIO112 GPIO114 GPIO135 THMODE CONFIG0
2
RTC_XI
GPIO119
GPIO97
GPIO98
1
GND
GPIO95
GPIO96
A
B
C
Figure 10.3
GPIO101 GPIO103
F
G
GND
H
GPIO107 GPIO110
J
K
GND
L
GPIO115 GPIO117 GPIO118
M
N
P
GND
R
GPIO140 GPIO141
T
U
GND
V
RZ/N1S Pinout BGA-324 (Top View)
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 202 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
10.3.4
Figure 10.4
Section 10 IOs
RZ/N1S BGA-196 Package
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14
GND
GPIO70
GND
GPIO48
GPIO51
GPIO57
GND
GPIO3
GPIO7
GPIO8
GND
GPIO89
GPIO87
GND
14
13
GPIO64
GPIO68
GPIO71
GPIO50
GPIO49
GPIO56
GPIO0
GPIO2
GPIO6
GPIO90
GPIO86
GPIO84
GPIO81
GPIO93
13
12
GPIO63
GPIO67
GPIO72
GPIO52
GPIO54
GPIO58
GPIO1
GPIO5
GPIO9
GPIO88
GPIO91
GPIO82
GPIO80
GPIO83
12
11
GPIO66
GPIO65
GPIO69
GPIO53
GPIO55
GPIO59
GPIO4
GPIO11
GPIO10
VDD33
GPIO85
GPIO92
GPIO94
GND
11
10
GND
GPIO45
GPIO62
GPIO73
VDD33
RGMII5
_VDDQ
RGMII5
_VDDQ
RGMII1
_VDDQ
RGMII1
_VDDQ
GND
VDD11
MRESET
_OUT
MCLK
_XO
MCLK
_XI
10
9
GPIO47
GPIO43
GPIO42
GPIO44
VDD11
GND
VDD11
GND
VDD11
PLL
_AVDD
PLL
_AGND
MRESET USB_VBU
_N
S
USB
_GND
9
8
GPIO46
GPIO39
GPIO38
GPIO41
RGMII4
_VDDQ
GND
GND
GND
GND
USB
_AVDD
USB
_RREF
USB
_GND
USB
_DM1
USB
_DP1
8
7
GND
GPIO36
GPIO37
GPIO40
RGMII4
_VDDQ
VDD11
GND
GND
VDD11
USB
_VD33
USB
_VD33
USB
_GND
USB
_DM2
USB
_DP2
7
6
GPIO61
GPIO77
GPIO79
GPIO76
VDD33
GND
GND
GND
GND
GND
ADC1
_AVDD
ADC1
_VREFN
USB
_GND
USB
_GND
6
5
GPIO60
GPIO75
GPIO78
GPIO74
VDD11
GND
VDD11
VDD11
GND
VDD11
ADC1
_AGND
ADC1
_VREFP
ADC1
_IN8
ADC1
_IN7
5
4
GND
RTC
_VDD33
VDD33
ANF_VDD
_PRG
VDD33
VDD33
VDD33
TMC2
ADC1
_IN2
ADC1
_IN0
ADC1
_IN6
4
3
RTC
_XO
CTRSTBY
CONFIG1
B
TMC1
ADC1
_IN4
ADC1
_IN3
3
2
RTC
_XI
GPIO98
GPIO96
GPIO102 GPIO104 GPIO108 GPIO110 GPIO114 GPIO116 THMODE CONFIG0
JTAG
_TCK
JTAG
_TMS
ADC1
_IN1
2
1
GND
GPIO99
GPIO101
GND
1
A
B
C
D
RTC_PWR
GPIO97
GOOD
GPIO95
GPIO105 GPIO107 GPIO112
GPIO100 GPIO103 GPIO111 GPIO115 GPIO117
GPIO106 GPIO109
E
F
GND
G
GPIO113 GPIO118
H
J
GND
JTAG
_TDO
JTAG
_TRST_N
JTAG
_TDI
GND
K
L
M
N
P
RZ/N1S Pinout BGA-196 (Top View)
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 203 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
10.3.5
Figure 10.5
Section 10 IOs
RZ/N1L BGA-196 Package
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14
GND
GPIO70
GND
GPIO48
GPIO51
GPIO57
GND
GPIO3
GPIO7
GPIO8
GND
GPIO89
GPIO87
GND
14
13
GPIO64
GPIO68
GPIO71
GPIO50
GPIO49
GPIO56
GPIO0
GPIO2
GPIO6
GPIO90
GPIO86
GPIO84
GPIO81
GPIO93
13
12
GPIO63
GPIO67
GPIO72
GPIO52
GPIO54
GPIO58
GPIO1
GPIO5
GPIO9
GPIO88
GPIO91
GPIO82
GPIO80
GPIO83
12
11
GPIO66
GPIO65
GPIO69
GPIO53
GPIO55
GPIO59
GPIO4
GPIO11
GPIO10
VDD33
GPIO85
GPIO92
GPIO94
GND
11
10
GND
GPIO45
GPIO62
GPIO73
VDD33
RGMII5
_VDDQ
RGMII5
_VDDQ
RGMII1
_VDDQ
RGMII1
_VDDQ
GND
VDD11
MRESET
_OUT
MCLK
_XO
MCLK
_XI
10
9
GPIO47
GPIO43
GPIO42
GPIO44
VDD11
GND
VDD11
GND
VDD11
PLL
_AVDD
PLL
_AGND
MRESET USB_VBU
_N
S
USB
_GND
9
8
GPIO46
GPIO39
GPIO38
GPIO41
RGMII4
_VDDQ
GND
GND
GND
GND
USB
_AVDD
USB
_RREF
USB
_GND
USB
_DM1
USB
_DP1
8
7
GND
GPIO36
GPIO37
GPIO40
RGMII4
_VDDQ
VDD11
GND
GND
VDD11
USB
_VD33
USB
_VD33
USB
_GND
USB
_DM2
USB
_DP2
7
6
GPIO61
GPIO77
GPIO79
GPIO76
VDD33
GND
GND
GND
GND
GND
ADC1
_AVDD
ADC1
_VREFN
USB
_GND
USB
_GND
6
5
GPIO60
GPIO75
GPIO78
GPIO74
VDD11
GND
VDD11
VDD11
GND
VDD11
ADC1
_AGND
ADC1
_VREFP
ADC1
_IN8
ADC1
_IN7
5
4
GND
VDD33
VDD33
GND
VDD33
VDD33
VDD33
TMC2
ADC1
_IN2
ADC1
_IN0
ADC1
_IN6
4
3
N.C.
VDD33
GPIO97
GPIO95
CTRSTBY
CONFIG1
B
TMC1
ADC1
_IN4
ADC1
_IN3
3
2
GND
GPIO98
GPIO96
GPIO102 GPIO104 GPIO108 GPIO110 GPIO114 GPIO116 THMODE CONFIG0
JTAG
_TCK
JTAG
_TMS
ADC1
_IN1
2
1
GND
GPIO99
GPIO101
GND
1
A
B
C
D
GPIO105 GPIO107 GPIO112
GPIO100 GPIO103 GPIO111 GPIO115 GPIO117
GPIO106 GPIO109
E
F
GND
G
GPIO113 GPIO118
H
J
GND
JTAG
_TDO
JTAG
_TRST_N
JTAG
_TDI
GND
K
L
M
N
P
RZ/N1L Pinout BGA-196 (Top View)
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 204 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Section 11
11.1
Section 11 Electrical Characteristics
Electrical Characteristics
Absolute Maximum Ratings
Table 11.1
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Value
Unit
Logic core
VDD11
—
−0.45 to +1.6
V
I/O
VDD33
—
−0.5 to +4.6
V
I/O for RGMII
VRGMII
—
−0.5 to +4.6
V
PLL
VPLL
—
−0.45 to +1.6
V
USB
VUSB
—
−0.5 to +4.6
V
ADC
VADC
—
−0.5 to +4.6
V
RTC
VRTC
—
−0.5 to +4.6
V
DDRPHY I/O
VDVDDQ
—
−0.5 to +2.5
V
DDRPHY core
VDVDD
—
−0.45 to +1.6
V
DDRPHY reference
VDDR REF
—
−0.5 to +2.5
V
OTP memory programming
VANFPRG
—
−0.5 to +7.5
V
Input/output voltage
VI / V O
VI / VO < VDD33 + 0.5 V
−0.5 to +4.6
V
Storage temperature
Tstg
—
−55 to +125
°C
Power supply voltage
CAUTION
Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Exceeding the
absolute maximum ratings can cause permanent damage. The parameters apply independently. The device should be
operated within the limits specified by the DC and AC characteristics.
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 205 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
11.2
Section 11 Electrical Characteristics
Recommended Operating Conditions
Table 11.2
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Power supply voltage
VDD11
1.10
1.15
1.20
V
VDD33
3.0
3.3
3.6
V
VRGMII
Conditions
RGMII mode
VPLL
3.14
3.3
3.46
V
1.10
1.15
1.20
V
VUSB
3.0
3.3
3.6
V
VADC
3.0
3.3
3.6
V
VADC REFP
VADC
VADC REFM
VRTC
V
0
Normal mode
V
3.0
3.3
3.6
V
Backup mode
1.8
—
3.6
V
DDR3
1.425
1.5
1.575
V
DDR2
1.7
1.8
1.9
V
VDVDD
1.10
1.15
1.20
V
VDDR REF
VDVDDQ
× 0.49
VDVDDQ
× 0.50
VDVDDQ
× 0.51
V
| VDD33 − VRTC | ≤ 0.3
VDVDDQ
VANFPRG
Clock input frequency
fOSC
Junction temperature
Tj
Note 1.
OTP memory programming
6.8
6.9
7.0
V
Normal
—
0
—
V
±50 ppm*1
—
40.0
—
MHz
−40
—
110
°C
±25 ppm for EtherCAT
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 206 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
11.3
Section 11 Electrical Characteristics
DC Characteristics
11.3.1
Current
Table 11.3
Current
Parameter
Symbol
Current drain
IDD11
Conditions
Min
Typ
Max
Unit
RZ/N1D
—
—
1450
mA
RZ/N1S, RZ/N1L
—
—
1300
mA
—
—
250
mA
IRGMII
RGMII 1 ch
—
—
50
mA
IPLL
RZ/N1S, RZ/N1L only
—
—
15
mA
IUSB
2 ports used
—
—
125
mA
IADC
ADC 1 unit
—
—
12
mA
IADC REF
ADC 1 unit
—
—
300
μA
IRTC_NM
Normal mode
—
—
1.5
mA
—
2.0
4.0
μA
IDD33
RTC_PCLK is supplied
IRTC_BU
Backup mode
Tj = 0 to 40°C, VRTC = 3.0 V
Input leakage current
Output current high
Output current low
Note 1.
IDVDDQ
DDR3
—
—
210
mA
IDVDD
DDR3
—
—
140
mA
IANFPRG
OTP memory programming
—
—
30
mA
—
ILI
−IOH*
IOL*
1
1
VI = VDD33 or GND
—
±5
μA
VI = GND with internal pull-up
−36
−96
μA
VI = VDD33 with internal pull-down
37
96
μA
VOH = 2.4 V
VOL = 0.4 V
4 mA
4
—
—
mA
6 mA
6
—
—
mA
8 mA
7.8
—
—
mA
12 mA
9.5
—
—
mA
4 mA
4
—
—
mA
6 mA
6
—
—
mA
8 mA
7.8
—
—
mA
12 mA
9.5
—
—
mA
Total output current values are strongly recommended to be within the values IDD33 and IRGMII to ensure the reliability of this
LSI.
IDD33: Total output current values of I/O pins from GPIO60 to GPIO169
IRGMII: Total output current values of each channel I/O pins (GPIO11 to GPIO0, GPIO23 to GPIO12, GPIO35 to GPIO24,
GPIO47 to GPIO36, GPIO59 to GPIO48)
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Page 207 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
11.3.2
Section 11 Electrical Characteristics
Digital IO
Table 11.4
Digital IO
Parameter
Symbol
High-level input voltage
VIH
3.3 V input
2.0
—
VDD33 + 0.3 V
Low-level input voltage
VIL
3.3 V input
−0.3
—
0.8
V
Positive trigger voltage
VP
Schmitt input
0.9
—
2.1
V
Negative trigger voltage
VN
Schmitt input
0.7
—
1.9
V
Hysteresis of Schmitt trigger
VH1
Schmitt input
0.2
—
1.4
V
High-level output voltage
VOH
IOH
2.4
—
—
V
Low-level output voltage
VOL
IOL
0
—
0.4
V
Input rise/fall time data
trid / tfid
—
0
—
200
ns
Input rise/fall time clock
tric / tfic
—
0
—
4
ns
Input rise/fall time Schmitt
tris / tfis
—
0
—
1
ms
Pull up/down resistor
RPUUD
—
37
50
82
kΩ
Input capacitance
Cin
—
—
—
6.0
pF
11.3.3
Conditions
Min
Typ
Max
Unit
DDR3/DDR2 SDRAM Interface
Table 11.5
DDR3/DDR2 SDRAM Interface
Parameter
Symbol
Min
Typ
Max
Unit
Reference voltage input
VDDR REF
VDVDDQ × 0.49
VDVDDQ
× 0.50
VDVDDQ × 0.51
V
DC input logic high
VDDRIH (dc)
VDDR REF + 0.1
—
VDVDDQ
V
*1
DC input logic low
VDDRIL (dc)
0
—
VDDR REF − 0.1
V
*1
DC differential input high
VDDRIHdiff (dc) 0.400
—
—
V
*2
DC differential input low
VDDRILdiff (dc) —
—
−0.400
V
*2
AC input logic high
VDDRIH (ac)
VDDR REF + 0.150
—
VDVDDQ + 0.5
V
*3
AC input logic low
VDDRIL (ac)
−0.5
—
VDDR REF − 0.150
V
*3
AC differential input high
VDDRIHdiff (ac) 0.500
—
—
V
*2
AC differential input low
VDDRILdiff (ac) —
—
−0.500
V
*2
AC differential cross point voltage (input)
VDDRIX (ac)
0.5 × VDVDDQ − 0.150
—
0.5 × VDVDDQ + 0.150
V
*2
AC differential cross point voltage (output)
VDDROX (ac)
0.5 × VDVDDQ − 0.050
—
0.5 × VDVDDQ + 0.050
V
*4
Note 1.
DDR_DQ, DDR_DQS, DDR_DQS_N
Note 2.
DDR_DQS, DDR_DQS_N
Note 3.
DDR_DQ
Note 4.
DDR_CLKP, DDR_CLKN, DDR_DQS, DDR_DQS_N
R01UH0750EJ0140
Feb 28, 2021
Rev.1.40
Note
Page 208 of 263
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
11.4
Section 11 Electrical Characteristics
Power-up/down Sequence
11.4.1
Power-up
100ms
VDD11
VDD33
RGMII_VDDQ
DVDDQ
USB_VD33
ADC_AVDD
At least 200ns
CTRSTBYB
> 1μs
Fixed level or Floating
Output
I/O Buffer
Default reset and config values
Prog by CPU
Normal operation mode
Hold time (10μs)
MRESET_N
(External Power-on reset)
Oscillation stabilization
time (~1ms)
Oscillator clock
(MCLK_XO, MCLK_XI)
1μs
MRESET_N
(External Power-on reset)
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