Datasheet
RAA210040
5V, 4A Step-Down DC/DC Mini Module with Integrated Inductor
The RAA210040 power module is a compact,
synchronous step-down, non-isolated complete
power supply, capable of delivering up to 4A of
continuous current. By operating from a single 2.7V to
5.5V input power rail and integrating the controller,
gate driver, power inductor, and MOSFETs, the
RAA210040 is optimized for space-constrained
applications.
Based on a peak current mode control scheme, the
RAA210040 provides fast transient response and
excellent loop stability. The output voltage can be set
as low as 0.6V, with setpoint accuracy better than
1.5% over line, load, and temperature. The operating
frequency has a 2MHz default setting; however, it can
also be set from 500kHz to 4MHz by an external
resistor. The external synchronization is supported
with an external clock signal up to 4MHz. The
RAA210040 supports a 100% duty cycle operation to
minimize the switching losses and allows less than
200mV dropout voltage. A dedicated enable pin and
power-good flag allows for easy system power rails
sequencing.
An array of protection features, including input
Undervoltage Lockout (UVLO), Overcurrent
Protection (OCP), output Overvoltage Protection
(OVP), and Over-temperature Protection (OTP),
ensures safe operations under abnormal operating
conditions.
Features
▪ 4A complete power supply
• Integrates controller, gate driver, MOSFETs, and
inductor
▪ 2.7V to 5.5V input voltage range
▪ Adjustable output voltage
• As low as 0.6V with ±1.5% accuracy over line,
load, and temperature
• Up to 95% efficiency
▪ Default 2MHz current mode control operation
• 500kHz to 4MHz resistor adjustable
• External synchronization up to 4MHz
• 100% duty cycle
▪ Dedicated enable pin and power-good flag
▪ Internal 1ms soft start-up time
▪ Soft-stop output discharge
▪ UVLO, OCP, negative OCP, OVP, and OTP
• OCP/Short-Circuit Protection (SCP) hiccup
mode
▪ Compact RoHS compliant 3mmx3mmx1.7mm
10 lead dual flat embedded laminate package
Applications
▪ Telecom, Industrial, optical, and medical equipment
▪ Point-of-load conversions
▪ MCU, MPU, DSP, and FPGA
95
RAA210040
CIN
VIN
100k
COMP
EN
FS
169k
PGND
390pF
FB
SYNC
100k
820pF
SGND
PGOOD
90
1.2V 4A Output
VOUT
Power-Good
COUT
Efficiency (%)
2.7V to 5.5V Input
85
80
75
70
3.3Vin, 1.2MHz
65
5Vin, 1.2MHz
60
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Load Current (A)
Figure 1. Typical Application Circuit
R16DS0137EU0101 Rev.1.01
Jun 15, 2023
Figure 2. Efficiency VOUT = 1.2V
Page 1
© 2021-2023 Renesas Electronics
RAA210040 Datasheet
Contents
1.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
2.
Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
3.
15
15
16
16
16
17
17
17
17
17
17
18
Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
19
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1
8.2
8.3
8.4
9.
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1
7.2
8.
Efficiency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Load Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Start-Up Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
6.2
6.3
6.4
7.
7
7
7
7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
6.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
4.4
4.5
5.
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
3.3
3.4
4.
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
22
22
22
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
11. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
R16DS0137EU0101 Rev.1.01
Jun 15, 2023
Page 2
RAA210040 Datasheet
1.
1.1
Overview
Typical Application Circuits
RAA210040
2.7V to 5.5V Input
VIN
R1 100k
CIN
2x22µF
COMP
C1 390pF
EN
FS
RFS
PGND
RRS
2
COUT
2x22µF
FB
R2
100k
SYNC
169k
1.2V 4A Output
VOUT
C2
820pF
SGND
PGOOD
Power-Good
Figure 3. VOUT = 1.2V, fSW = 1.2MHz, PWM Mode, tSS = 1ms
R16DS0137EU0101 Rev.1.01
Jun 15, 2023
Page 3
RAA210040 Datasheet
1.2
Block Diagram
Bandgap
SYNC
6
8
Shutdown
100k
Shutdown
7
FS
3
55pF
SoftStart
EN
COMP
VREF
Oscillator
COMP
EAMP
PWM Logic Controller
Protection
HS Driver
3pF
FB
VIN
5
VOUT
1
PGND
4
SGND
0.47µH
LS
Driver
2
6k
L
10
0.8V
Slope
COMP
OV
CSA
0.85 x VREF
UV
OCP
ISET
Threshold
SKIP
PG
9
1ms
Delay
Negative Current
Sensing
Zero-Crossing
Sensing
0.5V
SCP
100
Shutdown
Figure 4. Block Diagram
R16DS0137EU0101 Rev.1.01
Jun 15, 2023
Page 4
RAA210040 Datasheet
2.
Pin Information
2.1
Pin Assignments
PGND
1
10
VIN
FB
2
9
PG
COMP
3
8
SYNC
SGND
4
7
EN
VOUT
5
6
FS
EPAD
1.7mm
3mm
3mm
Top View
2.2
Pin Descriptions
Pin
Number
Pin
Name
Function
1
PGND
Power ground. Connect it close to the (-) terminals of the external input capacitors and output capacitors.
2
FB
Voltage setting pin. The module output voltage is set by an external resistor divider connected to FB. With
a properly selected divider, the output voltage is set to any voltage between 0.6V and 5V. Renesas also
recommends placing a ceramic capacitor in parallel to ensure system stability at extreme operating
conditions. Table 1 lists the resistor and capacitor values for various typical output voltages.
3
COMP
Compensation pin. COMP is the output of the transconductance error amplifier. For most applications,
directly connect COMP to VIN to select internal compensation to stabilize the system and achieve an
optimal transient response. For applications where external compensation is required, connect COMP to
SGND with an external compensation network.
4
SGND
Signal ground. Must connect it to EPAD for proper electrical performance.See Layout Guidelines for more
information.
5
VOUT
Power output of the module. Place the output capacitors as close as possible to the module output. See
Layout Guidelines for more information.
6
FS
Frequency selection pin. This pin sets the module switching frequency by connecting a resistor to SGND.
The frequency of operation can be programmed between 500kHz to 4MHz. The default frequency is
2MHz if FS is connected to VIN.
7
EN
Module enable pin. Enable the module by driving EN high. Shuts down the module and discharge the
output capacitor when driven low. Typically tied to VIN directly. Note: Do not leave this pin floating.
8
SYNC
9
PG
Power-good pin. Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected
between VIN and PG. During power-up or EN start-up, the PG rising edge is delayed by 1ms after the
output is in regulation.
10
VIN
Power input of the module. Tie directly to the input rail between 2.7V~5.5V. Note: You must place
minimum total 2x22µF X7R input ceramic capacitors as close as possible to the module input. Add
additional capacitance if possible. See Layout Guidelines for more information.
-
EPAD
Power ground. Must connect it to SGND for proper electrical performance. Place as many vias as
possible under the EPAD for optimal thermal performance.
Synchronization pin. Connect to logic high or the input voltage (VIN) for PWM mode. Drive with a 500kHz
to 4MHz square wave for external synchronization. Note: Do not leave this pin floating.
R16DS0137EU0101 Rev.1.01
Jun 15, 2023
Page 5
RAA210040 Datasheet
Table 1. RAA210040 Design Guide Matrix (See Figure 3)
CIN
COUT
VIN
VOUT
R1
R2
(Ceramic)
(Ceramic)
Freq
RFS
C1
C2
Case
(V)
(V)
(kΩ)
(kΩ)
(µF)
(µF)
(MHz)
(kΩ)
(pF)
(pF)
1
3.3
0.6
100
open
2x22
1x47
0.8
261
390
820
2
3.3
0.8
100
301
2x22
2x22
0.9
232
390
820
3
3.3
0.9
100
200
2x22
2x22
1
205
390
820
4
3.3
1
100
150
2x22
2x22
1
205
390
820
5
3.3
1.2
100
100
2x22
2x22
1.2
169
390
820
6
3.3
1.5
100
66.5
2x22
2x22
1.3
154
390
680
7
3.3
1.8
100
49.9
2x22
2x22
1.5
133
390
560
8
3.3
2.5
100
31.6
2x22
2x22
1.8
107
390
470
9
5
1
100
150
2x22
2x22
1
205
390
820
10
5
1.2
100
100
2x22
2x22
1.2
169
390
820
11
5
1.5
100
66.5
2x22
2x22
1.3
154
390
680
12
5
1.8
100
49.9
2x22
2x22
1.5
133
390
560
13
5
2.5
100
31.6
2x22
2x22
1.8
107
390
470
14
5
3.3
100
22.1
2x22
2x22
2.4
76.8
390
470
Table 2. Recommended Input/Output Capacitor
Vendor
Value
Part Number
Murata, Input Ceramic
22µF, 10V, 1206, X7R
GRM31CR71A226KE15L
Murata, Output Ceramic
22uF, 6.3V, 1206, X7R
GRM31CR70J226KE19L
Murata, Output Ceramic
47µF, 6.3V, 1206, X7R
GRM32ER70J476ME20L
R16DS0137EU0101 Rev.1.01
Jun 15, 2023
Page 6
RAA210040 Datasheet
3.
Specifications
3.1
Absolute Maximum Ratings
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such
conditions can adversely impact product reliability and result in failures not covered by warranty.
Parameter
Minimum
Maximum
Unit
VIN to PGND
-0.3
+5.8 (DC) or +7V
(20ms)
V
EN, FS, PG, FB, SYNC, COMP to SGND
-0.3
VIN + 0.3
V
VOUT to PGND
-0.3
VIN + 0.3
V
Maximum Storage Temperature Range
-65
+150
°C
Human Body Model (Tested per JS-001-2014)
-
2.0
kV
Charged Device Model (Tested per JS-002-2014)
-
750
V
Latch-Up (Tested per JESD78E; Class II, Level A, +125°C)
-
100
mA
3.2
Thermal Information
Parameter
Package
Symbol
Thermal Resistance
10 Lead Dual Flat
Embedded Laminate
Package
θJA[1]
θJC[2]
Typical
Value
Unit
Junction to air
33.84
°C/W
Junction to case
16.4
°C/W
Conditions
1. JA is measured in free air with the module mounted on a 4-layer thermal test board 3x4.5 inch in size with significant coverage of 2oz
Cu on both top and bottom layers, and 1oz Cu on internal layers, with numerous vias.
2. For JC, the case temperature location is the center of the exposed metal pad on the package underside.
3.3
Recommended Operating Conditions
Parameter
Minimum
Maximum
Unit
VIN to GND
2.7
5.5
V
Output Voltage, VOUT
0.6
5
V
Output Current, IOUT
0
4
A
-40
+125
°C
Junction Temperature Range, TJ
3.4
Electrical Specifications
.5
Unless otherwise noted, all parameter limits are established across the recommended operating conditions and the specification limits
are measured at the following conditions: TA=-40°C to +125°C, VIN = 3.6V, VOUT = 1.2V, unless otherwise noted. Typical specifications
are measured at TA= +25°C. Boldface limits apply across the internal junction temperature range, -40°C to +125°C.
Parameter
Symbol
Test Conditions
Min[1]
Typ
Max[1]
Unit
5.5
V
Module Input Supply
Input Voltage Range
R16DS0137EU0101 Rev.1.01
Jun 15, 2023
VIN
2.7
Page 7
RAA210040 Datasheet
Unless otherwise noted, all parameter limits are established across the recommended operating conditions and the specification limits
are measured at the following conditions: TA=-40°C to +125°C, VIN = 3.6V, VOUT = 1.2V, unless otherwise noted. Typical specifications
are measured at TA= +25°C. Boldface limits apply across the internal junction temperature range, -40°C to +125°C. (Cont.)
Parameter
VIN Undervoltage Lockout Threshold
Symbol
VUVLO
Test Conditions
Rising, no load
Falling, no load
Quiescent Supply Current
Shutdown Supply Current
IVIN
ISD
Min[1]
2.2
Typ
Max[1]
Unit
2.5
2.7
V
2.45
V
SYNC = VIN=3.6V, fSW = 2MHz,
EN = high, IOUT = 0A
19
25
mA
SYNC = VIN=5V, fSW = 2MHz, EN
= high, IOUT = 0A
23
30
mA
SYNC=VIN=5.5V, EN=low
4.5
10
uA
Output Regulation
Output Continuous Current Range[2]
Output Voltage
Range[2]
Output Voltage Accuracy[2]
IOUT
0
4
A
VOUT_RANGE
0.6
5
V
Total variation with line, load, and
temperature (-40°C ≤ TJ ≤
+125°C)
-1.5
1.5
%
VIN from 2.7V to 5.5V, IOUT = 0A
-1
1
%
From 0A to 4A, VIN = 5V
-1
1
%
VOUT_ACCY
Line Regulation[2]
∆VOUT/VOUT_S
Load Regulation[2]
∆VOUT/VOUT_S
ET
ET
Output Ripple Voltage
VOUT(AC)
VIN = 5V, VOUT = 1.2V, IOUT = 4A,
fSW = 1.2MHz, 2x22µF ceramic
capacitor
8
mVPP
Dynamic Characteristics
Voltage Change of Positive Load Step
VOUT_DP
Current slew rate = 2.5A/µs,
VIN = 5V, 2x22µF ceramic
capacitor VOUT = 1.2V, IOUT = 0A
to 4A
60
mV
Voltage Change of Negative Load Step
VOUT_DN
Current slew rate = 2.5A/µs,
VIN = 5V, 2x22µF ceramic
capacitor VOUT = 1.2V, IOUT = 4A
to 0A
60
mV
Current Protection
Current Limit Blanking Time
tOCON
17
clock
puls
es
Hiccup Time
thiccup
8
ms
Positive Peak Current Limit
IPLIMIT
5.2
6.6
9
A
Negative Current Limit
INLIMIT
-6
-3
-0.6
A
0.4
V
EN Threshold
Logic Input Low
Logic Input High
0.9
EN Logic Input Leakage Current
Pulled up to 3.6V
V
0.1
1
uA
Default Internal Soft-Starting
Default Internal Output Ramping Time
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tSS
SS=SGND
1
ms
Page 8
RAA210040 Datasheet
Unless otherwise noted, all parameter limits are established across the recommended operating conditions and the specification limits
are measured at the following conditions: TA=-40°C to +125°C, VIN = 3.6V, VOUT = 1.2V, unless otherwise noted. Typical specifications
are measured at TA= +25°C. Boldface limits apply across the internal junction temperature range, -40°C to +125°C. (Cont.)
Parameter
Symbol
Test Conditions
Min[1]
Typ
Max[1]
Unit
0.3
V
2
ms
Power-Good
Output Low Voltage
IPG =1mA
PG Delay Time (Rising Edge)
tPGR
PG Delay Time (Falling Edge)
tPGF
PG Leakage Current
IPGLKG
OVP PG Rising Threshold
VPGR_OVP
UVP PG Rising Threshold
VPGR_UVP
Time from VOUT reached
regulation
0.5
1
6.5
PG = 3.6V
10
us
100
0.8
80
UVP PG Hysteresis
86
nA
V
90
5.4
%
%
Reference Section
Internal Reference Voltage
FB Bias Current
VREF
IFBLKG
0.593
0.60
0
0.606
V
FB = 0.75V
0.1
uA
Internal Compensation
126
uA/V
External Compensation
132
uA/V
Compensation
Error Amplifier Transconductance
Current Sense Gain
0.145
0.2
0.25
Ω
PWM Regulator
Maximum Duty Cycle
Minimum On-Time
dMAX
100
tON_MIN
SYNC=high
fSW
fSW=2MHz
%
100
ns
Oscillator
Switching Frequency
1.7
2
2.35
MHz
Switching Frequency
RFS= 402kΩ
0.475
0.5
0.525
MHz
Switching Frequency
RFS= 42.2kΩ
3.94
4
4.125
MHz
4
MHz
0.84
V
Synchronization
SYNC Synchronization Range
fSYNC
0.5
SYNC Logic Low-to-High Transition
Range
0.67
SYNC Hysteresis
0.76
0.17
SYNC Logic Input Leakage Current
VIN = 3.6V
4
V
5
uA
Over-Temperature
Over-Temperature Shutdown
TOT-TH
150
°C
Over-Temperature Hysteresis
TOT-HYS
25
°C
1. Compliance to datasheet limit is assured by one or more methods: production test, characterization and/or design.
2. Compliance to limits is assured by characterization and design.
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RAA210040 Datasheet
4.
Typical Performance Graphs
4.1
Efficiency Performance
Operating condition: TA = +25°C, no air flow, PWM mode. Typical values are used unless otherwise noted.
95
95
90
85
Efficiency (%)
Efficiency (%)
90
80
75
0.8Vout, 900kHz
1Vout, 1MHz
1.5Vout, 1.3MHz
2.5Vout, 1.8MHz
70
65
0.9Vout, 1MHz
1.2Vout, 1.2MHz
1.8Vout, 1.5MHz
85
80
75
70
65
1.2Vout, 1.2MHz
1.5Vout, 1.3MHz
1.8Vout, 1.5MHz
2.5Vout, 1.8MHz
3.3Vout, 2.4MHz
60
60
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
Load Current (A)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Load Current (A)
Figure 5. VIN = 3.3V
4.2
1Vout, 1MHz
Figure 6. VIN = 5V
Output Voltage Ripple
Operating condition: TA = +25°C, no air flow, PWM mode. Typical values are used unless otherwise noted.
IOUT 0A
VOUT 10mV/Div
IOUT 0A
VOUT 10mV/Div
IOUT 4A
VOUT 10mV/Div
IOUT 4A
VOUT 10mV/Div
500ns/Div
500ns/Div
Figure 7. Output Ripple, VIN = 3.3V, VOUT = 0.8V,
fSW = 900kHz, COUT = 2x22µF Ceramic
Figure 8. Output Ripple, VIN = 3.3V, VOUT = 0.9V,
fSW = 1MHz, COUT = 2x22µF Ceramic
IOUT 0A
VOUT 10mV/Div
IOUT 0A
VOUT 10mV/Div
IOUT 4A
VOUT 10mV/Div
IOUT 4A
VOUT 10mV/Div
500ns/Div
Figure 9. Output Ripple, VIN = 5V, VOUT = 1V, fSW = 1MHz,
COUT = 2x22µF Ceramic
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500ns/Div
Figure 10. Output Ripple, VIN = 5V, VOUT = 1.2V,
fSW = 1.2MHz, COUT = 2x22µF Ceramic
Page 10
RAA210040 Datasheet
Operating condition: TA = +25°C, no air flow, PWM mode. Typical values are used unless otherwise noted. (Cont.)
IOUT 0A
VOUT 10mV/Div
IOUT 0A
VOUT 10mV/Div
IOUT 4A
VOUT 10mV/Div
IOUT 4A
VOUT 10mV/Div
500ns/Div
500ns/Div
Figure 11. Output Ripple, VIN = 5V, VOUT = 1.8V,
fSW = 1.5MHz, COUT = 2x22µF Ceramic
Figure 12. Output Ripple, VIN = 5V, VOUT = 3.3V,
fSW = 2.4MHz, COUT = 2x22µF Ceramic
IOUT 0A
VOUT 10mV/Div
IOUT 0A
VOUT 10mV/Div
IOUT 4A
VOUT 10mV/Div
IOUT 4A
VOUT 10mV/Div
500ns/Div
Figure 13. Output Ripple, VIN = 3.3V, VOUT = 0.8V,
fSW = 2MHz, COUT = 2x22µF Ceramic
4.3
500ns/Div
Figure 14. Output Ripple, VIN = 3.3V, VOUT = 0.9V,
fSW = 2MHz, COUT = 2x22µF Ceramic
Load Transient Response Performance
Operating condition: TA = +25°C, no air flow, PWM mode, 0.4A - 3.6A, 2.5A/µs step load. Typical values are used unless otherwise
noted.
IOUT 2A/Div
VOUT 100mV/Div
100µs/Div
Figure 15. VIN= 3.3V, VOUT = 0.8V, fSW = 900kHz,
COUT = 2x22µF Ceramic
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IOUT 2A/Div
VOUT 100mV/Div
100µs/Div
Figure 16. VIN= 3.3V, VOUT = 0.9V, fSW = 1MHz,
COUT = 2x22µF Ceramic
Page 11
RAA210040 Datasheet
Operating condition: TA = +25°C, no air flow, PWM mode, 0.4A - 3.6A, 2.5A/µs step load. Typical values are used unless otherwise
noted. (Cont.)
IOUT 2A/Div
IOUT 2A/Div
VOUT 100mV/Div
VOUT 100mV/Div
100µs/Div
100µs/Div
Figure 17. VIN = 5V, VOUT = 1V, fSW = 1MHz,
COUT = 2x22µF Ceramic
Figure 18. VIN = 5V, VOUT = 1.2V, fSW = 1.2MHz,
COUT = 2x22µF Ceramic
IOUT 2A/Div
IOUT 2A/Div
VOUT 100mV/Div
4.4
VOUT 100mV/Div
100µs/Div
100µs/Div
Figure 19. VIN = 5V, VOUT = 1.8V, fSW = 1.5MHz,
COUT = 2x22µF Ceramic
Figure 20. VIN = 5V, VOUT = 3.3V, fSW = 2.4MHz,
COUT = 2x22µF Ceramic
Start-Up Waveforms
Operating condition: TA = +25°C, no air flow. Typical values are used unless otherwise noted.
EN 1.5V/Div
EN 1.5V/Div
IOUT 2A/Div
IOUT 2A/Div
VOUT 500mV/Div
VOUT 500mV/Div
PG 2V/Div
PG 2V/Div
500µs/Div
500µs/Div
Figure 21. Start-Up Waveforms; VIN = 3.3V, VOUT = 0.8V,
IOUT = 4A
Figure 22. Start-Up Waveforms; VIN = 3.3V, VOUT = 0.9V,
IOUT = 4A
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RAA210040 Datasheet
Operating condition: TA = +25°C, no air flow. Typical values are used unless otherwise noted. (Cont.)
EN 1.5V/Div
EN 1.5V/Div
IOUT 2A/Div
IOUT 2A/Div
VOUT 500mV/Div
VOUT 500mV/Div
PG 2V/Div
PG 2V/Div
500µs/Div
500µs/Div
Figure 23. Start-Up Waveforms; VIN = 5V, VOUT = 1V,
IOUT = 4A
Figure 24. Start-Up Waveforms; VIN = 5V, VOUT = 1.2V,
IOUT = 4A
EN 1.5V/Div
EN 1.5V/Div
IOUT 2A/Div
IOUT 2A/Div
VOUT 1.5V/Div
VOUT 1V/Div
PG 2V/Div
PG 5V/Div
500µs/Div
500µs/Div
Figure 25. Start-Up Waveforms; VIN = 5V, VOUT = 1.8V,
IOUT = 4A
Figure 26. Start-Up Waveforms; VIN = 5V, VOUT = 3.3V,
IOUT = 4A
4.5
Derating
5
5
4
4
Load Current (A)
Load Current (A)
PWM operation. All of the following curves were plotted at TJ = +120°C. For the test conditions, see Table 1.
3
2
0 LFM
200 LFM
1
3
2
0 LFM
200 LFM
1
400 LFM
400 LFM
0
0
25
35
45
55
65
75
85
95
105
Ambient Temperature (°C)
Figure 27. VIN = 3.3V, VOUT = 0.8V, fSW = 900kHz
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115
25
35
45
55
65
75
85
95
105
115
Ambient Temperature (°C)
Figure 28. VIN = 3.3V, VOUT = 0.9V, fSW = 1MHz
Page 13
RAA210040 Datasheet
5
5
4
4
Load Current (A)
Load Current (A)
PWM operation. All of the following curves were plotted at TJ = +120°C. For the test conditions, see Table 1. (Cont.)
3
2
0 LFM
200 LFM
1
3
2
0 LFM
200 LFM
1
400 LFM
400 LFM
0
0
25
35
45
55
65
75
85
95
105
115
25
35
45
Ambient Temperature (°C)
5
5
4
4
3
0 LFM
200 LFM
1
65
75
85
95
105
115
Figure 30. VIN = 5V, VOUT = 1.2V, fSW = 1.2MHz
Load Current (A)
Load Current (A)
Figure 29. VIN = 5V, VOUT = 1V, fSW = 1MHz
2
55
Ambient Temperature (°C)
3
2
0 LFM
200 LFM
1
400 LFM
400 LFM
0
0
25
35
45
55
65
75
85
95
105
Ambient Temperature (°C)
Figure 31. VIN = 5V, VOUT = 1.8V, fSW = 1.5MHz
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115
25
35
45
55
65
75
85
95
105
115
Ambient Temperature (°C)
Figure 32. VIN = 5V, VOUT = 2.5V, fSW = 1.8MHz
Page 14
RAA210040 Datasheet
5.
Functional Description
The RAA210040 is a compact 4A step-down high-efficiency power module optimized for space-constrained
applications. The module switches at 2MHz by default when the FS pin is shorted to VIN. The switching frequency
is also adjustable from 500kHz to 4MHz through a resistor, RFS, from FS to SGND. Peak current mode control
scheme is implemented for a fast transient response. By shorting the COMP pin to VIN, the module uses internal
compensation to stabilize the system and optimize transient response. Other features include soft-stop output
discharge, external synchronization, 100% duty cycle operation, and low quiescent current. The supply current is
typically only 4.5µA when the module is shut down.
5.1
PWM Control Scheme
The RAA210040 employs peak current-mode Pulse-Width Modulation (PWM) for fast transient response and
pulse-by-pulse current limiting. Pulling the SYNC pin high (>0.8V) forces the module into PWM mode. As shown in
Figure 4, the current loop consists of the oscillator, PWM comparator, a current-sensing circuit, and slope
compensation for the current loop stability. The slope compensation is 440mV/Ts, which changes with frequency.
The gain for the current-sensing circuit is typically 200mV/A. The control reference for the current loops comes
from the output of the Error Amplifier (EAMP).
The PWM operation is initialized by the clock from the oscillator. The P-channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the Current-Sense
Amplifier (CSA) and the slope compensation reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the P-channel MOSFET and turn on the N-channel
MOSFET. The N-channel MOSFET stays on until the end of the PWM cycle. Figure 33 shows the typical
operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation
ramp and the output of the CSA.
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
Figure 33. PWM Operation Waveforms
The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a
0.6V reference voltage to the voltage loop. The feedback signal comes from the FB pin. The soft start-up block
only affects the operation during start-up and is discussed separately, see Soft Start-Up. The error amplifier is a
transconductance amplifier that converts the voltage error signal to a current output. When the COMP is tied to
VIN, the voltage loop is internally compensated with the 55pF and 100kΩ RC network.
5.2
Frequency Adjustment
The switching frequency of RAA210040 is adjustable ranging from 500kHz to 4MHz using a simple resistor RFS
across FS to SGND. The switching frequency setting is based on Equation 1:
(EQ. 1)
220 10 3
R FS k = ------------------------------ – 14
f OSC kHz
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RAA210040 Datasheet
When the FS pin is directly tied to VIN, the frequency of operation is fixed at 2MHz. See Table 1 to help with the
selection of switching frequency for typical operation conditions. More detailed information on recommended
switching frequency is provided in the Switching Frequency Selection section.
5.3
Overcurrent Protection (OCP)
The overcurrent protection is implemented by monitoring the CSA output with the OCP comparator, as shown in
Figure 4. The current-sensing circuit has a gain of 200mV/A, from the P-channel MOSFET current to the CSA
output. When the CSA output reaches the threshold, the OCP comparator is tripped and turns off the P-channel
MOSFET immediately. The overcurrent function protects the module from a shorted output by monitoring the
current flowing through the P-channel MOSFET.
With the detection of an overcurrent condition, the P-channel MOSFET is immediately turned off and is not turned
on again until the next switching cycle. With the detection of the initial overcurrent condition, the overcurrent fault
counter is set to 1. During the subsequent cycle, if another overcurrent condition is detected, the OC fault counter
is incremented. If there are 17 sequential OC fault detections, the module shuts down under an overcurrent fault
condition. An overcurrent fault condition results in the module attempting to restart in Hiccup mode within the
delay of eight soft start-up periods. At the end of the eighth soft start-up wait period, the fault counters are reset
and soft start-up is attempted again. If the overcurrent condition goes away during the delay of eight soft start-up
periods, the output resumes back into regulation after the Hiccup mode expires as shown in Figure 34.
8ms
VOUT 1V/Div
IIN 2A/Div
PG 5V/Div
500µs/Div
Figure 34. OCP Response; Output Short-Circuited from No Load to Ground and Released, VOUT = 1.2V
5.4
Negative Current Protection
Similar to overcurrent, the negative current protection is realized by monitoring the current across the low-side
N-channel MOSFET, as shown in Figure 4. When the valley point of the inductor current reaches -3A for four
consecutive cycles, both P-channel MOSFET and N-channel MOSFET are turned off. The 100Ω in parallel to the
N-channel MOSFET activates discharging the output into regulation. The control begins to switch when output is
within regulation.
5.5
Power-Good
Power-Good (PG) is the open-drain output of a window comparator that continuously monitors the module output
voltage. PG is actively held low when EN is low and during the module soft start-up period. After the 1ms delay of
the soft start-up period, PG becomes high impedance as long as the output voltage is within the nominal
regulation voltage set by VFB. During an output overvoltage fault condition (output voltage is 33% higher than
nominal value) or an output undervoltage fault condition (output voltage is 15% lower than nominal value), PG is
pulled low. Any fault condition forces PG low until the fault condition is cleared during soft start-up. For logic level
output voltages, connect an external pull-up resistor between PG and VIN. A 100kΩ resistor works well in most
applications.
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RAA210040 Datasheet
5.6
Undervoltage Lockout (UVLO)
When the input voltage is below the Undervoltage Lockout (UVLO) threshold, the module is disabled.
5.7
Soft Start-Up
The soft start-up reduces the inrush current during soft start-up. The soft-start block outputs a ramp reference to
the input of the error amplifier. This voltage ramp limits the inductor current and the output voltage rise time so that
the output voltage rises in a controlled fashion. When VFB is less than 0.1V at the beginning of the soft start-up,
the switching frequency is reduced to 200kHz, so that the output can start-up smoothly at light load conditions.
The RAA210040 supports pre-biased output condition during soft start-up. The default soft start-up period is
approximately 1ms.
5.8
External Synchronization Control
The operating frequency can be synchronized up to 4MHz by an external signal applied to the SYNC pin. The
rising edge of the SYNC signal triggers the rising edge of the PWM ON pulse. To ensure proper operation,
Renesas recommends using an external SYNC frequency within ±25% of the switching frequency set by the FS
pin.
1.5MHz
VSYNC 2V/Div
VOUT 10mV/Div
500ns/Div
Figure 35. External Frequency Synchronization Waveform, VIN = 5V, VOUT = 1.2V, fSYNC = 1.5MHz, IOUT = 0A
5.9
Enable
The enable (EN) input allows you to control the turning on or off of the module for purposes such as power-up
sequencing. When the module is enabled, there is typically a 600µs delay for waking up the bandgap reference,
and then the soft start-up begins. EN should be held below the logic input low until VIN exceeds VUVLO rising
threshold.
5.10 Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is set, the discharge function is to ensure a defined
down-ramp of the output voltage and keep the output voltage close to 0V. The output voltage is discharged to
SGND through an internal 100Ω switch.
5.11
100% Duty Cycle
The RAA210040 features a 100% duty cycle operation to minimize the switching losses. When the input voltage
drops to a level that the RAA210040 can no longer maintain regulation at the output, the module completely turns
on the P-channel MOSFET. This is particularly useful in battery-powered applications to make full use of the
battery voltage and maximize the operation time.
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RAA210040 Datasheet
5.12 Thermal Shutdown
The RAA210040 has built-in thermal protection. When the internal temperature reaches +150°C, the module shuts
down. Both MOSFETs are turned off and PG goes low. As the temperature drops to +125°C, the RAA210040 resumes
operation by stepping through the soft start-up.
6.
6.1
Application Information
Output Voltage Programming
The output voltage of the module is programmed by an external resistor divider (R1 and R2 in Figure 3). R2
combined with the internal 100kΩ 0.5% resistor connected from FB to VSENSE forms a resistor divider that sets
the output voltage. The output voltage is governed by Equation 2.
(EQ. 2)
R2 + R1
V OUT = V REF --------------------R
2
Note: The output voltage accuracy is also dependent on the resistor accuracy of R1 and R2. You need to select
high accuracy resistors to achieve the overall output accuracy.
Table 3. Output Voltage Resistor Settings
6.2
VOUT (V)
R1 (kΩ)
R2 (kΩ)
0.6
100
open
0.8
100
301
0.9
100
200
1.0
100
150
1.2
100
100
1.5
100
66.5
1.8
100
49.9
2.5
100
31.6
3.3
100
22.1
Switching Frequency Selection
With varieties of input and output voltage combinations, you must choose wisely on which frequency to operate at
according to the specific applications. The selection of switching frequency for each VIN and VOUT combination
needs to take into account a few trade-offs. Generally, lower switching frequency leads to higher efficiency at the
cost of higher output voltage ripple. Do not decrease the switching frequency too low because of the negative
current protection limit. Do not increase the switching frequency too high because of the minimum on-time limit,
especially at low VOUT. Moreover, when the output voltage is relatively high, low switching frequency results in
more sub-harmonic oscillation. Therefore, operating frequency needs to be kept relatively high under high VOUT
conditions. However, to ensure better thermal performance, the switching frequency cannot be increased too
much.
6.3
Input Capacitor Selection
The selection of the input filter capacitor is based on how much ripple the supply can tolerate on the DC input line.
The larger the capacitor, the less ripple expected; however, you need to consider the higher surge current during
power-up. The RAA210040 provides a soft start-up function that controls and limits the current surge. The total
capacitance of the input capacitor is calculated using Equation 3:
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RAA210040 Datasheet
(EQ. 3)
IO D 1 – D
C IN MIN = ---------------------------------V P-P f SW
where:
▪ CIN(MIN) is the minimum required input capacitance (µF)
▪ IO is the output current (A)
▪ D is the duty cycle
▪ VP-P is the allowable peak-to-peak input voltage (V)
▪ fSW is the switching frequency (Hz)
Renesas recommends placing a low Equivalent Series Resistance (ESR) ceramic capacitor as close as possible
to the module input. This input capacitor reduces voltage ringing created by the switching current across parasitic
circuit elements. It also reduces the input noise seen by the module. Moreover, you need to consider the estimated
RMS ripple current in choosing ceramic capacitors. The RMS ripple current is calculated using Equation 4.
(EQ. 4)
Io D 1 – D
I IN RMS = --------------------------------
Each 22µF X7R ceramic capacitor is typically good for 2A to 3A of RMS ripple current. See the capacitor
datasheet for the RMS current ratings.
Based on the previous considerations, a minimum total input capacitance of 2x22µF is required for the
RAA210040. Add additional capacitance if possible. Use X7R ceramic capacitors. The placement of the input
ceramic capacitors should be as close as possible to the module input. See PCB Layout Pattern Design for more
information. A bulk input capacitance may also be needed if the input source does not have enough output
capacitance. The typical value of a bulk input capacitor is 47µF. In such conditions, this bulk input capacitance can
supply the current during output load transient conditions.
6.4
Output Capacitor Selection
Ceramic capacitors with low ESR are typically used as the output capacitors for the RAA210040. To keep the low
resistance up to high frequencies and to get narrow capacitance variations with the temperatures, Renesas
recommends using dielectric X7R or equivalent. See Table 2 for recommended output capacitor values. Bulk
output capacitors that have adequately low ESR, such as low ESR polymer capacitors or a low ESR tantalum
capacitor, can also be used in combination with the ceramic capacitors, depending on the output voltage ripple
and transient requirements.
7.
Layout Guidelines
Careful attention to layout requirements is necessary for successful implementation of the RAA210040 power
module. The RAA210040 operates at high switching frequencies. Therefore, an optimized layout can minimize the
impacts of high di/dt and dv/dt. Conversely, a poor layout can lead to poor regulation (both line and load),
degraded efficiency, increased EMI radiation, noise sensitivity, and thermal stress.
7.1
Layout Considerations
The following are the layout considerations.
▪ Place the input ceramic capacitors as close as possible to the module input. These ceramic capacitors
minimize the high frequency noise by reducing the parasitic inductance of the power loop. Proper placement of
these capacitors not only leads to less PHASE node spikes and ringing, but also minimizes the switching noise
coupled to the module. Renesas recommends using dielectric X7R or equivalent with a minimum total
capacitance of 44µF at the module input. A layout example is shown in Figure 36 and Figure 37.
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RAA210040 Datasheet
▪ Use large copper planes to minimize conduction loss and thermal stress for VIN, VOUT, and PGND. Use
multiple vias to connect the power planes in different layers.
▪ Use a separate SGND plane for components that are connected to SGND. Connect SGND and PGND at a
single point on the top layer as shown in Figure 38.
▪ Use a remote-sensing trace to connect to the point-of-load and achieve tight output voltage regulation. Route
the remote-sensing trace underneath the PGND layer and avoid routing it near noisy planes. Place a 2Ω
resistor close to the output voltage resistor divider and FB pin to damp the noise on the trace.
CIN
PGND
CIN
VIN
COUT
COUT
COUT
VOUT
PGND
Figure 36. Layout Example - Top Layer
VIN
PGND
CIN
U1
SGND
Figure 37. Layout Example - Bottom Layer
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RAA210040 Datasheet
RAA210610
SGND Pad
PGND
Inner Layer
SGND
Inner Layer
RAA210610
PGND Pad
Inner Layer
Slots in PCB
Figure 38. Layout Example - SGND is Connected to PGND at Single Point
7.2
Thermal Considerations
Experimental power loss curves, along with JA from thermal modeling analysis, can evaluate the thermal
consideration for the module. The derating curves are derived from the maximum power allowed while
maintaining the temperature below the maximum junction temperature of +120°C. In applications in which the
system parameters and layout are different from the evaluation board, the customer can adjust the margin of
safety. All derating curves are obtained from tests on a 4-layer thermal test board 4.5x3 inches in size with 2oz
copper on both top and bottom layers and 1oz copper on internal layers. See TB379 for more details. In the actual
application, other heat sources and design margins should be considered.
8.
Package Description
The RAA210040 is integrated into a 10 Lead Dual Flat Embedded Laminate Package with exposed copper
thermal pads. This package has such advantages as good thermal and electrical conductivity, low weight, and
small size. The package is applicable for surface mounting technology and is becoming more common in the
industry. The embedded laminate substrate and inductor are overmolded with a polymer mold compound to
protect these devices.
The package outline, typical PCB layout pattern, and typical stencil pattern design are shown in the Package
Outline Drawing.
R70TB0004EU: PCB Design and Assembly Recommendations for Renesas Power Modules shows the typical
reflow profile parameters. These guidelines are general design rules. You can modify parameters according to
your specific application.
8.1
PCB Layout Pattern Design
The bottom of RAA210040 is an embedded laminate substrate, which is attached to the PCB by surface
mounting. The PCB layout pattern is in the Y10.3x3 Package Outline Drawing. The PCB layout pattern is
essentially 1:1 with the package exposed pad and the I/O termination dimensions, except that the PCB lands are
slightly longer than the dual flat embedded laminate package terminations by about 0.3mm. This extension allows
for solder filleting around the package periphery and ensures a more complete and inspectable solder joint. The
thermal lands on the PCB layout should match 1:1 with the package exposed die pads.
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RAA210040 Datasheet
8.2
Thermal Vias
Place a grid of 1.0mm to 1.2mm pitched thermal vias, which drops down and connects to buried copper planes
under the thermal land. The vias should be about 0.3mm to 0.33mm in diameter, with the barrel plated to about
2.0 ounce copper. Although adding more vias (by decreasing pitch) improves thermal performance, it also
diminishes results as more vias are added. Use only as many vias as needed for the thermal land size and as
your board design rules allow.
8.3
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have about a 50µm to 75µm (2 mil to 3 mil) standoff
height. The solder paste stencil design is the first step in developing optimized, reliable solder joins. The stencil
aperture size to land size ratio should typically be 1:1. Reduce the aperture width slightly to help prevent solder
bridging between adjacent I/O lands.
Renesas recommends using an array of smaller apertures instead of one large aperture to reduce the solder
paste volume on larger thermal lands. The stencil printing area should cover 50% to 80% of the PCB layout
pattern. Consider the symmetry of the whole stencil pattern when designing the pads.
Renesas recommends using a laser-cut, stainless-steel stencil with electropolished trapezoidal walls.
Electropolishing smooths the aperture walls, resulting in reduced surface friction and better paste release, which
reduces voids. Using a Trapezoidal Section Aperture (TSA) also promotes paste release and forms a brick-like
paste deposit, which assists in firm component placement.
8.4
Reflow Parameters
Renesas recommends using a No Clean Type 3 solder paste, per ANSI/J-STD-005 because of the low mount
height of the package. Nitrogen purge is also recommended during reflow. A system board reflow profile depends
on the thermal mass of the entire populated board, therefore, it is not practical to define a specific soldering profile
just for the package. The profile given in R70TB0004EU is provided as a guideline to customize for varying
manufacturing practices and applications.
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RAA210040 Datasheet
9.
Package Outline Drawing
For the most recent package outline drawing, see Y10.3x3.
Y10.3x3
10 Lead Dual Flat Embedded Laminate Package
Rev 1, 9/20
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RAA210040 Datasheet
10. Ordering Information
Part
Part Number[1][2]
RAA2100404GLG#HD0
0040
RAA2100404GLG#MD0
RTKA210040DR0000BU
Package Description[3]
(RoHS Compliant)
Marking
10 Lead Dual Flat Embedded
Laminate Package
Pkg.
Dwg. #
Carrier
Type[4]
Junction
Temperature
Y10.3x3
Reel, 3k
-40 to +125
Reel, 1k
Demonstration Board
1. These plastic packaged products are RoHS compliant by EU exemption 7C-I and employ special Pb-free material sets; molding
compounds/die attach materials and NiPdAu plate - e4 termination finish which is compatible with both SnPb and Pb-free soldering
operations. RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J-STD-020.
2. For Moisture Sensitivity Level (MSL), see the RAA210040 device page. For information about MSL, see TB363.
3. For the Pb-Free Reflow Profile, refer to R70TB0004EU.
4. See TB347 for details about reel specifications.
11. Revision History
Rev.
Date
1.01
Jun 15, 2023
Description
Changed all references for TB493 to R70TB0004EU.
Updated the package description throughout document.
1.00
Apr 13, 2021
Initial release
R16DS0137EU0101 Rev.1.01
Jun 15, 2023
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