RAA2231814GSP#HA0

Datasheet RAA223181 900V Off-Line Flyback Regulator The RAA223181 is an off-line Flyback regulator with a 900V integrated MOSFET, designed for high input voltage and high reliability application of smart meter power supplies and other general isolated power supplies. The RAA223181 operates in DCM with constant switching frequency at full load. The system is inherently stable with an easy feedback loop design, while switching at constant frequency without interfering the communication of the smart meter. At light load, RAA223181 enters burst mode operation to reduce the IC power consumption, while keeping the burst frequency less than 3kHz to avoid interference to the PLC frequency band. RAA223181 features a unique short-time heavy load operation mode, which delivers up to 12W output power for a programmed time period. This allows the smart meter power supply to be designed at regular power level without being over-designed for 2x power in the transmission mode, which greatly reduces system cost. RAA223181 also has a cost-saving feature for the input voltage higher than 265VAC, where usually two stacked 400v electrolytic capacitors are required after the bridge rectifier. RAA223181 uses only one 400V capacitor. The IC detects the over-voltage and disconnect the input capacitor from the DC bus with a MOSFET and stop switching. This saves the cost on expensive high voltage electrolytic capacitors. In addition, the RAA223181 adopts valley switching technique to reduce the switching losses to improve thermal performance at high temperature operation. Besides it also features input brown-out protection, output overload, short circuit, VccUV, VccOV, VinUV, peak current limit, primary short, and over-temperature protections. Features ▪ Flyback regulator with 900V 10Ω MOSFET ▪ Single 400V input capacitor for input up to 450VAC ▪ Frequency doubling for heavy load operation (up to 12W), with programmable duration 0.7V, switching frequency = 50kHz, D = 0.48 660 810 µA 500 570 mV VCC Quiescent Current VCC Current During Switching IVCC_Q IVCC IC stop switching Current Sense Max Current Sensing Threshold VCS_MAX VFB = 4V, 425 SCP Threshold VCS_SC 1000 mV Minimum Current Sensing Threshold VCS_MIN 75 mV Leading Edge Blank Time tLEB 300 350 570 ns Feedback Transconductance GM FB Pin Pull-Up Resistor RFB FB Threshold Entering Burst Mode VFB to VCS 0.225 V/V 24 35 kΩ VBURL 400 500 600 mV FB Threshold Exiting Burst Mode VBURH 650 750 850 mV FB Threshold Into 2x Frequency VFB_2XF 2.6 3.2 4 V FB Threshold Out of 2x Frequency VFB_1XF 2 2.6 3.2 V FB Threshold for Overload Protection VFB_OLP 3.6 4 4.8 V FB Internal Pull-Up Voltage VFB_MAX 4.4 4.9 V Programmable Heavy Load OVL Pin Source Current OVL Pin Discharge Current R16DS0195EU0100 Rev.1.00 Oct 13, 2021 IOVL IOVL_D 10.5 1.8 2 11.8 µA µA Page 6 RAA223181 Datasheet Typical operating conditions at 25°C, VCC = 12V, TJ = -40 to +125°C, unless otherwise specified. (Cont.) Parameter OVL Pin Threshold Symbol Test Conditions VOVL Min[1] Typ Max[1] Unit 3.6 4 4.6 V Input Undervoltage and Overvoltage Protection PRO Pin UV Rising Threshold VBUSUV_R 0.4 0.5 0.6 V PRO Pin UV Falling Threshold VBUSUV_F 0.33 0.4 0.48 V PRO Pin OV Threshold (Rising) VBUSOV_R 3.9 4.5 5.2 V PRO Pin OV Falling Hysteresis VBUSOV_HYS 0.4 0.5 0.6 V TBUSOV_DL 1.4 1.6 OV Falling Delay CDRV Driver Low-Side On-Resistance RDS_L 17 CDRV Driver Source Current IDRVS 25 ms 32 Ω mA Frequency FSET Pin Reference Voltage Oscillator Frequency VFSET fSW Dithering Double Frequency RFSET = 187k Percent frequency fSW_2x 2.3 2.5 2.7 V 42.5 49 55 kHz 4 % 98.5 kHz 1000 kHz 54 % -4 86 93 Valley Detection Ringing frequency Assured by design 550 fSW = 50kHz 42 Timing Maximum Duty Cycle DMAX OVL Blanking TOVL_BLK Startup Timer 48 2 Cycles, 50kHz 40 µs TST 4096 cycles, 50kHz 82 ms Hiccup Restart Delay THICC 16384 cycles, 50kHz 328 ms OLP/OCP Delay Timer TOLP 2048 cycles, fSW = 100kHz, VFB>4.5V 20.5 ms 2048 cycles, fSW = 100kHz 20.5 ms VinUV Delay Timer TVINUV Thermal Over-Temperature Threshold OTPTH 150 C Over-Temperature Hysteresis OTPHYS 30 C 1. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 7 RAA223181 Datasheet 4. Typical Performance Graphs 4.1 Characterization Curves 1,050 1,030 Rdson(Ω) BVDSS (V) 990 970 950 930 rDS(ON) (Ω) 1,010 910 890 870 850 -40 -25 -10 5 20 35 50 65 80 95 24 22 20 18 16 14 12 10 8 6 4 2 0 -40 110 125 -25 -10 5 Temperature (°C) Figure 3. Breakdown Voltage vs Temperature 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 4. rDS(ON) vs Temperature 6.0 510 5.5 500 5.0 VCS_MAX (mV) IVCC Start (mA) 4.5 4.0 3.5 3.0 2.5 2.0 490 480 470 460 1.5 1.0 450 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (°C) 50 65 80 95 110 125 Figure 6. Maximum Current Sensing Threshold vs Temperature 0.426 4.69 0.423 4.66 4.63 0.420 VBUSOV_R(V) VBUSUV_F (V) 35 Temperature (°C) Figure 5. VCC Start Current vs Temperature 0.417 0.414 0.411 4.60 4.57 4.54 4.51 0.408 4.48 4.45 0.405 -40 -25 -10 5 20 35 50 65 80 95 -40 110 125 -25 -10 5 Figure 7. PRO Undervoltage Falling vs Temperature Switching Frequency (kHz) 4.18 4.16 4.14 4.12 4.10 4.08 4.06 4.04 4.02 4.00 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 9. BUS Overvoltage Falling vs Temperature R16DS0195EU0100 Rev.1.00 Oct 13, 2021 35 50 65 80 95 110 125 Figure 8. BUS Overvoltage Rising vs Temperature 4.20 -40 20 Temperature (C) Temperature (°C) VBUSOV_F(V) 20 52.0 51.5 51.0 50.5 50.0 49.5 49.0 48.5 48.0 47.5 47.0 46.5 46.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 10. Switching Frequency vs Temperature (RFSET = 187k) Page 8 RAA223181 Datasheet 4.2 Typical Waveforms VIN = 230VAC, VO = 13V, IO = 450mA, LPRI = 1.3mH, CO = 1000uF, TA = 25C VS 60mV/Div VS 50mV/Div VFB 200mV/Div VOUT 2V/Div VCC 2V/Div VD 50V/Div 10ms/Div 4ms/Div Figure 11. Startup Figure 12. Light Load Operation VOVLD 500mV/Div 100mV/Div VS 55mV/Div 2V/Div VOUT 1.4V/Div 50V/Div IOUT 110mA/Div 10µs/Div 100ms/Div Figure 13. Full Load Operation Figure 14. Short-Time Heavy Load Operation VS 60mV/Div VBUS 20V/Div VS 60mV/Div VOUT 2V/Div VCC 2V/Div VOUT 2V/Div 200ms/Div 4ms/Div Figure 15. Short-Circuit/Overload Protection Figure 16. Input Brownout Protection (VIN = 80VAC) CDRV 2V/Div VOUT 100mV/Div VS 50mV/Div VBUS 100V/Div IOUT 100mA/Div PRO 650mV/Div 10ms/Div 20ms/Div Figure 17. BUS Overvoltage Protection Figure 18. Load Transient (45mA-450mA) R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 9 RAA223181 Datasheet 85 13.05 80 13.04 75 13.03 70 13.02 65 VOUT (V) Efficiency (%) VIN = 230VAC, VO = 13V, IO = 450mA, LPRI = 1.3mH, CO = 1000uF, TA = 25C 60 55 50 13.01 13.00 12.99 12.98 45 40 120Vac 12.97 120Vac 35 230Vac 12.96 230Vac 30 12.95 0 50 100 150 200 250 300 Load Current (mA) 350 400 450 0 50 Figure 19. Efficiency 5. 100 150 200 250 300 Load Current (mA) 350 400 450 Figure 20. Load Regulation Detailed Description The RAA223181 adopts constant frequency switching with secondary side regulation as Figure 21 shows. When power is less than 7W, it operates in DCM at the chosen switching frequency. When the power is bigger than 7W, it operates in CCM at the doubled frequency for a programmed time ( VFB_2XF, oscillator frequency is doubled, valley detection is disabled, and the part operates in CCM. At the same time, a programmable timer starts - an internal 10µA current charges the external capacitor on pin OVL. When the OVL pin reaches VOVL, the heavy load operation stops, and the IC waits for 5 times the programmed heavy load operation time before the heavy load operation is allowed again. When VFB < VFB_1XF, the part exits heavy load operation even before the heavy load timer expires. If the load is too heavy, FB continues rising to VFB_OLP, the heavy load operation stops, and the overload protection is triggered. The operation is shown in Figure 24. VOVL VOVL IOUT 0mA VOUT IPK_MAX IL VFB_2XF VFB VFB_1XF 0V Figure 24. Short-Time Heavy Load Operation Single capacitor operation for input overvoltage: The IC features a capacitor saving feature by employing an optional external MOSFET driven by the CDRV pin. The FET is connected in series with a 400V input buffer capacitor, as shown in Figure 29. The FET is on in normal operation. When the input has a voltage over the maximum operating voltage, sensed by the PRO pin through a resistor divider, the FET is turned off and disconnected the buffer capacitor from the BUS, protecting the capacitor from by overvoltage damage. When the bus voltage drops low enough, the IC resumes switching. The FET is initially off at the startup, controlled by a low R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 11 RAA223181 Datasheet CDRV, until the bus voltage is pulled down low enough by the switching current, it is turned on with minimum voltage and current stresses. Also, the inrush current is reduced. The operation is illustrated in Figure 25. CDRV 400V VBUS Vbus_low 0V IPRI VCAP 0V Figure 25. Input Overvoltage Protection and Zero-Voltage Turn-On/Off Buffer Capacitor MOSFET This feature allows the customer to use only one 400V buffer capacitor and a 650V MOSFET to sustain an input bus overvoltage event up to 650V, which can be caused by a wrong 265VAC input phase-to-phase connection, without using two stacked 400V buffer capacitors of twice the capacitance. This saves an expensive 400V capacitor with a cheaper power MOSFET. 5.1 Soft Start-Up When the input voltage (rectified bus) is higher than 50V or so, the IC starts up with the VCC capacitor being charged by an internal HV current source. When VCC reaches up to VCC_START, the IC begins switching, and a startup timer begins (~82ms). At the same time, the internal HV regulator turns off until VCC drops below 9V then it turns on again. Before the timer expires, the DCM operation with constant max peak current is enforced to ensure a soft start-up. The SCP is disabled during the start-up blanking time. When VOUT is fully established, VCC is supplied by the auxiliary winding, and the internal HV current source is off most of the time in steady-state operation to save power consumption. The startup process is illustrated in Figure 26. CDRV VBUS 50V VCC_START VCC_HVON VCC ID IPK VOUT Startup Figure 26. Start-Up Diagram R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 12 RAA223181 Datasheet 5.2 Overload and Short-Circuit Protection If an overload or a short-circuit occurs, VFB rises high. When VFB reaches to VFB_2XF, the heavy load operation is enabled with twice the switching frequency. If VFB continues to rise and reach to another threshold VFB_OLP, and current sense detected above VCS_MAX after a blanking time, a fault delay timer starts. If these thresholds are still reached after the timer expires (~20.5ms), the heavy load operation is disabled, and the IC stops switching for a hiccup time (~328ms). The IC resumes switching after the timer expires. The logic sequence is shown in Figure 27. VOUT VFB 0V VFB_OLP VFB_2XF VCC VCC_START VCC_HVON 0V IPK_MAX IPRI IOUT 0 OLP Delay Time Hiccup Time Startup Time Figure 27. Overload Protection Diagram R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 13 RAA223181 Datasheet 6. Application Topologies TR1 + COUT RB1 RB2 CB2 + CVCC RDET1 RDET2 + C1 VCC PRO VDET D HV Q1 CDRV S FSET OVLD FB RF RS TL431 COVL GND Figure 28. RAA223181 Flyback with BUS Overvoltage Protection TR1 + COUT RB1 RB2 C1 CB2 + CVCC RDET2 + VCC HV C2 RDET1 VDET D PRO + RF CDRV S FSET OVLD FB RS TL431 COVL GND Figure 29. RAA223181 Flyback without the capacitor MOSFET R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 14 RAA223181 Datasheet 7. 7.1 Design Guidance Input Buffer Capacitor The input buffer capacitor provides a DC voltage with less voltage ripple for a given power. For example, how low the bus voltage can drop to determines the power Flyback can deliver. Equation 1 calculates the required minimum bus valley voltage for the target output power, where IPKFL is the peak current required for your full load operation.  is the assumed full load efficiency at 85VAC. (EQ. 1) 2P OUT V valley = ------------------------------------I PKFL D MAX To keep the bus valley above this value, the buffer capacitance needs to be large enough to not only support normal output power but also a short-time heavy load up to 2x normal output power. The required capacitance is then calculated using Equation 2, . (EQ. 2) 7.2 2V acmin – V valley  1 - 2P OUT  0.25 + ------ asin -------------------------------------------------2   2V acmin C in = ------------------------------------------------------------------------------------------------------------------V acmin  2V acmin – 40 f LINE Transformer Primary Inductance and Turns Ratio Since the regulator operates in DCM operation, the primary inductance has to be small enough so that the inductor current always resets within a switching cycle while still large enough to deliver enough power at minimum AC input. Accordingly, the required primary inductance is calculated using Equation 3, while Equation 4 specifies its maximum value. To avoid subharmonics in 2x frequency operation at the minimum input voltage, LP must be smaller than 1.6mH according to the slope compensation. (EQ. 3) D MAX V valley L P  ------------------------------------f SW I PKFL (EQ. 4) D MAX V valley L P  -------------------------------------------------------------f SW  2I PKFL – I PKMAX  Since the bus voltage can be as low as 40V when operating in CCM for short-time heavy load at low input line, the transformer turns ratio needs to be set properly so duty cycle is not too big to maintain the require output voltage. Therefore, the maximum turns ratio is calculated using Equation 5. If Dmax is chosen as 0.67, and VHVMIN = 40V, Nmax = 6.25. (EQ. 5) D MAX V HVMIN N  -----------------------  -------------------------Vo 1 – D MAX In the meantime, the turns ratio needs to large enough so that the maximum peak current can fully reset when Dmax is reached at the valley of the minimum AC input. The minimum turns ratio needs to satisfy Equation 6. (EQ. 6) L P I PKFL f SW N  -------------------------------------- 1 – D MAX V O R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 15 RAA223181 Datasheet 7.3 Current Sensing Resistor The peak current is sensed through RSENSE on the S pin and compared with the internal current command. When the sensed voltage reaches the command, the MOSFET is turned off. With the chosen RSENSE, the maximum peak current is limited by an internal current sense voltage limit, VCS_MAX. To have a good regulation without hitting peak current limit, VSENSE should be set around 0.9VCS_MAX. RSENSE is calculated using Equation 7. Note: RSENSE must be evaluated for proper power capability. (EQ. 7) 7.4 0.9V CSMAX R SENSE = --------------------------------I PKFL FSET Pin Resistor The FSET pin resistor sets the switching frequency. The resistor value is calculated using Equation 8. (EQ. 8) 7.5 3.72V FSET 6 R FSET = ------------------------------- 10  k  f SW VDET Pin Resistors The valley switching is detected at VDET pin by resistor dividers, RDET1 and RDET2. RDET1 is calculated using Equation 9 and RDET2 is calculated using Equation 10. NPA is the turns ratio of primary winding to auxiliary winding, and VACMAX is the maximum AC input voltage. NSA is the turns ratio of the output winding to the auxiliary winding. VDF is forward voltage of the output diode. (EQ. 9) 2V ACMAX R DET1  --------------------------------  k  N PA (EQ. 10) R DET1  5 R DET2  ------------------------------------------V DF + V OUT ---------------------------------–5 N SA 7.6 PRO Pin Resistors The PRO pin sets the VIN OV threshold and VIN UV threshold. The resistor divider needs to ensure the VIN OV protection at right bus voltage. (EQ. 11) V BUSOV – V BUSOV_R R B1 = -----------------------------------------------------------  R B2 V BUSOV_R VBUSOV is the maximum bus voltage allowed and is usually chosen slightly above the voltage rating of the input capacitor, C1, but below 110% of the rated capacitor voltage if the input capacitor has to be protected by the CDRV feature. To minimize the power dissipation, RB2 is usually chosen between 5k-25kΩ. When RB1, RB2 are chosen, the VIN UV threshold is set around 50V and 40V for VIN rising and falling, respectively. 7.7 PRO Pin Capacitor The capacitor at the PRO pin, CB2, helps filter out the noise to ensure normal operation of the IC. It also delays the voltage rise on the PRO pin when an input surge occurs, so it does not trigger OV protection and keeps the bulky capacitor connected to the BUS using the external FET. The capacitance of CB2 is calculated using Equation 12, where VPROMAX = Vacmax*√2*RB1/(RB1+RB2). (EQ. 12) 30 C B2  ------------------------------------------------------------------------------------------------------------------------------------------------------------------------  F  R  R V  B1   –1 B2 BUSOVR – V PROMAX  -----------------------------  ln  1 – ---------------------------------------------------------------------------------------------------- 625  R B2   R B1 + R B2  – V PROMAX  R B1 + R B2  R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 16 RAA223181 Datasheet 7.8 MOSFET in Series with C1 The MOSFET in series with C1 is turned off during the input OV; therefore, it needs to have the voltage rating of 650V, so it can sustain a voltage as high as the rectified voltage of 450VAC input. Also, it needs to survive lightning events when a surge current passes through. Together with input surge energy absorbing components, the FET needs to have at least 200V at 10A pulse conduction rating, specified by its SOA curve. For details about the input stage design recommendation for surge energy control, see the evaluation board manual. 7.9 OLV Pin Capacitor The capacitor on the OLV programs the time duration when the short-time over load is allowed, which is recommended not more than 100ms. The capacitor value, COVL, is calculated using Equation 13. If a much longer time duration is programmed by using a cap bigger than what Equation 13 specifies, or shorting the pin to ground, the heavy load the IC can support may be limited by its thermal capability on a given PCB, especially at low AC input and high ambient temperature. If heavy load support is not required, the OVL pin can be floated. Therefore, the IC always operates with the constant frequency set by RFSET. (EQ. 13) I OVL C OLV  ---------------------10V OVL 7.10 Output Capacitance The minimum output capacitance is chosen by consideration of switching ripple, step load response, and in some applications, the required output hold-time when input is cut off. 7.11 PCB Layout Guidance Proper layout is important to ensure a stable operation, good thermal behavior, EMI performance, and reliable operation for various operating environments. Pay attention to the following layout recommendations. ▪ Leave proper spacing (recommend minimum 2mm) between high voltage (maximum 900V) traces and low voltage traces ▪ Keep a small loop from the input filter capacitor to IC, transformer primary winding, and to the ground of input capacitor, and a small loop consisted of transformer secondary winding, output capacitor, and output diode. ▪ Keep enough copper area on the IC drain pin (not less than 165mm2 for 6W output power) for better thermal performance. ▪ Place the VCC decoupling capacitor close to the VCC pin. R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 17 RAA223181 Datasheet The PCB layout example is shown in Figure 30 and Figure 31. Figure 30. PCB Top Layer Figure 31. PCB Bottom Layer R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 18 RAA223181 Datasheet 8. EMI Performance Conducted EMI pre-compliance for EN55022/CISPR22 (VOUT = 13V, IOUT = 450mA) Figure 32. Line, 120VAC Figure 33. Line, 230VAC Figure 34. Neutral, 120VAC Figure 35. Neutral, 230VAC R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 19 RAA223181 Datasheet 9. Package Outline Drawing For the most recent package outline drawing, see M13.15. M13.15 13 Lead Narrow Body Small Outline Plastic Package Rev 0, 6/20 R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 20 RAA223181 Datasheet 10. Ordering Information Part Number[1][2] RAA2231814GSP#HA0 Part Package Description Marking (RoHS Compliant) Pkg. Dwg. # Carrier Type[3] Temp Range 13 Ld SOIC M13.15 Reel, 2.5k -40 to +150°C 223181 RAA2231814GSP#MA0 RTKA223181DE0010BU Reel, 250 Evaluation Board 1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 2. For the Moisture Sensitivity Level (MSL), see the RAA223181 device page. For more information about MSL, see TB363. 3. See TB347 for details about reel specifications. 11. Revision History Rev. Date 1.00 Oct 13, 2021 Description Initial release R16DS0195EU0100 Rev.1.00 Oct 13, 2021 Page 21 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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