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RD74LVC126BFPEL

RD74LVC126BFPEL

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

  • 描述:

    RD74LVC126BFPEL - Quad. Bus Buffer Gates with 3-state Outputs - Renesas Technology Corp

  • 数据手册
  • 价格&库存
RD74LVC126BFPEL 数据手册
RD74LVC126B Quad. Bus Buffer Gates with 3-state Outputs REJ03D0499–0200 Rev.2.00 Dec. 10, 2004 Description The RD74LVC126B has four bus buffer gates in a 14 pin package. The device requires the three state control input OE to be taken low to put the output into the high impedance condition. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features VCC = 1.65 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±12 mA (@VCC = 2.7 V) ±24 mA (@VCC = 3.0 V to 5.5 V) • Ordering Information Part Name RD74LVC126BFPEL RD74LVC126BTELL Package Type SOP–14 pin (JEITA) TSSOP–14 pin Package Code FP–14DAV TTP–14DV Package Abbreviation FP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel) • • • • • • Function Table Inputs OE L H H H: L: X: Z: High level Low level Immaterial High impedance X L H A Z L H Outputs Y Rev.2.00 Dec. 10, 2004 page 1 of 8 RD74LVC126B Pin Arrangement 1OE 1 1A 1Y 2 3 14 V CC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y 2OE 4 2A 2Y GND 5 6 7 (Top view) Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg –0.5 to 7.0 –50 –0.5 to 7.0 –50 50 –0.5 to VCC +0.5 –0.5 to 7.0 ±50 ±100 –65 to +150 mA mA °C V Ratings V mA V mA VO = –0.5 V VO = VCC +0.5 V Output "H" or "L" Output "Z" or VCC: OFF VI = –0.5 V Unit Conditions Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00 Dec. 10, 2004 page 2 of 8 RD74LVC126B Recommended Operating Conditions Item Supply voltage Input / output voltage Symbol VCC VI VO Operating temperature Output current Ta IOH Ratings 1.5 to 5.5 1.65 to 5.5 0 to 5.5 0 to VCC 0 to 5.5 –40 to 85 –4 –8 –12 –24 IOL 4 8 12 24 Input rise / fall time *1 Note: tr, tf 20 10 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. ns/V mA °C mA VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 1.65 V to 2.7 V VCC = 3.0 V to 5.5 V V V Output "H" or "L" Output "Z" or VCC: OFF V Unit Data hold At operation Conditions Rev.2.00 Dec. 10, 2004 page 3 of 8 RD74LVC126B Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VIH VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 Output voltage VOH 1.65 to 5.5 1.65 2.3 2.7 3.0 3.0 4.5 VOL 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 Input current Output leak current Off state output current IIN IOFF IOZ 0 to 5.5 0 2.7 to 5.5 2.7 to 3.6 2.7 to 5.5 ∆ICC 2.7 to 3.6 Min VCC×0.65 — 1.7 2.0 VCC×0.7 — — — — VCC –0.2 1.2 1.7 2.2 2.4 2.2 3.8 — — — — — — — — — — — — — — — VCC×0.35 V 0.7 0.8 VCC×0.3 — — — — — — — 0.2 0.45 0.7 0.4 0.55 0.55 ±5.0 ±5.0 ±5.0 ±5.0 5.0 500 µA µA µA µA µA VIN = 5.5 V or GND VIN / VOUT = 5.5 V VIN = VCC or GND, VOUT = 5.5 V or GND VIN = 3.6 V to 5.5 V VIN = VCC or GND VIN = one input at (VCC –0.6) V, other inputs at VCC or GND V IOL = 100 µA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA IOH = –24 mA V IOH = –100 µA IOH = –4 mA IOH = –8 mA IOH = –12 mA Max V Unit Test Conditions Quiescent supply current ICC Rev.2.00 Dec. 10, 2004 page 4 of 8 RD74LVC126B Switching Characteristics Ta = –40 to 85°C Item Propagation delay time Symbol tPLH tPHL VCC (V) 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Output enable time tZH tZL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Output disable time tHZ tLZ 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Between output pins skew *1 From Unit ns A (Input) Y To (Output) Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.3 1.0 — — — — — — — — — — — — — — — — — — — — — — — — — — — Typ Max 9.8 7.2 5.2 4.7 3.7 10.0 8.3 6.3 5.7 4.7 12.6 8.7 6.7 6.0 5.0 — — — 1.0 1.0 — — pF pF ns ns ns OE Y OE Y tOSLH tOSHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Input capacitance Output capacitance Note: CIN CO 3.3 3.3 4.0 7.0 1. This parameter is characterized but not tested. tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn| Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol CPD VCC (V) 1.8 2.5 3.3 5.0 Min — — — — Typ 21 22 23 27 Max — — — — pF Unit Test conditions f = 10 MHz Rev.2.00 Dec. 10, 2004 page 5 of 8 RD74LVC126B Test Circuit VCC VCC See Function Table Input Output RL CL RL Pulse Generator Zout = 50 Ω S1 OPEN VTT GND Symbol t PLH / t PHL t ZH/ t HZ t ZL / t LZ S1 OPEN GND VTT Note: 1. CL includes probe and jig capacitance. Rev.2.00 Dec. 10, 2004 page 6 of 8 RD74LVC126B Waveforms – 1 tr 90 % Input A Vref 10 % t PLH Vref 90 % Vref 10 % t PHL VOH Output Y Vref VOL tf VIH GND Note: 1. Input waveform : PRR = 10 MHz, duty cycle 50% Waveforms – 2 tr Input OE 10 % t ZL Waveform - A t ZH Waveform - B Vref Vref t HZ VOH – ∆V 90 % Vref 90 % Vref 10 % t LZ tf VIH GND ≈ 1/2 VTT VOL + ∆V VOL VOH ≈ GND INPUTS VCC (V) VCC = 1.8±0.15 V VCC = 2.5±0.2 V VCC = 2.7 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V VI VCC VCC tr/tf Vref VTT CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1.0 kΩ 500 Ω 500 Ω 500 Ω 500 Ω ∆V 0.15 V 0.15 V 0.3 V 0.3 V 0.3 V ≤ 2 ns 1/2 VCC 2× VCC ≤ 2 ns 1/2 VCC 2× VCC 1.5 V 1.5 V 6V 6V 2.7 V ≤ 2.5 ns 2.7 V ≤ 2.5 ns VCC ≤ 2.5 ns 1/2 VCC 2× VCC Notes: 1. Input waveform : PRR = 10 MHz, duty cycle 50% 2. Waveform – A shows input conditions such that the output is "L" level when enable by the output control. 3. Waveform – B shows input conditions such that the output is "H" level when enable by the output control. Rev.2.00 Dec. 10, 2004 page 7 of 8 RD74LVC126B Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 14 8 1 7 5.5 *0.20 ± 0.05 2.20 Max 0.20 7.80 + 0.30 – 1.42 Max 1.15 0˚ – 8˚ 0.70 ± 0.20 1.27 *0.40 ± 0.06 0.12 M Package Code JEDEC JEITA Mass (reference value) FP-14DAV — Conforms 0.23 g *Ni/Pd/Au plating 0.10 ± 0.10 0.15 As of January, 2003 Unit: mm 5.00 5.30 Max 14 8 1 7 0.65 1.0 0.13 M 6.40 ± 0.20 0.83 Max 0˚ – 8˚ 0.50 ± 0.10 *0.20 ± 0.05 4.40 *0.15 ± 0.05 1.10 Max 0.10 0.07 +0.03 –0.04 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) TTP-14DV — — 0.05 g Rev.2.00 Dec. 10, 2004 page 8 of 8 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 http://www.renesas.com © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .2.0
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