RD74LVC138B

RD74LVC138B 3-to-8-line Decoder / Demultiplexer REJ03D0502–0200 Rev.2.00 Jan. 14, 2005 Description The RD74LVC138B has three binary select inputs in a 16 pin package. If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables are provided to ease the cascading of decoders. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features VCC = 1.65 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±12 mA (@VCC = 2.7 V) ±24 mA (@VCC = 3.0 V to 5.5 V) • Ordering Information Part Name RD74LVC138BFPEL RD74LVC138BTELL Package Type SOP–16 pin (JEITA) TSSOP–16 pin Package Code FP–16DAV TTP–16DAV FP T Package Abbreviation Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel) • • • • • Function Table Inputs Enable G1 X X L H H H H H H H H H: L: X: G2A X H X L L L L L L L L Low level Immaterial G2B H X X L L L L L L L L C X X X L L L L H H H H Select B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H Y3 H H H H H H L H H H H Outputs Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L High level Rev.2.00 Jan. 14, 2005 page 1 of 7 RD74LVC138B Pin Arrangement A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8 B C G2A G2B G1 A Y0 Y1 Y2 Y3 Y4 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 Y7 Y6 Y5 (Top view) Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg –0.5 to 7.0 –50 –0.5 to 7.0 –50 50 –0.5 to VCC +0.5 ±50 100 –65 to +150 V mA mA °C Ratings V mA V mA VO = –0.5 V VO = VCC +0.5 V VI = –0.5 V Unit Conditions Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00 Jan. 14, 2005 page 2 of 7 RD74LVC138B Recommended Operating Conditions Item Supply voltage Input / output voltage Operating temperature Output current Symbol VCC VI VO Ta IOH Ratings 1.5 to 5.5 1.65 to 5.5 0 to 5.5 0 to VCC –40 to 85 –4 –8 –12 –24 IOL 4 8 12 24 Input rise / fall time *1 Unit V V V °C mA Conditions Data retention At operation A, B, C, G1, G2A, G2B Y0 to Y7 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V mA VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V tr, tf 20 10 ns/V VCC = 1.65 V to 2.7 V VCC = 3.0 V to 5.5 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Jan. 14, 2005 page 3 of 7 RD74LVC138B Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VIH VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 Output voltage VOH 1.65 to 5.5 1.65 2.3 2.7 3.0 3.0 4.5 VOL 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 Input current Quiescent supply current IIN ICC ∆ICC 0 to 5.5 2.7 to 3.6 2.7 to 5.5 2.7 to 3.6 Min VCC×0.65 — 1.7 2.0 VCC×0.7 — — — — VCC–0.2 1.2 1.7 2.2 2.4 2.2 3.8 — — — — — — — — — — — — — VCC×0.35 V 0.7 0.8 VCC×0.3 — — — — — — — 0.2 0.45 0.7 0.4 0.55 0.55 ±5.0 ±5.0 5.0 500 µA µA µA VIN = 5.5 V or GND VIN = 3.6 V to 5.5 V VIN = VCC or GND VIN = one input at(VCC –0.6)V, other inputs at VCC or GND V IOL = 100 µA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA IOH = –24 mA V IOH = –100 µA IOH = –4 mA IOH = –8 mA IOH = –12 mA Max V Unit Test Conditions Rev.2.00 Jan. 14, 2005 page 4 of 7 RD74LVC138B Switching Characteristics Ta = –40 to 85°C Item Propagation delay time Symbol tPLH tPHL VCC (V) 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 tPLH tPHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 tPLH tPHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Output skew between 1 pins* tOSLH tOSHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Input capacitance Note: CIN 3.3 Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 — — — — — — — — — — — — — — — — — — — — — — — — — — 5.0 Typ Max 22.0 9.9 7.9 6.7 6.0 21.0 9.4 7.4 6.5 6.0 20.3 8.4 6.4 5.8 5.0 — — — 1.0 1.0 — pF ns ns G1 Y0 to Y7 ns G2A, G2B Y0 to Y7 ns Unit From (Input) A, B, C To (Output) Y0 to Y7 1. This parameter is characterized but not tested. tOSLH = |tPLHm – tPLHn|, tOSHL = |tPHLm – tPHLn| Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol CPD VCC = (V) 1.8 2.5 3.3 5.0 Min — — — — Typ 25 26 27 30 Max — — — — Unit pF Test Conditions f = 10 MHz Rev.2.00 Jan. 14, 2005 page 5 of 7 RD74LVC138B Test Circuit VCC VCC A See Function Table Input B C G1 G2A G2B Y0 to Y7 CL RL Output Pulse Generator Zout = 50 Ω Note: 1. CL includes probe and jig capacitance. Waveforms tr Input 10 % t PLH In phase output t PHL 90 % Vref 90 % Vref 10 % t PHL VOH Vref Vref VOL t PLH VOH Out of phase output Vref Vref VOL INPUTS VIH VCC VCC 2.7 V 2.7 V VCC tf VIH GND VCC (V) VCC = 1.8±0.15 V VCC = 2.5±0.2 V VCC = 2.7 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Vref 1/2 VCC 1/2 VCC 1.5 V 1.5 V 1/2 VCC CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1.0 kΩ 500 Ω 500 Ω 500 Ω 500 Ω Note: 1. Input waveform: PRR = 10 MHz, duty cycle 50% Rev.2.00 Jan. 14, 2005 page 6 of 7 RD74LVC138B Package Dimensions As of January, 2003 10.06 10.5 Max 16 9 Unit: mm 1 *0.20 ± 0.05 8 0.80 Max 5.5 0.20 7.80 + 0.30 – 2.20 Max 1.15 1.27 0.10 ± 0.10 0 ˚ – 8˚ 0.70 ± 0.20 *0.40 ± 0.06 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) FP-16DAV — Conforms 0.24 g *Ni/Pd/Au plating As of January, 2003 Unit: mm 5.00 5.30 Max 16 9 1 *0.20 ± 0.05 8 0.65 0.13 M 0.65 Max 6.40 ± 0.20 0˚ – 8˚ 0.50 ± 0.10 1.0 4.40 *0.15 ± 0.05 1.10 Max 0.10 0.07 +0.03 –0.04 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Rev.2.00 Jan. 14, 2005 page 7 of 7 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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