RD74LVC16374BTEL

RD74LVC16374B 16-bit D-type Flip Flops with 3-state Outputs REJ03D0501–0100 Rev.1.00 Jan. 24, 2005 Description The RD74LVC16374B has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up requirements are transferred to the Q outputs on positive going transitions of the clock input. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • • • • • • VCC = 1.65 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±12 mA (@VCC = 2.7 V) ±24 mA (@VCC = 3.0 V to 5.5 V) • Ordering Information Part Name RD74LVC16374BTEL Package Type TSSOP–48 pin Package Code (Previous Code) PTSP0048KA–A (TTP–48DBV) T Package Abbreviation Taping Abbreviation (Quantity) EL (1,000 pcs/reel) Function Table Inputs G H L L L H: L: X: Z: ↑: Q0 : High level Low level Immaterial High impedance Low to high transition Level of Q before the indicated steady input conditions were established. CK X ↑ ↑ L D X L H X Output Q Z L H Q0 Rev.1.00 Jan. 24, 2005 page 1 of 8 RD74LVC16374B Pin Arrangement 1G 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2G 24 G Q G Q CK D CK D G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q G Q CK D CK D CK D CK D CK D CK D CK D CK D CK D CK D CK D CK D 48 1CK 47 1D1 46 1D2 45 GND 44 1D3 43 1D4 42 VCC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 36 2D1 35 2D2 34 GND 33 2D3 32 2D4 31 VCC 30 2D5 29 2D6 28 GND 27 2D7 26 2D8 25 2CK CK D CK D (Top view) Rev.1.00 Jan. 24, 2005 page 2 of 8 RD74LVC16374B Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg Ratings –0.5 to 7.0 –50 –0.5 to 7.0 –50 50 –0.5 to VCC +0.5 –0.5 to 7.0 ±50 100 –65 to +150 mA mA °C V Unit V mA V mA VO = –0.5 V VO = VCC+0.5 V Output "H" or "L" Output "Z" or VCC:OFF VI = –0.5 V Conditions Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / output voltage Symbol VCC VI VO Operating temperature Output current Ta IOH Ratings 1.5 to 5.5 1.65 to 5.5 0 to 5.5 0 to VCC 0 to 5.5 –40 to 85 –4 –8 –12 –24 IOL 4 8 12 24 Input rise / fall time *1 Unit V V Data hold At operation G, CK, D Conditions Output "H" or "L" Output "Z" or VCC:OFF °C mA VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V mA VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V ns/V VCC = 1.65 V to 2.7 V VCC = 3.0 V to 5.5 V tr, tf 10 20 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.1.00 Jan. 24, 2005 page 3 of 8 RD74LVC16374B Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VIH VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 Output voltage VOH 1.65 to 5.5 1.65 2.3 2.7 3.0 3.0 4.5 VOL 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 Input current Output leak current Off state output current Quiescent supply current IIN IOFF IOZ ICC ∆ICC 0 to 5.5 0 2.7 to 5.5 2.7 to 3.6 2.7 to 5.5 2.7 to 3.6 Min VCC×0.65 1.7 2.0 VCC×0.7 — — — — VCC–0.2 1.2 1.7 2.2 2.4 2.2 3.8 — — — — — — — — — — — — Max — — — — VCC×0.35 0.7 0.8 VCC×0.3 — — — — — — — 0.2 0.45 0.7 0.4 0.55 0.55 ±5.0 ±5.0 ±5.0 ±10.0 10.0 500 µA µA µA µA µA µA VIN = 5.5 V or GND VIN / VOUT = 5.5 V VIN = VCC or GND VOUT = 5.5 V or GND VIN = 3.6 to 5.5 V VIN = VCC or GND VIN = one input at(VCC–0.6)V, other inputs at VCC or GND IOL = 100 µA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA IOH = –24 mA V IOH = –100 µA IOH = –4 mA IOH = –8 mA IOH = –12 mA Unit V Test Conditions Rev.1.00 Jan. 24, 2005 page 4 of 8 RD74LVC16374B Switching Characteristics Ta = –40 to 85°C Item Maximum clock frequency Symbol fmax VCC (V) 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Propagation delay time tPLH tPHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Output enable time tZH tZL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Output disable time tHZ tLZ 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Setup time tsu 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Hold time th 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Pulse width tw 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Between output *1 pins skew tOSLH tOSHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Input capacitance Output capacitance Note: CIN CO 3.3 3.3 Min — — — — — 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 6.0 4.0 2.0 2.0 2.0 4.0 2.0 1.5 1.5 1.5 9.0 4.0 3.3 3.3 3.3 — — — — — — — Typ — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 4.0 8.0 Max 55.0 95.0 150.0 150.0 150.0 19.1 9.6 7.7 7.0 5.5 20.0 10.5 8.0 7.0 6.0 20.0 10.5 8.0 7.0 6.0 — — — — — — — — — — — — — — — — — — 1.0 1.0 — — pF pF ns ns ns ns ns G Q ns G Q ns CK Q Unit MHz From (Input) To (Output) 1. This parameter is characterized but not tested. tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn| Rev.1.00 Jan. 24, 2005 page 5 of 8 RD74LVC16374B Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol CPD VCC (V) 1.8 2.5 3.3 5.0 Min     Typ 25 26 28 32 Max     Unit pF Test Conditions f = 10 MHz Test Circuit VCC VCC Output 1G, 2G Input 1Q1 to 2Q8 RL CL 1D1 to 2D8 Symbol t PLH / t PHL 1CK, 2CK t su / t h / t w t ZH/ t HZ t ZL / t LZ S1 OPEN GND VTT RL S1 OPEN V TT GND Pulse generator Zout = 50 Ω Input Pulse generator Zout = 50 Ω Note: 1. CL includes probe and jig capacitance. Waveforms – 1 tr Input CK 10 % tr Input D 90 % 10 % t PLH Output Q Vref 90 % 90 % Vref 10 % tf 90 % 10 % t PHL Vref VOL tf VIH Vref GND VIH See Function Table GND VOH Note: Input waveform: PRR = 10 MHz, duty cycle 50%. Rev.1.00 Jan. 24, 2005 page 6 of 8 RD74LVC16374B Waveforms – 2 tr Input CK 10 % tw ts Input D Vref th VIH Vref GND 90 % 90 % Vref Vref 10 % tw tf VIH Vref GND Note: Input waveform: PRR = 10 MHz, duty cycle 50%. Waveforms – 3 tf Input G 90 % Vref 10 % t ZL Waveform - A t ZH Waveform - B Vref Vref t HZ VOH – ∆V tr 90 % Vref 10 % t LZ VIH GND ≈ 1/2V TT VOL + ∆V VOL VOH ≈ GND INPUTS VIH VCC VCC 2.7 V 2.7 V VCC VCC (V) VCC = 1.8±0.15 V VCC = 2.5±0.2 V VCC = 2.7 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Vref 1/2 VCC 1/2 VCC 1.5 V 1.5 V 1/2 VCC VTT 2× VCC 2× VCC 6V 6V 2× VCC CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1.0 kΩ 500 Ω 500 Ω 500 Ω 500 Ω ∆V 0.15 V 0.15 V 0.3 V 0.3 V 0.3 V Notes: 1. Input waveform: PRR = 10 MHz, duty cycle 50%. 2. Waveform – A shows input conditions such that the output is "L" level when enable by the output control. 3. Waveform – B shows input conditions such that the output is "H" level when enable by the output control. Rev.1.00 Jan. 24, 2005 page 7 of 8 RD74LVC16374B Package Dimensions JEITA Package Code P-TSSOP48-6.1x12.5-0.50 RENESAS Code PTSP0048KA-A Previous Code TTP-48DBV MASS[Typ.] 0.2g *1 D F 25 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 48 bp HE E c Index mark Reference Symbol Dimension in Millimeters Min Nom 12.5 6.10 Max 12.7 *2 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 D E A2 24 bp L1 x M A1 A bp b1 c c 1 0.08 0.13 0.18 1.20 0.14 0.19 0.24 0.10 0.15 0.20 θ HE 0° 7.90 8.10 0.50 8° 8.30 A θ A1 y L e x y 0.08 0.10 0.65 0.4 1 Detail F Z L L 0.5 1.0 0.6 Rev.1.00 Jan. 24, 2005 page 8 of 8 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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