RD74LVC1G98WPE

RD74LVC1G98 Configurable Multiple–Function Gate REJ03D0730–0100 Rev.1.00 Jul 26, 2006 Description The RD74LVC1G98 has configurable multiple–function gate in a 6-pin package. The Output state is determined by eight patterns of 3–bit input. The user can choose the logic functions AND, NAND, OR, NOR, INVERTER, Non– Inverted Buffer, Data Selector. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features The basic gate function is lined up as Renesas uni logic series. Supply voltage range: 1.65 to 5.5 V Operating temperature range: –40 to +85°C All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Output current: ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±24 mA (@VCC = 3.0 V) ±32 mA (@VCC = 4.5 V) • All the logical input has hysteresis voltage for the slow transition. voltage • Ordering Information Part Name RD74LVC1G98WPE Package Type WCSP-6 pin Package Package Code (Previous Code) (Previous SXBG0006LA-A SXBG0006LA-A (TBS-6BV) (TBS-6BV) Package Abbreviation WP Taping Abbreviation (Quantity) E (3,000 pcs/reel) • • • • • • Article Indication Marking Year code Month code K1YM Rev.1.00 Jul 26, 2006 page 1 of 9 RD74LVC1G98 Function Table IN2 L L L L H H H H H: High level L: Low level Inputs IN1 L L H H L L H H IN0 L H L H L H L H Output Y H H L L H L H L Pin Arrangement 0.7 mm Height 0.4 mm 0.4 mm pitch 0.17 mm 6–Ball (WP) IN0 3 4 Y GND 2 5 VCC 1.1 mm Pin#1 INDEX IN1 1 6 IN2 (Bottom (Bottom view) (Top view) Logic Diagram IN0 Y IN1 IN2 Rev.1.00 Jul 26, 2006 page 2 of 9 RD74LVC1G98 Function Selection Table Logic Function 2 to 1 data Selector 2–inputs NAND 2–inputs NOR with one input inverted 2–inputs AND with one input inverted 2–inputs NAND with one input inverted 2–inputs OR with one input inverted 2–inputs NOR Non–Invert Buffer Inverter Figure No. 1 2 3 3 4 4 5 6 7 Rev.1.00 Jul 26, 2006 page 3 of 9 RD74LVC1G98 Logic Configurations VCC A/B A B A Y B 1 (IN1) (IN2) 6 A/B 2 (GND) (VCC) 5 3 (IN0) (Y) 4 Y Figure 1 2 to 1 Data Selector VCC VCC 1 (IN1) (IN2) 6 A B A B 1 (IN1) (IN2) 6 A Y 2 (GND) (VCC) 5 A B A B A Y 2 (GND) (VCC) 5 Y B Y 3 (IN0) (Y) 4 Y B 3 (IN0) (Y) 4 Y Figure 2 2–inputs NAND Gate VCC Figure 3 2–inputs NOR Gate with with A input inverted VCC A B A B B Y 1 (IN1) (IN2) 6 A A B A B Y Y B 1 (IN1) (IN2) 6 A 2 (GND) (VCC) 5 2 (GND) (VCC) 5 3 (IN0) (Y) 4 Y 3 (IN0) (Y) 4 Y Y Figure 4 2–inputs NAND Gate with with A input inverted VCC Figure 5 2–inputs NOR Gate VCC 1 (IN1) (IN2) 6 A A Y Y A 1 (IN1) (IN2) 6 A Y 2 (GND) (VCC) 5 3 (IN0) (Y) 4 2 (GND) (VCC) 5 3 (IN0) (Y) 4 Y Figure 6 Non–Invert Buffer Figure 7 Inverter Rev.1.00 Jul 26, 2006 page 4 of 9 RD74LVC1G98 Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Package Thermal impedance Storage temperature Notes: Symbol VCC VI VO IIK IOK IO ICC or IGND θja Tstg Ratings –0.5 to 6.5 –0.5 to 6.5 –0.5 to VCC + 0.5 –0.5 to 6.5 –50 –50 ±50 ±100 123 –65 to 150 Unit V V V mA mA mA mA °C/W °C WP Test Conditions Output : H or L VCC : OFF VI < 0 VO < 0 VO = 0 to VCC The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are output observed. 2. This value is limited to 5.5 V maximum. Recommended Operating Conditions Item Supply voltage range Input voltage range Output voltage range Symbol VCC VI VO Min 1.65 0 0 — — — — — — — — — Max 5.5 5.5 VCC 4 8 16 16 24 32 32 –4 –4 –8 –8 –16 –16 –24 –32 85 Unit V V V Conditions VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V mA VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V °C IOL Output current IOH — Operating Operating free-air temperature Ta –40 Note: Unused or floating inputs must be held high or low. Rev.1.00 Jul 26, 2006 page 5 of 9 RD74LVC1G98 Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V) 1.8 2.5 3.3 5.0 1.8 2.5 3.3 5.0 1.8 2.5 3.3 5.0 1.65 to 5.5 1.65 2.3 2.3 3.0 Output voltage 4.5 1.65 1.65 to 5.5 1.65 1.65 2.3 2.3 3.0 4.5 0 to 5.5 5.5 Min 0.8 1.2 1.6 2.3 0.4 0.6 0.9 1.5 0.4 0.4 0.4 0.4 VCC–0.1 –0.1 1.2 1.9 2.4 2.4 2.3 3.8 — — — — — — — Typ — — — — — — — — — — — — — — — — — — — — — — — — — Max 1.4 1.7 2.3 3.0 0.7 1.0 1.4 2.0 0.7 0.8 0.9 1.0 — — — — — — 0.1 0.45 0.3 0.4 0.4 0.55 0.55 0.55 ±5 10 µA Unit Test condition VT+ Threshold voltage VT– V ∆ VT VOH IOH = –100 µA IOH = –4 mA IOH = –8 mA IOH = –16 mA IOH = –24 mA V IOH = –32 mA IOL = 100 µA IOL = 4 mA IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 VOL Input current IIN ICC µA Quiescent supply current One input at VCC–0.6 V, Other input at VCC or GND Output Output leakage current IOFF 0 — — ±10 µA VIN or VO = 0 to 5.5 V Input capacitance CIN 3.3 — 3.5 — pF VIN = VCC or GND Note: Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. ∆ICC 3 to 5.5 — — 500 Rev.1.00 Jul 26, 2006 page 6 of 9 RD74LVC1G98 Switching Characteristics VCC = 1.8±0.15 V Item Propagation delay time Symbol tPLH tPHL Ta = –40 to 85°C Min Max 3.2 14.4 Unit ns Test Conditions CL = 30 pF, RL = 1.0 kΩ FROM (Input) IN TO (Output) Y VCC = 2.5±0.2 V Item Propagation delay time Symbol tPLH tPHL Ta = –40 to 85°C Min Max 2.0 8.3 Unit ns Test Conditions CL = 30 pF, RL = 500 Ω FROM (Input) IN TO (Output) Y VCC = 3.3±0.3 V Item Propagation delay time Symbol tPLH tPHL Ta = –40 to 85°C Min Max 1.5 6.3 Unit ns Test Conditions CL = 50 pF, RL = 500 Ω FROM (Input) IN TO (Output) Y VCC = 5.0±0.5 V Item Propagation delay time Symbol tPLH tPHL Ta = –40 to 85°C Min Max 1.1 1.1 5.1 Unit Unit ns Test Conditions CL = 50 pF, RL = 500 Ω FROM (Input) IN TO (Output) Y Operating Characteristics Item Symbol VCC (V) 1.8 2.5 3.3 5.0 Min Min — — — — Ta = 25°C Typ 23 23 23 26 Max — — — — Unit Test Conditions Power Power dissipation capacitance CPD pF f = 10 MHz Test Circuit Measurement point From Output CL * RL Note: CL includes probe and jig capacitance. Rev.1.00 Jul 26, 2006 page 7 of 9 RD74LVC1G98 • Waveforms tr tf 90% Input Vref 10% t PLH 90% Vref 10% t PHL VI GND VOH In phase output Vref Vref VOL VOH Out of phase output t PHL Vref Vref VOL t PLH VCC (V) VI 1.8±0.15 2.5±0.2 3.3±0.3 5.0±0.5 VCC VCC Inputs tr / tf ≤ 2 ns ≤ 2 ns Vref VCC / 2 VCC / 2 1.5 V VCC / 2 CL 30 pF 30 pF 50 pF 50 pF RL 1.0 kΩ 500 Ω 500 Ω 500 Ω 3 V ≤ 2.5 ns VCC ≤ 2.5 ns Notes: 1. Input waveform : PRR ≤ 10 MHz, Zo = 50 Ω. 2. 2. The output are measured one at a time with one transition per measurement. Rev.1.00 Jul 26, 2006 page 8 of 9 RD74LVC1G98 Package Dimensions JEITA Package Code S-XFBGA6-0.7x1.1-0.40 RENESAS Code SXBG0006LA-A Previous Code TBS-6BV MASS[Typ.] 0.001g D ZD e C ZE B E B e A Pin #1 index 1 C 2 6×φb φx M C A B φx M C C Seating plane A1 A2 Reference Symbol Dimension in Millimeters Min Nom Max 0.40 0.110 0.140 (0.235) * 0.15 0.70 1.10 0.40 0.05 0.05 0.15 0.15 0.19 A A1 A2 b D yC *Reference value. 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