RD74LVC273B

RD74LVC273B Octal D-type Flip-Flops with Clear REJ03D0323–0100Z Rev.1.00 Jun. 16, 2004 Description The RD74LVC273B has eight edge trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Low-voltage and high-speed operation is suitable for batterypowered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • VCC = 1.65 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High Output current ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±12 mA (@VCC = 2.7 V) ±24 mA (@VCC = 3.0 V to 5.5 V) • Ordering Information Part Name RD74LVC273BFPEL RD74LVC273BTELL Package Type SOP–20 pin(JEITA) TSSOP–20 pin Package Code FP–20DAV TTP–20DAV FP T Package Abbreviation Taping Abbreviation (Quantity) EL (2,000 pcs / reel) ELL (2,000 pcs / reel) Function Table Inputs CLR L H H H Note: H: High level L: Low level X: Immaterial ↑: Low to high transition ↓: High to low transition Q0 : Output level before the indicated steady state input conditions were established. X ↑ ↑ ↓ CLK X H L X D L H L Q0 Output Q Rev.1.00 Jun. 16, 2004 page 1 of 8 RD74LVC273B Pin Arrangement CLR 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 D CK R D CK R Q D CK R Q D CK R Q D CK R Q D CK R Q D CK R Q D CK R Q Q 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK (Top view) Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg –0.5 to 7.0 –50 –0.5 to 7.0 –50 50 –0.5 to VCC+0.5 –0.5 to 7.0 ±50 100 –65 to 150 mA mA °C V Ratings V mA V mA VO = –0.5 V VO = VCC+0.5 V Output “H” or “L” VCC: OFF VI = –0.5 V Unit Conditions Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.1.00 Jun. 16, 2004 page 2 of 8 RD74LVC273B Recommended Operating Conditions Item Supply voltage Input/Output voltage Symbol VCC VI VO Operating temperature Output current Ta IOH Ratings 1.5 to 5.5 1.65 to 5.5 0 to 5.5 0 to VCC 0 to 5.5 –40 to 85 –4 –8 –12 –24 IOL 4 8 12 24 Input rise / fall time* Note: 1 Unit V V Data hold Conditions At operation CLK, CLR, D Output “H” or “L” VCC: OFF °C mA VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V mA VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V ns/V VCC = 1.65 V to 2.7 V VCC = 3.0 V to 5.5 V tr / tf 20 10 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.1.00 Jun. 16, 2004 page 3 of 8 RD74LVC273B Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VIH VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 Output voltage VOH 1.65 to 5.5 1.65 2.3 2.7 3.0 3.0 4.5 VOL 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 Input current Output leak current Quiescent supply current IIN IOFF ICC ∆ICC 0 to 5.5 0 2.7 to 3.6 2.7 to 5.5 2.7 to 3.6 1.7 2.0 VCC × 0.7 — — — — VCC – 0.2 1.2 1.7 2.2 2.4 2.2 3.8 — — — — — — — — — — — Min VCC × 0.65 — — — — VCC × 0.35 0.7 0.8 VCC × 0.3 — — — — — — — 0.2 0.45 0.7 0.4 0.55 0.55 ±5.0 ±5.0 ±5.0 5.0 500 µA µA µA VIN = 5.5 V or GND VIN/VOUT = 5.5 V VIN = 3.6 V to 5.5 V VIN = VCC or GND VIN = one input at (VCC–0.6)V, other inputs at VCC or GND Max Unit V Test Conditions V IOH = –100 µA IOH = –4 mA IOH = –8 mA IOH = –12 mA IOH = –24 mA IOL = 100 µA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA Rev.1.00 Jun. 16, 2004 page 4 of 8 RD74LVC273B Switching Characteristics Ta = –40 to 85°C Item Maximum clock frequency Symbol fmax VCC (V) 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Propagation delay time tPLH tPHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 tPHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Setup time tSU 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Hold time th 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Pulse width tW 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Between output pins 1 skew* tOSLH tOSHL 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 Input capacitance Output capacitance Note: CIN CO 3.3 3.3 — — — — — 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 2.0 1.0 6.0 4.0 2.0 2.0 2.0 4.0 2.0 1.5 1.5 1.5 9.0 4.0 3.3 3.3 3.3 — — — — — — — Min — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 4.0 8.0 Typ Max 55.0 95.0 150.0 150.0 150.0 21.6 10.5 8.5 7.5 6.0 21.6 10.5 8.5 7.5 6.0 — — — — — — — — — — — — — — — — — — 1.0 1.0 — — pF pF ns ns ns ns ns CLR Q ns CLK Q Unit MHz FROM (Input) TO (Output) 1. This parameter is characterized but not tested. tOSLH = |tPLHm – tPLHn|, tOSHL = |tPHLm – tPHLn| Rev.1.00 Jun. 16, 2004 page 5 of 8 RD74LVC273B Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol CPD VCC = (V) 1.8 2.5 3.3 5.0 Min — — — — Typ 25 26 28 32 Max — — — — Unit pF Test Conditions f = 10 MHz Test Circuit VCC VCC Output CLR 1Q to 8Q Input Pulse generator Zout = 50 Ω Input Pulse generator Zout = 50 Ω See Function Table CL 1D to 8D RL CLK Note: 1. CL includes probe and jig capacitance. Rev.1.00 Jun. 16, 2004 page 6 of 8 RD74LVC273B tr tf 90 % Vref 10 % t su th 90 % Vref 10 % VIH GND • Waveform − 1 Timing input VIH Data input Vref tw VIH Input Vref Vref GND Vref GND tr tf 90 % Vref 90 % Vref 10 % t PLH t PHL VIH GND • Waveform − 2 10 % Input VOH In phase output t PHL Vref t PLH VOH Out of phase output Vref Vref VOL INPUTS Vcc (V) Vcc = 1.8±0.15 V Vcc = 2.5±0.2 V Vcc = 2.7 V Vcc = 3.3±0.3 V Vcc = 5.0±0.5 V VIH Vcc Vcc tr / tf Vref CL RL ≤ 2 ns 1/2 Vcc 30 pF 1.0 kΩ ≤ 2 ns 1/2 Vcc 30 pF 500 Ω 1.5 V 1.5 V 50 pF 500 Ω 50 pF 500 Ω Vref VOL 2.7 V ≤ 2.5 ns 2.7 V ≤ 2.5 ns Vcc ≤ 2.5 ns 1/2 Vcc 50 pF 500 Ω Notes: 1. Input waveform: PRR ≤ 10 MHz, duty cycle 50%. 2. The output is measured one at a time with one transition per measurement. Rev.1.00 Jun. 16, 2004 page 7 of 8 RD74LVC273B Package Dimensions As of January, 2002 12.6 13 Max 20 Unit: mm 11 1 10 5.5 0.80 Max 2.20 Max *0.20 ± 0.05 0.20 7.80 + 0.30 – 1.15 1.27 *0.40 ± 0.06 0.10 ± 0.10 0˚ – 8˚ 0.70 ± 0.20 0.15 0.12 M *Pd plating Package Code JEDEC JEITA Mass (reference value) FP–20DAV — Conforms 0.31 g As of January, 2002 Unit: mm 6.50 6.80 Max 20 11 1 10 0.65 1.0 6.40 ± 0.20 0.65 Max *0.20 ± 0.05 0.13 M 4.40 *0.15 ± 0.05 1.10 Max 0.10 0.07 +0.03 –0.04 0˚ – 8˚ 0.50 ± 0.10 *Pd plating Package Code JEDEC JEITA Mass (reference value) TTP–20DAV — — 0.07 g Rev.1.00 Jun. 16, 2004 page 8 of 8 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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