RD74VT1G125

RD74VT1G125 Bus Buffer Gate with 3–state output / Dual Supply Voltage Translator REJ03D0496–0200 Rev.2.00 Apr. 01, 2005 Description The RD74VT1G125 has a bus buffer gate with 3–state output in a 6 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCCIN through a pull-up resistor, the minimum value of the resistor is determined by the current sinking capability of the driver. The input is designed to track VCCIN, which accepts voltages from 1.2 V to 3.6 V, and the output is designed to track VCCOUT, which operates at 1.2 V to 3.6 V. Low voltage and high-speed operation is suitable suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • This product function as level shift that change VCCIN input level to VCCOUT output level by providing different IN supply voltage to VCCIN and VCCOUT. • Supplied on emboss taping for high-speed automatic mounting. • Supply voltage range: VCCIN = 1.2 V to 3.6 V IN VCCOUT = 1.2 V to 3.6 V OUT • Operating temperature range: −40°C to +85°C 40°C • All inputs VIH(Max.) = 3.6 V (@VCCIN = 0 V to 3.6 V) CC Outputs VO(Max.) = 3.6 V (@VCCOUT = 0 V) CC • Output current ±2 mA (@VCCOUT = 1.2 V) ±2 ±4 mA (@VCCOUT = 1.4 V to 1.6 V) ±4 ±6 mA (@VCCOUT = 1.65 V to 1.95 V) ±6 ±18 ±18 mA (@VCCOUT = 2.3 V to 2.7 V) ±24 ±24 mA (@VCCOUT = 3.0 V to 3.6 V) • Ordering Information Part Name RD74VT1G125CLE Package Type WCSP–6 pin Package Code (Previous Code) SXBG0006KB–A (TBS–6AV) Package Abbreviation CL Taping Abbreviation (Quantity) E (3,000 pcs / reel) Article Indication Marking Year code Month code VBYM Rev.2.00 Apr. 01, 2005 page 1 of 9 RD74VT1G125 Function Table Inputs OE L L H H: High level L: Low level X: Immaterial Z: High impedance A H L X OUTPUT Y H L Z Pin Arrangement 0.9 mm Height 0.5 mm 0.5 mm pitch 0.23 mm 6–Ball (CL) GND 3 4 Y A 2 5 VCCOUT 1.4 mm Pin#1 INDEX OE 1 6 VCCIN (Bottom (Bottom view) (Top view) Logic Diagram OE A Y Rev.2.00 Apr. 01, 2005 page 2 of 9 RD74VT1G125 Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Symbol VCCIN, VCCOUT VI VO Ratings –0.5 to 4.6 –0.5 to 4.6 –0.5 to VCCOUT+0.5 –0.5 to 4.6 Unit V V V Conditions A port or OE Output: “H” or “L” Output: “Z” or VCCOUT: OFF Input clamp current Output clamp current Continuous output current Continuous output current VCC or GND Package Thermal impedance Storage temperature Notes: IIK IOK IO ICCIN, ICCOUT, IGND θja Tstg –50 –50 50 ±50 ±100 123 –65 to 150 –65 mA mA mA mA °C/W °C VI < 0 VO < 0 VO > VCC+0.5 The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two st of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are ngs output observed. 2. This value is limited to 4.6 V maximum. Recommended Operating Conditions Item Supply voltage range Input/Output voltage Symbol VCCIN CC VCCOUT VI VO Output current IOH Ratings 1.2 to 3.6 1.2 to 3.6 0 to 3.6 0 to VCCOUT to 0 to 3.6 –2 –4 –6 –18 –24 IOL 2 4 6 18 24 Input transition rise or fall time Operation free-air temperature ∆t / ∆v Ta 10 –40 to 85 ns / V °C mA mA V V A port or OE Output: “H” or “L” Output: “Z” or VCCOUT: OFF VCCOUT = 1.2 V VCCOUT = 1.5±0.1 V VCCOUT = 1.8±0.15 V VCCOUT = 2.5±0.2 V VCCOUT = 3.3±0.3 V VCCOUT = 1.2 V VCCOUT = 1.5±0.1 V VCCOUT = 1.8±0.15 V VCCOUT = 2.5±0.2 V VCCOUT = 3.3±0.3 V Unit V Conditions Rev.2.00 Apr. 01, 2005 page 3 of 9 RD74VT1G125 Electrical Characteristics (Ta = −40 to 85°C) Item Input voltage Symbol VCCIN (V) VIH 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 VIL 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 Output voltage VOH 1.2 to 3.6 * VCCOUT (V) 1.2 to 3.6 * 1.2 to 3.6 VOL 1.2 to 3.6 Input current Off state output current Output leakage current Quiescent supply current IIN IOZ IOFF ICCIN OUT ICCOUT 3.6 3.6 0 1.2 to 3.6 1.2 to 3.6 3.6 3.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 3.6 3.6 0 1.2 to 3.6 1.2 to 3.6 3.6 3.3 Min VCCIN×0.75 VCCIN×0.70 VCCIN×0.65 1.6 2.0      VCCOUT−0.2 0.9 1.1 1.25 1.7 2.2       –1.0 –1.5  –3.0 –3.0   Typ                             3.5 Max      VCCIN×0.25 VCCIN×0.30 VCCIN×0.35 0.7 0.8       0.2 0.3 0.3 0.3 0.6 0.55 1.0 1.5 1.5 3.0 3.0 250  Unit V Test conditions A port Control input V A port Control input V V µA µA µA µA IOH = –100 µA IOH = –2 mA IOH = –4 mA IOH = –6 mA IOH = –18 mA IOH = –24 mA IOL = 100 µA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 18 mA IOL = 24 mA VIN = GND or VCCIN control input VIN = VIH or VIL VIN, VOUT = 0 to 3.6 V IO(Y port) = 0 VIN = VCCIN or GND IO(Y port) = 0 VIN = VCCIN or GND A port or control VCCIN–0.6 (1 input) VIN = VCC or GND Increase in ICC per input Input capacitance ∆ICC CIN µA pF Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00 Apr. 01, 2005 page 4 of 9 RD74VT1G125 Switching Characteristics VCCIN = 3.3±0.3 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To 1.2 V Typ 9.2 9.2 OE OE Y 10.2 10.2 Y 5.2 5.2 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A Y VCCOUT= 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 8.8 8.8 9.6 9.6 5.6 5.6 VCCOUT= 1.8±0.15 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 5.8 5.8 6.4 6.4 5.2 5.2 VCCOUT= 2.5±0.2 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.2 4.2 4.2 4.2 4.6 4.6 VCCOUT= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.5 3.5 3.7 3.7 4.5 4.5 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ VCCIN = 2.5±0.2 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To 1.2 V Typ Typ 9.5 9.5 9.5 9.5 OE OE Y 10.6 10.6 10.6 10.6 Y 5.4 5.4 5.4 5.4 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A Y VCCOUT= 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 9.0 9.0 10.2 10.2 5.7 5.7 VCCOUT= 1.8±0.15 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.0 6.0 6.6 6.6 5.3 5.3 VCCOUT= 2.5±0.2 V 2.5±0.2 Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.4 4.4 4.5 4.5 4.5 4.5 VCCOUT= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.7 3.7 3.8 3.8 4.4 4.4 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ VCCIN = 1.8±0.15 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To To 1.2 V 1.2 Typ Typ 9.6 9.6 9.6 9.6 OE OE Y 10.8 10.8 10.8 Y 5.8 5.8 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A Y VCCOUT= 1.5±0.1 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 9.2 9.2 10.8 10.8 6.0 6.0 VCCOUT= 1.8±0.15 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.5 6.5 7.0 7.0 5.8 5.8 VCCOUT= 2.5±0.2 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.7 4.7 5.2 5.2 5.4 5.4 VCCOUT= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.0 4.0 4.5 4.5 5.2 5.2 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ VCCIN = 1.5±0.1 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To 1.2 V Typ 9.8 9.8 OE OE Y 11.2 11.2 Y 6.4 6.4 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A Y VCCOUT= 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 10.0 10.0 11.2 11.2 7.2 7.2 VCCOUT= 1.8±0.15 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.9 6.9 7.8 7.8 6.4 6.4 VCCOUT= 2.5±0.2 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 5.1 5.1 5.4 5.4 5.8 5.8 VCCOUT= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.5 4.5 4.8 4.8 5.6 5.6 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ Rev.2.00 Apr. 01, 2005 page 5 of 9 RD74VT1G125 Switching Characteristics (Cont.) VCCIN = 1.2 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To 1.2 V Typ 10.5 10.5 OE OE Y 11.6 11.6 Y 7.0 7.0 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A Y VCCOUT= 1.5±0.1 V Typ 7.5 7.5 8.5 8.5 6.2 6.2 VCCOUT= 1.8±0.15 V Typ 6.0 6.0 6.5 6.5 6.0 6.0 VCCOUT= 2.5±0.2 V Typ 4.5 4.5 5.0 5.0 5.7 5.7 VCCOUT= 3.3±0.3 V Typ 4.0 4.0 4.2 4.2 5.5 5.5 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol CPD VCCIN (V) 3.3 VCCOUT (V) OUT 3.3 Min  Typ 12 Max  Unit pF Test conditions f = 10 MHz CL = 0 Power-up considerations Level-translation devices offer an opportunity for successful mixed-voltage signal design. for A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, be or other anomalies caused by improperly biased device pins. Take Take these precautions to guard against such power-up problems. 1. 1. 2. 2. Connect ground before any supply voltage is applied. Next, power up the control side of the device. (Power up of VCCIN is first. Next power up is VCCOUT) (Power Tie OE to VCCIN with a pull-up resistor so that it ramps with VCCIN. 3. Rev.2.00 Apr. 01, 2005 page 6 of 9 RD74VT1G125 Test Circuit VCCIN VCCOUT See Function Table Input Output RL =2kΩ S1 CL =15pF RL =2kΩ Pulse Generator Z OUT = 50 Ω *1 OPEN See under table GND Symbol S1 t PLH / t PHL OPEN t HZ / t ZH t LZ / t ZL GND VCC×2 Note: CL includes probe and jig capacitance. Waveforms tr tf 90% Input A V ref 10% 90% V ref 10% VIH GND t PHL VOH t PLH Output Y V ref V ref VOL Symbol VCC = 1.2 V to 3.6 V tr / tf VIH Vref 2.0 ns VCC 1/2 VCC Note: Input waveform : PRR ≤ 10 MHz, ZO = 50 Ω, duty cycle 50% Rev.2.00 Apr. 01, 2005 page 7 of 9 RD74VT1G125 tf tr 90% Input OE V ref 10% V ref 10% 90% VIH GND t LZ t ZL VOH Waveform–1 V ref VL Output Y t ZH t HZ VH Waveform–2 V ref VOL VOH VOL Symbol tr / t f V IH V ref VH / V L VCC = 1.2 V, 1.5±0.1 V 2.0 ns VCC 1/2 VCC VH = VOH-0.1 V VL = VOL+0.1 V VCC = 1.8±0.15 V VCC = 2.5±0.2 V VCC = 3.3±0.3 V 2.0 ns VCC 1/2 VCC 2.0 ns VCC 1/2 VCC 2.0 ns VCC 1/2 VCC VH = VOH-0.15 V VH = VOH-0.15 V VH = VOH-0.3 V VL = VOL+0.15 V VL = VOL+0.15 V VL = VOL+0.3 V Notes: 1. Input waveform : PRR ≤ 10 MHz, Zo = 50 Ω, duty cycle 50%. 2. 2. Waveform – 1 is for an output with internal conditions such that the output is low except when disabled by the output control. except 3. 3. Waveform – 2 is for an output with internal conditions such that the output is high except except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Apr. 01, 2005 page 8 of 9 RD74VT1G125 Package Dimensions JEITA Package Code S-XFBGA6-0.9x1.4-0.50 RENESAS Code SXBG0006KB-A Previous Code TBS-6AV MASS[Typ.] 0.001g e D ZD C B E B A 1 Pin#1 index area A 6 × φb y1 C 2 Reference Symbol e ZE Dimension in Millimeters Min Nom Max 0.50 0.155 0.185 (0.315) * 0.25 0.90 1.40 0.50 0.05 0.05 A A1 A2 b D 0.20 φ× M C A B φ× M C C Seating plane E e x A1 A2 A yC y y 1 D E 0.20 0.20 0.20 * Reference value. Z Z Rev.2.00 Apr. 01, 2005 page 9 of 9 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's 1. Technology application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of improvements publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvement or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distrib distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or e errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technolo Corp. Semiconductor Technology home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is pro prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 http://www.renesas.com © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .2.0