RD74VT1G240CLE

RD74VT1G240 Bus Buffer Inverted with 3-state Output / Dual Supply Voltage Translator REJ03D0518–0100 Rev.1.00 Jun. 01, 2005 Description The RD74VT1G240 has a bus buffer inverted with 3-state output in a 6 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The input is designed to track VCCIN, which accepts voltages from 1.2V to 3.6V, and the output is designed to track VCCOUT, which operates at 1.2V to 3.6V. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • This product function as level shift that change VCCIN input level to VCCOUT output level by providing different IN supply voltage to VCCIN and VCCOUT. • The basic gate function is lined up as Renesas uni logic series. up • Supplied on emboss taping for high-speed automatic mounting. • Supply voltage range: VCCIN = 1.2 V to 3.6 V VCCOUT = 1.2 V to 3.6 V OUT Operating temperature range: −40 to +85°C 40 • All inputs VIH (Max.) = 3.6 V (@VCCIN = 0 V to 3.6 V) IN Outputs VO (Max.) = 3.6 V (@VCCOUT = 0 V) OUT • Output current ±2 mA (@VCCOUT = 1.2 V) CC ±4 mA (@VCCOUT = 1.4 V to 1.6 V) mA ±6 mA (@VCCOUT = 1.65 V to 1.95 V) mA ±18 mA (@VCCOUT = 2.3 V to 2.7 V) 18 ±24 mA (@VCCOUT = 3.0 V to 3.6 V) 24 • Ordering Information Part Name RD74VT1G240CLE Package Type WCSP-6 pin Package Code (Previous Code) SXBG0006KB–A (TBS-6AV) Package Abbreviation CL Taping Abbreviation (Quantity) E (3,000 pcs/reel) Article Indication Marking Year code Month code VHYM Rev.1.00 Jun. 01, 2005 page 1 of 9 RD74VT1G240 Function Table Inputs OE L L H H: High level L: Low level X: Immaterial Z: High impedance A L H X Output Y H L Z Pin Arrangement 0.9 mm Height 0.5 mm 0.5 mm pitch 0.23 mm 6–Ball (CL) GND 3 4 Y A 2 5 VCCOUT 1.4 mm Pin#1 INDEX OE 1 6 VCCIN (Bottom (Bottom view) (Top view) Logic Diagram OE A Y Rev.1.00 Jun. 01, 2005 page 2 of 9 RD74VT1G240 Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Symbol VCCIN, VCCOUT VI VO Ratings –0.5 to 4.6 –0.5 to 4.6 –0.5 to VCCOUT+0.5 –0.5 to 4.6 Unit V V V Conditions A port or OE Output: “H” or “L” Output: “Z” or VCCOUT: OFF Input clamp current Output clamp current Continuous output current Continuous output current VCC or GND Package Thermal impedance Storage temperature Notes: IIK IOK IO ICCIN, ICCOUT, IGND θja Tstg –50 –50 50 ±50 ±100 123 –65 to 150 –65 mA mA mA mA °C/W °C VI < 0 VO < 0 VO > VCC+0.5 The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two st of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are ngs output observed. 2. This value is limited to 4.6 V maximum. Recommended Operating Conditions Item Supply voltage range Input/Output voltage Symbol VCCIN CC VCCOUT VI VO Output current IOH Ratings 1.2 to 3.6 1.2 to 3.6 0 to 3.6 0 to VCCOUT to 0 to 3.6 –2 –4 –6 –18 –24 IOL 2 4 6 18 24 Input transition rise or fall time Operation free-air temperature ∆t / ∆v Ta 10 –40 to 85 ns / V °C mA mA V V A port or OE Output: “H” or “L” Output: “Z” or VCCOUT: OFF VCCOUT = 1.2 V VCCOUT = 1.5±0.1 V VCCOUT = 1.8±0.15 V VCCOUT = 2.5±0.2 V VCCOUT = 3.3±0.3 V VCCOUT = 1.2 V VCCOUT = 1.5±0.1 V VCCOUT = 1.8±0.15 V VCCOUT = 2.5±0.2 V VCCOUT = 3.3±0.3 V Unit V Conditions Rev.1.00 Jun. 01, 2005 page 3 of 9 RD74VT1G240 Electrical Characteristics (Ta = −40 to 85°C) Symbol VCCIN (V) * VIH 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 VIL 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 Output voltage VOH 1.2 to 3.6 Item Input voltage VCCOUT (V) * Min 1.2 to 3.6 VCCIN×0.75 VCCIN×0.70 VCCIN×0.65 1.6 2.0 1.2 to 3.6      1.2 to 3.6 VCCOUT−0.2 1.2 0.9 1.5±0.1 1.1 1.8±0.15 1.25 2.5±0.2 1.7 3.3±0.3 2.2 1.2 to 3.6  1.2  1.5±0.1  1.8±0.15  2.5±0.2  3.3±0.3  3.6 –1.0 3.6 0 1.2 to 3.6 1.2 to 3.6 3.6 3.3 –1.5  –3.0 –3.0   Typ                             3.5 Max      VCCIN×0.25 VCCIN×0.30 VCCIN×0.35 0.7 0.8       0.2 0.3 0.3 0.3 0.6 0.55 1.0 1.5 1.5 3.0 3.0 250  µA pF Unit Test conditions V A port Control input V A port Control input V VOL 1.2 to 3.6 V Input current Off state output current Output leakage current Quiescent supply current IIN IOZ IOFF ICCIN IN OUT ICCOUT 3.6 3.6 0 1.2 to 3.6 1.2 to 3.6 3.6 3.3 µA µA µA µA IOH = –100 µA IOH = –2 mA IOH = –4 mA IOH = –6 mA IOH = –18 mA IOH = –24 mA IOL = 100 µA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 18 mA IOL = 24 mA VIN = GND or VCCIN control input VIN = VIH or VIL VIN, VOUT = 0 to 3.6 V IO(Y port) = 0 VIN = VCCIN or GND IO(Y port) = 0 VIN = VCCIN or GND A port or control VCCIN–0.6 (1 input) VIN = VCC or GND Increase in ICC per input Input capacitance ∆ICC CIN Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Switching Characteristics VCCIN = 3.3±0.3 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To Y Y Y 1.2 V Typ 9.6 9.6 OE OE 11.2 11.2 5.0 5.0 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A VCCOUT= 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 9.4 9.4 10.6 10.6 5.4 5.4 VCCOUT= 1.8±0.15 V Min 1.0 1.0 1.5 1.5 1.5 1.5 Max 6.0 6.0 6.8 6.8 4.7 4.7 VCCOUT= 2.5±0.2 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.0 4.0 4.2 4.2 4.0 4.0 VCCOUT= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.4 3.4 3.8 3.8 3.8 3.8 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ Rev.1.00 Jun. 01, 2005 page 4 of 9 RD74VT1G240 Switching Characteristics (Cont) VCCIN = 2.5±0.2 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To Y Y Y 1.2 V Typ 10.0 10.0 OE OE 11.6 11.6 5.2 5.2 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A VCCOUT= 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 9.4 9.4 11.4 11.4 5.0 5.0 VCCOUT= 1.8±0.15 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.0 6.0 7.2 7.2 4.7 4.7 VCCOUT= 2.5±0.2 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.0 4.0 4.8 4.8 4.0 4.0 VCCOUT= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 3.5 3.5 3.8 3.8 4.0 4.0 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ VCCIN = 1.8±0.15 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To Y Y Y 1.2 V Typ Typ 10.2 10.2 10.2 OE OE 11.6 11.6 11.6 5.8 5.8 5.8 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A VCCOUT= 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 9.8 9.8 11.8 11.8 5.6 5.6 VCCOUT= 1.8±0.15 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.5 6.5 7.6 7.6 5.4 5.4 VCCOUT= 2.5±0.2 V 2.5±0.2 Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.4 4.4 5.2 5.2 4.8 4.8 VCCOUT= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.1 4.1 4.4 4.4 5.0 5.0 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ VCCIN = 1.5±0.1 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To To Y Y Y 1.2 V 1.2 Typ Typ 11.4 11.4 11.4 OE OE OE OE 12.2 12.2 12.2 6.2 6.2 6.2 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A VCCOUT= 1.5±0.1 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 10.5 10.5 12.6 12.6 7.0 7.0 VCCOUT= 1.8±0.15 1.8±0.15 V Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 7.2 7.2 8.6 8.6 6.0 6.0 VCCOUT= 2.5±0.2 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.8 4.8 5.4 5.4 5.4 5.4 VCCOUT= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 Max 4.7 4.7 4.8 4.8 5.2 5.2 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ VCCIN = 1.2 V Ta = –40 to 85°C VCCOUT= From Item Propagation delay time Output enable time Output disable time To Y Y Y 1.2 V Typ 11.0 11.0 OE OE 12.8 12.8 7.0 7.0 Symbol (input) (output) tPLH tPHL tZH tZL tHZ tLZ A VCCOUT= 1.5±0.1 V Typ 7.5 7.5 9.5 9.5 6.0 6.0 VCCOUT= 1.8±0.15 V Typ 6.0 6.0 7.2 7.2 5.7 5.7 VCCOUT= 2.5±0.2 V Typ 4.5 4.5 5.2 5.2 5.5 5.5 VCCOUT= 3.3±0.3 V Typ 4.0 4.0 4.5 4.5 5.5 5.5 Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ Rev.1.00 Jun. 01, 2005 page 5 of 9 RD74VT1G240 Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol CPD VCCIN (V) 3.3 VCCOUT (V) 3.3 Min  Typ 12 Max  Unit pF Test conditions f = 10 MHz CL = 0 Power-up Considerations Level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up problems. 1. Connect ground before any supply voltage is applied. 2. Next, power up the control side of the device. (Power up of VCCIN is first. Next power up is VCCOUT) 3. Tie OE to VCCIN with a pull-up resistor so that it ramps with VCCIN. Test Circuit VCCIN VCCOUT Input Pulse Generator Z OUT = 50 Ω See Function Table Output RL=2.0kΩ S1 OPEN *1 see under table GND CL=15pF RL=2.0kΩ Symbol t PLH / tPHL t HZ / t ZH t LZ / t ZL S1 OPEN GND 2 × VCC Note: CL includes probe and jig capacitance. Rev.1.00 Jun. 01, 2005 page 6 of 9 RD74VT1G240 Waveforms–1 tr tf 90% Input A V ref 10% 90% V ref 10% VIH GND t PLH VOH t PHL Output Y V ref V ref VOL Symbol tr / t f V IH V ref V CC = 1.2 V to 3.6 V 2.0 ns VCC 1/2 VCC Note: 1. Input waveform : PRR ≤ 10 MHz, Zo = 50 Ω, duty cycle 50%. Rev.1.00 Jun. 01, 2005 page 7 of 9 RD74VT1G240 Waveforms–2 tr tf 90% Input OE V ref 10% 10% 90% V ref VIH GND t LZ t ZL VOH Waveform–1 V ref VL Output Y t ZH t HZ VOH VOL VH Waveform–2 V ref VOL V CC = 1.2 V, 1.5±0.1 V 2.0 ns VCC 1/2VCC VH = VOH-0.1 V VL = VOL+0.1 V Symbol tr / t f V IH V ref VH / V L V CC = 1.8±0.15 V V CC = 2.5±0.2 V 2.0 ns VCC 1/2VCC 2.0 ns VCC 1/2VCC V CC = 3.3±0.3 V 2.0 ns VCC 1/2VCC VH = VOH-0.15 V VH = VOH-0.15 V VH = VOH-0.3 V VL = VOL+0.15 V VL = VOL+0.15 V VL = VOL+0.3 V Notes: 1. Input waveform : PRR ≤ 10 MHz, ZO = 50 Ω, duty cycle 50% 2. 2. Waveform – 1 is for an output with internal conditions such that the output is low except except when disabled by the output control. 3. Waveform – 2 is for an output with internal conditions such that the output is high 3. except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.1.00 Jun. 01, 2005 page 8 of 9 RD74VT1G240 Package Dimensions JEITA Package Code S-XFBGA6-0.9x1.4-0.50 RENESAS Code SXBG0006KB-A Previous Code TBS-6AV MASS[Typ.] 0.001g e D ZD C B E B A 1 Pin#1 index area A 6 × φb y1 C 2 Reference Symbol e ZE Dimension in Millimeters Min Nom Max 0.50 0.155 0.185 (0.315) * 0.25 0.90 1.40 0.50 0.05 0.05 A A1 A2 b D 0.20 φ× M C A B φ× M C C Seating plane E e x A1 A2 A yC y y 1 D E 0.20 0.20 0.20 * Reference value. Z Z Rev.1.00 Jun. 01, 2005 page 9 of 9 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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