RD74VT1G245CLE

RD74VT1G245 Bus Transceiver with 3–state Output / Dual Supply Voltage Translator REJ03D0494–0200 Rev.2.00 Apr. 01, 2005 Description The RD74VT1G245 has one buffer in a 6 pin package. When DIR is high, data is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs to the A outputs. And this product has two terminals (VCCA, VCCB), VCCA is connected with control input and A bus side VCCB is connected with B bus side. VCCA and VCCB are isolated. The A port is designed to track VCCA, which accepts voltages from 1.2V to 3.6V, and the B port is designed to track VCCB, which operation at 1.2V to 3.6V. Therefore, Bidirectional board voltage conversion is which possible. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), possible. and the low power consumption extends the battery life. Features • This product function as level shift transceiver that change VCCA input level to VCCB output level, VCCB input level to VCCA output level by providing different supply voltage to VCCA and VCCB. • Supply voltage range: VCCA = 1.2 to 3.6 V VCCB = 1.2 to 3.6 V 40 • Operating temperature range: −40 to +85°C • Control input VI(max) = 3.6 V (@VCCA = 0 to 3.6 V) • A bus side input outputs VI/O (max) = 3.6 V (@VCCA = 0 V or Output off state) • B bus side input outputs VI/O (max) = 3.6 V (@VCCB = 0 V or Output off state) I/O • High output current A bus side: ±2 mA (@VCCA = 1.2 V) bus B bus side: ±2 mA (@VCCB = 1.2 V) ±4 mA (@VCCA = 1.5±0.1 V) ±4 ±4 mA (@VCCB = 1.5±0.1 V) ±6 ±6 mA (@VCCA = 1.8±0.15 V) ±6 mA (@VCCB = 1.8±0.15 V) ±18 mA (@VCCA = 2.5±0.2 V) ±18 ±18 mA (@VCCB = 2.5±0.2 V) ±24 mA (@VCCA = 3.3±0.3 V) ±24 ±24 mA (@VCCB = 3.3±0.3 V) • Ordering Information Part Part Name RD74VT1G245CLE Package Type WCSP–6 pin Package Code (Previous Code) SXBG0006KB–A (TBS–6AV) Package Abbreviation CL Taping Abbreviation (Quantity) E (3,000 pcs / reel) Rev.2.00 Apr. 01, 2005 page 1 of 13 RD74VT1G245 Article Indication Marking Year code Month code VYYM Function Table Input DIR L H H: High level L: Low level Operation B→A A→B Pin Arrangement 0.9 mm Height 0.5 mm 0.5 mm pitch 0.23 mm 6–Ball (CL) GND 3 4 B A 2 5 VCCB 1.4 mm Pin#1 INDEX DIR 1 6 VCCA (Bottom view) (Top view) Rev.2.00 Apr. 01, 2005 page 2 of 13 RD74VT1G245 Logic Diagram DIR A B Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Input/output voltage range *1, 2 Symbol VCCA, VCCB VI VI/O Ratings –0.5 to 4.6 –0.5 –0.5 to 4.6 –0.5 to VCCA+0.5 +0.5 –0.5 to 4.6 –0.5 –0.5 to VCCB+0.5 –0.5 –0.5 to 4.6 Unit V V V DIR Conditions A port output: “H” or “L” A port output: “Z” or VCCA: OFF port B port output: “H” or “L” B port output: “Z” or VCCB: OFF port Input clamp current Output clamp current Continuous output current Continuous output current VCC or GND Package Thermal impedance Storage temperature Notes: IIK IOK IO ICCA, ICCB, IGND CCA θja Tstg Tstg –50 –50 –50 50 ±50 ±100 123 –65 to 150 mA mA mA mA °C/W °C VI < 0 VO < 0 VO > VCC+0.5 The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two mu of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are 1. ratings observed. 2. This value is limited to 4.6 V maximum. 2. Rev.2.00 Apr. 01, 2005 page 3 of 13 RD74VT1G245 Recommended Operating Conditions Item Supply voltage range Input/Output voltage Symbol VCCA VCCB VI VI/O Ratings 1.2 to 3.6 1.2 to 3.6 0 to 3.6 0 to VCCA 0 to 3.6 0 to VCCB 0 to 3.6 Output current IOHA –2 –4 –6 –18 –24 IOHB –2 –4 –4 –6 –6 –18 –24 IOLA 2 4 6 18 18 24 IOLB 2 4 6 18 18 24 Input Input transition rise or fall time Operation free-air temperature ∆t / ∆v Ta Ta 10 –40 to 85 ns / V °C mA mA mA mA V V DIR A port output: “H” or “L” A port output: “Z” or VCCA: OFF B port output: “H” or “L” B port output: “Z” or VCCB: OFF VCCA = 1.2 V VCCA = 1.5±0.1 V VCCA = 1.8±0.15 V VCCA = 2.5±0.2 V VCCA = 3.3±0.3 V VCCB = 1.2 V VCCB = 1.5±0.1 V VCCB = 1.8±0.15 V VCCB = 2.5±0.2 V VCCB = 3.3±0.3 V VCCA = 1.2 V VCCA = 1.5±0.1 V VCCA = 1.8±0.15 V VCCA = 2.5±0.2 V VCCA = 3.3±0.3 V VCCB = 1.2 V VCCB = 1.5±0.1 V VCCB = 1.8±0.15 V VCCB = 2.5±0.2 V VCCB = 3.3±0.3 V Unit V Conditions Rev.2.00 Apr. 01, 2005 page 4 of 13 RD74VT1G245 Electrical Characteristics (Ta = −40 to 85°C) Item Input voltage Symbol VIHA VCCA (V) 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 * VCCB (V) 1.2 to 3.6 * VIHB VILA VILB 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 Output voltage VOH VOL Input current Off state output current Output leakage current Quiescent supply current IIN IOZ IOFF ICCA ICCB 1.2 to 3.6 1.2 1.5±0.1 1.5±0.1 1.8±0.15 1.8±0.15 2.5±0.2 2.5±0.2 3.3±0.3 1.2 1.2 to 3.6 1.2 1.5±0.1 1.5±0.1 1.8±0.15 1.8±0.15 2.5±0.2 2.5±0.2 3.3±0.3 3.3±0.3 3.6 3.6 0 1.2 to 3.6 1.2 to 3.6 3.6 3.6 3.3 3.3 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 3.6 3.6 0 1.2 to 3.6 1.2 to 3.6 3.6 3.6 3.3 3.3 Min VCCA×0.75 VCCA×0.70 VCCA×0.65 1.6 2.0 VCCB×0.75 VCCB×0.70 VCCB×0.65 1.6 2.0           VCC−0.2 0.9 1.1 1.25 1.7 2.2       –1.5 –1.5  –3.0 –3.0     Typ                                        3.5 6.0 Max           VCCA×0.25 VCCA×0.30 VCCA×0.35 0.7 0.8 VCCB×0.25 VCCB×0.30 VCCB×0.35 0.7 0.8       0.2 0.3 0.3 0.3 0.6 0.55 1.5 1.5 1.5 3.0 3.0 250 250   Unit V Test conditions A port Control input V B port V A port Control input V B port V V µA µA µA µA IOH = –100 µA IOH = –2 mA IOH = –4 mA IOH = –6 mA IOH = –18 mA IOH = –24 mA IOL = 100 µA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 18 mA IOL = 24 mA VIN = GND or VCCA control input VIN = VIH or VIL VIN, VOUT = 0 to 3.6 V IO(A port) = 0 VIN = VCCB or GND IO(B port) = 0 VIN = VCCA or GND A port or control VCCA–0.6 (1 input) B port VCCB–0.6 (1 input) VIN = VCC or GND VO = VCC or GND Increase in ICC per input ∆ICCA ∆ICCB µA Input capacitance Input/output capacitance CIN CI/O pF pF Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00 Apr. 01, 2005 page 5 of 13 RD74VT1G245 Switching Characteristics VCCA = 3.3±0.3 V Ta = –40 to 85°C VCCB= VCCB= 1.2 V 1.5±0.1 V From To Symbol (input) (output) Typ Min Max tPLH tPHL tPLH tPHL Output Disable time tHZ tLZ tHZ tLZ Output Enable time tZH tZL *1 VCCB= 1.8±0.15 V Min 1.5 1.5 1.0 1.0 1.0 1.0 1.5 1.5     Max 5.8 5.8 3.8 3.8 4.5 4.5 8.0 8.0 11.8 11.8 10.3 10.3 VCCB= 2.5±0.2 V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0     Max 4.0 4.0 3.4 3.4 4.5 4.5 6.0 6.0 9.4 9.4 8.5 8.5 VCCB= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0     Item Propagation delay time Test Max Unit conditions 3.2 3.2 3.2 3.2 4.5 4.5 5.5 5.5 8.7 8.7 7.7 7.7 ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ A B DIR DIR DIR DIR B A A B A B 9.1 9.1 4.0 4.0 4.0 4.0 11.2 11.2 15.2 15.2 13.1 13.1 2.0 2.0 1.0 1.0 1.0 1.0 2.0 2.0     8.8 8.8 4.2 4.2 4.5 4.5 10.2 10.2 14.4 14.4 13.3 13.3 *1 tZH*1 tZL*1 Note: 1. The enable time is a calculated value, derived using the formula shown in the section entitled enable times on ing page 12. VCCA = 2.5±0.2 V Ta = –40 to 85°C From To Symbol (input) (output) tPLH tPHL tPLH tPHL Output Disable time tHZ tLZ tHZ tLZ Output Enable time tZH*1 tZL*1 tZH*1 tZL Note: *1 VCCB= 1.2 1.2 V Typ 9.5 9.5 9.5 4.7 4.7 4.7 4.2 4.2 4.2 11.2 11.2 11.2 15.9 15.9 13.7 13.7 VCCB= 1.5±0.1 V Min 2.0 2.0 1.0 1.0 1.0 1.0 2.0 2.0     Max 9.2 9.2 4.8 4.8 4.7 4.7 10.6 10.6 15.4 15.4 13.9 13.9 VCCB= 1.8±0.15 V Min 1.5 1.5 1.0 1.0 1.0 1.0 1.5 1.5     Max 6. 6.0 6. 6.0 4. 4.6 4. 4.6 4. 4.7 4. 4.7 8.4 8. 8.4 13.0 13.0 10.7 10.7 VCCB= 2.5±0.2 V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0     Max 4.2 4.2 4.2 4.2 4.7 4.7 6.0 6.0 10.2 10.2 8.9 8.9 VCCB= 3.3±0.3 V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0     Item Propagation delay time Test Max Unit conditions 3.4 3.4 4.0 4.0 4.7 4.7 6.0 6.0 ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ A B DIR DIR DIR DIR DIR DIR DIR B A A B A B 10.0 10.0 8.1 8.1 ns CL = 15pF RL = 2.0kΩ 1. The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 12. Rev.2.00 Apr. 01, 2005 page 6 of 13 RD74VT1G245 Switching Characteristics (Cont.) VCCA = 1.8±0.15 V Ta = –40 to 85°C VCCB= VCCB= 1.2 V 1.5±0.1 V From To Symbol (input) (output) Typ Min Max tPLH tPHL tPLH tPHL Output Disable time tHZ tLZ tHZ tLZ Output Enable time tZH tZL *1 VCCB= 1.8±0.15 V Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5     Max 6.5 6.5 6.5 6.5 7.5 7.5 9.2 9.2 15.7 15.7 14.0 14.0 VCCB= 2.5±0.2 V Min 1.0 1.0 1.5 1.5 1.5 1.5 1.0 1.0     Max 4.6 4.6 6.0 6.0 7.5 7.5 7.2 7.2 13.2 13.2 12.1 12.1 VCCB= 3.3±0.3 V Min 1.0 1.0 1.5 1.5 1.5 1.5 1.0 1.0     Item Propagation delay time Test Max Unit conditions 3.8 3.8 5.8 5.8 7.5 7.5 7.0 7.0 ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ A B DIR DIR DIR DIR B A A B A B 9.8 9.8 6.4 6.4 5.5 5.5 12.0 12.0 18.4 18.4 15.3 15.3 2.0 2.0 1.5 1.5 1.5 1.5 2.0 2.0     9.6 9.6 7.2 7.2 7.5 7.5 11.5 11.5 18.7 18.7 17.1 17.1 12.8 12.8 11.3 11.3 *1 ns CL = 15pF RL = 2.0kΩ tZH*1 tZL*1 Note: 1. The enable time is a calculated value, derived using the formula shown in the section entitled enable times on ing page 12. VCCA = 1.5±0.1 V Ta = –40 to 85°C From To Symbol (input) (output) tPLH tPHL tPLH tPHL Output Disable time tHZ tLZ tHZ tLZ Output Enable time tZH*1 tZL*1 tZH*1 tZL Note: *1 VCCB= 1.2 1.2 V Typ 10.0 10.0 10.0 8.0 8.0 8.0 6.0 6.0 6.0 12.5 12.5 12.5 20.5 20.5 16.0 16.0 VCCB= 1.5±0.1 V Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0     Max 10.5 10.5 10.5 10.5 10.5 10.0 10.0 12.7 12.7 23.2 23.2 20.5 20.5 VCCB= 1.8±0.15 V Min 1.5 1.5 2.0 2.0 2.0 2.0 1.5 1.5     Max 7.2 7. 7.2 9.6 9. 9.6 10. 10.0 10. 10.0 12. 12.0 12. 12.0 21.6 21.6 17.2 17.2 VCCB= 2.5±0.2 V Min 1.0 1.0 2.0 2.0 2.0 2.0 1.0 1.0     Max 4.8 4.8 9.2 9.2 10.0 10.0 10.7 10.7 19.9 19.9 14.8 14.8 VCCB= 3.3±0.3 V Min 1.0 1.0 2.0 2.0 2.0 2.0 1.0 1.0     Item Propagation delay time Test Max Unit conditions 4.2 4.2 8.8 8.8 ns CL = 15pF RL = 2.0kΩ A B DIR DIR DIR DIR DIR DIR DIR B A A B A B 10.0 10.0 7.5 7.5 16.3 16.3 14.2 14.2 ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ 1. The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 12. Rev.2.00 Apr. 01, 2005 page 7 of 13 RD74VT1G245 Switching Characteristics (Cont.) VCCA = 1.2 V Ta = –40 to 85°C From To Symbol (input) (output) tPLH tPHL tPLH tPHL Output Disable time tHZ tLZ tHZ tLZ Output Enable time tZH tZL *1 VCCB= 1.2 V Typ 10.5 10.5 10.5 10.5 8.0 8.0 13.5 13.5 24.0 24.0 24.0 24.0 18.5 18.5 18.5 18.5 VCCB= VCCB= VCCB= 1.5±0.1 V 1.8±0.15 V 2.5±0.2 V Typ 8.0 8.0 10.0 10.0 8.0 8.0 10.5 10.5 20.5 20.5 16.0 16.0 Typ 6.4 6.4 9.8 9.8 8.0 8.0 9.5 9.5 19.3 19.3 14.4 14.4 Typ 4.7 4.7 9.5 9.5 8.0 8.0 7.5 7.5 17.0 17.0 12.7 12.7 VCCB= 3.3±0.3 V Typ 4.0 4.0 9.1 9.1 8.0 8.0 7.5 7.5 16.6 16.6 12.0 12.0 Item Propagation delay time Test Unit conditions ns CL = 15pF RL = 2.0kΩ A B DIR DIR DIR DIR B A A B A B ns CL = 15pF RL = 2.0kΩ *1 ns CL = 15pF RL = 2.0kΩ tZH*1 tZL*1 Note: 1. The enable time is a calculated value, derived using the formula shown in the section entitled enable times on ing page 12. Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol VCCA (V) VCCB (V) Min CCA CPD 3.3 3.3  Typ 12 Max  Unit pF Test conditions f = 10 MHz CL = 0 Power–up Power–up considerations Level–translation devices offer an opportunity for successful mixed–voltage signal design. for proper a A proper power–up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take Take these precautions to guard against such power–up problems. 1. 2. 3. Connect ground before any supply voltage is applied. Next, power up the control side of the device. (Power up of VCCA is first. Next power up is VCCB) Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with VCCA. Otherwise, DIR low is needed (B data to A bus), ramp it with GND. Rev.2.00 Apr. 01, 2005 page 8 of 13 RD74VT1G245 Test Circuit See under table 2 kΩ S1 OPEN GND *1 CL = 15 pF 2 kΩ Load circuit for outputs Symbol t PLH / tPHL t ZH / t HZ t ZL / t LZ S1 OPEN GND 2 × VCC Note: 1. CL includes probe and jig capacitance. Rev.2.00 Apr. 01, 2005 page 9 of 13 RD74VT1G245 • Waveforms – 1 tr 90 % Input Vref 10 % t PLH 90 % Vref 10 % t PHL VOH Vref Vref VOL tf VIH GND output • Waveforms – 2 90 % Vref 10 % tf 90 % 10 % t ZL Vref t ZH 90 % 10 % tr 90 % Vref 10 % t LZ VIH GND VOH VL t HZ Vref VH VOL VOH VOL Input DIR Output A or B Waveform–1 Output A or B Waveform–2 Symbol tr / t f V IH V ref VH / V L V CC = 1.2 V, 1.5±0.1 V 2.0 ns VCC 1/2 VCC VH = VOH-0.1 V VL = VOL+0.1 V V CC = 1.8±0.15 V V CC = 2.5±0.2 V 2.0 ns VCC 1/2 VCC 2.0 ns VCC 1/2 VCC V CC = 3.3±0.3 V 2.0 ns VCC 1/2 VCC VH = VOH-0.15 V VH = VOH-0.15 V VH = VOH-0.3 V VL = VOL+0.15 V VL = VOL+0.15 V VL = VOL+0.3 V Notes: 1. Input waveform : PRR ≤ 10 MHz, Zo = 50 Ω, duty cycle 50%. 2. Waveform – 1 is for an output with internal conditions such that the output is low 2. except when disabled by the output control. except 3. Waveform – 2 is for an output with internal conditions such that the output is high 3. except when disabled by the output control. except 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Apr. 01, 2005 page 10 of 13 RD74VT1G245 Application Information Figure 1 is an example circuit of the RD74VT1G245 being used in a bidirectional logic level–shifting application. VCC1 VCC2 1 VCC1 2 6 VCC2 5 3 4 SYSTEM–1 SYSTEM–2 SYSTEM–2 Figure 1. Bidirectional Logic Level–Shifting Application Pin Description PIN 1 2 3 4 5 6 NAME DIR A GND GND B VCCB VCCA FUNCTION DIR OUT GND IN VCC2 VCC1 DESCRIPTION DESCRIPTION The GND (low–level) determines B–port to A–port direction determines Output level depends on VCC1 voltage Device GND Input threshold value depends on VCC2 voltage SYSTEM–2 supply voltage (1.2V to 3.6V) SYSTEM–1 supply voltage (1.2V to 3.6V) Rev.2.00 Apr. 01, 2005 page 11 of 13 RD74VT1G245 Application Information (Cont.) Figure 2 shows the RD74VT1G245 used in a bidirectional logic level–shifting application. Since the RD74VT1G245 does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM–1 and SYSTEM–2 when changing directions. VCC1 Pullup/Down or Bus–Hold* VCC1 VCC2 VCC2 Pullup/Down I/O–1 1 6 or Bus–Hold* I/O–2 2 5 DIR CTRL 3 4 SYSTEM–1 SYSTEM–2 Notes: Notes: Following is a sequence that illustrates data transmission from SYSTEM–1 to SYSTEM–2 and then from SYSTEM–2 to SYSTEM–1. STATE DIR CTRL 1 2 3 H H L I/O–1 IN HI–Z HI–Z I/O–2 OUT HI–Z HI–Z DESCRIPTION SYSTEM–1 data to SYSTEM–2 SYSTEM–2 is getting ready to send data to SYSTEM–1. I/O–1 and SYSTEM–2 I/O–2 are disabled. The bus–line state depends on Pull–up or Down.* DIR bit is flipped. I/O–1 and I/O–2 are atill disabled. The bus–line state depends on Pull–up or Down.* SYSTEM–2 data to SYSTEM–1 4 L OUT IN *: SYSTEM–1 and SYSTEM–2 must use same conditions, i.e., both pull–up or both pull–down. Figure 2. Bidirectional Logic Level-Shifting Application Calculate the enable times for the RD74VT1G245 using the following formulas: 1. tZH (DIR to A) = tLZ (DIR to B) + tPLH (B to A) 2. tZL (DIR to A) = tHZ (DIR to B) + tPHL (B to A) 3. tZH (DIR to B) = tLZ (DIR to A) + tPLH (A to B) 4. tZL (DIR to B) = tHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the RD74VT1G245 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. Rev.2.00 Apr. 01, 2005 page 12 of 13 RD74VT1G245 Package Dimensions JEITA Package Code S-XFBGA6-0.9x1.4-0.50 RENESAS Code SXBG0006KB-A Previous Code TBS-6AV MASS[Typ.] 0.001g e D ZD C B E B A 1 Pin#1 index area A 6 × φb y1 C 2 Reference Symbol e ZE Dimension in Millimeters Min Nom Max 0.50 0.155 0.185 (0.315) * 0.25 0.90 1.40 0.50 0.05 0.05 A A1 A2 b D 0.20 φ× M C A B φ× M C C Seating plane E e x A1 A2 A yC y y 1 D E 0.20 0.20 0.20 * Reference value. Z Z Rev.2.00 Apr. 01, 2005 page 13 of 13 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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