RJM0306JSP_10

Preliminary Datasheet RJM0306JSP Silicon N / P Channel Power MOS FET High Speed Power Switching Features      Two elements each of N and P channels are incorporated (suitable for H-bridge circuit) High density mounting Low on-resistance Capable of 4 V gate drive High temperature D-S leakage guarantee Avalanche rating REJ03G1571-0101 Rev.1.01 May 28, 2010 Outline RENESAS Package code: PRSP0008DD-D (Package name: SOP-8 ) S7 Pin No. 1 2 D5 3 4 2G MOS1 Nch S3 4G MOS2 Nch 5 6 7 8 Element MOS1 (Nch) MOS4 (Pch) MOS1 (Nch) MOS1 (Nch) MOS2 (Nch) MOS2 (Nch) MOS2 (Nch) MOS3 (Pch) MOS3 (Pch) MOS3 (Pch) MOS4 (Pch) MOS4 (Pch) Drain Gate Source Gate Electrode Drain Gate Source Gate MOS4 Pch MOS3 Pch 6G 65 87 3 12 4 8G D1 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Avalanche current Avalanche energy Channel dissipation Channel dissipation Channel temperature Storage temperature Notes: 1. 2. 3. 4. Symbol VDSS VGSS ID ID (pulse)Note 1 Note 4 IAP Note 4 EAR PchNote 2 PchNote 3 Tch Tstg Value MOS1, 2 (Nch) 30 20 3.5 28 3.5 1.22 1.5 2.2 150 –55 to +150 MOS3, 4 (Pch) –30 20 –3.5 –28 –3.5 1.22 Unit V V A A A mJ W W C C PW  10 s, duty cycle  1% 1 Drive operation: When using the glass epoxy board (FR4 40  40  1.6 mm), PW  10 s 2 Drive operation: When using the glass epoxy board (FR4 40  40  1.6 mm), PW  10 s Value at Tch = 25C, Rg  50  REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 1 of 11 RJM0306JSP Preliminary Electrical Characteristics MOS1, 2 (Nch) (Ta = 25C) Item Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Zero gate voltage drain current Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Static drain to source on state resistance Static drain to source on state resistance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time Note: 5. Pulse test Symbol V(BR)DSS V(BR)GSS IDSS IDSS IGSS VGS(off) RDS(on) RDS(on) RDS(on) Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf VDF trr Min 30 20 — — — 1.0 — — — — — — — — — — — — — — — Typ — — — — — — 50 70 80 290 85 30 5.0 1.2 0.6 12 12 35 8 0.88 25 Max — — 1 10 10 2.5 65 105 130 — — — — — — — — — — 1.15 — Unit V V A A A V m m m pF pF pF nC nC nC ns ns ns ns V ns Test Conditions ID = 10 mA, VGS = 0 IG = 100 A, VDS = 0 VDS = 30 V, VGS = 0 VDS = 24 V, VGS = 0, Ta = 125C VGS = 16 V, VDS = 0 VDS = 10 V, ID = 1 mA ID = 2.0 ANote5, VGS = 10 V ID = 2.0 ANote5, VGS = 4.5 V ID = 2.0 ANote5, VGS = 4.0 V VDS = 10 V, VGS = 0 , f = 1 MHz VDD = 10 V, VGS = 10 V, ID = 3.5 A VGS = 10 V, ID = 2.0 A, VDD  10 V, RL = 5 , RG = 4.7  IF = 3.5 A, VGS = 0Note5 IF = 3.5A, VGS = 0 diF/dt = 100 A/s REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 2 of 11 RJM0306JSP MOS3, 4 (Pch) Preliminary (Ta = 25C) Item Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Zero gate voltage drain current Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Static drain to source on state resistance Static drain to source on state resistance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time Note: 5. Pulse test Symbol V(BR)DSS V(BR)GSS IDSS IDSS IGSS VGS(off) RDS(on) RDS(on) RDS(on) Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf VDF trr Min –30 20 — — — –1.0 — — — — — — — — — — — — — — — Typ — — — — — — 90 140 160 320 85 50 6.0 1.4 1.0 30 17 30 7 –0.92 30 Max — — –1 –10 10 –2.5 120 210 260 — — — — — — — — — — –1.2 — Unit V V A A A V m m m pF pF pF nC nC nC ns ns ns ns V ns Test Conditions ID = –10 mA, VGS = 0 IG = 100 A, VDS = 0 VDS = –30 V, VGS = 0 VDS = –24 V, VGS = 0, Ta = 125C VGS = 16 V, VDS = 0 VDS = –10 V, ID = –1 mA ID = –2.0 ANote5, VGS = –10 V ID = –2.0 ANote5, VGS = –4.5 V ID = –2.0 ANote5, VGS = –4.0 V VDS = –10 V, VGS = 0, f = 1 MHz VDD = –10 V, VGS = –10 V, ID = –3.5 A VGS = –10 V, ID= –2.0 A, VDD  –10 V, RL = 5.0 , RG = 4.7  IF = –3.5 A, VGS = 0Note5 IF = –3.5 A, VGS = 0 diF/dt = 100 A/s REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 3 of 11 RJM0306JSP Preliminary Main Characteristics MOS1, 2 (Nch) Maximum Safe Operation Area 100 10 DC Typical Output Characteristics 10 4.2 V 4.5 V 10 V 5 3.2 V 3.8 V Drain Current ID (A) PW Op er ati =1 1 0m on s( 1s (P ho W t) 0.1 Operation in this area is limited by RDS (on) ≤1 0 s ote6 ) N Drain Current ID (A) 10 μs 0 1 m μs s 10 2.8 V 0.01 0.001 0.1 Ta = 25°C 1 shot Pulse Pulse Test 1 10 100 0 5 VGS = 0 V 10 Drain to Source Voltage VDS (V) Note 6: When using the glass epoxy board (FR4 40 × 40 × 1.6 mm) Drain to Source Voltage VDS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS (on) (mΩ) 1000 Typical Transfer Characteristics 10 1 0.1 0.01 0.001 0.0001 0.00001 0 VDS = 10 V Pulse Test Drain Current ID (A) 100 4.5 V VGS = 4 V Tc = 150°C 25°C −40°C 1 2 3 4 5 10 V 10 0.1 1 Pulse Test 10 Gate to Source Voltage VGS (V) Static Drain to Source on State Resistance vs. Temperature 200 Pulse Test ID = 2 A 1000 Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage VGS = 0 f = 1 MHz Ciss Static Drain to Source on State Resistance RDS (on) (mΩ) 150 VGS = 4 V 100 4.5 V Capacitance C (pF) 100 Coss 50 10 V 0 −50 Crss −25 10 0 25 50 75 100 125 150 0 10 20 30 40 50 Case Temperature Tc (°C) Drain to Source Voltage VDS (V) REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 4 of 11 RJM0306JSP MOS1, 2 (Nch) Reverse Drain Current vs. Source to Drain Voltage Gate to Source Voltage VGS (V) 20 VGS 16 10 Preliminary Dynamic Input Characteristics Drain to Source Voltage VDS (V) 50 Reverse Drain Current IDR (A) ID = 3.5 A VDD = 25 V 10 V 5V VDS 10 V 5V 40 30 12 5 VGS = 0 V, –5 V 20 VDD = 25 V 10 V 5V 2 4 6 8 8 10 4 0 Pulse Test 0 0.4 0.8 1.2 1.6 2.0 0 10 Gate Charge Qg (nc) Maximum Avalanche Energy vs. Channel Temperature Derating Repetitive Avalanche Energy EAR (mJ) Source to Drain Voltage VSD (V) 2 L = 100 μH VDD = 15 V duty < 0.1 % Rg ≥ 50 Ω 1.5 1 0.5 0 25 50 75 100 125 150 Channel Temperature Tch (°C) Avalanche Test Circuit VDS Monitor L IAP Monitor EAR = Avalanche Waveform 1 2 L • IAP2 • VDSS VDSS – VDD V (BR)DSS Rg D. U. T VDD IAP VDS Vin 15 V 50 Ω ID 0 VDD REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 5 of 11 RJM0306JSP MOS1, 2 (Nch) Switching Time Test Circuit Vin Monitor D.U.T. Rg RL VDS = 10 V 90% td(on) tr 90% td(off) Vin Vout Vin 10 V 10% 10% Vout Monitor Preliminary Switching Time Waveform 90% 10% tf REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 6 of 11 RJM0306JSP MOS3, 4 (Pch) Maximum Safe Operation Area −100 −10 PW Preliminary Typical Output Characteristics −10 −4.5 V Pulse Test −5.0 V −10 V −4.0 V Drain Current ID (A) −1 −0.1 −0.01 DC =1 Op 0m er s( ati 1s on ho t) Drain Current ID (A) 10 μs 0 1 m μs s 10 (P −5 −3.0 V −2.5 V VGS = 0 V W Operation in this area is limited by RDS (on) Ta = 25°C 1 shot Pulse ≤1 0 s ote6 ) N −0.001 −0.1 −1 −10 −100 0 −5 −10 Drain to Source Voltage VDS (V) Note 6: When using the glass epoxy board (FR4 40 × 40 × 1.6 mm) Drain to Source Voltage VDS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS (on) (mΩ) 10000 Pulse Test Typical Transfer Characteristics −10 VDS = −10 V −1 Pulse Test Drain Current ID (A) −0.1 −0.01 −0.001 1000 VGS = −4 V −4.5 V Tc = 150°C 25°C −40°C −1 −2 −3 −4 −5 100 −10 V −0.0001 −0.00001 0 10 −0.1 −1 −10 Gate to Source Voltage VGS (V) Static Drain to Source on State Resistance vs. Temperature 250 ID = −2 A VGS = −4 V 1000 Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage VGS = 0 f = 1 MHz Static Drain to Source on State Resistance RDS (on) (mΩ) 150 −4.5 V −10 V Capacitance C (pF) 200 Ciss 100 Coss Crss 100 50 Pulse Test 0 −50 −25 0 25 50 75 100 125 150 10 −0 −10 −20 −30 −40 −50 Case Temperature Tc (°C) Drain to Source Voltage VDS (V) REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 7 of 11 RJM0306JSP MOS3, 4 (Pch) Reverse Drain Current vs. Source to Drain Voltage Gate to Source Voltage VGS (V) 0 –10 Preliminary Dynamic Input Characteristics Drain to Source Voltage VDS (V) 0 –10 –4 Reverse Drain Current IDR (A) VDD = –25 V –10 V –5 V –10 V –20 VDS VDD = –25 V –10 V –5 V –8 VGS –12 –5 –5 V VGS = 0 V, 5 V Pulse Test 0 –0.4 –0.8 –1.2 –1.6 –2.0 –30 –40 ID = –3.5 A –50 0 2 4 6 8 –16 –20 10 Gate Charge Qg (nc) Source to Drain Voltage VSD (V) Maximum Avalanche Energy vs. Channel Temperature Derating Repetitive Avalanche Energy EAR (mJ) 2 L = 100 μH VDD = –15 V duty < 0.1 % Rg ≥ 50 Ω 1.5 1 0.5 0 25 50 75 100 125 150 Channel Temperature Tch (°C) Avalanche Test Circuit VDS Monitor L EAR = IAP Monitor Rg Avalanche Waveform 1 2 VDSS VDSS – VDD L • IAP2 • V(BR)DSS D. U. T VDD IAP VDS ID Vin –15 V 50 Ω 0 VDD REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 8 of 11 RJM0306JSP MOS3, 4 (Pch) Switching Time Test Circuit Vin Monitor D.U.T. Rg RL VDD = –10 V Vout td(on) Vout Monitor Vin 10% 90% 90% Preliminary Switching Time Waveform Vin –10 V 90% 10% td(off) 10% tf tr REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 9 of 11 RJM0306JSP Common Power vs. Temperature Derating 4.0 Preliminary Pch (W) 3.0 Test Condition: When using the glass epoxy board (FR4 40 × 40 × 1.6 mm), PW ≤ 10 s Channel Dissipation 2.0 2 Dr ive O 1.0 1D pe riv ra eO tio pe n rat ion 0 50 100 150 200 Case Temperature Tc (°C) Normalized Transient Thermal Impedance γs (t) Normalized Transient Thermal Impedance vs. Pulse Width (1 Drive Operation) 10 1 D=1 0.5 0.2 0.1 0.05 0.02 0.1 0.01 1 1 0.0 lse t pu sho θch - f(t) = γs (t) x θch - f θch - f = 125°C/W, Ta = 25°C When using the glass epoxy board (FR4 40x40x1.6 mm) PDM D= PW T 0.001 PW T 0.0001 10 μ 100 μ 1m 10 m 100 m 1 10 100 1000 10000 Pulse Width PW (S) Normalized Transient Thermal Impedance γs (t) Normalized Transient Thermal Impedance vs. Pulse Width (2 Drive Operation) 10 1 D=1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 1sh ot p uls e θch - f(t) = γs (t) x θch - f θch - f = 210°C/W, Ta = 25°C When using the glass epoxy board (FR4 40x40x1.6 mm) PDM PW T 0.001 D= PW T 0.0001 10 μ 100 μ 1m 10 m 100 m 1 10 100 1000 10000 Pulse Width PW (S) REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 10 of 11 RJM0306JSP Preliminary Package Dimensions Package Name SOP-8 JEITA Package Code P-SOP8-3.95 × 4.9-1.27 RENESAS Code PRSP0008DD-D Previous Code FP-8DAV MASS[Typ.] 0.085g *1 D F 8 5 *2 E HE bp Index mark 1 Z e 4 * 3 bp xM c Terminal cross section (Ni/Pd/Au plating) NOTE) 1. DIMENSIONS "*1(Nom)" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Reference Dimension in Millimeters Symbol Min L1 L D E A2 A1 A bp b1 c c1 HE e x y Z L L1 Nom Max 4.90 5.3 3.95 A 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 A1 y Detail F 0° 8° 5.80 6.10 6.20 1.27 0.25 0.1 0.75 0.40 0.60 1.27 1.08 Ordering Information Part No. RJM0306JSP-00-J0 Quantity 2500 pcs Taping Shipping Container REJ03G1571-0101 Rev.1.01 May 28, 2010 Page 11 of 11 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. 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