Datasheet
RL78/G14
RENESAS MCU
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
True Low Power Platform (as low as 66 A/MHz, and 0.60 A for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 256 Kbyte Flash, 44 DMIPS at 32 MHz, for General Purpose Applications
1. OUTLINE
1.1 Features
Data Transfer Controller (DTC) • 39 sources & 24 different settings • Transfer data: 8 bits/16 bits • Normal mode and repeat mode Event Link Controller (ELC) • Reduce interrupt intervention • Link 26 events to specified peripheral function Multiple Communication Interfaces • Up to 8 x I2C master • Up to 2 x I2C multi-master • Up to 8 x CSI/SPI (7-, 8-bit) • Up to 4 x UART (7-, 8-, 9-bit) • Up to 1 x LIN Extended-Function Timers • Multi-function 16-bit timers: Up to 8 channels • Motor control timer (3 ph - complementary mode) • Timer with encoder function: 16-bit, 1 channel • Real-time clock (RTC): 1 channel (full calendar and alarm function with watch correction function) • Interval timer: 12-bit, 1 channel • 15 kHz watchdog timer: 1 channel (window function) Rich Analog Ultra-Low Power Technology • 1.6 V to 5.5 V operation from a single supply • Stop (RAM retained): 0.24 A, (LVD enabled): 0.32 A • Halt (RTC + LVD): 0.60 A • Snooze: T.B.D • Operating: 66 A/MHz 16-bit RL78 CPU Core • Delivers 44 DMIPS at maximum operating frequency of 32 MHz • Instruction execution: 86% of instructions can be executed in 1 to 2 clock cycles • CISC architecture (Harvard) with 3-stage pipeline • Multiply signed & unsigned: 16 x 16 to 32-bit result in 1 clock cycle • MAC: 16 x 16 to 32-bit result in 2 clock cycles • 16-bit barrel shifter for shift & rotate in 1 clock cycle • 1-wire on-chip debug function Code Flash Memory • Density: 16 KB to 256 KB • Block size: 1KB • On-chip single voltage flash memory with protection from block erase/writing • Self-programming with secure boot swap function and flash shield window function Data Flash Memory • Data flash with background operation • Data flash size: 4 KB to 8 KB size options • Erase cycles: 1 Million (typ.) • Erase/programming voltage: 1.8 V to 5.5 V RAM • 2.5 KB to 24 KB size options • Supports operands or instructions • Back-up retention in all modes High-speed On-chip Oscillator • 32 MHz with +/- 1% accuracy over voltage (1.8 V to 5.5 V) and temperature (-20°C to 85°C) • Pre-configured settings: 64 MHz,48 MHz,32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 4 MHz & 1 MHz • 64 MHz, 48 MHz for timer RD Reset and Supply Management • Power-on reset (POR) monitor/generator • Low voltage detection (LVD) with 14 setting options (Interrupt and/or reset function) General Purpose I/O • 5 V tolerant, high-current (up to 20 mA per pin) • Open-drain, on-chip pull-up resistor
• ADC: Up to 20 channels, 10-bit resolution, 2.1 s
• • • • • conversion time Supports 1.6 V 2 x window comparators, with ELC connection D/A converter: 2 channels, 8-bit resolution Internal voltage reference (1.45 V) On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance) • Flash memory CRC calculation • RAM parity error check • RAM write protection • SFR write protection • Illegal memory access detection • Clock stop/frequency detection • ADC self-test • I/O port read back function (echo) Operating Ambient Temperature • Standard: -40°C to + 85°C • Extended: -40°C to + 105°C Package Type and Pin Count From 4 mm x 4 mm to 14 mm x 20 mm QFP: 32, 44, 48, 52, 64, 80,100 QFN: 32, 40, 48 SSOP: 30 LGA: 36, 64
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RL78/G14
ROM, RAM capacities
RL78/G14 Flash ROM 192 KB 128 KB 96 KB 64 KB 48 KB 32 KB 16 KB Data flash 8 KB 8 KB 8 KB 4 KB 4 KB 4 KB 4 KB RAM 30 pins 20 KB 16 KB 12 KB 5.5 KB Note 1 5.5 KB Note 1 4 KB 2.5 KB — R5F104AG R5F104AF R5F104AE R5F104AD R5F104AC R5F104AA 32 pins — R5F104BG R5F104BF R5F104BE R5F104BD R5F104BC R5F104BA 36 pins — R5F104CG R5F104CF R5F104CE R5F104CD R5F104CC R5F104CA
1. OUTLINE
40 pins R5F104EH R5F104EG R5F104EF R5F104EE R5F104ED R5F104EC R5F104EA
RL78/G14 Flash ROM 256 KB 192 KB 128 KB 96 KB 64 KB 48 KB 32 KB 16 KB Data flash 8 KB 8 KB 8 KB 8 KB 4 KB 4 KB 4 KB 4 KB RAM 44 pins 24 KB
Note 2
48 pins R5F104GJ R5F104GH R5F104GG R5F104GF R5F104GE R5F104GD R5F104GC R5F104GA
52 pins R5F104JJ R5F104JH R5F104JG R5F104JF R5F104JE R5F104JD R5F104JC —
64 pins R5F104LJ R5F104LH R5F104LG R5F104LF R5F104LE R5F104LD R5F104LC —
R5F104FJ R5F104FH R5F104FG R5F104FF R5F104FE R5F104FD R5F104FC R5F104FA
20 KB 16 KB 12 KB 5.5 KB Note 1 5.5 KB Note 1 4 KB 2.5 KB
RL78/G14 Flash ROM 256 KB 192 KB 128 KB 96 KB Note 1. Note 2. Data flash 8 KB 8 KB 8 KB 8 KB RAM 80 pins 24 KB
Note 2
100 pins R5F104PJ R5F104PH R5F104PG R5F104PF
R5F104MJ R5F104MH R5F104MG R5F104MF
20 KB 16 KB 12 KB
This is about 4.5 KB when the self-programming function and data flash function are used. This is about 23 KB when the self-programming function and data flash function are used.
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RL78/G14
1. OUTLINE
1.2
Ordering Information
(1/2)
Pin count 30 pins
Package 30-pin plastic SSOP (7.62 mm (300))
Part Number R5F104AAASP, R5F104ACASP, R5F104ADASP, R5F104AEASP, R5F104AFASP, R5F104AGASP R5F104AADSP, R5F104ACDSP, R5F104ADDSP, R5F104AEDSP, R5F104AFDSP, R5F104AGDSP
32 pins
32-pin plastic WQFN (fine pitch) (5 × 5)
R5F104BAANA, R5F104BCANA, R5F104BDANA, R5F104BEANA, R5F104BFANA, R5F104BGANA R5F104BADNA, R5F104BCDNA, R5F104BDDNA, R5F104BEDNA, R5F104BFDNA, R5F104BGDNA
32-pin plastic LQFP (7 × 7)
R5F104BAAFP, R5F104BCAFP, R5F104BDAFP, R5F104BEAFP, R5F104BFAFP, R5F104BGAFP R5F104BADFP, R5F104BCDFP, R5F104BDDFP, R5F104BEDFP, R5F104BFDFP, R5F104BGDFP
36 pins
36-pin plastic FLGA (4 × 4)
R5F104CAALA, R5F104CCALA, R5F104CDALA, R5F104CEALA, R5F104CFALA, R5F104CGALA R5F104CADLA, R5F104CCDLA, R5F104CDDLA, R5F104CEDLA, R5F104CFDLA, R5F104CGDLA
40 pins
40-pin plastic WQFN (fine pitch) (6 × 6)
R5F104EAANA, R5F104ECANA, R5F104EDANA, R5F104EEANA, R5F104EFANA, R5F104EGANA, R5F104EHANA R5F104EADNA, R5F104ECDNA, R5F104EDDNA, R5F104EEDNA, R5F104EFDNA, R5F104EGDNA, R5F104EHDNA
44 pins
44-pin plastic LQFP (10 × 10)
R5F104FAAFP, R5F104FCAFP, R5F104FDAFP, R5F104FEAFP, R5F104FFAFP, R5F104FGAFP, R5F104FHAFP, R5F104FJAFP R5F104FADFP, R5F104FCDFP, R5F104FDDFP, R5F104FEDFP, R5F104FFDFP, R5F104FGDFP, R5F104FHDFP, R5F104FJDFP
48 pins
48-pin plastic LQFP (fine pitch) (7 × 7)
R5F104GAAFB, R5F104GCAFB, R5F104GDAFB, R5F104GEAFB, R5F104GFAFB, R5F104GGAFB, R5F104GHAFB, R5F104GJAFB R5F104GADFB, R5F104GCDFB, R5F104GDDFB, R5F104GEDFB, R5F104GFDFB, R5F104GGDFB, R5F104GHDFB, R5F104GJDFB
48-pin plastic WQFN (7 × 7)
R5F104GAANA, R5F104GCANA, R5F104GDANA, R5F104GEANA, R5F104GFANA, R5F104GGANA, R5F104GHANA, R5F104GJANA R5F104GADNA, R5F104GCDNA, R5F104GDDNA, R5F104GEDNA, R5F104GFDNA, R5F104GGDNA, R5F104GHDNA, R5F104GJDNA
52 pins
52-pin plastic LQFP (10 × 10)
R5F104JCAFA, R5F104JDAFA, R5F104JEAFA, R5F104JFAFA, R5F104JGAFA, R5F104JHAFA, R5F104JJAFA R5F104JCDFA, R5F104JDDFA, R5F104JEDFA, R5F104JFDFA, R5F104JGDFA, R5F104JHDFA, R5F104JJDFA
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RL78/G14
1. OUTLINE
(2/2) Pin count 64 pins Package 64-pin plastic LQFP (12 × 12) Part Number R5F104LCAFA, R5F104LDAFA, R5F104LEAFA, R5F104LFAFA, R5F104LGAFA, R5F104LHAFA, R5F104LJAFA R5F104LCDFA, R5F104LDDFA, R5F104LEDFA, R5F104LFDFA, R5F104LGDFA, R5F104LHDFA, R5F104LJDFA 64-pin plastic LQFP (fine pitch) (10 × 10) R5F104LCAFB, R5F104LDAFB, R5F104LEAFB, R5F104LFAFB, R5F104LGAFB, R5F104LHAFB, R5F104LJAFB R5F104LCDFB, R5F104LDDFB, R5F104LEDFB, R5F104LFDFB, R5F104LGDFB, R5F104LHDFB, R5F104LJDFB 64-pin plastic FLGA (5 × 5) R5F104LCALA, R5F104LDALA, R5F104LEALA, R5F104LFALA, R5F104LGALA, R5F104LHALA, R5F104LJALA R5F104LCDLA, R5F104LDDLA, R5F104LEDLA, R5F104LFDLA, R5F104LGDLA, R5F104LHDLA, R5F104LJDLA 64-pin plastic LQFP (14 × 14) R5F104LCAFP, R5F104LDAFP, R5F104LEAFP, R5F104LFAFP, R5F104LGAFP, R5F104LHAFP, R5F104LJAFP R5F104LCDFP, R5F104LDDFP, R5F104LEDFP, R5F104LFDFP, R5F104LGDFP, R5F104LHDFP, R5F104LJDFP 80 pins 80-pin plastic LQFP (fine pitch) (12 × 12) 80-pin plastic LQFP (14 × 14) 100 pins R5F104MFAFB, R5F104MGAFB, R5F104MHAFB, R5F104MJAFB R5F104MFDFB, R5F104MGDFB, R5F104MHDFB, R5F104MJDFB R5F104MFAFA, R5F104MGAFA, R5F104MHAFA, R5F104MJAFA R5F104MFDFA, R5F104MGDFA, R5F104MHDFA, R5F104MJDFA 100-pin plastic LQFP (fine pitch) (14 × 14) R5F104PFAFB, R5F104PGAFB, R5F104PHAFB, R5F104PJAFB R5F104PFDFB, R5F104PGDFB, R5F104PHDFB, R5F104PJDFB 100-pin plastic LQFP (14 × 20) R5F104PFAFA, R5F104PGAFA, R5F104PHAFA, R5F104PJAFA R5F104PFDFA, R5F104PGDFA, R5F104PHDFA, R5F104PJDFA
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RL78/G14
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14
1. OUTLINE
Part No. R 5 F 1 0 4 L E A x x x F B
Package type: SP: SSOP, 0.65 mm pitch FP: LQFP, 0.80 mm pitch FA: LQFP, 0.65 mm pitch FB: LQFP, 0.50 mm pitch NA: WQFN, 0.50 mm pitch LA: LGA, 0.50 mm pitch ROM number (Omitted with blank products) Classification: A: Consumer applications, operating ambient temperature: -40°C to 85°C D: Industrial applications, operating ambient temperature: -40°C to 85°C ROM capacity: A: 16 KB C: 32 KB D: 48 KB E: 64 KB F: 96 KB G: 128 KB H: 192 KB J: 256 KB Pin count: A: 30-pin B: 32-pin C: 36-pin E: 40-pin F: 44-pin G: 48-pin J: 52-pin L: 64-pin M: 80-pin P: 100-pin RL78/G14 Memory type: F : Flash memory Renesas MCU Renesas semiconductor product
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RL78/G14
1. OUTLINE
1.3 1.3.1
Pin Configuration (Top View) 30-pin products
• 30-pin plastic SSOP (7.62 mm (300))
P20/ANI0/AVREFP P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3 P147/ANI18/VCOUT1 Note P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/SCK00/SCL00/TRJO0
Note Caution
Mounted on the 96 KB or more code flash memory products. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
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RL78/G14
1. OUTLINE
1.3.2
32-pin products
• 32-pin plastic WQFN (fine pitch) (5 × 5) • 32-pin plastic LQFP (7 × 7)
P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) exposed die pad P147/ANI18/VCOUT1 Note P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 12345678
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/SCK00/SCL00/TRJO0 P70 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P62/SSI00 P61/SDAA0 P60/SCLA0
Note Caution
Mounted on the 96 KB or more code flash memory products. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD
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RL78/G14
1. OUTLINE
1.3.3
36-pin products
Top View Bottom View
• 36-pin plastic FLGA (4 × 4)
6 5 4 3 2 1 A B C D E F F E D C B A
INDEX MARK
A P60/SCLA0 6 P62/SSI00 VDD
B
C P121/X1
D P122/X2/EXCLK
E P137/INTP0
F P40/TOOL0 6
P61/SDAA0
VSS
REGC
5
RESET
P120/ANI19/ VCOUT0 Note 5
P72/SO21 4 P50/INTP1/ SI00/RxD0/ 3 TOOLRxD/ SDA00/TRGIOA/ (TRJO0) P30/INTP3/ 2 SCK00/SCL00/ TRJO0
P71/SI21/ SDA21
P14/RxD2/SI20/ (SCLA0)
P31/TI03/TO03/ (TRJIO0) P22/ANI2/ ANO0 Note
P00/TI00/TxD1/ (TRJO0) P20/ANI0/ AVREFP
P01/TO00/ RxD1/TRGCLKB/ TRJIO0 P21/ANI1/ AVREFM 3 4
SDA20/TRDIOD0/ INTP4/PCLBUZ0/ TRGCLKA/ P15/PCLBUZ1/ SCK20/SCL20/ TRDIOB0/ (SDAA0)
P70/SCK21/ SCL21
P16/TI01/TO01/ INTP5/TRDIOC0/ IVREF0 Note/ (RXD0) P17/TI02/TO02/ TRDIOA0/ TRDCLK0/ IVCMP0 Note/ (TXD0) B
P12/SO11/ TRDIOB1/ IVREF1 Note P13/TxD2/ SO20/TRDIOA1/ IVCMP1 Note
P11/SI11/ SDA11/ TRDIOC1
P24/ANI4
P23/ANI3/ ANO1 Note 2
P51/INTP2/ SO00/TxD0/ 1 TOOLTxD/ TRGIOB
P10/SCK11/ SCL11/ TRDIOD1
P147/ANI18/ VCOUT1 Note
P25/ANI5 1
A Note Caution
C
D
E
F
Mounted on the 96 KB or more code flash memory products. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
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RL78/G14
1. OUTLINE
1.3.4
40-pin products
• 40-pin plastic WQFN (fine pitch) (6 × 6)
P147/ANI18/VCOUT1 Note P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1/TRGCLKB/TRJIO0 P00/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note 30 29 28 27 26 25 24 23 22 21 20 31 exposed die pad 19 32 18 33 17 34 16 35 15 36 14 37 13 38 12 39 11 40 1 2 3 4 5 6 7 8 9 10
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P62/SSI00 P61/SDAA0 P60/SCLA0
Note Caution
Mounted on the 96 KB or more code flash memory products. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
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P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD
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RL78/G14
1. OUTLINE
1.3.5
44-pin products
• 44-pin plastic LQFP (10 × 10)
P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1/TRGCLKB/TRJIO0 P00/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0
Note Caution
Mounted on the 96 KB or more code flash memory products. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
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P41 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD
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1. OUTLINE
1.3.6
48-pin products
• 48-pin plastic LQFP (fine pitch) (7 × 7)
P00/TI00/TxD1/TRGCLKA/(TRJO0) P01/TO00/RxD1/TRGCLKB/TRJIO0 P130
P140/PCLBUZ0/INTP6
P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3/ANO1 Note
P24/ANI4 P25/ANI5
P120/ANI19/VCOUT0 Note P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD
36 35 34 33 32 31 30 29 28 27 26 25 24 37 23 38 22 39 21 40 20 41 19 42 18 43 17 44 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12
P26/ANI6 P27/ANI7
P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
Note Caution
Mounted on the 96 KB or more code flash memory products. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
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P61/SDAA0 P62/SSI00 P63 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P60/SCLA0
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RL78/G14
• 48-pin plastic WQFN (7 × 7)
P00/TI00/TxD1/TRGCLKA/(TRJO0) P01/TO00/RxD1/TRGCLKB/TRJIO0 P130
1. OUTLINE
P140/PCLBUZ0/INTP6
P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3/ANO1 Note
P24/ANI4 P25/ANI5
P120/ANI19/VCOUT0 Note P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD
36 35 34 33 32 31 30 29 28 27 26 25 24 37 exposed die pad 23 38 22 39 21 40 20 41 19 42 18 43 17 44 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12
P26/ANI6 P27/ANI7
P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
Note Caution
Mounted on the 96 KB or more code flash memory products. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
P61/SDAA0 P62/SSI00 P63 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P60/SCLA0
Page 12 of 97
RL78/G14
1. OUTLINE
1.3.7
52-pin products
• 52-pin plastic LQFP (10 × 10)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
39 38 37 36 35 34 33 32 31 30 29 28 27 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P03/ANI16/RxD1 P02/ANI17/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 34 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P146 P10/SCK11/SCL11/TRDIOD1
P147/ANI18/VCOUT1 Note
P12/SO11/TRDIOB1/IVREF1 Note
P11/SI11/SDA11/TRDIOC1
P120/ANI19/VCOUT0 Note
P40/TOOL0
P123/XT1
P122/X2/EXCLK
P140/PCLBUZ0/INTP6
RESET P124/XT2/EXCLKS
P137/INTP0
P121/X1
Note Caution
Mounted on the 96 KB or more code flash memory products. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
P41/(TRJIO0)
REGC
VDD
VSS
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
Page 13 of 97
RL78/G14
1. OUTLINE
1.3.8
64-pin products
• 64-pin plastic LQFP (14 × 14) • 64-pin plastic LQFP (12 × 12) • 64-pin plastic LQFP (fine pitch) (10 × 10)
P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00)/(INTP4) P54/(INTP3) P53/(INTP2) P52/(INTP1) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 60 61 62 63 64 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P05/(INTP10) P06/(INTP11)/(TRJIO0) P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0
Note
Mounted on the 96 KB or more code flash memory products.
Caution 1. Make EVSS0 pin the same potential as VSS pin. Caution 2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD a nd EVDD0 p ins and connect the V SS a nd EV SS0 p ins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
P120/ANI19/VCOUT0 Note P43/(INTP9) P42/(INTP8) P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0
Page 14 of 97
RL78/G14
• 64-pin plastic FLGA (5 × 5)
Top View Bottom View
1. OUTLINE
8 7 6 5 4 3 2 1 AB CDEF GH HGFEDCBA
INDEX MARK
A 8 EVDD0 EVSS0
B
C P121/X1
D P122/X2/ EXCLK
E P137/INTP0
F P123/XT1
G P124/XT2/ EXCLKS
H P120/ANI19/ VCOUT0 Note P140/ PCLBUZ0/ INTP6 P141/ PCLBUZ1/ INTP7 6 7 8
P60/SCLA0 7
VDD
VSS
REGC
RESET
P01/TO00/ TRGCLKB/ TRJIO0
P00/TI00/ TRGCLKA/ (TRJO0) P02/ANI17/ SO10/TxD1
P61/SDAA0 6
P62/SSI00
P63
P40/TOOL0
P41/(TRJIO0)
P43/(INTP9)
P77/KR7/ 5
P31/TI03/ (PCLBUZ0)/ (TRJIO0)
P53/(INTP2)
P42/(INTP8)
P03/ANI16/ SI10/RxD1/ SDA10
P04/SCK10/ SCL10
P130
P20/ANI0/ AVREFP 5
INTP11/(TXD2) TO03/INTP4/
P75/KR5/ INTP9/ 4 SCK01/ SCL01
P76/KR6/ INTP10/ (RXD2)
P52/(INTP1)
P54/(INTP3)
P16/TI01/ TO01/INTP5/ TRDIOC0/ IVREF0 Note/ (SI00)/(RXD0)
P21/ANI1/ AVREFM
P22/ANI2/ ANO0 Note
P23/ANI3/ ANO1 Note 4
P70/KR0/ SCK21/ 3 SCL21
P73/KR3/ SO01
P74/KR4/ INTP8/SI01/ SDA01
P17/TI02/TO02/ P15/SCK20/ TRDIOA0/ SCL20/ TRDCLK0/ IVCMP0 Note/ (SO00)/(TXD0) TRDIOB0/ (SDAA0) P14/RxD2/ SI20/SDA20/ TRDIOD0/ (SCLA0)
P12/SO11/ TRDIOB1/ IVREF1 Note/ (INTP5)
P24/ANI4
P26/ANI6 3
P30/INTP3/ 2 RTC1HZ/ SCK00/ SCL00/TRJO0 P05/(INTP10)
P72/KR2/ SO21
P71/KR1/ SI21/SDA21
P06/(INTP11)/ (TRJIO0)
P11/SI11/ SDA11/ TRDIOC1
P25/ANI5
P27/ANI7 2
P50/INTP1/ SI00/RxD0/ TOOLRxD/ SDA00/ TRGIOA/ (TRJO0)
P51/INTP2/ SO00/TxD0/ TOOLTxD/ TRGIOB
P55/ (PCLBUZ1)/ (SCK00)/ (INTP4)
P13/TxD2/ SO20/ TRDIOA1/ IVCMP1 Note
P10/SCK11/ SCL11/ TRDIOD1
P146
P147/ANI18/ VCOUT1 Note 1
1
A
B
C
D
E
F
G
H
Note
Mounted on the 96 KB or more code flash memory products.
Caution 1. Make EVSS0 pin the same potential as VSS pin. Caution 2. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). (Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 15 of 97
RL78/G14
1. OUTLINE
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD a nd EVDD0 p ins and connect the V SS a nd EV SS0 p ins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 16 of 97
RL78/G14
1. OUTLINE
1.3.9
80-pin products
• 80-pin plastic LQFP (14 × 14) • 80-pin plastic LQFP (fine pitch) (12 × 12)
P153/ANI11 P100/ANI20/(INTP10) P147/ANI18/VCOUT1 P146 P111 P110/(INTP11) P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00)/(INTP4) P54/SCK31/SCL31/(INTP3) P53/SI31/SDA31/(INTP2) P52/SO31/(INTP1) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 P22/ANI2/ANO0 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P142/SCK30/SCL30 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P05 P06/(TRJIO0) P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63/SDAA1 P62/SSI00/SCLA1 P61/SDAA0 P60/SCLA0
Caution
Make EVSS0 pin the same potential as VSS pin.
Caution 1. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Caution 2. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD a nd EVDD0 p ins and connect the V SS a nd EV SS0 p ins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/VCOUT0 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01/(INTP9) P42/(INTP8) P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0
Page 17 of 97
RL78/G14
1. OUTLINE
1.3.10
100-pin products
• 100-pin plastic LQFP (fine pitch) (14 × 14)
P100/ANI20/(INTP10) P147/ANI18/VCOUT1 P146/(INTP4) P111 P110/(INTP11) P101 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO00/TxD0/TOOLTxD/TRGIOB P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) EVDD1 76 77 78 79 80 81
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P156/ANI14 P155/ANI13 P154/ANI12 P153/ANI11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 P22/ANI2/ANO0 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P102 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P145 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TXD1) P81/(SI10)/(RXD1)/(SDA10) P80/(SCK10)/(SCL10) EVSS1 P05 P06/(TRJIO0) P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63/SDAA1 P62/SSI00/SCLA1
82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Caution
Make EVSS0, EVSS1 pins the same potential as VSS pin. Make EVDD1 pin the same potential as EVDD0 pin.
Caution 1. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Caution 2. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/VCOUT0 P47/INTP2 P46/INTP1 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42 P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P87/(INTP9)
Page 18 of 97
RL78/G14
• 100-pin plastic LQFP (fine pitch) (14 × 20)
1. OUTLINE
P120/ANI19/VCOUT0 P47/INTP2 P46/INTP1 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42 P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK30/SCL30 P143/SI30/RxD3/SDA30 P144/SO30/TxD3 P145 P00/TI00/TRGCLKA/(TRJO0) P01/TO00/TRGCLKB/TRJIO0 P02/ANI17/SO10/TxD1 P03/ANI16/SI10/RxD1/SDA10 P04/SCK10/SCL10 P102 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 P23/ANI3/ANO1 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P150/ANI8 P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 P100/ANI20/(INTP10) P147/ANI18/VCOUT1
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
P146/(INTP4) P111 P110/(INTP11) P101 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO00/TxD0/TOOLTxD/TRGIOB P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
Caution
Make EVSS0, EVSS1 pins the same potential as VSS pin. Make EVDD1 pin the same potential as EVDD0 pin
Caution 1. Make VDD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Caution 2. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1).
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
P60/SCLA0 P61/SDAA0 P62/SSI00/SCLA1 P63/SDAA1 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P64/TI10/TO10 P65/TI11/TO11 P66/TI12/TO12 P67/TI13/TO13 P77/KR7/INTP11/(TXD2) P76/KR6/INTP10/(RXD2) P75/KR5/INTP9 P74/KR4/INTP8 P73/KR3 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P06/(TRJIO0) P05 EVSS1 P80/(SCK10)/(SCL10) P81/(SI10)/(RXD1)/(SDA10) P82/(SO10)/(TXD1) P83 P84/(INTP7) P85/(INTP7) P86/(INTP8) P87/(INTP9) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 EVDD1
Page 19 of 97
RL78/G14
1. OUTLINE
1.4
Pin Identification
Analog input RxD0 to RxD3: Receive data
ANI0 to ANI14,: ANI16 to ANI20 ANO0, ANO1: AVREFM:
SCK00, SCK01, SCK10,: Serial clock input/output Analog output A/D converter reference potential ( side) input SCK11, SCK20, SCK21, SCK30, SCK31 SCLA0, SCLA1, SCL00,: Serial clock input/output SCL01, SCL10, SCL11, SCL20, SCL21, SCL30, SCL31 SDAA0, SDAA1, SDA00,: Serial data input/output SDA01, SDA10, SDA11, SDA20, SDA21, SDA30, SDA31 SI00, SI01, SI10, SI11,: SI20, SI21, SI30, SI31 SO00, SO01, SO10,: SO11, SO20, SO21, SO30, SO31 SSI00: TI00 to TI03,: TI10 to TI13 TO00 to TO03,: TO10 to TO13, TRJO0 TOOL0: TOOLRxD, TOOLTxD: TRDCLK0, TRGCLKA,: TRGCLKB TRDIOA0, TRDIOB0,: TRDIOC0, TRDIOD0, TRDIOA1, TRDIOB1, TRDIOC1, TRDIOD1, TRGIOA, TRGIOB, TRJIO0 TxD0 to TxD3: VCOUT0, VCOUT1: VDD: VSS: X1, X2: XT1, XT2: Transmit data Comparator output Power supply Ground Crystal oscillator (main system clock) Crystal oscillator (subsystem clock) Timer input/output Data input/output for tool Data input/output for external device Timer external input clock Timer output Serial interface chip select input Timer input Serial data output Serial data input
AVREFP:
A/D converter reference potential (+ side) input
EVDD0, EVDD1: EVSS0, EVSS1: EXCLK:
Power supply for port Ground for port External clock input (main system clock)
EXCLKS:
External clock input (sub system clock)
INTP0 to INTP11: IVCMP0, IVCMP1: IVREF0, IVREF1: KR0 to KR7: P00 to P06: P10 to P17: P20 to P27: P30, P31: P40 to P47: P50 to P57: P60 to P67: P70 to P77: P80 to P87: P100 to P102: P110, P111: P120 to P124: P130, P137: P140 to P147: P150 to P156: PCLBUZ0, PCLBUZ1:
External interrupt input Comparator input Comparator reference input Key return Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Programmable clock output/buzzer output
REGC: RESET: RTC1HZ:
Regulator capacitance Reset Real-time clock correction clock (1 Hz) output
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 20 of 97
RL78/G14
1. OUTLINE
1.5 1.5.1
Block Diagram 30-pin products
TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch2 PORT 3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 2 P50, P51 P40 2 P30, P31 PORT 0 2 P00, P01
PORT 1
8
P10 to P17
PORT 2
4
P20 to P23
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR PORT 12
2
P60, P61
INTERVAL TIMER
2
P120 P121, P122
PORT 13
P137 P147 ANI0/P20 to ANI3/P23 ANI16/P01, ANI17/P00 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21
PORT 14
4 4
RxD0/P50 TxD0/P51
UART0 LINSEL
DATA FLASH MEMORY
RxD1/P01 TxD1/P00 SCK00/P30 SI00/P50 SO00/P51 SSI00/P31 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL11/P10 SDA11/P11
UART1
CSI00
POWER ON RESET/ VOLTAGE DETECTOR
POR/LVD CONTROL
CSI11
RAM RESET CONTROL
IIC00 ON-CHIP DEBUG IIC11 VDD SERIAL ARRAY UNIT1 (2ch) VSS TOOLRxD/P50, TOOLTxD/P51 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR TOOL0/P40 RESET X1/P121 X2/EXCLK/P122
RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCL20/P15 SDA20/P14
UART2 SERIAL INTERFACE IICA0 CSI20 BUZZER OUTPUT IIC20 CLOCK OUTPUT CONTROL 2
SDAA0/P61 SCLA0/P60 VOLTAGE REGULATOR REGC
PCLBUZ0/P31, PCLBUZ1/P15 2
RxD0/P50 (LINSEL) INTP0/P137 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16
DATA TRANSFER CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT
INTERRUPT CONTROL
2
D/A CONVERTERNote COMPARATORNote (2ch)
COMPARATOR0
ANO0/P22
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
Note
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 21 of 97
RL78/G14
1. OUTLINE
1.5.2
32-pin products
TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch2 PORT 3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 2 P50, P51 P40 2 P30, P31 PORT 0 2 P00, P01
PORT 1
8
P10 to P17
PORT 2
4
P20 to P23
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR PORT 7
3
P60 to P62
P70 P120 P121, P122
INTERVAL TIMER
PORT 12
2
PORT 13
P137 P147 ANI0/P20 to ANI3/P23 ANI16/P01, ANI17/P00 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21
PORT 14
4 4
RxD0/P50 TxD0/P51
UART0 LINSEL
DATA FLASH MEMORY
RxD1/P01 TxD1/P00 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL11/P10 SDA11/P11
UART1
CSI00
POWER ON RESET/ VOLTAGE DETECTOR
POR/LVD CONTROL
CSI11
RAM RESET CONTROL
IIC00 ON-CHIP DEBUG IIC11 VDD SERIAL ARRAY UNIT1 (2ch) VSS TOOLRxD/P50, TOOLTxD/P51 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR TOOL0/P40 RESET X1/P121 X2/EXCLK/P122
RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCL20/P15 SDA20/P14
UART2 SERIAL INTERFACE IICA0 CSI20 BUZZER OUTPUT IIC20 2 CLOCK OUTPUT CONTROL DATA TRANSFER CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT
SDAA0/P61 SCLA0/P60 VOLTAGE REGULATOR REGC
PCLBUZ0/P31, PCLBUZ1/P15 2 INTERRUPT CONTROL 2
RxD0/P50 (LINSEL) INTP0/P137 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16
D/A CONVERTERNote COMPARATORNote (2ch)
COMPARATOR0
ANO0/P22 ANO1/P23
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
Note
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 22 of 97
RL78/G14
1. OUTLINE
1.5.3
36-pin products
TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch2 PORT 3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 2 P50, P51 P40 2 P30, P31 PORT 0 2 P00, P01
PORT 1
8
P10 to P17
PORT 2
6
P20 to P25
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR PORT 7
3
P60 to P62
3
P70 to P72 P120 P121, P122
INTERVAL TIMER
PORT 12
2
PORT 13
P137 P147 ANI0/P20 to ANI5/P25 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21
PORT 14
6 2
RxD0/P50 TxD0/P51
UART0 LINSEL
DATA FLASH MEMORY
RxD1/P01 TxD1/P00 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL11/P10 SDA11/P11
UART1
CSI00
POWER ON RESET/ VOLTAGE DETECTOR
POR/LVD CONTROL
CSI11
RAM RESET CONTROL
IIC00 ON-CHIP DEBUG IIC11 VDD SERIAL ARRAY UNIT1 (2ch) VSS TOOLRxD/P50, TOOLTxD/P51 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR TOOL0/P40 RESET X1/P121 X2/EXCLK/P122
RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71
UART2 SERIAL INTERFACE IICA0 CSI20 BUZZER OUTPUT 2 CSI21 CLOCK OUTPUT CONTROL DATA TRANSFER CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT
SDAA0/P61 SCLA0/P60 VOLTAGE REGULATOR REGC
PCLBUZ0/P31, PCLBUZ1/P15 2
RxD0/P50 (LINSEL) INTP0/P137 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16
IIC20
INTERRUPT CONTROL
2
IIC21
D/A CONVERTERNote COMPARATORNote (2ch)
COMPARATOR0
ANO0/P22 ANO1/P23
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
Note
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 23 of 97
RL78/G14
1. OUTLINE
1.5.4
40-pin products
TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch2 PORT 3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 2 P50, P51 P40 2 P30, P31 PORT 0 2 P00, P01
PORT 1
8
P10 to P17
PORT 2
7
P20 to P26
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR KEY RETURN DATA FLASH MEMORY PORT 7
3
P60 to P62
4
P70 to P73 P120 P121 to P124
INTERVAL TIMER
PORT 12
4
PORT 13
P137 P147 ANI0/P20 to ANI6/P26 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 4 KR0/P70 to KR3/P73
PORT 14
RTC1HZ/P30
7 2
RxD0/P50 TxD0/P51
UART0 LINSEL
RxD1/P01 TxD1/P00 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL11/P10 SDA11/P11
UART1
CSI00
POWER ON RESET/ VOLTAGE DETECTOR
POR/LVD CONTROL
CSI11
RAM RESET CONTROL
IIC00 ON-CHIP DEBUG IIC11 VDD SERIAL ARRAY UNIT1 (2ch) VSS TOOLRxD/P50, TOOLTxD/P51 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 TOOL0/P40
RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71
UART2 SERIAL INTERFACE IICA0 CSI20 BUZZER OUTPUT 2 CSI21 CLOCK OUTPUT CONTROL DATA TRANSFER CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT
SDAA0/P61 SCLA0/P60 VOLTAGE REGULATOR REGC
PCLBUZ0/P31, PCLBUZ1/P15 2
RxD0/P50 (LINSEL) INTP0/P137 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16
IIC20
INTERRUPT CONTROL
2
IIC21
D/A CONVERTERNote COMPARATORNote (2ch)
COMPARATOR0
ANO0/P22 ANO1/P23
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
Note
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 24 of 97
RL78/G14
1. OUTLINE
1.5.5
44-pin products
TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch2 PORT 3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 2 P50, P51 2 P40, P41 2 P30, P31 PORT 0 2 P00, P01
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR KEY RETURN DATA FLASH MEMORY PORT 7
4
P60 to P63
4
P70 to P73 P120 P121 to P124
INTERVAL TIMER
PORT 12
4
PORT 13
P137 2 P146, P147 ANI0/P20 to ANI7/P27 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 4 KR0/P70 to KR3/P73
PORT 14
RTC1HZ/P30
8 2
RxD0/P50 TxD0/P51
UART0 LINSEL
RxD1/P01 TxD1/P00 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL11/P10 SDA11/P11
UART1
CSI00
POWER ON RESET/ VOLTAGE DETECTOR
POR/LVD CONTROL
CSI11
RAM RESET CONTROL
IIC00 ON-CHIP DEBUG IIC11 VDD SERIAL ARRAY UNIT1 (2ch) VSS TOOLRxD/P50, TOOLTxD/P51 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 TOOL0/P40
RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71
UART2 SERIAL INTERFACE IICA0 CSI20 BUZZER OUTPUT 2 CSI21 CLOCK OUTPUT CONTROL DATA TRANSFER CONTROL EVENT LINK CONTROLLER BCD ADJUSTMENT
SDAA0/P61 SCLA0/P60 VOLTAGE REGULATOR REGC
PCLBUZ0/P31, PCLBUZ1/P15 2
RxD0/P50 (LINSEL) INTP0/P137 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16
IIC20
INTERRUPT CONTROL
2
IIC21
D/A CONVERTERNote COMPARATORNote (2ch)
COMPARATOR0
ANO0/P22 ANO1/P23
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
Note
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 25 of 97
RL78/G14
1. OUTLINE
1.5.6
48-pin products
TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch2 PORT 3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 2 P50, P51 2 P40, P41 2 P30, P31 PORT 0 2 P00, P01
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR KEY RETURN DATA FLASH MEMORY PORT 7
4
P60 to P63
6
P70 to P75 P120 P121 to P124 P130 P137
INTERVAL TIMER
PORT 12
4
PORT 13
PORT 14
3
P140, P146, P147 ANI0/P20 to ANI7/P27 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21
RTC1HZ/P30
8 2
RxD0/P50 TxD0/P51
UART0 LINSEL
6
KR0/P70 to KR5/P75
RxD1/P01 TxD1/P00 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK01/P75 SI01/P74 SO01/P73 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL01/P75 SDA01/P74 SCL11/P10 SDA11/P11
UART1
CSI00
POWER ON RESET/ VOLTAGE DETECTOR
POR/LVD CONTROL
CSI01
RAM RESET CONTROL
CSI11
ON-CHIP DEBUG SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR
TOOL0/P40
IIC00 VDD IIC01 IIC11 SERIAL INTERFACE IICA0 SERIAL ARRAY UNIT1 (2ch) VSS TOOLRxD/P50, TOOLTxD/P51
RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124
SDAA0/P61 SCLA0/P60 VOLTAGE REGULATOR REGC RxD0/P50 (LINSEL) INTP0/P137 2 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 INTP6/P140 2 INTP8/P74, INTP9/P75 ANO0/P22 ANO1/P23
RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71
BUZZER OUTPUT 2 CLOCK OUTPUT CONTROL PCLBUZ0/P140, PCLBUZ1/P15
UART2
CSI20 DATA TRANSFER CONTROL CSI21 EVENT LINK CONTROLLER BCD ADJUSTMENT
IIC20
D/A CONVERTERNote COMPARATORNote (2ch)
COMPARATOR0
IIC21
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
Note
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 26 of 97
RL78/G14
1. OUTLINE
1.5.7
52-pin products
TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch2 PORT 3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 2 P50, P51 2 P40, P41 2 P30, P31 PORT 0 4 P00 to P03
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR KEY RETURN DATA FLASH MEMORY PORT 7
4
P60 to P63
8
P70 to P77 P120 P121 to P124 P130 P137
INTERVAL TIMER
PORT 12
4
PORT 13
PORT 14
3
P140, P146, P147 ANI0/P20 to ANI7/P27 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21
RTC1HZ/P30
8 4
RxD0/P50 TxD0/P51
UART0 LINSEL
8
KR0/P70 to KR7/P77
RxD1/P03 TxD1/P02 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK01/P75 SI01/P74 SO01/P73 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL01/P75 SDA01/P74 SCL11/P10 SDA11/P11
UART1
CSI00
POWER ON RESET/ VOLTAGE DETECTOR
POR/LVD CONTROL
CSI01
RAM RESET CONTROL
CSI11
ON-CHIP DEBUG SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR
TOOL0/P40
IIC00 VDD IIC01 IIC11 SERIAL INTERFACE IICA0 SERIAL ARRAY UNIT1 (2ch) VSS TOOLRxD/P50, TOOLTxD/P51
RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124
SDAA0/P61 SCLA0/P60 VOLTAGE REGULATOR REGC RxD0/P50 (LINSEL) INTP0/P137 2 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 INTP6/P140 4 INTP8/P74 to INTP11/P77 ANO0/P22 ANO1/P23
RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71
BUZZER OUTPUT 2 CLOCK OUTPUT CONTROL PCLBUZ0/P140, PCLBUZ1/P15
UART2
CSI20 DATA TRANSFER CONTROL CSI21 EVENT LINK CONTROLLER BCD ADJUSTMENT
IIC20
D/A CONVERTERNote COMPARATORNote (2ch)
COMPARATOR0
IIC21
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
Note
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 27 of 97
RL78/G14
1. OUTLINE
1.5.8
64-pin products
TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch2 PORT 3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 6 P50 to P55 4 P40 to P43 2 P30, P31 PORT 0 7 P00 to P06
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR KEY RETURN DATA FLASH MEMORY PORT 7
4
P60 to P63
8
P70 to P77 P120 P121 to P124 P130 P137
INTERVAL TIMER
PORT 12
4
PORT 13
PORT 14
4
P140, P141, P146, P147 ANI0/P20 to ANI7/P27 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21
RTC1HZ/P30
8 4
RxD0/P50 TxD0/P51
UART0 LINSEL
8
KR0/P70 to KR7/P77
RxD1/P03 TxD1/P02 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK01/P75 SI01/P74 SO01/P73 SCK10/P04 SI10/P03 SO10/P02 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL01/P75 SDA01/P74 SCL10/P04 SDA10/P03 SCL11/P10 SDA11/P11
UART1
CSI00
POWER ON RESET/ VOLTAGE DETECTOR
POR/LVD CONTROL
CSI01
RAM RESET CONTROL
CSI10 ON-CHIP DEBUG CSI11 VDD, VSS, TOOLRxD/P50, EVDD0 EVSS0 TOOLTxD/P51 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR TOOL0/P40
IIC00 IIC01 IIC10 IIC11
RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124
SERIAL INTERFACE IICA0
SDAA0/P61 SCLA0/P60
VOLTAGE REGULATOR
REGC RxD0/P50 (LINSEL) INTP0/P137
BUZZER OUTPUT SERIAL ARRAY UNIT1 (2ch) RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 UART2 DATA TRANSFER CONTROL CSI20 EVENT LINK CONTROLLER CSI21 BCD ADJUSTMENT IIC20 D/A CONVERTERNote COMPARATORNote (2ch)
COMPARATOR0
2 CLOCK OUTPUT CONTROL
PCLBUZ0/P140, PCLBUZ1/P141 INTERRUPT CONTROL
2 2
INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16
2 4
INTP6/P140, INTP7/P141 INTP8/P74 to INTP11/P77 ANO0/P22 ANO1/P23
IIC21
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
Note
Mounted on the 96 KB or more code flash memory products.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 28 of 97
RL78/G14
1. OUTLINE
1.5.9
80-pin products
TIMER ARRAY UNIT0 (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch1 ch2 ch2 PORT 3 ch3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 6 P50 to P55 6 P40 to P45 TI13/TO13/P67 2 P30, P31 TI12/TO12/P66 TI11/TO11/P65 PORT 2 8 P20 to P27 TIMER ARRAY UNIT1 (4ch) ch0 TI10/TO10/P64 PORT 1 8 P10 to P17 PORT 0 7 P00 to P06
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) A/D CONVERTER PORT 7
8
P60 to P67
8
P70 to P77
INTERVAL TIMER 8 4 5 ANI0/P20 to ANI7/P27 ANI8/P150 to ANI11/P153 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 AVREFP/P20 AVREFM/P21 RL78 CPU CORE MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR CODE FLASH MEMORY
PORT 10
P100
PORT 11
2
P110, P111 P120 P121 to P124 P130 P137
PORT 12
4
RTC1HZ/P30
PORT 13
PORT 14
7
P140 to P144, P146, P147 P150 to P153 KR0/P70 to KR7/P77 POR/LVD CONTROL
RxD0/P50 TxD0/P51
UART0 LINSEL
PORT 15
4
RxD1/P03 TxD1/P02 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK01/P43 SI01/P44 SO01/P45 SCK10/P04 SI10/P03 SO10/P02 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL01/P43 SDA01/P44 SCL10/P04 SDA10/P03 SCL11/P10 SDA11/P11
DATA FLASH MEMORY
KEY RETURN POWER ON RESET/ VOLTAGE DETECTOR
8
UART1
CSI00
CSI01
RESET CONTROL RAM ON-CHIP DEBUG TOOL0/P40
CSI10 SYSTEM CONTROL CSI11 VDD, VSS, TOOLRxD/P50, EVDD0 EVSS0 TOOLTxD/P51 HIGH-SPEED ON-CHIP OSCILLATOR RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124
IIC00 IIC01 IIC10 IIC11
VOLTAGE REGULATOR SERIAL INTERFACE IICA0 SDAA0/P61 SCLA0/P60 2
REGC RxD0/P50 (LINSEL) INTP0/P137 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16
SERIAL ARRAY UNIT1 (4ch) RxD2/P14 TxD2/P13 RxD3/P143 TxD3/P144 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCK30/P142 SI30/P143 SO30/P144 SCK31/P54 SI31/P53 SO31/P52 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SCL30/P142 SDA30/P143 SCL31/P54 SDA31/P53 UART2
SERIAL INTERFACE IICA1
SDAA1/P63 SCLA1/P62 INTERRUPT CONTROL
2
BUZZER OUTPUT UART3 2 CLOCK OUTPUT CONTROL DATA TRANSFER CONTROL CSI21 EVENT LINK CONTROLLER CSI30 BCD ADJUSTMENT
COMPARATOR1
2 PCLBUZ0/P140, PCLBUZ1/P141 4
INTP6/P140, INTP7/P141 INTP8/P74 to INTP11/P77 ANO0/P22 ANO1/P23
CSI20
D/A CONVERTER COMPARATOR (2ch)
COMPARATOR0
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
CSI31
IIC20 IIC21 IIC30 IIC31
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 29 of 97
RL78/G14
1. OUTLINE
1.5.10
100-pin products
TIMER ARRAY UNIT0 (4ch) TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 RxD0/P50 (LINSEL) ch0 ch1 ch1 ch2 ch2 PORT 3 ch3 ch3 PORT 4 2 TIMER RD (2ch) TIMER RG 2 3 4 ch0 ch1 TRGIOA/P50, TRGIOB/P51 TRGCLKA/P00, TRGCLKB/P01 PORT 5 8 P50 to P57 8 P40 to P47 TI13/TO13/P67 2 P30, P31 TI12/TO12/P66 TI11/TO11/P65 PORT 2 8 P20 to P27 TIMER ARRAY UNIT1 (4ch) ch0 TI10/TO10/P64 PORT 1 8 P10 to P17 PORT 0 7 P00 to P06
TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 TRDIOA1/P13 toTRDIOD1/P10
PORT 6 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) A/D CONVERTER PORT 7
8
P60 to P67
8
P70 to P77
INTERVAL TIMER 8 7 5 ANI0/P20 to ANI7/P27 ANI8/P150 to ANI14/P156 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 AVREFP/P20 AVREFM/P21 RL78 CPU CORE MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR CODE FLASH MEMORY
PORT 8
8
P80 to P87
PORT 10
3
P100 to P102
PORT 11
2
P110, P111 P120 P121 to P124 P130 P137
RTC1HZ/P30
PORT 12
4
PORT 13
RxD0/P50 TxD0/P51
UART0 LINSEL
PORT 14
8
P140 to P147
RxD1/P03 TxD1/P02 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 SCK01/P43 SI01/P44 SO01/P45 SCK10/P04 SI10/P03 SO10/P02 SCK11/P10 SI11/P11 SO11/P12 SCL00/P30 SDA00/P50 SCL01/P43 SDA01/P44 SCL10/P04 SDA10/P03 SCL11/P10 SDA11/P11
DATA FLASH MEMORY
PORT 15
7
P150 to P156 KR0/P70 to KR7/P77 POR/LVD CONTROL
UART1 KEY RETURN CSI00 POWER ON RESET/ VOLTAGE DETECTOR RAM RESET CONTROL CSI10 ON-CHIP DEBUG CSI11 VDD, VSS, TOOLRxD/P50, EVDD0, EVSS0, TOOLTxD/P51 EVDD1 EVSS1 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 TOOL0/P40 8
CSI01
IIC00 IIC01 IIC10 IIC11
SERIAL INTERFACE IICA0
SDAA0/P61 SCLA0/P60
VOLTAGE REGULATOR
REGC RxD0/P50 (LINSEL) INTP0/P137 2 INTP1/P47, INTP2/P46 INTP3/P30, INTP4/P31 INTP5/P16 2 4 INTP6/P140, INTP7/P141 INTP8/P74 to INTP11/P77 ANO0/P22 ANO1/P23
SERIAL ARRAY UNIT1 (4ch) RxD2/P14 TxD2/P13 RxD3/P143 TxD3/P144 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCK30/P142 SI30/P143 SO30/P144 SCK31/P54 SI31/P53 SO31/P52 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SCL30/P142 SDA30/P143 SCL31/P54 SDA31/P53 UART2
SERIAL INTERFACE IICA1
SDAA1/P63 SCLA1/P62 INTERRUPT CONTROL
2
BUZZER OUTPUT UART3 2 CLOCK OUTPUT CONTROL DATA TRANSFER CONTROL CSI21 EVENT LINK CONTROLLER CSI30 BCD ADJUSTMENT CSI31 PCLBUZ0/P140, PCLBUZ1/P141
CSI20
D/A CONVERTER COMPARATOR (2ch)
COMPARATOR0
VCOUT0/P120 IVCMP0/P17 IVREF0/P16 VCOUT1/P147 IVCMP1/P13 IVREF1/P12
COMPARATOR1
IIC20 IIC21 IIC30 IIC31
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 30 of 97
RL78/G14
1. OUTLINE
1.6
Outline of Functions
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2)
30-pin Item R5F104Ax (x = A, C to E) 16 to 64 4 2.5 to 5.5 Note 1 MB High-speed system clock High-speed on-chip oscillator clock (fIH) X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) 32-pin R5F104Bx (x = A, C to E) 16 to 64 4 2.5 to 5.5 Note 36-pin R5F104Cx (x = A, C to E) 16 to 64 4 2.5 to 5.5 Note 40-pin R5F104Ex (x = A, C to E) 16 to 64 4 2.5 to 5.5 Note
[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 16 KB to 64 KB)] Caution
Code flash memory (KB) Data flash memory (KB) RAM (KB) Memory space Main system clock
Subsystem clock
—
XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock General-purpose register Minimum instruction execution time
15 kHz (TYP.): VDD = 1.6 to 5.5 V 8 bits × 32 registers (8 bits × 8 registers × 4 banks) 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) — 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
• • • • • Total CMOS I/O CMOS input CMOS output N-ch open-drain I/O (6 V tolerance)
Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) Multiplication and Accumulation (16 bits × 16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. 26 21 3 — 2 28 22 3 — 3 32 26 3 — 3 36 28 5 — 3
I/O port
Timer
16-bit timer
8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer Real-time clock (RTC) 12-bit interval timer Timer output
1 channel 1 channel 1 channel 16 (TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
—
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
Note
In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 31 of 97
RL78/G14
1. OUTLINE
(2/2)
30-pin Item R5F104Ax (x = A, C to E) 2 [30-pin, 32-pin, 36-pin products] • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) [40-pin products] • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 32-pin R5F104Bx (x = A, C to E) 2 36-pin R5F104Cx (x = A, C to E) 2 40-pin R5F104Ex (x = A, C to E) 2
Clock output/buzzer output
8/10-bit resolution A/D converter Serial interface
8 channels [30-pin, 32-pin products]
8 channels
8 channels
9 channels
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [36-pin, 40-pin products] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 1 channel 28 sources Event input: 20 Event trigger output: 7 Vectored interrupt sources Key interrupt Reset • • • • Internal External 1 channel 1 channel 1 channel 29 sources
Data transfer controller (DTC) Event link controller (ELC)
24 6 —
Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector
24 6 —
24 6 —
24 7 4
• Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V • Power-down-reset: 1.50 ±0.03 V 1.63 V to 4.06 V (14 stages) Provided VDD = 1.6 to 5.5 V TA = 40 to +85 °C
Voltage detector On-chip debug function Power supply voltage Operating ambient temperature
Note
The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 32 of 97
RL78/G14
[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 96 KB to 256 KB)] Caution
1. OUTLINE
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2)
30-pin Item R5F104Ax (x = F, G) 96 to 128 8 12 to 16 1 MB High-speed system clock High-speed on-chip oscillator clock (fIH) X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) 32-pin R5F104Bx (x = F, G) 96 to 128 8 12 to 16 36-pin R5F104Cx (x = F, G) 96 to 128 8 12 to 16 40-pin R5F104Ex (x = F to H) 96 to 192 8 12 to 20
Code flash memory (KB) Data flash memory (KB) RAM (KB) Memory space Main system clock
Subsystem clock
—
XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock General-purpose register Minimum instruction execution time
15 kHz (TYP.): VDD = 1.6 to 5.5 V 8 bits × 32 registers (8 bits × 8 registers × 4 banks) 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) — 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
• • • • • Total CMOS I/O CMOS input CMOS output N-ch open-drain I/O (6 V tolerance)
Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) Multiplication and Accumulation (16 bits × 16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. 26 21 3 — 2 28 22 3 — 3 32 26 3 — 3 36 28 5 — 3
I/O port
Timer
16-bit timer
8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer Real-time clock (RTC) 12-bit interval timer Timer output
1 channel 1 channel 1 channel 16 (TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1)
RTC output
—
1 • 1 Hz (subsystem clock: fSUB = 32.768 kHz)
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 33 of 97
RL78/G14
1. OUTLINE
(2/2)
30-pin Item R5F104Ax (x = F, G) 32-pin R5F104Bx (x = F, G) 36-pin R5F104Cx (x = F, G) 40-pin R5F104Ex (x = F to H)
Clock output/buzzer output
2
[30-pin, 32-pin, 36-pin products]
2
2
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) [40-pin products] • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter D/A converter Comparator Serial interface 8 channels 1 channel 2 channels [30-pin, 32-pin products] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [36-pin, 40-pin products] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus Data transfer controller (DTC) Event link controller (ELC) 1 channel 28 sources Event input: 20 Event trigger output: 7 Vectored interrupt sources Key interrupt Reset • • • • Internal External 1 channel 1 channel 1 channel 29 sources 8 channels 2 channels 8 channels 9 channels
24 6 —
Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector
24 6 —
24 6 —
24 7 4
• Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V • Power-down-reset: 1.50 ±0.03 V 1.63 V to 4.06 V (14 stages) Provided VDD = 1.6 to 5.5 V TA = 40 to +85 °C
Voltage detector On-chip debug function Power supply voltage Operating ambient temperature
Note
The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 34 of 97
RL78/G14
[44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 16 KB to 64 KB)] Caution
1. OUTLINE
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2)
44-pin Item R5F104Fx (x = A, C to E) 16 to 64 4 2.5 to 5.5 1 MB High-speed system clock High-speed on-chip oscillator clock (fIH) X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V 15 kHz (TYP.): VDD = 1.6 to 5.5 V 8 bits × 32 registers (8 bits × 8 registers × 4 banks) 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Note
48-pin R5F104Gx (x = A, C to E) 16 to 64 4 2.5 to 5.5
Note
52-pin R5F104Jx (x = C to E) 32 to 64 4 4 to 5.5
Note
64-pin R5F104Lx (x = C to E) 32 to 64 4 4 to 5.5 Note
Code flash memory (KB) Data flash memory (KB) RAM (KB) Memory space Main system clock
Subsystem clock Low-speed on-chip oscillator clock General-purpose register Minimum instruction execution time
Instruction set
• Data transfer (8/16 bits) • Adder and subtractor/logical operation (8/16 bits) • Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) • Multiplication and Accumulation (16 bits × 16 bits + 32 bits) • Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port
Total CMOS I/O CMOS input CMOS output N-ch open-drain I/O (6 V tolerance)
40 31 5 — 4 8 channels
44 34 5 1 4
48 38 5 1 4
58 48 5 1 4
Timer
16-bit timer Watchdog timer Real-time clock (RTC) 12-bit interval timer Timer output
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) 1 channel 1 channel 1 channel 16 (TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1) RTC output 1 • 1 Hz (subsystem clock: fSUB = 32.768 kHz) Note In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
Page 35 of 97
RL78/G14
1. OUTLINE
(2/2)
44-pin Item R5F104Fx (x = A, C to E) 2 48-pin R5F104Gx (x = A, C to E) 2 52-pin R5F104Jx (x = C to E) 2 64-pin R5F104Lx (x = C to E) 2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter Serial interface 10 channels [44-pin products] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [48-pin, 52-pin products] • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [64-pin products] • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus Data transfer controller (DTC) Event link controller (ELC) Vectored interrupt sources Key interrupt Reset Internal External 1 channel 29 sources Event input: 20 Event trigger output: 7 24 7 4 • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit Voltage detector On-chip debug function Power supply voltage Operating ambient temperature Note • Power-on-reset: • Power-down-reset: 1.51 ±0.03 V 1.50 ±0.03 V 24 10 6 24 12 8 24 13 8 1 channel 30 sources 1 channel 1 channel 31 sources 10 channels 12 channels 12 channels
1.63 V to 4.06 V (14 stages) Provided VDD = 1.6 to 5.5 V TA = 40 to +85 °C
The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator.
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RL78/G14
[44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 96 KB to 256 KB)] Caution
1. OUTLINE
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2)
44-pin Item R5F104Fx (x = F to H, J) 96 to 256 8 12 to 24 1 MB High-speed system clock High-speed on-chip oscillator clock (fIH) X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V 15 kHz (TYP.): VDD = 1.6 to 5.5 V 8 bits × 32 registers (8 bits × 8 registers × 4 banks) 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Note
48-pin R5F104Gx (x = F to H, J) 96 to 256 8 12 to 24
Note
52-pin R5F104Jx (x = F to H, J) 96 to 256 8 12 to 24
Note
64-pin R5F104Lx (x = F to H, J) 96 to 256 8 12 to 24 Note
Code flash memory (KB) Data flash memory (KB) RAM (KB) Memory space Main system clock
Subsystem clock Low-speed on-chip oscillator clock General-purpose register Minimum instruction execution time
Instruction set
• Data transfer (8/16 bits) • Adder and subtractor/logical operation (8/16 bits) • Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) • Multiplication and Accumulation (16 bits × 16 bits + 32 bits) • Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port
Total CMOS I/O CMOS input CMOS output N-ch open-drain I/O (6 V tolerance)
40 31 5 — 4 8 channels
44 34 5 1 4
48 38 5 1 4
58 48 5 1 4
Timer
16-bit timer Watchdog timer Real-time clock (RTC) 12-bit interval timer Timer output
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) 1 channel 1 channel 1 channel 16 (TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1) RTC output 1 • 1 Hz (subsystem clock: fSUB = 32.768 kHz) Note In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used.
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1. OUTLINE
(2/2)
44-pin Item R5F104Fx (x = F to H, J) 2 48-pin R5F104Gx (x = F to H, J) 2 52-pin R5F104Jx (x = F to H, J) 2 64-pin R5F104Lx (x = F to H, J) 2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter D/A converter Comparator Serial interface 10 channels 2 channels 2 channels [44-pin products] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [48-pin, 52-pin products] • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [64-pin products] • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus Data transfer controller (DTC) Event link controller (ELC) Vectored interrupt sources Key interrupt Reset Internal External 1 channel 29 sources Event input: 20 Event trigger output: 7 24 7 4 • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit Voltage detector On-chip debug function Power supply voltage Operating ambient temperature Note • Power-on-reset: • Power-down-reset: 1.51 ±0.03 V 1.50 ±0.03 V 24 10 6 24 12 8 24 13 8 1 channel 30 sources 1 channel 1 channel 31 sources 10 channels 12 channels 12 channels
1.63 V to 4.06 V (14 stages) Provided VDD = 1.6 to 5.5 V TA = 40 to +85 °C
The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator.
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RL78/G14
[80-pin, 100-pin products (code flash memory 96 KB to 256 KB)] Caution
1. OUTLINE
This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2)
80-pin Item R5F104Mx (x = F to H, J) 96 to 256 8 12 to 24 1 MB High-speed system clock High-speed on-chip oscillator clock (fIH) X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V 15 kHz (TYP.): VDD = 1.6 to 5.5 V 8 bits × 32 registers (8 bits × 8 registers × 4 banks) 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Note
100-pin R5F104Px (x = F to H, J) 96 to 256 8 12 to 24 Note
Code flash memory (KB) Data flash memory (KB) RAM (KB) Memory space Main system clock
Subsystem clock Low-speed on-chip oscillator clock General-purpose register Minimum instruction execution time
Instruction set
• Data transfer (8/16 bits) • Adder and subtractor/logical operation (8/16 bits) • Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) • Multiplication and Accumulation (16 bits × 16 bits + 32 bits) • Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port
Total CMOS I/O CMOS input CMOS output N-ch open-drain I/O (6 V tolerance)
74 64 5 1 4 12 channels
92 82 5 1 4
Timer
16-bit timer Watchdog timer Real-time clock (RTC) 12-bit interval timer Timer output
(TAU: 8 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) 1 channel 1 channel 1 channel 20 (TAU: 8, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 13 (TAU: 6, Timer RD: 6, Timer RG: 1) RTC output 1 • 1 Hz (subsystem clock: fSUB = 32.768 kHz) Note In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used.
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1. OUTLINE
(2/2)
80-pin Item R5F104Mx (x = F to H, J) 2 (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 100-pin R5F104Px (x = F to H, J) 2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
8/10-bit resolution A/D converter D/A converter Comparator Serial interface
17 channels 2 channels 2 channels [80-pin, 100-pin products]
20 channels 2 channels 2 channels
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus Data transfer controller (DTC) Event link controller (ELC) Vectored interrupt sources Key interrupt Reset Internal External 2 channels 39 sources Event input: 26 Event trigger output: 9 32 13 8 • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit Voltage detector On-chip debug function Power supply voltage Operating ambient temperature Note • Power-on-reset: • Power-down-reset: 1.51 ±0.03 V 1.50 ±0.03 V 32 13 8 2 channels 39 sources
1.63 V to 4.06 V (14 stages) Provided VDD = 1.6 to 5.5 V TA = 40 to +85 °C
The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator.
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2. ELECTRICAL SPECIFICATIONS
2. ELECTRICAL SPECIFICATIONS
Caution 1. The RL78/G14 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.1
Absolute Maximum Ratings
(1/2)
Conditions Ratings -0.5 to +6.5 -0.5 to +6.5 -0.5 to +0.3 EVSS0 = EVSS1 REGC -0.5 to +0.3 -0.3 to +2.8 and -0.3 to VDD +0.3 Note 1 Unit V V V V V
Absolute Maximum Ratings (TA = 25 C) (1/2)
Parameter Supply voltage Symbols VDD EVDD0, EVDD1 EVDD0 = EVDD1 VSS EVSS0, EVSS1 REGC pin input voltage VIREGC
Input voltage
VI1
P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147
-0.3 to EVDD0 +0.3 and -0.3 to VDD +0.3 Note 2
V
VI2 VI3 Output voltage VO1
P60 to P63 (N-ch open-drain) P20 to P27, P121 to P124, P137, P150 to P156, EXCLK, EXCLKS, RESET P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147
-0.3 to +6.5 -0.3 to VDD +0.3
Note 2
V V V
-0.3 to EVDD0 +0.3 Note 2
VO2 Analog input voltage VAI1 VAI2 Note 1. Note 2. Caution
P20 to P27, P150 to P156 ANI16 to ANI20 ANI0 to ANI14
-0.3 to VDD +0.3 -0.3 to EVDD0 +0.3 -0.3 to VDD +0.3
Note 2
V V V
Note 2
Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Must be 6.5 V or lower. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. (2/2)
Conditions Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 Total of all P00 to P04, P40 to P47, P102, P120, P130, pins -170 mA P140 to P145 P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 IOH2 Per pin Total of all pins P20 to P27, P150 to P156 -0.5 -2 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 Total of all P00 to P04, P40 to P47, P102, P120, P130, pins 170 mA P140 to P145 P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 IOL2 Per pin Total of all pins P20 to P27, P150 to P156 1 5 -40 to +85 mA mA C 100 mA 70 mA 40 mA mA mA -100 mA -70 mA Ratings -40 Unit mA
Absolute Maximum Ratings (TA = 25 C) (2/2)
Parameter Output current, high Symbols IOH1
Output current, low
IOL1
Per pin
Operating ambient temperature Storage temperature Caution
TA
In normal operation mode In flash memory programming mode
Tstg
-65 to +150
C
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.2 2.2.1
Oscillator Characteristics Main system clock oscillator characteristics
(TA = -40 to +85 °C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Resonator Ceramic resonator
VSS X1 X2 Rd C1 C2
Recommended Circuit (fX) Note
Parameter X1 clock oscillation frequency
Conditions 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 1.6 V VDD < 1.8 V
MIN. 1.0 1.0 1.0
TYP.
MAX. 20.0 8.0 4.0
Unit MHz
Crystal resonator
VSS X1 X2 Rd C1 C2
X1 clock oscillation frequency (fX) Note
2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 1.6 V VDD < 1.8 V
1.0 1.0 1.0
20.0 8.0 4.0
MHz
Note
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. Caution 2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.2.2
On-chip oscillator characteristics
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Oscillators High-speed on-chip oscillator clock frequency Note 1 High-speed on-chip oscillator clock frequency accuracy
Note 2
Parameters fIH -20 to +85 C
Conditions
MIN. 1
TYP.
MAX. 32
Unit MHz
1.8 V VDD 5.5 V 1.6 V VDD 1.8 V
-1 -5 -1.5 -5.5 15 -15
+1 +5 +1.5 +5.5
% % % % kHz
-40 to -20 C
1.8 V VDD < 5.5 V 1.6 V VDD 1.8 V
Low-speed on-chip oscillator clock frequency Low-speed on-chip oscillator clock frequency accuracy Note 1. Note 2.
fIL
+15
%
High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/010C2H) and bits 0 to 2 of the HOCODIV register. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. When SSOP (30-pin), WQFN (32-, 40-, 48-pin), FLGA (36-pin), LQFP (7 × 7) (48-pin), LQFP (10 × 10) (52-pin), LQFP (12 × 12) (64-, 80-pin), LQFP (14 × 14) (80-, 100-pin), LQFP (14 × 20) (100-pin) products, these specifications show target values, which may change after device evaluation.
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2. ELECTRICAL SPECIFICATIONS
2.2.3
Subsystem clock oscillator characteristics
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Resonator Crystal resonator
VSS XT2 Rd C4 C3 XT1
Recommended Circuit (fXT) Note
Items XT1 clock oscillation frequency
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
Note
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. Caution 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.3 2.3.1
DC Characteristics Pin characteristics
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Output current, high Note 1 Symbol IOH1 Per pin for P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 Total of P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 (When duty = 70% Note 3) 4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 (When duty = 70% Note 3) Total of all pins (When duty = 70% Note 3) IOH2 Per pin for P20 to P27, P150 to P156 Total of all pins (When duty = 70% Note 3) Note 1. Note 2. Note 3. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to an output pin. However, do not exceed the total current value. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70 % to n %). • Total output current of pins = (IOH × 0.7)/(n × 0.01) Where n = 50 % and IOH = -10.0 mA Total output current of pins = (-10.0 × 0.7)/(50 × 0.01) = -14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Note 4. Caution The applied current for the products of industrial application (R5F104xxDxx) is -100 mA. P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 1.6 V VDD 5.5 V 1.6 V EVDD0 5.5 V 1.6 V VDD 5.5 V -135.0
Note 4
Conditions 1.6 V EVDD0 5.5 V
MIN.
TYP.
MAX. -10.0
Note 2
Unit mA
-55.0 -10.0 -5.0 -2.5 -80.0 -19.0 -10.0 -5.0
mA mA mA mA mA mA mA mA
4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
mA mA
-0.1
Note 2
-1.5
mA
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Output current, low
Note 1
Symbol IOL1 Per pin for P00 to P06, P10 to P17, P30, P31,
Conditions
MIN.
TYP.
MAX. 20.0
Note 2
Unit mA
P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 Per pin for P60 to P63 4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 (When duty = 70% Note 3) Total of all pins (When duty = 70% Note 3) IOL2 Per pin for P20 to P27, P150 to P156 Total of all pins (When duty = 70% Note 3) Note 1. Note 2. Note 3. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0, EVSS1, and VSS pins. However, do not exceed the total current value. Specification under conditions where the duty factor is 70 %. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70 % to n %). • Total output current of pins = (IOL × 0.7)/(n × 0.01) Where n = 50 % and IOL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 1.6 V VDD 5.5 V 0.4
Note 2
15.0
Note 2
mA
Total of P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 (When duty = 70% Note 3)
70.0 15.0 9.0 4.5 80.0 35.0 20.0 10.0
mA mA mA mA mA mA mA mA
4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
150.0
mA
mA
5.0
mA
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Input voltage, high Symbol VIH1 Conditions P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VIH2 P01, P03, P04, P10, P14 to P17, TTL input buffer P30, P31, P43, P44, P50, P53 to P55, P80, P81, P142, P143 4.0 V EVDD0 5.5 V TTL input buffer 3.3 V EVDD0 < 4.0 V TTL input buffer 1.6 V EVDD0 < 3.3 V VIH3 VIH4 VIH5 Input voltage, low VIL1 P20 to P27, P150 to P156 P60 to P63 P121 to P124, P137, EXCLK, EXCLKS, RESET P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VIL2 P01, P03, P04, P10, P14 to P17, TTL input buffer P30, P31, P43, P44, P50, P53 to P55, P80, P81, P142, P143 4.0 V EVDD0 5.5 V TTL input buffer 2.7 V EVDD0 < 4.0 V TTL input buffer 1.6 V EVDD0 < 2.7 V VIL3 VIL4 VIL5 Caution P20 to P27, P150 to P156 P60 to P63 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0 0 0.3 VDD 0.3 EVDD0 0.2 VDD V V V 0 0.32 V 0 0.5 V 0 0.8 V Normal input buffer 0.7 VDD 0.7 EVDD0 0.8 VDD 0 VDD 6.0 VDD 0.2 EVDD0 V V V V 1.50 EVDD0 V 2.0 EVDD0 V 2.2 EVDD0 V Normal input buffer MIN. 0.8 EVDD0 TYP. MAX. EVDD0 Unit V
The maximum value of VIH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Output voltage, high Symbol VOH1 Conditions P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, 4.0 V EVDD0 5.5 V, IOH1 = -10.0 mA EVDD0 - 0.7 EVDD0 - 0.5 EVDD0 - 0.5 VDD - 0.5 1.3 0.7 0.4 0.4 0.4 0.4 0.4 2.0 0.4 0.4 0.4 0.4 V V V V V V V V V V V V V V V V MIN. EVDD0 - 1.5 TYP. MAX. Unit V
4.0 V EVDD0 5.5 V, P80 to P87, P100 to P102, P110, IOH1 = -3.0 mA P111, P120, P130, P140 to P147 1.8 V EVDD0 5.5 V, IOH1 = -1.5 mA 1.6 V EVDD0 < 1.8 V, IOH1 = -1.0 mA VOH2 Output voltage, low VOL1 P20 to P27, P150 to P156 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, 1.6 V VDD 5.5 V, IOH2 = -100 A 4.0 V EVDD0 5.5 V, IOL1 = 20.0 mA
4.0 V EVDD0 5.5 V, P80 to P87, P100 to P102, P110, IOL1 = 8.5 mA P111, P120, P130, 4.0 V EVDD0 5.5 V, P140 to P147 IOL1 = 4.0 mA 2.7 V EVDD0 5.5 V, IOL1 = 1.5 mA 1.8 V EVDD0 5.5 V, IOL1 = 0.6 mA 1.6 V EVDD0 < 1.8 V, IOL1 = 0.3 mA VOL2 VOL3 P20 to P27, P150 to P156 P60 to P63 1.6 V VDD 5.5 V, IOL2 = 400 A 4.0 V EVDD0 5.5 V, IOL3 = 15.0 mA 4.0 V EVDD0 5.5 V, IOL3 = 5.0 mA 2.7 V EVDD0 5.5 V, IOL3 = 3.0 mA 1.8 V EVDD0 5.5 V, IOL3 = 2.0 mA 1.6 V EVDD0 5.5 V, IOL3 = 1.0 mA Caution
P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, P142 to P144 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Input leakage current, high Symbol ILIH1 Conditions P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 ILIH2 P20 to P27, P137, P150 to P156, RESET ILIH3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) VI = VDD In input port or external clock input In resonator connection Input leakage current, low ILIL1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 ILIL2 P20 to P27, P137, P150 to P156, RESET ILIL3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) VI = VSS In input port or external clock input In resonator connection On-chip pll-up resistance RU P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. VI = EVSS0, In input port 10 20 100 k -10 A -1 A VI = VSS -1 A VI = EVSS0 -1 A 10 A 1 A VI = VDD 1 A VI = EVDD0 MIN. TYP. MAX. 1 Unit A
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.3.2
Supply current characteristics
(1/2)
MIN. TYP. MAX. Unit Basic VDD = 5.0 V 2.4 2.4 2.1 2.1 5.2 5.2 4.8 4.8 4.1 4.1 3.8 3.8 2.8 2.8 1.3 1.3 1.3 1.3 3.3 3.5 3.3 3.5 2.0 2.1 2.0 2.1 1.2 1.2 1.2 1.2 4.7 4.7 4.7 4.7 4.8 4.8 4.8 4.8 5.4 5.4 6.1 6.1 6.7 6.7 7.5 7.5 8.9 8.9 8.7 8.7 8.1 8.1 6.9 6.9 6.3 6.3 4.6 4.6 2.0 2.0 1.8 1.8 5.3 5.5 5.3 5.5 3.1 3.2 3.1 3.2 1.9 2.0 1.9 2.0 A mA mA mA mA mA mA operation VDD = 3.0 V Basic VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 3.0 V operation VDD = 2.0 V Normal VDD = 3.0 V operation VDD = 2.0 V Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Square wave input operation Resonator connection Square wave input operation Resonator connection Square wave input operation Resonator connection Square wave input operation Resonator connection Square wave input operation Resonator connection
(1) Flash ROM: 16 to 64 KB of 30- to 64-pin products (TA = -40 to +85 C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V)
Parameter Symbol Supply current
Note 1
Conditions Operating High-speed mode fHOCO = 64 MHz, operation Notes 3, 5 fIH = 32 MHz fHOCO = 32 MHz, fIH = 32 MHz High-speed fHOCO = 64 MHz,
IDD1
operation Notes 3, 5 fIH = 32 MHz fHOCO = 32 MHz, fIH = 32 MHz fHOCO = 48 MHz, fIH = 24 MHz fHOCO = 24 MHz, fIH = 24 MHz fHOCO = 16 MHz, fIH = 16 MHz Low-speed fHOCO = 8 MHz,
operation Notes 3, 5 fIH = 8 MHz Low-voltage fHOCO = 4 MHz, operation Notes 3, 5 fIH = 4 MHz High-speed operation
Notes 2, 5
fMX = 20 MHz, VDD = 5.0 V fMX = 20 MHz, VDD = 3.0 V fMX = 10 MHz, VDD = 5.0 V fMX = 10 MHz, VDD = 3.0 V
Low-speed operation
Notes 2, 5
fMX = 8 MHz, VDD = 3.0 V fMX = 8 MHz, VDD = 2.0 V
Subsystem clock operation
Note 4
fSUB = 32.768 kHz Normal TA = -40 C TA = +25 C TA = +50 C TA = +70 C TA = +85 C
fSUB = 32.768 kHz Normal
fSUB = 32.768 kHz Normal
fSUB = 32.768 kHz Normal
fSUB = 32.768 kHz Normal
(Notes and Remarks are listed on the next page.)
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Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
Note 2. Note 3. Note 4. Note 5.
When high-speed on-chip oscillator and subsystem clock are stopped. When high-speed system clock and subsystem clock are stopped. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 5.5 V@1 MHz to 32 MHz VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C Note fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(1) Flash ROM: 16 to 64 KB of 30- to 64-pin products (TA = -40 to +85 C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V)
Parameter Supply current
Note 1
(2/2)
MIN. VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 3.0 V VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection TYP. 0.80 0.80 0.54 0.54 0.62 0.62 0.44 0.44 0.40 0.40 260 260 420 420 0.28 0.53 0.28 0.49 0.19 0.30 0.19 0.30 95 145 95 145 0.25 0.44 0.30 0.49 0.33 0.52 0.36 0.55 0.97 0.16 0.18 0.24 0.26 0.29 0.90 0.51 1.10 1.90 3.30 0.57 0.76 1.17 1.36 1.97 2.16 3.37 3.56 A MAX. 3.09 3.09 2.40 2.40 2.40 2.40 1.83 1.83 1.38 1.38 710 710 700 700 1.55 1.74 1.55 1.74 0.86 0.93 0.86 0.93 550 590 550 590 A A mA A A Unit mA
Symbol IDD2
Note 2
Conditions HALT mode High-speed fHOCO = 64 MHz, operation Notes 4, 7 fIH = 32 MHz fHOCO = 32 MHz, fIH = 32 MHz fHOCO = 48 MHz, fIH = 24 MHz fHOCO = 24 MHz, fIH = 24 MHz fHOCO = 16 MHz, fIH = 16 MHz Low-speed operation
Notes 4, 7
fHOCO = 8 MHz, fIH = 8 MHz fHOCO = 4 MHz, fIH = 4 MHz fMX = 20 MHz, VDD = 5.0 V fMX = 20 MHz, VDD = 3.0 V fMX = 10 MHz, VDD = 5.0 V fMX = 10 MHz, VDD = 3.0 V
Low-voltage operation
Notes 4, 7
High-speed operation Notes 3, 7
Low-speed operation Notes 3, 7
fMX = 7 MHz, VDD = 3.0 V fMX = 8 MHz, VDD = 2.0 V
Subsystem clock operation
Note 5
fSUB = 32.768 kHz, TA = -40 C fSUB = 32.768 kHz, TA = +25 C fSUB = 32.768 kHz, TA = +50 C fSUB = 32.768 kHz, TA = +70 C fSUB = 32.768 kHz, TA = +85 C
IDD3
STOP mode
Note 6
TA = -40 C TA = +25 C TA = +50 C TA = +70 C TA = +85 C
(Notes and Remarks are listed on the next page.)
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Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD , EV DD0 o r V SS , EVSS0 . The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
Note 2. Note 3. Note 4. Note 5.
During HALT instruction execution by flash memory. When high-speed on-chip oscillator and subsystem clock are stopped. When high-speed system clock and subsystem clock are stopped. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When high-speed onchip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current.
Note 6. Note 7.
When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 5.5 V@1 MHz to 32 MHz VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C Note fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Supply current
Note 1
(1/2)
MIN. TYP. MAX. Unit 2.6 2.6 2.3 2.3 5.8 5.8 5.4 5.4 4.5 4.5 4.2 4.2 3.1 3.1 1.4 1.4 1.4 1.4 3.7 3.9 3.7 3.9 2.2 2.3 2.2 2.3 1.3 1.3 1.3 1.3 5.0 5.0 5.0 5.0 5.1 5.1 5.5 5.5 6.5 6.5 7.1 7.1 8.8 8.8 10.5 10.5 14.5 14.5 10.2 10.2 9.6 9.6 7.8 7.8 7.4 7.4 5.3 5.3 2.3 2.3 1.9 1.9 6.2 6.4 6.2 6.4 3.6 3.7 3.6 3.7 2.2 2.3 2.2 2.3 A mA mA mA mA mA mA
Conditions Operating High-speed mode fHOCO = 64 MHz, Basic VDD = 5.0 V operation Notes 3, 5 fIH = 32 MHz fHOCO = 32 MHz, fIH = 32 MHz High-speed fHOCO = 64 MHz, operation VDD = 3.0 V Basic VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 3.0 V operation VDD = 2.0 V Normal VDD = 3.0 V
IDD1
operation Notes 3, 5 fIH = 32 MHz fHOCO = 32 MHz, fIH = 32 MHz fHOCO = 48 MHz, fIH = 24 MHz fHOCO = 24 MHz, fIH = 24 MHz fHOCO = 16 MHz, fIH = 16 MHz Low-speed operation Notes 3, 5 Low-voltage operation Notes 3, 5 High-speed operation
Notes 2, 5
fHOCO = 8 MHz, fIH = 8 MHz fHOCO = 4 MHz, fIH = 4 MHz fMX = 20 MHz, VDD = 5.0 V fMX = 20 MHz, VDD = 3.0 V fMX = 10 MHz, VDD = 5.0 V fMX = 10 MHz, VDD = 3.0 V
operation VDD = 2.0 V Normal Square wave input
operation Resonator connection Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Normal Square wave input operation Resonator connection Square wave input operation Resonator connection Square wave input operation Resonator connection Square wave input operation Resonator connection Square wave input operation Resonator connection Square wave input operation Resonator connection
Low-speed operation
Notes 2, 5
fMX = 8 MHz, VDD = 3.0 V fMX = 8 MHz, VDD = 2.0 V
Subsystem clock operation Note 4
fSUB = 32.768 kHz Normal TA = -40 C TA = +25 C TA = +50 C TA = +70 C TA = +85 C
fSUB = 32.768 kHz Normal
fSUB = 32.768 kHz Normal
fSUB = 32.768 kHz Normal
fSUB = 32.768 kHz Normal
(Notes and Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
Note 2. Note 3. Note 4. Note 5.
When high-speed on-chip oscillator and subsystem clock are stopped. When high-speed system clock and subsystem clock are stopped. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 5.5 V@1 MHz to 32 MHz VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25 °C Note fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Supply current
Note 1
(2/2)
MIN. TYP. 0.88 0.88 0.62 0.62 0.68 0.68 0.50 0.50 0.44 0.44 290 290 440 440 0.31 0.50 0.31 0.50 0.21 0.30 0.21 0.30 110 160 110 160 0.28 0.47 0.34 0.53 0.37 0.56 0.61 0.80 1.55 1.74 0.19 0.25 0.28 0.52 1.46 0.57 2.26 3.99 8.00 0.66 0.85 2.35 2.54 4.08 4.27 8.09 8.28 A MAX. 3.32 3.32 2.63 2.63 2.57 2.57 2.00 2.00 1.49 1.49 800 800 755 755 1.63 1.85 1.63 1.85 0.89 0.97 0.89 0.97 580 630 580 630 A A mA A A Unit mA
Conditions HALT mode High-speed
Note 2
IDD2
fHOCO = 64 MHz,
VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 3.0 V VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection
operation Notes 4, 7 fIH = 32 MHz fHOCO = 32 MHz, fIH = 32 MHz fHOCO = 48 MHz, fIH = 24 MHz fHOCO = 24 MHz, fIH = 24 MHz fHOCO = 16 MHz, fIH = 16 MHz Low-speed operation
Notes 4, 7
fHOCO = 8 MHz, fIH = 8 MHz fHOCO = 4 MHz, fIH = 4 MHz fMX = 20 MHz, VDD = 5.0 V fMX = 20 MHz, VDD = 3.0 V fMX = 10 MHz, VDD = 5.0 V fMX = 10 MHz, VDD = 3.0 V
Low-voltage operation
Notes 4, 7
High-speed operation Notes 3, 7
Low-speed operation Notes 3, 7
fMX = 8 MHz, VDD = 3.0 V fMX = 8 MHz, VDD = 2.0 V
Subsystem clock operation
Note 5
fSUB = 32.768 kHz, TA = -40 C fSUB = 32.768 kHz, TA = +25 C fSUB = 32.768 kHz, TA = +50 C fSUB = 32.768 kHz, TA = +70 C fSUB = 32.768 kHz, TA = +85 C
IDD3
STOP
TA = -40 C TA = +50 C TA = +70 C TA = +85 C
mode Note 6 TA = +25 C
(Notes and Remarks are listed on the next page.)
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Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
Note 2. Note 3. Note 4. Note 5.
During HALT instruction execution by flash memory. When high-speed on-chip oscillator and subsystem clock are stopped. When high-speed system clock and subsystem clock are stopped. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When high-speed onchip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current.
Note 6. Note 7.
When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 5.5 V@1 MHz to 32 MHz VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C Note fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(3) Common to RL78/G14 all products (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol fSUB = 32.768 kHz
Notes 1, 2
Conditions Real-time clock operation 12-bit interval timer operation fIL = 15 kHz
MIN.
TYP. 0.02 0.02 0.22
MAX.
Unit A
RTC operating current IRTC
Watchdog timer operating current A/D converter operating current A/D converter reference voltage current D/A converter operating current
IWDT
Notes 2, 3
A
IADC
Note 4
When conversion
Normal mode, AVREFP = VDD = 5.0 V
1.3 0.5 75
1.7 0.7
mA mA A
at maximum speed Low voltage mode, AVREFP = VDD = 3.0 V
IADREF
IDAC Notes
5, 9
Per D/A converter channel
1.5
mA A A A A A A A A
Comparator operating ICMP Notes 6, 9 current
VDD = 5.0 V, Regulator output voltage = 2.1 V VDD = 5.0 V, Regulator output voltage = 1.8 V
Window comparator mode High-speed comparator mode Low-speed comparator mode Window comparator mode High-speed comparator mode Low-speed comparator mode
12.5 6.5 1.7 8.0 4.0 1.3 75 0.08 2.50 12.20
Temperature sensor operating current LVD operating current BGO operating current Note 1.
ITMPS ILVI Note 7 IBGO Note 8
mA
Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The TYP. value of the current value of the RL78/G14 is the sum of the TYP. values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. The IDD1 and IDD2 MAX. values also include the real-time clock operating current. However, IDD2 subsystem clock operation includes the operational current of the real-time clock.
Note 2. Note 3.
When high speed on-chip oscillator and high-speed system clock are stopped. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78/G14 is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates in STOP mode.
Note 4. Note 5. Note 6. Note 7. Note 8. Note 9.
Current flowing only to the A/D converter. The current value of the RL78/G14 is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Current flowing only to the D/A converter. The current value of the RL78/G14 is the sum of IDD1 or IDD2 and IADC when the D/A converter operates in an operation mode or the HALT mode. Current flowing only to the comparator circuit. The current value of the RL78/G14 is the sum of IDD1, IDD2 or IDD3 and ICMP when the comparator circuit operates in the Operating, HALT or STOP mode. Current flowing only to the LVD circuit. The current value of the RL78/G14 is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. Current flowing only to the BGO. The current value of the RL78/G14 is the sum of IDD1 or IDD2 and IBGO when the BGO operates in an operation mode. A comparator and D/A converter are provided in products with 96 KB or more code flash memory.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP. value is TA = 25 °C
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.4 2.4.1
AC Characteristics Basic operation
(1/2)
MIN. 2.7 V VDD 5.5 V 2.4 V VDD < 2.7 V 1.6 V VDD 5.5 V 1.8 V VDD 5.5 V 1.8 V VDD 5.5 V 2.7 V VDD 5.5 V 2.4 V VDD < 2.7 V 1.8 V VDD 5.5 V 1.8 V VDD 5.5 V 0.03125 0.0625 0.25 0.125 28.5 0.03125 0.0625 0.25 0.125 1.0 1.0 1.0 32 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 1.6 V VDD < 1.8 V tEXHS, tEXLS 24 60 120 13.7 1/fMCK + 10
Note
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Instruction cycle (minimum instruction execution time) Symbol TCY Main system clock (fMAIN) operation Conditions High-speed main mode Low voltage main mode Low-speed main mode Subsystem clock (fSUB) operation In the self programming mode High-speed main mode Low voltage main mode Low-speed main mode External main system clock frequency fEX 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 1.6 V VDD < 1.8 V fEXS External main system clock input high-level width, low-level width tEXH, tEXL 20.0 8.0 4.0 35 1 30.5 31.3 1 1 1 1 TYP. MAX. 1 1 1
Unit s s s s s s s s s MHz MHz MHz kHz ns ns ns s ns
TI00 to TI03, TI10 to TI13 input high-level width, low-level width Timer RJ input cycle
tTIH, tTIL
fC
TRJIO
2.7 V EVDD0 5.5 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
100 300 500 40 120 200
ns ns ns ns ns ns
Timer RJ input highlevel width, low-level width Note
fWH, fWL
TRJIO
2.7 V EVDD0 5.5 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
The following conditions are required for low voltage interface when EVDD0 < VDD 1.8 V EVDD0 < 2.7 V : MIN. 125 ns 1.6 V EVDD0 < 1.8 V : MIN. 250 ns
Remark
fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3))
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2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items TO00 to TO03, TO10 to T13 output frequency Symbol fTO Conditions High-speed main mode 4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V Low voltage main mode Low-speed main mode 1.6 V EVDD0 5.5 V 1.8 V EVDD0 5.5 V 1.6 V EVDD0 < 1.8 V PCLBUZ0, PCLBUZ1 output frequency fPCL High-speed main mode 4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V Low voltage main mode 1.8 V EVDD0 5.5 V 1.6 V EVDD0 < 1.8 V Low-speed main mode 1.8 V EVDD0 5.5 V 1.6 V EVDD0 < 1.8 V Interrupt input high-level width, low-level width Key interrupt input low-level width RESET low-level width tRSL tINTH, tINTL tKR INTP0 INTP1 to INTP11 1.8 V EVDD0 5.5 V 1.6 V EVDD0 < 1.8 V 1.6 V VDD 5.5 V 1.6 V EVDD0 5.5 V 1 1 250 1 10 MIN. TYP. MAX. 16 8 4 2 2 4 2 16 8 4 2 4 2 4 2
(2/2)
Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz s s ns s s
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.5 2.5.1
Peripheral Functions Characteristics Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Transfer rate
Note 1
Symbol
Conditions
MIN.
TYP.
MAX. fMCK/6
Note 2
Unit bps Mbps
Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK
5.3
UART mode connection diagram (during communication at same potential)
TxDq
RL78/G14
Rx User’s device
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq
Note 1. Note 2.
Transfer rate in the SNOOZE mode is MAX. 9600 bps and MIN. 4800 bps. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V EVDD0 < 1.8 V : MAX. 0.6 Mbps
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(2) During communication at same potential (CSI mode) (master mode (fMCK/2), SCKp... internal clock output) (TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SCKp cycle time SCKp high-/low-level width Symbol tKCY1 tKH1, tKL1 SIp setup time (to SCKp↑) Note 2 tSIK1 Conditions 2.7 V EVDD0 5.5 V 4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V 4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V SIp hold time (from SCKp↑) Note 3 Delay time from SCKp↓ to SOp output
Note 4
MIN. 62.5 Note 1 tKCY1/2 - 7 tKCY1/2 - 10 23 33
Note 5
TYP.
MAX.
Unit ns ns ns ns ns ns
tKSI1 tKSO1
2.7 V EVDD0 5.5 V C = 20 pF Note 6
10 10
ns
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Caution
The value must also be 2/fCLK or more. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Using the fMCK within 24 MHz. C is the load capacitance of the SCKp and SOp output lines.
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used. Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00))
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(3) During communication at same potential (CSI mode) (master mode (fMCK/4), SCKp... internal clock output) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SCKp cycle time Symbol tKCY1 Conditions 2.7 V EVDD0 5.5 V 2.4 V EVDD0 5.5 V 1.8 V EVDD0 5.5 V 1.6 V EVDD0 5.5 V SCKp high-/low-level width tKH1, tKL1 4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V 2.4 V EVDD0 5.5 V 1.8 V EVDD0 5.5 V 1.6 V EVDD0 5.5 V SIp setup time (to SCKp↑) Note 2 tSIK1 4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V 2.4 V EVDD0 5.5 V 1.8 V EVDD0 5.5 V 1.6 V EVDD0 5.5 V SIp hold time (from SCKp↑) Note 3 Delay time from SCKp↓ to SOp output
Note 4
MIN. 125 Note 1 250 Note 1 500 Note 1 1000 Note 1 tKCY1/2 - 12 tKCY1/2 - 18 tKCY1/2 - 38 tKCY1/2 - 50 tKCY1/2 - 100 44 44 75 110 220 19
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKSI1 tKSO1 C = 30 pF Note 5
25
ns
Note 1. Note 2. Note 3. Note 4. Note 5. Caution
The value must also be 4/fCLK or more. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines.
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SCKp cycle time Note 5 Symbol tKCY2 Conditions 4.0 V EVDD0 5.5 V 20 MHz < fMCK fMCK 20 MHz 2.7 V EVDD0 < 4.0 V 16 MHz < fMCK fMCK 16 MHz 1.8 V EVDD0 < 2.7 V 16 MHz < fMCK fMCK 16 MHz 1.6 V EVDD0 < 1.8 V SCKp high-/low-level width tKH2, tKL2 SIp setup time (to SCKp↑)
Note 1
(1/2)
TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2/fMCK + 44 2/fMCK + 44 2/fMCK + 75 2/fMCK + 110 2/fMCK + 220 ns ns ns ns ns
MIN. 8/fMCK 6/fMCK 8/fMCK 6/fMCK 8/fMCK 6/fMCK 6/fMCK tKCY2/2 1/fMCK + 20 1/fMCK + 30 1/fMCK + 40 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 1/fMCK + 250
1.6 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
tSIK2
SIp hold time (from SCKp↑)
Note 2
tKSI2
2.7 V EVDD0 5.5 V 2.4 V EVDD0 < 2.7 V 1.8 V EVDD0 < 2.4 V 1.6 V EVDD0 < 1.8 V
Delay time from SCKp↓ to SOp output
Note 3
tKSO2
C = 30 pF Note 4
4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V 2.4 V EVDD0 < 2.7 V 1.8 V EVDD0 < 2.4 V 1.6 V EVDD0 < 1.8 V
Note 1. Note 2. Note 3. Note 4. Note 5. Caution
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SOp output lines. The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Select the TTL input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SSI00 setup time Symbol tSSIK DAPmn = 0 Conditions 2.7 V EVDD0 5.5 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V DAPmn = 1 2.7 V EVDD0 5.5 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V SSI00 hold time tKSSI DAPmn = 0 2.7 V EVDD0 5.5 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V DAPmn = 1 2.7 V EVDD0 5.5 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
Caution
(2/2)
TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
MIN. 120 200 400 1/fMCK + 120 1/fMCK + 200 1/fMCK + 400 1/fMCK + 120 1/fMCK + 200 1/fMCK + 400 120 200 400
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5)
CSI mode connection diagram (during communication at same potential)
SCKp RL78/G14 SIp SOp
SCK SO SI User's device
CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00))
SCK00 SI00 RL78/G14 SO00 SSI00
SCK SO User's device SI SS0
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2 tKL1, 2 tKH1, 2
SCKp tSIK1, 2 tKSI1, 2
SIp tKSO1, 2
Input data
SOp
Output data
tSSIK SSI00 (CSI00 only)
tKSSI
CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2 tKH1, 2 tKL1, 2
SCKp tSIK1, 2 tKSI1, 2
SIp tKSO1, 2
Input data
SOp
Output data
tSSIK SSI00 (CSI00 only)
tKSSI
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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RL78/G14
Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(5) During communication at same potential (simplified I2C mode) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SCLr clock frequency Symbol fSCL Conditions 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = “L” tLOW 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1.8 V VDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = “H” tHIGH 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Data setup time (reception) tSU:DAT 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Data hold time (transmission) tHD:DAT 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k
Note
MIN.
MAX. 1000 400 300 250
Unit kHz kHz kHz kHz ns ns ns ns ns ns ns ns ns
475 1150 1550 1850 475 1150 1550 1850 1/fMCK + 85
Note
1/fMCK + 145
Note
ns
1/fMCK + 230
Note
ns
1/fMCK + 290
Note
ns
0 0 0 0
305 355 405 405
ns ns ns ns
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
(Caution and Remarks are listed on the next page.)
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. Simplified I2C mode mode connection diagram (during communication at same potential)
VDD Rb SDAr RL78/G14 SCLr SCL SDA User’s device
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL tLOW tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Caution
Select the TTL input buffer and the N-ch open drain output (EVDD0 tolerance) mode for the SDAr pin and the N-ch open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 3 to 5, 14),
h: POM number (h = 0, 1, 3 to 5, 7, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00 to 03, 10 to 13)
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(6) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Transfer rate
Notes 1, 2
(1/2)
TYP. MAX. fMCK/6 Note 1 Unit bps Mbps
Symbol reception
Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate fCLK = 8 MHz, fMCK = fCLK
MIN.
5.3
fMCK/6 Note 1 5.3
bps Mbps
fMCK/6
Note 1 to Note 3
bps
1.3
Mbps
Note 1. Note 2. Note 3.
Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps Use it with EVDD0 Vb. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V EVDD0 < 1.8 V : MAX. 0.6 Mbps
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD0 tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in UART mode. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 5. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(6) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Transfer rate Symbol Conditions transmission 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V
Note 1.
Notes 2, 6, 7 Notes 2, 4
(2/2)
MIN. TYP. MAX.
Notes 1, 2
Unit bps Mbps
2.8
Note 3
bps Mbps
1.2
Note 5
bps Mbps
0.40
Note 8
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V and 2.7 V Vb 4.0 V
1 Maximum transfer rate = {-Cb Rb In (1 2.2 Vb )} 3 [bps]
1 Transfer rate 2 Baud rate error (theoretical value) = ( 1 Transfer rate
- {-Cb Rb In (1 -
2.2 Vb
)} 100 [%]
) Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 2. Note 3. Note 4.
Transfer rate in the SNOOZE mode: MAX. 9600 bps, MIN. 4800 bps This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V and 2.3 V Vb 2.7 V
1 Maximum transfer rate = {-Cb Rb In (1 2.0 Vb )} 3 [bps]
1 Transfer rate 2 Baud rate error (theoretical value) = ( 1 Transfer rate
- {-Cb Rb In (1 -
2.0 Vb
)} 100 [%]
) Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 5. Note 6.
This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. Use it with EVDD0 Vb.
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Note 7.
2. ELECTRICAL SPECIFICATIONS
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V EVDD0 < 3.3 V and 1.6 V Vb 2.0 V
1 Maximum transfer rate = {-Cb Rb In (1 1.5 Vb )} 3 [bps]
1 Transfer rate 2 Baud rate error (theoretical value) = ( 1 Transfer rate
- {-Cb Rb In (1 -
1.5 Vb
)} 100 [%]
) Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 8.
This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD0 tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in UART mode. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 5. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
UART mode connection diagram (during communication at different potential)
Vb Rb TxDq RL78/G14 Rx User’s device RxDq Tx
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. UART mode bit width (during communication at different potential) (reference)
1/Transfer rate Low-bit width High-bit width Baud rate error tolerance
TxDq
1/Transfer rate High-/Low-bit width Baud rate error tolerance
RxDq
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD0 tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
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Caution (7)
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output)
Parameter Symbol tKCY1 Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k tKH1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k tKL1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k tSIK1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k tKSI1
Note 2
(TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
MIN. 200 Note 1 300 Note 1 tKCY1/2 - 50 tKCY1/2 - 120 tKCY1/2 - 7 tKCY1/2 - 10 58 121 10 10 60 130 23 33 10 10 10 10 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SCKp cycle time
SCKp high-level width
SCKp low-level width
SIp setup time (to SCKp↑) Note 2
SIp hold time (from SCKp↑)
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k
Delay time from SCKp↓ to SOp output Note 2
tKSO1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k
SIp setup time (to SCKp↓)
Note 3
tSIK1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k
SIp hold time (from SCKp↓) Note 3
tKSI1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k
Delay time from SCKp↑ to SOp output
Note 3
tKSO1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k
(Notes, Caution and Remarks are listed on the next page.)
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. CSI mode connection diagram (during communication at different potential)
Vb Rb SCKp Vb Rb SCK SO SI User’s device
RL78/G14
SIp SOp
Note 1. Note 2. Note 3. Caution
The value must also be 2/fCLK or more. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in CSI mode. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V: VIH = 2.0 V, VIL = 0.5 V
Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Remark 5. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(8) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SCKp cycle time Symbol tKCY1 Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k
Note 1.
(1/2)
TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
MIN. 300 Note 500 Note 1150 Note tKCY1/2 - 75 tKCY1/2 - 170 tKCY1/2 - 458 tKCY1/2 - 12 tKCY1/2 - 18 tKCY1/2 - 50
The value must also be 4/fCLK or more.
Caution 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Caution 2. Use it with EVDD0 Vb. Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in CSI mode. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 4. 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(8) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SIp setup time (to SCKp↑) Note 1 Symbol tSIK1 Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time (from SCKp↑) Note 1 tKSI1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp↓ to SOp output
Note 1
(2/2)
MIN. 81 177 479 19 19 19 100 195 483 44 44 110 19 19 19 25 25 25 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKSO1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k
SIp setup time (to SCKp↓)
Note 2
tSIK1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k
SIp hold time (from SCKp↓) Note 2
tKSI1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp↑ to SOp output Note 2
tKSO1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k
(Notes, Caution and Remarks are listed on the next page.)
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. CSI mode connection diagram (during communication at different potential
Vb Rb SCKp RL78/G14 SIp SOp Vb Rb SCK SO SI User’s device
Note 1. Note 2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Caution 2. Use it with EVDD0 Vb. Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in CSI mode. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1 tKL1 tKH1
SCKp
tSIK1
tKSI1
SIp
Input data
tKSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1 tKH1 tKL1
SCKp
tSIK1
tKSI1
SIp
Input data
tKSO1
SOp
Output data
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(9) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SCKp cycle time Note 1 Symbol tKCY2 2.7 V Vb 4.0 V Conditions 4.0 V EVDD0 5.5 V, 24 MHz fMCK 20 MHz < fMCK 24 MHz 8 MHz < fMCK 20 MHz 4 MHz < fMCK 8 MHz fMCK 4 MHz 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V 24 MHz < fMCK 20 MHz < fMCK 24 MHz 16 MHz < fMCK 20 MHz 8 MHz < fMCK 16 MHz 4 MHz < fMCK 8 MHz fMCK 4 MHz 1.8 V EVDD0 < 3.3 V, 24 MHz fMCK 1.6 V Vb 2.0 V Note 2 20 MHz < fMCK 24 MHz 16 MHz < fMCK 20 MHz 8 MHz < fMCK 16 MHz 4 MHz < fMCK 8 MHz fMCK 4 MHz SCKp high-/low-level width tKH2, tKL2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 2 SIp setup time (to SCKp↑) Note 3 SIp hold time (from SCKp↑) Note 4 Delay time from SCKp↓ to SOp output Note 5 tKSO2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k (Notes, Caution and Remarks are listed on the next page.) 2/fMCK + 573 ns 2/fMCK + 214 ns 1/fMCK + 250 2/fMCK + 120 ns tKSI2 tSIK2 2.7 V EVDD0 < 5.5 V 1.8 V EVDD0 < 3.3 V MIN. 14/fMCK 12/fMCK 10/fMCK 8/fMCK 6/fMCK 20/fMCK 16/fMCK 14/fMCK 12/fMCK 8/fMCK 6/fMCK 48/fMCK 36/fMCK 32/fMCK 26/fMCK 16/fMCK 10/fMCK tKCY2/2 - 12 tKCY2/2 - 18 tKCY2/2 - 50 1/fMCK + 20 1/fMCK + 30 1/fMCK + 31 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. CSI mode connection diagram (during communication at different potential)
Vb Rb SCKp RL78/G14 SIp SOp SCK SO SI User’s device
Note 1. Note 2. Note 3. Note 4. Note 5.
Transfer rate in the SNOOZE mode: MAX. 1 Mbps Use it with EVDD0 Vb. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10))
Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in CSI mode. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V: VIH = 1.50 V, VIL = 0.32 V
Remark 5. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential. Also, communication at different potential cannot be performed during clock synchronous serial communication with the slave select function.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2 tKL2 tKH2
SCKp
tSIK2
tKSI2
SIp
Input data
tKSO2
SOp
Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2 tKH2 tKL2
SCKp
tSIK2
tKSI2
SIp
Input data
tKSO2
SOp
Output data
Caution
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential. Also, communication at different potential cannot be performed during clock synchronous serial communication with the slave select function.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter SCLr clock frequency Symbol fSCL Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = “L” tLOW 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = “H” tHIGH 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k (Notes, Caution and Remarks are listed on the next page.) 610 ns 600 ns 675 ns 200 ns 245 ns 1550 ns 1150 ns 1150 ns 475 ns 475 ns 300 kHz 400 kHz 400 kHz 1000 kHz MIN. MAX. 1000
(1/2)
Unit kHz
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Data setup time (reception) Symbol tSU:DAT Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k Data hold time (transmission) tHD:DAT 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k
Note 1. Note 2. Caution
(2/2)
MIN. 1/fMCK + 135
Note 2
MAX.
Unit ns
1/fMCK + 135
Note 2
ns
1/fMCK + 190
Note 2
ns
1/fMCK + 190
Note 2
ns
1/fMCK + 190
Note 2
ns
0
305
ns
0
305
ns
0
355
ns
0
355
ns
0
405
ns
Use it with EVDD0 Vb. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Select the TTL input buffer and the N-ch open drain output (EVDD0 tolerance) mode for the SDAr pin and the N-ch open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg).
(Remarks are listed on the next page.)
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. Simplified I2C mode connection diagram (during communication at different potential)
Vb Rb SDAr RL78/G14 SCLr SCL Vb Rb SDA User’s device
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL tLOW tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Caution
Select the TTL input buffer and the N-ch open drain output (EVDD0 tolerance) mode for the SDAr pin and the N-ch open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 30, 31), g: PIM, POM number (g = 0, 1, 3 to 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 3), mn = 00 to 03, 10, 12, 13)
Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at
different potentials in simplified I2C mode. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V: VIH = 1.50 V, VIL = 0.32 V
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.5.2
Serial interface IICA
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Standard Parameter Symbol Conditions 2.7 V EVDD0 5.5 V 1.8 V EVDD0 5.5 V 1.6 V EVDD0 5.5 V 0 4.7 100 0.6 0.26 0 400 Mode Fast Mode Fast Mode Plus Unit
MIN. MAX. MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode plus: fCLK 10 MHz Fast mode: fCLK 3.5 MHz Normal mode: fCLK 1 MHz Setup time of restart condition Note 1 Hold time Hold time when SCLA0 = “L” tHD:STA tLOW 4.0 4.7 4.0 250 0 4.0 4.7 3.45 0.6 1.3 0.6 100 0 0.6 1.3 0.9 0.26 0.5 0.26 50 0 0.26 0.5
s s s
0
1000
kHz kHz kHz
s
tSU:STA
Hold time when SCLA0 = “H” tHIGH Data setup time (reception)
Note 2
tSU:DAT
ns
s s s
Data hold time (transmission) tHD:DAT
Setup time of stop condition Bus-free time
Note 1. Note 2.
tSU:STO tBUF
The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k Fast mode: Cb = 320 pF, Rb = 1.1 k Fast mode plus: Cb = 120 pF, Rb = 1.1 k
IICA serial transfer timing
tLOW SCL0 tHD: DAT tHD: STA
tHIGH tSU: DAT
tSU: STA
tHD: STA
tSU: STO
SDA0 tLOW
Stop condition Start condition Restart condition Stop condition
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.5.3
On-chip debug (UART)
(TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Transfer rate Symbol Conditions MIN. 115.2 k TYP. MAX. 1M Unit bps
2.6 2.6.1
Analog Characteristics A/D converter characteristics
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin: ANI2 to ANI14 (supply ANI pin to VDD) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter Resolution Overall error Notes 1, 2 Symbol RES AINL 10-bit resolution AVREFP = VDD Conversion time tCONV 10-bit resolution AVREFP = VDD 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V 3.6 V VDD 5.5 V 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Zero-scale error
Notes 1, 2
Conditions
MIN. 8
TYP.
MAX. 10
Unit bit LSB LSB
s s s s
1.2 1.2 2.125 3.1875 17 57
3.5 7.0
39 39 39 95
0.25 0.50 0.25 0.50 2.5 5.0 1.5 2.0
EZS
10-bit resolution AVREFP = VDD
1.8 V VDD 5.5 V 1.6 V VDD < 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5V 1.6 0
% FSR % FSR % FSR % FSR LSB LSB LSB LSB V V V
Full-scale error Notes 1, 2
EFS
10-bit resolution AVREFP = VDD
Integral linearity error
Note 1
ILE
10-bit resolution AVREFP = VDD
Differential linearity error
Note 1
DLE
10-bit resolution AVREFP = VDD
Reference voltage (+) Analog input voltage
AVREFP VAIN VBGR 2.4 V VDD < 5.5 V, HS (high-speed main) mode
VDD AVREFP 1.45 1.5
1.38
Note 1. Note 2.
Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (% FSR) to the full-scale value.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(2) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin: ANI16 to ANI20 (supply ANI pin to EVDD0) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter Resolution Overall error Notes 1, 2 Symbol RES AINL 10-bit resolution AVREFP = VDD Conversion time tCONV 10-bit resolution AVREFP = VDD 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V 3.6 V VDD 5.5 V 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Zero-scale error
Notes 1, 2
Conditions
MIN. 8
TYP.
MAX. 10
Unit bit LSB LSB
s s s s
1.2 1.2 2.125 3.1875 17 57
5.0 8.5
39 39 39 95
0.35 0.60 0.35 0.60 3.5 6.0 2.0 2.5
EZS
10-bit resolution AVREFP = VDD
1.8 V VDD 5.5 V 1.6 V VDD 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V 1.6 0
% FSR % FSR % FSR % FSR LSB LSB LSB LSB V V V
Full-scale error Notes 1, 2
EFS
10-bit resolution AVREFP = VDD
Integral linearity error
Note 1
ILE
10-bit resolution AVREFP = VDD
Differential linearity error
Note 1
DLE
10-bit resolution AVREFP = VDD
Reference voltage (+) Analog input voltage
AVREFP VAIN
VDD AVREFP and EVDD0 1.45 1.5
VBGR
2.4 V VDD 5.5 V, HS (high-speed main) mode
1.38
Note 1. Note 2.
Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (% FSR) to the full-scale value.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(3) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (-) = VSS (ADREFM = 0), target ANI pin: ANI0 to ANI14, ANI16 to ANI20 (TA = -40 to +85 °C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS)
Parameter Resolution Overall error Notes 1, 2 Symbol RES AINL 10-bit resolution 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Conversion time tCONV 10-bit resolution 3.6 V VDD 5.5 V 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Zero-scale error
Notes 1, 2
Conditions
MIN. 8
TYP.
MAX. 10
Unit bit LSB LSB
s s s s
1.2 1.2 2.125 3.1875 17 57
7.0 10.5
39 39 39 95
0.60 0.85 0.60 0.85 4.0 6.5 2.0 2.5
EZS
10-bit resolution
1.8 V VDD 5.5 V 1.6 V VDD 5.5 V
% FSR % FSR % FSR % FSR LSB LSB LSB LSB V V V
Full-scale error Notes 1, 2
EFS
10-bit resolution
1.8 V VDD 5.5 V 1.6 V VDD 5.5 V
Integral linearity error
Note 1
ILE
10-bit resolution
1.8 V VDD 5.5 V 1.6 V VDD 5.5 V
Differential linearity error
Note 1
DLE
10-bit resolution
1.8 V VDD 5.5 V 1.6 V VDD 5.5 V
Analog input voltage
VAIN
ANI0 to ANI14 ANI16 to ANI20
0 0 1.38 1.45
VDD EVDD0 1.5
VBGR
2.4 V VDD 5.5 V, HS (high-speed main) mode
Note 1. Note 2.
Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (% FSR) to the full-scale value.
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
(4) When AVREF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin: ANI0 to ANI14, ANI16 to ANI20 (TA = -40 to +85 °C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR, Reference voltage (-) = AVREFM = 0 V, HS (high-speed main) mode)
Parameter Resolution Conversion time Zero-scale error Notes 1, 2 Integral linearity error Note 1 Symbol RES tCONV EZS ILE 8-bit resolution 8-bit resolution 8-bit resolution 8-bit resolution 2.4 V VDD 5.5 V 2.4 V VDD 5.5 V 2.4 V VDD 5.5 V 2.4 V VDD 5.5 V 1.38 1.45 VSS 0 VBGR 17 Conditions MIN. TYP. 8 39
0.60 2.0 1.0
MAX.
Unit bit
s
% FSR LSB LSB V V V
Differential linearity error Note 1 DLE Reference voltage (+) Reference voltage (-) Analog input voltage
Note 1. Note 2.
VBGR AVREFM VAIN
1.5
Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (% FSR) to the full-scale value.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.6.2
Temperature sensor characteristics
(TA = -40 to +85 °C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-speed main) mode)
Parameter Symbol Conditions Setting ADS register = 80H, TA = +25 C Setting ADS register = 81H Temperature sensor that depends on the temperature Operation stabilization wait time tAMP 1.38 MIN. TYP. 1.05 1.45 -3.6 5 1.5 MAX. Unit V V mV/C
s
Temperature sensor output voltage VTMPS25 Reference output voltage Temperature coefficient VCONST FVTMPS
2.6.3
D/A converter characteristics
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Resolution Overall error Symbol RES AINL Rload = 4 M Rload = 8 M Settling time tSET Cload = 20 pF 1.8 V VDD 5.5 V 1.8 V VDD 5.5 V 2.7 V VDD 5.5 V 1.6 V VDD < 2.7 V Conditions MIN. TYP. MAX. 8
2.5 2.5
Unit bit LSB LSB
s s
3 6
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2. ELECTRICAL SPECIFICATIONS
2.6.4
Comparator
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Input voltage range Symbol Ivref Ivcmp Output delay td VDD = 3.0 V High-speed comparator High-speed comparator mode, window mode Low-speed comparator mode, standard mode High-electric-potential VTW+ judgment voltage Low-electric-potential judgment voltage VTWHigh-speed comparator mode, window mode 0.24 VDD V High-speed comparator mode, window mode 0.76 VDD V 3
s
Conditions
MIN. 0 -0.3
TYP.
MAX. EVDD0 1.4 EVDD0 + 0.3 1.2 2.0
Unit V V
s s
Input slew rate > 50 mV/s mode, standard mode
2.6.5
POR circuit characteristics
(TA = -40 to +85 C, VSS = 0 V)
Parameter Detection voltage Symbol VPOR VPDR Minimum pulse width Detection delay time TPW Conditions Power supply rise time Power supply fall time 300 350 MIN. TYP. 1.51 1.50 MAX. 1.54 1.53 Unit V V
s s
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.6.6
LVD circuit characteristics
(TA = -40 to +85 C, VPDR EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Detection voltage VLVI1 Supply voltage level Symbol VLVI0 Conditions Power supply rise time Power supply fall time Power supply rise time Power supply fall time VLVI2 Power supply rise time Power supply fall time VLVI3 Power supply rise time Power supply fall time VLVI4 Power supply rise time Power supply fall time VLVI5 Power supply rise time Power supply fall time VLVI6 Power supply rise time Power supply fall time VLVI7 Power supply rise time Power supply fall time VLVI8 Power supply rise time Power supply fall time VLVI9 Power supply rise time Power supply fall time VLVI10 Power supply rise time Power supply fall time VLVI11 Power supply rise time Power supply fall time VLVI12 Power supply rise time Power supply fall time VLVI13 Power supply rise time Power supply fall time Minimum pulse width Detection delay time
Caution
MIN. 3.98 3.90 3.68 3.60 3.07 3.00 2.96 2.90 2.86 2.80 2.76 2.70 2.66 2.60 2.56 2.50 2.45 2.40 2.05 2.00 1.94 1.90 1.84 1.80 1.74 1.70 1.64 1.60 300
TYP. 4.06 3.98 3.75 3.67 3.13 3.06 3.02 2.96 2.92 2.86 2.81 2.75 2.71 2.65 2.61 2.55 2.50 2.45 2.09 2.04 1.98 1.94 1.88 1.84 1.77 1.73 1.67 1.63
MAX. 4.14 4.06 3.82 3.74 3.19 3.12 3.08 3.02 2.97 2.91 2.87 2.81 2.76 2.70 2.66 2.60 2.55 2.50 2.13 2.08 2.02 1.98 1.91 1.87 1.81 1.77 1.70 1.66
Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V
s
tLW tLD
300
s
Set the detection voltage (VLVI) to be within the operating voltage range. The operating voltage range depends on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range. HS (high-speed main) mode: LS (low-speed main) mode: LV (low voltage main) mode: VDD = 2.7 to 5.5 V@1 MHz to 32 MHz VDD = 2.4 to 5.5 V@1 MHz to 16 MHz VDD = 1.8 to 5.5 V@1 MHz to 8 MHz VDD = 1.6 to 5.5 V@1 MHz to 4 MHz
Remark
VLVI (n - 1) > VLVIn: n = 1 to 13
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85 C, VPDR EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Interrupt and reset mode Symbol VLVI13 VLVI12 Conditions VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage: 1.6 V LVIS0, LVIS1 = 1, 0 (+0.1 V) VLVI11 LVIS0, LVIS1 = 0, 1 (+0.2 V) VLVI4 LVIS0, LVIS1 = 0, 0 (+1.2 V) VLVI11 VLVI10 Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage MIN. 1.60 1.74 1.70 1.84 1.80 2.86 2.80 1.80 1.94 1.90 2.05 2.00 3.07 3.00 2.40 2.56 2.50 2.66 2.60 3.68 3.60 2.70 2.86 2.80 2.96 2.90 3.98 3.90 TYP. 1.63 1.77 1.73 1.88 1.84 2.92 2.86 1.84 1.98 1.94 2.09 2.04 3.13 3.06 2.45 2.61 2.55 2.71 2.65 3.75 3.67 2.75 2.92 2.86 3.02 2.96 4.06 3.98 MAX. 1.66 1.81 1.77 1.91 1.87 2.97 2.91 1.87 2.02 1.98 2.13 2.08 3.19 3.12 2.50 2.66 2.60 2.76 2.70 3.82 3.74 2.81 2.97 2.91 3.08 3.02 4.14 4.06 Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V
VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage: 1.8 V LVIS0, LVIS1 = 1, 0 (+0.1 V) Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage
VLVI9
LVIS0, LVIS1 = 0, 1 (+0.2 V)
VLVI2
LVIS0, LVIS1 = 0, 0 (+1.2 V)
VLVI8 VLVI7
VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage: 2.4 V LVIS0, LVIS1 = 1, 0 (+0.1 V) Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage
VLVI6
LVIS0, LVIS1 = 0, 1 (+0.2 V)
VLVI1
LVIS0, LVIS1 = 0, 0 (+1.2 V)
VLVI5 VLVI4
VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V LVIS0, LVIS1 = 1, 0 (+0.1 V) Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage
VLVI3
LVIS0, LVIS1 = 0, 1 (+0.2 V)
VLVI0
LVIS0, LVIS1 = 0, 0 (+1.2 V)
Caution
Set the detection voltage (VLVI) to be within the operating voltage range. The operating voltage range depends on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range. HS (high-speed main) mode: LS (low-speed main) mode: LV (low voltage main) mode: VDD = 2.7 to 5.5 V@1 MHz to 32 MHz VDD = 2.4 to 5.5 V@1 MHz to 16 MHz VDD = 1.8 to 5.5 V@1 MHz to 8 MHz VDD = 1.6 to 5.5 V@1 MHz to 4 MHz
R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.7
Power Supply Rise Time
(TA = -40 to +85 C, VSS = EVSS0 = EVSS1 = 0 V)
Parameter VDD rise inclination TPUP Conditions MIN. TYP. MAX. 53.0 Unit V/ms
2.8
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = -40 to +85 C)
Parameter Data retention supply voltage
Note
Symbol VDDDR
Conditions
MIN. 1.5 Note
TYP.
MAX. 5.5
Unit V
The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.
STOP mode Data retention mode
Operation mode
VDD VDDDR STOP instruction execution Standby release signal (interrupt request)
2.9
Flash Memory Programming Characteristics
(TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter CPU/peripheral hardware clock frequency Number of code flash rewrites Cerwr 1 erase + 1 write after the erase is regarded as 1 rewrite. Number of data flash rewrites The retaining years are until next rewrite after the rewrite. Retained for 20 years (Self/serial programming) Note Retained for 1 years (Self/serial programming) (Self/serial programming) Note
Note Remark
Note
Symbol fCLK 1.8 V VDD 5.5 V
Conditions
MIN. 1
TYP.
MAX. 32
Unit MHz Times
1,000
1,000,000
Retained for 5 years
100,000
When using flash memory programmer and Renesas Electronics self programming library. When updating data multiple times, use the flash memory as one for updating data.
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Caution
2. ELECTRICAL SPECIFICATIONS
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.10
Timing Specs for Switching Modes
Parameter Symbol tSUINIT tSU tHD Conditions POR and LVD reset must end before the pin reset ends. POR and LVD reset must end before the pin reset ends. POR and LVD reset must end before the pin reset ends. 1 ms 10
s
MIN.
TYP.
MAX. 100
Unit ms
How long from when a pin reset ends until the initial communication settings are specified How long from when the TOOL0 pin is placed at the low level until a pin reset ends How long the TOOL0 pin must be kept at the low level after a reset ends
RESET
tHD+ software processing time TOOL0
tSU
The low level is input to the TOOL0 pin.
tSUINIT
The pins reset ends (POR and LVD reset must end before the pin reset ends.). The TOOL0 pin is set to the high level. Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external and internal resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end
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REVISION HISTORY
RL78/G14 Datasheet
Description
Rev. 0.01 0.02
Date Feb 10, 2011 May 01, 2011
Page — 1 to 2 3 4 to 13 14 15 to 17 23 to 26 First Edition issued 1.1 Features revised 1.2 Ordering Information revised
Summary
1.3 Pin Configuration (Top View) revised 1.4 Pin Identification revised 1.5.1 30-pin products to 1.5.3 36-pin products revised 1.6 Outline of Functions revised 1.1 Features revised 1. OUTLINE revised 2. ELECTRICAL SPECIFICATIONS added
0.03 1.00
Jul 28, 2011 Feb 21, 2012
1 1 to 40 41 to 97
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
C-1
NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) (Note 2) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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