RM25C64C-BTAC-B

RM25C64C 64Kbit 2.7V Minimum Non-volatile Serial Memory SPI Bus Features  Memory array: 64Kbit EEPROM-compatible serial memory  Single supply voltage: 2.7V - 3.6V  Serial peripheral interface (SPI) compatible  Supports SPI modes 0 and 3  1.6MHz maximum clock rate for normal read  5MHz maximum clock rate for fast read  Page size: 32 byte          -Byte and Page Write from 1 to 32 bytes -Byte Write within 25µs -Page Write within 1ms Self-timed erase and write cycles Page or chip erase capability 1mA read current, 1.5mA write current, 5µA power-down current 8-lead packages RoHS-compliant and halogen-free packaging Based on Adesto's proprietary CBRAM® technology Data Retention: 10 years Endurance: 25,000 Write Cycles Unlimited Read Cycles Description The Mavriq™ RM25C64C is an EEPROM-compatible, 64Kbit non-volatile serial memory utilizing Adesto's CBRAM resistive memory technology. The memory device uses a single low-voltage supply ranging from 2.7V to 3.6V. The RM25C64C is accessed through a 4-wire SPI interface consisting of a Serial Data Input (SDI), Serial Data Output (SDO), Serial Clock (SCK), and Chip Select (CS). The maximum clock (SCK) frequency in normal read mode is 1.6MHz. In fast read mode the maximum clock frequency is 5MHz. Writing into the device can be done from one to 32 bytes at a time. All writing is internally self-timed. The device also features an Erase which can be performed on 32-byte pages, or the whole chip. Writing a single byte to the Mavriq RM25C32C device consumes only 10% of the energy required by a Byte Write operation of EEPROM devices of similar size. DS-RM25C64C–064E–9/2015 Block Diagram VCC Status Registers & Control Logic I/O Buffers and Data Latches Page Buffer SCK SDI SDO CS Y-Decoder SPI Interface WP HOLD GND Address Latch & Counter X-Decoder 1. 64Kb CBRAM Memory Figure 1-1. Block Diagram RM25C64C DS-RM25C64C–064E–9/2015 2 2. Absolute Maximum Ratings Table 2-1. Absolute Maximum Ratings(1) Parameter Specification Operating ambient temp range 0°C to +70° C Storage temperature range Input supply voltage, VCC to GND Voltage on any pin with respect to GND -20°C to +100°C - 0.3V to 3.6V -0.3V to (VCC + 0.3) ESD protection on all pins (Human Body Model) >2kV Junction temperature 85°C DC output current 5mA 1. CAUTION: Stresses greater than Absolute Maximum Ratings may cause permanent damage to the devices. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in other sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may reduce device reliability RM25C64C DS-RM25C64C–064E–9/2015 3 3. Electrical Characteristics 3.1 DC Operating Characteristics  Applicable over recommended operating range: TA = 0°C to +70° C, VCC = 2.7V to 3.6V Symbol Parameter Condition VCC Supply Range VVCCI VCC Inhibit  ICC1  Supply current, Fast Read VCC= 3.6V SCK at 5 MHz VCC= 3.6V SCK at 1.6 MHz ICC2  Supply Current, Read Operation ICC3 Supply Current, Program or Erase ICC4 Min Typ Max Units 3.6 V 2.4 V 1.2 3 mA 1 2 mA VCC= 3.6V SCK at 5 MHz 1.5 3 mA Supply Current, Standby VCC= 3.6V CS = VCC 100 200 µA ICC5 Supply Current, Power Down VCC= 3.6V Power Down 5 20 µA IIL Input Leakage SCK, SDI, CS, HOLD, WP VIN=0V to VCC 1 µA ILO Output Leakage SDO , CS = VCC  VIN=0V to VCC 1 µA VIL Input Low Voltage SCK, SDI, CS, HOLD, WP -0.3 VCC x 0.3 V VIH Input High Voltage SCK, SDI, CS, HOLD, WP VCC x 0.7 VCC + 0.3 V VOL Output Low Voltage IOL = 3.0mA 0.4 V VOH Output High Voltage IOH = -100µA 2.7 SDO = Open, Read SDO = Open, Read VCC - 0.2 V          RM25C64C DS-RM25C64C–064E–9/2015 4 3.2 AC Operating Characteristics Applicable over recommended operating range: TA = 0°C to +70° C, VCC = 2.7V to 3.6V Symbol Parameter fSCKF SCK Clock Frequency for Fast Read Mode fSCK SCK Clock Frequency for Normal Read Mode tRI Min Typ Max Units 0 5 MHz 0 1.6 MHz SCK Input Rise Time 1 µs tFL SCK Input Fall Time 1 µs tSCKH SCK High Time 7.5 ns tSCKL SCK Low Time 7.5 ns tCS CS High Time 100 ns tCSS CS Setup Time 10 ns tCSH CS Hold Time 10 ns tDS Data In Setup Time 4 ns tDH Data In Hold Time 4 ns tHS HOLD Setup Time 30 ns tHD HOLD Hold Time 30 ns tOV Output Valid tOH Output Hold Time Normal Mode 0 tLZ HOLD to output Low Z 0 tHZ 6.5 ns ns 200 ns HOLD to output High Z 200 ns tDIS Output Disable Time 100 ns tPW Page Write Cycle Time 1 3 ms tBP Byte Write Cycle Time 25 100 µs tPUD Vcc Power-up Delay(1) 75 µs tRPD Return from Power-Down Time CIN SCK, SDI, CS, HOLD, WP VIN=0V 6 pf COUT SDO VIN=0V 8 pf 50 µs 25000(2) Write Cycles Unlimited(3) Read Cycles 10 Years Endurance Retention 70C Notes: 1. VCC must be within operating range. 2. Adesto memory products based on CBRAM technology are “Direct‐Write” memories. Endurance cycle calculations follow  JEDEC specification JESD22‐A117B. 3. Subject to expected 10‐year data retention specification. RM25C64C DS-RM25C64C–064E–9/2015 5 3.3 AC Test Conditions Timing Measurement Reference Level AC Waveform VLO = 0.2V VHI = 3.4V Input 0.5 Vcc 0.5 Vcc Output CL = 30pF (for 1.6MHz SCK) CL = 10pF (for 5MHz SCK) 4. Timing Diagrams Figure 4-1. Synchronous Data Timing with HOLD high CS VIH tCS VIL tCSS t CSH VIH SCK tSCKH tDS SDI tSCKL VIL t DH VIH VALID IN VIL tOV VIH SDO tOH HI-Z tDIS HI-Z VIL Figure 4-2. Hold Timing CS t HD t HD SCK t HS t HS HOLD t HZ SDO t LZ RM25C64C DS-RM25C64C–064E–9/2015 6 Figure 4-3. Power-up Timing VCC VCCmax Program, Read, Erase and Write Commands Rejected VCCmin Device Fully Accessible Device in Reset VVCCI tPUD TIME 5. Pin Descriptions and Pin-out Table 5-1. Mnemonic Pin Descriptions Pin Number Pin Name Description CS 1 Chip Select Making CS low activates the internal circuitry for device operation. Making CS high deselects the device and switches into standby mode to reduce power. When the device is not selected (CS high), data is not accepted via the Serial Data Input pin (SDI) and the Serial Data Output pin (SDO) remains in a high-impedance state. SDO 2 Serial Data Out Sends read data or status on the falling edge of SCK. WP 3 Write Protect N/A GND 4 Ground SDI 5 Serial Data In Device data input; accepts commands, addresses, and data on the rising edge of SCK. SCK 6 Serial Clock Provides timing for the SPI interface. SPI commands, addresses, and data are latched on the rising edge on the Serial Clock signal, and output data is shifted out on the falling edge of the Serial Clock signal. HOLD 7 Hold When pulled low, serial communication with the master device is paused, without resetting the serial sequence. Vcc 8 Power Power supply pin. RM25C64C DS-RM25C64C–064E–9/2015 7 Figure 5-1. Pin Out CS 1 8 VCC SDO 2 7 HOLD WP 3 6 SCK GND 4 5 SDI SPI 6. SPI Modes Description Multiple Adesto SPI devices can be connected onto a Serial Peripheral Interface (SPI) serial bus controlled by an SPI master, such as a microcontroller, as shown in Figure 6-1, Figure 6-1. Connection Diagram, SPI Master and SPI Slaves SDO SPI Interface with Mode 0 or Mode 3 SPI Master (i.e. Microcontroller) SDI SCK SCK SDO SDI SPI Memory Device CS3 CS2 SCK SDO SDI SPI Memory Device SCK SDO SDI SPI Memory Device CS1 CS CS CS The Adesto RM25C64C supports two SPI modes: Mode 0 (0, 0) and Mode 3 (1, 1). The difference between these two modes is the clock polarity when the SPI master is in standby mode (CS high). In Mode 0, the Serial Clock (SCK) stays at 0 during standby. In Mode 3, the SCK stays at 1 during standby. An example sequence for the two SPI modes is shown in Figure 6-2. For both modes, input data (on SDI) is latched in on the rising edge of Serial Clock (SCK), and output data (SDO) is available beginning with the falling edge of Serial Clock (SCK). RM25C64C DS-RM25C64C–064E–9/2015 8 Figure 6-2. SPI Modes CS Mode 0 (0,0) SCK Mode 3 (1,1) SCK SDI MSB MSB SDO 7. Registers 7.1 Instruction Register The Adesto RM25C64C uses a single 8-bit instruction register. The instructions and their operation codes are listed in Table 7.1. All instructions, addresses, and data are transferred with the MSB first, and begin transferring with the first low-to-high SCK transition after the CS pin goes low. Table 7-1. Instruction Device Operating Instructions Description Operation  Code Address Cycles Dummy Cycles Data Cycles WR Write 1 to 32 bytes 02H 2 0 1-32 READ Read data from memory array 03H 2 0 1 to ∞ FREAD Fast Read data from data memory 0BH 2 1 1 to ∞ WRDI Write Disable 04H 0 0 0 RDSR Read Status Register 05H 0 0 1 to ∞ WREN Write Enable 06H 0 0 0 PERS Page Erase 32 bytes 42H 2 0 0 CERS Chip Erase 60H 0 0 0 C7H 0 0 0 PD Power Down B9H 0 0 0 RES Resume from Power Down ABH 0 0 0 RM25C64C DS-RM25C64C–064E–9/2015 9 7.2 Status Register The Adesto RM25C64C uses a single 8-bit Status Register. The Write In Progress (WIP) and Write Enable (WEL) status of the device can be determined by reading this register. The Status Register format is shown in Table 7-2 The Status Register bit definitions are shown in Table 7-3. Table 7-2. Status Register Format Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 WEL WIP Table 7-3. Bit Status Register Bit Definitions Name Description R/W Non-Volatile Bit R No R/W No Reserved. Read as “0” N/A No 0 WIP Write In Progress “0” indicates the device is ready “1” indicates that the program/erase cycle is in progress and the device is busy 1 WEL Write Enable Latch “0” Indicates that the device is disabled “1” indicates that the device is enabled 2 N/A 3 N/A 4 N/A 5 N/A Reserved. Read as “0” N/A No 6 N/A Reserved. Read as “0” N/A No 7 N/A Reserved. Read as “0” N/A No 8. Command Descriptions 8.1 WREN (Write Enable):  The device powers up with the Write Enable Latch set to zero. This means that no write or erase instructions can be executed until the Write Enable Latch is set using the Write Enable (WREN) instruction. The Write Enable Latch is also set to zero automatically after any non-read instruction. Therefore, all page programming instructions and erase instructions must be preceded by a Write Enable (WREN) instruction. The sequence for the Write Enable instruction is shown in Figure 8-1. RM25C64C DS-RM25C64C–064E–9/2015 10 Figure 8-1. WREN Sequence CS 0 1 2 3 4 5 6 7 0 0 0 0 0 1 1 0 SCK SDI HI-Z SDO The following table is a list of actions that will automatically set the Write Enable Latch to zero when successfully executed. If an instruction is not successfully executed, for example if the CS pin is brought high before an integer multiple of 8 bits is clocked, the Write Enable Latch will not be reset. Table 8-1. Write Enable Latch to Zero Instruction/Operation Power-Up WRDI (Write Disable) WR (Write) PERS (Page Erase) CERS (Chip Erase) PD (Power Down) 8.2 WRDI (Write Disable): To protect the device against inadvertent writes, the Write Disable instruction disables all write modes. Since the Write Enable Latch is automatically reset after each successful write instruction, it is not necessary to issue a WRDI instruction following a write instruction. The WRDI instruction is independent of the status of the WP pin. The WRDI sequence is shown in Figure 8-2. Figure 8-2. WRDI Sequence CS 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0 SCK SDI SDO HI-Z RM25C64C DS-RM25C64C–064E–9/2015 11 8.3 RDSR (Read Status Register): The Read Status Register instruction provides access to the Status Register and indication of write protection status of the memory. Caution: The Write In Progress (WIP) and Write Enable Latch (WEL) indicate the status of the device. The RDSR sequence is shown in Figure 8-3. (Note: The Write Status Register command is not available in this device, and should not be used. Use of this command may cause unexpected behavior.) CS 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 1 8 9 10 11 12 13 5 4 3 2 14 15 1 0 SCK SDI HI-Z SDO 7 6 WEL WIP Figure 8-3. RDSR Sequence 8.4 READ (Read Data): Reading the Adesto RM25C64C via the Serial Data Output (SDO) pin requires the following sequence: First the CS line is pulled low to select the device; then the READ op-code is transmitted via the SDI line, followed by the address to be read (A15-A0). Although not all 16 address bits are used, a full 2 bytes of address must be transmitted to the device. For the 32Kbit device, only address A0 to A11 are used; the rest are don't cares and must be set to "0". For the 64Kbit device, only address A0 to A12 are used; the rest are don't cares and must be set to "0". Once the read instruction and address have been sent, any further data on the SDI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SDO line. If only one byte is to be read, the CS line should be driven high after the byte of data comes out. This completes the reading of one byte of data. The READ sequence can be automatically continued by keeping the CS low. At the end of the first data byte the byte address is internally incremented and the next higher address data byte will be shifted out. When the highest address is reached, the address counter will roll over to the lowest address (00000), thus allowing the entire memory to be read in one continuous read cycle. The READ sequence is shown in Figure 8-4. Figure 8-4. Single Byte READ Sequence CS 0 1 2 3 4 5 0 0 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK INSTRUCTION SDI 0 0 0 0 2 BYTE ADDRESS 1 1 15 14 13 3 2 1 0 DATA OUT HI-Z 7 6 5 4 3 2 1 0 RM25C64C DS-RM25C64C–064E–9/2015 12 8.5 FREAD (Fast Read Data): The Adesto RM25C64C also includes the Fast Read Data command, which facilitates reading memory data at higher clock rates, up to 5MHz. After the CS line is pulled low to select the device, the FREAD op-code is transmitted via the SDI line. This is followed by the 2-byte address to be read (A15-A0) and then a 1-byte dummy. For the 64Kbit device, only address A0 to A12 are used; the rest are don't cares and must be set to "0". The next 8 bits transmitted on the SDI are dummy bits. The data (D7-D0) at the specified address is then shifted out onto the SDO line. If only one byte is to be read, the CS line should be driven high after the data comes out. This completes the reading of one byte of data. The FREAD sequence can be automatically continued by keeping the CS low. At the end of the first data byte, the byte address is internally incremented and the next higher address data byte is then shifted out. When the highest address is reached, the address counter rolls over to the lowest address (00000), allowing the entire memory to be read in one continuous read cycle. The FREAD sequence is shown in Figure 8-5. Figure 8-5. Two Byte FREAD Sequence CS 0 1 2 3 4 5 1 0 6 7 8 9 10 20 21 22 23 SCK INSTRUCTION 0 SDI 0 0 0 2 BYTE ADDRESS 1 1 30 31 32 1 0 15 14 13 3 2 1 36 37 38 0 HI-Z SDO CS 24 25 26 7 6 27 28 29 33 34 35 39 40 41 0 7 42 43 44 45 46 47 2 1 SCK DUMMY BYTE SDI 5 4 3 2 DATA BYTE 1 OUT HI-Z SDO 8.6 7 6 5 4 3 2 DATA BYTE 2 OUT 1 6 5 4 3 0 WRITE (WR): Product Density Page Size (byte) RM25C64C 64Kbit 32 The Write (WR) instruction allows bytes to be written to the memory. But first, the device must be write-enabled via the WREN instruction. The CS pin must be brought high after completion of the WREN instruction; then the CS pin can be brought back low to start the WR instruction. The CS pin going high at the end of the WR input sequence initiates the internal write cycle. During the internal write cycle, all commands except the RDSR instruction are ignored. RM25C64C DS-RM25C64C–064E–9/2015 13 A WR instruction requires the following sequence. After the CS line is pulled low to select the device, the WR op-code is transmitted via the SDI line, followed by the byte address (A15-A0) and the data (D7-D0) to be written. The internal write cycle sequence will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit. The Write In Progress status of the device can be determined by initiating a Read Status Register (RDSR) instruction and monitoring the WIP bit. If the WIP bit (Bit 0) is a “1”, the write cycle is still in progress. If the WIP bit is “0”, the write cycle has ended. Only the RDSR instruction is enabled during the write cycle. The sequence of a one-byte WR is shown in Figure 8-6. Figure 8-6. One Byte Write Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK INSTRUCTION SDI SDO 0 0 0 0 0 0 2 BYTE ADDRESS 1 0 15 14 13 3 2 1 DATA IN 0 7 6 5 4 3 2 1 0 HI-Z The Adesto RM25C64C is capable of a 32-byte write operation. For the RM25C64C: After each byte of data is received, the five low-order address bits (A4-A0) are internally incremented by one; the high-order bits of the address will remain constant. All transmitted data that goes beyond the end of the current page are written from the start address of the same page (from the address whose 5 least significant bits [A4-A0] are all zero). If more than 32 bytes are sent to the device, previously latched data are discarded and the last 32 data bytes are ensured to be written correctly within the same page. If less than 32 data bytes are sent to the device, they are correctly written at the requested addresses without having any effects on the other bytes of the same page. The Adesto R25C64C is automatically returned to the write disable state at the completion of a program cycle. The sequence for a 32 byte WR is shown in Figure 8-7. Note that the Multi-Byte Write operation is internally executed by sequentially writing the words in the Page Buffer. NOTE: If the device is not write enabled (WREN) previous to the Write instruction, the device will ignore the write instruction and return to the standby state when CS is brought high. A new CS falling edge is required to reinitiate the serial communication.   RM25C64C DS-RM25C64C–064E–9/2015 14 Figure 8-7. WRITE Sequence CS 0 1 0 0 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 0 7 6 26 27 28 29 30 31 2 1 0 SCK INSTRUCTION SDI 0 0 0 2 BYTE ADDRESS 0 1 0 15 14 13 3 2 DATA BYTE 1 1 5 4 3 HI-Z SDO CS 32 33 7 6 34 35 36 37 38 39 40 41 2 1 0 7 6 42 43 44 45 46 47 2 1 0 SCK DATA BYTE 2 SDI 4 3 DATA BYTE 3 5 4 3 DATA BYTE N (N= 32) 7 6 5 4 3 2 1 0 HI-Z SDO 8.7 5 PER (Page Erase 32 bytes): Page Erase sets all bits inside the addressed 32-byte page to a 1. A Write Enable (WREN) instruction is required prior to a Page Erase. After the WREN instruction is shifted in, the CS pin must be brought high to set the Write Enable Latch. The Page Erase sequence is initiated by bringing the CS pin low; this is followed by the instruction code, then 2 address bytes. Any address inside the page to be erased is valid. This means the bottom five/six bits (A4-A0)/(A5-A0) of the address are ignored. Once the address is shifted in, the CS pin is brought high, which initiates the self-timed Page Erase function. The WIP bit in the Status Register can be read, using the RDSR instruction, to determine when the Page Erase cycle is complete. The sequence for the PER is shown in Figure 8-8. Figure 8-8. PERS Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 1 0 SCK INSTRUCTION SDI SDO 0 1 0 0 2 BYTE ADDRESS 0 0 1 0 15 14 13 3 2 HI-Z RM25C64C DS-RM25C64C–064E–9/2015 15 8.8 CER (Chip Erase): Chip Erase sets all bits inside the device to a 1. A Write Enable (WREN) instruction is required prior to a Chip Erase. After the WREN instruction is shifted in, the CS pin must be brought high to set the Write Enable Latch. The Chip Erase sequence is initiated by bringing the CS pin low; this is followed by the instruction code. There are two different instruction codes for CER, 60h and C7h. Either instruction code will initiate the Chip Erase sequence. No address bytes are needed. Once the instruction code is shifted in, the CS pin is brought high, which initiates the selftimed Chip Erase function. The WIP bit in the Status Register can be read, using the RDSR instruction, to determine when the Chip Erase cycle is complete. The sequence for the 60h CER instruction is shown in Figure 8-9. The sequence for the C7h CER instruction is shown in Figure 8-10. Figure 8-9. CERS Sequence (60h) CS 0 1 2 3 4 5 6 7 0 1 1 0 0 0 0 0 SCK SDI HI-Z SDO Figure 8-10. CERS Sequence (C7h) CS 0 1 2 3 4 5 6 7 1 1 0 0 0 1 1 1 SCK SDI SDO 8.9 HI-Z PD (Power Down): Power Down mode allows the user to reduce the power of the device to its lowest power consumption state. All instructions given during the Power Down mode are ignored except the Resume from Power down (RES) instruction. Therefore this mode can be used as an additional software write protection feature. The Power Down sequence is initiated by bringing the CS pin low; this is followed by the instruction code. Once the instruction code is shifted in the CS pin is brought high, which initiates the PD mode. The sequence for PD is shown in Figure 8-11. RM25C64C DS-RM25C64C–064E–9/2015 16 Figure 8-11. PD Sequence CS 0 1 2 3 4 5 6 7 1 0 1 1 1 0 0 1 SCK SDI HI-Z SDO 8.10 RES (Resume from Power Down): The Resume from Power Down mode is the only command that will wake the device up from the Power Down mode. All other commands are ignored. In the simple instruction command, after the CS pin is brought low, the RES instruction is shifted in. At the end of the instruction, the CS pin is brought back high. The rising edge of the SCK clock number 7 (8th rising edge) initiates the internal RES instruction. The device becomes available for Read and Write instructions 75μS after the 8th rising edge of the SCK (tPUD, see AC Characteristics). The sequence for simple RES instruction is shown in Figure 8-12. Figure 8-12. Simple RES Sequence CS 0 1 2 3 4 5 1 0 6 7 SCK INSTRUCTION SDI SDO 1 0 1 0 1 1 HI-Z tRPD RM25C64C DS-RM25C64C–064E–9/2015 17 9. Package Information 9.1 SN (JEDEC SOIC) C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. NOTE 1.27 BSC L 0.40 – 1.27 Ø 0° – 8° 8/20/14 TITLE Package Drawing Contact: contact@adestotech.com 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) GPC DRAWING NO. SWB 8S1 RM25C64C DS-RM25C64C–064E–9/2015 REV. G 18 9.2 TA-TSSOP C 1 Pin 1 indicator this corner E1 E L1 H N L Top View End View A b A1 e A2 MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 D 2.90 3.00 3.10 2, 5 4.40 4.50 3, 5 – 0.30 4 SYMBOL D Side View Notes: COMMON DIMENSIONS (Unit of Measure = mm) 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. E 6.40 BSC E1 4.30 b 0.19 e L 0.65 BSC 0.45 L1 C NOTE 0.60 0.75 1.00 REF 0.09 - 0.20 12/8/11 ® Package Drawing Contact: contact@adestotech.com TITLE TA, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) GPC TNR DRAWING NO. 8X REV. E RM25C64C DS-RM25C64C–064E–9/2015 19 10. Ordering Information 10.1 Ordering Detail RM25C64C-BSNC-T Device Type Shipping Carrier Option RM25C = SPI serial access EEPROM B = Tube T = Tape & Reel Density Grade & Temperature 64 = 64Kbit C = Green, Commercial temperature (0-70°C) Package Option Device/Die Revision SN = 8 lead 0.150” SOIC, Narrow TA = 8 lead TSSOP C Operating Voltage B = 2.7V to 3.6V  10.2 Ordering Codes Ordering Code RM25C64C-BSNC-B RM25C64C-BSNC-T RM25C64C-BTAC-B RM25C64C-BTAC-T Package Density Operating Voltage fSCKF SN 64Kbit 2.7V to 3.6V 5MHz TA 64Kbit 2.7V to 3.6V 5MHz Device Grade Ship Carrier Qty. Carrier Commercial Tube 100 (0C to 70C) Reel 4000 Commercial Tube 100 (0C to 70C) Reel 6000 Package Type SN 8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) TA 8-lead 3 x 4.4 mm, Thin Shrink Small Outline Package RM25C64C DS-RM25C64C–064E–9/2015 20 11. Revision History Doc. Rev. Date Comments RM25C64C-064A 10/2014 Initial document release. RM25C64C-064B 1/2015 Updated Power Down Current. RM25C64C-064C 3/2015 Updated formatting and syntax. RM25C64C-064D 4/2015 Updated Endurance specifications for Read and Write cycles. RM25C64C-064E 9/2015 Removed Preliminary document status (document complete). RM25C64C DS-RM25C64C–064E–9/2015 21 Corporate Office California | USA Adesto Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: (+1) 408.400.0578 Email: contact@adestotech.com © 2015 Adesto Technologies. All rights reserved. / Rev.: DS-RM25C64C–064E–9/2015 Adesto®, the Adesto logo, CBRAM®, MavriqTM and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective owners. Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems. For Release Only Under Non-Disclosure Agreement (NDA)