RMLV0408EGSB-4S2#AA1

RMLV0416E Series 4Mb Advanced LPSRAM (256-kword × 16-bit) R10DS0205EJ0300 Rev.3.00 2021.8.18 Description The RMLV0416E Series is a family of 4-Mbit static RAMs organized 262,144-word × 16-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV0416E Series has realized higher density, higher performance and low power consumption. The RMLV0416E Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 44-pin TSOP (II) or 48-ball fine pitch ball grid array. Features • Single 3V supply: 2.7V to 3.6V • Access time: 45ns (max.) • Current consumption: ── Standby: 0.3µA (typ.) • Equal access and cycle times • Common data input and output ── Three state output • Directly TTL compatible ── All inputs and outputs • Battery backup operation Orderable part number information Orderable part number Access time Temperature range Package Tray RMLV0416EGSB-4S2#AA* 400-mil 44pin plastic TSOP (II) Embossed tape RMLV0416EGSB-4S2#HA* 45 ns -40 ~ +85°C RMLV0416EGBG-4S2#AC* RMLV0416EGBG-4S2#KC* Note 1. Shipping container 48-ball FBGA with 0.75mm ball pitch Tray Embossed tape * = Revision code for Assembly site change, etc. (* = 0, 1, etc.) R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 1 of 13 RMLV0416E Series Pin Arrangement 44pin TSOP (II) 48-ball FBGA A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# CS1# 6 39 LB# I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 Vcc 11 34 Vss Vss 12 33 Vcc I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE# 17 28 CS2 A17 18 27 A8 A16 19 26 A9 A15 20 25 A10 A14 21 24 A11 A13 22 23 A12 1 2 3 4 5 A LB# OE# A0 A1 A2 CS2 B I/O8 UB# A3 A4 CS1# I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D Vss I/O11 A17 A7 I/O3 Vcc E Vcc I/O12 NC A16 I/O4 Vss F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE# I/O7 H NC A8 A9 A10 A11 NC (Top view) 6 (Top view) Pin Description Pin name VCC VSS A0 to A17 I/O0 to I/O15 CS1# CS2 OE# WE# LB# UB# NC Function Power supply Ground Address input Data input/output Chip select 1 Chip select 2 Output enable Write enable Lower byte select Upper byte select No connection R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 2 of 13 RMLV0416E Series Block Diagram VCC A1 A2 A3 A4 A6 A8 A13 A14 A15 A16 A17 VSS Row Decoder I/O0 ・ ・ ・ ・ ・ Memory Matrix ・ ・ Column I/O 2,048 x 2,048 ・ ・ Column Decoder Input Data Control I/O15 A0 A5 A7 A9 A10 A11 A12 ・ ・ CS2 CS1# LB# UB# WE# Control logic OE# Operation Table CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation H X X X X X High-Z High-Z Standby X L X X X X High-Z High-Z Standby X X X X H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L X L L Din Din Write L H L X H L Din High-Z Lower byte write L H L X L H High-Z Din Upper byte write L H H H X X High-Z High-Z Output disable Note 2. H: VIH L:VIL X: VIH or VIL R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 3 of 13 RMLV0416E Series Absolute Maximum Ratings Parameter Symbol Power supply voltage relative to VSS VCC Terminal voltage on any pin relative to VSS VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 3. -3.0V for pulse ≤ 30ns (full width at half maximum) 4. Maximum voltage is +4.6V. Value -0.5 to +4.6 -0.5*3 to VCC+0.3*4 0.7 -40 to +85 -65 to +150 -40 to +85 unit V V W °C °C °C DC Operating Conditions Parameter Symbol VCC VSS Input high voltage VIH Input low voltage VIL Ambient temperature range Ta Note 5. -3.0V for pulse ≤ 30ns (full width at half maximum) Supply voltage Min. 2.7 0 2.2 -0.3 -40 Typ. 3.0 0 ─ ─ ─ Max. 3.6 0 VCC+0.3 0.6 +85 Unit V V V V °C Note 5 DC Characteristics Parameter Input leakage current Output leakage current Operating current Average operating current Standby current Standby current Symbol | ILI | Min. ─ Typ. ─ Max. 1 Unit µA | ILO | ─ ─ 1 µA ICC ─ ─ 10 mA ─ ─ 20 mA ─ ─ 25 mA ICC2 ─ ─ 2.5 mA ISB ─ 0.1*6 0.3 mA ─ 0.3 2 µA ~+25°C ─ ─ 3 µA ~+40°C ─ ─ 5 µA ~+70°C ─ ─ 7 µA ~+85°C ICC1 ISB1 *6 Test conditions Vin = VSS to VCC CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC CS1# = VIL, CS2 = VIH, Others = VIH/VIL, II/O = 0mA Cycle = 55ns, duty =100%, II/O = 0mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL Cycle = 45ns, duty =100%, II/O = 0mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL Cycle =1µs, duty =100%, II/O = 0mA, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V CS2 = VIL, Others = VSS to VCC Vin = VSS to VCC, (1) CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V Output high voltage VOH 2.4 ─ ─ V IOH = -1mA VOH2 VCC-0.2 ─ ─ V IOH = -0.1mA Output low voltage VOL ─ ─ 0.4 V IOL = 2mA VOL2 ─ ─ 0.2 V IOL = 0.1mA Note 6. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C) Parameter Symbol Min. Input capacitance C in ─ Input / output capacitance C I/O ─ Note 7. This parameter is sampled and not 100% tested. R10DS0205EJ0300 Rev.3.00 2021.8.18 Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 7 7 Page 4 of 13 RMLV0416E Series AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C) • • • • 1.4V Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.4V Output load: See figures (Including scope and jig) RL = 500 ohm I/O CL = 30 pF Read Cycle Parameter Read cycle time Address access time Symbol Min. tRC tAA 45 ─ ─ ─ ─ 10 ─ 10 10 5 5 0 0 0 0 Max. Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 tACS1 45 Chip select access time tACS2 45 Output enable to output valid tOE 22 Output hold from address change tOH ─ LB#, UB# access time tBA 45 tCLZ1 ─ 8,9 Chip select to output in low-Z tCLZ2 ─ 8,9 LB#, UB# enable to low-Z tBLZ ─ 8,9 Output enable to output in low-Z tOLZ ─ 8,9 tCHZ1 18 8,9,10 Chip deselect to output in high-Z tCHZ2 18 8,9,10 LB#, UB# disable to high-Z tBHZ 18 8,9,10 Output disable to output in high-Z tOHZ 18 8,9,10 Note 8. This parameter is sampled and not 100% tested. 9. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. 10. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 5 of 13 RMLV0416E Series Write Cycle Parameter Symbol Min. Max. Unit Note Write cycle time tWC 45 ─ ns Address valid to write end tAW 35 ─ ns Chip select to write end tCW 35 ─ ns Write pulse width tWP 35 ─ ns 11 LB#,UB# valid to write end tBW 35 ─ ns Address setup time to write start tAS 0 ─ ns Write recovery time from write end tWR 0 ─ ns Data to write time overlap tDW 25 ─ ns Data hold from write end tDH 0 ─ ns Output enable from write end tOW 5 ─ ns 12 Output disable to output in high-Z tOHZ 0 18 ns 12,13 Write to output in high-Z tWHZ 0 18 ns 12,13 Note 11. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 12. This parameter is sampled and not 100% tested. 13. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 6 of 13 RMLV0416E Series Timing Waveforms Read Cycle tRC A0~17 Valid address tAA tACS1 CS1# tCHZ1 *14,15,16 tCLZ1 *15,16 CS2 tACS2 tCLZ2 *15,16 tCHZ2 *14,15,16 tBA LB#,UB# tBLZ *15,16 WE# tBHZ *14,15,16 VIH WE# = “H” level tOHZ *14,15,16 tOE OE# tOLZ I/O0~15 High impedance tOH *15,16 Valid Data Note 14. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 15. This parameter is sampled and not 100% tested 16. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 7 of 13 RMLV0416E Series Write Cycle (1) (WE# CLOCK, OE#=”H” while writing) tWC Valid address A0~17 tCW CS1# CS2 tCW tBW LB#,UB# tAW WE# tAS OE# tWHZ *18,19 tOHZ *18,19 I/O0~15 tWP tWR *17 *20 tDW tDH Valid Data Note 17. tWP is the minimum time to perform a write. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 18. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 19. This parameter is sampled and not 100% tested 20. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins. R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 8 of 13 RMLV0416E Series Write Cycle (2) (WE# CLOCK, OE# Low Fixed) tWC Valid address A0~17 tCW CS1# CS2 tCW tBW LB#,UB# tAW WE# OE# OE# = “L” level tWP tWR *21 tAS VIL tWHZ *22,23 I/O0~15 *24 tOW Valid Data tDW *24 tDH Note 21. tWP is the minimum time to perform a write. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 22. tWHZ is defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 23. This parameter is sampled and not 100% tested. 24. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins. R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 9 of 13 RMLV0416E Series Write Cycle (3) (CS1#, CS2 CLOCK) tWC Valid address A0~17 tAW tAS tCW tAS tCW tWR CS1# CS2 tBW LB#,UB# tWP *25 WE# OE# OE# = “H” level VIH tDW I/O0~15 tDH Valid Valid Data Data Note 25. tWP is the minimum time to perform a write. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 10 of 13 RMLV0416E Series Write Cycle (4) (LB#, UB# CLOCK) tWC Valid address A0~17 tAW tCW CS1# tCW CS2 tAS tWR tBW LB#,UB# tWP *26 WE# OE# OE# = “H” level VIH tDW I/O0~15 tDH Valid Data Note 26. tWP is the minimum time to perform a write. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 11 of 13 RMLV0416E Series Low VCC Data Retention Characteristics Parameter VCC for data retention Data retention current Symbol VDR Min. Typ. Max. Unit Test conditions*28 1.5 ─ ─ V Vin ≥ 0V, (1) CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V ─ 0.3*27 2 µA ~+25°C ─ ─ 3 µA ~+40°C ─ ─ 5 µA ~+70°C ─ ─ 7 µA ~+85°C ICCDR VCC = 3.0V, Vin ≥ 0V, (1) CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V Chip deselect time to data retention tCDR 0 ─ ─ ns See retention waveform. Operation recovery time tR 5 ─ ─ ms Note 27. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 28. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB# buffer, UB# buffer and I/O buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V. The other inputs levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high-impedance state. R10DS0205EJ0300 Rev.3.00 2021.8.18 Page 12 of 13 RMLV0416E Series Low Vcc Data Retention Timing Waveforms (CS1# controlled) CS1# Controlled VCC tCDR 2.7V 2.7V tR VDR 2.2V 2.2V CS1# ≥ VCC - 0.2V CS1# Low Vcc Data Retention Timing Waveforms (CS2 controlled) CS2 Controlled VCC tCDR CS2 2.7V 2.7V tR VDR 0.6V 0.6V CS2 ≤ 0.2V Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled) LB#,UB# Controlled VCC tCDR 2.2V LB#,UB# R10DS0205EJ0300 Rev.3.00 2021.8.18 2.7V 2.7V VDR tR 2.2V LB#,UB# ≥ VCC - 0.2V Page 13 of 13 Revision History RMLV0416E Series Data Sheet Rev. 1.00 2.00 Date 2014.2.27 2016.1.12 Page ─ 1 2.01 3.00 2020.2.20 2021.8.18 Last page 1,4,12 Description Summary First edition issued Changed section from “Part Name Information” to “Orderable part number information” Updated the Notice to the latest version Changed the typical value of ISB1 and ICCDR from 0.4µA to 0.3µA. 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