RMLV0816BGSB-4S2#AA0

RMLV0816BGSB - 4S2 8Mb Advanced LPSRAM (512k word × 16bit) R10DS0231EJ0201 Rev.2.01 2020.02.20 Description The RMLV0816BGSB is a family of 8-Mbit static RAMs organized 524,288-word × 16-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV0816BGSB has realized higher density, higher performance and low power consumption. The RMLV0816BGSB offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 44pin TSOP (II). Features  Single 3V supply: 2.4V to 3.6V  Access time: ── Power supply voltage from 2.7V to 3.6V: 45ns (max.) ── Power supply voltage from 2.4V to 2.7V: 55ns (max.)  Current consumption: ── Standby: 0.45µA (typ.)  Equal access and cycle times  Common data input and output ── Three state output  Directly TTL compatible ── All inputs and outputs  Battery backup operation Part Name Information Part Name Power supply Access time 2.7V to 3.6V 45 ns 2.4V to 2.7V 55 ns RMLV0816BGSB-4S2 R10DS0231EJ0201 Rev.2.01 2020.02.20 Temperature Range Package -40 ~ +85°C 11.76mm×18.41mm 44pin plastic TSOP(II) Page 1 of 12 RMLV0816BGSB - 4S2 Pin Arrangement 44pin TSOP(II) A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# CS# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 DQ9 DQ7 16 29 DQ8 WE# 17 28 A8 A18 18 27 A9 A17 19 26 A10 A16 20 25 A11 A15 21 24 A12 A14 22 23 A13 (Top view) Pin Description Pin name Function VCC VSS A0 to A18 DQ0 to DQ15 CS# OE# WE# Ground Address input Data input/output Chip select Output enable Write enable Power supply LB# UB# Lower byte select Upper byte select R10DS0231EJ0201 Rev.2.01 2020.02.20 Page 2 of 12 RMLV0816BGSB - 4S2 Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 512k-word x16-bit DQ0 DQ1 A18 DQ BUFFER DQ7 DATA SENSE / WRITE AMPLIFIER SELECTOR DQ8 DQ9 DQ COLUMN DECODER BUFFER CLOCK DQ15 GENERATOR CS# UPPER or LB# Vcc LOWER BYTE Vss CONTROL UB# WE# OE# Operation Table CS# WE# OE# UB# LB# DQ0 to DQ7 DQ8 to DQ15 Operation H X X X X High-Z High-Z Standby X X X H H High-Z High-Z Standby L H L L L Dout Dout Read L H L H L Dout High-Z Lower byte read L H L L H High-Z Dout Upper byte read L L X L L Din Din Write L L X H L Din High-Z Lower byte write L L X L H High-Z Din Upper byte write L H H X X High-Z High-Z Output disable Note 1. H: VIH L:VIL X: VIH or VIL R10DS0231EJ0201 Rev.2.01 2020.02.20 Page 3 of 12 RMLV0816BGSB - 4S2 Absolute Maximum Ratings Parameter Symbol Power supply voltage relative to VSS VCC Terminal voltage on any pin relative to VSS VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 2. -3.0V for pulse ≤ 30ns (full width at half maximum) 3. Maximum voltage is +4.6V. Value -0.5 to +4.6 -0.5*2 to VCC+0.3*3 0.7 -40 to +85 -65 to +150 -40 to +85 unit V V W °C °C °C DC Operating Conditions Parameter Supply voltage Symbol VCC VSS Input high voltage VIH Input low voltage VIL Min. 2.4 0 Typ. 3.0 0 ─ Max. 3.6 0 VCC+0.2 Unit V V V 2.0 2.2 Test conditions Note Vcc=2.4V to 2.7V ─ VCC+0.2 V Vcc=2.7V to 3.6V -0.2 ─ 0.4 V Vcc=2.4V to 2.7V 4 -0.2 ─ 0.6 V Vcc=2.7V to 3.6V 4 Ambient temperature range Ta -40 ─ Note 4. -3.0V for pulse ≤ 30ns (full width at half maximum) +85 °C DC Characteristics Parameter Input leakage current Output leakage current Symbol | ILI | Min. ─ Typ. ─ Max. 1 Unit A | ILO | ─ ─ 1 A ─ 20*5 25 mA ─ 25*5 30 mA ICC2 ─ 1.5*5 3 mA ISB ─ ─ 0.3 mA Vin = VSS to VCC CS# = VIH or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Cycle = 55ns, duty =100%, II/O = 0mA, CS# = VIL, Others = VIH/VIL Cycle = 45ns, duty =100%, II/O = 0mA, CS# = VIL, Others = VIH/VIL Cycle =1s, duty =100%, II/O = 0mA CS# ≤ 0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V CS# = VIH, Others = VSS to VCC ─ 0.45*5 2 A ~+25°C ─ 0.6*6 4 A ~+40°C ─ ─ 7 A ~+70°C ─ ─ 10 A ~+85°C Average operating current ICC1 Standby current Standby current Test conditions ISB1 Vin = VSS to VCC, (1) CS# ≥ VCC-0.2V or (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V IOH = -1mA Vcc≥2.7V VOH2 2.0 ─ ─ V IOH = -0.1mA Output low voltage IOL = 2mA VOL ─ ─ 0.4 V Vcc≥2.7V VOL2 ─ ─ 0.4 V IOL = 0.1mA Note 5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. Note 6. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested. Output high voltage R10DS0231EJ0201 Rev.2.01 2020.02.20 VOH 2.4 ─ ─ V Page 4 of 12 RMLV0816BGSB - 4S2 Capacitance (Ta =25°C, f =1MHz) Parameter Symbol Min. Input capacitance C in ─ Input / output capacitance C I/O ─ Note 7. This parameter is sampled and not 100% tested. Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 7 7 AC Characteristics Test Conditions (Vcc = 2.4V ~ 3.6V, Ta = -40 ~ +85°C) 1.4V  Input pulse levels: VIL = 0.4V, VIH = 2.4V (Vcc=2.7V to 3.6V) VIL = 0.4V, VIH = 2.2V (Vcc=2.4V to 2.7V)  Input rise and fall time: 5ns  Input and output timing reference level: 1.4V  Output load: See figures (Including scope and jig) RL = 500 ohm DQ CL = 30 pF Read Cycle Parameter Vcc=2.7V to 3.6V Vcc=2.4V to 2.7V Unit Note Min. Max. Min. Max. Read cycle time tRC 45 ─ 55 ─ ns Address access time tAA ─ 45 ─ 55 ns Chip select access time tACS ─ 45 ─ 55 ns Output enable to output valid tOE ─ 22 ─ 30 ns Output hold from address change tOH 10 ─ 10 ─ ns LB#, UB# access time tBA ─ 45 ─ 55 ns Chip select to output in low-Z tCLZ 10 ─ 10 ─ ns 8,9 LB#, UB# enable to low-Z tBLZ 5 ─ 5 ─ ns 8,9 Output enable to output in low-Z tOLZ 5 ─ 5 ─ ns 8,9 Chip deselect to output in high-Z tCHZ 0 18 0 20 ns 8,9,10 LB#, UB# disable to high-Z tBHZ 0 18 0 20 ns 8,9,10 Output disable to output in high-Z tOHZ 0 18 0 20 ns 8,9,10 Note 8. This parameter is sampled and not 100% tested. 9. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. 10. tCHZ, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. R10DS0231EJ0201 Rev.2.01 2020.02.20 Symbol Page 5 of 12 RMLV0816BGSB - 4S2 Write Cycle Vcc=2.4V to 2.7V Unit Note Min. Max. Min. Max. Write cycle time tWC 45 ─ 55 ─ ns Address valid to write end tAW 35 ─ 50 ─ ns Chip select to write end tCW 35 ─ 50 ─ ns Write pulse width tWP 35 ─ 40 ─ ns 11 LB#,UB# valid to write end tBW 35 ─ 50 ─ ns Address setup time to write start tAS 0 ─ 0 ─ ns Write recovery time from write end tWR 0 ─ 0 ─ ns Data to write time overlap tDW 25 ─ 25 ─ ns Data hold from write end tDH 0 ─ 0 ─ ns Output enable from write end tOW 5 ─ 5 ─ ns 12 Output disable to output in high-Z tOHZ 0 18 0 20 ns 12,13 Write to output in high-Z tWHZ 0 18 0 20 ns 12,13 Note 11. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. 12. This parameter is sampled and not 100% tested. 13. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. Parameter R10DS0231EJ0201 Rev.2.01 2020.02.20 Symbol Vcc=2.7V to 3.6V Page 6 of 12 RMLV0816BGSB - 4S2 Timing Waveforms Read Cycle tRC Valid address A0~18 tAA tACS CS# tCHZ*14,15,16 tCLZ *15,16 tBA LB#,UB# tBLZ *15,16 WE# tBHZ*14,15,16 VIH WE# = “H” level tOHZ *14,15,16 tOE OE# tOLZ DQ0~15 High impedance tOH *15,16 Valid Data Note 14. tCHZ, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 15. This parameter is sampled and not 100% tested 16. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. R10DS0231EJ0201 Rev.2.01 2020.02.20 Page 7 of 12 RMLV0816BGSB - 4S2 Write Cycle (1) (WE# CLOCK, OE#=”H” while writing) tWC Valid address A0~18 tCW CS# tBW LB#,UB# tAW tWR tWP *17 WE# tAS OE# tWHZ *18,19 tOHZ *18,19 DQ0~15 *20 tDW tDH Valid Data Note 17. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. 18. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 19. This parameter is sampled and not 100% tested 20. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins. R10DS0231EJ0201 Rev.2.01 2020.02.20 Page 8 of 12 RMLV0816BGSB - 4S2 Write Cycle (2) (WE# CLOCK, OE# Low Fixed) tWC Valid address A0~18 tCW CS# tBW LB#,UB# tAW tWR tWP *21 WE# OE# OE# = “L” level tAS VIL tWHZ *22,23 DQ0~15 *24 tOW Valid Data tDW *24 tDH Note 21. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. 22. tWHZ is defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 23. This parameter is sampled and not 100% tested. 24. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins. R10DS0231EJ0201 Rev.2.01 2020.02.20 Page 9 of 12 RMLV0816BGSB - 4S2 Write Cycle (3) (CS# CLOCK) tWC Valid address A0~18 tAW tAS tWR tCW CS# tBW LB#,UB# tWP *25 WE# OE# VIH OE# = “H” level tDW DQ0~15 tDH Valid Data Note 25. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0231EJ0201 Rev.2.01 2020.02.20 Page 10 of 12 RMLV0816BGSB - 4S2 Write Cycle (4) (LB#, UB# CLOCK) tWC Valid address A0~18 tAW tCW CS# tAS tWR tBW LB#,UB# tWP *26 WE# OE# VIH OE# = “H” level tDW DQ0~15 tDH Valid Data Note 26. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0231EJ0201 Rev.2.01 2020.02.20 Page 11 of 12 RMLV0816BGSB - 4S2 Low VCC Data Retention Characteristics Parameter Symbol VCC for data retention Data retention current VDR Min. Typ. Max. Test conditions*29 Unit 1.5 ─ 3.6 V Vin ≥ 0V, (1) CS# ≥ VCC-0.2V or (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V ─ 0.45*27 2 A ~+25°C ─ 0.6*28 4 A ~+40°C ─ ─ 7 A ~+70°C ─ ─ 10 A ~+85°C ICCDR VCC=3.0V, Vin ≥ 0V, (1) CS# ≥ VCC-0.2V or (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V Chip deselect time to data retention tCDR 0 ─ ─ ns See retention waveform. Operation recovery time tR 5 ─ ─ ms Note 27. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 28. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested. 29. CS# controls address buffer, WE# buffer, OE# buffer, LB# buffer, UB# buffer and DQ buffer. If CS# controls data retention mode, Vin levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high impedance state. Low Vcc Data Retention Timing Waveforms (CS# controlled) CS# Controlled VCC tCDR 2.4V 2.4V tR VDR 2.0V 2.0V CS# ≥ VCC - 0.2V CS# Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled) LB#,UB# Controlled VCC tCDR 2.0V 2.4V 2.4V VDR tR 2.0V LB#,UB# ≥ VCC - 0.2V LB#,UB# R10DS0231EJ0201 Rev.2.01 2020.02.20 Page 12 of 12 Revision History Rev. 1.00 2.00 Date 2014.11.28 2015.06.26 2.01 2020.02.20 Page ─ P.1, 4 P.2 P.4 P.12 Last page RMLV0816BGSB Data Sheet Description Summary First Edition issued Standby current ISB1 : 25°C 0.6µA ->0.45µA (typ.), 40°C 2µA ->0.6µA (typ.) Modefy Pin Arrangement : Add 1pin Mark Average operating current ICC2 : 25°C 2mA ->1.5mA (typ.) Data retention current ICCDR : 25°C 0.6µA ->0.45µA (typ.), 40°C 2µA ->0.6µA (typ.) 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