RMLV1616AGSD-5S2#AC0

RMLV1616A Series 16Mb Advanced LPSRAM (1M word × 16bit / 2M word x 8bit) R10DS0258EJ0101 Rev.1.01 2020.02.20 Description The RMLV1616A Series is a family of 16-Mbit static RAMs organized 1,048,576-word × 16-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV1616A Series has realized higher density, higher performance and low power consumption. The RMLV1616A Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 48pin TSOP (I), 52pin TSOP (II) or 48-ball fine pitch ball grid array. Features  Single 3V supply: 2.7V to 3.6V  Access time: 55ns (max.)  Current consumption: ── Standby: 0.5µA (typ.)  Common data input and output ── Three state output  Directly TTL compatible ── All inputs and outputs  Battery backup operation Part Name Information Part Name Access time Temperature Range RMLV1616AGSA-5S2 RMLV1616AGSD-5S2 Package 12mm x 20mm 48pin plastic TSOP (I) 55 ns RMLV1616AGBG-5S2 R10DS0258EJ0101 Rev.1.01 2020.02.20 -40 ~ +85°C 10.79mm × 10.49mm 52pin plastic µTSOP (II) 48-ball FBGA with 0.75mm ball pitch Page 1 of 14 RMLV1616A Series Pin Arrangement A15 1 48 A16 A14 2 47 BYTE# A13 3 46 Vss A12 4 45 DQ15/A-1 A11 5 44 DQ7 A10 6 43 DQ14 A9 7 42 DQ6 A8 8 41 DQ13 A19 9 40 DQ5 NC 10 39 DQ12 WE# 11 38 DQ4 CS2 12 37 Vcc NC 13 36 DQ11 UB# 14 35 DQ3 LB# 15 34 DQ10 A18 16 33 DQ2 A17 17 32 DQ9 A7 18 31 DQ1 A6 19 30 DQ8 A5 20 29 DQ0 A4 21 28 OE# A3 22 27 Vss A2 23 26 CS1# A1 24 25 A0 A15 1 52 A16 A14 2 51 BYTE# A13 3 50 UB# A12 4 49 Vss A11 5 48 LB# A10 6 47 DQ15/A-1 A9 7 46 DQ7 A8 8 45 DQ14 A19 9 44 DQ6 CS1# 10 43 DQ13 WE# 11 42 DQ5 NC 12 41 DQ12 NC 13 40 DQ4 Vcc 14 39 NC CS2 15 38 DQ11 NC 16 37 DQ3 NC 17 36 DQ10 A18 18 35 DQ2 A17 19 34 DQ9 A7 20 33 DQ1 A6 21 32 DQ8 A5 22 31 DQ0 A4 23 30 OE# A3 24 29 Vss A2 25 28 NC A1 26 27 A0 48pin TSOP (I) 52pin TSOP (II) R10DS0258EJ0101 Rev.1.01 2020.02.20 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CS2 B DQ15 UB# A3 A4 CS1# DQ0 C DQ13 DQ14 A5 A6 DQ1 DQ2 D Vss DQ12 A17 A7 DQ3 Vcc E Vcc DQ11 NC A16 DQ4 Vss F DQ10 DQ9 A14 A15 DQ6 DQ5 G DQ8 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 NC 48-ball FBGA (TOP VIEW) Page 2 of 14 RMLV1616A Series Pin Description Pin name VCC VSS A0 to A19 A-1 to A19 DQ0 to DQ15 CS1# CS2 OE# WE# LB# UB# BYTE# NC Function Power supply Ground Address input (word mode) Address input (byte mode) Data input/output Chip select 1 Chip select 2 Output enable Write enable Lower byte select Upper byte select Byte control mode enable No connection DATA SELECTOR x8/x16 SWITCHING CIRCUIT UB# BYTE# OUTPUT BUFFER DATA INPUT BUFFER LB# DQ7 DQ8 DATA INPUT BUFFER CLOCK GENERATOR CS1# OUTPUT BUFFER DQ0 DATA SELECTOR CS2 1048576 Words x 16BITS OR 2097152 Words x 8BITS SENSE Amp. A19 Memory Array DECODER ADDRESS BUFFER A0 SENSE Amp. Block Diagram DQ15 / A-1 Vcc Vss WE# OE# Note 1. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 3 of 14 RMLV1616A Series Operation Table CS1# CS2 BYTE# UB# LB# WE# OE# DQ0~7 DQ8~14 DQ15 Operation H X X X X X X High-Z High-Z High-Z Stand-by X L X X X X X High-Z High-Z High-Z Stand-by X X H H H X X High-Z High-Z High-Z Stand-by L H H H L L X Din High-Z High-Z Write in lower byte L H H H L H L Dout High-Z High-Z Read in lower byte L H H H L H H High-Z High-Z High-Z Output disable L H H L H L X High-Z Din Din Write in upper byte L H H L H H L High-Z Dout Dout Read in upper byte L H H L H H H High-Z High-Z High-Z Output disable L H H L L L X Din Din Din Word write L H H L L H L Dout Dout Dout Word read L H H L L H H High-Z High-Z High-Z Output disable L H L X X L X Din High-Z A-1 Byte write L H L X X H L Dout High-Z A-1 Byte read L H L X X H H High-Z High-Z A-1 Output disable Note 2. 3. H: VIH L:VIL X: VIH or VIL BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. 48-ball FBGA type equals BYTE#=H mode. Absolute Maximum Ratings Parameter Symbol Power supply voltage relative to VSS VCC Terminal voltage on any pin relative to VSS VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 4. -2.0V for pulse ≤ 30ns (full width at half maximum) 5. Maximum voltage is +4.6V. Value -0.5 to +4.6 -0.5*4 to VCC+0.3*5 0.7 -40 to +85 -65 to +150 -40 to +85 unit V V W °C °C °C DC Operating Conditions Parameter Supply voltage Symbol Min. Typ. Max. Unit VCC 2.7 3.0 3.6 V VSS 0 0 0 V Input high voltage VIH 2.2 ─ VCC+0.3 V Input low voltage VIL -0.3 ─ 0.6 V Ambient temperature range Ta -40 ─ +85 °C Note 6. Note 6 -2.0V for pulse ≤ 30ns (full width at half maximum) R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 4 of 14 RMLV1616A Series DC Characteristics Parameter Input leakage current Output leakage current Test conditions*7 Vin = VSS to VCC CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Symbol | ILI | Min. ─ Typ. ─ Max. 1 Unit A | ILO | ─ ─ 1 A ICC1 ─ 23*8 30 mA ICC2 ─ 1.6*8 4 mA ISB ─ ─ 0.3 mA Cycle = 1s, duty =100%, II/O = 0mA, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V CS2 = VIL, Others = VSS to VCC ─ 0.5*8 3 A ~+25°C ─ 0.8*9 5 A ~+40°C ─ 2.5*10 12 A ~+70°C ─ 5*11 16 A ~+85°C Average operating current Standby current Standby current Cycle = 55ns, duty =100%, II/O = 0mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL ISB1 Vin = VSS to VCC, (1) CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V Output high voltage VOH 2.4 ─ ─ V IOH = -1mA VOH2 Vcc - 0.2 ─ ─ V IOH = -0.1mA Output low voltage VOL ─ ─ 0.4 V IOL = 2mA VOL2 ─ ─ 0.2 V IOL = 0.1mA Note 7. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V 8. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 9. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested. 10. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=70ºC), and not 100% tested. 11. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=85ºC), and not 100% tested. Capacitance (Ta =25°C, f =1MHz) Parameter Symbol Min. Input capacitance C in ─ Input / output capacitance C I/O ─ Note 12. This parameter is sampled and not 100% tested. R10DS0258EJ0101 Rev.1.01 2020.02.20 Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 12 12 Page 5 of 14 RMLV1616A Series AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C) 1.4V  Input pulse levels: VIL = 0.4V, VIH = 2.4V  Input rise and fall time: 5ns  Input and output timing reference level: 1.4V  Output load: See figures (Including scope and jig) RL = 500 ohm DQ CL = 30 pF Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z LB#, UB# enable to low-Z Output enable to output in low-Z Symbol Min. tRC tAA 55 ─ ─ ─ ─ 10 ─ 10 10 5 5 0 0 0 0 tACS1 tACS2 tOE tOH tBA tCLZ1 tCLZ2 tBLZ tOLZ Max. Unit Note 55 45 45 22 ─ 45 ─ ─ ─ ─ 18 18 18 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13,14 13,14 13,14 13,14 13,14,15 13,14,15 13,14,15 13,14,15 tCHZ1 tCHZ2 LB#, UB# disable to high-Z tBHZ Output disable to output in high-Z tOHZ Note 13. This parameter is sampled and not 100% tested. 14 At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. 15. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. Chip deselect to output in high-Z R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 6 of 14 RMLV1616A Series Write Cycle Parameter Symbol Min. Max. Unit Note Write cycle time tWC 55 ─ ns Address valid to write end tAW 35 ─ ns Chip select to write end tCW 35 ─ ns Write pulse width tWP 35 ─ ns 16 LB#,UB# valid to write end tBW 35 ─ ns Address setup time to write start tAS 0 ─ ns Write recovery time from write end tWR 0 ─ ns Data to write time overlap tDW 25 ─ ns Data hold from write end tDH 0 ─ ns Output enable from write end tOW 5 ─ ns 17 Output disable to output in high-Z tOHZ 0 18 ns 17,18 Write to output in high-Z tWHZ 0 18 ns 17,18 Note 16. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 17. This parameter is sampled and not 100% tested. 18. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. BYTE# Timing Conditions (BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types) Parameter Byte setup time Byte recovery time Symbol Min. Max. Unit tBS tBR 5 5 - ms ms Note BYTE# Timing Waveforms CS1# CS2 tBS tBR BYTE# R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 7 of 14 RMLV1616A Series Timing Waveforms Read Cycle*19 tRC A0~19 Valid address (Word Mode) A -1~19 tAA (Byte Mode) tACS1 CS1# tCLZ1 *21,22 CS2 tCHZ1 *20,21,22 tACS2 tCLZ2 *21,22 tCHZ2 *20,21,22 tBA LB#,UB# tBLZ *21,22 WE# tBHZ *20,21,22 VIH WE# = “H” level tOHZ *20,21,22 tOE OE# tOLZ tOH *21,22 DQ0~15 (Word Mode) DQ0~7 High impedance Valid Data (Byte Mode) Note 19. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode) 20. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 21. This parameter is sampled and not 100% tested. 22. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2 min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 8 of 14 RMLV1616A Series Write Cycle (1)*23 (WE# CLOCK, OE#=”H” while writing) tWC A0~19 Valid address (Word Mode) A -1~19 (Byte Mode) tCW CS1# CS2 tCW tBW LB#,UB# tWR tAW tWP WE# tAS OE# DQ0~15 (Word Mode) DQ0~7 *24 tWHZ *25,26 tOHZ *25,26 *27 tDW tDH Valid Data (Byte Mode) Note 23. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode) 24. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 25. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 26. This parameter is sampled and not 100% tested. 27. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins. R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 9 of 14 RMLV1616A Series Write Cycle (2)*28 (WE# CLOCK, OE# Low Fixed) tWC A0~19 Valid address (Word Mode) A -1~19 (Byte Mode) tCW CS1# CS2 tCW tBW LB#,UB# tAW tWR tWP *29 WE# OE# OE# = “L” level tAS VIL tWHZ *30,31 DQ0~15 tOW (Word Mode) DQ0~7 (Byte Mode) *32 Valid Data tDW *32 tDH Note 28. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode) 29. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. 30. tWHZ is defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ levels. 31. This parameter is sampled and not 100% tested. 32. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins. R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 10 of 14 RMLV1616A Series Write Cycle (3)*33 (CS1#, CS2 CLOCK) tWC A0~19 (Word Mode) Valid address A -1~19 (Byte Mode) tAW tAS tCW tAS tCW tWR CS1# CS2 tBW LB#,UB# tWP *34 WE# OE# VIH OE# = “H” level DQ0~15 (Word Mode) DQ0~7 tDW tDH Valid Valid Data Data (Byte Mode) Note 33. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode) 34. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 11 of 14 RMLV1616A Series Write Cycle (4)*35 (LB#, UB# CLOCK, Word Mode) tWC A0~19 Valid address (Word Mode) tAW tCW CS1# tCW CS2 tAS tWR tBW LB#,UB# tWP *36 WE# OE# VIH OE# = “H” level tDW DQ0~15 (Word Mode) tDH Valid Data Note 35. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V (Word mode) 36. tWP is the interval between write start and write end. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 12 of 14 RMLV1616A Series Low VCC Data Retention Characteristics Parameter VCC for data retention Data retention current Chip deselect time to data retention Operation recovery time Symbol VDR Min. Typ. Max. Test conditions*37,38 Unit 1.5 ─ 3.6 V Vin ≥ 0V (1) CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V ─ 0.5*39 3 A ~+25°C ─ 0.8*40 5 A ~+40°C ─ 2.5*41 12 A ~+70°C ─ 5*42 16 A ~+85°C 0 5 ─ ─ ─ ─ ns ms See retention waveform. ICCDR tCDR tR VCC = 3.0V, Vin ≥ 0V (1) CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V Note 37. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V 38. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB# buffer, UB# buffer and DQ buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, LB#, UB#, DQ) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V. The other inputs levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high-impedance state. 39. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 40. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested. 41. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=70ºC), and not 100% tested. 42. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=85ºC), and not 100% tested. R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 13 of 14 RMLV1616A Series Low Vcc Data Retention Timing Waveforms (CS1# controlled)*43 CS1# Controlled VCC tCDR 2.7V 2.7V tR VDR 2.4V 2.4V CS1# ≥ VCC - 0.2V CS1# Low Vcc Data Retention Timing Waveforms (CS2 controlled)*43 CS2 Controlled VCC tCDR CS2 2.7V 2.7V tR VDR 0.4V 0.4V CS2 ≤ 0.2V Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled, Word Mode)*44 LB#,UB# Controlled VCC tCDR 2.4V 2.7V 2.7V tR VDR 2.4V LB#,UB# ≥ VCC - 0.2V LB#,UB# Note 43. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V or BYTE# ≤ 0.2V 44. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types. BYTE# ≥ Vcc - 0.2V (Word mode) R10DS0258EJ0101 Rev.1.01 2020.02.20 Page 14 of 14 Revision History Rev. 1.00 1.01 Date 2016.01.06 2020.02.20 Page ─ Last page RMLV1616A Series Data Sheet Description Summary First Edition issued Updated the Notice to the latest version All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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