RTK7TBS5D3S00001BU

Datasheet Cover S5D3 Microcontroller Group Datasheet Renesas Synergy™ Platform Synergy Microcontrollers S5 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.1.00 Aug 2018 S5D3 Microcontroller Group Datasheet Leading performance 120-MHz Arm® Cortex®-M4 core, 512-KB code flash memory, 256-KB SRAM, Capacitive Touch Sensing Unit, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and advanced analog. Features ■ Arm Cortex-M4 Core with Floating Point Unit (FPU)      Armv7E-M architecture with DSP instruction set Maximum operating frequency: 120 MHz Support for 4-GB address space On-chip debugging system: JTAG, SWD, and ETM Boundary scan and Arm Memory Protection Unit (Arm MPU) ■ Memory        512-KB code flash memory (40 MHz zero wait states) 8-KB data flash memory (125,000 erase/write cycles) 256-KB SRAM Flash Cache (FCACHE) Memory Protection Units (MPU) Memory Mirror Function (MMF) 128-bit unique ID ■ Connectivity  USB 2.0 Full-Speed (USBFS) module - On-chip transceiver  Serial Communications Interface (SCI) with FIFO × 7  Serial Peripheral Interface (SPI) × 2  I2C bus interface (IIC) × 2  CAN module (CAN) × 2  Serial Sound Interface Enhanced (SSIE)  SD/MMC Host Interface (SDHI) × 2  Quad Serial Peripheral Interface (QSPI)  IrDA interface  Sampling Rate Converter (SRC)  External address space - 8-bit bus space ■ Analog  12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits each × 2  12-bit D/A Converter (DAC12) × 2  High-Speed Analog Comparator (ACMPHS) × 6  Programmable Gain Amplifier (PGA) × 6  Temperature Sensor (TSN) ■ Timers  General PWM Timer 32-bit Enhanced High Resolution (GPT32EH) × 4  General PWM Timer 32-bit Enhanced (GPT32E) × 4  General PWM Timer 32-bit (GPT32) × 5  Asynchronous General-Purpose Timer (AGT) × 2  Watchdog Timer (WDT) ■ Safety              ■ System and Power Management         Low power modes Realtime Clock (RTC) with calendar and VBATT support Event Link Controller (ELC) DMA Controller (DMAC) × 8 Data Transfer Controller (DTC) Key Interrupt Function (KINT) Power-on reset Low Voltage Detection (LVD) with voltage settings ■ Security and Encryption       AES128/192/256 3DES/ARC4 SHA1/SHA224/SHA256/MD5 GHASH RSA/DSA/ECC True Random Number Generator (TRNG) ■ Human Machine Interface (HMI)  Capacitive Touch Sensing Unit (CTSU) ■ Multiple Clock Sources         Main clock oscillator (MOSC) (8 to 24 MHz) Sub-clock oscillator (SOSC) (32.768 kHz) High-speed on-chip oscillator (HOCO) (16/18/20 MHz) Middle-speed on-chip oscillator (MOCO) (8 MHz) Low-speed on-chip oscillator (LOCO) (32.768 kHz) IWDT-dedicated on-chip oscillator (15 kHz) Clock trim function for HOCO/MOCO/LOCO Clock out support ■ General-Purpose I/O Ports  Up to 76 input/output pins - Up to 9 CMOS input - Up to 67 CMOS input/output - Up to 14 input/output 5 V tolerant - Up to 13 high current (20 mA) ■ Operating Voltage  VCC: 2.7 to 3.6 V ■ Operating Temperature and Packages  Ta = -40°C to +85°C - 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch)  Ta = -40°C to +105°C - 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) - 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch) - 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch) Error Code Correction (ECC) in SRAM SRAM parity error check Flash area protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO readback level detection Register write protection Main oscillator stop detection Illegal memory access R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 2 of 92 S5D3 Datasheet 1. 1. Overview Overview The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU in this series incorporates a high-performance Arm Cortex®-M4 core running up to 120 MHz with the following features:  512-KB code flash memory  256-KB SRAM  Capacitive Touch Sensing Unit (CTSU)  USBFS  SD/MMC Host Interface  Quad Serial Peripheral Interface (QSPI)  Security and safety features  12-bit A/D Converter (ADC12)  12-bit D/A Converter (DAC12)  Analog peripherals. 1.1 Function Outline Table 1.1 Arm core Feature Functional description Arm Cortex-M4 core  Maximum operating frequency: up to 120 MHz  Arm Cortex-M4 core: - Revision: r0p1-01rel0 - Armv7E-M architecture profile - Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.  Arm Memory Protection Unit (Arm MPU): - Armv7 Protected Memory System Architecture - 8 protect regions.  SysTick timer: - Driven by SYSTICCLK (LOCO) or ICLK. Table 1.2 Memory Feature Functional description Code flash memory 512 KB of code flash memory. See section 50, Flash Memory in User’s Manual. Data flash memory 8 KB of data flash memory. See section 50, Flash Memory in User’s Manual. Memory Mirror Function (MMF) The Memory Mirror Function (MMF) can be configured to mirror the target application image load address in code flash memory to the application image link address in the 23-bit unused memory space (memory mirror space addresses). Your application code is developed and linked to run from this MMF destination address. Your application code does not need to know the load location where it is stored in code flash memory. See section 5, Memory Mirror Function (MMF) in User’s Manual. Option-setting memory The option-setting memory determines the state of the MCU after a reset. See section 7, Option-Setting Memory in User’s Manual. SRAM On-chip high-speed SRAM with either parity-bit or Error Correction Code (ECC). The first 32 KB in SRAM0 provides error correction capability using ECC. Parity check is performed for other areas. See section 48, SRAM in User’s Manual. Standby SRAM On-chip SRAM that can retain data in Deep Software Standby mode. See section 49, Standby SRAM in User’s Manual. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 3 of 92 S5D3 Datasheet Table 1.3 1. Overview System (1 of 2) Feature Functional description Operating modes Two operating modes:  Single-chip mode  SCI or USB boot mode. See section 3, Operating Modes in User’s Manual. Resets 14 resets:  RES pin reset  Power-on reset  Voltage monitor 0 reset  Voltage monitor 1 reset  Voltage monitor 2 reset  Independent watchdog timer reset  Watchdog timer reset  Deep Software Standby reset  SRAM parity error reset  SRAM ECC error reset  Bus master MPU error reset  Bus slave MPU error reset  Stack pointer error reset  Software reset. See section 6, Resets in User’s Manual. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and the detection level can be selected using a software program. See section 8, Low Voltage Detection (LVD) in User’s Manual. Clocks  Main clock oscillator (MOSC)  Sub-clock oscillator (SOSC)  High-speed on-chip oscillator (HOCO)  Middle-speed on-chip oscillator (MOCO)  Low-speed on-chip oscillator (LOCO)  PLL frequency synthesizer  IDWT-dedicated on-chip oscillator  Clock out support. See section 9, Clock Generation Circuit in User’s Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range. When measurement is complete or the number of pulses within the time generated by the measurement reference clock is not within the allowable range, an interrupt request is generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt Controller Unit (ICU) in User’s Manual. Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function (KINT) in User’s Manual. Low power modes Power consumption can be reduced in multiple ways, such as by setting clock dividers, controlling EBCLK output, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 11, Low Power Modes in User’s Manual. Battery backup function A battery backup function is provided for partial powering by a battery. The battery-powered area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See section 12, Battery Backup Function in User’s Manual. Register write protection The register write protection function protects important registers from being overwritten because of software errors. See section 13, Register Write Protection in User’s Manual. Memory Protection Unit (MPU) Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided for memory protection. See section 16, Memory Protection Unit (MPU) in User’s Manual. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 4 of 92 S5D3 Datasheet Table 1.3 1. Overview System (2 of 2) Feature Functional description Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A refresh-permitted period can be set to refresh the counter and used as the condition for detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in User’s Manual. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt or interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by a refresh of the count value in the registers. See section 28, Independent Watchdog Timer (IWDT) in User’s Manual. Table 1.4 Event link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 19, Event Link Controller (ELC) in User’s Manual. Table 1.5 Direct memory access Feature Functional description Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an interrupt request. See section 18, Data Transfer Controller (DTC) in User’s Manual. DMA Controller (DMAC) An 8-channel DMA Controller (DMAC) module is provided for transferring data without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. See section 17, DMA Controller (DMAC) in User’s Manual. Table 1.6 External bus interface Feature Functional description External buses  CS area (EXBIU): Connected to the external devices (external memory interface)  QSPI area (EXBIUT2): Connected to the QSPI (external device interface). Table 1.7 Timers (1 of 2) Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 13 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a general-purpose timer. See section 23, General PWM Timer (GPT) in User’s Manual. Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT) output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in User’s Manual. Asynchronous General-Purpose Timer (AGT) The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting of external events. This 16-bit timer consists of a reload register and a down-counter. The reload register and the down-counter are allocated to the same address, and can be accessed with the AGT register. See section 25, Asynchronous General-Purpose Timer (AGT) in User’s Manual. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 5 of 92 S5D3 Datasheet Table 1.7 1. Overview Timers (2 of 2) Feature Functional description Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count mode, that are controlled by the register settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count mode can be used for calendars other than the Gregorian (Western) calendar. See section 26, Realtime Clock (RTC) in User’s Manual. Table 1.8 Communication interfaces (1 of 2) Feature Functional description Serial Communications Interface (SCI) The Serial Communications Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:  Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter (ACIA))  8-bit clock synchronous interface  Simple IIC (master-only)  Simple SPI  Smart card interface. The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. See section 30, Serial Communications Interface (SCI) in User’s Manual. IrDA Interface (IrDA) The IrDA interface sends and receives IrDA data communication waveforms in cooperation with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 31, IrDA Interface in User’s Manual. I2C bus interface (IIC) The 2-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C bus (Inter-Integrated Circuit) bus interface functions. See section 32, I2C Bus Interface (IIC) in User’s Manual. Serial Peripheral Interface (SPI) Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, fullduplex synchronous serial communications with multiple processors and peripheral devices. See section 34, Serial Peripheral Interface (SPI) in User’s Manual. Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with digital audio devices for transmitting I2S (Inter-Integrated Sound) 2ch, 4ch, 6ch, 8ch, Word Select (WS) Continue/Monaural/TDM audio data over a serial bus. The SSIE supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master receiver, transmitter, or transceiver to suit various applications. The SSIE includes 32-stage FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception and transmission. See section 37, Serial Sound Interface Enhanced (SSIE) in User’s Manual. Quad Serial Peripheral Interface (QSPI) The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has an SPI-compatible interface. See section 35, Quad Serial Peripheral Interface (QSPI) in User’s Manual. Controller Area Network (CAN) module The Controller Area Network (CAN) module provides functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagneticallynoisy applications. The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. See section 33, Controller Area Network (CAN) Module in User’s Manual. USB 2.0 Full-Speed Module (USBFS) module The USB 2.0 Full-Speed (USBFS) module can operate as a host controller or device controller. The module supports full-speed and low-speed (host controller only) transfer as defined in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned any endpoint number based on the peripheral devices used for communication or based on your system. See section 29, USB 2.0 Full-Speed Module (USBFS) in User’s Manual. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 6 of 92 S5D3 Datasheet Table 1.8 1. Overview Communication interfaces (2 of 2) Feature Functional description SD/MMC Host Interface (SDHI) The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to connect a variety of external memory cards to the MCU. The SDHI supports both 1-bit and 4bit buses for connecting memory cards that support SD, SDHC, and SDXC formats. When developing host devices that are compliant with the SD Specifications, you must comply with the SD Host/Ancillary Product License Agreement (SD HALA). The MMC interface supports 1-bit and 4-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84-B451) device access. This interface also provides backward compatibility and supports high-speed SDR transfer modes. See section 39, SD/MMC Host Interface (SDHI) in User’s Manual. Table 1.9 Analog Feature Functional description 12-bit A/D Converter (ADC12) Up to two successive approximation 12-bit A/D Converters (ADC12) are provided. In unit 0, up to 11 analog input channels are selectable. In unit 1, up to eight analog input channels, the temperature sensor output, and an internal reference voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit, 10-bit, and 8-bit conversion, making it possible to optimize the tradeoff between speed and resolution in generating a digital value. See section 42, 12-Bit A/D Converter (ADC12) in User’s Manual. 12-bit D/A Converter (DAC12) A 12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section 43, 12-Bit D/A Converter (DAC12) in User’s Manual. Temperature Sensor (TSN) The on-chip Temperature Sensor (TSN) can determine and monitor the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. The output voltage is provided to the ADC12 for conversion and can also be used by the end application. See section 44, Temperature Sensor (TSN) in User’s Manual. High-Speed Analog Comparator (ACMPHS) The High-Speed Analog Comparator (ACMPHS) compares a test voltage with a reference voltage and provides a digital output based on the conversion result. Both the test and reference voltages can be provided to the comparator from internal sources such as the DAC12 output and internal reference voltage, and an external source with or without an internal PGA. Such flexibility is useful in applications that require go/no-go comparisons to be performed between analog signals without necessarily requiring A/D conversion. See section 45, HighSpeed Analog Comparator (ACMPHS) in User’s Manual. Table 1.10 Human machine interfaces Feature Functional description Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor is usually enclosed with an electrical insulator so that a finger does not come into direct contact with the electrodes. See section 46, Capacitive Touch Sensing Unit (CTSU) in User’s Manual. Table 1.11 Data processing (1 of 2) Feature Functional description Cyclic Redundancy Check (CRC) calculator The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication. Additionally, various CRC-generating polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This function is useful in applications that require CRC code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See section 36, Cyclic Redundancy Check (CRC) Calculator in User’s Manual. Data Operation Circuit (DOC) The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 47, Data Operation Circuit (DOC) in User’s Manual. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 7 of 92 S5D3 Datasheet Table 1.11 1. Overview Data processing (2 of 2) Feature Functional description Sampling Rate Converter (SRC) The Sampling Rate Converter (SRC) converts the sampling rate of data produced by various audio decoders, such as the WMA, MP3, and AAC. Both 16-bit stereo and monaural data are supported. See section 38, Sampling Rate Converter (SRC) in User’s Manual. Table 1.12 Security Feature Functional description Secure Crypto Engine 7 (SCE7)  Security algorithms: - Symmetric algorithms: AES, 3DES, and ARC4 - Asymmetric algorithms: RSA, DSA, and ECC.  Other support features: - TRNG (True Random Number Generator) - Hash-value generation: SHA1, SHA224, SHA256, GHASH, and MD5 - 128-bit unique ID. 1.2 Block Diagram Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the features. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 8 of 92 S5D3 Datasheet 1. Overview Memory Bus Arm Cortex-M4 512 KB code flash External 8 KB data flash CSC DSP System FPU Clocks POR/LVD MOSC/SOSC MPU Reset (H/M/L) OCO 256 KB SRAM MPU NVIC 8 KB Standby SRAM Mode control PLL Power control CAC ICU Battery backup KINT Register write protection System timer DMA Test and DBG interface DTC DMAC × 8 Timers GPT32EH x 4 GPT32E x 4 GPT32 x 5 AGT × 2 Communication interfaces SCI × 7 Human machine interfaces QSPI CTSU IrDA × 1 IIC × 2 SDHI × 2 SPI × 2 CAN × 2 SSIE USBFS RTC WDT/IWDT Event link Data processing ELC CRC Security DOC SRC Analog ADC12 with PGA × 2 TSN DAC12 ACMPHS × 6 SCE7 Figure 1.1 Block diagram R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 9 of 92 S5D3 Datasheet 1.3 1. Overview Part Numbering Figure 1.2 shows the product part number information, including memory capacity, and package type. Table 1.13 shows a list of products. R 7 F S 5 D 3 7A 3 A 0 1 C F P # A A 0 Production identification code Packaging, Terminal material (Pb-free) #AA: Tray/Sn (Tin) only #AC: Tray/others Package type FP: LQFP 100 pins FM: LQFP 64 pins LJ: LGA 100 pins NB: QFN 64 pins Quality ID Software ID Operating temperature 2: -40°C to 85°C 3: -40°C to 105°C Code flash memory size A: 512 KB Feature set 7: Superset D3 : S5D3 Group, Arm Cortex-M4, 120MHz Series name 5: High integration Renesas Synergy™ family Flash memory Renesas microcontroller unit Renesas Figure 1.2 Table 1.13 Part numbering scheme Product list Product part number Orderable part number Package code Code flash Data flash SRAM Operating temperature R7FS5D37A2A01CLJ R7FS5D37A2A01CLJ#AC0 PTLG0100JA-A 512 KB 8 KB 256 KB -40 to +85°C R7FS5D37A3A01CFP R7FS5D37A3A01CFP#AA0 PLQP0100KB-B -40 to +105°C R7FS5D37A3A01CFM R7FS5D37A3A01CFM#AA0 PLQP0064KB-C -40 to +105°C R7FS5D37A3A01CNB R7FS5D37A3A01CNB#AC0 PWQN0064LA-A -40 to +105°C R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 10 of 92 S5D3 Datasheet 1.4 1. Overview Function Comparison Table 1.14 Functional comparison Part numbers Function R7FS5D37A2A01CLJ R7FS5D37A3A01CFP R7FS5D37A3A01CFM R7FS5D37A3A01CNB Pin count 100 100 64 64 Package LGA LQFP LQFP QFN Code flash memory 512 KB Data flash memory 8 KB SRAM 256 KB Parity 224 KB ECC 32 KB Standby SRAM System 8 KB CPU clock 120 MHz Backup registers 512 B ICU Yes KINT 8 Event link ELC Yes DMA DTC Yes BUS External bus Timers GPT32EH DMAC Communication 8 8-bit bus GPT32E 4 3 GPT32 5 4 AGT 2 RTC Yes WDT/IWDT Yes SCI 7 IIC 2 SPI SSIE 2 1 QSPI SDHI 2 Yes 19 DAC12 6 TSN CTSU Data processing CRC 10 2 ACMPHS HMI No 2 USBFS ADC12 No 1 CAN Analog No 4 Yes 12 7 Yes DOC Yes SRC Yes Security R01DS0328EU0100 Rev.1.00 Aug 10, 2018 SCE7 Page 11 of 92 S5D3 Datasheet 1.5 1. Overview Pin Functions Table 1.15 Pin functions (1 of 4) Function Signal I/O Description Power supply VCC Input Power supply pin. This is used as the digital power supply for the respective modules and internal voltage regulator, and used to monitor the voltage of the POR/LVD. Connect this pin to the system power supply. Connect it to VSS by a 0.1-μF capacitor. Place the capacitor close to the pin. VCL0 - VCL - Connect this pin to VSS through a 0.1-μF smoothing capacitor close to each VCL pin. Stabilize the internal power supply. VSS Input Ground pin. Connect to the system power supply (0 V). VBATT Input Backup power pin XTAL Output EXTAL Input Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. Clock XCIN Input XCOUT Output Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCOUT and XCIN. EBCLK Output Outputs the external bus clock for external devices CLKOUT Output Clock output pin Operating mode control MD Input Pin for setting the operating mode. The signal level on this pin must not be changed during operation mode transition on release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin Interrupt NMI Input Non-maskable interrupt request pin IRQ0 to IRQ13 Input Maskable interrupt request pins KINT KR00 to KR07 Input A key interrupt can be generated by inputting a falling edge to the key interrupt input pins On-chip emulator TMS I/O On-chip emulator or boundary scan pins External bus interface TDI Input TCK Input TDO Output TCLK Output TDATA0 to TDATA3 Output Trace data output SWDIO I/O Serial wire debug data input/output pin SWCLK Input Serial wire clock pin SWO Output Serial wire trace output pin RD Output Strobe signal indicating that reading from the external bus interface space is in progress, active-low WR0 Output Strobe signal indicating that writing to the external bus interface space is in progress, active-low ALE Output Address latch signal when address/data multiplexed bus is selected WAIT Input Input pin for wait request signals in access to the external space, active-low CS0, CS1, CS4 to CS7 Output Select signals for CS areas, active-low A00 to A12 Output Address bus D00 to D07 I/O Data bus A00/D00 to A07/D07 I/O Address/data multiplexed bus R01DS0328EU0100 Rev.1.00 Aug 10, 2018 This pin outputs the clock for synchronization with the trace data Page 12 of 92 S5D3 Datasheet Table 1.15 1. Overview Pin functions (2 of 4) Function Signal I/O Description GPT GTETRGA, GTETRGB, GTETRGC, GTETRGD Input External trigger input pins GTIOC0A to GTIOC12A, GTIOC0B to GTIOC12B I/O Input capture, output compare, or PWM output pins GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W AGT RTC SCI IIC SSIE GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase) GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase) GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase) GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase) GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase) GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase) AGTEE0, AGTEE1 Input External event input enable signals AGTIO0, AGTIO1 I/O External event input and pulse output pins AGTO0, AGTO1 Output Pulse output pins AGTOA0, AGTOA1 Output Output compare match A output pins AGTOB0, AGTOB1 Output Output compare match B output pins RTCOUT Output Output pin for 1-Hz or 64-Hz clock RTCIC0 to RTCIC2 Input Time capture event input pins SCK0 to SCK4, SCK8, SCK9 I/O Input/output pins for the clock (clock synchronous mode) RXD0 to RXD4, RXD8, RXD9 Input Input pins for received data (asynchronous mode/clock synchronous mode) TXD0 to TXD4, TXD8, TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous mode) CTS0_RTS0 to CTS4_RTS4, CTS8_RTS8, CTS9_RTS9 I/O Input/output pins for controlling the start of transmission and reception (asynchronous mode/clock synchronous mode), active-low SCL0 to SCL4, SCL8, SCL9 I/O Input/output pins for the IIC clock (simple IIC mode) SDA0 to SDA4, SDA8, SDA9 I/O Input/output pins for the IIC data (simple IIC mode) SCK0 to SCK4, SCK8, SCK9 I/O Input/output pins for the clock (simple SPI mode) MISO0 to MISO4, MISO8, MISO9 I/O Input/output pins for slave transmission of data (simple SPI mode) MOSI0 to MOSI4, MOSI8, MOSI9 I/O Input/output pins for master transmission of data (simple SPI mode) SS0 to SS4, SS8, SS9 Input Chip-select input pins (simple SPI mode), active-low SCL0, SCL1 I/O Input/output pins for the clock SDA0, SDA1 I/O Input/output pins for data SSIBCK0 I/O SSIE serial bit clock pins SSILRCK0/SSIFS0 I/O LR clock/frame synchronization pins SSITXD0 Output Serial data output pins SSIRXD0 Input Serial data input pins AUDIO_CLK Input External clock pin for audio (input oversampling clock) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 13 of 92 S5D3 Datasheet Table 1.15 1. Overview Pin functions (3 of 4) Function Signal I/O Description SPI RSPCKA, RSPCKB I/O Clock input/output pin MOSIA, MOSIB I/O Input or output pins for data output from the master MISOA, MISOB I/O Input or output pins for data output from the slave SSLA0, SSLB0 I/O Input or output pin for slave selection SSLA1 to SSLA3, SSLB1 to SSLB3 Output Output pins for slave selection QSPCLK Output QSPI clock output pin QSSL Output QSPI slave output pin QSPI CAN USBFS SDHI Analog power supply QIO0 to QIO3 I/O Data0 to Data3 CRX0, CRX1 Input Receive data CTX0, CTX1 Output Transmit data VCC_USB Input Power supply pins VSS_USB Input Ground pins USB_DP I/O D+ I/O pin of the USB on-chip transceiver. Connect this pin to the D+ pin of the USB bus USB_DM I/O D- I/O pin of the USB on-chip transceiver. Connect this pin to the D- pin of the USB bus USB_VBUS Input USB cable connection monitor pin. Connect this pin to VBUS of the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a device controller. USB_EXICEN Output Low-power control signal for external power supply (OTG) chip USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip USB_OVRCURA, USB_OVRCURB Input Connect the external overcurrent detection signals to these pins. Connect the VBUS comparator signals to these pins when the OTG power supply chip is connected. USB_ID Input Connect the MicroAB connector ID input signal to this pin during operation in OTG mode SD0CLK, SD1CLK Output SD clock output pins SD0CMD, SD1CMD I/O Command output pin and response input signal pins SD0DAT0 to SD0DAT3, SD1DAT0 to SD1DAT3 I/O SD and MMC data bus pins SD0CD Input SD card detection pins SD0WP Input SD write-protect signals AVCC0 Input Analog voltage supply pin. This is used as the analog power supply for the respective modules. Supply this pin with the same voltage as the VCC pin. AVSS0 Input Analog ground pin. This is used as the analog ground for the respective modules. Supply this pin with the same voltage as the VSS pin. VREFH0 Input Analog reference voltage supply pin for the ADC12 (unit 0). Connect this pin to VCC when not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to AN002. VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to VSS when not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to AN002 VREFH Input Analog reference voltage supply pin for the ADC12 (unit 1) and D/A Converter. Connect this pin to VCC when not using the ADC12 (unit 1), sample-and-hold circuit for AN100 to AN102, and D/A Converter. VREFL Input Analog reference ground pin for the ADC12 and D/A Converter. Connect this pin to VSS when not using the ADC12 (unit 1), sample-and-hold circuit for AN100 to AN102, and D/A Converter. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 14 of 92 S5D3 Datasheet Table 1.15 1. Overview Pin functions (4 of 4) Function Signal I/O Description ADC12 AN000 to AN003, AN005 to AN007, AN016 to AN018, AN020 Input Input pins for the analog signals to be processed by the ADC12 AN100 to AN102, AN105 to AN107, AN116, AN117 Input ADTRG0 Input ADTRG1 Input PGAVSS000, PGAVSS100 Input Input pins for the external trigger signals that start the A/D conversion Differential input pins DAC12 DA0, DA1 Output Output pins for the analog signals processed by the D/A converter ACMPHS VCOUT Output Comparator output pin CTSU I/O ports IVREF0 to IVREF3 Input Reference voltage input pins for comparator IVCMP0 to IVCMP3 Input Analog voltage input pins for comparator TS01 to TS12 Input Capacitive touch detection pins (touch pins) TSCAP - Secondary power supply pin for the touch driver P000 to P007 Input General-purpose input pins P008, P014, P015 I/O General-purpose input/output pins P100 to P115 I/O General-purpose input/output pins P200 Input General-purpose input pin P201, P205 to P214 I/O General-purpose input/output pins P300 to P307 I/O General-purpose input/output pins P400 to P415 I/O General-purpose input/output pins P500 to P504, P508 I/O General-purpose input/output pins P600 to P602, P608 to P610 I/O General-purpose input/output pins P708 I/O General-purpose input/output pin R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 15 of 92 S5D3 Datasheet 1.6 1. Overview Pin Assignments Figure 1.3 to Figure 1.6 show the pin assignments. R7FS5D37A2A01CLJ 10 A B C D E F G H J K P407 P409 P412 VCC P212/ EXTAL XCOUT VCL0 P403 P400 P000 10 P411 VSS P213/ XTAL XCIN VBATT P405 P401 P001 9 9 USB_DM USB_DP Figure 1.3 8 VCC_ USB VSS_ USB P207 P413 P415 P708 P404 P003 P004 P002 8 7 P205 P214 P206 P408 P414 P406 P006 P007 P008 P005 7 6 P209 P208 P210 P211 P410 P402 P508 AVSS0 VREFL0 VREFH0 6 5 P200 P201/MD P307 RES P113 P600 P504 AVCC0 VREFL VREFH 5 4 VCC P304 P305 P306 P115 P601 P503 P100 P015 P014 4 3 VSS P303 P110/TDI P111 P609 P602 P107 P103 VSS VCC 3 2 P300/ TCK/ SWCLK P302 P301 P114 P610 VSS P106 P101 P501 P502 2 1 P108/ TMS/ SWDIO P109/ TDO P112 P608 VCC VCL P105 P104 P102 P500 1 A B C D E F G H J K Pin assignment for 100-pin LGA (top view) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 16 of 92 Figure 1.4 P100 P101 P102 P103 P104 P105 P106 P107 P600 P601 P602 VCL VSS VCC P610 P609 P608 P115 P114 P113 P112 P111 P110/TDI P109/TDO P108/TMS/SWDIO 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1. Overview 75 S5D3 Datasheet P500 76 50 P501 77 49 P300/TCK/SWCLK P301 P502 78 48 P302 P503 79 47 P303 P504 80 46 VCC P508 81 45 VSS VCC 82 44 P304 VSS 83 43 P305 P015 84 42 P306 P014 85 41 P307 VREFL 86 40 P200 VREFH 87 39 P201/MD AVCC0 88 38 RES AVSS0 89 37 P208 VREFL0 90 36 P209 VREFH0 91 35 P210 P008 92 34 P211 P007 93 33 P214 P006 94 32 P205 P005 95 31 P206 P004 96 30 P207 P003 97 29 VCC_USB P002 98 28 USB_DP P001 99 27 USB_DM P000 100 26 VSS_USB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P400 P401 P402 P403 P404 P405 P406 VBATT VCL0 XCIN XCOUT VSS P213/XTAL P212/EXTAL VCC P708 P415 P414 P413 P412 P411 P410 P409 P408 P407 R7FS5D37AXA01CFP Pin assignment for 100-pin LQFP (top view) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 17 of 92 Figure 1.5 P100 P101 P102 P103 P104 P105 P106 P107 VCL VSS VCC P112 P111 P110/TDI P109/TDO P108/TMS/SWDIO 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1. Overview 48 S5D3 Datasheet P500 49 32 P300/TCK/SWCLK P501 50 31 P301 VCC 51 30 P302 VSS 52 29 VCC P015 53 28 VSS P014 54 27 P200 VREFL 55 26 P201/MD VREFH 56 25 RES AVCC0 57 24 P210 AVSS0 58 23 P205 VREFL0 59 22 P206 VREFH0 60 21 P207 P003 61 20 VCC_USB P002 62 19 USB_DP P001 63 18 USB_DM P000 64 17 VSS_USB 13 14 15 16 P410 P409 P408 P407 VSS 12 8 XCOUT 11 7 XCIN VCC 6 VCL0 P411 5 VBATT 10 4 P402 9 3 P401 P213/XTAL 2 P212/EXTAL 1 P400 R7FS5D37A3A01CFM Pin assignment for 64-pin LQFP (top view) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 18 of 92 33 34 35 36 37 38 39 40 41 42 43 44 P102 P103 P104 P105 P106 P107 VCL VSS VCC P112 P111 P110/TDI P109/TDO P108/TMS/SWDIO 45 46 47 P100 P101 1. Overview 48 S5D3 Datasheet P500 P501 VCC VSS P015 P014 VREFL VREFH AVCC0 AVSS0 VREFL0 VREFH0 P003 P002 P001 49 32 50 31 58 23 59 22 60 21 61 20 62 19 63 18 P300/TCK/SWCLK P301 P302 VCC VSS P200 P201/MD RES P210 P205 P206 P207 VCC_USB USB_DP USB_DM 51 30 52 29 53 28 54 27 55 26 P000 64 17 VSS_USB 24 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 P400 P401 P402 VBATT VCL0 XCIN XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P409 P408 P407 1 57 2 R7FS5D37A3A01CNB 56 Figure 1.6 Pin assignment for 64-pin QFN (top view) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 19 of 92 S5D3 Datasheet Pin Lists J10 1 1 1 - IRQ0 - AGTIO1 GTETRGA CTSU DAC12, ACMPHS HMI ADC12 SDHI SSIE SPI, QSPI Analog IIC SCI1,3,9 (30 MHz) USBFS, CAN RTC GPT GPT P400 SCI0,2,4,8 (30 MHz) Communication interfaces AGT I/O port External bus Timers Interrupt QFN64 LQFP64 LGA100 LQFP100 Pin number Power, System, Clock, Debug, CAC 1.7 1. Overview GTIOC6 A - SCK4 - SCL0_ A AUDIO_ CLK ADTRG1 - - GTIOC6 B CTX0 CTS4_RT S4/SS4 SDA0_ A - - - - - - CRX0 - - - - AUDIO_ CLK - - - J9 2 2 2 - IRQ5DS P401 - - F6 3 3 3 CACREF IRQ4DS P402 - AGTIO0/A GTIO1 H10 4 - - - - P403 - AGTIO0/A GTIO1 GTIOC3 RTCI A C1 - - - - - SSIBCK 0_A - - - G8 5 - - - - P404 - - - GTIOC3 RTCI B C2 - - - - - SSILRC K0/SSIF S0_A - - - H9 6 - - - - P405 - - - GTIOC1 A - - - - - SSITXD 0_A - - - RTCI C0 F7 7 - - - - P406 - - - GTIOC1 B - - - - - SSIRXD 0_A - - - G9 8 4 4 VBATT - - - - - - - - - - - - - - - - - G10 9 5 5 VCL0 - - - - - - - - - - - - - - - - - F9 10 6 6 XCIN - - - - - - - - - - - - - - - - - F10 11 7 7 XCOUT - - - - - - - - - - - - - - - - - D9 12 8 8 VSS - - - - - - - - - - - - - - - - - E9 13 9 9 XTAL IRQ2 P213 - - GTETRGC GTIOC0 A - - TXD1/MO SI1/SDA1 - - - ADTRG1 - - E10 14 10 10 EXTAL IRQ3 P212 - AGTEE1 GTETRGD GTIOC0 B - - RXD1/MIS O1/SCL1 - - - - - - D10 15 11 11 VCC - - - - - - - - - - - - - - - - F8 16 - - CACREF IRQ11 P708 - - - - - - - RXD1/MIS O1/SCL1 SSLA3_ AUDIO_ B CLK - - TS12 E8 17 - - - IRQ8 P415 - - - GTIOC0 A USB_V BUSEN - - SSLA2_ B SD0CD - - TS11 E7 18 - - - IRQ9 P414 - - - GTIOC0 B - - - SSLA1_ B SD0WP - - TS10 D8 19 - - - - P413 - - GTOUUP - - - CTS0_RT S0/SS0 - SSLA0_ B SD0CLK _A - TS09 C10 20 - - - - P412 - AGTEE1 GTOULO - - - SCK0 - RSPCK A_B SD0CMD _A - TS08 C9 21 12 12 - IRQ4 P411 - AGTOA1 GTOVUP GTIOC9 A - TXD0/MO CTS3_RT SI0/SDA0 S3/SS3 MOSIA_ B SD0DAT 0_A - TS07 E6 22 13 13 - IRQ5 P410 - AGTOB1 GTOVLO GTIOC9 B - RXD0/MIS SCK3 O0/SCL0 MISOA_ B SD0DAT 1_A - TS06 - - - - B10 23 14 14 - IRQ6 P409 - - GTOWUP GTIOC10 A USB_E XICEN TXD3/MO SI3/SDA3 - - - - - TS05 D7 24 15 15 - IRQ7 P408 - - GTOWLO GTIOC10 B USB_ID - RXD3/MIS SCL0_ O3/SCL3 B - - - - TS04 A10 25 16 16 - - P407 - AGTIO0 - - RTCO USB_V CTS4_RT UT BUS S4/SS4 SDA0_ B - - ADTRG0 - TS03 B8 26 17 17 VSS_USB - - - - - - - - - - - - - - - - - A9 27 18 18 - - - - - - - - USB_D M - - - - - - - - B9 28 19 19 - - - - - - - - USB_D P - - - - - - - - A8 29 20 20 VCC_USB - - - - - - - - - - - - - - - - - C8 30 21 21 - - P207 - - - - - - - - - QSSL - - - - TS02 C7 31 22 22 - IRQ0DS P206 WAIT - GTIU - - USB_V RXD4/MIS BUSEN O4/SCL4 SDA1_ A - SD0DAT 2_A - TS01 A7 32 23 23 CLKOUT IRQ1DS P205 - AGTO1 GTIV GTIOC4 A USB_O TXD4/MO CTS9_RT SCL1_ VRCUR SI4/SDA4 S9/SS9 A A-DS - SD0DAT 3_A - TSCAP B7 33 - - TRCLK - P214 - - GTIU - - - - - - QSPCL K SD0CLK _B - - D6 34 - - TRDATA0 - P211 CS7 - GTIV - - - - - - QIO0 SD0CMD _B - - C6 35 24 24 TRDATA1 - P210 CS6 - GTIW - - - - - - QIO1 - SD0CD - - - A6 36 - - TRDATA2 - P209 CS5 - GTOVUP - - - - - - QIO2 - SD0WP - - - B6 37 - - TRDATA3 - P208 CS4 - GTOVLO - - - - - - QIO3 - SD0DAT 0_B - - D5 38 25 25 RES - - - - - - - - - - - - - - - - - B5 39 26 26 MD - P201 - - - - - - - - - - - - - - - - A5 40 27 27 - NMI P200 - - - - - - - - - - - - - - C5 41 - - - - P307 A12 - GTOUUP - - - - - - QIO0 - - - - - D4 42 - - - - P306 A11 - GTOULO - - - - - - QSSL - - - - - C4 43 - - - IRQ8 P305 A10 - GTOWUP - - - - - - QSPCL K - - - - B4 44 - - - IRQ9 P304 A09 - GTOWLO GTIOC7 A - - - - - - - - - A3 45 28 28 VSS - - - - - - - - - - - - - - - - - A4 46 29 29 VCC - - - - - - - - - - - - - - - - - - B3 47 - - - - P303 A08 - - GTIOC7 B - - - - - - - - - - B2 48 30 30 - IRQ5 P302 A07 - GTOUUP GTIOC4 A - TXD2/MO SI2/SDA2 - SSLB3_ B - - - - C2 49 31 31 - IRQ6 P301 A06 AGTIO0 GTOULO GTIOC4 B - RXD2/MIS CTS9_RT O2/SCL2 S9/SS9 SSLB2_ B - - - - A2 50 32 32 TCK/SWC LK P300 - - GTOUUP GTIOC0 A_A - - - - SSLB1_ B - - - - A1 51 33 33 TMS/SWD IO P108 - - GTOULO GTIOC0 B_A - - CTS9_RT S9/SS9 SSLB0_ B - - - - R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 20 of 92 S5D3 Datasheet B1 52 34 34 P109 - - GTIOC1 A_A CTX1 - TXD9/MO SI9/SDA9 C3 53 35 35 TDI IRQ3 P110 - - GTOVLO GTIOC1 B_A CRX1 CTS2_RT RXD9/MIS S2/SS2 O9/SCL9 D3 54 36 36 - IRQ4 P111 A05 - - GTIOC3 A_A - SCK2 CTSU DAC12, ACMPHS HMI ADC12 SDHI SSIE SPI, QSPI Analog IIC SCI1,3,9 (30 MHz) USBFS, CAN RTC GPT GPT GTOVUP SCI0,2,4,8 (30 MHz) Communication interfaces AGT I/O port Interrupt CLKOUT/T DO/SWO External bus Timers Power, System, Clock, Debug, CAC QFN64 LQFP64 LGA100 LQFP100 Pin number 1. Overview MOSIB_ B - - - - MISOB_ B - - VCOUT - SCK9 - RSPCK B_B - - - - C1 55 37 37 - - P112 A04 - - GTIOC3 B_A - TXD2/MO SCK1 SI2/SDA2 - SSLB0_ SSIBCK B 0_B - - - E5 56 - - - - P113 A03 - - GTIOC2 A - RXD2/MIS O2/SCL2 - - SSILRC K0/SSIF S0_B - - - D2 57 - - - - P114 A02 - - GTIOC2 B - - - - SSIRXD 0_B - - - - E4 58 - - - - P115 A01 - - GTIOC4 A - - - - - SSITXD 0_B - - - D1 59 - - - - P608 A00 - - GTIOC4 B - - - - - - - - - - E3 60 - - - - P609 CS1 - - GTIOC5 A CTX1 - - - - - - - - - E2 61 - - - - P610 CS0 - - GTIOC5 B CRX1 - - - - - - - - - E1 62 38 38 VCC - - - - - - - - - - - - - - - - F2 63 39 39 VSS - - - - - - - - - - - - - - - - - F1 64 40 40 VCL - - - - - - - - - - - - - - - - - F3 65 - - - - P602 EBCL K - GTIOC7 B - - TXD9 - - - - - - - - F4 66 - - - - P601 WR0 - - GTIOC6 A - - RXD9 - - - - - - - F5 67 - - CLKOUT/ CACREF - P600 RD - - GTIOC6 B - - SCK9 - - - - - - - G3 68 41 41 - KR07 P107 D07[A AGTOA0 07/D0 7] - GTIOC8 A - CTS8_RT S8/SS8 - QIO3 - - - - - G2 69 42 42 - KR06 P106 D06[A AGTOB0 06/D0 6] - GTIOC8 B - SCK8 - - SSLA3_ A/QIO2 - - - - G1 70 43 43 - IRQ0/K P105 R05 D05[A 05/D0 5] GTETRGA GTIOC1 A - TXD8/MO SI8/SDA8 - SSLA2_ A/QIO1 - - - - H1 71 44 44 - IRQ1/K P104 R04 D04[A 04/D0 4] GTETRGB GTIOC1 B - RXD8/MIS O8/SCL8 - SSLA1_ A/QIO0 - - - - H3 72 45 45 - KR03 P103 D03[A 03/D0 3] GTOWUP GTIOC2 A_A CTX0 CTS0_RT S0/SS0 - SSLA0_ A - - - - J1 73 46 46 - KR02 P102 D02[A AGTO0 02/D0 2] GTOWLO GTIOC2 B_A CRX0 SCK0 - RSPCK A_A - ADTRG0 - - H2 74 47 47 - IRQ1/K P101 R01 D01[A AGTEE0 01/D0 1] GTETRGB GTIOC5 A - TXD0/MO CTS1_RT SDA1_ MOSIA_ SI0/SDA0 S1/SS1 B A - - - - H4 75 48 48 - IRQ2/K P100 R00 D00[A AGTIO0 00/D0 0] GTETRGA GTIOC5 B - RXD0/MIS SCK1 O0/SCL0 SCL1_ MISOA_ B A - - - - K1 76 49 49 - - P500 - AGTOA0 GTIU GTIOC11 A USB_V BUSEN - - QSPCL K SD1CLK AN016 _A IVREF0 - J2 77 50 50 - IRQ11 P501 - AGTOB0 GTIV GTIOC11 B USB_O VRCUR A - - QSSL - SD1CMD AN116 _A IVREF1 - K2 78 - - - IRQ12 P502 - - GTIW GTIOC12 A USB_O VRCUR B - - QIO0 - SD1DAT AN017 0_A IVCMP0 - G4 79 - - - - P503 - - GTETRGC GTIOC12 B USB_E XICEN - - QIO1 - SD1DAT AN117 1_A - - G5 80 - - - - P504 ALE - GTETRGD - - USB_ID - - - QIO2 - SD1DAT AN018 2_A - - G6 81 - - - - P508 - - - - - - - - - - - SD1DAT AN020 3_A - - K3 - 82 51 51 VCC - - - - - - - - - - - - - - - - - J3 83 52 52 VSS - - - - - - - - - - - - - - - - - J4 84 53 53 - IRQ13 P015 - - - - - - - - - - - - AN006/A N106 DA1/ IVCMP1 - K4 85 54 54 - - P014 - - - - - - - - - - - - AN005/A N105 DA0/ IVREF3 - J5 86 55 55 VREFL - - - - - - - - - - - - - - - - - K5 87 56 56 VREFH - - - - - - - - - - - - - - - - - H5 88 57 57 AVCC0 - - - - - - - - - - - - - - - - - H6 89 58 58 AVSS0 - - - - - - - - - - - - - - - - - J6 90 59 59 VREFL0 - - - - - - - - - - - - - - - - - K6 91 60 60 VREFH0 - - - - - - - - - - - - - - - - - J7 92 - - - IRQ12- P008 DS - - - - - - - - - - - - AN003 - - H7 93 - - - - P007 - - - - - - - - - - - - PGAVSS1 00/AN107 - G7 94 - - - IRQ11- P006 DS - - - - - - - - - - - - AN102 IVCMP2 - K7 95 - - - IRQ10- P005 DS - - - - - - - - - - - - AN101 IVCMP2 - IVCMP2 - J8 96 - - - IRQ9DS P004 - - - - - - - - - - - - AN100 H8 97 61 61 - - P003 - - - - - - - - - - - - PGAVSS0 00/AN007 - K8 98 62 62 - IRQ8DS P002 - - - - - - - - - - - - AN002 - R01DS0328EU0100 Rev.1.00 Aug 10, 2018 IVCMP2 Page 21 of 92 HMI CTSU DAC12, ACMPHS ADC12 SDHI SSIE SPI, QSPI Analog IIC SCI1,3,9 (30 MHz) USBFS, CAN RTC GPT GPT SCI0,2,4,8 (30 MHz) Communication interfaces AGT I/O port External bus Timers Interrupt QFN64 LQFP64 LGA100 LQFP100 Pin number 1. Overview Power, System, Clock, Debug, CAC S5D3 Datasheet K9 99 63 63 - IRQ7DS P001 - - - - - - - - - - - - AN001 IVCMP2 - K10 100 64 64 - IRQ6DS P000 - - - - - - - - - - - - AN000 IVCMP2 - Note: Some pin names have the added suffix of _A and _B. When assigning the GPT, IIC, SPI, SSIE, and SDHI functionality, select the functional pins with the same suffix. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 22 of 92 S5D3 Datasheet 2. 2. Electrical Characteristics Electrical Characteristics Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:  VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V  2.7 ≤ VREFH0/VREFH ≤ AVCC0  VSS = AVSS0 = VREFL0/VREFL = VSS_USB = 0 V  Ta = Topr. Figure 2.1 shows the timing conditions. For example P100 C VOH = VCC × 0.7, VOL = VCC × 0.3 VIH = VCC × 0.7, VIL = VCC × 0.3 Load capacitance C = 30 pF Figure 2.1 Input or output timing measurement conditions The measurement conditions for the timing specification of each peripheral are recommended for the best peripheral operation. However, make sure to adjust the driving abilities of each pin to meet the conditions of your system. Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function pin is mixed, the A/C specification of each function is not guaranteed. 2.1 Absolute Maximum Ratings Table 2.1 Absolute maximum ratings Parameter Symbol Value Unit Power supply voltage VCC, VCC_USB *2 -0.3 to +4.0 V VBATT power supply voltage VBATT -0.3 to +4.0 V Input voltage (except for 5 V-tolerant ports*1) Vin -0.3 to VCC + 0.3 V Input voltage (5 V-tolerant ports*1) Vin -0.3 to + VCC + 4.0 (max. 5.8) V Reference power supply voltage VREFH/VREFH0 -0.3 to AVCC0 + 0.3 V Analog power supply voltage AVCC0 *2 -0.3 to +4.0 V Analog input voltage (except for P000 to P007) VAN -0.3 to AVCC0 + 0.3 V Analog input voltage (P000 to P007) when PGA differential input is disabled VAN -0.3 to AVCC0 + 0.3 V Analog input voltage (P000 to P002, P004 to P006) when PGA differential input is enabled VAN -1.3 to AVCC0 + 0.3 V Analog input voltage (P003, P007) when PGA differential input is enabled VAN -0.8 to AVCC0 + 0.3 V Operating temperature*3, *4, *5 Topr -40 to +85 -40 to +105 °C Storage temperature Tstg -55 to +125 °C Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 23 of 92 S5D3 Datasheet Note 1. Note 2. Note 3. Note 4. Note 5. 2. Electrical Characteristics Ports P205, P206, P400, P401, P407 to P415, and P708 are 5 V tolerant. Connect AVCC0 and VCC_USB to VCC. See section 2.2.1, Tj/Ta Definition. Contact Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the systematic reduction of load for improved reliability. The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section 1.3, Part Numbering. Table 2.2 Recommended operating conditions Parameter Symbol Value Min Typ Max Unit Power supply voltages VCC When USB is not used 2.7 - 3.6 V When USB is used 3.0 - 3.6 V VSS - 0 - V VCC_USB - VCC - V VSS_USB - 0 - V VBATT power supply voltage VBATT 1.8 - 3.6 V Analog power supply voltages AVCC0*1 - VCC - V AVSS0 - 0 - V USB power supply voltages Note 1. Connect AVCC0 to VCC. When the A/D converter, the D/A converter, or the comparator are not in use, do not leave the AVCC0, VREFH/VREFH0, AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and VREFL/VREFL0 pins to VSS, respectively. 2.2 DC Characteristics 2.2.1 Tj/Ta Definition Table 2.3 DC characteristics Conditions: Products with operating temperature (Ta) -40 to +105°C. Parameter Permissible junction temperature Note: 100-pin LQFP 64-pin LQFP Symbol Typ Max Unit Test conditions Tj - 125 °C High-speed mode Low-speed mode Subosc-speed mode. 64-pin QFN 117 100-pin LGA 105 Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC. The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section 1.3, Part Numbering. 2.2.2 Table 2.4 I/O VIH, VIL I/O VIH, VIL (1 of 2) Parameter Input voltage (except for Schmitt trigger input pins) Peripheral function pin EXTAL(external clock input), WAIT, SPI (except RSPCK) D00 to D07 IIC (SMBus)*1 IIC (SMBus)*2 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Symbo l Min Typ Max Unit VIH VCC × 0.8 - - V VIL - - VCC × 0.2 VIH VCC × 0.7 - - VIL - - VCC × 0.3 VIH 2.1 - - VIL - - 0.8 VIH 2.1 - VCC + 3.6 (max 5.8) VIL - - 0.8 Page 24 of 92 S5D3 Datasheet Table 2.4 2. Electrical Characteristics I/O VIH, VIL (2 of 2) Parameter Schmitt trigger input voltage Peripheral function pin IIC (except for SMBus)*1 IIC (except for SMBus)*2 5 V-tolerant ports*3, *7 RTCIC0, RTCIC1, RTCIC2 When using the battery backup function When VBATT power supply is selected When VCC power supply is selected When not using the battery backup function Other input pins*4 Ports 5 V-tolerant ports*5, *7 Other input Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. pins*6 Symbo l Min Typ Max Unit VIH VCC × 0.7 - - V VIL - - VCC × 0.3 ΔVT VCC × 0.05 - - VIH VCC × 0.7 - VCC + 3.6 (max 5.8) VIL - - VCC × 0.3 ΔVT VCC × 0.05 - - VIH VCC × 0.8 - VCC + 3.6 (max 5.8) VIL - - VCC × 0.2 ΔVT VCC × 0.05 - - VIH VBATT × 0.8 - VBATT + 0.3 VIL - - VBATT × 0.2 ΔVT VBATT × 0.05 - - VIH VCC × 0.8 - Higher voltage either VCC + 0.3 V or VBATT + 0.3 V VIL - - VCC × 0.2 ΔVT VCC × 0.05 - - VIH VCC × 0.8 - VCC + 0.3 VIL - - VCC × 0.2 ΔVT VCC × 0.05 - - VIH VCC × 0.8 - - VIL - - VCC × 0.2 ΔVT VCC × 0.05 - - VIH VCC × 0.8 - VCC + 3.6 (max 5.8) VIL - - VCC × 0.2 VIH VCC × 0.8 - - VIL - - VCC × 0.2 V V SCL1_B, SDA1_B (total 2 pins). SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A (total 6 pins). RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P708 (total 15 pins). All input pins except for the peripheral function pins already described in the table. P205, P206, P400, P401, P407 to P415, P708 (total 14 pins). All input pins except for the ports already described in the table. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur because 5 V-tolerant ports are electrically controlled so as not to violate the breakdown voltage. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 25 of 92 S5D3 Datasheet 2.2.3 2. Electrical Characteristics I/O IOH, IOL Table 2.5 I/O IOH, IOL Parameter Permissible output current (average value per pin) Ports P008, P201 - Ports P014, P015 - Ports P205, P206, P407 to P415, P602, P708 (total 13 pins) Low drive*1 Middle drive*2 High drive*3 Low drive*1 Middle drive*2 High drive*3 Other output pins*4 Permissible output current (max value per pin) Caution: Note 1. Note 2. Note 3. Note 4. Min Typ Max Unit IOH - - -2.0 mA IOL - - 2.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -2.0 mA IOL - - 2.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -20 mA IOL - - 20 mA IOH - - -2.0 mA IOL - - 2.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -16 mA IOL - - 16 mA IOH - - -4.0 mA Ports P008, P201 - IOL - - 4.0 mA Ports P014, P015 - IOH - - -8.0 mA IOL - - 8.0 mA Ports P205, P206, P407 to P415, P602, P708 (total 13 pins) Low drive*1 IOH - - -4.0 mA IOL - - 4.0 mA Middle drive*2 IOH - - -8.0 mA IOL - - 8.0 mA High drive*3 IOH - - -40 mA IOL - - 40 mA Low drive*1 IOH - - -4.0 mA IOL - - 4.0 mA Middle drive*2 IOH - - -8.0 mA IOL - - 8.0 mA High drive*3 IOH - - -32 mA Other output pins*4 Permissible output current (max value of total of all pins) Symbol Maximum of all output pins IOL - - 32 mA ΣIOH (max) - - -80 mA ΣIOL (max) - - 80 mA To protect the reliability of the MCU, the output current values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 μs. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. Except for P000 to P007, P200, which are input ports. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 26 of 92 S5D3 Datasheet 2.2.4 2. Electrical Characteristics I/O VOH, VOL, and Other Characteristics Table 2.6 I/O VOH, VOL, and other characteristics Parameter Output voltage Symbol Min Typ Max Unit Test conditions IIC VOL - - 0.4 V IOL = 3.0 mA VOL - - 0.6 IOL = 6.0 mA IIC*1 VOL - - 0.4 IOL = 15.0 mA (ICFER.FMPE = 1) VOL - 0.4 - IOL = 20.0 mA (ICFER.FMPE = 1) VOH VCC - 1.0 - - IOH = -20 mA VCC = 3.3 V VOL - - 1.0 IOL = 20 mA VCC = 3.3 V Other output pins VOH VCC - 0.5 - - IOH = -1.0 mA VOL - - 0.5 RES |Iin| - - 5.0 Ports P000 to P002, P004 to P006, P200 - - 1.0 Vin = 0 V Vin = VCC Ports P003, P007 Before initialization*3 - - 45.0 Vin = 0 V Vin = VCC After initialization*4 - - 1.0 Vin = 0 V Vin = VCC - - 5.0 - - 1.0 Ports P205, P206, P407 to P415, P602, P708 (total of 13 pins)*2 Input leakage current Three-state leakage current (off state) 5 V-tolerant ports |ITSI| Other ports (except for ports P000 to P007, P200) IOL = 1.0 mA μA μA Vin = 0 V Vin = 5.5 V Vin = 0 V Vin = 5.5 V Vin = 0 V Vin = VCC Input pull-up MOS current Ports P0 to P7 (except for ports P000 to P007) Ip -300 - -10 μA VCC = 2.7 to 3.6 V Vin = 0 V Input capacitance USB_DP, USB_DM, and ports P003, P007, P014, P015, P400, P401 Cin - - 16 pF - - 8 Vbias = 0 V Vamp = 20 mV f = 1 MHz Ta = 25°C Other input pins Note 1. Note 2. Note 3. Note 4. SCL0_A, SDA0_A (total 2 pins). This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving ability is retained in Deep Software Standby mode. P0nPFS.ASEL(n = 3 or 7) = 1 P0nPFS.ASEL(n = 3 or 7) = 0 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 27 of 92 S5D3 Datasheet 2.2.5 2. Electrical Characteristics Operating and Standby Current Table 2.7 Operating and standby current (1 of 2) Parameter Maximum*2 Supply current*1 Symbol Min Typ Max Unit Test conditions ICC*3 - - 87 mA ICLK = 120 MHz PCLKA = 120 MHz PCLKB = 60 MHz PCLKC = 60 MHz PCLKD = 120 MHz FCLK = 60 MHz BCLK = 120 MHz CoreMark®*5 High-speed mode Normal mode - 17 - All peripheral clocks enabled, while (1) code executing from flash*4 - 24 - All peripheral clocks disabled, while (1) code executing from flash*5, *6 - 12 - - 9 33.5 Sleep mode*5, *6 Increase during BGO operation Data flash P/E - 6 - Code flash P/E - 8 - - 1.2 - ICLK = 1 MHz Low-speed mode*5 - 1.0 - ICLK = 32.768 kHz Software Standby mode - 1.3 13 Ta ≤ 85°C - 1.3 21 Power supplied to Standby SRAM and USB resume detecting unit - 28 65 - 28 93 Ta ≤ 105°C Power not supplied to SRAM or USB resume detecting unit Power-on reset circuit low power function disabled - 11.6 28 Ta ≤ 85°C - 11.6 32 Ta ≤ 105°C Power-on reset circuit low power function enabled - 4.9 21 Ta ≤ 85°C - 4.9 26 Ta ≤ 105°C When the low-speed on-chip oscillator (LOCO) is in use - 4.4 - - When a crystal oscillator for low clock loads is in use - 1.0 - - When a crystal oscillator for standard clock loads is in use - 1.4 - - When a crystal oscillator for low clock loads is in use - 0.9 - VBATT = 1.8 V, VCC = 0 V - 1.1 - VBATT = 3.3 V, VCC = 0 V When a crystal oscillator for standard clock loads is in use - 1.0 - VBATT = 1.8 V, VCC = 0 V - 1.6 - VBATT = 3.3 V, VCC = 0 V Deep Software Standby mode Subosc-speed mode*5 Increase when the RTC and AGT are operating RTC operating while VCC is off (with the battery backup function, only the RTC and sub-clock oscillator operate) Analog power supply current Ta ≤ 105°C μA Ta ≤ 85°C - 0.8 1.1 mA During 12-bit A/D conversion with S/H amp - 2.3 3.3 mA - PGA (1ch) - 1 3 mA - ACMPHS (1 unit) - 100 150 µA - Temperature sensor - 0.1 0.2 mA - - 0.1 0.2 mA - During 12-bit A/D conversion During D/A conversion (per unit) AICC Without AMP output With AMP output - - 0.6 1.1 mA Waiting for A/D, D/A conversion (all units) - 0.9 1.6 mA - ADC12, DAC12 in standby modes (all units)*7 - 2 8 µA - - 70 120 μA - Reference power supply current (VREFH0) During 12-bit A/D conversion (unit 0) Reference power supply current (VREFH) During 12-bit A/D conversion (unit 1) AIREFH0 Waiting for 12-bit A/D conversion (unit 0) - 0.07 0.5 μA - ADC12 in standby modes (unit 0) - 0.07 0.5 µA - During D/A conversion (per unit) AIREFH - 70 120 µA - Without AMP output - 0.1 0.4 mA - With AMP ouput - 0.1 0.4 mA - Waiting for 12-bit A/D (unit 1), D/A (all units) conversion - 0.07 0.8 µA - ADC12 unit 1 in standby modes - 0.07 0.8 µA - R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 28 of 92 S5D3 Datasheet Table 2.7 2. Electrical Characteristics Operating and standby current (2 of 2) Parameter USB operating current Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Symbol Min Typ Max Unit Test conditions Low speed USB ICCUSBLS - 3.5 6.5 mA VCC_USB Full speed USB ICCUSBFS - 4.0 10.0 mA VCC_USB Supply current values are with all output pins unloaded and all input pull-up MOS transistors in the off state. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation. ICC depends on f (ICLK) as follows. (ICLK:PCLKA:PCLKB:PCLKC:PCLKD:BCK:EBCLK = 2:2:1:1:2:1:1) ICC Max. = 0.53 x f + 23 (maximum operation in High-speed mode) ICC Typ. = 0.08 x f + 2.4 (normal operation in High-speed mode) ICC Typ. = 0.1 x f + 1.1 (Low-speed mode) ICC Max. = 0.09 x f + 23 (Sleep mode). This does not include the BGO operation. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.75 MHz). When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-bit A/D Converter 0 Module Stop bit) and MSTPCRD.MSTPD15 (12-bit A/D Converter 1 Module Stop bit) are in the module-stop state. See section 42.6.8, Available functions and register settings of AN000 to AN002, AN007, AN100 to AN102, and AN107 in User’s Manual. 100.0 ICC (mA) 10.0 1.0 -40 -20 0.1 0 20 40 60 80 100 Ta (Ԩ) Average value of the tested middle samples during product evaluation. Average value of the tested upper-limit samples during product evaluation. Figure 2.2 Temperature dependency in Software Standby mode (reference data) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 29 of 92 S5D3 Datasheet 2. Electrical Characteristics Figure 2.3 Temperature dependency in Deep Software Standby mode, power supplied to standby SRAM and USB resume detecting unit (reference data) Figure 2.4 Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or USB resume detecting unit, power-on reset circuit low power function disabled (reference data) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 30 of 92 S5D3 Datasheet Figure 2.5 2.2.6 2. Electrical Characteristics Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or USB resume detecting unit, power-on reset circuit low power function enabled (reference data) VCC Rise and Fall Gradient and Ripple Frequency Table 2.8 Rise and fall gradient characteristics Parameter VCC rising gradient Voltage monitor 0 reset disabled at startup Symbol Min Typ Max Unit Test conditions SrVCC 0.0084 - 20 ms/V - 0.0084 - - 0.0084 - 20 0.0084 - - Voltage monitor 0 reset enabled at startup SCI/USB boot mode*1 VCC falling gradient*2 Note 1. Note 2. SfVCC ms/V - At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit. This applies when VBATT is used. Table 2.9 Rise and fall gradient and ripple frequency characteristics The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (2.7 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met. Parameter Symbol Min Typ Max Unit Test conditions Allowable ripple frequency fr (VCC) - - 10 kHz Figure 2.6 Vr (VCC) ≤ VCC × 0.2 - - 1 MHz Figure 2.6 Vr (VCC) ≤ VCC × 0.08 - - 10 MHz Figure 2.6 Vr (VCC) ≤ VCC × 0.06 1.0 - - ms/V When VCC change exceeds VCC ±10% Allowable voltage change rising and falling gradient R01DS0328EU0100 Rev.1.00 Aug 10, 2018 dt/dVCC Page 31 of 92 S5D3 Datasheet 2. Electrical Characteristics 1/fr(VCC) VCC Figure 2.6 2.3 Vr( VCC) Ripple waveform AC Characteristics 2.3.1 Frequency Table 2.10 Operation frequency value in high-speed mode Parameter Symbol Operation frequency System clock (ICLK*2) 120 120 Peripheral module clock (PCLKB)*2 - - 60 Peripheral module clock (PCLKC)*2 -*3 - 60 - - 120 -*1 - 60 (PCLKD)*2 (BCLK)*2 - - 120 - - 60 FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK frequencies. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz. Table 2.11 Operation frequency value in low-speed mode Parameter Operation frequency Symbol System clock (ICLK)*2 Typ Max Unit MHz - - 1 - - 1 Peripheral module clock (PCLKB)*2 - - 1 Peripheral module clock (PCLKC)*2,*3 -*3 - 1 - - 1 - - 1 Peripheral module clock f Min Peripheral module clock (PCLKA)*2 (PCLKD)*2 Flash interface clock (FCLK)*1, *2 Note 3. MHz - External bus clock Note 1. Note 2. Unit - EBCLK pin output Note 3. Max - Flash interface clock (FCLK)*2 Note 1. Note 2. Typ Peripheral module clock (PCLKA)*2 Peripheral module clock f Min External bus clock (BCLK) - - 1 EBCLK pin output - - 1 Programming or erasing the flash memory is disabled in Low-speed mode. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK frequencies. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 32 of 92 S5D3 Datasheet Table 2.12 2. Electrical Characteristics Operation frequency value in Subosc-speed mode Parameter Operation frequency Symbol Min Typ Max Unit f 29.4 - 36.1 kHz Peripheral module clock (PCLKA)*2 - - 36.1 Peripheral module clock (PCLKB)*2 - - 36.1 - - 36.1 - - 36.1 System clock (ICLK)*2 Peripheral module clock (PCLKC)*2,*3 Peripheral module clock (PCLKD)*2 Flash interface clock Note 1. Note 2. Note 3. (FCLK)*1, *2 29.4 - 36.1 External bus clock (BCLK)*2 - - 36.1 EBCLK pin output - - 36.1 Programming or erasing the flash memory is disabled in Subosc-speed mode. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK frequencies. The ADC12 cannot be used. 2.3.2 Table 2.13 Clock Timing Clock timing except for sub-clock oscillator (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions Figure 2.7 EBCLK pin output cycle time tBcyc 16.6 - - ns EBCLK pin output high pulse width tCH 3.3 - - ns EBCLK pin output low pulse width tCL 3.3 - - ns EBCLK pin output rise time tCr - - 5.0 ns EBCLK pin output fall time tCf - - 5.0 ns EXTAL external clock input cycle time tEXcyc 41.66 - - ns EXTAL external clock input high pulse width tEXH 15.83 - - ns EXTAL external clock input low pulse width tEXL 15.83 - - ns EXTAL external clock rise time tEXr - - 5.0 ns EXTAL external clock fall time tEXf - - 5.0 ns Main clock oscillator frequency fMAIN 8 - 24 MHz - Main clock oscillation stabilization wait time (crystal) *1 tMAINOSCWT - - -*1 ms Figure 2.9 LOCO clock oscillation frequency fLOCO 29.4912 32.768 36.0448 kHz - LOCO clock oscillation stabilization wait time tLOCOWT - - 60.4 μs Figure 2.10 ILOCO clock oscillation frequency fILOCO 13.5 15 16.5 kHz - MOCO clock oscillation frequency FMOCO 6.8 8 9.2 MHz - MOCO clock oscillation stabilization wait time tMOCOWT - - 15.0 μs - HOCO clock oscillator oscillation frequency fHOCO16 15.78 16 16.22 MHz -20 ≤ Ta ≤ 105°C fHOCO18 17.75 18 18.25 fHOCO20 19.72 20 20.28 fHOCO16 15.71 16 16.29 fHOCO18 17.68 18 18.32 Without FLL Figure 2.8 -40 ≤ Ta ≤ -20°C fHOCO20 19.64 20 20.36 fHOCO16 15.955 16 16.045 fHOCO18 17.949 18 18.051 fHOCO20 19.944 20 20.056 tHOCOWT - - 64.7 FLL stabilization wait time tFLLWT - - 1.8 ms - PLL clock frequency fPLL 120 - 240 MHz - With FLL HOCO clock oscillation stabilization wait time*2 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 -40 ≤ Ta ≤ 105°C Sub-clock frequency accuracy is ±50 ppm. μs - Page 33 of 92 S5D3 Datasheet Table 2.13 2. Electrical Characteristics Clock timing except for sub-clock oscillator (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions PLL clock oscillation stabilization wait time tPLLWT - - 174.9 μs Figure 2.11 Note 1. Note 2. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as the recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended value. After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm that it is 1, and then start using the main clock oscillator. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed operation. Table 2.14 Clock timing for the sub-clock oscillator Parameter Symbol Min Typ Max Unit Test conditions Sub-clock frequency fSUB - 32.768 - kHz - Sub-clock oscillation stabilization wait time tSUBOSCWT - - -*1 s - Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the recommended oscillation stabilization time. After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after the sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is recommended. tBcyc tCH tCf EBCLK pin output tCL Figure 2.7 tCr EBCLK output timing tEXcyc tEXH EXTAL external clock input VCC × 0.5 tEXr Figure 2.8 tEXL tEXf EXTAL external clock input timing MOSCCR.MOSTP Main clock oscillator output tMAINOSCWT Main clock Figure 2.9 Main clock oscillation start timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 34 of 92 S5D3 Datasheet 2. Electrical Characteristics LOCOCR.LCSTP On-chip oscillator output tLOCOWT LOCO clock Figure 2.10 LOCO clock oscillation start timing PLLCR.PLLSTP PLL circuit output tPLLWT OSCSF.PLLSF PLL clock Figure 2.11 Note: PLL clock oscillation start timing Only operate the PLL after the main clock oscillation has stabilized. SOSCCR.SOSTP tSUBOSC Sub-clock oscillator output Sub-clock Figure 2.12 2.3.3 Table 2.15 Sub-clock oscillation start timing Reset Timing Reset timing (1 of 2) Symbol Min Typ Max Unit Test conditions Power-on tRESWP 1 - - ms Figure 2.13 Deep Software Standby mode tRESWD 0.6 - - ms Figure 2.14 Software Standby mode, Subosc-speed mode tRESWS 0.3 - - ms All other tRESW 200 - - μs tRESWT - 29 32 μs Parameter RES pulse width Wait time after RES cancellation R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Figure 2.13 Page 35 of 92 S5D3 Datasheet Table 2.15 2. Electrical Characteristics Reset timing (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions Wait time after internal reset cancellation (IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error reset, bus master MPU error reset, bus slave MPU error reset, stack pointer error reset) tRESW2 - 320 390 μs - VCC RES Internal reset signal (active-low) tRESWP tRESWT Figure 2.13 Power-on reset timing tRESWD, tRESWS, tRESW RES Internal reset signal (active-low) tRESWT Figure 2.14 2.3.4 Table 2.16 Reset input timing Wakeup Timing Timing of recovery from low power modes (1 of 2) Parameter Recovery time from Software Standby mode*1 Symbol Min Typ Max Unit Crystal resonator connected to main clock oscillator System clock source is main clock oscillator*2 tSBYMC - 2.4*9 2.8*9 ms System clock source is PLL with main clock oscillator*3 tSBYPC - 2.7*9 3.2*9 ms External clock input to main clock oscillator System clock source is main clock oscillator*4 tSBYEX - 230*9 280*9 μs System clock source is PLL with main clock oscillator*5 tSBYPE - 570*9 700*9 μs System clock source is sub-clock oscillator*8 tSBYSC - 1.2*9 1.3*9 ms System clock source is LOCO*8 tSBYLO - 1.2*9 1.4*9 ms 300 *9, *10 µs 300*9 µs HOCO*6 tSBYHO - 240*9, *10 System clock source is MOCO*7 tSBYMO - 220*9 System clock source is R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Test conditions Figure 2.15 The division ratio of all oscillators is 1. Page 36 of 92 S5D3 Datasheet Table 2.16 2. Electrical Characteristics Timing of recovery from low power modes (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Deep Software Standby mode tDSBY - 0.65 1.0 ms Figure 2.16 Wait time after cancellation of Deep Software Standby mode tDSBYWT 34 - 35 tcyc 70 *9, *10 μs 14*9 μs Recovery time from Software Standby mode to Snooze mode High-speed mode when system clock source is HOCO (20 MHz) tSNZ - 35*9, *10 High-speed mode when system clock source is MOCO (8 MHz) tSNZ - 11*9 Figure 2.17 Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined with the following equation: Total recovery time = recovery time for an oscillator as the system clock source + the longest oscillation stabilization time of any oscillators requiring longer stabilization times than the system clock source + 2 LOCO cycles (when LOCO is operating) + 3 SOSC cycles (when Subosc is oscillating and MSTPC0 = 0 (CAC module stop)). Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation: tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR = 05h)) Note 3. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation: tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR = 05h)) Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation: tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 00h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR = 00h)) Note 5. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation: tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 00h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR = 00h)) Note 6. The HOCO frequency is 20 MHz. Note 7. The MOCO frequency is 8 MHz. Note 8. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode. Note 9. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time: STCONR.STCON[1:0] = 00b:16 µs (typical), 34 µs (maximum) STCONR.STCON[1:0] = 11b:16 µs (typical), 104 µs (maximum). Note 10. When the SNZCR.RXDREQEN bit is set to 0, 16 μs (typical) or 18 μs (maximum) is added as the HOCO wait time. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 37 of 92 S5D3 Datasheet 2. Electrical Characteristics Oscillator (system clock) tSBYOSCWT tSBYSEQ Oscillator (not the system clock) ICLK IRQ Software Standby mode tSBYMC, tSBYEX, tSBYPC, tSBYPE, tSBYPH, tSBYSC, tSBYHO, tSBYLO When stabilization of the system clock oscillator is slower Oscillator (system clock) tSBYOSCWT tSBYSEQ Oscillator (not the system clock) tSBYOSCWT ICLK IRQ Software Standby mode tSBYMC, tSBYEX, tSBYPC, tSBYPE, tSBYPH, tSBYSC, tSBYHO, tSBYLO When stabilization of an oscillator other than the system clock is slower Figure 2.15 Software Standby mode cancellation timing Oscillator IRQ Deep Software Standby reset (active-low) Internal reset (active-low) Deep Software Standby mode tDSBY tDSBYWT Reset exception handling start Figure 2.16 Deep Software Standby mode cancellation timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 38 of 92 S5D3 Datasheet 2. Electrical Characteristics Oscillator ICLK(except DTC, SRAM) ICLK(to DTC, SRAM)*1 PCLK IRQ Software Standby mode Snooze mode tSNZ Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM. Figure 2.17 2.3.5 Recovery timing from Software Standby mode to Snooze mode NMI and IRQ Noise Filter Table 2.17 NMI and IRQ noise filter Parameter Symbol Min NMI pulse width tNMIW 200 tPcyc × 2*1 200 - - tNMICK × IRQ pulse width Note: Note 1. Note 2. Note 3. tIRQW Typ 3.5*2 Max Unit Test conditions - - ns NMI digital filter disabled - - - - 200 - - tPcyc × 2*1 - - 200 - - tIRQCK × 3.5*3 - - tPcyc × 2 ≤ 200 ns tPcyc × 2 > 200 ns NMI digital filter enabled tNMICK × 3 ≤ 200 ns IRQ digital filter disabled tPcyc × 2 ≤ 200 ns tNMICK × 3 > 200 ns ns tPcyc × 2 > 200 ns IRQ digital filter enabled tIRQCK × 3 ≤ 200 ns tIRQCK × 3 > 200 ns 200 ns minimum in Software Standby mode. tPcyc indicates the PCLKB cycle. tNMICK indicates the cycle of the NMI digital filter sampling clock. tIRQCK indicates the cycle of the IRQi digital filter sampling clock. NMI tNMIW Figure 2.18 NMI interrupt input timing IRQ tIRQW Figure 2.19 IRQ interrupt input timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 39 of 92 S5D3 Datasheet 2.3.6 2. Electrical Characteristics Bus Timing Table 2.18 Bus timing Conditions: BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz. VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0. Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF. EBCLK: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Others: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions Address delay tAD - 12.5 ns CS delay tCSD - 12.5 ns Figure 2.22 to Figure 2.25 ALE delay time tALED - 12.5 ns RD delay tRSD - 12.5 ns Read data setup time tRDS 12.5 - ns Read data hold time tRDH 0 - ns WR0 delay tWRD - 12.5 ns Write data delay tWDD - 12.5 ns Write data hold time tWDH 0 - ns WAIT setup time tWTS 12.5 - ns WAIT hold time tWTH 0 - ns Figure 2.26 Data cycle Address cycle Ta1 Ta1 Tan TW1 TW2 TW3 TW4 TW5 Tend Tn1 Tn2 EBCLK tAD Address bus Address bus/ data bus tAD tRDS tAD tALED tRDH tALED Address latch (ALE) tRSD tRSD Data read (RD) tCSD Chip select (CSn) Figure 2.20 tCSD Address/data multiplexed bus read access timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 40 of 92 S5D3 Datasheet 2. Electrical Characteristics Data cycle Address cycle Ta1 Ta1 Tan TW1 TW2 TW3 TW4 TW5 Tend Tn1 Tn2 Tn3 EBCLK tAD Address bus Address bus/ data bus tAD tAD tALED tWDD tWDH tALED Address latch (ALE) tWRD tWRD Data write (WR0) tCSD Chip select (CSn) Figure 2.21 tCSD Address/data multiplexed bus write access timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 41 of 92 S5D3 Datasheet 2. Electrical Characteristics CSRWAIT: 2 RDON:1 CSROFF: 2 CSON: 0 TW1 TW2 Tend Tn1 Tn2 EBCLK tAD tAD A12 to A00 tCSD tCSD CS7 to CS4, CS1, CS0 tRSD tRSD RD (read) tRDS tRDH D07 to D00 (read) Figure 2.22 External bus timing for normal read cycle with bus clock synchronized R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 42 of 92 S5D3 Datasheet 2. Electrical Characteristics CSWWAIT: 2 WRON: 1 WDON: 1*1 CSWOFF: 2 WDOFF: 1*1 CSON:0 TW1 TW2 Tend Tn1 Tn2 EBCLK tAD tAD A12 to A00 tCSD tCSD CS7 to CS4, CS1, CS0 tWRD tWRD WR0 (write) tWDD tWDH D07 to D00 (write) Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle. Figure 2.23 External bus timing for normal write cycle with bus clock synchronized R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 43 of 92 S5D3 Datasheet 2. Electrical Characteristics CSRWAIT:2 CSPRWAIT:2 RDON:1 CSON:0 TW1 TW2 Tend CSPRWAIT:2 CSPRWAIT:2 RDON:1 RDON:1 Tpw1 Tpw2 Tend CSROFF:2 RDON:1 Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tn1 Tn2 EBCLK tAD tAD tAD tAD tAD A12 to A00 tCSD tCSD CS7 to CS4, CS1, CS0 tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD RD (Read) tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH D07 to D00 (Read) Figure 2.24 External bus timing for page read cycle with bus clock synchronized CSPWWAIT:2 CSWWAIT:2 WRON:1 WDON:1*1 CSON:0 TW1 WDOFF:1*1 TW2 Tend Tdw1 WRON:1 WDON:1*1 Tpw1 CSPWWAIT:2 WDOFF:1*1 Tpw2 Tend Tdw1 WRON:1 WDON:1*1 Tpw1 CSWOFF:2 WDOFF:1*1 Tpw2 Tend Tn1 Tn2 EBCLK tAD tAD tAD tAD A12 to A00 tCSD tCSD CS7 to CS4, CS1, CS0 tWRD tWRD tWRD tWRD tWRD tWRD WR0 (write) tWDD tWDH tWDD tWDH tWDD tWDH D07 to D00 (write) Note 1. Figure 2.25 Always specify WDON and WDOFF as at least one EBCLK cycle. External bus timing for page write cycle with bus clock synchronized R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 44 of 92 S5D3 Datasheet 2. Electrical Characteristics CSRWAIT:3 CSWWAIT:3 TW1 TW2 TW3 (Tend) Tend Tn1 Tn2 EBCLK A12 to A00 CS7 to CS4, CS1, CS0 RD (read) WR0 (write) External wait tWTS tWTH tWTS tWTH WAIT Figure 2.26 2.3.7 Table 2.19 External bus timing for external wait control I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (1 of 2) GPT32 conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. AGT conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions I/O ports Input data pulse width tPRW 1.5 - tPcyc Figure 2.27 POEG POEG input trigger pulse width tPOEW 3 - tPcyc Figure 2.28 GPT32 Input capture pulse width tGTICW 1.5 - tPDcyc Figure 2.29 2.5 - - 4 ns Figure 2.30 Single edge Dual edge GPT (PWM Delay Generation Circuit) tGTISK*2 GTIOCxY output skew (x = 0 to 7, Y= A or B) Middle drive buffer High drive buffer - 4 GTIOCxY output skew (x = 8 to 12, Y = A or B) Middle drive buffer - 4 High drive buffer - 4 GTIOCxY output skew (x = 0 to 12, Y = A or B) Middle drive buffer - 6 High drive buffer - 6 OPS output skew GTOUUP, GTOULO, GTOVUP, GTOVLO, GTOWUP, GTOWLO tGTOSK - 5 ns Figure 2.31 GTIOCxY_Z output skew (x = 0 to 3, Y = A or B, Z = A) tHRSK*3 - 2.0 ns Figure 2.32 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 45 of 92 S5D3 Datasheet Table 2.19 2. Electrical Characteristics I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (2 of 2) GPT32 conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. AGT conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Symbol Min Max Unit Test conditions AGTIO, AGTEE input cycle tACYC*4 100 - ns Figure 2.33 AGTIO, AGTEE input high width, low width tACKWH, tACKWL 40 - ns Parameter AGT AGTIO, AGTO, AGTOA, AGTOB output cycle tACYC2 62.5 - ns ADC12 ADC12 trigger input pulse width tTRGW 1.5 - tPcyc Figure 2.34 KINT KRn(n = 00 to 07) pulse width tKR 250 - ns Figure 2.35 Note 1. Note 2. Note 3. Note 4. tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed. The load is 30 pF. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC. Port tPRW Figure 2.27 I/O ports input timing POEG input trigger tPOEW Figure 2.28 POEG input trigger timing Input capture tGTICW Figure 2.29 GPT32 input capture timing PCLKD Output delay GPT32 output tGTISK Figure 2.30 GPT32 output delay skew R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 46 of 92 S5D3 Datasheet 2. Electrical Characteristics PCLKD Output delay GPT32 output tGTOSK Figure 2.31 GPT32 output delay skew for OPS PCLKD Output delay GPT32 output (PWM delay generation circuit) tHRSK Figure 2.32 GPT32 (PWM delay generation circuit) output delay skew tACYC tACKWL tACKWH AGTIO, AGTEE (input) tACYC2 AGTIO, AGTO, AGTOA, AGTOB (output) Figure 2.33 AGT input/output timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 47 of 92 S5D3 Datasheet 2. Electrical Characteristics ADTRG0, ADTRG1 tTRGW Figure 2.34 ADC12 trigger input timing KR00 to KR07 tKR Figure 2.35 2.3.8 Key interrupt input timing PWM Delay Generation Circuit Timing Table 2.20 PWM Delay Generation Circuit timing Parameter Min Typ Max Unit Test conditions Operation frequency 80 - 120 MHz - Resolution - 260 - ps PCLKD = 120 MHz DNL*1 - ±2.0 - LSB - Note 1. This value normalizes the differences between lines in 1-LSB resolution. 2.3.9 CAC Timing Table 2.21 CAC timing Parameter CAC CACREF input pulse width tPBcyc ≤ tcac*2 tPBcyc > Note 1. Note 2. tcac*2 Symbol Min Typ Max Unit Test conditions tCACREF 4.5 × tcac + 3 × tPBcyc - - ns - 5 × tcac + 6.5 × tPBcyc - - ns tPBcyc: PCLKB cycle. tcac: CAC count clock source cycle. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 48 of 92 S5D3 Datasheet 2.3.10 2. Electrical Characteristics SCI Timing Table 2.22 SCI timing (1) Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SCK0 to SCK4, SCK8, SCK9. For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter SCI Input clock cycle Asynchronous Unit*1 Test conditions 4 - tPcyc Figure 2.36 6 - Min tScyc Clock synchronous Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr - 5 ns tSCKf - 5 ns tScyc 6 - tPcyc 4 - Input clock fall time Output clock cycle Asynchronous Clock synchronous Note 1. Max Symbol Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr - 5 ns Output clock fall time tSCKf - 5 ns Transmit data delay Clock synchronous tTXD - 25 ns Receive data setup time Clock synchronous tRXS 15 - ns Receive data hold time Clock synchronous tRXH 5 - ns Figure 2.37 tPcyc: PCLKA cycle. tSCKW tSCKr tSCKf SCKn (n = 0 to 4, 8, 9) tScyc Figure 2.36 SCK clock input/output timing SCKn tTXD TxDn tRXS tRXH RxDn (n = 0 to 4, 8, 9) Figure 2.37 SCI input/output timing in clock synchronous mode R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 49 of 92 S5D3 Datasheet Table 2.23 2. Electrical Characteristics SCI timing (2) Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SCK0 to SCK4, SCK8, SCK9. For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions Simple SPI tSPcyc 4 (PCLKA ≤ 60 MHz) 8 (PCLKA > 60 MHz) 65536 tPcyc Figure 2.38 SCK clock cycle input (slave) - 6 (PCLKA ≤ 60 MHz) 12 (PCLKA > 60 MHz) 65536 SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc SCK clock rise and fall time tSPCKr, tSPCKf - 20 ns Data input setup time tSU 33.3 - ns Data input hold time tH 33.3 - ns SS input setup time tLEAD 1 - tSPcyc SS input hold time tLAG 1 - tSPcyc Data output delay tOD - 33.3 ns Data output hold time tOH -10 - ns Data rise and fall time tDr, tDf - 16.6 ns SS input rise and fall time tSSLr, tSSLf - 16.6 ns Slave access time tSA - 4 (PCLKA ≤ 60 MHz) 8 (PCLKA > 60 MHz) tPcyc Slave output release time tREL - 5 (PCLKA ≤ 60 MHz) 10 (PCLKA > 60 MHz) tPcyc SCK clock cycle output (master) tSPCKr tSPCKWH SCKn master select output VOH VOH VOL Figure 2.39 to Figure 2.42 Figure 2.42 tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH SCKn slave select input VIH VIL (n = 0 to 4, 8, 9) tSPCKf VIH VIL tSPCKWL VIH VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC Figure 2.38 SCI simple SPI mode clock timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 50 of 92 S5D3 Datasheet 2. Electrical Characteristics SCKn CKPOL = 0 output SCKn CKPOL = 1 output tSU MISOn input tH MSB IN DATA tDr, tDf MOSIn output tOH MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT (n = 0 to 4, 8, 9) Figure 2.39 SCI simple SPI mode timing for master when CKPH = 1 SCKn CKPOL = 1 output SCKn CKPOL = 0 output tSU MISOn input tH MSB IN tOH DATA LSB IN tOD MOSIn output MSB IN tDr, tDf MSB OUT DATA LSB OUT IDLE MSB OUT (n = 0 to 4, 8, 9) Figure 2.40 SCI simple SPI mode timing for master when CKPH = 0 tTD SSn input tLEAD tLAG SCKn CKPOL = 0 input SCKn CKPOL = 1 input tSA tOH MISOn output MSB OUT tSU MOSIn input tOD DATA tREL LSB OUT tH MSB IN MSB IN MSB OUT tDr, tDf DATA LSB IN MSB IN (n = 0 to 4, 8, 9) Figure 2.41 SCI simple SPI mode timing for slave when CKPH = 1 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 51 of 92 S5D3 Datasheet 2. Electrical Characteristics tTD SSn input tLEAD tLAG SCKn CKPOL = 1 input SCKn CKPOL = 0 input tSA tOH tOD LSB OUT (Last data) MISOn output MSB OUT tSU MOSIn input tREL LSB OUT DATA tH MSB OUT tDr, tDf MSB IN DATA LSB IN MSB IN (n = 0 to 4, 8, 9) Figure 2.42 Table 2.24 SCI simple SPI mode timing for slave when CKPH = 0 SCI timing (3) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Simple IIC (Standard mode) Simple IIC (Fast mode) Note: Note 1. Symbol Min Max Unit Test conditions Figure 2.43 SDA input rise time tSr - 1000 ns SDA input fall time tSf - 300 ns SDA input spike pulse removal time tSP 0 4 × tIICcyc ns Data input setup time tSDAS 250 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb*1 - 400 pF SDA input rise time tSr - 300 ns SDA input fall time tSf - 300 ns SDA input spike pulse removal time tSP 0 4 × tIICcyc ns Data input setup time tSDAS 100 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb*1 - 400 pF Figure 2.43 tIICcyc: IIC internal reference clock (IICφ) cycle. Cb indicates the total capacity of the bus line. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 52 of 92 S5D3 Datasheet 2. Electrical Characteristics VIH SDAn VIL tSr tSf tSP SCLn (n = 0 to 4, 8, 9) P*1 S*1 tSDAH Note 1. S, P, and Sr indicate the following: S: Start condition P: Stop condition Sr: Restart condition Figure 2.43 P*1 Sr*1 tSDAS Test conditions: VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6 V, IOL = 6 mA SCI simple IIC mode timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 53 of 92 S5D3 Datasheet 2.3.11 2. Electrical Characteristics SPI Timing Table 2.25 SPI timing Conditions: For RSPCKA and RSPCKB pins, high drive output is selected with the Port Drive Capability bit in the PmnPFS register. For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. Symbol Min Max Unit*1 Test conditions*2 tSPcyc 2 (PCLKA  60 MHz) 4 (PCLKA > 60 MHz) 4096 tPcyc Figure 2.44 C = 30 pF 4 4096 (tSPcyc - tSPCKr tSPCKf) / 2 - 3 - 2 × tPcyc - tSPCKWL (tSPcyc - tSPCKr tSPCKf) / 2 - 3 - 2 × tPcyc - - 5 ns Slave tSPCKr, tSPCKf - 1 µs Master tSU ns Parameter SPI RSPCK clock cycle Master Slave RSPCK clock high pulse width Master tSPCKWH Slave RSPCK clock low pulse width Master Slave RSPCK clock rise and fall time Data input setup time Master Slave Data input hold time SSL setup time tHF 0 - Master (PCLKA division ratio set to a value other than 1/2) tH tPcyc - Slave tH 20 - Master tLEAD N × tSPcyc - 10*3 N× tSPcyc + 100*3 ns 6 x tPcyc - ns N× tSPcyc + 100*4 ns 6 x tPcyc - ns - 6.3 ns Master tLAG Slave Data output delay Master Data output hold time Master tOD Slave tOH Slave Successive transmission delay Master tTD Slave MOSI and MISO rise and fall time Output SSL rise and fall time Output N × tSPcyc - 10 *4 Figure 2.45 to Figure 2.50 C = 30 pF ns - 20 0 - 0 - tSPcyc + 2 × tPcyc 8× tSPcyc + 2 × tPcyc ns 5 ns ns 6 × tPcyc tDr, tDf - 1 μs tSSLr, tSSLf - 5 ns - 1 μs Slave access time tSA - 2 x tPcyc + 28 ns Slave output release time tREL - 2 x tPcyc + 28 Input Input Note 1. - ns Master (PCLKA division ratio set to 1/2) Slave SSL hold time 4 5 ns Figure 2.49 and Figure 2.50 C = 30PF tPcyc: PCLKA cycle. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 54 of 92 S5D3 Datasheet Note 2. Note 3. Note 4. 2. Electrical Characteristics Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SPI interface, the AC portion of the electrical characteristics is measured for each group. N is set to an integer from 1 to 8 by the SPCKD register. N is set to an integer from 1 to 8 by the SSLND register. tSPCKr tSPCKWH SPI VOH RSPCKn master select output VOH tSPCKf VOH VOL VOH VOL VOL tSPCKWL tSPcyc tSPCKr tSPCKWH VIH VIH RSPCKn slave select input tSPCKf VIH VIL VIH VIL VIL tSPCKWL tSPcyc n = A or B VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC Figure 2.44 SPI clock timing SPI tTD SSLn0 to SSLn3 output tLEAD t LAG tSSLr, t SSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output t SU MISOn input tH MSB IN tDr, t Df MOSIn output DATA tOH MSB OUT LSB IN MSB IN t OD DATA LSB OUT IDLE MSB OUT n = A or B Figure 2.45 SPI timing for master when CPHA = 0 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 55 of 92 S5D3 Datasheet 2. Electrical Characteristics SPI SSLn0 to SSLn3 output tTD tLEAD t LAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn input tHF tHF MSB IN tDr, tDf MOSIn output LSB IN DATA tOH MSB OUT MSB IN t OD DATA LSB OUT IDLE MSB OUT n = A or B Figure 2.46 SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2 SPI tTD SSLn0 to SSLn3 output t LEAD tLAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn input tH MSB IN tOH MOSIn output DATA LSB IN tOD MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT n = A or B Figure 2.47 SPI timing for master when CPHA = 1 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 56 of 92 S5D3 Datasheet 2. Electrical Characteristics SPI tTD SSLn0 to SSLn3 output tLEAD tLAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn input tHF MSB IN tOH tH DATA LSB IN tOD MOSIn output MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT n = A or B Figure 2.48 RSPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2 SPI tTD SSLn0 input tLEAD tLAG RSPCKn CPOL = 0 input RSPCKn CPOL = 1 input tSA tOH MISOn output MSB OUT tSU MOSIn input tOD DATA tREL LSB OUT tH MSB IN MSB IN MSB OUT tDr, tDf DATA LSB IN MSB IN n = A or B Figure 2.49 SPI timing for slave when CPHA = 0 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 57 of 92 S5D3 Datasheet 2. Electrical Characteristics SPI tTD SSLAn input tLEAD tLAG RSPCKn CPOL = 0 input RSPCKn CPOL = 1 input tSA tOH MISOn output tOD LSB OUT (last data) MSB OUT tSU MOSIn input tREL LSB OUT DATA MSB OUT tDr, tDf tH MSB IN DATA LSB IN MSB IN n = A or B Figure 2.50 2.3.12 SPI timing for slave when CPHA = 1 QSPI Timing Table 2.26 QSPI timing Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit*1 Test conditions QSPI tQScyc 2 48 tPcyc Figure 2.51 Note 1. Note 2. Note 3. QSPCK clock cycle QSPCK clock high pulse width tQSWH tQScyc × 0.4 - ns QSPCK clock low pulse width tQSWL tQScyc × 0.4 - ns Data input setup time tSu 8 - ns Data input hold time tIH 0 - ns QSSL setup time tLEAD (N+0.5) x tQscyc - 5 *2 (N+0.5) x tQscyc +100 *2 ns QSSL hold time tLAG (N+0.5) x tQscyc - 5 *3 (N+0.5) x tQscyc +100 *3 ns Data output delay tOD - 4 ns Data output hold time tOH -3.3 - ns Successive transmission delay tTD 1 16 tQScyc Figure 2.52 tPcyc: PCLKA cycle. N is set to 0 or 1 in SFMSLD. N is set to 0 or 1 in SFMSHD. tQSWH tQSWL QSPCLK output tQScyc Figure 2.51 QSPI clock timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 58 of 92 S5D3 Datasheet 2. Electrical Characteristics tTD QSSL output tLEAD tLAG QSPCLK output tSU QIO0-3 input tH MSB IN DATA tOH QIO0-3 output Figure 2.52 2.3.13 Table 2.27 LSB IN tOD MSB OUT DATA LSB OUT IDLE Transmit and receive timing IIC Timing IIC timing (1) (1 of 2) (1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B. (2) The following pins do not require setting: SCL0_A, SDA0_A. (3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Symbol Min*1 Max Unit Test conditions*3 SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 - ns Figure 2.53 SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time tSr - 1000 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time when wakeup function is disabled tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time when wakeup function is enabled tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 - ns START condition input hold time when wakeup function is disabled tSTAH tIICcyc + 300 - ns START condition input hold time when wakeup function is enabled tSTAH 1 (5) × tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time tSTOS 1000 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 400 pF Parameter IIC (Standard mode, SMBus) ICFER.FMPE = 0 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 59 of 92 S5D3 Datasheet Table 2.27 2. Electrical Characteristics IIC timing (1) (2 of 2) (1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B. (2) The following pins do not require setting: SCL0_A, SDA0_A. (3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Symbol Min*1 Max Unit Test conditions*3 SCL input cycle time tSCL 6 (12) × tIICcyc + 600 - ns Figure 2.53 SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time tSr 20 × (external pullup voltage/5.5V)*2 300 ns SCL, SDA input fall time tSf 20 × (external pullup voltage/5.5V)*2 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time when wakeup function is disabled tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time when wakeup function is enabled tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 - ns START condition input hold time when wakeup function is disabled tSTAH tIICcyc + 300 - ns START condition input hold time when wakeup function is enabled tSTAH 1 (5) × tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time tSTOS 300 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 400 pF Parameter IIC (Fast mode) Note: Note 1. Note 2. Note 3. tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Only supported for SCL0_A, SDA0_A. Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 60 of 92 S5D3 Datasheet Table 2.28 2. Electrical Characteristics IIC timing (2) Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register. Symbol Min*1,*2 Max Unit Test conditions SCL input cycle time tSCL 6 (12) × tIICcyc + 240 - ns Figure 2.53 SCL input high pulse width tSCLH 3 (6) × tIICcyc + 120 - ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 120 - ns SCL, SDA input rise time tSr - 120 ns SCL, SDA input fall time tSf - 120 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time when wakeup function is disabled tBUF 3 (6) × tIICcyc + 120 - ns SDA input bus free time when wakeup function is enabled tBUF 3 (6) × tIICcyc + 4 × tPcyc + 120 - ns Start condition input hold time when wakeup function is disabled tSTAH tIICcyc + 120 - ns START condition input hold time when wakeup function is enabled tSTAH 1 (5) × tIICcyc + tPcyc + 120 - ns Restart condition input setup time tSTAS 120 - ns Stop condition input setup time tSTOS 120 - ns Parameter IIC (Fast mode+) ICFER.FMPE = 1 Note: Note 1. Note 2. Data input setup time tSDAS tIICcyc + 30 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 550 pF tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Cb indicates the total capacity of the bus line. VIH SDA0, SDA1 VIL tBUF tSCLH tSTAH tSTAS tSTOS tSP SCL0, SCL1 P*1 S*1 tSf tSCLL tSr tSCL tSDAS tSDAH Note 1. S, P, and Sr indicate the following: S: Start condition P: Stop condition Sr: Restart condition Figure 2.53 P*1 Sr*1 Test conditions: VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0) VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1) I2C bus interface input/output timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 61 of 92 S5D3 Datasheet 2.3.14 2. Electrical Characteristics SSIE Timing Table 2.29 SSIE timing (1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register. (2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the AC portion of the electrical characteristics is measured for each group. Target specification Parameter SSIBCK0 Symbol Min. Max. Unit Comments Master tO 80 - ns Figure 2.54 Slave tI 80 - ns High level/low level Master tHC/tLC 0.35 - tO 0.35 - tI Rising time/falling time Master - 0.15 tO / tI - 0.15 tO / tI Cycle Slave tRC/tFC Slave SSILRCK0/SSIFS0, SSITXD0, SSIRXD0 Input set up time Master tSR 12 - ns 12 - ns 8 - ns 15 - ns -10 5 ns 0 20 ns Figure 2.56, Figure 2.57 tDTRW - 20 ns Figure 2.58*1 Cycle tEXcyc 20 - ns Figure 2.55 High level/low level tEXL/ tEXH 0.4 0.6 tEXcyc Slave Input hold time Master Output delay time Master tHR Slave tDTR Slave Output delay time from SSILRCK0/SSIFS0 change GTIOC1A, AUDIO_CLK Note 1. Slave Figure 2.56, Figure 2.57 For slave-mode transmission, SSIE has a path through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate transmit data, and the transmit data is logically output to the SSITXD0 pin. tHC SSIBCK0 tRC tFC tLC tO, tI Figure 2.54 SSIE clock input/output timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 62 of 92 S5D3 Datasheet 2. Electrical Characteristics tEXcyc tEXH tEXL GTIOC1A, AUDIO_CLK (input) 1/2 VCC tEXf Figure 2.55 tEXr Clock input timing SSIBCK0 (input or output) SSILRCK0/SSIFS0 (input), SSIRXD0 (input) tSR tHR SSILRCK0/SSIFS0 (output), SSITXD0 (output) tDTR Figure 2.56 SSIE data transmit and receive timing when SSICR.BCKP = 0 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 63 of 92 S5D3 Datasheet 2. Electrical Characteristics SSIBCK0 (input or output) SSILRCK0/SSIFS0 (input), SSIRXD0 (input) tSR tHR SSILRCK0/SSIFS0 (output), SSITXD0 (output) tDTR Figure 2.57 SSIE data transmit and receive timing when SSICR.BCKP = 1 SSILRCK0/SSIFS0 (input) SSITXD0 (output) tDTRW MSB bit output delay after SSILRCK0/SSIFS0 change for slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR. Figure 2.58 2.3.15 Table 2.30 SSIE data output delay after SSILRCK0/SSIFS0 change SD/MMC Host Interface Timing SD/MMC Host Interface signal timing Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Clock duty ratio is 50%. Parameter Symbol Min Max Unit Test conditions*1 SDCLK clock cycle TSDCYC 20 - ns Figure 2.59 SDCLK clock high pulse width TSDWH 6.5 - ns SDCLK clock low pulse width TSDWL 6.5 - ns SDCLK clock rise time TSDLH - 3 ns SDCLK clock fall time TSDHL - 3 ns SDCMD/SDDAT output data delay TSDODLY -6 5 ns SDCMD/SDDAT input data setup TSDIS 4 - ns SDCMD/SDDAT input data hold TSDIH 2 - ns Note 1. Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SD/MMC Host interface, the AC portion of the electrical characteristics is measured for each group. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 64 of 92 S5D3 Datasheet 2. Electrical Characteristics T SD C YC T SD W L SDnCLK (output) T SD HL T SD W H T SD LH T SD O D LY(m ax) T SD O DLY(m in) SD nCM D /SDnDATm (output) T SD IS T SD IH SD nCM D /SDnDATm (input) n = 0, 1, m = 0 to 3 Figure 2.59 2.4 SD/MMC Host Interface signal timing USB Characteristics 2.4.1 Table 2.31 USBFS Timing USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics) Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, UCLK = 48 MHz Parameter Input characteristics Output characteristics Pull-up and pulldown characteristics Symbol Min Typ Max Unit Test conditions Input high voltage VIH 2.0 - - V - Input low voltage VIL - - 0.8 V - Differential input sensitivity VDI 0.2 - - V | USB_DP - USB_DM | Differential common-mode range VCM 0.8 - 2.5 V - Output high voltage VOH 2.8 - 3.6 V IOH = -200 μA Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA Cross-over voltage VCRS 1.3 - 2.0 V Figure 2.60 Rise time tLR 75 - 300 ns Fall time tLF 75 - 300 ns Rise/fall time ratio tLR / tLF 80 - 125 % tLR/ tLF USB_DP and USB_DM pulldown resistance in host controller mode Rpd 14.25 - 24.80 kΩ - USB_DP, USB_DM VCRS 90% 90% 10% tLR Figure 2.60 10% tLF USB_DP and USB_DM output timing in low-speed mode R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 65 of 92 S5D3 Datasheet 2. Electrical Characteristics Observation point USB_DP 200 pF to 600 pF 27  3.6 V 1.5 K USB_DM 200 pF to 600 pF Figure 2.61 Table 2.32 Test circuit in low-speed mode USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics) Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, UCLK = 48 MHz Parameter Input characteristics Output characteristics Pull-up and pulldown characteristics Symbol Min Typ Max Unit Test conditions Input high voltage VIH 2.0 - - V - Input low voltage VIL - - 0.8 V - Differential input sensitivity VDI 0.2 - - V | USB_DP - USB_DM | Differential common-mode range VCM 0.8 - 2.5 V - Output high voltage VOH 2.8 - 3.6 V IOH = -200 μA Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA Cross-over voltage VCRS 1.3 - 2.0 V Figure 2.62 Rise time tLR 4 - 20 ns Fall time tLF 4 - 20 ns Rise/fall time ratio tLR / tLF 90 - 111.11 % Output resistance ZDRV 28 - 44 Ω USBFS: Rs = 27 Ω included DM pull-up resistance in device controller mode Rpu 0.900 - 1.575 kΩ During idle state 1.425 - 3.090 kΩ During transmission and reception USB_DP and USB_DM pulldown resistance in host controller mode Rpd 14.25 - 24.80 kΩ - USB_DP, USB_DM VCRS 90% 90% 10% tFR Figure 2.62 tFR/ tFF 10% tFF USB_DP and USB_DM output timing in full-speed mode R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 66 of 92 S5D3 Datasheet 2. Electrical Characteristics Observation point USB_DP 50 pF 27  USB_DM 50 pF Figure 2.63 2.5 Test circuit in full-speed mode ADC12 Characteristics Table 2.33 A/D conversion characteristics for unit 0 (1 of 2) Conditions: PCLKC = 1 to 60 MHz Parameter Min Typ Max Unit Frequency 1 - 60 MHz Test conditions - Analog input capacitance - - 30 pF - Quantization error - ±0.5 - LSB - Resolution - - 12 Bits - 1.06 (0.4 + 0.25)*2 - - μs  Sampling of channeldedicated sample-and-hold circuits in 24 states  Sampling in 15 states Offset error - ±1.5 ±3.5 LSB AN000 to AN002 = 0.25 V Full-scale error - ±1.5 ±3.5 LSB AN000 to AN002 = VREFH0- 0.25 V Absolute accuracy - ±2.5 ±5.5 LSB - DNL differential nonlinearity error - ±1.0 ±2.0 LSB - INL integral nonlinearity error - ±1.5 ±3.0 LSB - Holding characteristics of sample-and hold circuits - - 20 μs - Dynamic range 0.25 - VREFH0 - 0.25 V - 0.48 (0.267)*2 - - μs Sampling in 16 states Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - Conversion time*1 (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.48 (0.267)*2 - - μs Sampling in 16 states Max. = 400 Ω 0.40 (0.183)*2 - - μs Sampling in 11 states VCC = AVCC0 = 3.0 to 3.6 V 3.0 V ≤ VREFH0 ≤ AVCC0 - ±1.0 ±2.5 LSB - Channel-dedicated sample-and-hold circuits in use*3 (AN000 to AN002) Channel-dedicated sample-and-hold circuits not in use (AN000 to AN002) High-precision channels (AN003, AN005, AN006) Conversion time*1 (operation at PCLKC = 60 MHz) Conversion time*1 (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ Permissible signal source impedance Max. = 1 kΩ Offset error Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL differential nonlinearity error - ±0.5 ±1.5 LSB - R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 67 of 92 S5D3 Datasheet Table 2.33 2. Electrical Characteristics A/D conversion characteristics for unit 0 (2 of 2) Conditions: PCLKC = 1 to 60 MHz Parameter High-precision channels (AN007) Min Typ Max INL integral nonlinearity error - ±1.0 Conversion time*1 (operation at PCLKC = 60 MHz) 0.75 (0.533)*2 - - ±1.0 Permissible signal source impedance Max. = 1 kΩ Offset error Note: Note 1. Note 2. Note 3. Test conditions ±2.5 LSB - - μs Sampling in 32 states ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - - - μs Sampling in 40 states ±1.0 ±5.5 LSB - time*1 Normal-precision channels (AN016 to AN018, AN020) Unit Conversion (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.88 Offset error (0.667)*2 - Full-scale error - ±1.0 ±5.5 LSB - Absolute accuracy - ±2.0 ±7.5 LSB - DNL differential nonlinearity error - ±0.5 ±4.5 LSB - INL integral nonlinearity error - ±1.0 ±5.5 LSB - These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D conversion, the values might not fall within the indicated ranges. The use of ports 0 as digital outputs is not allowed when the 12-bit A/D converter is used. The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are stable. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test conditions. Values in parentheses indicate the sampling time. When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.35. Table 2.34 A/D conversion characteristics for unit 1 (1 of 2) Conditions: PCLKC = 1 to 60 MHz Parameter Min Typ Max Unit Frequency 1 - 60 MHz Test conditions - Analog input capacitance - - 30 pF - Quantization error - ±0.5 - LSB - Resolution - - 12 Bits - 1.06 (0.4 + 0.25)*2 - - μs  Sampling of channeldedicated sample-and-hold circuits in 24 states  Sampling in 15 states Channel-dedicated sample-and-hold circuits in use*3 (AN100 to AN102) Conversion time*1 (operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ Offset error - ±1.5 ±3.5 LSB AN100 to AN102 = 0.25 V Full-scale error - ±1.5 ±3.5 LSB AN100 to AN102 = VREFH - 0.25 V Absolute accuracy - ±2.5 ±5.5 LSB - DNL differential nonlinearity error - ±1.0 ±2.0 LSB - INL integral nonlinearity error - ±1.5 ±3.0 LSB - Holding characteristics of sample-and hold circuits - - 20 μs - Dynamic range 0.25 - VREFH - 0.25 V - R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 68 of 92 S5D3 Datasheet Table 2.34 2. Electrical Characteristics A/D conversion characteristics for unit 1 (2 of 2) Conditions: PCLKC = 1 to 60 MHz Parameter Channel-dedicated sample-and-hold circuits not in use (AN100 to AN102) High-precision channels (AN105, AN106) High-precision channels (AN107) Normal-precision channels (AN116, AN117) time*1 Conversion (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ Note 1. Note 2. Note 3. Typ Max Unit Test conditions 0.48 (0.267)*2 - - μs Sampling in 16 states Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - Conversion time*1 (Operation at PCLKC = 60 MHz) Permissible signal source impedance Max. = 1 kΩ 0.48 (0.267)*2 - - μs Sampling in 16 states Max. = 400 Ω 0.40 (0.183)*2 - - μs Sampling in 11 states VCC = AVCC0 = 3.0 to 3.6 V 3.0 V ≤ VREFH ≤ AVCC0 Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - Conversion time*1 (Operation at PCLKC = 60 MHz) 0.75 (0.533)*2 - - μs Sampling in 32 states Permissible signal source impedance Max. = 1 kΩ Offset error - ±1.0 ±2.5 LSB - Full-scale error - ±1.0 ±2.5 LSB - Absolute accuracy - ±2.0 ±4.5 LSB - DNL differential nonlinearity error - ±0.5 ±1.5 LSB - INL integral nonlinearity error - ±1.0 ±2.5 LSB - Conversion time*1 (Operation at PCLKC = 60 MHz) 0.88 (0.667)*2 - - μs Sampling in 40 states - ±1.0 ±5.5 LSB - Permissible signal source impedance Max. = 1 kΩ Offset error Note: Min Full-scale error - ±1.0 ±5.5 LSB - Absolute accuracy - ±2.0 ±7.5 LSB - DNL differential nonlinearity error - ±0.5 ±4.5 LSB - INL integral nonlinearity error - ±1.0 ±5.5 LSB - These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D conversion, the values might not fall within the indicated ranges. The use of ports 0 as digital outputs is not allowed when the 12-bit A/D converter is used. The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are stable. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test conditions. Values in parentheses indicate the sampling time. When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.35. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 69 of 92 S5D3 Datasheet Table 2.35 2. Electrical Characteristics A/D conversion characteristics for simultaneous use of channel-dedicated sample-and-hold circuits in unit 0 and unit 1 Conditions: PCLKC = 30/60 MHz Parameter Channel-dedicated sample-and-hold circuits in use with continious sampling function enabled (AN000 to AN002) Channel-dedicated sample-and-hold circuits in use with continious sampling function enabled (AN100 to AN102) Channel-dedicated sample-and-hold circuits in use with continious sampling function enabled (AN000 to AN002) Channel-dedicated sample-and-hold circuits in use with continious sampling function enabled (AN100 to AN102) Note: Min Typ Max Test conditions Offset error - ±1.5 ±5.0 Full-scale error - ±2.5 ±5.0  PCLKC = 60 MHz  Sampling in 15 states Absolute accuracy - ±4.0 ±8.0 Offset error - ±1.5 ±5.0 Full-scale error - ±2.5 ±5.0 Absolute accuracy - ±4.0 ±8.0 Offset error - ±1.5 ±3.5 Full-scale error - ±1.5 ±3.5 Absolute accuracy - ±3.0 +4.5/-6.5 Offset error - ±1.5 ±3.5 Full-scale error - ±1.5 ±3.5 Absolute accuracy - ±3.0 +4.5/-6.5  PCLKC = 30 MHz  Sampling in 7 states When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, setting the ADSHMSR.SHMD bit to 1 is recommended. Table 2.36 A/D internal reference voltage characteristics Parameter Min Typ Max Unit Test conditions A/D internal reference voltage 1.13 1.18 1.23 V - Sampling time 4.15 - - μs - FFFh Full-scale error Integral nonlinearity error (INL) A/D converter output code Ideal line of actual A/D conversion characteristic Actual A/D conversion characteristic Ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Absolute accuracy 000h Offset error 0 Figure 2.64 Analog input voltage VREFH0 (full-scale) Illustration of ADC12 characteristic terms R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 70 of 92 S5D3 Datasheet 2. Electrical Characteristics Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 is 3.072 V, then the 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion characteristics and the width of the actual output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code. 2.6 DAC12 Characteristics Table 2.37 D/A conversion characteristics Parameter Min Typ Max Unit Test conditions Resolution - - 12 Bits - Absolute accuracy - - ±24 LSB Resistive load 2 MΩ INL - ±2.0 ±8.0 LSB Resistive load 2 MΩ DNL - ±1.0 ±2.0 LSB - Output impedance - 8.5 - kΩ - Conversion time - - 3.0 μs Resistive load 2 MΩ, Capacitive load 20 pF Output voltage range 0 - VREFH V - INL - ±2.0 ±4.0 LSB - DNL - ±1.0 ±2.0 LSB - Without output amplifier With output amplifier Conversion time - - 4.0 μs - Resistive load 5 - - kΩ - Capacitive load - - 50 pF - Output voltage range 0.2 - VREFH - 0.2 V - R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 71 of 92 S5D3 Datasheet 2.7 2. Electrical Characteristics TSN Characteristics Table 2.38 TSN characteristics Parameter Symbol Min Typ Max Unit Test conditions Relative accuracy - - ±1.0 - °C - Temperature slope - - 4.0 - mV/°C - Output voltage (at 25°C) - - 1.24 - V - Temperature sensor start time tSTART - - 30 μs - Sampling time - 4.15 - - μs - 2.8 OSC Stop Detect Characteristics Table 2.39 Oscillation stop detection circuit characteristics Parameter Symbol Min Typ Max Unit Test conditions Detection time tdr - - 1 ms Figure 2.65 Main clock tdr OSTDSR.OSTDF MOCO clock ICLK Figure 2.65 2.9 Oscillation stop detection timing POR and LVD Characteristics Table 2.40 Power-on reset circuit and voltage detection circuit characteristics (1 of 2) Parameter Voltage detection level Power-on reset (POR) Module-stop function disabled*2 Symbol Min Typ Max Unit Test conditions VPOR 2.5 2.6 2.7 V Figure 2.66 1.8 2.25 2.7 Module-stop function enabled*3 Voltage detection circuit (LVD0) Voltage detection circuit (LVD1) Voltage detection circuit (LVD2) Internal reset time Vdet0_1 2.84 2.94 3.04 Vdet0_2 2.77 2.87 2.97 Vdet0_3 2.70 2.80 2.90 Vdet1_1 2.89 2.99 3.09 Vdet1_2 2.82 2.92 3.02 Vdet1_3 2.75 2.85 2.95 Vdet2_1 2.89 2.99 3.09 Vdet2_2 2.82 2.92 3.02 Figure 2.67 Figure 2.68 Figure 2.69 Vdet2_3 2.75 2.85 2.95 Power-on reset time tPOR - 4.5 - LVD0 reset time tLVD0 - 0.51 - Figure 2.67 LVD1 reset time tLVD1 - 0.38 - Figure 2.68 LVD2 reset time tLVD2 - 0.38 - Figure 2.69 R01DS0328EU0100 Rev.1.00 Aug 10, 2018 ms Figure 2.66 Page 72 of 92 S5D3 Datasheet Table 2.40 2. Electrical Characteristics Power-on reset circuit and voltage detection circuit characteristics (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions tVOFF 200 - - μs Figure 2.66, Figure 2.67 Response delay tdet - - 200 μs Figure 2.66 to Figure 2.69 LVD operation stabilization time (after LVD is enabled) td(E-A) - - 10 μs Hysteresis width (LVD1 and LVD2) VLVH - 70 - mV Figure 2.68, Figure 2.69 Minimum VCC down Note 1. Note 2. Note 3. time*1 The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1, and Vdet2 for POR and LVD. The low power function is disabled and DEEPCUT[1:0] = 00b or 01b. The low power function is enabled and DEEPCUT[1:0] = 11b. tVOFF VPOR VCC Internal reset signal (active-low) tdet Figure 2.66 tPOR tdet tdet tPOR Power-on reset timing tVOFF VCC Vdet0 Internal reset signal (active-low) tdet Figure 2.67 tdet tLVD0 Voltage detection circuit timing (Vdet0) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 73 of 92 S5D3 Datasheet 2. Electrical Characteristics tVOFF VCC VLVH Vdet1 LVCMPCR.LVD1E td(E-A) LVD1 Comparator output LVD1CR0.CMPE LVD1SR.MON Internal reset signal (active-low) When LVD1CR0.RN = 0 tdet tdet tLVD1 When LVD1CR0.RN = 1 tLVD1 Figure 2.68 Voltage detection circuit timing (Vdet1) tVOFF VCC VLVH Vdet2 LVCMPCR.LVD2E LVD2 Comparator output td(E-A) LVD2CR0.CMPE LVD2SR.MON Internal reset signal (active-low) When LVD2CR0.RN = 0 tdet tdet tLVD2 When LVD2CR0.RN = 1 tLVD2 Figure 2.69 Voltage detection circuit timing (Vdet2) R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 74 of 92 S5D3 Datasheet 2.10 2. Electrical Characteristics VBATT Characteristics Table 2.41 Battery backup function characteristics Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.8 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Voltage level for switching to battery backup VDETBATT 2.50 2.60 2.70 V Figure 2.70 Lower-limit VBATT voltage for power supply switching caused by VCC voltage drop VBATTSW 2.70 - - V VCC-off period for starting power supply switching tVOFFBATT 200 - - μs Note: The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage level for switching to battery backup (VDETBATT). tVOFFBATT VDETBATT VCC VBATT Backup power area Figure 2.70 2.11 VBATTSW VCC supply VBATT supply VCC supply Battery backup function characteristics CTSU Characteristics Table 2.42 CTSU characteristics Parameter Symbol Min Typ Max Unit Test conditions External capacitance connected to TSCAP pin Ctscap 9 10 11 nF - TS pin capacitive load Cbase - - 50 pF - Permissible output high current ΣIoH - - -40 mA When the mutual capacitance method is applied Parameter Symbol Min Typ Max Unit Test conditions Reference voltage range VREF 0 - AVCC0 V - Input voltage range VI 0 - AVCC0 V - Td - 50 100 ns VI = VREF ± 100 mV Vref 1.13 1.18 1.23 V - 2.12 ACMPHS Characteristics Table 2.43 Output ACMPHS characteristics delay*1 Internal reference voltage Note 1. This value is the internal propagation delay. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 75 of 92 S5D3 Datasheet 2.13 2. Electrical Characteristics PGA Characteristics Table 2.44 PGA characteristics in single mode Parameter Symbol Min Typ Max Unit PGAVSS input voltage range PGAVSS 0 - 0 V AIN0 (G = 2.000) 0.050 × AVCC0 - 0.45 × AVCC0 V AIN1 (G = 2.500) 0.047 × AVCC0 - 0.360 × AVCC0 V AIN2 (G = 2.667) 0.046 × AVCC0 - 0.337 × AVCC0 V AIN3 (G = 2.857) 0.046 × AVCC0 - 0.32 × AVCC0 V AIN4 (G = 3.077) 0.045 × AVCC0 - 0.292 × AVCC0 V AIN5 (G = 3.333) 0.044 × AVCC0 - 0.265 × AVCC0 V AIN6 (G = 3.636) 0.042 × AVCC0 - 0.247 × AVCC0 V AIN7 (G = 4.000) 0.040 × AVCC0 - 0.212 × AVCC0 V AIN8 (G = 4.444) 0.036 × AVCC0 - 0.191 × AVCC0 V AIN9 (G = 5.000) 0.033 × AVCC0 - 0.17 × AVCC0 V AIN10 (G = 5.714) 0.031 × AVCC0 - 0.148 × AVCC0 V AIN11 (G = 6.667) 0.029 × AVCC0 - 0.127 × AVCC0 V AIN12 (G = 8.000) 0.027 × AVCC0 - 0.09 × AVCC0 V AIN13 (G = 10.000) 0.025 × AVCC0 - 0.08 × AVCC0 V Gain error Offset error Table 2.45 AIN14 (G = 13.333) 0.023 × AVCC0 - 0.06 × AVCC0 V Gerr0 (G = 2.000) -1.0 - 1.0 % Gerr1 (G = 2.500) -1.0 - 1.0 % Gerr2 (G = 2.667) -1.0 - 1.0 % Gerr3 (G = 2.857) -1.0 - 1.0 % Gerr4 (G = 3.077) -1.0 - 1.0 % Gerr5 (G = 3.333) -1.5 - 1.5 % Gerr6 (G = 3.636) -1.5 - 1.5 % Gerr7 (G = 4.000) -1.5 - 1.5 % Gerr8 (G = 4.444) -2.0 - 2.0 % Gerr9 (G = 5.000) -2.0 - 2.0 % Gerr10 (G = 5.714) -2.0 - 2.0 % Gerr11 (G = 6.667) -2.0 - 2.0 % Gerr12 (G = 8.000) -2.0 - 2.0 % Gerr13 (G = 10.000) -2.0 - 2.0 % Gerr14 (G = 13.333) -2.0 - 2.0 % Voff -8 - 8 mV PGA characteristics in differential mode (1 of 2) Parameter Symbol Min PGAVSS input voltage range PGAVSS -0.5 - 0.3 V Differential input voltage range AIN-PGAVSS -0.5 - 0.5 V -0.4 - 0.4 V G = 1.500 G = 2.333 Typ Max Unit G = 4.000 -0.2 - 0.2 V G = 5.667 -0.15 - 0.15 V R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 76 of 92 S5D3 Datasheet Table 2.45 2. Electrical Characteristics PGA characteristics in differential mode (2 of 2) Parameter Gain error 2.14 Symbol Min Typ Max Unit Gerr -1.0 - 1.0 % G = 2.333 -1.0 - 1.0 G = 4.000 -1.0 - 1.0 G = 5.667 -1.0 - 1.0 G = 1.500 Flash Memory Characteristics 2.14.1 Code Flash Memory Characteristics Table 2.46 Code flash memory characteristics Conditions: Program or erase: FCLK = 4 to 60 MHz Read: FCLK ≤ 60 MHz FCLK = 4 MHz Parameter 20 MHz ≤ FCLK ≤ 60 MHz Symbol Min Typ Max Min Typ Max Unit Programming time NPEC  100 times 128-byte tP128 - 0.75 13.2 - 0.34 6.0 ms 8-KB tP8K - 49 176 - 22 80 ms 32-KB tP32K - 194 704 - 88 320 ms Programming time NPEC > 100 times 128-byte tP128 - 0.91 15.8 - 0.41 7.2 ms 8-KB tP8K - 60 212 - 27 96 ms 32-KB tP32K - 234 848 - 106 384 ms Erasure time NPEC  100 times 8-KB tE8K - 78 216 - 43 120 ms 32-KB tE32K - 283 864 - 157 480 ms Erasure time NPEC > 100 times 8-KB tE8K - 94 260 - 52 144 ms 32-KB tE32K - 341 1040 - 189 576 ms NPEC 10000*1 - - 10000*1 - - Times tSPD Reprogramming/erasure cycle*4 - - 264 - - 120 μs First suspend delay during erasure in tSESD1 suspend priority mode - - 216 - - 120 μs Second suspend delay during erasure in suspend priority mode tSESD2 - - 1.7 - - 1.7 ms Suspend delay during erasure in erasure priority mode tSEED - - 1.7 - - 1.7 ms Forced stop command tFD - - 32 - - 20 μs Data hold time*2 tDRP 10*2, *3 - - 10*2, *3 - - Years - 30*2, *3 - - Suspend delay during programming 30*2, *3 Note 1. Note 2. Note 3. Note 4. - Test conditions Ta = +85°C This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to the minimum value. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range. This result is obtained from reliability testing. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10000), erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address several times as one erasure is not enabled. Overwriting is prohibited. R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 77 of 92 S5D3 Datasheet 2. Electrical Characteristics • Suspension during programming FCU command Program Suspend tSPD FSTATR0.FRDY Ready Not Ready Programming pulse Ready Programming • Suspension during erasure in suspend priority mode FCU command Erase Suspend Resume Suspend tSESD1 FSTATR0.FRDY Ready tSESD2 Not Ready Erasure pulse Ready Erasing Not Ready Erasing • Suspension during erasure in erasure priority mode FCU command Erase Suspend tSEED FSTATR0.FRDY Ready Not Ready Erasure pulse Ready Erasing • Forced Stop FACI command Forced Stop tFD FSTATR.FRDY Figure 2.71 Not Ready Ready Suspension and forced stop timing for flash memory programming and erasure R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 78 of 92 S5D3 Datasheet 2.14.2 2. Electrical Characteristics Data Flash Memory Characteristics Table 2.47 Data flash memory characteristics Conditions: Program or erase: FCLK = 4 to 60 MHz Read: FCLK ≤ 60 MHz FCLK = 4 MHz Parameter Programming time Erasure time Blank check time Min Typ Max Min Typ Max Unit tDP4 - 0.36 3.8 - 0.16 1.7 ms 8-byte tDP8 - 0.38 4.0 - 0.17 1.8 16-byte tDP16 - 0.42 4.5 - 0.19 2.0 64-byte tDE64 - 3.1 18 - 1.7 10 128-byte tDE128 - 4.7 27 - 2.6 15 256-byte tDE256 - 8.9 50 - 4.9 28 4-byte tDBC4 - - 84 - - 30 μs NDPEC 125000*2 - - 125000*2 - - - tDSPD - - 264 - - 120 μs - - 264 - - 120 4-byte Reprogramming/erasure Suspend delay during programming 20 MHz ≤ FCLK ≤ 60 MHz Symbol cycle*1 4-byte 8-byte 16-byte First suspend delay 64-byte during erasure in 128-byte suspend priority mode 256-byte Second suspend delay during erasure in suspend priority mode 64-byte Suspend delay during erasing in erasure priority mode 64-byte tDSESD1 tDSESD2 128-byte 256-byte tDSEED 128-byte 256-byte - - 264 - - 120 - - 216 - - 120 - - 216 - - 120 - - 216 - - 120 - - 300 - - 300 - - 390 - - 390 - - 570 - - 570 - - 300 - - 300 - - 390 - - 390 ms μs μs μs - - 570 - - 570 Forced stop command tFD - - 32 - - 20 μs Data hold time*3 tDRP 10*3,*4 - - 10*3,*4 - - Year - 30*3,*4 - - 30*3,*4 Note 1. Note 2. Note 3. Note 4. 2.15 - Test conditions Ta = +85°C The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125000), erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address several times as one erasure is not enabled. Overwriting is prohibited. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to the minimum value. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range. This result is obtained from reliability testing. Boundary Scan Table 2.48 Boundary scan characteristics (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 100 - - ns Figure 2.72 TCK clock high pulse width tTCKH 45 - - ns TCK clock low pulse width tTCKL 45 - - ns TCK clock rise time tTCKr - - 5 ns TCK clock fall time tTCKf - - 5 ns R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 79 of 92 S5D3 Datasheet Table 2.48 2. Electrical Characteristics Boundary scan characteristics (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions TMS setup time tTMSS 20 - - ns Figure 2.73 TMS hold time tTMSH 20 - - ns TDI setup time tTDIS 20 - - ns TDI hold time tTDIH 20 - - ns tTDOD - - 40 ns TBSSTUP tRESWP - - - TDO data delay Boundary scan circuit startup Note 1. time*1 Figure 2.74 Boundary scan does not function until the power-on reset becomes negative. tTCKcyc tTCKH tTCKf TCK tTCKr tTCKL Figure 2.72 Boundary scan TCK timing TCK tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD TDO Figure 2.73 Boundary scan input/output timing VCC RES tBSSTUP (= tRESWP) Figure 2.74 Boundary scan execute Boundary scan circuit startup timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 80 of 92 S5D3 Datasheet 2.16 2. Electrical Characteristics Joint Test Action Group (JTAG) Table 2.49 JTAG Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 40 - - ns Figure 2.72 TCK clock high pulse width tTCKH 15 - - ns TCK clock low pulse width tTCKL 15 - - ns TCK clock rise time tTCKr - - 5 ns TCK clock fall time tTCKf - - 5 ns TMS setup time tTMSS 8 - - ns TMS hold time tTMSH 8 - - ns TDI setup time tTDIS 8 - - ns TDI hold time tTDIH 8 - - ns TDO data delay time tTDOD - - 20 ns Figure 2.73 tTCKcyc tTCKH TCK tTCKf tTCKr tTCKL Figure 2.75 JTAG TCK timing TCK tTMSS tTMSH TMS tTDIS tTDIH TDI tTDOD TDO Figure 2.76 JTAG input/output timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 81 of 92 S5D3 Datasheet 2.17 2. Electrical Characteristics Serial Wire Debug (SWD) Table 2.50 SWD Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 40 - - ns Figure 2.77 SWCLK clock high pulse width tSWCKH 15 - - ns SWCLK clock low pulse width tSWCKL 15 - - ns SWCLK clock rise time tSWCKr - - 5 ns SWCLK clock fall time tSWCKf - - 5 ns SWDIO setup time tSWDS 8 - - ns SWDIO hold time tSWDH 8 - - ns SWDIO data delay time tSWDD 2 - 28 ns Figure 2.78 tSWCKcyc tSWCKH SWCLK tSWCKL Figure 2.77 SWD SWCLK timing SWCLK tSWDS tSWDH SWDIO (input) tSWDD SWDIO (output) tSWDD SWDIO (output) tSWDD SWDIO (output) Figure 2.78 SWD input/output timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 82 of 92 S5D3 Datasheet 2.18 2. Electrical Characteristics Embedded Trace Macro Interface (ETM) Table 2.51 ETM Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Typ Max Unit Test conditions TCLK clock cycle time tTCLKcyc 33.3 - - ns Figure 2.79 TCLK clock high pulse width tTCLKH 13.6 - - ns TCLK clock low pulse width tTCLKL 13.6 - - ns TCLK clock rise time tTCLKr - - 3 ns TCLK clock fall time tTCLKf - - 3 ns TDATA[3:0] output setup time tTRDS 3.5 - - ns TDATA[3:0] output hold time tTRDH 2.5 - - ns Figure 2.80 tTCLKcyc tTCLKH TCLK tTCLKf tTCLKL Figure 2.79 tTCLKr ETM TCLK timing TCLK tTRDS tTRDH tTRDS tTRDH TDATA[3:0] Figure 2.80 ETM output timing R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 83 of 92 S5D3 Datasheet Appendix 1. Package Dimensions Appendix 1.Package Dimensions Information on the latest version of the package dimensions or mountings is shown in “Packages” on the Renesas Electronics Corporation website. JEITA Package Code P-TFLGA100-7x7-0.65 RENESAS Code PTLG0100JA-A Previous Code 100F0G MASS[Typ.] 0.1g w S B φ b1 D φ× M S φb w S A ZD AB e A e A AB φ× M S K J H G B E F E D C B ×4 y S v Index mark (Laser mark) Figure 1.1 S ZE A 1 2 3 Index mark 4 5 6 7 8 9 10 Reference Dimension in Millimeters Symbol Min Nom D 7.0 E 7.0 v w A e 0.65 b 0.31 0.35 b1 0.385 0.435 x y ZD 0.575 ZE 0.575 Max 0.15 0.20 1.05 0.39 0.485 0.08 0.10 100-pin LGA R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 84 of 92 S5D3 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP100-14x14-0.50 PLQP0100KB-B — 0.6 HD Unit: mm *1 D 75 51 *2 E 50 100 HE 76 26 1 25 NOTE 4 Index area NOTE 3 F S y S *3 0.25 T A1 Lp L1 Detail F Reference Dimensions in millimeters Symbol bp M Min Nom Max D 13.9 14.0 14.1 14.1 E 13.9 14.0 A2  1.4  HD 15.8 16.0 16.2 HE 15.8 16.0 16.2 A   1.7 A1 0.05  0.15 bp 0.15 0.20 0.27 c 0.09  0.20 T 0q 3.5q 8q e  0.5  x   0.08 y   0.08 Lp 0.45 0.6 0.75 L1  1.0  c A2 A e NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. © 2015 Renesas Electronics Corporation. All rights reserved. Figure 1.2 100-pin LQFP R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 85 of 92 S5D3 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP64-10x10-0.50 PLQP0064KB-C — 0.3 Unit: mm HD *1 D 48 33 64 HE 32 *2 E 49 17 1 16 NOTE 4 Index area NOTE 3 F S y S *3 bp 0.25 c A1 T A2 A e Lp L1 Detail F M NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. Reference Dimensions in millimeters Symbol Min Nom Max D 9.9 10.0 10.1 10.1 E 9.9 10.0 A2  1.4  HD 11.8 12.0 12.2 HE 11.8 12.0 12.2 A   1.7 A1 0.05  0.15 bp 0.15 0.20 0.27 c 0.09  0.20 T 0q 3.5q 8q e  0.5  x   0.08 y   0.08 Lp 0.45 0.6 0.75 L1  1.0  © 2015 Renesas Electronics Corporation. All rights reserved. Figure 1.3 64-pin LQFP R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 86 of 92 S5D3 Datasheet Appendix 1. Package Dimensions JEITA Package code P-HWQFN64-8x8-0.40 RENESAS code Previous code MASS(TYP.)[g] PWQN0064LA-A P64K8-40-9B5-3 0.16 D 33 48 DETAIL OF A PART 32 49 E A A1 17 64 c2 16 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 16 1 64 17 Dimension in Millimeters Min Nom Max D 7.95 8.00 8.05 E 7.95 8.00 8.05 A 0.80 A1 0.00 b 0.17 e Lp B E2 0.20 0.30 0.40 x y 32 49 0.05 48 33 ZD e b x M 1.00 ZE c2 0.50 0.05 ZD ZE 0.23 0.40 1.00 0.15 0.20 D2 6.50 E2 6.50 0.25 S AB 2013 Renesas Electronics Corporation. All rights reserved. Figure 1.4 64-pin QFN R01DS0328EU0100 Rev.1.00 Aug 10, 2018 Page 87 of 92 Revision History Rev. Date 1.00 Aug 10, 2018 S5D3 Microcontroller Group Datasheet Summary First release Website and Support Visit the following vanity URLs to learn about key elements of the Synergy Platform, download components and related documentation, and get support. Synergy Software renesassynergy.com/software Synergy Software Package renesassynergy.com/ssp Software add-ons renesassynergy.com/addons Software glossary renesassynergy.com/softwareglossary Development tools renesassynergy.com/tools Synergy Hardware renesassynergy.com/hardware Microcontrollers renesassynergy.com/mcus MCU glossary renesassynergy.com/mcuglossary Parametric search renesassynergy.com/parametric Kits renesassynergy.com/kits Synergy Solutions Gallery renesassynergy.com/solutionsgallery Partner projects renesassynergy.com/partnerprojects Application projects renesassynergy.com/applicationprojects Self-service support resources: Documentation renesassynergy.com/docs Knowledgebase renesassynergy.com/knowledgebase Forums renesassynergy.com/forum Training renesassynergy.com/training Videos renesassynergy.com/videos Chat and web ticket renesassynergy.com/support Proprietary Notice All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated, transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior written consent from Renesas. Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited. CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium. Magic Packet™ is a trademark of Advanced Micro Devices, Inc. SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective holders. Colophon S5D3 Microcontroller Group Datasheet Publication Date: Rev.1.00 Aug 10, 2018 Published by: Renesas Electronics Corporation Address List General Precautions 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during poweroff state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product. S5D3 Datasheet Notice 1. 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