User’s Manual
RTKA2108332H00000BU
User’s Manual: Evaluation Board
Industrial Analog and Power
Rev 0.00
Sep 2018
USER’S MANUAL
RTKA2108332H00000BU
UG179
Rev.0.00
Sep 12, 2018
Evaluation Board
1.
Overview
The RAA210833 is a pin-strap configurable 33A step-down PMBus-compliant DC/DC power supply module that
integrates a digital PWM controller, synchronous MOSFETs, a power inductor, and passive components. Only input
and output capacitors are needed to finish the design. Because of its thermally-enhanced HDA packaging technology,
the module can deliver up to 33A of continuous output current without the need for airflow or additional heat sinking.
The RAA210833 simplifies configuration and control of Renesas digital power technology while offering an upgrade
path to full PMBus configuration through the pin-compatible ISL8278M.
The RTKA2108332H00000BU evaluation board is a 4inx4.5in 4-layer FR4 board with 2oz. copper in all layers. The
RAA210833 comes with a preprogrammed configuration for operating in a pin-strap mode. Output voltage, switching
frequency, input UVLO, soft-start/stop delay and ramp times, and the device SMBus address can be programmed with
external pin-strap resistors.
The ZLUSBEVAL3Z (USB to PMBus adapter) is provided with this evaluation board, which connects the evaluation
board to a PC to activate the PMBus communication interface. The PMBus command set is accessed by using
PowerNavigator™ evaluation software from a PC running Microsoft Windows.
The RTKA2108332H0000BBU can operate in Pin-Strap mode without needing the ZLUSBEVAL3Z adapter or
PMBus communication.
1.1
Key Features
• VIN range of 4.5V to 14V, VOUT adjustable from 0.6V to 5V
• Pin-Strap mode for standard settings: VOUT, switching frequency, input UVLO, soft-start/stop, and external
synchronization
• Real-time telemetry for VIN, VOUT, IOUT, temperature, duty cycle and switching frequency, and fault logging
• ChargeMode™ control that is tunable with pin-strap resistors or the PMBus interface
• Mechanical switch for enable and the power-good LED indicator
1.2
Specifications
This board is configured for the following operating conditions by default:
• VIN = 5V to 12V
• VOUT = 1.2V
• IMAX = 33A
• fSW = 364kHz
• ASCR gain = 250, ASCR residual = 90
• On/off delay = 5ms, on/off ramp time = 5ms
• Input UVLO = 4.2V
• PMBus address = 0x28h
1.3
Ordering Information
Part Number
RTKA2108332H00000BU
UG179 Rev.0.00
Sep 12, 2018
Description
RAA210833 board (EVB, ZLUSBEVAL3Z adapter, USB cable)
Page 2 of 21
RTKA2108332H00000BU
1.4
1. Overview
Related Literature
For a full list of related documents, visit our website
• RAA210833 product page
1.5
Recommended Equipment
• DC power supply with minimum 15V/25A sourcing capacity
• Electronic load capable of sinking current up to 33A
• Digital Multimeters (DMMs)
• Oscilloscope with higher than 100MHz bandwidth
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Figure 1. RTKA2108332H00000BU Block Diagram
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Sep 12, 2018
Page 3 of 21
RTKA2108332H00000BU
2.
2. Functional Description
Functional Description
The RTKA2108332H00000BU provides all circuitry required to evaluate the features of the RAA210833. A majority
of the features of the RAA210833, such as compensation-free ChargeMode control, soft-start delay, ramp times,
external clock synchronization, and Bode plot measurement are available on this evaluation board.
Figure 4 on page 10 shows an image of the RTKA2108332H00000BU evaluation board.
2.1
Operating Range
By default, the RTKA2108332H00000BU is configured to operate at VOUT = 1.2V, fSW = 364kHz. VIN ranges
from 4.5V to 12V. The board can also support a wider operating range to meet the requirements of specific
applications. The VOUT can be adjusted from 0.6V to 5V. Load current range is from 0A to 33A. Note that airflow
across the board may be needed for continuous operation at 33A at elevated ambient temperature. The fSW and
output voltage can also be tuned. However, to ensure sufficient stability margins, the switching frequency and
output capacitors should be selected using the “RAA210833 Design Guide Matrix and Output Voltage Response”
table in the RAA210833 datasheet.
If the input voltage is less than 5.3V, tie the VCC test point directly to VIN or to a separate 5V power supply for
normal operation and best efficiency.
The RTKA2108332H00000BU can handle a 0A to 33A output current transient in which the slew rate is less than
2A/µs, such as an electronic load. If the slew rate exceeds the 2A/µs, it may be necessary to increase the output
capacitance or change the VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT values for proper
operation (refer to “PMBus Option” on page 5).
If external synchronization is used, connect the SYNC test point to the external clock. Note that the external clock
signal should be active before the module is enabled.
2.2
PMBus Operation
The RTKA2108332H0000BBU can be evaluated for all features using the provided ZLUSBEVAL3Z dongle and
PowerNavigator. Complete the following steps to evaluate the RAA210833 with the PMBus option.
Install the PowerNavigator evaluation software from the Renesas website.
For board operation, connect the included ZLUSBEVAL3Z dongle to the 6-pin male connector labeled “PMBus
DONGLE IN”. Connect the desired load and an appropriate power supply to the input and connect the included
USB cable to the PC running PowerNavigator. Set the ENABLE switch to “DISABLE” before turning on the
power.
PowerNavigator allows modification of all RAA210833 PMBus parameters for debugging purposes. The
RAA210833 device on the board has been preconfigured as described in this document, but the user can modify the
operating parameters through PowerNavigator.
The ENABLE switch can then be moved to “ENABLE” and the RTKA2108332H00000BU board can be tested.
Alternately, the PMBus ON_OFF_CONFIG and OPERATION commands can be used from PowerNavigator.
2.3
Quick Start Guide
2.3.1
Pin-Strap Option
The RTKA2108332H00000BU can be configured in Pin-Strap mode with standard 1% 0603 resistors. The
PMBus interface is not required to evaluate the RAA210833 in Pin-Strap mode. Output voltage (VOUT),
switching frequency (fSW), input undervoltage protection (UVLO) threshold, start/stop time delay, ramp time,
ASCR settings, and the device PMBus address can be changed by populating the recommended resistors at
placeholders provided in the evaluation board. By default, the evaluation board is programmed to regulate at
VOUT = 1.2V, fSW = 364kHz, UVLO = 4.2V, ASCR Gain = 250, ACSR Residual = 90,
Ton_delay = Ton_rise = Toff_delay = Toff_fall = 5ms, and PMBus address = 28h.
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RTKA2108332H00000BU
2. Functional Description
Complete the following steps to evaluate the RAA210833 in Pin-Strap mode:
(1) Set the ENABLE switch to “DISABLE”.
(2) Connect a load to the VOUT lug connectors (J8 and J9).
(3) Connect a power supply to the VIN connectors (J1 and J2). Make sure the power supply is not enabled
when making the connection.
(4) Adjust VIN to 12V and turn the power supply on.
(5) Set the ENABLE switch to “ENABLE”.
(6) Measure 1.2V VOUT at probe points TP9 and TP13.
(7) Observe the switching frequency of 364kHz at the probe point labeled VSWH (TP8).
(8) To change VOUT, disconnect the board from the setup and populate with a 1% standard 0603 resistor at the
R6 placeholder location on the bottom layer. Refer to the “Output Voltage Resistor Settings” table in the
RAA210833 datasheet for recommended values. By default, VOUT_MAX is set to 110% of VOUT set by
the pin-strap resistor.
(9) To change the switching frequency, disconnect the board from the setup and populate with a 1% standard
0603 resistor at the R2 placeholder location on the bottom layer. Refer to the “Switching Frequency
Resistor Settings” table in the RAA210833 datasheet for recommended values.
(10) To change the Soft-Start/Stop Ramp time or UVLO, disconnect the board from the setup and populate with a
1% standard 0603 resistor at the R7 placeholder location on the bottom layer. Refer to the “Soft-Start/Stop
and Input UVLO Resistor Settings” table or the “UVLO Resistor Settings” table in the RAA210833
datasheet for the recommended values.
(11) To change the ASCR, disconnect the board from the setup and populate with a 1% standard 0603 resistor
at the R8 placeholder location on the bottom layer. Refer to the “ASCR Resistor Settings” table in the
RAA210833 datasheet for the recommended values.
2.3.2
PMBus Option
The RTKA2108332H00000BU can be evaluated for all features using the provided ZLUSBEVAL3Z dongle
and PowerNavigator. Complete the following steps to evaluate the RAA210833 with the PMBus option.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Install PowerNavigator.
Set the ENABLE switch to “DISABLE”.
Connect a load to the VOUT lug connectors (J8 and J9).
Connect a power supply to the VIN connectors (J1 and J2). Make sure the power supply is not enabled
when making the connection.
Adjust the VIN to 12V and turn the power supply on.
Connect the ZLUSBEVAL3Z dongle (USB to PMBus adapter) to the RTKA2108332H00000BU board to
the 6-pin male connector labeled “PMBus DONGLE IN”.
Connect the supplied USB cable from the computer through USB to the ZLUSBEVAL3Z dongle.
Launch PowerNavigator.
The RAA210833 device on the board operates in Pin-Strap mode from factory default, but the user can
modify the operating parameters through PowerNavigator to monitor faults and debug a test case and read
real-time values of input/output parameters, switching frequency, duty cycle, and temperature.
Set the ENABLE switch to “ENABLE”. Alternatively, the PMBus ON_OFF_CONFIG and OPERATION
commands can be used from PowerNavigator to allow PMBus Enable.
Monitor and configure the RTKA2108332H00000BU board using the PMBus commands in
PowerNavigator. PowerNavigator tutorial videos are available at the Renesas PowerNavigator website.
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Page 5 of 21
RTKA2108332H00000BU
3.
3. Evaluation Board Information
Evaluation Board Information
3.1
External Clock Synchronization
The RAA210833 can synchronize to an external clock. External clock synchronization allows the user to operate
multiple converters at the same switching frequency and can lead to improved EMI characteristics. The
RTKA2108332H00000BU evaluation board can assess this functionality. A function generator is required.
Complete the following steps to operate the RAA210833 with an external clock frequency of 593kHz:
(1) Set the Enable switch to the “DISABLE” position.
(2) Solder a 17.8kΩ resistor at RSET on the CFG pin (R16).
(3) Program the function generator to output a continuous square pulse waveform of 593kHz. Program the pulse
width to be at least 150ns.
(4) Ensure that the clock signal is stable by monitoring the waveform on an oscilloscope.
(5) After verifying clock stability, connect the output cables from the function generator to test point J4 (labeled
“SYNC”).
(6) Turn the function generator output to “ON”.
(7) Enable the module by setting the Enable switch to “ENABLE”.
(8) Observe the switching frequency at test point TP8 (labeled “VSWH”).
(9) The module synchronizes to the 593kHz external clock from the function generator.
(10) Always ensure that the module is disabled before changing the frequency of the external clock.
(11) A Loss of Sync fault is generated when the external clock is lost.
3.2
Bode Plot Measurement
Assessing the stability of the converter is an important step in the design process. Bode plots are a useful and
reliable tool to identify the converter’s loop response. Phase margin and gain margin give an insight into the
stability of the system, and the bandwidth can indicate how quickly the converter responds to disturbances in input
voltage or load transients. Correctly measuring the loop response is critical for designing stable converter systems.
A network analyzer is required to perform the frequency response measurements on the RTKA2108332H00000BU
evaluation board. Complete the following steps to evaluate the RAA210833 converter loop response on the
RTKA2108332H00000BU evaluation board.
(1) Break the feedback loop by removing the R9 resistor in the remote sense path, connected between VSEN+ and
VOUT.
(2) Solder a 20Ω resistor in its place. The value of the resistor should be in the range of 10Ω to 50Ω.
(3) Solder a twisted wire pair to the 20Ω resistor. Ensure that the wires are short in length. A small twisted pair
works well by minimizing noise pickup, which is important for a good measurement.
(4) Enable the module.
(5) Use a network analyzer to inject a small AC signal (~20mV) across the 20Ω resistor as shown in Figure 2 on
page 7.
(6) Measure the amplitudes of the signals at points A and B as shown in Figure 2.
(7) Sweep the frequency using the network analyzer to observe the bandwidth, phase, and gain margin.
UG179 Rev.0.00
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Page 6 of 21
RTKA2108332H00000BU
3. Evaluation Board Information
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Figure 2. Network Analyzer Connection
Figure 3 shows an example plot generated by the network analyzer for the RAA210833 at 12V input and 1.2V/33A
output at 364 kHz. 10x100uF ceramic capacitors + 4x470uF POSCAPs are used at the output, with ASCR
gain = 250 and Residual = 90. The plot shows a crossover frequency of 41.69 kHz with a phase margin of 70.2°. A
12.7dB gain margin is observed at 182 kHz.
Figure 3. Example of Bode Plot Generated Using Network Analyzer
Refer to the “RAA210833 Design Guide Matrix and Output Voltage Response” table in the RAA210833 datasheet
for detailed design guidelines, including selection of input/output capacitors and different ASCR gain and residual
values.
3.3
Interleave Operation
When multiple point-of-load converters share a common DC input supply, Renesas recommends adjusting the
clock phase offset of each device so that not all devices start to switch simultaneously. Setting each converter to
start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and
efficiency losses. Because the peak current drawn from the input supply is effectively spread out over a period of
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Sep 12, 2018
Page 7 of 21
RTKA2108332H00000BU
3. Evaluation Board Information
time, the peak current drawn at any given moment is reduced, and the power losses proportional to the I2RMS are
reduced dramatically.
To enable phase spreading in a multi-module operation, all converters must be synchronized to the same switching
clock. The phase offset of each device can be set to any value between 0° and 360° in 22.5° increments by choosing
the device PMBus address from the “Interleave Settings from SA” table in the RAA210833 datasheet. The lower
four bits of the PMBUS address set the value of the INTERLEAVE command. To implement Interleave
functionality for a two module operation, complete the following steps:
(1) Choose SA (SMBus Address) for Module 1 and Module 2 from the “Interleave Settings from SA” table in the
RAA210833 datasheet based on the desired phase difference. Populate the corresponding RSET for SA (R5)
according to the RAA210833 datasheet.
For example, when Module 1 has SA = 28h (INTERLEAVE = 8, 180° phase shift from the rising edge of the
external clock) and Module 2 has SA=24h (INTERLEAVE = 4, 90° phase shift from the rising edge of the
external clock), the net phase difference between Module 1 and Module 2 is 90° (180° – 90°).
(2) Populate RSET on CFG for both boards to synchronize to an external clock source of a particular switching
frequency based on the “External Frequency SYNC Settings” table in the RAA210833 datasheet.
(3) Connect the power supply to the VIN connectors (VIN/GND) on both boards.
(4) Connect the ZLUSBEVAL3Z dongle to the 6-pin male connector labeled “PMBus DONGLE In” to one of the
boards.
(5) Daisy chain the second board to the first board by connecting “PMBus DONGLE Out” of the first board to the
“PMBus DONGLE In” of the second board.
(6) Provide an external clock on the SYNC pins of the two boards from a function generator. The external clock
frequency from the function generator should be within ±10% of the listed options shown in the “External
Frequency SYNC Settings” table in the RAA210833 datasheet. The incoming clock signal must be stable
before the enable pin is asserted. The external clock signal must not vary more than 10% from its initial value
and should have a minimum pulse width of 150ns.
(7) Turn the input power supply on. Next, set the ENABLE switch to the “ENABLE” position.
(8) Monitor the VSWH node at the probe point labeled VSWH (TP8) on the two boards using an oscilloscope to
verify the phase spread set. This functionality can also be verified using the INTERLEAVE command in
PowerNavigator.
Note that every module gets assigned a unique Rail ID based on the SA setting. This can be observed in the
Power Map window of PowerNavigator.
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RTKA2108332H00000BU
4.
4. PCB Layout Guidelines
PCB Layout Guidelines
To achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary.
The key features of the RTKA2108332H00000BU layout are:
• Establish separate SGND and PGND planes, then connect the SGND plane to the PGND plane in the middle layer. To
make connections between SGND/PGND on the top layer and other layers, use multiple vias for each pin to connect
to the inner SGND/PGND layers. Do not connect SGND directly to PGND on a top layer. Connecting SGND directly
to PGND without establishing the SGND plane bypasses the decoupling capacitor at the internal reference supplies,
making the controller susceptible to noise.
• Place enough ceramic capacitors between VIN and PGND and VOUT and PGND. Bypass capacitors between VDD
and the ground plane, as close to the module as possible to minimize high-frequency noise.
• Use large copper areas for a power path (VIN, PGND, and VOUT) to minimize conduction loss and thermal stress.
Use multiple vias to connect the power planes in different layers. Extra ceramic capacitors at VIN and VOUT can be
placed on the bottom layer under the VIN and VOUT pads when using multiple vias to connect copper pads on the
top and bottom layers.
• Connect differential remote sensing traces to the regulation point to achieve a tight output voltage regulation. Route a
trace from VSEN+ and VSEN- to the point-of-load where tight output voltage is desired. Avoid routing any sensitive
signal traces, such as the VSENSE signal, near the VSWH pads.
• For noise sensitive applications, Renesas recommends connecting the VSWH pads only on the top layer; however,
thermal performance is sacrificed. External airflow might be required to keep module heat at desired levels. For
applications in which switching noise is less critical, excellent thermal performance can be achieved in this power
module by increasing the copper mass attached to the VSWH pad. To increase copper mass on the VSWH node,
create copper islands in the middle and bottom layers under the VSWH pad and connect them to the top layer with
multiple vias. Shield those copper islands with a PGND layer to avoid any interference to noise sensitive signals.
4.1
Thermal Considerations and Current Derating
Board layout is critical for safe module operation and maximum allowable power delivery. To work in high
temperature environments and carry large currents, the board layout needs to be carefully designed to maximize
thermal performance. To achieve this, select enough trace width, copper weight, and the proper connectors.
The RTKA2108332H00000BU evaluation board is designed for running 33A at room temperature without additional
cooling systems. However, if the output voltage is increased or the board is operated at elevated temperatures, then the
available current is derated. Refer to the derated current curves in the RAA210833 datasheet to determine the
maximum output current the evaluation board can supply. JA is measured by inserting a thermocouple inside the
module to measure peak junction temperature.
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RTKA2108332H00000BU
4.2
4. PCB Layout Guidelines
Board Pictures
PGOOD LED
ENABLE Switch
Connect to ZLUSBEVAL3Z
Dongle. For multiple board
evaluation, connect to
PMBUS DONGLE OUT
connection of the other
board
To Daisy Chain PMBus
Connection
Placeholder for SMA
Connector to monitor
VOUT ripple
Figure 4. RTKA2108332H00000BU Evaluation Board (Top Side)
Pinstrap resistor
placeholders
Figure 5. RTKA2108332H00000BU Evaluation Board (Bottom Side)
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RTKA2108332H00000BU
RTKA2108332H00000BU Board Schematic
COMMUNICATION CONNECTION
D1
PREQUEL
1
3
5
1 2
3 4
5 6
SALRT
2
4
6
VR5
OUT
VOUT+
SEQUEL
E
J7
C17
SDA
SCL
VI2C
1K
SALRT
2
4
6
1 2
3 4
5 6
R12
1
3
5
10K
SDA
SCL
VI2C
UNNAMED_1_SMLED_I8_B
J5
R11
J3
UNNAMED_1_NCHANNEL_I13_D
E
3
U1
Q1
UNNAMED_1_NCHANNEL_I13_G
V25
OUT
1UF
UG179 Rev.0.00
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4.3
1
2N7002
2
RAA2108332GLG
E
0
VSWH
13
SGND
PGND
NC
NC
NC
NC
NC
4
5
22
26
32
200
DNP
31
34
NC
NC
3
R13
23
C29
40
PGND
470UF
SGND
C28
PGND
SGND
27
C16
C15
TP13
12
470UF
PGND
DNP
C14
100UF
C13
E
33
S1
DNP
IN
VOUTTP8
SS/UVLO
ASCR
J9
IN
0
30
R18
V25
R10
470UF
VSWH
R9
C27
DNP
E
CFG
VSEN-
470UF
R17
TP2
PHASE
VSEN+
7
C26
15
GND
VSET
6
C25
2
VSEN-
OPEN
29
ASCR
VSEN+
VDRVOUT
VOUT
C24
UVLO
J2
VDD
VDRVIN
E
OPEN
100UF
24
C3
UNNAMED_1_SMCAP_I99_B
0
14
100UF
25
CFG
VOUT
4.7UF
41
C23
VSET
VIN
10
R14
J8
TP9
100UF
8
VR55
SYNC
VOUT+
TP7
C10
100UF
9
VCC
UNNAMED_1_SMCAP_I81_B
C22
C8
10UF
C6
22UF
22UF
C5
C4
22UF
C2
150UF
C1
C7
0
VIN
VDRVIN
VDRVOUT
EN
VR6
35
C21
10UF
E
R3
S1
J1
VR6
VOUT= +0.6 - 5V
TP6
OPEN
TP1
VIN= +4.5-14V
SCL
OUT
TP5
36
100UF
16
VR5
100UF
R21
11
C9
DNP
R2
19.6K
4.99K
39
S1
150UF
17
SW1
SDA
TP4
VDDC
37
C12
EN
UNNAMED_1_GTSERIES_I35_NO
VDDC
C20
S1
2
R15
1
18
UNNAMED_1_GTSERIES_I35_NC
V25
SALRT
VOUT
S1
100UF
SCL
S1
3
19
SA
38
C11
R5
10K
20
SDA
28
100UF
IN
DNP
SYNC
10UF
VR5
SALRT
1 2
PG
C19
J4
TP3
R1
21
C18
SA
NC
100UF
1
R19
E
DNP
R20
E
R8
51.1K
R7
DNP
R16
DNP
R6
VSEN+
DNP
DNP
1 2
J10
VSEN-
EGND TIED TO SND_S1
S1
UNDER DUT
E
EGND
Figure 6. Schematic
Page 11 of 21
4. PCB Layout Guidelines
S1
GND_S1
RTKA2108332H00000BU
4. PCB Layout Guidelines
4.4
Bill of Materials
Qty
Reference
Designator
1
2
4
2
10
C1, C2
Description
Manufacturer Part
PCB, RTKA2108332H00000BU, ROHS Renesas
PCB, RTKA2108332H00000BU
CAP-POSCAP, SMD, 7.3x4.3, 150μF,
16V, 20%, 50mΩ, ROHS
Sanyo/
Panasonic
16TQC150MYF
Sanyo
6TPE470MI
TDK
C3225X5R0J107M
Murata
GRM188R61C106MA73D
CAP CER 4.7μF, 16V, 10%, X5R, 0603, Murata
ROHS
GRM188R61C475KAAJD
C26, C27, C28, C29 CAP TANT POLY 470μF, 6.3V, 20%,
18mΩ 2917, ROHS
C15, C16
Manufacturer
DO NOT POPULATE_PLACE
HOLDER
C11, C12, C13, C14, CAP CER 100μF, 6.3V, 20%, X5R,
C18, C19, C20, C22, 1210, ROHS
C23, C24
2
C7, C8
1
C10
3
C4, C5, C6
CAP CER 22μF, 25V, 10%, X7R, 1210,
ROHS
Murata
GRM32ER71E226KE15L
1
C17
CAP CER 1μF, 6.3V, 10%, X5R, 0402,
ROHS
Panasonic
ECJ-0EB0J105K
1
C3
DO NOT POPULATE_PLACE
HOLDER
1
C9
CAP CER 10μF, 25V, 10%, X5R, 0805,
ROHS
TDK
C2012X5R1E106K
2
C21, C25
RES SMD 0Ω JUMPER, 1/10W, 0603,
ROHS
Panasonic
ERJ-3GEY0R00V
9
CAP CER 10μF, 16V, 20%, X5R, 0603,
ROHS
DO NOT POPULATE_PLACE
HOLDER
DO NOT POPULATE_PLACE
R5, R6, R7, R16,
R17, R18, R19, R20, HOLDER
R21
4
R3, R9, R10, R14
1
R12
RES SMD 1kΩ, 1%, 1/10W, 0603,
ROHS
Panasonic
ERJ-3EKF1001V
2
R1, R11
RES SMD 10kΩ, 1%, 1/10W, 0603,
ROHS
Panasonic
ERJ-3EKF1002V
1
R2
RES SMD 19.6kΩ, 1%, 1/10W, 0603,
ROHS
Panasonic
ERJ-3EKF1962V
1
R15
RES SMD 4.99kΩ, 1%, 1/10W, 0603,
ROHS
Panasonic
ERJ-3EKF4991V
1
R8
RES SMD 51.1kΩ, 1%, 1/10W, 0603,
ROHS
Panasonic
ERJ-3EKF5112V
1
R13
RES SMD 200Ω, 1%, 1/4W, 1206,
ROHS
Panasonic
ERJ-8ENF2000V
1
U1
33A Digital DC/DC PMBus Power
Supply Module, ROHS
Renesas
RAA2108332GLG
1
D1
LED, SMD, 0805, GREEN, CLEAR,
10mcd, 2.1V, 20mA, 570nm, ROHS
Chicago Miniature Lamp
CMD17-21VGC-TR8
1
Q1
MOSFET N-CH 60V 115MA SOT-23,
ROHS
Fairchild
2N7002
UG179 Rev.0.00
Sep 12, 2018
Page 12 of 21
RTKA2108332H00000BU
Qty
Reference
Designator
1
SW1
8
4. PCB Layout Guidelines
Description
SWITCH-TOGGLE, THRU-HOLE,
SPDT, 5P, ROHS
TP1, TP3, TP4, TP5, CONN-MINI TEST PT, VERTICAL,
TP6, TP7, TP8, TP9 RED, ROHS
Manufacturer
Manufacturer Part
C&K
GT11MCBE
Keystone
5000
2
TP2, TP13
CONN-MINI TEST PT, VERTICAL,
BLK, ROHS
Keystone
5001
2
J1, J2
CONN-JACK, MINI BANANA, 0.175
PLUG, NICKEL/BRASS, ROHS
Keystone
575-4
2
J8, J9
HDWARE, MTG, CABLE TERMINAL,
6-14AWG, LUG&SCREW, ROHS
Burndy
KPA8CTP
1
J5
CONN-SOCKET STRIP, TH, 2x3,
2.54mm, TIN, R/A, ROHS
Samtec
SSQ-103-02-T-D-RA
2
J4, J10
CONN HEADER 2POS .100" SNGL,
ROHS
Samtec
TSW-102-07-F-S
1
J3
CONN-HEADER, 2x3, BRKAWY,
2.54mm, TIN, R/A, ROHS
Samtec
TSW-103-08-T-D-RA
1
J7
SMA Straight Jack Receptacle, ROHS
Johnson Components
142-0711-231
UG179 Rev.0.00
Sep 12, 2018
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RTKA2108332H00000BU
4.5
4. PCB Layout Guidelines
RTKA2108332H00000BU Board Layout
Figure 7. Silkscreen Top
Figure 8. PCB - Top Layer Component Side
UG179 Rev.0.00
Sep 12, 2018
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RTKA2108332H00000BU
4. PCB Layout Guidelines
Figure 9. PCB - Layer 2
Figure 10. PCB - Layer 3
UG179 Rev.0.00
Sep 12, 2018
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RTKA2108332H00000BU
4. PCB Layout Guidelines
Figure 11. PCB - Layer 4 (Bottom Layer Solder Side)
Figure 12. Silkscreen Bottom
UG179 Rev.0.00
Sep 12, 2018
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RTKA2108332H00000BU
5.
5. Typical Performance Curves
Typical Performance Curves
100
100
95
95
90
90
Efficiency (KHz)
Efficiency (%)
The following data was acquired using an RTKA2108332H00000BU evaluation board.
85
80
75
70
5Vout
1.8Vout
1Vout
65
3.3Vout
1.5Vout
0.9Vout
2.5Vout
1.2Vout
0.8Vout
85
80
75
70
65
60
3.3Vout
2.5Vout
1.8Vout
1.5Vout
1.2Vout
1Vout
0.9Vout
0.8Vout
0.7Vout
60
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 33
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 33
IOUT (A)
IOUT (A)
Figure 14. Efficiency vs Output Current at VIN = 5V and
fSW = 364kHz for Various Output Voltages
95
95
90
90
Efficiency (%)
Efficiency (%)
Figure 13. Efficiency vs Output Current at VIN = 12V and
fSW = 364kHz for Various Output Voltages
85
80
75
70
0.7Vout
1Vout
1.8Vout
5Vout
0.8Vout
1.2Vout
2.5Vout
0.9Vout
1.5Vout
3.3Vout
85
80
75
0.7Vout
1Vout
1.8Vout
0.8Vout
1.2Vout
2.5Vout
70
Switching Frequency (kHz)
Switching Frequency (kHz)
Figure 15. Efficiency vs Switching Frequency at VIN = 12V
and IOUT = 33A for Various Output Voltages
VOUT (50mV/Div)
Figure 16. Efficiency vs Switching Frequency at VIN = 5V
and IOUT = 33A for Various Output Voltages
VOUT (50mV/Div)
IOUT (10A/Div)
IOUT (10A/Div)
IOUT Slew Rate = 15A/µs
IOUT Slew Rate = 15A/µs
100µs/Div
Figure 17. 5VIN to 1.2VOUT, fSW = 364kHz,
COUT = 10x100µF Ceramic + 4x470µF POSCAP,
ASCR Residual = 90, ASCR Gain = 250
UG179 Rev.0.00
Sep 12, 2018
0.9Vout
1.5Vout
3.3Vout
100µs/Div
Figure 18. 12VIN to 1.2VOUT, fSW = 364kHz,
COUT = 10x100µF Ceramic + 4x470µF POSCAP,
ASCR Residual = 90, ASCR Gain = 250
Page 17 of 21
RTKA2108332H00000BU
5. Typical Performance Curves
The following data was acquired using an RTKA2108332H00000BU evaluation board. (Continued)
SW (10V/Div)
SW (10V/Div)
IOUT (20A/Div)
IOUT (20A/Div)
VOUT (500mV/Div)
VOUT (500mV/Div)
PG (5V/Div)
PG (5V/Div)
5ms/Div
5ms/Div
Figure 19. Startup at 12VIN, 1.2VOUT, 33A
Figure 20. Soft-Off at 12VIN, 1.2VOUT, 33A
UG179 Rev.0.00
Sep 12, 2018
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RTKA2108332H00000BU
6.
6. Revision History
Revision History
Rev.
Date
0.00
Sep 12, 2018
UG179 Rev.0.00
Sep 12, 2018
Description
Initial release
Page 19 of 21
Notice
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Colophon 7.1
RTKA2108332H00000BU
UG179
