RX62T

Datasheet RX62T Group Renesas MCUs 100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data register, amplifier, comparator): two units, 10-bit ADC one unit, the three ADC units are capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary channels and four single-phase complementary channels or three three-phase complementary channels and one single-phase complementary channel) R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Features ■ 32-bit RX CPU core  Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz  Single precision 32-bit IEEE-754 floating point  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  Divider (fastest instruction execution takes two CPU clock cycles)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions: Ultra-compact code  Background JTAG debugging plus high-speed tracing ■ Operating voltage  Single 3.3- or 5-V supply; 5-V analog supply is possible with 3.3-V products ■ Low-power design and architecture  Four low-power modes ■ On-chip main flash memory, no wait states  100-MHz operation, 10-ns read cycle  No wait states for reading at full CPU speed  64-Kbyte/128-Kbyte/256-Kbyte capacities  For instructions and operands  User code programmable via the SCI or JTAG ■ On-chip data flash memory  Max. 32 Kbytes, reprogrammable up to 30,000 times  Erasing and programming impose no load on the CPU. ■ On-chip SRAM, no wait states  8-Kbyte/16-Kbyte SRAM  For instructions and operands ■ DMA  DTC: The single unit is capable of transfer on multiple channels ■ Reset and supply management  Power-on reset (POR)  Low voltage detection (LVD) with voltage settings ■ Clock functions  External crystal oscillator or internal PLL for operation at 8 to 12.5 MHz  Internal 125-kHz LOCO for the IWDT  Detection of main oscillator stoppage (for IEC 60730 compliance) ■ Independent watchdog timer (for IEC60730compliance)  125-kHz LOCO clock operation  Software is incapable of stopping the robust WDT. PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A 20×20mm, 0.65mm pitch 14×14mm, 0.5mm pitch 14×14mm, 0.65mm pitch 10×10mm, 0.5mm pitch ■ Up to 7 communications interfaces  1: CAN (compliant with ISO11898-1), incorporating 32 mailboxes  3: SCIs, with asynchronous mode (incorporating noise cancellation), clock-synchronous mode, and smart-card interface mode  1: I2C bus interface, capable of SMBus operation  1: RSPI  1: LIN ■ Up to 16 16-bit timers  8: 16-bit MTU3: 100-MHz operation, input capture, output compare, two three-phase complementary PWM output channels, complementary PWM imposing no load on the CPU, phase-counting mode  4: 16-bit GPT: 100-MHz operation, input capture, output compare, four complementary single-phase PWM output channels, or one three-phase complementary PWM output channel and one single-phase complementary PWM output channel, complementary PWM imposing no load on the CPU, operation linked with comparator (for counting and control of PWM-signal negation), detection of abnormal oscillation frequencies (for IEC 60730 compliance)  4: 16-bit CMT ■ Three A/D converter units for 1-MHz operation, for a total of 20 channels  Three units are capable of simultaneous sampling on seven channels  Self diagnosis (for IEC60730 compliance)  8: Two 12-bit ADC units: three sample-and-hold circuits, double data registers, amplifier, comparator  12: Single 10-bit ADC unit ■ CRC (cyclic redundancy check) calculation unit  Monitoring of data being transferred (for IEC 60730 compliance)  Monitoring of data in memory (for IEC 60730 compliance) ■ Up to 61 input–output ports and up to 21 input-only ports  PORT registers: Monitoring of output ports (for IEC 60730 compliance) ■ Operating temp. range  –40C to +85C R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 1 of 92 RX62T Group 1. Overview 1. 1.1 Overview Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products. Table 1.1 Outline of Specifications (1 / 5) Module/Function CPU                   Description Maximum operating frequency: 100MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 Floating-point instructions: 8 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 x 32  64 bits On-chip divider: 32 / 32  32 bits Barrel shifter: 32 bits Classification CPU FPU Memory ROM  Single precision (32-bit) floating point  Data types and floating-point exceptions in conformance with the IEEE754 standard       ROM capacity: 256 Kbytes (max.) Two on-board programming modes Boot mode (The user MAT is programmable via the SCI) User program mode Off-board programming A PROM programmer can be used to program the user mat. RAM Data flash MCU operating mode Clock Clock generation circuit  RAM capacity: 16 Kbytes (max.)  Data flash capacity: 32 Kbytes (max.)  Supports background operations (BGO)  Single-chip mode  One circuit: Main clock oscillator  Internal oscillator: Low-speed on-chip oscillator dedicated to IWDT  Structure of a PLL frequency synthesizer and frequency divider for selectable operating frequency  Oscillation stoppage detection  Independent frequency-division and multiplication settings for the system clock (ICLK) and peripheral module clock (PCLK)  The CPU and system sections such as other bus masters, MTU3, and GPT run in synchronization with the system clock (ICLK): 8 to 100 MHz.  Peripheral modules run in synchronization with the peripheral module clock (PCLK): 8 to 50 MHz Pin reset, power-on reset (automatic power-on reset when the power is turned on), voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, and deep software standby reset When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset or internal interrupt is generated.  Module stop function  Four low power consumption modes  Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode Reset Voltage detection circuit (LVD) Low power consumption Low power consumption facilities R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 2 of 92 RX62T Group Table 1.1 Outline of Specifications (2 / 5) Module/Function Interrupt control unit (ICU) Description 1. Overview Classification Interrupt  Peripheral function interrupts: 101 sources  External interrupts: 9 (NMI and IRQ0 to IRQ7 pins)  Non-maskable interrupts: 3 (the NMI pin, oscillation stop detection interrupt, and voltagemonitoring interrupt)  16 levels specifiable for the order of priority  Three transfer modes: Normal transfer, repeat transfer, and block transfer  Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral functions I/O port pins for devices in the 112-pin LQFP/100-pin LQFP/80-pin LQFP/64-pin LQFP  I/O: 61/55/44/37  Input only: 21/21/13/9  Open-drain outputs: 2/2/2/2 (I2C bus interface pins)  Large-current outputs: 12/12/6/6(0) (MTU3 and GPT pins) The 5-V version of the 64-pin product does not have large-current outputs.  Reading out the states of pins is always possible.  16 bits x 8 channels  Up to 24 pulse inputs/outputs and three pulse inputs  Select from among six to eight counter-input clock signals for each channel (ICLK/1, ICLK/4, ICLK/16, ICLK/64, ICLK/256, ICLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for which only four signals are available.  24 output compare or input capture registers  Counter clearing (clearing is synchronizable with compare match or input capture)  Simultaneous writing to multiple timer counters (TCNT)  Input to and output from all registers in synchronization with counter operation  Buffered operation  Cascade-connected operation  38 kinds of interrupt source  Automatic transfer of register data  Pulse output modes Toggled, PWM, complementary PWM, and reset synchronous PWM  Complementary PWM output mode Outputs non-overlapping waveforms for controlling 3-phase inverters Automatic specification of dead times PWM duty cycle: Selectable as any value from 0% to 100% Delay can be applied to requests for A/D conversion. Non-generation of interrupt requests at peak or trough values of counters can be selected. Double buffering  Reset-synchronous PWM mode Three PWM waveforms and corresponding inverse waveforms are output with the desired duty cycles.  Phase-counting mode  Counter functionality for dead-time compensation  Generation of triggers for A/D converters  Differential timing for initiation of A/D conversion  Control of the high-impedance state of the MTU3 and GPT’s waveform output pins 5 pins for input from signal sources: POE0, POE4, POE8, POE10, POE11 Initiation on detection of short-circuited outputs (detection of simultaneous switching of large-current pins to the active level) Initiation by comparator-detection of analog level input to the 12-bit A/D converter Initiation by oscillation-stoppage detection Initiation by software  Selection of which output pins should be placed in the high-impedance state at the time of each POE input or comparator detection Data transfer Data transfer controller (DTC) Programmable I/O ports I/O ports Timers Multi-function timer pulse unit 3 (MTU3) Port output enable 3 (POE3) R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 3 of 92 RX62T Group Table 1.1 Outline of Specifications (3 / 5) Module/Function General PWM timer (GPT) Description 1. Overview Classification Timers  16 bits x 4 channels  Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels  Clock sources independently selectable for all channels  2 input/output pins per channel  2 output compare/input capture registers per channel  For the 2 output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use.  In output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically PWM waveforms.  Registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow)  Synchronizable operation of the several counters  Modes of synchronized operation (synchronized, or displaced by desired times for phase shifting)  Generation of dead times in PWM operation  Through combination of three counters, generation of automatic three-phase PWM waveforms incorporating dead times  Starting, clearing, and stopping counters in response to external or internal triggers  Internal trigger sources: output of the internal comparator detection, software, and compare-match  The frequency-divided system clock (ICLK) can be used as a counter clock for measuring timing of the edges of signals produced by frequency-dividing the low-speed on-chip oscillator clock signal dedicated to IWDT (to detect abnormal oscillation).  (16 bits x 2 channels) x 2 units  Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)  8 bits x 1 channel  Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072)  Switchable between watchdog timer mode and interval timer mode  14 bits x 1 channel  Counter-input clock: low-speed on-chip oscillator dedicated to IWDT  3 channels  Serial communications modes: Asynchronous, clock synchronous, and smart-card interface  Multiprocessor communications  On-chip baud rate generator allows selection of the desired bit rate  Choice of LSB-first or MSB-first transfer  Noise cancellation (only available in asynchronous mode)  1 channel  Communications formats I2C bus format/SMBus format Master/slave selectable Compare match timer (CMT) Watchdog timer (WDT) Independent watchdog timer (IWDT) Communications Serial communications interface (SCIb) I2C bus interface (RIIC) R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 4 of 92 RX62T Group Table 1.1 Outline of Specifications (4 / 5) Module/Function CAN module (CAN) (as an optional function) Serial peripheral interface (RSPI)  1 channel  32 mailboxes Description 1. Overview Classification Communications  1 unit  RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave  Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits)  Buffered structure  Double buffers for both transmission and reception  1 channel (LIN master)  Supports revisions 1.3, 2.0, and 2.1 of the LIN protocol  12 bits (2 units x 4 channels)  12-bit resolution  Conversion time: 1.0 s per channel (in operation with A/D conversion clock ADCLK at 50 MHz) for AVCC = 4.0 to 5.5 V 2.0 s per channel (in operation with A/D conversion clock ADCLK at 25 MHz) for AVCC0 = 3.0 to 3.6 V  Two basic operating modes Single mode and scan mode  Scan mode One-cycle scan mode Continuous scan mode 2-channel scan mode (Input ports of the A/D unit are divided into two groups in this mode, and the activation sources are separately selectable for each group.)  Sample-and-hold function A common sample-and-hold circuit for both units is included. Additionally, sample-and-hold circuit for each unit is included. (three channels per unit)  A/D-conversion register settings for each input pin.  Two registers for the result of conversion are provided for a single analog input pin of each unit (AN000 and AN100).  Three ways to start A/D conversion Conversion can be started by software, a conversion start trigger from a timer (MTU3 or GPT), or an external trigger signal.  Functionality for 8- or 10-bit precision output Right-shifting of the results of conversion for output by two or four bits is selectable.  Self-diagnostic function The self-diagnostic function internally generates three analog input voltages (VREFL0, VREFH0 x 1/2, VREFH0).  Amplification of input signals by a programmable gain amplifier (three channels per unit) Amplification rate: 2.0-, 2.5-, 3.077-, 3.636-, 4.0-, 4.444-, 5.0-, 5.714-, 6.667-, 10.0-, or 13.333-times amplification (a total of 11 steps)  Window comparators (three channels per unit) LIN module (LIN) A/D converter 12-bit A/D converter (S12ADA) R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 5 of 92 RX62T Group Table 1.1 Outline of Specifications (5 / 5) Module/Function 10-bit A/D converter (ADA) Description 1. Overview Classification A/D converter  10 bits (1 unit x 12 channels)  10-bit resolution  Conversion time: 1.0 s per channel (in operation with A/D conversion clock ADCLK at 50 MHz) for AVCC0 = 4.0 to 5.5 V 2.0 s per channel (in operation with A/D conversion clock ADCLK at 25 MHz) for AVCC = 3.0 to 3.6 V  Two basic operating modes Single mode and scan mode  Scan mode One-cycle scan mode Continuous scan mode  Sample-and-hold function A common sample-and-hold circuit for both units is included.  A/D-conversion register settings for each input pin  Three ways to start A/D conversion Conversion can be started by software, a conversion start trigger from a timer (MTU3 or GPT), or an external trigger signal.  Functionality for 8-bit precision output Right-shifting the results of conversion for output by two bits is selectable.  Self-diagnostic function The self-diagnostic function internally generates three analog input voltages (AVSS, VREF x 1/2, VREF).  CRC code generation for arbitrary amounts of data in 8-bit units  Select any of three generating polynomials: X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.  Generation of CRC codes for use with LSB-first or MSB-first communications is selectable. ICLK: 8 to 100 MHz PCLK: 8 to 50 MHz  3-V version VCC = PLLVCC = 2.7 to 3.6V AVCC0 = AVCC = 3.0 to 3.6V, or 4.0 to 5.5V VREFH0 = 3.0 to AVCC0, or 4.0 to AVCC0 VREF = 3.0 to AVCC, or 4.0 to AVCC  5-V version VCC = PLLVCC = 4.0 to 5.5V AVCC0 = AVCC = 4.0 to 5.5V VREFH0 = 4.0 to AVCC0 VREF = 4.0 to AVCC 40 to +85C 112-pin LQFP (PLQP0112JA-A, 20x20-0.65-mm pitch) 100-pin LQFP (PLQP0100KB-A, 14x14-0.5-mm pitch) 80-pin LQFP (PLQP0080JA-A, 14x14-0.65-mm pitch) 64-pin LQFP (PLQP0064KB-A, 10x10-0.5-mm pitch) CRC calculator (CRC) Operating frequency Power supply voltage Operating temperature Packages R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 6 of 92 RX62T Group 1. Overview Table 1.2 Functions Pin number Data transfer Interrupt control unit (ICU) Timers Functions of RX62T Group Products RX62T Group 112 Pin Data transfer controller (DTC) Input on the NMI pin Input on the IRQ pins Multi-function timer pulse unit 3 (MTU3) General PWM timer (GPT) Port output enable 3 (POE3) Compare match timer (CMT) Watchdog timer (WDT) Independent watchdog timer (IWDT) O O O (POE pins: 5) O O O O O O O O O (4 ch. x 2 units) O (2 units) O (3 ch. x 2 units) O (3 ch. x 2 units) O (12 ch.) O 61 21 LQFP2020 (0.65-mm pitch) 55 21 LQFP1414 (0.5-mm pitch) 44 13 LQFP1414 (0.65-mm pitch) 37 9 LQFP1010 (0.5-mm pitch) O (4 ch.) ¾ O (8) O* O* O (POE pins: 3) 100 Pin O O O (4) 80 Pin 64 Pin Communication function Serial communications interface (SCI) I2C bus interface (RIIC) CAN module (CAN) (as an optional function) LIN module (LIN) Serial peripheral interface (RSPI) 12-bit A/D converter (S12ADA) Simultaneous sampling on three channels Programmable gain amplifier Window comparator 10-bit A/D converter (ADA) CRC calculator (CRC) I/O ports I/O pins Input pins Package Note 1. O: Supported, : Not supported Note 2. * For the MTU and GPT, the number of pins will differ with the package. See the list of pins and pin functions for details. In addition, the CAN module is an optional function. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 7 of 92 RX62T Group 1. Overview 1.2 List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no. Table 1.3 List of Products Package Group RX62T Operating Voltage Pin Pitch 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.65 mm 0.5 mm Part No. R5F562TAADFH R5F562TAADFP R5F562TAADFF R5F562TAADFM R5F562T7ADFH R5F562T7ADFP R5F562T7ADFF R5F562T7ADFM R5F562T6ADFF R5F562T6ADFM R5F562TABDFH R5F562TABDFP R5F562TABDFF R5F562TABDFM R5F562T7BDFH R5F562T7BDFP R5F562T7BDFF R5F562T7BDFM R5F562T6BDFF R5F562T6BDFM R5F562TADDFH R5F562TADDFP R5F562TADDFF R5F562TADDFM R5F562T7DDFH R5F562T7DDFP R5F562T7DDFF R5F562T7DDFM R5F562T6DFFF R5F562T6DDFM R5F562TAEDFH R5F562TAEDFP R5F562TAEDFF R5F562TAEDFM R5F562T7EDFH R5F562T7EDFP R5F562T7EDFF R5F562T7EDFM R5F562T6EDFF R5F562T6EDFM Package Type LQFP2020-112 LQFP1414-100 LQFP1414-80 LQFP1010-64 LQFP2020-112 LQFP1414-100 LQFP1414-80 LQFP1010-64 LQFP1414-80 LQFP1010-64 LQFP2020-112 LQFP1414-100 LQFP1414-80 LQFP1010-64 LQFP2020-112 LQFP1414-100 LQFP1414-80 LQFP1010-64 LQFP1414-80 LQFP1010-64 LQFP2020-112 LQFP1414-100 LQFP1414-80 LQFP1010-64 LQFP2020-112 LQFP1414-100 LQFP1414-80 LQFP1010-64 LQFP1414-80 LQFP1010-64 LQFP2020-112 LQFP1414-100 LQFP1414-80 LQFP1010-64 LQFP2020-112 LQFP1414-100 LQFP1414-80 LQFP1010-64 LQFP1414-80 LQFP1010-64 Package Code PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A PLQP0080JA-A PLQP0064KB-A PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A PLQP0080JA-A PLQP0064KB-A PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A PLQP0080JA-A PLQP0064KB-A PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A PLQP0112JA-A PLQP0100KB-A PLQP0080JA-A PLQP0064KB-A PLQP0080JA-A PLQP0064KB-A Operating Frequency (Max.) 100 MHz ROM Capacity 256 Kbytes RAM Capacity 16 Kbytes Data Flash 32K bytes VCC/ PLLVCC 4.0 to 5.5 V AVCC/ AVCC0 4.0 to 5.5 V CAN Supp orted 128 Kbytes 8 Kbytes 8K bytes 64 Kbytes 8 Kbytes 256 Kbytes 16 Kbytes 32K bytes 2.7 to 3.6 V 3.0 to 3.6 V or 4.0 to 5.5 V 128 Kbytes 8 Kbytes 8K bytes 64 Kbytes 8 Kbytes 256 Kbytes 16 Kbytes 32K bytes 4.0 to 5.5 V 4.0 to 5.5 V Not supp orted 128 Kbytes 8 Kbytes 8K bytes 64 Kbytes 8 Kbytes 256 Kbytes 16 Kbytes 32K bytes 2.7 to 3.6 V 3.0 to 3.6 V or 4.0 to 5.5 V 128 Kbytes 8 Kbytes 8K bytes 64 Kbytes 8 Kbytes R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 8 of 92 RX62T Group 1. Overview R 5F 56 2TA BD FH Indicates the package type, number of pins, and pin pitch. FH: LQFP112-0.65 FP: LQFP100-0.50 FF: LQFP80-0.65 FM: LQFP64-0.50 A: 5-V version, CAN 1 channel B: 3-V version, CAN 1 channel D: 5-V version, CAN not supported E: 3-V version, CAN not supported Indicates the ROM capacity, RAM capacity, and data flash capacity. A: 256 Kbytes/16 Kbytes/32 Kbytes 7: 128 Kbytes/8 Kbytes/8 Kbytes 6: 64 Kbytes/8 Kbytes/8 Kbytes Indicates a group name. 2T: RX62T Group Indicates a series name (RX600 Series) Indicates the type of memory. F: Flash memory version Indicates a Renesas MCU. Indicates a Renesas semiconductor product. Figure 1.1 How to Read the Product Part No. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 9 of 92 RX62T Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram. Data flash WDT IWDT CRC SCI  3 channels RSPI CAN (as an optional function) LIN POE3 Internal peripheral buses 1 to 6 *2 CMT  2 channels (unit 0) CMT  2 channels (unit 1) *1 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 RIIC 12-bit A/D converter  4 channels (unit 0) Programmable gain amps  3 channels Sample-and-hold circuits for the pin section  3 channels Window comparator  3 channels MTU3 GPT ROM Internal main bus 2 ICU DTC 12-bit A/D converter  4 channels (unit 1) Programmable gain amps  3 channels Sample-and-hold circuits for the pin section  3 channels Window comparator  3 channels Port 7 Port 8 Port 9 Port A Port B Instruction bus Operand bus RAM RX CPU Clock generation circuit Internal main bus 1 * 10-bit A/D converter  12 channels Port D Port E Port G 1 POR LVD [Legend] POR: Power-on reset circuit DTC: Data transfer controller MTU3: Multi-function timer pulse unit 3 POE3: Port output enable 3 GPT: General PWM timer CMT: Compare match timer SCI: Serial communications interface RIIC: I2C bus interface Notes: CAN: CAN module LIN: LIN module RSPI: Renesas serial peripheral interface LVD: Voltage detection circuit ICU: Interrupt control unit WDT: Watchdog timer IWDT: Independent watchdog timer CRC: CRC (cyclic redundancy check) calculator 1. The installation of the 10-bit A/D converter and ports 1 to G is different depending on the package. 2. For details on the internal peripheral bus configuration, see section 12, Buses in the User's Manual: Hardware. Figure 1.2 Block Diagram R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 10 of 92 RX62T Group 1. Overview 1.4 Pin Assignments Figure 1.3 to Figure 1.6 show the pins assignments. Table 1.4 to Table 1.7 show the list of pins and pin functions. P61/AN1 P60/AN0 P55/AN11 P54/AN10 P53/AN9 P52/AN8 P51/AN7 P50/AN6 P47/AN103/CVREFH P46/AN102 P45/AN101 P44/AN100 P43/AN003/CVREFL P42/AN002 P41/AN001 P40/AN000 AVCC0 VREFH0 VREFL0 AVSS0 P82/MTIC5U/SCK2-B P81/MTIC5V/TXD2-B P80/MTIC5W/RXD2-B WDTOVF# P11/MTCLKC-B/IRQ1-A P10/MTCLKD-B/IRQ0-A TRST# TMS 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 P62/AN2 P63/AN3 AVSS VREF AVCC P64/AN4 P65/AN5 P20/ADTRG0#-B/MTCLKB-B/IRQ7 P21/ADTRG1#-B/MTCLKA-B/IRQ6 P22/ADTRG#/CRX-B/LRX/MISO-A P23/CTX-B/LTX/MOSI-A P24/RSPCK-A P30/MTIOC0B-B/MTCLKD-A/SSL0-A VSS P31/MTIOC0A-B/MTCLKC-A/SSL1-A VCC P32/MTIOC3C/MTCLKB-A/SSL2-A P33/MTIOC3A/MTCLKA-A/SSL3-A P70/IRQ5/POE0# P71/MTIOC3B/GTIOC0A-A P72/MTIOC4A/GTIOC1A-A P73/MTIOC4B/GTIOC2A-A P74/MTIOC3D/GTIOC0B-A P75/MTIOC4C/GTIOC1B-A P76/MTIOC4D/GTIOC2B-A PG0/IRQ0-C/TRSYNC PG1/IRQ1-C/TRDATA0 PG2/IRQ2-B/TRDATA1 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 RX62T Group PLQP0112JA-A (112-pin LQFP) (Top view) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PG3/TRDATA2 PG4/TRDATA3 PG5/TRCLK P90/MTIOC7D P91/MTIOC7C P92/MTIOC6D P93/MTIOC7B P94/MTIOC7A P95/MTIOC6B VSS P96/IRQ4/POE4# VCC PA0/MTIOC6C/SSL3-B PA1/MTIOC6A/SSL2-B PA2/MTIOC2B/SSL1-B PA3/MTIOC2A/SSL0-B PA4/ADTRG0#-A/MTIOC1B/RSPCK-B PA5/ADTRG1#-A/MTIOC1A/MISO-B PB0/MTIOC0D/MOSI-B PB1/MTIOC0C/RXD0/SCL PB2/MTIOC0B-A/TXD0/SDA PB3/MTIOC0A-A/SCK0 PLLVSS PB4/GTETRG/IRQ3/POE8# PLLVCC PB5/CTX-A/TXD2-A PB6/CRX-A/RXD2-A PB7/SCK2-A Figure 1.3 Pin Assignment of the 112-Pin LQFP R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 PE5/IRQ0-B EMLE VSS MDE VCL MD1 MD0 PE4/MTCLKC-C/IRQ1-B/POE10#-B PE3/MTCLKD-C/IRQ2-A/POE11# RES# XTAL VSS EXTAL VCC PE2/NMI/POE10#-A PE1/SSL3-C PE0/CRX-C/SSL2-C PD7/GTIOC0A-B/CTX-C/SSL1-C PD6/GTIOC0B-B/SSL0-C PD5/GTIOC1A-B/RXD1 PD4/GTIOC1B-B/SCK1 PD3/GTIOC2A-B/TXD1 PD2/GTIOC2B-B/MOSI-C PD1/GTIOC3A/MISO-C PD0/GTIOC3B/RSPCK-C TDI TCK TDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Page 11 of 92 RX62T Group 1. Overview P30/MTIOC0B-B/MTCLKD-A/SSL0-A VSS P31/MTIOC0A-B/MTCLKC-A/SSL1-A P20/ADTRG0#-B/MTCLKB-B/IRQ7 P21/ADTRG1#-B/MTCLKA-B/IRQ6 P32/MTIOC3C/MTCLKB-A/SSL2-A P22/ADTRG#/CRX-B/LRX/MISO-A P33/MTIOC3A/MTCLKA-A/SSL3-A P74/MTIOC3D/GTIOC0B-A 53 P75/MTIOC4C/GTIOC1B-A 52 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 51 P76/MTIOC4D/GTIOC2B-A P72/MTIOC4A/GTIOC1A-A P73/MTIOC4B/GTIOC2A-A P71/MTIOC3B/GTIOC0A-A P23/CTX-B/LTX/MOSI-A VCC P70/IRQ5/POE0# P24/RSPCK-A P62/AN2 P63/AN3 AVSS P64/AN4 P65/AN5 AVCC VREF P61/AN1 P60/AN0 P55/AN11 P54/AN10 P53/AN9 P52/AN8 P51/AN7 P50/AN6 P47/AN103/CVREFH P46/AN102 P45/AN101 P44/AN100 P43/AN003/CVREFL P42/AN002 P41/AN001 P40/AN000 AVCC0 VREFH0 VREFL0 AVSS0 P82/MTIC5U/SCK2-B P81/MTIC5V/TXD2-B P80/MTIC5W/RXD2-B P11/MTCLKC-B/IRQ1-A P10/MTCLKD-B/IRQ0-A 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 P90/MTIOC7D P91/MTIOC7C P92/MTIOC6D P93/MTIOC7B P94/MTIOC7A P95/MTIOC6B VSS P96/IRQ4/POE4# VCC PA0/MTIOC6C/SSL3-B PA1/MTIOC6A/SSL2-B PA2/MTIOC2B/SSL1-B PA3/MTIOC2A/SSL0-B PA4/ADTRG0#-A/MTIOC1B/RSPCK-B PA5/ADTRG1#-A/MTIOC1A/MISO-B PB0/MTIOC0D/MOSI-B PB1/MTIOC0C/RXD0/SCL PB2/MTIOC0B-A/TXD0/SDA PB3/MTIOC0A-A/SCK0 PLLVSS PB4/GTETRG/IRQ3/POE8# PLLVCC PB5/CTX-A/TXD2-A/TRSYNC PB6/CRX-A/RXD2-A/TRDATA0 PB7/SCK2-A/TRDATA1 RX62T Group PLQP0100KB-A (100-pin LQFP) (Top view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 PD3/GTIOC2A-B/TXD1/TDO PE0/CRX-C/SSL2-C PE1/SSL3-C VCC PD2/GTIOC2B-B/MOSI-C/TRCLK PD4/GTIOC1B-B/SCK1/TCK PD5/GTIOC1A-B/RXD1/TDI PD1/GTIOC3A/MISO-C/TRDATA3 VSS PD6/GTIOC0B-B/SSL0-C/TMS PE5/IRQ0-B MDE EMLE VSS Figure 1.4 Pin Assignment of the 100-Pin LQFP R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 PD7/GTIOC0A-B/CTX-C/SSL1-C/TRST# PD0/GTIOC3B/RSPCK-C/TRDATA2 EXTAL PE4/MTCLKC-C/IRQ1-B/POE10#-B PE3/MTCLKD-C/IRQ2-A/POE11# PE2/NMI/POE10#-A RES# XTAL MD1 MD0 VCL Page 12 of 92 RX62T Group 1. Overview 59 58 57 56 55 54 53 47 46 45 44 43 42 60 52 51 50 49 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P47/AN103/CVREFH P46/AN102 P45/AN101 P44/AN100 P43/AN003/CVREFL P42/AN002 P41/AN001 P40/AN000 AVCC0 VREFH0 VREFL0 AVSS0 P11/MTCLKC-B/IRQ1-A P10/MTCLKD-B/IRQ0-A PA5/ADTRG1#-A/MTIOC1A/MISO-B PA4/ADTRG0#-A/MTIOC1B/RSPCK-B 48 41 AVSS AVCC P20/ADTRG0#-B/MTCLKB-B/IRQ7 P21/ADTRG1#-B/MTCLKA-B/IRQ6 P22/ADTRG#/CRX-B/LRX/MISO-A P23/CTX-B/LTX/MOSI-A P24/RSPCK-A P30/MTIOC0B-B/MTCLKD-A/SSL0-A VSS P31/MTIOC0A-B/MTCLKC-A/SSL1-A VCC P32/MTIOC3C/MTCLKB-A/SSL2-A P33/MTIOC3A/MTCLKA-A/SSL3-A P70/IRQ5/POE0# P71/MTIOC3B/GTIOC0A-A P72/MTIOC4A/GTIOC1A-A P73/MTIOC4B/GTIOC2A-A P74/MTIOC3D/GTIOC0B-A P75/MTIOC4C/GTIOC1B-A P76/MTIOC4D/GTIOC2B-A 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 RX62T Group PLQP0080JA-A (80-pin LQFP) (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 P91/MTIOC7C P92/MTIOC6D P93/MTIOC7B P94/MTIOC7A P95/MTIOC6B VSS P96/IRQ4/POE4# VCC PA2/MTIOC2B/SSL1-B PA3/MTIOC2A/SSL0-B PB0/MTIOC0D/MOSI-B PB1/MTIOC0C/RXD0/SCL PB2/MTIOC0B-A/TXD0/SDA PB3/MTIOC0A-A/SCK0 PLLVSS PB4/GTETRG/IRQ3/POE8# PLLVCC PB5/CTX-A/TxD2-A PB6/CRX-A/RXD2-A PB7/SCK2-A Figure 1.5 Pin Assignment of the 80-Pin LQFP R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 EMLE VSS MDE VCL MD1 MD0 PE4/MTCLKC-C/IRQ1-B/POE10#-B PE3/MTCLKD-C/IRQ2-A/POE11# RES# XTAL VSS EXTAL VCC PE2/NMI/POE10#-A PE0/CRX-C PD7/GTIOC0A-B/CTX-C/TRST# PD6/GTIOC0B-B/TMS PD5/GTIOC1A-B/RXD1/TDI PD4/GTIOC1B-B/SCK1/TCK PD3/GTIOC2A-B/TXD1/TDO Page 13 of 92 RX62T Group 1. Overview P30/MTIOC0B-B/MTCLKD-A/SSL0-A P31/MTIOC0A-B/MTCLKC-A/SSL1-A P32/MTIOC3C/MTCLKB-A/SSL2-A P33/MTIOC3A/MTCLKA-A/SSL3-A P74/MTIOC3D/GTIOC0B-A 35 P75/MTIOC4C/GTIOC1B-A 34 48 47 46 45 44 43 42 41 40 39 38 37 36 P47/AN103/CVREFH P46/AN102 P45/AN101 P44/AN100 P43/AN003/CVREFL P42/AN002 P41/AN001 P40/AN000 AVCC0 VREFH0 VREFL0 AVSS0 P11/MTCLKC-B/IRQ1-A P10/MTCLKD-B/IRQ0-A PA5/ADTRG1#-A/MTIOC1A/MISO-B PA4/ADTRG0#-A/MTIOC1B/RSPCK-B 33 P76/MTIOC4D/GTIOC2B-A P71/MTIOC3B/GTIOC0A-A P72/MTIOC4A/GTIOC1A-A P73/MTIOC4B/GTIOC2A-A P22/CRX-B/LRX/MISO-A P23/CTX-B/LTX/MOSI-A P70/IRQ5/POE0# P24/RSPCK-A VCC VSS 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 P91/MTIOC7C P92/MTIOC6D P93/MTIOC7B P94/MTIOC7A PA2/MTIOC2B/SSL1-B PA3/MTIOC2A/SSL0-B PB0/MTIOC0D/MOSI-B PB1/MTIOC0C/RXD0/SCL PB2/MTIOC0B-A/TXD0/SDA PB3/MTIOC0A-A/SCK0 PLLVSS PB4/GTETRG/IRQ3/POE8# PLLVCC PB5/CTX-A/TXD2-A PB6/CRX-A/RXD2-A PB7/SCK2-A RX62T Group PLQP0064KB-A (64-pin LQFP) (Top view) 26 25 24 23 22 21 20 19 18 17 VCC PD6/GTIOC0B-B/TMS PD4/GTIOC1B-B/SCK1/TCK PD7/GTIOC0A-B/TRST# EXTAL PE2/NMI/POE10#-A EMLE VCL XTAL Figure 1.6 Pin Assignment of the 64-Pin LQFP R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 PD3/GTIOC2A-B/TXD1/TDO MDE MD1 MD0 RES# VSS PD5/GTIOC1A-B/RXD1/TDI Page 14 of 92 RX62T Group 1. Overview Table 1.4 Pin No. (112-Pin LQFP) List of Pins and Pin Functions (112-Pin LQFP) (1 / 3) Power Supply Clock System Control Communication I/O Port Analog Timer Interrupt POE Debugging 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PLLVSS PLLVCC RES# XTAL VSS EXTAL VCC EMLE VSS MDE VCL MD1 MD0 PE5 IRQ0-B PE4 PE3 MTCLKC-C MTCLKD-C IRQ1-B IRQ2-A POE10#-B POE11# PE2 PE1 PE0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 GTIOC0A-B GTIOC0B-B GTIOC1A-B GTIOC1B-B GTIOC2A-B GTIOC2B-B GTIOC3A GTIOC3B SSL3-C CRX-C/ SSL2-C CTX-C/ SSL1-C SSL0-C RXD1 SCK1 TXD1 MOSI-C MISO-C RSPCK-C NMI POE10#-A TDI TCK TDO PB7 PB6 PB5 SCK2-A CRX-A/ RXD2-A CTX-A/ TXD2-A PB4 GTETRG IRQ3 POE8# PB3 PB2 PB1 PB0 PA5 PA4 PA3 PA2 PA1 ADTRG1#-A ADTRG0#-A MTIOC0A-A MTIOC0B-A MTIOC0C MTIOC0D MTIOC1A MTIOC1B MTIOC2A MTIOC2B MTIOC6A SCK0 TXD0/SDA RXD0/SCL MOSI-B MISO-B RSPCK-B SSL0-B SSL1-B SSL2-B R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 15 of 92 RX62T Group Table 1.4 Pin No. (112-Pin LQFP) 1. Overview List of Pins and Pin Functions (112-Pin LQFP) (2 / 3) Power Supply Clock System Control I/O Port Analog Timer Communication Interrupt POE Debugging 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 VSS VCC VSS VCC PA0 MTIOC6C SSL3-B P96 IRQ4 POE4# P95 P94 P93 P92 P91 P90 PG5 PG4 PG3 PG2 PG1 PG0 P76 P75 P74 P73 P72 P71 P70 P33 P32 MTIOC6B MTIOC7A MTIOC7B MTIOC6D MTIOC7C MTIOC7D TRCLK TRDATA3 TRDATA2 IRQ2-B IRQ1-C IRQ0-C MTIOC4D/ GTIOC2B-A MTIOC4C/ GTIOC1B-A MTIOC3D/ GTIOC0B-A MTIOC4B/ GTIOC2A-A MTIOC4A/ GTIOC1A-A MTIOC3B/ GTIOC0A-A IRQ5 MTIOC3A/ MTCLKA-A MTIOC3C/ MTCLKB-A SSL3-A SSL2-A POE0# TRDATA1 TRDATA0 TRSYNC P31 MTIOC0A-B/ MTCLKC-A SSL1-A P30 P24 P23 P22 P21 P20 P65 P64 ADTRG# ADTRG1#-B ADTRG0#-B AN5 AN4 MTIOC0B-B/ MTCLKD-A SSL0-A RSPCK-A CTX-B/ LTX/ MOSI-A CRX-B/ LRX/ MISO-A MTCLKA-B MTCLKB-B IRQ6 IRQ7 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 16 of 92 RX62T Group Table 1.4 Pin No. (112-Pin LQFP) 1. Overview List of Pins and Pin Functions (112-Pin LQFP) (3 / 3) Power Supply Clock System Control I/O Port Analog Timer Communication Interrupt POE Debugging 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 AVCC VREF AVSS P63 P62 P61 P60 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 AVCC0 VREFH0 VREFL0 AVSS0 P82 P81 P80 MTIC5U MTIC5V MTIC5W WDTOVF# P11 P10 MTCLKC-B MTCLKD-B IRQ1-A IRQ0-A TRST# TMS SCK2-B TXD2-B RXD2-B AN3 AN2 AN1 AN0 AN11 AN10 AN9 AN8 AN7 AN6 AN103/ CVREFH AN102 AN101 AN100 AN003/ CVREFL AN002 AN001 AN000 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 17 of 92 RX62T Group 1. Overview Table 1.5 Pin No. (80-Pin LQFP) List of Pins and Pin Functions (100-Pin LQFP) (1 / 3) Power Supply Clock System Control Communication I/O Port Analog Timer Interrupt POE Debugging 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PLLVSS PLLVCC RES# XTAL VSS EXTAL VCC EMLE VSS MDE VCL MD1 MD0 PE5 IRQ0-B PE4 PE3 MTCLKC-C MTCLKD-C IRQ1-B IRQ2-A POE10#-B POE11# PE2 PE1 PE0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PB7 PB6 PB5 GTIOC0A-B GTIOC0B-B GTIOC1A-B GTIOC1B-B GTIOC2A-B GTIOC2B-B GTIOC3A GTIOC3B SSL3-C CRX-C/ SSL2C CTX-C/ SSL1-C SSL0-C RXD1 SCK1 TXD1 MOSI-C MISO-C RSPCK-C SCK2-A CRX-A/ RXD2A CTX-A/ TXD2-A NMI POE10#-A TRST# TMS TDI TCK TDO TRCLK TRDATA3 TRDATA2 TRDATA1 TRDATA0 TRSYNC PB4 GTETRG IRQ3 POE8# PB3 PB2 PB1 PB0 PA5 PA4 PA3 PA2 PA1 ADTRG1#-A ADTRG0#-A MTIOC0A-A MTIOC0B-A MTIOC0C MTIOC0D MTIOC1A MTIOC1B MTIOC2A MTIOC2B MTIOC6A SCK0 TXD0/SDA RXD0/SCL MOSI-B MISO-B RSPCK-B SSL0-B SSL1-B SSL2-B R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 18 of 92 RX62T Group Table 1.5 Pin No. (80-Pin LQFP) 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (2 / 3) Power Supply Clock System Control I/O Port Analog Timer Communication Interrupt POE Debugging 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 AVCC VREF AVSS VSS VCC VSS VCC PA0 MTIOC6C SSL3-B P96 IRQ4 POE4# P95 P94 P93 P92 P91 P90 P76 P75 P74 P73 P72 P71 P70 P33 P32 MTIOC6B MTIOC7A MTIOC7B MTIOC6D MTIOC7C MTIOC7D MTIOC4D/ GTIOC2B-A MTIOC4C/ GTIOC1B-A MTIOC3D/ GTIOC0B-A MTIOC4B/ GTIOC2A-A MTIOC4A/ GTIOC1A-A MTIOC3B/ GTIOC0A-A IRQ5 MTIOC3A/ MTCLKA-A MTIOC3C/ MTCLKB-A SSL3-A SSL2-A POE0# P31 MTIOC0A-B/ MTCLKC-A SSL1-A P30 P24 P23 P22 P21 P20 P65 P64 ADTRG# ADTRG1#-B ADTRG0#-B AN5 AN4 MTIOC0B-B/ MTCLKD-A SSL0-A RSPCK-A CTX-B/ LTX/ MOSI-A CRX-B/ LRX/ MISO-A MTCLKA-B MTCLKB-B IRQ6 IRQ7 P63 P62 P61 AN3 AN2 AN1 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 19 of 92 RX62T Group Table 1.5 Pin No. (80-Pin LQFP) 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (3 / 3) Power Supply Clock System Control I/O Port Analog Timer Communication Interrupt POE Debugging 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 AVCC0 VREFH0 VREFL0 AVSS0 P60 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 AN0 AN11 AN10 AN9 AN8 AN7 AN6 AN103/ CVREFH AN102 AN101 AN100 AN003/ CVREFL AN002 AN001 AN000 P82 P81 P80 P11 P10 MTIC5U MTIC5V MTIC5W MTCLKC-B MTCLKD-B SCK2-B TXD2-B RXD2-B IRQ1-A IRQ0-A R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 20 of 92 RX62T Group 1. Overview Table 1.6 Pin No. (80-Pin LQFP) List of Pins and Pin Functions (80-Pin LQFP) (1 / 3) Power Supply Clock System Control Communication I/O Port Analog Timer Interrupt POE Debugging 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 EMLE VSS MDE VCL MD1 MD0 PE4 PE3 RES# XTAL VSS EXTAL VCC PE2 PE0 PD7 PD6 PD5 PD4 PD3 PB7 PB6 PB5 PLLVCC PB4 PLLVSS PB3 PB2 PB1 PB0 PA3 PA2 VCC P96 VSS P95 P94 P93 P92 P91 P76 MTIOC6B MTIOC7A MTIOC7B MTIOC6D MTIOC7C MTIOC4D/ GTIOC2B-A IRQ4 POE4# MTIOC0A-A MTIOC0B-A MTIOC0C MTIOC0D MTIOC2A MTIOC2B SCK0 TXD0/SDA RXD0/SCL MOSI-B SSL0-B SSL1-B GTETRG IRQ3 POE8# GTIOC0A-B GTIOC0B-B GTIOC1A-B GTIOC1B-B GTIOC2A-B RXD1 SCK1 TXD1 SCK2-A CRX-A/ RXD2-A CTX-A/ TXD2-A CRX-C CTX-C TRST# TMS TDI TCK TDO NMI POE10#-A MTCLKC-C MTCLKD-C IRQ1-B IRQ2-A POE10#-B POE11# R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 21 of 92 RX62T Group Table 1.6 Pin No. (80-Pin LQFP) 1. Overview List of Pins and Pin Functions (80-Pin LQFP) (2 / 3) Power Supply Clock System Control I/O Port Analog Timer Communication Interrupt POE Debugging 42 43 44 45 46 47 48 49 50 51 52 53 54 55 VSS VCC P75 P74 P73 P72 P71 P70 P33 P32 MTIOC4C/ GTIOC1B-A MTIOC3D/ GTIOC0B-A MTIOC4B/ GTIOC2A-A MTIOC4A/ GTIOC1A-A MTIOC3B/ GTIOC0A-A IRQ5 MTIOC3A/ MTCLKA-A MTIOC3C/ MTCLKB-A SSL3-A SSL2-A POE0# P31 MTIOC0A-B/ MTCLKC-A SSL1-A P30 P24 P23 MTIOC0B-B/ MTCLKD-A SSL0-A RSPCK-A CTX-B/ LTX/ MOSI-A 56 P22 ADTRG# CRX-B/ LRX/ MISO-A MTCLKA-B MTCLKB-B IRQ6 IRQ7 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 AVCC0 VREFH0 VREFL0 AVCC AVSS P21 P20 ADTRG1#-B ADTRG0#-B P63 P62 P61 P60 P47 P46 P45 P44 P43 P42 P41 P40 AN3 AN2 AN1 AN0 AN103/ CVREFH AN102 AN101 AN100 AN003/ CVREFL AN002 AN001 AN000 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 22 of 92 RX62T Group Table 1.6 Pin No. (80-Pin LQFP) 1. Overview List of Pins and Pin Functions (80-Pin LQFP) (3 / 3) Power Supply Clock System Control I/O Port Analog Timer Communication Interrupt POE Debugging 76 77 78 79 80 AVSS0 P11 P10 PA5 PA4 ADTRG1#-A ADTRG0#-A MTCLKC-B MTCLKD-B MTIOC1A MTIOC1B MISO-B RSPCK-B IRQ1-A IRQ0-A R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 23 of 92 RX62T Group 1. Overview Table 1.7 Pin No. (64-Pin LQFP) List of Pins and Pin Functions (64-Pin LQFP) (1 / 2) Power Supply Clock System Control Communication Debuggi ng I/O Port Analog Timer Interrupt POE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 EMLE MDE VCL MD1 MD0 RES# XTAL VSS EXTAL VCC PE2 PD7 PD6 PD5 PD4 PD3 PB7 PB6 PB5 PLLVCC PB4 PLLVSS PB3 PB2 PB1 PB0 PA3 PA2 P94 P93 P92 P91 P76 P75 P74 P73 P72 P71 P70 MTIOC0A-A MTIOC0B-A MTIOC0C MTIOC0D MTIOC2A MTIOC2B MTIOC7A MTIOC7B MTIOC6D MTIOC7C MTIOC4D/ GTIOC2B-A MTIOC4C/ GTIOC1B-A MTIOC3D/ GTIOC0B-A MTIOC4B/ GTIOC2A-A MTIOC4A/ GTIOC1A-A MTIOC3B/ GTIOC0A-A IRQ5 POE0# SCK0 TXD0/SDA RXD0/SCL MOSI-B SSL0-B SSL1-B GTETRG IRQ3 POE8# GTIOC0A-B GTIOC0B-B GTIOC1A-B GTIOC1B-B GTIOC2A-B RXD1 SCK1 TXD1 SCK2-A CRX-A/ RXD2-A CTX-A/ TXD2-A NMI POE10#-A TRST# TMS TDI TCK TDO R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 24 of 92 RX62T Group Table 1.7 Pin No. (64-Pin LQFP) 1. Overview List of Pins and Pin Functions (64-Pin LQFP) (2 / 2) Power Supply Clock System Control I/O Port Analog Timer Communication Interrupt POE Debuggi ng 40 41 42 43 44 45 46 47 VSS VCC P33 P32 MTIOC3A/ MTCLKA-A MTIOC3C/ MTCLKB-A SSL3-A SSL2-A P31 MTIOC0A-B/ MTCLKC-A SSL1-A P30 P24 P23 MTIOC0B-B/ MTCLKD-A SSL0-A RSPCK-A CTX-B/ LTX/ MOSI-A CRX-B/ LRX/ MISO-A 48 P22 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AVCC0 VREFH0 VREFL0 AVSS0 P47 P46 P45 P44 P43 P42 P41 P40 AN103/ CVREFH AN102 AN101 AN100 AN003/ CVREFL AN002 AN001 AN000 P11 P10 PA5 PA4 ADTRG1#-A ADTRG0#-A MTCLKC-B MTCLKD-B MTIOC1A MTIOC1B MISO-B RSPCK-B IRQ1-A IRQ0-A R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 25 of 92 RX62T Group 1. Overview 1.5 Pin Functions Table 1.8 lists the pin functions. Table 1.8 Classifications Pin Functions (1 / 4) Pin Name I/O Description Power supply VCC VCL VSS PLLVCC PLLVSS Input Input Input Input Input Output Input Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS via a 0.1-F capacitor. The capacitor should be placed close to the pin. Ground pin. Connect it to the system power supply (0 V). Power supply pin for the PLL circuit. Connect it to the system power supply. Ground pin for the PLL circuit. Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. Pins for setting the operating mode. The signal levels on these pins must not be changed during operation. Reset signal input pin. This LSI enters the reset state when this signal goes low. Input pin for the on-chip emulator enable signal. When the onchip emulator is used, this pin should be driven high. When not used, it should be driven low. On-chip emulator pins. When the EMLE pin is driven high, these pins are dedicated for the on-chip emulator. Clock XTAL EXTAL Operating mode control MD0 MD1 MDE RES# EMLE System control Input Input On-chip emulator TRST# TMS TDI TCK TDO TRCLK TRSYNC TRDATA0 to TRDATA3 Input Input Input Input Output Output Output Output Input Input This pin outputs the clock for synchronization with the trace data. Not included in the 80-/64-pin versions. This pin indicates that output from the TRDATA0 to TRDATA3 pins is valid. Not included in the 80-/64-pin versions. These pins output the trace information. Not included in the 80/64-pin versions. Non-maskable interrupt request signal. Interrupt request signals. The IRQ0-C/IRQ1-C/IRQ2-B pin is not included in the 100-pin version. The IRQ0-B/IRQ0-C/IRQ1-C/ IRQ2-B pin is not included in the 80-pin version. The IRQ0-B/ IRQ0-C/IRQ1-B/IRQ1-/IRQ2-A/IRQ2-B/IRQ4/IRQ6/IRQ7 pin is not included in the 64-pin version. Interrupt (ICU) NMI IRQ0-A/IRQ0-B/IRQ0-C IRQ1-A/IRQ1-B/IRQ1-C IRQ2-A/IRQ2-B IRQ3 to IRQ7 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 26 of 92 RX62T Group Table 1.8 Classifications 1. Overview Pin Functions (2 / 4) Pin Name I/O Description Multi-function timer pulse unit 3 (MTU3) MTIOC0A-A/MTIOC0A-B MTIOC0B-A/MTIOC0B-B MTIOC0C, MTIOC0D MTIOC1A, MTIOC1B MTIOC2A, MTIOC2B MTIOC3A, MTIOC3B MTIOC3C, MTIOC3D I/O The MTU0.TGRA to MTU0.TGRD input capture input/output compare output/PWM output pins. The MTU1.TGRA and MTU1.TGRB input capture input/output compare output/PWM output pins. The MTU2.TGRA and MTU2.TGRB input capture input/output compare output/PWM output pins. The MTU3.TGRA and MTU3.TGRD input capture input/output compare output/PWM output pins. Pins MTIOC3B and MTIOC3D can be used for large-current output. The MTU4.TGRA and MTU4.TGRD input capture input/output compare output/PWM output pins. These pins can be used for large-current output. The MTU5.TGRU, MTU5.TGRV, and MTU5.TGRW input capture input/dead time compensation input pins. Not included in the 80-/64-pin versions. The MTU6.TGRA to MTU6.TGRD input capture input/output compare output/PWM output pins. Pins MTIOC6B and MTIOC6D can be used for large-current output. The MTIOC6A/MTIOC6C pin is not included in the 80-pin version. The MTIOC6A/MTIOC6B/MTIOC6C pin is not included in the 64-pin version. I/O I/O I/O MTIOC4A, MTIOC4B MTIOC4C, MTIOC4D MTIC5U, MTIC5V, MTIC5W I/O Input MTIOC6A, MTIOC6B MTIOC6C, MTIOC6D I/O MTIOC7A, MTIOC7B MTIOC7C, MTIOC7D I/O The MTU7.TGRA to MTU7.TGRD input capture input/output compare output/PWM output pins. These pins can be used for large-current output. The MTIOC7D pin is not included in the 80-/64-pin versions. MTCLKA-A/MTCLKA-B MTCLKB-A/MTCLKB-B MTCLKC-A/MTCLKC-B/ MTCLKC-C MTCLKD-A/MTCLKD-B/ MTCLKD-C General PWM timer (GPT) GTIOC0A-A/GTIOC0A-B GTIOC0B-A/GTIOC0B-B Input Input pins for external clock signals. The MTCLKA-B/MTCLKB-B/ MTCLKC-C/MTCLKD-C pin is not included in the 64-pin version. I/O The GPT0.GTCCRA and GPT0.GTCCRB CCRB input capture input/output compare output/PWM output pins. Pins GTIOC0A-A and GTIOC0B-A can be used for largecurrent output. The GPT1.GTCCRA and GPT1.GTCCRB input capture input/ output compare output/PWM output pins. Pins GTIOC1A-A and GTIOC1B-A can be used for largecurrent output. The GPT2.GTCCRA and GPT2.GTCCRB input capture input/ output compare output/PWM output pins. Pins GTIOC2A-A and GTIOC2B-A can be used for largecurrent output. The GTIOC2B-B pin is not included in the 80pin version. The GPT3.GTCCRA and GPT3.GTCCRB input capture input/ output compare output/PWM output pins. Not included in the 80-/64-pin versions. External trigger input pin for the GPT Input pins for request signals to place the MTU3 and GPT large-current pins in the high impedance state. The POE4#/ POE10#-B/POE11# pin is not included in the 64-pin version. Output pin for the counter-overflow signal in watchdog-timer mode. Not included in the 100-/80-/64-pin versions. GTIOC1A-A/GTIOC1A-B GTIOC1B-A/GTIOC1B-B I/O GTIOC2A-A/GTIOC2A-B GTIOC2B-A/GTIOC2B-B I/O GTIOC3A, GTIOC3B I/O GTETRG Port output enable 3 (POE3) Watchdog timer (WDT) POE0#, POE4#, POE8# POE10#-A/POE10#-B POE11# WDTOVF# Input Input Output R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 27 of 92 RX62T Group Table 1.8 Classifications 1. Overview Pin Functions (3 / 4) Pin Name I/O Description Serial communications interface (SCIb) TXD0, TXD1?TXD2-A/TXD2B RXD0, RXD1, RXD2-A/ RXD2-B SCK0, SCK1, SCK2-A/ SCK2-B Output Input I/O I/O I/O Input Output Input Output I/O I/O I/O I/O Output Output pins for data transmission. The TXD2-B pin is not included in the 80-/64-pin versions. Input pins for data reception. The RXD2-B pin is not included in the 80-/64-pin versions. Input/output pins for clock signals. The SCK2-B pin is not included in the 80-/64-pin versions. Input/output pin for I2C bus interface clocks. Bus can be directly driven by the NMOS open drain output. Input/output pin for I2C bus interface data. Bus can be directly driven by the NMOS open drain output. Input pin for the CAN. The CRX-C pin is not included in the 64pin version. Output pin for the CAN. The CTX-C pin is not included in the 64-pin version. Input pin for the LIN. Output pin for the LIN. Clock input/output pin for the RSPI. The RSPCK-C pin is not included in the 80-/64-pin versions. Inputs or outputs data output from the master for the RSPI. The MOSI-C pin is not included in the 80-/64-pin versions. Inputs or outputs data output from the slave for the RSPI. The MISO-C pin is not included in the 80-/64-pin versions. Select the slave for the RSPI. The SSL0-C/SSL1-C/SSL2-C/ SSL3-C pin is not included in the 80-/64-pin versions. I2C bus interface (RIIC) SCL SDA CAN module (CAN) (as an optional function) CRX-A/CRX-B/CRX-C CTX-A/CTX-B/CTX-C LIN module (LIN) LRX LTX Serial peripheral interface (RSPI) RSPCK-A/RSPCK-B/ RSPCK-C MOSI-A/MOSI-B/MOSI-C MISO-A/MISO-B/MISO-C SSL0-A/SSL0-B/SSL0-C SSL1-A/SSL1-B/SSL1-C SSL2-A/SSL2-B/SSL2-C SSL3-A/SSL3-B/SSL3-C A/D converter AN000 to AN003 AN100 to AN103 AN0 to AN11 Input Input Input pins for the analog signals to be processed by the 12-bit A/D converter. Input pins for the analog signals to be processed by the 10-bit A/D converter. The AN4 to AN11 pins are not included in the 80-pin version. Not included in the 64-pin version. Input pins for the external trigger signals that start the A/D conversion. The ADTRG0#-B/ADTRG1#-B/ADTRG# pin is not included in the 64-pin version. Input pin for the high-level reference voltage to the comparator Input pin for the low-level reference voltage to the comparator Analog power supply pin for the 12-bit A/D converter. When the A/D converter is not in use, connect this pin to the system power supply. Ground pin for the 12-bit A/D converter. Connect this pin to the system power supply (0 V). Reference power supply pin for the 12-bit A/D converter. When the 12-bit A/D converter is not in use, connect this pin to the system power supply. Ground pin of the reference power supply pin for the 12-bit A/D converter. When the 12-bit A/D converter is not in use, connect this pin to the system power supply (0 V). Analog power supply pin for the 10-bit A/D converter. When the A/D converter is not in use, connect this pin to the system power supply. Not included in the 64-pin version. Ground pin for the 10-bit A/D converter. Connect this pin to the system power supply (0 V). Not included in the 64-pin version. Reference power supply pin for the 10-bit A/D converter. When the 10-bit A/D converter is not in use, connect this pin to the system power supply. Not included in the 80-/64-pin versions. ADTRG0#-A/ADTRG0#-B ADTRG1#-A/ADTRG1#-B ADTRG# CVREFH CVREFL Analog power supply AVCC0 Input Input Input Input AVSS0 VREFH0 Input Input VREFL0 Input AVCC Input AVSS VREF Input Input R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 28 of 92 RX62T Group Table 1.8 Classifications 1. Overview Pin Functions (4 / 4) Pin Name I/O Description I/O ports P10, P11 P20 to P24 P30 to P33 P40 to P47 P50 to P55 P60 to P65 P70 to P76 P80 to P82 P90 to P96 I/O I/O I/O Input Input Input I/O I/O I/O 2-bit input/output pins. 5-bit input/output pins. The P20/P21 pin is not included in the 64-pin version. 4-bit input/output pins. 8-bit input pins. 6-bit input pins. Not included in the 80-/64-pin versions. 6-bit input pins. The P64/P6 pin is not included in the 80-pin version. Not included in the 64-pin version. 7-bit input/output pins. 3-bit input/output pins. Not included in the 80-/64-pin versions. 7-bit input/output pins. The P90 pin is not included in the 80-pin version. The P90/P95/P96 pin is not included in the 64-pin version. 6-bit input/output pins. The PA0/PA1 pin is not included in the 80-/64-pin versions. 8-bit input/output pins. 8-bit input/output pins. The PD0/PD1/PD2 pin is not included in the 80-/64-pin versions. 5-bit input/output pins. The PE1/PE5 pin is not included in the 80-pin version. Not included in the 64-pin version. 1-bit input pin. 6-bit input/output pins. Not included in the 100-/80-/64-pin versions. PA0 to PA5 PB0 to PB7 PD0 to PD7 PE0, PE1, PE3 to PE5 PE2 PG0 to PG5 I/O I/O I/O I/O Input I/O Note: • Which pins are and are not incorporated depends on the package. For details, see the list of pins and pin functions in Table 1.4 to Table 1.7. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 29 of 92 RX62T Group 2. CPU 2. CPU The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP instructions. General-purpose register b31 b0 R0 (SP) * R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Control register b31 b0 ISP USP INTB PC PSW BPC BPSW FINTV FPSW DSP instruction register b63 (Interrupt stack pointer) (User stack pointer) (Interrupt table register) (Program counter) (Processor status word) (Backup PC) (Backup PSW) (Fast interrupt vector register) (Floating-point status word) b0 ACC (Accumulator) Note: * The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to the value of the U bit in the PSW register. Figure 2.1 Register Set of the CPU R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 30 of 92 RX62T Group 2. CPU 2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.2 (1) Control Registers Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW). Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) Interrupt Table Register (INTB) The interrupt table register (INTB) specifies the address where the relocatable vector table starts. Set INTB to a multiple of four. (3) Program Counter (PC) The program counter (PC) indicates the address of the instruction being executed. (4) Processor Status Word (PSW) The processor status word (PSW) indicates results of instruction execution or the state of the CPU. (5) Backup PC (BPC) The backup PC (BPC) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC. (6) Backup PSW (BPSW) The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW. (7) Fast Interrupt Vector Register (FINTV) The fast interrupt vector register (FINTV) is provided to speed up response to interrupts. The FINTV register specifies a branch destination address when a fast interrupt has been generated. (8) Floating-Point Status Word (FPSW) The floating-point status word (FPSW) indicates the results of floating-point operations. When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V). R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 31 of 92 RX62T Group 2. CPU (9) Accumulator (ACC) The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in the accumulator is modified by execution of the instruction. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 32 of 92 RX62T Group 3. Address Space 3. 3.1 Address Space Address Space This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 3.1 shows the memory maps. Single-chip mode*1 R5F562TAxxxx 0000 0000h 0000 4000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*2 007F C000h 007F C500h Peripheral I/O registers Reserved 007F FC00h 0080 0000h Reserved 00FC 0000h 0100 0000h area*2 00FE 0000h 0100 0000h area*2 007F FC00h 0080 0000h Reserved area*2 00FF 0000h 0100 0000h 007F C000h 007F C500h On-chip ROM (data flash) Reserved area*2 FCU-RAM*3 0010 0000h 0010 2000h 007F 8000h 007F A000h Reserved area*2 Peripheral I/O registers Reserved area*2 007F FC00h 0080 0000h Reserved area*2 On-chip ROM (program ROM) (write only) 007F C000h 007F C500h On-chip RAM Reserved area*2 0000 0000h 0000 2000h 0008 0000h Peripheral I/O registers On-chip ROM (data flash) Reserved area*2 FCU-RAM*3 0010 0000h 0010 2000h 007F 8000h 007F A000h Reserved area*2 Peripheral I/O registers Reserved area*2 Peripheral I/O registers Single-chip mode*1 R5F562T7xxxx On-chip RAM Reserved area*2 0000 0000h 0000 2000h 0008 0000h Single-chip mode*1 R5F562T6xxxx On-chip RAM Reserved area*2 Peripheral I/O registers On-chip ROM (data flash) Reserved area*2 FCU-RAM*3 Peripheral I/O registers Peripheral I/O registers On-chip ROM (program ROM) (write only) On-chip ROM (program ROM) (write only) Reserved area*2 Reserved area*2 Reserved area*2 FEFF E000h FF00 0000h On-chip ROM (FCU firmware)*3 (read only) FEFF E000h FF00 0000h On-chip ROM (FCU firmware)*3 (read only) FEFF E000h FF00 0000h On-chip ROM (FCU firmware)*3 (read only) Reserved area*2 Reserved area*2 Reserved area*2 FFFC 0000h FFFF FFFFh On-chip ROM (program ROM) (read only) FFFE 0000h FFFF FFFFh On-chip ROM (program ROM) (read only) FFFF 0000h FFFF FFFFh On-chip ROM (program ROM) (read only) Notes: 1. The layout of the address space in boot mode is the same as in single-chip mode. 2. Reserved areas should not be accessed, since the correct operation of LSI is not guaranteed if they are accessed. 3. For details on the FCU, see section 30, ROM (Flash Memory for Code Storage) and section 31, Data Flash (Flash Memory for Data Storage) in the User’s manual: Hardware. Figure 3.1 Memory Map (RX62T Group) R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 33 of 92 RX62T Group 4. I/O Registers 4. Table 4.1 I/O Registers List of I/O Registers (Address Order) (1 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size Number of Access Cycles Address Register Name 0008 0000h 0008 0002h 0008 0006h 0008 0008h 0008 000Ch 0008 0010h 0008 0014h 0008 0018h 0008 0020h 0008 0040h 0008 1300h 0008 1304h 0008 1308h 0008 130Ah 0008 2400h 0008 2404h 0008 2408h 0008 240Ch 0008 240Eh 0008 7010h 0008 7015h 0008 7017h 0008 701Bh 0008 701Ch 0008 701Dh 0008 701Eh 0008 701Fh 0008 702Ch 0008 702Dh 0008 702Eh 0008 702Fh 0008 7038h 0008 7039h 0008 703Ah 0008 703Bh 0008 703Ch 0008 7040h 0008 7041h 0008 7042h 0008 7043h 0008 7044h 0008 7045h SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM BSC BSC BSC BSC DTC DTC DTC DTC DTC ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Mode monitor register Mode status register System control register 0 System control register 1 Standby control register Module stop control register A Module stop control register B Module stop control register C System clock control register Oscillation stop detection control register Bus error status clear register Bus error monitoring enable register Bus error status register 1 Bus error status register 2 DTC control register DTC vector base register DTC address mode register DTC module start register DTC status register Interrupt request register 016 Interrupt request register 021 Interrupt request register 023 Interrupt request register 027 Interrupt request register 028 Interrupt request register 029 Interrupt request register 030 Interrupt request register 031 Interrupt request register 044 Interrupt request register 045 Interrupt request register 046 Interrupt request register 047 Interrupt request register 056 Interrupt request register 057 Interrupt request register 058 Interrupt request register 059 Interrupt request register 060 Interrupt request register 064 Interrupt request register 065 Interrupt request register 066 Interrupt request register 067 Interrupt request register 068 Interrupt request register 069 MDMONR MDSR SYSCR0 SYSCR1 SBYCR MSTPCRA MSTPCRB MSTPCRC SCKCR OSTDCR BERCLR BEREN BERSR1 BERSR2 DTCCR DTCVBR DTCADMOD DTCST DTCSTS IR016 IR021 IR023 IR027 IR028 IR029 IR030 IR031 IR044 IR045 IR046 IR047 IR056 IR057 IR058 IR059 IR060 IR064 IR065 IR066 IR067 IR068 IR069 16 16 16 16 16 32 32 32 32 16 8 8 8 16 8 32 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 32 32 32 32 16 8 8 8 16 8 32 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3ICLK 3ICLK 3ICLK 3ICLK 3ICLK 3ICLK 3ICLK 3ICLK 3ICLK 3ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 34 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (2 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 7046h 0008 7047h 0008 7060h 0008 7062h 0008 7066h 0008 7067h 0008 706Ah 0008 7072h 0008 7073h 0008 7074h 0008 7075h 0008 7076h 0008 7077h 0008 7078h 0008 7079h 0008 707Ah 0008 707Bh 0008 707Ch 0008 707Dh 0008 707Eh 0008 707Fh 0008 7080h 0008 7081h 0008 7082h 0008 7083h 0008 7084h 0008 7085h 0008 7086h 0008 7087h 0008 7088h 0008 7089h 0008 708Ah 0008 708Bh 0008 708Ch 0008 708Dh 0008 708Eh 0008 708Fh 0008 7090h 0008 7091h 0008 7092h 0008 7095h 0008 7096h 0008 7097h 0008 7098h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 070 Interrupt request register 071 Interrupt request register 096 Interrupt request register 098 Interrupt request register 102 Interrupt request register 103 Interrupt request register 106 Interrupt request register 114 Interrupt request register 115 Interrupt request register 116 Interrupt request register 117 Interrupt request register 118 Interrupt request register 119 Interrupt request register 120 Interrupt request register 121 Interrupt request register 122 Interrupt request register 123 Interrupt request register 124 Interrupt request register 125 Interrupt request register 126 Interrupt request register 127 Interrupt request register 128 Interrupt request register 129 Interrupt request register 130 Interrupt request register 131 Interrupt request register 132 Interrupt request register 133 Interrupt request register 134 Interrupt request register 135 Interrupt request register 136 Interrupt request register 137 Interrupt request register 138 Interrupt request register 139 Interrupt request register 140 Interrupt request register 141 Interrupt request register 142 Interrupt request register 143 Interrupt request register 144 Interrupt request register 145 Interrupt request register 146 Interrupt request register 149 Interrupt request register 150 Interrupt request register 151 Interrupt request register 152 IR070 IR071 IR096 IR098 IR102 IR103 IR106 IR114 IR115 IR116 IR117 IR118 IR119 IR120 IR121 IR122 IR123 IR124 IR125 IR126 IR127 IR128 IR129 IR130 IR131 IR132 IR133 IR134 IR135 IR136 IR137 IR138 IR139 IR140 IR141 IR142 IR143 IR144 IR145 IR146 IR149 IR150 IR151 IR152 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 35 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (3 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 7099h 0008 70AAh 0008 70ABh 0008 70ACh 0008 70ADh 0008 70AEh 0008 70AFh 0008 70B0h 0008 70B1h 0008 70B2h 0008 70B3h 0008 70B4h 0008 70B5h 0008 70B6h 0008 70B7h 0008 70B8h 0008 70BAh 0008 70BBh 0008 70BCh 0008 70BDh 0008 70BEh 0008 70C0h 0008 70C1h 0008 70C2h 0008 70C3h 0008 70C4h 0008 70D6h 0008 70D7h 0008 70D8h 0008 70D9h 0008 70DAh 0008 70DBh 0008 70DCh 0008 70DDh 0008 70DEh 0008 70DFh 0008 70E0h 0008 70E1h 0008 70F6h 0008 70F7h 0008 70F8h 0008 70F9h 0008 70FEh 0008 711Bh ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 153 Interrupt request register 170 Interrupt request register 171 Interrupt request register 172 Interrupt request register 173 Interrupt request register 174 Interrupt request register 175 Interrupt request register 176 Interrupt request register 177 Interrupt request register 178 Interrupt request register 179 Interrupt request register 180 Interrupt request register 181 Interrupt request register 182 Interrupt request register 183 Interrupt request register 184 Interrupt request register 186 Interrupt request register 187 Interrupt request register 188 Interrupt request register 189 Interrupt request register 190 Interrupt request register 192 Interrupt request register 193 Interrupt request register 194 Interrupt request register 195 Interrupt request register 196 Interrupt request register 214 Interrupt request register 215 Interrupt request register 216 Interrupt request register 217 Interrupt request register 218 Interrupt request register 219 Interrupt request register 220 Interrupt request register 221 Interrupt request register 222 Interrupt request register 223 Interrupt request register 224 Interrupt request register 225 Interrupt request register 246 Interrupt request register 247 Interrupt request register 248 Interrupt request register 249 Interrupt request register 254 DTC activation enable register 027 IR153 IR170 IR171 IR172 IR173 IR174 IR175 IR176 IR177 IR178 IR179 IR180 IR181 IR182 IR183 IR184 IR186 IR187 IR188 IR189 IR190 IR192 IR193 IR194 IR195 IR196 IR214 IR215 IR216 IR217 IR218 IR219 IR220 IR221 IR222 IR223 IR224 IR225 IR246 IR247 IR248 IR249 IR254 DTCER027 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 36 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (4 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 711Ch 0008 711Dh 0008 711Eh 0008 711Fh 0008 712Dh 0008 712Eh 0008 7140h 0008 7141h 0008 7142h 0008 7143h 0008 7144h 0008 7145h 0008 7146h 0008 7147h 0008 7162h 0008 7166h 0008 7167h 0008 716Ah 0008 7172h 0008 7173h 0008 7174h 0008 7175h 0008 7179h 0008 717Ah 0008 717Dh 0008 717Eh 0008 7181h 0008 7182h 0008 7183h 0008 7184h 0008 7186h 0008 7187h 0008 7188h 0008 7189h 0008 718Ah 0008 718Bh 0008 718Ch 0008 718Dh 0008 718Eh 0008 718Fh 0008 7190h 0008 7191h 0008 7195h 0008 7196h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU DTC activation enable register 028 DTC activation enable register 029 DTC activation enable register 030 DTC activation enable register 031 DTC activation enable register 045 DTC activation enable register 046 DTC activation enable register 064 DTC activation enable register 065 DTC activation enable register 066 DTC activation enable register 067 DTC activation enable register 068 DTC activation enable register 069 DTC activation enable register 070 DTC activation enable register 071 DTC activation enable register 098 DTC activation enable register 102 DTC activation enable register 103 DTC activation enable register 106 DTC activation enable register 114 DTC activation enable register 115 DTC activation enable register 116 DTC activation enable register 117 DTC activation enable register 121 DTC activation enable register 122 DTC activation enable register 125 DTC activation enable register 126 DTC activation enable register 129 DTC activation enable register 130 DTC activation enable register 131 DTC activation enable register 132 DTC activation enable register 134 DTC activation enable register 135 DTC activation enable register 136 DTC activation enable register 137 DTC activation enable register 138 DTC activation enable register 139 DTC activation enable register 140 DTC activation enable register 141 DTC activation enable register 142 DTC activation enable register 143 DTC activation enable register 144 DTC activation enable register 145 DTC activation enable register 149 DTC activation enable register 150 DTCER028 DTCER029 DTCER030 DTCER031 DTCER045 DTCER046 DTCER064 DTCER065 DTCER066 DTCER067 DTCER068 DTCER069 DTCER070 DTCER071 DTCER098 DTCER102 DTCER103 DTCER106 DTCER114 DTCER115 DTCER116 DTCER117 DTCER121 DTCER122 DTCER125 DTCER126 DTCER129 DTCER130 DTCER131 DTCER132 DTCER134 DTCER135 DTCER136 DTCER137 DTCER138 DTCER139 DTCER140 DTCER141 DTCER142 DTCER143 DTCER144 DTCER145 DTCER149 DTCER150 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 37 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (5 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 7197h 0008 7198h 0008 7199h 0008 71AEh 0008 71AFh 0008 71B0h 0008 71B1h 0008 71B2h 0008 71B3h 0008 71B4h 0008 71B5h 0008 71B6h 0008 71B7h 0008 71B8h 0008 71BAh 0008 71BBh 0008 71BCh 0008 71BDh 0008 71BEh 0008 71C0h 0008 71C1h 0008 71C2h 0008 71C3h 0008 71C4h 0008 71D7h 0008 71D8h 0008 71DBh 0008 71DCh 0008 71DFh 0008 71E0h 0008 71F7h 0008 71F8h 0008 71FEh 0008 7202h 0008 7203h 0008 7205h 0008 7207h 0008 7208h 0008 720Ch 0008 720Dh 0008 720Eh 0008 720Fh 0008 7210h 0008 7211h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU DTC activation enable register 151 DTC activation enable register 152 DTC activation enable register 153 DTC activation enable register 174 DTC activation enable register 175 DTC activation enable register 176 DTC activation enable register 177 DTC activation enable register 178 DTC activation enable register 179 DTC activation enable register 180 DTC activation enable register 181 DTC activation enable register 182 DTC activation enable register 183 DTC activation enable register 184 DTC activation enable register 186 DTC activation enable register 187 DTC activation enable register 188 DTC activation enable register 189 DTC activation enable register 190 DTC activation enable register 192 DTC activation enable register 193 DTC activation enable register 194 DTC activation enable register 195 DTC activation enable register 196 DTC activation enable register 215 DTC activation enable register 216 DTC activation enable register 219 DTC activation enable register 220 DTC activation enable register 223 DTC activation enable register 224 DTC activation enable register 247 DTC activation enable register 248 DTC activation enable register 254 Interrupt request enable register 02 Interrupt request enable register 03 Interrupt request enable register 05 Interrupt request enable register 07 Interrupt request enable register 08 Interrupt request enable register 0C Interrupt request enable register 0D Interrupt request enable register 0E Interrupt request enable register 0F Interrupt request enable register 10 Interrupt request enable register 11 DTCER151 DTCER152 DTCER153 DTCER174 DTCER175 DTCER176 DTCER177 DTCER178 DTCER179 DTCER180 DTCER181 DTCER182 DTCER183 DTCER184 DTCER186 DTCER187 DTCER188 DTCER189 DTCER190 DTCER192 DTCER193 DTCER194 DTCER195 DTCER196 DTCER215 DTCER216 DTCER219 DTCER220 DTCER223 DTCER224 DTCER247 DTCER248 DTCER254 IER02 IER03 IER05 IER07 IER08 IER0C IER0D IER0E IER0F IER10 IER11 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 38 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (6 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 7212h 0008 7213h 0008 7215h 0008 7216h 0008 7217h 0008 7218h 0008 721Ah 0008 721Bh 0008 721Ch 0008 721Eh 0008 721Fh 0008 72E0h 0008 72F0h 0008 7300h 0008 7301h 0008 7302h 0008 7303h 0008 7304h 0008 7305h 0008 7306h 0008 7307h 0008 7314h 0008 7318h 0008 7320h 0008 7321h 0008 7322h 0008 7323h 0008 7324h 0008 7325h 0008 7326h 0008 7327h 0008 7340h 0008 7344h 0008 7348h 0008 7349h 0008 7351h 0008 7352h 0008 7353h 0008 7354h 0008 7355h 0008 7356h 0008 7357h 0008 7358h 0008 7359h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request enable register 12 Interrupt request enable register 13 Interrupt request enable register 15 Interrupt request enable register 16 Interrupt request enable register 17 Interrupt request enable register 18 Interrupt request enable register 1A Interrupt request enable register 1B Interrupt request enable register 1C Interrupt request enable register 1E Interrupt request enable register 1F Software interrupt activation register Fast interrupt set register Interrupt source priority register 00 Interrupt source priority register 01 Interrupt source priority register 02 Interrupt source priority register 03 Interrupt source priority register 04 Interrupt source priority register 05 Interrupt source priority register 06 Interrupt source priority register 07 Interrupt source priority register 14 Interrupt source priority register 18 Interrupt source priority register 20 Interrupt source priority register 21 Interrupt source priority register 22 Interrupt source priority register 23 Interrupt source priority register 24 Interrupt source priority register 25 Interrupt source priority register 26 Interrupt source priority register 27 Interrupt source priority register 40 Interrupt source priority register 44 Interrupt source priority register 48 Interrupt source priority register 49 Interrupt source priority register 51 Interrupt source priority register 52 Interrupt source priority register 53 Interrupt source priority register 54 Interrupt source priority register 55 Interrupt source priority register 56 Interrupt source priority register 57 Interrupt source priority register 58 Interrupt source priority register 59 IER12 IER13 IER15 IER16 IER17 IER18 IER1A IER1B IER1C IER1E IER1F SWINTR FIR IPR00 IPR01 IPR02 IPR03 IPR04 IPR05 IPR06 IPR07 IPR14 IPR18 IPR20 IPR21 IPR22 IPR23 IPR24 IPR25 IPR26 IPR27 IPR40 IPR44 IPR48 IPR49 IPR51 IPR52 IPR53 IPR54 IPR55 IPR56 IPR57 IPR58 IPR59 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 39 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (7 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 735Ah 0008 735Bh 0008 735Ch 0008 735Dh 0008 735Eh 0008 735Fh 0008 7360h 0008 7367h 0008 7368h 0008 7369h 0008 736Ah 0008 736Bh 0008 736Ch 0008 736Dh 0008 736Eh 0008 736Fh 0008 7380h 0008 7381h 0008 7382h 0008 7388h 0008 7389h 0008 738Ah 0008 738Bh 0008 7390h 0008 7500h 0008 7501h 0008 7502h 0008 7503h 0008 7504h 0008 7505h 0008 7506h 0008 7507h 0008 7580h 0008 7581h 0008 7582h 0008 7583h 0008 8000h 0008 8002h 0008 8004h 0008 8006h 0008 8008h 0008 800Ah 0008 800Ch 0008 8010h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU CMT CMT0 CMT0 CMT0 CMT1 CMT1 CMT1 CMT Interrupt source priority register 5A Interrupt source priority register 5B Interrupt source priority register 5C Interrupt source priority register 5D Interrupt source priority register 5E Interrupt source priority register 5F Interrupt source priority register 60 Interrupt source priority register 67 Interrupt source priority register 68 Interrupt source priority register 69 Interrupt source priority register 6A Interrupt source priority register 6B Interrupt source priority register 6C Interrupt source priority register 6D Interrupt source priority register 6E Interrupt source priority register 6F Interrupt source priority register 80 Interrupt source priority register 81 Interrupt source priority register 82 Interrupt source priority register 88 Interrupt source priority register 89 Interrupt source priority register 8A Interrupt source priority register 8B Interrupt source priority register 90 IRQ control register 0 IRQ control register 1 IRQ control register 2 IRQ control register 3 IRQ control register 4 IRQ control register 5 IRQ control register 6 IRQ control register 7 Non-maskable interrupt status register Non-maskable interrupt enable register Non-maskable interrupt clear register NMI pin interrupt control register Compare match timer start register 0 Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer start register 1 IPR5A IPR5B IPR5C IPR5D IPR5E IPR5F IPR60 IPR67 IPR68 IPR69 IPR6A IPR6B IPR6C IPR6D IPR6E IPR6F IPR80 IPR81 IPR82 IPR88 IPR89 IPR8A IPR8B IPR90 IRQCR0 IRQCR1 IRQCR2 IRQCR3 IRQCR4 IRQCR5 IRQCR6 IRQCR7 NMISR NMIER NMICLR NMICR CMSTR0 CMCR CMCNT CMCOR CMCR CMCNT CMCOR CMSTR1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2ICLK 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 40 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (8 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 8012h 0008 8014h 0008 8016h 0008 8018h 0008 801Ah 0008 801Ch 0008 8028h 0008 8028h 0008 8029h 0008 802Ah 0008 802Bh 0008 8030h 0008 8032h 0008 8034h 0008 8040h 0008 8042h 0008 8044h 0008 8046h 0008 8048h 0008 804Ah 0008 804Ch 0008 804Eh 0008 8050h 0008 8051h 0008 805Bh 0008 805Dh 0008 8060h 0008 8062h 0008 8064h 0008 8066h 0008 8070h 0008 8072h 0008 8240h 0008 8241h 0008 8242h 0008 8243h 0008 8244h 0008 8245h 0008 8246h 0008 8247h 0008 8240h 0008 8241h 0008 8242h 0008 8243h CMT2 CMT2 CMT2 CMT3 CMT3 CMT3 WDT WDT WDT WDT WDT IWDT IWDT IWDT ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA ADA SCI0 SCI0 SCI0 SCI0 SCI0 SCI0 SCI0 SCI0 SMCI0 SMCI0 SMCI0 SMCI0 Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer control register Compare match timer counter Compare match timer constant register Timer control/status register Write window A register Timer counter Write window B register Reset control/status register IWDT refresh register IWDT control register IWDT status register A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H A/D control/status register A/D control register A/D sampling state register A/D self-diagnostic register A/D data register I A/D data register J A/D data register K A/D data register L A/D start trigger select register A/D data placement register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register CMCR CMCNT CMCOR CMCR CMCNT CMCOR TCSR WINA TCNT WINB RSTCSR IWDTRR IWDTCR IWDTSR ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR ADSSTR ADDIAGR ADDRI ADDRJ ADDRK ADDRL ADSTRGR ADDPR SMR*1 BRR SCR*1 TDR SSR*1 RDR SCMR SEMR SMR BRR SCR TDR 16 16 16 16 16 16 8 16 8 16 8 8 16 16 16 16 16 16 16 16 16 16 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 8 16 8 16 8 8 16 16 16 16 16 16 16 16 16 16 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 41 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (9 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 8244h 0008 8245h 0008 8246h 0008 8248h 0008 8249h 0008 824Ah 0008 824Bh 0008 824Ch 0008 824Dh 0008 824Eh 0008 824Fh 0008 8248h 0008 8249h 0008 824Ah 0008 824Bh 0008 824Ch 0008 824Dh 0008 824Eh 0008 8250h 0008 8251h 0008 8252h 0008 8253h 0008 8254h 0008 8255h 0008 8256h 0008 8257h 0008 8250h 0008 8251h 0008 8252h 0008 8253h 0008 8254h 0008 8255h 0008 8256h 0008 8280h 0008 8281h 0008 8282h 0008 8300h 0008 8301h 0008 8302h 0008 8303h 0008 8304h 0008 8305h 0008 8306h 0008 8307h SMCI0 SMCI0 SMCI0 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SMCI1 SMCI1 SMCI1 SMCI1 SMCI1 SMCI1 SMCI1 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SMCI2 SMCI2 SMCI2 SMCI2 SMCI2 SMCI2 SMCI2 CRC CRC CRC RIIC RIIC RIIC RIIC RIIC RIIC RIIC RIIC Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register CRC control register CRC data input register CRC data output register I2C bus control register 1 I2C bus control register 2 I 2C bus mode register 1 SSR RDR SCMR SMR*1 BRR SCR*1 TDR SSR*1 RDR SCMR SEMR SMR BRR SCR TDR SSR RDR SCMR SMR*1 BRR SCR*1 TDR SSR*1 RDR SCMR SEMR SMR*1 BRR SCR*1 TDR SSR*1 RDR SCMR CRCCR CRCDIR CRCDOR ICCR1 ICCR2 ICMR1 ICMR2 ICMR3 ICFER ICSER ICIER 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 I2C bus mode register 2 I2C bus mode register 3 I 2C bus function enable register I2C bus status enable register I 2C bus interrupt enable register R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 42 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (10 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 8308h 0008 8309h 0008 830Ah 0008 830Bh 0008 830Ch 0008 830Dh 0008 830Eh 0008 830Fh 0008 8310h 0008 8311h 0008 8312h 0008 8313h 0008 8380h 0008 8381h 0008 8382h 0008 8383h 0008 8384h 0008 8388h 0008 8389h 0008 838Ah 0008 838Bh 0008 838Ch 0008 838Dh 0008 838Eh 0008 838Fh 0008 8390h 0008 8392h 0008 8394h 0008 8396h 0008 8398h 0008 839Ah 0008 839Ch 0008 839Eh 0008 9000h 0008 9004h 0008 900Ah 0008 900Eh 0008 9010h 0008 9012h 0008 9014h 0008 9016h 0008 9018h 0008 901Ah 0008 901Ch RIIC RIIC RIIC RIIC RIIC RIIC RIIC RIIC RIIC RIIC RIIC RIIC RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI RSPI S12AD0 S12AD0 S12AD0 S12AD0 S12AD0 S12AD S12AD S12AD S12AD S12AD S12AD I2C bus status register 1 I2C bus status register 2 Slave address register L0 Slave address register U0 Slave address register L1 Slave address register U1 Slave address register L2 Slave address register U2 I2C bus bit rate low-level register I 2C bus bit rate high-level register ICSR1 ICSR2 SARL0 SARU0 SARL1 SARU1 SARL2 SARU2 ICBRL ICBRH ICDRT ICDRR SPCR SSLP SPPCR SPSR SPDR SPSCR SPSSR SPBR SPDCR SPCKD SSLND SPND SPCR2 SPCMD0 SPCMD1 SPCMD2 SPCMD3 SPCMD4 SPCMD5 SPCMD6 SPCMD7 ADCSR ADANS ADPG ADCER ADSTRGR ADCMPMD0 ADCMPMD1 ADCMPNR0 ADCMPNR1 ADCMPFR ADCMPSEL 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16, 32 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 16 16 16 16 16 16 16 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16, 32 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 16 16 16 16 16 16 16 16 8 16 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 I2C bus transmit data register I2C bus receive data register RSPI control register RSPI slave select polarity register RSPI pin control register RSPI status register RSPI data register RSPI sequence control register RSPI sequence status register RSPI bit rate register RSPI data control register RSPI clock delay register RSPI slave select negation delay register RSPI next-access delay register RSPI control register 2 RSPI command register 0 RSPI command register 1 RSPI command register 2 RSPI command register 3 RSPI command register 4 RSPI command register 5 RSPI command register 6 RSPI command register 7 A/D control register A/D channel select register A/D programmable gain amplifier register A/D control extended register A/D start trigger select register Comparator operating mode select register 0 Comparator operating mode select register 1 Comparator filter mode register 0 Comparator filter mode register 1 Comparator detection flag register Comparator interrupt select register R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 43 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (11 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 901Eh 0008 9020h 0008 9022h 0008 9024h 0008 9026h 0008 9030h 0008 9060h 0008 9080h 0008 9084h 0008 908Ah 0008 908Eh 0008 9090h 0008 909Eh 0008 90A0h 0008 90A2h 0008 90A4h 0008 90A6h 0008 90B0h 0008 90E0h 0008 C001h 0008 C002h 0008 C003h 0008 C007h 0008 C008h 0008 C009h 0008 C00Ah 0008 C00Bh 0008 C00Dh 0008 C00Eh 0008 C010h 0008 C021h 0008 C022h 0008 C023h 0008 C027h 0008 C028h 0008 C029h 0008 C02Ah 0008 C02Bh 0008 C02Dh 0008 C02Eh 0008 C030h 0008 C041h 0008 C042h 0008 C043h S12AD0 S12AD0 S12AD0 S12AD0 S12AD0 S12AD0 S12AD0 S12AD1 S12AD1 S12AD1 S12AD1 S12AD1 S12AD1 S12AD1 S12AD1 S12AD1 S12AD1 S12AD1 S12AD1 PORT1 PORT2 PORT3 PORT7 PORT8 PORT9 PORTA PORTB PORTD PORTE PORTG PORT1 PORT2 PORT3 PORT7 PORT8 PORT9 PORTA PORTB PORTD PORTE PORTG PORT1 PORT2 PORT3 A/D data register Diag A/D data register 0A A/D data register 1 A/D data register 2 A/D data register 3 A/D data register 0B A/D sampling state register A/D control register A/D channel select register A/D programmable gain amplifier register A/D control extended register A/D start trigger select register A/D data register Diag A/D data register 0A A/D data register 1 A/D data register 2 A/D data register 3 A/D data register 0B A/D sampling state register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register ADRD ADDR0A ADDR1 ADDR2 ADDR3 ADDR0B ADSSTR ADCSR ADANS ADPG ADCER ADSTRGR ADRD ADDR0A ADDR1 ADDR2 ADDR3 ADDR0B ADSSTR DDR DDR DDR DDR DDR*2*3 DDR DDR DDR DDR DDR DDR*1*2*3 DR DR DR DR DR*2*3 DR DR DR DR DR DR*1*2*3 PORT PORT PORT 16 16 16 16 16 16 8 8 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 8 8 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 44 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (12 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 C044h 0008 C045h 0008 C046h 0008 C047h 0008 C048h 0008 C049h 0008 C04Ah 0008 C04Bh 0008 C04Dh 0008 C04Eh 0008 C050h 0008 C061h 0008 C062h 0008 C063h 0008 C064h 0008 C065h 0008 C066h 0008 C067h 0008 C068h 0008 C069h 0008 C06Ah 0008 C06Bh 0008 C06Dh 0008 C06Eh 0008 C070h 0008 C108h 0008 C109h 0008 C10Ah 0008 C10Ch 0008 C10Dh 0008 C10Fh 0008 C110h 0008 C111h 0008 C113h 0008 C114h 0008 C116h 0008 C117h 0008 C280h 0008 C281h 0008 C282h 0008 C283h 0008 C284h 0008 C285h 0008 C289h PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 PORTA PORTB PORTD PORTE PORTG PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 PORTA PORTB PORTD PORTE PORTG IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM FLASH Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Port register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Port function register 8 Port function register 9 Port function register A Port function register C Port function register D Port function register F Port function register G Port function register H Port function register J Port function register K Port function register M Port function register N Deep standby control register Deep standby wait control register Deep standby interrupt enable register Deep standby interrupt flag register Deep standby interrupt edge register Reset status register Flash write erase protection register PORT PORT*2*3 PORT*3 PORT PORT*2*3 PORT PORT PORT PORT PORT PORT*1*2*3 ICR ICR ICR ICR ICR*2*3 ICR*3 ICR ICR*2*3 ICR ICR ICR ICR ICR ICR*1*2*3 PF8IRQ PF9IRQ PFAADC PFCMTU PFDGPT PFFSCI PFGSPI PFHSPI PFJCAN PFKLIN PFMPOE PFNPOE DPSBYCR DPSWCR DPSIER DPSIFR DPSIEGR RSTSR FWEPROR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 45 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (13 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 C28Ch 0008 C28Dh 0008 C290h 0008 C291h 0008 C292h 0008 C293h 0008 C294h 0008 C295h 0008 C296h 0008 C297h 0008 C298h 0008 C299h 0008 C29Ah 0008 C29Bh 0008 C29Ch 0008 C29Dh 0008 C29Eh 0008 C29Fh 0008 C2A0h 0008 C2A1h 0008 C2A2h 0008 C2A3h 0008 C2A4h 0008 C2A5h 0008 C2A6h 0008 C2A7h 0008 C2A8h 0008 C2A9h 0008 C2AAh 0008 C2ABh 0008 C2ACh 0008 C2ADh 0008 C2AEh 0008 C2AFh 0008 C4C0h 0008 C4C2h 0008 C4C4h 0008 C4C6h 0008 C4C8h 0008 C4CAh 0008 C4CBh 0008 C4CCh 0008 C4CEh SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM POE POE POE POE POE POE POE POE POE Key code register for low-voltage detection control register Voltage detection control register Deep standby backup register 0 Deep standby backup register 1 Deep standby backup register 2 Deep standby backup register 3 Deep standby backup register 4 Deep standby backup register 5 Deep standby backup register 6 Deep standby backup register 7 Deep standby backup register 8 Deep standby backup register 9 Deep standby backup register 10 Deep standby backup register 11 Deep standby backup register 12 Deep standby backup register 13 Deep standby backup register 14 Deep standby backup register 15 Deep standby backup register 16 Deep standby backup register 17 Deep standby backup register 18 Deep standby backup register 19 Deep standby backup register 20 Deep standby backup register 21 Deep standby backup register 22 Deep standby backup register 23 Deep standby backup register 24 Deep standby backup register 25 Deep standby backup register 26 Deep standby backup register 27 Deep standby backup register 28 Deep standby backup register 29 Deep standby backup register 30 Deep standby backup register 31 Input level control/status register 1 Output level control/status register 1 Input level control/status register 2 Output level control/status register 2 Input level control/status register 3 Software port output enable register Port output enable control register 1 Port output enable control register 2 Port output enable control register 3 LVDKEYR LVDCR DPSBKR0 DPSBKR1 DPSBKR2 DPSBKR3 DPSBKR4 DPSBKR5 DPSBKR6 DPSBKR7 DPSBKR8 DPSBKR9 DPSBKR10 DPSBKR11 DPSBKR12 DPSBKR13 DPSBKR14 DPSBKR15 DPSBKR16 DPSBKR17 DPSBKR18 DPSBKR19 DPSBKR20 DPSBKR21 DPSBKR22 DPSBKR23 DPSBKR24 DPSBKR25 DPSBKR26 DPSBKR27 DPSBKR28 DPSBKR29 DPSBKR30 DPSBKR31 ICSR1 OCSR1 ICSR2 OCSR2 ICSR3 SPOER POECR1 POECR2 POECR3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8, 16 8, 16 8, 16 8, 16 8, 16 8 8 16 16 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 4 to 5PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 46 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (14 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0008 C4D0h 0008 C4D2h 0008 C4D4h 0008 C4D6h 0008 C4D8h 0008 C4DAh 0009 0200h to 0009 03FFh 0009 0400h 0009 0404h 0009 0408h 0009 040Ch 0009 0410h 0009 0414h 0009 0418h 0009 041Ch 0009 0420h 0009 0424h 0009 0428h 0009 042Ch 0009 0820h to 0009 083Fh 0009 0840h 0009 0842h 0009 0844h 0009 0848h 0009 0849h 0009 084Ah 0009 084Bh 0009 084Ch 0009 084Dh 0009 084Eh 0009 084Fh 0009 0850h 0009 0851h 0009 0852h 0009 0853h 0009 0854h 0009 0856h 0009 0858h 0009 4001h 0009 4002h 0009 4003h POE POE POE POE POE POE CAN0*4 Port output enable control register 4 Port output enable control register 5 Port output enable control register 6 Input level control/status register 4 Input level control/status register 5 Active level setting register 1 Mailbox registers 0 to 31 POECR4 POECR5 POECR6 ICSR4 ICSR5 ALR1 MB0 to MB 31 MKR0 MKR1 MKR2 MKR3 MKR4 MKR5 MKR6 MKR7 FIDCR0 FIDCR1 MKIVLR MIER MCTL0 to MCTL31 CTLR STR BCR RFCR RFPCR TFCR TFPCR EIER EIFR RECR TECR ECSR CSSR MSSR MSMR TSR AFSR TCR LWBR LBRP0 LBRP1 16 16 16 16 16 16 128 16 16 16 8, 16 8, 16 8, 16 8, 16, 32 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 Mask register 0 Mask register 1 Mask register 2 Mask register 3 Mask register 4 Mask register 5 Mask register 6 Mask register 7 FIFO received ID compare register 0 FIFO received ID compare register 1 Mask invalid register Mailbox interrupt enable register Message control registers 0 to 31 32 32 32 32 32 32 32 32 32 32 32 32 8 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 CAN0*4 LIN0 LIN0 LIN0 Control register Status register Bit configuration register Receive FIFO control register Receive FIFO pointer control register Transmit FIFO control register Transmit FIFO pointer control register Error interrupt enable register Error interrupt factor judge register Receive error count register Transmit error count register Error code store register Channel search support register Mailbox search status register Mailbox search mode register Time stamp register Acceptance filter support register Test control register LIN wake-up baud rate select register LIN baud rate prescaler 0 register LIN baud rate prescaler 1 register 16 16 32 8 8 8 8 8 8 8 8 8 8 8 8 16 16 8 8 8 8 8, 16 8, 16 8, 16, 32 8 8 8 8 8 8 8 8 8 8 8 8 8, 16 8, 16 8 8 8, 16 8, 16 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 47 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (15 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 0009 4004h 0009 4008h 0009 4009h 0009 400Ah 0009 400Bh 0009 400Ch 0009 400Dh 0009 400Eh 0009 4010h 0009 4011h 0009 4012h 0009 4013h 0009 4014h 0009 4015h 0009 4016h 0009 4018h 0009 4019h 0009 401Ah 0009 401Bh 0009 401Ch 0009 401Dh 0009 401Eh 0009 401Fh 000C 1200h 000C 1201h 000C 1202h 000C 1203h 000C 1204h 000C 1205h 000C 1206h 000C 1207h 000C 1208h 000C 1209h 000C 120Ah 000C 120Dh 000C 120Eh 000C 120Fh 000C 1210h 000C 1212h 000C 1214h 000C 1216h 000C 1218h 000C 121Ah 000C 121Ch LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 LIN0 MTU3 MTU4 MTU3 MTU4 MTU3 MTU3 MTU4 MTU4 MTU3 MTU4 MTU MTU MTU MTU MTU3 MTU4 MTU MTU MTU3 MTU3 MTU4 LIN self-test control register Mode register Break field setting register Space setting register Wake-up setting register Interrupt enable register Error detection enable register Control register Transmission control register Mode status register Status register Error status register Response field set register Buffer register Check sum buffer register Data 1 buffer register Data 2 buffer register Data 3 buffer register Data 4 buffer register Data 5 buffer register Data 6 buffer register Data 7 buffer register Data 8 buffer register Timer control register Timer control register Timer mode register 1 Timer mode register 1 Timer I/O control register H Timer I/O control register L Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer interrupt enable register Timer output master enable register A Timer gate control register A Timer output control register 1A Timer output control register 2A Timer counter Timer counter Timer cycle data register A Timer dead time data register A Timer general register A Timer general register B Timer general register A LSTC L0MD L0BRK L0SPC L0WUP L0IE L0EDE L0C L0TC L0MST L0ST L0EST L0RFC L0IDB L0CBR L0DB1 L0DB2 L0DB3 L0DB4 L0DB5 L0DB6 L0DB7 L0DB8 TCR TCR TMDR1 TMDR1 TIORH TIORL TIORH TIORL TIER TIER TOERA TGCRA TOCR1A TOCR2A TCNT TCNT TCDRA TDDRA TGRA TGRB TGRA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16 8, 16 8 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16 8, 16 8 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8 8, 16 8 8, 16, 32 8 8, 16 8 8, 16 8 8 8 8, 16 8 16, 32 16 16, 32 16 16, 32 16 16, 32 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 48 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (16 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 000C 121Eh 000C 1220h 000C 1222h 000C 1224h 000C 1226h 000C 1228h 000C 122Ah 000C 122Ch 000C 122Dh 000C 1230h 000C 1231h 000C 1232h 000C 1234h 000C 1236h 000C 1238h 000C 1239h 000C 123Ah 000C 123Bh 000C 123Ch 000C 1240h 000C 1244h 000C 1246h 000C 1248h 000C 124Ah 000C 1260h 000C 1270h 000C 1272h 000C 1274h 000C 1276h 000C 1280h 000C 1281h 000C 1282h 000C 1284h 000C 1300h 000C 1301h 000C 1302h 000C 1303h 000C 1304h 000C 1305h 000C 1306h 000C 1308h MTU4 MTU MTU MTU3 MTU3 MTU4 MTU4 MTU3 MTU4 MTU MTU MTU MTU MTU MTU3 MTU4 MTU MTU MTU MTU4 MTU4 MTU4 MTU4 MTU4 MTU MTU3 MTU3 MTU4 MTU4 MTU MTU MTU MTU MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 Timer general register B Timer subcounter A Timer cycle buffer register A Timer general register C Timer general register D Timer general register C Timer general register D Timer status register Timer status register Timer interrupt skipping set register 1A Timer interrupt skipping counter 1A Timer buffer transfer set register A Timer dead time enable register A Timer output level buffer register A Timer buffer operation transfer mode register Timer buffer operation transfer mode register Timer interrupt skipping mode register A Timer interrupt skipping set register 2A Timer interrupt skipping counter 2A Timer A/D converter start request control register Timer A/D converter start request cycle set register A Timer A/D converter start request cycle set register B Timer A/D converter start request cycle set buffer register A Timer A/D converter start request cycle set buffer register B Timer waveform control register A Timer mode register 2A Timer general register E Timer general register E Timer general register F Timer start register A Timer synchronous register A Timer counter synchronous start register Timer read/write enable register A Timer control register Timer mode register 1 Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer status register Timer counter Timer general register A TGRB TCNTSA TCBRA TGRC TGRD TGRC TGRD TSR TSR TITCR1A TITCNT1A TBTERA TDERA TOLBRA TBTM TBTM TITMRA TITCR2A TITCNT2A TADCR TADCORA TADCORB TADCOBRA TADCOBRB TWCRA TMDR2A TGRE TGRE TGRF TSTRA TSYRA TCSYSTR TRWERA TCR TMDR1 TIORH TIORL TIER TSR TCNT TGRA 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 16 16 16 16, 32 16 16, 32 16 16, 32 16 8, 16 8 8, 16 8 8 8 8 8, 16 8 8 8 8 16 16, 32 16 16, 32 16 8 8 16 16 16 8, 16 8 8 8 8, 16, 32 8 8, 16 8 8, 16, 32 8 16 16, 32 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 49 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (17 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 000C 130Ah 000C 130Ch 000C 130Eh 000C 1320h 000C 1322h 000C 1324h 000C 1325h 000C 1326h 000C 1380h 000C 1381h 000C 1382h 000C 1384h 000C 1385h 000C 1386h 000C 1388h 000C 138Ah 000C 1390h 000C 1400h 000C 1401h 000C 1402h 000C 1404h 000C 1405h 000C 1406h 000C 1408h 000C 140Ah 000C 1A00h 000C 1A01h 000C 1A02h 000C 1A03h 000C 1A04h 000C 1A05h 000C 1A06h 000C 1A07h 000C 1A08h 000C 1A09h 000C 1A0Ah 000C 1A0Eh 000C 1A0Fh 000C 1A10h 000C 1A12h 000C 1A14h 000C 1A16h 000C 1A18h 000C 1A1Ah MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU1 MTU1 MTU1 MTU1 MTU1 MTU1 MTU1 MTU1 MTU1 MTU2 MTU2 MTU2 MTU2 MTU2 MTU2 MTU2 MTU2 MTU6 MTU7 MTU6 MTU7 MTU6 MTU6 MTU7 MTU7 MTU6 MTU7 MTU MTU MTU MTU6 MTU7 MTU MTU MTU6 MTU6 Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer interrupt enable register 2 Timer status register 2 Timer buffer operation transfer mode register Timer control register Timer mode register 1 Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer input capture control register Timer control register Timer mode register 1 Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer control register Timer control register Timer mode register 1 Timer mode register 1 Timer I/O control register H Timer I/O control register L Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer interrupt enable register Timer output master enable register B Timer output control register 1B Timer output control register 2B Timer counter Timer counter Timer cycle data register B Timer dead time data register B Timer general register A Timer general register B TGRB TGRC TGRD TGRE TGRF TIER2 TSR2 TBTM TCR TMDR1 TIOR TIER TSR TCNT TGRA TGRB TICCR TCR TMDR1 TIOR TIER TSR TCNT TGRA TGRB TCR TCR TMDR1 TMDR1 TIORH TIORL TIORH TIORL TIER TIER TOERB TOCR1B TOCR2B TCNT TCNT TCDRB TDDRB TGRA TGRB 16 16 16 16 16 8 8 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16, 32 16 16, 32 16 8, 16 8 8 8, 16 8 8 8, 16, 32 8 16 16, 32 16 8 8, 16 8 8 8, 16, 32 8 16 16, 32 16 8, 16, 32 8 8, 16 8 8, 16, 32 8 8, 16 8 8, 16 8 8 8, 16 8 16, 32 16 16, 32 16 16, 32 16 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 50 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (18 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 000C 1A1Ch 000C 1A1Eh 000C 1A20h 000C 1A22h 000C 1A24h 000C 1A26h 000C 1A28h 000C 1A2Ah 000C 1A2Ch 000C 1A2Dh 000C 1A30h 000C 1A31h 000C 1A32h 000C 1A34h 000C 1A36h 000C 1A38h 000C 1A39h 000C 1A3Ah 000C 1A3Bh 000C 1A3Ch 000C 1A40h 000C 1A44h 000C 1A46h 000C 1A48h 000C 1A4Ah 000C 1A50h 000C 1A60h 000C 1A70h 000C 1A72h 000C 1A74h 000C 1A76h 000C 1A80h 000C 1A81h 000C 1A84h 000C 1C80h 000C 1C82h 000C 1C84h 000C 1C86h 000C 1C90h 000C 1C92h 000C 1C94h MTU7 MTU7 MTU MTU MTU6 MTU6 MTU7 MTU7 MTU6 MTU7 MTU MTU MTU MTU MTU MTU6 MTU7 MTU MTU MTU MTU7 MTU7 MTU7 MTU7 MTU7 MTU6 MTU MTU MTU6 MTU7 MTU7 MTU MTU MTU MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 Timer general register A Timer general register B Timer subcounter B Timer cycle buffer register B Timer general register C Timer general register D Timer general register C Timer general register D Timer status register Timer status register Timer interrupt skipping set register 1B Timer interrupt skipping counter 1B Timer buffer transfer set register B Timer dead time enable register B Timer output level buffer register B Timer buffer operation transfer mode register Timer buffer operation transfer mode register Timer interrupt skipping mode register B Timer interrupt skipping set register 2B Timer interrupt skipping counter 2B Timer A/D converter start request control register Timer A/D converter start request cycle set register A Timer A/D converter start request cycle set register B Timer A/D converter start request cycle set buffer register A Timer A/D converter start request cycle set buffer register B Timer synchronous clear register Timer waveform control register B Timer mode register 2B Timer general register E Timer general register E Timer general register F Timer start register B Timer synchronous register B Timer read/write enable register B Timer counter U Timer general register U Timer control register U Timer I/O control register U Timer counter V Timer general register V Timer control register V TGRA TGRB TCNTSB TCBRB TGRC TGRD TGRC TGRD TSR TSR TITCR1B TITCNT1B TBTERB TDERB TOLBRB TBTM TBTM TITMRB TITCR2B TITCNT2B TADCR TADCORA TADCORB TADCOBRA TADCOBRB TSYCR TWCRB TMDR2B TGRE TGRE TGRF TSTRB TSYRB TRWERB TCNTU TGRU TCRU TIORU TCNTV TGRV TCRV 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 16 16 16 8 8 8 16 16 8 8 16 16 8 16, 32 16 16, 32 16 16, 32 16 16, 32 16 8, 16 8 8, 16 8 8 8 8 8, 16 8 8 8 8 16 16, 32 16 16, 32 16 8 8 8 16 16 16 8, 16 8 8 16, 32 16 8 8 16, 32 16 8 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 51 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (19 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 000C 1C96h 000C 1CA0h 000C 1CA2h 000C 1CA4h 000C 1CA6h 000C 1CB0h 000C 1CB2h 000C 1CB4h 000C 1CB6h 000C 2000h 000C 2004h 000C 2006h 000C 2008h 000C 200Ah 000C 200Ch 000C 200Eh 000C 2010h 000C 2014h 000C 2080h 000C 2082h 000C 2084h 000C 2086h 000C 2088h 000C 208Ah 000C 208Ch 000C 208Eh 000C 2090h 000C 2092h 000C 2094h 000C 2096h '000C 2098h 000C 209Ah 000C 209Ch 000C 209Eh 000C 20A0h 000C 20A2h 000C 20A4h 000C 20A6h 000C 20A8h MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT GPT Timer I/O control register V Timer counter W Timer general register W Timer control register W Timer I/O control register W Timer status register Timer interrupt enable register Timer start register Timer compare match clear register General PWM timer software start register General PWM timer hardware source start control register General PWM timer hardware source clear control register General PWM timer hardware start source select register General PWM timer hardware stop/clear source select register General PWM timer write-protection register General PWM timer sync register General PWM timer external trigger input interrupt register General PWM timer buffer operation disable register LOCO count control register LOCO count status register LOCO count value register LOCO count result average register LOCO count result register 0 LOCO count result register 1 LOCO count result register 2 LOCO count result register 3 LOCO count result register 4 LOCO count result register 5 LOCO count result register 6 LOCO count result register 7 LOCO count result register 8 LOCO count result register 9 LOCO count result register 10 LOCO count result register 11 LOCO count result register 12 LOCO count result register 13 LOCO count result register 14 LOCO count result register 15 LOCO count upper permissible deviation register TIORV TCNTW TGRW TCRW TIORW TSR TIER TSTR TCNTCMPC LR GTSTR GTHSCR GTHCCR GTHSSR GTHPSR GTWP GTSYNC GTETINT GTBDR LCCR LCST LCNT LCNTA LCNT00 LCNT01 LCNT02 LCNT03 LCNT04 LCNT05 LCNT06 LCNT07 LCNT08 LCNT09 LCNT10 LCNT11 LCNT12 LCNT13 LCNT14 LCNT15 LCNTDU 8 16 16 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 16, 32 16 8 8 8 8 8 8 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 5ICLK 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 52 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (20 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 000C 20AAh 000C 2100h 000C 2102h 000C 2104h 000C 2106h 000C 2108h 000C 210Ah 000C 210Ch 000C 210Eh 000C 2110h 000C 2112h 000C 2114h 000C 2116h 000C 2118h 000C 211Ah 000C 211Ch 000C 211Eh 000C 2120h 000C 2124h 000C 2126h 000C 2128h 000C 212Ch 000C 212Eh 000C 2130h 000C 2134h 000C 2136h 000C 2138h 000C 213Ah 000C 213Ch 000C 213Eh 000C 2140h 000C 2142h 000C 2180h 000C 2182h 000C 2184h 000C 2186h GPT GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT0 GPT1 GPT1 GPT1 GPT1 LOCO count lower permissible deviation register General PWM timer I/O control register General PWM timer interrupt output setting register General PWM timer control register General PWM timer buffer enable register General PWM timer count direction register General PWM timer interrupt and A/D converter start request skipping setting register General PWM timer status register General PWM timer counter General PWM timer compare capture register A General PWM timer compare capture register B General PWM timer compare capture register C General PWM timer compare capture register D General PWM timer compare capture register E General PWM timer compare capture register F General PWM timer cycle setting register General PWM timer cycle setting buffer register General PWM timer cycle setting double-buffer register A/D converter start request timing register A A/D converter start request timing buffer register A A/D converter start request timing double-buffer register A A/D converter start request timing register B A/D converter start request timing buffer register B A/D converter start request timing double-buffer register B General PWM timer output negate control register General PWM timer dead time control register General PWM timer dead time value register General PWM timer dead time value register General PWM timer dead time buffer register General PWM timer dead time buffer register General PWM timer output protection function status register General PWM timer output protection function temporary release register General PWM timer I/O control register General PWM timer interrupt output setting register General PWM timer control register General PWM timer buffer enable register LCNTDL GTIOR GTINTAD GTCR GTBER GTUDC GTITC GTST GTCNT GTCCRA GTCCRB GTCCRC GTCCRD GTCCRE GTCCRF GTPR GTPBR GTPDBR GTADTRA GTADTBRA GTADTDBRA GTADTRB GTADTBRB GTADTDBRB GTONCR GTDTCR GTDVU GTDVD GTDBU GTDBD GTSOS GTSOTR GTIOR GTINTAD GTCR GTBER 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 53 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (21 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 000C 2188h 000C 218Ah 000C 218Ch 000C 218Eh 000C 2190h 000C 2192h 000C 2194h 000C 2196h 000C 2198h 000C 219Ah 000C 219Ch 000C 219Eh 000C 21A0h 000C 21A4h 000C 21A6h 000C 21A8h 000C 21ACh 000C 21AEh 000C 21B0h 000C 21B4h 000C 21B6h 000C 21B8h 000C 21BAh 000C 21BCh 000C 21BEh 000C 21C0h 000C 21C2h 000C 2200h 000C 2202h 000C 2204h 000C 2206h 000C 2208h 000C 220Ah 000C 220Ch 000C 220Eh 000C 2210h GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT1 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 General PWM timer count direction register General PWM timer interrupt and A/D converter start request skipping setting register General PWM timer status register General PWM timer counter General PWM timer compare capture register A General PWM timer compare capture register B General PWM timer compare capture register C General PWM timer compare capture register D General PWM timer compare capture register E General PWM timer compare capture register F General PWM timer cycle setting register General PWM timer cycle setting buffer register General PWM timer cycle setting double-buffer register A/D converter start request timing register A A/D converter start request timing buffer register A A/D converter start request timing double-buffer register A A/D converter start request timing register B A/D converter start request timing buffer register B A/D converter start request timing double-buffer register B General PWM timer output negate control register General PWM timer dead time control register General PWM timer dead time value register General PWM timer dead time value register General PWM timer dead time buffer register General PWM timer dead time buffer register General PWM timer output protection function status register General PWM timer output protection temporary release register General PWM timer I/O control register General PWM timer interrupt output setting register General PWM timer control register General PWM timer buffer enable register General PWM timer count direction register General PWM timer interrupt and A/D converter start request skipping setting register General PWM timer status register General PWM timer counter General PWM timer compare capture register A GTUDC GTITC GTST GTCNT GTCCRA GTCCRB GTCCRC GTCCRD GTCCRE GTCCRF GTPR GTPBR GTPDBR GTADTRA GTADTBRA GTADTDBRA GTADTRB GTADTBRB GTADTDBRB GTONCR GTDTCR GTDVU GTDVD GTDBU GTDBD GTSOS GTSOTR GTIOR GTINTAD GTCR GTBER GTUDC GTITC GTST GTCNT GTCCRA 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8, 16, 32 8, 16, 32 8, 16, 32 16 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16 16, 32 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 54 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (22 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 000C 2212h 000C 2214h 000C 2216h 000C 2218h 000C 221Ah 000C 221Ch 000C 221Eh 000C 2220h 000C 2224h 000C 2226h 000C 2228h 000C 222Ch 000C 222Eh 000C 2230h 000C 2234h 000C 2236h 000C 2238h 000C 223Ah 000C 223Ch 000C 223Eh 000C 2240h 000C 2242h 000C 2280h 000C 2282h 000C 2284h 000C 2286h 000C 2288h 000C 228Ah 000C 228Ch 000C 228Eh 000C 2290h 000C 2292h 000C 2294h 000C 2296h 000C 2298h 000C 229Ah 000C 229Ch GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 General PWM timer compare capture register B General PWM timer compare capture register C General PWM timer compare capture register D General PWM timer compare capture register E General PWM timer compare capture register F General PWM timer cycle setting register General PWM timer cycle setting buffer register General PWM timer cycle setting double-buffer register A/D converter start request timing register A A/D converter start request timing buffer register A A/D converter start request timing double-buffer register A A/D converter start request timing register B A/D converter start request timing buffer register B A/D converter start request timing double-buffer register B General PWM timer output negate control register General PWM timer dead time control register General PWM timer dead time value register General PWM timer dead time value register General PWM timer dead time buffer register General PWM timer dead time buffer register General PWM timer output protection function status register General PWM timer output protection temporary release register General PWM timer I/O control register General PWM timer interrupt output setting register General PWM timer control register General PWM timer buffer enable register General PWM timer count direction register General PWM timer interrupt and A/D converter start request skipping setting register General PWM timer status register General PWM timer counter General PWM timer compare capture register A General PWM timer compare capture register B General PWM timer compare capture register C General PWM timer compare capture register D General PWM timer compare capture register E General PWM timer compare capture register F General PWM timer cycle setting register GTCCRB GTCCRC GTCCRD GTCCRE GTCCRF GTPR GTPBR GTPDBR GTADTRA GTADTBRA GTADTDBRA GTADTRB GTADTBRB GTADTDBRB GTONCR GTDTCR GTDVU GTDVD GTDBU GTDBD GTSOS GTSOTR GTIOR GTINTAD GTCR GTBER GTUDC GTITC GTST GTCNT GTCCRA GTCCRB GTCCRC GTCCRD GTCCRE GTCCRF GTPR 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 55 of 92 RX62T Group Table 4.1 List of I/O Registers (Address Order) (23 / 23) Module Abbreviation Register Number Access Abbreviation of Bits Size 4. I/O Registers Address Register Name Number of Access Cycles 000C 229Eh 000C 22A0h 000C 22A4h 000C 22A6h 000C 22A8h 000C 22ACh 000C 22AEh 000C 22B0h 000C 22B4h 000C 22B6h 000C 22B8h 000C 22BAh 000C 22BCh 000C 22BEh 000C 22C0h 000C 22C2h 007F C402h 007F C410h 007F C411h 007F C412h 007F C440h 007F C442h 007F C450h 007F C452h 007F C454h 007F FFB0h 007F FFB1h 007F FFB2h 007F FFB4h 007F FFB6h 007F FFBAh 007F FFC8h 007F FFCAh 007F FFCCh 007F FFCEh 007F FFE8h GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH General PWM timer cycle setting buffer register General PWM timer cycle setting double-buffer register A/D converter start request timing register A A/D converter start request timing buffer register A A/D converter start request timing double-buffer register A A/D converter start request timing register B A/D converter start request timing buffer register B A/D converter start request timing double-buffer register B General PWM timer output negate control register General PWM timer dead time control register General PWM timer dead time value register General PWM timer dead time value register General PWM timer dead time buffer register General PWM timer dead time buffer register General PWM timer output protection function status register General PWM timer output protection temporary release register Flash mode register Flash access status register Flash access error interrupt enable register Flash ready interrupt enable register Data flash read enable register 0 Data flash read enable register 1 Data flash programming/erasure enable register 0 Data flash programming/erasure enable register 1 FCU RAM enable register Flash status register 0 Flash status register 1 Flash P/E mode entry register Flash protect register Flash reset register FCU command register FCU processing switching register Data flash blank check control register Flash P/E status register Data flash blank check status register Peripheral clock notification register GTPBR GTPDBR GTADTRA GTADTBRA GTADTDBRA GTADTRB GTADTBRB GTADTDBRB GTONCR GTDTCR GTDVU GTDVD GTDBU GTDBD GTSOS GTSOTR FMODR FASTAT FAEINT FRDYIE DFLRE0 DFLRE1 DFLWE0 DFLWE1 FCURAME FSTATR0 FSTATR1 FENTRYR FPROTR FRESETR FCMDR FCPSR DFLBCCNT FPESTAT DFLBCSTAT PCKAR 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 16 16 16 16 16 8 8 16 16 16 16 16 16 16 16 16 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8 8 8 8 16 16 16 16 16 8 8 16 16 16 16 16 16 16 16 16 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 3 to 5ICLK*6 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 2 to 3PCLK*5 Note 1. This register is not supported by the 100-pin LQFP version. Note 2. This register is not supported by the 80-pin LQFP version. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 56 of 92 RX62T Group Note 3. Note 4. Note 5. Note 6. 4. I/O Registers This register is not supported by the 64-pin LQFP version. This register is not supported by the product without the CAN function. The number of access states depends on the number of divided cycles for clock synchronization (0 to 1 PCLK). Reading the registers takes 3 cycles of ICLK and writing to the registers takes 5 cycles of ICLK. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 57 of 92 RX62T Group 5. Electrical Characteristics 5. 5.1 Table 5.1 Item Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings Symbol Value Unit Power supply voltage Input voltage (except for ports 4 to 6) Input voltage (port 4) Input voltage (ports 5 and 6) Analog power supply voltage Reference power supply voltage VCC PLLVCC VIN VIN VIN AVCC0, AVCC*1 VREFH0*1 VREF*1 -0.3 to +6.5 -0.3 to VCC+0.3 -0.3 to AVCC0+0.3 -0.3 to AVCC+0.3 -0.3 to +6.5 -0.3 to AVCC0+0.3 -0.3 to AVCC+0.3 -0.3 to AVCC0+0.3 -0.3 to AVCC+0.3 -40 to +85 -55 to +125 V V V V V V Analog input voltage (port 4) Analog input voltage (ports 5 and 6) Operating temperature Storage temperature VAN VAN Topr Tstg V V C C Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note 1. When the A/D converter is not in use, do not leave the AVCC0, VREFH0, VREFL0, AVSS0, AVCC, VREF, and AVSS pins open. Connect the AVCC0, VREFH0, AVCC, and VREF pins to VCC, and the AVSS0, VREFL0, and AVSS pins to VSS, respectively. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 58 of 92 RX62T Group 5. Electrical Characteristics 5.2 Table 5.2 DC Characteristics DC Characteristics (1) (1 / 3) Note: Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Schmitt trigger input voltage CAN input pin IRQ input pin MTU3 input pin POE3 input pin SCI input pin A/D trigger input pin NMI input pin GPT input pin LIN input pin RES# RIIC input pin (IICBus) VIH VIL ΔV T VCC0.8 -0.3 VCC 0.06 - VCC+0.3 VCC0.2 - V VIH VIL ΔV T VCC0.7 -0.3 VCC 0.05 AVCC0 0.8 - 0.3 AVCC0 0.06 AVCC 0.8 -0.3 AVCC 0.06 VCC0.8 -0.3 VCC 0.06 VCC0.9 VCC0.8 2.1 - VCC+0.3 VCC0.3 AVCC0 +0.3 AVCC0 0.2 AVCC +0.3 AVCC 0.2 VCC+0.3 VCC0.2 VCC+0.3 VCC+0.3 VCC+0.3 Conditions 1 and 2 V V Port 4*1 (also usable as an analog port) VIH VIL ΔV T Ports 5 and 6*1 (also usable as analog ports) VIH VIL ΔV T Ports 1 to 3*1 Ports 7 to B*1 Ports D, E, and G*1 VIH VIL ΔV T Input high voltage (except Schmitt trigger input pin) MD pin, EMLE EXTAL RSPI input pin RIIC input pin (SMBus) VIH Input low voltage (except Schmitt trigger input pin) MD pin, EMLE EXTAL RSPI input pin RIIC input pin (SMBus) VIL -0.3 -0.3 -0.3 - VCC0.1 VCC0.2 0.8 Conditions 1 and 2 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 59 of 92 RX62T Group Table 5.2 DC Characteristics (1) (2 / 3) 5. Electrical Characteristics Note: Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Output high voltage All output pins (except for P71 to P76 and P90 to P95) P71 to P76 VOH VCC-0.5 - - V IOH = -1 mA VCC-0.5 - - IOH = -1mA 64-pin LQFP Condition 3 IOH = -5mA 64-pin LQFP Other than condition 3 IOH = -1mA 80-pin LQFP or 64-pin LQFP IOH = -5 mA 112-pin LQFP or 100-pin LQFP V IOL = 1.0 mA VCC-1.0 - - P90 to P95 VCC-0.5 - - VCC-1.0 - - Output low voltage All output pins (except for P71 to P76, P90 to P95, and RIIC) P71 to P76 VOL - - 0.5 - - 0.5 IOL = 1.0 mA 64-pin LQFP Other than condition 3 IOL = 15 mA Conditions 1 and 2 IOL = 15 mA Other than 64-pin LQFP Condition 3 IOL = 1.0 mA 80-pin LQFP or 64-pin LQFP IOL = 15 mA 112-pin LQFP or 100-pin LQFP Conditions 1 and 2 IOL = 1 mA 112-pin LQFP or 100-pin LQFP Condition 3 IOL = 3 mA IOL = 6 mA - - 1.1 1.4 P90 to P95 - - 0.5 - - 1.1 - - 1.4 RIIC pin - - 0.4 0.6 1.0 1.0 5.0 Input leakage current Three-state leakage current (off state) RES#, MD pin, EMLE Ports 1 to A, PB0, PB3 to PB7, D, E, G Ports PB1 and PB2 Iin ITSI - A A Vin = 0 V, Vin = VCC Vin = 0 V, Vin = VCC R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 60 of 92 RX62T Group Table 5.2 DC Characteristics (1) (3 / 3) 5. Electrical Characteristics Note: Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Input capacitance All input pins (except for ports PB1 and PB2) Ports PB1 and PB2 Cin - - 15 pF Vin = 0 V, f = 1 MHz, Ta = 25C - - 30 Note 1. This includes the multiplexed input pins, except in cases where port pins PB1 and PB2 are used as RIIC input pins or port pins P22 to P24, P30, PA3 to PA5, PB0, PD0 to PD2, or PD6 are used as RSPI input pins. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 61 of 92 RX62T Group 5. Electrical Characteristics Table 5.3 DC Characteristics (2) Note: Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Supply current*1 In operation Max.*2 Normal*4 Increased by BGO operation*5 ICC*3 - 35 15 22 14 70 60 28 3 60 5 5 mA ICLK = 100 MHz PCLK = 50 MHz Sleep All-module-clock-stop mode*6 Standby mode Software standby mode Deep software standby mode AICC0 - 0.10 20 3 3 mA A mA mA Analog power supply current During 12-bit A/D conversion (when a sample-and-hold circuit is in use; per unit) During 12-bit A/D conversion (when a sample-and-hold circuit is not in use; per unit) Programmable gain amp (per channel) Window comparator (1 channel) Window comparator (6 channels) During 12-bit A/D conversion (per unit) During 10-bit A/D conversion (per unit) Waiting for 10-bit A/D conversion (all units) - 1 0.5 2 1 2 90 2 3 3 3 1 3 20 mA mA mA AICC AIREFH0 AIREF SVCC - 1 60 0.9 0.3 1.6 1.6 0.1 0.1 - A mA A mA mA mA Reference power supply current During 12-bit A/D conversion (per unit) Waiting for 12-bit A/D conversion (all units) During 10-bit A/D conversion (per unit) Waiting for 10-bit A/D conversion (all units) A ms/V VCC rising gradient Note 1. Supply current values are with all output pins unloaded. Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation. Note 3. ICC depends on f (ICLK) as follows. (ICLK : PCLK = 8:4) ICC max. = 0.54 x f + 16 (max.) ICC max. = 0.14 x f + 6 (normal operation) ICC max. = 0.44 x f + 16 (sleep mode) Note 4. Measured with clocks not supplied to the peripheral functions. This does not include the BGO operation. Note 5. Incremented if data is written to or erased from the ROM or data flash for data storage during the program execution. Note 6. The values are for reference. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 62 of 92 RX62T Group 5. Electrical Characteristics Table 5.4 Permissible Output Currents Note: Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Permissible output low current (average value per pin) Permissible output low current (max. value per pin) Permissible output low current (total) Permissible output high current (average value per pin) Permissible output high current (max. value per pin) Permissible output high current (total) IOL IOL ΣIOL - - 2.0*1 4.0*1 110 2.0*1 4.0*1 35 mA mA mA mA mA mA - IOH - IOH Σ- IOH Caution: To protect the LSI's reliability, the output current values should not exceed the permissible output current. Note 1. IOL = 15 mA (max.)/ - IOH = 5 mA (max.) for P71 to P76 and P90 to P95. Note, however, that up to 6 (112-pin or 100-pin LQFP) or 3 (80-pin or 64-pin LQFP) pins can accept over 2.0-mA IOL / - IOH at the same time. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 63 of 92 RX62T Group 5. Electrical Characteristics 5.3 Table 5.5 AC Characteristics Operation Frequency Value Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Operating frequency System clock (ICLK) Peripheral module clock (PCLK) f 8 8 - 100 50 MHz 5.3.1 Table 5.6 Clock Timing Clock Timing Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min. Max. Unit Test Conditions Oscillation settling time after reset (crystal) Oscillation settling time after leaving software standby mode (crystal) Oscillation settling time after leaving deep software standby mode (crystal) EXTAL external clock output delay settling time EXTAL external clock input low pulse width EXTAL external clock input high pulse width EXTAL external clock rising time EXTAL external clock falling time On-chip oscillator (IWDTCLK) oscillation frequency tOSC1 tOSC2 tOSC3 tDEXT tEXL tEXH tEXr tEXf fIWDTCLK 10 10 10 1 35 35 62.5 5 5 187.5 ms ms ms ms ns ns ns ns kHz Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.1 Figure 5.4 R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 64 of 92 RX62T Group 5. Electrical Characteristics EXTAL tDEXT VCC tOSC1 RES# ICLK Figure 5.1 Oscillation Settling Timing Oscillator ICLK IRQ IRQCRn.IRQMD[1:0] 01 10 SSBY IRQ exception handling IRQMD[1:0] = 10b SSBY = 1 WAIT instruction Software standby mode (power-down mode) Oscillation settling time tOSC2 IRQ exception handling Figure 5.2 Oscillation Settling Timing after Software Standby Mode R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 65 of 92 RX62T Group 5. Electrical Characteristics Oscillator ICLK IRQ Invalid by the internal reset IRQ interrupt DIRQnF set request Set DIRQnEG bit Set DPSBY bit When IOKEEP=H Set IOKEEP bit L Set H Cleared I/O port When IOKEEP=L Operating Retained Operating IOKEEP bit L I/O port Operating Retained Operating DPSRSTF flag Internal reset IRQ exception handling DIRQnEG = 1 SSBY = 1 Deep software standby mode (power-down mode) Oscillation settling time tOSC3 Reset exception handling WAIT instruction Figure 5.3 Oscillation Settling Timing after Deep Software Standby Mode R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 66 of 92 RX62T Group 5. Electrical Characteristics tEXH tEXL EXTAL VCC×0.5 tEXr Figure 5.4 tEXf EXTAL External Input Clock Timing R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 67 of 92 RX62T Group 5. Electrical Characteristics 5.3.2 Table 5.7 Control Signal Timing Control Signal Timing Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min. Max. Unit Test Conditions RES# pulse width (except for programming or erasure of the ROM or data-flash memory or blank checking of the data-flash memory*1) Internal reset time*3 NMI pulse width IRQ pulse width tRESW*2 20 1.5 - tIcyc*4 Figure 5.5 s s ns ns Figure 5.6 Figure 5.7 tRESW2 tNMIW tIRQW 35 200 200 Note 1. Do not allow a reset by the signal on the RES# pin during programming or erasure of the ROM or data-flash memory or during blank checking of the data-flash memory. For details, see section 30.12, Usage Notes in section 30, ROM (Flash Memory for Code Storage). Note 2. Both the time and the number of cycles should satisfy the specifications. Note 3. This is to specify the FCU reset and the WDT reset. Note 4. ICLK cycles. RES# tRESW Figure 5.5 Reset Input Timing NMI tNMIW Figure 5.6 NMI Interrupt Input Timing IRQ tIRQW Figure 5.7 IRQ Interrupt Input Timing R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 68 of 92 RX62T Group 5. Electrical Characteristics 5.3.3 Table 5.8 Timing of On-Chip Peripheral Modules Timing of On-Chip Peripheral Modules (1) Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit SCI Input clock cycle Asynchronous Clock synchronous tScyc 4tPcyc 6tPcyc 0.4tPcyc 4tPcyc 6tPcyc 0.4tScyc 40 40 0.6tScyc 20 20 0.6tScyc 20 20 40 - ns Figure 5.8 Input clock pulse width Input clock rise time Input clock fall time Output clock cycle Asynchronous Clock synchronous Output clock pulse width Output clock rise time Output clock fall time Transmit data delay time (clock synchronous) Receive data setup time (clock synchronous) Receive data hold time (clock synchronous) Note: • tPcyc: PCLK cycle tSCKW tSCKr tSCKf tScyc ns ns ns ns ns ns ns ns ns ns ns Figure 5.9 tSCKW tSCKr tSCKf tTXD tRXS tRXH tSCKW SCKn (n = 0 to 2) tSCKr tSCKf tScyc Figure 5.8 SCK Clock Input Timing SCKn tTXD TxDn tRXS tRXH RxDn n = 0 to 2 Figure 5.9 SCI Input/Output Timing: Clock Synchronous Mode R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 69 of 92 RX62T Group 5. Electrical Characteristics Table 5.9 Timing of On-Chip Peripheral Modules (2) Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min.*1 *2 Max. Unit Test Conditions RIIC (standard mode) SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time Start condition input hold time Re-start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb 6(12) tllCcyc + 1300 3(6)  tllCcyc + 300 3(6)  tllCcyc + 1000 0 3(6)  tllCcyc + 300 tllCcyc + 300 1000 1000 tllCcyc + 50 0 6(12) tllCcyc + 600 3(6)  tllCcyc + 300 3(6)  tllCcyc + 300 20 + 0.1Cb 20 + 0.1Cb 0 3(6)  tllCcyc + 300 tllCcyc + 300 300 300 tllCcyc + 50 0 - 1000 300 1(4) tllCcyc 400 300 300 1(4) tllCcyc 400 ns ns ns ns ns ns ns ns ns ns ns ns pF ns ns ns ns ns ns ns ns ns ns ns ns pF Figure 5.10 RIIC (fast mode) SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time Start condition input hold time Re-start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Note: • tIICcyc: Cycles of internal base clock (IICφ) for the RIIC module Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1. Note 2. Cb indicates the total capacity of the bus line. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 70 of 92 RX62T Group 5. Electrical Characteristics VIH SDA VIL tBUF tSCLH tSTAH tSTAS tSP tSTOS SCL P *1 S *1 tSCLL tSf tSCL tSr tSDAH Test conditions VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0) VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1) Sr *1 tSDAS P *1 Note 1: S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Figure 5.10 I2C Bus Interface Input/Output Timing R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 71 of 92 RX62T Group 5. Electrical Characteristics Table 5.10 Timing of On-Chip Peripheral Modules (3) Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min. Max. Unit Test Conditions RSPI RSPCK clock cycle Master Slave tSPcyc 4 8 4096 4096 5 1 8 8 20 3tPcyc +40 8tSPcyc +2tPcyc 15 1 15 1 4 3 tPcyc Figure 5.11 RSPCK clock high pulse width Master Slave tSPCKWH (tSpcyc - tSPCKR tSPCKF) / 2-3 (tSpcyc - tSPCKR tSPCKF) / 2 ns RSPCK clock low pulse width Master Slave tSPCKWL (tSpcyc - tSPCKR tSPCKF) / 2-3 (tSpcyc - tSPCKR tSPCKF) / 2 ns RSPCK clock rise/fall time Output Input tSPCKR tSPCKF tSU 25 0 ns s ns Figure 5.12 to Figure 5.15 Data input setup time Master Slave Data input hold time Master Slave tH 0 20+2tPcyc ns SSL setup time Master Slave tLEAD 1 4 tSPcyc tPcyc tSPcyc tPcyc ns SSL hold time Master Slave tLAG 1 4 Data output delay time Master Slave tOD - Data output hold time Master Slave tOH 0 0 tSPcyc+2tPcyc 4tPcyc ns Sucessive transmission delay time Master Slave tTD ns MOSI, MISO rise/fall time Output Input tDR tDF tSSLR tSSLF tSA tREL - ns s ns Figure 5.12 to Figure 5.15 SSL rise/fall time Output Input s tPcyc tPcyc Figure 5.12 to Figure 5.15 Slave access time Slave output release time Note: • Note 1: tPcyc: PCLK cycle R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 72 of 92 RX62T Group 5. Electrical Characteristics tSPCKWH VOH RSPCK Master select output tSPCKr VOH VOL VOL tSPCKWL tSPcyc VOH VOH tSPCKf VOL tSPCKWH VIH RSPCK Slave select output tSPCKr VIH VIL VIL tSPCKWL VIH VIH tSPCKf VIL tSPcyc Figure 5.11 RSPI Clock Timing tTD SSL0 to SSL3 output tLEAD RSPCK CPOL=0 output RSPCK CPOL=1 output tLAG tSSLr、tSSLf tSU tH DATA tOH MSB OUT DATA tOD LSB OUT IDLE MSB OUT LSB IN MSB IN MISO input MSB IN tDr、tDf MOSI output Figure 5.12 RSPI Timing (Master, CPHA = 0) R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 73 of 92 RX62T Group 5. Electrical Characteristics tTD SSL0 to SSL3 output tLEAD RSPCK CPOL=0 output RSPCK CPOL=1 output MISO input tOH MOSI output MSB OUT tLAG tSSLr、tSSLf tSU tH DATA tOD DATA LSB OUT LSB IN tDr、tDf IDLE MSB OUT MSB IN MSB IN Figure 5.13 RSPI Timing (Master, CPHA = 1) tTD SSL0 input tLEAD RSPCK CPOL=0 input RSPCK CPOL=1 input tSA MISO output tSU MOSI input tOH MSB OUT tH DATA LSB IN DATA tOD LSB OUT tDr、tDf MSB IN tREL MSB IN MSB OUT tLAG MSB IN Figure 5.14 RSPI Timing (Slave, CPHA = 0) R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 74 of 92 RX62T Group 5. Electrical Characteristics tTD SSL0 input tLEAD RSPCK CPOL=0 input RSPCK CPOL=1 input tLAG tSA tOH LSB OUT (Last data) MSB OUT tSU tH tOD DATA tDr、tDf DATA LSB IN LSB OUT tREL MSB OUT MISO output MOSI input MSB IN MSB IN Figure 5.15 RSPI Timing (Slave, CPHA = 1) R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 75 of 92 RX62T Group 5. Electrical Characteristics Table 5.11 Timing of On-Chip Peripheral Modules (4) Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min. Max. Unit Test Conditions MTU3 Input capture input pulse width (single-edge setting) Input capture input pulse width (both-edge setting) Timer clock pulse width (single-edge setting) Timer clock pulse width (both-edge setting) Timer clock pulse width (phase coefficient mode) tTICW tTICW tTCKWH/L tTCKWH/L tTCKWH/L tGTICW tGTICW 3.0 5.0 3.0 5.0 5.0 3.0 5.0 - tIcyc tIcyc tIcyc tIcyc tIcyc tIcyc tIcyc Figure 5.16 Figure 5.17 GPT Input capture input pulse width (single-edge setting) Input capture input pulse width (both-edge setting) Figure 5.18 Note: • tIcyc: ICLK cycle ICLK Input capture input tTICW Figure 5.16 MTU3 Input/Output Timing ICLK MTCLKA to MTCLKD tTCKWL Figure 5.17 MTU3 Clock Input Timing tTCKWH R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 76 of 92 RX62T Group 5. Electrical Characteristics ICLK Input capture input tGTICW Figure 5.18 Table 5.12 GPT Input/Output Timing Timing of On-Chip Peripheral Modules (5) Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Max. Unit Test Conditions POE3 POE# input pulse width tPOEW 1.5 - tPcyc Figure 5.19 Note: • tPcyc: PCLK cycle PCLK POEn# input tPOEW Figure 5.19 POE3# Clock Timing R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 77 of 92 RX62T Group 5. Electrical Characteristics 5.4 A/D Conversion Characteristics 10-Bit A/D Conversion Characteristics Table 5.13 Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Ta = -40 to +85°C Item Min. Typ. Max. Unit Test Conditions Resolution Conversion time*1 (AD clock = 25-MHz operation) Analog input capacitance Integral nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Permissible signal source impedance 10 2.0 - 10 0.5 10 4 3.0 3.0 3.0 Bit s Sampling 25 states pF LSB LSB LSB LSB LSB k 4.0 - 1.0 Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Min. Typ. Max. Unit Test Conditions Resolution Conversion (AD clock = 50-MHz operation) Analog input capacitance Integral nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Permissible signal source impedance time*1 10 1.0 - 10 0.5 10 4 3.0 3.0 3.0 Bit s Sampling 25 states pF LSB LSB LSB LSB LSB k 4.0 - 1.0 Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 78 of 92 RX62T Group 5. Electrical Characteristics Table 5.14 12-Bit A/D Conversion Characteristics Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Ta = -40 to +85°C, ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz Item Min. Typ. Max. Unit Test Conditions Resolution Conversion time*1 (AD clock = 25-MHz operation) Analog input capacitance Integral nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy When a sample-and-hold circuit is in use When a sample-and-hold circuit is not in use Permissible signal source impedance 12 2.0 - 12 - 12 6 Bit s pF LSB LSB LSB LSB LSB LSB k Sampling 20 states 4.0 7.5 7.5 - 0.5 - 8.0 8.0 3.0 AVin = 0.25 to AVREFH 0.25 AVin = AVREFL to AVREFH Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz. Item Min. Typ. Max. Unit Test Conditions Resolution Conversion time*1 (AD clock = 25-MHz operation) Analog input capacitance Integral nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy When a sample-and-hold circuit is in use When a sample-and-hold circuit is not in use Permissible signal source impedance 12 1.0 - 12 - 12 6 Bit s pF LSB LSB LSB LSB LSB LSB k Sampling 20 states 4.0 7.5 7.5 - 0.5 - 8.0 8.0 3.0 AVin = 0.25 to AVREFH 0.25 AVin = AVREFL to AVREFH Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 79 of 92 RX62T Group 5. Electrical Characteristics Table 5.15 Programmable Gain Amp Characteristics Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Analog input capacitance Input offset voltage Input voltage range (Vin) Gain  2.000 Gain  2.500 Gain  3.077 Gain  3.636 Gain  4.000 Gain  4.444 Gain  5.000 Gain  5.714 Gain  6.667 Gain  10.000 Gain  13.333 Slew rate Gain error Gain  2.000 Gain  2.500 Gain  3.077 Gain  3.636 Gain  4.000 Gain  4.444 Gain  5.000 Gain  5.714 Gain  6.667 Gain  10.000 Gain  13.333 Cin Voff Vin 0.050 x AVcc 0.047 x AVcc 0.045 x AVcc 0.042 x AVcc 0.040 x AVcc 0.036 x AVcc 0.033 x AVcc 0.031 x AVcc 0.029 x AVcc 0.025 x AVcc 0.023 x AVcc - 6 8 0.38 x AVcc 0.30 x AVcc 0.24 x AVcc 0.21 x AVcc 0.19 x AVcc 0.17 x AVcc 0.15 x AVcc 0.13 x AVcc 0.11 x AVcc 0.08 x AVcc 0.06 x AVcc 1 1 1 1.5 1.5 2 2 2 3 4 4 pF mV V SR - 10 - V/s % R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 80 of 92 RX62T Group 5. Electrical Characteristics Table 5.16 Comparator Characteristics Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Analog input capacitance REFH pin offset voltage REFL pin offset voltage REFH input voltage range REFL input voltage range REFH reply time REFL reply time Cin Voff - - 6 5 5 AVcc – 0.3 AVcc – 1.7 1 1 pF mV mV V V Vin 1.7 0.3 tCR tCF - s s R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 81 of 92 RX62T Group 5. Electrical Characteristics 5.5 Power-on Reset Circuit, Voltage Detection Circuit Characteristics Power-on Reset Circuit, Voltage Detection Circuit Characteristics Table 5.17 Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Voltage detection level Power-on reset (POR) Voltage detection circuit (LVD) VPOR Vdet1 Vdet2 tPOR tVOFF tdet 2.48 2.68 2.98 20 200 - 2.60 2.80 3.10 35 - 2.72 2.92 3.22 50 200 V Figure 5.20 Figure 5.21 Figure 5.22 Internal reset time Min. VCC down time*1 Reply delay time ms us us Figure 5.21 and Figure 5.22 Figure 5.20 to Figure 5.22 Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C Item Symbol Min. Typ. Max. Unit Test Conditions Voltage detection level Power-on reset (POR) Voltage detection circuit (LVD) VPOR Vdet1 Vdet2 tPOR tVOFF tdet 3.70 3.95 4.40 20 200 - 3.90 4.15 4.60 35 - 4.10 4.35 4.80 50 200 V Figure 5.20 Figure 5.21 Figure 5.22 Internal reset time Min. VCC down time*1 Reply delay time ms us us Figure 5.21 and Figure 5.22 Figure 5.20 to Figure 5.22 Note 1. The power-off time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1, and Vdet2 for the POR/ LVD. t VOFF VCC VPOR Internal reset signal (low valid) t POR Figure 5.20 Power-on Reset Timing t det t POR R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 82 of 92 RX62T Group 5. Electrical Characteristics t VOFF VCC Vdet1 Internal reset signal (low valid) t det Figure 5.21 Voltage Detection Circuit Timing (Vdet1) t POR t VOFF Vdet2 VCC Internal reset signal (low valid) t det Figure 5.22 Voltage Detection Circuit Timing (Vdet2) t POR R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 83 of 92 RX62T Group 5. Electrical Characteristics 5.6 Oscillation Stop Detection Timing Oscillation Stop Detection Circuit Characteristics Table 5.18 Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Detection time Internal oscillation frequency when oscillation stop is detected tdr fMAIN 0.5 - 1.0 7.0 ms MHz Figure 5.23 Main clock oscillator t dr OSTDF* Normal operation Abnormal operation Internal oscillation ICLK Note : * This indicates the OSTDF flag in the oscillation detection control register (OSTDCR). Figure 5.23 Oscillation Stop Detection Timing R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 84 of 92 RX62T Group 5. Electrical Characteristics 5.7 ROM (Flash Memory for Code Storage) Characteristics ROM (Flash Memory for Code Storage) Characteristics Table 5.19 Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Temperature range for the programming/erasure operation: Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Programming time 256 bytes 4 Kbytes 16 Kbytes 256 byte 4 Kbytes 16 Kbytes Erasure time 4 Kbytes 16 Kbytes 4 Kbytes 16 Kbytes Rewrite/erase cycle*1 Suspend delay time during writing First suspend delay time during erasing (in suspend priority mode) Second suspend delay time during erasing (in suspend priority mode) Suspend delay time during erasing (in erasure priority mode) Data hold time*3 tP256 tP4K tP16K tP256 tP4K tP16K tE4K tE16K tE4K tE16K NPEC tSPD tSESD1 tSESD2 tSEED tDRP 1000*2 10 2 23 90 2.4 27.6 108 25 100 30 120 - 12 50 200 14.4 60 240 60 240 72 288 120 120 1.7 1.7 - ms ms ms ms ms ms ms ms ms ms Times PCLK = 50 MHz NPEC  100 PCLK = 50 MHz NPEC > 100 PCLK = 50 MHz NPEC  100 PCLK = 50 MHz NPEC > 100 s s ms ms Year Figure 5.24 PCLK = 50 MHz Note 1. Definition of rewrite/erase cycle: The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 256-byte writing is performed 16 times for different addresses in 4Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address for several times as one erasing is not enabled (overwriting is prohibited). Note 2. This indicates the minimum number that guarantees the characteristics after rewriting. (The guaranteed value is in the range from one to the minimum number.) Note 3. This indicates the characteristic when rewrite is performed within the specification range including the minimum number. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 85 of 92 RX62T Group 5. Electrical Characteristics 5.8 Data Flash (Flash Memory for Data Storage) Characteristics Data Flash (Flash Memory for Data Storage) Characteristics Table 5.20 Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Temperature range for the programming/erasure operation: Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Typ. Max. Unit Test Conditions Programming time 8 bytes 128 bytes tDP8 tDP128 tDE2K tDBC8 tDBC2K NDPEC tDSPD tDSESD1 tDSESD2 tDSEED tDDRP 30000*2 10 0.4 1 70 - 2 5 250 30 0.7 120 120 1.7 1.7 - ms ms ms PCLK = 50 MHz PCLK = 50 MHz PCLK = 50 MHz Erasure time Blank check time Rewrite/erase cycle*1 2 Kbytes 8 bytes 2 Kbytes s ms Times Suspend delay time during writing First suspend delay time during erasing (in suspend priority mode) Second suspend delay time during erasing (in suspend priority mode) Suspend delay time during erasing (in erasure priority mode) Data hold time*3 s s ms ms Year Figure 5.24 PCLK = 50 MHz Note 1. Definition of rewrite/erase cycle: The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 30000), erasing can be performed n times for each block. For instance, when 128-byte writing is performed 16 times for different addresses in 2Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address for several times as one erasing is not enabled (overwriting is prohibited). Note 2. This indicates the minimum number that guarantees the characteristics after rewriting. (The guaranteed value is in the range from one to the minimum number.) Note 3. This indicates the characteristic when rewrite is performed within the specification range including the minimum number. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 86 of 92 RX62T Group 5. Electrical Characteristics ● Write suspend FCU command Program Suspend tSPD FSTATR0.FRDY Ready Not Ready Ready Write pulse Programming ● Erasure suspend in suspend priority mode FCU command Erase Suspend tSESD1 FSTATR0.FRDY Ready Not Ready Ready Not Ready Resume Suspend tSESD2 Erasure pulse Erasing Erasing ● Erasure suspend in erasure priority mode FCU command Erase Suspend tSEED FSTATR0.FRDY Ready Not Ready Ready Erasure pulse Erasing Figure 5.24 Flash Memory Write/Erase Suspend Timing R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 87 of 92 RX62T Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-LQFP112-20x20-0.65 RENESAS Code PLQP0112JA-A Previous Code FP-112E / FP-112EV MASS[Typ.] 1.2g HD *1 D 84 57 85 56 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 c1 HE E c Reference Dimension in Millimeters Symbol *2 Terminal cross section 112 29 1 ZD Index mark 28 F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 L L1 e y *3 bp x Detail F Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.27 0.32 0.37 0.30 0.09 0.145 0.20 0.125 0° 8° 0.65 0.13 0.10 1.225 1.225 0.35 0.5 0.65 1.0 ZE A2 A Figure A 112-Pin LQFP (PLQP0112JA-A) Package Dimensions R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 A1 c Page 88 of 92 RX62T Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 75 51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 76 50 bp b1 HE E Reference Symbol *2 Dimension in Millimeters c1 c Terminal cross section 1 Index mark ZD 25 F ZE 100 26 A2 A D E A2 HD HE A A1 bp b1 c c1 c A1 y e *3 bp L L1 Detail F x e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 Figure B 100-Pin LQFP (PLQP0100KB-A) Package Dimensions R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 89 of 92 RX62T Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP80-14x14-0.65 RENESAS Code PLQP0080JA-A Previous Code FP-80W / FP-80WV MASS[Typ.] 0.6g HD *1 D 41 60 61 40 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp HE E b1 *2 c1 Reference Symbol c Dimension in Millimeters 80 21 1 ZD Index mark 20 ZE Terminal cross section A2 A F A1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 L y e *3 L1 bp Detail F x Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.27 0.32 0.37 0.30 0.09 0.145 0.20 0.125 0° 8° 0.65 0.13 0.10 0.825 0.825 0.35 0.5 0.65 1.0 Figure C 80-Pin LQFP (PLQP0080JA-A) Package Dimensions R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 c Page 90 of 92 RX62T Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 48 D 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 HE E Reference Dimension in Millimeters Symbol 49 32 *2 c1 c 64 1 Index mark ZD 16 ZE 17 Terminal cross section F A2 A D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 e *3 A1 y bp x L L1 Detail F Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 Figure D 64-Pin LQFP (PLQP0064KB-A) Package Dimensions R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 c Page 91 of 92 REVISION HISTORY RX62T Group REVISION HISTORY REVISION HISTORY Description Rev. Date Page Summary RX62T Group Datasheet 1.00 Apr 20, 2011 — First edition issued All trademarks and registered trademarks are the property of their respective owners. R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 Page 92 of 92 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. 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